diff options
Diffstat (limited to 'gcc-4.8/gcc/doc')
27 files changed, 4667 insertions, 2178 deletions
diff --git a/gcc-4.8/gcc/doc/aot-compile.1 b/gcc-4.8/gcc/doc/aot-compile.1 index c5ee9a688..9c0f0fee9 100644 --- a/gcc-4.8/gcc/doc/aot-compile.1 +++ b/gcc-4.8/gcc/doc/aot-compile.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "AOT-COMPILE 1" -.TH AOT-COMPILE 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH AOT-COMPILE 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/cpp.1 b/gcc-4.8/gcc/doc/cpp.1 index c6e5d4f3a..8eb660f30 100644 --- a/gcc-4.8/gcc/doc/cpp.1 +++ b/gcc-4.8/gcc/doc/cpp.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "CPP 1" -.TH CPP 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH CPP 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/cpp.info b/gcc-4.8/gcc/doc/cpp.info index bcf62824b..36327d348 100644 --- a/gcc-4.8/gcc/doc/cpp.info +++ b/gcc-4.8/gcc/doc/cpp.info @@ -1,5 +1,5 @@ -This is doc/cpp.info, produced by makeinfo version 4.13 from -/d/gcc-4.8.1/gcc-4.8.1/gcc/doc/cpp.texi. +This is doc/cpp.info, produced by makeinfo version 4.12 from +/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/doc/cpp.texi. Copyright (C) 1987-2013 Free Software Foundation, Inc. @@ -1734,11 +1734,10 @@ with `__FILE__' and `__LINE__', though. This macro is defined when the C++ compiler is in use. You can use `__cplusplus' to test whether a header is compiled by a C compiler or a C++ compiler. This macro is similar to `__STDC_VERSION__', in - that it expands to a version number. A fully conforming - implementation of the 1998 C++ standard will define this macro to - `199711L'. The GNU C++ compiler is not yet fully conforming, so - it uses `1' instead. It is hoped to complete the implementation - of standard C++ in the near future. + that it expands to a version number. Depending on the language + standard selected, the value of the macro is `199711L', as + mandated by the 1998 C++ standard, or `201103L', per the 2011 C++ + standard. `__OBJC__' This macro is defined, with value 1, when the Objective-C compiler @@ -2112,7 +2111,7 @@ double underscores. `__GXX_EXPERIMENTAL_CXX0X__' This macro is defined when compiling a C++ source file with the option `-std=c++0x' or `-std=gnu++0x'. It indicates that some - features likely to be included in C++0x are available. Note that + features likely to be included in C++0x are available. Note that these features are experimental, and may change or be removed in future versions of GCC. @@ -4510,9 +4509,9 @@ single-letter options may _not_ be grouped: `-dM' is very different from When used without `-E', this option has no effect. `-ftrack-macro-expansion[=LEVEL]' - Track locations of tokens across macro expansions. This allows the + Track locations of tokens across macro expansions. This allows the compiler to emit diagnostic about the current macro expansion stack - when a compilation error occurs in a macro expansion. Using this + when a compilation error occurs in a macro expansion. Using this option makes the preprocessor and the compiler consume more memory. The LEVEL parameter can be used to choose the level of precision of token location tracking thus decreasing the memory @@ -5156,7 +5155,7 @@ GNU Free Documentation License not permanently reinstated, receipt of a copy of some or all of the same material does not give you any rights to use it. - 10. FUTURE REVISIONS OF THIS LICENSE + 10. FUTURE REVISIONS OF THIS LICENSE The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new @@ -5177,7 +5176,7 @@ GNU Free Documentation License proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Document. - 11. RELICENSING + 11. RELICENSING "Massive Multiauthor Collaboration Site" (or "MMC Site") means any World Wide Web server that publishes copyrightable works and also @@ -5224,7 +5223,7 @@ notices just after the title page: Free Documentation License''. If you have Invariant Sections, Front-Cover Texts and Back-Cover -Texts, replace the "with...Texts." line with this: +Texts, replace the "with...Texts." line with this: with the Invariant Sections being LIST THEIR TITLES, with the Front-Cover Texts being LIST, and with the Back-Cover Texts @@ -5519,79 +5518,79 @@ Concept Index Tag Table: -Node: Top982 -Node: Overview3587 -Node: Character sets6420 -Ref: Character sets-Footnote-18603 -Node: Initial processing8784 -Ref: trigraphs10343 -Node: Tokenization14545 -Ref: Tokenization-Footnote-121681 -Node: The preprocessing language21792 -Node: Header Files24670 -Node: Include Syntax26586 -Node: Include Operation28223 -Node: Search Path30071 -Node: Once-Only Headers33272 -Node: Alternatives to Wrapper #ifndef34931 -Node: Computed Includes36674 -Node: Wrapper Headers39832 -Node: System Headers42258 -Node: Macros44308 -Node: Object-like Macros45449 -Node: Function-like Macros49039 -Node: Macro Arguments50655 -Node: Stringification54800 -Node: Concatenation58006 -Node: Variadic Macros61114 -Node: Predefined Macros65901 -Node: Standard Predefined Macros66489 -Node: Common Predefined Macros72426 -Node: System-specific Predefined Macros90049 -Node: C++ Named Operators92072 -Node: Undefining and Redefining Macros93036 -Node: Directives Within Macro Arguments95140 -Node: Macro Pitfalls96688 -Node: Misnesting97221 -Node: Operator Precedence Problems98333 -Node: Swallowing the Semicolon100199 -Node: Duplication of Side Effects102222 -Node: Self-Referential Macros104405 -Node: Argument Prescan106814 -Node: Newlines in Arguments110568 -Node: Conditionals111519 -Node: Conditional Uses113349 -Node: Conditional Syntax114707 -Node: Ifdef115027 -Node: If118188 -Node: Defined120492 -Node: Else121775 -Node: Elif122345 -Node: Deleted Code123634 -Node: Diagnostics124881 -Node: Line Control126428 -Node: Pragmas130232 -Node: Other Directives134988 -Node: Preprocessor Output136038 -Node: Traditional Mode139239 -Node: Traditional lexical analysis140297 -Node: Traditional macros142800 -Node: Traditional miscellany146602 -Node: Traditional warnings147599 -Node: Implementation Details149796 -Node: Implementation-defined behavior150417 -Ref: Identifier characters151169 -Node: Implementation limits154247 -Node: Obsolete Features156921 -Node: Differences from previous versions159809 -Node: Invocation164017 -Ref: Wtrigraphs168469 -Ref: dashMF173244 -Ref: fdollars-in-identifiers182975 -Node: Environment Variables192844 -Node: GNU Free Documentation License195810 -Node: Index of Directives220974 -Node: Option Index223054 -Node: Concept Index229457 +Node: Top996 +Node: Overview3601 +Node: Character sets6434 +Ref: Character sets-Footnote-18617 +Node: Initial processing8798 +Ref: trigraphs10357 +Node: Tokenization14559 +Ref: Tokenization-Footnote-121695 +Node: The preprocessing language21806 +Node: Header Files24684 +Node: Include Syntax26600 +Node: Include Operation28237 +Node: Search Path30085 +Node: Once-Only Headers33286 +Node: Alternatives to Wrapper #ifndef34945 +Node: Computed Includes36688 +Node: Wrapper Headers39846 +Node: System Headers42272 +Node: Macros44322 +Node: Object-like Macros45463 +Node: Function-like Macros49053 +Node: Macro Arguments50669 +Node: Stringification54814 +Node: Concatenation58020 +Node: Variadic Macros61128 +Node: Predefined Macros65915 +Node: Standard Predefined Macros66503 +Node: Common Predefined Macros72345 +Node: System-specific Predefined Macros89968 +Node: C++ Named Operators91991 +Node: Undefining and Redefining Macros92955 +Node: Directives Within Macro Arguments95059 +Node: Macro Pitfalls96607 +Node: Misnesting97140 +Node: Operator Precedence Problems98252 +Node: Swallowing the Semicolon100118 +Node: Duplication of Side Effects102141 +Node: Self-Referential Macros104324 +Node: Argument Prescan106733 +Node: Newlines in Arguments110487 +Node: Conditionals111438 +Node: Conditional Uses113268 +Node: Conditional Syntax114626 +Node: Ifdef114946 +Node: If118107 +Node: Defined120411 +Node: Else121694 +Node: Elif122264 +Node: Deleted Code123553 +Node: Diagnostics124800 +Node: Line Control126347 +Node: Pragmas130151 +Node: Other Directives134907 +Node: Preprocessor Output135957 +Node: Traditional Mode139158 +Node: Traditional lexical analysis140216 +Node: Traditional macros142719 +Node: Traditional miscellany146521 +Node: Traditional warnings147518 +Node: Implementation Details149715 +Node: Implementation-defined behavior150336 +Ref: Identifier characters151088 +Node: Implementation limits154166 +Node: Obsolete Features156840 +Node: Differences from previous versions159728 +Node: Invocation163936 +Ref: Wtrigraphs168388 +Ref: dashMF173163 +Ref: fdollars-in-identifiers182894 +Node: Environment Variables192763 +Node: GNU Free Documentation License195729 +Node: Index of Directives220893 +Node: Option Index222973 +Node: Concept Index229376 End Tag Table diff --git a/gcc-4.8/gcc/doc/cppinternals.info b/gcc-4.8/gcc/doc/cppinternals.info index 3336fb002..aed69bac7 100644 --- a/gcc-4.8/gcc/doc/cppinternals.info +++ b/gcc-4.8/gcc/doc/cppinternals.info @@ -1,5 +1,5 @@ -This is doc/cppinternals.info, produced by makeinfo version 4.13 from -/d/gcc-4.8.1/gcc-4.8.1/gcc/doc/cppinternals.texi. +This is doc/cppinternals.info, produced by makeinfo version 4.12 from +/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/doc/cppinternals.texi. INFO-DIR-SECTION Software development START-INFO-DIR-ENTRY @@ -1019,17 +1019,17 @@ Concept Index Tag Table: -Node: Top944 -Node: Conventions2629 -Node: Lexer3571 -Ref: Invalid identifiers11484 -Ref: Lexing a line13433 -Node: Hash Nodes18206 -Node: Macro Expansion21085 -Node: Token Spacing30032 -Node: Line Numbering35892 -Node: Guard Macros39977 -Node: Files44768 -Node: Concept Index48234 +Node: Top958 +Node: Conventions2643 +Node: Lexer3585 +Ref: Invalid identifiers11498 +Ref: Lexing a line13447 +Node: Hash Nodes18220 +Node: Macro Expansion21099 +Node: Token Spacing30046 +Node: Line Numbering35906 +Node: Guard Macros39991 +Node: Files44782 +Node: Concept Index48248 End Tag Table diff --git a/gcc-4.8/gcc/doc/extend.texi b/gcc-4.8/gcc/doc/extend.texi index b6075b7cb..860f2e83f 100644 --- a/gcc-4.8/gcc/doc/extend.texi +++ b/gcc-4.8/gcc/doc/extend.texi @@ -3121,6 +3121,17 @@ this function attribute to make GCC generate the ``hot-patching'' function prologue used in Win32 API functions in Microsoft Windows XP Service Pack 2 and newer. +@item hotpatch [(@var{prologue-halfwords})] +@cindex @code{hotpatch} attribute + +On S/390 System z targets, you can use this function attribute to +make GCC generate a ``hot-patching'' function prologue. The +@code{hotpatch} has no effect on funtions that are explicitly +inline. If the @option{-mhotpatch} or @option{-mno-hotpatch} +command-line option is used at the same time, the @code{hotpatch} +attribute takes precedence. If an argument is given, the maximum +allowed value is 1000000. + @item naked @cindex function without a prologue/epilogue code Use this attribute on the ARM, AVR, MCORE, RX and SPU ports to indicate that @@ -8793,6 +8804,7 @@ instructions, but allow the compiler to schedule those calls. * picoChip Built-in Functions:: * PowerPC Built-in Functions:: * PowerPC AltiVec/VSX Built-in Functions:: +* PowerPC Hardware Transactional Memory Built-in Functions:: * RX Built-in Functions:: * S/390 System z Built-in Functions:: * SH Built-in Functions:: @@ -11840,9 +11852,12 @@ float __builtin_recipdivf (float, float); float __builtin_rsqrtf (float); double __builtin_recipdiv (double, double); double __builtin_rsqrt (double); -long __builtin_bpermd (long, long); uint64_t __builtin_ppc_get_timebase (); unsigned long __builtin_ppc_mftb (); +double __builtin_unpack_longdouble (long double, int); +double __builtin_longdouble_dw0 (long double); +double __builtin_longdouble_dw1 (long double); +long double __builtin_pack_longdouble (double, double); @end smallexample The @code{vec_rsqrt}, @code{__builtin_rsqrt}, and @@ -11862,6 +11877,57 @@ The @code{__builtin_ppc_mftb} function always generates one instruction and returns the Time Base Register value as an unsigned long, throwing away the most significant word on 32-bit environments. +The following built-in functions are available for the PowerPC family +of processors, starting with ISA 2.06 or later (@option{-mcpu=power7} +or @option{-mpopcntd}): +@smallexample +long __builtin_bpermd (long, long); +int __builtin_divwe (int, int); +int __builtin_divweo (int, int); +unsigned int __builtin_divweu (unsigned int, unsigned int); +unsigned int __builtin_divweuo (unsigned int, unsigned int); +long __builtin_divde (long, long); +long __builtin_divdeo (long, long); +unsigned long __builtin_divdeu (unsigned long, unsigned long); +unsigned long __builtin_divdeuo (unsigned long, unsigned long); +unsigned int cdtbcd (unsigned int); +unsigned int cbcdtd (unsigned int); +unsigned int addg6s (unsigned int, unsigned int); +@end smallexample + +The @code{__builtin_divde}, @code{__builtin_divdeo}, +@code{__builitin_divdeu}, @code{__builtin_divdeou} functions require a +64-bit environment support ISA 2.06 or later. + +The following built-in functions are available for the PowerPC family +of processors when hardware decimal floating point +(@option{-mhard-dfp}) is available: +@smallexample +_Decimal64 __builtin_dxex (_Decimal64); +_Decimal128 __builtin_dxexq (_Decimal128); +_Decimal64 __builtin_ddedpd (int, _Decimal64); +_Decimal128 __builtin_ddedpdq (int, _Decimal128); +_Decimal64 __builtin_denbcd (int, _Decimal64); +_Decimal128 __builtin_denbcdq (int, _Decimal128); +_Decimal64 __builtin_diex (_Decimal64, _Decimal64); +_Decimal128 _builtin_diexq (_Decimal128, _Decimal128); +_Decimal64 __builtin_dscli (_Decimal64, int); +_Decimal128 __builitn_dscliq (_Decimal128, int); +_Decimal64 __builtin_dscri (_Decimal64, int); +_Decimal128 __builitn_dscriq (_Decimal128, int); +unsigned long long __builtin_unpack_dec128 (_Decimal128, int); +_Decimal128 __builtin_pack_dec128 (unsigned long long, unsigned long long); +@end smallexample + +The following built-in functions are available for the PowerPC family +of processors when the Vector Scalar (vsx) instruction set is +available: +@smallexample +unsigned long long __builtin_unpack_vector_int128 (vector __int128_t, int); +vector __int128_t __builtin_pack_vector_int128 (unsigned long long, + unsigned long long); +@end smallexample + @node PowerPC AltiVec/VSX Built-in Functions @subsection PowerPC AltiVec Built-in Functions @@ -13912,6 +13978,35 @@ void vec_vsx_st (vector unsigned char, int, unsigned char *); void vec_vsx_st (vector bool char, int, vector bool char *); void vec_vsx_st (vector bool char, int, unsigned char *); void vec_vsx_st (vector bool char, int, signed char *); + +vector double vec_xxpermdi (vector double, vector double, int); +vector float vec_xxpermdi (vector float, vector float, int); +vector long long vec_xxpermdi (vector long long, vector long long, int); +vector unsigned long long vec_xxpermdi (vector unsigned long long, + vector unsigned long long, int); +vector int vec_xxpermdi (vector int, vector int, int); +vector unsigned int vec_xxpermdi (vector unsigned int, + vector unsigned int, int); +vector short vec_xxpermdi (vector short, vector short, int); +vector unsigned short vec_xxpermdi (vector unsigned short, + vector unsigned short, int); +vector signed char vec_xxpermdi (vector signed char, vector signed char, int); +vector unsigned char vec_xxpermdi (vector unsigned char, + vector unsigned char, int); + +vector double vec_xxsldi (vector double, vector double, int); +vector float vec_xxsldi (vector float, vector float, int); +vector long long vec_xxsldi (vector long long, vector long long, int); +vector unsigned long long vec_xxsldi (vector unsigned long long, + vector unsigned long long, int); +vector int vec_xxsldi (vector int, vector int, int); +vector unsigned int vec_xxsldi (vector unsigned int, vector unsigned int, int); +vector short vec_xxsldi (vector short, vector short, int); +vector unsigned short vec_xxsldi (vector unsigned short, + vector unsigned short, int); +vector signed char vec_xxsldi (vector signed char, vector signed char, int); +vector unsigned char vec_xxsldi (vector unsigned char, + vector unsigned char, int); @end smallexample Note that the @samp{vec_ld} and @samp{vec_st} built-in functions always @@ -13920,6 +14015,593 @@ if the VSX instruction set is available. The @samp{vec_vsx_ld} and @samp{vec_vsx_st} built-in functions always generate the VSX @samp{LXVD2X}, @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions. +If the ISA 2.07 additions to the vector/scalar (power8-vector) +instruction set is available, the following additional functions are +available for both 32-bit and 64-bit targets. For 64-bit targets, you +can use @var{vector long} instead of @var{vector long long}, +@var{vector bool long} instead of @var{vector bool long long}, and +@var{vector unsigned long} instead of @var{vector unsigned long long}. + +@smallexample +vector long long vec_abs (vector long long); + +vector long long vec_add (vector long long, vector long long); +vector unsigned long long vec_add (vector unsigned long long, + vector unsigned long long); + +int vec_all_eq (vector long long, vector long long); +int vec_all_ge (vector long long, vector long long); +int vec_all_gt (vector long long, vector long long); +int vec_all_le (vector long long, vector long long); +int vec_all_lt (vector long long, vector long long); +int vec_all_ne (vector long long, vector long long); +int vec_any_eq (vector long long, vector long long); +int vec_any_ge (vector long long, vector long long); +int vec_any_gt (vector long long, vector long long); +int vec_any_le (vector long long, vector long long); +int vec_any_lt (vector long long, vector long long); +int vec_any_ne (vector long long, vector long long); + +vector long long vec_eqv (vector long long, vector long long); +vector long long vec_eqv (vector bool long long, vector long long); +vector long long vec_eqv (vector long long, vector bool long long); +vector unsigned long long vec_eqv (vector unsigned long long, + vector unsigned long long); +vector unsigned long long vec_eqv (vector bool long long, + vector unsigned long long); +vector unsigned long long vec_eqv (vector unsigned long long, + vector bool long long); +vector int vec_eqv (vector int, vector int); +vector int vec_eqv (vector bool int, vector int); +vector int vec_eqv (vector int, vector bool int); +vector unsigned int vec_eqv (vector unsigned int, vector unsigned int); +vector unsigned int vec_eqv (vector bool unsigned int, + vector unsigned int); +vector unsigned int vec_eqv (vector unsigned int, + vector bool unsigned int); +vector short vec_eqv (vector short, vector short); +vector short vec_eqv (vector bool short, vector short); +vector short vec_eqv (vector short, vector bool short); +vector unsigned short vec_eqv (vector unsigned short, vector unsigned short); +vector unsigned short vec_eqv (vector bool unsigned short, + vector unsigned short); +vector unsigned short vec_eqv (vector unsigned short, + vector bool unsigned short); +vector signed char vec_eqv (vector signed char, vector signed char); +vector signed char vec_eqv (vector bool signed char, vector signed char); +vector signed char vec_eqv (vector signed char, vector bool signed char); +vector unsigned char vec_eqv (vector unsigned char, vector unsigned char); +vector unsigned char vec_eqv (vector bool unsigned char, vector unsigned char); +vector unsigned char vec_eqv (vector unsigned char, vector bool unsigned char); + +vector long long vec_max (vector long long, vector long long); +vector unsigned long long vec_max (vector unsigned long long, + vector unsigned long long); + +vector long long vec_min (vector long long, vector long long); +vector unsigned long long vec_min (vector unsigned long long, + vector unsigned long long); + +vector long long vec_nand (vector long long, vector long long); +vector long long vec_nand (vector bool long long, vector long long); +vector long long vec_nand (vector long long, vector bool long long); +vector unsigned long long vec_nand (vector unsigned long long, + vector unsigned long long); +vector unsigned long long vec_nand (vector bool long long, + vector unsigned long long); +vector unsigned long long vec_nand (vector unsigned long long, + vector bool long long); +vector int vec_nand (vector int, vector int); +vector int vec_nand (vector bool int, vector int); +vector int vec_nand (vector int, vector bool int); +vector unsigned int vec_nand (vector unsigned int, vector unsigned int); +vector unsigned int vec_nand (vector bool unsigned int, + vector unsigned int); +vector unsigned int vec_nand (vector unsigned int, + vector bool unsigned int); +vector short vec_nand (vector short, vector short); +vector short vec_nand (vector bool short, vector short); +vector short vec_nand (vector short, vector bool short); +vector unsigned short vec_nand (vector unsigned short, vector unsigned short); +vector unsigned short vec_nand (vector bool unsigned short, + vector unsigned short); +vector unsigned short vec_nand (vector unsigned short, + vector bool unsigned short); +vector signed char vec_nand (vector signed char, vector signed char); +vector signed char vec_nand (vector bool signed char, vector signed char); +vector signed char vec_nand (vector signed char, vector bool signed char); +vector unsigned char vec_nand (vector unsigned char, vector unsigned char); +vector unsigned char vec_nand (vector bool unsigned char, vector unsigned char); +vector unsigned char vec_nand (vector unsigned char, vector bool unsigned char); + +vector long long vec_orc (vector long long, vector long long); +vector long long vec_orc (vector bool long long, vector long long); +vector long long vec_orc (vector long long, vector bool long long); +vector unsigned long long vec_orc (vector unsigned long long, + vector unsigned long long); +vector unsigned long long vec_orc (vector bool long long, + vector unsigned long long); +vector unsigned long long vec_orc (vector unsigned long long, + vector bool long long); +vector int vec_orc (vector int, vector int); +vector int vec_orc (vector bool int, vector int); +vector int vec_orc (vector int, vector bool int); +vector unsigned int vec_orc (vector unsigned int, vector unsigned int); +vector unsigned int vec_orc (vector bool unsigned int, + vector unsigned int); +vector unsigned int vec_orc (vector unsigned int, + vector bool unsigned int); +vector short vec_orc (vector short, vector short); +vector short vec_orc (vector bool short, vector short); +vector short vec_orc (vector short, vector bool short); +vector unsigned short vec_orc (vector unsigned short, vector unsigned short); +vector unsigned short vec_orc (vector bool unsigned short, + vector unsigned short); +vector unsigned short vec_orc (vector unsigned short, + vector bool unsigned short); +vector signed char vec_orc (vector signed char, vector signed char); +vector signed char vec_orc (vector bool signed char, vector signed char); +vector signed char vec_orc (vector signed char, vector bool signed char); +vector unsigned char vec_orc (vector unsigned char, vector unsigned char); +vector unsigned char vec_orc (vector bool unsigned char, vector unsigned char); +vector unsigned char vec_orc (vector unsigned char, vector bool unsigned char); + +vector int vec_pack (vector long long, vector long long); +vector unsigned int vec_pack (vector unsigned long long, + vector unsigned long long); +vector bool int vec_pack (vector bool long long, vector bool long long); + +vector int vec_packs (vector long long, vector long long); +vector unsigned int vec_packs (vector unsigned long long, + vector unsigned long long); + +vector unsigned int vec_packsu (vector long long, vector long long); + +vector long long vec_rl (vector long long, + vector unsigned long long); +vector long long vec_rl (vector unsigned long long, + vector unsigned long long); + +vector long long vec_sl (vector long long, vector unsigned long long); +vector long long vec_sl (vector unsigned long long, + vector unsigned long long); + +vector long long vec_sr (vector long long, vector unsigned long long); +vector unsigned long long char vec_sr (vector unsigned long long, + vector unsigned long long); + +vector long long vec_sra (vector long long, vector unsigned long long); +vector unsigned long long vec_sra (vector unsigned long long, + vector unsigned long long); + +vector long long vec_sub (vector long long, vector long long); +vector unsigned long long vec_sub (vector unsigned long long, + vector unsigned long long); + +vector long long vec_unpackh (vector int); +vector unsigned long long vec_unpackh (vector unsigned int); + +vector long long vec_unpackl (vector int); +vector unsigned long long vec_unpackl (vector unsigned int); + +vector long long vec_vaddudm (vector long long, vector long long); +vector long long vec_vaddudm (vector bool long long, vector long long); +vector long long vec_vaddudm (vector long long, vector bool long long); +vector unsigned long long vec_vaddudm (vector unsigned long long, + vector unsigned long long); +vector unsigned long long vec_vaddudm (vector bool unsigned long long, + vector unsigned long long); +vector unsigned long long vec_vaddudm (vector unsigned long long, + vector bool unsigned long long); + +vector long long vec_vbpermq (vector signed char, vector signed char); +vector long long vec_vbpermq (vector unsigned char, vector unsigned char); + +vector long long vec_vclz (vector long long); +vector unsigned long long vec_vclz (vector unsigned long long); +vector int vec_vclz (vector int); +vector unsigned int vec_vclz (vector int); +vector short vec_vclz (vector short); +vector unsigned short vec_vclz (vector unsigned short); +vector signed char vec_vclz (vector signed char); +vector unsigned char vec_vclz (vector unsigned char); + +vector signed char vec_vclzb (vector signed char); +vector unsigned char vec_vclzb (vector unsigned char); + +vector long long vec_vclzd (vector long long); +vector unsigned long long vec_vclzd (vector unsigned long long); + +vector short vec_vclzh (vector short); +vector unsigned short vec_vclzh (vector unsigned short); + +vector int vec_vclzw (vector int); +vector unsigned int vec_vclzw (vector int); + +vector signed char vec_vgbbd (vector signed char); +vector unsigned char vec_vgbbd (vector unsigned char); + +vector long long vec_vmaxsd (vector long long, vector long long); + +vector unsigned long long vec_vmaxud (vector unsigned long long, + unsigned vector long long); + +vector long long vec_vminsd (vector long long, vector long long); + +vector unsigned long long vec_vminud (vector long long, + vector long long); + +vector int vec_vpksdss (vector long long, vector long long); +vector unsigned int vec_vpksdss (vector long long, vector long long); + +vector unsigned int vec_vpkudus (vector unsigned long long, + vector unsigned long long); + +vector int vec_vpkudum (vector long long, vector long long); +vector unsigned int vec_vpkudum (vector unsigned long long, + vector unsigned long long); +vector bool int vec_vpkudum (vector bool long long, vector bool long long); + +vector long long vec_vpopcnt (vector long long); +vector unsigned long long vec_vpopcnt (vector unsigned long long); +vector int vec_vpopcnt (vector int); +vector unsigned int vec_vpopcnt (vector int); +vector short vec_vpopcnt (vector short); +vector unsigned short vec_vpopcnt (vector unsigned short); +vector signed char vec_vpopcnt (vector signed char); +vector unsigned char vec_vpopcnt (vector unsigned char); + +vector signed char vec_vpopcntb (vector signed char); +vector unsigned char vec_vpopcntb (vector unsigned char); + +vector long long vec_vpopcntd (vector long long); +vector unsigned long long vec_vpopcntd (vector unsigned long long); + +vector short vec_vpopcnth (vector short); +vector unsigned short vec_vpopcnth (vector unsigned short); + +vector int vec_vpopcntw (vector int); +vector unsigned int vec_vpopcntw (vector int); + +vector long long vec_vrld (vector long long, vector unsigned long long); +vector unsigned long long vec_vrld (vector unsigned long long, + vector unsigned long long); + +vector long long vec_vsld (vector long long, vector unsigned long long); +vector long long vec_vsld (vector unsigned long long, + vector unsigned long long); + +vector long long vec_vsrad (vector long long, vector unsigned long long); +vector unsigned long long vec_vsrad (vector unsigned long long, + vector unsigned long long); + +vector long long vec_vsrd (vector long long, vector unsigned long long); +vector unsigned long long char vec_vsrd (vector unsigned long long, + vector unsigned long long); + +vector long long vec_vsubudm (vector long long, vector long long); +vector long long vec_vsubudm (vector bool long long, vector long long); +vector long long vec_vsubudm (vector long long, vector bool long long); +vector unsigned long long vec_vsubudm (vector unsigned long long, + vector unsigned long long); +vector unsigned long long vec_vsubudm (vector bool long long, + vector unsigned long long); +vector unsigned long long vec_vsubudm (vector unsigned long long, + vector bool long long); + +vector long long vec_vupkhsw (vector int); +vector unsigned long long vec_vupkhsw (vector unsigned int); + +vector long long vec_vupklsw (vector int); +vector unsigned long long vec_vupklsw (vector int); +@end smallexample + +If the ISA 2.07 additions to the vector/scalar (power8-vector) +instruction set is available, the following additional functions are +available for 64-bit targets. New vector types +(@var{vector __int128_t} and @var{vector __uint128_t}) are available +to hold the @var{__int128_t} and @var{__uint128_t} types to use these +builtins. + +The normal vector extract, and set operations work on +@var{vector __int128_t} and @var{vector __uint128_t} types, +but the index value must be 0. + +@smallexample +vector __int128_t vec_vaddcuq (vector __int128_t, vector __int128_t); +vector __uint128_t vec_vaddcuq (vector __uint128_t, vector __uint128_t); + +vector __int128_t vec_vadduqm (vector __int128_t, vector __int128_t); +vector __uint128_t vec_vadduqm (vector __uint128_t, vector __uint128_t); + +vector __int128_t vec_vaddecuq (vector __int128_t, vector __int128_t, + vector __int128_t); +vector __uint128_t vec_vaddecuq (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + +vector __int128_t vec_vaddeuqm (vector __int128_t, vector __int128_t, + vector __int128_t); +vector __uint128_t vec_vaddeuqm (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + +vector __int128_t vec_vsubecuq (vector __int128_t, vector __int128_t, + vector __int128_t); +vector __uint128_t vec_vsubecuq (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + +vector __int128_t vec_vsubeuqm (vector __int128_t, vector __int128_t, + vector __int128_t); +vector __uint128_t vec_vsubeuqm (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + +vector __int128_t vec_vsubcuq (vector __int128_t, vector __int128_t); +vector __uint128_t vec_vsubcuq (vector __uint128_t, vector __uint128_t); + +__int128_t vec_vsubuqm (__int128_t, __int128_t); +__uint128_t vec_vsubuqm (__uint128_t, __uint128_t); + +vector __int128_t __builtin_bcdadd (vector __int128_t, vector__int128_t); +int __builtin_bcdadd_lt (vector __int128_t, vector__int128_t); +int __builtin_bcdadd_eq (vector __int128_t, vector__int128_t); +int __builtin_bcdadd_gt (vector __int128_t, vector__int128_t); +int __builtin_bcdadd_ov (vector __int128_t, vector__int128_t); +vector __int128_t bcdsub (vector __int128_t, vector__int128_t); +int __builtin_bcdsub_lt (vector __int128_t, vector__int128_t); +int __builtin_bcdsub_eq (vector __int128_t, vector__int128_t); +int __builtin_bcdsub_gt (vector __int128_t, vector__int128_t); +int __builtin_bcdsub_ov (vector __int128_t, vector__int128_t); +@end smallexample + +If the cryptographic instructions are enabled (@option{-mcrypto} or +@option{-mcpu=power8}), the following builtins are enabled. + +@smallexample +vector unsigned long long __builtin_crypto_vsbox (vector unsigned long long); + +vector unsigned long long __builtin_crypto_vcipher (vector unsigned long long, + vector unsigned long long); + +vector unsigned long long __builtin_crypto_vcipherlast + (vector unsigned long long, + vector unsigned long long); + +vector unsigned long long __builtin_crypto_vncipher (vector unsigned long long, + vector unsigned long long); + +vector unsigned long long __builtin_crypto_vncipherlast + (vector unsigned long long, + vector unsigned long long); + +vector unsigned char __builtin_crypto_vpermxor (vector unsigned char, + vector unsigned char, + vector unsigned char); + +vector unsigned short __builtin_crypto_vpermxor (vector unsigned short, + vector unsigned short, + vector unsigned short); + +vector unsigned int __builtin_crypto_vpermxor (vector unsigned int, + vector unsigned int, + vector unsigned int); + +vector unsigned long long __builtin_crypto_vpermxor (vector unsigned long long, + vector unsigned long long, + vector unsigned long long); + +vector unsigned char __builtin_crypto_vpmsumb (vector unsigned char, + vector unsigned char); + +vector unsigned short __builtin_crypto_vpmsumb (vector unsigned short, + vector unsigned short); + +vector unsigned int __builtin_crypto_vpmsumb (vector unsigned int, + vector unsigned int); + +vector unsigned long long __builtin_crypto_vpmsumb (vector unsigned long long, + vector unsigned long long); + +vector unsigned long long __builtin_crypto_vshasigmad + (vector unsigned long long, int, int); + +vector unsigned int __builtin_crypto_vshasigmaw (vector unsigned int, + int, int); +@end smallexample + +The second argument to the @var{__builtin_crypto_vshasigmad} and +@var{__builtin_crypto_vshasigmaw} builtin functions must be a constant +integer that is 0 or 1. The third argument to these builtin functions +must be a constant integer in the range of 0 to 15. + +@node PowerPC Hardware Transactional Memory Built-in Functions +@subsection PowerPC Hardware Transactional Memory Built-in Functions +GCC provides two interfaces for accessing the Hardware Transactional +Memory (HTM) instructions available on some of the PowerPC family +of prcoessors (eg, POWER8). The two interfaces come in a low level +interface, consisting of built-in functions specific to PowerPC and a +higher level interface consisting of inline functions that are common +between PowerPC and S/390. + +@subsubsection PowerPC HTM Low Level Built-in Functions + +The following low level built-in functions are available with +@option{-mhtm} or @option{-mcpu=CPU} where CPU is `power8' or later. +They all generate the machine instruction that is part of the name. + +The HTM built-ins return true or false depending on their success and +their arguments match exactly the type and order of the associated +hardware instruction's operands. Refer to the ISA manual for a +description of each instruction's operands. + +@smallexample +unsigned int __builtin_tbegin (unsigned int) +unsigned int __builtin_tend (unsigned int) + +unsigned int __builtin_tabort (unsigned int) +unsigned int __builtin_tabortdc (unsigned int, unsigned int, unsigned int) +unsigned int __builtin_tabortdci (unsigned int, unsigned int, int) +unsigned int __builtin_tabortwc (unsigned int, unsigned int, unsigned int) +unsigned int __builtin_tabortwci (unsigned int, unsigned int, int) + +unsigned int __builtin_tcheck (unsigned int) +unsigned int __builtin_treclaim (unsigned int) +unsigned int __builtin_trechkpt (void) +unsigned int __builtin_tsr (unsigned int) +@end smallexample + +In addition to the above HTM built-ins, we have added built-ins for +some common extended mnemonics of the HTM instructions: + +@smallexample +unsigned int __builtin_tendall (void) +unsigned int __builtin_tresume (void) +unsigned int __builtin_tsuspend (void) +@end smallexample + +The following set of built-in functions are available to gain access +to the HTM specific special purpose registers. + +@smallexample +unsigned long __builtin_get_texasr (void) +unsigned long __builtin_get_texasru (void) +unsigned long __builtin_get_tfhar (void) +unsigned long __builtin_get_tfiar (void) + +void __builtin_set_texasr (unsigned long); +void __builtin_set_texasru (unsigned long); +void __builtin_set_tfhar (unsigned long); +void __builtin_set_tfiar (unsigned long); +@end smallexample + +Example usage of these low level built-in functions may look like: + +@smallexample +#include <htmintrin.h> + +int num_retries = 10; + +while (1) + @{ + if (__builtin_tbegin (0)) + @{ + /* Transaction State Initiated. */ + if (is_locked (lock)) + __builtin_tabort (0); + ... transaction code... + __builtin_tend (0); + break; + @} + else + @{ + /* Transaction State Failed. Use locks if the transaction + failure is "persistent" or we've tried too many times. */ + if (num_retries-- <= 0 + || _TEXASRU_FAILURE_PERSISTENT (__builtin_get_texasru ())) + @{ + acquire_lock (lock); + ... non transactional fallback path... + release_lock (lock); + break; + @} + @} + @} +@end smallexample + +One final built-in function has been added that returns the value of +the 2-bit Transaction State field of the Machine Status Register (MSR) +as stored in @code{CR0}. + +@smallexample +unsigned long __builtin_ttest (void) +@end smallexample + +This built-in can be used to determine the current transaction state +using the following code example: + +@smallexample +#include <htmintrin.h> + +unsigned char tx_state = _HTM_STATE (__builtin_ttest ()); + +if (tx_state == _HTM_TRANSACTIONAL) + @{ + /* Code to use in transactional state. */ + @} +else if (tx_state == _HTM_NONTRANSACTIONAL) + @{ + /* Code to use in non-transactional state. */ + @} +else if (tx_state == _HTM_SUSPENDED) + @{ + /* Code to use in transaction suspended state. */ + @} +@end smallexample + +@subsubsection PowerPC HTM High Level Inline Functions + +The following high level HTM interface is made available by including +@code{<htmxlintrin.h>} and using @option{-mhtm} or @option{-mcpu=CPU} +where CPU is `power8' or later. This interface is common between PowerPC +and S/390, allowing users to write one HTM source implementation that +can be compiled and executed on either system. + +@smallexample +long __TM_simple_begin (void) +long __TM_begin (void* const TM_buff) +long __TM_end (void) +void __TM_abort (void) +void __TM_named_abort (unsigned char const code) +void __TM_resume (void) +void __TM_suspend (void) + +long __TM_is_user_abort (void* const TM_buff) +long __TM_is_named_user_abort (void* const TM_buff, unsigned char *code) +long __TM_is_illegal (void* const TM_buff) +long __TM_is_footprint_exceeded (void* const TM_buff) +long __TM_nesting_depth (void* const TM_buff) +long __TM_is_nested_too_deep(void* const TM_buff) +long __TM_is_conflict(void* const TM_buff) +long __TM_is_failure_persistent(void* const TM_buff) +long __TM_failure_address(void* const TM_buff) +long long __TM_failure_code(void* const TM_buff) +@end smallexample + +Using these common set of HTM inline functions, we can create +a more portable version of the HTM example in the previous +section that will work on either PowerPC or S/390: + +@smallexample +#include <htmxlintrin.h> + +int num_retries = 10; +TM_buff_type TM_buff; + +while (1) + @{ + if (__TM_begin (TM_buff)) + @{ + /* Transaction State Initiated. */ + if (is_locked (lock)) + __TM_abort (); + ... transaction code... + __TM_end (); + break; + @} + else + @{ + /* Transaction State Failed. Use locks if the transaction + failure is "persistent" or we've tried too many times. */ + if (num_retries-- <= 0 + || __TM_is_failure_persistent (TM_buff)) + @{ + acquire_lock (lock); + ... non transactional fallback path... + release_lock (lock); + break; + @} + @} + @} +@end smallexample + @node RX Built-in Functions @subsection RX Built-in Functions GCC supports some of the RX instructions which cannot be expressed in diff --git a/gcc-4.8/gcc/doc/fsf-funding.7 b/gcc-4.8/gcc/doc/fsf-funding.7 index 5cf80b133..bc192f1ad 100644 --- a/gcc-4.8/gcc/doc/fsf-funding.7 +++ b/gcc-4.8/gcc/doc/fsf-funding.7 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "FSF-FUNDING 7" -.TH FSF-FUNDING 7 "2013-05-31" "gcc-4.8.1" "GNU" +.TH FSF-FUNDING 7 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -133,7 +141,7 @@ fsf\-funding \- Funding Free Software .SH "DESCRIPTION" .IX Header "DESCRIPTION" -.SS "Funding Free Software" +.Sh "Funding Free Software" .IX Subsection "Funding Free Software" If you want to have more free software a few years from now, it makes sense for you to help encourage people to contribute funds for its diff --git a/gcc-4.8/gcc/doc/g++.1 b/gcc-4.8/gcc/doc/g++.1 index 88e400d95..24005b6cc 100644 --- a/gcc-4.8/gcc/doc/g++.1 +++ b/gcc-4.8/gcc/doc/g++.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GCC 1" -.TH GCC 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GCC 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -180,7 +188,7 @@ these have both positive and negative forms; the negative form of only one of these two forms, whichever one is not the default. .SH "OPTIONS" .IX Header "OPTIONS" -.SS "Option Summary" +.Sh "Option Summary" .IX Subsection "Option Summary" Here is a summary of all the options, grouped by type. Explanations are in the following sections. @@ -190,7 +198,7 @@ in the following sections. \&\-pipe \-pass\-exit\-codes \&\-x\fR \fIlanguage\fR \fB\-v \-### \-\-help\fR[\fB=\fR\fIclass\fR[\fB,...\fR]] \fB\-\-target\-help \&\-\-version \-wrapper @\fR\fIfile\fR \fB\-fplugin=\fR\fIfile\fR \fB\-fplugin\-arg\-\fR\fIname\fR\fB=\fR\fIarg\fR -\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \fB\-fada\-spec\-parent=\fR\fIarg\fR \fB\-fdump\-go\-spec=\fR\fIfile\fR +\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \fB\-fada\-spec\-parent=\fR\fIunit\fR \fB\-fdump\-go\-spec=\fR\fIfile\fR .IP "\fIC Language Options\fR" 4 .IX Item "C Language Options" \&\fB\-ansi \-std=\fR\fIstandard\fR \fB\-fgnu89\-inline @@ -867,7 +875,12 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-mno\-recip\-precision \&\-mveclibabi=\fR\fItype\fR \fB\-mfriz \-mno\-friz \&\-mpointers\-to\-nested\-functions \-mno\-pointers\-to\-nested\-functions -\&\-msave\-toc\-indirect \-mno\-save\-toc\-indirect\fR +\&\-msave\-toc\-indirect \-mno\-save\-toc\-indirect +\&\-mpower8\-fusion \-mno\-mpower8\-fusion \-mpower8\-vector \-mno\-power8\-vector +\&\-mcrypto \-mno\-crypto \-mdirect\-move \-mno\-direct\-move +\&\-mquad\-memory \-mno\-quad\-memory +\&\-mquad\-memory\-atomic \-mno\-quad\-memory\-atomic +\&\-mcompat\-align\-parm \-mno\-compat\-align\-parm\fR .Sp \&\fI\s-1RX\s0 Options\fR \&\fB\-m64bit\-doubles \-m32bit\-doubles \-fpu \-nofpu @@ -891,7 +904,8 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-msmall\-exec \-mno\-small\-exec \-mmvcle \-mno\-mvcle \&\-m64 \-m31 \-mdebug \-mno\-debug \-mesa \-mzarch \&\-mtpf\-trace \-mno\-tpf\-trace \-mfused\-madd \-mno\-fused\-madd -\&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard\fR +\&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard +\&\-mhotpatch[=\fR\fIhalfwords\fR\fB] \-mno\-hotpatch\fR .Sp \&\fIScore Options\fR \&\fB\-meb \-mel @@ -936,11 +950,12 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-mhard\-quad\-float \-msoft\-quad\-float \&\-mstack\-bias \-mno\-stack\-bias \&\-munaligned\-doubles \-mno\-unaligned\-doubles +\&\-muser\-mode \-mno\-user\-mode \&\-mv8plus \-mno\-v8plus \-mvis \-mno\-vis \&\-mvis2 \-mno\-vis2 \-mvis3 \-mno\-vis3 \&\-mcbcond \-mno\-cbcond \&\-mfmaf \-mno\-fmaf \-mpopc \-mno\-popc -\&\-mfix\-at697f\fR +\&\-mfix\-at697f \-mfix\-ut699\fR .Sp \&\fI\s-1SPU\s0 Options\fR \&\fB\-mwarn\-reloc \-merror\-reloc @@ -1029,7 +1044,7 @@ See S/390 and zSeries Options. \&\fB\-fstack\-reuse=\fR\fIreuse_level\fR \&\fB\-ftrapv \-fwrapv \-fbounds\-check \&\-fvisibility \-fstrict\-volatile\-bitfields \-fsync\-libcalls\fR -.SS "Options Controlling the Kind of Output" +.Sh "Options Controlling the Kind of Output" .IX Subsection "Options Controlling the Kind of Output" Compilation can involve up to four stages: preprocessing, compilation proper, assembly and linking, always in that order. \s-1GCC\s0 is capable of @@ -1459,8 +1474,11 @@ Define an argument called \fIkey\fR with a value of \fIvalue\fR for the plugin called \fIname\fR. .IP "\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR]" 4 .IX Item "-fdump-ada-spec[-slim]" -For C and \*(C+ source and include files, generate corresponding Ada -specs. +For C and \*(C+ source and include files, generate corresponding Ada specs. +.IP "\fB\-fada\-spec\-parent=\fR\fIunit\fR" 4 +.IX Item "-fada-spec-parent=unit" +In conjunction with \fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] above, generate +Ada specs as child units of parent \fIunit\fR. .IP "\fB\-fdump\-go\-spec=\fR\fIfile\fR" 4 .IX Item "-fdump-go-spec=file" For input files in any language, generate corresponding Go @@ -1481,8 +1499,8 @@ option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The \fIfile\fR may itself contain additional @\fIfile\fR options; any such options will be processed recursively. -.SS "Compiling \*(C+ Programs" -.IX Subsection "Compiling Programs" +.Sh "Compiling \*(C+ Programs" +.IX Subsection "Compiling Programs" \&\*(C+ source files conventionally use one of the suffixes \fB.C\fR, \&\fB.cc\fR, \fB.cpp\fR, \fB.CPP\fR, \fB.c++\fR, \fB.cp\fR, or \&\fB.cxx\fR; \*(C+ header files often use \fB.hh\fR, \fB.hpp\fR, @@ -1505,7 +1523,7 @@ When you compile \*(C+ programs, you may specify many of the same command-line options that you use for compiling programs in any language; or command-line options meaningful for C and related languages; or options that are meaningful only for \*(C+ programs. -.SS "Options Controlling C Dialect" +.Sh "Options Controlling C Dialect" .IX Subsection "Options Controlling C Dialect" The following options control the dialect of C (or languages derived from C, such as \*(C+, Objective-C and Objective\-\*(C+) that the compiler @@ -1892,8 +1910,8 @@ These options control whether a bit-field is signed or unsigned, when the declaration does not use either \f(CW\*(C`signed\*(C'\fR or \f(CW\*(C`unsigned\*(C'\fR. By default, such a bit-field is signed, because this is consistent: the basic integer types such as \f(CW\*(C`int\*(C'\fR are signed types. -.SS "Options Controlling \*(C+ Dialect" -.IX Subsection "Options Controlling Dialect" +.Sh "Options Controlling \*(C+ Dialect" +.IX Subsection "Options Controlling Dialect" This section describes the command-line options that are only meaningful for \*(C+ programs. You can also use most of the \s-1GNU\s0 compiler options regardless of what language your program is in. For example, you @@ -2250,7 +2268,7 @@ Do not assume \fBinline\fR for functions defined inside a class scope. functions have linkage like inline functions; they just aren't inlined by default. .IP "\fB\-Wabi\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 -.IX Item "-Wabi (C, Objective-C, and Objective- only)" +.IX Item "-Wabi (C, Objective-C, and Objective- only)" Warn when G++ generates code that is probably not compatible with the vendor-neutral \*(C+ \s-1ABI\s0. Although an effort has been made to warn about all such cases, there are probably some cases that are not warned about, @@ -2562,7 +2580,7 @@ Warn when overload resolution chooses a promotion from unsigned or enumerated type to a signed type, over a conversion to an unsigned type of the same size. Previous versions of G++ tried to preserve unsignedness, but the standard mandates the current behavior. -.SS "Options Controlling Objective-C and Objective\-\*(C+ Dialects" +.Sh "Options Controlling Objective-C and Objective\-\*(C+ Dialects" .IX Subsection "Options Controlling Objective-C and Objective- Dialects" (\s-1NOTE:\s0 This manual does not describe the Objective-C and Objective\-\*(C+ languages themselves. @@ -2759,7 +2777,7 @@ that methods and selectors must be declared before being used. .IX Item "-print-objc-runtime-info" Generate C header describing the largest structure that is passed by value, if any. -.SS "Options to Control Diagnostic Messages Formatting" +.Sh "Options to Control Diagnostic Messages Formatting" .IX Subsection "Options to Control Diagnostic Messages Formatting" Traditionally, diagnostic messages have been formatted irrespective of the output device's aspect (e.g. its width, ...). You can use the @@ -2800,7 +2818,7 @@ option is known to the diagnostic machinery). Specifying the By default, each diagnostic emitted includes the original source line and a caret '^' indicating the column. This option suppresses this information. -.SS "Options to Request or Suppress Warnings" +.Sh "Options to Request or Suppress Warnings" .IX Subsection "Options to Request or Suppress Warnings" Warnings are diagnostic messages that report constructions that are not inherently erroneous but that are risky or suggest there @@ -3186,7 +3204,7 @@ enabled by default and it is made into an error by Same as \fB\-Wimplicit\-int\fR and \fB\-Wimplicit\-function\-declaration\fR. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wignored\-qualifiers\fR (C and \*(C+ only)" 4 -.IX Item "-Wignored-qualifiers (C and only)" +.IX Item "-Wignored-qualifiers (C and only)" Warn if the return type of a function has a type qualifier such as \f(CW\*(C`const\*(C'\fR. For \s-1ISO\s0 C such a type qualifier has no effect, since the value returned by a function is not an lvalue. @@ -3358,7 +3376,7 @@ between \fB\-Wswitch\fR and this option is that this option gives a warning about an omitted enumeration code even if there is a \&\f(CW\*(C`default\*(C'\fR label. .IP "\fB\-Wsync\-nand\fR (C and \*(C+ only)" 4 -.IX Item "-Wsync-nand (C and only)" +.IX Item "-Wsync-nand (C and only)" Warn when \f(CW\*(C`_\|_sync_fetch_and_nand\*(C'\fR and \f(CW\*(C`_\|_sync_nand_and_fetch\*(C'\fR built-in functions are used. These functions changed semantics in \s-1GCC\s0 4.4. .IP "\fB\-Wtrigraphs\fR" 4 @@ -3397,7 +3415,7 @@ This warning is enabled by \fB\-Wall\fR. .Sp To suppress this warning use the \fBunused\fR attribute. .IP "\fB\-Wunused\-local\-typedefs\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 -.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" +.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" Warn when a typedef locally defined in a function is not used. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wunused\-parameter\fR" 4 @@ -4355,7 +4373,7 @@ a suffix. When used together with \fB\-Wsystem\-headers\fR it warns about such constants in system header files. This can be useful when preparing code to use with the \f(CW\*(C`FLOAT_CONST_DECIMAL64\*(C'\fR pragma from the decimal floating-point extension to C99. -.SS "Options for Debugging Your Program or \s-1GCC\s0" +.Sh "Options for Debugging Your Program or \s-1GCC\s0" .IX Subsection "Options for Debugging Your Program or GCC" \&\s-1GCC\s0 has various special options that are used for debugging either your program or \s-1GCC:\s0 @@ -5859,7 +5877,7 @@ in that compilation unit, for example if, in the debugger, you want to cast a value to a type that is not actually used in your program (but is declared). More often, however, this results in a significant amount of wasted space. -.SS "Options That Control Optimization" +.Sh "Options That Control Optimization" .IX Subsection "Options That Control Optimization" These options control various sorts of optimizations. .PP @@ -8968,7 +8986,7 @@ seeking a basis for a new straight-line strength reduction candidate. .RE .RS 4 .RE -.SS "Options Controlling the Preprocessor" +.Sh "Options Controlling the Preprocessor" .IX Subsection "Options Controlling the Preprocessor" These options control the C preprocessor, which is run on each C source file before actual compilation. @@ -9770,7 +9788,7 @@ header file is printed with \fB...x\fR and a valid one with \fB...!\fR . .PD Print out \s-1GNU\s0 \s-1CPP\s0's version number. With one dash, proceed to preprocess as normal. With two dashes, exit immediately. -.SS "Passing Options to the Assembler" +.Sh "Passing Options to the Assembler" .IX Subsection "Passing Options to the Assembler" You can pass options to the assembler. .IP "\fB\-Wa,\fR\fIoption\fR" 4 @@ -9785,7 +9803,7 @@ recognize. .Sp If you want to pass an option that takes an argument, you must use \&\fB\-Xassembler\fR twice, once for the option and once for the argument. -.SS "Options for Linking" +.Sh "Options for Linking" .IX Subsection "Options for Linking" These options come into play when the compiler links object files into an executable output file. They are meaningless if the compiler is @@ -10024,7 +10042,7 @@ linker. When using the \s-1GNU\s0 linker, you can also get the same effect with Pretend the symbol \fIsymbol\fR is undefined, to force linking of library modules to define it. You can use \fB\-u\fR multiple times with different symbols to force loading of additional library modules. -.SS "Options for Directory Search" +.Sh "Options for Directory Search" .IX Subsection "Options for Directory Search" These options specify directories to search for header files, for libraries and for parts of the compiler: @@ -10159,13 +10177,13 @@ by default, but it is often satisfactory. \&\fB\-I\-\fR does not inhibit the use of the standard system directories for header files. Thus, \fB\-I\-\fR and \fB\-nostdinc\fR are independent. -.SS "Specifying Target Machine and Compiler Version" +.Sh "Specifying Target Machine and Compiler Version" .IX Subsection "Specifying Target Machine and Compiler Version" The usual way to run \s-1GCC\s0 is to run the executable called \fBgcc\fR, or \&\fImachine\fR\fB\-gcc\fR when cross-compiling, or \&\fImachine\fR\fB\-gcc\-\fR\fIversion\fR to run a version other than the one that was installed last. -.SS "Hardware Models and Configurations" +.Sh "Hardware Models and Configurations" .IX Subsection "Hardware Models and Configurations" Each target machine types can have its own special options, starting with \fB\-m\fR, to choose among various @@ -10489,11 +10507,31 @@ order. That is, a byte order of the form \fB32107654\fR. Note: this option should only be used if you require compatibility with code for big-endian \s-1ARM\s0 processors generated by versions of the compiler prior to 2.8. This option is now deprecated. -.IP "\fB\-mcpu=\fR\fIname\fR" 4 -.IX Item "-mcpu=name" -This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name -to determine what kind of instructions it can emit when generating -assembly code. Permissible names are: \fBarm2\fR, \fBarm250\fR, +.IP "\fB\-march=\fR\fIname\fR" 4 +.IX Item "-march=name" +This specifies the name of the target \s-1ARM\s0 architecture. \s-1GCC\s0 uses this +name to determine what kind of instructions it can emit when generating +assembly code. This option can be used in conjunction with or instead +of the \fB\-mcpu=\fR option. Permissible names are: \fBarmv2\fR, +\&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR, +\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5e\fR, \fBarmv5te\fR, +\&\fBarmv6\fR, \fBarmv6j\fR, +\&\fBarmv6t2\fR, \fBarmv6z\fR, \fBarmv6zk\fR, \fBarmv6\-m\fR, +\&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7\-r\fR, \fBarmv7\-m\fR, \fBarmv7e\-m\fR +\&\fBarmv8\-a\fR, +\&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR. +.Sp +\&\fB\-march=native\fR causes the compiler to auto-detect the architecture +of the build computer. At present, this feature is only supported on +Linux, and not all architectures are recognized. If the auto-detect is +unsuccessful the option has no effect. +.IP "\fB\-mtune=\fR\fIname\fR" 4 +.IX Item "-mtune=name" +This option specifies the name of the target \s-1ARM\s0 processor for +which \s-1GCC\s0 should tune the performance of the code. +For some \s-1ARM\s0 implementations better performance can be obtained by using +this option. +Permissible names are: \fBarm2\fR, \fBarm250\fR, \&\fBarm3\fR, \fBarm6\fR, \fBarm60\fR, \fBarm600\fR, \fBarm610\fR, \&\fBarm620\fR, \fBarm7\fR, \fBarm7m\fR, \fBarm7d\fR, \fBarm7dm\fR, \&\fBarm7di\fR, \fBarm7dmi\fR, \fBarm70\fR, \fBarm700\fR, @@ -10521,25 +10559,6 @@ assembly code. Permissible names are: \fBarm2\fR, \fBarm250\fR, \&\fBfa526\fR, \fBfa626\fR, \&\fBfa606te\fR, \fBfa626te\fR, \fBfmp626\fR, \fBfa726te\fR. .Sp -\&\fB\-mcpu=generic\-\fR\fIarch\fR is also permissible, and is -equivalent to \fB\-march=\fR\fIarch\fR \fB\-mtune=generic\-\fR\fIarch\fR. -See \fB\-mtune\fR for more information. -.Sp -\&\fB\-mcpu=native\fR causes the compiler to auto-detect the \s-1CPU\s0 -of the build computer. At present, this feature is only supported on -Linux, and not all architectures are recognized. If the auto-detect is -unsuccessful the option has no effect. -.IP "\fB\-mtune=\fR\fIname\fR" 4 -.IX Item "-mtune=name" -This option is very similar to the \fB\-mcpu=\fR option, except that -instead of specifying the actual target processor type, and hence -restricting which instructions can be used, it specifies that \s-1GCC\s0 should -tune the performance of the code as if the target were of the type -specified in this option, but still choosing the instructions it -generates based on the \s-1CPU\s0 specified by a \fB\-mcpu=\fR option. -For some \s-1ARM\s0 implementations better performance can be obtained by using -this option. -.Sp \&\fB\-mtune=generic\-\fR\fIarch\fR specifies that \s-1GCC\s0 should tune the performance for a blend of processors within architecture \fIarch\fR. The aim is to generate code that run well on the current most popular @@ -10551,21 +10570,23 @@ this option may change in future \s-1GCC\s0 versions as \s-1CPU\s0 models come a of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. -.IP "\fB\-march=\fR\fIname\fR" 4 -.IX Item "-march=name" -This specifies the name of the target \s-1ARM\s0 architecture. \s-1GCC\s0 uses this -name to determine what kind of instructions it can emit when generating -assembly code. This option can be used in conjunction with or instead -of the \fB\-mcpu=\fR option. Permissible names are: \fBarmv2\fR, -\&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR, -\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5e\fR, \fBarmv5te\fR, -\&\fBarmv6\fR, \fBarmv6j\fR, -\&\fBarmv6t2\fR, \fBarmv6z\fR, \fBarmv6zk\fR, \fBarmv6\-m\fR, -\&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7\-r\fR, \fBarmv7\-m\fR, -\&\fBarmv8\-a\fR, -\&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name +to derive the name of the target \s-1ARM\s0 architecture (as if specified +by \fB\-march\fR) and the \s-1ARM\s0 processor type for which to tune for +performance (as if specified by \fB\-mtune\fR). Where this option +is used in conjunction with \fB\-march\fR or \fB\-mtune\fR, +those options take precedence over the appropriate part of this option. .Sp -\&\fB\-march=native\fR causes the compiler to auto-detect the architecture +Permissible names for this option are the same as those for +\&\fB\-mtune\fR. +.Sp +\&\fB\-mcpu=generic\-\fR\fIarch\fR is also permissible, and is +equivalent to \fB\-march=\fR\fIarch\fR \fB\-mtune=generic\-\fR\fIarch\fR. +See \fB\-mtune\fR for more information. +.Sp +\&\fB\-mcpu=native\fR causes the compiler to auto-detect the \s-1CPU\s0 of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. @@ -10649,8 +10670,11 @@ responsible for initializing this register with an appropriate value before execution begins. .IP "\fB\-mpic\-register=\fR\fIreg\fR" 4 .IX Item "-mpic-register=reg" -Specify the register to be used for \s-1PIC\s0 addressing. The default is R10 -unless stack-checking is enabled, when R9 is used. +Specify the register to be used for \s-1PIC\s0 addressing. +For standard \s-1PIC\s0 base case, the default will be any suitable register +determined by compiler. For single \s-1PIC\s0 base case, the default is +\&\fBR9\fR if target is \s-1EABI\s0 based or stack-checking is enabled, +otherwise the default is \fBR10\fR. .IP "\fB\-mpoke\-function\-name\fR" 4 .IX Item "-mpoke-function-name" Write the name of each function into the text section, directly @@ -10805,7 +10829,7 @@ The default for this option is@tie{}\f(CW\*(C`avr2\*(C'\fR. .el .IP "\f(CWavr5\fR" 4 .IX Item "avr5" \&\*(L"Enhanced\*(R" devices with 16@tie{}KiB up to 64@tie{}KiB of program memory. -\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata5790\*(C'\fR, \f(CW\*(C`ata5790n\*(C'\fR, \f(CW\*(C`ata5795\*(C'\fR, \f(CW\*(C`atmega16\*(C'\fR, \f(CW\*(C`atmega16a\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvbrevb\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega161\*(C'\fR, \f(CW\*(C`atmega162\*(C'\fR, \f(CW\*(C`atmega163\*(C'\fR, \f(CW\*(C`atmega164a\*(C'\fR, \f(CW\*(C`atmega164p\*(C'\fR, \f(CW\*(C`atmega164pa\*(C'\fR, \f(CW\*(C`atmega165\*(C'\fR, \f(CW\*(C`atmega165a\*(C'\fR, \f(CW\*(C`atmega165p\*(C'\fR, \f(CW\*(C`atmega165pa\*(C'\fR, \f(CW\*(C`atmega168\*(C'\fR, \f(CW\*(C`atmega168a\*(C'\fR, \f(CW\*(C`atmega168p\*(C'\fR, \f(CW\*(C`atmega168pa\*(C'\fR, \f(CW\*(C`atmega169\*(C'\fR, \f(CW\*(C`atmega169a\*(C'\fR, \f(CW\*(C`atmega169p\*(C'\fR, \f(CW\*(C`atmega169pa\*(C'\fR, \f(CW\*(C`atmega26hvg\*(C'\fR, \f(CW\*(C`atmega32\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvbrevb\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega323\*(C'\fR, \f(CW\*(C`atmega324a\*(C'\fR, \f(CW\*(C`atmega324p\*(C'\fR, \f(CW\*(C`atmega324pa\*(C'\fR, \f(CW\*(C`atmega325\*(C'\fR, \f(CW\*(C`atmega325a\*(C'\fR, \f(CW\*(C`atmega325p\*(C'\fR, \f(CW\*(C`atmega3250\*(C'\fR, \f(CW\*(C`atmega3250a\*(C'\fR, \f(CW\*(C`atmega3250p\*(C'\fR, \f(CW\*(C`atmega3250pa\*(C'\fR, \f(CW\*(C`atmega328\*(C'\fR, \f(CW\*(C`atmega328p\*(C'\fR, \f(CW\*(C`atmega329\*(C'\fR, \f(CW\*(C`atmega329a\*(C'\fR, \f(CW\*(C`atmega329p\*(C'\fR, \f(CW\*(C`atmega329pa\*(C'\fR, \f(CW\*(C`atmega3290\*(C'\fR, \f(CW\*(C`atmega3290a\*(C'\fR, \f(CW\*(C`atmega3290p\*(C'\fR, \f(CW\*(C`atmega3290pa\*(C'\fR, \f(CW\*(C`atmega406\*(C'\fR, \f(CW\*(C`atmega48hvf\*(C'\fR, \f(CW\*(C`atmega64\*(C'\fR, \f(CW\*(C`atmega64a\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64hve\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64rfa2\*(C'\fR, \f(CW\*(C`atmega64rfr2\*(C'\fR, \f(CW\*(C`atmega640\*(C'\fR, \f(CW\*(C`atmega644\*(C'\fR, \f(CW\*(C`atmega644a\*(C'\fR, \f(CW\*(C`atmega644p\*(C'\fR, \f(CW\*(C`atmega644pa\*(C'\fR, \f(CW\*(C`atmega645\*(C'\fR, \f(CW\*(C`atmega645a\*(C'\fR, \f(CW\*(C`atmega645p\*(C'\fR, \f(CW\*(C`atmega6450\*(C'\fR, \f(CW\*(C`atmega6450a\*(C'\fR, \f(CW\*(C`atmega6450p\*(C'\fR, \f(CW\*(C`atmega649\*(C'\fR, \f(CW\*(C`atmega649a\*(C'\fR, \f(CW\*(C`atmega649p\*(C'\fR, \f(CW\*(C`atmega6490\*(C'\fR, \f(CW\*(C`atmega6490a\*(C'\fR, \f(CW\*(C`atmega6490p\*(C'\fR, \f(CW\*(C`at90can32\*(C'\fR, \f(CW\*(C`at90can64\*(C'\fR, \f(CW\*(C`at90pwm161\*(C'\fR, \f(CW\*(C`at90pwm216\*(C'\fR, \f(CW\*(C`at90pwm316\*(C'\fR, \f(CW\*(C`at90scr100\*(C'\fR, \f(CW\*(C`at90usb646\*(C'\fR, \f(CW\*(C`at90usb647\*(C'\fR, \f(CW\*(C`at94k\*(C'\fR, \f(CW\*(C`m3000\*(C'\fR. +\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata5790\*(C'\fR, \f(CW\*(C`ata5790n\*(C'\fR, \f(CW\*(C`ata5795\*(C'\fR, \f(CW\*(C`atmega16\*(C'\fR, \f(CW\*(C`atmega16a\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvbrevb\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega161\*(C'\fR, \f(CW\*(C`atmega162\*(C'\fR, \f(CW\*(C`atmega163\*(C'\fR, \f(CW\*(C`atmega164a\*(C'\fR, \f(CW\*(C`atmega164p\*(C'\fR, \f(CW\*(C`atmega164pa\*(C'\fR, \f(CW\*(C`atmega165\*(C'\fR, \f(CW\*(C`atmega165a\*(C'\fR, \f(CW\*(C`atmega165p\*(C'\fR, \f(CW\*(C`atmega165pa\*(C'\fR, \f(CW\*(C`atmega168\*(C'\fR, \f(CW\*(C`atmega168a\*(C'\fR, \f(CW\*(C`atmega168p\*(C'\fR, \f(CW\*(C`atmega168pa\*(C'\fR, \f(CW\*(C`atmega169\*(C'\fR, \f(CW\*(C`atmega169a\*(C'\fR, \f(CW\*(C`atmega169p\*(C'\fR, \f(CW\*(C`atmega169pa\*(C'\fR, \f(CW\*(C`atmega26hvg\*(C'\fR, \f(CW\*(C`atmega32\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvbrevb\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega323\*(C'\fR, \f(CW\*(C`atmega324a\*(C'\fR, \f(CW\*(C`atmega324p\*(C'\fR, \f(CW\*(C`atmega324pa\*(C'\fR, \f(CW\*(C`atmega325\*(C'\fR, \f(CW\*(C`atmega325a\*(C'\fR, \f(CW\*(C`atmega325p\*(C'\fR, \f(CW\*(C`atmega3250\*(C'\fR, \f(CW\*(C`atmega3250a\*(C'\fR, \f(CW\*(C`atmega3250p\*(C'\fR, \f(CW\*(C`atmega3250pa\*(C'\fR, \f(CW\*(C`atmega328\*(C'\fR, \f(CW\*(C`atmega328p\*(C'\fR, \f(CW\*(C`atmega329\*(C'\fR, \f(CW\*(C`atmega329a\*(C'\fR, \f(CW\*(C`atmega329p\*(C'\fR, \f(CW\*(C`atmega329pa\*(C'\fR, \f(CW\*(C`atmega3290\*(C'\fR, \f(CW\*(C`atmega3290a\*(C'\fR, \f(CW\*(C`atmega3290p\*(C'\fR, \f(CW\*(C`atmega3290pa\*(C'\fR, \f(CW\*(C`atmega406\*(C'\fR, \f(CW\*(C`atmega48hvf\*(C'\fR, \f(CW\*(C`atmega64\*(C'\fR, \f(CW\*(C`atmega64a\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64hve\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64rfa2\*(C'\fR, \f(CW\*(C`atmega64rfr2\*(C'\fR, \f(CW\*(C`atmega640\*(C'\fR, \f(CW\*(C`atmega644\*(C'\fR, \f(CW\*(C`atmega644a\*(C'\fR, \f(CW\*(C`atmega644p\*(C'\fR, \f(CW\*(C`atmega644pa\*(C'\fR, \f(CW\*(C`atmega645\*(C'\fR, \f(CW\*(C`atmega645a\*(C'\fR, \f(CW\*(C`atmega645p\*(C'\fR, \f(CW\*(C`atmega6450\*(C'\fR, \f(CW\*(C`atmega6450a\*(C'\fR, \f(CW\*(C`atmega6450p\*(C'\fR, \f(CW\*(C`atmega649\*(C'\fR, \f(CW\*(C`atmega649a\*(C'\fR, \f(CW\*(C`atmega649p\*(C'\fR, \f(CW\*(C`atmega6490\*(C'\fR, \f(CW\*(C`atmega6490a\*(C'\fR, \f(CW\*(C`atmega6490p\*(C'\fR, \f(CW\*(C`at90can32\*(C'\fR, \f(CW\*(C`at90can64\*(C'\fR, \f(CW\*(C`at90pwm161\*(C'\fR, \f(CW\*(C`at90pwm216\*(C'\fR, \f(CW\*(C`at90pwm316\*(C'\fR, \f(CW\*(C`at90scr100\*(C'\fR, \f(CW\*(C`at90usb646\*(C'\fR, \f(CW\*(C`at90usb647\*(C'\fR, \f(CW\*(C`at94k\*(C'\fR, \f(CW\*(C`m3000\*(C'\fR. .ie n .IP """avr51""" 4 .el .IP "\f(CWavr51\fR" 4 .IX Item "avr51" @@ -11043,7 +11067,7 @@ command-line option. .IX Item "-<Switch/case dispatch tables. If you do not want such dispatch>" tables you can specify the \fB\-fno\-jump\-tables\fR command-line option. .IP "\-<C and \*(C+ constructors/destructors called during startup/shutdown.>" 4 -.IX Item "-<C and constructors/destructors called during startup/shutdown.>" +.IX Item "-<C and constructors/destructors called during startup/shutdown.>" .PD 0 .ie n .IP "\-<If the tools hit a ""gs()"" modifier explained above.>" 4 .el .IP "\-<If the tools hit a \f(CWgs()\fR modifier explained above.>" 4 @@ -11790,7 +11814,7 @@ an executable when linking, using the Darwin \fIlibtool\fR command. This causes \s-1GCC\s0's output file to have the \fI\s-1ALL\s0\fR subtype, instead of one controlled by the \fB\-mcpu\fR or \fB\-march\fR option. .IP "\fB\-allowable_client\fR \fIclient_name\fR" 4 -.IX Item "-allowable_client client_name" +.IX Item "-allowable_client client_name" .PD 0 .IP "\fB\-client_name\fR" 4 .IX Item "-client_name" @@ -12865,9 +12889,14 @@ Intel Core i7 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SS Intel Core \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0 and F16C instruction set support. +.IP "\fBcore\-avx2\fR" 4 +.IX Item "core-avx2" +Intel Core \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AVX2\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, \s-1FMA\s0, \s-1BMI\s0, \s-1BMI2\s0 +and F16C instruction set support. .IP "\fBatom\fR" 4 .IX Item "atom" -Intel Atom \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 +Intel Atom \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 instruction set support. .IP "\fBk6\fR" 4 .IX Item "k6" @@ -16284,7 +16313,9 @@ following options: \&\fB\-maltivec \-mfprnd \-mhard\-float \-mmfcrf \-mmultiple \&\-mpopcntb \-mpopcntd \-mpowerpc64 \&\-mpowerpc\-gpopt \-mpowerpc\-gfxopt \-msingle\-float \-mdouble\-float -\&\-msimple\-fpu \-mstring \-mmulhw \-mdlmzb \-mmfpgpr \-mvsx\fR +\&\-msimple\-fpu \-mstring \-mmulhw \-mdlmzb \-mmfpgpr \-mvsx +\&\-mcrypto \-mdirect\-move \-mpower8\-fusion \-mpower8\-vector +\&\-mquad\-memory \-mquad\-memory\-atomic\fR .Sp The particular options set for any particular \s-1CPU\s0 varies between compiler versions, depending on what setting seems to produce optimal @@ -16331,6 +16362,36 @@ enable the use of built-in functions that allow more direct access to the AltiVec instruction set. You may also need to set \&\fB\-mabi=altivec\fR to adjust the current \s-1ABI\s0 with AltiVec \s-1ABI\s0 enhancements. +.Sp +When \fB\-maltivec\fR is used, rather than \fB\-maltivec=le\fR or +\&\fB\-maltivec=be\fR, the element order for Altivec intrinsics such +as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and \f(CW\*(C`vec_insert\*(C'\fR will +match array element order corresponding to the endianness of the +target. That is, element zero identifies the leftmost element in a +vector register when targeting a big-endian platform, and identifies +the rightmost element in a vector register when targeting a +little-endian platform. +.IP "\fB\-maltivec=be\fR" 4 +.IX Item "-maltivec=be" +Generate Altivec instructions using big-endian element order, +regardless of whether the target is big\- or little-endian. This is +the default when targeting a big-endian platform. +.Sp +The element order is used to interpret element numbers in Altivec +intrinsics such as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and +\&\f(CW\*(C`vec_insert\*(C'\fR. By default, these will match array element order +corresponding to the endianness for the target. +.IP "\fB\-maltivec=le\fR" 4 +.IX Item "-maltivec=le" +Generate Altivec instructions using little-endian element order, +regardless of whether the target is big\- or little-endian. This is +the default when targeting a little-endian platform. This option is +currently ignored when targeting a big-endian platform. +.Sp +The element order is used to interpret element numbers in Altivec +intrinsics such as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and +\&\f(CW\*(C`vec_insert\*(C'\fR. By default, these will match array element order +corresponding to the endianness for the target. .IP "\fB\-mvrsave\fR" 4 .IX Item "-mvrsave" .PD 0 @@ -16399,6 +16460,61 @@ This option has been deprecated. Use \fB\-mspe\fR and Generate code that uses (does not use) vector/scalar (\s-1VSX\s0) instructions, and also enable the use of built-in functions that allow more direct access to the \s-1VSX\s0 instruction set. +.IP "\fB\-mcrypto\fR" 4 +.IX Item "-mcrypto" +.PD 0 +.IP "\fB\-mno\-crypto\fR" 4 +.IX Item "-mno-crypto" +.PD +Enable the use (disable) of the built-in functions that allow direct +access to the cryptographic instructions that were added in version +2.07 of the PowerPC \s-1ISA\s0. +.IP "\fB\-mdirect\-move\fR" 4 +.IX Item "-mdirect-move" +.PD 0 +.IP "\fB\-mno\-direct\-move\fR" 4 +.IX Item "-mno-direct-move" +.PD +Generate code that uses (does not use) the instructions to move data +between the general purpose registers and the vector/scalar (\s-1VSX\s0) +registers that were added in version 2.07 of the PowerPC \s-1ISA\s0. +.IP "\fB\-mpower8\-fusion\fR" 4 +.IX Item "-mpower8-fusion" +.PD 0 +.IP "\fB\-mno\-power8\-fusion\fR" 4 +.IX Item "-mno-power8-fusion" +.PD +Generate code that keeps (does not keeps) some integer operations +adjacent so that the instructions can be fused together on power8 and +later processors. +.IP "\fB\-mpower8\-vector\fR" 4 +.IX Item "-mpower8-vector" +.PD 0 +.IP "\fB\-mno\-power8\-vector\fR" 4 +.IX Item "-mno-power8-vector" +.PD +Generate code that uses (does not use) the vector and scalar +instructions that were added in version 2.07 of the PowerPC \s-1ISA\s0. Also +enable the use of built-in functions that allow more direct access to +the vector instructions. +.IP "\fB\-mquad\-memory\fR" 4 +.IX Item "-mquad-memory" +.PD 0 +.IP "\fB\-mno\-quad\-memory\fR" 4 +.IX Item "-mno-quad-memory" +.PD +Generate code that uses (does not use) the non-atomic quad word memory +instructions. The \fB\-mquad\-memory\fR option requires use of +64\-bit mode. +.IP "\fB\-mquad\-memory\-atomic\fR" 4 +.IX Item "-mquad-memory-atomic" +.PD 0 +.IP "\fB\-mno\-quad\-memory\-atomic\fR" 4 +.IX Item "-mno-quad-memory-atomic" +.PD +Generate code that uses (does not use) the atomic quad word memory +instructions. The \fB\-mquad\-memory\-atomic\fR option requires use of +64\-bit mode. .IP "\fB\-mfloat\-gprs=\fR\fIyes/single/double/no\fR" 4 .IX Item "-mfloat-gprs=yes/single/double/no" .PD 0 @@ -16828,7 +16944,8 @@ Return structures smaller than 8 bytes in registers (as specified by the .IX Item "-mabi=abi-type" Extend the current \s-1ABI\s0 with a particular extension, or remove such extension. Valid values are \fIaltivec\fR, \fIno-altivec\fR, \fIspe\fR, -\&\fIno-spe\fR, \fIibmlongdouble\fR, \fIieeelongdouble\fR. +\&\fIno-spe\fR, \fIibmlongdouble\fR, \fIieeelongdouble\fR, +\&\fIelfv1\fR, \fIelfv2\fR. .IP "\fB\-mabi=spe\fR" 4 .IX Item "-mabi=spe" Extend the current \s-1ABI\s0 with \s-1SPE\s0 \s-1ABI\s0 extensions. This does not change @@ -16845,6 +16962,18 @@ This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. .IX Item "-mabi=ieeelongdouble" Change the current \s-1ABI\s0 to use \s-1IEEE\s0 extended-precision long double. This is a PowerPC 32\-bit Linux \s-1ABI\s0 option. +.IP "\fB\-mabi=elfv1\fR" 4 +.IX Item "-mabi=elfv1" +Change the current \s-1ABI\s0 to use the ELFv1 \s-1ABI\s0. +This is the default \s-1ABI\s0 for big-endian PowerPC 64\-bit Linux. +Overriding the default \s-1ABI\s0 requires special system support and is +likely to fail in spectacular ways. +.IP "\fB\-mabi=elfv2\fR" 4 +.IX Item "-mabi=elfv2" +Change the current \s-1ABI\s0 to use the ELFv2 \s-1ABI\s0. +This is the default \s-1ABI\s0 for little-endian PowerPC 64\-bit Linux. +Overriding the default \s-1ABI\s0 requires special system support and is +likely to fail in spectacular ways. .IP "\fB\-mprototype\fR" 4 .IX Item "-mprototype" .PD 0 @@ -17132,6 +17261,25 @@ stack location in the function prologue if the function calls through a pointer on \s-1AIX\s0 and 64\-bit Linux systems. If the \s-1TOC\s0 value is not saved in the prologue, it is saved just before the call through the pointer. The \fB\-mno\-save\-toc\-indirect\fR option is the default. +.IP "\fB\-mcompat\-align\-parm\fR" 4 +.IX Item "-mcompat-align-parm" +.PD 0 +.IP "\fB\-mno\-compat\-align\-parm\fR" 4 +.IX Item "-mno-compat-align-parm" +.PD +Generate (do not generate) code to pass structure parameters with a +maximum alignment of 64 bits, for compatibility with older versions +of \s-1GCC\s0. +.Sp +Older versions of \s-1GCC\s0 (prior to 4.9.0) incorrectly did not align a +structure parameter on a 128\-bit boundary when that structure contained +a member requiring 128\-bit alignment. This is corrected in more +recent versions of \s-1GCC\s0. This option may be used to generate code +that is compatible with functions compiled with older versions of +\&\s-1GCC\s0. +.Sp +In this version of the compiler, the \fB\-mcompat\-align\-parm\fR +is the default, except when using the Linux ELFv2 \s-1ABI\s0. .PP \fI\s-1RX\s0 Options\fR .IX Subsection "RX Options" @@ -17514,6 +17662,23 @@ values have to be exact powers of 2 and \fIstack-size\fR has to be greater than In order to be efficient the extra code makes the assumption that the stack starts at an address aligned to the value given by \fIstack-size\fR. The \fIstack-guard\fR option can only be used in conjunction with \fIstack-size\fR. +.IP "\fB\-mhotpatch[=\fR\fIhalfwords\fR\fB]\fR" 4 +.IX Item "-mhotpatch[=halfwords]" +.PD 0 +.IP "\fB\-mno\-hotpatch\fR" 4 +.IX Item "-mno-hotpatch" +.PD +If the hotpatch option is enabled, a \*(L"hot-patching\*(R" function +prologue is generated for all functions in the compilation unit. +The funtion label is prepended with the given number of two-byte +Nop instructions (\fIhalfwords\fR, maximum 1000000) or 12 Nop +instructions if no argument is present. Functions with a +hot-patching prologue are never inlined automatically, and a +hot-patching prologue is never generated for functions functions +that are explicitly inline. +.Sp +This option can be overridden for individual functions with the +\&\f(CW\*(C`hotpatch\*(C'\fR attribute. .PP \fIScore Options\fR .IX Subsection "Score Options" @@ -18039,8 +18204,9 @@ These \fB\-m\fR options are supported on the \s-1SPARC:\s0 .IX Item "-mapp-regs" .PD Specify \fB\-mapp\-regs\fR to generate output using the global registers -2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. This -is the default. +2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. Like the +global register 1, each global register 2 through 4 is then treated as an +allocable register that is clobbered by function calls. This is the default. .Sp To be fully \s-1SVR4\s0 ABI-compliant at the cost of some performance loss, specify \fB\-mno\-app\-regs\fR. You should compile libraries and system @@ -18116,6 +18282,15 @@ absolute address. Otherwise, it assumes they have 4\-byte alignment. Specifying this option avoids some rare compatibility problems with code generated by other compilers. It is not the default because it results in a performance loss, especially for floating-point code. +.IP "\fB\-muser\-mode\fR" 4 +.IX Item "-muser-mode" +.PD 0 +.IP "\fB\-mno\-user\-mode\fR" 4 +.IX Item "-mno-user-mode" +.PD +Do not generate code that can only run in supervisor mode. This is relevant +only for the \f(CW\*(C`casa\*(C'\fR instruction emitted for the \s-1LEON3\s0 processor. The +default is \fB\-mno\-user\-mode\fR. .IP "\fB\-mno\-faster\-structs\fR" 4 .IX Item "-mno-faster-structs" .PD 0 @@ -18135,10 +18310,10 @@ the rules of the \s-1ABI\s0. Set the instruction set, register set, and instruction scheduling parameters for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are \&\fBv7\fR, \fBcypress\fR, \fBv8\fR, \fBsupersparc\fR, \fBhypersparc\fR, -\&\fBleon\fR, \fBsparclite\fR, \fBf930\fR, \fBf934\fR, \fBsparclite86x\fR, -\&\fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, \fBultrasparc\fR, -\&\fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR, -and \fBniagara4\fR. +\&\fBleon\fR, \fBleon3\fR, \fBsparclite\fR, \fBf930\fR, \fBf934\fR, +\&\fBsparclite86x\fR, \fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, +\&\fBultrasparc\fR, \fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, +\&\fBniagara3\fR and \fBniagara4\fR. .Sp Native Solaris and GNU/Linux toolchains also support the value \fBnative\fR, which selects the best architecture option for the host processor. @@ -18157,7 +18332,7 @@ implementations. cypress .IP "v8" 4 .IX Item "v8" -supersparc, hypersparc, leon +supersparc, hypersparc, leon, leon3 .IP "sparclite" 4 .IX Item "sparclite" f930, f934, sparclite86x @@ -18220,10 +18395,11 @@ option \fB\-mcpu=\fR\fIcpu_type\fR does. The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for \&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those that select a particular \s-1CPU\s0 implementation. Those are \fBcypress\fR, -\&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBf930\fR, \fBf934\fR, -\&\fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, \fBultrasparc3\fR, -\&\fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR and \fBniagara4\fR. With -native Solaris and GNU/Linux toolchains, \fBnative\fR can also be used. +\&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBleon3\fR, \fBf930\fR, +\&\fBf934\fR, \fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, +\&\fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR and +\&\fBniagara4\fR. With native Solaris and GNU/Linux toolchains, \fBnative\fR +can also be used. .IP "\fB\-mv8plus\fR" 4 .IX Item "-mv8plus" .PD 0 @@ -18298,6 +18474,10 @@ later. .IX Item "-mfix-at697f" Enable the documented workaround for the single erratum of the Atmel \s-1AT697F\s0 processor (which corresponds to erratum #13 of the \s-1AT697E\s0 processor). +.IP "\fB\-mfix\-ut699\fR" 4 +.IX Item "-mfix-ut699" +Enable the documented workarounds for the floating-point errata and the data +cache nullify errata of the \s-1UT699\s0 processor. .PP These \fB\-m\fR options are supported in addition to the above on \s-1SPARC\-V9\s0 processors in 64\-bit environments: @@ -18977,7 +19157,7 @@ every cross-file call, not just those that really are out of range. .IX Subsection "zSeries Options" .PP These are listed under -.SS "Options for Code Generation Conventions" +.Sh "Options for Code Generation Conventions" .IX Subsection "Options for Code Generation Conventions" These machine-independent options control the interface conventions used in code generation. diff --git a/gcc-4.8/gcc/doc/gc-analyze.1 b/gcc-4.8/gcc/doc/gc-analyze.1 index b996198bd..c149d2ad1 100644 --- a/gcc-4.8/gcc/doc/gc-analyze.1 +++ b/gcc-4.8/gcc/doc/gc-analyze.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GC-ANALYZE 1" -.TH GC-ANALYZE 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GC-ANALYZE 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/gcc.1 b/gcc-4.8/gcc/doc/gcc.1 index 88e400d95..24005b6cc 100644 --- a/gcc-4.8/gcc/doc/gcc.1 +++ b/gcc-4.8/gcc/doc/gcc.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GCC 1" -.TH GCC 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GCC 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -180,7 +188,7 @@ these have both positive and negative forms; the negative form of only one of these two forms, whichever one is not the default. .SH "OPTIONS" .IX Header "OPTIONS" -.SS "Option Summary" +.Sh "Option Summary" .IX Subsection "Option Summary" Here is a summary of all the options, grouped by type. Explanations are in the following sections. @@ -190,7 +198,7 @@ in the following sections. \&\-pipe \-pass\-exit\-codes \&\-x\fR \fIlanguage\fR \fB\-v \-### \-\-help\fR[\fB=\fR\fIclass\fR[\fB,...\fR]] \fB\-\-target\-help \&\-\-version \-wrapper @\fR\fIfile\fR \fB\-fplugin=\fR\fIfile\fR \fB\-fplugin\-arg\-\fR\fIname\fR\fB=\fR\fIarg\fR -\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \fB\-fada\-spec\-parent=\fR\fIarg\fR \fB\-fdump\-go\-spec=\fR\fIfile\fR +\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \fB\-fada\-spec\-parent=\fR\fIunit\fR \fB\-fdump\-go\-spec=\fR\fIfile\fR .IP "\fIC Language Options\fR" 4 .IX Item "C Language Options" \&\fB\-ansi \-std=\fR\fIstandard\fR \fB\-fgnu89\-inline @@ -867,7 +875,12 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-mno\-recip\-precision \&\-mveclibabi=\fR\fItype\fR \fB\-mfriz \-mno\-friz \&\-mpointers\-to\-nested\-functions \-mno\-pointers\-to\-nested\-functions -\&\-msave\-toc\-indirect \-mno\-save\-toc\-indirect\fR +\&\-msave\-toc\-indirect \-mno\-save\-toc\-indirect +\&\-mpower8\-fusion \-mno\-mpower8\-fusion \-mpower8\-vector \-mno\-power8\-vector +\&\-mcrypto \-mno\-crypto \-mdirect\-move \-mno\-direct\-move +\&\-mquad\-memory \-mno\-quad\-memory +\&\-mquad\-memory\-atomic \-mno\-quad\-memory\-atomic +\&\-mcompat\-align\-parm \-mno\-compat\-align\-parm\fR .Sp \&\fI\s-1RX\s0 Options\fR \&\fB\-m64bit\-doubles \-m32bit\-doubles \-fpu \-nofpu @@ -891,7 +904,8 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-msmall\-exec \-mno\-small\-exec \-mmvcle \-mno\-mvcle \&\-m64 \-m31 \-mdebug \-mno\-debug \-mesa \-mzarch \&\-mtpf\-trace \-mno\-tpf\-trace \-mfused\-madd \-mno\-fused\-madd -\&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard\fR +\&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard +\&\-mhotpatch[=\fR\fIhalfwords\fR\fB] \-mno\-hotpatch\fR .Sp \&\fIScore Options\fR \&\fB\-meb \-mel @@ -936,11 +950,12 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-mhard\-quad\-float \-msoft\-quad\-float \&\-mstack\-bias \-mno\-stack\-bias \&\-munaligned\-doubles \-mno\-unaligned\-doubles +\&\-muser\-mode \-mno\-user\-mode \&\-mv8plus \-mno\-v8plus \-mvis \-mno\-vis \&\-mvis2 \-mno\-vis2 \-mvis3 \-mno\-vis3 \&\-mcbcond \-mno\-cbcond \&\-mfmaf \-mno\-fmaf \-mpopc \-mno\-popc -\&\-mfix\-at697f\fR +\&\-mfix\-at697f \-mfix\-ut699\fR .Sp \&\fI\s-1SPU\s0 Options\fR \&\fB\-mwarn\-reloc \-merror\-reloc @@ -1029,7 +1044,7 @@ See S/390 and zSeries Options. \&\fB\-fstack\-reuse=\fR\fIreuse_level\fR \&\fB\-ftrapv \-fwrapv \-fbounds\-check \&\-fvisibility \-fstrict\-volatile\-bitfields \-fsync\-libcalls\fR -.SS "Options Controlling the Kind of Output" +.Sh "Options Controlling the Kind of Output" .IX Subsection "Options Controlling the Kind of Output" Compilation can involve up to four stages: preprocessing, compilation proper, assembly and linking, always in that order. \s-1GCC\s0 is capable of @@ -1459,8 +1474,11 @@ Define an argument called \fIkey\fR with a value of \fIvalue\fR for the plugin called \fIname\fR. .IP "\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR]" 4 .IX Item "-fdump-ada-spec[-slim]" -For C and \*(C+ source and include files, generate corresponding Ada -specs. +For C and \*(C+ source and include files, generate corresponding Ada specs. +.IP "\fB\-fada\-spec\-parent=\fR\fIunit\fR" 4 +.IX Item "-fada-spec-parent=unit" +In conjunction with \fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] above, generate +Ada specs as child units of parent \fIunit\fR. .IP "\fB\-fdump\-go\-spec=\fR\fIfile\fR" 4 .IX Item "-fdump-go-spec=file" For input files in any language, generate corresponding Go @@ -1481,8 +1499,8 @@ option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The \fIfile\fR may itself contain additional @\fIfile\fR options; any such options will be processed recursively. -.SS "Compiling \*(C+ Programs" -.IX Subsection "Compiling Programs" +.Sh "Compiling \*(C+ Programs" +.IX Subsection "Compiling Programs" \&\*(C+ source files conventionally use one of the suffixes \fB.C\fR, \&\fB.cc\fR, \fB.cpp\fR, \fB.CPP\fR, \fB.c++\fR, \fB.cp\fR, or \&\fB.cxx\fR; \*(C+ header files often use \fB.hh\fR, \fB.hpp\fR, @@ -1505,7 +1523,7 @@ When you compile \*(C+ programs, you may specify many of the same command-line options that you use for compiling programs in any language; or command-line options meaningful for C and related languages; or options that are meaningful only for \*(C+ programs. -.SS "Options Controlling C Dialect" +.Sh "Options Controlling C Dialect" .IX Subsection "Options Controlling C Dialect" The following options control the dialect of C (or languages derived from C, such as \*(C+, Objective-C and Objective\-\*(C+) that the compiler @@ -1892,8 +1910,8 @@ These options control whether a bit-field is signed or unsigned, when the declaration does not use either \f(CW\*(C`signed\*(C'\fR or \f(CW\*(C`unsigned\*(C'\fR. By default, such a bit-field is signed, because this is consistent: the basic integer types such as \f(CW\*(C`int\*(C'\fR are signed types. -.SS "Options Controlling \*(C+ Dialect" -.IX Subsection "Options Controlling Dialect" +.Sh "Options Controlling \*(C+ Dialect" +.IX Subsection "Options Controlling Dialect" This section describes the command-line options that are only meaningful for \*(C+ programs. You can also use most of the \s-1GNU\s0 compiler options regardless of what language your program is in. For example, you @@ -2250,7 +2268,7 @@ Do not assume \fBinline\fR for functions defined inside a class scope. functions have linkage like inline functions; they just aren't inlined by default. .IP "\fB\-Wabi\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 -.IX Item "-Wabi (C, Objective-C, and Objective- only)" +.IX Item "-Wabi (C, Objective-C, and Objective- only)" Warn when G++ generates code that is probably not compatible with the vendor-neutral \*(C+ \s-1ABI\s0. Although an effort has been made to warn about all such cases, there are probably some cases that are not warned about, @@ -2562,7 +2580,7 @@ Warn when overload resolution chooses a promotion from unsigned or enumerated type to a signed type, over a conversion to an unsigned type of the same size. Previous versions of G++ tried to preserve unsignedness, but the standard mandates the current behavior. -.SS "Options Controlling Objective-C and Objective\-\*(C+ Dialects" +.Sh "Options Controlling Objective-C and Objective\-\*(C+ Dialects" .IX Subsection "Options Controlling Objective-C and Objective- Dialects" (\s-1NOTE:\s0 This manual does not describe the Objective-C and Objective\-\*(C+ languages themselves. @@ -2759,7 +2777,7 @@ that methods and selectors must be declared before being used. .IX Item "-print-objc-runtime-info" Generate C header describing the largest structure that is passed by value, if any. -.SS "Options to Control Diagnostic Messages Formatting" +.Sh "Options to Control Diagnostic Messages Formatting" .IX Subsection "Options to Control Diagnostic Messages Formatting" Traditionally, diagnostic messages have been formatted irrespective of the output device's aspect (e.g. its width, ...). You can use the @@ -2800,7 +2818,7 @@ option is known to the diagnostic machinery). Specifying the By default, each diagnostic emitted includes the original source line and a caret '^' indicating the column. This option suppresses this information. -.SS "Options to Request or Suppress Warnings" +.Sh "Options to Request or Suppress Warnings" .IX Subsection "Options to Request or Suppress Warnings" Warnings are diagnostic messages that report constructions that are not inherently erroneous but that are risky or suggest there @@ -3186,7 +3204,7 @@ enabled by default and it is made into an error by Same as \fB\-Wimplicit\-int\fR and \fB\-Wimplicit\-function\-declaration\fR. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wignored\-qualifiers\fR (C and \*(C+ only)" 4 -.IX Item "-Wignored-qualifiers (C and only)" +.IX Item "-Wignored-qualifiers (C and only)" Warn if the return type of a function has a type qualifier such as \f(CW\*(C`const\*(C'\fR. For \s-1ISO\s0 C such a type qualifier has no effect, since the value returned by a function is not an lvalue. @@ -3358,7 +3376,7 @@ between \fB\-Wswitch\fR and this option is that this option gives a warning about an omitted enumeration code even if there is a \&\f(CW\*(C`default\*(C'\fR label. .IP "\fB\-Wsync\-nand\fR (C and \*(C+ only)" 4 -.IX Item "-Wsync-nand (C and only)" +.IX Item "-Wsync-nand (C and only)" Warn when \f(CW\*(C`_\|_sync_fetch_and_nand\*(C'\fR and \f(CW\*(C`_\|_sync_nand_and_fetch\*(C'\fR built-in functions are used. These functions changed semantics in \s-1GCC\s0 4.4. .IP "\fB\-Wtrigraphs\fR" 4 @@ -3397,7 +3415,7 @@ This warning is enabled by \fB\-Wall\fR. .Sp To suppress this warning use the \fBunused\fR attribute. .IP "\fB\-Wunused\-local\-typedefs\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 -.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" +.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" Warn when a typedef locally defined in a function is not used. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wunused\-parameter\fR" 4 @@ -4355,7 +4373,7 @@ a suffix. When used together with \fB\-Wsystem\-headers\fR it warns about such constants in system header files. This can be useful when preparing code to use with the \f(CW\*(C`FLOAT_CONST_DECIMAL64\*(C'\fR pragma from the decimal floating-point extension to C99. -.SS "Options for Debugging Your Program or \s-1GCC\s0" +.Sh "Options for Debugging Your Program or \s-1GCC\s0" .IX Subsection "Options for Debugging Your Program or GCC" \&\s-1GCC\s0 has various special options that are used for debugging either your program or \s-1GCC:\s0 @@ -5859,7 +5877,7 @@ in that compilation unit, for example if, in the debugger, you want to cast a value to a type that is not actually used in your program (but is declared). More often, however, this results in a significant amount of wasted space. -.SS "Options That Control Optimization" +.Sh "Options That Control Optimization" .IX Subsection "Options That Control Optimization" These options control various sorts of optimizations. .PP @@ -8968,7 +8986,7 @@ seeking a basis for a new straight-line strength reduction candidate. .RE .RS 4 .RE -.SS "Options Controlling the Preprocessor" +.Sh "Options Controlling the Preprocessor" .IX Subsection "Options Controlling the Preprocessor" These options control the C preprocessor, which is run on each C source file before actual compilation. @@ -9770,7 +9788,7 @@ header file is printed with \fB...x\fR and a valid one with \fB...!\fR . .PD Print out \s-1GNU\s0 \s-1CPP\s0's version number. With one dash, proceed to preprocess as normal. With two dashes, exit immediately. -.SS "Passing Options to the Assembler" +.Sh "Passing Options to the Assembler" .IX Subsection "Passing Options to the Assembler" You can pass options to the assembler. .IP "\fB\-Wa,\fR\fIoption\fR" 4 @@ -9785,7 +9803,7 @@ recognize. .Sp If you want to pass an option that takes an argument, you must use \&\fB\-Xassembler\fR twice, once for the option and once for the argument. -.SS "Options for Linking" +.Sh "Options for Linking" .IX Subsection "Options for Linking" These options come into play when the compiler links object files into an executable output file. They are meaningless if the compiler is @@ -10024,7 +10042,7 @@ linker. When using the \s-1GNU\s0 linker, you can also get the same effect with Pretend the symbol \fIsymbol\fR is undefined, to force linking of library modules to define it. You can use \fB\-u\fR multiple times with different symbols to force loading of additional library modules. -.SS "Options for Directory Search" +.Sh "Options for Directory Search" .IX Subsection "Options for Directory Search" These options specify directories to search for header files, for libraries and for parts of the compiler: @@ -10159,13 +10177,13 @@ by default, but it is often satisfactory. \&\fB\-I\-\fR does not inhibit the use of the standard system directories for header files. Thus, \fB\-I\-\fR and \fB\-nostdinc\fR are independent. -.SS "Specifying Target Machine and Compiler Version" +.Sh "Specifying Target Machine and Compiler Version" .IX Subsection "Specifying Target Machine and Compiler Version" The usual way to run \s-1GCC\s0 is to run the executable called \fBgcc\fR, or \&\fImachine\fR\fB\-gcc\fR when cross-compiling, or \&\fImachine\fR\fB\-gcc\-\fR\fIversion\fR to run a version other than the one that was installed last. -.SS "Hardware Models and Configurations" +.Sh "Hardware Models and Configurations" .IX Subsection "Hardware Models and Configurations" Each target machine types can have its own special options, starting with \fB\-m\fR, to choose among various @@ -10489,11 +10507,31 @@ order. That is, a byte order of the form \fB32107654\fR. Note: this option should only be used if you require compatibility with code for big-endian \s-1ARM\s0 processors generated by versions of the compiler prior to 2.8. This option is now deprecated. -.IP "\fB\-mcpu=\fR\fIname\fR" 4 -.IX Item "-mcpu=name" -This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name -to determine what kind of instructions it can emit when generating -assembly code. Permissible names are: \fBarm2\fR, \fBarm250\fR, +.IP "\fB\-march=\fR\fIname\fR" 4 +.IX Item "-march=name" +This specifies the name of the target \s-1ARM\s0 architecture. \s-1GCC\s0 uses this +name to determine what kind of instructions it can emit when generating +assembly code. This option can be used in conjunction with or instead +of the \fB\-mcpu=\fR option. Permissible names are: \fBarmv2\fR, +\&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR, +\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5e\fR, \fBarmv5te\fR, +\&\fBarmv6\fR, \fBarmv6j\fR, +\&\fBarmv6t2\fR, \fBarmv6z\fR, \fBarmv6zk\fR, \fBarmv6\-m\fR, +\&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7\-r\fR, \fBarmv7\-m\fR, \fBarmv7e\-m\fR +\&\fBarmv8\-a\fR, +\&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR. +.Sp +\&\fB\-march=native\fR causes the compiler to auto-detect the architecture +of the build computer. At present, this feature is only supported on +Linux, and not all architectures are recognized. If the auto-detect is +unsuccessful the option has no effect. +.IP "\fB\-mtune=\fR\fIname\fR" 4 +.IX Item "-mtune=name" +This option specifies the name of the target \s-1ARM\s0 processor for +which \s-1GCC\s0 should tune the performance of the code. +For some \s-1ARM\s0 implementations better performance can be obtained by using +this option. +Permissible names are: \fBarm2\fR, \fBarm250\fR, \&\fBarm3\fR, \fBarm6\fR, \fBarm60\fR, \fBarm600\fR, \fBarm610\fR, \&\fBarm620\fR, \fBarm7\fR, \fBarm7m\fR, \fBarm7d\fR, \fBarm7dm\fR, \&\fBarm7di\fR, \fBarm7dmi\fR, \fBarm70\fR, \fBarm700\fR, @@ -10521,25 +10559,6 @@ assembly code. Permissible names are: \fBarm2\fR, \fBarm250\fR, \&\fBfa526\fR, \fBfa626\fR, \&\fBfa606te\fR, \fBfa626te\fR, \fBfmp626\fR, \fBfa726te\fR. .Sp -\&\fB\-mcpu=generic\-\fR\fIarch\fR is also permissible, and is -equivalent to \fB\-march=\fR\fIarch\fR \fB\-mtune=generic\-\fR\fIarch\fR. -See \fB\-mtune\fR for more information. -.Sp -\&\fB\-mcpu=native\fR causes the compiler to auto-detect the \s-1CPU\s0 -of the build computer. At present, this feature is only supported on -Linux, and not all architectures are recognized. If the auto-detect is -unsuccessful the option has no effect. -.IP "\fB\-mtune=\fR\fIname\fR" 4 -.IX Item "-mtune=name" -This option is very similar to the \fB\-mcpu=\fR option, except that -instead of specifying the actual target processor type, and hence -restricting which instructions can be used, it specifies that \s-1GCC\s0 should -tune the performance of the code as if the target were of the type -specified in this option, but still choosing the instructions it -generates based on the \s-1CPU\s0 specified by a \fB\-mcpu=\fR option. -For some \s-1ARM\s0 implementations better performance can be obtained by using -this option. -.Sp \&\fB\-mtune=generic\-\fR\fIarch\fR specifies that \s-1GCC\s0 should tune the performance for a blend of processors within architecture \fIarch\fR. The aim is to generate code that run well on the current most popular @@ -10551,21 +10570,23 @@ this option may change in future \s-1GCC\s0 versions as \s-1CPU\s0 models come a of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. -.IP "\fB\-march=\fR\fIname\fR" 4 -.IX Item "-march=name" -This specifies the name of the target \s-1ARM\s0 architecture. \s-1GCC\s0 uses this -name to determine what kind of instructions it can emit when generating -assembly code. This option can be used in conjunction with or instead -of the \fB\-mcpu=\fR option. Permissible names are: \fBarmv2\fR, -\&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR, -\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5e\fR, \fBarmv5te\fR, -\&\fBarmv6\fR, \fBarmv6j\fR, -\&\fBarmv6t2\fR, \fBarmv6z\fR, \fBarmv6zk\fR, \fBarmv6\-m\fR, -\&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7\-r\fR, \fBarmv7\-m\fR, -\&\fBarmv8\-a\fR, -\&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name +to derive the name of the target \s-1ARM\s0 architecture (as if specified +by \fB\-march\fR) and the \s-1ARM\s0 processor type for which to tune for +performance (as if specified by \fB\-mtune\fR). Where this option +is used in conjunction with \fB\-march\fR or \fB\-mtune\fR, +those options take precedence over the appropriate part of this option. .Sp -\&\fB\-march=native\fR causes the compiler to auto-detect the architecture +Permissible names for this option are the same as those for +\&\fB\-mtune\fR. +.Sp +\&\fB\-mcpu=generic\-\fR\fIarch\fR is also permissible, and is +equivalent to \fB\-march=\fR\fIarch\fR \fB\-mtune=generic\-\fR\fIarch\fR. +See \fB\-mtune\fR for more information. +.Sp +\&\fB\-mcpu=native\fR causes the compiler to auto-detect the \s-1CPU\s0 of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. @@ -10649,8 +10670,11 @@ responsible for initializing this register with an appropriate value before execution begins. .IP "\fB\-mpic\-register=\fR\fIreg\fR" 4 .IX Item "-mpic-register=reg" -Specify the register to be used for \s-1PIC\s0 addressing. The default is R10 -unless stack-checking is enabled, when R9 is used. +Specify the register to be used for \s-1PIC\s0 addressing. +For standard \s-1PIC\s0 base case, the default will be any suitable register +determined by compiler. For single \s-1PIC\s0 base case, the default is +\&\fBR9\fR if target is \s-1EABI\s0 based or stack-checking is enabled, +otherwise the default is \fBR10\fR. .IP "\fB\-mpoke\-function\-name\fR" 4 .IX Item "-mpoke-function-name" Write the name of each function into the text section, directly @@ -10805,7 +10829,7 @@ The default for this option is@tie{}\f(CW\*(C`avr2\*(C'\fR. .el .IP "\f(CWavr5\fR" 4 .IX Item "avr5" \&\*(L"Enhanced\*(R" devices with 16@tie{}KiB up to 64@tie{}KiB of program memory. -\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata5790\*(C'\fR, \f(CW\*(C`ata5790n\*(C'\fR, \f(CW\*(C`ata5795\*(C'\fR, \f(CW\*(C`atmega16\*(C'\fR, \f(CW\*(C`atmega16a\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvbrevb\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega161\*(C'\fR, \f(CW\*(C`atmega162\*(C'\fR, \f(CW\*(C`atmega163\*(C'\fR, \f(CW\*(C`atmega164a\*(C'\fR, \f(CW\*(C`atmega164p\*(C'\fR, \f(CW\*(C`atmega164pa\*(C'\fR, \f(CW\*(C`atmega165\*(C'\fR, \f(CW\*(C`atmega165a\*(C'\fR, \f(CW\*(C`atmega165p\*(C'\fR, \f(CW\*(C`atmega165pa\*(C'\fR, \f(CW\*(C`atmega168\*(C'\fR, \f(CW\*(C`atmega168a\*(C'\fR, \f(CW\*(C`atmega168p\*(C'\fR, \f(CW\*(C`atmega168pa\*(C'\fR, \f(CW\*(C`atmega169\*(C'\fR, \f(CW\*(C`atmega169a\*(C'\fR, \f(CW\*(C`atmega169p\*(C'\fR, \f(CW\*(C`atmega169pa\*(C'\fR, \f(CW\*(C`atmega26hvg\*(C'\fR, \f(CW\*(C`atmega32\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvbrevb\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega323\*(C'\fR, \f(CW\*(C`atmega324a\*(C'\fR, \f(CW\*(C`atmega324p\*(C'\fR, \f(CW\*(C`atmega324pa\*(C'\fR, \f(CW\*(C`atmega325\*(C'\fR, \f(CW\*(C`atmega325a\*(C'\fR, \f(CW\*(C`atmega325p\*(C'\fR, \f(CW\*(C`atmega3250\*(C'\fR, \f(CW\*(C`atmega3250a\*(C'\fR, \f(CW\*(C`atmega3250p\*(C'\fR, \f(CW\*(C`atmega3250pa\*(C'\fR, \f(CW\*(C`atmega328\*(C'\fR, \f(CW\*(C`atmega328p\*(C'\fR, \f(CW\*(C`atmega329\*(C'\fR, \f(CW\*(C`atmega329a\*(C'\fR, \f(CW\*(C`atmega329p\*(C'\fR, \f(CW\*(C`atmega329pa\*(C'\fR, \f(CW\*(C`atmega3290\*(C'\fR, \f(CW\*(C`atmega3290a\*(C'\fR, \f(CW\*(C`atmega3290p\*(C'\fR, \f(CW\*(C`atmega3290pa\*(C'\fR, \f(CW\*(C`atmega406\*(C'\fR, \f(CW\*(C`atmega48hvf\*(C'\fR, \f(CW\*(C`atmega64\*(C'\fR, \f(CW\*(C`atmega64a\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64hve\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64rfa2\*(C'\fR, \f(CW\*(C`atmega64rfr2\*(C'\fR, \f(CW\*(C`atmega640\*(C'\fR, \f(CW\*(C`atmega644\*(C'\fR, \f(CW\*(C`atmega644a\*(C'\fR, \f(CW\*(C`atmega644p\*(C'\fR, \f(CW\*(C`atmega644pa\*(C'\fR, \f(CW\*(C`atmega645\*(C'\fR, \f(CW\*(C`atmega645a\*(C'\fR, \f(CW\*(C`atmega645p\*(C'\fR, \f(CW\*(C`atmega6450\*(C'\fR, \f(CW\*(C`atmega6450a\*(C'\fR, \f(CW\*(C`atmega6450p\*(C'\fR, \f(CW\*(C`atmega649\*(C'\fR, \f(CW\*(C`atmega649a\*(C'\fR, \f(CW\*(C`atmega649p\*(C'\fR, \f(CW\*(C`atmega6490\*(C'\fR, \f(CW\*(C`atmega6490a\*(C'\fR, \f(CW\*(C`atmega6490p\*(C'\fR, \f(CW\*(C`at90can32\*(C'\fR, \f(CW\*(C`at90can64\*(C'\fR, \f(CW\*(C`at90pwm161\*(C'\fR, \f(CW\*(C`at90pwm216\*(C'\fR, \f(CW\*(C`at90pwm316\*(C'\fR, \f(CW\*(C`at90scr100\*(C'\fR, \f(CW\*(C`at90usb646\*(C'\fR, \f(CW\*(C`at90usb647\*(C'\fR, \f(CW\*(C`at94k\*(C'\fR, \f(CW\*(C`m3000\*(C'\fR. +\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata5790\*(C'\fR, \f(CW\*(C`ata5790n\*(C'\fR, \f(CW\*(C`ata5795\*(C'\fR, \f(CW\*(C`atmega16\*(C'\fR, \f(CW\*(C`atmega16a\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvbrevb\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega161\*(C'\fR, \f(CW\*(C`atmega162\*(C'\fR, \f(CW\*(C`atmega163\*(C'\fR, \f(CW\*(C`atmega164a\*(C'\fR, \f(CW\*(C`atmega164p\*(C'\fR, \f(CW\*(C`atmega164pa\*(C'\fR, \f(CW\*(C`atmega165\*(C'\fR, \f(CW\*(C`atmega165a\*(C'\fR, \f(CW\*(C`atmega165p\*(C'\fR, \f(CW\*(C`atmega165pa\*(C'\fR, \f(CW\*(C`atmega168\*(C'\fR, \f(CW\*(C`atmega168a\*(C'\fR, \f(CW\*(C`atmega168p\*(C'\fR, \f(CW\*(C`atmega168pa\*(C'\fR, \f(CW\*(C`atmega169\*(C'\fR, \f(CW\*(C`atmega169a\*(C'\fR, \f(CW\*(C`atmega169p\*(C'\fR, \f(CW\*(C`atmega169pa\*(C'\fR, \f(CW\*(C`atmega26hvg\*(C'\fR, \f(CW\*(C`atmega32\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvbrevb\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega323\*(C'\fR, \f(CW\*(C`atmega324a\*(C'\fR, \f(CW\*(C`atmega324p\*(C'\fR, \f(CW\*(C`atmega324pa\*(C'\fR, \f(CW\*(C`atmega325\*(C'\fR, \f(CW\*(C`atmega325a\*(C'\fR, \f(CW\*(C`atmega325p\*(C'\fR, \f(CW\*(C`atmega3250\*(C'\fR, \f(CW\*(C`atmega3250a\*(C'\fR, \f(CW\*(C`atmega3250p\*(C'\fR, \f(CW\*(C`atmega3250pa\*(C'\fR, \f(CW\*(C`atmega328\*(C'\fR, \f(CW\*(C`atmega328p\*(C'\fR, \f(CW\*(C`atmega329\*(C'\fR, \f(CW\*(C`atmega329a\*(C'\fR, \f(CW\*(C`atmega329p\*(C'\fR, \f(CW\*(C`atmega329pa\*(C'\fR, \f(CW\*(C`atmega3290\*(C'\fR, \f(CW\*(C`atmega3290a\*(C'\fR, \f(CW\*(C`atmega3290p\*(C'\fR, \f(CW\*(C`atmega3290pa\*(C'\fR, \f(CW\*(C`atmega406\*(C'\fR, \f(CW\*(C`atmega48hvf\*(C'\fR, \f(CW\*(C`atmega64\*(C'\fR, \f(CW\*(C`atmega64a\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64hve\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64rfa2\*(C'\fR, \f(CW\*(C`atmega64rfr2\*(C'\fR, \f(CW\*(C`atmega640\*(C'\fR, \f(CW\*(C`atmega644\*(C'\fR, \f(CW\*(C`atmega644a\*(C'\fR, \f(CW\*(C`atmega644p\*(C'\fR, \f(CW\*(C`atmega644pa\*(C'\fR, \f(CW\*(C`atmega645\*(C'\fR, \f(CW\*(C`atmega645a\*(C'\fR, \f(CW\*(C`atmega645p\*(C'\fR, \f(CW\*(C`atmega6450\*(C'\fR, \f(CW\*(C`atmega6450a\*(C'\fR, \f(CW\*(C`atmega6450p\*(C'\fR, \f(CW\*(C`atmega649\*(C'\fR, \f(CW\*(C`atmega649a\*(C'\fR, \f(CW\*(C`atmega649p\*(C'\fR, \f(CW\*(C`atmega6490\*(C'\fR, \f(CW\*(C`atmega6490a\*(C'\fR, \f(CW\*(C`atmega6490p\*(C'\fR, \f(CW\*(C`at90can32\*(C'\fR, \f(CW\*(C`at90can64\*(C'\fR, \f(CW\*(C`at90pwm161\*(C'\fR, \f(CW\*(C`at90pwm216\*(C'\fR, \f(CW\*(C`at90pwm316\*(C'\fR, \f(CW\*(C`at90scr100\*(C'\fR, \f(CW\*(C`at90usb646\*(C'\fR, \f(CW\*(C`at90usb647\*(C'\fR, \f(CW\*(C`at94k\*(C'\fR, \f(CW\*(C`m3000\*(C'\fR. .ie n .IP """avr51""" 4 .el .IP "\f(CWavr51\fR" 4 .IX Item "avr51" @@ -11043,7 +11067,7 @@ command-line option. .IX Item "-<Switch/case dispatch tables. If you do not want such dispatch>" tables you can specify the \fB\-fno\-jump\-tables\fR command-line option. .IP "\-<C and \*(C+ constructors/destructors called during startup/shutdown.>" 4 -.IX Item "-<C and constructors/destructors called during startup/shutdown.>" +.IX Item "-<C and constructors/destructors called during startup/shutdown.>" .PD 0 .ie n .IP "\-<If the tools hit a ""gs()"" modifier explained above.>" 4 .el .IP "\-<If the tools hit a \f(CWgs()\fR modifier explained above.>" 4 @@ -11790,7 +11814,7 @@ an executable when linking, using the Darwin \fIlibtool\fR command. This causes \s-1GCC\s0's output file to have the \fI\s-1ALL\s0\fR subtype, instead of one controlled by the \fB\-mcpu\fR or \fB\-march\fR option. .IP "\fB\-allowable_client\fR \fIclient_name\fR" 4 -.IX Item "-allowable_client client_name" +.IX Item "-allowable_client client_name" .PD 0 .IP "\fB\-client_name\fR" 4 .IX Item "-client_name" @@ -12865,9 +12889,14 @@ Intel Core i7 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SS Intel Core \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0 and F16C instruction set support. +.IP "\fBcore\-avx2\fR" 4 +.IX Item "core-avx2" +Intel Core \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AVX2\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, \s-1FMA\s0, \s-1BMI\s0, \s-1BMI2\s0 +and F16C instruction set support. .IP "\fBatom\fR" 4 .IX Item "atom" -Intel Atom \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 +Intel Atom \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 instruction set support. .IP "\fBk6\fR" 4 .IX Item "k6" @@ -16284,7 +16313,9 @@ following options: \&\fB\-maltivec \-mfprnd \-mhard\-float \-mmfcrf \-mmultiple \&\-mpopcntb \-mpopcntd \-mpowerpc64 \&\-mpowerpc\-gpopt \-mpowerpc\-gfxopt \-msingle\-float \-mdouble\-float -\&\-msimple\-fpu \-mstring \-mmulhw \-mdlmzb \-mmfpgpr \-mvsx\fR +\&\-msimple\-fpu \-mstring \-mmulhw \-mdlmzb \-mmfpgpr \-mvsx +\&\-mcrypto \-mdirect\-move \-mpower8\-fusion \-mpower8\-vector +\&\-mquad\-memory \-mquad\-memory\-atomic\fR .Sp The particular options set for any particular \s-1CPU\s0 varies between compiler versions, depending on what setting seems to produce optimal @@ -16331,6 +16362,36 @@ enable the use of built-in functions that allow more direct access to the AltiVec instruction set. You may also need to set \&\fB\-mabi=altivec\fR to adjust the current \s-1ABI\s0 with AltiVec \s-1ABI\s0 enhancements. +.Sp +When \fB\-maltivec\fR is used, rather than \fB\-maltivec=le\fR or +\&\fB\-maltivec=be\fR, the element order for Altivec intrinsics such +as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and \f(CW\*(C`vec_insert\*(C'\fR will +match array element order corresponding to the endianness of the +target. That is, element zero identifies the leftmost element in a +vector register when targeting a big-endian platform, and identifies +the rightmost element in a vector register when targeting a +little-endian platform. +.IP "\fB\-maltivec=be\fR" 4 +.IX Item "-maltivec=be" +Generate Altivec instructions using big-endian element order, +regardless of whether the target is big\- or little-endian. This is +the default when targeting a big-endian platform. +.Sp +The element order is used to interpret element numbers in Altivec +intrinsics such as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and +\&\f(CW\*(C`vec_insert\*(C'\fR. By default, these will match array element order +corresponding to the endianness for the target. +.IP "\fB\-maltivec=le\fR" 4 +.IX Item "-maltivec=le" +Generate Altivec instructions using little-endian element order, +regardless of whether the target is big\- or little-endian. This is +the default when targeting a little-endian platform. This option is +currently ignored when targeting a big-endian platform. +.Sp +The element order is used to interpret element numbers in Altivec +intrinsics such as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and +\&\f(CW\*(C`vec_insert\*(C'\fR. By default, these will match array element order +corresponding to the endianness for the target. .IP "\fB\-mvrsave\fR" 4 .IX Item "-mvrsave" .PD 0 @@ -16399,6 +16460,61 @@ This option has been deprecated. Use \fB\-mspe\fR and Generate code that uses (does not use) vector/scalar (\s-1VSX\s0) instructions, and also enable the use of built-in functions that allow more direct access to the \s-1VSX\s0 instruction set. +.IP "\fB\-mcrypto\fR" 4 +.IX Item "-mcrypto" +.PD 0 +.IP "\fB\-mno\-crypto\fR" 4 +.IX Item "-mno-crypto" +.PD +Enable the use (disable) of the built-in functions that allow direct +access to the cryptographic instructions that were added in version +2.07 of the PowerPC \s-1ISA\s0. +.IP "\fB\-mdirect\-move\fR" 4 +.IX Item "-mdirect-move" +.PD 0 +.IP "\fB\-mno\-direct\-move\fR" 4 +.IX Item "-mno-direct-move" +.PD +Generate code that uses (does not use) the instructions to move data +between the general purpose registers and the vector/scalar (\s-1VSX\s0) +registers that were added in version 2.07 of the PowerPC \s-1ISA\s0. +.IP "\fB\-mpower8\-fusion\fR" 4 +.IX Item "-mpower8-fusion" +.PD 0 +.IP "\fB\-mno\-power8\-fusion\fR" 4 +.IX Item "-mno-power8-fusion" +.PD +Generate code that keeps (does not keeps) some integer operations +adjacent so that the instructions can be fused together on power8 and +later processors. +.IP "\fB\-mpower8\-vector\fR" 4 +.IX Item "-mpower8-vector" +.PD 0 +.IP "\fB\-mno\-power8\-vector\fR" 4 +.IX Item "-mno-power8-vector" +.PD +Generate code that uses (does not use) the vector and scalar +instructions that were added in version 2.07 of the PowerPC \s-1ISA\s0. Also +enable the use of built-in functions that allow more direct access to +the vector instructions. +.IP "\fB\-mquad\-memory\fR" 4 +.IX Item "-mquad-memory" +.PD 0 +.IP "\fB\-mno\-quad\-memory\fR" 4 +.IX Item "-mno-quad-memory" +.PD +Generate code that uses (does not use) the non-atomic quad word memory +instructions. The \fB\-mquad\-memory\fR option requires use of +64\-bit mode. +.IP "\fB\-mquad\-memory\-atomic\fR" 4 +.IX Item "-mquad-memory-atomic" +.PD 0 +.IP "\fB\-mno\-quad\-memory\-atomic\fR" 4 +.IX Item "-mno-quad-memory-atomic" +.PD +Generate code that uses (does not use) the atomic quad word memory +instructions. The \fB\-mquad\-memory\-atomic\fR option requires use of +64\-bit mode. .IP "\fB\-mfloat\-gprs=\fR\fIyes/single/double/no\fR" 4 .IX Item "-mfloat-gprs=yes/single/double/no" .PD 0 @@ -16828,7 +16944,8 @@ Return structures smaller than 8 bytes in registers (as specified by the .IX Item "-mabi=abi-type" Extend the current \s-1ABI\s0 with a particular extension, or remove such extension. Valid values are \fIaltivec\fR, \fIno-altivec\fR, \fIspe\fR, -\&\fIno-spe\fR, \fIibmlongdouble\fR, \fIieeelongdouble\fR. +\&\fIno-spe\fR, \fIibmlongdouble\fR, \fIieeelongdouble\fR, +\&\fIelfv1\fR, \fIelfv2\fR. .IP "\fB\-mabi=spe\fR" 4 .IX Item "-mabi=spe" Extend the current \s-1ABI\s0 with \s-1SPE\s0 \s-1ABI\s0 extensions. This does not change @@ -16845,6 +16962,18 @@ This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. .IX Item "-mabi=ieeelongdouble" Change the current \s-1ABI\s0 to use \s-1IEEE\s0 extended-precision long double. This is a PowerPC 32\-bit Linux \s-1ABI\s0 option. +.IP "\fB\-mabi=elfv1\fR" 4 +.IX Item "-mabi=elfv1" +Change the current \s-1ABI\s0 to use the ELFv1 \s-1ABI\s0. +This is the default \s-1ABI\s0 for big-endian PowerPC 64\-bit Linux. +Overriding the default \s-1ABI\s0 requires special system support and is +likely to fail in spectacular ways. +.IP "\fB\-mabi=elfv2\fR" 4 +.IX Item "-mabi=elfv2" +Change the current \s-1ABI\s0 to use the ELFv2 \s-1ABI\s0. +This is the default \s-1ABI\s0 for little-endian PowerPC 64\-bit Linux. +Overriding the default \s-1ABI\s0 requires special system support and is +likely to fail in spectacular ways. .IP "\fB\-mprototype\fR" 4 .IX Item "-mprototype" .PD 0 @@ -17132,6 +17261,25 @@ stack location in the function prologue if the function calls through a pointer on \s-1AIX\s0 and 64\-bit Linux systems. If the \s-1TOC\s0 value is not saved in the prologue, it is saved just before the call through the pointer. The \fB\-mno\-save\-toc\-indirect\fR option is the default. +.IP "\fB\-mcompat\-align\-parm\fR" 4 +.IX Item "-mcompat-align-parm" +.PD 0 +.IP "\fB\-mno\-compat\-align\-parm\fR" 4 +.IX Item "-mno-compat-align-parm" +.PD +Generate (do not generate) code to pass structure parameters with a +maximum alignment of 64 bits, for compatibility with older versions +of \s-1GCC\s0. +.Sp +Older versions of \s-1GCC\s0 (prior to 4.9.0) incorrectly did not align a +structure parameter on a 128\-bit boundary when that structure contained +a member requiring 128\-bit alignment. This is corrected in more +recent versions of \s-1GCC\s0. This option may be used to generate code +that is compatible with functions compiled with older versions of +\&\s-1GCC\s0. +.Sp +In this version of the compiler, the \fB\-mcompat\-align\-parm\fR +is the default, except when using the Linux ELFv2 \s-1ABI\s0. .PP \fI\s-1RX\s0 Options\fR .IX Subsection "RX Options" @@ -17514,6 +17662,23 @@ values have to be exact powers of 2 and \fIstack-size\fR has to be greater than In order to be efficient the extra code makes the assumption that the stack starts at an address aligned to the value given by \fIstack-size\fR. The \fIstack-guard\fR option can only be used in conjunction with \fIstack-size\fR. +.IP "\fB\-mhotpatch[=\fR\fIhalfwords\fR\fB]\fR" 4 +.IX Item "-mhotpatch[=halfwords]" +.PD 0 +.IP "\fB\-mno\-hotpatch\fR" 4 +.IX Item "-mno-hotpatch" +.PD +If the hotpatch option is enabled, a \*(L"hot-patching\*(R" function +prologue is generated for all functions in the compilation unit. +The funtion label is prepended with the given number of two-byte +Nop instructions (\fIhalfwords\fR, maximum 1000000) or 12 Nop +instructions if no argument is present. Functions with a +hot-patching prologue are never inlined automatically, and a +hot-patching prologue is never generated for functions functions +that are explicitly inline. +.Sp +This option can be overridden for individual functions with the +\&\f(CW\*(C`hotpatch\*(C'\fR attribute. .PP \fIScore Options\fR .IX Subsection "Score Options" @@ -18039,8 +18204,9 @@ These \fB\-m\fR options are supported on the \s-1SPARC:\s0 .IX Item "-mapp-regs" .PD Specify \fB\-mapp\-regs\fR to generate output using the global registers -2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. This -is the default. +2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. Like the +global register 1, each global register 2 through 4 is then treated as an +allocable register that is clobbered by function calls. This is the default. .Sp To be fully \s-1SVR4\s0 ABI-compliant at the cost of some performance loss, specify \fB\-mno\-app\-regs\fR. You should compile libraries and system @@ -18116,6 +18282,15 @@ absolute address. Otherwise, it assumes they have 4\-byte alignment. Specifying this option avoids some rare compatibility problems with code generated by other compilers. It is not the default because it results in a performance loss, especially for floating-point code. +.IP "\fB\-muser\-mode\fR" 4 +.IX Item "-muser-mode" +.PD 0 +.IP "\fB\-mno\-user\-mode\fR" 4 +.IX Item "-mno-user-mode" +.PD +Do not generate code that can only run in supervisor mode. This is relevant +only for the \f(CW\*(C`casa\*(C'\fR instruction emitted for the \s-1LEON3\s0 processor. The +default is \fB\-mno\-user\-mode\fR. .IP "\fB\-mno\-faster\-structs\fR" 4 .IX Item "-mno-faster-structs" .PD 0 @@ -18135,10 +18310,10 @@ the rules of the \s-1ABI\s0. Set the instruction set, register set, and instruction scheduling parameters for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are \&\fBv7\fR, \fBcypress\fR, \fBv8\fR, \fBsupersparc\fR, \fBhypersparc\fR, -\&\fBleon\fR, \fBsparclite\fR, \fBf930\fR, \fBf934\fR, \fBsparclite86x\fR, -\&\fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, \fBultrasparc\fR, -\&\fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR, -and \fBniagara4\fR. +\&\fBleon\fR, \fBleon3\fR, \fBsparclite\fR, \fBf930\fR, \fBf934\fR, +\&\fBsparclite86x\fR, \fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, +\&\fBultrasparc\fR, \fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, +\&\fBniagara3\fR and \fBniagara4\fR. .Sp Native Solaris and GNU/Linux toolchains also support the value \fBnative\fR, which selects the best architecture option for the host processor. @@ -18157,7 +18332,7 @@ implementations. cypress .IP "v8" 4 .IX Item "v8" -supersparc, hypersparc, leon +supersparc, hypersparc, leon, leon3 .IP "sparclite" 4 .IX Item "sparclite" f930, f934, sparclite86x @@ -18220,10 +18395,11 @@ option \fB\-mcpu=\fR\fIcpu_type\fR does. The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for \&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those that select a particular \s-1CPU\s0 implementation. Those are \fBcypress\fR, -\&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBf930\fR, \fBf934\fR, -\&\fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, \fBultrasparc3\fR, -\&\fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR and \fBniagara4\fR. With -native Solaris and GNU/Linux toolchains, \fBnative\fR can also be used. +\&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBleon3\fR, \fBf930\fR, +\&\fBf934\fR, \fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, +\&\fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR and +\&\fBniagara4\fR. With native Solaris and GNU/Linux toolchains, \fBnative\fR +can also be used. .IP "\fB\-mv8plus\fR" 4 .IX Item "-mv8plus" .PD 0 @@ -18298,6 +18474,10 @@ later. .IX Item "-mfix-at697f" Enable the documented workaround for the single erratum of the Atmel \s-1AT697F\s0 processor (which corresponds to erratum #13 of the \s-1AT697E\s0 processor). +.IP "\fB\-mfix\-ut699\fR" 4 +.IX Item "-mfix-ut699" +Enable the documented workarounds for the floating-point errata and the data +cache nullify errata of the \s-1UT699\s0 processor. .PP These \fB\-m\fR options are supported in addition to the above on \s-1SPARC\-V9\s0 processors in 64\-bit environments: @@ -18977,7 +19157,7 @@ every cross-file call, not just those that really are out of range. .IX Subsection "zSeries Options" .PP These are listed under -.SS "Options for Code Generation Conventions" +.Sh "Options for Code Generation Conventions" .IX Subsection "Options for Code Generation Conventions" These machine-independent options control the interface conventions used in code generation. diff --git a/gcc-4.8/gcc/doc/gcc.info b/gcc-4.8/gcc/doc/gcc.info index e5a735552..cb0d668de 100644 --- a/gcc-4.8/gcc/doc/gcc.info +++ b/gcc-4.8/gcc/doc/gcc.info @@ -1,5 +1,5 @@ -This is doc/gcc.info, produced by makeinfo version 4.13 from -/d/gcc-4.8.1/gcc-4.8.1/gcc/doc/gcc.texi. +This is doc/gcc.info, produced by makeinfo version 4.12 from +/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/doc/gcc.texi. Copyright (C) 1988-2013 Free Software Foundation, Inc. @@ -58,7 +58,7 @@ Introduction This manual documents how to use the GNU compilers, as well as their features and incompatibilities, and how to report bugs. It corresponds -to the compilers (GCC) version 4.8.1. The internals of the GNU +to the compilers (GCC) version 4.8.3. The internals of the GNU compilers, including how to port them to new targets and some information about how to write front ends for new languages, are documented in a separate manual. *Note Introduction: (gccint)Top. @@ -264,7 +264,7 @@ experimental support for the second ISO C++ standard (2011). The original ISO C++ standard was published as the ISO standard (ISO/IEC 14882:1998) and amended by a Technical Corrigenda published in -2003 (ISO/IEC 14882:2003). These standards are referred to as C++98 and +2003 (ISO/IEC 14882:2003). These standards are referred to as C++98 and C++03, respectively. GCC implements the majority of C++98 (`export' is a notable exception) and most of the changes in C++03. To select this standard in GCC, use one of the options `-ansi', `-std=c++98', or @@ -323,7 +323,7 @@ at a number of web sites: * `http://objc.toodarkpark.net' is the same document in another format; - * + * `http://developer.apple.com/mac/library/documentation/Cocoa/Conceptual/ObjectiveC/' has an updated version but make sure you search for "Object Oriented Programming and the Objective-C Programming Language 1.0", @@ -349,7 +349,7 @@ by GCC 4.0, and to produce an error if one of the new features is used. GCC has currently no support for non-fragile instance variables. The authoritative manual on Objective-C 2.0 is available from Apple: - * + * `http://developer.apple.com/mac/library/documentation/Cocoa/Conceptual/ObjectiveC/' For more information concerning the history of Objective-C that is @@ -463,7 +463,7 @@ _Overall Options_ -pipe -pass-exit-codes -x LANGUAGE -v -### --help[=CLASS[,...]] --target-help --version -wrapper @FILE -fplugin=FILE -fplugin-arg-NAME=ARG - -fdump-ada-spec[-slim] -fada-spec-parent=ARG -fdump-go-spec=FILE + -fdump-ada-spec[-slim] -fada-spec-parent=UNIT -fdump-go-spec=FILE _C Language Options_ *Note Options Controlling C Dialect: C Dialect Options. @@ -1155,6 +1155,11 @@ _Machine Dependent Options_ -mveclibabi=TYPE -mfriz -mno-friz -mpointers-to-nested-functions -mno-pointers-to-nested-functions -msave-toc-indirect -mno-save-toc-indirect + -mpower8-fusion -mno-mpower8-fusion -mpower8-vector -mno-power8-vector + -mcrypto -mno-crypto -mdirect-move -mno-direct-move + -mquad-memory -mno-quad-memory + -mquad-memory-atomic -mno-quad-memory-atomic + -mcompat-align-parm -mno-compat-align-parm _RX Options_ -m64bit-doubles -m32bit-doubles -fpu -nofpu @@ -1179,6 +1184,7 @@ _Machine Dependent Options_ -m64 -m31 -mdebug -mno-debug -mesa -mzarch -mtpf-trace -mno-tpf-trace -mfused-madd -mno-fused-madd -mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard + -mhotpatch[=HALFWORDS] -mno-hotpatch _Score Options_ -meb -mel @@ -1223,11 +1229,12 @@ _Machine Dependent Options_ -mhard-quad-float -msoft-quad-float -mstack-bias -mno-stack-bias -munaligned-doubles -mno-unaligned-doubles + -muser-mode -mno-user-mode -mv8plus -mno-v8plus -mvis -mno-vis -mvis2 -mno-vis2 -mvis3 -mno-vis3 -mcbcond -mno-cbcond -mfmaf -mno-fmaf -mpopc -mno-popc - -mfix-at697f + -mfix-at697f -mfix-ut699 _SPU Options_ -mwarn-reloc -merror-reloc @@ -1596,7 +1603,7 @@ do nothing at all. `params' Display the values recognized by the `--param' option. - LANGUAGE + LANGUAGE Display the options supported for LANGUAGE, where LANGUAGE is the name of one of the languages supported in this version of GCC. @@ -1704,10 +1711,14 @@ do nothing at all. `-fdump-ada-spec[-slim]' For C and C++ source and include files, generate corresponding Ada - specs. *Note Generating Ada Bindings for C and C++ headers: + specs. *Note Generating Ada Bindings for C and C++ headers: (gnat_ugn)Generating Ada Bindings for C and C++ headers, which provides detailed documentation on this feature. +`-fada-spec-parent=UNIT' + In conjunction with `-fdump-ada-spec[-slim]' above, generate Ada + specs as child units of parent UNIT. + `-fdump-go-spec=FILE' For input files in any language, generate corresponding Go declarations in FILE. This generates Go `const', `type', `var', @@ -1806,7 +1817,7 @@ accepts: affected. `-std=' - Determine the language standard. *Note Language Standards + Determine the language standard. *Note Language Standards Supported by GCC: Standards, for details of these standard versions. This option is currently only supported when compiling C or C++. @@ -1857,7 +1868,7 @@ accepts: `gnu90' `gnu89' - GNU dialect of ISO C90 (including some C99 features). This is + GNU dialect of ISO C90 (including some C99 features). This is the default for C code. `gnu99' @@ -2578,7 +2589,7 @@ have meanings only for C++ programs: changes at this point include: * For SysV/x86-64, unions with `long double' members are passed - in memory as specified in psABI. For example: + in memory as specified in psABI. For example: union U { long double ld; @@ -2597,7 +2608,7 @@ have meanings only for C++ programs: `-Wdelete-non-virtual-dtor (C++ and Objective-C++ only)' Warn when `delete' is used to destroy an instance of a class that - has virtual functions and non-virtual destructor. It is unsafe to + has virtual functions and non-virtual destructor. It is unsafe to delete an instance of a derived class through a pointer to a base class if the base class does not have a virtual destructor. This warning is enabled by `-Wall'. @@ -2681,9 +2692,9 @@ have meanings only for C++ programs: * Item 11: Define a copy constructor and an assignment operator for classes with dynamically-allocated memory. - * Item 12: Prefer initialization to assignment in constructors. + * Item 12: Prefer initialization to assignment in constructors. - * Item 14: Make destructors virtual in base classes. + * Item 14: Make destructors virtual in base classes. * Item 15: Have `operator=' return a reference to `*this'. @@ -2694,7 +2705,7 @@ have meanings only for C++ programs: Also warn about violations of the following style guidelines from Scott Meyers' `More Effective C++' book: - * Item 6: Distinguish between prefix and postfix forms of + * Item 6: Distinguish between prefix and postfix forms of increment and decrement operators. * Item 7: Never overload `&&', `||', or `,'. @@ -2825,7 +2836,7 @@ and Objective-C++ programs: support for properties and other Objective-C 2.0 additions. Version 1 is the traditional (32-bit) ABI with support for properties and other Objective-C 2.0 additions. Version 2 is the - modern (64-bit) ABI. If nothing is specified, the default is + modern (64-bit) ABI. If nothing is specified, the default is Version 0 on 32-bit target machines, and Version 2 on 64-bit target machines. @@ -3624,9 +3635,9 @@ present. `-Wunused-value' Warn whenever a statement computes a result that is explicitly not - used. To suppress this warning cast the unused expression to + used. To suppress this warning cast the unused expression to `void'. This includes an expression-statement or the left-hand - side of a comma expression that contains no side effects. For + side of a comma expression that contains no side effects. For example, an expression such as `x[i,j]' causes a warning, while `x[(void)i,j]' does not. @@ -3686,7 +3697,7 @@ present. } If the value of `y' is always 1, 2 or 3, then `x' is always - initialized, but GCC doesn't know this. To suppress the warning, + initialized, but GCC doesn't know this. To suppress the warning, you need to provide a default case with assert(0) or similar code. This option also warns when a non-volatile automatic variable @@ -3808,7 +3819,7 @@ present. level gives a very large number of false positives. `-Wsuggest-attribute=[pure|const|noreturn|format]' - Warn for cases where adding an attribute may be beneficial. The + Warn for cases where adding an attribute may be beneficial. The attributes currently supported are listed below. `-Wsuggest-attribute=pure' @@ -3818,7 +3829,7 @@ present. `pure', `const' or `noreturn'. The compiler only warns for functions visible in other compilation units or (in the case of `pure' and `const') if it cannot prove that the function - returns normally. A function returns normally if it doesn't + returns normally. A function returns normally if it doesn't contain an infinite loop or return abnormally by throwing, calling `abort()' or trapping. This analysis requires option `-fipa-pure-const', which is enabled by default at `-O' and @@ -3872,10 +3883,10 @@ present. Warn about trampolines generated for pointers to nested functions. A trampoline is a small piece of data or code that is created at - run time on the stack when the address of a nested function is - taken, and is used to call the nested function indirectly. For - some targets, it is made up of data only and thus requires no - special treatment. But, for most targets, it is made up of code + run time on the stack when the address of a nested function is + taken, and is used to call the nested function indirectly. For + some targets, it is made up of data only and thus requires no + special treatment. But, for most targets, it is made up of code and thus requires the stack to be made executable in order for the program to work properly. @@ -3997,7 +4008,7 @@ present. `-Wshadow' Warn whenever a local variable or type declaration shadows another variable, parameter, type, or class member (in C++), or whenever a - built-in function is shadowed. Note that in C++, the compiler + built-in function is shadowed. Note that in C++, the compiler warns if a local variable shadows an explicit typedef, but not if it shadows a struct/class/enum. @@ -4134,7 +4145,7 @@ present. For C++, also warn for confusing overload resolution for user-defined conversions; and conversions that never use a type conversion operator: conversions to `void', the same type, a base - class or a reference to them. Warnings about conversions between + class or a reference to them. Warnings about conversions between signed and unsigned integers are disabled by default in C++ unless `-Wsign-conversion' is explicitly enabled. @@ -4180,7 +4191,7 @@ present. `-Wsign-conversion' Warn for implicit conversions that may change the sign of an integer value, like assigning a signed integer expression to an - unsigned integer variable. An explicit cast silences the warning. + unsigned integer variable. An explicit cast silences the warning. In C, this option is enabled also by `-Wconversion'. `-Wsizeof-pointer-memaccess' @@ -4238,7 +4249,7 @@ present. `-Wold-style-declaration (C and Objective-C only)' Warn for obsolescent usages, according to the C Standard, in a - declaration. For example, warn if storage-class specifiers like + declaration. For example, warn if storage-class specifiers like `static' are not the first things in a declaration. This warning is also enabled by `-Wextra'. @@ -4444,7 +4455,7 @@ present. `-Wno-int-to-pointer-cast' Suppress warnings from casts to pointer type of an integer of a - different size. In C++, casting to a pointer type of smaller size + different size. In C++, casting to a pointer type of smaller size is an error. `Wint-to-pointer-cast' is enabled by default. `-Wno-pointer-to-int-cast (C and Objective-C only)' @@ -5023,11 +5034,11 @@ program or GCC: `-fdisable-KIND-PASS=RANGE-LIST' This is a set of options that are used to explicitly disable/enable optimization passes. These options are intended for use for - debugging GCC. Compiler users should use regular options for + debugging GCC. Compiler users should use regular options for enabling/disabling passes instead. `-fdisable-ipa-PASS' - Disable IPA pass PASS. PASS is the pass name. If the same + Disable IPA pass PASS. PASS is the pass name. If the same pass is statically invoked in the compiler multiple times, the pass name should be appended with a sequential number starting from 1. @@ -5094,7 +5105,7 @@ program or GCC: by LETTERS. This is used for debugging the RTL-based passes of the compiler. The file names for most of the dumps are made by appending a pass number and a word to the DUMPNAME, and the files - are created in the directory of the output file. In case of + are created in the directory of the output file. In case of `=FILENAME' option, the dump is output on the given file instead of the pass numbered dump files. Note that the pass number is computed statically as passes get registered into the pass manager. @@ -5396,7 +5407,7 @@ program or GCC: Control the dumping at various stages of processing the intermediate language tree to a file. The file name is generated by appending a switch-specific suffix to the source file name, and - the file is created in the same directory as the output file. In + the file is created in the same directory as the output file. In case of `=FILENAME' option, the dump is output on the given file instead of the auto named dump files. If the `-OPTIONS' form is used, OPTIONS is a list of `-' separated options which control the @@ -5618,7 +5629,7 @@ program or GCC: source file name. `vrp' - Dump each function after Value Range Propagation (VRP). The + Dump each function after Value Range Propagation (VRP). The file name is made by appending `.vrp' to the source file name. `all' @@ -5628,7 +5639,7 @@ program or GCC: `-fopt-info' `-fopt-info-OPTIONS' `-fopt-info-OPTIONS=FILENAME' - Controls optimization dumps from various optimization passes. If + Controls optimization dumps from various optimization passes. If the `-OPTIONS' form is used, OPTIONS is a list of `-' separated options to select the dump details and optimizations. If OPTIONS is not specified, it defaults to `all' for details and `optall' @@ -5640,10 +5651,10 @@ program or GCC: The options can be divided into two groups, 1) options describing the verbosity of the dump, and 2) options describing which - optimizations should be included. The options from both the groups - can be freely mixed as they are non-overlapping. However, in case + optimizations should be included. The options from both the groups + can be freely mixed as they are non-overlapping. However, in case of any conflicts, the latter options override the earlier options - on the command line. Though multiple -fopt-info options are + on the command line. Though multiple -fopt-info options are accepted, only one of them can have `=filename'. If other filenames are provided then all but the first one are ignored. @@ -5651,12 +5662,12 @@ program or GCC: `optimized' Print information when an optimization is successfully - applied. It is up to a pass to decide which information is - relevant. For example, the vectorizer passes print the source + applied. It is up to a pass to decide which information is + relevant. For example, the vectorizer passes print the source location of loops which got successfully vectorized. `missed' - Print information about missed optimizations. Individual + Print information about missed optimizations. Individual passes control which information to include in the output. For example, @@ -5670,7 +5681,7 @@ program or GCC: transformations, more detailed messages about decisions etc. `all' - Print detailed optimization information. This includes + Print detailed optimization information. This includes OPTIMIZED, MISSED, and NOTE. The second set of options describes a group of optimizations and @@ -5717,7 +5728,7 @@ program or GCC: gcc -fopt-info-vec-missed=vec.miss -fopt-info-loop-optimized=loop.opt Here the two output filenames `vec.miss' and `loop.opt' are in - conflict since only one output file is allowed. In this case, only + conflict since only one output file is allowed. In this case, only the first option takes effect and the subsequent options are ignored. Thus only the `vec.miss' is produced which cotaints dumps from the vectorizer about missed opportunities. @@ -5725,12 +5736,12 @@ program or GCC: `-ftree-vectorizer-verbose=N' This option is deprecated and is implemented in terms of `-fopt-info'. Please use `-fopt-info-KIND' form instead, where - KIND is one of the valid opt-info options. It prints additional + KIND is one of the valid opt-info options. It prints additional optimization information. For N=0 no diagnostic information is reported. If N=1 the vectorizer reports each loop that got vectorized, and the total number of loops that got vectorized. If N=2 the vectorizer reports locations which could not be vectorized - and the reasons for those. For any higher verbosity levels all the + and the reasons for those. For any higher verbosity levels all the analysis and transformation information from the vectorizer is reported. @@ -6854,9 +6865,9 @@ optimizations to be performed is desired. `-fipa-profile' Perform interprocedural profile propagation. The functions called - only from cold functions are marked as cold. Also functions + only from cold functions are marked as cold. Also functions executed once (such as `cold', `noreturn', static constructors or - destructors) are identified. Cold functions and loop less parts of + destructors) are identified. Cold functions and loop less parts of functions executed once are then optimized for size. Enabled by default at `-O' and higher. @@ -6879,7 +6890,7 @@ optimizations to be performed is desired. `-O3'. `-ftree-sink' - Perform forward store motion on trees. This flag is enabled by + Perform forward store motion on trees. This flag is enabled by default at `-O' and higher. `-ftree-bit-ccp' @@ -6920,7 +6931,7 @@ optimizations to be performed is desired. Perform a variety of simple scalar cleanups (constant/copy propagation, redundancy elimination, range propagation and expression simplification) based on a dominator tree traversal. - This also performs jump threading (to reduce jumps to jumps). This + This also performs jump threading (to reduce jumps to jumps). This flag is enabled by default at `-O' and higher. `-ftree-dse' @@ -7182,11 +7193,11 @@ optimizations to be performed is desired. is enabled by default at `-O' and higher. `-ftree-vectorize' - Perform loop vectorization on trees. This flag is enabled by + Perform loop vectorization on trees. This flag is enabled by default at `-O3'. `-ftree-slp-vectorize' - Perform basic block vectorization on trees. This flag is enabled + Perform basic block vectorization on trees. This flag is enabled by default at `-O3' and when `-ftree-vectorize' is enabled. `-ftree-vect-loop-version' @@ -7709,7 +7720,7 @@ optimizations to be performed is desired. available in gold or in GNU ld 2.21 or newer. This option enables the extraction of object files with GIMPLE - bytecode out of library archives. This improves the quality of + bytecode out of library archives. This improves the quality of optimization by exposing more code to the link-time optimizer. This information specifies what symbols can be accessed externally (by non-LTO object or during dynamic linking). Resulting code @@ -7768,9 +7779,9 @@ optimizations to be performed is desired. `-fprofile-correction' Profiles collected using an instrumented binary for multi-threaded - programs may be inconsistent due to missed counter updates. When + programs may be inconsistent due to missed counter updates. When this option is specified, GCC uses heuristics to correct or smooth - out such inconsistencies. By default, GCC emits an error message + out such inconsistencies. By default, GCC emits an error message when an inconsistent profile is detected. `-fprofile-dir=PATH' @@ -7864,7 +7875,7 @@ correctness. All must be specifically enabled. This option is not turned on by any `-O' option besides `-Ofast' since it can result in incorrect output for programs that depend on an exact implementation of IEEE or ISO rules/specifications for - math functions. It may, however, yield faster code for programs + math functions. It may, however, yield faster code for programs that do not require the guarantees of these specifications. `-fno-math-errno' @@ -7876,7 +7887,7 @@ correctness. All must be specifically enabled. This option is not turned on by any `-O' option since it can result in incorrect output for programs that depend on an exact implementation of IEEE or ISO rules/specifications for math - functions. It may, however, yield faster code for programs that do + functions. It may, however, yield faster code for programs that do not require the guarantees of these specifications. The default is `-fmath-errno'. @@ -7895,7 +7906,7 @@ correctness. All must be specifically enabled. This option is not turned on by any `-O' option since it can result in incorrect output for programs that depend on an exact implementation of IEEE or ISO rules/specifications for math - functions. It may, however, yield faster code for programs that do + functions. It may, however, yield faster code for programs that do not require the guarantees of these specifications. Enables `-fno-signed-zeros', `-fno-trapping-math', `-fassociative-math' and `-freciprocal-math'. @@ -7934,7 +7945,7 @@ correctness. All must be specifically enabled. This option is not turned on by any `-O' option since it can result in incorrect output for programs that depend on an exact implementation of IEEE or ISO rules/specifications for math - functions. It may, however, yield faster code for programs that do + functions. It may, however, yield faster code for programs that do not require the guarantees of these specifications. The default is `-fno-finite-math-only'. @@ -8204,7 +8215,7 @@ includes experimental options that may produce broken code. `predictable-branch-outcome' When branch is predicted to be taken with probability lower than this threshold (in percent), then it is considered well - predictable. The default is 10. + predictable. The default is 10. `max-crossjump-edges' The maximum number of incoming edges to consider for @@ -8561,7 +8572,7 @@ includes experimental options that may produce broken code. `hot-bb-count-ws-permille' A basic block profile count is considered hot if it - contributes to the given permillage (i.e. 0...1000) of the + contributes to the given permillage (i.e. 0...1000) of the entire profiled execution. `hot-bb-frequency-fraction' @@ -9017,7 +9028,7 @@ includes experimental options that may produce broken code. `tree-reassoc-width' Set the maximum number of instructions executed in parallel in - reassociated tree. This parameter overrides target dependent + reassociated tree. This parameter overrides target dependent heuristics used by default if has non zero value. `sched-pressure-algorithm' @@ -9575,9 +9586,9 @@ cause the preprocessor output to be unsuitable for actual compilation. When used without `-E', this option has no effect. `-ftrack-macro-expansion[=LEVEL]' - Track locations of tokens across macro expansions. This allows the + Track locations of tokens across macro expansions. This allows the compiler to emit diagnostic about the current macro expansion stack - when a compilation error occurs in a macro expansion. Using this + when a compilation error occurs in a macro expansion. Using this option makes the preprocessor and the compiler consume more memory. The LEVEL parameter can be used to choose the level of precision of token location tracking thus decreasing the memory @@ -9888,8 +9899,8 @@ doing a link step. `-rdynamic' Pass the flag `-export-dynamic' to the ELF linker, on targets that - support it. This instructs the linker to add all symbols, not only - used ones, to the dynamic symbol table. This option is needed for + support it. This instructs the linker to add all symbols, not only + used ones, to the dynamic symbol table. This option is needed for some uses of `dlopen' or to allow obtaining backtraces from within a program. @@ -10017,7 +10028,7 @@ doing a link step. library modules to define it. You can use `-u' multiple times with different symbols to force loading of additional library modules. - ---------- Footnotes ---------- + ---------- Footnotes ---------- (1) On some systems, `gcc -shared' needs to build supplementary stub code for constructors to work. On multi-libbed systems, `gcc -shared' @@ -10412,7 +10423,7 @@ or combine them with constant text in a single argument. `%T' Current argument is the name of a linker script. Search for that - file in the current list of directories to scan for libraries. If + file in the current list of directories to scan for libraries. If the file is located insert a `--script' option into the command line followed by the full path name found. If the file is not found then generate an error message. Note: the current working @@ -10974,7 +10985,7 @@ These `-m' options are defined for Adapteva Epiphany: `int' This is the mode used to perform integer calculations in the - FPU, e.g. integer multiply, or integer + FPU, e.g. integer multiply, or integer multiply-and-accumulate. The default is `-mfp-mode=caller' @@ -11085,45 +11096,41 @@ architectures: versions of the compiler prior to 2.8. This option is now deprecated. -`-mcpu=NAME' - This specifies the name of the target ARM processor. GCC uses +`-march=NAME' + This specifies the name of the target ARM architecture. GCC uses this name to determine what kind of instructions it can emit when - generating assembly code. Permissible names are: `arm2', `arm250', - `arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7', - `arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700', - `arm700i', `arm710', `arm710c', `arm7100', `arm720', `arm7500', - `arm7500fe', `arm7tdmi', `arm7tdmi-s', `arm710t', `arm720t', - `arm740t', `strongarm', `strongarm110', `strongarm1100', - `strongarm1110', `arm8', `arm810', `arm9', `arm9e', `arm920', - `arm920t', `arm922t', `arm946e-s', `arm966e-s', `arm968e-s', - `arm926ej-s', `arm940t', `arm9tdmi', `arm10tdmi', `arm1020t', - `arm1026ej-s', `arm10e', `arm1020e', `arm1022e', `arm1136j-s', - `arm1136jf-s', `mpcore', `mpcorenovfp', `arm1156t2-s', - `arm1156t2f-s', `arm1176jz-s', `arm1176jzf-s', `cortex-a5', - `cortex-a7', `cortex-a8', `cortex-a9', `cortex-a15', `cortex-r4', - `cortex-r4f', `cortex-r5', `cortex-m4', `cortex-m3', `cortex-m1', - `cortex-m0', `cortex-m0plus', `marvell-pj4', `xscale', `iwmmxt', - `iwmmxt2', `ep9312', `fa526', `fa626', `fa606te', `fa626te', - `fmp626', `fa726te'. - - `-mcpu=generic-ARCH' is also permissible, and is equivalent to - `-march=ARCH -mtune=generic-ARCH'. See `-mtune' for more - information. + generating assembly code. This option can be used in conjunction + with or instead of the `-mcpu=' option. Permissible names are: + `armv2', `armv2a', `armv3', `armv3m', `armv4', `armv4t', `armv5', + `armv5t', `armv5e', `armv5te', `armv6', `armv6j', `armv6t2', + `armv6z', `armv6zk', `armv6-m', `armv7', `armv7-a', `armv7-r', + `armv7-m', `armv7e-m' `armv8-a', `iwmmxt', `iwmmxt2', `ep9312'. - `-mcpu=native' causes the compiler to auto-detect the CPU of the - build computer. At present, this feature is only supported on - Linux, and not all architectures are recognized. If the + `-march=native' causes the compiler to auto-detect the architecture + of the build computer. At present, this feature is only supported + on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. `-mtune=NAME' - This option is very similar to the `-mcpu=' option, except that - instead of specifying the actual target processor type, and hence - restricting which instructions can be used, it specifies that GCC - should tune the performance of the code as if the target were of - the type specified in this option, but still choosing the - instructions it generates based on the CPU specified by a `-mcpu=' - option. For some ARM implementations better performance can be - obtained by using this option. + This option specifies the name of the target ARM processor for + which GCC should tune the performance of the code. For some ARM + implementations better performance can be obtained by using this + option. Permissible names are: `arm2', `arm250', `arm3', `arm6', + `arm60', `arm600', `arm610', `arm620', `arm7', `arm7m', `arm7d', + `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700', `arm700i', + `arm710', `arm710c', `arm7100', `arm720', `arm7500', `arm7500fe', + `arm7tdmi', `arm7tdmi-s', `arm710t', `arm720t', `arm740t', + `strongarm', `strongarm110', `strongarm1100', `strongarm1110', + `arm8', `arm810', `arm9', `arm9e', `arm920', `arm920t', `arm922t', + `arm946e-s', `arm966e-s', `arm968e-s', `arm926ej-s', `arm940t', + `arm9tdmi', `arm10tdmi', `arm1020t', `arm1026ej-s', `arm10e', + `arm1020e', `arm1022e', `arm1136j-s', `arm1136jf-s', `mpcore', + `mpcorenovfp', `arm1156t2-s', `arm1156t2f-s', `arm1176jz-s', + `arm1176jzf-s', `cortex-a5', `cortex-a7', `cortex-a8', `cortex-a9', + `cortex-a15', `cortex-r4', `cortex-r4f', `cortex-r5', `cortex-m4', + `cortex-m3', `cortex-m1', `cortex-m0', `cortex-m0plus', + `marvell-pj4', `xscale', `iwmmxt', `iwmmxt2', `ep9312', `fa526', + `fa626', `fa606te', `fa626te', `fmp626', `fa726te'. `-mtune=generic-ARCH' specifies that GCC should tune the performance for a blend of processors within architecture ARCH. @@ -11138,19 +11145,24 @@ architectures: Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. -`-march=NAME' - This specifies the name of the target ARM architecture. GCC uses - this name to determine what kind of instructions it can emit when - generating assembly code. This option can be used in conjunction - with or instead of the `-mcpu=' option. Permissible names are: - `armv2', `armv2a', `armv3', `armv3m', `armv4', `armv4t', `armv5', - `armv5t', `armv5e', `armv5te', `armv6', `armv6j', `armv6t2', - `armv6z', `armv6zk', `armv6-m', `armv7', `armv7-a', `armv7-r', - `armv7-m', `armv8-a', `iwmmxt', `iwmmxt2', `ep9312'. +`-mcpu=NAME' + This specifies the name of the target ARM processor. GCC uses + this name to derive the name of the target ARM architecture (as if + specified by `-march') and the ARM processor type for which to + tune for performance (as if specified by `-mtune'). Where this + option is used in conjunction with `-march' or `-mtune', those + options take precedence over the appropriate part of this option. - `-march=native' causes the compiler to auto-detect the architecture - of the build computer. At present, this feature is only supported - on Linux, and not all architectures are recognized. If the + Permissible names for this option are the same as those for + `-mtune'. + + `-mcpu=generic-ARCH' is also permissible, and is equivalent to + `-march=ARCH -mtune=generic-ARCH'. See `-mtune' for more + information. + + `-mcpu=native' causes the compiler to auto-detect the CPU of the + build computer. At present, this feature is only supported on + Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. `-mfpu=NAME' @@ -11229,8 +11241,11 @@ architectures: appropriate value before execution begins. `-mpic-register=REG' - Specify the register to be used for PIC addressing. The default - is R10 unless stack-checking is enabled, when R9 is used. + Specify the register to be used for PIC addressing. For standard + PIC base case, the default will be any suitable register + determined by compiler. For single PIC base case, the default is + `R9' if target is EABI based or stack-checking is enabled, + otherwise the default is `R10'. `-mpoke-function-name' Write the name of each function into the text section, directly @@ -11366,7 +11381,7 @@ These options are defined for AVR implementations: `attiny87', `attiny88', `at86rf401'. `avr3' - "Classic" devices with 16 KiB up to 64 KiB of program memory. + "Classic" devices with 16 KiB up to 64 KiB of program memory. MCU = `at43usb355', `at76c711'. `avr31' @@ -11390,33 +11405,29 @@ These options are defined for AVR implementations: `avr5' "Enhanced" devices with 16 KiB up to 64 KiB of program memory. MCU = `ata5790', `ata5790n', `ata5795', `atmega16', - `atmega16a', `atmega16hva', `atmega16hva', `atmega16hva2', - `atmega16hva2', `atmega16hvb', `atmega16hvb', - `atmega16hvbrevb', `atmega16m1', `atmega16m1', `atmega16u4', - `atmega16u4', `atmega161', `atmega162', `atmega163', - `atmega164a', `atmega164p', `atmega164pa', `atmega165', - `atmega165a', `atmega165p', `atmega165pa', `atmega168', - `atmega168a', `atmega168p', `atmega168pa', `atmega169', - `atmega169a', `atmega169p', `atmega169pa', `atmega26hvg', - `atmega32', `atmega32a', `atmega32a', `atmega32c1', - `atmega32c1', `atmega32hvb', `atmega32hvb', - `atmega32hvbrevb', `atmega32m1', `atmega32m1', `atmega32u4', - `atmega32u4', `atmega32u6', `atmega32u6', `atmega323', - `atmega324a', `atmega324p', `atmega324pa', `atmega325', - `atmega325a', `atmega325p', `atmega3250', `atmega3250a', - `atmega3250p', `atmega3250pa', `atmega328', `atmega328p', - `atmega329', `atmega329a', `atmega329p', `atmega329pa', - `atmega3290', `atmega3290a', `atmega3290p', `atmega3290pa', - `atmega406', `atmega48hvf', `atmega64', `atmega64a', - `atmega64c1', `atmega64c1', `atmega64hve', `atmega64m1', - `atmega64m1', `atmega64rfa2', `atmega64rfr2', `atmega640', - `atmega644', `atmega644a', `atmega644p', `atmega644pa', - `atmega645', `atmega645a', `atmega645p', `atmega6450', - `atmega6450a', `atmega6450p', `atmega649', `atmega649a', - `atmega649p', `atmega6490', `atmega6490a', `atmega6490p', - `at90can32', `at90can64', `at90pwm161', `at90pwm216', - `at90pwm316', `at90scr100', `at90usb646', `at90usb647', - `at94k', `m3000'. + `atmega16a', `atmega16hva', `atmega16hva2', `atmega16hvb', + `atmega16hvbrevb', `atmega16m1', `atmega16u4', `atmega161', + `atmega162', `atmega163', `atmega164a', `atmega164p', + `atmega164pa', `atmega165', `atmega165a', `atmega165p', + `atmega165pa', `atmega168', `atmega168a', `atmega168p', + `atmega168pa', `atmega169', `atmega169a', `atmega169p', + `atmega169pa', `atmega26hvg', `atmega32', `atmega32a', + `atmega32c1', `atmega32hvb', `atmega32hvbrevb', `atmega32m1', + `atmega32u4', `atmega32u6', `atmega323', `atmega324a', + `atmega324p', `atmega324pa', `atmega325', `atmega325a', + `atmega325p', `atmega3250', `atmega3250a', `atmega3250p', + `atmega3250pa', `atmega328', `atmega328p', `atmega329', + `atmega329a', `atmega329p', `atmega329pa', `atmega3290', + `atmega3290a', `atmega3290p', `atmega3290pa', `atmega406', + `atmega48hvf', `atmega64', `atmega64a', `atmega64c1', + `atmega64hve', `atmega64m1', `atmega64rfa2', `atmega64rfr2', + `atmega640', `atmega644', `atmega644a', `atmega644p', + `atmega644pa', `atmega645', `atmega645a', `atmega645p', + `atmega6450', `atmega6450a', `atmega6450p', `atmega649', + `atmega649a', `atmega649p', `atmega6490', `atmega6490a', + `atmega6490p', `at90can32', `at90can64', `at90pwm161', + `at90pwm216', `at90pwm316', `at90scr100', `at90usb646', + `at90usb647', `at94k', `m3000'. `avr51' "Enhanced" devices with 128 KiB of program memory. @@ -11488,7 +11499,7 @@ These options are defined for AVR implementations: `-mbranch-cost=COST' Set the branch costs for conditional branch instructions to COST. - Reasonable values for COST are small, non-negative integers. The + Reasonable values for COST are small, non-negative integers. The default branch cost is 0. `-mcall-prologues' @@ -11512,7 +11523,7 @@ These options are defined for AVR implementations: linker is called. Jump relaxing is performed by the linker because jump offsets are - not known before code is located. Therefore, the assembler code + not known before code is located. Therefore, the assembler code generated by the compiler is the same, but the instructions in the executable may differ from instructions in the assembler code. @@ -11581,12 +11592,12 @@ the compiler and are subject to some limitations: prologue/epilogue. * For indirect calls to functions and computed goto, the linker - generates _stubs_. Stubs are jump pads sometimes also called - _trampolines_. Thus, the indirect call/jump jumps to such a stub. + generates _stubs_. Stubs are jump pads sometimes also called + _trampolines_. Thus, the indirect call/jump jumps to such a stub. The stub contains a direct jump to the desired address. * Linker relaxation must be turned on so that the linker will - generate the stubs correctly an all situaltion. See the compiler + generate the stubs correctly an all situaltion. See the compiler option `-mrelax' and the linler option `--relax'. There are corner cases where the linker is supposed to generate stubs but aborts without relaxation and without a helpful error message. @@ -11598,7 +11609,7 @@ the compiler and are subject to some limitations: points to. * The startup code from libgcc never sets `EIND'. Notice that - startup code is a blend of code from libgcc and AVR-LibC. For the + startup code is a blend of code from libgcc and AVR-LibC. For the impact of AVR-LibC on `EIND', see the AVR-LibC user manual (http://nongnu.org/avr-libc/user-manual/). @@ -11639,7 +11650,7 @@ the compiler and are subject to some limitations: - If prologue-save function is used, see `-mcall-prologues' command-line option. - - Switch/case dispatch tables. If you do not want such dispatch + - Switch/case dispatch tables. If you do not want such dispatch tables you can specify the `-fno-jump-tables' command-line option. @@ -11771,7 +11782,7 @@ Spaces:: and *note AVR Built-in Functions::. also means that the program counter (PC) is 3 bytes wide. `__AVR_2_BYTE_PC__' - The program counter (PC) is 2 bytes wide. This is the case for + The program counter (PC) is 2 bytes wide. This is the case for devices with up to 128 KiB of program memory. `__AVR_HAVE_8BIT_SP__' @@ -11869,7 +11880,7 @@ File: gcc.info, Node: Blackfin Options, Next: C6X Options, Prev: AVR Options, `-mspecld-anomaly' When enabled, the compiler ensures that the generated code does not - contain speculative loads after jump instructions. If this option + contain speculative loads after jump instructions. If this option is used, `__WORKAROUND_SPECULATIVE_LOADS' is defined. `-mno-specld-anomaly' @@ -11950,7 +11961,7 @@ File: gcc.info, Node: Blackfin Options, Next: C6X Options, Prev: AVR Options, handle function calls via function pointers. `-mfast-fp' - Link with the fast floating-point library. This library relaxes + Link with the fast floating-point library. This library relaxes some of the IEEE floating-point standard's rules for checking inputs against Not-a-Number (NAN), in the interest of performance. @@ -11975,14 +11986,14 @@ File: gcc.info, Node: Blackfin Options, Next: C6X Options, Prev: AVR Options, `-mcorea' Build a standalone application for Core A of BF561 when using the - one-application-per-core programming model. Proper start files and + one-application-per-core programming model. Proper start files and link scripts are used to support Core A, and the macro `__BFIN_COREA' is defined. This option can only be used in conjunction with `-mmulticore'. `-mcoreb' Build a standalone application for Core B of BF561 when using the - one-application-per-core programming model. Proper start files and + one-application-per-core programming model. Proper start files and link scripts are used to support Core B, and the macro `__BFIN_COREB' is defined. When this option is used, `coreb_main' should be used instead of `main'. This option can only be used in @@ -12154,7 +12165,7 @@ File: gcc.info, Node: CR16 Options, Next: Darwin Options, Prev: CRIS Options, These options are defined specifically for the CR16 ports. `-mmac' - Enable the use of multiply-accumulate instructions. Disabled by + Enable the use of multiply-accumulate instructions. Disabled by default. `-mcr16cplus' @@ -12393,7 +12404,7 @@ These `-m' options are defined for the DEC Alpha implementations: operations. Unless they are replaced by routines that emulate the floating-point operations, or compiled in such a way as to call such emulations routines, these routines issue floating-point - operations. If you are compiling for an Alpha without + operations. If you are compiling for an Alpha without floating-point operations, you must ensure that the library is built so as not to call them. @@ -13289,9 +13300,15 @@ computers: SSSE3, SSE4.1, SSE4.2, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C instruction set support. + `core-avx2' + Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, + SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AES, PCLMUL, + FSGSBASE, RDRND, FMA, BMI, BMI2 and F16C instruction set + support. + `atom' - Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 - and SSSE3 instruction set support. + Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, + SSE3 and SSSE3 instruction set support. `k6' AMD K6 CPU with MMX instruction set support. @@ -13369,7 +13386,7 @@ computers: `winchip2' IDT WinChip 2 CPU, dealt in same way as i486 with additional - MMX and 3DNow! instruction set support. + MMX and 3DNow! instruction set support. `c3' VIA C3 CPU with MMX and 3DNow! instruction set support. (No @@ -13558,7 +13575,7 @@ computers: `-mlong-double-80' These switches control the size of `long double' type. A size of 64 bits makes the `long double' type equivalent to the `double' - type. This is the default for Bionic C library. + type. This is the default for Bionic C library. *Warning:* if you override the default value for your target ABI, this changes the size of structures and arrays containing `long @@ -13763,7 +13780,7 @@ computers: These switches enable or disable the use of instructions in the MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM, BMI, BMI2, - LZCNT, RTM or 3DNow! extended instruction sets. These extensions + LZCNT, RTM or 3DNow! extended instruction sets. These extensions are also available as built-in functions: see *note X86 Built-in Functions::, for details of the functions enabled and disabled by these switches. @@ -14108,7 +14125,7 @@ These additional options are available for Microsoft Windows targets: specifies that the `dllimport' attribute should be ignored. `-mthread' - This option is available for MinGW targets. It specifies that + This option is available for MinGW targets. It specifies that MinGW-specific thread support is to be used. `-municode' @@ -14128,7 +14145,7 @@ These additional options are available for Microsoft Windows targets: the linker to set the PE header subsystem type appropriately. `-fno-set-stack-executable' - This option is available for MinGW targets. It specifies that the + This option is available for MinGW targets. It specifies that the executable flag for the stack used by nested functions isn't set. This is necessary for binaries running in kernel mode of Microsoft Windows, as there the User32 API, which is used to set executable @@ -15080,7 +15097,7 @@ File: gcc.info, Node: MicroBlaze Options, Next: MIPS Options, Prev: MeP Optio instead. `-mcpu=CPU-TYPE' - Use features of, and schedule code for, the given CPU. Supported + Use features of, and schedule code for, the given CPU. Supported values are in the format `vX.YY.Z', where X is a major version, YY is the minor version, and Z is compatibility code. Example values are `v3.00.a', `v4.00.b', `v5.00.a', `v5.00.b', `v5.00.b', @@ -15132,20 +15149,20 @@ File: gcc.info, Node: MicroBlaze Options, Next: MIPS Options, Prev: MeP Optio `xmdstub' for use with Xilinx Microprocessor Debugger (XMD) based - software intrusive debug agent called xmdstub. This uses + software intrusive debug agent called xmdstub. This uses startup file `crt1.o' and sets the start address of the program to 0x800. `bootstrap' for applications that are loaded using a bootloader. This model uses startup file `crt2.o' which does not contain a - processor reset vector handler. This is suitable for + processor reset vector handler. This is suitable for transferring control on a processor reset to the bootloader rather than the application. `novectors' for applications that do not require any of the MicroBlaze - vectors. This option may be useful for applications running + vectors. This option may be useful for applications running within a monitoring application. This model uses `crt3.o' as a startup file. @@ -16275,6 +16292,8 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: -mpopcntb -mpopcntd -mpowerpc64 -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float -msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx + -mcrypto -mdirect-move -mpower8-fusion -mpower8-vector + -mquad-memory -mquad-memory-atomic The particular options set for any particular CPU varies between compiler versions, depending on what setting seems to produce @@ -16318,6 +16337,36 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: `-mabi=altivec' to adjust the current ABI with AltiVec ABI enhancements. + When `-maltivec' is used, rather than `-maltivec=le' or + `-maltivec=be', the element order for Altivec intrinsics such as + `vec_splat', `vec_extract', and `vec_insert' will match array + element order corresponding to the endianness of the target. That + is, element zero identifies the leftmost element in a vector + register when targeting a big-endian platform, and identifies the + rightmost element in a vector register when targeting a + little-endian platform. + +`-maltivec=be' + Generate Altivec instructions using big-endian element order, + regardless of whether the target is big- or little-endian. This is + the default when targeting a big-endian platform. + + The element order is used to interpret element numbers in Altivec + intrinsics such as `vec_splat', `vec_extract', and `vec_insert'. + By default, these will match array element order corresponding to + the endianness for the target. + +`-maltivec=le' + Generate Altivec instructions using little-endian element order, + regardless of whether the target is big- or little-endian. This is + the default when targeting a little-endian platform. This option + is currently ignored when targeting a big-endian platform. + + The element order is used to interpret element numbers in Altivec + intrinsics such as `vec_splat', `vec_extract', and `vec_insert'. + By default, these will match array element order corresponding to + the endianness for the target. + `-mvrsave' `-mno-vrsave' Generate VRSAVE instructions when generating AltiVec code. @@ -16368,6 +16417,43 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: instructions, and also enable the use of built-in functions that allow more direct access to the VSX instruction set. +`-mcrypto' +`-mno-crypto' + Enable the use (disable) of the built-in functions that allow + direct access to the cryptographic instructions that were added in + version 2.07 of the PowerPC ISA. + +`-mdirect-move' +`-mno-direct-move' + Generate code that uses (does not use) the instructions to move + data between the general purpose registers and the vector/scalar + (VSX) registers that were added in version 2.07 of the PowerPC ISA. + +`-mpower8-fusion' +`-mno-power8-fusion' + Generate code that keeps (does not keeps) some integer operations + adjacent so that the instructions can be fused together on power8 + and later processors. + +`-mpower8-vector' +`-mno-power8-vector' + Generate code that uses (does not use) the vector and scalar + instructions that were added in version 2.07 of the PowerPC ISA. + Also enable the use of built-in functions that allow more direct + access to the vector instructions. + +`-mquad-memory' +`-mno-quad-memory' + Generate code that uses (does not use) the non-atomic quad word + memory instructions. The `-mquad-memory' option requires use of + 64-bit mode. + +`-mquad-memory-atomic' +`-mno-quad-memory-atomic' + Generate code that uses (does not use) the atomic quad word memory + instructions. The `-mquad-memory-atomic' option requires use of + 64-bit mode. + `-mfloat-gprs=YES/SINGLE/DOUBLE/NO' `-mfloat-gprs' This switch enables or disables the generation of floating-point @@ -16535,7 +16621,7 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: `-mavoid-indexed-addresses' `-mno-avoid-indexed-addresses' Generate code that tries to avoid (not avoid) the use of indexed - load or store instructions. These instructions can incur a + load or store instructions. These instructions can incur a performance penalty on Power6 processors in certain situations, such as when stepping through large arrays that cross a 16M boundary. This option is enabled by default when targeting Power6 @@ -16654,7 +16740,7 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: `store_to_load' Any dependence from store to load is costly. - NUMBER + NUMBER Any dependence for which the latency is greater than or equal to NUMBER is costly. @@ -16676,7 +16762,7 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: insn to a new group, according to the estimated processor grouping. - NUMBER + NUMBER Insert NOPs to force costly dependent insns into separate groups. Insert NUMBER NOPs to force an insn to a new group. @@ -16724,7 +16810,7 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: `-mabi=ABI-TYPE' Extend the current ABI with a particular extension, or remove such extension. Valid values are ALTIVEC, NO-ALTIVEC, SPE, NO-SPE, - IBMLONGDOUBLE, IEEELONGDOUBLE. + IBMLONGDOUBLE, IEEELONGDOUBLE, ELFV1, ELFV2. `-mabi=spe' Extend the current ABI with SPE ABI extensions. This does not @@ -16742,6 +16828,18 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: Change the current ABI to use IEEE extended-precision long double. This is a PowerPC 32-bit Linux ABI option. +`-mabi=elfv1' + Change the current ABI to use the ELFv1 ABI. This is the default + ABI for big-endian PowerPC 64-bit Linux. Overriding the default + ABI requires special system support and is likely to fail in + spectacular ways. + +`-mabi=elfv2' + Change the current ABI to use the ELFv2 ABI. This is the default + ABI for little-endian PowerPC 64-bit Linux. Overriding the + default ABI requires special system support and is likely to fail + in spectacular ways. + `-mprototype' `-mno-prototype' On System V.4 and embedded PowerPC systems assume that all calls to @@ -16992,6 +17090,22 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: the call through the pointer. The `-mno-save-toc-indirect' option is the default. +`-mcompat-align-parm' +`-mno-compat-align-parm' + Generate (do not generate) code to pass structure parameters with a + maximum alignment of 64 bits, for compatibility with older versions + of GCC. + + Older versions of GCC (prior to 4.9.0) incorrectly did not align a + structure parameter on a 128-bit boundary when that structure + contained a member requiring 128-bit alignment. This is corrected + in more recent versions of GCC. This option may be used to + generate code that is compatible with functions compiled with + older versions of GCC. + + In this version of the compiler, the `-mcompat-align-parm' is the + default, except when using the Linux ELFv2 ABI. + File: gcc.info, Node: RX Options, Next: S/390 and zSeries Options, Prev: RS/6000 and PowerPC Options, Up: Submodel Options @@ -17024,7 +17138,7 @@ These command-line options are defined for RX targets: `-mcpu=NAME' Selects the type of RX CPU to be targeted. Currently three types are supported, the generic RX600 and RX200 series hardware and the - specific RX610 CPU. The default is RX600. + specific RX610 CPU. The default is RX600. The only difference between RX600 and RX610 is that the RX610 does not support the `MVTIPL' instruction. @@ -17180,7 +17294,7 @@ architecture. `-mlong-double-128' These switches control the size of `long double' type. A size of 64 bits makes the `long double' type equivalent to the `double' - type. This is the default. + type. This is the default. `-mbackchain' `-mno-backchain' @@ -17321,6 +17435,20 @@ architecture. value given by STACK-SIZE. The STACK-GUARD option can only be used in conjunction with STACK-SIZE. +`-mhotpatch[=HALFWORDS]' +`-mno-hotpatch' + If the hotpatch option is enabled, a "hot-patching" function + prologue is generated for all functions in the compilation unit. + The funtion label is prepended with the given number of two-byte + Nop instructions (HALFWORDS, maximum 1000000) or 12 Nop + instructions if no argument is present. Functions with a + hot-patching prologue are never inlined automatically, and a + hot-patching prologue is never generated for functions functions + that are explicitly inline. + + This option can be overridden for individual functions with the + `hotpatch' attribute. + File: gcc.info, Node: Score Options, Next: SH Options, Prev: S/390 and zSeries Options, Up: Submodel Options @@ -17342,7 +17470,7 @@ These options are defined for Score implementations: Enable generation of unaligned load and store instructions. `-mmac' - Enable the use of multiply-accumulate instructions. Disabled by + Enable the use of multiply-accumulate instructions. Disabled by default. `-mscore5' @@ -17669,7 +17797,7 @@ These `-m' options are defined for the SH implementations: Calls a library function that performs the operation in double precision floating point. Division by zero causes a floating-point exception. This is the default for SHcompact - with FPU. Specifying this for targets that do not have a + with FPU. Specifying this for targets that do not have a double precision FPU will default to `call-div1'. `call-table' @@ -17853,7 +17981,9 @@ These `-m' options are supported on the SPARC: `-mapp-regs' Specify `-mapp-regs' to generate output using the global registers 2 through 4, which the SPARC SVR4 ABI reserves for applications. - This is the default. + Like the global register 1, each global register 2 through 4 is + then treated as an allocable register that is clobbered by + function calls. This is the default. To be fully SVR4 ABI-compliant at the cost of some performance loss, specify `-mno-app-regs'. You should compile libraries and @@ -17923,6 +18053,12 @@ These `-m' options are supported on the SPARC: default because it results in a performance loss, especially for floating-point code. +`-muser-mode' +`-mno-user-mode' + Do not generate code that can only run in supervisor mode. This + is relevant only for the `casa' instruction emitted for the LEON3 + processor. The default is `-mno-user-mode'. + `-mno-faster-structs' `-mfaster-structs' With `-mfaster-structs', the compiler assumes that structures @@ -17938,9 +18074,9 @@ These `-m' options are supported on the SPARC: Set the instruction set, register set, and instruction scheduling parameters for machine type CPU_TYPE. Supported values for CPU_TYPE are `v7', `cypress', `v8', `supersparc', `hypersparc', - `leon', `sparclite', `f930', `f934', `sparclite86x', `sparclet', - `tsc701', `v9', `ultrasparc', `ultrasparc3', `niagara', - `niagara2', `niagara3', and `niagara4'. + `leon', `leon3', `sparclite', `f930', `f934', `sparclite86x', + `sparclet', `tsc701', `v9', `ultrasparc', `ultrasparc3', + `niagara', `niagara2', `niagara3' and `niagara4'. Native Solaris and GNU/Linux toolchains also support the value `native', which selects the best architecture option for the host @@ -17954,19 +18090,19 @@ These `-m' options are supported on the SPARC: Here is a list of each supported architecture and their supported implementations. - v7 + v7 cypress - v8 - supersparc, hypersparc, leon + v8 + supersparc, hypersparc, leon, leon3 - sparclite + sparclite f930, f934, sparclite86x - sparclet + sparclet tsc701 - v9 + v9 ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4 By default (unless configured otherwise), GCC generates code for @@ -18021,7 +18157,7 @@ These `-m' options are supported on the SPARC: The same values for `-mcpu=CPU_TYPE' can be used for `-mtune=CPU_TYPE', but the only useful values are those that select a particular CPU implementation. Those are `cypress', - `supersparc', `hypersparc', `leon', `f930', `f934', + `supersparc', `hypersparc', `leon', `leon3', `f930', `f934', `sparclite86x', `tsc701', `ultrasparc', `ultrasparc3', `niagara', `niagara2', `niagara3' and `niagara4'. With native Solaris and GNU/Linux toolchains, `native' can also be used. @@ -18081,6 +18217,10 @@ These `-m' options are supported on the SPARC: Atmel AT697F processor (which corresponds to erratum #13 of the AT697E processor). +`-mfix-ut699' + Enable the documented workarounds for the floating-point errata + and the data cache nullify errata of the UT699 processor. + These `-m' options are supported in addition to the above on SPARC-V9 processors in 64-bit environments: @@ -18408,7 +18548,7 @@ These `-m' options are defined for V850 implementations: is used. `-mv850es' - Specify that the target processor is the V850ES. This is an alias + Specify that the target processor is the V850ES. This is an alias for the `-mv850e1' option. `-mv850e' @@ -18460,7 +18600,7 @@ These `-m' options are defined for V850 implementations: `-mrh850-abi' `-mghs' - Enables support for the RH850 version of the V850 ABI. This is the + Enables support for the RH850 version of the V850 ABI. This is the default. With this version of the ABI the following rules apply: * Integer sized structures and unions are returned via a memory @@ -18481,7 +18621,7 @@ These `-m' options are defined for V850 implementations: `__V850_RH850_ABI__' is defined. `-mgcc-abi' - Enables support for the old GCC version of the V850 ABI. With this + Enables support for the old GCC version of the V850 ABI. With this version of the ABI the following rules apply: * Integer sized structures and unions are returned in register @@ -18561,7 +18701,7 @@ These `-m' options are defined for the VMS implementations: Default to 64-bit memory allocation routines. `-mpointer-size=SIZE' - Set the default size of pointers. Possible options for SIZE are + Set the default size of pointers. Possible options for SIZE are `32' or `short' for 32 bit pointers, `64' or `long' for 64 bit pointers, and `no' for supporting only 32 bit pointers. The later option disables `pragma pointer_size'. @@ -18799,13 +18939,13 @@ form by either removing `no-' or adding it. } The lifetime of a compiler generated temporary is well defined by - the C++ standard. When a lifetime of a temporary ends, and if the + the C++ standard. When a lifetime of a temporary ends, and if the temporary lives in memory, the optimizing compiler has the freedom to reuse its stack space with other temporaries or scoped local - variables whose live range does not overlap with it. However some + variables whose live range does not overlap with it. However some of the legacy code relies on the behavior of older compilers in which temporaries' stack space is not reused, the aggressive stack - reuse can lead to runtime errors. This option is used to control + reuse can lead to runtime errors. This option is used to control the temporary stack reuse optimization. `-ftrapv' @@ -19419,7 +19559,7 @@ Controlling the Compilation Driver `gcc': (gccint)Driver. tries looking in the usual places for the subprogram. The default value of `GCC_EXEC_PREFIX' is `PREFIX/lib/gcc/' where - PREFIX is the prefix to the installed compiler. In many cases + PREFIX is the prefix to the installed compiler. In many cases PREFIX is the value of `prefix' when you ran the `configure' script. @@ -19998,9 +20138,9 @@ File: gcc.info, Node: Arrays and pointers implementation, Next: Hints implemen determined by the ABI. - ---------- Footnotes ---------- + ---------- Footnotes ---------- - (1) Future versions of GCC may zero-extend, or use a target-defined + (1) Future versions of GCC may zero-extend, or use a target-defined `ptr_extend' pattern. Do not rely on sign extension. @@ -20269,8 +20409,8 @@ File: gcc.info, Node: C++ Implementation, Next: C Extensions, Prev: C Impleme A conforming implementation of ISO C++ is required to document its choice of behavior in each of the areas that are designated "implementation defined". The following lists all such areas, along -with the section numbers from the ISO/IEC 14822:1998 and ISO/IEC -14822:2003 standards. Some areas are only implementation-defined in +with the section numbers from the ISO/IEC 14882:1998 and ISO/IEC +14882:2003 standards. Some areas are only implementation-defined in one version of the standard. Some choices depend on the externally determined ABI for the platform @@ -20650,9 +20790,9 @@ on them being always the same, inlining and cloning. If `&&foo' is used in a static variable initializer, inlining and cloning is forbidden. - ---------- Footnotes ---------- + ---------- Footnotes ---------- - (1) The analogous feature in Fortran is called an assigned goto, but + (1) The analogous feature in Fortran is called an assigned goto, but that name seems inappropriate in C, where one can do more than simply store label addresses in label variables. @@ -20825,7 +20965,7 @@ acting as mere forwarders for their arguments. the containing function. You should specify, for RESULT, a value returned by `__builtin_apply'. - -- Built-in Function: __builtin_va_arg_pack () + -- Built-in Function: __builtin_va_arg_pack () This built-in function represents all anonymous arguments of an inline function. It can be used only in inline functions that are always inlined, never compiled as a separate function, such as @@ -22463,7 +22603,7 @@ attributes. `thiscall' On the Intel 386, the `thiscall' attribute causes the compiler to pass the first argument (if of integral type) in the register ECX. - Subsequent and other typed arguments are passed on the stack. The + Subsequent and other typed arguments are passed on the stack. The called function pops the arguments off the stack. If the number of arguments is variable all arguments are pushed on the stack. The `thiscall' attribute is intended for C++ non-static member @@ -22613,11 +22753,11 @@ attributes. of these calls. On M16C/M32C targets, the `function_vector' attribute declares a - special page subroutine call function. Use of this attribute + special page subroutine call function. Use of this attribute reduces the code size by 2 bytes for each call generated to the - subroutine. The argument to the attribute is the vector number + subroutine. The argument to the attribute is the vector number entry from the special page vector table which contains the 16 - low-order bits of the subroutine's entry address. Each vector + low-order bits of the subroutine's entry address. Each vector table has special page number (18 to 255) that is used in `jsrs' instructions. Jump addresses of the routines are generated by adding 0x0F0000 (in case of M16C targets) or 0xFF0000 (in case of @@ -22812,7 +22952,7 @@ attributes. `l1_text' This attribute specifies a function to be placed into L1 - Instruction SRAM. The function is put into a specific section + Instruction SRAM. The function is put into a specific section named `.l1.text'. With `-mfdpic', function calls with a such function as the callee or caller uses inlined PLT. @@ -22963,6 +23103,14 @@ attributes. "hot-patching" function prologue used in Win32 API functions in Microsoft Windows XP Service Pack 2 and newer. +`hotpatch [(PROLOGUE-HALFWORDS)]' + On S/390 System z targets, you can use this function attribute to + make GCC generate a "hot-patching" function prologue. The + `hotpatch' has no effect on funtions that are explicitly inline. + If the `-mhotpatch' or `-mno-hotpatch' command-line option is used + at the same time, the `hotpatch' attribute takes precedence. If + an argument is given, the maximum allowed value is 1000000. + `naked' Use this attribute on the ARM, AVR, MCORE, RX and SPU ports to indicate that the specified function does not need @@ -23133,8 +23281,8 @@ attributes. The `OS_task' attribute can be used when there is _no guarantee_ that interrupts are disabled at that time when the function is - entered like for, e.g. task functions in a multi-threading - operating system. In that case, changing the stack pointer + entered like for, e.g. task functions in a multi-threading + operating system. In that case, changing the stack pointer register is guarded by save/clear/restore of the global interrupt enable flag. @@ -23149,7 +23297,7 @@ attributes. `pcs' The `pcs' attribute can be used to control the calling convention - used for a function on ARM. The attribute takes an argument that + used for a function on ARM. The attribute takes an argument that specifies the calling convention to use. When compiling using the AAPCS ABI (or a variant of it) then valid @@ -23259,7 +23407,7 @@ attributes. clobbered, as per the standard calling conventions. Solaris 8 is affected by this. Systems with the GNU C Library version 2.1 or higher and FreeBSD are believed to be safe since the loaders there - save EAX, EDX and ECX. (Lazy binding can be disabled with the + save EAX, EDX and ECX. (Lazy binding can be disabled with the linker or the loader if desired, to avoid the problem.) `sseregparm' @@ -23773,7 +23921,7 @@ attributes. The possible values of VISIBILITY_TYPE correspond to the visibility settings in the ELF gABI. - "default" + "default" Default visibility is the normal case for the object file format. This value is available for the visibility attribute to override other options that may change the assumed @@ -23789,13 +23937,13 @@ attributes. Default visibility corresponds to "external linkage" in the language. - "hidden" + "hidden" Hidden visibility indicates that the entity declared has a new form of linkage, which we call "hidden linkage". Two declarations of an object with hidden linkage refer to the same object if they are in the same shared object. - "internal" + "internal" Internal visibility is like hidden visibility, but with additional processor specific semantics. Unless otherwise specified by the psABI, GCC defines internal visibility to @@ -23807,7 +23955,7 @@ attributes. for instance omit the load of a PIC register since it is known that the calling function loaded the correct value. - "protected" + "protected" Protected visibility is like default visibility except that it indicates that references within the defining module bind to the definition in that module. That is, the declared entity @@ -26609,7 +26757,7 @@ _picoChip family--`picochip.h'_ 16-bit signed integer. -_PowerPC and IBM RS6000--`config/rs6000/rs6000.h'_ +_PowerPC and IBM RS6000--`config/rs6000/constraints.md'_ `b' Address base register @@ -26623,17 +26771,64 @@ _PowerPC and IBM RS6000--`config/rs6000/rs6000.h'_ `v' Altivec vector register + `wa' + Any VSX register if the -mvsx option was used or NO_REGS. + `wd' - VSX vector register to hold vector double data + VSX vector register to hold vector double data or NO_REGS. `wf' - VSX vector register to hold vector float data + VSX vector register to hold vector float data or NO_REGS. + + `wg' + If `-mmfpgpr' was used, a floating point register or NO_REGS. + + `wl' + Floating point register if the LFIWAX instruction is enabled + or NO_REGS. + + `wm' + VSX register if direct move instructions are enabled, or + NO_REGS. + + `wn' + No register (NO_REGS). + + `wr' + General purpose register if 64-bit instructions are enabled + or NO_REGS. `ws' - VSX vector register to hold scalar float data + VSX vector register to hold scalar double values or NO_REGS. - `wa' - Any VSX register + `wt' + VSX vector register to hold 128 bit integer or NO_REGS. + + `wu' + Altivec register to use for float/32-bit int loads/stores or + NO_REGS. + + `wv' + Altivec register to use for double loads/stores or NO_REGS. + + `ww' + FP or VSX register to perform float operations under `-mvsx' + or NO_REGS. + + `wx' + Floating point register if the STFIWX instruction is enabled + or NO_REGS. + + `wy' + VSX vector register to hold scalar float values or NO_REGS. + + `wz' + Floating point register if the LFIWZX instruction is enabled + or NO_REGS. + + `wQ' + A memory address that will work with the `lq' and `stq' + instructions. `h' `MQ', `CTR', or `LINK' register @@ -27058,7 +27253,7 @@ _Blackfin family--`config/bfin/constraints.md'_ M register `c' - Registers used for circular buffering, i.e. I, B, or L + Registers used for circular buffering, i.e. I, B, or L registers. `C' @@ -28608,7 +28803,7 @@ assignment, for example `r0' below: register int *p2 asm ("r1") = ...; In those cases, a solution is to use a temporary variable for each -arbitrary expression. *Note Example of asm with clobbered asm reg::. +arbitrary expression. *Note Example of asm with clobbered asm reg::. File: gcc.info, Node: Alternate Keywords, Next: Incomplete Enums, Prev: Explicit Reg Vars, Up: C Extensions @@ -28832,7 +29027,7 @@ corresponding mode of `foo' is V4SI. The `vector_size' attribute is only applicable to integral and float scalars, although arrays, pointers, and function return values are -allowed in conjunction with this construct. Only sizes that are a power +allowed in conjunction with this construct. Only sizes that are a power of two are currently allowed. All the basic integer types can be used as base types, both as signed @@ -28869,13 +29064,13 @@ elements in the operand. It is possible to use shifting operators `<<', `>>' on integer-type vectors. The operation is defined as following: `{a0, a1, ..., an} >> -{b0, b1, ..., bn} == {a0 >> b0, a1 >> b1, ..., an >> bn}'. Vector +{b0, b1, ..., bn} == {a0 >> b0, a1 >> b1, ..., an >> bn}'. Vector operands must have the same number of elements. For convenience, it is allowed to use a binary vector operation where -one operand is a scalar. In that case the compiler transforms the +one operand is a scalar. In that case the compiler transforms the scalar operand into a vector where each element is the scalar from the -operation. The transformation happens only if the scalar could be +operation. The transformation happens only if the scalar could be safely converted to the vector-element type. Consider the following code. @@ -28903,7 +29098,7 @@ operands with a signed integral element type. Vectors are compared element-wise producing 0 when comparison is false and -1 (constant of the appropriate type where all bits are set) -otherwise. Consider the following example. +otherwise. Consider the following example. typedef int v4si __attribute__ ((vector_size (16))); @@ -29241,7 +29436,7 @@ values ensures proper usage. model can be used here. False is returned otherwise, and the execution is considered to - conform to FAILURE_MEMMODEL. This memory model cannot be + conform to FAILURE_MEMMODEL. This memory model cannot be `__ATOMIC_RELEASE' nor `__ATOMIC_ACQ_REL'. It also cannot be a stronger model than that specified by SUCCESS_MEMMODEL. @@ -29268,7 +29463,7 @@ values ensures proper usage. -- Built-in Function: TYPE __atomic_nand_fetch (TYPE *ptr, TYPE val, int memmodel) These built-in functions perform the operation suggested by the - name, and return the result of the operation. That is, + name, and return the result of the operation. That is, { *ptr OP= val; return *ptr; } @@ -29301,14 +29496,19 @@ values ensures proper usage. This built-in function performs an atomic test-and-set operation on the byte at `*PTR'. The byte is set to some implementation defined nonzero "set" value and the return value is `true' if and - only if the previous contents were "set". + only if the previous contents were "set". It should be only used + for operands of type `bool' or `char'. For other types only part + of the value may be set. All memory models are valid. -- Built-in Function: void __atomic_clear (bool *ptr, int memmodel) This built-in function performs an atomic clear operation on - `*PTR'. After the operation, `*PTR' contains 0. + `*PTR'. After the operation, `*PTR' contains 0. It should be + only used for operands of type `bool' or `char' and in conjunction + with `__atomic_test_and_set'. For other types it may only clear + partially. If the type is not `bool' prefer using `__atomic_store'. The valid memory model variants are `__ATOMIC_RELAXED', `__ATOMIC_SEQ_CST', and `__ATOMIC_RELEASE'. @@ -29371,17 +29571,19 @@ specified in addition to an existing memory model to atomic intrinsics. End lock elision on a lock variable. Memory model must be `__ATOMIC_RELEASE' or stronger. - When a lock acquire fails it's required for good performance to abort + When a lock acquire fails it is required for good performance to abort the transaction quickly. This can be done with a `_mm_pause' #include <immintrin.h> // For _mm_pause + int lockvar; + /* Acquire lock with lock elision */ while (__atomic_exchange_n(&lockvar, 1, __ATOMIC_ACQUIRE|__ATOMIC_HLE_ACQUIRE)) _mm_pause(); /* Abort failed transaction */ ... /* Free lock with lock elision */ - __atomic_clear(&lockvar, __ATOMIC_RELEASE|__ATOMIC_HLE_RELEASE); + __atomic_store_n(&lockvar, 0, __ATOMIC_RELEASE|__ATOMIC_HLE_RELEASE); File: gcc.info, Node: Object Size Checking, Next: Other Builtins, Prev: x86 specific memory model extensions for transactional memory, Up: C Extensions @@ -30136,7 +30338,9 @@ instructions, but allow the compiler to schedule those calls. * picoChip Built-in Functions:: * PowerPC Built-in Functions:: * PowerPC AltiVec/VSX Built-in Functions:: +* PowerPC Hardware Transactional Memory Built-in Functions:: * RX Built-in Functions:: +* S/390 System z Built-in Functions:: * SH Built-in Functions:: * SPARC VIS Built-in Functions:: * SPU Built-in Functions:: @@ -36231,7 +36435,7 @@ starts at `0'. If the address does not point to flash memory, return unsigned char __builtin_avr_insert_bits (unsigned long map, unsigned char bits, unsigned char val) -Insert bits from BITS into VAL and return the resulting value. The +Insert bits from BITS into VAL and return the resulting value. The nibbles of MAP determine how the insertion is performed: Let X be the N-th nibble of MAP 1. If X is `0xf', then the N-th bit of VAL is returned unaltered. @@ -36243,7 +36447,7 @@ N-th nibble of MAP undefined. One typical use case for this built-in is adjusting input and output -values to non-contiguous port layouts. Some examples: +values to non-contiguous port layouts. Some examples: // same as val, bits is unused __builtin_avr_insert_bits (0xffffffff, bits, val) @@ -36427,22 +36631,22 @@ Function prototype Example usage Assembly output `void __MQMACHS (acc, sw2, sw2)' `__MQMACHS (C, A, B)' `MQMACHS A,B,C' `void __MQMACHU (acc, uw2, uw2)' `__MQMACHU (C, A, B)' `MQMACHU A,B,C' `void __MQMACXHS (acc, sw2, `__MQMACXHS (C, A, B)' `MQMACXHS A,B,C' -sw2)' +sw2)' `void __MQMULHS (acc, sw2, sw2)' `__MQMULHS (C, A, B)' `MQMULHS A,B,C' `void __MQMULHU (acc, uw2, uw2)' `__MQMULHU (C, A, B)' `MQMULHU A,B,C' `void __MQMULXHS (acc, sw2, `__MQMULXHS (C, A, B)' `MQMULXHS A,B,C' -sw2)' +sw2)' `void __MQMULXHU (acc, uw2, `__MQMULXHU (C, A, B)' `MQMULXHU A,B,C' -uw2)' +uw2)' `sw2 __MQSATHS (sw2, sw2)' `C = __MQSATHS (A, B)' `MQSATHS A,B,C' `uw2 __MQSLLHI (uw2, int)' `C = __MQSLLHI (A, B)' `MQSLLHI A,B,C' `sw2 __MQSRAHI (sw2, int)' `C = __MQSRAHI (A, B)' `MQSRAHI A,B,C' `sw2 __MQSUBHSS (sw2, sw2)' `C = __MQSUBHSS (A, B)' `MQSUBHSS A,B,C' `uw2 __MQSUBHUS (uw2, uw2)' `C = __MQSUBHUS (A, B)' `MQSUBHUS A,B,C' `void __MQXMACHS (acc, sw2, `__MQXMACHS (C, A, B)' `MQXMACHS A,B,C' -sw2)' +sw2)' `void __MQXMACXHS (acc, sw2, `__MQXMACXHS (C, A, B)' `MQXMACXHS A,B,C' -sw2)' +sw2)' `uw1 __MRDACC (acc)' `B = __MRDACC (A)' `MRDACC A,B' `uw1 __MRDACCG (acc)' `B = __MRDACCG (A)' `MRDACCG A,B' `uw1 __MROTLI (uw1, const)' `C = __MROTLI (A, B)' `MROTLI A,#B,C' @@ -37847,8 +38051,8 @@ that is part of the name. v2si __builtin_ia32_pswapdsi (v2si) The following built-in functions are available when `-mrtm' is used -They are used for restricted transactional memory. These are the -internal low level functions. Normally the functions in *note X86 +They are used for restricted transactional memory. These are the +internal low level functions. Normally the functions in *note X86 transactional memory intrinsics:: should be used instead. int __builtin_ia32_xbegin () @@ -37862,7 +38066,7 @@ File: gcc.info, Node: X86 transactional memory intrinsics, Next: MIPS DSP Buil 6.56.8 X86 transaction memory intrinsics ---------------------------------------- -Hardware transactional memory intrinsics for i386. These allow to use +Hardware transactional memory intrinsics for i386. These allow to use memory transactions with RTM (Restricted Transactional Memory). For using HLE (Hardware Lock Elision) see *note x86 specific memory model extensions for transactional memory:: instead. This support is enabled @@ -37915,8 +38119,8 @@ and suitable fallback code always needs to be supplied. Transaction abort in a inner nested transaction -- RTM Function: void _xend () - Commit the current transaction. When no transaction is active this - will fault. All memory side effects of the transactions will + Commit the current transaction. When no transaction is active this + will fault. All memory side effects of the transactions will become visible to other threads in an atomic matter. -- RTM Function: int _xtest () @@ -37924,7 +38128,7 @@ and suitable fallback code always needs to be supplied. otherwise 0. -- RTM Function: void _xabort (status) - Abort the current transaction. When no transaction is active this + Abort the current transaction. When no transaction is active this is a no-op. status must be a 8bit constant, that is included in the status code returned by `_xbegin' @@ -38687,9 +38891,12 @@ processors: float __builtin_rsqrtf (float); double __builtin_recipdiv (double, double); double __builtin_rsqrt (double); - long __builtin_bpermd (long, long); uint64_t __builtin_ppc_get_timebase (); unsigned long __builtin_ppc_mftb (); + double __builtin_unpack_longdouble (long double, int); + double __builtin_longdouble_dw0 (long double); + double __builtin_longdouble_dw1 (long double); + long double __builtin_pack_longdouble (double, double); The `vec_rsqrt', `__builtin_rsqrt', and `__builtin_rsqrtf' functions generate multiple instructions to implement the reciprocal sqrt @@ -38707,8 +38914,52 @@ The `__builtin_ppc_mftb' function always generates one instruction and returns the Time Base Register value as an unsigned long, throwing away the most significant word on 32-bit environments. - -File: gcc.info, Node: PowerPC AltiVec/VSX Built-in Functions, Next: RX Built-in Functions, Prev: PowerPC Built-in Functions, Up: Target Builtins + The following built-in functions are available for the PowerPC family +of processors, starting with ISA 2.06 or later (`-mcpu=power7' or +`-mpopcntd'): + long __builtin_bpermd (long, long); + int __builtin_divwe (int, int); + int __builtin_divweo (int, int); + unsigned int __builtin_divweu (unsigned int, unsigned int); + unsigned int __builtin_divweuo (unsigned int, unsigned int); + long __builtin_divde (long, long); + long __builtin_divdeo (long, long); + unsigned long __builtin_divdeu (unsigned long, unsigned long); + unsigned long __builtin_divdeuo (unsigned long, unsigned long); + unsigned int cdtbcd (unsigned int); + unsigned int cbcdtd (unsigned int); + unsigned int addg6s (unsigned int, unsigned int); + + The `__builtin_divde', `__builtin_divdeo', `__builitin_divdeu', +`__builtin_divdeou' functions require a 64-bit environment support ISA +2.06 or later. + + The following built-in functions are available for the PowerPC family +of processors when hardware decimal floating point (`-mhard-dfp') is +available: + _Decimal64 __builtin_dxex (_Decimal64); + _Decimal128 __builtin_dxexq (_Decimal128); + _Decimal64 __builtin_ddedpd (int, _Decimal64); + _Decimal128 __builtin_ddedpdq (int, _Decimal128); + _Decimal64 __builtin_denbcd (int, _Decimal64); + _Decimal128 __builtin_denbcdq (int, _Decimal128); + _Decimal64 __builtin_diex (_Decimal64, _Decimal64); + _Decimal128 _builtin_diexq (_Decimal128, _Decimal128); + _Decimal64 __builtin_dscli (_Decimal64, int); + _Decimal128 __builitn_dscliq (_Decimal128, int); + _Decimal64 __builtin_dscri (_Decimal64, int); + _Decimal128 __builitn_dscriq (_Decimal128, int); + unsigned long long __builtin_unpack_dec128 (_Decimal128, int); + _Decimal128 __builtin_pack_dec128 (unsigned long long, unsigned long long); + + The following built-in functions are available for the PowerPC family +of processors when the Vector Scalar (vsx) instruction set is available: + unsigned long long __builtin_unpack_vector_int128 (vector __int128_t, int); + vector __int128_t __builtin_pack_vector_int128 (unsigned long long, + unsigned long long); + + +File: gcc.info, Node: PowerPC AltiVec/VSX Built-in Functions, Next: PowerPC Hardware Transactional Memory Built-in Functions, Prev: PowerPC Built-in Functions, Up: Target Builtins 6.56.15 PowerPC AltiVec Built-in Functions ------------------------------------------ @@ -40743,16 +40994,614 @@ additional functions are available: void vec_vsx_st (vector bool char, int, unsigned char *); void vec_vsx_st (vector bool char, int, signed char *); + vector double vec_xxpermdi (vector double, vector double, int); + vector float vec_xxpermdi (vector float, vector float, int); + vector long long vec_xxpermdi (vector long long, vector long long, int); + vector unsigned long long vec_xxpermdi (vector unsigned long long, + vector unsigned long long, int); + vector int vec_xxpermdi (vector int, vector int, int); + vector unsigned int vec_xxpermdi (vector unsigned int, + vector unsigned int, int); + vector short vec_xxpermdi (vector short, vector short, int); + vector unsigned short vec_xxpermdi (vector unsigned short, + vector unsigned short, int); + vector signed char vec_xxpermdi (vector signed char, vector signed char, int); + vector unsigned char vec_xxpermdi (vector unsigned char, + vector unsigned char, int); + + vector double vec_xxsldi (vector double, vector double, int); + vector float vec_xxsldi (vector float, vector float, int); + vector long long vec_xxsldi (vector long long, vector long long, int); + vector unsigned long long vec_xxsldi (vector unsigned long long, + vector unsigned long long, int); + vector int vec_xxsldi (vector int, vector int, int); + vector unsigned int vec_xxsldi (vector unsigned int, vector unsigned int, int); + vector short vec_xxsldi (vector short, vector short, int); + vector unsigned short vec_xxsldi (vector unsigned short, + vector unsigned short, int); + vector signed char vec_xxsldi (vector signed char, vector signed char, int); + vector unsigned char vec_xxsldi (vector unsigned char, + vector unsigned char, int); + Note that the `vec_ld' and `vec_st' built-in functions always generate the AltiVec `LVX' and `STVX' instructions even if the VSX instruction set is available. The `vec_vsx_ld' and `vec_vsx_st' built-in functions always generate the VSX `LXVD2X', `LXVW4X', `STXVD2X', and `STXVW4X' instructions. + If the ISA 2.07 additions to the vector/scalar (power8-vector) +instruction set is available, the following additional functions are +available for both 32-bit and 64-bit targets. For 64-bit targets, you +can use VECTOR LONG instead of VECTOR LONG LONG, VECTOR BOOL LONG +instead of VECTOR BOOL LONG LONG, and VECTOR UNSIGNED LONG instead of +VECTOR UNSIGNED LONG LONG. + + vector long long vec_abs (vector long long); + + vector long long vec_add (vector long long, vector long long); + vector unsigned long long vec_add (vector unsigned long long, + vector unsigned long long); + + int vec_all_eq (vector long long, vector long long); + int vec_all_ge (vector long long, vector long long); + int vec_all_gt (vector long long, vector long long); + int vec_all_le (vector long long, vector long long); + int vec_all_lt (vector long long, vector long long); + int vec_all_ne (vector long long, vector long long); + int vec_any_eq (vector long long, vector long long); + int vec_any_ge (vector long long, vector long long); + int vec_any_gt (vector long long, vector long long); + int vec_any_le (vector long long, vector long long); + int vec_any_lt (vector long long, vector long long); + int vec_any_ne (vector long long, vector long long); + + vector long long vec_eqv (vector long long, vector long long); + vector long long vec_eqv (vector bool long long, vector long long); + vector long long vec_eqv (vector long long, vector bool long long); + vector unsigned long long vec_eqv (vector unsigned long long, + vector unsigned long long); + vector unsigned long long vec_eqv (vector bool long long, + vector unsigned long long); + vector unsigned long long vec_eqv (vector unsigned long long, + vector bool long long); + vector int vec_eqv (vector int, vector int); + vector int vec_eqv (vector bool int, vector int); + vector int vec_eqv (vector int, vector bool int); + vector unsigned int vec_eqv (vector unsigned int, vector unsigned int); + vector unsigned int vec_eqv (vector bool unsigned int, + vector unsigned int); + vector unsigned int vec_eqv (vector unsigned int, + vector bool unsigned int); + vector short vec_eqv (vector short, vector short); + vector short vec_eqv (vector bool short, vector short); + vector short vec_eqv (vector short, vector bool short); + vector unsigned short vec_eqv (vector unsigned short, vector unsigned short); + vector unsigned short vec_eqv (vector bool unsigned short, + vector unsigned short); + vector unsigned short vec_eqv (vector unsigned short, + vector bool unsigned short); + vector signed char vec_eqv (vector signed char, vector signed char); + vector signed char vec_eqv (vector bool signed char, vector signed char); + vector signed char vec_eqv (vector signed char, vector bool signed char); + vector unsigned char vec_eqv (vector unsigned char, vector unsigned char); + vector unsigned char vec_eqv (vector bool unsigned char, vector unsigned char); + vector unsigned char vec_eqv (vector unsigned char, vector bool unsigned char); + + vector long long vec_max (vector long long, vector long long); + vector unsigned long long vec_max (vector unsigned long long, + vector unsigned long long); + + vector long long vec_min (vector long long, vector long long); + vector unsigned long long vec_min (vector unsigned long long, + vector unsigned long long); + + vector long long vec_nand (vector long long, vector long long); + vector long long vec_nand (vector bool long long, vector long long); + vector long long vec_nand (vector long long, vector bool long long); + vector unsigned long long vec_nand (vector unsigned long long, + vector unsigned long long); + vector unsigned long long vec_nand (vector bool long long, + vector unsigned long long); + vector unsigned long long vec_nand (vector unsigned long long, + vector bool long long); + vector int vec_nand (vector int, vector int); + vector int vec_nand (vector bool int, vector int); + vector int vec_nand (vector int, vector bool int); + vector unsigned int vec_nand (vector unsigned int, vector unsigned int); + vector unsigned int vec_nand (vector bool unsigned int, + vector unsigned int); + vector unsigned int vec_nand (vector unsigned int, + vector bool unsigned int); + vector short vec_nand (vector short, vector short); + vector short vec_nand (vector bool short, vector short); + vector short vec_nand (vector short, vector bool short); + vector unsigned short vec_nand (vector unsigned short, vector unsigned short); + vector unsigned short vec_nand (vector bool unsigned short, + vector unsigned short); + vector unsigned short vec_nand (vector unsigned short, + vector bool unsigned short); + vector signed char vec_nand (vector signed char, vector signed char); + vector signed char vec_nand (vector bool signed char, vector signed char); + vector signed char vec_nand (vector signed char, vector bool signed char); + vector unsigned char vec_nand (vector unsigned char, vector unsigned char); + vector unsigned char vec_nand (vector bool unsigned char, vector unsigned char); + vector unsigned char vec_nand (vector unsigned char, vector bool unsigned char); + + vector long long vec_orc (vector long long, vector long long); + vector long long vec_orc (vector bool long long, vector long long); + vector long long vec_orc (vector long long, vector bool long long); + vector unsigned long long vec_orc (vector unsigned long long, + vector unsigned long long); + vector unsigned long long vec_orc (vector bool long long, + vector unsigned long long); + vector unsigned long long vec_orc (vector unsigned long long, + vector bool long long); + vector int vec_orc (vector int, vector int); + vector int vec_orc (vector bool int, vector int); + vector int vec_orc (vector int, vector bool int); + vector unsigned int vec_orc (vector unsigned int, vector unsigned int); + vector unsigned int vec_orc (vector bool unsigned int, + vector unsigned int); + vector unsigned int vec_orc (vector unsigned int, + vector bool unsigned int); + vector short vec_orc (vector short, vector short); + vector short vec_orc (vector bool short, vector short); + vector short vec_orc (vector short, vector bool short); + vector unsigned short vec_orc (vector unsigned short, vector unsigned short); + vector unsigned short vec_orc (vector bool unsigned short, + vector unsigned short); + vector unsigned short vec_orc (vector unsigned short, + vector bool unsigned short); + vector signed char vec_orc (vector signed char, vector signed char); + vector signed char vec_orc (vector bool signed char, vector signed char); + vector signed char vec_orc (vector signed char, vector bool signed char); + vector unsigned char vec_orc (vector unsigned char, vector unsigned char); + vector unsigned char vec_orc (vector bool unsigned char, vector unsigned char); + vector unsigned char vec_orc (vector unsigned char, vector bool unsigned char); + + vector int vec_pack (vector long long, vector long long); + vector unsigned int vec_pack (vector unsigned long long, + vector unsigned long long); + vector bool int vec_pack (vector bool long long, vector bool long long); + + vector int vec_packs (vector long long, vector long long); + vector unsigned int vec_packs (vector unsigned long long, + vector unsigned long long); + + vector unsigned int vec_packsu (vector long long, vector long long); + + vector long long vec_rl (vector long long, + vector unsigned long long); + vector long long vec_rl (vector unsigned long long, + vector unsigned long long); + + vector long long vec_sl (vector long long, vector unsigned long long); + vector long long vec_sl (vector unsigned long long, + vector unsigned long long); + + vector long long vec_sr (vector long long, vector unsigned long long); + vector unsigned long long char vec_sr (vector unsigned long long, + vector unsigned long long); + + vector long long vec_sra (vector long long, vector unsigned long long); + vector unsigned long long vec_sra (vector unsigned long long, + vector unsigned long long); + + vector long long vec_sub (vector long long, vector long long); + vector unsigned long long vec_sub (vector unsigned long long, + vector unsigned long long); + + vector long long vec_unpackh (vector int); + vector unsigned long long vec_unpackh (vector unsigned int); + + vector long long vec_unpackl (vector int); + vector unsigned long long vec_unpackl (vector unsigned int); + + vector long long vec_vaddudm (vector long long, vector long long); + vector long long vec_vaddudm (vector bool long long, vector long long); + vector long long vec_vaddudm (vector long long, vector bool long long); + vector unsigned long long vec_vaddudm (vector unsigned long long, + vector unsigned long long); + vector unsigned long long vec_vaddudm (vector bool unsigned long long, + vector unsigned long long); + vector unsigned long long vec_vaddudm (vector unsigned long long, + vector bool unsigned long long); + + vector long long vec_vbpermq (vector signed char, vector signed char); + vector long long vec_vbpermq (vector unsigned char, vector unsigned char); + + vector long long vec_vclz (vector long long); + vector unsigned long long vec_vclz (vector unsigned long long); + vector int vec_vclz (vector int); + vector unsigned int vec_vclz (vector int); + vector short vec_vclz (vector short); + vector unsigned short vec_vclz (vector unsigned short); + vector signed char vec_vclz (vector signed char); + vector unsigned char vec_vclz (vector unsigned char); + + vector signed char vec_vclzb (vector signed char); + vector unsigned char vec_vclzb (vector unsigned char); + + vector long long vec_vclzd (vector long long); + vector unsigned long long vec_vclzd (vector unsigned long long); + + vector short vec_vclzh (vector short); + vector unsigned short vec_vclzh (vector unsigned short); + + vector int vec_vclzw (vector int); + vector unsigned int vec_vclzw (vector int); + + vector signed char vec_vgbbd (vector signed char); + vector unsigned char vec_vgbbd (vector unsigned char); + + vector long long vec_vmaxsd (vector long long, vector long long); + + vector unsigned long long vec_vmaxud (vector unsigned long long, + unsigned vector long long); + + vector long long vec_vminsd (vector long long, vector long long); + + vector unsigned long long vec_vminud (vector long long, + vector long long); + + vector int vec_vpksdss (vector long long, vector long long); + vector unsigned int vec_vpksdss (vector long long, vector long long); + + vector unsigned int vec_vpkudus (vector unsigned long long, + vector unsigned long long); + + vector int vec_vpkudum (vector long long, vector long long); + vector unsigned int vec_vpkudum (vector unsigned long long, + vector unsigned long long); + vector bool int vec_vpkudum (vector bool long long, vector bool long long); + + vector long long vec_vpopcnt (vector long long); + vector unsigned long long vec_vpopcnt (vector unsigned long long); + vector int vec_vpopcnt (vector int); + vector unsigned int vec_vpopcnt (vector int); + vector short vec_vpopcnt (vector short); + vector unsigned short vec_vpopcnt (vector unsigned short); + vector signed char vec_vpopcnt (vector signed char); + vector unsigned char vec_vpopcnt (vector unsigned char); + + vector signed char vec_vpopcntb (vector signed char); + vector unsigned char vec_vpopcntb (vector unsigned char); + + vector long long vec_vpopcntd (vector long long); + vector unsigned long long vec_vpopcntd (vector unsigned long long); + + vector short vec_vpopcnth (vector short); + vector unsigned short vec_vpopcnth (vector unsigned short); + + vector int vec_vpopcntw (vector int); + vector unsigned int vec_vpopcntw (vector int); + + vector long long vec_vrld (vector long long, vector unsigned long long); + vector unsigned long long vec_vrld (vector unsigned long long, + vector unsigned long long); + + vector long long vec_vsld (vector long long, vector unsigned long long); + vector long long vec_vsld (vector unsigned long long, + vector unsigned long long); + + vector long long vec_vsrad (vector long long, vector unsigned long long); + vector unsigned long long vec_vsrad (vector unsigned long long, + vector unsigned long long); + + vector long long vec_vsrd (vector long long, vector unsigned long long); + vector unsigned long long char vec_vsrd (vector unsigned long long, + vector unsigned long long); + + vector long long vec_vsubudm (vector long long, vector long long); + vector long long vec_vsubudm (vector bool long long, vector long long); + vector long long vec_vsubudm (vector long long, vector bool long long); + vector unsigned long long vec_vsubudm (vector unsigned long long, + vector unsigned long long); + vector unsigned long long vec_vsubudm (vector bool long long, + vector unsigned long long); + vector unsigned long long vec_vsubudm (vector unsigned long long, + vector bool long long); + + vector long long vec_vupkhsw (vector int); + vector unsigned long long vec_vupkhsw (vector unsigned int); + + vector long long vec_vupklsw (vector int); + vector unsigned long long vec_vupklsw (vector int); + + If the ISA 2.07 additions to the vector/scalar (power8-vector) +instruction set is available, the following additional functions are +available for 64-bit targets. New vector types (VECTOR __INT128_T and +VECTOR __UINT128_T) are available to hold the __INT128_T and +__UINT128_T types to use these builtins. + + The normal vector extract, and set operations work on VECTOR +__INT128_T and VECTOR __UINT128_T types, but the index value must be 0. + + vector __int128_t vec_vaddcuq (vector __int128_t, vector __int128_t); + vector __uint128_t vec_vaddcuq (vector __uint128_t, vector __uint128_t); + + vector __int128_t vec_vadduqm (vector __int128_t, vector __int128_t); + vector __uint128_t vec_vadduqm (vector __uint128_t, vector __uint128_t); + + vector __int128_t vec_vaddecuq (vector __int128_t, vector __int128_t, + vector __int128_t); + vector __uint128_t vec_vaddecuq (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + + vector __int128_t vec_vaddeuqm (vector __int128_t, vector __int128_t, + vector __int128_t); + vector __uint128_t vec_vaddeuqm (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + + vector __int128_t vec_vsubecuq (vector __int128_t, vector __int128_t, + vector __int128_t); + vector __uint128_t vec_vsubecuq (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + + vector __int128_t vec_vsubeuqm (vector __int128_t, vector __int128_t, + vector __int128_t); + vector __uint128_t vec_vsubeuqm (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + + vector __int128_t vec_vsubcuq (vector __int128_t, vector __int128_t); + vector __uint128_t vec_vsubcuq (vector __uint128_t, vector __uint128_t); + + __int128_t vec_vsubuqm (__int128_t, __int128_t); + __uint128_t vec_vsubuqm (__uint128_t, __uint128_t); + + vector __int128_t __builtin_bcdadd (vector __int128_t, vector__int128_t); + int __builtin_bcdadd_lt (vector __int128_t, vector__int128_t); + int __builtin_bcdadd_eq (vector __int128_t, vector__int128_t); + int __builtin_bcdadd_gt (vector __int128_t, vector__int128_t); + int __builtin_bcdadd_ov (vector __int128_t, vector__int128_t); + vector __int128_t bcdsub (vector __int128_t, vector__int128_t); + int __builtin_bcdsub_lt (vector __int128_t, vector__int128_t); + int __builtin_bcdsub_eq (vector __int128_t, vector__int128_t); + int __builtin_bcdsub_gt (vector __int128_t, vector__int128_t); + int __builtin_bcdsub_ov (vector __int128_t, vector__int128_t); + + If the cryptographic instructions are enabled (`-mcrypto' or +`-mcpu=power8'), the following builtins are enabled. + + vector unsigned long long __builtin_crypto_vsbox (vector unsigned long long); + + vector unsigned long long __builtin_crypto_vcipher (vector unsigned long long, + vector unsigned long long); + + vector unsigned long long __builtin_crypto_vcipherlast + (vector unsigned long long, + vector unsigned long long); + + vector unsigned long long __builtin_crypto_vncipher (vector unsigned long long, + vector unsigned long long); + + vector unsigned long long __builtin_crypto_vncipherlast + (vector unsigned long long, + vector unsigned long long); + + vector unsigned char __builtin_crypto_vpermxor (vector unsigned char, + vector unsigned char, + vector unsigned char); + + vector unsigned short __builtin_crypto_vpermxor (vector unsigned short, + vector unsigned short, + vector unsigned short); + + vector unsigned int __builtin_crypto_vpermxor (vector unsigned int, + vector unsigned int, + vector unsigned int); + + vector unsigned long long __builtin_crypto_vpermxor (vector unsigned long long, + vector unsigned long long, + vector unsigned long long); + + vector unsigned char __builtin_crypto_vpmsumb (vector unsigned char, + vector unsigned char); + + vector unsigned short __builtin_crypto_vpmsumb (vector unsigned short, + vector unsigned short); + + vector unsigned int __builtin_crypto_vpmsumb (vector unsigned int, + vector unsigned int); + + vector unsigned long long __builtin_crypto_vpmsumb (vector unsigned long long, + vector unsigned long long); + + vector unsigned long long __builtin_crypto_vshasigmad + (vector unsigned long long, int, int); + + vector unsigned int __builtin_crypto_vshasigmaw (vector unsigned int, + int, int); + + The second argument to the __BUILTIN_CRYPTO_VSHASIGMAD and +__BUILTIN_CRYPTO_VSHASIGMAW builtin functions must be a constant +integer that is 0 or 1. The third argument to these builtin functions +must be a constant integer in the range of 0 to 15. + + +File: gcc.info, Node: PowerPC Hardware Transactional Memory Built-in Functions, Next: RX Built-in Functions, Prev: PowerPC AltiVec/VSX Built-in Functions, Up: Target Builtins + +6.56.16 PowerPC Hardware Transactional Memory Built-in Functions +---------------------------------------------------------------- + +GCC provides two interfaces for accessing the Hardware Transactional +Memory (HTM) instructions available on some of the PowerPC family of +prcoessors (eg, POWER8). The two interfaces come in a low level +interface, consisting of built-in functions specific to PowerPC and a +higher level interface consisting of inline functions that are common +between PowerPC and S/390. + +6.56.16.1 PowerPC HTM Low Level Built-in Functions +.................................................. + +The following low level built-in functions are available with `-mhtm' +or `-mcpu=CPU' where CPU is `power8' or later. They all generate the +machine instruction that is part of the name. + + The HTM built-ins return true or false depending on their success and +their arguments match exactly the type and order of the associated +hardware instruction's operands. Refer to the ISA manual for a +description of each instruction's operands. + + unsigned int __builtin_tbegin (unsigned int) + unsigned int __builtin_tend (unsigned int) + + unsigned int __builtin_tabort (unsigned int) + unsigned int __builtin_tabortdc (unsigned int, unsigned int, unsigned int) + unsigned int __builtin_tabortdci (unsigned int, unsigned int, int) + unsigned int __builtin_tabortwc (unsigned int, unsigned int, unsigned int) + unsigned int __builtin_tabortwci (unsigned int, unsigned int, int) + + unsigned int __builtin_tcheck (unsigned int) + unsigned int __builtin_treclaim (unsigned int) + unsigned int __builtin_trechkpt (void) + unsigned int __builtin_tsr (unsigned int) + + In addition to the above HTM built-ins, we have added built-ins for +some common extended mnemonics of the HTM instructions: + + unsigned int __builtin_tendall (void) + unsigned int __builtin_tresume (void) + unsigned int __builtin_tsuspend (void) + + The following set of built-in functions are available to gain access +to the HTM specific special purpose registers. + + unsigned long __builtin_get_texasr (void) + unsigned long __builtin_get_texasru (void) + unsigned long __builtin_get_tfhar (void) + unsigned long __builtin_get_tfiar (void) + + void __builtin_set_texasr (unsigned long); + void __builtin_set_texasru (unsigned long); + void __builtin_set_tfhar (unsigned long); + void __builtin_set_tfiar (unsigned long); + + Example usage of these low level built-in functions may look like: + + #include <htmintrin.h> + + int num_retries = 10; + + while (1) + { + if (__builtin_tbegin (0)) + { + /* Transaction State Initiated. */ + if (is_locked (lock)) + __builtin_tabort (0); + ... transaction code... + __builtin_tend (0); + break; + } + else + { + /* Transaction State Failed. Use locks if the transaction + failure is "persistent" or we've tried too many times. */ + if (num_retries-- <= 0 + || _TEXASRU_FAILURE_PERSISTENT (__builtin_get_texasru ())) + { + acquire_lock (lock); + ... non transactional fallback path... + release_lock (lock); + break; + } + } + } + + One final built-in function has been added that returns the value of +the 2-bit Transaction State field of the Machine Status Register (MSR) +as stored in `CR0'. + + unsigned long __builtin_ttest (void) + + This built-in can be used to determine the current transaction state +using the following code example: + + #include <htmintrin.h> + + unsigned char tx_state = _HTM_STATE (__builtin_ttest ()); + + if (tx_state == _HTM_TRANSACTIONAL) + { + /* Code to use in transactional state. */ + } + else if (tx_state == _HTM_NONTRANSACTIONAL) + { + /* Code to use in non-transactional state. */ + } + else if (tx_state == _HTM_SUSPENDED) + { + /* Code to use in transaction suspended state. */ + } + +6.56.16.2 PowerPC HTM High Level Inline Functions +................................................. + +The following high level HTM interface is made available by including +`<htmxlintrin.h>' and using `-mhtm' or `-mcpu=CPU' where CPU is +`power8' or later. This interface is common between PowerPC and S/390, +allowing users to write one HTM source implementation that can be +compiled and executed on either system. + + long __TM_simple_begin (void) + long __TM_begin (void* const TM_buff) + long __TM_end (void) + void __TM_abort (void) + void __TM_named_abort (unsigned char const code) + void __TM_resume (void) + void __TM_suspend (void) + + long __TM_is_user_abort (void* const TM_buff) + long __TM_is_named_user_abort (void* const TM_buff, unsigned char *code) + long __TM_is_illegal (void* const TM_buff) + long __TM_is_footprint_exceeded (void* const TM_buff) + long __TM_nesting_depth (void* const TM_buff) + long __TM_is_nested_too_deep(void* const TM_buff) + long __TM_is_conflict(void* const TM_buff) + long __TM_is_failure_persistent(void* const TM_buff) + long __TM_failure_address(void* const TM_buff) + long long __TM_failure_code(void* const TM_buff) + + Using these common set of HTM inline functions, we can create a more +portable version of the HTM example in the previous section that will +work on either PowerPC or S/390: + + #include <htmxlintrin.h> + + int num_retries = 10; + TM_buff_type TM_buff; + + while (1) + { + if (__TM_begin (TM_buff)) + { + /* Transaction State Initiated. */ + if (is_locked (lock)) + __TM_abort (); + ... transaction code... + __TM_end (); + break; + } + else + { + /* Transaction State Failed. Use locks if the transaction + failure is "persistent" or we've tried too many times. */ + if (num_retries-- <= 0 + || __TM_is_failure_persistent (TM_buff)) + { + acquire_lock (lock); + ... non transactional fallback path... + release_lock (lock); + break; + } + } + } + -File: gcc.info, Node: RX Built-in Functions, Next: SH Built-in Functions, Prev: PowerPC AltiVec/VSX Built-in Functions, Up: Target Builtins +File: gcc.info, Node: RX Built-in Functions, Next: S/390 System z Built-in Functions, Prev: PowerPC Hardware Transactional Memory Built-in Functions, Up: Target Builtins -6.56.16 RX Built-in Functions +6.56.17 RX Built-in Functions ----------------------------- GCC supports some of the RX instructions which cannot be expressed in @@ -40848,9 +41697,117 @@ following functions are supported: Generates the `wait' machine instruction. -File: gcc.info, Node: SH Built-in Functions, Next: SPARC VIS Built-in Functions, Prev: RX Built-in Functions, Up: Target Builtins +File: gcc.info, Node: S/390 System z Built-in Functions, Next: SH Built-in Functions, Prev: RX Built-in Functions, Up: Target Builtins + +6.56.18 S/390 System z Built-in Functions +----------------------------------------- + + -- Built-in Function: int __builtin_tbegin (void*) + Generates the `tbegin' machine instruction starting a + non-constraint hardware transaction. If the parameter is non-NULL + the memory area is used to store the transaction diagnostic buffer + and will be passed as first operand to `tbegin'. This buffer can + be defined using the `struct __htm_tdb' C struct defined in + `htmintrin.h' and must reside on a double-word boundary. The + second tbegin operand is set to `0xff0c'. This enables + save/restore of all GPRs and disables aborts for FPR and AR + manipulations inside the transaction body. The condition code set + by the tbegin instruction is returned as integer value. The tbegin + instruction by definition overwrites the content of all FPRs. The + compiler will generate code which saves and restores the FPRs. For + soft-float code it is recommended to used the `*_nofloat' variant. + In order to prevent a TDB from being written it is required to + pass an constant zero value as parameter. Passing the zero value + through a variable is not sufficient. Although modifications of + access registers inside the transaction will not trigger an + transaction abort it is not supported to actually modify them. + Access registers do not get saved when entering a transaction. + They will have undefined state when reaching the abort code. + + Macros for the possible return codes of tbegin are defined in the +`htmintrin.h' header file: + +`_HTM_TBEGIN_STARTED' + `tbegin' has been executed as part of normal processing. The + transaction body is supposed to be executed. + +`_HTM_TBEGIN_INDETERMINATE' + The transaction was aborted due to an indeterminate condition which + might be persistent. + +`_HTM_TBEGIN_TRANSIENT' + The transaction aborted due to a transient failure. The + transaction should be re-executed in that case. + +`_HTM_TBEGIN_PERSISTENT' + The transaction aborted due to a persistent failure. Re-execution + under same circumstances will not be productive. + + -- Macro: _HTM_FIRST_USER_ABORT_CODE + The `_HTM_FIRST_USER_ABORT_CODE' defined in `htmintrin.h' + specifies the first abort code which can be used for + `__builtin_tabort'. Values below this threshold are reserved for + machine use. + + -- Data type: struct __htm_tdb + The `struct __htm_tdb' defined in `htmintrin.h' describes the + structure of the transaction diagnostic block as specified in the + Principles of Operation manual chapter 5-91. + + -- Built-in Function: int __builtin_tbegin_nofloat (void*) + Same as `__builtin_tbegin' but without FPR saves and restores. + Using this variant in code making use of FPRs will leave the FPRs + in undefined state when entering the transaction abort handler + code. -6.56.17 SH Built-in Functions + -- Built-in Function: int __builtin_tbegin_retry (void*, int) + In addition to `__builtin_tbegin' a loop for transient failures is + generated. If tbegin returns a condition code of 2 the transaction + will be retried as often as specified in the second argument. The + perform processor assist instruction is used to tell the CPU about + the number of fails so far. + + -- Built-in Function: int __builtin_tbegin_retry_nofloat (void*, int) + Same as `__builtin_tbegin_retry' but without FPR saves and + restores. Using this variant in code making use of FPRs will leave + the FPRs in undefined state when entering the transaction abort + handler code. + + -- Built-in Function: void __builtin_tbeginc (void) + Generates the `tbeginc' machine instruction starting a constraint + hardware transaction. The second operand is set to `0xff08'. + + -- Built-in Function: int __builtin_tend (void) + Generates the `tend' machine instruction finishing a transaction + and making the changes visible to other threads. The condition + code generated by tend is returned as integer value. + + -- Built-in Function: void __builtin_tabort (int) + Generates the `tabort' machine instruction with the specified + abort code. Abort codes from 0 through 255 are reserved and will + result in an error message. + + -- Built-in Function: void __builtin_tx_assist (int) + Generates the `ppa rX,rY,1' machine instruction. Where the + integer parameter is loaded into rX and a value of zero is loaded + into rY. The integer parameter specifies the number of times the + transaction repeatedly aborted. + + -- Built-in Function: int __builtin_tx_nesting_depth (void) + Generates the `etnd' machine instruction. The current nesting + depth is returned as integer value. For a nesting depth of 0 the + code is not executed as part of an transaction. + + -- Built-in Function: void __builtin_non_tx_store (uint64_t *, + uint64_t) + Generates the `ntstg' machine instruction. The second argument is + written to the first arguments location. The store operation will + not be rolled-back in case of an transaction abort. + + +File: gcc.info, Node: SH Built-in Functions, Next: SPARC VIS Built-in Functions, Prev: S/390 System z Built-in Functions, Up: Target Builtins + +6.56.19 SH Built-in Functions ----------------------------- The following built-in functions are supported on the SH1, SH2, SH3 and @@ -40885,7 +41842,7 @@ SH4 families of processors: File: gcc.info, Node: SPARC VIS Built-in Functions, Next: SPU Built-in Functions, Prev: SH Built-in Functions, Up: Target Builtins -6.56.18 SPARC VIS Built-in Functions +6.56.20 SPARC VIS Built-in Functions ------------------------------------ GCC supports SIMD operations on the SPARC using both the generic vector @@ -41026,7 +41983,7 @@ functions also become available: File: gcc.info, Node: SPU Built-in Functions, Next: TI C6X Built-in Functions, Prev: SPARC VIS Built-in Functions, Up: Target Builtins -6.56.19 SPU Built-in Functions +6.56.21 SPU Built-in Functions ------------------------------ GCC provides extensions for the SPU processor as described in the @@ -41065,14 +42022,14 @@ differs in several ways. _Note:_ Only the interface described in the aforementioned -specification is supported. Internally, GCC uses built-in functions to +specification is supported. Internally, GCC uses built-in functions to implement the required functionality, but these are not supported and are subject to change without notice. File: gcc.info, Node: TI C6X Built-in Functions, Next: TILE-Gx Built-in Functions, Prev: SPU Built-in Functions, Up: Target Builtins -6.56.20 TI C6X Built-in Functions +6.56.22 TI C6X Built-in Functions --------------------------------- GCC provides intrinsics to access certain instructions of the TI C6X @@ -41111,7 +42068,7 @@ C6X instructions. File: gcc.info, Node: TILE-Gx Built-in Functions, Next: TILEPro Built-in Functions, Prev: TI C6X Built-in Functions, Up: Target Builtins -6.56.21 TILE-Gx Built-in Functions +6.56.23 TILE-Gx Built-in Functions ---------------------------------- GCC provides intrinsics to access every instruction of the TILE-Gx @@ -41143,7 +42100,7 @@ after it. File: gcc.info, Node: TILEPro Built-in Functions, Prev: TILE-Gx Built-in Functions, Up: Target Builtins -6.56.22 TILEPro Built-in Functions +6.56.24 TILEPro Built-in Functions ---------------------------------- GCC provides intrinsics to access every instruction of the TILEPro @@ -41435,7 +42392,7 @@ File: gcc.info, Node: Symbol-Renaming Pragmas, Next: Structure-Packing Pragmas For compatibility with the Solaris system headers, GCC supports two `#pragma' directives that change the name used in assembly for a given -declaration. To get this effect on all platforms supported by GCC, use +declaration. To get this effect on all platforms supported by GCC, use the asm labels extension (*note Asm Labels::). `redefine_extname OLDNAME NEWNAME' @@ -41471,7 +42428,7 @@ File: gcc.info, Node: Structure-Packing Pragmas, Next: Weak Pragmas, Prev: Sy For compatibility with Microsoft Windows compilers, GCC supports a set of `#pragma' directives that change the maximum alignment of members of structures (other than zero-width bit-fields), unions, and classes -subsequently defined. The N value below always is required to be a +subsequently defined. The N value below always is required to be a small power of two and specifies the new alignment in bytes. 1. `#pragma pack(N)' simply sets the new alignment. @@ -41628,7 +42585,7 @@ pop_macro("MACRO_NAME")'. `#pragma pop_macro("MACRO_NAME")' This pragma sets the value of the macro named as MACRO_NAME to the - value on top of the stack for this macro. If the stack for + value on top of the stack for this macro. If the stack for MACRO_NAME is empty, the value of the macro remains unchanged. For example: @@ -42286,9 +43243,9 @@ If all calls to the function can be inlined, you can avoid emitting the function by compiling with `-fno-implement-inlines'. If any calls are not inlined, you will get linker errors. - ---------- Footnotes ---------- + ---------- Footnotes ---------- - (1) A file's "basename" is the name stripped of all leading path + (1) A file's "basename" is the name stripped of all leading path information and of trailing suffixes, such as `.h' or `.C' or `.cc'. @@ -42561,10 +43518,10 @@ the execution platform. Here is an example. return 0; } - In the above example, four versions of function foo are created. The + In the above example, four versions of function foo are created. The first version of foo with the target attribute "default" is the default version. This version gets executed when no other target specific -version qualifies for execution on a particular platform. A new version +version qualifies for execution on a particular platform. A new version of foo is created by using the same function signature but with a different target string. Function foo is called or a pointer to it is taken just like a regular function. GCC takes care of doing the @@ -42850,7 +43807,7 @@ expressions, e.g. ` enum E { e = int(2.2 * 3.7) } ' This extension is deprecated and will be removed from a future version. G++ allows static data members of const floating-point type to be -declared with an initializer in a class definition. The standard only +declared with an initializer in a class definition. The standard only allows initializers for static members of const integral types and const enumeration types so this extension has been deprecated and will be removed from a future version. @@ -42867,8 +43824,8 @@ used to be acceptable in previous drafts of the standard, such as the ARM [Annotated C++ Reference Manual], are no longer accepted. In order to allow compilation of C++ written to such drafts, G++ contains some backwards compatibilities. _All such backwards compatibility features -are liable to disappear in future versions of G++._ They should be -considered deprecated. *Note Deprecated Features::. +are liable to disappear in future versions of G++._ They should be +considered deprecated. *Note Deprecated Features::. `For scope' If a variable is declared at for scope, it used to remain in scope @@ -43163,7 +44120,7 @@ selectors and methods and about objects and classes. `unsigned long' `L' `long long' `q' `unsigned long `Q' -long' +long' `float' `f' `double' `d' `long double' `D' @@ -43221,12 +44178,12 @@ compiler on an i386 machine: Objective-C type Compiler encoding int a[10]; `[10i]' struct { `{?=i[3f]b128i3b131i2c}' - int i; - float f[3]; - int a:3; - int b:2; - char c; - } + int i; + float f[3]; + int a:3; + int b:2; + char c; + } int a __attribute__ ((vector_size (16)));`![16,16i]' (alignment would depend on the machine) @@ -43329,7 +44286,7 @@ File: gcc.info, Node: Method signatures, Prev: @encode, Up: Type encoding ----------------------- This section documents the encoding of method types, which is rarely -needed to use Objective-C. You should skip it at a first reading; the +needed to use Objective-C. You should skip it at a first reading; the runtime provides functions that will work on methods and can walk through the list of parameters and interpret them for you. These functions are part of the public "API" and are the preferred way to @@ -43592,7 +44549,7 @@ the `finally' clause in Java. needed in the NeXT Objective-C runtime. * As mentioned above, the new exceptions do not support handling - types other than Objective-C objects. Furthermore, when used from + types other than Objective-C objects. Furthermore, when used from Objective-C++, the Objective-C exception model does not interoperate with C++ exceptions at this time. This means you cannot `@throw' an exception from Objective-C and `catch' it in @@ -44629,7 +45586,7 @@ can relocate the data files based on two environment variables: to strip off the hardwired absolute paths. Default value is 0. _Note:_ If GCOV_PREFIX_STRIP is set without GCOV_PREFIX is - undefined, then a relative path is made out of the hardwired + undefined, then a relative path is made out of the hardwired absolute paths. For example, if the object file `/user/build/foo.o' was built with @@ -45340,9 +46297,9 @@ where variables in base classes are used (as in the example above). these examples wrong and accept above code without an error. Those compilers do not implement two-stage name lookup correctly. - ---------- Footnotes ---------- + ---------- Footnotes ---------- - (1) The C++ standard just uses the term "dependent" for names that + (1) The C++ standard just uses the term "dependent" for names that depend on the type or value of template parameters. This shorter term will also be used in the rest of this section. @@ -45624,7 +46581,7 @@ do not make because we think GCC is better without them. programs run any faster. However, the rationale here is that optimization of a nonempty loop - cannot produce an empty one. This held for carefully written C + cannot produce an empty one. This held for carefully written C compiled with less powerful optimizers but is not always the case for carefully written C++ or with more powerful optimizers. Thus GCC will remove operations from loops whenever it can determine @@ -46379,7 +47336,7 @@ TERMS AND CONDITIONS by modifying or propagating a covered work, you indicate your acceptance of this License to do so. - 10. Automatic Licensing of Downstream Recipients. + 10. Automatic Licensing of Downstream Recipients. Each time you convey a covered work, the recipient automatically receives a license from the original licensors, to run, modify and @@ -46407,7 +47364,7 @@ TERMS AND CONDITIONS using, selling, offering for sale, or importing the Program or any portion of it. - 11. Patents. + 11. Patents. A "contributor" is a copyright holder who authorizes use under this License of the Program or a work on which the Program is based. @@ -46480,7 +47437,7 @@ TERMS AND CONDITIONS any implied license or other defenses to infringement that may otherwise be available to you under applicable patent law. - 12. No Surrender of Others' Freedom. + 12. No Surrender of Others' Freedom. If conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this @@ -46494,7 +47451,7 @@ TERMS AND CONDITIONS terms and this License would be to refrain entirely from conveying the Program. - 13. Use with the GNU Affero General Public License. + 13. Use with the GNU Affero General Public License. Notwithstanding any other provision of this License, you have permission to link or combine any covered work with a work licensed @@ -46505,7 +47462,7 @@ TERMS AND CONDITIONS General Public License, section 13, concerning interaction through a network will apply to the combination as such. - 14. Revised Versions of this License. + 14. Revised Versions of this License. The Free Software Foundation may publish revised and/or new versions of the GNU General Public License from time to time. @@ -46532,19 +47489,19 @@ TERMS AND CONDITIONS author or copyright holder as a result of your choosing to follow a later version. - 15. Disclaimer of Warranty. + 15. Disclaimer of Warranty. THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY - APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE + APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. - 16. Limitation of Liability. + 16. Limitation of Liability. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES @@ -46557,7 +47514,7 @@ TERMS AND CONDITIONS PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. - 17. Interpretation of Sections 15 and 16. + 17. Interpretation of Sections 15 and 16. If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, @@ -47030,7 +47987,7 @@ GNU Free Documentation License not permanently reinstated, receipt of a copy of some or all of the same material does not give you any rights to use it. - 10. FUTURE REVISIONS OF THIS LICENSE + 10. FUTURE REVISIONS OF THIS LICENSE The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new @@ -47051,7 +48008,7 @@ GNU Free Documentation License proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Document. - 11. RELICENSING + 11. RELICENSING "Massive Multiauthor Collaboration Site" (or "MMC Site") means any World Wide Web server that publishes copyrightable works and also @@ -47098,7 +48055,7 @@ notices just after the title page: Free Documentation License''. If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts, -replace the "with...Texts." line with this: +replace the "with...Texts." line with this: with the Invariant Sections being LIST THEIR TITLES, with the Front-Cover Texts being LIST, and with the Back-Cover Texts @@ -48058,7 +49015,7 @@ GCC version 4.1: and improvements. * Thomas Fitzsimmons for lots of upgrades to the gtk+ AWT and Cairo - 2D support. Lots of imageio framework additions, lots of AWT and + 2D support. Lots of imageio framework additions, lots of AWT and Free Swing bug fixes. * Jeroen Frijters for `ClassLoader' and nio cleanups, serialization @@ -48093,7 +49050,7 @@ GCC version 4.1: * Ito Kazumitsu for `NetworkInterface' implementation and updates. * Roman Kennke for `BoxLayout', `GrayFilter' and `SplitPane', plus - bug fixes all over. Lots of Free Swing work including styled text. + bug fixes all over. Lots of Free Swing work including styled text. * Simon Kitching for `String' cleanups and optimization suggestions. @@ -48350,7 +49307,7 @@ look up both forms. * -mcpu: RX Options. (line 30) * -mpointer-size=SIZE: VMS Options. (line 20) * 8bit-idiv: i386 and x86-64 Options. - (line 818) + (line 824) * A: Preprocessor Options. (line 597) * all_load: Darwin Options. (line 110) @@ -48364,9 +49321,9 @@ look up both forms. * arch_errors_fatal: Darwin Options. (line 114) * aux-info: C Dialect Options. (line 168) * avx256-split-unaligned-load: i386 and x86-64 Options. - (line 826) + (line 832) * avx256-split-unaligned-store: i386 and x86-64 Options. - (line 826) + (line 832) * B: Directory Options. (line 46) * Bdynamic: VxWorks Options. (line 22) * bind_at_load: Darwin Options. (line 118) @@ -48418,6 +49375,7 @@ look up both forms. * F: Darwin Options. (line 31) * fabi-version: C++ Dialect Options. (line 20) +* fada-spec-parent: Overall Options. (line 369) * faggressive-loop-optimizations: Optimize Options. (line 509) * falign-functions: Optimize Options. (line 1462) * falign-jumps: Optimize Options. (line 1511) @@ -48482,8 +49440,10 @@ look up both forms. * fdollars-in-identifiers: Preprocessor Options. (line 495) * fdse: Optimize Options. (line 543) +* fdump-ada-spec: Overall Options. (line 363) * fdump-class-hierarchy: Debugging Options. (line 805) * fdump-final-insns: Debugging Options. (line 194) +* fdump-go-spec: Overall Options. (line 373) * fdump-ipa: Debugging Options. (line 813) * fdump-noaddr: Debugging Options. (line 778) * fdump-passes: Debugging Options. (line 831) @@ -48646,7 +49606,7 @@ look up both forms. * finput-charset: Preprocessor Options. (line 567) * finstrument-functions <1>: Function Attributes. - (line 946) + (line 954) * finstrument-functions: Code Gen Options. (line 375) * finstrument-functions-exclude-file-list: Code Gen Options. (line 411) * finstrument-functions-exclude-function-list: Code Gen Options. @@ -48902,7 +49862,7 @@ look up both forms. * fsingle-precision-constant: Optimize Options. (line 2052) * fsplit-ivs-in-unroller: Optimize Options. (line 1281) * fsplit-stack <1>: Function Attributes. - (line 951) + (line 959) * fsplit-stack: Code Gen Options. (line 496) * fsplit-wide-types: Optimize Options. (line 437) * fstack-check: Code Gen Options. (line 443) @@ -49004,7 +49964,7 @@ look up both forms. (line 141) * G <1>: System V Options. (line 10) * G <2>: RS/6000 and PowerPC Options. - (line 662) + (line 743) * G <3>: MIPS Options. (line 330) * G: M32R/D Options. (line 57) * g: Debugging Options. (line 10) @@ -49070,13 +50030,13 @@ look up both forms. * l: Link Options. (line 26) * lobjc: Link Options. (line 53) * m: RS/6000 and PowerPC Options. - (line 515) + (line 584) * M: Preprocessor Options. (line 185) * m1: SH Options. (line 9) * m10: PDP-11 Options. (line 29) * m128bit-long-double: i386 and x86-64 Options. - (line 336) + (line 342) * m16-bit: CRIS Options. (line 64) * m1reg-: Adapteva Epiphany Options. (line 132) @@ -49091,11 +50051,11 @@ look up both forms. (line 87) * m32 <1>: TILEPro Options. (line 13) * m32 <2>: TILE-Gx Options. (line 23) -* m32 <3>: SPARC Options. (line 245) +* m32 <3>: SPARC Options. (line 257) * m32 <4>: RS/6000 and PowerPC Options. - (line 207) + (line 276) * m32: i386 and x86-64 Options. - (line 835) + (line 841) * m32-bit: CRIS Options. (line 64) * m32bit-doubles: RX Options. (line 10) * m32r: M32R/D Options. (line 15) @@ -49103,7 +50063,7 @@ look up both forms. * m32rx: M32R/D Options. (line 12) * m340: MCore Options. (line 43) * m3dnow: i386 and x86-64 Options. - (line 565) + (line 571) * m3e: SH Options. (line 37) * m4: SH Options. (line 51) * m4-nofpu: SH Options. (line 40) @@ -49123,13 +50083,13 @@ look up both forms. * m5307: M680x0 Options. (line 164) * m5407: M680x0 Options. (line 168) * m64 <1>: TILE-Gx Options. (line 23) -* m64 <2>: SPARC Options. (line 245) +* m64 <2>: SPARC Options. (line 257) * m64 <3>: S/390 and zSeries Options. (line 87) * m64 <4>: RS/6000 and PowerPC Options. - (line 207) + (line 276) * m64: i386 and x86-64 Options. - (line 835) + (line 841) * m64bit-doubles: RX Options. (line 10) * m68000: M680x0 Options. (line 95) * m68010: M680x0 Options. (line 103) @@ -49143,65 +50103,73 @@ look up both forms. * m8-bit: CRIS Options. (line 64) * m8byte-align: V850 Options. (line 170) * m96bit-long-double: i386 and x86-64 Options. - (line 336) + (line 342) * mabi <1>: RS/6000 and PowerPC Options. - (line 542) + (line 611) * mabi <2>: i386 and x86-64 Options. - (line 715) + (line 721) * mabi: ARM Options. (line 10) * mabi=32: MIPS Options. (line 131) * mabi=64: MIPS Options. (line 131) * mabi=eabi: MIPS Options. (line 131) +* mabi=elfv1: RS/6000 and PowerPC Options. + (line 632) +* mabi=elfv2: RS/6000 and PowerPC Options. + (line 638) * mabi=gnu: MMIX Options. (line 20) * mabi=ibmlongdouble: RS/6000 and PowerPC Options. - (line 555) + (line 624) * mabi=ieeelongdouble: RS/6000 and PowerPC Options. - (line 559) + (line 628) * mabi=mmixware: MMIX Options. (line 20) * mabi=n32: MIPS Options. (line 131) * mabi=no-spe: RS/6000 and PowerPC Options. - (line 552) + (line 621) * mabi=o64: MIPS Options. (line 131) * mabi=spe: RS/6000 and PowerPC Options. - (line 547) + (line 616) * mabicalls: MIPS Options. (line 155) -* mabort-on-noreturn: ARM Options. (line 183) +* mabort-on-noreturn: ARM Options. (line 184) * mabsdiff: MeP Options. (line 7) * mabshi: PDP-11 Options. (line 55) * mac0: PDP-11 Options. (line 16) * macc-4: FRV Options. (line 113) * macc-8: FRV Options. (line 116) -* maccumulate-args: AVR Options. (line 139) +* maccumulate-args: AVR Options. (line 135) * maccumulate-outgoing-args <1>: SH Options. (line 330) * maccumulate-outgoing-args: i386 and x86-64 Options. - (line 738) + (line 744) * maddress-mode=long: i386 and x86-64 Options. - (line 878) + (line 884) * maddress-mode=short: i386 and x86-64 Options. - (line 883) + (line 889) * maddress-space-conversion: SPU Options. (line 63) * mads: RS/6000 and PowerPC Options. - (line 585) + (line 666) * maix-struct-return: RS/6000 and PowerPC Options. - (line 535) + (line 604) * maix32: RS/6000 and PowerPC Options. - (line 245) + (line 314) * maix64: RS/6000 and PowerPC Options. - (line 245) + (line 314) * malign-300: H8/300 Options. (line 41) * malign-double: i386 and x86-64 Options. - (line 320) + (line 326) * malign-int: M680x0 Options. (line 267) * malign-labels: FRV Options. (line 104) * malign-loops: M32R/D Options. (line 73) * malign-natural: RS/6000 and PowerPC Options. - (line 284) + (line 353) * malign-power: RS/6000 and PowerPC Options. - (line 284) + (line 353) * mall-opts: MeP Options. (line 11) * malloc-cc: FRV Options. (line 25) * maltivec: RS/6000 and PowerPC Options. - (line 132) + (line 134) +* maltivec=be: RS/6000 and PowerPC Options. + (line 150) +* maltivec=le: RS/6000 and PowerPC Options. + (line 160) * mam33: MN10300 Options. (line 17) * mam33-2: MN10300 Options. (line 24) * mam34: MN10300 Options. (line 27) @@ -49219,18 +50187,18 @@ look up both forms. * march <5>: HPPA Options. (line 9) * march <6>: CRIS Options. (line 10) * march <7>: C6X Options. (line 7) -* march <8>: ARM Options. (line 128) +* march <8>: ARM Options. (line 75) * march: AArch64 Options. (line 55) -* marm: ARM Options. (line 244) +* marm: ARM Options. (line 248) * mas100-syntax: RX Options. (line 76) * masm=DIALECT: i386 and x86-64 Options. - (line 275) + (line 281) * matomic-model=MODEL: SH Options. (line 144) * matomic-updates: SPU Options. (line 78) * mauto-pic: IA-64 Options. (line 50) * maverage: MeP Options. (line 16) * mavoid-indexed-addresses: RS/6000 and PowerPC Options. - (line 354) + (line 423) * max-vect-align: Adapteva Epiphany Options. (line 120) * mb: SH Options. (line 74) @@ -49242,9 +50210,9 @@ look up both forms. * mbcopy: PDP-11 Options. (line 36) * mbcopy-builtin: PDP-11 Options. (line 32) * mbig: RS/6000 and PowerPC Options. - (line 434) + (line 503) * mbig-endian <1>: RS/6000 and PowerPC Options. - (line 434) + (line 503) * mbig-endian <2>: MicroBlaze Options. (line 57) * mbig-endian <3>: MCore Options. (line 39) * mbig-endian <4>: IA-64 Options. (line 9) @@ -49257,16 +50225,16 @@ look up both forms. * mbigtable: SH Options. (line 89) * mbionic: GNU/Linux Options. (line 17) * mbit-align: RS/6000 and PowerPC Options. - (line 386) + (line 455) * mbit-ops: CR16 Options. (line 25) * mbitfield: M680x0 Options. (line 235) * mbitops <1>: SH Options. (line 93) * mbitops: MeP Options. (line 26) * mblock-move-inline-limit: RS/6000 and PowerPC Options. - (line 656) + (line 737) * mbranch-cheap: PDP-11 Options. (line 65) * mbranch-cost <1>: MIPS Options. (line 635) -* mbranch-cost <2>: AVR Options. (line 154) +* mbranch-cost <2>: AVR Options. (line 150) * mbranch-cost: Adapteva Epiphany Options. (line 18) * mbranch-cost=NUM: SH Options. (line 396) @@ -49276,7 +50244,7 @@ look up both forms. * mbranch-likely: MIPS Options. (line 642) * mbranch-predict: MMIX Options. (line 49) * mbss-plt: RS/6000 and PowerPC Options. - (line 155) + (line 187) * mbuild-constants: DEC Alpha Options. (line 141) * mbwx: DEC Alpha Options. (line 163) * mc68000: M680x0 Options. (line 95) @@ -49284,50 +50252,50 @@ look up both forms. * mc=: MeP Options. (line 31) * mcache-size: SPU Options. (line 70) * mcall-eabi: RS/6000 and PowerPC Options. - (line 509) + (line 578) * mcall-freebsd: RS/6000 and PowerPC Options. - (line 523) + (line 592) * mcall-linux: RS/6000 and PowerPC Options. - (line 519) + (line 588) * mcall-netbsd: RS/6000 and PowerPC Options. - (line 527) -* mcall-prologues: AVR Options. (line 159) + (line 596) +* mcall-prologues: AVR Options. (line 155) * mcall-sysv: RS/6000 and PowerPC Options. - (line 501) + (line 570) * mcall-sysv-eabi: RS/6000 and PowerPC Options. - (line 509) + (line 578) * mcall-sysv-noeabi: RS/6000 and PowerPC Options. - (line 512) -* mcallee-super-interworking: ARM Options. (line 262) -* mcaller-super-interworking: ARM Options. (line 269) + (line 581) +* mcallee-super-interworking: ARM Options. (line 266) +* mcaller-super-interworking: ARM Options. (line 273) * mcallgraph-data: MCore Options. (line 31) -* mcbcond: SPARC Options. (line 216) +* mcbcond: SPARC Options. (line 224) * mcbranchdi: SH Options. (line 411) * mcc-init: CRIS Options. (line 41) * mcfv4e: M680x0 Options. (line 172) * mcheck-zero-division: MIPS Options. (line 441) * mcix: DEC Alpha Options. (line 163) * mcld: i386 and x86-64 Options. - (line 588) + (line 594) * mclip: MeP Options. (line 35) -* mcmodel: SPARC Options. (line 250) +* mcmodel: SPARC Options. (line 262) * mcmodel=kernel: i386 and x86-64 Options. - (line 862) + (line 868) * mcmodel=large <1>: TILE-Gx Options. (line 14) * mcmodel=large <2>: RS/6000 and PowerPC Options. - (line 126) + (line 128) * mcmodel=large <3>: i386 and x86-64 Options. - (line 874) + (line 880) * mcmodel=large: AArch64 Options. (line 33) * mcmodel=medium <1>: RS/6000 and PowerPC Options. - (line 122) + (line 124) * mcmodel=medium: i386 and x86-64 Options. - (line 867) + (line 873) * mcmodel=small <1>: TILE-Gx Options. (line 9) * mcmodel=small <2>: RS/6000 and PowerPC Options. - (line 118) + (line 120) * mcmodel=small <3>: i386 and x86-64 Options. - (line 856) + (line 862) * mcmodel=small: AArch64 Options. (line 27) * mcmodel=tiny: AArch64 Options. (line 20) * mcmove: Adapteva Epiphany Options. @@ -49336,6 +50304,8 @@ look up both forms. (line 27) * mcmpeqdi: SH Options. (line 414) * mcode-readable: MIPS Options. (line 401) +* mcompat-align-parm: RS/6000 and PowerPC Options. + (line 895) * mcond-exec: FRV Options. (line 152) * mcond-move: FRV Options. (line 128) * mconfig=: MeP Options. (line 39) @@ -49351,17 +50321,17 @@ look up both forms. * mcoreb: Blackfin Options. (line 164) * mcpu <1>: TILEPro Options. (line 9) * mcpu <2>: TILE-Gx Options. (line 18) -* mcpu <3>: SPARC Options. (line 94) +* mcpu <3>: SPARC Options. (line 102) * mcpu <4>: RS/6000 and PowerPC Options. (line 69) * mcpu <5>: picoChip Options. (line 9) * mcpu <6>: M680x0 Options. (line 28) * mcpu <7>: i386 and x86-64 Options. - (line 223) + (line 229) * mcpu <8>: FRV Options. (line 212) * mcpu <9>: DEC Alpha Options. (line 215) * mcpu <10>: CRIS Options. (line 10) -* mcpu <11>: ARM Options. (line 75) +* mcpu <11>: ARM Options. (line 124) * mcpu: AArch64 Options. (line 69) * mcpu32: M680x0 Options. (line 138) * mcpu= <1>: MicroBlaze Options. (line 20) @@ -49370,10 +50340,12 @@ look up both forms. * mcr16c: CR16 Options. (line 14) * mcr16cplus: CR16 Options. (line 14) * mcrc32: i386 and x86-64 Options. - (line 635) + (line 641) +* mcrypto: RS/6000 and PowerPC Options. + (line 222) * mcsync-anomaly: Blackfin Options. (line 60) * mcx16: i386 and x86-64 Options. - (line 612) + (line 618) * MD: Preprocessor Options. (line 274) * mdalign: SH Options. (line 80) @@ -49385,6 +50357,8 @@ look up both forms. * mdebug: M32R/D Options. (line 69) * mdebug-main=PREFIX: VMS Options. (line 13) * mdec-asm: PDP-11 Options. (line 72) +* mdirect-move: RS/6000 and PowerPC Options. + (line 228) * mdisable-callt: V850 Options. (line 92) * mdisable-fpregs: HPPA Options. (line 33) * mdisable-indexing: HPPA Options. (line 39) @@ -49399,11 +50373,11 @@ look up both forms. * mdll: i386 and x86-64 Windows Options. (line 16) * mdlmzb: RS/6000 and PowerPC Options. - (line 379) + (line 448) * mdmx: MIPS Options. (line 290) * mdouble: FRV Options. (line 38) * mdouble-float <1>: RS/6000 and PowerPC Options. - (line 302) + (line 371) * mdouble-float: MIPS Options. (line 248) * mdsp: MIPS Options. (line 267) * mdspr2: MIPS Options. (line 273) @@ -49411,11 +50385,11 @@ look up both forms. * mdwarf2-asm: IA-64 Options. (line 94) * mdword: FRV Options. (line 32) * mdynamic-no-pic: RS/6000 and PowerPC Options. - (line 439) + (line 508) * mea32: SPU Options. (line 55) * mea64: SPU Options. (line 55) * meabi: RS/6000 and PowerPC Options. - (line 604) + (line 685) * mearly-stop-bits: IA-64 Options. (line 100) * meb <1>: Score Options. (line 9) * meb <2>: Moxie Options. (line 7) @@ -49426,7 +50400,7 @@ look up both forms. * melf <1>: MMIX Options. (line 44) * melf: CRIS Options. (line 87) * memb: RS/6000 and PowerPC Options. - (line 599) + (line 680) * membedded-data: MIPS Options. (line 388) * memregs=: M32C Options. (line 21) * mep: V850 Options. (line 16) @@ -49444,19 +50418,20 @@ look up both forms. (line 220) * mfast-fp: Blackfin Options. (line 133) * mfast-indirect-calls: HPPA Options. (line 51) -* mfaster-structs: SPARC Options. (line 84) +* mfaster-structs: SPARC Options. (line 92) * mfdpic: FRV Options. (line 56) * mfentry: i386 and x86-64 Options. - (line 811) + (line 817) * mfix: DEC Alpha Options. (line 163) * mfix-24k: MIPS Options. (line 500) * mfix-and-continue: Darwin Options. (line 104) -* mfix-at697f: SPARC Options. (line 236) -* mfix-cortex-m3-ldrd: ARM Options. (line 302) +* mfix-at697f: SPARC Options. (line 244) +* mfix-cortex-m3-ldrd: ARM Options. (line 306) * mfix-r10000: MIPS Options. (line 527) * mfix-r4000: MIPS Options. (line 506) * mfix-r4400: MIPS Options. (line 520) * mfix-sb1: MIPS Options. (line 559) +* mfix-ut699: SPARC Options. (line 249) * mfix-vr4120: MIPS Options. (line 538) * mfix-vr4130: MIPS Options. (line 552) * mfixed-cc: FRV Options. (line 28) @@ -49464,11 +50439,11 @@ look up both forms. * mfixed-range <2>: SH Options. (line 343) * mfixed-range <3>: IA-64 Options. (line 105) * mfixed-range: HPPA Options. (line 58) -* mflat: SPARC Options. (line 20) +* mflat: SPARC Options. (line 22) * mflip-mips16: MIPS Options. (line 111) * mfloat-abi: ARM Options. (line 42) * mfloat-gprs: RS/6000 and PowerPC Options. - (line 190) + (line 259) * mfloat-ieee: DEC Alpha Options. (line 171) * mfloat-vax: DEC Alpha Options. (line 171) * mfloat32: PDP-11 Options. (line 52) @@ -49476,7 +50451,7 @@ look up both forms. * mflush-func: MIPS Options. (line 626) * mflush-func=NAME: M32R/D Options. (line 93) * mflush-trap=NUMBER: M32R/D Options. (line 86) -* mfmaf: SPARC Options. (line 230) +* mfmaf: SPARC Options. (line 238) * mfmovd: SH Options. (line 96) * mforce-no-pic: Xtensa Options. (line 41) * mfp-exceptions: MIPS Options. (line 653) @@ -49485,33 +50460,33 @@ look up both forms. * mfp-reg: DEC Alpha Options. (line 25) * mfp-rounding-mode: DEC Alpha Options. (line 85) * mfp-trap-mode: DEC Alpha Options. (line 63) -* mfp16-format: ARM Options. (line 163) +* mfp16-format: ARM Options. (line 164) * mfp32: MIPS Options. (line 221) * mfp64: MIPS Options. (line 224) * mfpmath <1>: i386 and x86-64 Options. - (line 226) + (line 232) * mfpmath: Optimize Options. (line 1898) * mfpr-32: FRV Options. (line 13) * mfpr-64: FRV Options. (line 16) * mfprnd: RS/6000 and PowerPC Options. (line 27) -* mfpu <1>: SPARC Options. (line 33) +* mfpu <1>: SPARC Options. (line 35) * mfpu <2>: RS/6000 and PowerPC Options. - (line 310) + (line 379) * mfpu <3>: PDP-11 Options. (line 9) -* mfpu: ARM Options. (line 143) +* mfpu: ARM Options. (line 144) * mfriz: RS/6000 and PowerPC Options. - (line 785) + (line 866) * mfsca: SH Options. (line 428) * mfsrra: SH Options. (line 437) * mfull-toc: RS/6000 and PowerPC Options. - (line 218) + (line 287) * mfused-madd <1>: Xtensa Options. (line 19) * mfused-madd <2>: SH Options. (line 419) * mfused-madd <3>: S/390 and zSeries Options. (line 137) * mfused-madd <4>: RS/6000 and PowerPC Options. - (line 363) + (line 432) * mfused-madd <5>: MIPS Options. (line 482) * mfused-madd: IA-64 Options. (line 88) * mg: VAX Options. (line 17) @@ -49520,7 +50495,7 @@ look up both forms. * mgas: HPPA Options. (line 74) * mgcc-abi: V850 Options. (line 148) * mgen-cell-microcode: RS/6000 and PowerPC Options. - (line 143) + (line 175) * mgeneral-regs-only: AArch64 Options. (line 13) * mgettrcost=NUMBER: SH Options. (line 360) * mghs: V850 Options. (line 127) @@ -49544,20 +50519,22 @@ look up both forms. * mhard-dfp: RS/6000 and PowerPC Options. (line 27) * mhard-float <1>: V850 Options. (line 113) -* mhard-float <2>: SPARC Options. (line 33) +* mhard-float <2>: SPARC Options. (line 35) * mhard-float <3>: S/390 and zSeries Options. (line 11) * mhard-float <4>: RS/6000 and PowerPC Options. - (line 296) + (line 365) * mhard-float <5>: MIPS Options. (line 227) * mhard-float <6>: MicroBlaze Options. (line 10) * mhard-float <7>: M680x0 Options. (line 197) * mhard-float: FRV Options. (line 19) -* mhard-quad-float: SPARC Options. (line 54) +* mhard-quad-float: SPARC Options. (line 56) * mhardlit: MCore Options. (line 10) * mhint-max-distance: SPU Options. (line 102) * mhint-max-nops: SPU Options. (line 96) * mhitachi: SH Options. (line 100) +* mhotpatch: S/390 and zSeries Options. + (line 174) * mhp-ld: HPPA Options. (line 122) * micplb: Blackfin Options. (line 178) * mid-shared-library: Blackfin Options. (line 81) @@ -49565,15 +50542,15 @@ look up both forms. * mieee: DEC Alpha Options. (line 39) * mieee-conformant: DEC Alpha Options. (line 134) * mieee-fp: i386 and x86-64 Options. - (line 281) + (line 287) * mieee-with-inexact: DEC Alpha Options. (line 52) * milp32: IA-64 Options. (line 121) * mimpure-text: Solaris 2 Options. (line 9) * mincoming-stack-boundary: i386 and x86-64 Options. - (line 486) + (line 492) * mindexed-addressing: SH Options. (line 350) * minline-all-stringops: i386 and x86-64 Options. - (line 759) + (line 765) * minline-float-divide-max-throughput: IA-64 Options. (line 58) * minline-float-divide-min-latency: IA-64 Options. (line 54) * minline-ic_invalidate: SH Options. (line 125) @@ -49584,15 +50561,15 @@ look up both forms. * minline-sqrt-max-throughput: IA-64 Options. (line 80) * minline-sqrt-min-latency: IA-64 Options. (line 76) * minline-stringops-dynamically: i386 and x86-64 Options. - (line 766) + (line 772) * minsert-sched-nops: RS/6000 and PowerPC Options. - (line 479) + (line 548) * mint-register: RX Options. (line 100) * mint16: PDP-11 Options. (line 40) * mint32 <1>: PDP-11 Options. (line 44) * mint32 <2>: H8/300 Options. (line 38) * mint32: CR16 Options. (line 22) -* mint8: AVR Options. (line 163) +* mint8: AVR Options. (line 159) * minterlink-mips16: MIPS Options. (line 118) * minvalid-symbols: SH Options. (line 386) * mio-volatile: MeP Options. (line 74) @@ -49607,7 +50584,7 @@ look up both forms. * mips64: MIPS Options. (line 96) * mips64r2: MIPS Options. (line 99) * misel: RS/6000 and PowerPC Options. - (line 161) + (line 193) * misize: SH Options. (line 137) * missue-rate=NUMBER: M32R/D Options. (line 79) * mivc2: MeP Options. (line 59) @@ -49618,7 +50595,7 @@ look up both forms. * ml: MeP Options. (line 78) * mlarge-data: DEC Alpha Options. (line 187) * mlarge-data-threshold: i386 and x86-64 Options. - (line 372) + (line 378) * mlarge-mem: SPU Options. (line 35) * mlarge-text: DEC Alpha Options. (line 205) * mleadz: MeP Options. (line 81) @@ -49629,9 +50606,9 @@ look up both forms. * mlinker-opt: HPPA Options. (line 84) * mlinux: CRIS Options. (line 91) * mlittle: RS/6000 and PowerPC Options. - (line 428) + (line 497) * mlittle-endian <1>: RS/6000 and PowerPC Options. - (line 428) + (line 497) * mlittle-endian <2>: MicroBlaze Options. (line 60) * mlittle-endian <3>: MCore Options. (line 39) * mlittle-endian <4>: IA-64 Options. (line 13) @@ -49646,7 +50623,7 @@ look up both forms. * mlong-calls <2>: MIPS Options. (line 468) * mlong-calls <3>: FRV Options. (line 99) * mlong-calls <4>: Blackfin Options. (line 121) -* mlong-calls <5>: ARM Options. (line 188) +* mlong-calls <5>: ARM Options. (line 189) * mlong-calls: Adapteva Epiphany Options. (line 55) * mlong-double-128: S/390 and zSeries Options. @@ -49654,15 +50631,15 @@ look up both forms. * mlong-double-64 <1>: S/390 and zSeries Options. (line 29) * mlong-double-64: i386 and x86-64 Options. - (line 361) + (line 367) * mlong-double-80: i386 and x86-64 Options. - (line 361) + (line 367) * mlong-jumps: V850 Options. (line 108) * mlong-load-store: HPPA Options. (line 65) * mlong32: MIPS Options. (line 313) * mlong64: MIPS Options. (line 308) * mlongcall: RS/6000 and PowerPC Options. - (line 676) + (line 757) * mlongcalls: Xtensa Options. (line 72) * mloop: V850 Options. (line 121) * mlow-64k: Blackfin Options. (line 70) @@ -49686,42 +50663,42 @@ look up both forms. * mmemcpy <1>: MIPS Options. (line 462) * mmemcpy: MicroBlaze Options. (line 13) * mmemory-latency: DEC Alpha Options. (line 268) -* mmemory-model: SPARC Options. (line 278) +* mmemory-model: SPARC Options. (line 290) * mmfcrf: RS/6000 and PowerPC Options. (line 27) * mmfpgpr: RS/6000 and PowerPC Options. (line 27) * mminimal-toc: RS/6000 and PowerPC Options. - (line 218) + (line 287) * mminmax: MeP Options. (line 87) * mmmx: i386 and x86-64 Options. - (line 565) + (line 571) * mmodel=large: M32R/D Options. (line 33) * mmodel=medium: M32R/D Options. (line 27) * mmodel=small: M32R/D Options. (line 18) * mmovbe: i386 and x86-64 Options. - (line 631) + (line 637) * mmt: MIPS Options. (line 301) * mmul: RL78 Options. (line 13) * mmul-bug-workaround: CRIS Options. (line 31) * mmuladd: FRV Options. (line 50) * mmulhw: RS/6000 and PowerPC Options. - (line 372) + (line 441) * mmult: MeP Options. (line 90) * mmult-bug: MN10300 Options. (line 9) * mmulti-cond-exec: FRV Options. (line 176) * mmulticore: Blackfin Options. (line 142) * mmultiple: RS/6000 and PowerPC Options. - (line 322) + (line 391) * mmvcle: S/390 and zSeries Options. (line 105) * mmvme: RS/6000 and PowerPC Options. - (line 580) + (line 661) * mn: H8/300 Options. (line 20) * mnested-cond-exec: FRV Options. (line 189) * mnhwloop: Score Options. (line 15) * mno-3dnow: i386 and x86-64 Options. - (line 565) + (line 571) * mno-4byte-functions: MCore Options. (line 27) * mno-8byte-align: V850 Options. (line 170) * mno-abicalls: MIPS Options. (line 155) @@ -49729,31 +50706,31 @@ look up both forms. * mno-ac0: PDP-11 Options. (line 20) * mno-address-space-conversion: SPU Options. (line 63) * mno-align-double: i386 and x86-64 Options. - (line 320) + (line 326) * mno-align-int: M680x0 Options. (line 267) * mno-align-loops: M32R/D Options. (line 76) * mno-align-stringops: i386 and x86-64 Options. - (line 754) + (line 760) * mno-altivec: RS/6000 and PowerPC Options. - (line 132) + (line 134) * mno-am33: MN10300 Options. (line 20) * mno-app-regs <1>: V850 Options. (line 185) * mno-app-regs: SPARC Options. (line 10) * mno-as100-syntax: RX Options. (line 76) * mno-atomic-updates: SPU Options. (line 78) * mno-avoid-indexed-addresses: RS/6000 and PowerPC Options. - (line 354) + (line 423) * mno-backchain: S/390 and zSeries Options. (line 35) * mno-base-addresses: MMIX Options. (line 54) * mno-bit-align: RS/6000 and PowerPC Options. - (line 386) + (line 455) * mno-bitfield: M680x0 Options. (line 231) * mno-branch-likely: MIPS Options. (line 642) * mno-branch-predict: MMIX Options. (line 49) * mno-bwx: DEC Alpha Options. (line 163) * mno-callgraph-data: MCore Options. (line 31) -* mno-cbcond: SPARC Options. (line 216) +* mno-cbcond: SPARC Options. (line 224) * mno-check-zero-division: MIPS Options. (line 441) * mno-cix: DEC Alpha Options. (line 163) * mno-clearbss: MicroBlaze Options. (line 16) @@ -49765,22 +50742,26 @@ look up both forms. * mno-const16: Xtensa Options. (line 10) * mno-crt0 <1>: Moxie Options. (line 14) * mno-crt0: MN10300 Options. (line 43) +* mno-crypto: RS/6000 and PowerPC Options. + (line 222) * mno-csync-anomaly: Blackfin Options. (line 66) * mno-data-align: CRIS Options. (line 55) * mno-debug: S/390 and zSeries Options. (line 112) +* mno-direct-move: RS/6000 and PowerPC Options. + (line 228) * mno-disable-callt: V850 Options. (line 92) * mno-div <1>: MCore Options. (line 15) * mno-div: M680x0 Options. (line 209) * mno-dlmzb: RS/6000 and PowerPC Options. - (line 379) + (line 448) * mno-double: FRV Options. (line 41) * mno-dsp: MIPS Options. (line 267) * mno-dspr2: MIPS Options. (line 273) * mno-dwarf2-asm: IA-64 Options. (line 94) * mno-dword: FRV Options. (line 35) * mno-eabi: RS/6000 and PowerPC Options. - (line 604) + (line 685) * mno-early-stop-bits: IA-64 Options. (line 100) * mno-eflags: FRV Options. (line 125) * mno-embedded-data: MIPS Options. (line 388) @@ -49791,28 +50772,28 @@ look up both forms. * mno-exr: H8/300 Options. (line 33) * mno-extern-sdata: MIPS Options. (line 350) * mno-fancy-math-387: i386 and x86-64 Options. - (line 309) -* mno-faster-structs: SPARC Options. (line 84) + (line 315) +* mno-faster-structs: SPARC Options. (line 92) * mno-fix: DEC Alpha Options. (line 163) * mno-fix-24k: MIPS Options. (line 500) * mno-fix-r10000: MIPS Options. (line 527) * mno-fix-r4000: MIPS Options. (line 506) * mno-fix-r4400: MIPS Options. (line 520) -* mno-flat: SPARC Options. (line 20) +* mno-flat: SPARC Options. (line 22) * mno-float: MIPS Options. (line 234) * mno-float32: PDP-11 Options. (line 48) * mno-float64: PDP-11 Options. (line 52) * mno-flush-func: M32R/D Options. (line 98) * mno-flush-trap: M32R/D Options. (line 90) -* mno-fmaf: SPARC Options. (line 230) +* mno-fmaf: SPARC Options. (line 238) * mno-fp-in-toc: RS/6000 and PowerPC Options. - (line 218) + (line 287) * mno-fp-regs: DEC Alpha Options. (line 25) * mno-fp-ret-in-387: i386 and x86-64 Options. - (line 299) + (line 305) * mno-fprnd: RS/6000 and PowerPC Options. (line 27) -* mno-fpu: SPARC Options. (line 38) +* mno-fpu: SPARC Options. (line 40) * mno-fsca: SH Options. (line 428) * mno-fsrra: SH Options. (line 437) * mno-fused-madd <1>: Xtensa Options. (line 19) @@ -49820,7 +50801,7 @@ look up both forms. * mno-fused-madd <3>: S/390 and zSeries Options. (line 137) * mno-fused-madd <4>: RS/6000 and PowerPC Options. - (line 363) + (line 432) * mno-fused-madd <5>: MIPS Options. (line 482) * mno-fused-madd: IA-64 Options. (line 88) * mno-gnu-as: IA-64 Options. (line 18) @@ -49834,16 +50815,16 @@ look up both forms. * mno-hardlit: MCore Options. (line 10) * mno-id-shared-library: Blackfin Options. (line 88) * mno-ieee-fp: i386 and x86-64 Options. - (line 281) + (line 287) * mno-inline-float-divide: IA-64 Options. (line 62) * mno-inline-int-divide: IA-64 Options. (line 73) * mno-inline-sqrt: IA-64 Options. (line 84) * mno-int16: PDP-11 Options. (line 44) * mno-int32: PDP-11 Options. (line 40) * mno-interlink-mips16: MIPS Options. (line 118) -* mno-interrupts: AVR Options. (line 169) +* mno-interrupts: AVR Options. (line 165) * mno-isel: RS/6000 and PowerPC Options. - (line 161) + (line 193) * mno-knuthdiv: MMIX Options. (line 33) * mno-leaf-id-shared-library: Blackfin Options. (line 98) * mno-libfuncs: MMIX Options. (line 10) @@ -49853,10 +50834,10 @@ look up both forms. * mno-long-calls <2>: MIPS Options. (line 468) * mno-long-calls <3>: HPPA Options. (line 135) * mno-long-calls <4>: Blackfin Options. (line 121) -* mno-long-calls: ARM Options. (line 188) +* mno-long-calls: ARM Options. (line 189) * mno-long-jumps: V850 Options. (line 108) * mno-longcall: RS/6000 and PowerPC Options. - (line 676) + (line 757) * mno-longcalls: Xtensa Options. (line 72) * mno-low-64k: Blackfin Options. (line 74) * mno-lsim <1>: MCore Options. (line 46) @@ -49875,16 +50856,16 @@ look up both forms. * mno-mips16: MIPS Options. (line 103) * mno-mips3d: MIPS Options. (line 296) * mno-mmx: i386 and x86-64 Options. - (line 565) + (line 571) * mno-mt: MIPS Options. (line 301) * mno-mul-bug-workaround: CRIS Options. (line 31) * mno-muladd: FRV Options. (line 53) * mno-mulhw: RS/6000 and PowerPC Options. - (line 372) + (line 441) * mno-mult-bug: MN10300 Options. (line 13) * mno-multi-cond-exec: FRV Options. (line 183) * mno-multiple: RS/6000 and PowerPC Options. - (line 322) + (line 391) * mno-mvcle: S/390 and zSeries Options. (line 105) * mno-nested-cond-exec: FRV Options. (line 195) @@ -49895,12 +50876,12 @@ look up both forms. * mno-packed-stack: S/390 and zSeries Options. (line 54) * mno-paired: RS/6000 and PowerPC Options. - (line 175) + (line 207) * mno-paired-single: MIPS Options. (line 284) * mno-pic: IA-64 Options. (line 26) * mno-pid: RX Options. (line 117) * mno-plt: MIPS Options. (line 182) -* mno-popc: SPARC Options. (line 223) +* mno-popc: SPARC Options. (line 231) * mno-popcntb: RS/6000 and PowerPC Options. (line 27) * mno-popcntd: RS/6000 and PowerPC Options. @@ -49909,6 +50890,10 @@ look up both forms. (line 110) * mno-postmodify: Adapteva Epiphany Options. (line 110) +* mno-power8-fusion: RS/6000 and PowerPC Options. + (line 234) +* mno-power8-vector: RS/6000 and PowerPC Options. + (line 240) * mno-powerpc-gfxopt: RS/6000 and PowerPC Options. (line 27) * mno-powerpc-gpopt: RS/6000 and PowerPC Options. @@ -49918,20 +50903,24 @@ look up both forms. * mno-prolog-function: V850 Options. (line 23) * mno-prologue-epilogue: CRIS Options. (line 71) * mno-prototype: RS/6000 and PowerPC Options. - (line 564) + (line 645) * mno-push-args: i386 and x86-64 Options. - (line 731) + (line 737) +* mno-quad-memory: RS/6000 and PowerPC Options. + (line 247) +* mno-quad-memory-atomic: RS/6000 and PowerPC Options. + (line 253) * mno-red-zone: i386 and x86-64 Options. - (line 848) + (line 854) * mno-register-names: IA-64 Options. (line 37) * mno-regnames: RS/6000 and PowerPC Options. - (line 670) + (line 751) * mno-relax: V850 Options. (line 103) * mno-relax-immediate: MCore Options. (line 19) * mno-relocatable: RS/6000 and PowerPC Options. - (line 402) + (line 471) * mno-relocatable-lib: RS/6000 and PowerPC Options. - (line 413) + (line 482) * mno-round-nearest: Adapteva Epiphany Options. (line 51) * mno-rtd: M680x0 Options. (line 262) @@ -49947,7 +50936,7 @@ look up both forms. * mno-sched-prefer-non-data-spec-insns: IA-64 Options. (line 168) * mno-sched-prolog: ARM Options. (line 33) * mno-sdata <1>: RS/6000 and PowerPC Options. - (line 651) + (line 732) * mno-sdata: IA-64 Options. (line 42) * mno-sep-data: Blackfin Options. (line 116) * mno-serialize-volatile: Xtensa Options. (line 35) @@ -49964,53 +50953,54 @@ look up both forms. * mno-soft-float: DEC Alpha Options. (line 10) * mno-space-regs: HPPA Options. (line 44) * mno-spe: RS/6000 and PowerPC Options. - (line 170) + (line 202) * mno-specld-anomaly: Blackfin Options. (line 56) * mno-split-addresses: MIPS Options. (line 426) * mno-sse: i386 and x86-64 Options. - (line 565) + (line 571) * mno-stack-align: CRIS Options. (line 55) -* mno-stack-bias: SPARC Options. (line 302) +* mno-stack-bias: SPARC Options. (line 314) * mno-strict-align <1>: RS/6000 and PowerPC Options. - (line 397) + (line 466) * mno-strict-align: M680x0 Options. (line 287) * mno-string: RS/6000 and PowerPC Options. - (line 333) + (line 402) * mno-sum-in-toc: RS/6000 and PowerPC Options. - (line 218) + (line 287) * mno-sym32: MIPS Options. (line 323) * mno-target-align: Xtensa Options. (line 59) * mno-text-section-literals: Xtensa Options. (line 47) * mno-tls-markers: RS/6000 and PowerPC Options. - (line 709) + (line 790) * mno-toc: RS/6000 and PowerPC Options. - (line 422) + (line 491) * mno-toplevel-symbols: MMIX Options. (line 40) * mno-tpf-trace: S/390 and zSeries Options. (line 131) -* mno-unaligned-access: ARM Options. (line 309) -* mno-unaligned-doubles: SPARC Options. (line 72) +* mno-unaligned-access: ARM Options. (line 313) +* mno-unaligned-doubles: SPARC Options. (line 74) * mno-uninit-const-in-rodata: MIPS Options. (line 396) * mno-update: RS/6000 and PowerPC Options. - (line 344) -* mno-v8plus: SPARC Options. (line 187) + (line 413) +* mno-user-mode: SPARC Options. (line 86) +* mno-v8plus: SPARC Options. (line 195) * mno-vect-double: Adapteva Epiphany Options. (line 116) -* mno-vis: SPARC Options. (line 194) -* mno-vis2: SPARC Options. (line 200) -* mno-vis3: SPARC Options. (line 208) +* mno-vis: SPARC Options. (line 202) +* mno-vis2: SPARC Options. (line 208) +* mno-vis3: SPARC Options. (line 216) * mno-vliw-branch: FRV Options. (line 170) * mno-volatile-asm-stop: IA-64 Options. (line 32) * mno-vrsave: RS/6000 and PowerPC Options. - (line 140) + (line 172) * mno-vsx: RS/6000 and PowerPC Options. - (line 184) + (line 216) * mno-warn-multiple-fast-interrupts: RX Options. (line 143) * mno-wide-bitfields: MCore Options. (line 23) * mno-xgot <1>: MIPS Options. (line 192) * mno-xgot: M680x0 Options. (line 319) * mno-xl-compat: RS/6000 and PowerPC Options. - (line 253) + (line 322) * mno-zdcbranch: SH Options. (line 403) * mno-zero-extend: MMIX Options. (line 27) * mnobitfield: M680x0 Options. (line 231) @@ -50025,7 +51015,7 @@ look up both forms. * mnosplit-lohi: Adapteva Epiphany Options. (line 110) * momit-leaf-frame-pointer <1>: i386 and x86-64 Options. - (line 788) + (line 794) * momit-leaf-frame-pointer <2>: Blackfin Options. (line 44) * momit-leaf-frame-pointer: AArch64 Options. (line 43) * mone-byte-bool: Darwin Options. (line 90) @@ -50040,32 +51030,36 @@ look up both forms. (line 54) * mpadstruct: SH Options. (line 140) * mpaired: RS/6000 and PowerPC Options. - (line 175) + (line 207) * mpaired-single: MIPS Options. (line 284) * mpc32: i386 and x86-64 Options. - (line 435) + (line 441) * mpc64: i386 and x86-64 Options. - (line 435) + (line 441) * mpc80: i386 and x86-64 Options. - (line 435) + (line 441) * mpcrel: M680x0 Options. (line 279) * mpdebug: CRIS Options. (line 35) * mpe: RS/6000 and PowerPC Options. - (line 273) + (line 342) * mpe-aligned-commons: i386 and x86-64 Windows Options. (line 59) -* mpic-register: ARM Options. (line 218) +* mpic-register: ARM Options. (line 219) * mpid: RX Options. (line 117) * mplt: MIPS Options. (line 182) * mpointers-to-nested-functions: RS/6000 and PowerPC Options. - (line 793) -* mpoke-function-name: ARM Options. (line 222) -* mpopc: SPARC Options. (line 223) + (line 874) +* mpoke-function-name: ARM Options. (line 226) +* mpopc: SPARC Options. (line 231) * mpopcntb: RS/6000 and PowerPC Options. (line 27) * mpopcntd: RS/6000 and PowerPC Options. (line 27) * mportable-runtime: HPPA Options. (line 70) +* mpower8-fusion: RS/6000 and PowerPC Options. + (line 234) +* mpower8-vector: RS/6000 and PowerPC Options. + (line 240) * mpowerpc-gfxopt: RS/6000 and PowerPC Options. (line 27) * mpowerpc-gpopt: RS/6000 and PowerPC Options. @@ -50073,52 +51067,56 @@ look up both forms. * mpowerpc64: RS/6000 and PowerPC Options. (line 27) * mprefer-avx128: i386 and x86-64 Options. - (line 608) + (line 614) * mprefer-short-insn-regs: Adapteva Epiphany Options. (line 13) * mprefergot: SH Options. (line 225) * mpreferred-stack-boundary: i386 and x86-64 Options. - (line 465) + (line 471) * mpretend-cmove: SH Options. (line 446) * mprioritize-restricted-insns: RS/6000 and PowerPC Options. - (line 451) + (line 520) * mprolog-function: V850 Options. (line 23) * mprologue-epilogue: CRIS Options. (line 71) * mprototype: RS/6000 and PowerPC Options. - (line 564) + (line 645) * mpt-fixed: SH Options. (line 364) * mpush-args: i386 and x86-64 Options. - (line 731) + (line 737) * MQ: Preprocessor Options. (line 265) +* mquad-memory: RS/6000 and PowerPC Options. + (line 247) +* mquad-memory-atomic: RS/6000 and PowerPC Options. + (line 253) * mr10k-cache-barrier: MIPS Options. (line 564) * mrecip <1>: RS/6000 and PowerPC Options. - (line 721) + (line 802) * mrecip: i386 and x86-64 Options. - (line 641) + (line 647) * mrecip-precision: RS/6000 and PowerPC Options. - (line 757) + (line 838) * mrecip=opt <1>: RS/6000 and PowerPC Options. - (line 734) + (line 815) * mrecip=opt: i386 and x86-64 Options. - (line 663) + (line 669) * mregister-names: IA-64 Options. (line 37) * mregnames: RS/6000 and PowerPC Options. - (line 670) + (line 751) * mregparm: i386 and x86-64 Options. - (line 402) + (line 408) * mrelax <1>: V850 Options. (line 103) * mrelax <2>: SH Options. (line 85) * mrelax <3>: RX Options. (line 95) * mrelax <4>: MN10300 Options. (line 46) * mrelax <5>: H8/300 Options. (line 9) -* mrelax: AVR Options. (line 173) +* mrelax: AVR Options. (line 169) * mrelax-immediate: MCore Options. (line 19) * mrelax-pic-calls: MIPS Options. (line 689) * mrelocatable: RS/6000 and PowerPC Options. - (line 402) + (line 471) * mrelocatable-lib: RS/6000 and PowerPC Options. - (line 413) + (line 482) * mrepeat: MeP Options. (line 96) * mreturn-pointer-on-d0: MN10300 Options. (line 36) * mrh850-abi: V850 Options. (line 127) @@ -50126,7 +51124,7 @@ look up both forms. (line 177) * mrtd <2>: M680x0 Options. (line 240) * mrtd: i386 and x86-64 Options. - (line 378) + (line 384) * mrtp: VxWorks Options. (line 11) * ms <1>: MeP Options. (line 100) * ms: H8/300 Options. (line 17) @@ -50134,11 +51132,11 @@ look up both forms. * msafe-dma: SPU Options. (line 17) * msafe-hints: SPU Options. (line 107) * msahf: i386 and x86-64 Options. - (line 621) + (line 627) * msatur: MeP Options. (line 105) * msave-acc-in-interrupts: RX Options. (line 109) * msave-toc-indirect: RS/6000 and PowerPC Options. - (line 805) + (line 886) * mscc: FRV Options. (line 140) * msched-ar-data-spec: IA-64 Options. (line 134) * msched-ar-in-data-spec: IA-64 Options. (line 155) @@ -50146,7 +51144,7 @@ look up both forms. * msched-br-in-data-spec: IA-64 Options. (line 148) * msched-control-spec: IA-64 Options. (line 140) * msched-costly-dep: RS/6000 and PowerPC Options. - (line 458) + (line 527) * msched-count-spec-in-critical-path: IA-64 Options. (line 182) * msched-fp-mem-deps-zero-cost: IA-64 Options. (line 198) * msched-in-control-spec: IA-64 Options. (line 162) @@ -50163,28 +51161,28 @@ look up both forms. * mscore7d: Score Options. (line 34) * msda: V850 Options. (line 40) * msdata <1>: RS/6000 and PowerPC Options. - (line 638) + (line 719) * msdata: IA-64 Options. (line 42) * msdata=all: C6X Options. (line 30) * msdata=data: RS/6000 and PowerPC Options. - (line 643) + (line 724) * msdata=default <1>: RS/6000 and PowerPC Options. - (line 638) + (line 719) * msdata=default: C6X Options. (line 22) * msdata=eabi: RS/6000 and PowerPC Options. - (line 618) + (line 699) * msdata=none <1>: RS/6000 and PowerPC Options. - (line 651) + (line 732) * msdata=none <2>: M32R/D Options. (line 40) * msdata=none: C6X Options. (line 35) * msdata=sdata: M32R/D Options. (line 49) * msdata=sysv: RS/6000 and PowerPC Options. - (line 629) + (line 710) * msdata=use: M32R/D Options. (line 53) * msdram <1>: MeP Options. (line 110) * msdram: Blackfin Options. (line 172) * msecure-plt: RS/6000 and PowerPC Options. - (line 150) + (line 182) * msel-sched-dont-check-control-spec: IA-64 Options. (line 203) * msep-data: Blackfin Options. (line 110) * mserialize-volatile: Xtensa Options. (line 35) @@ -50195,7 +51193,7 @@ look up both forms. * msim <1>: Xstormy16 Options. (line 9) * msim <2>: RX Options. (line 71) * msim <3>: RS/6000 and PowerPC Options. - (line 574) + (line 655) * msim <4>: RL78 Options. (line 7) * msim <5>: MeP Options. (line 114) * msim <6>: M32C Options. (line 13) @@ -50204,14 +51202,14 @@ look up both forms. * msim: Blackfin Options. (line 37) * msimnovec: MeP Options. (line 117) * msimple-fpu: RS/6000 and PowerPC Options. - (line 306) + (line 375) * msingle-exit: MMIX Options. (line 66) * msingle-float <1>: RS/6000 and PowerPC Options. - (line 302) + (line 371) * msingle-float: MIPS Options. (line 244) * msingle-pic-base <1>: RS/6000 and PowerPC Options. - (line 445) -* msingle-pic-base: ARM Options. (line 212) + (line 514) +* msingle-pic-base: ARM Options. (line 213) * msio: HPPA Options. (line 104) * mslow-bytes: MCore Options. (line 35) * msmall-data: DEC Alpha Options. (line 187) @@ -50226,38 +51224,38 @@ look up both forms. (line 67) * msmartmips: MIPS Options. (line 280) * msoft-float <1>: V850 Options. (line 113) -* msoft-float <2>: SPARC Options. (line 38) +* msoft-float <2>: SPARC Options. (line 40) * msoft-float <3>: S/390 and zSeries Options. (line 11) * msoft-float <4>: RS/6000 and PowerPC Options. - (line 296) + (line 365) * msoft-float <5>: PDP-11 Options. (line 13) * msoft-float <6>: MIPS Options. (line 230) * msoft-float <7>: MicroBlaze Options. (line 7) * msoft-float <8>: M680x0 Options. (line 203) * msoft-float <9>: i386 and x86-64 Options. - (line 286) + (line 292) * msoft-float <10>: HPPA Options. (line 90) * msoft-float <11>: FRV Options. (line 22) * msoft-float: DEC Alpha Options. (line 10) -* msoft-quad-float: SPARC Options. (line 58) -* msp8: AVR Options. (line 187) +* msoft-quad-float: SPARC Options. (line 60) +* msp8: AVR Options. (line 183) * mspace <1>: V850 Options. (line 30) * mspace: SH Options. (line 222) * mspe: RS/6000 and PowerPC Options. - (line 170) + (line 202) * mspecld-anomaly: Blackfin Options. (line 51) * msplit-addresses: MIPS Options. (line 426) * msplit-vecmove-early: Adapteva Epiphany Options. (line 127) * msse: i386 and x86-64 Options. - (line 565) + (line 571) * msse2avx: i386 and x86-64 Options. - (line 806) + (line 812) * msseregparm: i386 and x86-64 Options. - (line 413) + (line 419) * mstack-align: CRIS Options. (line 55) -* mstack-bias: SPARC Options. (line 302) +* mstack-bias: SPARC Options. (line 314) * mstack-check-l1: Blackfin Options. (line 77) * mstack-guard: S/390 and zSeries Options. (line 156) @@ -50267,20 +51265,20 @@ look up both forms. * mstack-size: S/390 and zSeries Options. (line 156) * mstackrealign: i386 and x86-64 Options. - (line 456) + (line 462) * mstdmain: SPU Options. (line 40) * mstrict-align <1>: RS/6000 and PowerPC Options. - (line 397) + (line 466) * mstrict-align <2>: M680x0 Options. (line 287) * mstrict-align: AArch64 Options. (line 38) -* mstrict-X: AVR Options. (line 200) +* mstrict-X: AVR Options. (line 196) * mstring: RS/6000 and PowerPC Options. - (line 333) + (line 402) * mstringop-strategy=ALG: i386 and x86-64 Options. - (line 770) -* mstructure-size-boundary: ARM Options. (line 169) + (line 776) +* mstructure-size-boundary: ARM Options. (line 170) * msvr4-struct-return: RS/6000 and PowerPC Options. - (line 538) + (line 607) * msym32: MIPS Options. (line 323) * msynci: MIPS Options. (line 674) * MT: Preprocessor Options. @@ -50293,47 +51291,47 @@ look up both forms. * mthread: i386 and x86-64 Windows Options. (line 26) * mthreads: i386 and x86-64 Options. - (line 746) -* mthumb: ARM Options. (line 244) + (line 752) +* mthumb: ARM Options. (line 248) * mthumb-interwork: ARM Options. (line 25) -* mtiny-stack: AVR Options. (line 214) +* mtiny-stack: AVR Options. (line 210) * mtiny=: MeP Options. (line 125) * mtls: FRV Options. (line 75) * mTLS: FRV Options. (line 72) * mtls-dialect <1>: i386 and x86-64 Options. - (line 724) -* mtls-dialect: ARM Options. (line 285) + (line 730) +* mtls-dialect: ARM Options. (line 289) * mtls-dialect=desc: AArch64 Options. (line 47) * mtls-dialect=traditional: AArch64 Options. (line 51) * mtls-direct-seg-refs: i386 and x86-64 Options. - (line 796) + (line 802) * mtls-markers: RS/6000 and PowerPC Options. - (line 709) + (line 790) * mtls-size: IA-64 Options. (line 112) * mtoc: RS/6000 and PowerPC Options. - (line 422) + (line 491) * mtomcat-stats: FRV Options. (line 209) * mtoplevel-symbols: MMIX Options. (line 40) -* mtp: ARM Options. (line 277) -* mtpcs-frame: ARM Options. (line 250) -* mtpcs-leaf-frame: ARM Options. (line 256) +* mtp: ARM Options. (line 281) +* mtpcs-frame: ARM Options. (line 254) +* mtpcs-leaf-frame: ARM Options. (line 260) * mtpf-trace: S/390 and zSeries Options. (line 131) * mtrap-precision: DEC Alpha Options. (line 109) -* mtune <1>: SPARC Options. (line 173) +* mtune <1>: SPARC Options. (line 181) * mtune <2>: S/390 and zSeries Options. (line 124) * mtune <3>: RS/6000 and PowerPC Options. - (line 110) + (line 112) * mtune <4>: MN10300 Options. (line 30) * mtune <5>: MIPS Options. (line 63) * mtune <6>: M680x0 Options. (line 70) * mtune <7>: IA-64 Options. (line 116) * mtune <8>: i386 and x86-64 Options. - (line 189) + (line 195) * mtune <9>: DEC Alpha Options. (line 259) * mtune <10>: CRIS Options. (line 16) -* mtune <11>: ARM Options. (line 105) +* mtune <11>: ARM Options. (line 90) * mtune: AArch64 Options. (line 82) * muclibc: GNU/Linux Options. (line 13) * muls: Score Options. (line 18) @@ -50343,8 +51341,8 @@ look up both forms. * multiply-enabled: LM32 Options. (line 15) * multiply_defined: Darwin Options. (line 196) * multiply_defined_unused: Darwin Options. (line 196) -* munaligned-access: ARM Options. (line 309) -* munaligned-doubles: SPARC Options. (line 72) +* munaligned-access: ARM Options. (line 313) +* munaligned-doubles: SPARC Options. (line 74) * municode: i386 and x86-64 Windows Options. (line 30) * muninit-const-in-rodata: MIPS Options. (line 396) @@ -50352,8 +51350,9 @@ look up both forms. * munix-asm: PDP-11 Options. (line 68) * munsafe-dma: SPU Options. (line 17) * mupdate: RS/6000 and PowerPC Options. - (line 344) + (line 413) * muser-enabled: LM32 Options. (line 21) +* muser-mode: SPARC Options. (line 86) * musermode: SH Options. (line 230) * mv850: V850 Options. (line 49) * mv850e: V850 Options. (line 79) @@ -50363,30 +51362,30 @@ look up both forms. * mv850e2v4: V850 Options. (line 57) * mv850e3v5: V850 Options. (line 52) * mv850es: V850 Options. (line 75) -* mv8plus: SPARC Options. (line 187) +* mv8plus: SPARC Options. (line 195) * mveclibabi <1>: RS/6000 and PowerPC Options. - (line 766) + (line 847) * mveclibabi: i386 and x86-64 Options. - (line 692) + (line 698) * mvect8-ret-in-mem: i386 and x86-64 Options. - (line 423) -* mvis: SPARC Options. (line 194) -* mvis2: SPARC Options. (line 200) -* mvis3: SPARC Options. (line 208) + (line 429) +* mvis: SPARC Options. (line 202) +* mvis2: SPARC Options. (line 208) +* mvis3: SPARC Options. (line 216) * mvliw-branch: FRV Options. (line 164) * mvms-return-codes: VMS Options. (line 9) * mvolatile-asm-stop: IA-64 Options. (line 32) * mvr4130-align: MIPS Options. (line 663) * mvrsave: RS/6000 and PowerPC Options. - (line 140) + (line 172) * mvsx: RS/6000 and PowerPC Options. - (line 184) + (line 216) * mvxworks: RS/6000 and PowerPC Options. - (line 595) + (line 676) * mvzeroupper: i386 and x86-64 Options. - (line 602) + (line 608) * mwarn-cell-microcode: RS/6000 and PowerPC Options. - (line 146) + (line 178) * mwarn-dynamicstack: S/390 and zSeries Options. (line 150) * mwarn-framesize: S/390 and zSeries Options. @@ -50398,17 +51397,17 @@ look up both forms. (line 35) * mwindows: i386 and x86-64 Windows Options. (line 41) -* mword-relocations: ARM Options. (line 296) +* mword-relocations: ARM Options. (line 300) * mwords-little-endian: ARM Options. (line 66) * mx32: i386 and x86-64 Options. - (line 835) + (line 841) * mxgot <1>: MIPS Options. (line 192) * mxgot: M680x0 Options. (line 319) * mxilinx-fpu: RS/6000 and PowerPC Options. - (line 317) + (line 386) * mxl-barrel-shift: MicroBlaze Options. (line 33) * mxl-compat: RS/6000 and PowerPC Options. - (line 253) + (line 322) * mxl-float-convert: MicroBlaze Options. (line 51) * mxl-float-sqrt: MicroBlaze Options. (line 54) * mxl-gp-opt: MicroBlaze Options. (line 45) @@ -50419,7 +51418,7 @@ look up both forms. * mxl-soft-mul: MicroBlaze Options. (line 27) * mxl-stack-check: MicroBlaze Options. (line 42) * myellowknife: RS/6000 and PowerPC Options. - (line 590) + (line 671) * mzarch: S/390 and zSeries Options. (line 95) * mzda: V850 Options. (line 45) @@ -50500,7 +51499,7 @@ look up both forms. * private_bundle: Darwin Options. (line 196) * pthread <1>: Solaris 2 Options. (line 31) * pthread: RS/6000 and PowerPC Options. - (line 716) + (line 797) * pthreads: Solaris 2 Options. (line 25) * Q: Debugging Options. (line 340) * Qn: System V Options. (line 18) @@ -50587,7 +51586,7 @@ look up both forms. * Wa: Assembler Options. (line 9) * Wabi: C++ Dialect Options. (line 362) -* Waddr-space-convert: AVR Options. (line 217) +* Waddr-space-convert: AVR Options. (line 213) * Waddress: Warning Options. (line 1177) * Waggregate-return: Warning Options. (line 1195) * Waggressive-loop-optimizations: Warning Options. (line 1200) @@ -50992,7 +51991,7 @@ Keyword Index * #pragma implementation, implied: C++ Interface. (line 46) * #pragma interface: C++ Interface. (line 20) * #pragma, reason for not using: Function Attributes. - (line 1870) + (line 1878) * $: Dollar Signs. (line 6) * % in constraint: Modifiers. (line 45) * %include: Spec Files. (line 27) @@ -51010,7 +52009,7 @@ Keyword Index * -nodefaultlibs and unresolved references: Link Options. (line 85) * -nostdlib and unresolved references: Link Options. (line 85) * .sdata/.sdata2 references (PowerPC): RS/6000 and PowerPC Options. - (line 662) + (line 743) * //: C++ Comments. (line 6) * 0 in constraint: Simple Constraints. (line 127) * < in constraint: Simple Constraints. (line 48) @@ -51021,9 +52020,9 @@ Keyword Index * ?: side effect: Conditionals. (line 20) * _ in variables in macros: Typeof. (line 46) * __atomic_add_fetch: __atomic Builtins. (line 169) -* __atomic_always_lock_free: __atomic Builtins. (line 242) +* __atomic_always_lock_free: __atomic Builtins. (line 247) * __atomic_and_fetch: __atomic Builtins. (line 173) -* __atomic_clear: __atomic Builtins. (line 219) +* __atomic_clear: __atomic Builtins. (line 221) * __atomic_compare_exchange: __atomic Builtins. (line 161) * __atomic_compare_exchange_n: __atomic Builtins. (line 138) * __atomic_exchange: __atomic Builtins. (line 130) @@ -51034,17 +52033,17 @@ Keyword Index * __atomic_fetch_or: __atomic Builtins. (line 197) * __atomic_fetch_sub: __atomic Builtins. (line 191) * __atomic_fetch_xor: __atomic Builtins. (line 195) -* __atomic_is_lock_free: __atomic Builtins. (line 256) +* __atomic_is_lock_free: __atomic Builtins. (line 261) * __atomic_load: __atomic Builtins. (line 98) * __atomic_load_n: __atomic Builtins. (line 89) * __atomic_nand_fetch: __atomic Builtins. (line 179) * __atomic_or_fetch: __atomic Builtins. (line 177) -* __atomic_signal_fence: __atomic Builtins. (line 234) +* __atomic_signal_fence: __atomic Builtins. (line 239) * __atomic_store: __atomic Builtins. (line 113) * __atomic_store_n: __atomic Builtins. (line 104) * __atomic_sub_fetch: __atomic Builtins. (line 171) * __atomic_test_and_set: __atomic Builtins. (line 210) -* __atomic_thread_fence: __atomic Builtins. (line 227) +* __atomic_thread_fence: __atomic Builtins. (line 232) * __atomic_xor_fetch: __atomic Builtins. (line 175) * __builtin___clear_cache: Other Builtins. (line 372) * __builtin___fprintf_chk: Object Size Checking. @@ -51146,6 +52145,8 @@ Keyword Index * __builtin_nans: Other Builtins. (line 509) * __builtin_nansf: Other Builtins. (line 513) * __builtin_nansl: Other Builtins. (line 516) +* __builtin_non_tx_store: S/390 System z Built-in Functions. + (line 104) * __builtin_object_size: Object Size Checking. (line 6) * __builtin_offsetof: Offsetof. (line 6) @@ -51205,9 +52206,27 @@ Keyword Index (line 96) * __builtin_set_thread_pointer: SH Built-in Functions. (line 10) +* __builtin_tabort: S/390 System z Built-in Functions. + (line 87) +* __builtin_tbegin: S/390 System z Built-in Functions. + (line 7) +* __builtin_tbegin_nofloat: S/390 System z Built-in Functions. + (line 59) +* __builtin_tbegin_retry: S/390 System z Built-in Functions. + (line 65) +* __builtin_tbegin_retry_nofloat: S/390 System z Built-in Functions. + (line 72) +* __builtin_tbeginc: S/390 System z Built-in Functions. + (line 78) +* __builtin_tend: S/390 System z Built-in Functions. + (line 82) * __builtin_thread_pointer: SH Built-in Functions. (line 20) * __builtin_trap: Other Builtins. (line 281) +* __builtin_tx_assist: S/390 System z Built-in Functions. + (line 92) +* __builtin_tx_nesting_depth: S/390 System z Built-in Functions. + (line 98) * __builtin_types_compatible_p: Other Builtins. (line 111) * __builtin_unreachable: Other Builtins. (line 288) * __builtin_va_arg_pack: Constructing Calls. (line 53) @@ -51274,6 +52293,8 @@ Keyword Index * _exit: Other Builtins. (line 6) * _Exit: Other Builtins. (line 6) * _Fract data type: Fixed-Point. (line 6) +* _HTM_FIRST_USER_ABORT_CODE: S/390 System z Built-in Functions. + (line 48) * _Sat data type: Fixed-Point. (line 6) * _xabort: X86 transactional memory intrinsics. (line 68) @@ -51314,7 +52335,7 @@ Keyword Index * alloca: Other Builtins. (line 6) * alloca vs variable-length arrays: Variable Length. (line 26) * Allow nesting in an interrupt handler on the Blackfin processor.: Function Attributes. - (line 935) + (line 943) * alternate keywords: Alternate Keywords. (line 6) * always_inline function attribute: Function Attributes. (line 91) @@ -51479,9 +52500,9 @@ Keyword Index * code generation conventions: Code Gen Options. (line 6) * code, mixed with declarations: Mixed Declarations. (line 6) * cold function attribute: Function Attributes. - (line 1158) + (line 1166) * cold label attribute: Function Attributes. - (line 1176) + (line 1184) * command options: Invoking GCC. (line 6) * comments, C++ style: C++ Comments. (line 6) * common attribute: Variable Attributes. @@ -51614,7 +52635,7 @@ Keyword Index * earlyclobber operand: Modifiers. (line 25) * eight-bit data on the H8/300, H8/300H, and H8S: Function Attributes. (line 346) -* EIND: AVR Options. (line 224) +* EIND: AVR Options. (line 220) * empty structures: Empty Structures. (line 6) * environment variables: Environment Variables. (line 6) @@ -51692,7 +52713,7 @@ Keyword Index * fmodf: Other Builtins. (line 6) * fmodl: Other Builtins. (line 6) * force_align_arg_pointer attribute: Function Attributes. - (line 1218) + (line 1226) * format function attribute: Function Attributes. (line 419) * format_arg function attribute: Function Attributes. @@ -51724,7 +52745,7 @@ Keyword Index * function versions: Function Multiversioning. (line 6) * function without a prologue/epilogue code: Function Attributes. - (line 912) + (line 920) * function, size of pointer to: Pointer Arith. (line 6) * functions called via pointer on the RS/6000 and PowerPC: Function Attributes. (line 808) @@ -51737,7 +52758,7 @@ Keyword Index * functions that behave like malloc: Function Attributes. (line 6) * functions that do not handle memory bank switching on 68HC11/68HC12: Function Attributes. - (line 925) + (line 933) * functions that do not pop the argument stack on the 386: Function Attributes. (line 6) * functions that do pop the argument stack on the 386: Function Attributes. @@ -51804,9 +52825,11 @@ Keyword Index * hosted environment: Standards. (line 13) * hosted implementation: Standards. (line 13) * hot function attribute: Function Attributes. - (line 1136) + (line 1144) * hot label attribute: Function Attributes. - (line 1148) + (line 1156) +* hotpatch attribute: Function Attributes. + (line 912) * HPPA Options: HPPA Options. (line 6) * HR fixed-suffix: Fixed-Point. (line 6) * hr fixed-suffix: Fixed-Point. (line 6) @@ -51859,7 +52882,7 @@ Keyword Index * interrupt handler functions: Function Attributes. (line 141) * interrupt handler functions on the AVR processors: Function Attributes. - (line 1313) + (line 1321) * interrupt handler functions on the Blackfin, m68k, H8/300 and SH processors: Function Attributes. (line 735) * interrupt service routines on ARM: Function Attributes. @@ -52097,31 +53120,31 @@ Keyword Index * NFC: Warning Options. (line 1284) * NFKC: Warning Options. (line 1284) * NMI handler functions on the Blackfin processor: Function Attributes. - (line 940) + (line 948) * no_instrument_function function attribute: Function Attributes. - (line 946) + (line 954) * no_sanitize_address function attribute: Function Attributes. - (line 1186) + (line 1194) * no_split_stack function attribute: Function Attributes. - (line 951) + (line 959) * noclone function attribute: Function Attributes. - (line 968) + (line 976) * nocommon attribute: Variable Attributes. (line 105) * noinline function attribute: Function Attributes. - (line 957) + (line 965) * nomips16 attribute: Function Attributes. (line 839) * non-constant initializers: Initializers. (line 6) * non-static inline function: Inline. (line 85) * nonnull function attribute: Function Attributes. - (line 974) + (line 982) * noreturn function attribute: Function Attributes. - (line 998) + (line 1006) * nosave_low_regs attribute: Function Attributes. - (line 1048) + (line 1056) * nothrow function attribute: Function Attributes. - (line 1040) + (line 1048) * o in constraint: Simple Constraints. (line 23) * OBJC_INCLUDE_PATH: Environment Variables. (line 132) @@ -52139,7 +53162,7 @@ Keyword Index * OpenMP parallel: C Dialect Options. (line 256) * operand constraints, asm: Constraints. (line 6) * optimize function attribute: Function Attributes. - (line 1054) + (line 1062) * optimize options: Optimize Options. (line 6) * options to control diagnostics formatting: Language Independent Options. (line 6) @@ -52162,9 +53185,9 @@ Keyword Index * order of evaluation, side effects: Non-bugs. (line 196) * order of options: Invoking GCC. (line 30) * OS_main AVR function attribute: Function Attributes. - (line 1071) + (line 1079) * OS_task AVR function attribute: Function Attributes. - (line 1071) + (line 1079) * other register constraints: Simple Constraints. (line 163) * output file option: Overall Options. (line 191) * overloaded virtual function, warning: C++ Dialect Options. @@ -52175,7 +53198,7 @@ Keyword Index * parameter forward declaration: Variable Length. (line 59) * Pascal: G++ and GCC. (line 23) * pcs function attribute: Function Attributes. - (line 1096) + (line 1104) * PDP-11 Options: PDP-11 Options. (line 6) * PIC: Code Gen Options. (line 267) * picoChip options: picoChip Options. (line 6) @@ -52227,7 +53250,7 @@ Keyword Index * pragma, push_macro: Push/Pop Macro Pragmas. (line 11) * pragma, reason for not using: Function Attributes. - (line 1870) + (line 1878) * pragma, redefine_extname: Symbol-Renaming Pragmas. (line 12) * pragma, segment: Darwin Pragmas. (line 21) @@ -52252,7 +53275,7 @@ Keyword Index * promotion of formal parameters: Function Prototypes. (line 6) * pure function attribute: Function Attributes. - (line 1114) + (line 1122) * push address instruction: Simple Constraints. (line 154) * putchar: Other Builtins. (line 6) * puts: Other Builtins. (line 6) @@ -52263,10 +53286,10 @@ Keyword Index * R fixed-suffix: Fixed-Point. (line 6) * r fixed-suffix: Fixed-Point. (line 6) * r in constraint: Simple Constraints. (line 66) -* RAMPD: AVR Options. (line 340) -* RAMPX: AVR Options. (line 340) -* RAMPY: AVR Options. (line 340) -* RAMPZ: AVR Options. (line 340) +* RAMPD: AVR Options. (line 336) +* RAMPX: AVR Options. (line 336) +* RAMPY: AVR Options. (line 336) +* RAMPZ: AVR Options. (line 336) * ranges in case statements: Case Ranges. (line 6) * read-only strings: Incompatibilities. (line 9) * register variable after longjmp: Global Reg Vars. (line 65) @@ -52276,7 +53299,7 @@ Keyword Index * registers, global allocation: Explicit Reg Vars. (line 6) * registers, global variables in: Global Reg Vars. (line 6) * regparm attribute: Function Attributes. - (line 1194) + (line 1202) * relocation truncated to fit (ColdFire): M680x0 Options. (line 329) * relocation truncated to fit (MIPS): MIPS Options. (line 200) * remainder: Other Builtins. (line 6) @@ -52286,12 +53309,12 @@ Keyword Index * remquof: Other Builtins. (line 6) * remquol: Other Builtins. (line 6) * renesas attribute: Function Attributes. - (line 1226) + (line 1234) * reordering, warning: C++ Dialect Options. (line 533) * reporting bugs: Bugs. (line 6) * resbank attribute: Function Attributes. - (line 1230) + (line 1238) * rest argument (in macro): Variadic Macros. (line 6) * restricted pointers: Restricted Pointers. (line 6) @@ -52300,7 +53323,7 @@ Keyword Index * restricted this pointer: Restricted Pointers. (line 6) * returns_twice attribute: Function Attributes. - (line 1244) + (line 1252) * rindex: Other Builtins. (line 6) * rint: Other Builtins. (line 6) * rintf: Other Builtins. (line 6) @@ -52318,9 +53341,9 @@ Keyword Index * S/390 and zSeries Options: S/390 and zSeries Options. (line 6) * save all registers on the Blackfin, H8/300, H8/300H, and H8S: Function Attributes. - (line 1253) + (line 1261) * save volatile registers on the MicroBlaze: Function Attributes. - (line 1258) + (line 1266) * scalb: Other Builtins. (line 6) * scalbf: Other Builtins. (line 6) * scalbl: Other Builtins. (line 6) @@ -52336,11 +53359,11 @@ Keyword Index * Score Options: Score Options. (line 6) * search path: Directory Options. (line 6) * section function attribute: Function Attributes. - (line 1266) + (line 1274) * section variable attribute: Variable Attributes. (line 166) * sentinel function attribute: Function Attributes. - (line 1282) + (line 1290) * setjmp: Global Reg Vars. (line 65) * setjmp incompatibilities: Incompatibilities. (line 39) * shared strings: Incompatibilities. (line 9) @@ -52373,11 +53396,11 @@ Keyword Index * sizeof: Typeof. (line 6) * smaller data references: M32R/D Options. (line 57) * smaller data references (PowerPC): RS/6000 and PowerPC Options. - (line 662) + (line 743) * snprintf: Other Builtins. (line 6) * Solaris 2 options: Solaris 2 Options. (line 6) * sp_switch attribute: Function Attributes. - (line 1331) + (line 1339) * SPARC options: SPARC Options. (line 6) * Spec Files: Spec Files. (line 6) * specified registers: Explicit Reg Vars. (line 6) @@ -52396,7 +53419,7 @@ Keyword Index * sscanf: Other Builtins. (line 6) * sscanf, and constant strings: Incompatibilities. (line 17) * sseregparm attribute: Function Attributes. - (line 1211) + (line 1219) * statements inside expressions: Statement Exprs. (line 6) * static data in C++, declaring and defining: Static Definitions. (line 6) @@ -52423,6 +53446,8 @@ Keyword Index * strspn: Other Builtins. (line 6) * strstr: Other Builtins. (line 6) * struct: Unnamed Fields. (line 6) +* struct __htm_tdb: S/390 System z Built-in Functions. + (line 54) * structures: Incompatibilities. (line 146) * structures, constructor expression: Compound Literals. (line 6) * submodel options: Submodel Options. (line 6) @@ -52436,7 +53461,7 @@ Keyword Index (line 6) * syntax checking: Warning Options. (line 13) * syscall_linkage attribute: Function Attributes. - (line 1346) + (line 1354) * system headers, warnings from: Warning Options. (line 843) * sysv_abi attribute: Function Attributes. (line 881) @@ -52447,111 +53472,111 @@ Keyword Index * tanhl: Other Builtins. (line 6) * tanl: Other Builtins. (line 6) * target function attribute: Function Attributes. - (line 1353) + (line 1361) * target machine, specifying: Target Options. (line 6) * target options: Target Options. (line 6) * target("abm") attribute: Function Attributes. - (line 1379) + (line 1387) * target("aes") attribute: Function Attributes. - (line 1384) + (line 1392) * target("align-stringops") attribute: Function Attributes. - (line 1478) + (line 1486) * target("altivec") attribute: Function Attributes. - (line 1504) + (line 1512) * target("arch=ARCH") attribute: Function Attributes. - (line 1487) + (line 1495) * target("avoid-indexed-addresses") attribute: Function Attributes. - (line 1625) + (line 1633) * target("cld") attribute: Function Attributes. - (line 1449) + (line 1457) * target("cmpb") attribute: Function Attributes. - (line 1510) + (line 1518) * target("cpu=CPU") attribute: Function Attributes. - (line 1640) + (line 1648) * target("default") attribute: Function Attributes. - (line 1387) + (line 1395) * target("dlmzb") attribute: Function Attributes. - (line 1516) + (line 1524) * target("fancy-math-387") attribute: Function Attributes. - (line 1453) + (line 1461) * target("fma4") attribute: Function Attributes. - (line 1433) + (line 1441) * target("fpmath=FPMATH") attribute: Function Attributes. - (line 1495) + (line 1503) * target("fprnd") attribute: Function Attributes. - (line 1523) + (line 1531) * target("friz") attribute: Function Attributes. - (line 1616) + (line 1624) * target("fused-madd") attribute: Function Attributes. - (line 1458) + (line 1466) * target("hard-dfp") attribute: Function Attributes. - (line 1529) + (line 1537) * target("ieee-fp") attribute: Function Attributes. - (line 1463) + (line 1471) * target("inline-all-stringops") attribute: Function Attributes. - (line 1468) + (line 1476) * target("inline-stringops-dynamically") attribute: Function Attributes. - (line 1472) + (line 1480) * target("isel") attribute: Function Attributes. - (line 1535) + (line 1543) * target("longcall") attribute: Function Attributes. - (line 1635) + (line 1643) * target("lwp") attribute: Function Attributes. - (line 1441) + (line 1449) * target("mfcrf") attribute: Function Attributes. - (line 1539) + (line 1547) * target("mfpgpr") attribute: Function Attributes. - (line 1546) + (line 1554) * target("mmx") attribute: Function Attributes. - (line 1392) + (line 1400) * target("mulhw") attribute: Function Attributes. - (line 1553) + (line 1561) * target("multiple") attribute: Function Attributes. - (line 1560) + (line 1568) * target("paired") attribute: Function Attributes. - (line 1630) + (line 1638) * target("pclmul") attribute: Function Attributes. - (line 1396) + (line 1404) * target("popcnt") attribute: Function Attributes. - (line 1400) + (line 1408) * target("popcntb") attribute: Function Attributes. - (line 1571) + (line 1579) * target("popcntd") attribute: Function Attributes. - (line 1578) + (line 1586) * target("powerpc-gfxopt") attribute: Function Attributes. - (line 1584) + (line 1592) * target("powerpc-gpopt") attribute: Function Attributes. - (line 1590) + (line 1598) * target("recip") attribute: Function Attributes. - (line 1482) + (line 1490) * target("recip-precision") attribute: Function Attributes. - (line 1596) + (line 1604) * target("sse") attribute: Function Attributes. - (line 1404) + (line 1412) * target("sse2") attribute: Function Attributes. - (line 1408) + (line 1416) * target("sse3") attribute: Function Attributes. - (line 1412) + (line 1420) * target("sse4") attribute: Function Attributes. - (line 1416) + (line 1424) * target("sse4.1") attribute: Function Attributes. - (line 1421) + (line 1429) * target("sse4.2") attribute: Function Attributes. - (line 1425) + (line 1433) * target("sse4a") attribute: Function Attributes. - (line 1429) + (line 1437) * target("ssse3") attribute: Function Attributes. - (line 1445) + (line 1453) * target("string") attribute: Function Attributes. - (line 1602) + (line 1610) * target("tune=TUNE") attribute: Function Attributes. - (line 1491) + (line 1499) * target("update") attribute: Function Attributes. - (line 1565) + (line 1573) * target("vsx") attribute: Function Attributes. - (line 1608) + (line 1616) * target("xop") attribute: Function Attributes. - (line 1437) + (line 1445) * TC1: Standards. (line 13) * TC2: Standards. (line 13) * TC3: Standards. (line 13) @@ -52570,7 +53595,7 @@ Keyword Index * TILE-Gx options: TILE-Gx Options. (line 6) * TILEPro options: TILEPro Options. (line 6) * tiny data section on the H8/300H and H8S: Function Attributes. - (line 1669) + (line 1677) * TLS: Thread-Local. (line 6) * tls_model attribute: Variable Attributes. (line 235) @@ -52583,9 +53608,9 @@ Keyword Index * towupper: Other Builtins. (line 6) * traditional C language: C Dialect Options. (line 307) * trap_exit attribute: Function Attributes. - (line 1676) + (line 1684) * trapa_handler attribute: Function Attributes. - (line 1681) + (line 1689) * trunc: Other Builtins. (line 6) * truncf: Other Builtins. (line 6) * truncl: Other Builtins. (line 6) @@ -52620,7 +53645,7 @@ Keyword Index * unresolved references and -nodefaultlibs: Link Options. (line 85) * unresolved references and -nostdlib: Link Options. (line 85) * unused attribute.: Function Attributes. - (line 1685) + (line 1693) * UR fixed-suffix: Fixed-Point. (line 6) * ur fixed-suffix: Fixed-Point. (line 6) * use_debug_exception_return attribute: Function Attributes. @@ -52628,7 +53653,7 @@ Keyword Index * use_shadow_register_set attribute: Function Attributes. (line 703) * used attribute.: Function Attributes. - (line 1690) + (line 1698) * User stack pointer in interrupts on the Blackfin: Function Attributes. (line 754) * V in constraint: Simple Constraints. (line 43) @@ -52650,14 +53675,14 @@ Keyword Index * variadic macros: Variadic Macros. (line 6) * VAX options: VAX Options. (line 6) * version_id attribute: Function Attributes. - (line 1700) + (line 1708) * vfprintf: Other Builtins. (line 6) * vfscanf: Other Builtins. (line 6) * visibility attribute: Function Attributes. - (line 1710) + (line 1718) * VLAs: Variable Length. (line 6) * vliw attribute: Function Attributes. - (line 1803) + (line 1811) * void pointers, arithmetic: Pointer Arith. (line 6) * void, size of pointer to: Pointer Arith. (line 6) * volatile access <1>: C++ Volatiles. (line 6) @@ -52678,7 +53703,7 @@ Keyword Index * W floating point suffix: Floating Types. (line 6) * w floating point suffix: Floating Types. (line 6) * warn_unused_result attribute: Function Attributes. - (line 1809) + (line 1817) * warning for comparison of signed and unsigned values: Warning Options. (line 1156) * warning for overloaded virtual function: C++ Dialect Options. @@ -52693,9 +53718,9 @@ Keyword Index * warnings vs errors: Warnings and Errors. (line 6) * weak attribute: Function Attributes. - (line 1826) + (line 1834) * weakref attribute: Function Attributes. - (line 1835) + (line 1843) * whitespace: Incompatibilities. (line 112) * X in constraint: Simple Constraints. (line 124) * X3.159-1989: Standards. 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Options788191 +Node: x86-64 Options789346 +Node: Xstormy16 Options789564 +Node: Xtensa Options789853 +Node: zSeries Options794164 +Node: Code Gen Options794360 +Node: Environment Variables824194 +Node: Precompiled Headers832195 +Node: C Implementation838203 +Node: Translation implementation839872 +Node: Environment implementation840446 +Node: Identifiers implementation840996 +Node: Characters implementation842050 +Node: Integers implementation844856 +Node: Floating point implementation846681 +Node: Arrays and pointers implementation849610 +Ref: Arrays and pointers implementation-Footnote-1851045 +Node: Hints implementation851169 +Node: Structures unions enumerations and bit-fields implementation852635 +Node: Qualifiers implementation854621 +Node: Declarators implementation856393 +Node: Statements implementation856735 +Node: Preprocessing directives implementation857062 +Node: Library functions implementation859167 +Node: Architecture implementation859807 +Node: Locale-specific behavior implementation860510 +Node: C++ Implementation860815 +Node: Conditionally-supported behavior862097 +Node: Exception handling862607 +Node: C Extensions863016 +Node: Statement Exprs868010 +Node: Local Labels872469 +Node: Labels as Values875442 +Ref: Labels as Values-Footnote-1877841 +Node: Nested Functions878024 +Node: Constructing Calls881982 +Node: Typeof886700 +Node: Conditionals890008 +Node: __int128890898 +Node: Long Long891422 +Node: Complex892898 +Node: Floating Types895487 +Node: Half-Precision896615 +Node: Decimal Float898797 +Node: Hex Floats900652 +Node: Fixed-Point901688 +Node: Named Address Spaces904970 +Ref: AVR Named Address Spaces905651 +Node: Zero Length910857 +Node: Empty Structures914144 +Node: Variable Length914550 +Node: Variadic Macros917226 +Node: Escaped Newlines919604 +Node: Subscripting920443 +Node: Pointer Arith921169 +Node: Initializers921737 +Node: Compound Literals922233 +Node: Designated Inits925594 +Node: Case Ranges929226 +Node: Cast to Union929907 +Node: Mixed Declarations930998 +Node: Function Attributes931508 +Node: Attribute Syntax1017836 +Node: Function Prototypes1028227 +Node: C++ Comments1030008 +Node: Dollar Signs1030527 +Node: Character Escapes1030992 +Node: Variable Attributes1031286 +Ref: AVR Variable Attributes1044953 +Ref: MeP Variable Attributes1047614 +Ref: i386 Variable Attributes1049560 +Node: Type Attributes1055224 +Ref: MeP Type Attributes1069112 +Ref: i386 Type Attributes1069386 +Ref: PowerPC Type Attributes1070077 +Ref: SPU Type Attributes1070939 +Node: Alignment1071230 +Node: Inline1072600 +Node: Volatiles1077575 +Node: Extended Asm1080457 +Ref: Example of asm with clobbered asm reg1086361 +Ref: Extended asm with goto1096068 +Node: Constraints1103919 +Node: Simple Constraints1105003 +Node: Multi-Alternative1112324 +Node: Modifiers1114041 +Node: Machine Constraints1117055 +Node: Asm Labels1167278 +Node: Explicit Reg Vars1168954 +Node: Global Reg Vars1170557 +Node: Local Reg Vars1175053 +Node: Alternate Keywords1177470 +Node: Incomplete Enums1178956 +Node: Function Names1179712 +Node: Return Address1181873 +Node: Vector Extensions1185380 +Node: Offsetof1191555 +Node: __sync Builtins1192368 +Node: __atomic Builtins1197838 +Node: x86 specific memory model extensions for transactional memory1209477 +Node: Object Size Checking1210739 +Node: Other Builtins1216228 +Node: Target Builtins1245372 +Node: Alpha Built-in Functions1246611 +Node: ARM iWMMXt Built-in Functions1249620 +Node: ARM NEON Intrinsics1256600 +Node: AVR Built-in Functions1465019 +Node: Blackfin Built-in Functions1468089 +Node: FR-V Built-in Functions1468706 +Node: Argument Types1469565 +Node: Directly-mapped Integer Functions1471317 +Node: Directly-mapped Media Functions1472399 +Node: Raw read/write Functions1479431 +Node: Other Built-in Functions1480343 +Node: X86 Built-in Functions1481527 +Node: X86 transactional memory intrinsics1540495 +Node: MIPS DSP Built-in Functions1543169 +Node: MIPS Paired-Single Support1555677 +Node: MIPS Loongson Built-in Functions1557176 +Node: Paired-Single Arithmetic1563696 +Node: Paired-Single Built-in Functions1564644 +Node: MIPS-3D Built-in Functions1567311 +Node: Other MIPS Built-in Functions1572688 +Node: picoChip Built-in Functions1573212 +Node: PowerPC Built-in Functions1574561 +Node: PowerPC AltiVec/VSX Built-in Functions1578373 +Node: PowerPC Hardware Transactional Memory Built-in Functions1711271 +Node: RX Built-in Functions1717812 +Node: S/390 System z Built-in Functions1721845 +Node: SH Built-in Functions1727082 +Node: SPARC VIS Built-in Functions1728475 +Node: SPU Built-in Functions1734079 +Node: TI C6X Built-in Functions1735895 +Node: TILE-Gx Built-in Functions1736919 +Node: TILEPro Built-in Functions1738036 +Node: Target Format Checks1739103 +Node: Solaris Format Checks1739535 +Node: Darwin Format Checks1739961 +Node: Pragmas1740779 +Node: ARM Pragmas1741489 +Node: M32C Pragmas1742092 +Node: MeP Pragmas1743166 +Node: RS/6000 and PowerPC Pragmas1745235 +Node: Darwin Pragmas1745976 +Node: Solaris Pragmas1747043 +Node: Symbol-Renaming Pragmas1748204 +Node: Structure-Packing Pragmas1749758 +Node: Weak Pragmas1751408 +Node: Diagnostic Pragmas1752142 +Node: Visibility Pragmas1755249 +Node: Push/Pop Macro Pragmas1756001 +Node: Function Specific Option Pragmas1756973 +Node: Unnamed Fields1759230 +Node: Thread-Local1761458 +Node: C99 Thread-Local Edits1763563 +Node: C++98 Thread-Local Edits1765575 +Node: Binary constants1769019 +Node: C++ Extensions1769690 +Node: C++ Volatiles1771401 +Node: Restricted Pointers1773749 +Node: Vague Linkage1775340 +Node: C++ Interface1778964 +Ref: C++ Interface-Footnote-11783250 +Node: Template Instantiation1783386 +Node: Bound member functions1789973 +Node: C++ Attributes1791505 +Node: Function Multiversioning1794161 +Node: Namespace Association1795976 +Node: Type Traits1797356 +Node: Java Exceptions1803844 +Node: Deprecated Features1805234 +Node: Backwards Compatibility1808199 +Node: Objective-C1809551 +Node: GNU Objective-C runtime API1810160 +Node: Modern GNU Objective-C runtime API1811167 +Node: Traditional GNU Objective-C runtime API1813604 +Node: Executing code before main1814332 +Node: What you can and what you cannot do in +load1817070 +Node: Type encoding1819460 +Node: Legacy type encoding1824536 +Node: @encode1825627 +Node: Method signatures1826168 +Node: Garbage Collection1828163 +Node: Constant string objects1830852 +Node: compatibility_alias1833360 +Node: Exceptions1834082 +Node: Synchronization1836793 +Node: Fast enumeration1837977 +Node: Using fast enumeration1838289 +Node: c99-like fast enumeration syntax1839500 +Node: Fast enumeration details1840203 +Node: Fast enumeration protocol1842544 +Node: Messaging with the GNU Objective-C runtime1845696 +Node: Dynamically registering methods1847067 +Node: Forwarding hook1848758 +Node: Compatibility1851798 +Node: Gcov1858365 +Node: Gcov Intro1858898 +Node: Invoking Gcov1861616 +Node: Gcov and Optimization1874527 +Node: Gcov Data Files1877527 +Node: Cross-profiling1878922 +Node: Trouble1880773 +Node: Actual Bugs1882185 +Node: Interoperation1882632 +Node: Incompatibilities1889524 +Node: Fixed Headers1897675 +Node: Standard Libraries1899338 +Node: Disappointments1900710 +Node: C++ Misunderstandings1905068 +Node: Static Definitions1905879 +Node: Name lookup1906932 +Ref: Name lookup-Footnote-11911710 +Node: Temporaries1911897 +Node: Copy Assignment1913873 +Node: Non-bugs1915680 +Node: Warnings and Errors1926187 +Node: Bugs1927949 +Node: Bug Criteria1928513 +Node: Bug Reporting1930723 +Node: Service1930944 +Node: Contributing1931763 +Node: Funding1932503 +Node: GNU Project1934992 +Node: Copying1935638 +Node: GNU Free Documentation License1973166 +Node: Contributors1998303 +Node: Option Index2035705 +Node: Keyword Index2228711 End Tag Table diff --git a/gcc-4.8/gcc/doc/gccinstall.info b/gcc-4.8/gcc/doc/gccinstall.info index 30f065533..9dcfde6f4 100644 --- a/gcc-4.8/gcc/doc/gccinstall.info +++ b/gcc-4.8/gcc/doc/gccinstall.info @@ -1,5 +1,5 @@ -This is doc/gccinstall.info, produced by makeinfo version 4.13 from -/d/gcc-4.8.1/gcc-4.8.1/gcc/doc/install.texi. +This is doc/gccinstall.info, produced by makeinfo version 4.12 from +/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/doc/install.texi. Copyright (C) 1988-2013 Free Software Foundation, Inc. @@ -207,7 +207,7 @@ simplest way to install the libraries. GNU Multiple Precision Library (GMP) version 4.3.2 (or later) Necessary to build GCC. If a GMP source distribution is found in a subdirectory of your GCC sources named `gmp', it will be built - together with GCC. Alternatively, if GMP is already installed but + together with GCC. Alternatively, if GMP is already installed but it is not in your library search path, you will have to configure with the `--with-gmp' configure option. See also `--with-gmp-lib' and `--with-gmp-include'. @@ -561,7 +561,7 @@ option. between cross and native configurations. `--with-specs=SPECS' - Specify additional command line driver SPECS. This can be + Specify additional command line driver SPECS. This can be useful if you need to turn on a non-standard feature by default without modifying the compiler's source code, for instance @@ -1435,13 +1435,13 @@ option. `--with-boot-ldflags=FLAGS' This option may be used to set linker flags to be used when linking - stage 2 and later when bootstrapping GCC. If neither + stage 2 and later when bootstrapping GCC. If neither -with-boot-libs nor -with-host-libstdcxx is set to a value, then the default is `-static-libstdc++ -static-libgcc'. `--with-boot-libs=LIBS' This option may be used to set libraries to be used when linking - stage 2 and later when bootstrapping GCC. The default is the + stage 2 and later when bootstrapping GCC. The default is the argument to `--with-host-libstdcxx', if specified. `--with-debug-prefix-map=MAP' @@ -1730,19 +1730,19 @@ General Options `--with-arch-directory=ARCH' Specifies the name to use for the `jre/lib/ARCH' directory in the - SDK environment created when -enable-java-home is passed. Typical + SDK environment created when -enable-java-home is passed. Typical names for this directory include i386, amd64, ia64, etc. `--with-os-directory=DIR' - Specifies the OS directory for the SDK include directory. This is + Specifies the OS directory for the SDK include directory. This is set to auto detect, and is typically 'linux'. `--with-origin-name=NAME' - Specifies the JPackage origin name. This defaults to the 'gcj' in + Specifies the JPackage origin name. This defaults to the 'gcj' in java-1.5.0-gcj. `--with-arch-suffix=SUFFIX' - Specifies the suffix for the sdk directory. Defaults to the empty + Specifies the suffix for the sdk directory. Defaults to the empty string. Examples include '.x86_64' in 'java-1.5.0-gcj-1.5.0.0.x86_64'. @@ -1750,7 +1750,7 @@ General Options Specifies where to install the SDK. Default is $(prefix)/lib/jvm. `--with-jvm-jar-dir=DIR' - Specifies where to install jars. Default is + Specifies where to install jars. Default is $(prefix)/lib/jvm-exports. `--with-python-dir=DIR' @@ -1758,7 +1758,7 @@ General Options aot-compile. DIR should not include the prefix used in installation. For example, if the Python modules are to be installed in /usr/lib/python2.5/site-packages, then - -with-python-dir=/lib/python2.5/site-packages should be passed. If + -with-python-dir=/lib/python2.5/site-packages should be passed. If this is not specified, then the Python modules are installed in $(prefix)/share/python. @@ -1769,7 +1769,7 @@ General Options Build the gcjwebplugin web browser plugin. `--enable-static-libjava' - Build static libraries in libjava. The default is to only build + Build static libraries in libjava. The default is to only build shared libraries. `ansi' @@ -2161,7 +2161,7 @@ disable building the Ada front end. `ADA_INCLUDE_PATH' and `ADA_OBJECT_PATH' environment variables must not be set when building the Ada compiler, the Ada tools, or the Ada -runtime libraries. You can check that your build environment is clean +runtime libraries. You can check that your build environment is clean by verifying that `gnatls -v' lists only one explicit path in each section. @@ -2628,7 +2628,7 @@ tools can also be obtained from: Blackfin ======== -The Blackfin processor, an Analog Devices DSP. *Note Blackfin Options: +The Blackfin processor, an Analog Devices DSP. *Note Blackfin Options: (gcc)Blackfin Options, More information, and a version of binutils with support for this @@ -2637,7 +2637,7 @@ processor, is available at `http://blackfin.uclinux.org' CR16 ==== -The CR16 CompactRISC architecture is a 16-bit architecture. This +The CR16 CompactRISC architecture is a 16-bit architecture. This architecture is used in embedded applications. *Note CR16 Options: (gcc)CR16 Options, @@ -3056,7 +3056,7 @@ assembler change that sometimes produces corrupt assembly files causing AIX linker errors. The bug breaks GCC bootstrap on AIX and can cause compilation failures with existing GCC installations. An AIX iFix for AIX 5.3 is available (APAR IZ98385 for AIX 5.3 TL10, APAR IZ98477 for -AIX 5.3 TL11 and IZ98134 for AIX 5.3 TL12). AIX 5.3 TL11 SP8, AIX 5.3 +AIX 5.3 TL11 and IZ98134 for AIX 5.3 TL12). AIX 5.3 TL11 SP8, AIX 5.3 TL12 SP5, AIX 6.1 TL04 SP11, AIX 6.1 TL05 SP7, AIX 6.1 TL06 SP6, AIX 6.1 TL07 and AIX 7.1 TL01 should include the fix. @@ -3246,7 +3246,7 @@ use the `--with-divide=breaks' `configure' option when configuring GCC. The default is to use traps on systems that support them. The assembler from GNU binutils 2.17 and earlier has a bug in the way -it sorts relocations for REL targets (o32, o64, EABI). This can cause +it sorts relocations for REL targets (o32, o64, EABI). This can cause bad code to be generated for simple C++ programs. Also the linker from GNU binutils versions prior to 2.17 has a bug which causes the runtime linker stubs in very large programs, like `libgcj.so', to be @@ -3373,7 +3373,7 @@ been removed in GCC 4.6. though you can download the Sun Studio compilers for free. In Solaris 10 and 11, GCC 3.4.3 is available as `/usr/sfw/bin/gcc'. Solaris 11 also provides GCC 4.5.2 as `/usr/gcc/4.5/bin/gcc'. Alternatively, you -can install a pre-built GCC to bootstrap and install GCC. See the +can install a pre-built GCC to bootstrap and install GCC. See the binaries page for details. The Solaris 2 `/bin/sh' will often fail to configure `libstdc++-v3', @@ -3522,7 +3522,7 @@ library or the MPC library on a Solaris 7 or later system, the canonical target triplet must be specified as the `build' parameter on the configure line. This target triplet can be obtained by invoking `./config.guess' in the toplevel source directory of GCC (and not that -of GMP or MPFR or MPC). For example on a Solaris 9 system: +of GMP or MPFR or MPC). For example on a Solaris 9 system: % ./configure --build=sparc-sun-solaris2.9 --prefix=xxx @@ -3530,7 +3530,7 @@ sparc-sun-solaris2.10 ===================== There is a bug in older versions of the Sun assembler which breaks -thread-local storage (TLS). A typical error message is +thread-local storage (TLS). A typical error message is ld: fatal: relocation error: R_SPARC_TLS_LE_HIX22: file /var/tmp//ccamPA1v.o: symbol <unknown>: bad symbol type SECT: symbol type must be TLS @@ -3689,7 +3689,7 @@ and which C libraries are used. * MinGW *-*-mingw32: MinGW is a native GCC port for the Win32 subsystem that provides a subset of POSIX. - * MKS i386-pc-mks: NuTCracker from MKS. See + * MKS i386-pc-mks: NuTCracker from MKS. See `http://www.mkssoftware.com/' for more information. Intel 64-bit versions @@ -3742,7 +3742,7 @@ version 2.20 or above if building your own. =========== The Interix target is used by OpenNT, Interix, Services For UNIX (SFU), -and Subsystem for UNIX-based Applications (SUA). Applications compiled +and Subsystem for UNIX-based Applications (SUA). Applications compiled with this target run in the Interix subsystem, which is separate from the Win32 subsystem. This target was last known to work in GCC 3.3. @@ -4354,7 +4354,7 @@ GNU Free Documentation License not permanently reinstated, receipt of a copy of some or all of the same material does not give you any rights to use it. - 10. FUTURE REVISIONS OF THIS LICENSE + 10. FUTURE REVISIONS OF THIS LICENSE The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new @@ -4375,7 +4375,7 @@ GNU Free Documentation License proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Document. - 11. RELICENSING + 11. RELICENSING "Massive Multiauthor Collaboration Site" (or "MMC Site") means any World Wide Web server that publishes copyrightable works and also @@ -4422,7 +4422,7 @@ notices just after the title page: Free Documentation License''. If you have Invariant Sections, Front-Cover Texts and Back-Cover -Texts, replace the "with...Texts." line with this: +Texts, replace the "with...Texts." line with this: with the Invariant Sections being LIST THEIR TITLES, with the Front-Cover Texts being LIST, and with the Back-Cover Texts @@ -4474,93 +4474,93 @@ Concept Index Tag Table: -Node: Top1733 -Node: Installing GCC2291 -Node: Prerequisites3928 -Node: Downloading the source14255 -Node: Configuration15809 -Ref: with-gnu-as30815 -Ref: with-as31713 -Ref: with-gnu-ld33126 -Node: Building80044 -Node: Testing95529 -Node: Final install103401 -Node: Binaries108715 -Node: Specific110227 -Ref: alpha-x-x110737 -Ref: alpha-dec-osf51111226 -Ref: amd64-x-solaris210111751 -Ref: arm-x-eabi111854 -Ref: avr112065 -Ref: bfin112705 -Ref: cr16112947 -Ref: cris113362 -Ref: dos114178 -Ref: epiphany-x-elf114501 -Ref: x-x-freebsd114606 -Ref: h8300-hms116443 -Ref: hppa-hp-hpux116795 -Ref: hppa-hp-hpux10119166 -Ref: hppa-hp-hpux11119579 -Ref: x-x-linux-gnu125238 -Ref: ix86-x-linux125431 -Ref: ix86-x-solaris29125744 -Ref: ix86-x-solaris210126523 -Ref: ia64-x-linux127714 -Ref: ia64-x-hpux128484 -Ref: x-ibm-aix129039 -Ref: iq2000-x-elf135902 -Ref: lm32-x-elf136042 -Ref: lm32-x-uclinux136146 -Ref: m32c-x-elf136274 -Ref: m32r-x-elf136376 -Ref: m68k-x-x136478 -Ref: m68k-x-uclinux137516 -Ref: mep-x-elf137762 -Ref: microblaze-x-elf137872 -Ref: mips-x-x137991 -Ref: mips-sgi-irix5140387 -Ref: mips-sgi-irix6140467 -Ref: moxie-x-elf140654 -Ref: powerpc-x-x140701 -Ref: powerpc-x-darwin140906 -Ref: powerpc-x-elf141400 -Ref: powerpc-x-linux-gnu141485 -Ref: powerpc-x-netbsd141580 -Ref: powerpc-x-eabisim141668 -Ref: powerpc-x-eabi141794 -Ref: powerpcle-x-elf141870 -Ref: powerpcle-x-eabisim141962 -Ref: powerpcle-x-eabi142095 -Ref: rl78-x-elf142178 -Ref: rx-x-elf142284 -Ref: s390-x-linux142483 -Ref: s390x-x-linux142555 -Ref: s390x-ibm-tpf142642 -Ref: x-x-solaris2142773 -Ref: sparc-x-x147536 -Ref: sparc-sun-solaris2148038 -Ref: sparc-sun-solaris210150792 -Ref: sparc-x-linux151168 -Ref: sparc64-x-solaris2151393 -Ref: sparcv9-x-solaris2152046 -Ref: c6x-x-x152133 -Ref: tilegx-*-linux152224 -Ref: tilepro-*-linux152343 -Ref: x-x-vxworks152464 -Ref: x86-64-x-x153986 -Ref: x86-64-x-solaris210154314 -Ref: xtensa-x-elf154976 -Ref: xtensa-x-linux155647 -Ref: windows155988 -Ref: x-x-cygwin157925 -Ref: x-x-interix158478 -Ref: x-x-mingw32158787 -Ref: older159013 -Ref: elf161130 -Node: Old161388 -Node: Configurations164525 -Node: GNU Free Documentation License168066 -Node: Concept Index193213 +Node: Top1747 +Node: Installing GCC2305 +Node: Prerequisites3942 +Node: Downloading the source14269 +Node: Configuration15823 +Ref: with-gnu-as30829 +Ref: with-as31727 +Ref: with-gnu-ld33140 +Node: Building80058 +Node: Testing95543 +Node: Final install103415 +Node: Binaries108729 +Node: Specific110241 +Ref: alpha-x-x110751 +Ref: alpha-dec-osf51111240 +Ref: amd64-x-solaris210111765 +Ref: arm-x-eabi111868 +Ref: avr112079 +Ref: bfin112719 +Ref: cr16112961 +Ref: cris113376 +Ref: dos114192 +Ref: epiphany-x-elf114515 +Ref: x-x-freebsd114620 +Ref: h8300-hms116457 +Ref: hppa-hp-hpux116809 +Ref: hppa-hp-hpux10119180 +Ref: hppa-hp-hpux11119593 +Ref: x-x-linux-gnu125252 +Ref: ix86-x-linux125445 +Ref: ix86-x-solaris29125758 +Ref: ix86-x-solaris210126537 +Ref: ia64-x-linux127728 +Ref: ia64-x-hpux128498 +Ref: x-ibm-aix129053 +Ref: iq2000-x-elf135916 +Ref: lm32-x-elf136056 +Ref: lm32-x-uclinux136160 +Ref: m32c-x-elf136288 +Ref: m32r-x-elf136390 +Ref: m68k-x-x136492 +Ref: m68k-x-uclinux137530 +Ref: mep-x-elf137776 +Ref: microblaze-x-elf137886 +Ref: mips-x-x138005 +Ref: mips-sgi-irix5140401 +Ref: mips-sgi-irix6140481 +Ref: moxie-x-elf140668 +Ref: powerpc-x-x140715 +Ref: powerpc-x-darwin140920 +Ref: powerpc-x-elf141414 +Ref: powerpc-x-linux-gnu141499 +Ref: powerpc-x-netbsd141594 +Ref: powerpc-x-eabisim141682 +Ref: powerpc-x-eabi141808 +Ref: powerpcle-x-elf141884 +Ref: powerpcle-x-eabisim141976 +Ref: powerpcle-x-eabi142109 +Ref: rl78-x-elf142192 +Ref: rx-x-elf142298 +Ref: s390-x-linux142497 +Ref: s390x-x-linux142569 +Ref: s390x-ibm-tpf142656 +Ref: x-x-solaris2142787 +Ref: sparc-x-x147550 +Ref: sparc-sun-solaris2148052 +Ref: sparc-sun-solaris210150806 +Ref: sparc-x-linux151182 +Ref: sparc64-x-solaris2151407 +Ref: sparcv9-x-solaris2152060 +Ref: c6x-x-x152147 +Ref: tilegx-*-linux152238 +Ref: tilepro-*-linux152357 +Ref: x-x-vxworks152478 +Ref: x86-64-x-x154000 +Ref: x86-64-x-solaris210154328 +Ref: xtensa-x-elf154990 +Ref: xtensa-x-linux155661 +Ref: windows156002 +Ref: x-x-cygwin157939 +Ref: x-x-interix158492 +Ref: x-x-mingw32158801 +Ref: older159027 +Ref: elf161144 +Node: Old161402 +Node: Configurations164539 +Node: GNU Free Documentation License168080 +Node: Concept Index193227 End Tag Table diff --git a/gcc-4.8/gcc/doc/gccint.info b/gcc-4.8/gcc/doc/gccint.info index e41c572a0..83f533215 100644 --- a/gcc-4.8/gcc/doc/gccint.info +++ b/gcc-4.8/gcc/doc/gccint.info @@ -1,5 +1,5 @@ -This is doc/gccint.info, produced by makeinfo version 4.13 from -/d/gcc-4.8.1/gcc-4.8.1/gcc/doc/gccint.texi. +This is doc/gccint.info, produced by makeinfo version 4.12 from +/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/doc/gccint.texi. Copyright (C) 1988-2013 Free Software Foundation, Inc. @@ -57,7 +57,7 @@ Introduction This manual documents the internals of the GNU compilers, including how to port them to new targets and some information about how to write front ends for new languages. It corresponds to the compilers -(GCC) version 4.8.1. The use of the GNU compilers is documented in a +(GCC) version 4.8.3. The use of the GNU compilers is documented in a separate manual. *Note Introduction: (gcc)Top. This manual is mainly a reference manual rather than a tutorial. It @@ -3132,7 +3132,7 @@ that contain parts of GCC and its runtime libraries: The Ada runtime library. `libatomic' - The runtime support library for atomic operations (e.g. for + The runtime support library for atomic operations (e.g. for `__sync' and `__atomic'). `libcpp' @@ -3600,7 +3600,7 @@ languages that are not enabled by default in stage1. For example, `make f951' will build a Fortran compiler even in the stage1 build directory. - ---------- Footnotes ---------- + ---------- Footnotes ---------- (1) Except if the compiler was buggy and miscompiled some of the files that were not modified. In this case, it's best to use `make restrap'. @@ -4935,6 +4935,12 @@ specified for the particular test in an earlier `dg-options' or 7.2.3.8 PowerPC-specific attributes ................................... +`dfp_hw' + PowerPC target supports executing hardware DFP instructions. + +`p8vector_hw' + PowerPC target supports executing VSX instructions (ISA 2.07). + `powerpc64' Test system supports executing 64-bit instructions. @@ -4944,12 +4950,24 @@ specified for the particular test in an earlier `dg-options' or `powerpc_altivec_ok' PowerPC target supports `-maltivec'. +`powerpc_eabi_ok' + PowerPC target supports `-meabi'. + +`powerpc_elfv2' + PowerPC target supports `-mabi=elfv2'. + `powerpc_fprs' PowerPC target supports floating-point registers. `powerpc_hard_double' PowerPC target supports hardware double-precision floating-point. +`powerpc_htm_ok' + PowerPC target supports `-mhtm' + +`powerpc_p8vector_ok' + PowerPC target supports `-mpower8-vector' + `powerpc_ppu_ok' PowerPC target supports `-mcpu=cell'. @@ -4963,10 +4981,6 @@ specified for the particular test in an earlier `dg-options' or `powerpc_spu' PowerPC target supports PowerPC SPU. -`spu_auto_overlay' - SPU target has toolchain that supports automatic overlay - generation. - `powerpc_vsx_ok' PowerPC target supports `-mvsx'. @@ -4974,9 +4988,19 @@ specified for the particular test in an earlier `dg-options' or Including the options used to compile this particular test, the PowerPC target supports PowerPC 405. +`ppc_recip_hw' + PowerPC target supports executing reciprocal estimate instructions. + +`spu_auto_overlay' + SPU target has toolchain that supports automatic overlay + generation. + `vmx_hw' PowerPC target supports executing AltiVec instructions. +`vsx_hw' + PowerPC target supports executing VSX instructions (ISA 2.06). + 7.2.3.9 Other hardware attributes ................................. @@ -5086,8 +5110,8 @@ specified for the particular test in an earlier `dg-options' or non-empty string. `simulator' - Test system runs executables on a simulator (i.e. slowly) rather - than hardware (i.e. fast). + Test system runs executables on a simulator (i.e. slowly) rather + than hardware (i.e. fast). `stdint_types' Target has the basic signed and unsigned C types in `stdint.h'. @@ -6951,7 +6975,7 @@ run after gimplification and what source files they are located in. Range Propagation, J. R. C. Patterson, PLDI '95). In contrast to Patterson's algorithm, this implementation does not propagate branch probabilities nor it uses more than a single range per SSA - name. This means that the current implementation cannot be used + name. This means that the current implementation cannot be used for branch prediction (though adapting it would not be difficult). The pass is located in `tree-vrp.c' and is described by `pass_vrp'. @@ -6971,7 +6995,7 @@ run after gimplification and what source files they are located in. * Control dependence dead code elimination This pass is a stronger form of dead code elimination that can - eliminate unnecessary control flow statements. It is located in + eliminate unnecessary control flow statements. It is located in `tree-ssa-dce.c' and is described by `pass_cd_dce'. * Tail call elimination @@ -7027,7 +7051,7 @@ run after gimplification and what source files they are located in. If a function always returns the same local variable, and that local variable is an aggregate type, then the variable is replaced with the return value for the function (i.e., the function's - DECL_RESULT). This is equivalent to the C++ named return value + DECL_RESULT). This is equivalent to the C++ named return value optimization applied to GIMPLE. The pass is located in `tree-nrv.c' and is described by `pass_nrv'. @@ -8265,10 +8289,10 @@ object of `BITS_PER_UNIT' bits (*note Storage Layout::). "Double Integer" mode represents an eight-byte integer. `TImode' - "Tetra Integer" (?) mode represents a sixteen-byte integer. + "Tetra Integer" (?) mode represents a sixteen-byte integer. `OImode' - "Octa Integer" (?) mode represents a thirty-two-byte integer. + "Octa Integer" (?) mode represents a thirty-two-byte integer. `QFmode' "Quarter-Floating" mode represents a quarter-precision (single @@ -8279,7 +8303,7 @@ object of `BITS_PER_UNIT' bits (*note Storage Layout::). floating point number. `TQFmode' - "Three-Quarter-Floating" (?) mode represents a + "Three-Quarter-Floating" (?) mode represents a three-quarter-precision (three byte) floating point number. `SFmode' @@ -8840,7 +8864,7 @@ registers and to main memory. `subreg's come in two distinct flavors, each having its own usage and rules: - Paradoxical subregs + Paradoxical subregs When M1 is strictly wider than M2, the `subreg' expression is called "paradoxical". The canonical test for this class of `subreg' is: @@ -8885,7 +8909,7 @@ registers and to main memory. bytes to an unknown value assuming `SUBREG_PROMOTED_VAR_P' is false. - Normal subregs + Normal subregs When M1 is at least as narrow as M2 the `subreg' expression is called "normal". @@ -11108,12 +11132,12 @@ case label. Objective-C++ front ends by allowing efficient comparison between two type nodes in `same_type_p': if the `TYPE_CANONICAL' values of the types are equal, the types are equivalent; otherwise, the types - are not equivalent. The notion of equivalence for canonical types + are not equivalent. The notion of equivalence for canonical types is the same as the notion of type equivalence in the language - itself. For instance, + itself. For instance, When `TYPE_CANONICAL' is `NULL_TREE', there is no canonical type - for the given type node. In this case, comparison between this + for the given type node. In this case, comparison between this type and any other type requires the compiler to perform a deep, "structural" comparison to see if the two type nodes have the same form and properties. @@ -11124,7 +11148,7 @@ case label. canonical type. Similarly, `I*' and a typedef `IP' (defined to `I*') will has `int*' as their canonical type. When building a new type node, be sure to set `TYPE_CANONICAL' to the appropriate - canonical type. If the new type is a compound type (built from + canonical type. If the new type is a compound type (built from other types), and any of those other types require structural equality, use `SET_TYPE_STRUCTURAL_EQUALITY' to ensure that the new type also requires structural equality. Finally, if for some @@ -12663,7 +12687,7 @@ clauses used by the OpenMP API `http://www.openmp.org/'. which is implicitly private to each thread. Bounds `N1' and `N2' and the increment expression `INCR' are required to be loop invariant integer expressions that are evaluated without any - synchronization. The evaluation order, frequency of evaluation and + synchronization. The evaluation order, frequency of evaluation and side-effects are unspecified by the standard. `OMP_SECTIONS' @@ -12711,7 +12735,7 @@ clauses used by the OpenMP API `http://www.openmp.org/'. `OMP_RETURN' This does not represent any OpenMP directive, it is an artificial - marker to indicate the end of the body of an OpenMP. It is used by + marker to indicate the end of the body of an OpenMP. It is used by the flow graph (`tree-cfg.c') and OpenMP region building code (`omp-low.c'). @@ -13740,7 +13764,7 @@ at McGill University, though we have made some different choices. For one thing, SIMPLE doesn't support `goto'. Temporaries are introduced to hold intermediate values needed to -compute complex expressions. Additionally, all the control structures +compute complex expressions. Additionally, all the control structures used in GENERIC are lowered into conditional jumps, lexical scopes are removed and exception regions are converted into an on the side exception region tree. @@ -13751,7 +13775,7 @@ tuples out of the original GENERIC expressions. One of the early implementation strategies used for the GIMPLE representation was to use the same internal data structures used by -front ends to represent parse trees. This simplified implementation +front ends to represent parse trees. This simplified implementation because we could leverage existing functionality and interfaces. However, GIMPLE is a much more restrictive representation than abstract syntax trees (AST), therefore it does not require the full structural @@ -13812,14 +13836,14 @@ File: gccint.info, Node: Tuple representation, Next: GIMPLE instruction set, GIMPLE instructions are tuples of variable size divided in two groups: a header describing the instruction and its locations, and a variable -length body with all the operands. Tuples are organized into a +length body with all the operands. Tuples are organized into a hierarchy with 3 main classes of tuples. 12.1.1 `gimple_statement_base' (gsbase) --------------------------------------- This is the root of the hierarchy, it holds basic information needed by -most GIMPLE statements. There are some fields that may not be relevant +most GIMPLE statements. There are some fields that may not be relevant to every GIMPLE statement, but those were moved into the base structure to take advantage of holes left by other fields (thus making the structure more compact). The structure takes 4 words (32 bytes) on 64 @@ -13845,12 +13869,12 @@ Total size 32 bytes * `code' Main identifier for a GIMPLE instruction. * `subcode' Used to distinguish different variants of the same basic - instruction or provide flags applicable to a given code. The + instruction or provide flags applicable to a given code. The `subcode' flags field has different uses depending on the code of the instruction, but mostly it distinguishes instructions of the - same family. The most prominent use of this field is in + same family. The most prominent use of this field is in assignments, where subcode indicates the operation done on the RHS - of the assignment. For example, a = b + c is encoded as + of the assignment. For example, a = b + c is encoded as `GIMPLE_ASSIGN <PLUS_EXPR, a, b, c>'. * `no_warning' Bitflag to indicate whether a warning has already @@ -13865,7 +13889,7 @@ Total size 32 bytes bit holes left by the previous fields. * `plf' Pass Local Flags. This 2-bit mask can be used as general - purpose markers by any pass. Passes are responsible for clearing + purpose markers by any pass. Passes are responsible for clearing and setting these two flags accordingly. * `modified' Bitflag to indicate whether the statement has been @@ -13881,11 +13905,11 @@ Total size 32 bytes memory). * `uid' This is an unsigned integer used by passes that want to - assign IDs to every statement. These IDs must be assigned and used + assign IDs to every statement. These IDs must be assigned and used by each pass. * `location' This is a `location_t' identifier to specify source code - location for this statement. It is inherited from the front end. + location for this statement. It is inherited from the front end. * `num_ops' Number of operands that this statement has. This specifies the size of the operand vector embedded in the tuple. @@ -13902,8 +13926,8 @@ Total size 32 bytes This tuple is actually split in two: `gimple_statement_with_ops_base' and `gimple_statement_with_ops'. This is needed to accommodate the way -the operand vector is allocated. The operand vector is defined to be an -array of 1 element. So, to allocate a dynamic number of operands, the +the operand vector is allocated. The operand vector is defined to be an +array of 1 element. So, to allocate a dynamic number of operands, the memory allocator (`gimple_alloc') simply allocates enough memory to hold the structure itself plus `N - 1' operands which run "off the end" of the structure. For example, to allocate space for a tuple with 3 @@ -13925,7 +13949,7 @@ Total size 48 + 8 * `num_ops' bytes * `def_ops' Array of pointers into the operand array indicating all the slots that contain a variable written-to by the statement. - This array is also used for immediate use chaining. Note that it + This array is also used for immediate use chaining. Note that it would be possible to not rely on this array, but the changes required to implement this are pretty invasive. @@ -13956,11 +13980,11 @@ Field Size (bits) Total size 80 + 8 * `num_ops' bytes * `vdef_ops' Similar to `def_ops' but for `VDEF' operators. There is - one entry per memory symbol written by this statement. This is + one entry per memory symbol written by this statement. This is used to maintain the memory SSA use-def and def-def chains. * `vuse_ops' Similar to `use_ops' but for `VUSE' operators. There is - one entry per memory symbol loaded by this statement. This is used + one entry per memory symbol loaded by this statement. This is used to maintain the memory SSA use-def chains. * `stores' Bitset with all the UIDs for the symbols written-to by the @@ -13974,7 +13998,7 @@ Total size 80 + 8 * `num_ops' bytes memory utilization further by removing these sets). All the other tuples are defined in terms of these three basic ones. -Each tuple will add some fields. The main gimple type is defined to be +Each tuple will add some fields. The main gimple type is defined to be the union of all these structures (`GTY' markers elided for clarity): union gimple_statement_d @@ -14111,9 +14135,9 @@ value is explicitly loaded into a temporary first. Similarly, storing the value of an expression to a memory variable goes through a temporary. - ---------- Footnotes ---------- + ---------- Footnotes ---------- - (1) These restrictions are derived from those in Morgan 4.8. + (1) These restrictions are derived from those in Morgan 4.8. File: gccint.info, Node: Operands, Next: Manipulating GIMPLE statements, Prev: Temporaries, Up: GIMPLE @@ -14190,7 +14214,7 @@ branch assigning to the same temporary. So, a = T1; The GIMPLE level if-conversion pass re-introduces `?:' expression, if -appropriate. It is used to vectorize loops with conditions using vector +appropriate. It is used to vectorize loops with conditions using vector conditional operations. Note that in GIMPLE, `if' statements are represented using @@ -14336,7 +14360,7 @@ exhaustive): -- GIMPLE function: bool is_gimple_ip_invariant (tree t) Return true if t is an interprocedural invariant. This means that - t is a valid invariant in all functions (e.g. it can be an address + t is a valid invariant in all functions (e.g. it can be an address of a global variable but not of a local one). -- GIMPLE function: bool is_gimple_ip_invariant_address (tree t) @@ -14838,7 +14862,7 @@ File: gccint.info, Node: `GIMPLE_CALL', Next: `GIMPLE_CATCH', Prev: `GIMPLE_B -- GIMPLE function: void gimple_call_set_tail (gimple s) Mark call statement `S' as being a tail call (i.e., a call just - before the exit of a function). These calls are candidate for tail + before the exit of a function). These calls are candidate for tail call optimization. -- GIMPLE function: bool gimple_call_tail_p (gimple s) @@ -15219,7 +15243,7 @@ File: gccint.info, Node: `GIMPLE_OMP_FOR', Next: `GIMPLE_OMP_MASTER', Prev: ` gimple_seq pre_body, enum tree_code omp_for_cond) Build a `GIMPLE_OMP_FOR' statement. `BODY' is sequence of statements inside the for loop. `CLAUSES', are any of the `OMP' - loop construct's clauses: private, firstprivate, lastprivate, + loop construct's clauses: private, firstprivate, lastprivate, reductions, ordered, schedule, and nowait. `PRE_BODY' is the sequence of statements that are loop invariant. `INDEX' is the index variable. `INITIAL' is the initial value of `INDEX'. @@ -16454,7 +16478,7 @@ File: gccint.info, Node: SSA, Next: Alias analysis, Prev: SSA Operands, Up: Most of the tree optimizers rely on the data flow information provided by the Static Single Assignment (SSA) form. We implement the SSA form as described in `R. Cytron, J. Ferrante, B. Rosen, M. Wegman, and K. -Zadeck. Efficiently Computing Static Single Assignment Form and the +Zadeck. Efficiently Computing Static Single Assignment Form and the Control Dependence Graph. ACM Transactions on Programming Languages and Systems, 13(4):451-490, October 1991'. @@ -16816,10 +16840,10 @@ disambiguate explicit and implicit memory references. walking statements related to a reference ref. `walk_non_aliased_vuses' walks over dominating memory defining statements and calls back if the statement does not clobber ref - providing the non-aliased VUSE. The walk stops at the first + providing the non-aliased VUSE. The walk stops at the first clobbering statement or if asked to. `walk_aliased_vdefs' walks over dominating memory defining statements and calls back on each - statement clobbering ref providing its aliasing VDEF. The walk + statement clobbering ref providing its aliasing VDEF. The walk stops if asked to. @@ -17133,7 +17157,7 @@ File: gccint.info, Node: LCSSA, Next: Scalar evolutions, Prev: Loop manipulat ========================= Throughout the loop optimizations on tree level, one extra condition is -enforced on the SSA form: No SSA name is used outside of the loop in +enforced on the SSA form: No SSA name is used outside of the loop in that it is defined. The SSA form satisfying this condition is called "loop-closed SSA form" - LCSSA. To enforce LCSSA, PHI nodes must be created at the exits of the loops for the SSA names that are used @@ -17360,9 +17384,9 @@ and mapping this order to the elements of this array avoids costly queries to the loop body representation. Three types of data references are currently handled: ARRAY_REF, -INDIRECT_REF and COMPONENT_REF. The data structure for the data +INDIRECT_REF and COMPONENT_REF. The data structure for the data reference is `data_reference', where `data_reference_p' is a name of a -pointer to the data reference structure. The structure contains the +pointer to the data reference structure. The structure contains the following elements: * `base_object_info': Provides information about the base object of @@ -17377,10 +17401,10 @@ following elements: * `first_location_in_loop': Provides information about the first location accessed by the data reference in the loop and about the access function used to represent evolution relative to this - location. This data is used to support pointers, and is not used - for arrays (for which we have base objects). Pointer accesses are + location. This data is used to support pointers, and is not used + for arrays (for which we have base objects). Pointer accesses are represented as a one-dimensional access that starts from the first - location accessed in the loop. For example: + location accessed in the loop. For example: for1 i for2 j @@ -17461,7 +17485,7 @@ File: gccint.info, Node: Lambda, Next: Omega, Prev: Dependency analysis, Up: Lambda is a framework that allows transformations of loops using non-singular matrix based transformations of the iteration space and -loop bounds. This allows compositions of skewing, scaling, interchange, +loop bounds. This allows compositions of skewing, scaling, interchange, and reversal transformations. These transformations are often used to improve cache behavior or remove inner loop dependencies to allow parallelization and vectorization to take place. @@ -17588,7 +17612,7 @@ all the basic blocks in lexicographical order, except `ENTRY_BLOCK' and lexicographical order, including `ENTRY_BLOCK' and `EXIT_BLOCK'. The functions `post_order_compute' and `inverted_post_order_compute' -can be used to compute topological orders of the CFG. The orders are +can be used to compute topological orders of the CFG. The orders are stored as vectors of basic block indices. The `BASIC_BLOCK' array can be used to iterate each basic block by index. Dominator traversals are also possible using `walk_dominator_tree'. Given two basic blocks A @@ -18019,7 +18043,7 @@ available, including the following: This function inserts a statement before the `gimple_stmt_iterator' passed in. The final parameter determines whether the statement iterator is updated to point to the newly inserted statement, or - left pointing to the original statement. + left pointing to the original statement. `gsi_remove' This function removes the `gimple_stmt_iterator' passed in and @@ -19934,7 +19958,7 @@ _picoChip family--`picochip.h'_ 16-bit signed integer. -_PowerPC and IBM RS6000--`config/rs6000/rs6000.h'_ +_PowerPC and IBM RS6000--`config/rs6000/constraints.md'_ `b' Address base register @@ -19948,17 +19972,64 @@ _PowerPC and IBM RS6000--`config/rs6000/rs6000.h'_ `v' Altivec vector register + `wa' + Any VSX register if the -mvsx option was used or NO_REGS. + `wd' - VSX vector register to hold vector double data + VSX vector register to hold vector double data or NO_REGS. `wf' - VSX vector register to hold vector float data + VSX vector register to hold vector float data or NO_REGS. + + `wg' + If `-mmfpgpr' was used, a floating point register or NO_REGS. + + `wl' + Floating point register if the LFIWAX instruction is enabled + or NO_REGS. + + `wm' + VSX register if direct move instructions are enabled, or + NO_REGS. + + `wn' + No register (NO_REGS). + + `wr' + General purpose register if 64-bit instructions are enabled + or NO_REGS. `ws' - VSX vector register to hold scalar float data + VSX vector register to hold scalar double values or NO_REGS. - `wa' - Any VSX register + `wt' + VSX vector register to hold 128 bit integer or NO_REGS. + + `wu' + Altivec register to use for float/32-bit int loads/stores or + NO_REGS. + + `wv' + Altivec register to use for double loads/stores or NO_REGS. + + `ww' + FP or VSX register to perform float operations under `-mvsx' + or NO_REGS. + + `wx' + Floating point register if the STFIWX instruction is enabled + or NO_REGS. + + `wy' + VSX vector register to hold scalar float values or NO_REGS. + + `wz' + Floating point register if the LFIWZX instruction is enabled + or NO_REGS. + + `wQ' + A memory address that will work with the `lq' and `stq' + instructions. `h' `MQ', `CTR', or `LINK' register @@ -20400,7 +20471,7 @@ _Blackfin family--`config/bfin/constraints.md'_ M register `c' - Registers used for circular buffering, i.e. I, B, or L + Registers used for circular buffering, i.e. I, B, or L registers. `C' @@ -21784,7 +21855,7 @@ in the machine description files: definitions with more than one alternative. Otherwise the insn pattern should be disabled or enabled using the insn condition.) - E.g. the following two patterns could easily be merged using the + E.g. the following two patterns could easily be merged using the `enabled' attribute: @@ -21882,27 +21953,27 @@ constraint matches. expression, obeying the same rules as the RTL expressions in predicate definitions. *Note Defining Predicates::, for details. If it evaluates true, the constraint matches; if it evaluates - false, it doesn't. Constraint expressions should indicate which + false, it doesn't. Constraint expressions should indicate which RTL codes they might match, just like predicate expressions. `match_test' C expressions have access to the following variables: - OP + OP The RTL object defining the operand. - MODE + MODE The machine mode of OP. - IVAL + IVAL `INTVAL (OP)', if OP is a `const_int'. - HVAL + HVAL `CONST_DOUBLE_HIGH (OP)', if OP is an integer `const_double'. - LVAL + LVAL `CONST_DOUBLE_LOW (OP)', if OP is an integer `const_double'. - RVAL + RVAL `CONST_DOUBLE_REAL_VALUE (OP)', if OP is a floating-point `const_double'. @@ -21966,7 +22037,7 @@ that match `const_double's or `const_int's. Each docstring in a constraint definition should be one or more complete sentences, marked up in Texinfo format. _They are currently -unused._ In the future they will be copied into the GCC manual, in +unused._ In the future they will be copied into the GCC manual, in *note Machine Constraints::, replacing the hand-maintained tables currently found in that section. Also, in the future the compiler may use this to give more helpful diagnostics when poor choice of `asm' @@ -22002,7 +22073,7 @@ not contain angle brackets or underscores are left unchanged. Underscores are doubled, each `<' is replaced with `_l', and each `>' with `_g'. Here are some examples: - *Original* *Mangled* + *Original* *Mangled* `x' `x' `P42x' `P42x' `P4_x' `P4__x' @@ -22373,36 +22444,36 @@ pattern to accomplish a certain task. the result. `reduc_smin_M', `reduc_smax_M' - Find the signed minimum/maximum of the elements of a vector. The + Find the signed minimum/maximum of the elements of a vector. The vector is operand 1, and the scalar result is stored in the least - significant bits of operand 0 (also a vector). The output and + significant bits of operand 0 (also a vector). The output and input vector should have the same modes. `reduc_umin_M', `reduc_umax_M' - Find the unsigned minimum/maximum of the elements of a vector. The + Find the unsigned minimum/maximum of the elements of a vector. The vector is operand 1, and the scalar result is stored in the least - significant bits of operand 0 (also a vector). The output and + significant bits of operand 0 (also a vector). The output and input vector should have the same modes. `reduc_splus_M' - Compute the sum of the signed elements of a vector. The vector is + Compute the sum of the signed elements of a vector. The vector is operand 1, and the scalar result is stored in the least significant bits of operand 0 (also a vector). The output and input vector should have the same modes. `reduc_uplus_M' - Compute the sum of the unsigned elements of a vector. The vector + Compute the sum of the unsigned elements of a vector. The vector is operand 1, and the scalar result is stored in the least - significant bits of operand 0 (also a vector). The output and + significant bits of operand 0 (also a vector). The output and input vector should have the same modes. `sdot_prodM' `udot_prodM' Compute the sum of the products of two signed/unsigned elements. - Operand 1 and operand 2 are of the same mode. Their product, which - is of a wider mode, is computed and added to operand 3. Operand 3 - is of a mode equal or wider than the mode of the product. The + Operand 1 and operand 2 are of the same mode. Their product, which + is of a wider mode, is computed and added to operand 3. Operand 3 + is of a mode equal or wider than the mode of the product. The result is placed in operand 0, which is of the same mode as operand 3. @@ -22421,7 +22492,7 @@ pattern to accomplish a certain task. output and input vectors should have the same modes. `vec_pack_trunc_M' - Narrow (demote) and merge the elements of two vectors. Operands 1 + Narrow (demote) and merge the elements of two vectors. Operands 1 and 2 are vectors of the same mode having N integral or floating point elements of size S. Operand 0 is the resulting vector in which 2*N elements of size N/2 are concatenated after narrowing @@ -22452,7 +22523,7 @@ pattern to accomplish a certain task. `vec_unpacku_hi_M', `vec_unpacku_lo_M' Extract and widen (promote) the high/low part of a vector of unsigned integral elements. The input vector (operand 1) has N - elements of size S. Widen (promote) the high/low elements of the + elements of size S. Widen (promote) the high/low elements of the vector using zero extension and place the resulting N/2 values of size 2*S in the output vector (operand 0). @@ -22834,7 +22905,7 @@ pattern to accomplish a certain task. Optional operands 5 and 6 specify expected alignment and size of block respectively. The expected alignment differs from alignment in operand 4 in a way that the blocks are not required to be - aligned according to it in all cases. This expected alignment is + aligned according to it in all cases. This expected alignment is also in bytes, just like operand 4. Expected size, when unknown, is set to `(const_int -1)'. @@ -22859,7 +22930,7 @@ pattern to accomplish a certain task. Block set instruction. The destination string is the first operand, given as a `mem:BLK' whose address is in mode `Pmode'. The number of bytes to set is the second operand, in mode M. The - value to initialize the memory with is the third operand. Targets + value to initialize the memory with is the third operand. Targets that only support the clearing of memory should reject any value that is not the constant 0. See `movmemM' for a discussion of the choice of mode. @@ -22872,7 +22943,7 @@ pattern to accomplish a certain task. Optional operands 5 and 6 specify expected alignment and size of block respectively. The expected alignment differs from alignment in operand 4 in a way that the blocks are not required to be - aligned according to it in all cases. This expected alignment is + aligned according to it in all cases. This expected alignment is also in bytes, just like operand 4. Expected size, when unknown, is set to `(const_int -1)'. @@ -23150,7 +23221,7 @@ pattern to accomplish a certain task. target and branching around an assignment of zero to the target--or a libcall. If the predicate for operand 1 only rejects some operators, it will also try reordering the operands and/or - inverting the result value (e.g. by an exclusive OR). These + inverting the result value (e.g. by an exclusive OR). These possibilities could be cheaper or equivalent to the instructions used for the `cstoreMODE4' pattern followed by those required to convert a positive result from `STORE_FLAG_VALUE' to 1; in this @@ -23845,7 +23916,7 @@ pattern to accomplish a certain task. `atomic_orMODE', `atomic_andMODE' `atomic_xorMODE', `atomic_nandMODE' These patterns emit code for an atomic operation on memory with - memory model semantics. Operand 0 is the memory on which the + memory model semantics. Operand 0 is the memory on which the atomic operation is performed. Operand 1 is the second operand to the binary operator. Operand 2 is the memory model to be used by the operation. @@ -23859,7 +23930,7 @@ pattern to accomplish a certain task. `atomic_fetch_orMODE', `atomic_fetch_andMODE' `atomic_fetch_xorMODE', `atomic_fetch_nandMODE' These patterns emit code for an atomic operation on memory with - memory model semantics, and return the original value. Operand 0 + memory model semantics, and return the original value. Operand 0 is an output operand which contains the value of the memory location before the operation was performed. Operand 1 is the memory on which the atomic operation is performed. Operand 2 is @@ -24057,7 +24128,7 @@ distinct signed and unsigned flavors) as in the x86 or SPARC, and the case where there are distinct signed and unsigned compare instructions and only one set of conditional branch instructions as in the PowerPC. - ---------- Footnotes ---------- + ---------- Footnotes ---------- (1) `note' insns can separate them, though. @@ -24308,7 +24379,7 @@ for RTL generation and it can produce more than one RTL insn. RTL insns directly by calling routines such as `emit_insn', etc. Any such insns precede the ones that come from the RTL template. - * Optionally, a vector containing the values of attributes. *Note + * Optionally, a vector containing the values of attributes. *Note Insn Attributes::. Every RTL insn emitted by a `define_expand' must match some @@ -25023,7 +25094,7 @@ The `enabled' attribute can be used to conditionally enable or disable insn alternatives (*note Disable Insn Alternatives::). The `predicable' attribute, together with a suitable `define_cond_exec' (*note Conditional Execution::), can be used to automatically generate -conditional variants of instruction patterns. The compiler internally +conditional variants of instruction patterns. The compiler internally uses the names `ce_enabled' and `nonce_enabled', so they should not be used elsewhere as alternative names. @@ -25071,12 +25142,12 @@ attributes are not free to use for other purposes: `length' The `length' attribute is used to calculate the length of emitted code chunks. This is especially important when verifying branch - distances. *Note Insn Lengths::. + distances. *Note Insn Lengths::. `enabled' The `enabled' attribute can be defined to prevent certain alternatives of an insn definition from being used during code - generation. *Note Disable Insn Alternatives::. + generation. *Note Disable Insn Alternatives::. For each of these special attributes, the corresponding `HAVE_ATTR_NAME' `#define' is also written when the attribute is not @@ -25181,14 +25252,14 @@ Attribute value expressions must have one of the following forms: The test is true if C expression C-EXPR is true. In non-constant attributes, C-EXPR has access to the following variables: - INSN + INSN The rtl instruction under test. - WHICH_ALTERNATIVE + WHICH_ALTERNATIVE The `define_insn' alternative that INSN matches. *Note Output Statement::. - OPERANDS + OPERANDS An array of INSN's rtl operands. C-EXPR behaves like the condition in a C `if' statement, so there @@ -25589,7 +25660,7 @@ there must be no insn for which tests in two `define_delay' expressions are both true. For example, if we have a machine that requires one delay slot for -branches but two for calls, no delay slot can contain a branch or call +branches but two for calls, no delay slot can contain a branch or call insn, and any valid insn in the delay slot for the branch can be annulled if the branch is true, we might represent this as follows: @@ -26009,9 +26080,9 @@ construction (define_insn_reservation "simple" 2 (eq_attr "type" "int") "(i0_pipeline | i1_pipeline), finish") - ---------- Footnotes ---------- + ---------- Footnotes ---------- - (1) However, the size of the automaton depends on processor + (1) However, the size of the automaton depends on processor complexity. To limit this effect, machine descriptions can split orthogonal parts of the machine description among several automata: but then, since each of these must be stepped independently, this does @@ -26129,7 +26200,7 @@ source RTL template is not matched against the input-template of the `define_subst'. In such case the copy is deleted. `define_subst' can be used only in `define_insn' and `define_expand', -it cannot be used in other expressions (e.g. in +it cannot be used in other expressions (e.g. in `define_insn_and_split'). * Menu: @@ -27306,11 +27377,11 @@ You can control the compilation driver. and the machine suffix. 10. The macro `STANDARD_STARTFILE_PREFIX_1', but only if this is a - native compiler, or we have a target system root. The default for + native compiler, or we have a target system root. The default for this macro is `/lib/'. 11. The macro `STANDARD_STARTFILE_PREFIX_2', but only if this is a - native compiler, or we have a target system root. The default for + native compiler, or we have a target system root. The default for this macro is `/usr/lib/'. @@ -27404,22 +27475,22 @@ Here are run-time target specifications. -- C Target Hook: tree TARGET_OBJC_CONSTRUCT_STRING_OBJECT (tree STRING) Targets may provide a string object type that can be used within - and between C, C++ and their respective Objective-C dialects. A + and between C, C++ and their respective Objective-C dialects. A string object might, for example, embed encoding and length - information. These objects are considered opaque to the compiler - and handled as references. An ideal implementation makes the + information. These objects are considered opaque to the compiler + and handled as references. An ideal implementation makes the composition of the string object match that of the Objective-C `NSString' (`NXString' for GNUStep), allowing efficient - interworking between C-only and Objective-C code. If a target + interworking between C-only and Objective-C code. If a target implements string objects then this hook should return a reference to such an object constructed from the normal `C' string - representation provided in STRING. At present, the hook is used by + representation provided in STRING. At present, the hook is used by Objective-C only, to obtain a common-format string object when the target provides one. -- C Target Hook: void TARGET_OBJC_DECLARE_UNRESOLVED_CLASS_REFERENCE (const char *CLASSNAME) - Declare that Objective C class CLASSNAME is referenced by the + Declare that Objective C class CLASSNAME is referenced by the current TU. -- C Target Hook: void TARGET_OBJC_DECLARE_CLASS_DEFINITION (const @@ -27816,7 +27887,7 @@ expressions that refer to static variables, such as the `target_flags'. -- Target Hook: HOST_WIDE_INT TARGET_VECTOR_ALIGNMENT (const_tree TYPE) This hook can be used to define the alignment for a vector of type - TYPE, in order to comply with a platform ABI. The default is to + TYPE, in order to comply with a platform ABI. The default is to require natural alignment for vector types. The alignment returned by this hook must be a power-of-two multiple of the default alignment of the vector element type. @@ -28469,7 +28540,7 @@ languages, rather than to fundamental aspects of storage layout. By default, the vtable entries are void pointers, the so the alignment is the same as pointer alignment. The value of this macro specifies the alignment of the vtable entry in bits. It - should be defined only when special alignment is necessary. */ + should be defined only when special alignment is necessary. */ -- Macro: TARGET_VTABLE_DATA_ENTRY_DISTANCE There are a few non-descriptor entries in the vtable at offsets @@ -29131,7 +29202,7 @@ return. class to use when it is necessary to rename a register in class RCLASS to another class, or perhaps NO_REGS, if no preferred register class is found or hook `preferred_rename_class' is not - implemented. Sometimes returning a more restrictive class makes + implemented. Sometimes returning a more restrictive class makes better code. For example, on ARM, thumb-2 instructions using `LO_REGS' may be smaller than instructions using `GENERIC_REGS'. By returning `LO_REGS' from `preferred_rename_class', code size @@ -29276,7 +29347,7 @@ return. If copying a register of RELOAD_CLASS from/to X requires an intermediate register, the hook `secondary_reload' should return the register class required for this intermediate register. If no - intermediate register is required, it should return NO_REGS. If + intermediate register is required, it should return NO_REGS. If more than one intermediate register is required, describe the one that is closest in the copy chain to the reload register. @@ -29475,12 +29546,12 @@ return. -- Target Hook: bool TARGET_LRA_P (void) A target hook which returns true if we use LRA instead of reload - pass. It means that LRA was ported to the target. The default + pass. It means that LRA was ported to the target. The default version of this target hook returns always false. -- Target Hook: int TARGET_REGISTER_PRIORITY (int) A target hook which returns the register priority number to which - the register HARD_REGNO belongs to. The bigger the number, the + the register HARD_REGNO belongs to. The bigger the number, the more preferable the hard register usage (when all other conditions are the same). This hook can be used to prefer some hard register over others in LRA. For example, some x86-64 register @@ -30812,7 +30883,7 @@ the stack. **PNAME, tree *PTREE) This target hook is used in function `c_common_nodes_and_builtins' to iterate through the target specific builtin types for va_list. - The variable IDX is used as iterator. PNAME has to be a pointer to + The variable IDX is used as iterator. PNAME has to be a pointer to a `const char *' and PTREE a pointer to a `tree' typed variable. The arguments PNAME and PTREE are used to store the result of this macro and are set to the name of the va_list builtin type and its @@ -30827,7 +30898,7 @@ the stack. -- Target Hook: tree TARGET_CANONICAL_VA_LIST_TYPE (tree TYPE) This hook returns the va_list type of the calling convention - specified by the type of TYPE. If TYPE is not a valid va_list + specified by the type of TYPE. If TYPE is not a valid va_list type, it returns `NULL_TREE'. -- Target Hook: tree TARGET_GIMPLIFY_VA_ARG_EXPR (tree VALIST, tree @@ -32139,7 +32210,7 @@ This is about addressing modes. The autovectorizer, when vectorizing a load operation from an address ADDR that may be unaligned, will generate two vector loads - from the two aligned addresses around ADDR. It then generates a + from the two aligned addresses around ADDR. It then generates a `REALIGN_LOAD' operation to extract the relevant data from the two loaded vectors. The first two arguments to `REALIGN_LOAD', V1 and V2, are the two vectors, each of size VS, and the third argument, @@ -32250,7 +32321,7 @@ TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES (void) -- Target Hook: void TARGET_VECTORIZE_DESTROY_COST_DATA (void *DATA) This hook should release DATA and any related data structures - allocated by TARGET_VECTORIZE_INIT_COST. The default releases the + allocated by TARGET_VECTORIZE_INIT_COST. The default releases the accumulator. -- Target Hook: tree TARGET_VECTORIZE_BUILTIN_TM_LOAD (tree) @@ -32507,7 +32578,7 @@ File: gccint.info, Node: MODE_CC Condition Codes, Next: Cond Exec Macros, Pre are the left and right operands of the comparison, respectively. If OP0_PRESERVE_VALUE is `true' the implementation is not allowed to change the value of OP0 since the value might be used in RTXs - which aren't comparisons. E.g. the implementation is not allowed + which aren't comparisons. E.g. the implementation is not allowed to swap operands in that case. GCC will not assume that the comparison resulting from this macro @@ -32692,7 +32763,7 @@ on the target machine. Parameter SPEED_P is true when the branch in question should be optimized for speed. When it is false, `BRANCH_COST' should return a value optimal for code size rather than performance. - PREDICTABLE_P is true for well-predicted branches. On many + PREDICTABLE_P is true for well-predicted branches. On many architectures the `BRANCH_COST' can be reduced then. Here are additional macros which do not specify precise relative costs, @@ -33520,7 +33591,7 @@ target does not provide them. -- Target Hook: section * TARGET_ASM_TM_CLONE_TABLE_SECTION (void) Return the section that should be used for transactional memory - clone tables. + clone tables. -- Target Hook: section * TARGET_ASM_SELECT_RTX_SECTION (enum machine_mode MODE, rtx X, unsigned HOST_WIDE_INT ALIGN) @@ -36414,7 +36485,7 @@ File: gccint.info, Node: C++ ABI, Next: Named Address Spaces, Prev: PCH Targe in the same manner as `__cxa_atexit' to register C++ static destructors. This requires that `atexit'-registered functions in shared libraries are run in the correct order when the libraries - are unloaded. The default is to return false. + are unloaded. The default is to return false. -- Target Hook: void TARGET_CXX_ADJUST_CLASS_AT_DEFINITION (tree TYPE) TYPE is a C++ class (i.e., RECORD_TYPE or UNION_TYPE) that has @@ -37032,10 +37103,10 @@ Here are several miscellaneous parameters. -- Macro: TARGET_POSIX_IO Define this macro if the target supports the following POSIX file - functions, access, mkdir and file locking with fcntl / F_SETLKW. + functions, access, mkdir and file locking with fcntl / F_SETLKW. Defining `TARGET_POSIX_IO' will enable the test coverage code to use file locking when exiting a program, which avoids race - conditions if the program has forked. It will also create + conditions if the program has forked. It will also create directories at run-time for cross-profiling. -- Macro: MAX_CONDITIONAL_EXECUTE @@ -37186,7 +37257,7 @@ Here are several miscellaneous parameters. low-overhead loop, otherwise return a string explaining why doloop could not be applied. - Many targets use special registers for low-overhead looping. For + Many targets use special registers for low-overhead looping. For any instruction that clobbers these this function should return a string indicating the reason why the doloop could not be applied. By default, the RTL loop optimizer does not use a present doloop @@ -37208,10 +37279,10 @@ Here are several miscellaneous parameters. -- Target Hook: bool TARGET_CAN_FOLLOW_JUMP (const_rtx FOLLOWER, const_rtx FOLLOWEE) - FOLLOWER and FOLLOWEE are JUMP_INSN instructions; return true if - FOLLOWER may be modified to follow FOLLOWEE; false, if it can't. + FOLLOWER and FOLLOWEE are JUMP_INSN instructions; return true if + FOLLOWER may be modified to follow FOLLOWEE; false, if it can't. For example, on some targets, certain kinds of branches can't be - made to follow through a hot/cold partitioning. + made to follow through a hot/cold partitioning. -- Target Hook: bool TARGET_COMMUTATIVE_P (const_rtx X, int OUTER_CODE) This target hook returns `true' if X is considered to be @@ -37340,9 +37411,9 @@ Here are several miscellaneous parameters. -- Target Hook: unsigned TARGET_LOOP_UNROLL_ADJUST (unsigned NUNROLL, struct loop *LOOP) This target hook returns a new value for the number of times LOOP - should be unrolled. The parameter NUNROLL is the number of times - the loop is to be unrolled. The parameter LOOP is a pointer to the - loop, which is going to be checked for unrolling. This target hook + should be unrolled. The parameter NUNROLL is the number of times + the loop is to be unrolled. The parameter LOOP is a pointer to the + loop, which is going to be checked for unrolling. This target hook is required only when the target has special constraints like maximum number of memory accesses. @@ -37474,13 +37545,13 @@ Here are several miscellaneous parameters. -- Macro: TARGET_USE_JCR_SECTION This macro determines whether to use the JCR section to register - Java classes. By default, TARGET_USE_JCR_SECTION is defined to 1 + Java classes. By default, TARGET_USE_JCR_SECTION is defined to 1 if both SUPPORTS_WEAK and TARGET_HAVE_NAMED_SECTIONS are true, else 0. -- Macro: OBJC_JBLEN This macro determines the size of the objective C jump buffer for - the NeXT runtime. By default, OBJC_JBLEN is defined to an + the NeXT runtime. By default, OBJC_JBLEN is defined to an innocuous value. -- Macro: LIBGCC2_UNWIND_ATTRIBUTE @@ -37516,7 +37587,7 @@ Here are several miscellaneous parameters. synthesize a constant. If there is another constant already in a register that is close enough in value then it is preferable that the new constant is computed from this register using immediate - addition or subtraction. We accomplish this through CSE. Besides + addition or subtraction. We accomplish this through CSE. Besides the value of the constant we also add a lower and an upper constant anchor to the available expressions. These are then queried when encountering new constants. The anchors are computed @@ -37535,7 +37606,7 @@ Here are several miscellaneous parameters. -- Target Hook: unsigned HOST_WIDE_INT TARGET_MEMMODEL_CHECK (unsigned HOST_WIDE_INT VAL) - Validate target specific memory model mask bits. When NULL no + Validate target specific memory model mask bits. When NULL no target specific memory model bits are allowed. -- Target Hook: unsigned char TARGET_ATOMIC_TEST_AND_SET_TRUEVAL @@ -38600,7 +38671,7 @@ In these snippets, there is only one type `T', but there could be more. gt_pch_nx (&(tp->fld), op, cookie); } - Support for user-defined types is currently limited. The following + Support for user-defined types is currently limited. The following restrictions apply: 1. Type `TP' and all the argument types `T' must be marked with `GTY'. @@ -38697,9 +38768,9 @@ File: gccint.info, Node: Invoking the garbage collector, Next: Troubleshooting 22.5 How to invoke the garbage collector ======================================== -The GCC garbage collector GGC is only invoked explicitly. In contrast +The GCC garbage collector GGC is only invoked explicitly. In contrast with many other garbage collectors, it is not implicitly invoked by -allocation routines when a lot of memory has been consumed. So the only +allocation routines when a lot of memory has been consumed. So the only way to have GGC reclaim storage is to call the `ggc_collect' function explicitly. This call is an expensive operation, as it may have to scan the entire heap. Beware that local variables (on the GCC call @@ -38830,7 +38901,7 @@ this is enough: ---------------------------- Every plugin should export a function called `plugin_init' that is -called right after the plugin is loaded. This function is responsible +called right after the plugin is loaded. This function is responsible for registering all the callbacks required by the plugin and do any other required initialization. @@ -38872,7 +38943,7 @@ following structure: }; The function `plugin_default_version_check' takes two pointers to such -structure and compare them field by field. It can be used by the +structure and compare them field by field. It can be used by the plugin's `plugin_init' function. The version of GCC used to compile the plugin can be found in the @@ -38977,12 +39048,12 @@ File: gccint.info, Node: Plugins pass, Next: Plugins GC, Prev: Plugin API, U 23.3 Interacting with the pass manager ====================================== -There needs to be a way to add/reorder/remove passes dynamically. This +There needs to be a way to add/reorder/remove passes dynamically. This is useful for both analysis plugins (plugging in after a certain pass such as CFG or an IPA pass) and optimization plugins. Basic support for inserting new passes or replacing existing passes is -provided. A plugin registers a new pass with GCC by calling +provided. A plugin registers a new pass with GCC by calling `register_callback' with the `PLUGIN_PASS_MANAGER_SETUP' event and a pointer to a `struct register_pass_info' object defined as follows @@ -39031,19 +39102,19 @@ File: gccint.info, Node: Plugins GC, Next: Plugins description, Prev: Plugins =============================================== Some plugins may want to be informed when GGC (the GCC Garbage -Collector) is running. They can register callbacks for the +Collector) is running. They can register callbacks for the `PLUGIN_GGC_START' and `PLUGIN_GGC_END' events (for which the callback is called with a null `gcc_data') to be notified of the start or end of the GCC garbage collection. - Some plugins may need to have GGC mark additional data. This can be + Some plugins may need to have GGC mark additional data. This can be done by registering a callback (called with a null `gcc_data') for the `PLUGIN_GGC_MARKING' event. Such callbacks can call the `ggc_set_mark' routine, preferably through the `ggc_mark' macro (and conversely, these routines should usually not be used in plugins outside of the `PLUGIN_GGC_MARKING' event). - Some plugins may need to add extra GGC root tables, e.g. to handle + Some plugins may need to add extra GGC root tables, e.g. to handle their own `GTY'-ed data. This can be done with the `PLUGIN_REGISTER_GGC_ROOTS' pseudo-event with a null callback and the extra root table (of type `struct ggc_root_tab*') as `user_data'. @@ -39064,7 +39135,7 @@ File: gccint.info, Node: Plugins description, Next: Plugins attr, Prev: Plugi 23.5 Giving information about a plugin ====================================== -A plugin should give some information to the user about itself. This +A plugin should give some information to the user about itself. This uses the following structure: struct plugin_info @@ -39390,7 +39461,7 @@ dealing with the reading/writing of each section are described below. * Symbol table (`.gnu.lto_.symtab') This table replaces the ELF symbol table for functions and - variables represented in the LTO IL. Symbols used and exported by + variables represented in the LTO IL. Symbols used and exported by the optimized assembly code of "fat" objects might not match the ones used and exported by the intermediate code. This table is necessary because the intermediate code is less optimized and thus @@ -39716,7 +39787,7 @@ made. The linker plugin obtains the symbol resolution information which specifies which symbols provided by the claimed objects are bound from the rest of a binary being linked. - Currently, the linker plugin works only in combination with the Gold + Currently, the linker plugin works only in combination with the Gold linker, but a GNU ld implementation is under development. GCC is designed to be independent of the rest of the toolchain and @@ -40301,7 +40372,7 @@ TERMS AND CONDITIONS by modifying or propagating a covered work, you indicate your acceptance of this License to do so. - 10. Automatic Licensing of Downstream Recipients. + 10. Automatic Licensing of Downstream Recipients. Each time you convey a covered work, the recipient automatically receives a license from the original licensors, to run, modify and @@ -40329,7 +40400,7 @@ TERMS AND CONDITIONS using, selling, offering for sale, or importing the Program or any portion of it. - 11. Patents. + 11. Patents. A "contributor" is a copyright holder who authorizes use under this License of the Program or a work on which the Program is based. @@ -40402,7 +40473,7 @@ TERMS AND CONDITIONS any implied license or other defenses to infringement that may otherwise be available to you under applicable patent law. - 12. No Surrender of Others' Freedom. + 12. No Surrender of Others' Freedom. If conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this @@ -40416,7 +40487,7 @@ TERMS AND CONDITIONS terms and this License would be to refrain entirely from conveying the Program. - 13. Use with the GNU Affero General Public License. + 13. Use with the GNU Affero General Public License. Notwithstanding any other provision of this License, you have permission to link or combine any covered work with a work licensed @@ -40427,7 +40498,7 @@ TERMS AND CONDITIONS General Public License, section 13, concerning interaction through a network will apply to the combination as such. - 14. Revised Versions of this License. + 14. Revised Versions of this License. The Free Software Foundation may publish revised and/or new versions of the GNU General Public License from time to time. @@ -40454,19 +40525,19 @@ TERMS AND CONDITIONS author or copyright holder as a result of your choosing to follow a later version. - 15. Disclaimer of Warranty. + 15. Disclaimer of Warranty. THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY - APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE + APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. - 16. Limitation of Liability. + 16. Limitation of Liability. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES @@ -40479,7 +40550,7 @@ TERMS AND CONDITIONS PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. - 17. Interpretation of Sections 15 and 16. + 17. Interpretation of Sections 15 and 16. If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, @@ -40952,7 +41023,7 @@ GNU Free Documentation License not permanently reinstated, receipt of a copy of some or all of the same material does not give you any rights to use it. - 10. FUTURE REVISIONS OF THIS LICENSE + 10. FUTURE REVISIONS OF THIS LICENSE The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new @@ -40973,7 +41044,7 @@ GNU Free Documentation License proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Document. - 11. RELICENSING + 11. RELICENSING "Massive Multiauthor Collaboration Site" (or "MMC Site") means any World Wide Web server that publishes copyrightable works and also @@ -41020,7 +41091,7 @@ notices just after the title page: Free Documentation License''. If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts, -replace the "with...Texts." line with this: +replace the "with...Texts." line with this: with the Invariant Sections being LIST THEIR TITLES, with the Front-Cover Texts being LIST, and with the Back-Cover Texts @@ -41980,7 +42051,7 @@ GCC version 4.1: and improvements. * Thomas Fitzsimmons for lots of upgrades to the gtk+ AWT and Cairo - 2D support. Lots of imageio framework additions, lots of AWT and + 2D support. Lots of imageio framework additions, lots of AWT and Free Swing bug fixes. * Jeroen Frijters for `ClassLoader' and nio cleanups, serialization @@ -42015,7 +42086,7 @@ GCC version 4.1: * Ito Kazumitsu for `NetworkInterface' implementation and updates. * Roman Kennke for `BoxLayout', `GrayFilter' and `SplitPane', plus - bug fixes all over. Lots of Free Swing work including styled text. + bug fixes all over. Lots of Free Swing work including styled text. * Simon Kitching for `String' cleanups and optimization suggestions. @@ -49400,373 +49471,373 @@ Concept Index Tag Table: -Node: Top1828 -Node: Contributing4916 -Node: Portability5657 -Node: Interface7445 -Node: Libgcc10485 -Node: Integer library routines12326 -Node: Soft float library routines19168 -Node: Decimal float library routines31105 -Node: Fixed-point fractional library routines46862 -Node: Exception handling routines147260 -Node: Miscellaneous routines148367 -Node: Languages150487 -Node: Source Tree152036 -Node: Configure Terms152618 -Node: Top Level155576 -Node: gcc Directory159150 -Node: Subdirectories160100 -Node: Configuration162267 -Node: Config Fragments162987 -Node: System Config164216 -Node: Configuration Files165152 -Node: Build167977 -Node: Makefile168389 -Ref: Makefile-Footnote-1175192 -Ref: Makefile-Footnote-2175337 -Node: Library Files175409 -Node: Headers175971 -Node: Documentation178054 -Node: Texinfo Manuals178913 -Node: Man Page Generation181246 -Node: Miscellaneous Docs183161 -Node: Front End184555 -Node: Front End Directory188248 -Node: Front End Config189568 -Node: Front End Makefile192394 -Node: Back End196176 -Node: Testsuites199973 -Node: Test Idioms200904 -Node: Test Directives204301 -Node: Directives204828 -Node: Selectors215138 -Node: Effective-Target Keywords216496 -Ref: arm_neon_ok224055 -Ref: arm_neonv2_ok224213 -Ref: arm_neon_fp16_ok224385 -Node: Add Options234186 -Node: Require Support235383 -Node: Final Actions237890 -Node: Ada Tests243057 -Node: C Tests244389 -Node: libgcj Tests248812 -Node: LTO Testing249939 -Node: gcov Testing251586 -Node: profopt Testing254573 -Node: compat Testing256288 -Node: Torture Tests260528 -Node: Options262145 -Node: Option file format262585 -Node: Option properties269575 -Node: Passes282454 -Node: Parsing pass283198 -Node: Gimplification pass286728 -Node: Pass manager288561 -Node: Tree SSA passes290355 -Node: RTL passes312827 -Node: RTL325958 -Node: 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2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GCJ-DBTOOL 1" -.TH GCJ-DBTOOL 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GCJ-DBTOOL 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/gcj.1 b/gcc-4.8/gcc/doc/gcj.1 index 1de730eee..2d7c4e612 100644 --- a/gcc-4.8/gcc/doc/gcj.1 +++ b/gcc-4.8/gcc/doc/gcj.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GCJ 1" -.TH GCJ 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GCJ 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -147,7 +155,7 @@ of the same options as gcc. This manual only documents the options specific to \fBgcj\fR. .SH "OPTIONS" .IX Header "OPTIONS" -.SS "Input and output files" +.Sh "Input and output files" .IX Subsection "Input and output files" A \fBgcj\fR command is like a \fBgcc\fR command, in that it consists of a number of options and file names. The following kinds @@ -195,7 +203,7 @@ but not when using \f(CW\*(C`\-C\*(C'\fR or \f(CW\*(C`\-\-resource\*(C'\fR. (This is an extension beyond the what plain \fBgcc\fR allows.) (If more than one input file is specified, all must currently be \f(CW\*(C`.java\*(C'\fR files, though we hope to fix this.) -.SS "Input Options" +.Sh "Input Options" .IX Subsection "Input Options" \&\fBgcj\fR has options to control where it looks to find files it needs. For instance, \fBgcj\fR might need to load a class that is referenced @@ -269,7 +277,7 @@ issue an error if it isn't found. .IX Item "-fsource=VERSION" This option is used to choose the source version accepted by \&\fBgcj\fR. The default is \fB1.5\fR. -.SS "Encodings" +.Sh "Encodings" .IX Subsection "Encodings" The Java programming language uses Unicode throughout. In an effort to integrate well with other locales, \fBgcj\fR allows \fI.java\fR files @@ -292,7 +300,7 @@ to platform (since they are not standardized anywhere). However, \&\fBgcj\fR implements the encoding named \fB\s-1UTF\-8\s0\fR internally, so if you choose to use this for your source files you can be assured that it will work on every host. -.SS "Warnings" +.Sh "Warnings" .IX Subsection "Warnings" \&\fBgcj\fR implements several warnings. As with other generic \&\fBgcc\fR warnings, if an option of the form \f(CW\*(C`\-Wfoo\*(C'\fR enables a @@ -322,7 +330,7 @@ This is the same as \fBgcc\fR's \f(CW\*(C`\-Wunused\*(C'\fR. .IX Item "-Wall" This is the same as \f(CW\*(C`\-Wredundant\-modifiers \-Wextraneous\-semicolon \&\-Wunused\*(C'\fR. -.SS "Linking" +.Sh "Linking" .IX Subsection "Linking" To turn a Java application into an executable program, you need to link it with the needed libraries, just as for C or \*(C+. @@ -383,7 +391,7 @@ link time, it can omit the referred to classes. The result is usually runtime. Caution must be used when using this option. For more details see: <\fBhttp://gcc.gnu.org/wiki/Statically%20linking%20libgcj\fR> -.SS "Code Generation" +.Sh "Code Generation" .IX Subsection "Code Generation" In addition to the many \fBgcc\fR options controlling code generation, \&\fBgcj\fR has several options specific to itself. @@ -517,7 +525,7 @@ with \f(CW\*(C`\-freduced\-reflection\*(C'\fR. a \f(CW\*(C`SecurityManager\*(C'\fR may not work properly. Also calling \&\f(CW\*(C`Class.forName()\*(C'\fR may fail if the calling method has no reflection meta-data. -.SS "Configure-time Options" +.Sh "Configure-time Options" .IX Subsection "Configure-time Options" Some \fBgcj\fR code generations options affect the resulting \s-1ABI\s0, and so can only be meaningfully given when \f(CW\*(C`libgcj\*(C'\fR, the runtime diff --git a/gcc-4.8/gcc/doc/gcj.info b/gcc-4.8/gcc/doc/gcj.info index 5d089f3f8..a892e6757 100644 --- a/gcc-4.8/gcc/doc/gcj.info +++ b/gcc-4.8/gcc/doc/gcj.info @@ -1,5 +1,5 @@ -This is doc/gcj.info, produced by makeinfo version 4.13 from -/d/gcc-4.8.1/gcc-4.8.1/gcc/java/gcj.texi. +This is doc/gcj.info, produced by makeinfo version 4.12 from +/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/java/gcj.texi. Copyright (C) 2001-2013 Free Software Foundation, Inc. @@ -570,7 +570,7 @@ TERMS AND CONDITIONS by modifying or propagating a covered work, you indicate your acceptance of this License to do so. - 10. Automatic Licensing of Downstream Recipients. + 10. Automatic Licensing of Downstream Recipients. Each time you convey a covered work, the recipient automatically receives a license from the original licensors, to run, modify and @@ -598,7 +598,7 @@ TERMS AND CONDITIONS using, selling, offering for sale, or importing the Program or any portion of it. - 11. Patents. + 11. Patents. A "contributor" is a copyright holder who authorizes use under this License of the Program or a work on which the Program is based. @@ -671,7 +671,7 @@ TERMS AND CONDITIONS any implied license or other defenses to infringement that may otherwise be available to you under applicable patent law. - 12. No Surrender of Others' Freedom. + 12. No Surrender of Others' Freedom. If conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this @@ -685,7 +685,7 @@ TERMS AND CONDITIONS terms and this License would be to refrain entirely from conveying the Program. - 13. Use with the GNU Affero General Public License. + 13. Use with the GNU Affero General Public License. Notwithstanding any other provision of this License, you have permission to link or combine any covered work with a work licensed @@ -696,7 +696,7 @@ TERMS AND CONDITIONS General Public License, section 13, concerning interaction through a network will apply to the combination as such. - 14. Revised Versions of this License. + 14. Revised Versions of this License. The Free Software Foundation may publish revised and/or new versions of the GNU General Public License from time to time. @@ -723,19 +723,19 @@ TERMS AND CONDITIONS author or copyright holder as a result of your choosing to follow a later version. - 15. Disclaimer of Warranty. + 15. Disclaimer of Warranty. THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY - APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE + APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. - 16. Limitation of Liability. + 16. Limitation of Liability. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES @@ -748,7 +748,7 @@ TERMS AND CONDITIONS PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. - 17. Interpretation of Sections 15 and 16. + 17. Interpretation of Sections 15 and 16. If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, @@ -1221,7 +1221,7 @@ GNU Free Documentation License not permanently reinstated, receipt of a copy of some or all of the same material does not give you any rights to use it. - 10. FUTURE REVISIONS OF THIS LICENSE + 10. FUTURE REVISIONS OF THIS LICENSE The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new @@ -1242,7 +1242,7 @@ GNU Free Documentation License proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Document. - 11. RELICENSING + 11. RELICENSING "Massive Multiauthor Collaboration Site" (or "MMC Site") means any World Wide Web server that publishes copyrightable works and also @@ -1289,7 +1289,7 @@ notices just after the title page: Free Documentation License''. If you have Invariant Sections, Front-Cover Texts and Back-Cover -Texts, replace the "with...Texts." line with this: +Texts, replace the "with...Texts." line with this: with the Invariant Sections being LIST THEIR TITLES, with the Front-Cover Texts being LIST, and with the Back-Cover Texts @@ -1679,7 +1679,7 @@ In addition to the many `gcc' options controlling code generation, Note that, at present, `-findirect-dispatch' can only be used when compiling `.class' files. It will not work when compiling from source. CNI also does not yet work with the binary compatibility - ABI. These restrictions will be lifted in some future release. + ABI. These restrictions will be lifted in some future release. However, if you compile CNI code with the standard ABI, you can call it from code built with the binary compatibility ABI. @@ -1701,7 +1701,7 @@ In addition to the many `gcc' options controlling code generation, environment. When set all meta-data except for that which is needed to obtain correct runtime semantics is eliminated. - For code that does not use reflection (i.e. serialization, RMI, + For code that does not use reflection (i.e. serialization, RMI, CORBA or call methods in the `java.lang.reflect' package), `-freduced-reflection' will result in proper operation with a savings in executable code size. @@ -1773,8 +1773,8 @@ against us. So, there are caveats to using `gcj'. * Menu: -* Limitations:: -* Extensions:: +* Limitations:: +* Extensions:: File: gcj.info, Node: Limitations, Next: Extensions, Up: Compatibility @@ -1866,7 +1866,7 @@ have been added are to facilitate this functionality. particular `GCJ_PROPERTIES' holds a list of assignments to global properties, such as would be set with the `-D' option to `java'. For instance, `java.compiler=gcj' is a valid (but currently - meaningless) setting. + meaningless) setting. @@ -1959,7 +1959,7 @@ been compiled and put into a shared library on the class path. Equivalent to `-Xmx'. `-noverify' - Do not verify compliance of bytecode with the VM specification. In + Do not verify compliance of bytecode with the VM specification. In addition, this option disables type verification which is otherwise performed on BC-ABI compiled code. @@ -2492,7 +2492,7 @@ C++ pointer, so for instance a Java `java.lang.String' becomes, in C++, Every Java class or interface has a corresponding `Class' instance. These can be accessed in CNI via the static `class$' field of a class. The `class$' field is of type `Class' (and not `Class *'), so you will -typically take the address of it. +typically take the address of it. Here is how you can refer to the class of `String', which in Java would be written `String.class': @@ -3139,13 +3139,13 @@ File: gcj.info, Node: Invocation, Next: Reflection, Prev: Synchronization, U ================ CNI permits C++ applications to make calls into Java classes, in -addition to allowing Java code to call into C++. Several functions, +addition to allowing Java code to call into C++. Several functions, known as the "invocation API", are provided to support this. -- Function: jint JvCreateJavaVM (JvVMInitArgs* VM_ARGS) - Initializes the Java runtime. This function performs essential + Initializes the Java runtime. This function performs essential initialization of the threads interface, garbage collector, - exception handling and other key aspects of the runtime. It must + exception handling and other key aspects of the runtime. It must be called once by an application with a non-Java `main()' function, before any other Java or CNI calls are made. It is safe, but not recommended, to call `JvCreateJavaVM()' more than @@ -3200,9 +3200,9 @@ known as the "invocation API", are provided to support this. thread object is returned. -- Function: jint JvDetachCurrentThread () - Unregisters a thread from the Java runtime. This should be called + Unregisters a thread from the Java runtime. This should be called by threads that were attached using `JvAttachCurrentThread()', - after they have finished making calls to Java code. This ensures + after they have finished making calls to Java code. This ensures that any resources associated with the thread become eligible for garbage collection. This function returns `0' upon success, or `-1' if the current thread is not attached. @@ -3212,7 +3212,7 @@ known as the "invocation API", are provided to support this. If an exception is thrown from Java code called using the invocation API, and no handler for the exception can be found, the runtime will -abort the application. In order to make the application more robust, it +abort the application. In order to make the application more robust, it is recommended that code which uses the invocation API be wrapped by a top-level try/catch block that catches all Java exceptions. @@ -3506,7 +3506,7 @@ normally not be found in other core libraries for the java language. `java.net.PlainDatagramSocketImpl'. `gnu.gcj.progname' - The class or binary name that was used to invoke the program. This + The class or binary name that was used to invoke the program. This will be the name of the "main" class in the case where the `gij' front end is used, or the program binary name in the case where an application is compiled to a native binary. @@ -3519,7 +3519,7 @@ normally not be found in other core libraries for the java language. `gnu.gcj.runtime.NameFinder.use_addr2line' Whether an external process, `addr2line', should be used to - determine line number information when tracing the stack. Setting + determine line number information when tracing the stack. Setting this to `false' may suppress line numbers when printing stack traces and when using the java.util.logging infrastructure. However, performance may improve significantly for applications @@ -3641,51 +3641,51 @@ Index Tag Table: -Node: Top2715 -Node: Copying4134 -Node: GNU Free Documentation License41684 -Node: Invoking gcj66827 -Node: Input and output files67590 -Node: Input Options69116 -Node: Encodings72390 -Node: Warnings73596 -Node: Linking74709 -Node: Code Generation77648 -Node: Configure-time Options84428 -Node: Compatibility86168 -Node: Limitations86652 -Node: Extensions88234 -Node: Invoking jcf-dump91328 -Node: Invoking gij92273 -Node: Invoking gcj-dbtool95524 -Node: Invoking jv-convert97990 -Node: Invoking grmic99069 -Node: Invoking gc-analyze100455 -Node: Invoking aot-compile101896 -Node: Invoking rebuild-gcj-db102845 -Node: About CNI103155 -Node: Basic concepts104614 -Node: Packages107510 -Node: Primitive types109838 -Node: Reference types111516 -Node: Interfaces112605 -Node: Objects and Classes113516 -Node: Class Initialization115711 -Node: Object allocation118053 -Node: Memory allocation118843 -Node: Arrays119475 -Node: Methods122285 -Node: Strings125106 -Node: Mixing with C++126610 -Node: Exception Handling130081 -Node: Synchronization131715 -Node: Invocation133705 -Node: Reflection138641 -Node: System properties139102 -Node: Standard Properties139979 -Node: GNU Classpath Properties144411 -Node: libgcj Runtime Properties145458 -Node: Resources149960 -Node: Index150774 +Node: Top2729 +Node: Copying4148 +Node: GNU Free Documentation License41698 +Node: Invoking gcj66841 +Node: Input and output files67604 +Node: Input Options69130 +Node: Encodings72404 +Node: Warnings73610 +Node: Linking74723 +Node: Code Generation77662 +Node: Configure-time Options84442 +Node: Compatibility86182 +Node: Limitations86666 +Node: Extensions88248 +Node: Invoking jcf-dump91342 +Node: Invoking gij92287 +Node: Invoking gcj-dbtool95538 +Node: Invoking jv-convert98004 +Node: Invoking grmic99083 +Node: Invoking gc-analyze100469 +Node: Invoking aot-compile101910 +Node: Invoking rebuild-gcj-db102859 +Node: About CNI103169 +Node: Basic concepts104628 +Node: Packages107524 +Node: Primitive types109852 +Node: Reference types111530 +Node: Interfaces112619 +Node: Objects and Classes113530 +Node: Class Initialization115725 +Node: Object allocation118067 +Node: Memory allocation118857 +Node: Arrays119489 +Node: Methods122299 +Node: Strings125120 +Node: Mixing with C++126624 +Node: Exception Handling130095 +Node: Synchronization131729 +Node: Invocation133719 +Node: Reflection138655 +Node: System properties139116 +Node: Standard Properties139993 +Node: GNU Classpath Properties144425 +Node: libgcj Runtime Properties145472 +Node: Resources149974 +Node: Index150788 End Tag Table diff --git a/gcc-4.8/gcc/doc/gcov.1 b/gcc-4.8/gcc/doc/gcov.1 index 145b71a34..27cb28aaf 100644 --- a/gcc-4.8/gcc/doc/gcov.1 +++ b/gcc-4.8/gcc/doc/gcov.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GCOV 1" -.TH GCOV 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GCOV 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -579,7 +587,7 @@ profiling code first attempts to read in an existing \fI.gcda\fR file; if the file doesn't match the executable (differing number of basic block counts) it will ignore the contents of the file. It then adds in the new execution counts and finally writes the data to the file. -.SS "Using \fBgcov\fP with \s-1GCC\s0 Optimization" +.Sh "Using \fBgcov\fP with \s-1GCC\s0 Optimization" .IX Subsection "Using gcov with GCC Optimization" If you plan to use \fBgcov\fR to help optimize your code, you must first compile your program with two special \s-1GCC\s0 options: diff --git a/gcc-4.8/gcc/doc/gfdl.7 b/gcc-4.8/gcc/doc/gfdl.7 index 46f4005fd..dc99bad35 100644 --- a/gcc-4.8/gcc/doc/gfdl.7 +++ b/gcc-4.8/gcc/doc/gfdl.7 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GFDL 7" -.TH GFDL 7 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GFDL 7 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -133,9 +141,9 @@ gfdl \- GNU Free Documentation License .SH "DESCRIPTION" .IX Header "DESCRIPTION" -.SS "\s-1GNU\s0 Free Documentation License" +.Sh "\s-1GNU\s0 Free Documentation License" .IX Subsection "GNU Free Documentation License" -.SS "Version 1.3, 3 November 2008" +.Sh "Version 1.3, 3 November 2008" .IX Subsection "Version 1.3, 3 November 2008" .Vb 2 \& Copyright (c) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. @@ -592,7 +600,7 @@ and (2) were thus incorporated prior to November 1, 2008. The operator of an \s-1MMC\s0 Site may republish an \s-1MMC\s0 contained in the site under CC-BY-SA on the same site at any time before August 1, 2009, provided the \s-1MMC\s0 is eligible for relicensing. -.SS "\s-1ADDENDUM:\s0 How to use this License for your documents" +.Sh "\s-1ADDENDUM:\s0 How to use this License for your documents" .IX Subsection "ADDENDUM: How to use this License for your documents" To use this License in a document you have written, include a copy of the License in the document and put the following copyright and diff --git a/gcc-4.8/gcc/doc/gfortran.1 b/gcc-4.8/gcc/doc/gfortran.1 index acaf61f9f..eff1ba070 100644 --- a/gcc-4.8/gcc/doc/gfortran.1 +++ b/gcc-4.8/gcc/doc/gfortran.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GFORTRAN 1" -.TH GFORTRAN 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GFORTRAN 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -224,7 +232,7 @@ by type. Explanations are in the following sections. \&\-fno\-automatic \-fno\-protect\-parens \-fno\-underscoring \-fno\-whole\-file \&\-fsecond\-underscore \-fpack\-derived \-frealloc\-lhs \-frecursive \&\-frepack\-arrays \-fshort\-enums \-fstack\-arrays\fR -.SS "Options controlling Fortran dialect" +.Sh "Options controlling Fortran dialect" .IX Subsection "Options controlling Fortran dialect" The following options control the details of the Fortran dialect accepted by the compiler: @@ -406,7 +414,7 @@ that are permitted but obsolescent in later standards. \fB\-std=f2008ts\fR allows the Fortran 2008 standard including the additions of the Technical Specification (\s-1TS\s0) 29113 on Further Interoperability of Fortran with C. -.SS "Enable and customize preprocessing" +.Sh "Enable and customize preprocessing" .IX Subsection "Enable and customize preprocessing" Preprocessor related options. See section \&\fBPreprocessing and conditional compilation\fR for more detailed @@ -594,7 +602,7 @@ by the linemarkers. .IX Item "-Uname" Cancel any previous definition of \fIname\fR, either built in or provided with a \fB\-D\fR option. -.SS "Options to request or suppress errors and warnings" +.Sh "Options to request or suppress errors and warnings" .IX Subsection "Options to request or suppress errors and warnings" Errors are diagnostic messages that report that the \s-1GNU\s0 Fortran compiler cannot compile the relevant piece of source code. The compiler will @@ -825,7 +833,7 @@ target. This option is implied by \fB\-Wall\fR. Turns all warnings into errors. .PP Some of these have no effect when compiling programs written in Fortran. -.SS "Options for debugging your program or \s-1GNU\s0 Fortran" +.Sh "Options for debugging your program or \s-1GNU\s0 Fortran" .IX Subsection "Options for debugging your program or GNU Fortran" \&\s-1GNU\s0 Fortran has various special options that are used for debugging either your program or the \s-1GNU\s0 Fortran compiler. @@ -834,11 +842,12 @@ either your program or the \s-1GNU\s0 Fortran compiler. Output the internal parse tree after translating the source program into internal representation. Only really useful for debugging the \&\s-1GNU\s0 Fortran compiler itself. -.IP "\fB\-fdump\-optimized\-tree\fR" 4 -.IX Item "-fdump-optimized-tree" +.IP "\fB\-fdump\-fortran\-optimized\fR" 4 +.IX Item "-fdump-fortran-optimized" Output the parse tree after front-end optimization. Only really useful for debugging the \s-1GNU\s0 Fortran compiler itself. -.Sp +.IP "\fB\-fdump\-parse\-tree\fR" 4 +.IX Item "-fdump-parse-tree" Output the internal parse tree after translating the source program into internal representation. Only really useful for debugging the \&\s-1GNU\s0 Fortran compiler itself. This option is deprecated; use @@ -879,7 +888,7 @@ action \fBcore\fR), the Fortran runtime library tries to output a backtrace of the error. \f(CW\*(C`\-fno\-backtrace\*(C'\fR disables the backtrace generation. This option only has influence for compilation of the Fortran main program. -.SS "Options for directory search" +.Sh "Options for directory search" .IX Subsection "Options for directory search" These options affect how \s-1GNU\s0 Fortran searches for files specified by the \f(CW\*(C`INCLUDE\*(C'\fR directive and where it searches @@ -911,7 +920,7 @@ The default is the current directory. .IX Item "-fintrinsic-modules-path dir" This option specifies the location of pre-compiled intrinsic modules, if they are not in the default location expected by the compiler. -.SS "Influencing the linking step" +.Sh "Influencing the linking step" .IX Subsection "Influencing the linking step" These options come into play when the compiler links object files into an executable output file. They are meaningless if the compiler is not doing @@ -922,7 +931,7 @@ On systems that provide \fIlibgfortran\fR as a shared and a static library, this option forces the use of the static version. If no shared version of \fIlibgfortran\fR was built when the compiler was configured, this option has no effect. -.SS "Influencing runtime behavior" +.Sh "Influencing runtime behavior" .IX Subsection "Influencing runtime behavior" These options affect the runtime behavior of programs compiled with \s-1GNU\s0 Fortran. .IP "\fB\-fconvert=\fR\fIconversion\fR" 4 @@ -957,7 +966,7 @@ negative in the \f(CW\*(C`SIGN\*(C'\fR intrinsic. \fB\-fno\-sign\-zero\fR does print the negative sign of zero values (or values rounded to zero for I/O) and regards zero as positive number in the \f(CW\*(C`SIGN\*(C'\fR intrinsic for compatibility with Fortran 77. The default is \fB\-fsign\-zero\fR. -.SS "Options for code generation conventions" +.Sh "Options for code generation conventions" .IX Subsection "Options for code generation conventions" These machine-independent options control the interface conventions used in code generation. diff --git a/gcc-4.8/gcc/doc/gij.1 b/gcc-4.8/gcc/doc/gij.1 index b9f753ea5..df2a7dc00 100644 --- a/gcc-4.8/gcc/doc/gij.1 +++ b/gcc-4.8/gcc/doc/gij.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GIJ 1" -.TH GIJ 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GIJ 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/gpl.7 b/gcc-4.8/gcc/doc/gpl.7 index 30cfa1c71..324dbb93a 100644 --- a/gcc-4.8/gcc/doc/gpl.7 +++ b/gcc-4.8/gcc/doc/gpl.7 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GPL 7" -.TH GPL 7 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GPL 7 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -133,9 +141,9 @@ gpl \- GNU General Public License .SH "DESCRIPTION" .IX Header "DESCRIPTION" -.SS "\s-1GNU\s0 General Public License" +.Sh "\s-1GNU\s0 General Public License" .IX Subsection "GNU General Public License" -.SS "Version 3, 29 June 2007" +.Sh "Version 3, 29 June 2007" .IX Subsection "Version 3, 29 June 2007" .Vb 1 \& Copyright (c) 2007 Free Software Foundation, Inc. <http://fsf.org/> @@ -143,7 +151,7 @@ gpl \- GNU General Public License \& Everyone is permitted to copy and distribute verbatim copies of this \& license document, but changing it is not allowed. .Ve -.SS "Preamble" +.Sh "Preamble" .IX Subsection "Preamble" The \s-1GNU\s0 General Public License is a free, copyleft license for software and other kinds of works. @@ -207,7 +215,7 @@ assures that patents cannot be used to render the program non-free. .PP The precise terms and conditions for copying, distribution and modification follow. -.SS "\s-1TERMS\s0 \s-1AND\s0 \s-1CONDITIONS\s0" +.Sh "\s-1TERMS\s0 \s-1AND\s0 \s-1CONDITIONS\s0" .IX Subsection "TERMS AND CONDITIONS" .IP "0. Definitions." 4 .IX Item "0. Definitions." @@ -770,9 +778,9 @@ reviewing courts shall apply local law that most closely approximates an absolute waiver of all civil liability in connection with the Program, unless a warranty or assumption of liability accompanies a copy of the Program in return for a fee. -.SS "\s-1END\s0 \s-1OF\s0 \s-1TERMS\s0 \s-1AND\s0 \s-1CONDITIONS\s0" +.Sh "\s-1END\s0 \s-1OF\s0 \s-1TERMS\s0 \s-1AND\s0 \s-1CONDITIONS\s0" .IX Subsection "END OF TERMS AND CONDITIONS" -.SS "How to Apply These Terms to Your New Programs" +.Sh "How to Apply These Terms to Your New Programs" .IX Subsection "How to Apply These Terms to Your New Programs" If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it diff --git a/gcc-4.8/gcc/doc/grmic.1 b/gcc-4.8/gcc/doc/grmic.1 index 8c29a7604..517d51ad8 100644 --- a/gcc-4.8/gcc/doc/grmic.1 +++ b/gcc-4.8/gcc/doc/grmic.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GRMIC 1" -.TH GRMIC 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GRMIC 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/invoke.texi b/gcc-4.8/gcc/doc/invoke.texi index cb0d50ec7..a09553ccf 100644 --- a/gcc-4.8/gcc/doc/invoke.texi +++ b/gcc-4.8/gcc/doc/invoke.texi @@ -161,7 +161,7 @@ in the following sections. -pipe -pass-exit-codes @gol -x @var{language} -v -### --help@r{[}=@var{class}@r{[},@dots{}@r{]]} --target-help @gol --version -wrapper @@@var{file} -fplugin=@var{file} -fplugin-arg-@var{name}=@var{arg} @gol --fdump-ada-spec@r{[}-slim@r{]} -fada-spec-parent=@var{arg} -fdump-go-spec=@var{file}} +-fdump-ada-spec@r{[}-slim@r{]} -fada-spec-parent=@var{unit} -fdump-go-spec=@var{file}} @item C Language Options @xref{C Dialect Options,,Options Controlling C Dialect}. @@ -857,7 +857,12 @@ See RS/6000 and PowerPC Options. -mno-recip-precision @gol -mveclibabi=@var{type} -mfriz -mno-friz @gol -mpointers-to-nested-functions -mno-pointers-to-nested-functions @gol --msave-toc-indirect -mno-save-toc-indirect} +-msave-toc-indirect -mno-save-toc-indirect @gol +-mpower8-fusion -mno-mpower8-fusion -mpower8-vector -mno-power8-vector @gol +-mcrypto -mno-crypto -mdirect-move -mno-direct-move @gol +-mquad-memory -mno-quad-memory @gol +-mquad-memory-atomic -mno-quad-memory-atomic @gol +-mcompat-align-parm -mno-compat-align-parm} @emph{RX Options} @gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol @@ -881,7 +886,8 @@ See RS/6000 and PowerPC Options. -msmall-exec -mno-small-exec -mmvcle -mno-mvcle @gol -m64 -m31 -mdebug -mno-debug -mesa -mzarch @gol -mtpf-trace -mno-tpf-trace -mfused-madd -mno-fused-madd @gol --mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard} +-mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard @gol +-mhotpatch[=@var{halfwords}] -mno-hotpatch} @emph{Score Options} @gccoptlist{-meb -mel @gol @@ -926,11 +932,12 @@ See RS/6000 and PowerPC Options. -mhard-quad-float -msoft-quad-float @gol -mstack-bias -mno-stack-bias @gol -munaligned-doubles -mno-unaligned-doubles @gol +-muser-mode -mno-user-mode @gol -mv8plus -mno-v8plus -mvis -mno-vis @gol -mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol -mcbcond -mno-cbcond @gol -mfmaf -mno-fmaf -mpopc -mno-popc @gol --mfix-at697f} +-mfix-at697f -mfix-ut699} @emph{SPU Options} @gccoptlist{-mwarn-reloc -merror-reloc @gol @@ -1462,11 +1469,18 @@ Define an argument called @var{key} with a value of @var{value} for the plugin called @var{name}. @item -fdump-ada-spec@r{[}-slim@r{]} -For C and C++ source and include files, generate corresponding Ada -specs. @xref{Generating Ada Bindings for C and C++ headers,,, gnat_ugn, +@opindex fdump-ada-spec +For C and C++ source and include files, generate corresponding Ada specs. +@xref{Generating Ada Bindings for C and C++ headers,,, gnat_ugn, GNAT User's Guide}, which provides detailed documentation on this feature. +@item -fada-spec-parent=@var{unit} +@opindex fada-spec-parent +In conjunction with @option{-fdump-ada-spec@r{[}-slim@r{]}} above, generate +Ada specs as child units of parent @var{unit}. + @item -fdump-go-spec=@var{file} +@opindex fdump-go-spec For input files in any language, generate corresponding Go declarations in @var{file}. This generates Go @code{const}, @code{type}, @code{var}, and @code{func} declarations which may be a @@ -11317,11 +11331,32 @@ option should only be used if you require compatibility with code for big-endian ARM processors generated by versions of the compiler prior to 2.8. This option is now deprecated. -@item -mcpu=@var{name} -@opindex mcpu -This specifies the name of the target ARM processor. GCC uses this name -to determine what kind of instructions it can emit when generating -assembly code. Permissible names are: @samp{arm2}, @samp{arm250}, +@item -march=@var{name} +@opindex march +This specifies the name of the target ARM architecture. GCC uses this +name to determine what kind of instructions it can emit when generating +assembly code. This option can be used in conjunction with or instead +of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, +@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t}, +@samp{armv5}, @samp{armv5t}, @samp{armv5e}, @samp{armv5te}, +@samp{armv6}, @samp{armv6j}, +@samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, @samp{armv6-m}, +@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, @samp{armv7e-m} +@samp{armv8-a}, +@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. + +@option{-march=native} causes the compiler to auto-detect the architecture +of the build computer. At present, this feature is only supported on +Linux, and not all architectures are recognized. If the auto-detect is +unsuccessful the option has no effect. + +@item -mtune=@var{name} +@opindex mtune +This option specifies the name of the target ARM processor for +which GCC should tune the performance of the code. +For some ARM implementations better performance can be obtained by using +this option. +Permissible names are: @samp{arm2}, @samp{arm250}, @samp{arm3}, @samp{arm6}, @samp{arm60}, @samp{arm600}, @samp{arm610}, @samp{arm620}, @samp{arm7}, @samp{arm7m}, @samp{arm7d}, @samp{arm7dm}, @samp{arm7di}, @samp{arm7dmi}, @samp{arm70}, @samp{arm700}, @@ -11349,27 +11384,6 @@ assembly code. Permissible names are: @samp{arm2}, @samp{arm250}, @samp{fa526}, @samp{fa626}, @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}. - -@option{-mcpu=generic-@var{arch}} is also permissible, and is -equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}. -See @option{-mtune} for more information. - -@option{-mcpu=native} causes the compiler to auto-detect the CPU -of the build computer. At present, this feature is only supported on -Linux, and not all architectures are recognized. If the auto-detect is -unsuccessful the option has no effect. - -@item -mtune=@var{name} -@opindex mtune -This option is very similar to the @option{-mcpu=} option, except that -instead of specifying the actual target processor type, and hence -restricting which instructions can be used, it specifies that GCC should -tune the performance of the code as if the target were of the type -specified in this option, but still choosing the instructions it -generates based on the CPU specified by a @option{-mcpu=} option. -For some ARM implementations better performance can be obtained by using -this option. - @option{-mtune=generic-@var{arch}} specifies that GCC should tune the performance for a blend of processors within architecture @var{arch}. The aim is to generate code that run well on the current most popular @@ -11382,21 +11396,23 @@ of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. -@item -march=@var{name} -@opindex march -This specifies the name of the target ARM architecture. GCC uses this -name to determine what kind of instructions it can emit when generating -assembly code. This option can be used in conjunction with or instead -of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, -@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t}, -@samp{armv5}, @samp{armv5t}, @samp{armv5e}, @samp{armv5te}, -@samp{armv6}, @samp{armv6j}, -@samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, @samp{armv6-m}, -@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, -@samp{armv8-a}, -@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. +@item -mcpu=@var{name} +@opindex mcpu +This specifies the name of the target ARM processor. GCC uses this name +to derive the name of the target ARM architecture (as if specified +by @option{-march}) and the ARM processor type for which to tune for +performance (as if specified by @option{-mtune}). Where this option +is used in conjunction with @option{-march} or @option{-mtune}, +those options take precedence over the appropriate part of this option. -@option{-march=native} causes the compiler to auto-detect the architecture +Permissible names for this option are the same as those for +@option{-mtune}. + +@option{-mcpu=generic-@var{arch}} is also permissible, and is +equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}. +See @option{-mtune} for more information. + +@option{-mcpu=native} causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. @@ -11485,8 +11501,11 @@ before execution begins. @item -mpic-register=@var{reg} @opindex mpic-register -Specify the register to be used for PIC addressing. The default is R10 -unless stack-checking is enabled, when R9 is used. +Specify the register to be used for PIC addressing. +For standard PIC base case, the default will be any suitable register +determined by compiler. For single PIC base case, the default is +@samp{R9} if target is EABI based or stack-checking is enabled, +otherwise the default is @samp{R10}. @item -mpoke-function-name @opindex mpoke-function-name @@ -17313,7 +17332,9 @@ following options: @gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol -mpopcntb -mpopcntd -mpowerpc64 @gol -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol --msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx} +-msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx @gol +-mcrypto -mdirect-move -mpower8-fusion -mpower8-vector @gol +-mquad-memory -mquad-memory-atomic} The particular options set for any particular CPU varies between compiler versions, depending on what setting seems to produce optimal @@ -17364,6 +17385,38 @@ the AltiVec instruction set. You may also need to set @option{-mabi=altivec} to adjust the current ABI with AltiVec ABI enhancements. +When @option{-maltivec} is used, rather than @option{-maltivec=le} or +@option{-maltivec=be}, the element order for Altivec intrinsics such +as @code{vec_splat}, @code{vec_extract}, and @code{vec_insert} will +match array element order corresponding to the endianness of the +target. That is, element zero identifies the leftmost element in a +vector register when targeting a big-endian platform, and identifies +the rightmost element in a vector register when targeting a +little-endian platform. + +@item -maltivec=be +@opindex maltivec=be +Generate Altivec instructions using big-endian element order, +regardless of whether the target is big- or little-endian. This is +the default when targeting a big-endian platform. + +The element order is used to interpret element numbers in Altivec +intrinsics such as @code{vec_splat}, @code{vec_extract}, and +@code{vec_insert}. By default, these will match array element order +corresponding to the endianness for the target. + +@item -maltivec=le +@opindex maltivec=le +Generate Altivec instructions using little-endian element order, +regardless of whether the target is big- or little-endian. This is +the default when targeting a little-endian platform. This option is +currently ignored when targeting a big-endian platform. + +The element order is used to interpret element numbers in Altivec +intrinsics such as @code{vec_splat}, @code{vec_extract}, and +@code{vec_insert}. By default, these will match array element order +corresponding to the endianness for the target. + @item -mvrsave @itemx -mno-vrsave @opindex mvrsave @@ -17431,6 +17484,55 @@ Generate code that uses (does not use) vector/scalar (VSX) instructions, and also enable the use of built-in functions that allow more direct access to the VSX instruction set. +@item -mcrypto +@itemx -mno-crypto +@opindex mcrypto +@opindex mno-crypto +Enable the use (disable) of the built-in functions that allow direct +access to the cryptographic instructions that were added in version +2.07 of the PowerPC ISA. + +@item -mdirect-move +@itemx -mno-direct-move +@opindex mdirect-move +@opindex mno-direct-move +Generate code that uses (does not use) the instructions to move data +between the general purpose registers and the vector/scalar (VSX) +registers that were added in version 2.07 of the PowerPC ISA. + +@item -mpower8-fusion +@itemx -mno-power8-fusion +@opindex mpower8-fusion +@opindex mno-power8-fusion +Generate code that keeps (does not keeps) some integer operations +adjacent so that the instructions can be fused together on power8 and +later processors. + +@item -mpower8-vector +@itemx -mno-power8-vector +@opindex mpower8-vector +@opindex mno-power8-vector +Generate code that uses (does not use) the vector and scalar +instructions that were added in version 2.07 of the PowerPC ISA. Also +enable the use of built-in functions that allow more direct access to +the vector instructions. + +@item -mquad-memory +@itemx -mno-quad-memory +@opindex mquad-memory +@opindex mno-quad-memory +Generate code that uses (does not use) the non-atomic quad word memory +instructions. The @option{-mquad-memory} option requires use of +64-bit mode. + +@item -mquad-memory-atomic +@itemx -mno-quad-memory-atomic +@opindex mquad-memory-atomic +@opindex mno-quad-memory-atomic +Generate code that uses (does not use) the atomic quad word memory +instructions. The @option{-mquad-memory-atomic} option requires use of +64-bit mode. + @item -mfloat-gprs=@var{yes/single/double/no} @itemx -mfloat-gprs @opindex mfloat-gprs @@ -17850,7 +17952,8 @@ SVR4 ABI)@. @opindex mabi Extend the current ABI with a particular extension, or remove such extension. Valid values are @var{altivec}, @var{no-altivec}, @var{spe}, -@var{no-spe}, @var{ibmlongdouble}, @var{ieeelongdouble}@. +@var{no-spe}, @var{ibmlongdouble}, @var{ieeelongdouble}, +@var{elfv1}, @var{elfv2}@. @item -mabi=spe @opindex mabi=spe @@ -17872,6 +17975,20 @@ This is a PowerPC 32-bit SYSV ABI option. Change the current ABI to use IEEE extended-precision long double. This is a PowerPC 32-bit Linux ABI option. +@item -mabi=elfv1 +@opindex mabi=elfv1 +Change the current ABI to use the ELFv1 ABI. +This is the default ABI for big-endian PowerPC 64-bit Linux. +Overriding the default ABI requires special system support and is +likely to fail in spectacular ways. + +@item -mabi=elfv2 +@opindex mabi=elfv2 +Change the current ABI to use the ELFv2 ABI. +This is the default ABI for little-endian PowerPC 64-bit Linux. +Overriding the default ABI requires special system support and is +likely to fail in spectacular ways. + @item -mprototype @itemx -mno-prototype @opindex mprototype @@ -18157,6 +18274,23 @@ stack location in the function prologue if the function calls through a pointer on AIX and 64-bit Linux systems. If the TOC value is not saved in the prologue, it is saved just before the call through the pointer. The @option{-mno-save-toc-indirect} option is the default. + +@item -mcompat-align-parm +@itemx -mno-compat-align-parm +@opindex mcompat-align-parm +Generate (do not generate) code to pass structure parameters with a +maximum alignment of 64 bits, for compatibility with older versions +of GCC. + +Older versions of GCC (prior to 4.9.0) incorrectly did not align a +structure parameter on a 128-bit boundary when that structure contained +a member requiring 128-bit alignment. This is corrected in more +recent versions of GCC. This option may be used to generate code +that is compatible with functions compiled with older versions of +GCC. + +In this version of the compiler, the @option{-mcompat-align-parm} +is the default, except when using the Linux ELFv2 ABI. @end table @node RX Options @@ -18536,6 +18670,21 @@ values have to be exact powers of 2 and @var{stack-size} has to be greater than In order to be efficient the extra code makes the assumption that the stack starts at an address aligned to the value given by @var{stack-size}. The @var{stack-guard} option can only be used in conjunction with @var{stack-size}. + +@item -mhotpatch[=@var{halfwords}] +@itemx -mno-hotpatch +@opindex mhotpatch +If the hotpatch option is enabled, a ``hot-patching'' function +prologue is generated for all functions in the compilation unit. +The funtion label is prepended with the given number of two-byte +Nop instructions (@var{halfwords}, maximum 1000000) or 12 Nop +instructions if no argument is present. Functions with a +hot-patching prologue are never inlined automatically, and a +hot-patching prologue is never generated for functions functions +that are explicitly inline. + +This option can be overridden for individual functions with the +@code{hotpatch} attribute. @end table @node Score Options @@ -19126,8 +19275,9 @@ These @samp{-m} options are supported on the SPARC: @opindex mno-app-regs @opindex mapp-regs Specify @option{-mapp-regs} to generate output using the global registers -2 through 4, which the SPARC SVR4 ABI reserves for applications. This -is the default. +2 through 4, which the SPARC SVR4 ABI reserves for applications. Like the +global register 1, each global register 2 through 4 is then treated as an +allocable register that is clobbered by function calls. This is the default. To be fully SVR4 ABI-compliant at the cost of some performance loss, specify @option{-mno-app-regs}. You should compile libraries and system @@ -19202,6 +19352,14 @@ Specifying this option avoids some rare compatibility problems with code generated by other compilers. It is not the default because it results in a performance loss, especially for floating-point code. +@item -muser-mode +@itemx -mno-user-mode +@opindex muser-mode +@opindex mno-user-mode +Do not generate code that can only run in supervisor mode. This is relevant +only for the @code{casa} instruction emitted for the LEON3 processor. The +default is @option{-mno-user-mode}. + @item -mno-faster-structs @itemx -mfaster-structs @opindex mno-faster-structs @@ -19220,10 +19378,10 @@ the rules of the ABI@. Set the instruction set, register set, and instruction scheduling parameters for machine type @var{cpu_type}. Supported values for @var{cpu_type} are @samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{hypersparc}, -@samp{leon}, @samp{sparclite}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, -@samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, -@samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, @samp{niagara3}, -and @samp{niagara4}. +@samp{leon}, @samp{leon3}, @samp{sparclite}, @samp{f930}, @samp{f934}, +@samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9}, +@samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, +@samp{niagara3} and @samp{niagara4}. Native Solaris and GNU/Linux toolchains also support the value @samp{native}, which selects the best architecture option for the host processor. @@ -19242,7 +19400,7 @@ implementations. cypress @item v8 -supersparc, hypersparc, leon +supersparc, hypersparc, leon, leon3 @item sparclite f930, f934, sparclite86x @@ -19304,10 +19462,11 @@ option @option{-mcpu=@var{cpu_type}} does. The same values for @option{-mcpu=@var{cpu_type}} can be used for @option{-mtune=@var{cpu_type}}, but the only useful values are those that select a particular CPU implementation. Those are @samp{cypress}, -@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{f930}, @samp{f934}, -@samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, @samp{ultrasparc3}, -@samp{niagara}, @samp{niagara2}, @samp{niagara3} and @samp{niagara4}. With -native Solaris and GNU/Linux toolchains, @samp{native} can also be used. +@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{leon3}, @samp{f930}, +@samp{f934}, @samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, +@samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, @samp{niagara3} and +@samp{niagara4}. With native Solaris and GNU/Linux toolchains, @samp{native} +can also be used. @item -mv8plus @itemx -mno-v8plus @@ -19376,6 +19535,11 @@ later. @opindex mfix-at697f Enable the documented workaround for the single erratum of the Atmel AT697F processor (which corresponds to erratum #13 of the AT697E processor). + +@item -mfix-ut699 +@opindex mfix-ut699 +Enable the documented workarounds for the floating-point errata and the data +cache nullify errata of the UT699 processor. @end table These @samp{-m} options are supported in addition to the above diff --git a/gcc-4.8/gcc/doc/jcf-dump.1 b/gcc-4.8/gcc/doc/jcf-dump.1 index 72a9e4def..2cc5c6172 100644 --- a/gcc-4.8/gcc/doc/jcf-dump.1 +++ b/gcc-4.8/gcc/doc/jcf-dump.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "JCF-DUMP 1" -.TH JCF-DUMP 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH JCF-DUMP 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/jv-convert.1 b/gcc-4.8/gcc/doc/jv-convert.1 index 65f6136f3..66e5cb3d5 100644 --- a/gcc-4.8/gcc/doc/jv-convert.1 +++ b/gcc-4.8/gcc/doc/jv-convert.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "JV-CONVERT 1" -.TH JV-CONVERT 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH JV-CONVERT 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/md.texi b/gcc-4.8/gcc/doc/md.texi index 63ec92f6b..dacb83a70 100644 --- a/gcc-4.8/gcc/doc/md.texi +++ b/gcc-4.8/gcc/doc/md.texi @@ -2055,7 +2055,7 @@ Any constant whose absolute value is no greater than 4-bits. @end table -@item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h} +@item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md} @table @code @item b Address base register @@ -2069,17 +2069,57 @@ Floating point register (containing 32-bit value) @item v Altivec vector register +@item wa +Any VSX register if the -mvsx option was used or NO_REGS. + @item wd -VSX vector register to hold vector double data +VSX vector register to hold vector double data or NO_REGS. @item wf -VSX vector register to hold vector float data +VSX vector register to hold vector float data or NO_REGS. + +@item wg +If @option{-mmfpgpr} was used, a floating point register or NO_REGS. + +@item wl +Floating point register if the LFIWAX instruction is enabled or NO_REGS. + +@item wm +VSX register if direct move instructions are enabled, or NO_REGS. + +@item wn +No register (NO_REGS). + +@item wr +General purpose register if 64-bit instructions are enabled or NO_REGS. @item ws -VSX vector register to hold scalar float data +VSX vector register to hold scalar double values or NO_REGS. -@item wa -Any VSX register +@item wt +VSX vector register to hold 128 bit integer or NO_REGS. + +@item wu +Altivec register to use for float/32-bit int loads/stores or NO_REGS. + +@item wv +Altivec register to use for double loads/stores or NO_REGS. + +@item ww +FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS. + +@item wx +Floating point register if the STFIWX instruction is enabled or NO_REGS. + +@item wy +VSX vector register to hold scalar float values or NO_REGS. + +@item wz +Floating point register if the LFIWZX instruction is enabled or NO_REGS. + +@item wQ +A memory address that will work with the @code{lq} and @code{stq} +instructions. @item h @samp{MQ}, @samp{CTR}, or @samp{LINK} register diff --git a/gcc-4.8/gcc/doc/rebuild-gcj-db.1 b/gcc-4.8/gcc/doc/rebuild-gcj-db.1 index c0fce32e8..899aa6b52 100644 --- a/gcc-4.8/gcc/doc/rebuild-gcj-db.1 +++ b/gcc-4.8/gcc/doc/rebuild-gcj-db.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "REBUILD-GCJ-DB 1" -.TH REBUILD-GCJ-DB 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH REBUILD-GCJ-DB 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/sourcebuild.texi b/gcc-4.8/gcc/doc/sourcebuild.texi index 90bd0bdf2..9330aae52 100644 --- a/gcc-4.8/gcc/doc/sourcebuild.texi +++ b/gcc-4.8/gcc/doc/sourcebuild.texi @@ -1596,6 +1596,13 @@ MIPS target supports @code{-mpaired-single}. @subsubsection PowerPC-specific attributes @table @code + +@item dfp_hw +PowerPC target supports executing hardware DFP instructions. + +@item p8vector_hw +PowerPC target supports executing VSX instructions (ISA 2.07). + @item powerpc64 Test system supports executing 64-bit instructions. @@ -1605,12 +1612,24 @@ PowerPC target supports AltiVec. @item powerpc_altivec_ok PowerPC target supports @code{-maltivec}. +@item powerpc_eabi_ok +PowerPC target supports @code{-meabi}. + +@item powerpc_elfv2 +PowerPC target supports @code{-mabi=elfv2}. + @item powerpc_fprs PowerPC target supports floating-point registers. @item powerpc_hard_double PowerPC target supports hardware double-precision floating-point. +@item powerpc_htm_ok +PowerPC target supports @code{-mhtm} + +@item powerpc_p8vector_ok +PowerPC target supports @code{-mpower8-vector} + @item powerpc_ppu_ok PowerPC target supports @code{-mcpu=cell}. @@ -1624,9 +1643,6 @@ PowerPC target supports PowerPC SPE. @item powerpc_spu PowerPC target supports PowerPC SPU. -@item spu_auto_overlay -SPU target has toolchain that supports automatic overlay generation. - @item powerpc_vsx_ok PowerPC target supports @code{-mvsx}. @@ -1634,8 +1650,17 @@ PowerPC target supports @code{-mvsx}. Including the options used to compile this particular test, the PowerPC target supports PowerPC 405. +@item ppc_recip_hw +PowerPC target supports executing reciprocal estimate instructions. + +@item spu_auto_overlay +SPU target has toolchain that supports automatic overlay generation. + @item vmx_hw PowerPC target supports executing AltiVec instructions. + +@item vsx_hw +PowerPC target supports executing VSX instructions (ISA 2.06). @end table @subsubsection Other hardware attributes |