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Diffstat (limited to 'gcc-4.8/gcc/doc/invoke.texi')
| -rw-r--r-- | gcc-4.8/gcc/doc/invoke.texi | 286 |
1 files changed, 225 insertions, 61 deletions
diff --git a/gcc-4.8/gcc/doc/invoke.texi b/gcc-4.8/gcc/doc/invoke.texi index cb0d50ec7..a09553ccf 100644 --- a/gcc-4.8/gcc/doc/invoke.texi +++ b/gcc-4.8/gcc/doc/invoke.texi @@ -161,7 +161,7 @@ in the following sections. -pipe -pass-exit-codes @gol -x @var{language} -v -### --help@r{[}=@var{class}@r{[},@dots{}@r{]]} --target-help @gol --version -wrapper @@@var{file} -fplugin=@var{file} -fplugin-arg-@var{name}=@var{arg} @gol --fdump-ada-spec@r{[}-slim@r{]} -fada-spec-parent=@var{arg} -fdump-go-spec=@var{file}} +-fdump-ada-spec@r{[}-slim@r{]} -fada-spec-parent=@var{unit} -fdump-go-spec=@var{file}} @item C Language Options @xref{C Dialect Options,,Options Controlling C Dialect}. @@ -857,7 +857,12 @@ See RS/6000 and PowerPC Options. -mno-recip-precision @gol -mveclibabi=@var{type} -mfriz -mno-friz @gol -mpointers-to-nested-functions -mno-pointers-to-nested-functions @gol --msave-toc-indirect -mno-save-toc-indirect} +-msave-toc-indirect -mno-save-toc-indirect @gol +-mpower8-fusion -mno-mpower8-fusion -mpower8-vector -mno-power8-vector @gol +-mcrypto -mno-crypto -mdirect-move -mno-direct-move @gol +-mquad-memory -mno-quad-memory @gol +-mquad-memory-atomic -mno-quad-memory-atomic @gol +-mcompat-align-parm -mno-compat-align-parm} @emph{RX Options} @gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol @@ -881,7 +886,8 @@ See RS/6000 and PowerPC Options. -msmall-exec -mno-small-exec -mmvcle -mno-mvcle @gol -m64 -m31 -mdebug -mno-debug -mesa -mzarch @gol -mtpf-trace -mno-tpf-trace -mfused-madd -mno-fused-madd @gol --mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard} +-mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard @gol +-mhotpatch[=@var{halfwords}] -mno-hotpatch} @emph{Score Options} @gccoptlist{-meb -mel @gol @@ -926,11 +932,12 @@ See RS/6000 and PowerPC Options. -mhard-quad-float -msoft-quad-float @gol -mstack-bias -mno-stack-bias @gol -munaligned-doubles -mno-unaligned-doubles @gol +-muser-mode -mno-user-mode @gol -mv8plus -mno-v8plus -mvis -mno-vis @gol -mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol -mcbcond -mno-cbcond @gol -mfmaf -mno-fmaf -mpopc -mno-popc @gol --mfix-at697f} +-mfix-at697f -mfix-ut699} @emph{SPU Options} @gccoptlist{-mwarn-reloc -merror-reloc @gol @@ -1462,11 +1469,18 @@ Define an argument called @var{key} with a value of @var{value} for the plugin called @var{name}. @item -fdump-ada-spec@r{[}-slim@r{]} -For C and C++ source and include files, generate corresponding Ada -specs. @xref{Generating Ada Bindings for C and C++ headers,,, gnat_ugn, +@opindex fdump-ada-spec +For C and C++ source and include files, generate corresponding Ada specs. +@xref{Generating Ada Bindings for C and C++ headers,,, gnat_ugn, GNAT User's Guide}, which provides detailed documentation on this feature. +@item -fada-spec-parent=@var{unit} +@opindex fada-spec-parent +In conjunction with @option{-fdump-ada-spec@r{[}-slim@r{]}} above, generate +Ada specs as child units of parent @var{unit}. + @item -fdump-go-spec=@var{file} +@opindex fdump-go-spec For input files in any language, generate corresponding Go declarations in @var{file}. This generates Go @code{const}, @code{type}, @code{var}, and @code{func} declarations which may be a @@ -11317,11 +11331,32 @@ option should only be used if you require compatibility with code for big-endian ARM processors generated by versions of the compiler prior to 2.8. This option is now deprecated. -@item -mcpu=@var{name} -@opindex mcpu -This specifies the name of the target ARM processor. GCC uses this name -to determine what kind of instructions it can emit when generating -assembly code. Permissible names are: @samp{arm2}, @samp{arm250}, +@item -march=@var{name} +@opindex march +This specifies the name of the target ARM architecture. GCC uses this +name to determine what kind of instructions it can emit when generating +assembly code. This option can be used in conjunction with or instead +of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, +@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t}, +@samp{armv5}, @samp{armv5t}, @samp{armv5e}, @samp{armv5te}, +@samp{armv6}, @samp{armv6j}, +@samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, @samp{armv6-m}, +@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, @samp{armv7e-m} +@samp{armv8-a}, +@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. + +@option{-march=native} causes the compiler to auto-detect the architecture +of the build computer. At present, this feature is only supported on +Linux, and not all architectures are recognized. If the auto-detect is +unsuccessful the option has no effect. + +@item -mtune=@var{name} +@opindex mtune +This option specifies the name of the target ARM processor for +which GCC should tune the performance of the code. +For some ARM implementations better performance can be obtained by using +this option. +Permissible names are: @samp{arm2}, @samp{arm250}, @samp{arm3}, @samp{arm6}, @samp{arm60}, @samp{arm600}, @samp{arm610}, @samp{arm620}, @samp{arm7}, @samp{arm7m}, @samp{arm7d}, @samp{arm7dm}, @samp{arm7di}, @samp{arm7dmi}, @samp{arm70}, @samp{arm700}, @@ -11349,27 +11384,6 @@ assembly code. Permissible names are: @samp{arm2}, @samp{arm250}, @samp{fa526}, @samp{fa626}, @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}. - -@option{-mcpu=generic-@var{arch}} is also permissible, and is -equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}. -See @option{-mtune} for more information. - -@option{-mcpu=native} causes the compiler to auto-detect the CPU -of the build computer. At present, this feature is only supported on -Linux, and not all architectures are recognized. If the auto-detect is -unsuccessful the option has no effect. - -@item -mtune=@var{name} -@opindex mtune -This option is very similar to the @option{-mcpu=} option, except that -instead of specifying the actual target processor type, and hence -restricting which instructions can be used, it specifies that GCC should -tune the performance of the code as if the target were of the type -specified in this option, but still choosing the instructions it -generates based on the CPU specified by a @option{-mcpu=} option. -For some ARM implementations better performance can be obtained by using -this option. - @option{-mtune=generic-@var{arch}} specifies that GCC should tune the performance for a blend of processors within architecture @var{arch}. The aim is to generate code that run well on the current most popular @@ -11382,21 +11396,23 @@ of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. -@item -march=@var{name} -@opindex march -This specifies the name of the target ARM architecture. GCC uses this -name to determine what kind of instructions it can emit when generating -assembly code. This option can be used in conjunction with or instead -of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, -@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t}, -@samp{armv5}, @samp{armv5t}, @samp{armv5e}, @samp{armv5te}, -@samp{armv6}, @samp{armv6j}, -@samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, @samp{armv6-m}, -@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, -@samp{armv8-a}, -@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. +@item -mcpu=@var{name} +@opindex mcpu +This specifies the name of the target ARM processor. GCC uses this name +to derive the name of the target ARM architecture (as if specified +by @option{-march}) and the ARM processor type for which to tune for +performance (as if specified by @option{-mtune}). Where this option +is used in conjunction with @option{-march} or @option{-mtune}, +those options take precedence over the appropriate part of this option. -@option{-march=native} causes the compiler to auto-detect the architecture +Permissible names for this option are the same as those for +@option{-mtune}. + +@option{-mcpu=generic-@var{arch}} is also permissible, and is +equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}. +See @option{-mtune} for more information. + +@option{-mcpu=native} causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. @@ -11485,8 +11501,11 @@ before execution begins. @item -mpic-register=@var{reg} @opindex mpic-register -Specify the register to be used for PIC addressing. The default is R10 -unless stack-checking is enabled, when R9 is used. +Specify the register to be used for PIC addressing. +For standard PIC base case, the default will be any suitable register +determined by compiler. For single PIC base case, the default is +@samp{R9} if target is EABI based or stack-checking is enabled, +otherwise the default is @samp{R10}. @item -mpoke-function-name @opindex mpoke-function-name @@ -17313,7 +17332,9 @@ following options: @gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol -mpopcntb -mpopcntd -mpowerpc64 @gol -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol --msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx} +-msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx @gol +-mcrypto -mdirect-move -mpower8-fusion -mpower8-vector @gol +-mquad-memory -mquad-memory-atomic} The particular options set for any particular CPU varies between compiler versions, depending on what setting seems to produce optimal @@ -17364,6 +17385,38 @@ the AltiVec instruction set. You may also need to set @option{-mabi=altivec} to adjust the current ABI with AltiVec ABI enhancements. +When @option{-maltivec} is used, rather than @option{-maltivec=le} or +@option{-maltivec=be}, the element order for Altivec intrinsics such +as @code{vec_splat}, @code{vec_extract}, and @code{vec_insert} will +match array element order corresponding to the endianness of the +target. That is, element zero identifies the leftmost element in a +vector register when targeting a big-endian platform, and identifies +the rightmost element in a vector register when targeting a +little-endian platform. + +@item -maltivec=be +@opindex maltivec=be +Generate Altivec instructions using big-endian element order, +regardless of whether the target is big- or little-endian. This is +the default when targeting a big-endian platform. + +The element order is used to interpret element numbers in Altivec +intrinsics such as @code{vec_splat}, @code{vec_extract}, and +@code{vec_insert}. By default, these will match array element order +corresponding to the endianness for the target. + +@item -maltivec=le +@opindex maltivec=le +Generate Altivec instructions using little-endian element order, +regardless of whether the target is big- or little-endian. This is +the default when targeting a little-endian platform. This option is +currently ignored when targeting a big-endian platform. + +The element order is used to interpret element numbers in Altivec +intrinsics such as @code{vec_splat}, @code{vec_extract}, and +@code{vec_insert}. By default, these will match array element order +corresponding to the endianness for the target. + @item -mvrsave @itemx -mno-vrsave @opindex mvrsave @@ -17431,6 +17484,55 @@ Generate code that uses (does not use) vector/scalar (VSX) instructions, and also enable the use of built-in functions that allow more direct access to the VSX instruction set. +@item -mcrypto +@itemx -mno-crypto +@opindex mcrypto +@opindex mno-crypto +Enable the use (disable) of the built-in functions that allow direct +access to the cryptographic instructions that were added in version +2.07 of the PowerPC ISA. + +@item -mdirect-move +@itemx -mno-direct-move +@opindex mdirect-move +@opindex mno-direct-move +Generate code that uses (does not use) the instructions to move data +between the general purpose registers and the vector/scalar (VSX) +registers that were added in version 2.07 of the PowerPC ISA. + +@item -mpower8-fusion +@itemx -mno-power8-fusion +@opindex mpower8-fusion +@opindex mno-power8-fusion +Generate code that keeps (does not keeps) some integer operations +adjacent so that the instructions can be fused together on power8 and +later processors. + +@item -mpower8-vector +@itemx -mno-power8-vector +@opindex mpower8-vector +@opindex mno-power8-vector +Generate code that uses (does not use) the vector and scalar +instructions that were added in version 2.07 of the PowerPC ISA. Also +enable the use of built-in functions that allow more direct access to +the vector instructions. + +@item -mquad-memory +@itemx -mno-quad-memory +@opindex mquad-memory +@opindex mno-quad-memory +Generate code that uses (does not use) the non-atomic quad word memory +instructions. The @option{-mquad-memory} option requires use of +64-bit mode. + +@item -mquad-memory-atomic +@itemx -mno-quad-memory-atomic +@opindex mquad-memory-atomic +@opindex mno-quad-memory-atomic +Generate code that uses (does not use) the atomic quad word memory +instructions. The @option{-mquad-memory-atomic} option requires use of +64-bit mode. + @item -mfloat-gprs=@var{yes/single/double/no} @itemx -mfloat-gprs @opindex mfloat-gprs @@ -17850,7 +17952,8 @@ SVR4 ABI)@. @opindex mabi Extend the current ABI with a particular extension, or remove such extension. Valid values are @var{altivec}, @var{no-altivec}, @var{spe}, -@var{no-spe}, @var{ibmlongdouble}, @var{ieeelongdouble}@. +@var{no-spe}, @var{ibmlongdouble}, @var{ieeelongdouble}, +@var{elfv1}, @var{elfv2}@. @item -mabi=spe @opindex mabi=spe @@ -17872,6 +17975,20 @@ This is a PowerPC 32-bit SYSV ABI option. Change the current ABI to use IEEE extended-precision long double. This is a PowerPC 32-bit Linux ABI option. +@item -mabi=elfv1 +@opindex mabi=elfv1 +Change the current ABI to use the ELFv1 ABI. +This is the default ABI for big-endian PowerPC 64-bit Linux. +Overriding the default ABI requires special system support and is +likely to fail in spectacular ways. + +@item -mabi=elfv2 +@opindex mabi=elfv2 +Change the current ABI to use the ELFv2 ABI. +This is the default ABI for little-endian PowerPC 64-bit Linux. +Overriding the default ABI requires special system support and is +likely to fail in spectacular ways. + @item -mprototype @itemx -mno-prototype @opindex mprototype @@ -18157,6 +18274,23 @@ stack location in the function prologue if the function calls through a pointer on AIX and 64-bit Linux systems. If the TOC value is not saved in the prologue, it is saved just before the call through the pointer. The @option{-mno-save-toc-indirect} option is the default. + +@item -mcompat-align-parm +@itemx -mno-compat-align-parm +@opindex mcompat-align-parm +Generate (do not generate) code to pass structure parameters with a +maximum alignment of 64 bits, for compatibility with older versions +of GCC. + +Older versions of GCC (prior to 4.9.0) incorrectly did not align a +structure parameter on a 128-bit boundary when that structure contained +a member requiring 128-bit alignment. This is corrected in more +recent versions of GCC. This option may be used to generate code +that is compatible with functions compiled with older versions of +GCC. + +In this version of the compiler, the @option{-mcompat-align-parm} +is the default, except when using the Linux ELFv2 ABI. @end table @node RX Options @@ -18536,6 +18670,21 @@ values have to be exact powers of 2 and @var{stack-size} has to be greater than In order to be efficient the extra code makes the assumption that the stack starts at an address aligned to the value given by @var{stack-size}. The @var{stack-guard} option can only be used in conjunction with @var{stack-size}. + +@item -mhotpatch[=@var{halfwords}] +@itemx -mno-hotpatch +@opindex mhotpatch +If the hotpatch option is enabled, a ``hot-patching'' function +prologue is generated for all functions in the compilation unit. +The funtion label is prepended with the given number of two-byte +Nop instructions (@var{halfwords}, maximum 1000000) or 12 Nop +instructions if no argument is present. Functions with a +hot-patching prologue are never inlined automatically, and a +hot-patching prologue is never generated for functions functions +that are explicitly inline. + +This option can be overridden for individual functions with the +@code{hotpatch} attribute. @end table @node Score Options @@ -19126,8 +19275,9 @@ These @samp{-m} options are supported on the SPARC: @opindex mno-app-regs @opindex mapp-regs Specify @option{-mapp-regs} to generate output using the global registers -2 through 4, which the SPARC SVR4 ABI reserves for applications. This -is the default. +2 through 4, which the SPARC SVR4 ABI reserves for applications. Like the +global register 1, each global register 2 through 4 is then treated as an +allocable register that is clobbered by function calls. This is the default. To be fully SVR4 ABI-compliant at the cost of some performance loss, specify @option{-mno-app-regs}. You should compile libraries and system @@ -19202,6 +19352,14 @@ Specifying this option avoids some rare compatibility problems with code generated by other compilers. It is not the default because it results in a performance loss, especially for floating-point code. +@item -muser-mode +@itemx -mno-user-mode +@opindex muser-mode +@opindex mno-user-mode +Do not generate code that can only run in supervisor mode. This is relevant +only for the @code{casa} instruction emitted for the LEON3 processor. The +default is @option{-mno-user-mode}. + @item -mno-faster-structs @itemx -mfaster-structs @opindex mno-faster-structs @@ -19220,10 +19378,10 @@ the rules of the ABI@. Set the instruction set, register set, and instruction scheduling parameters for machine type @var{cpu_type}. Supported values for @var{cpu_type} are @samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{hypersparc}, -@samp{leon}, @samp{sparclite}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, -@samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, -@samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, @samp{niagara3}, -and @samp{niagara4}. +@samp{leon}, @samp{leon3}, @samp{sparclite}, @samp{f930}, @samp{f934}, +@samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9}, +@samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, +@samp{niagara3} and @samp{niagara4}. Native Solaris and GNU/Linux toolchains also support the value @samp{native}, which selects the best architecture option for the host processor. @@ -19242,7 +19400,7 @@ implementations. cypress @item v8 -supersparc, hypersparc, leon +supersparc, hypersparc, leon, leon3 @item sparclite f930, f934, sparclite86x @@ -19304,10 +19462,11 @@ option @option{-mcpu=@var{cpu_type}} does. The same values for @option{-mcpu=@var{cpu_type}} can be used for @option{-mtune=@var{cpu_type}}, but the only useful values are those that select a particular CPU implementation. Those are @samp{cypress}, -@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{f930}, @samp{f934}, -@samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, @samp{ultrasparc3}, -@samp{niagara}, @samp{niagara2}, @samp{niagara3} and @samp{niagara4}. With -native Solaris and GNU/Linux toolchains, @samp{native} can also be used. +@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{leon3}, @samp{f930}, +@samp{f934}, @samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, +@samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, @samp{niagara3} and +@samp{niagara4}. With native Solaris and GNU/Linux toolchains, @samp{native} +can also be used. @item -mv8plus @itemx -mno-v8plus @@ -19376,6 +19535,11 @@ later. @opindex mfix-at697f Enable the documented workaround for the single erratum of the Atmel AT697F processor (which corresponds to erratum #13 of the AT697E processor). + +@item -mfix-ut699 +@opindex mfix-ut699 +Enable the documented workarounds for the floating-point errata and the data +cache nullify errata of the UT699 processor. @end table These @samp{-m} options are supported in addition to the above |