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Diffstat (limited to 'gcc-4.8/gcc/doc/gcc.1')
| -rw-r--r-- | gcc-4.8/gcc/doc/gcc.1 | 364 |
1 files changed, 272 insertions, 92 deletions
diff --git a/gcc-4.8/gcc/doc/gcc.1 b/gcc-4.8/gcc/doc/gcc.1 index 88e400d95..24005b6cc 100644 --- a/gcc-4.8/gcc/doc/gcc.1 +++ b/gcc-4.8/gcc/doc/gcc.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GCC 1" -.TH GCC 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GCC 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -180,7 +188,7 @@ these have both positive and negative forms; the negative form of only one of these two forms, whichever one is not the default. .SH "OPTIONS" .IX Header "OPTIONS" -.SS "Option Summary" +.Sh "Option Summary" .IX Subsection "Option Summary" Here is a summary of all the options, grouped by type. Explanations are in the following sections. @@ -190,7 +198,7 @@ in the following sections. \&\-pipe \-pass\-exit\-codes \&\-x\fR \fIlanguage\fR \fB\-v \-### \-\-help\fR[\fB=\fR\fIclass\fR[\fB,...\fR]] \fB\-\-target\-help \&\-\-version \-wrapper @\fR\fIfile\fR \fB\-fplugin=\fR\fIfile\fR \fB\-fplugin\-arg\-\fR\fIname\fR\fB=\fR\fIarg\fR -\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \fB\-fada\-spec\-parent=\fR\fIarg\fR \fB\-fdump\-go\-spec=\fR\fIfile\fR +\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \fB\-fada\-spec\-parent=\fR\fIunit\fR \fB\-fdump\-go\-spec=\fR\fIfile\fR .IP "\fIC Language Options\fR" 4 .IX Item "C Language Options" \&\fB\-ansi \-std=\fR\fIstandard\fR \fB\-fgnu89\-inline @@ -867,7 +875,12 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-mno\-recip\-precision \&\-mveclibabi=\fR\fItype\fR \fB\-mfriz \-mno\-friz \&\-mpointers\-to\-nested\-functions \-mno\-pointers\-to\-nested\-functions -\&\-msave\-toc\-indirect \-mno\-save\-toc\-indirect\fR +\&\-msave\-toc\-indirect \-mno\-save\-toc\-indirect +\&\-mpower8\-fusion \-mno\-mpower8\-fusion \-mpower8\-vector \-mno\-power8\-vector +\&\-mcrypto \-mno\-crypto \-mdirect\-move \-mno\-direct\-move +\&\-mquad\-memory \-mno\-quad\-memory +\&\-mquad\-memory\-atomic \-mno\-quad\-memory\-atomic +\&\-mcompat\-align\-parm \-mno\-compat\-align\-parm\fR .Sp \&\fI\s-1RX\s0 Options\fR \&\fB\-m64bit\-doubles \-m32bit\-doubles \-fpu \-nofpu @@ -891,7 +904,8 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-msmall\-exec \-mno\-small\-exec \-mmvcle \-mno\-mvcle \&\-m64 \-m31 \-mdebug \-mno\-debug \-mesa \-mzarch \&\-mtpf\-trace \-mno\-tpf\-trace \-mfused\-madd \-mno\-fused\-madd -\&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard\fR +\&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard +\&\-mhotpatch[=\fR\fIhalfwords\fR\fB] \-mno\-hotpatch\fR .Sp \&\fIScore Options\fR \&\fB\-meb \-mel @@ -936,11 +950,12 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-mhard\-quad\-float \-msoft\-quad\-float \&\-mstack\-bias \-mno\-stack\-bias \&\-munaligned\-doubles \-mno\-unaligned\-doubles +\&\-muser\-mode \-mno\-user\-mode \&\-mv8plus \-mno\-v8plus \-mvis \-mno\-vis \&\-mvis2 \-mno\-vis2 \-mvis3 \-mno\-vis3 \&\-mcbcond \-mno\-cbcond \&\-mfmaf \-mno\-fmaf \-mpopc \-mno\-popc -\&\-mfix\-at697f\fR +\&\-mfix\-at697f \-mfix\-ut699\fR .Sp \&\fI\s-1SPU\s0 Options\fR \&\fB\-mwarn\-reloc \-merror\-reloc @@ -1029,7 +1044,7 @@ See S/390 and zSeries Options. \&\fB\-fstack\-reuse=\fR\fIreuse_level\fR \&\fB\-ftrapv \-fwrapv \-fbounds\-check \&\-fvisibility \-fstrict\-volatile\-bitfields \-fsync\-libcalls\fR -.SS "Options Controlling the Kind of Output" +.Sh "Options Controlling the Kind of Output" .IX Subsection "Options Controlling the Kind of Output" Compilation can involve up to four stages: preprocessing, compilation proper, assembly and linking, always in that order. \s-1GCC\s0 is capable of @@ -1459,8 +1474,11 @@ Define an argument called \fIkey\fR with a value of \fIvalue\fR for the plugin called \fIname\fR. .IP "\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR]" 4 .IX Item "-fdump-ada-spec[-slim]" -For C and \*(C+ source and include files, generate corresponding Ada -specs. +For C and \*(C+ source and include files, generate corresponding Ada specs. +.IP "\fB\-fada\-spec\-parent=\fR\fIunit\fR" 4 +.IX Item "-fada-spec-parent=unit" +In conjunction with \fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] above, generate +Ada specs as child units of parent \fIunit\fR. .IP "\fB\-fdump\-go\-spec=\fR\fIfile\fR" 4 .IX Item "-fdump-go-spec=file" For input files in any language, generate corresponding Go @@ -1481,8 +1499,8 @@ option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The \fIfile\fR may itself contain additional @\fIfile\fR options; any such options will be processed recursively. -.SS "Compiling \*(C+ Programs" -.IX Subsection "Compiling Programs" +.Sh "Compiling \*(C+ Programs" +.IX Subsection "Compiling Programs" \&\*(C+ source files conventionally use one of the suffixes \fB.C\fR, \&\fB.cc\fR, \fB.cpp\fR, \fB.CPP\fR, \fB.c++\fR, \fB.cp\fR, or \&\fB.cxx\fR; \*(C+ header files often use \fB.hh\fR, \fB.hpp\fR, @@ -1505,7 +1523,7 @@ When you compile \*(C+ programs, you may specify many of the same command-line options that you use for compiling programs in any language; or command-line options meaningful for C and related languages; or options that are meaningful only for \*(C+ programs. -.SS "Options Controlling C Dialect" +.Sh "Options Controlling C Dialect" .IX Subsection "Options Controlling C Dialect" The following options control the dialect of C (or languages derived from C, such as \*(C+, Objective-C and Objective\-\*(C+) that the compiler @@ -1892,8 +1910,8 @@ These options control whether a bit-field is signed or unsigned, when the declaration does not use either \f(CW\*(C`signed\*(C'\fR or \f(CW\*(C`unsigned\*(C'\fR. By default, such a bit-field is signed, because this is consistent: the basic integer types such as \f(CW\*(C`int\*(C'\fR are signed types. -.SS "Options Controlling \*(C+ Dialect" -.IX Subsection "Options Controlling Dialect" +.Sh "Options Controlling \*(C+ Dialect" +.IX Subsection "Options Controlling Dialect" This section describes the command-line options that are only meaningful for \*(C+ programs. You can also use most of the \s-1GNU\s0 compiler options regardless of what language your program is in. For example, you @@ -2250,7 +2268,7 @@ Do not assume \fBinline\fR for functions defined inside a class scope. functions have linkage like inline functions; they just aren't inlined by default. .IP "\fB\-Wabi\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 -.IX Item "-Wabi (C, Objective-C, and Objective- only)" +.IX Item "-Wabi (C, Objective-C, and Objective- only)" Warn when G++ generates code that is probably not compatible with the vendor-neutral \*(C+ \s-1ABI\s0. Although an effort has been made to warn about all such cases, there are probably some cases that are not warned about, @@ -2562,7 +2580,7 @@ Warn when overload resolution chooses a promotion from unsigned or enumerated type to a signed type, over a conversion to an unsigned type of the same size. Previous versions of G++ tried to preserve unsignedness, but the standard mandates the current behavior. -.SS "Options Controlling Objective-C and Objective\-\*(C+ Dialects" +.Sh "Options Controlling Objective-C and Objective\-\*(C+ Dialects" .IX Subsection "Options Controlling Objective-C and Objective- Dialects" (\s-1NOTE:\s0 This manual does not describe the Objective-C and Objective\-\*(C+ languages themselves. @@ -2759,7 +2777,7 @@ that methods and selectors must be declared before being used. .IX Item "-print-objc-runtime-info" Generate C header describing the largest structure that is passed by value, if any. -.SS "Options to Control Diagnostic Messages Formatting" +.Sh "Options to Control Diagnostic Messages Formatting" .IX Subsection "Options to Control Diagnostic Messages Formatting" Traditionally, diagnostic messages have been formatted irrespective of the output device's aspect (e.g. its width, ...). You can use the @@ -2800,7 +2818,7 @@ option is known to the diagnostic machinery). Specifying the By default, each diagnostic emitted includes the original source line and a caret '^' indicating the column. This option suppresses this information. -.SS "Options to Request or Suppress Warnings" +.Sh "Options to Request or Suppress Warnings" .IX Subsection "Options to Request or Suppress Warnings" Warnings are diagnostic messages that report constructions that are not inherently erroneous but that are risky or suggest there @@ -3186,7 +3204,7 @@ enabled by default and it is made into an error by Same as \fB\-Wimplicit\-int\fR and \fB\-Wimplicit\-function\-declaration\fR. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wignored\-qualifiers\fR (C and \*(C+ only)" 4 -.IX Item "-Wignored-qualifiers (C and only)" +.IX Item "-Wignored-qualifiers (C and only)" Warn if the return type of a function has a type qualifier such as \f(CW\*(C`const\*(C'\fR. For \s-1ISO\s0 C such a type qualifier has no effect, since the value returned by a function is not an lvalue. @@ -3358,7 +3376,7 @@ between \fB\-Wswitch\fR and this option is that this option gives a warning about an omitted enumeration code even if there is a \&\f(CW\*(C`default\*(C'\fR label. .IP "\fB\-Wsync\-nand\fR (C and \*(C+ only)" 4 -.IX Item "-Wsync-nand (C and only)" +.IX Item "-Wsync-nand (C and only)" Warn when \f(CW\*(C`_\|_sync_fetch_and_nand\*(C'\fR and \f(CW\*(C`_\|_sync_nand_and_fetch\*(C'\fR built-in functions are used. These functions changed semantics in \s-1GCC\s0 4.4. .IP "\fB\-Wtrigraphs\fR" 4 @@ -3397,7 +3415,7 @@ This warning is enabled by \fB\-Wall\fR. .Sp To suppress this warning use the \fBunused\fR attribute. .IP "\fB\-Wunused\-local\-typedefs\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 -.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" +.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" Warn when a typedef locally defined in a function is not used. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wunused\-parameter\fR" 4 @@ -4355,7 +4373,7 @@ a suffix. When used together with \fB\-Wsystem\-headers\fR it warns about such constants in system header files. This can be useful when preparing code to use with the \f(CW\*(C`FLOAT_CONST_DECIMAL64\*(C'\fR pragma from the decimal floating-point extension to C99. -.SS "Options for Debugging Your Program or \s-1GCC\s0" +.Sh "Options for Debugging Your Program or \s-1GCC\s0" .IX Subsection "Options for Debugging Your Program or GCC" \&\s-1GCC\s0 has various special options that are used for debugging either your program or \s-1GCC:\s0 @@ -5859,7 +5877,7 @@ in that compilation unit, for example if, in the debugger, you want to cast a value to a type that is not actually used in your program (but is declared). More often, however, this results in a significant amount of wasted space. -.SS "Options That Control Optimization" +.Sh "Options That Control Optimization" .IX Subsection "Options That Control Optimization" These options control various sorts of optimizations. .PP @@ -8968,7 +8986,7 @@ seeking a basis for a new straight-line strength reduction candidate. .RE .RS 4 .RE -.SS "Options Controlling the Preprocessor" +.Sh "Options Controlling the Preprocessor" .IX Subsection "Options Controlling the Preprocessor" These options control the C preprocessor, which is run on each C source file before actual compilation. @@ -9770,7 +9788,7 @@ header file is printed with \fB...x\fR and a valid one with \fB...!\fR . .PD Print out \s-1GNU\s0 \s-1CPP\s0's version number. With one dash, proceed to preprocess as normal. With two dashes, exit immediately. -.SS "Passing Options to the Assembler" +.Sh "Passing Options to the Assembler" .IX Subsection "Passing Options to the Assembler" You can pass options to the assembler. .IP "\fB\-Wa,\fR\fIoption\fR" 4 @@ -9785,7 +9803,7 @@ recognize. .Sp If you want to pass an option that takes an argument, you must use \&\fB\-Xassembler\fR twice, once for the option and once for the argument. -.SS "Options for Linking" +.Sh "Options for Linking" .IX Subsection "Options for Linking" These options come into play when the compiler links object files into an executable output file. They are meaningless if the compiler is @@ -10024,7 +10042,7 @@ linker. When using the \s-1GNU\s0 linker, you can also get the same effect with Pretend the symbol \fIsymbol\fR is undefined, to force linking of library modules to define it. You can use \fB\-u\fR multiple times with different symbols to force loading of additional library modules. -.SS "Options for Directory Search" +.Sh "Options for Directory Search" .IX Subsection "Options for Directory Search" These options specify directories to search for header files, for libraries and for parts of the compiler: @@ -10159,13 +10177,13 @@ by default, but it is often satisfactory. \&\fB\-I\-\fR does not inhibit the use of the standard system directories for header files. Thus, \fB\-I\-\fR and \fB\-nostdinc\fR are independent. -.SS "Specifying Target Machine and Compiler Version" +.Sh "Specifying Target Machine and Compiler Version" .IX Subsection "Specifying Target Machine and Compiler Version" The usual way to run \s-1GCC\s0 is to run the executable called \fBgcc\fR, or \&\fImachine\fR\fB\-gcc\fR when cross-compiling, or \&\fImachine\fR\fB\-gcc\-\fR\fIversion\fR to run a version other than the one that was installed last. -.SS "Hardware Models and Configurations" +.Sh "Hardware Models and Configurations" .IX Subsection "Hardware Models and Configurations" Each target machine types can have its own special options, starting with \fB\-m\fR, to choose among various @@ -10489,11 +10507,31 @@ order. That is, a byte order of the form \fB32107654\fR. Note: this option should only be used if you require compatibility with code for big-endian \s-1ARM\s0 processors generated by versions of the compiler prior to 2.8. This option is now deprecated. -.IP "\fB\-mcpu=\fR\fIname\fR" 4 -.IX Item "-mcpu=name" -This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name -to determine what kind of instructions it can emit when generating -assembly code. Permissible names are: \fBarm2\fR, \fBarm250\fR, +.IP "\fB\-march=\fR\fIname\fR" 4 +.IX Item "-march=name" +This specifies the name of the target \s-1ARM\s0 architecture. \s-1GCC\s0 uses this +name to determine what kind of instructions it can emit when generating +assembly code. This option can be used in conjunction with or instead +of the \fB\-mcpu=\fR option. Permissible names are: \fBarmv2\fR, +\&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR, +\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5e\fR, \fBarmv5te\fR, +\&\fBarmv6\fR, \fBarmv6j\fR, +\&\fBarmv6t2\fR, \fBarmv6z\fR, \fBarmv6zk\fR, \fBarmv6\-m\fR, +\&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7\-r\fR, \fBarmv7\-m\fR, \fBarmv7e\-m\fR +\&\fBarmv8\-a\fR, +\&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR. +.Sp +\&\fB\-march=native\fR causes the compiler to auto-detect the architecture +of the build computer. At present, this feature is only supported on +Linux, and not all architectures are recognized. If the auto-detect is +unsuccessful the option has no effect. +.IP "\fB\-mtune=\fR\fIname\fR" 4 +.IX Item "-mtune=name" +This option specifies the name of the target \s-1ARM\s0 processor for +which \s-1GCC\s0 should tune the performance of the code. +For some \s-1ARM\s0 implementations better performance can be obtained by using +this option. +Permissible names are: \fBarm2\fR, \fBarm250\fR, \&\fBarm3\fR, \fBarm6\fR, \fBarm60\fR, \fBarm600\fR, \fBarm610\fR, \&\fBarm620\fR, \fBarm7\fR, \fBarm7m\fR, \fBarm7d\fR, \fBarm7dm\fR, \&\fBarm7di\fR, \fBarm7dmi\fR, \fBarm70\fR, \fBarm700\fR, @@ -10521,25 +10559,6 @@ assembly code. Permissible names are: \fBarm2\fR, \fBarm250\fR, \&\fBfa526\fR, \fBfa626\fR, \&\fBfa606te\fR, \fBfa626te\fR, \fBfmp626\fR, \fBfa726te\fR. .Sp -\&\fB\-mcpu=generic\-\fR\fIarch\fR is also permissible, and is -equivalent to \fB\-march=\fR\fIarch\fR \fB\-mtune=generic\-\fR\fIarch\fR. -See \fB\-mtune\fR for more information. -.Sp -\&\fB\-mcpu=native\fR causes the compiler to auto-detect the \s-1CPU\s0 -of the build computer. At present, this feature is only supported on -Linux, and not all architectures are recognized. If the auto-detect is -unsuccessful the option has no effect. -.IP "\fB\-mtune=\fR\fIname\fR" 4 -.IX Item "-mtune=name" -This option is very similar to the \fB\-mcpu=\fR option, except that -instead of specifying the actual target processor type, and hence -restricting which instructions can be used, it specifies that \s-1GCC\s0 should -tune the performance of the code as if the target were of the type -specified in this option, but still choosing the instructions it -generates based on the \s-1CPU\s0 specified by a \fB\-mcpu=\fR option. -For some \s-1ARM\s0 implementations better performance can be obtained by using -this option. -.Sp \&\fB\-mtune=generic\-\fR\fIarch\fR specifies that \s-1GCC\s0 should tune the performance for a blend of processors within architecture \fIarch\fR. The aim is to generate code that run well on the current most popular @@ -10551,21 +10570,23 @@ this option may change in future \s-1GCC\s0 versions as \s-1CPU\s0 models come a of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. -.IP "\fB\-march=\fR\fIname\fR" 4 -.IX Item "-march=name" -This specifies the name of the target \s-1ARM\s0 architecture. \s-1GCC\s0 uses this -name to determine what kind of instructions it can emit when generating -assembly code. This option can be used in conjunction with or instead -of the \fB\-mcpu=\fR option. Permissible names are: \fBarmv2\fR, -\&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR, -\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5e\fR, \fBarmv5te\fR, -\&\fBarmv6\fR, \fBarmv6j\fR, -\&\fBarmv6t2\fR, \fBarmv6z\fR, \fBarmv6zk\fR, \fBarmv6\-m\fR, -\&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7\-r\fR, \fBarmv7\-m\fR, -\&\fBarmv8\-a\fR, -\&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name +to derive the name of the target \s-1ARM\s0 architecture (as if specified +by \fB\-march\fR) and the \s-1ARM\s0 processor type for which to tune for +performance (as if specified by \fB\-mtune\fR). Where this option +is used in conjunction with \fB\-march\fR or \fB\-mtune\fR, +those options take precedence over the appropriate part of this option. .Sp -\&\fB\-march=native\fR causes the compiler to auto-detect the architecture +Permissible names for this option are the same as those for +\&\fB\-mtune\fR. +.Sp +\&\fB\-mcpu=generic\-\fR\fIarch\fR is also permissible, and is +equivalent to \fB\-march=\fR\fIarch\fR \fB\-mtune=generic\-\fR\fIarch\fR. +See \fB\-mtune\fR for more information. +.Sp +\&\fB\-mcpu=native\fR causes the compiler to auto-detect the \s-1CPU\s0 of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. @@ -10649,8 +10670,11 @@ responsible for initializing this register with an appropriate value before execution begins. .IP "\fB\-mpic\-register=\fR\fIreg\fR" 4 .IX Item "-mpic-register=reg" -Specify the register to be used for \s-1PIC\s0 addressing. The default is R10 -unless stack-checking is enabled, when R9 is used. +Specify the register to be used for \s-1PIC\s0 addressing. +For standard \s-1PIC\s0 base case, the default will be any suitable register +determined by compiler. For single \s-1PIC\s0 base case, the default is +\&\fBR9\fR if target is \s-1EABI\s0 based or stack-checking is enabled, +otherwise the default is \fBR10\fR. .IP "\fB\-mpoke\-function\-name\fR" 4 .IX Item "-mpoke-function-name" Write the name of each function into the text section, directly @@ -10805,7 +10829,7 @@ The default for this option is@tie{}\f(CW\*(C`avr2\*(C'\fR. .el .IP "\f(CWavr5\fR" 4 .IX Item "avr5" \&\*(L"Enhanced\*(R" devices with 16@tie{}KiB up to 64@tie{}KiB of program memory. -\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata5790\*(C'\fR, \f(CW\*(C`ata5790n\*(C'\fR, \f(CW\*(C`ata5795\*(C'\fR, \f(CW\*(C`atmega16\*(C'\fR, \f(CW\*(C`atmega16a\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvbrevb\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega161\*(C'\fR, \f(CW\*(C`atmega162\*(C'\fR, \f(CW\*(C`atmega163\*(C'\fR, \f(CW\*(C`atmega164a\*(C'\fR, \f(CW\*(C`atmega164p\*(C'\fR, \f(CW\*(C`atmega164pa\*(C'\fR, \f(CW\*(C`atmega165\*(C'\fR, \f(CW\*(C`atmega165a\*(C'\fR, \f(CW\*(C`atmega165p\*(C'\fR, \f(CW\*(C`atmega165pa\*(C'\fR, \f(CW\*(C`atmega168\*(C'\fR, \f(CW\*(C`atmega168a\*(C'\fR, \f(CW\*(C`atmega168p\*(C'\fR, \f(CW\*(C`atmega168pa\*(C'\fR, \f(CW\*(C`atmega169\*(C'\fR, \f(CW\*(C`atmega169a\*(C'\fR, \f(CW\*(C`atmega169p\*(C'\fR, \f(CW\*(C`atmega169pa\*(C'\fR, \f(CW\*(C`atmega26hvg\*(C'\fR, \f(CW\*(C`atmega32\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvbrevb\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega323\*(C'\fR, \f(CW\*(C`atmega324a\*(C'\fR, \f(CW\*(C`atmega324p\*(C'\fR, \f(CW\*(C`atmega324pa\*(C'\fR, \f(CW\*(C`atmega325\*(C'\fR, \f(CW\*(C`atmega325a\*(C'\fR, \f(CW\*(C`atmega325p\*(C'\fR, \f(CW\*(C`atmega3250\*(C'\fR, \f(CW\*(C`atmega3250a\*(C'\fR, \f(CW\*(C`atmega3250p\*(C'\fR, \f(CW\*(C`atmega3250pa\*(C'\fR, \f(CW\*(C`atmega328\*(C'\fR, \f(CW\*(C`atmega328p\*(C'\fR, \f(CW\*(C`atmega329\*(C'\fR, \f(CW\*(C`atmega329a\*(C'\fR, \f(CW\*(C`atmega329p\*(C'\fR, \f(CW\*(C`atmega329pa\*(C'\fR, \f(CW\*(C`atmega3290\*(C'\fR, \f(CW\*(C`atmega3290a\*(C'\fR, \f(CW\*(C`atmega3290p\*(C'\fR, \f(CW\*(C`atmega3290pa\*(C'\fR, \f(CW\*(C`atmega406\*(C'\fR, \f(CW\*(C`atmega48hvf\*(C'\fR, \f(CW\*(C`atmega64\*(C'\fR, \f(CW\*(C`atmega64a\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64hve\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64rfa2\*(C'\fR, \f(CW\*(C`atmega64rfr2\*(C'\fR, \f(CW\*(C`atmega640\*(C'\fR, \f(CW\*(C`atmega644\*(C'\fR, \f(CW\*(C`atmega644a\*(C'\fR, \f(CW\*(C`atmega644p\*(C'\fR, \f(CW\*(C`atmega644pa\*(C'\fR, \f(CW\*(C`atmega645\*(C'\fR, \f(CW\*(C`atmega645a\*(C'\fR, \f(CW\*(C`atmega645p\*(C'\fR, \f(CW\*(C`atmega6450\*(C'\fR, \f(CW\*(C`atmega6450a\*(C'\fR, \f(CW\*(C`atmega6450p\*(C'\fR, \f(CW\*(C`atmega649\*(C'\fR, \f(CW\*(C`atmega649a\*(C'\fR, \f(CW\*(C`atmega649p\*(C'\fR, \f(CW\*(C`atmega6490\*(C'\fR, \f(CW\*(C`atmega6490a\*(C'\fR, \f(CW\*(C`atmega6490p\*(C'\fR, \f(CW\*(C`at90can32\*(C'\fR, \f(CW\*(C`at90can64\*(C'\fR, \f(CW\*(C`at90pwm161\*(C'\fR, \f(CW\*(C`at90pwm216\*(C'\fR, \f(CW\*(C`at90pwm316\*(C'\fR, \f(CW\*(C`at90scr100\*(C'\fR, \f(CW\*(C`at90usb646\*(C'\fR, \f(CW\*(C`at90usb647\*(C'\fR, \f(CW\*(C`at94k\*(C'\fR, \f(CW\*(C`m3000\*(C'\fR. +\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata5790\*(C'\fR, \f(CW\*(C`ata5790n\*(C'\fR, \f(CW\*(C`ata5795\*(C'\fR, \f(CW\*(C`atmega16\*(C'\fR, \f(CW\*(C`atmega16a\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvbrevb\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega161\*(C'\fR, \f(CW\*(C`atmega162\*(C'\fR, \f(CW\*(C`atmega163\*(C'\fR, \f(CW\*(C`atmega164a\*(C'\fR, \f(CW\*(C`atmega164p\*(C'\fR, \f(CW\*(C`atmega164pa\*(C'\fR, \f(CW\*(C`atmega165\*(C'\fR, \f(CW\*(C`atmega165a\*(C'\fR, \f(CW\*(C`atmega165p\*(C'\fR, \f(CW\*(C`atmega165pa\*(C'\fR, \f(CW\*(C`atmega168\*(C'\fR, \f(CW\*(C`atmega168a\*(C'\fR, \f(CW\*(C`atmega168p\*(C'\fR, \f(CW\*(C`atmega168pa\*(C'\fR, \f(CW\*(C`atmega169\*(C'\fR, \f(CW\*(C`atmega169a\*(C'\fR, \f(CW\*(C`atmega169p\*(C'\fR, \f(CW\*(C`atmega169pa\*(C'\fR, \f(CW\*(C`atmega26hvg\*(C'\fR, \f(CW\*(C`atmega32\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvbrevb\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega323\*(C'\fR, \f(CW\*(C`atmega324a\*(C'\fR, \f(CW\*(C`atmega324p\*(C'\fR, \f(CW\*(C`atmega324pa\*(C'\fR, \f(CW\*(C`atmega325\*(C'\fR, \f(CW\*(C`atmega325a\*(C'\fR, \f(CW\*(C`atmega325p\*(C'\fR, \f(CW\*(C`atmega3250\*(C'\fR, \f(CW\*(C`atmega3250a\*(C'\fR, \f(CW\*(C`atmega3250p\*(C'\fR, \f(CW\*(C`atmega3250pa\*(C'\fR, \f(CW\*(C`atmega328\*(C'\fR, \f(CW\*(C`atmega328p\*(C'\fR, \f(CW\*(C`atmega329\*(C'\fR, \f(CW\*(C`atmega329a\*(C'\fR, \f(CW\*(C`atmega329p\*(C'\fR, \f(CW\*(C`atmega329pa\*(C'\fR, \f(CW\*(C`atmega3290\*(C'\fR, \f(CW\*(C`atmega3290a\*(C'\fR, \f(CW\*(C`atmega3290p\*(C'\fR, \f(CW\*(C`atmega3290pa\*(C'\fR, \f(CW\*(C`atmega406\*(C'\fR, \f(CW\*(C`atmega48hvf\*(C'\fR, \f(CW\*(C`atmega64\*(C'\fR, \f(CW\*(C`atmega64a\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64hve\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64rfa2\*(C'\fR, \f(CW\*(C`atmega64rfr2\*(C'\fR, \f(CW\*(C`atmega640\*(C'\fR, \f(CW\*(C`atmega644\*(C'\fR, \f(CW\*(C`atmega644a\*(C'\fR, \f(CW\*(C`atmega644p\*(C'\fR, \f(CW\*(C`atmega644pa\*(C'\fR, \f(CW\*(C`atmega645\*(C'\fR, \f(CW\*(C`atmega645a\*(C'\fR, \f(CW\*(C`atmega645p\*(C'\fR, \f(CW\*(C`atmega6450\*(C'\fR, \f(CW\*(C`atmega6450a\*(C'\fR, \f(CW\*(C`atmega6450p\*(C'\fR, \f(CW\*(C`atmega649\*(C'\fR, \f(CW\*(C`atmega649a\*(C'\fR, \f(CW\*(C`atmega649p\*(C'\fR, \f(CW\*(C`atmega6490\*(C'\fR, \f(CW\*(C`atmega6490a\*(C'\fR, \f(CW\*(C`atmega6490p\*(C'\fR, \f(CW\*(C`at90can32\*(C'\fR, \f(CW\*(C`at90can64\*(C'\fR, \f(CW\*(C`at90pwm161\*(C'\fR, \f(CW\*(C`at90pwm216\*(C'\fR, \f(CW\*(C`at90pwm316\*(C'\fR, \f(CW\*(C`at90scr100\*(C'\fR, \f(CW\*(C`at90usb646\*(C'\fR, \f(CW\*(C`at90usb647\*(C'\fR, \f(CW\*(C`at94k\*(C'\fR, \f(CW\*(C`m3000\*(C'\fR. .ie n .IP """avr51""" 4 .el .IP "\f(CWavr51\fR" 4 .IX Item "avr51" @@ -11043,7 +11067,7 @@ command-line option. .IX Item "-<Switch/case dispatch tables. If you do not want such dispatch>" tables you can specify the \fB\-fno\-jump\-tables\fR command-line option. .IP "\-<C and \*(C+ constructors/destructors called during startup/shutdown.>" 4 -.IX Item "-<C and constructors/destructors called during startup/shutdown.>" +.IX Item "-<C and constructors/destructors called during startup/shutdown.>" .PD 0 .ie n .IP "\-<If the tools hit a ""gs()"" modifier explained above.>" 4 .el .IP "\-<If the tools hit a \f(CWgs()\fR modifier explained above.>" 4 @@ -11790,7 +11814,7 @@ an executable when linking, using the Darwin \fIlibtool\fR command. This causes \s-1GCC\s0's output file to have the \fI\s-1ALL\s0\fR subtype, instead of one controlled by the \fB\-mcpu\fR or \fB\-march\fR option. .IP "\fB\-allowable_client\fR \fIclient_name\fR" 4 -.IX Item "-allowable_client client_name" +.IX Item "-allowable_client client_name" .PD 0 .IP "\fB\-client_name\fR" 4 .IX Item "-client_name" @@ -12865,9 +12889,14 @@ Intel Core i7 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SS Intel Core \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0 and F16C instruction set support. +.IP "\fBcore\-avx2\fR" 4 +.IX Item "core-avx2" +Intel Core \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AVX2\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, \s-1FMA\s0, \s-1BMI\s0, \s-1BMI2\s0 +and F16C instruction set support. .IP "\fBatom\fR" 4 .IX Item "atom" -Intel Atom \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 +Intel Atom \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 instruction set support. .IP "\fBk6\fR" 4 .IX Item "k6" @@ -16284,7 +16313,9 @@ following options: \&\fB\-maltivec \-mfprnd \-mhard\-float \-mmfcrf \-mmultiple \&\-mpopcntb \-mpopcntd \-mpowerpc64 \&\-mpowerpc\-gpopt \-mpowerpc\-gfxopt \-msingle\-float \-mdouble\-float -\&\-msimple\-fpu \-mstring \-mmulhw \-mdlmzb \-mmfpgpr \-mvsx\fR +\&\-msimple\-fpu \-mstring \-mmulhw \-mdlmzb \-mmfpgpr \-mvsx +\&\-mcrypto \-mdirect\-move \-mpower8\-fusion \-mpower8\-vector +\&\-mquad\-memory \-mquad\-memory\-atomic\fR .Sp The particular options set for any particular \s-1CPU\s0 varies between compiler versions, depending on what setting seems to produce optimal @@ -16331,6 +16362,36 @@ enable the use of built-in functions that allow more direct access to the AltiVec instruction set. You may also need to set \&\fB\-mabi=altivec\fR to adjust the current \s-1ABI\s0 with AltiVec \s-1ABI\s0 enhancements. +.Sp +When \fB\-maltivec\fR is used, rather than \fB\-maltivec=le\fR or +\&\fB\-maltivec=be\fR, the element order for Altivec intrinsics such +as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and \f(CW\*(C`vec_insert\*(C'\fR will +match array element order corresponding to the endianness of the +target. That is, element zero identifies the leftmost element in a +vector register when targeting a big-endian platform, and identifies +the rightmost element in a vector register when targeting a +little-endian platform. +.IP "\fB\-maltivec=be\fR" 4 +.IX Item "-maltivec=be" +Generate Altivec instructions using big-endian element order, +regardless of whether the target is big\- or little-endian. This is +the default when targeting a big-endian platform. +.Sp +The element order is used to interpret element numbers in Altivec +intrinsics such as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and +\&\f(CW\*(C`vec_insert\*(C'\fR. By default, these will match array element order +corresponding to the endianness for the target. +.IP "\fB\-maltivec=le\fR" 4 +.IX Item "-maltivec=le" +Generate Altivec instructions using little-endian element order, +regardless of whether the target is big\- or little-endian. This is +the default when targeting a little-endian platform. This option is +currently ignored when targeting a big-endian platform. +.Sp +The element order is used to interpret element numbers in Altivec +intrinsics such as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and +\&\f(CW\*(C`vec_insert\*(C'\fR. By default, these will match array element order +corresponding to the endianness for the target. .IP "\fB\-mvrsave\fR" 4 .IX Item "-mvrsave" .PD 0 @@ -16399,6 +16460,61 @@ This option has been deprecated. Use \fB\-mspe\fR and Generate code that uses (does not use) vector/scalar (\s-1VSX\s0) instructions, and also enable the use of built-in functions that allow more direct access to the \s-1VSX\s0 instruction set. +.IP "\fB\-mcrypto\fR" 4 +.IX Item "-mcrypto" +.PD 0 +.IP "\fB\-mno\-crypto\fR" 4 +.IX Item "-mno-crypto" +.PD +Enable the use (disable) of the built-in functions that allow direct +access to the cryptographic instructions that were added in version +2.07 of the PowerPC \s-1ISA\s0. +.IP "\fB\-mdirect\-move\fR" 4 +.IX Item "-mdirect-move" +.PD 0 +.IP "\fB\-mno\-direct\-move\fR" 4 +.IX Item "-mno-direct-move" +.PD +Generate code that uses (does not use) the instructions to move data +between the general purpose registers and the vector/scalar (\s-1VSX\s0) +registers that were added in version 2.07 of the PowerPC \s-1ISA\s0. +.IP "\fB\-mpower8\-fusion\fR" 4 +.IX Item "-mpower8-fusion" +.PD 0 +.IP "\fB\-mno\-power8\-fusion\fR" 4 +.IX Item "-mno-power8-fusion" +.PD +Generate code that keeps (does not keeps) some integer operations +adjacent so that the instructions can be fused together on power8 and +later processors. +.IP "\fB\-mpower8\-vector\fR" 4 +.IX Item "-mpower8-vector" +.PD 0 +.IP "\fB\-mno\-power8\-vector\fR" 4 +.IX Item "-mno-power8-vector" +.PD +Generate code that uses (does not use) the vector and scalar +instructions that were added in version 2.07 of the PowerPC \s-1ISA\s0. Also +enable the use of built-in functions that allow more direct access to +the vector instructions. +.IP "\fB\-mquad\-memory\fR" 4 +.IX Item "-mquad-memory" +.PD 0 +.IP "\fB\-mno\-quad\-memory\fR" 4 +.IX Item "-mno-quad-memory" +.PD +Generate code that uses (does not use) the non-atomic quad word memory +instructions. The \fB\-mquad\-memory\fR option requires use of +64\-bit mode. +.IP "\fB\-mquad\-memory\-atomic\fR" 4 +.IX Item "-mquad-memory-atomic" +.PD 0 +.IP "\fB\-mno\-quad\-memory\-atomic\fR" 4 +.IX Item "-mno-quad-memory-atomic" +.PD +Generate code that uses (does not use) the atomic quad word memory +instructions. The \fB\-mquad\-memory\-atomic\fR option requires use of +64\-bit mode. .IP "\fB\-mfloat\-gprs=\fR\fIyes/single/double/no\fR" 4 .IX Item "-mfloat-gprs=yes/single/double/no" .PD 0 @@ -16828,7 +16944,8 @@ Return structures smaller than 8 bytes in registers (as specified by the .IX Item "-mabi=abi-type" Extend the current \s-1ABI\s0 with a particular extension, or remove such extension. Valid values are \fIaltivec\fR, \fIno-altivec\fR, \fIspe\fR, -\&\fIno-spe\fR, \fIibmlongdouble\fR, \fIieeelongdouble\fR. +\&\fIno-spe\fR, \fIibmlongdouble\fR, \fIieeelongdouble\fR, +\&\fIelfv1\fR, \fIelfv2\fR. .IP "\fB\-mabi=spe\fR" 4 .IX Item "-mabi=spe" Extend the current \s-1ABI\s0 with \s-1SPE\s0 \s-1ABI\s0 extensions. This does not change @@ -16845,6 +16962,18 @@ This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. .IX Item "-mabi=ieeelongdouble" Change the current \s-1ABI\s0 to use \s-1IEEE\s0 extended-precision long double. This is a PowerPC 32\-bit Linux \s-1ABI\s0 option. +.IP "\fB\-mabi=elfv1\fR" 4 +.IX Item "-mabi=elfv1" +Change the current \s-1ABI\s0 to use the ELFv1 \s-1ABI\s0. +This is the default \s-1ABI\s0 for big-endian PowerPC 64\-bit Linux. +Overriding the default \s-1ABI\s0 requires special system support and is +likely to fail in spectacular ways. +.IP "\fB\-mabi=elfv2\fR" 4 +.IX Item "-mabi=elfv2" +Change the current \s-1ABI\s0 to use the ELFv2 \s-1ABI\s0. +This is the default \s-1ABI\s0 for little-endian PowerPC 64\-bit Linux. +Overriding the default \s-1ABI\s0 requires special system support and is +likely to fail in spectacular ways. .IP "\fB\-mprototype\fR" 4 .IX Item "-mprototype" .PD 0 @@ -17132,6 +17261,25 @@ stack location in the function prologue if the function calls through a pointer on \s-1AIX\s0 and 64\-bit Linux systems. If the \s-1TOC\s0 value is not saved in the prologue, it is saved just before the call through the pointer. The \fB\-mno\-save\-toc\-indirect\fR option is the default. +.IP "\fB\-mcompat\-align\-parm\fR" 4 +.IX Item "-mcompat-align-parm" +.PD 0 +.IP "\fB\-mno\-compat\-align\-parm\fR" 4 +.IX Item "-mno-compat-align-parm" +.PD +Generate (do not generate) code to pass structure parameters with a +maximum alignment of 64 bits, for compatibility with older versions +of \s-1GCC\s0. +.Sp +Older versions of \s-1GCC\s0 (prior to 4.9.0) incorrectly did not align a +structure parameter on a 128\-bit boundary when that structure contained +a member requiring 128\-bit alignment. This is corrected in more +recent versions of \s-1GCC\s0. This option may be used to generate code +that is compatible with functions compiled with older versions of +\&\s-1GCC\s0. +.Sp +In this version of the compiler, the \fB\-mcompat\-align\-parm\fR +is the default, except when using the Linux ELFv2 \s-1ABI\s0. .PP \fI\s-1RX\s0 Options\fR .IX Subsection "RX Options" @@ -17514,6 +17662,23 @@ values have to be exact powers of 2 and \fIstack-size\fR has to be greater than In order to be efficient the extra code makes the assumption that the stack starts at an address aligned to the value given by \fIstack-size\fR. The \fIstack-guard\fR option can only be used in conjunction with \fIstack-size\fR. +.IP "\fB\-mhotpatch[=\fR\fIhalfwords\fR\fB]\fR" 4 +.IX Item "-mhotpatch[=halfwords]" +.PD 0 +.IP "\fB\-mno\-hotpatch\fR" 4 +.IX Item "-mno-hotpatch" +.PD +If the hotpatch option is enabled, a \*(L"hot-patching\*(R" function +prologue is generated for all functions in the compilation unit. +The funtion label is prepended with the given number of two-byte +Nop instructions (\fIhalfwords\fR, maximum 1000000) or 12 Nop +instructions if no argument is present. Functions with a +hot-patching prologue are never inlined automatically, and a +hot-patching prologue is never generated for functions functions +that are explicitly inline. +.Sp +This option can be overridden for individual functions with the +\&\f(CW\*(C`hotpatch\*(C'\fR attribute. .PP \fIScore Options\fR .IX Subsection "Score Options" @@ -18039,8 +18204,9 @@ These \fB\-m\fR options are supported on the \s-1SPARC:\s0 .IX Item "-mapp-regs" .PD Specify \fB\-mapp\-regs\fR to generate output using the global registers -2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. This -is the default. +2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. Like the +global register 1, each global register 2 through 4 is then treated as an +allocable register that is clobbered by function calls. This is the default. .Sp To be fully \s-1SVR4\s0 ABI-compliant at the cost of some performance loss, specify \fB\-mno\-app\-regs\fR. You should compile libraries and system @@ -18116,6 +18282,15 @@ absolute address. Otherwise, it assumes they have 4\-byte alignment. Specifying this option avoids some rare compatibility problems with code generated by other compilers. It is not the default because it results in a performance loss, especially for floating-point code. +.IP "\fB\-muser\-mode\fR" 4 +.IX Item "-muser-mode" +.PD 0 +.IP "\fB\-mno\-user\-mode\fR" 4 +.IX Item "-mno-user-mode" +.PD +Do not generate code that can only run in supervisor mode. This is relevant +only for the \f(CW\*(C`casa\*(C'\fR instruction emitted for the \s-1LEON3\s0 processor. The +default is \fB\-mno\-user\-mode\fR. .IP "\fB\-mno\-faster\-structs\fR" 4 .IX Item "-mno-faster-structs" .PD 0 @@ -18135,10 +18310,10 @@ the rules of the \s-1ABI\s0. Set the instruction set, register set, and instruction scheduling parameters for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are \&\fBv7\fR, \fBcypress\fR, \fBv8\fR, \fBsupersparc\fR, \fBhypersparc\fR, -\&\fBleon\fR, \fBsparclite\fR, \fBf930\fR, \fBf934\fR, \fBsparclite86x\fR, -\&\fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, \fBultrasparc\fR, -\&\fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR, -and \fBniagara4\fR. +\&\fBleon\fR, \fBleon3\fR, \fBsparclite\fR, \fBf930\fR, \fBf934\fR, +\&\fBsparclite86x\fR, \fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, +\&\fBultrasparc\fR, \fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, +\&\fBniagara3\fR and \fBniagara4\fR. .Sp Native Solaris and GNU/Linux toolchains also support the value \fBnative\fR, which selects the best architecture option for the host processor. @@ -18157,7 +18332,7 @@ implementations. cypress .IP "v8" 4 .IX Item "v8" -supersparc, hypersparc, leon +supersparc, hypersparc, leon, leon3 .IP "sparclite" 4 .IX Item "sparclite" f930, f934, sparclite86x @@ -18220,10 +18395,11 @@ option \fB\-mcpu=\fR\fIcpu_type\fR does. The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for \&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those that select a particular \s-1CPU\s0 implementation. Those are \fBcypress\fR, -\&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBf930\fR, \fBf934\fR, -\&\fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, \fBultrasparc3\fR, -\&\fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR and \fBniagara4\fR. With -native Solaris and GNU/Linux toolchains, \fBnative\fR can also be used. +\&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBleon3\fR, \fBf930\fR, +\&\fBf934\fR, \fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, +\&\fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR and +\&\fBniagara4\fR. With native Solaris and GNU/Linux toolchains, \fBnative\fR +can also be used. .IP "\fB\-mv8plus\fR" 4 .IX Item "-mv8plus" .PD 0 @@ -18298,6 +18474,10 @@ later. .IX Item "-mfix-at697f" Enable the documented workaround for the single erratum of the Atmel \s-1AT697F\s0 processor (which corresponds to erratum #13 of the \s-1AT697E\s0 processor). +.IP "\fB\-mfix\-ut699\fR" 4 +.IX Item "-mfix-ut699" +Enable the documented workarounds for the floating-point errata and the data +cache nullify errata of the \s-1UT699\s0 processor. .PP These \fB\-m\fR options are supported in addition to the above on \s-1SPARC\-V9\s0 processors in 64\-bit environments: @@ -18977,7 +19157,7 @@ every cross-file call, not just those that really are out of range. .IX Subsection "zSeries Options" .PP These are listed under -.SS "Options for Code Generation Conventions" +.Sh "Options for Code Generation Conventions" .IX Subsection "Options for Code Generation Conventions" These machine-independent options control the interface conventions used in code generation. |