diff options
Diffstat (limited to 'gcc-4.8/gcc/config/i386/driver-i386.c')
| -rw-r--r-- | gcc-4.8/gcc/config/i386/driver-i386.c | 63 |
1 files changed, 41 insertions, 22 deletions
diff --git a/gcc-4.8/gcc/config/i386/driver-i386.c b/gcc-4.8/gcc/config/i386/driver-i386.c index 763758495..148fbc227 100644 --- a/gcc-4.8/gcc/config/i386/driver-i386.c +++ b/gcc-4.8/gcc/config/i386/driver-i386.c @@ -126,6 +126,18 @@ decode_caches_intel (unsigned reg, bool xeon_mp, case 0x0c: level1->sizekb = 16; level1->assoc = 4; level1->line = 32; break; + case 0x0d: + level1->sizekb = 16; level1->assoc = 4; level1->line = 64; + break; + case 0x0e: + level1->sizekb = 24; level1->assoc = 6; level1->line = 64; + break; + case 0x21: + level2->sizekb = 256; level2->assoc = 8; level2->line = 64; + break; + case 0x24: + level2->sizekb = 1024; level2->assoc = 16; level2->line = 64; + break; case 0x2c: level1->sizekb = 32; level1->assoc = 8; level1->line = 64; break; @@ -162,6 +174,9 @@ decode_caches_intel (unsigned reg, bool xeon_mp, case 0x45: level2->sizekb = 2048; level2->assoc = 4; level2->line = 32; break; + case 0x48: + level2->sizekb = 3072; level2->assoc = 12; level2->line = 64; + break; case 0x49: if (xeon_mp) break; @@ -203,6 +218,9 @@ decode_caches_intel (unsigned reg, bool xeon_mp, case 0x7f: level2->sizekb = 512; level2->assoc = 2; level2->line = 64; break; + case 0x80: + level2->sizekb = 512; level2->assoc = 8; level2->line = 64; + break; case 0x82: level2->sizekb = 256; level2->assoc = 8; level2->line = 32; break; @@ -470,6 +488,28 @@ const char *host_detect_local_cpu (int argc, const char **argv) has_xsaveopt = eax & bit_XSAVEOPT; } + /* Check cpuid level of extended features. */ + __cpuid (0x80000000, ext_level, ebx, ecx, edx); + + if (ext_level > 0x80000000) + { + __cpuid (0x80000001, eax, ebx, ecx, edx); + + has_lahf_lm = ecx & bit_LAHF_LM; + has_sse4a = ecx & bit_SSE4a; + has_abm = ecx & bit_ABM; + has_lwp = ecx & bit_LWP; + has_fma4 = ecx & bit_FMA4; + has_xop = ecx & bit_XOP; + has_tbm = ecx & bit_TBM; + has_lzcnt = ecx & bit_LZCNT; + has_prfchw = ecx & bit_PRFCHW; + + has_longmode = edx & bit_LM; + has_3dnowp = edx & bit_3DNOWP; + has_3dnow = edx & bit_3DNOW; + } + /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */ #define XCR_XFEATURE_ENABLED_MASK 0x0 #define XSTATE_FP 0x1 @@ -488,33 +528,12 @@ const char *host_detect_local_cpu (int argc, const char **argv) has_avx2 = 0; has_fma = 0; has_fma4 = 0; + has_f16c = 0; has_xop = 0; has_xsave = 0; has_xsaveopt = 0; } - /* Check cpuid level of extended features. */ - __cpuid (0x80000000, ext_level, ebx, ecx, edx); - - if (ext_level > 0x80000000) - { - __cpuid (0x80000001, eax, ebx, ecx, edx); - - has_lahf_lm = ecx & bit_LAHF_LM; - has_sse4a = ecx & bit_SSE4a; - has_abm = ecx & bit_ABM; - has_lwp = ecx & bit_LWP; - has_fma4 = ecx & bit_FMA4; - has_xop = ecx & bit_XOP; - has_tbm = ecx & bit_TBM; - has_lzcnt = ecx & bit_LZCNT; - has_prfchw = ecx & bit_PRFCHW; - - has_longmode = edx & bit_LM; - has_3dnowp = edx & bit_3DNOWP; - has_3dnow = edx & bit_3DNOW; - } - if (!arch) { if (vendor == signature_AMD_ebx |