4300 files changed, 130510 insertions, 0 deletions

diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/20000715-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/20000715-1.c
new file mode 100644
index 000000000..ce06d0817
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/20000715-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile { target alpha*-*-* } } */
+/* { dg-options "-O2 -mieee" } */
+
+float foo(unsigned char n)
+{
+  float r = 10 * n;
+  asm volatile("" : : : "memory");
+  return r;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/20011018-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/20011018-1.c
new file mode 100644
index 000000000..aed5d327d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/20011018-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target alpha*-*-* } } */
+/* { dg-options "-O2 -mieee" } */
+
+double foo (void);
+void bar (float, float);
+
+void test (void)
+{
+  float f, g;
+
+  f = foo();
+  g = foo();
+  asm ("");
+  bar (f, g);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/980217-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/980217-1.c
new file mode 100644
index 000000000..ad261eb7d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/980217-1.c
@@ -0,0 +1,39 @@
+/* Test float on alpha. */
+
+/* { dg-do run { target alpha*-*-* } } */
+/* { dg-options "-mieee -O2" } */
+
+extern void abort(void);
+extern int printf(const char *, ...);
+
+typedef int int32_t __attribute__ ((__mode__ (  __SI__ ))) ;
+typedef union
+{
+  float value;
+  int32_t word;
+} ieee_float_shape_type;
+
+int isinff(float x)
+{
+  int32_t ix,t;
+  ieee_float_shape_type gf_u;
+  gf_u.value = x;
+  ix = gf_u.word;
+  printf ("%x\n", ix);
+  t = ix & 0x7fffffff;
+  t ^= 0x7f800000;
+  t |= -t;
+  return ~(t >> 31) & (1 - ((ix & 0x80000000) >> 30));
+}
+
+main ()
+{
+  float x = 1.0 / 0.0;
+  int i = isinff (x);
+
+  if (i == 0)
+    abort ();
+
+  printf ("%d\n", i);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/alpha.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/alpha.exp
new file mode 100644
index 000000000..edd8d68c1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/alpha.exp
@@ -0,0 +1,41 @@
+#   Copyright (C) 2005, 2007 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an Alpha target.
+if ![istarget alpha*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/asm-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/asm-1.c
new file mode 100644
index 000000000..7b8d0f2f6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/asm-1.c
@@ -0,0 +1,82 @@
+/* Asm operands that are given as hard registers must keep the same
+   hard register all the way through compilation.  Example derived
+   from glibc source.  */
+/* { dg-do compile { target alpha*-*-* } } */
+/* { dg-options "-O2 -frename-registers -fcprop-registers" } */
+/* { dg-final { scan-assembler "callsys1 .0 .19 .0 .16 .17" } } */
+/* { dg-final { scan-assembler "callsys2 .0 .19 .0 .16 .17" } } */
+
+struct stat {
+  int dummy;
+};
+
+struct kernel_stat {
+  int dummy;
+};
+
+extern int xstat_conv (int vers, struct kernel_stat *kbuf, void *ubuf);
+extern int *__errno_location (void) __attribute__ ((__const__));
+
+int
+__fxstat (int vers, int fd, struct stat *buf)
+{
+  struct kernel_stat kbuf;
+  int result;
+
+  if (vers == 0)
+    return
+      ({
+	long _sc_ret, _sc_err;
+	{
+	  register long _sc_0 __asm__("$0");
+	  register long _sc_16 __asm__("$16");
+	  register long _sc_17 __asm__("$17");
+	  register long _sc_19 __asm__("$19");
+	  _sc_0 = 91;
+	  _sc_16 = (long) (fd);
+	  _sc_17 = (long) (((struct kernel_stat *) buf));
+	  __asm__("callsys1 %0 %1 %2 %3 %4"
+		  : "=r"(_sc_0), "=r"(_sc_19)
+		  : "0"(_sc_0), "r"(_sc_16), "r"(_sc_17)
+		  : "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8",
+		    "$22", "$23", "$24", "$25", "$27", "$28", "memory");
+	  _sc_ret = _sc_0, _sc_err = _sc_19;
+	}
+	if (_sc_err)
+	  {
+	    (*__errno_location ()) = (_sc_ret);
+	    _sc_ret = -1L;
+	  }
+	_sc_ret;
+      });
+
+  result =
+      ({
+	long _sc_ret, _sc_err;
+	{
+	  register long _sc_0 __asm__("$0");
+	  register long _sc_16 __asm__("$16");
+	  register long _sc_17 __asm__("$17");
+	  register long _sc_19 __asm__("$19");
+	  _sc_0 = 91;
+	  _sc_16 = (long) (fd);
+	  _sc_17 = (long) ((&kbuf));
+	  __asm__("callsys2 %0 %1 %2 %3 %4"
+		  : "=r"(_sc_0), "=r"(_sc_19)
+		  : "0"(_sc_0), "r"(_sc_16), "r"(_sc_17)
+		  : "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8",
+		    "$22", "$23", "$24", "$25", "$27", "$28", "memory");
+	  _sc_ret = _sc_0, _sc_err = _sc_19;
+	}
+	if (_sc_err)
+	  {
+	    (*__errno_location ()) = (_sc_ret);
+	    _sc_ret = -1L;
+	  }
+	_sc_ret;
+      });
+  if (result == 0)
+    result = xstat_conv (vers, &kbuf, buf);
+
+  return result;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/base-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/base-1.c
new file mode 100644
index 000000000..542ed6bc6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/base-1.c
@@ -0,0 +1,73 @@
+/* Test that the base isa builtins compile.  */
+/* { dg-do link { target alpha*-*-* } } */
+/* { dg-options "-mcpu=ev4" } */
+
+void test_BASE (long x, long y)
+{
+  volatile long sink;
+  long z;
+
+  sink = __builtin_alpha_implver ();
+  sink = __builtin_alpha_rpcc ();
+
+  sink = __builtin_alpha_amask (-1);
+  sink = __builtin_alpha_amask (x);
+
+  sink = __builtin_alpha_cmpbge (x, y);
+  sink = __builtin_alpha_cmpbge (-1, x);
+
+  sink = __builtin_alpha_extbl (x, y);
+  sink = __builtin_alpha_extwl (x, y);
+  sink = __builtin_alpha_extll (x, y);
+  sink = __builtin_alpha_extql (x, y);
+  sink = __builtin_alpha_extwh (x, y);
+  sink = __builtin_alpha_extlh (x, y);
+  sink = __builtin_alpha_extqh (x, y);
+
+  sink = __builtin_alpha_insbl (x, y);
+  sink = __builtin_alpha_inswl (x, y);
+  sink = __builtin_alpha_insll (x, y);
+  sink = __builtin_alpha_insql (x, y);
+  sink = __builtin_alpha_inswh (x, y);
+  sink = __builtin_alpha_inslh (x, y);
+  sink = __builtin_alpha_insqh (x, y);
+
+  sink = __builtin_alpha_mskbl (x, y);
+  sink = __builtin_alpha_mskwl (x, y);
+  sink = __builtin_alpha_mskll (x, y);
+  sink = __builtin_alpha_mskql (x, y);
+  sink = __builtin_alpha_mskwh (x, y);
+  sink = __builtin_alpha_msklh (x, y);
+  sink = __builtin_alpha_mskqh (x, y);
+
+  sink = __builtin_alpha_umulh (x, y);
+}
+
+void test_zap (long x, long y)
+{
+  volatile long sink;
+  long z;
+  sink = __builtin_alpha_zap (x, y);
+  sink = __builtin_alpha_zap (x, 0xaa);
+  z = 0xaa;
+  sink = __builtin_alpha_zap (x, z);
+  z = 0;
+  sink = __builtin_alpha_zap (z, x);
+  sink = __builtin_alpha_zap (x, z);
+}
+
+void test_zapnot (long x, long y)
+{
+  volatile long sink;
+  long z;
+
+  sink = __builtin_alpha_zapnot (x, y);
+  sink = __builtin_alpha_zapnot (x, 0xaa);
+  z = 0xaa;
+  sink = __builtin_alpha_zapnot (x, z);
+  z = 0;
+  sink = __builtin_alpha_zapnot (z, x);
+  sink = __builtin_alpha_zapnot (x, z);
+}
+
+int main() { return 0; }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/base-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/base-2.c
new file mode 100644
index 000000000..22a34f044
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/base-2.c
@@ -0,0 +1,5 @@
+/* Test that alpha-base-1.c compiles with optimization.  */
+/* { dg-do link { target alpha*-*-* } } */
+/* { dg-options "-mcpu=ev4 -O2" } */
+
+#include "base-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/cix-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/cix-1.c
new file mode 100644
index 000000000..c52befb1b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/cix-1.c
@@ -0,0 +1,14 @@
+/* Test that the CIX isa builtins compile.  */
+/* { dg-do link { target alpha*-*-* } } */
+/* { dg-options "-mcpu=ev67" } */
+
+void test_CIX (long x)
+{
+  volatile long sink;
+
+  sink = __builtin_alpha_cttz (x);
+  sink = __builtin_alpha_ctlz (x);
+  sink = __builtin_alpha_ctpop (x);
+}
+
+int main() { return 0; }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/cix-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/cix-2.c
new file mode 100644
index 000000000..b20b50610
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/cix-2.c
@@ -0,0 +1,5 @@
+/* Test that alpha-cix-1.c compiles with optimization.  */
+/* { dg-do link { target alpha*-*-* } } */
+/* { dg-options "-mcpu=ev67 -O2" } */
+
+#include "cix-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/max-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/max-1.c
new file mode 100644
index 000000000..b73bbb9a2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/max-1.c
@@ -0,0 +1,27 @@
+/* Test that the MAX isa builtins compile.  */
+/* { dg-do link { target alpha*-*-* } } */
+/* { dg-options "-mcpu=pca56" } */
+
+void test_MAX (long x, long y)
+{
+  volatile long sink;
+
+  sink = __builtin_alpha_pklb (x);
+  sink = __builtin_alpha_pkwb (x);
+  sink = __builtin_alpha_unpkbl (x);
+  sink = __builtin_alpha_unpkbw (x);
+
+  sink = __builtin_alpha_minub8 (0, x);
+  sink = __builtin_alpha_minub8 (1, x);
+  sink = __builtin_alpha_minub8 (x, y);
+  sink = __builtin_alpha_minsb8 (x, y);
+  sink = __builtin_alpha_minuw4 (x, y);
+  sink = __builtin_alpha_minsw4 (x, y);
+  sink = __builtin_alpha_maxub8 (x, y);
+  sink = __builtin_alpha_maxsb8 (x, y);
+  sink = __builtin_alpha_maxuw4 (x, y);
+  sink = __builtin_alpha_maxsw4 (x, y);
+  sink = __builtin_alpha_perr (x, y);
+}
+
+int main() { return 0; }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/max-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/max-2.c
new file mode 100644
index 000000000..90b4f8c04
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/max-2.c
@@ -0,0 +1,5 @@
+/* Test that alpha-max-1.c compiles with optimization.  */
+/* { dg-do link { target alpha*-*-* } } */
+/* { dg-options "-mcpu=pca56 -O2" } */
+
+#include "max-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr19518.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr19518.c
new file mode 100644
index 000000000..42c58b5a5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr19518.c
@@ -0,0 +1,60 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ev67" } */
+
+typedef short INT16;
+typedef unsigned int CARD32;
+typedef unsigned short CARD16;
+typedef unsigned char CARD8;
+typedef struct _Picture *PicturePtr;
+typedef int FbStride;
+typedef unsigned long __m64;
+extern __m64 load8888 (__m64);
+static __inline __m64 _mm_adds_pu8(__m64 __m1, __m64 __m2)
+{
+    return __m1 + __builtin_alpha_minsb8(__m2, ~__m1);
+}
+static __inline __m64 _mm_packs_pu16(__m64 __m1, __m64 __m2)
+{
+    __m1 = __builtin_alpha_minuw4(__m1, 0x00ff00ff00ff00ff);
+    __m2 = __builtin_alpha_minuw4(__m2, 0x00ff00ff00ff00ff);
+    return __m1 | (__m2 << 32);
+}
+typedef unsigned long long ullong;
+static __inline__ __m64 pix_multiply(__m64 a)
+{
+    if (a)
+	return a;
+}
+static __inline__ __m64 over(__m64 src, __m64 srca, __m64 dest)
+{
+    return _mm_adds_pu8(src, pix_multiply(dest));
+}
+
+void fbCompositeSolid_nx8888mmx(CARD8 op, PicturePtr pSrc, PicturePtr pMask,
+				INT16 yDst, CARD16 width, CARD16 height)
+{
+    CARD32 src;
+    CARD32 *dstLine, *dst;
+    CARD16 w;
+    FbStride dstStride;
+    __m64 vsrc, vsrca;
+    vsrc = load8888(src);
+    while (height--) {
+	dst = dstLine;
+	dstLine += dstStride;
+	while (w && (unsigned long) dst & 7) {
+	    *dst = _mm_packs_pu16(_mm_adds_pu8(vsrc, load8888(*dst)),
+				  _mm_setzero_si64());
+	    dst++;
+	}
+	while (w >= 2) {
+	    __m64 dest0, dest1;
+	    *(__m64 *) dst = _mm_packs_pu16(dest0, dest1);
+	    w -= 2;
+	}
+	while (w) {
+	    *dst = _mm_packs_pu16(_mm_adds_pu8(vsrc, pix_multiply(0)), 0);
+	    w--;
+	}
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr22093.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr22093.c
new file mode 100644
index 000000000..aa00e1550
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr22093.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct shared_ptr_struct
+{
+  unsigned long phase : 48;
+  unsigned thread : 16;
+  void *addr;
+} x;
+
+void foo (void)
+{
+   x.thread = 2;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr24178.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr24178.c
new file mode 100644
index 000000000..0a31aa736
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr24178.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ev4" } */
+
+struct S {
+    long l;
+    unsigned char c;
+};
+unsigned long f(unsigned char *p10) {
+    struct S *p = (struct S *) (p10 + 10);
+    return p->c;
+}
+
+/* { dg-final { scan-assembler "ldl.*,18\\(" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr39740.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr39740.c
new file mode 100644
index 000000000..230beb7db
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr39740.c
@@ -0,0 +1,162 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -std=c99 -mexplicit-relocs" } */
+
+typedef int R_len_t;
+typedef unsigned int SEXPTYPE;
+struct sxpinfo_struct
+{
+  SEXPTYPE type:5;
+};
+
+struct vecsxp_struct
+{
+  R_len_t length;
+  R_len_t truelength;
+};
+
+struct listsxp_struct
+{
+  struct SEXPREC *carval;
+  struct SEXPREC *cdrval;
+  struct SEXPREC *tagval;
+};
+
+typedef struct SEXPREC
+{
+  struct sxpinfo_struct sxpinfo;
+  union
+  {
+    struct listsxp_struct listsxp;
+  } u;
+} SEXPREC, *SEXP;
+
+typedef struct VECTOR_SEXPREC
+{
+  struct vecsxp_struct vecsxp;
+} VECTOR_SEXPREC, *VECSEXP;
+
+typedef union
+{
+  VECTOR_SEXPREC s;
+  double align;
+} SEXPREC_ALIGN;
+
+extern SEXP R_NilValue;
+extern SEXP R_MissingArg;
+
+int Rf_envlength (SEXP rho);
+SEXP Rf_protect (SEXP);
+const char *Rf_translateChar (SEXP);
+
+inline R_len_t
+Rf_length (SEXP s)
+{
+  int i;
+  switch (((s)->sxpinfo.type))
+    {
+    case 0:
+      return 0;
+    case 24:
+      return (((VECSEXP) (s))->vecsxp.length);
+    case 6:
+    case 17:
+      i = 0;
+      while (s != ((void *) 0) && s != R_NilValue)
+	{
+	  i++;
+	  s = ((s)->u.listsxp.cdrval);
+	}
+      return i;
+    case 4:
+      return Rf_envlength (s);
+    default:
+      return 1;
+    }
+}
+
+inline SEXP
+Rf_lang3 (SEXP s, SEXP t, SEXP u)
+{
+  return s;
+}
+
+typedef SEXP (*CCODE) (SEXP, SEXP, SEXP, SEXP);
+
+static SEXP PlusSymbol;
+static SEXP MinusSymbol;
+static SEXP DivideSymbol;
+
+int isZero (SEXP s);
+SEXP PP (SEXP s);
+SEXP AddParens (SEXP expr);
+SEXP Rf_install ();
+
+static int
+isUminus (SEXP s)
+{
+  if (((s)->sxpinfo.type) == 6 && ((s)->u.listsxp.carval) == MinusSymbol)
+    {
+      switch (Rf_length (s))
+	{
+	case 2:
+	  return 1;
+	case 3:
+	  if (((((((s)->u.listsxp.cdrval))->u.listsxp.cdrval))->u.listsxp.
+	       carval) == R_MissingArg)
+	    return 1;
+	  else
+	    return 0;
+	}
+    }
+  else
+    return 0;
+}
+
+static SEXP
+simplify (SEXP fun, SEXP arg1, SEXP arg2)
+{
+  SEXP ans;
+  if (fun == PlusSymbol)
+    {
+      if (isZero (arg1))
+	ans = arg2;
+      else if (isUminus (arg1))
+	ans =
+	  simplify (MinusSymbol, arg2,
+		    ((((arg1)->u.listsxp.cdrval))->u.listsxp.carval));
+      else if (isUminus (arg2))
+	ans =
+	  simplify (MinusSymbol, arg1,
+		    ((((arg2)->u.listsxp.cdrval))->u.listsxp.carval));
+    }
+  else if (fun == DivideSymbol)
+    {
+      ans = Rf_lang3 (DivideSymbol, arg1, arg2);
+    }
+
+  return ans;
+}
+
+
+static SEXP
+D (SEXP expr, SEXP var)
+{
+  return simplify (PlusSymbol,
+		   PP (D
+		       (((((expr)->u.listsxp.cdrval))->u.listsxp.carval),
+			var)),
+		   PP (D
+		       (((((((expr)->u.listsxp.cdrval))->u.listsxp.cdrval))->
+			 u.listsxp.carval), var)));
+}
+
+SEXP
+do_D (SEXP call, SEXP op, SEXP args, SEXP env)
+{
+  SEXP expr, var;
+  var = Rf_install ();
+  expr = ((args)->u.listsxp.carval);
+  Rf_protect (expr = D (expr, var));
+  expr = AddParens (expr);
+  return expr;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr42113.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr42113.c
new file mode 100644
index 000000000..228c14abb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr42113.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int foo (int a, int b)
+{
+  int bar = a * sizeof (int);
+
+  if (b)
+    bar += sizeof (int);
+
+  return bar;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr42448-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr42448-1.c
new file mode 100644
index 000000000..4e2c376e3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr42448-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-mcpu=21064 -O0" } */
+
+extern void abort (void);
+
+struct S2180
+{
+  char t;
+  _Complex char u[2];
+};
+
+struct S2180 s2180;
+
+int
+main (void)
+{
+  volatile struct S2180 x;
+
+  s2180.u[1] = 3 + 4i;
+
+  x.u[1] = s2180.u[1];
+
+  if (x.u[1] != s2180.u[1])
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr42448-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr42448-2.c
new file mode 100644
index 000000000..aeebad280
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr42448-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-mcpu=21064 -O0" } */
+
+extern void abort (void);
+
+struct S2180
+{
+  char t;
+  _Complex char u[4];
+};
+
+struct S2180 s2180;
+
+int
+main (void)
+{
+  volatile struct S2180 x;
+
+  s2180.u[3] = 3 + 4i;
+
+  x.u[3] = s2180.u[3];
+
+  if (x.u[3] != s2180.u[3])
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr42774.c b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr42774.c
new file mode 100644
index 000000000..65688002b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/alpha/pr42774.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ev4" } */
+
+unsigned int ntfs_getinfo(void *p)
+{
+    char bootsect[8];
+
+    __builtin_memcpy(bootsect, p, sizeof bootsect);
+    return *(unsigned short *)(bootsect + 3);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/20030909-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/20030909-1.c
new file mode 100644
index 000000000..4ed3640b5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/20030909-1.c
@@ -0,0 +1,5 @@
+/* Verify that ands are combined.  */
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+/* { dg-final { scan-assembler-not "#255.*#255" } } */
+int f(int a, int b) { return ((a & 0xff) + (b & 0xff)) & 0xff; }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/20031108-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/20031108-1.c
new file mode 100644
index 000000000..6573d2b10
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/20031108-1.c
@@ -0,0 +1,35 @@
+/* PR optimization/10467  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mthumb" } */
+
+typedef enum {Ident_1} Enumeration;
+
+typedef struct record
+{
+    struct record *Ptr_Comp;
+    Enumeration Discr;
+    union {
+	struct {
+	    Enumeration Enum_Comp;
+	    int Int_Comp;
+	    char Str_Comp [31];
+        } var_1;
+    } variant;
+} *Rec_Pointer;
+
+Rec_Pointer Ptr_Glob;
+
+Proc_1 (Ptr_Val_Par)
+    Rec_Pointer Ptr_Val_Par;
+{
+    Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;
+
+    *Ptr_Val_Par->Ptr_Comp = *Ptr_Glob;
+
+    if (Next_Record->Discr == Ident_1)
+    {
+	Proc_7 (Next_Record->variant.var_1.Int_Comp, 10,
+		&Next_Record->variant.var_1.Int_Comp);
+    }
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/20051215-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/20051215-1.c
new file mode 100644
index 000000000..0519dc7ce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/20051215-1.c
@@ -0,0 +1,36 @@
+/* ARM's load-and-call patterns used to allow automodified addresses.
+   This was wrong, because if the modified register were spilled,
+   the call would need an output reload.  */
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-omit-frame-pointer" } */
+extern void abort (void);
+typedef void (*callback) (void);
+
+static void
+foo (callback *first, callback *p)
+{
+  while (p > first)
+    {
+      (*--p) ();
+#ifndef __thumb__
+      asm ("" : "=r" (p) : "0" (p)
+	   : "r4", "r5", "r6", "r7", "r8", "r9", "r10");
+#endif
+    }   
+}
+
+static void
+dummy (void)
+{
+  static int count;
+  if (count++ == 1)
+    abort ();
+}
+
+int
+main (void)
+{
+  callback list[1] = { dummy };
+  foo (&list[0], &list[1]);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/arm.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/arm.exp
new file mode 100644
index 000000000..0838d37b3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/arm.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 1997, 2004, 2006, 2007 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an ARM target.
+if ![istarget arm*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/asm.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/asm.c
new file mode 100644
index 000000000..452ebf4de
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/asm.c
@@ -0,0 +1,13 @@
+/* ARM and Thumb asm statements should be able to access the constant
+   pool.  */
+/* { dg-do compile } */
+extern unsigned x[];
+unsigned *trapTable()
+{
+  unsigned *i;
+
+  __asm__ volatile("ldr %0,%1" : "=r"(i) : "m"(x[0]));
+
+  return i;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/cond-asm.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/cond-asm.c
new file mode 100644
index 000000000..450bd9d6a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/cond-asm.c
@@ -0,0 +1,13 @@
+/* Check that %? in inline asm expands to nothing.  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm32 } */
+int b;
+int foo(int a)
+{
+  if (a)
+    b = 42;
+  asm ("test%?me":"=r"(a):"0"(a));
+  return a;
+}
+/* { dg-final { scan-assembler "testme" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/eabi1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/eabi1.c
new file mode 100644
index 000000000..e88ba021f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/eabi1.c
@@ -0,0 +1,337 @@
+/* { dg-do run { target arm*-*-symbianelf* arm*-*-eabi* } } */
+/* { dg-options "" } */
+
+/* This file tests most of the non-C++ run-time helper functions
+   described in Section 4 of the "Run-Time ABI for the ARM
+   Architecture".  These are basic tests; they do not try to validate
+   all of the corner cases in these routines.  
+
+   The functions not tested here are:
+
+     __aeabi_cdcmpeq
+     __aeabi_cdcmple
+     __aeabi_cdrcmple
+     __aeabi_cfcmpeq
+     __aeabi_cfcmple
+     __aeabi_cfrcmple
+     __aeabi_ldivmod
+     __aeabi_uldivmod
+     __aeabi_idivmod
+     __aeabi_uidivmod
+
+   These functions have non-standard calling conventions that would
+   require the use of inline assembly to test.  It would be good to
+   add such tests, but they have not yet been implemented.  
+
+   There are also no tests for the "division by zero", "memory copying,
+   clearing, and setting" functions.  */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <math.h>
+
+#define decl_float(code, type)					\
+  extern type __aeabi_ ## code ## add (type, type);		\
+  extern type __aeabi_ ## code ## div (type, type);		\
+  extern type __aeabi_ ## code ## mul (type, type);		\
+  extern type __aeabi_ ## code ## neg (type);			\
+  extern type __aeabi_ ## code ## rsub (type, type);		\
+  extern type __aeabi_ ## code ## sub (type, type);		\
+  extern int __aeabi_ ## code ## cmpeq (type, type);		\
+  extern int __aeabi_ ## code ## cmplt (type, type);		\
+  extern int __aeabi_ ## code ## cmple (type, type);		\
+  extern int __aeabi_ ## code ## cmpge (type, type);		\
+  extern int __aeabi_ ## code ## cmpgt (type, type);		\
+  extern int __aeabi_ ## code ## cmpun (type, type);		\
+  extern int __aeabi_ ## code ## 2iz (type);			\
+  extern unsigned int __aeabi_ ## code ## 2uiz (type);		\
+  extern long long __aeabi_ ## code ## 2lz (type);		\
+  extern unsigned long long __aeabi_ ## code ## 2ulz (type);	\
+  extern type __aeabi_i2 ## code (int);				\
+  extern type __aeabi_ui2 ## code (int);			\
+  extern type __aeabi_l2 ## code (long long);			\
+  extern type __aeabi_ul2 ## code (unsigned long long);		\
+								\
+  type code ## zero = 0.0;					\
+  type code ## one = 1.0;					\
+  type code ## two = 2.0;					\
+  type code ## four = 4.0;					\
+  type code ## minus_one = -1.0;				\
+  type code ## minus_two = -2.0;				\
+  type code ## minus_four = -4.0;				\
+  type code ## epsilon = 1E-32;					\
+  type code ## NaN = 0.0 / 0.0;				
+
+decl_float (d, double)
+decl_float (f, float)
+
+extern float __aeabi_d2f (double);
+extern double __aeabi_f2d (float);
+extern long long __aeabi_lmul (long long, long long);
+extern long long __aeabi_llsl (long long, int);
+extern long long __aeabi_llsr (long long, int);
+extern long long __aeabi_lasr (long long, int);
+extern int __aeabi_lcmp (long long, long long);
+extern int __aeabi_ulcmp (unsigned long long, unsigned long long);
+extern int __aeabi_idiv (int, int);
+extern unsigned int __aeabi_uidiv (unsigned int, unsigned int);
+extern int __aeabi_uread4 (void *);
+extern int __aeabi_uwrite4 (int, void *);
+extern long long __aeabi_uread8 (void *);
+extern long long __aeabi_uwrite8 (long long, void *);
+
+#define eq(a, b, type, abs, epsilon, format)			\
+  {								\
+    type a1;							\
+    type b1;							\
+								\
+    a1 = a;							\
+    b1 = b;							\
+    if (abs (a1 - b1) > epsilon)				\
+    {								\
+      fprintf (stderr, "%d: Test %s == %s\n", __LINE__, #a, #b);	\
+      fprintf (stderr, "%d: " format " != " format "\n",	\
+	       __LINE__, a1, b1);				\
+      abort ();							\
+    }								\
+  }
+
+#define ieq(a, b) eq (a, b, int, abs, 0, "%d")
+#define ueq(a, b) eq (a, b, unsigned int, abs, 0, "%u")
+#define leq(a, b) eq (a, b, long long, abs, 0, "%lld")
+#define uleq(a, b) eq (a, b, unsigned long long, abs, 0, "%llu")
+#define feq(a, b) eq (a, b, float, fabs, fepsilon, "%f")
+#define deq(a, b) eq (a, b, double, fabs, depsilon, "%g")
+
+#define NUM_CMP_VALUES 6
+
+/* Values picked to cover a range of small, large, positive and negative.  */
+static unsigned int cmp_val[NUM_CMP_VALUES] = 
+{
+  0,
+  1,
+  0x40000000,
+  0x80000000,
+  0xc0000000,
+  0xffffffff
+};
+
+/* All combinations for each of the above values. */
+#define ulcmp(l, s, m) \
+    s, l, l, l, l, l,  m, s, l, l, l, l, \
+    m, m, s, l, l, l,  m, m, m, s, l, l, \
+    m, m, m, m, s, l,  m, m, m, m, m, s
+
+#define lcmp(l, s, m) \
+    s, l, l, m, m, m,  m, s, l, m, m, m, \
+    m, m, s, m, m, m,  l, l, l, s, l, l, \
+    l, l, l, m, s, l,  l, l, l, m, m, s
+
+/* All combinations of the above for high/low words.  */
+static int lcmp_results[] =
+{
+  lcmp(ulcmp(-1, -1, -1), ulcmp(-1, 0, 1), ulcmp(1, 1, 1))
+};
+
+static int ulcmp_results[] =
+{
+  ulcmp(ulcmp(-1, -1, -1), ulcmp(-1, 0, 1), ulcmp(1, 1, 1))
+};
+
+static int signof(int i)
+{
+  if (i < 0)
+    return -1;
+
+  if (i == 0)
+    return 0;
+
+  return 1;
+}
+
+int main () {
+  unsigned char bytes[256];
+  int i, j, k, n;
+  int *result;
+
+  /* Table 2.  Double-precision floating-point arithmetic.  */
+  deq (__aeabi_dadd (dzero, done), done);
+  deq (__aeabi_dadd (done, done), dtwo);
+  deq (__aeabi_ddiv (dminus_four, dminus_two), dtwo);
+  deq (__aeabi_ddiv (dminus_two, dtwo), dminus_one);
+  deq (__aeabi_dmul (dtwo, dtwo), dfour);
+  deq (__aeabi_dmul (dminus_one, dminus_two), dtwo);
+  deq (__aeabi_dneg (dminus_one), done);
+  deq (__aeabi_dneg (dfour), dminus_four);
+  deq (__aeabi_drsub (done, dzero), dminus_one);
+  deq (__aeabi_drsub (dtwo, dminus_two), dminus_four);
+  deq (__aeabi_dsub (dzero, done), dminus_one);
+  deq (__aeabi_dsub (dminus_two, dtwo), dminus_four);
+
+  /* Table 3.  Double-precision floating-point comparisons.  */
+  ieq (__aeabi_dcmpeq (done, done), 1);
+  ieq (__aeabi_dcmpeq (done, dzero), 0);
+  ieq (__aeabi_dcmpeq (dNaN, dzero), 0);
+  ieq (__aeabi_dcmpeq (dNaN, dNaN), 0);
+
+  ieq (__aeabi_dcmplt (dzero, done), 1);
+  ieq (__aeabi_dcmplt (done, dzero), 0);
+  ieq (__aeabi_dcmplt (dzero, dzero), 0);
+  ieq (__aeabi_dcmplt (dzero, dNaN), 0);
+  ieq (__aeabi_dcmplt (dNaN, dNaN), 0);
+
+  ieq (__aeabi_dcmple (dzero, done), 1);
+  ieq (__aeabi_dcmple (done, dzero), 0);
+  ieq (__aeabi_dcmple (dzero, dzero), 1);
+  ieq (__aeabi_dcmple (dzero, dNaN), 0);
+  ieq (__aeabi_dcmple (dNaN, dNaN), 0);
+
+  ieq (__aeabi_dcmpge (dzero, done), 0);
+  ieq (__aeabi_dcmpge (done, dzero), 1);
+  ieq (__aeabi_dcmpge (dzero, dzero), 1);
+  ieq (__aeabi_dcmpge (dzero, dNaN), 0);
+  ieq (__aeabi_dcmpge (dNaN, dNaN), 0);
+
+  ieq (__aeabi_dcmpgt (dzero, done), 0);
+  ieq (__aeabi_dcmpgt (done, dzero), 1);
+  ieq (__aeabi_dcmplt (dzero, dzero), 0);
+  ieq (__aeabi_dcmpgt (dzero, dNaN), 0);
+  ieq (__aeabi_dcmpgt (dNaN, dNaN), 0);
+
+  ieq (__aeabi_dcmpun (done, done), 0);
+  ieq (__aeabi_dcmpun (done, dzero), 0);
+  ieq (__aeabi_dcmpun (dNaN, dzero), 1);
+  ieq (__aeabi_dcmpun (dNaN, dNaN), 1);
+
+  /* Table 4.  Single-precision floating-point arithmetic.  */
+  feq (__aeabi_fadd (fzero, fone), fone);
+  feq (__aeabi_fadd (fone, fone), ftwo);
+  feq (__aeabi_fdiv (fminus_four, fminus_two), ftwo);
+  feq (__aeabi_fdiv (fminus_two, ftwo), fminus_one);
+  feq (__aeabi_fmul (ftwo, ftwo), ffour);
+  feq (__aeabi_fmul (fminus_one, fminus_two), ftwo);
+  feq (__aeabi_fneg (fminus_one), fone);
+  feq (__aeabi_fneg (ffour), fminus_four);
+  feq (__aeabi_frsub (fone, fzero), fminus_one);
+  feq (__aeabi_frsub (ftwo, fminus_two), fminus_four);
+  feq (__aeabi_fsub (fzero, fone), fminus_one);
+  feq (__aeabi_fsub (fminus_two, ftwo), fminus_four);
+
+  /* Table 5.  Single-precision floating-point comparisons.  */
+  ieq (__aeabi_fcmpeq (fone, fone), 1);
+  ieq (__aeabi_fcmpeq (fone, fzero), 0);
+  ieq (__aeabi_fcmpeq (fNaN, fzero), 0);
+  ieq (__aeabi_fcmpeq (fNaN, fNaN), 0);
+
+  ieq (__aeabi_fcmplt (fzero, fone), 1);
+  ieq (__aeabi_fcmplt (fone, fzero), 0);
+  ieq (__aeabi_fcmplt (fzero, fzero), 0);
+  ieq (__aeabi_fcmplt (fzero, fNaN), 0);
+  ieq (__aeabi_fcmplt (fNaN, fNaN), 0);
+
+  ieq (__aeabi_fcmple (fzero, fone), 1);
+  ieq (__aeabi_fcmple (fone, fzero), 0);
+  ieq (__aeabi_fcmple (fzero, fzero), 1);
+  ieq (__aeabi_fcmple (fzero, fNaN), 0);
+  ieq (__aeabi_fcmple (fNaN, fNaN), 0);
+
+  ieq (__aeabi_fcmpge (fzero, fone), 0);
+  ieq (__aeabi_fcmpge (fone, fzero), 1);
+  ieq (__aeabi_fcmpge (fzero, fzero), 1);
+  ieq (__aeabi_fcmpge (fzero, fNaN), 0);
+  ieq (__aeabi_fcmpge (fNaN, fNaN), 0);
+
+  ieq (__aeabi_fcmpgt (fzero, fone), 0);
+  ieq (__aeabi_fcmpgt (fone, fzero), 1);
+  ieq (__aeabi_fcmplt (fzero, fzero), 0);
+  ieq (__aeabi_fcmpgt (fzero, fNaN), 0);
+  ieq (__aeabi_fcmpgt (fNaN, fNaN), 0);
+
+  ieq (__aeabi_fcmpun (fone, fone), 0);
+  ieq (__aeabi_fcmpun (fone, fzero), 0);
+  ieq (__aeabi_fcmpun (fNaN, fzero), 1);
+  ieq (__aeabi_fcmpun (fNaN, fNaN), 1);
+
+  /* Table 6.  Floating-point to integer conversions.  */
+  ieq (__aeabi_d2iz (dminus_one), -1);
+  ueq (__aeabi_d2uiz (done), 1);
+  leq (__aeabi_d2lz (dminus_two), -2LL);
+  uleq (__aeabi_d2ulz (dfour), 4LL);
+  ieq (__aeabi_f2iz (fminus_one), -1);
+  ueq (__aeabi_f2uiz (fone), 1);
+  leq (__aeabi_f2lz (fminus_two), -2LL);
+  uleq (__aeabi_f2ulz (ffour), 4LL);
+
+  /* Table 7.  Conversions between floating types.  */
+  feq (__aeabi_d2f (dtwo), ftwo);
+  deq (__aeabi_f2d (fminus_four), dminus_four);
+
+  /* Table 8.  Integer to floating-point conversions.  */
+  deq (__aeabi_i2d (-1), dminus_one);
+  deq (__aeabi_ui2d (2), dtwo);
+  deq (__aeabi_l2d (-1), dminus_one);
+  deq (__aeabi_ul2d (2ULL), dtwo);
+  feq (__aeabi_i2f (-1), fminus_one);
+  feq (__aeabi_ui2f (2), ftwo);
+  feq (__aeabi_l2f (-1), fminus_one);
+  feq (__aeabi_ul2f (2ULL), ftwo);
+
+  /* Table 9.  Long long functions.  */
+  leq (__aeabi_lmul (4LL, -1LL), -4LL);
+  leq (__aeabi_llsl (2LL, 1), 4LL);
+  leq (__aeabi_llsr (-1LL, 63), 1);
+  leq (__aeabi_lasr (-1LL, 63), -1);
+
+  result = lcmp_results;
+  for (i = 0; i < NUM_CMP_VALUES; i++)
+    for (j = 0; j < NUM_CMP_VALUES; j++)
+      for (k = 0; k < NUM_CMP_VALUES; k++)
+	for (n = 0; n < NUM_CMP_VALUES; n++)
+	  {
+	    ieq (signof (__aeabi_lcmp
+			  (((long long)cmp_val[i] << 32) | cmp_val[k],
+			   ((long long)cmp_val[j] << 32) | cmp_val[n])),
+			   *result);
+	    result++;
+	  }
+  result = ulcmp_results;
+  for (i = 0; i < NUM_CMP_VALUES; i++)
+    for (j = 0; j < NUM_CMP_VALUES; j++)
+      for (k = 0; k < NUM_CMP_VALUES; k++)
+	for (n = 0; n < NUM_CMP_VALUES; n++)
+	  {
+	    ieq (signof (__aeabi_ulcmp
+			  (((long long)cmp_val[i] << 32) | cmp_val[k],
+			   ((long long)cmp_val[j] << 32) | cmp_val[n])),
+			   *result);
+	    result++;
+	  }
+
+  ieq (__aeabi_idiv (-550, 11), -50);
+  ueq (__aeabi_uidiv (4000000000U, 1000000U), 4000U);
+
+  for (i = 0; i < 256; i++)
+    bytes[i] = i;
+
+#ifdef __ARMEB__
+  ieq (__aeabi_uread4 (bytes + 1), 0x01020304U);
+  leq (__aeabi_uread8 (bytes + 3), 0x030405060708090aLL);
+  ieq (__aeabi_uwrite4 (0x66778899U, bytes + 5), 0x66778899U);
+  leq (__aeabi_uwrite8 (0x2030405060708090LL, bytes + 15),
+       0x2030405060708090LL);
+#else
+  ieq (__aeabi_uread4 (bytes + 1), 0x04030201U);
+  leq (__aeabi_uread8 (bytes + 3), 0x0a09080706050403LL);
+  ieq (__aeabi_uwrite4 (0x99887766U, bytes + 5), 0x99887766U);
+  leq (__aeabi_uwrite8 (0x9080706050403020LL, bytes + 15),
+       0x9080706050403020LL);
+#endif
+
+  for (i = 0; i < 4; i++)
+    ieq (bytes[5 + i], (6 + i) * 0x11);
+
+  for (i = 0; i < 8; i++)
+    ieq (bytes[15 + i], (2 + i) * 0x10);
+
+  exit (0);		
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/g2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/g2.c
new file mode 100644
index 000000000..031b93657
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/g2.c
@@ -0,0 +1,20 @@
+/* Verify that hardware multiply is preferred on XScale. */
+/* { dg-do compile } */
+/* { dg-options "-mcpu=xscale -O2" } */
+/* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-march=*" } { "-march=xscale" } } */
+/* { dg-require-effective-target arm32 } */
+
+/* Brett Gaines' test case. */
+unsigned BCPL(unsigned) __attribute__ ((naked));
+unsigned BCPL(unsigned seed)
+{
+    /* Best code would be:
+       ldr r1, =2147001325
+       ldr r2, =715136305
+       mla r0, r1, r0, r2
+       mov pc, lr */
+
+    return seed * 2147001325U + 715136305U;
+}
+
+/* { dg-final { scan-assembler "mla\[ 	].*" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/got1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/got1.c
new file mode 100644
index 000000000..46a67fb9b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/got1.c
@@ -0,0 +1,10 @@
+/* { dg-options "-Os -fpic" }  */
+/* { dg-final { scan-assembler "GOT_PREL" } } */
+
+extern int x;
+int foo(int j)
+{
+  int t = x;
+  x = j;
+  return t;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/got2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/got2.c
new file mode 100644
index 000000000..725f49e9c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/got2.c
@@ -0,0 +1,11 @@
+/* We should not use GOT_PREL relocation to load global address with so
+   many global accesses.  */
+
+/* { dg-options "-Os -fpic" }  */
+/* { dg-final { scan-assembler-not "GOT_PREL" } } */
+
+extern int x1, x2, x3, x4, x5;
+int sum()
+{
+  return x1 + x2 + x3 + x4 + x5;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/long-calls-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/long-calls-1.c
new file mode 100644
index 000000000..587f6d6f2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/long-calls-1.c
@@ -0,0 +1,132 @@
+/* Check that long calls to different sections are not optimized to "bl".  */
+/* { dg-do compile { target { arm32 && nonpic } } } */
+/* { dg-options "-O2" } */
+
+#define section(S) __attribute__((section(S)))
+#define weak __attribute__((weak))
+#define noinline __attribute__((noinline))
+#define long_call __attribute__((long_call))
+#define short_call __attribute__((short_call))
+
+#define REMOTE_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS ID (void);					\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }
+
+#define EXTERN_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS noinline ID (void) { return #ID; }		\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define STATIC_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  static const char *TARGET_ATTRS noinline ID (void) { return #ID; }	\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define DO_TESTS_SECTION(ID, TEST, TARGET_ATTRS)			\
+  TEST (ID##1, TARGET_ATTRS, )						\
+  TEST (ID##2, TARGET_ATTRS section (".test.a"), section (".test.b"))	\
+  TEST (ID##3, TARGET_ATTRS section (".test.c"), section (".test.c"))
+
+#define DO_TESTS_CALL_ATTR(ID, TEST, TARGET_ATTRS)			\
+  DO_TESTS_SECTION (ID##n, TEST, TARGET_ATTRS)				\
+  DO_TESTS_SECTION (ID##l, TEST, TARGET_ATTRS long_call)		\
+  DO_TESTS_SECTION (ID##s, TEST, TARGET_ATTRS short_call)
+
+DO_TESTS_CALL_ATTR (remote_, REMOTE_CALL,)
+DO_TESTS_CALL_ATTR (strong_, EXTERN_CALL,)
+DO_TESTS_CALL_ATTR (weak_, EXTERN_CALL, weak)
+DO_TESTS_CALL_ATTR (static_, STATIC_CALL,)
+
+
+/* Calls to remote_* should honor the call type attribute,
+   with "short" being the default.
+
+   In the regular expressions below:
+   
+   * We allow both "b" and "bl" in some cases to allow for the
+     possibility of sibling calls.  As of this writing, GCC does not
+     use sibling calls in Thumb-2 mode.  */
+
+/* { dg-final { scan-assembler "\tbl\tremote_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_n3\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl\tremote_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l2\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tremote_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s3\n" } } */
+
+
+/* Calls to strong_*2 calls should honor the call type attribute,
+   with "short" being the default.  Calls to other strong_* functions
+   should be short.  */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_n3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_l1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_l2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_l3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s3\n" } } */
+
+
+/* Calls to weak_* should honor the call type attribute,
+   with "short" being the default.  */
+
+/* { dg-final { scan-assembler "\tbl\tweak_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_n3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_n3\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l2\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tweak_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s3\n" } } */
+
+
+/* Calls to static_*2 calls should honor the call type attribute,
+   with "short" being the default.  Calls to other static_* functions
+   should be short.  */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_n3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_l1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstatic_l2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_l3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s3\n" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/long-calls-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/long-calls-2.c
new file mode 100644
index 000000000..8ce2404c1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/long-calls-2.c
@@ -0,0 +1,127 @@
+/* Check that long calls to different sections are not optimized to "bl".  */
+/* { dg-do compile { target { arm32 && nonpic } } } */
+/* { dg-options "-O2 -mlong-calls" } */
+
+#define section(S) __attribute__((section(S)))
+#define weak __attribute__((weak))
+#define noinline __attribute__((noinline))
+#define long_call __attribute__((long_call))
+#define short_call __attribute__((short_call))
+
+#define REMOTE_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS ID (void);					\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }
+
+#define EXTERN_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS noinline ID (void) { return #ID; }		\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define STATIC_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  static const char *TARGET_ATTRS noinline ID (void) { return #ID; }	\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define DO_TESTS_SECTION(ID, TEST, TARGET_ATTRS)			\
+  TEST (ID##1, TARGET_ATTRS, )						\
+  TEST (ID##2, TARGET_ATTRS section (".test.a"), section (".test.b"))	\
+  TEST (ID##3, TARGET_ATTRS section (".test.c"), section (".test.c"))
+
+#define DO_TESTS_CALL_ATTR(ID, TEST, TARGET_ATTRS)			\
+  DO_TESTS_SECTION (ID##n, TEST, TARGET_ATTRS)				\
+  DO_TESTS_SECTION (ID##l, TEST, TARGET_ATTRS long_call)		\
+  DO_TESTS_SECTION (ID##s, TEST, TARGET_ATTRS short_call)
+
+DO_TESTS_CALL_ATTR (remote_, REMOTE_CALL,)
+DO_TESTS_CALL_ATTR (strong_, EXTERN_CALL,)
+DO_TESTS_CALL_ATTR (weak_, EXTERN_CALL, weak)
+DO_TESTS_CALL_ATTR (static_, STATIC_CALL,)
+
+
+/* Calls to remote_* should honor the call type attribute,
+   with "long" being the default.
+
+   In the regular expressions below:
+   
+   * We allow both "b" and "bl" in some cases to allow for the
+     possibility of sibling calls.  As of this writing, GCC does not
+     use sibling calls in Thumb-2 mode.  */
+
+/* { dg-final { scan-assembler-not "\tbl\tremote_n1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_n2\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_n3\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl\tremote_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l2\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tremote_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s3\n" } } */
+
+
+/* Calls to strong_*2 calls should honor the call type attribute,
+   with "long" being the default.  Calls to other strong_* functions
+   should be short.  */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tstrong_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_n3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_l1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_l2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_l3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s3\n" } } */
+
+
+/* Calls to weak_* should honor the call type attribute,
+   with "long" being the default.  */
+
+/* { dg-final { scan-assembler-not "\tbl?\tweak_n1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_n2\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_n3\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l2\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tweak_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s3\n" } } */
+
+
+/* Calls to static_*2 calls should honor the call type attribute,
+   with "long" being the default.  Calls to other static_* functions
+   should be short.  */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstatic_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_n3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_l1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstatic_l2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_l3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s3\n" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/long-calls-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/long-calls-3.c
new file mode 100644
index 000000000..bd1891c00
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/long-calls-3.c
@@ -0,0 +1,126 @@
+/* Check that long calls to different sections are not optimized to "bl".  */
+/* { dg-do compile { target { arm32 && fpic } } } */
+/* { dg-options "-O2 -fpic" } */
+
+#define section(S) __attribute__((section(S)))
+#define weak __attribute__((weak))
+#define noinline __attribute__((noinline))
+#define long_call __attribute__((long_call))
+#define short_call __attribute__((short_call))
+
+#define REMOTE_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS ID (void);					\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }
+
+#define EXTERN_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS noinline ID (void) { return #ID; }		\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define STATIC_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  static const char *TARGET_ATTRS noinline ID (void) { return #ID; }	\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define DO_TESTS_SECTION(ID, TEST, TARGET_ATTRS)			\
+  TEST (ID##1, TARGET_ATTRS, )						\
+  TEST (ID##2, TARGET_ATTRS section (".test.a"), section (".test.b"))	\
+  TEST (ID##3, TARGET_ATTRS section (".test.c"), section (".test.c"))
+
+#define DO_TESTS_CALL_ATTR(ID, TEST, TARGET_ATTRS)			\
+  DO_TESTS_SECTION (ID##n, TEST, TARGET_ATTRS)				\
+  DO_TESTS_SECTION (ID##l, TEST, TARGET_ATTRS long_call)		\
+  DO_TESTS_SECTION (ID##s, TEST, TARGET_ATTRS short_call)
+
+DO_TESTS_CALL_ATTR (remote_, REMOTE_CALL,)
+DO_TESTS_CALL_ATTR (strong_, EXTERN_CALL,)
+DO_TESTS_CALL_ATTR (weak_, EXTERN_CALL, weak)
+DO_TESTS_CALL_ATTR (static_, STATIC_CALL,)
+
+
+/* Calls to remote_*, strong_* and weak_* should honor the call type
+   attribute, with "short" being the default.  
+
+   In the regular expressions below:
+   
+   * The PLT marker is optional, even though we are using -fpic,
+     because it is not used (or required) on some targets.
+
+   * We allow both "b" and "bl" in some cases to allow for the
+     possibility of sibling calls.  As of this writing, GCC does not
+     use sibling calls in Thumb-2 mode.  */
+
+/* { dg-final { scan-assembler "\tbl\tremote_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_n3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl\tremote_l1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tremote_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s3(\\(PLT\\))?\n" } } */
+
+
+/* { dg-final { scan-assembler "\tbl\tstrong_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_n3(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl\tstrong_l1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_l2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tstrong_l3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s3(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s3(\\(PLT\\))?\n" } } */
+
+
+/* { dg-final { scan-assembler "\tbl\tweak_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_n3(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_n3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tweak_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s3(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s3(\\(PLT\\))?\n" } } */
+
+
+/* Calls to static_*2 calls should honor the call type attribute,
+   with "short" being the default.  Calls to other static_* functions
+   should be short.  */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_n1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_n2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_n3((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n3((\\(PLT\\))?)\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_l1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstatic_l2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_l3((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l3((\\(PLT\\))?)\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_s1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s3((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s3((\\(PLT\\))?)\n" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/long-calls-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/long-calls-4.c
new file mode 100644
index 000000000..dc184b8f8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/long-calls-4.c
@@ -0,0 +1,119 @@
+/* Check that long calls to different sections are not optimized to "bl".  */
+/* { dg-do compile { target { arm32 && fpic } } } */
+/* { dg-options "-O2 -fpic -mlong-calls" } */
+
+#define section(S) __attribute__((section(S)))
+#define weak __attribute__((weak))
+#define noinline __attribute__((noinline))
+#define long_call __attribute__((long_call))
+#define short_call __attribute__((short_call))
+
+#define REMOTE_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS ID (void);					\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }
+
+#define EXTERN_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS noinline ID (void) { return #ID; }		\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define STATIC_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  static const char *TARGET_ATTRS noinline ID (void) { return #ID; }	\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define DO_TESTS_SECTION(ID, TEST, TARGET_ATTRS)			\
+  TEST (ID##1, TARGET_ATTRS, )						\
+  TEST (ID##2, TARGET_ATTRS section (".test.a"), section (".test.b"))	\
+  TEST (ID##3, TARGET_ATTRS section (".test.c"), section (".test.c"))
+
+#define DO_TESTS_CALL_ATTR(ID, TEST, TARGET_ATTRS)			\
+  DO_TESTS_SECTION (ID##n, TEST, TARGET_ATTRS)				\
+  DO_TESTS_SECTION (ID##l, TEST, TARGET_ATTRS long_call)		\
+  DO_TESTS_SECTION (ID##s, TEST, TARGET_ATTRS short_call)
+
+DO_TESTS_CALL_ATTR (remote_, REMOTE_CALL,)
+DO_TESTS_CALL_ATTR (strong_, EXTERN_CALL,)
+DO_TESTS_CALL_ATTR (weak_, EXTERN_CALL, weak)
+DO_TESTS_CALL_ATTR (static_, STATIC_CALL,)
+
+
+/* Calls to remote_*, strong_* and weak_* should honor the call type
+   attribute, with "long" being the default.  
+
+   In the regular expressions below:
+   
+   * The PLT marker is optional, even though we are using -fpic,
+     because it is not used (or required) on some targets.
+
+   * We allow both "b" and "bl" in some cases to allow for the
+     possibility of sibling calls.  As of this writing, GCC does not
+     use sibling calls in Thumb-2 mode.  */
+
+/* { dg-final { scan-assembler-not "\tbl\tremote_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_n3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl\tremote_l1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tremote_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s3(\\(PLT\\))?\n" } } */
+
+
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_n3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_l1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_l2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_l3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s3(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s3(\\(PLT\\))?\n" } } */
+
+
+/* { dg-final { scan-assembler-not "\tbl?\tweak_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_n3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tweak_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s3(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s3(\\(PLT\\))?\n" } } */
+
+
+/* Calls to static_*2 calls should honor the call type attribute,
+   with "long" being the default.  Calls to other static_* functions
+   should be short.  */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_n1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstatic_n2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_n3((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n3((\\(PLT\\))?)\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_l1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstatic_l2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_l3((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l3((\\(PLT\\))?)\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_s1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s3((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s3((\\(PLT\\))?)\n" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/mmx-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/mmx-1.c
new file mode 100644
index 000000000..21cc47912
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/mmx-1.c
@@ -0,0 +1,24 @@
+/* Verify that if IP is saved to ensure stack alignment, we don't load
+   it into sp.  */
+/* { dg-do compile } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mfloat-abi=softfp" } { "" } } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */
+/* { dg-options "-O -mno-apcs-frame -mcpu=iwmmxt -mabi=iwmmxt" } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler "ldmfd\[ 	]sp!.*ip,\[ ]*pc" } } */
+
+/* This function uses all the call-saved registers, namely r4, r5, r6,
+   r7, r8, r9, sl, fp.  Since we also save lr, that leaves an odd
+   number of registers, and the compiler will push ip to align the
+   stack.  Make sure that we restore ip into ip, not into sp as is
+   done when using a frame pointer.  The -mno-apcs-frame option
+   permits the frame pointer to be used as an ordinary register.  */
+
+void
+foo(void)
+{
+  __asm volatile ("" : : :
+		  "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "lr");
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/naked-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/naked-1.c
new file mode 100644
index 000000000..8f9ff711a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/naked-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+/* Check that function arguments aren't assigned and copied to stack slots
+   in naked functions.  This ususally happens at -O0 (presumably for
+   better debugging), but is highly undesirable if we haven't created
+   a stack frame.  */
+void __attribute__((naked))
+foo(int n)
+{
+  __asm__ volatile ("frob r0\n");
+}
+/* { dg-final { scan-assembler "\tfrob r0" } } */
+/* { dg-final { scan-assembler-not "\tstr" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/naked-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/naked-2.c
new file mode 100644
index 000000000..92e7db444
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/naked-2.c
@@ -0,0 +1,12 @@
+/* Verify that __attribute__((naked)) produces a naked function 
+   that does not use bx to return. Naked functions could be used
+   to implement interrupt routines and must not return using bx.  */
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+/* Use more arguments than we have argument registers.  */
+int __attribute__((naked)) foo(int a, int b, int c, int d, int e, int f)
+{
+  __asm__ volatile ("@ naked");
+}
+/* { dg-final { scan-assembler "\t@ naked" } } */
+/* { dg-final { scan-assembler-not "\tbx\tlr" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon-cond-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon-cond-1.c
new file mode 100644
index 000000000..7d87b6e12
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon-cond-1.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp" } */
+/* Check that the arm_final_prescan_insn ccfsm code does not try to
+ * conditionally execute NEON instructions.  */
+#include <arm_neon.h>
+#include <stdlib.h>
+
+int __attribute__((noinline))
+foo(uint32x2_t a, uint32_t *p, uint32_t *q)
+{
+  if (p != q)
+    /* This vst1 instruction could be conditional, except that NEON
+       instructions are never conditional in ARM mode.  */
+    vst1_u32(p, a);
+  return 0;
+}
+
+int
+main()
+{
+    uint32x2_t v;
+    uint32_t a[2] = {1, 42};
+    v = vld1_u32(a);
+    v = vadd_u32(v, v);
+    foo(v, a, a);
+    if (a[0] != 1 || a[1] != 42)
+      abort();
+    exit(0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c
new file mode 100644
index 000000000..882285131
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c
@@ -0,0 +1,98 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2 -mthumb -march=armv7-a -mfloat-abi=softfp -mfpu=neon" } */
+
+#include <arm_neon.h>
+#include <stddef.h>
+
+void *
+memset (DST, C, LENGTH)
+     void *DST;
+     int C;
+     size_t LENGTH;
+{
+  void* DST0 = DST;
+  unsigned char C_BYTE = C;
+
+
+  if (__builtin_expect(LENGTH < 4, 1)) {
+    size_t i = 0;
+    while (i < LENGTH) {
+      ((char*)DST)[i] = C_BYTE;
+      i++;
+    }
+    return DST;
+  }
+
+  const char* DST_end = (char*)DST + LENGTH;
+
+
+  while ((uintptr_t)DST % 4 != 0) {
+    *(char*) (DST++) = C_BYTE;
+  }
+
+
+  uint32_t C_SHORTWORD = (uint32_t)(unsigned char)(C_BYTE) * 0x01010101;
+
+
+  if (__builtin_expect(DST_end - (char*)DST >= 16, 0)) {
+    while ((uintptr_t)DST % 16 != 0) {
+      *((uint32_t*)((char*)(DST) + (0))) = C_SHORTWORD;
+      DST += 4;
+    }
+
+
+    uint8x16_t C_WORD = vdupq_n_u8(C_BYTE);
+
+
+
+
+
+    size_t i = 0;
+    LENGTH = DST_end - (char*)DST;
+    while (i + 16 * 16 <= LENGTH) {
+      *((uint8x16_t*)((char*)(DST) + (i))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 1))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 2))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 3))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 4))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 5))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 6))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 7))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 8))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 9))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 10))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 11))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 12))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 13))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 14))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 15))) = C_WORD;
+      i += 16 * 16;
+    }
+    while (i + 16 * 4 <= LENGTH) {
+      *((uint8x16_t*)((char*)(DST) + (i))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 1))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 2))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 3))) = C_WORD;
+      i += 16 * 4;
+    }
+    while (i + 16 <= LENGTH) {
+      *((uint8x16_t*)((char*)(DST) + (i))) = C_WORD;
+      i += 16;
+    }
+    DST += i;
+  }
+
+  while (4 <= DST_end - (char*)DST) {
+    *((uint32_t*)((char*)(DST) + (0))) = C_SHORTWORD;
+    DST += 4;
+  }
+
+
+  while ((char*)DST < DST_end) {
+    *((char*)DST) = C_BYTE;
+    DST++;
+  }
+
+  return DST0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/neon.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/neon.exp
new file mode 100644
index 000000000..fcc433346
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/neon.exp
@@ -0,0 +1,35 @@
+# Copyright (C) 1997, 2004, 2006, 2007 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an ARM target.
+if ![istarget arm*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" ""
+
+# All done.
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/polytypes.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/polytypes.c
new file mode 100644
index 000000000..4fa3eac08
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/polytypes.c
@@ -0,0 +1,48 @@
+/* Check that NEON polynomial vector types are suitably incompatible with
+   integer vector types of the same layout.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-mfpu=neon -mfloat-abi=softfp" } */
+
+#include <arm_neon.h>
+
+void s64_8 (int8x8_t a) {}
+void u64_8 (uint8x8_t a) {}
+void p64_8 (poly8x8_t a) {}
+void s64_16 (int16x4_t a) {}
+void u64_16 (uint16x4_t a) {}
+void p64_16 (poly16x4_t a) {}
+
+void s128_8 (int8x16_t a) {}
+void u128_8 (uint8x16_t a) {}
+void p128_8 (poly8x16_t a) {}
+void s128_16 (int16x8_t a) {}
+void u128_16 (uint16x8_t a) {}
+void p128_16 (poly16x8_t a) {}
+
+void foo ()
+{
+  poly8x8_t v64_8;
+  poly16x4_t v64_16;
+  poly8x16_t v128_8;
+  poly16x8_t v128_16;
+
+  s64_8 (v64_8); /* { dg-message "use -flax-vector-conversions" } */
+  /* { dg-error "incompatible type for argument 1 of 's64_8'" "" { target *-*-* } 31 } */
+  u64_8 (v64_8); /* { dg-error "incompatible type for argument 1 of 'u64_8'" } */
+  p64_8 (v64_8);
+
+  s64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 's64_16'" } */
+  u64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 'u64_16'" } */
+  p64_16 (v64_16);
+
+  s128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 's128_8'" } */
+  u128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 'u128_8'" } */
+  p128_8 (v128_8);
+
+  s128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 's128_16'" } */
+  u128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 'u128_16'" } */
+  p128_16 (v128_16);
+}
+/* { dg-message "note: expected '\[^'\n\]*' but argument is of type '\[^'\n\]*'" "note: expected" { target *-*-* } 0 } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c
new file mode 100644
index 000000000..68834af06
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRaddhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vraddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c
new file mode 100644
index 000000000..afa4307f3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRaddhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vraddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c
new file mode 100644
index 000000000..efa777cd0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRaddhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vraddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c
new file mode 100644
index 000000000..2406ba614
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRaddhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vraddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c
new file mode 100644
index 000000000..3266f8b16
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRaddhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vraddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c
new file mode 100644
index 000000000..e77356f27
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRaddhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRaddhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vraddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c
new file mode 100644
index 000000000..dae4fe9b6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vrhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c
new file mode 100644
index 000000000..bcd72ab60
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vrhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c
new file mode 100644
index 000000000..0c5874e13
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vrhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c
new file mode 100644
index 000000000..175211091
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vrhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c
new file mode 100644
index 000000000..92fb39911
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c
new file mode 100644
index 000000000..39a8e0106
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vrhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c
new file mode 100644
index 000000000..2a301d482
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c
@@ -0,0 +1,20 @@
+/* Test the `vRhadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vrhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c
new file mode 100644
index 000000000..91d6494e9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c
@@ -0,0 +1,20 @@
+/* Test the `vRhadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vrhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c
new file mode 100644
index 000000000..25703e55b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c
@@ -0,0 +1,20 @@
+/* Test the `vRhadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vrhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c
new file mode 100644
index 000000000..b655963d0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vrhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c
new file mode 100644
index 000000000..7ab8d5b50
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vrhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c
new file mode 100644
index 000000000..8f1cae990
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRhaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRhaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vrhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c
new file mode 100644
index 000000000..81c79b16f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c
new file mode 100644
index 000000000..a91618cc0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c
new file mode 100644
index 000000000..f20de10fd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c
new file mode 100644
index 000000000..4c63dc470
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c
new file mode 100644
index 000000000..fe8981e1b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c
new file mode 100644
index 000000000..cdb4c323f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c
new file mode 100644
index 000000000..877150415
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c
new file mode 100644
index 000000000..6ab254e60
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshls16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshls16.c
new file mode 100644
index 000000000..e33198833
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshls16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshls32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshls32.c
new file mode 100644
index 000000000..2ba12c4ab
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshls32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshls64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshls64.c
new file mode 100644
index 000000000..360c0c1d1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshls64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshls8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshls8.c
new file mode 100644
index 000000000..a9b68eba4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshls8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c
new file mode 100644
index 000000000..d493b441a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c
new file mode 100644
index 000000000..82edc7eed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c
new file mode 100644
index 000000000..b821e2c27
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c
new file mode 100644
index 000000000..f609ce00e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c
new file mode 100644
index 000000000..3ea1a5f4b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vrshrq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c
new file mode 100644
index 000000000..e66dec53f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vrshrq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c
new file mode 100644
index 000000000..8d4d23c55
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vrshrq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c
new file mode 100644
index 000000000..3ac4b093b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrshrq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c
new file mode 100644
index 000000000..2454b80eb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vrshrq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c
new file mode 100644
index 000000000..8a8b35129
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrshrq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c
new file mode 100644
index 000000000..1388e75aa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vrshrq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c
new file mode 100644
index 000000000..0218268b2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrshrq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c
new file mode 100644
index 000000000..45be077f0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vrshr_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c
new file mode 100644
index 000000000..1921daa9c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vrshr_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c
new file mode 100644
index 000000000..8369afb68
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vrshr_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c
new file mode 100644
index 000000000..3632be0f3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrshr_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c
new file mode 100644
index 000000000..262783de5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vrshr_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c
new file mode 100644
index 000000000..ed480252b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrshr_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c
new file mode 100644
index 000000000..5e66caa4c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vrshr_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c
new file mode 100644
index 000000000..720f9cab6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vRshr_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrshr_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c
new file mode 100644
index 000000000..864aa5e6f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vrshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c
new file mode 100644
index 000000000..a313892e7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vrshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c
new file mode 100644
index 000000000..e95ef9230
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vrshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c
new file mode 100644
index 000000000..09e3299b6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vrshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c
new file mode 100644
index 000000000..548d89e93
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vrshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c
new file mode 100644
index 000000000..9a67f2d8e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vRshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vrshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c
new file mode 100644
index 000000000..803eab09d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vrsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c
new file mode 100644
index 000000000..541528fe5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vrsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c
new file mode 100644
index 000000000..26f404982
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vrsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c
new file mode 100644
index 000000000..9d701f3f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vrsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c
new file mode 100644
index 000000000..a3ff5f035
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vrsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c
new file mode 100644
index 000000000..7830c435a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vrsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c
new file mode 100644
index 000000000..bd12da149
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vrsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c
new file mode 100644
index 000000000..928dcd8a3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRsraQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vrsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c
new file mode 100644
index 000000000..e7b2d1a1f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vrsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c
new file mode 100644
index 000000000..dd3c11536
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vrsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c
new file mode 100644
index 000000000..98944d675
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vrsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c
new file mode 100644
index 000000000..187bbc015
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vrsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c
new file mode 100644
index 000000000..56009bb29
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vrsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c
new file mode 100644
index 000000000..f7879dbcd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vrsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c
new file mode 100644
index 000000000..25d25d55c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vrsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c
new file mode 100644
index 000000000..07f587a55
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRsra_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vrsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c
new file mode 100644
index 000000000..ec62a28f4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsubhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vrsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c
new file mode 100644
index 000000000..a049aab22
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsubhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vrsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c
new file mode 100644
index 000000000..515bac135
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsubhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vrsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c
new file mode 100644
index 000000000..0e5294601
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsubhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vrsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c
new file mode 100644
index 000000000..f4ec78887
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsubhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vrsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c
new file mode 100644
index 000000000..1b41a20ad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRsubhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vRsubhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vrsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c
new file mode 100644
index 000000000..e15a611df
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabaQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vabaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c
new file mode 100644
index 000000000..b14068ab5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabaQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vabaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c
new file mode 100644
index 000000000..91a1582ff
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabaQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vabaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c
new file mode 100644
index 000000000..61642ac1e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabaQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vabaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c
new file mode 100644
index 000000000..2227524cd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabaQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vabaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c
new file mode 100644
index 000000000..4e92d0345
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vabaQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabaQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vabaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabals16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabals16.c
new file mode 100644
index 000000000..65f1b9d41
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabals16.c
@@ -0,0 +1,21 @@
+/* Test the `vabals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabals16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vabal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabals32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabals32.c
new file mode 100644
index 000000000..13a696b13
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabals32.c
@@ -0,0 +1,21 @@
+/* Test the `vabals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabals32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vabal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabals8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabals8.c
new file mode 100644
index 000000000..c7275b357
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabals8.c
@@ -0,0 +1,21 @@
+/* Test the `vabals8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabals8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int16x8_t = vabal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabalu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabalu16.c
new file mode 100644
index 000000000..0be2473dc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabalu16.c
@@ -0,0 +1,21 @@
+/* Test the `vabalu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabalu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vabal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabalu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabalu32.c
new file mode 100644
index 000000000..508420b4b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabalu32.c
@@ -0,0 +1,21 @@
+/* Test the `vabalu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabalu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vabal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabalu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabalu8.c
new file mode 100644
index 000000000..0580eb3df
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabalu8.c
@@ -0,0 +1,21 @@
+/* Test the `vabalu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabalu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint16x8_t = vabal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabas16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabas16.c
new file mode 100644
index 000000000..4122be9a1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabas16.c
@@ -0,0 +1,21 @@
+/* Test the `vabas16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabas16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vaba_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabas32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabas32.c
new file mode 100644
index 000000000..ca089864f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabas32.c
@@ -0,0 +1,21 @@
+/* Test the `vabas32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabas32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vaba_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabas8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabas8.c
new file mode 100644
index 000000000..e03f2285a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabas8.c
@@ -0,0 +1,21 @@
+/* Test the `vabas8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabas8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vaba_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabau16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabau16.c
new file mode 100644
index 000000000..f67beca53
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabau16.c
@@ -0,0 +1,21 @@
+/* Test the `vabau16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabau16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vaba_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabau32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabau32.c
new file mode 100644
index 000000000..b57d1cf39
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabau32.c
@@ -0,0 +1,21 @@
+/* Test the `vabau32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabau32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vaba_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabau8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabau8.c
new file mode 100644
index 000000000..03ce6665b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabau8.c
@@ -0,0 +1,21 @@
+/* Test the `vabau8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabau8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vaba_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c
new file mode 100644
index 000000000..0cec3095b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vabdq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c
new file mode 100644
index 000000000..cd7cedbde
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vabdq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c
new file mode 100644
index 000000000..06a2d6a81
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vabdq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c
new file mode 100644
index 000000000..dc52032a7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vabdq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c
new file mode 100644
index 000000000..72cfd3a32
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vabdq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c
new file mode 100644
index 000000000..cd0c36193
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vabdq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c
new file mode 100644
index 000000000..15afaa9e6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vabdQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vabdq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdf32.c
new file mode 100644
index 000000000..58465a617
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdf32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vabd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdls16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdls16.c
new file mode 100644
index 000000000..a9c495df9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdls16.c
@@ -0,0 +1,20 @@
+/* Test the `vabdls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vabdl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdls32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdls32.c
new file mode 100644
index 000000000..8f189479e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdls32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vabdl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdls8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdls8.c
new file mode 100644
index 000000000..1696bbca0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdls8.c
@@ -0,0 +1,20 @@
+/* Test the `vabdls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vabdl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c
new file mode 100644
index 000000000..cb26a67ad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vabdlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdlu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vabdl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c
new file mode 100644
index 000000000..34541ee54
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdlu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vabdl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c
new file mode 100644
index 000000000..b84a0457a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vabdlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdlu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vabdl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabds16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabds16.c
new file mode 100644
index 000000000..209b6daeb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabds16.c
@@ -0,0 +1,20 @@
+/* Test the `vabds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vabd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabds32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabds32.c
new file mode 100644
index 000000000..e7d5d4023
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabds32.c
@@ -0,0 +1,20 @@
+/* Test the `vabds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vabd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabds8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabds8.c
new file mode 100644
index 000000000..aba217882
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabds8.c
@@ -0,0 +1,20 @@
+/* Test the `vabds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vabd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdu16.c
new file mode 100644
index 000000000..bbb779ad8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdu16.c
@@ -0,0 +1,20 @@
+/* Test the `vabdu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vabd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdu32.c
new file mode 100644
index 000000000..d51068cb6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdu32.c
@@ -0,0 +1,20 @@
+/* Test the `vabdu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vabd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdu8.c
new file mode 100644
index 000000000..066c6555f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabdu8.c
@@ -0,0 +1,20 @@
+/* Test the `vabdu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabdu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vabd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c
new file mode 100644
index 000000000..137a568fd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c
@@ -0,0 +1,19 @@
+/* Test the `vabsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vabsq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c
new file mode 100644
index 000000000..47cf5a66f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vabsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vabsq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c
new file mode 100644
index 000000000..f775b5a24
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vabsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vabsq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c
new file mode 100644
index 000000000..131244923
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vabsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vabsq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabsf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabsf32.c
new file mode 100644
index 000000000..53d6c0c5d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabsf32.c
@@ -0,0 +1,19 @@
+/* Test the `vabsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vabs_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabss16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabss16.c
new file mode 100644
index 000000000..8f91a70c6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabss16.c
@@ -0,0 +1,19 @@
+/* Test the `vabss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vabs_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabss32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabss32.c
new file mode 100644
index 000000000..75033665a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabss32.c
@@ -0,0 +1,19 @@
+/* Test the `vabss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vabs_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabss8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabss8.c
new file mode 100644
index 000000000..c7e77f665
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vabss8.c
@@ -0,0 +1,19 @@
+/* Test the `vabss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vabss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vabs_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c
new file mode 100644
index 000000000..7a232f85e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vaddq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c
new file mode 100644
index 000000000..a034cfcb1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c
new file mode 100644
index 000000000..e99ddb589
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c
new file mode 100644
index 000000000..381ce4d74
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vaddq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c
new file mode 100644
index 000000000..28a26765f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c
new file mode 100644
index 000000000..dd860af23
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c
new file mode 100644
index 000000000..d04f60663
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c
new file mode 100644
index 000000000..ed5b54a71
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c
new file mode 100644
index 000000000..94c27aa81
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddf32.c
new file mode 100644
index 000000000..646674ed9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddf32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vadd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c
new file mode 100644
index 000000000..1328a850f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vaddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c
new file mode 100644
index 000000000..7b54f1500
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vaddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c
new file mode 100644
index 000000000..5bd6cc02d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vaddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c
new file mode 100644
index 000000000..87661d821
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vaddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c
new file mode 100644
index 000000000..db1860df0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vaddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c
new file mode 100644
index 000000000..461d4ba94
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c
@@ -0,0 +1,20 @@
+/* Test the `vaddhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vaddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddls16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddls16.c
new file mode 100644
index 000000000..042eb51eb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddls16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vaddl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddls32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddls32.c
new file mode 100644
index 000000000..b2364250e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddls32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vaddl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddls8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddls8.c
new file mode 100644
index 000000000..b04da8a98
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddls8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vaddl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c
new file mode 100644
index 000000000..813a8714f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddlu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vaddl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c
new file mode 100644
index 000000000..9815f81ca
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddlu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vaddl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c
new file mode 100644
index 000000000..269f1c2c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddlu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vaddl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vadds16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vadds16.c
new file mode 100644
index 000000000..2cf2e53aa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vadds16.c
@@ -0,0 +1,20 @@
+/* Test the `vadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vadds32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vadds32.c
new file mode 100644
index 000000000..a2ec12196
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vadds32.c
@@ -0,0 +1,20 @@
+/* Test the `vadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vadds64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vadds64.c
new file mode 100644
index 000000000..21a917dae
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vadds64.c
@@ -0,0 +1,20 @@
+/* Test the `vadds64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vadds64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vadds8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vadds8.c
new file mode 100644
index 000000000..a14e94b6f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vadds8.c
@@ -0,0 +1,20 @@
+/* Test the `vadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddu16.c
new file mode 100644
index 000000000..bcf484eae
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddu16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddu32.c
new file mode 100644
index 000000000..d92147666
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddu32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddu64.c
new file mode 100644
index 000000000..6684785d3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddu64.c
@@ -0,0 +1,20 @@
+/* Test the `vaddu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddu8.c
new file mode 100644
index 000000000..c06ea4bc3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddu8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddws16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddws16.c
new file mode 100644
index 000000000..2ca47d0de
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddws16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddws16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddws16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vaddw_s16 (arg0_int32x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddws32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddws32.c
new file mode 100644
index 000000000..87a8090b3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddws32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddws32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddws32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vaddw_s32 (arg0_int64x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddws8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddws8.c
new file mode 100644
index 000000000..1ebe6a856
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddws8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddws8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddws8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vaddw_s8 (arg0_int16x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c
new file mode 100644
index 000000000..bfea209aa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c
@@ -0,0 +1,20 @@
+/* Test the `vaddwu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddwu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vaddw_u16 (arg0_uint32x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c
new file mode 100644
index 000000000..738171969
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c
@@ -0,0 +1,20 @@
+/* Test the `vaddwu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddwu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vaddw_u32 (arg0_uint64x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c
new file mode 100644
index 000000000..f87802bee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c
@@ -0,0 +1,20 @@
+/* Test the `vaddwu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vaddwu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vaddw_u8 (arg0_uint16x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQs16.c
new file mode 100644
index 000000000..b3778cf52
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vandQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vandq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQs32.c
new file mode 100644
index 000000000..b153d2cd6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vandQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vandq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQs64.c
new file mode 100644
index 000000000..6a804e5e7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vandQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vandq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQs8.c
new file mode 100644
index 000000000..bcc3c6fa4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vandQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vandq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQu16.c
new file mode 100644
index 000000000..4f1b03c77
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vandQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vandq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQu32.c
new file mode 100644
index 000000000..3979f264c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vandQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vandq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQu64.c
new file mode 100644
index 000000000..cc523d809
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vandQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vandq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQu8.c
new file mode 100644
index 000000000..84f098524
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vandQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vandq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vands16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vands16.c
new file mode 100644
index 000000000..ee77d193b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vands16.c
@@ -0,0 +1,20 @@
+/* Test the `vands16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vands16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vand_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vands32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vands32.c
new file mode 100644
index 000000000..26abfdff6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vands32.c
@@ -0,0 +1,20 @@
+/* Test the `vands32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vands32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vand_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vands64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vands64.c
new file mode 100644
index 000000000..5a680a897
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vands64.c
@@ -0,0 +1,20 @@
+/* Test the `vands64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vands64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vands8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vands8.c
new file mode 100644
index 000000000..6404bf515
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vands8.c
@@ -0,0 +1,20 @@
+/* Test the `vands8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vands8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vand_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandu16.c
new file mode 100644
index 000000000..470c90fa0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandu16.c
@@ -0,0 +1,20 @@
+/* Test the `vandu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vand_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandu32.c
new file mode 100644
index 000000000..f8369cf38
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandu32.c
@@ -0,0 +1,20 @@
+/* Test the `vandu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vand_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandu64.c
new file mode 100644
index 000000000..6c1c0ee10
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandu64.c
@@ -0,0 +1,20 @@
+/* Test the `vandu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandu8.c
new file mode 100644
index 000000000..fa4cfb6b6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vandu8.c
@@ -0,0 +1,20 @@
+/* Test the `vandu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vandu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vand_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c
new file mode 100644
index 000000000..2da6e98e2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vbicq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c
new file mode 100644
index 000000000..0457f4019
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vbicq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c
new file mode 100644
index 000000000..22095ccb3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vbicq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c
new file mode 100644
index 000000000..4baa0e2be
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vbicq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c
new file mode 100644
index 000000000..4ae91ea48
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vbicq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c
new file mode 100644
index 000000000..2c74f88e5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vbicq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c
new file mode 100644
index 000000000..61839b92a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vbicq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c
new file mode 100644
index 000000000..b39f91caf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vbicQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vbicq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbics16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbics16.c
new file mode 100644
index 000000000..f8b5cb13f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbics16.c
@@ -0,0 +1,20 @@
+/* Test the `vbics16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbics16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vbic_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbics32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbics32.c
new file mode 100644
index 000000000..63e854cee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbics32.c
@@ -0,0 +1,20 @@
+/* Test the `vbics32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbics32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vbic_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbics64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbics64.c
new file mode 100644
index 000000000..10a0b5a11
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbics64.c
@@ -0,0 +1,20 @@
+/* Test the `vbics64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbics64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbics8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbics8.c
new file mode 100644
index 000000000..d1e6db56b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbics8.c
@@ -0,0 +1,20 @@
+/* Test the `vbics8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbics8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vbic_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicu16.c
new file mode 100644
index 000000000..c961e8026
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicu16.c
@@ -0,0 +1,20 @@
+/* Test the `vbicu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vbic_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicu32.c
new file mode 100644
index 000000000..8c95eb4e1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicu32.c
@@ -0,0 +1,20 @@
+/* Test the `vbicu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vbic_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicu64.c
new file mode 100644
index 000000000..e77701680
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicu64.c
@@ -0,0 +1,20 @@
+/* Test the `vbicu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicu8.c
new file mode 100644
index 000000000..c121432a9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbicu8.c
@@ -0,0 +1,20 @@
+/* Test the `vbicu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbicu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vbic_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
new file mode 100644
index 000000000..76e50053e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vbslq_f32 (arg0_uint32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
new file mode 100644
index 000000000..ba97cbe61
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+  poly16x8_t arg2_poly16x8_t;
+
+  out_poly16x8_t = vbslq_p16 (arg0_uint16x8_t, arg1_poly16x8_t, arg2_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
new file mode 100644
index 000000000..475739a6d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+  poly8x16_t arg2_poly8x16_t;
+
+  out_poly8x16_t = vbslq_p8 (arg0_uint8x16_t, arg1_poly8x16_t, arg2_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
new file mode 100644
index 000000000..6780fdad0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vbslq_s16 (arg0_uint16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
new file mode 100644
index 000000000..6f2835caa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vbslq_s32 (arg0_uint32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
new file mode 100644
index 000000000..017f07370
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+  int64x2_t arg2_int64x2_t;
+
+  out_int64x2_t = vbslq_s64 (arg0_uint64x2_t, arg1_int64x2_t, arg2_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
new file mode 100644
index 000000000..e2ed40219
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vbslq_s8 (arg0_uint8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c
new file mode 100644
index 000000000..99d379c30
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vbslq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c
new file mode 100644
index 000000000..7fc71bd76
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vbslq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c
new file mode 100644
index 000000000..89e19ea70
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+  uint64x2_t arg2_uint64x2_t;
+
+  out_uint64x2_t = vbslq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, arg2_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c
new file mode 100644
index 000000000..c2ea8dd96
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vbslQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vbslq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
new file mode 100644
index 000000000..edbe7dfc1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
@@ -0,0 +1,21 @@
+/* Test the `vbslf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vbsl_f32 (arg0_uint32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
new file mode 100644
index 000000000..bd02dac04
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
@@ -0,0 +1,21 @@
+/* Test the `vbslp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+  poly16x4_t arg2_poly16x4_t;
+
+  out_poly16x4_t = vbsl_p16 (arg0_uint16x4_t, arg1_poly16x4_t, arg2_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
new file mode 100644
index 000000000..2456c53d2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
@@ -0,0 +1,21 @@
+/* Test the `vbslp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+  poly8x8_t arg2_poly8x8_t;
+
+  out_poly8x8_t = vbsl_p8 (arg0_uint8x8_t, arg1_poly8x8_t, arg2_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbsls16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
new file mode 100644
index 000000000..f21d509b1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
@@ -0,0 +1,21 @@
+/* Test the `vbsls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbsls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vbsl_s16 (arg0_uint16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbsls32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
new file mode 100644
index 000000000..81a797525
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
@@ -0,0 +1,21 @@
+/* Test the `vbsls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbsls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vbsl_s32 (arg0_uint32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbsls64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
new file mode 100644
index 000000000..fd5e6842a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
@@ -0,0 +1,21 @@
+/* Test the `vbsls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbsls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+  int64x1_t arg2_int64x1_t;
+
+  out_int64x1_t = vbsl_s64 (arg0_uint64x1_t, arg1_int64x1_t, arg2_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbsls8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
new file mode 100644
index 000000000..1e7b39a36
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
@@ -0,0 +1,21 @@
+/* Test the `vbsls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbsls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vbsl_s8 (arg0_uint8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslu16.c
new file mode 100644
index 000000000..8c6480f32
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslu16.c
@@ -0,0 +1,21 @@
+/* Test the `vbslu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vbsl_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslu32.c
new file mode 100644
index 000000000..16938cd37
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslu32.c
@@ -0,0 +1,21 @@
+/* Test the `vbslu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vbsl_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslu64.c
new file mode 100644
index 000000000..1370691f6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslu64.c
@@ -0,0 +1,21 @@
+/* Test the `vbslu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+  uint64x1_t arg2_uint64x1_t;
+
+  out_uint64x1_t = vbsl_u64 (arg0_uint64x1_t, arg1_uint64x1_t, arg2_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslu8.c
new file mode 100644
index 000000000..a3ab7662c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vbslu8.c
@@ -0,0 +1,21 @@
+/* Test the `vbslu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vbslu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vbsl_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c
new file mode 100644
index 000000000..667f0c4ff
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcageQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcageQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcageq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcagef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcagef32.c
new file mode 100644
index 000000000..58feeadc3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcagef32.c
@@ -0,0 +1,20 @@
+/* Test the `vcagef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcagef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcage_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c
new file mode 100644
index 000000000..6ef7e1450
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcagtQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcagtQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcagtq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c
new file mode 100644
index 000000000..a6bc406cd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcagtf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcagtf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcagt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c
new file mode 100644
index 000000000..b26f68d4c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcaleQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcaleQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcaleq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcalef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcalef32.c
new file mode 100644
index 000000000..8a3b87db1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcalef32.c
@@ -0,0 +1,20 @@
+/* Test the `vcalef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcalef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcale_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c
new file mode 100644
index 000000000..6bab9d7c8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcaltQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcaltQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcaltq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c
new file mode 100644
index 000000000..7862aa485
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcaltf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcaltf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcalt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c
new file mode 100644
index 000000000..f8666c297
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vceqq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c
new file mode 100644
index 000000000..5c7976c5c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQp8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_uint8x16_t = vceqq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c
new file mode 100644
index 000000000..d072120d3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vceqq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c
new file mode 100644
index 000000000..5e6e2a5f9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vceqq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c
new file mode 100644
index 000000000..3b141ec2e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vceqq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c
new file mode 100644
index 000000000..85a0d890d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vceqq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c
new file mode 100644
index 000000000..20824d43e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vceqq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c
new file mode 100644
index 000000000..7a1bb2592
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vceqQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vceqq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqf32.c
new file mode 100644
index 000000000..5f341e6ff
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqf32.c
@@ -0,0 +1,20 @@
+/* Test the `vceqf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vceq_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqp8.c
new file mode 100644
index 000000000..8a9496041
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqp8.c
@@ -0,0 +1,20 @@
+/* Test the `vceqp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqp8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_uint8x8_t = vceq_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqs16.c
new file mode 100644
index 000000000..6bb327628
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqs16.c
@@ -0,0 +1,20 @@
+/* Test the `vceqs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqs16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vceq_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqs32.c
new file mode 100644
index 000000000..254cb0737
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqs32.c
@@ -0,0 +1,20 @@
+/* Test the `vceqs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqs32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vceq_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqs8.c
new file mode 100644
index 000000000..f54eb7703
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vceqs8.c
@@ -0,0 +1,20 @@
+/* Test the `vceqs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vceqs8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vceq_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcequ16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcequ16.c
new file mode 100644
index 000000000..f183aa562
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcequ16.c
@@ -0,0 +1,20 @@
+/* Test the `vcequ16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcequ16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vceq_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcequ32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcequ32.c
new file mode 100644
index 000000000..2c15f6fb5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcequ32.c
@@ -0,0 +1,20 @@
+/* Test the `vcequ32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcequ32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vceq_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcequ8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcequ8.c
new file mode 100644
index 000000000..049158578
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcequ8.c
@@ -0,0 +1,20 @@
+/* Test the `vcequ8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcequ8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vceq_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c
new file mode 100644
index 000000000..52d77b3e8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcgeq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c
new file mode 100644
index 000000000..97c6ba820
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcgeq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c
new file mode 100644
index 000000000..e0d33743e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcgeq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c
new file mode 100644
index 000000000..d655943d5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcgeq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c
new file mode 100644
index 000000000..58887c8bb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcgeq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c
new file mode 100644
index 000000000..af891ba48
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcgeq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c
new file mode 100644
index 000000000..a42747c46
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcgeq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgef32.c
new file mode 100644
index 000000000..6b3e502c6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgef32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcge_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcges16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcges16.c
new file mode 100644
index 000000000..7294f37ab
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcges16.c
@@ -0,0 +1,20 @@
+/* Test the `vcges16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcges16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vcge_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcges32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcges32.c
new file mode 100644
index 000000000..3310b9e8c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcges32.c
@@ -0,0 +1,20 @@
+/* Test the `vcges32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcges32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vcge_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcges8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcges8.c
new file mode 100644
index 000000000..d4f2b4e8b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcges8.c
@@ -0,0 +1,20 @@
+/* Test the `vcges8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcges8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vcge_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c
new file mode 100644
index 000000000..1ddc763f3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vcge_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c
new file mode 100644
index 000000000..dd18404c3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vcge_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c
new file mode 100644
index 000000000..38484e16b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgeu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgeu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vcge_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c
new file mode 100644
index 000000000..2fecd4f6a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcgtq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c
new file mode 100644
index 000000000..d6830cb52
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcgtq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c
new file mode 100644
index 000000000..b6ad60d4f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcgtq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c
new file mode 100644
index 000000000..357e33ee2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcgtq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c
new file mode 100644
index 000000000..875e30ffb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcgtq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c
new file mode 100644
index 000000000..691a65dc6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcgtq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c
new file mode 100644
index 000000000..d5148f776
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcgtq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c
new file mode 100644
index 000000000..ea5a97d72
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcgt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgts16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgts16.c
new file mode 100644
index 000000000..24ae89b5d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgts16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgts16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vcgt_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgts32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgts32.c
new file mode 100644
index 000000000..b724e6669
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgts32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgts32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vcgt_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgts8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgts8.c
new file mode 100644
index 000000000..9ab5955b8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgts8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgts8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vcgt_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c
new file mode 100644
index 000000000..c13c5cb29
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vcgt_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c
new file mode 100644
index 000000000..a9e709d0c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vcgt_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c
new file mode 100644
index 000000000..0c4a6aa59
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcgtu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcgtu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vcgt_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c
new file mode 100644
index 000000000..6adad811d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcleq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c
new file mode 100644
index 000000000..076ae2de1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcleq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c
new file mode 100644
index 000000000..e0ac85874
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcleq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c
new file mode 100644
index 000000000..20fe30c78
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcleq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c
new file mode 100644
index 000000000..8d264811c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcleq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c
new file mode 100644
index 000000000..627078190
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcleq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c
new file mode 100644
index 000000000..38500e088
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcleQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcleq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclef32.c
new file mode 100644
index 000000000..02256e753
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclef32.c
@@ -0,0 +1,20 @@
+/* Test the `vclef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcle_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcles16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcles16.c
new file mode 100644
index 000000000..029d2a0a0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcles16.c
@@ -0,0 +1,20 @@
+/* Test the `vcles16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcles16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vcle_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcles32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcles32.c
new file mode 100644
index 000000000..f29b6eede
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcles32.c
@@ -0,0 +1,20 @@
+/* Test the `vcles32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcles32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vcle_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcles8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcles8.c
new file mode 100644
index 000000000..d3de08f2a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcles8.c
@@ -0,0 +1,20 @@
+/* Test the `vcles8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcles8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vcle_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleu16.c
new file mode 100644
index 000000000..f6d8f805a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcleu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vcle_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleu32.c
new file mode 100644
index 000000000..853222033
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcleu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vcle_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleu8.c
new file mode 100644
index 000000000..6043941ea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcleu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcleu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcleu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vcle_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c
new file mode 100644
index 000000000..34ab6f438
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vclsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vclsq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c
new file mode 100644
index 000000000..2db0d672f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vclsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vclsq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c
new file mode 100644
index 000000000..191a2d009
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vclsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vclsq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclss16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclss16.c
new file mode 100644
index 000000000..c765308b6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclss16.c
@@ -0,0 +1,19 @@
+/* Test the `vclss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vcls_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclss32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclss32.c
new file mode 100644
index 000000000..1eae0d404
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclss32.c
@@ -0,0 +1,19 @@
+/* Test the `vclss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vcls_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclss8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclss8.c
new file mode 100644
index 000000000..9c405a876
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclss8.c
@@ -0,0 +1,19 @@
+/* Test the `vclss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vcls_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c
new file mode 100644
index 000000000..7cdb46ab0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcltq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c
new file mode 100644
index 000000000..e7bfb19bf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcltq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c
new file mode 100644
index 000000000..abe15d2ca
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcltq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c
new file mode 100644
index 000000000..209bdee63
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcltq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c
new file mode 100644
index 000000000..03d1abbc6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcltq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c
new file mode 100644
index 000000000..221fe483a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcltq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c
new file mode 100644
index 000000000..69c63fd6e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcltQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcltq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltf32.c
new file mode 100644
index 000000000..ad0463bc0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltf32.c
@@ -0,0 +1,20 @@
+/* Test the `vcltf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vclt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclts16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclts16.c
new file mode 100644
index 000000000..65cf14e50
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclts16.c
@@ -0,0 +1,20 @@
+/* Test the `vclts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclts16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vclt_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclts32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclts32.c
new file mode 100644
index 000000000..a349dce64
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclts32.c
@@ -0,0 +1,20 @@
+/* Test the `vclts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclts32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vclt_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclts8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclts8.c
new file mode 100644
index 000000000..48f2bfb55
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclts8.c
@@ -0,0 +1,20 @@
+/* Test the `vclts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclts8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vclt_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltu16.c
new file mode 100644
index 000000000..b98f8bb53
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcltu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vclt_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltu32.c
new file mode 100644
index 000000000..cd219eea9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcltu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vclt_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltu8.c
new file mode 100644
index 000000000..88f66a251
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcltu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcltu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcltu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vclt_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c
new file mode 100644
index 000000000..11cb6c504
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vclzq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c
new file mode 100644
index 000000000..13ffe35c7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vclzq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c
new file mode 100644
index 000000000..80040052f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vclzq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c
new file mode 100644
index 000000000..23069ad99
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vclzq_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c
new file mode 100644
index 000000000..48d27fdb6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vclzq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c
new file mode 100644
index 000000000..f5249ef0e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c
@@ -0,0 +1,19 @@
+/* Test the `vclzQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vclzq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzs16.c
new file mode 100644
index 000000000..004dce96f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzs16.c
@@ -0,0 +1,19 @@
+/* Test the `vclzs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vclz_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzs32.c
new file mode 100644
index 000000000..5b650f367
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzs32.c
@@ -0,0 +1,19 @@
+/* Test the `vclzs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vclz_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzs8.c
new file mode 100644
index 000000000..460f1ff49
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzs8.c
@@ -0,0 +1,19 @@
+/* Test the `vclzs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vclz_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzu16.c
new file mode 100644
index 000000000..90fb91bb0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzu16.c
@@ -0,0 +1,19 @@
+/* Test the `vclzu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vclz_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzu32.c
new file mode 100644
index 000000000..1b7fffc95
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzu32.c
@@ -0,0 +1,19 @@
+/* Test the `vclzu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vclz_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzu8.c
new file mode 100644
index 000000000..df256ce1e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vclzu8.c
@@ -0,0 +1,19 @@
+/* Test the `vclzu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vclzu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vclz_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c
new file mode 100644
index 000000000..5622ffc9e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c
@@ -0,0 +1,19 @@
+/* Test the `vcntQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcntQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vcntq_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c
new file mode 100644
index 000000000..61d13f20c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vcntQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcntQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vcntq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c
new file mode 100644
index 000000000..4a72cbb1a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c
@@ -0,0 +1,19 @@
+/* Test the `vcntQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcntQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vcntq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcntp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcntp8.c
new file mode 100644
index 000000000..39acf6e06
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcntp8.c
@@ -0,0 +1,19 @@
+/* Test the `vcntp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcntp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vcnt_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcnts8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcnts8.c
new file mode 100644
index 000000000..cc51c60f3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcnts8.c
@@ -0,0 +1,19 @@
+/* Test the `vcnts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcnts8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vcnt_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcntu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcntu8.c
new file mode 100644
index 000000000..925f74147
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcntu8.c
@@ -0,0 +1,19 @@
+/* Test the `vcntu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcntu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vcnt_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c
new file mode 100644
index 000000000..4e6236c0d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c
@@ -0,0 +1,19 @@
+/* Test the `vcombinef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombinef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x4_t = vcombine_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c
new file mode 100644
index 000000000..5d966ee52
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c
@@ -0,0 +1,19 @@
+/* Test the `vcombinep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombinep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x8_t = vcombine_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c
new file mode 100644
index 000000000..4c5b7e408
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c
@@ -0,0 +1,19 @@
+/* Test the `vcombinep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombinep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x16_t = vcombine_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombines16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombines16.c
new file mode 100644
index 000000000..066bd8c9c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombines16.c
@@ -0,0 +1,19 @@
+/* Test the `vcombines16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombines16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vcombine_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombines32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombines32.c
new file mode 100644
index 000000000..e20b4c429
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombines32.c
@@ -0,0 +1,19 @@
+/* Test the `vcombines32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombines32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vcombine_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombines64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombines64.c
new file mode 100644
index 000000000..2a36c3130
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombines64.c
@@ -0,0 +1,19 @@
+/* Test the `vcombines64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombines64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x2_t = vcombine_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombines8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombines8.c
new file mode 100644
index 000000000..16985c64b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombines8.c
@@ -0,0 +1,19 @@
+/* Test the `vcombines8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombines8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x16_t = vcombine_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c
new file mode 100644
index 000000000..3a850b057
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c
@@ -0,0 +1,19 @@
+/* Test the `vcombineu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombineu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x8_t = vcombine_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c
new file mode 100644
index 000000000..bf4689918
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c
@@ -0,0 +1,19 @@
+/* Test the `vcombineu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombineu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x4_t = vcombine_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c
new file mode 100644
index 000000000..b9417c480
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c
@@ -0,0 +1,19 @@
+/* Test the `vcombineu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombineu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x2_t = vcombine_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c
new file mode 100644
index 000000000..156b67855
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c
@@ -0,0 +1,19 @@
+/* Test the `vcombineu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcombineu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x16_t = vcombine_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c
new file mode 100644
index 000000000..bbd88782a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c
@@ -0,0 +1,18 @@
+/* Test the `vcreatef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreatef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_float32x2_t = vcreate_f32 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c
new file mode 100644
index 000000000..3a90e4dae
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c
@@ -0,0 +1,18 @@
+/* Test the `vcreatep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreatep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint64_t arg0_uint64_t;
+
+  out_poly16x4_t = vcreate_p16 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c
new file mode 100644
index 000000000..c91a1dc70
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c
@@ -0,0 +1,18 @@
+/* Test the `vcreatep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreatep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint64_t arg0_uint64_t;
+
+  out_poly8x8_t = vcreate_p8 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreates16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreates16.c
new file mode 100644
index 000000000..912d19b04
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreates16.c
@@ -0,0 +1,18 @@
+/* Test the `vcreates16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreates16 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint64_t arg0_uint64_t;
+
+  out_int16x4_t = vcreate_s16 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreates32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreates32.c
new file mode 100644
index 000000000..18455b3d0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreates32.c
@@ -0,0 +1,18 @@
+/* Test the `vcreates32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreates32 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_int32x2_t = vcreate_s32 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreates64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreates64.c
new file mode 100644
index 000000000..a46d2c26f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreates64.c
@@ -0,0 +1,18 @@
+/* Test the `vcreates64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreates64 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_int64x1_t = vcreate_s64 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreates8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreates8.c
new file mode 100644
index 000000000..eb13d0822
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreates8.c
@@ -0,0 +1,18 @@
+/* Test the `vcreates8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreates8 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint64_t arg0_uint64_t;
+
+  out_int8x8_t = vcreate_s8 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c
new file mode 100644
index 000000000..e7f78b4b5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c
@@ -0,0 +1,18 @@
+/* Test the `vcreateu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreateu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint16x4_t = vcreate_u16 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c
new file mode 100644
index 000000000..5014d0f22
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c
@@ -0,0 +1,18 @@
+/* Test the `vcreateu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreateu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint32x2_t = vcreate_u32 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c
new file mode 100644
index 000000000..917fe77ee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c
@@ -0,0 +1,18 @@
+/* Test the `vcreateu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreateu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x1_t = vcreate_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c
new file mode 100644
index 000000000..d47561868
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c
@@ -0,0 +1,18 @@
+/* Test the `vcreateu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcreateu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint8x8_t = vcreate_u8 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c
new file mode 100644
index 000000000..90fbf2b0e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQ_nf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_nf32_s32 (void)
+{
+  float32x4_t out_float32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_float32x4_t = vcvtq_n_f32_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c
new file mode 100644
index 000000000..483d5a894
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQ_nf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_nf32_u32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_float32x4_t = vcvtq_n_f32_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c
new file mode 100644
index 000000000..0f111f541
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQ_ns32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_ns32_f32 (void)
+{
+  int32x4_t out_int32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int32x4_t = vcvtq_n_s32_f32 (arg0_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c
new file mode 100644
index 000000000..4f2a40719
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQ_nu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_nu32_f32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint32x4_t = vcvtq_n_u32_f32 (arg0_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c
new file mode 100644
index 000000000..bd81d8b5c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQf32_s32 (void)
+{
+  float32x4_t out_float32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_float32x4_t = vcvtq_f32_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c
new file mode 100644
index 000000000..8ccf41ef2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQf32_u32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_float32x4_t = vcvtq_f32_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c
new file mode 100644
index 000000000..f6e762363
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQs32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQs32_f32 (void)
+{
+  int32x4_t out_int32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int32x4_t = vcvtq_s32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c
new file mode 100644
index 000000000..6d1eed6fc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtQu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtQu32_f32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint32x4_t = vcvtq_u32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c
new file mode 100644
index 000000000..fee5b805d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvt_nf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvt_nf32_s32 (void)
+{
+  float32x2_t out_float32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_float32x2_t = vcvt_n_f32_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c
new file mode 100644
index 000000000..24e1e5f0e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvt_nf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvt_nf32_u32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_float32x2_t = vcvt_n_f32_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c
new file mode 100644
index 000000000..526b95035
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvt_ns32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvt_ns32_f32 (void)
+{
+  int32x2_t out_int32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int32x2_t = vcvt_n_s32_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c
new file mode 100644
index 000000000..059e3de10
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvt_nu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvt_nu32_f32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint32x2_t = vcvt_n_u32_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c
new file mode 100644
index 000000000..fe71a254f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtf32_s32 (void)
+{
+  float32x2_t out_float32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_float32x2_t = vcvt_f32_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c
new file mode 100644
index 000000000..d257a46ca
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtf32_u32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_float32x2_t = vcvt_f32_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c
new file mode 100644
index 000000000..e6b6d91d8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvts32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvts32_f32 (void)
+{
+  int32x2_t out_int32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int32x2_t = vcvt_s32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c
new file mode 100644
index 000000000..6f331e959
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vcvtu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vcvtu32_f32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint32x2_t = vcvt_u32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
new file mode 100644
index 000000000..30f8fee5b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x4_t = vdupq_lane_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
new file mode 100644
index 000000000..bc923571d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x8_t = vdupq_lane_p16 (arg0_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
new file mode 100644
index 000000000..edba0c156
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x16_t = vdupq_lane_p8 (arg0_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
new file mode 100644
index 000000000..b987ac112
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x8_t = vdupq_lane_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
new file mode 100644
index 000000000..1180bce9b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x4_t = vdupq_lane_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c
new file mode 100644
index 000000000..568bf7a08
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c
@@ -0,0 +1,18 @@
+/* Test the `vdupQ_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x2_t = vdupq_lane_s64 (arg0_int64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
new file mode 100644
index 000000000..114bf3251
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x16_t = vdupq_lane_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
new file mode 100644
index 000000000..73a173cf8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x8_t = vdupq_lane_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
new file mode 100644
index 000000000..1266c9f86
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x4_t = vdupq_lane_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c
new file mode 100644
index 000000000..ec7742f15
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c
@@ -0,0 +1,18 @@
+/* Test the `vdupQ_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x2_t = vdupq_lane_u64 (arg0_uint64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
new file mode 100644
index 000000000..14b3d5b80
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x16_t = vdupq_lane_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c
new file mode 100644
index 000000000..c38959a3f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32_t arg0_float32_t;
+
+  out_float32x4_t = vdupq_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c
new file mode 100644
index 000000000..6e3e72641
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x8_t = vdupq_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c
new file mode 100644
index 000000000..647ff2c08
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x16_t = vdupq_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c
new file mode 100644
index 000000000..1fb27efb7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16_t arg0_int16_t;
+
+  out_int16x8_t = vdupq_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c
new file mode 100644
index 000000000..a0e8f7f91
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32_t arg0_int32_t;
+
+  out_int32x4_t = vdupq_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c
new file mode 100644
index 000000000..7147960f4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64_t arg0_int64_t;
+
+  out_int64x2_t = vdupq_n_s64 (arg0_int64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c
new file mode 100644
index 000000000..6f2aea7bd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8_t arg0_int8_t;
+
+  out_int8x16_t = vdupq_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c
new file mode 100644
index 000000000..bbf502016
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x8_t = vdupq_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c
new file mode 100644
index 000000000..e14933578
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x4_t = vdupq_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c
new file mode 100644
index 000000000..d989e6f58
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c
new file mode 100644
index 000000000..81cf6264f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x16_t = vdupq_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
new file mode 100644
index 000000000..4f21c51e0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vdup_lane_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
new file mode 100644
index 000000000..eba3a1b39
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x4_t = vdup_lane_p16 (arg0_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
new file mode 100644
index 000000000..90bdc97cc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vdup_lane_p8 (arg0_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
new file mode 100644
index 000000000..ee7f855e1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vdup_lane_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
new file mode 100644
index 000000000..f16262410
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vdup_lane_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c
new file mode 100644
index 000000000..5d26382a9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c
@@ -0,0 +1,18 @@
+/* Test the `vdup_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vdup_lane_s64 (arg0_int64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
new file mode 100644
index 000000000..8874bc836
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vdup_lane_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
new file mode 100644
index 000000000..244b5a258
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vdup_lane_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
new file mode 100644
index 000000000..8fd5c6a59
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vdup_lane_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c
new file mode 100644
index 000000000..5939b33c3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c
@@ -0,0 +1,18 @@
+/* Test the `vdup_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vdup_lane_u64 (arg0_uint64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
new file mode 100644
index 000000000..2ba6a866d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vdup_lane_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c
new file mode 100644
index 000000000..277b200f9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32_t arg0_float32_t;
+
+  out_float32x2_t = vdup_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c
new file mode 100644
index 000000000..76f1c1740
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x4_t = vdup_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c
new file mode 100644
index 000000000..ea66a607d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x8_t = vdup_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c
new file mode 100644
index 000000000..89794c3e6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16_t arg0_int16_t;
+
+  out_int16x4_t = vdup_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c
new file mode 100644
index 000000000..8b0fed938
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32_t arg0_int32_t;
+
+  out_int32x2_t = vdup_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c
new file mode 100644
index 000000000..53b71216a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64_t arg0_int64_t;
+
+  out_int64x1_t = vdup_n_s64 (arg0_int64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c
new file mode 100644
index 000000000..0d39eec6d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8_t arg0_int8_t;
+
+  out_int8x8_t = vdup_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c
new file mode 100644
index 000000000..eb02c3766
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x4_t = vdup_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c
new file mode 100644
index 000000000..84e8c76fe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x2_t = vdup_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c
new file mode 100644
index 000000000..863fc785c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x1_t = vdup_n_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c
new file mode 100644
index 000000000..4d6ab331a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x8_t = vdup_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQs16.c
new file mode 100644
index 000000000..a2f4ece04
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQs16.c
@@ -0,0 +1,20 @@
+/* Test the `veorQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = veorq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQs32.c
new file mode 100644
index 000000000..8f9cacb19
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQs32.c
@@ -0,0 +1,20 @@
+/* Test the `veorQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = veorq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQs64.c
new file mode 100644
index 000000000..e50bd8c60
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQs64.c
@@ -0,0 +1,20 @@
+/* Test the `veorQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = veorq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQs8.c
new file mode 100644
index 000000000..be5c56b8a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQs8.c
@@ -0,0 +1,20 @@
+/* Test the `veorQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = veorq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQu16.c
new file mode 100644
index 000000000..6ef6b6a8b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQu16.c
@@ -0,0 +1,20 @@
+/* Test the `veorQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = veorq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQu32.c
new file mode 100644
index 000000000..b95ac5039
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQu32.c
@@ -0,0 +1,20 @@
+/* Test the `veorQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = veorq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQu64.c
new file mode 100644
index 000000000..f9f8b1317
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQu64.c
@@ -0,0 +1,20 @@
+/* Test the `veorQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = veorq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQu8.c
new file mode 100644
index 000000000..4aa85679e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veorQu8.c
@@ -0,0 +1,20 @@
+/* Test the `veorQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veorQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = veorq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veors16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veors16.c
new file mode 100644
index 000000000..d6e488f6d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veors16.c
@@ -0,0 +1,20 @@
+/* Test the `veors16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veors16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = veor_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veors32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veors32.c
new file mode 100644
index 000000000..6b897db41
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veors32.c
@@ -0,0 +1,20 @@
+/* Test the `veors32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veors32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = veor_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veors64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veors64.c
new file mode 100644
index 000000000..b82f054e8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veors64.c
@@ -0,0 +1,20 @@
+/* Test the `veors64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veors64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veors8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veors8.c
new file mode 100644
index 000000000..8a33c1e1d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veors8.c
@@ -0,0 +1,20 @@
+/* Test the `veors8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veors8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = veor_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veoru16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veoru16.c
new file mode 100644
index 000000000..418cf80f8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veoru16.c
@@ -0,0 +1,20 @@
+/* Test the `veoru16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veoru16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = veor_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veoru32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veoru32.c
new file mode 100644
index 000000000..06f843739
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veoru32.c
@@ -0,0 +1,20 @@
+/* Test the `veoru32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veoru32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = veor_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veoru64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veoru64.c
new file mode 100644
index 000000000..d73173ecd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veoru64.c
@@ -0,0 +1,20 @@
+/* Test the `veoru64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veoru64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veoru8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veoru8.c
new file mode 100644
index 000000000..87001b746
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/veoru8.c
@@ -0,0 +1,20 @@
+/* Test the `veoru8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_veoru8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = veor_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQf32.c
new file mode 100644
index 000000000..e7d67ce74
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vextQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vextq_f32 (arg0_float32x4_t, arg1_float32x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQp16.c
new file mode 100644
index 000000000..8714a1c3f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQp16.c
@@ -0,0 +1,20 @@
+/* Test the `vextQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vextq_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQp8.c
new file mode 100644
index 000000000..b33fbaf04
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vextQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vextq_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQs16.c
new file mode 100644
index 000000000..81e157bc4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vextQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vextq_s16 (arg0_int16x8_t, arg1_int16x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQs32.c
new file mode 100644
index 000000000..bb964dd5f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vextQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vextq_s32 (arg0_int32x4_t, arg1_int32x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQs64.c
new file mode 100644
index 000000000..dd57bf305
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vextQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vextq_s64 (arg0_int64x2_t, arg1_int64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQs8.c
new file mode 100644
index 000000000..2f334cb91
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vextQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vextq_s8 (arg0_int8x16_t, arg1_int8x16_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQu16.c
new file mode 100644
index 000000000..de8d65ae7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vextQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vextq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQu32.c
new file mode 100644
index 000000000..bac73954e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vextQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vextq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQu64.c
new file mode 100644
index 000000000..31ef034e7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vextQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vextq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQu8.c
new file mode 100644
index 000000000..a894ccef8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vextQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vextq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextf32.c
new file mode 100644
index 000000000..53218b287
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextf32.c
@@ -0,0 +1,20 @@
+/* Test the `vextf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vext_f32 (arg0_float32x2_t, arg1_float32x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextp16.c
new file mode 100644
index 000000000..a352a6e8d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextp16.c
@@ -0,0 +1,20 @@
+/* Test the `vextp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vext_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextp8.c
new file mode 100644
index 000000000..5465cc487
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextp8.c
@@ -0,0 +1,20 @@
+/* Test the `vextp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vext_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vexts16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vexts16.c
new file mode 100644
index 000000000..0aa791b5e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vexts16.c
@@ -0,0 +1,20 @@
+/* Test the `vexts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vexts16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vext_s16 (arg0_int16x4_t, arg1_int16x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vexts32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vexts32.c
new file mode 100644
index 000000000..1087e8aa8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vexts32.c
@@ -0,0 +1,20 @@
+/* Test the `vexts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vexts32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vext_s32 (arg0_int32x2_t, arg1_int32x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vexts64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vexts64.c
new file mode 100644
index 000000000..ca0256da8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vexts64.c
@@ -0,0 +1,20 @@
+/* Test the `vexts64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vexts64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vext_s64 (arg0_int64x1_t, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vexts8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vexts8.c
new file mode 100644
index 000000000..145f80930
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vexts8.c
@@ -0,0 +1,20 @@
+/* Test the `vexts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vexts8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vext_s8 (arg0_int8x8_t, arg1_int8x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextu16.c
new file mode 100644
index 000000000..ca751abfe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextu16.c
@@ -0,0 +1,20 @@
+/* Test the `vextu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vext_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextu32.c
new file mode 100644
index 000000000..4a3d01ef4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextu32.c
@@ -0,0 +1,20 @@
+/* Test the `vextu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vext_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextu64.c
new file mode 100644
index 000000000..3f37d94ea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextu64.c
@@ -0,0 +1,20 @@
+/* Test the `vextu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vext_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextu8.c
new file mode 100644
index 000000000..e2dcc5925
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vextu8.c
@@ -0,0 +1,20 @@
+/* Test the `vextu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vextu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vext_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
new file mode 100644
index 000000000..4d0561b1e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanef32 (void)
+{
+  float32_t out_float32_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32_t = vgetq_lane_f32 (arg0_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
new file mode 100644
index 000000000..a18a38452
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanep16 (void)
+{
+  poly16_t out_poly16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16_t = vgetq_lane_p16 (arg0_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
new file mode 100644
index 000000000..2e6c7d29b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanep8 (void)
+{
+  poly8_t out_poly8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8_t = vgetq_lane_p8 (arg0_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
new file mode 100644
index 000000000..f341ae0e3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes16 (void)
+{
+  int16_t out_int16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16_t = vgetq_lane_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
new file mode 100644
index 000000000..0f87fdb3b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes32 (void)
+{
+  int32_t out_int32_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32_t = vgetq_lane_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c
new file mode 100644
index 000000000..ec361e795
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes64 (void)
+{
+  int64_t out_int64_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64_t = vgetq_lane_s64 (arg0_int64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
new file mode 100644
index 000000000..fa2726a9f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes8 (void)
+{
+  int8_t out_int8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8_t = vgetq_lane_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
new file mode 100644
index 000000000..2c2a94063
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu16 (void)
+{
+  uint16_t out_uint16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16_t = vgetq_lane_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
new file mode 100644
index 000000000..5a9344a80
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu32 (void)
+{
+  uint32_t out_uint32_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32_t = vgetq_lane_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c
new file mode 100644
index 000000000..8cdab031f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu64 (void)
+{
+  uint64_t out_uint64_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64_t = vgetq_lane_u64 (arg0_uint64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
new file mode 100644
index 000000000..df63fc110
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vgetQ_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu8 (void)
+{
+  uint8_t out_uint8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8_t = vgetq_lane_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c
new file mode 100644
index 000000000..5176c5bb0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x2_t = vget_high_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c
new file mode 100644
index 000000000..e58700839
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x4_t = vget_high_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c
new file mode 100644
index 000000000..0feab86eb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x8_t = vget_high_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c
new file mode 100644
index 000000000..786428a0b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x4_t = vget_high_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c
new file mode 100644
index 000000000..515ba139d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x2_t = vget_high_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c
new file mode 100644
index 000000000..f191556f8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x1_t = vget_high_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c
new file mode 100644
index 000000000..1c057b7df
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x8_t = vget_high_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c
new file mode 100644
index 000000000..d3f070244
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x4_t = vget_high_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c
new file mode 100644
index 000000000..bd9cb4bbc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x2_t = vget_high_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c
new file mode 100644
index 000000000..b791863c8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x1_t = vget_high_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c
new file mode 100644
index 000000000..f8c804ba5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c
@@ -0,0 +1,18 @@
+/* Test the `vget_highu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_highu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x8_t = vget_high_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
new file mode 100644
index 000000000..e469c6ec4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lanef32 (void)
+{
+  float32_t out_float32_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32_t = vget_lane_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
new file mode 100644
index 000000000..22851e7b2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lanep16 (void)
+{
+  poly16_t out_poly16_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16_t = vget_lane_p16 (arg0_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
new file mode 100644
index 000000000..83c9a15be
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lanep8 (void)
+{
+  poly8_t out_poly8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8_t = vget_lane_p8 (arg0_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
new file mode 100644
index 000000000..d7feb6ec7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes16 (void)
+{
+  int16_t out_int16_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16_t = vget_lane_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
new file mode 100644
index 000000000..50b8f40cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes32 (void)
+{
+  int32_t out_int32_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32_t = vget_lane_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c
new file mode 100644
index 000000000..f70a47793
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes64 (void)
+{
+  int64_t out_int64_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
new file mode 100644
index 000000000..86fcf63e3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes8 (void)
+{
+  int8_t out_int8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8_t = vget_lane_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
new file mode 100644
index 000000000..363fa2ba4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu16 (void)
+{
+  uint16_t out_uint16_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16_t = vget_lane_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
new file mode 100644
index 000000000..fd09ad4d0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu32 (void)
+{
+  uint32_t out_uint32_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32_t = vget_lane_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c
new file mode 100644
index 000000000..3f1891067
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu64 (void)
+{
+  uint64_t out_uint64_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
new file mode 100644
index 000000000..f244a75c9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu8 (void)
+{
+  uint8_t out_uint8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8_t = vget_lane_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c
new file mode 100644
index 000000000..ae63430f7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lowf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x2_t = vget_low_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c
new file mode 100644
index 000000000..c24ac0cf1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lowp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x4_t = vget_low_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c
new file mode 100644
index 000000000..45d65bcaf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lowp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x8_t = vget_low_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c
new file mode 100644
index 000000000..8e6c29aa7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lows16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lows16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x4_t = vget_low_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c
new file mode 100644
index 000000000..e018afd7f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lows32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lows32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x2_t = vget_low_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c
new file mode 100644
index 000000000..e2e2bd66f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lows64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lows64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x1_t = vget_low_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c
new file mode 100644
index 000000000..0be24de35
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lows8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lows8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x8_t = vget_low_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c
new file mode 100644
index 000000000..67bcd5090
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x4_t = vget_low_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c
new file mode 100644
index 000000000..d21d97acd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x2_t = vget_low_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c
new file mode 100644
index 000000000..79cf1c53d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x1_t = vget_low_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c
new file mode 100644
index 000000000..03996493c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x8_t = vget_low_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c
new file mode 100644
index 000000000..69e15afc3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c
new file mode 100644
index 000000000..76f5c0a94
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c
new file mode 100644
index 000000000..403c77c54
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c
new file mode 100644
index 000000000..aebfc02cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c
new file mode 100644
index 000000000..72f237395
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c
new file mode 100644
index 000000000..bcfe44c09
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhadds16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhadds16.c
new file mode 100644
index 000000000..d412ccced
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhadds16.c
@@ -0,0 +1,20 @@
+/* Test the `vhadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhadds32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhadds32.c
new file mode 100644
index 000000000..db1749e03
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhadds32.c
@@ -0,0 +1,20 @@
+/* Test the `vhadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhadds8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhadds8.c
new file mode 100644
index 000000000..086f5690a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhadds8.c
@@ -0,0 +1,20 @@
+/* Test the `vhadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c
new file mode 100644
index 000000000..1f230e136
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c
new file mode 100644
index 000000000..fbdc8efb5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c
new file mode 100644
index 000000000..38b82bc9e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c
@@ -0,0 +1,20 @@
+/* Test the `vhaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c
new file mode 100644
index 000000000..df790e430
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vhsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c
new file mode 100644
index 000000000..044217375
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vhsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c
new file mode 100644
index 000000000..b98ada251
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vhsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c
new file mode 100644
index 000000000..b8ded58eb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vhsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c
new file mode 100644
index 000000000..f8e2bfe0b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vhsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c
new file mode 100644
index 000000000..b3ca8b4f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vhsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c
new file mode 100644
index 000000000..841f9f24b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vhsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c
new file mode 100644
index 000000000..8564c4c7d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vhsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c
new file mode 100644
index 000000000..7bd4ec3fd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vhsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c
new file mode 100644
index 000000000..e5fab5165
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vhsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c
new file mode 100644
index 000000000..ea6bf12d7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vhsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c
new file mode 100644
index 000000000..d4569d83f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c
@@ -0,0 +1,20 @@
+/* Test the `vhsubu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vhsubu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vhsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
new file mode 100644
index 000000000..0989045f7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupf32 (void)
+{
+  float32x4_t out_float32x4_t;
+
+  out_float32x4_t = vld1q_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
new file mode 100644
index 000000000..ba9e56fd2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+
+  out_poly16x8_t = vld1q_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
new file mode 100644
index 000000000..b914ff2a6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+
+  out_poly8x16_t = vld1q_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
new file mode 100644
index 000000000..6be2a73f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups16 (void)
+{
+  int16x8_t out_int16x8_t;
+
+  out_int16x8_t = vld1q_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
new file mode 100644
index 000000000..37b47a667
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups32 (void)
+{
+  int32x4_t out_int32x4_t;
+
+  out_int32x4_t = vld1q_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
new file mode 100644
index 000000000..a7199f096
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups64 (void)
+{
+  int64x2_t out_int64x2_t;
+
+  out_int64x2_t = vld1q_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
new file mode 100644
index 000000000..b540c2d98
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups8 (void)
+{
+  int8x16_t out_int8x16_t;
+
+  out_int8x16_t = vld1q_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
new file mode 100644
index 000000000..23a6adefb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+
+  out_uint16x8_t = vld1q_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
new file mode 100644
index 000000000..4b8c2ba60
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+
+  out_uint32x4_t = vld1q_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
new file mode 100644
index 000000000..7c1f803a1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+
+  out_uint64x2_t = vld1q_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
new file mode 100644
index 000000000..94e47c299
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Q_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+
+  out_uint8x16_t = vld1q_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
new file mode 100644
index 000000000..c1bd1d9ee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
new file mode 100644
index 000000000..2c0a1a9b1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
new file mode 100644
index 000000000..171954966
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
new file mode 100644
index 000000000..9342b196b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
new file mode 100644
index 000000000..3751aa641
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
new file mode 100644
index 000000000..b5fafa9f8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
new file mode 100644
index 000000000..44c39177b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
new file mode 100644
index 000000000..19fd69f98
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
new file mode 100644
index 000000000..b66d4e418
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
new file mode 100644
index 000000000..ef77c5b9b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
new file mode 100644
index 000000000..70f1b6e3b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
new file mode 100644
index 000000000..d41bfc68f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qf32 (void)
+{
+  float32x4_t out_float32x4_t;
+
+  out_float32x4_t = vld1q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
new file mode 100644
index 000000000..2be07496d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+
+  out_poly16x8_t = vld1q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
new file mode 100644
index 000000000..f6ddd396e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+
+  out_poly8x16_t = vld1q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
new file mode 100644
index 000000000..790c3714b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs16 (void)
+{
+  int16x8_t out_int16x8_t;
+
+  out_int16x8_t = vld1q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
new file mode 100644
index 000000000..66c28eb01
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs32 (void)
+{
+  int32x4_t out_int32x4_t;
+
+  out_int32x4_t = vld1q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
new file mode 100644
index 000000000..4ee914516
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs64 (void)
+{
+  int64x2_t out_int64x2_t;
+
+  out_int64x2_t = vld1q_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
new file mode 100644
index 000000000..28aad33fb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+
+  out_int8x16_t = vld1q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
new file mode 100644
index 000000000..cbf758c18
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+
+  out_uint16x8_t = vld1q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
new file mode 100644
index 000000000..6f7c45aa4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+
+  out_uint32x4_t = vld1q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
new file mode 100644
index 000000000..90a191b3b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+
+  out_uint64x2_t = vld1q_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
new file mode 100644
index 000000000..b55be21ac
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+
+  out_uint8x16_t = vld1q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
new file mode 100644
index 000000000..dc0380180
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupf32 (void)
+{
+  float32x2_t out_float32x2_t;
+
+  out_float32x2_t = vld1_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
new file mode 100644
index 000000000..cb87a398b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+
+  out_poly16x4_t = vld1_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
new file mode 100644
index 000000000..9dd5be305
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+
+  out_poly8x8_t = vld1_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
new file mode 100644
index 000000000..ca5b29153
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups16 (void)
+{
+  int16x4_t out_int16x4_t;
+
+  out_int16x4_t = vld1_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
new file mode 100644
index 000000000..b5652054f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups32 (void)
+{
+  int32x2_t out_int32x2_t;
+
+  out_int32x2_t = vld1_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
new file mode 100644
index 000000000..723ae79e8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups64 (void)
+{
+  int64x1_t out_int64x1_t;
+
+  out_int64x1_t = vld1_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
new file mode 100644
index 000000000..ca78ecf5b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups8 (void)
+{
+  int8x8_t out_int8x8_t;
+
+  out_int8x8_t = vld1_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
new file mode 100644
index 000000000..f6ffab61f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+
+  out_uint16x4_t = vld1_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
new file mode 100644
index 000000000..8a769b06c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+
+  out_uint32x2_t = vld1_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
new file mode 100644
index 000000000..8108c6d49
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+
+  out_uint64x1_t = vld1_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
new file mode 100644
index 000000000..dac97a6b4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+
+  out_uint8x8_t = vld1_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
new file mode 100644
index 000000000..512db1c10
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
new file mode 100644
index 000000000..60abc9b2d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
new file mode 100644
index 000000000..60b2f1ece
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
new file mode 100644
index 000000000..25f07cf93
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
new file mode 100644
index 000000000..a166c431d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
new file mode 100644
index 000000000..09b658a8c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
new file mode 100644
index 000000000..12eb7a0f9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
new file mode 100644
index 000000000..2295380cf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
new file mode 100644
index 000000000..6c540e131
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
new file mode 100644
index 000000000..4507ae895
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
new file mode 100644
index 000000000..5dc352d83
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
new file mode 100644
index 000000000..6b493547a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1f32 (void)
+{
+  float32x2_t out_float32x2_t;
+
+  out_float32x2_t = vld1_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
new file mode 100644
index 000000000..80c2240b6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1p16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+
+  out_poly16x4_t = vld1_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
new file mode 100644
index 000000000..588ee4f2f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+
+  out_poly8x8_t = vld1_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
new file mode 100644
index 000000000..cc8277b8b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1s16 (void)
+{
+  int16x4_t out_int16x4_t;
+
+  out_int16x4_t = vld1_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
new file mode 100644
index 000000000..575bf39b8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1s32 (void)
+{
+  int32x2_t out_int32x2_t;
+
+  out_int32x2_t = vld1_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
new file mode 100644
index 000000000..0af7c1c20
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1s64 (void)
+{
+  int64x1_t out_int64x1_t;
+
+  out_int64x1_t = vld1_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
new file mode 100644
index 000000000..d63836b4d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1s8 (void)
+{
+  int8x8_t out_int8x8_t;
+
+  out_int8x8_t = vld1_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
new file mode 100644
index 000000000..6419661cf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
@@ -0,0 +1,18 @@
+/* Test the `vld1u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1u16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+
+  out_uint16x4_t = vld1_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
new file mode 100644
index 000000000..20306f3f0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
@@ -0,0 +1,18 @@
+/* Test the `vld1u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1u32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+
+  out_uint32x2_t = vld1_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
new file mode 100644
index 000000000..f992088a9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
@@ -0,0 +1,18 @@
+/* Test the `vld1u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1u64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+
+  out_uint64x1_t = vld1_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
new file mode 100644
index 000000000..d8bac1f49
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
@@ -0,0 +1,18 @@
+/* Test the `vld1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld1u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+
+  out_uint8x8_t = vld1_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
new file mode 100644
index 000000000..c2c32cc04
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanef32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4x2_t arg1_float32x4x2_t;
+
+  out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
new file mode 100644
index 000000000..5b5dec000
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanep16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8x2_t arg1_poly16x8x2_t;
+
+  out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
new file mode 100644
index 000000000..43582692c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanes16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8x2_t arg1_int16x8x2_t;
+
+  out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
new file mode 100644
index 000000000..27c4ee83f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanes32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4x2_t arg1_int32x4x2_t;
+
+  out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
new file mode 100644
index 000000000..909df9693
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_laneu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8x2_t arg1_uint16x8x2_t;
+
+  out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
new file mode 100644
index 000000000..72cdaa92c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_laneu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4x2_t arg1_uint32x4x2_t;
+
+  out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
new file mode 100644
index 000000000..dcd895a47
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+
+  out_float32x4x2_t = vld2q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
new file mode 100644
index 000000000..96d74ebe6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+
+  out_poly16x8x2_t = vld2q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
new file mode 100644
index 000000000..6d51f75ce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+
+  out_poly8x16x2_t = vld2q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
new file mode 100644
index 000000000..01c80a087
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+
+  out_int16x8x2_t = vld2q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
new file mode 100644
index 000000000..cd1d22b9c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+
+  out_int32x4x2_t = vld2q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
new file mode 100644
index 000000000..b67f87a55
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+
+  out_int8x16x2_t = vld2q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
new file mode 100644
index 000000000..a5f7b0b90
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+
+  out_uint16x8x2_t = vld2q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
new file mode 100644
index 000000000..9b4e1c089
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+
+  out_uint32x4x2_t = vld2q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
new file mode 100644
index 000000000..952cf65f6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2Qu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+
+  out_uint8x16x2_t = vld2q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
new file mode 100644
index 000000000..ffba7c837
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+
+  out_float32x2x2_t = vld2_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
new file mode 100644
index 000000000..1e40efcc6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+
+  out_poly16x4x2_t = vld2_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
new file mode 100644
index 000000000..f33424f26
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+
+  out_poly8x8x2_t = vld2_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
new file mode 100644
index 000000000..e647bab93
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+
+  out_int16x4x2_t = vld2_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
new file mode 100644
index 000000000..818a5bfd1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+
+  out_int32x2x2_t = vld2_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
new file mode 100644
index 000000000..eaf82c307
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups64 (void)
+{
+  int64x1x2_t out_int64x1x2_t;
+
+  out_int64x1x2_t = vld2_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
new file mode 100644
index 000000000..4fb209521
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+
+  out_int8x8x2_t = vld2_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
new file mode 100644
index 000000000..3ffdc1f99
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+
+  out_uint16x4x2_t = vld2_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
new file mode 100644
index 000000000..bed506a60
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+
+  out_uint32x2x2_t = vld2_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
new file mode 100644
index 000000000..5535a58d8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu64 (void)
+{
+  uint64x1x2_t out_uint64x1x2_t;
+
+  out_uint64x1x2_t = vld2_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
new file mode 100644
index 000000000..6722befce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+
+  out_uint8x8x2_t = vld2_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
new file mode 100644
index 000000000..1daf7311b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanef32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2x2_t arg1_float32x2x2_t;
+
+  out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
new file mode 100644
index 000000000..5384d2c79
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanep16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4x2_t arg1_poly16x4x2_t;
+
+  out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
new file mode 100644
index 000000000..f26b55f3b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanep8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+
+  out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
new file mode 100644
index 000000000..f9596353c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanes16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4x2_t arg1_int16x4x2_t;
+
+  out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
new file mode 100644
index 000000000..f3147c026
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanes32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2x2_t arg1_int32x2x2_t;
+
+  out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
new file mode 100644
index 000000000..60de66309
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanes8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8x2_t arg1_int8x8x2_t;
+
+  out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
new file mode 100644
index 000000000..9f5fbb1de
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_laneu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4x2_t arg1_uint16x4x2_t;
+
+  out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
new file mode 100644
index 000000000..12425bd42
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_laneu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2x2_t arg1_uint32x2x2_t;
+
+  out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
new file mode 100644
index 000000000..2c6fb34d4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2_laneu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+
+  out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
new file mode 100644
index 000000000..f66cd947a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2f32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+
+  out_float32x2x2_t = vld2_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
new file mode 100644
index 000000000..f01c101b7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2p16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+
+  out_poly16x4x2_t = vld2_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
new file mode 100644
index 000000000..972af50d3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2p8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+
+  out_poly8x8x2_t = vld2_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
new file mode 100644
index 000000000..0c678bc7f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2s16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+
+  out_int16x4x2_t = vld2_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
new file mode 100644
index 000000000..cc18c1922
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2s32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+
+  out_int32x2x2_t = vld2_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
new file mode 100644
index 000000000..4534bc467
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
@@ -0,0 +1,18 @@
+/* Test the `vld2s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2s64 (void)
+{
+  int64x1x2_t out_int64x1x2_t;
+
+  out_int64x1x2_t = vld2_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
new file mode 100644
index 000000000..36f18038c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2s8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+
+  out_int8x8x2_t = vld2_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
new file mode 100644
index 000000000..b1c7ab73e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
@@ -0,0 +1,18 @@
+/* Test the `vld2u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2u16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+
+  out_uint16x4x2_t = vld2_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
new file mode 100644
index 000000000..3f01c2632
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
@@ -0,0 +1,18 @@
+/* Test the `vld2u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2u32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+
+  out_uint32x2x2_t = vld2_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
new file mode 100644
index 000000000..5f16b330a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
@@ -0,0 +1,18 @@
+/* Test the `vld2u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2u64 (void)
+{
+  uint64x1x2_t out_uint64x1x2_t;
+
+  out_uint64x1x2_t = vld2_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
new file mode 100644
index 000000000..9bdf75bc1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
@@ -0,0 +1,18 @@
+/* Test the `vld2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld2u8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+
+  out_uint8x8x2_t = vld2_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
new file mode 100644
index 000000000..dc02a4dee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanef32 (void)
+{
+  float32x4x3_t out_float32x4x3_t;
+  float32x4x3_t arg1_float32x4x3_t;
+
+  out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
new file mode 100644
index 000000000..3013d933a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanep16 (void)
+{
+  poly16x8x3_t out_poly16x8x3_t;
+  poly16x8x3_t arg1_poly16x8x3_t;
+
+  out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
new file mode 100644
index 000000000..df711767d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanes16 (void)
+{
+  int16x8x3_t out_int16x8x3_t;
+  int16x8x3_t arg1_int16x8x3_t;
+
+  out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
new file mode 100644
index 000000000..fd1ceefb1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanes32 (void)
+{
+  int32x4x3_t out_int32x4x3_t;
+  int32x4x3_t arg1_int32x4x3_t;
+
+  out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
new file mode 100644
index 000000000..fcf07f2cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_laneu16 (void)
+{
+  uint16x8x3_t out_uint16x8x3_t;
+  uint16x8x3_t arg1_uint16x8x3_t;
+
+  out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
new file mode 100644
index 000000000..5f3e89256
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_laneu32 (void)
+{
+  uint32x4x3_t out_uint32x4x3_t;
+  uint32x4x3_t arg1_uint32x4x3_t;
+
+  out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
new file mode 100644
index 000000000..97c499f78
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qf32 (void)
+{
+  float32x4x3_t out_float32x4x3_t;
+
+  out_float32x4x3_t = vld3q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
new file mode 100644
index 000000000..14c202e24
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qp16 (void)
+{
+  poly16x8x3_t out_poly16x8x3_t;
+
+  out_poly16x8x3_t = vld3q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
new file mode 100644
index 000000000..d58ee32fb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qp8 (void)
+{
+  poly8x16x3_t out_poly8x16x3_t;
+
+  out_poly8x16x3_t = vld3q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
new file mode 100644
index 000000000..6adc17603
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qs16 (void)
+{
+  int16x8x3_t out_int16x8x3_t;
+
+  out_int16x8x3_t = vld3q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
new file mode 100644
index 000000000..92f191c79
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qs32 (void)
+{
+  int32x4x3_t out_int32x4x3_t;
+
+  out_int32x4x3_t = vld3q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
new file mode 100644
index 000000000..a9de5d6f7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qs8 (void)
+{
+  int8x16x3_t out_int8x16x3_t;
+
+  out_int8x16x3_t = vld3q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
new file mode 100644
index 000000000..50c4d51d0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qu16 (void)
+{
+  uint16x8x3_t out_uint16x8x3_t;
+
+  out_uint16x8x3_t = vld3q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
new file mode 100644
index 000000000..6678a87e2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qu32 (void)
+{
+  uint32x4x3_t out_uint32x4x3_t;
+
+  out_uint32x4x3_t = vld3q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
new file mode 100644
index 000000000..6a97f7c24
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3Qu8 (void)
+{
+  uint8x16x3_t out_uint8x16x3_t;
+
+  out_uint8x16x3_t = vld3q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
new file mode 100644
index 000000000..2bbf936b1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupf32 (void)
+{
+  float32x2x3_t out_float32x2x3_t;
+
+  out_float32x2x3_t = vld3_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
new file mode 100644
index 000000000..301888451
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupp16 (void)
+{
+  poly16x4x3_t out_poly16x4x3_t;
+
+  out_poly16x4x3_t = vld3_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
new file mode 100644
index 000000000..76aba84c0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupp8 (void)
+{
+  poly8x8x3_t out_poly8x8x3_t;
+
+  out_poly8x8x3_t = vld3_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
new file mode 100644
index 000000000..08b7c09b1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups16 (void)
+{
+  int16x4x3_t out_int16x4x3_t;
+
+  out_int16x4x3_t = vld3_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
new file mode 100644
index 000000000..016ade44f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups32 (void)
+{
+  int32x2x3_t out_int32x2x3_t;
+
+  out_int32x2x3_t = vld3_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
new file mode 100644
index 000000000..9292d59de
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups64 (void)
+{
+  int64x1x3_t out_int64x1x3_t;
+
+  out_int64x1x3_t = vld3_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
new file mode 100644
index 000000000..959ea3d62
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups8 (void)
+{
+  int8x8x3_t out_int8x8x3_t;
+
+  out_int8x8x3_t = vld3_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
new file mode 100644
index 000000000..633fff514
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu16 (void)
+{
+  uint16x4x3_t out_uint16x4x3_t;
+
+  out_uint16x4x3_t = vld3_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
new file mode 100644
index 000000000..88133e44a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu32 (void)
+{
+  uint32x2x3_t out_uint32x2x3_t;
+
+  out_uint32x2x3_t = vld3_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
new file mode 100644
index 000000000..3eb502461
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu64 (void)
+{
+  uint64x1x3_t out_uint64x1x3_t;
+
+  out_uint64x1x3_t = vld3_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
new file mode 100644
index 000000000..b9a0d9ebb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu8 (void)
+{
+  uint8x8x3_t out_uint8x8x3_t;
+
+  out_uint8x8x3_t = vld3_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
new file mode 100644
index 000000000..30590edad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanef32 (void)
+{
+  float32x2x3_t out_float32x2x3_t;
+  float32x2x3_t arg1_float32x2x3_t;
+
+  out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
new file mode 100644
index 000000000..ea1d05e49
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanep16 (void)
+{
+  poly16x4x3_t out_poly16x4x3_t;
+  poly16x4x3_t arg1_poly16x4x3_t;
+
+  out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
new file mode 100644
index 000000000..1f2674e43
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanep8 (void)
+{
+  poly8x8x3_t out_poly8x8x3_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+
+  out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
new file mode 100644
index 000000000..076128c6f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanes16 (void)
+{
+  int16x4x3_t out_int16x4x3_t;
+  int16x4x3_t arg1_int16x4x3_t;
+
+  out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
new file mode 100644
index 000000000..bd3b3d6f7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanes32 (void)
+{
+  int32x2x3_t out_int32x2x3_t;
+  int32x2x3_t arg1_int32x2x3_t;
+
+  out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
new file mode 100644
index 000000000..551cc39a3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanes8 (void)
+{
+  int8x8x3_t out_int8x8x3_t;
+  int8x8x3_t arg1_int8x8x3_t;
+
+  out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
new file mode 100644
index 000000000..13855ec6d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_laneu16 (void)
+{
+  uint16x4x3_t out_uint16x4x3_t;
+  uint16x4x3_t arg1_uint16x4x3_t;
+
+  out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
new file mode 100644
index 000000000..c3b274a9e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_laneu32 (void)
+{
+  uint32x2x3_t out_uint32x2x3_t;
+  uint32x2x3_t arg1_uint32x2x3_t;
+
+  out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
new file mode 100644
index 000000000..ddfabd3f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3_laneu8 (void)
+{
+  uint8x8x3_t out_uint8x8x3_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+
+  out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
new file mode 100644
index 000000000..7e52b37b4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3f32 (void)
+{
+  float32x2x3_t out_float32x2x3_t;
+
+  out_float32x2x3_t = vld3_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
new file mode 100644
index 000000000..123deeb77
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3p16 (void)
+{
+  poly16x4x3_t out_poly16x4x3_t;
+
+  out_poly16x4x3_t = vld3_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
new file mode 100644
index 000000000..8fabf5e38
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3p8 (void)
+{
+  poly8x8x3_t out_poly8x8x3_t;
+
+  out_poly8x8x3_t = vld3_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
new file mode 100644
index 000000000..2b7212ec3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3s16 (void)
+{
+  int16x4x3_t out_int16x4x3_t;
+
+  out_int16x4x3_t = vld3_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
new file mode 100644
index 000000000..9dfc6189c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3s32 (void)
+{
+  int32x2x3_t out_int32x2x3_t;
+
+  out_int32x2x3_t = vld3_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
new file mode 100644
index 000000000..b4b452709
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
@@ -0,0 +1,18 @@
+/* Test the `vld3s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3s64 (void)
+{
+  int64x1x3_t out_int64x1x3_t;
+
+  out_int64x1x3_t = vld3_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
new file mode 100644
index 000000000..2526f1906
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3s8 (void)
+{
+  int8x8x3_t out_int8x8x3_t;
+
+  out_int8x8x3_t = vld3_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
new file mode 100644
index 000000000..54ea8b57d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
@@ -0,0 +1,18 @@
+/* Test the `vld3u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3u16 (void)
+{
+  uint16x4x3_t out_uint16x4x3_t;
+
+  out_uint16x4x3_t = vld3_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
new file mode 100644
index 000000000..d6ab84cb0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
@@ -0,0 +1,18 @@
+/* Test the `vld3u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3u32 (void)
+{
+  uint32x2x3_t out_uint32x2x3_t;
+
+  out_uint32x2x3_t = vld3_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
new file mode 100644
index 000000000..f31c4804d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
@@ -0,0 +1,18 @@
+/* Test the `vld3u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3u64 (void)
+{
+  uint64x1x3_t out_uint64x1x3_t;
+
+  out_uint64x1x3_t = vld3_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
new file mode 100644
index 000000000..3a6f3cc44
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
@@ -0,0 +1,18 @@
+/* Test the `vld3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld3u8 (void)
+{
+  uint8x8x3_t out_uint8x8x3_t;
+
+  out_uint8x8x3_t = vld3_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
new file mode 100644
index 000000000..2d37f626d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanef32 (void)
+{
+  float32x4x4_t out_float32x4x4_t;
+  float32x4x4_t arg1_float32x4x4_t;
+
+  out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
new file mode 100644
index 000000000..5af87b48a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanep16 (void)
+{
+  poly16x8x4_t out_poly16x8x4_t;
+  poly16x8x4_t arg1_poly16x8x4_t;
+
+  out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
new file mode 100644
index 000000000..355f11238
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanes16 (void)
+{
+  int16x8x4_t out_int16x8x4_t;
+  int16x8x4_t arg1_int16x8x4_t;
+
+  out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
new file mode 100644
index 000000000..d8908b68e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanes32 (void)
+{
+  int32x4x4_t out_int32x4x4_t;
+  int32x4x4_t arg1_int32x4x4_t;
+
+  out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
new file mode 100644
index 000000000..17750856f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_laneu16 (void)
+{
+  uint16x8x4_t out_uint16x8x4_t;
+  uint16x8x4_t arg1_uint16x8x4_t;
+
+  out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
new file mode 100644
index 000000000..78ffe9035
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_laneu32 (void)
+{
+  uint32x4x4_t out_uint32x4x4_t;
+  uint32x4x4_t arg1_uint32x4x4_t;
+
+  out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
new file mode 100644
index 000000000..4ebabb3ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qf32 (void)
+{
+  float32x4x4_t out_float32x4x4_t;
+
+  out_float32x4x4_t = vld4q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
new file mode 100644
index 000000000..9f22715ad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qp16 (void)
+{
+  poly16x8x4_t out_poly16x8x4_t;
+
+  out_poly16x8x4_t = vld4q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
new file mode 100644
index 000000000..b1ff16019
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qp8 (void)
+{
+  poly8x16x4_t out_poly8x16x4_t;
+
+  out_poly8x16x4_t = vld4q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
new file mode 100644
index 000000000..2416bf472
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qs16 (void)
+{
+  int16x8x4_t out_int16x8x4_t;
+
+  out_int16x8x4_t = vld4q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
new file mode 100644
index 000000000..29e68e734
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qs32 (void)
+{
+  int32x4x4_t out_int32x4x4_t;
+
+  out_int32x4x4_t = vld4q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
new file mode 100644
index 000000000..8dc99383b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qs8 (void)
+{
+  int8x16x4_t out_int8x16x4_t;
+
+  out_int8x16x4_t = vld4q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
new file mode 100644
index 000000000..d12817c9b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qu16 (void)
+{
+  uint16x8x4_t out_uint16x8x4_t;
+
+  out_uint16x8x4_t = vld4q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
new file mode 100644
index 000000000..4122cb654
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qu32 (void)
+{
+  uint32x4x4_t out_uint32x4x4_t;
+
+  out_uint32x4x4_t = vld4q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
new file mode 100644
index 000000000..bde99675a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4Qu8 (void)
+{
+  uint8x16x4_t out_uint8x16x4_t;
+
+  out_uint8x16x4_t = vld4q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
new file mode 100644
index 000000000..b8e38be28
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupf32 (void)
+{
+  float32x2x4_t out_float32x2x4_t;
+
+  out_float32x2x4_t = vld4_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
new file mode 100644
index 000000000..b5a990050
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupp16 (void)
+{
+  poly16x4x4_t out_poly16x4x4_t;
+
+  out_poly16x4x4_t = vld4_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
new file mode 100644
index 000000000..d85c25276
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupp8 (void)
+{
+  poly8x8x4_t out_poly8x8x4_t;
+
+  out_poly8x8x4_t = vld4_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
new file mode 100644
index 000000000..1b90af65b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups16 (void)
+{
+  int16x4x4_t out_int16x4x4_t;
+
+  out_int16x4x4_t = vld4_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
new file mode 100644
index 000000000..bf448d200
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups32 (void)
+{
+  int32x2x4_t out_int32x2x4_t;
+
+  out_int32x2x4_t = vld4_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
new file mode 100644
index 000000000..9c14ca182
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups64 (void)
+{
+  int64x1x4_t out_int64x1x4_t;
+
+  out_int64x1x4_t = vld4_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
new file mode 100644
index 000000000..25f32d702
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups8 (void)
+{
+  int8x8x4_t out_int8x8x4_t;
+
+  out_int8x8x4_t = vld4_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
new file mode 100644
index 000000000..f2d714fe6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu16 (void)
+{
+  uint16x4x4_t out_uint16x4x4_t;
+
+  out_uint16x4x4_t = vld4_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
new file mode 100644
index 000000000..88ad8baae
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu32 (void)
+{
+  uint32x2x4_t out_uint32x2x4_t;
+
+  out_uint32x2x4_t = vld4_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
new file mode 100644
index 000000000..70186d89e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu64 (void)
+{
+  uint64x1x4_t out_uint64x1x4_t;
+
+  out_uint64x1x4_t = vld4_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
new file mode 100644
index 000000000..c4332e55f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu8 (void)
+{
+  uint8x8x4_t out_uint8x8x4_t;
+
+  out_uint8x8x4_t = vld4_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
new file mode 100644
index 000000000..88996ae7f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanef32 (void)
+{
+  float32x2x4_t out_float32x2x4_t;
+  float32x2x4_t arg1_float32x2x4_t;
+
+  out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
new file mode 100644
index 000000000..5c11a675a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanep16 (void)
+{
+  poly16x4x4_t out_poly16x4x4_t;
+  poly16x4x4_t arg1_poly16x4x4_t;
+
+  out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
new file mode 100644
index 000000000..2fdbbc869
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanep8 (void)
+{
+  poly8x8x4_t out_poly8x8x4_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+
+  out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
new file mode 100644
index 000000000..370a256fe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanes16 (void)
+{
+  int16x4x4_t out_int16x4x4_t;
+  int16x4x4_t arg1_int16x4x4_t;
+
+  out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
new file mode 100644
index 000000000..b0baefd08
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanes32 (void)
+{
+  int32x2x4_t out_int32x2x4_t;
+  int32x2x4_t arg1_int32x2x4_t;
+
+  out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
new file mode 100644
index 000000000..f3383ee30
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanes8 (void)
+{
+  int8x8x4_t out_int8x8x4_t;
+  int8x8x4_t arg1_int8x8x4_t;
+
+  out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
new file mode 100644
index 000000000..7cfddaf0f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_laneu16 (void)
+{
+  uint16x4x4_t out_uint16x4x4_t;
+  uint16x4x4_t arg1_uint16x4x4_t;
+
+  out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
new file mode 100644
index 000000000..3c9397d11
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_laneu32 (void)
+{
+  uint32x2x4_t out_uint32x2x4_t;
+  uint32x2x4_t arg1_uint32x2x4_t;
+
+  out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
new file mode 100644
index 000000000..ef429680a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4_laneu8 (void)
+{
+  uint8x8x4_t out_uint8x8x4_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+
+  out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
new file mode 100644
index 000000000..04a40c68e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4f32 (void)
+{
+  float32x2x4_t out_float32x2x4_t;
+
+  out_float32x2x4_t = vld4_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
new file mode 100644
index 000000000..7852b45e2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4p16 (void)
+{
+  poly16x4x4_t out_poly16x4x4_t;
+
+  out_poly16x4x4_t = vld4_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
new file mode 100644
index 000000000..a13719b67
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4p8 (void)
+{
+  poly8x8x4_t out_poly8x8x4_t;
+
+  out_poly8x8x4_t = vld4_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
new file mode 100644
index 000000000..bf50d09f8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4s16 (void)
+{
+  int16x4x4_t out_int16x4x4_t;
+
+  out_int16x4x4_t = vld4_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
new file mode 100644
index 000000000..eaea85c12
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4s32 (void)
+{
+  int32x2x4_t out_int32x2x4_t;
+
+  out_int32x2x4_t = vld4_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
new file mode 100644
index 000000000..f3572a9ab
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
@@ -0,0 +1,18 @@
+/* Test the `vld4s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4s64 (void)
+{
+  int64x1x4_t out_int64x1x4_t;
+
+  out_int64x1x4_t = vld4_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
new file mode 100644
index 000000000..077650dec
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4s8 (void)
+{
+  int8x8x4_t out_int8x8x4_t;
+
+  out_int8x8x4_t = vld4_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
new file mode 100644
index 000000000..7820fb353
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
@@ -0,0 +1,18 @@
+/* Test the `vld4u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4u16 (void)
+{
+  uint16x4x4_t out_uint16x4x4_t;
+
+  out_uint16x4x4_t = vld4_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
new file mode 100644
index 000000000..32c821927
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
@@ -0,0 +1,18 @@
+/* Test the `vld4u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4u32 (void)
+{
+  uint32x2x4_t out_uint32x2x4_t;
+
+  out_uint32x2x4_t = vld4_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
new file mode 100644
index 000000000..f8946a58d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
@@ -0,0 +1,18 @@
+/* Test the `vld4u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4u64 (void)
+{
+  uint64x1x4_t out_uint64x1x4_t;
+
+  out_uint64x1x4_t = vld4_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
new file mode 100644
index 000000000..c66b105c3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
@@ -0,0 +1,18 @@
+/* Test the `vld4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vld4u8 (void)
+{
+  uint8x8x4_t out_uint8x8x4_t;
+
+  out_uint8x8x4_t = vld4_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
new file mode 100644
index 000000000..8af37bc2e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vmaxq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c
new file mode 100644
index 000000000..8de85673d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vmaxq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c
new file mode 100644
index 000000000..0fb3731de
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vmaxq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c
new file mode 100644
index 000000000..b50939f0d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vmaxq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c
new file mode 100644
index 000000000..bfa6394f7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vmaxq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c
new file mode 100644
index 000000000..0ea042e2b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vmaxq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c
new file mode 100644
index 000000000..7e53e6220
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vmaxq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c
new file mode 100644
index 000000000..f668f2433
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c
new file mode 100644
index 000000000..94a663930
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c
new file mode 100644
index 000000000..4ffbdc43b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c
new file mode 100644
index 000000000..b633aabdc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c
new file mode 100644
index 000000000..60b058b65
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c
new file mode 100644
index 000000000..0acc33a63
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c
new file mode 100644
index 000000000..17a2ede6a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmaxu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmaxu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQf32.c
new file mode 100644
index 000000000..3fe60bac5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vminQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vminq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQs16.c
new file mode 100644
index 000000000..07c413875
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vminQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vminq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQs32.c
new file mode 100644
index 000000000..7bec8e75c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vminQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vminq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQs8.c
new file mode 100644
index 000000000..fb7b544c3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vminQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vminq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQu16.c
new file mode 100644
index 000000000..be13f5ecc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vminQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vminq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQu32.c
new file mode 100644
index 000000000..1ab6fc51a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vminQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vminq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQu8.c
new file mode 100644
index 000000000..5039f2146
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vminQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vminq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminf32.c
new file mode 100644
index 000000000..4f4e772d4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminf32.c
@@ -0,0 +1,20 @@
+/* Test the `vminf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmins16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmins16.c
new file mode 100644
index 000000000..2ada1c10e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmins16.c
@@ -0,0 +1,20 @@
+/* Test the `vmins16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmins16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmins32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmins32.c
new file mode 100644
index 000000000..b0172fa02
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmins32.c
@@ -0,0 +1,20 @@
+/* Test the `vmins32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmins32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmins8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmins8.c
new file mode 100644
index 000000000..99697d5c8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmins8.c
@@ -0,0 +1,20 @@
+/* Test the `vmins8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmins8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminu16.c
new file mode 100644
index 000000000..62a8367b0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminu16.c
@@ -0,0 +1,20 @@
+/* Test the `vminu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminu32.c
new file mode 100644
index 000000000..a6b3dd042
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminu32.c
@@ -0,0 +1,20 @@
+/* Test the `vminu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminu8.c
new file mode 100644
index 000000000..e53ea9d8f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vminu8.c
@@ -0,0 +1,20 @@
+/* Test the `vminu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vminu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
new file mode 100644
index 000000000..a8dc703e2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x4_t = vmlaq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
new file mode 100644
index 000000000..45735bb46
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x8_t = vmlaq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
new file mode 100644
index 000000000..4567e5474
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x4_t = vmlaq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
new file mode 100644
index 000000000..2f816b7c2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x8_t = vmlaq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
new file mode 100644
index 000000000..e01352e34
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x4_t = vmlaq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
new file mode 100644
index 000000000..39fb23037
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32_t arg2_float32_t;
+
+  out_float32x4_t = vmlaq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
new file mode 100644
index 000000000..54b5c86fc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16_t arg2_int16_t;
+
+  out_int16x8_t = vmlaq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
new file mode 100644
index 000000000..52c21915d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32_t arg2_int32_t;
+
+  out_int32x4_t = vmlaq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
new file mode 100644
index 000000000..2691478fc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x8_t = vmlaq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
new file mode 100644
index 000000000..2ad903e74
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x4_t = vmlaq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c
new file mode 100644
index 000000000..207b3300c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vmlaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c
new file mode 100644
index 000000000..f8d3d7289
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vmlaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c
new file mode 100644
index 000000000..52300484f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vmlaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c
new file mode 100644
index 000000000..14597748f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vmlaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c
new file mode 100644
index 000000000..82b5e4493
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vmlaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c
new file mode 100644
index 000000000..7b8bbed47
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vmlaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c
new file mode 100644
index 000000000..d6c22f54a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vmlaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
new file mode 100644
index 000000000..65947891f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmla_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
new file mode 100644
index 000000000..0b3b49500
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmla_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
new file mode 100644
index 000000000..67c03f326
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmla_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
new file mode 100644
index 000000000..9a028e5f6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmla_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
new file mode 100644
index 000000000..820410ca5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmla_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
new file mode 100644
index 000000000..b138b4f38
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32_t arg2_float32_t;
+
+  out_float32x2_t = vmla_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
new file mode 100644
index 000000000..79c8cd76d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int16x4_t = vmla_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
new file mode 100644
index 000000000..af04a34a8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int32x2_t = vmla_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
new file mode 100644
index 000000000..66ed0b588
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x4_t = vmla_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
new file mode 100644
index 000000000..4574fbdd2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmla_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmla_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x2_t = vmla_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c
new file mode 100644
index 000000000..3da54850b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlaf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlaf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmla_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
new file mode 100644
index 000000000..d27decf86
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
new file mode 100644
index 000000000..67d8651f0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
new file mode 100644
index 000000000..5645d066b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_laneu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlal_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
new file mode 100644
index 000000000..6afa8e8dd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_laneu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlal_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
new file mode 100644
index 000000000..03e1f9710
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
new file mode 100644
index 000000000..9b7623295
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
new file mode 100644
index 000000000..7b423f113
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint32x4_t = vmlal_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
new file mode 100644
index 000000000..4195d1ea6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlal_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlal_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint64x2_t = vmlal_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlals16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlals16.c
new file mode 100644
index 000000000..d3ccb6b2a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlals16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlals16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlals32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlals32.c
new file mode 100644
index 000000000..257462e2a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlals32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlals32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlals8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlals8.c
new file mode 100644
index 000000000..8be8a4010
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlals8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlals8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlals8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int16x8_t = vmlal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c
new file mode 100644
index 000000000..614f314fa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlalu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlalu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c
new file mode 100644
index 000000000..6d7c9e4e6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlalu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlalu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c
new file mode 100644
index 000000000..fbb30c644
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlalu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlalu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint16x8_t = vmlal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlas16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlas16.c
new file mode 100644
index 000000000..88630ba64
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlas16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlas16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlas16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmla_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlas32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlas32.c
new file mode 100644
index 000000000..281502d9c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlas32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlas32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlas32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmla_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlas8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlas8.c
new file mode 100644
index 000000000..05e17f3b8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlas8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlas8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlas8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vmla_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlau16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlau16.c
new file mode 100644
index 000000000..a39e61d93
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlau16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlau16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlau16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmla_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlau32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlau32.c
new file mode 100644
index 000000000..35943a9bd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlau32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlau32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlau32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmla_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlau8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlau8.c
new file mode 100644
index 000000000..2876021ac
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlau8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlau8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlau8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vmla_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
new file mode 100644
index 000000000..e7b50dc9a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x4_t = vmlsq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
new file mode 100644
index 000000000..6f33fb4b0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x8_t = vmlsq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
new file mode 100644
index 000000000..989f085de
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x4_t = vmlsq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
new file mode 100644
index 000000000..f47f5d010
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x8_t = vmlsq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
new file mode 100644
index 000000000..b1283eb60
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
new file mode 100644
index 000000000..fd628ffd6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32_t arg2_float32_t;
+
+  out_float32x4_t = vmlsq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
new file mode 100644
index 000000000..71d3ed728
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16_t arg2_int16_t;
+
+  out_int16x8_t = vmlsq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
new file mode 100644
index 000000000..4a9d26ca6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32_t arg2_int32_t;
+
+  out_int32x4_t = vmlsq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
new file mode 100644
index 000000000..bbac90eb6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x8_t = vmlsq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
new file mode 100644
index 000000000..dfd44bae7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x4_t = vmlsq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c
new file mode 100644
index 000000000..7670dd1bc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vmlsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c
new file mode 100644
index 000000000..502647b63
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vmlsq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c
new file mode 100644
index 000000000..9a7cd058e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vmlsq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c
new file mode 100644
index 000000000..5516a562b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vmlsq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c
new file mode 100644
index 000000000..4a6109ab7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vmlsq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c
new file mode 100644
index 000000000..1e5192d71
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vmlsq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c
new file mode 100644
index 000000000..1d92cf0c1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vmlsq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
new file mode 100644
index 000000000..6e7acc43c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmls_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
new file mode 100644
index 000000000..35c4f657c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmls_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
new file mode 100644
index 000000000..6bac73488
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmls_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
new file mode 100644
index 000000000..4a3e246c6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmls_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
new file mode 100644
index 000000000..c20cbd6c6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmls_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
new file mode 100644
index 000000000..7567a17ee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32_t arg2_float32_t;
+
+  out_float32x2_t = vmls_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
new file mode 100644
index 000000000..ebc4c9c08
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int16x4_t = vmls_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
new file mode 100644
index 000000000..7dec64d31
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int32x2_t = vmls_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
new file mode 100644
index 000000000..3ef90d1ad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x4_t = vmls_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
new file mode 100644
index 000000000..9716ede80
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmls_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmls_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x2_t = vmls_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c
new file mode 100644
index 000000000..5c37698d0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmls_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
new file mode 100644
index 000000000..306111bcc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
new file mode 100644
index 000000000..c36675522
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
new file mode 100644
index 000000000..bf239d43f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_laneu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlsl_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
new file mode 100644
index 000000000..8a4b82aea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_laneu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlsl_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
new file mode 100644
index 000000000..ab0feb220
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
new file mode 100644
index 000000000..685e0175a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
new file mode 100644
index 000000000..63fe4a79f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint32x4_t = vmlsl_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
new file mode 100644
index 000000000..ad7ff60d5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsl_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint64x2_t = vmlsl_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c
new file mode 100644
index 000000000..86b498148
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c
new file mode 100644
index 000000000..9e399e41c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c
new file mode 100644
index 000000000..a5fd648ea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int16x8_t = vmlsl_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c
new file mode 100644
index 000000000..95f8f1540
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlslu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlslu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlsl_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c
new file mode 100644
index 000000000..7bdbdcb0d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlslu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlslu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlsl_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c
new file mode 100644
index 000000000..64ab744b4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlslu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlslu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint16x8_t = vmlsl_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlss16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlss16.c
new file mode 100644
index 000000000..9f05cbb76
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlss16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmls_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlss32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlss32.c
new file mode 100644
index 000000000..19a701e4a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlss32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmls_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlss8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlss8.c
new file mode 100644
index 000000000..4e449c731
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlss8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vmls_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c
new file mode 100644
index 000000000..edf534bfa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmls_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c
new file mode 100644
index 000000000..8d0e65a80
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmls_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c
new file mode 100644
index 000000000..cc77dd341
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmlsu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmlsu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vmls_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c
new file mode 100644
index 000000000..7776b34d4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32_t arg0_float32_t;
+
+  out_float32x4_t = vmovq_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c
new file mode 100644
index 000000000..72fbeda4c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x8_t = vmovq_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c
new file mode 100644
index 000000000..d908658d7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x16_t = vmovq_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c
new file mode 100644
index 000000000..77a2a41a7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16_t arg0_int16_t;
+
+  out_int16x8_t = vmovq_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c
new file mode 100644
index 000000000..13ba030f7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32_t arg0_int32_t;
+
+  out_int32x4_t = vmovq_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c
new file mode 100644
index 000000000..7141de1ca
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vmovQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64_t arg0_int64_t;
+
+  out_int64x2_t = vmovq_n_s64 (arg0_int64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c
new file mode 100644
index 000000000..999d709f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8_t arg0_int8_t;
+
+  out_int8x16_t = vmovq_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c
new file mode 100644
index 000000000..f02aca6ea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x8_t = vmovq_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c
new file mode 100644
index 000000000..3c01d39c9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x4_t = vmovq_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c
new file mode 100644
index 000000000..84a4b0421
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vmovQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c
new file mode 100644
index 000000000..30136192a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x16_t = vmovq_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c
new file mode 100644
index 000000000..88fa47b85
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32_t arg0_float32_t;
+
+  out_float32x2_t = vmov_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c
new file mode 100644
index 000000000..5a726bf8b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x4_t = vmov_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c
new file mode 100644
index 000000000..d49655c31
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x8_t = vmov_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c
new file mode 100644
index 000000000..faa4d547e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16_t arg0_int16_t;
+
+  out_int16x4_t = vmov_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c
new file mode 100644
index 000000000..9f31a5c56
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32_t arg0_int32_t;
+
+  out_int32x2_t = vmov_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c
new file mode 100644
index 000000000..c57a0a447
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64_t arg0_int64_t;
+
+  out_int64x1_t = vmov_n_s64 (arg0_int64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c
new file mode 100644
index 000000000..f68b01bd7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8_t arg0_int8_t;
+
+  out_int8x8_t = vmov_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c
new file mode 100644
index 000000000..a6053ebbe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x4_t = vmov_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c
new file mode 100644
index 000000000..9f0634eaf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x2_t = vmov_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c
new file mode 100644
index 000000000..6d6d7c439
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x1_t = vmov_n_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c
new file mode 100644
index 000000000..62f9d4ad2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x8_t = vmov_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovls16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovls16.c
new file mode 100644
index 000000000..08f4a4de3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovls16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x4_t = vmovl_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovls32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovls32.c
new file mode 100644
index 000000000..69d6cc8bb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovls32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x2_t = vmovl_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovls8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovls8.c
new file mode 100644
index 000000000..6619eb0d9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovls8.c
@@ -0,0 +1,19 @@
+/* Test the `vmovls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x8_t = vmovl_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c
new file mode 100644
index 000000000..50978bca7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovlu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x4_t = vmovl_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c
new file mode 100644
index 000000000..190fc0c5c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovlu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x2_t = vmovl_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c
new file mode 100644
index 000000000..b8483e7a8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c
@@ -0,0 +1,19 @@
+/* Test the `vmovlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovlu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x8_t = vmovl_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovns16.c
new file mode 100644
index 000000000..9ce728e74
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovns16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vmovn_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovns32.c
new file mode 100644
index 000000000..e5d6ca1f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovns32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vmovn_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovns64.c
new file mode 100644
index 000000000..5030a42dc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovns64.c
@@ -0,0 +1,19 @@
+/* Test the `vmovns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vmovn_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c
new file mode 100644
index 000000000..85de70c0c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmovnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vmovn_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c
new file mode 100644
index 000000000..72577c4c6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmovnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vmovn_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c
new file mode 100644
index 000000000..96ada07a9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c
@@ -0,0 +1,19 @@
+/* Test the `vmovnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmovnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vmovn_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
new file mode 100644
index 000000000..c06916f79
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x4_t = vmulq_lane_f32 (arg0_float32x4_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
new file mode 100644
index 000000000..82b4c622c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vmulq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
new file mode 100644
index 000000000..a4a4269e5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vmulq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
new file mode 100644
index 000000000..aa8e3372e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x8_t = vmulq_lane_u16 (arg0_uint16x8_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
new file mode 100644
index 000000000..04f060f15
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x4_t = vmulq_lane_u32 (arg0_uint32x4_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
new file mode 100644
index 000000000..ff3f18aef
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32_t arg1_float32_t;
+
+  out_float32x4_t = vmulq_n_f32 (arg0_float32x4_t, arg1_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
new file mode 100644
index 000000000..7db9c73bc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16_t arg1_int16_t;
+
+  out_int16x8_t = vmulq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
new file mode 100644
index 000000000..cc46dc667
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32_t arg1_int32_t;
+
+  out_int32x4_t = vmulq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
new file mode 100644
index 000000000..bff55011d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint16x8_t = vmulq_n_u16 (arg0_uint16x8_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
new file mode 100644
index 000000000..9ab5bf108
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint32x4_t = vmulq_n_u32 (arg0_uint32x4_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c
new file mode 100644
index 000000000..6cd786852
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vmulq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c
new file mode 100644
index 000000000..b46627c22
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vmulq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.p8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c
new file mode 100644
index 000000000..e83d127ca
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vmulq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c
new file mode 100644
index 000000000..282808589
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vmulq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c
new file mode 100644
index 000000000..ddc36f1f2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vmulq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c
new file mode 100644
index 000000000..b5aceec51
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vmulq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c
new file mode 100644
index 000000000..4926b5cb7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vmulq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c
new file mode 100644
index 000000000..431540f46
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vmulq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
new file mode 100644
index 000000000..d5761b38d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmul_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
new file mode 100644
index 000000000..63f91aa39
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmul_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
new file mode 100644
index 000000000..34c99641f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmul_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
new file mode 100644
index 000000000..acca1fe54
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmul_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
new file mode 100644
index 000000000..712b27385
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmul_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
new file mode 100644
index 000000000..b2353e2e5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32_t arg1_float32_t;
+
+  out_float32x2_t = vmul_n_f32 (arg0_float32x2_t, arg1_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
new file mode 100644
index 000000000..1be1ac54b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int16x4_t = vmul_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
new file mode 100644
index 000000000..8ff82bbc6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int32x2_t = vmul_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
new file mode 100644
index 000000000..4821925f3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint16x4_t = vmul_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
new file mode 100644
index 000000000..e55330aa7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmul_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmul_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint32x2_t = vmul_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulf32.c
new file mode 100644
index 000000000..b2078b933
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmul_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
new file mode 100644
index 000000000..2f6cabb91
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
new file mode 100644
index 000000000..711bc3dbb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
new file mode 100644
index 000000000..31151a276
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_laneu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vmull_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
new file mode 100644
index 000000000..be4b6b096
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_laneu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vmull_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
new file mode 100644
index 000000000..6b7f0803d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int32x4_t = vmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
new file mode 100644
index 000000000..19a24d7c8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int64x2_t = vmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
new file mode 100644
index 000000000..32a22aedf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint32x4_t = vmull_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
new file mode 100644
index 000000000..80ba52188
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmull_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmull_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint64x2_t = vmull_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmullp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmullp8.c
new file mode 100644
index 000000000..849537eef
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmullp8.c
@@ -0,0 +1,20 @@
+/* Test the `vmullp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmullp8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly16x8_t = vmull_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.p8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulls16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulls16.c
new file mode 100644
index 000000000..84f8abc48
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulls16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulls32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulls32.c
new file mode 100644
index 000000000..38ca3bccc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulls32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulls8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulls8.c
new file mode 100644
index 000000000..c8652084a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulls8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vmull_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmullu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmullu16.c
new file mode 100644
index 000000000..1ff7232b7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmullu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmullu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmullu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vmull_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmullu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmullu32.c
new file mode 100644
index 000000000..39f910221
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmullu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmullu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmullu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vmull_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmullu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmullu8.c
new file mode 100644
index 000000000..679395efc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmullu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmullu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmullu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vmull_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulp8.c
new file mode 100644
index 000000000..2ec17dd73
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulp8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vmul_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.p8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmuls16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmuls16.c
new file mode 100644
index 000000000..1fb5047d5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmuls16.c
@@ -0,0 +1,20 @@
+/* Test the `vmuls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmuls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmul_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmuls32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmuls32.c
new file mode 100644
index 000000000..2724c389a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmuls32.c
@@ -0,0 +1,20 @@
+/* Test the `vmuls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmuls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmul_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmuls8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmuls8.c
new file mode 100644
index 000000000..79de6b737
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmuls8.c
@@ -0,0 +1,20 @@
+/* Test the `vmuls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmuls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vmul_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulu16.c
new file mode 100644
index 000000000..8c8aeff89
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmulu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmul_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulu32.c
new file mode 100644
index 000000000..c00bb003c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmulu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmul_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulu8.c
new file mode 100644
index 000000000..a6349f4db
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmulu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmulu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmulu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vmul_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c
new file mode 100644
index 000000000..82a159848
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vmvnq_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c
new file mode 100644
index 000000000..32fff2ec7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vmvnq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c
new file mode 100644
index 000000000..9dea79d65
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vmvnq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c
new file mode 100644
index 000000000..223367159
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vmvnq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c
new file mode 100644
index 000000000..7517830f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vmvnq_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c
new file mode 100644
index 000000000..58ebc8ddb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vmvnq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c
new file mode 100644
index 000000000..5cb87429d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vmvnq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c
new file mode 100644
index 000000000..56e01901a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vmvn_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvns16.c
new file mode 100644
index 000000000..d543e3465
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvns16.c
@@ -0,0 +1,19 @@
+/* Test the `vmvns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vmvn_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvns32.c
new file mode 100644
index 000000000..03b8999e6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvns32.c
@@ -0,0 +1,19 @@
+/* Test the `vmvns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vmvn_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvns8.c
new file mode 100644
index 000000000..8e368e368
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvns8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vmvn_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c
new file mode 100644
index 000000000..25209de01
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vmvn_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c
new file mode 100644
index 000000000..9a8133211
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vmvn_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c
new file mode 100644
index 000000000..0668576ab
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c
@@ -0,0 +1,19 @@
+/* Test the `vmvnu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vmvnu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vmvn_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c
new file mode 100644
index 000000000..203232d74
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c
@@ -0,0 +1,19 @@
+/* Test the `vnegQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vnegq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c
new file mode 100644
index 000000000..dbe927730
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vnegQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vnegq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c
new file mode 100644
index 000000000..6f1d81cc5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vnegQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vnegq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c
new file mode 100644
index 000000000..88ae9eb01
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vnegQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vnegq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegf32.c
new file mode 100644
index 000000000..30834574d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegf32.c
@@ -0,0 +1,19 @@
+/* Test the `vnegf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vneg_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegs16.c
new file mode 100644
index 000000000..bf7e9fcef
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegs16.c
@@ -0,0 +1,19 @@
+/* Test the `vnegs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vneg_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegs32.c
new file mode 100644
index 000000000..e0cae01b2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegs32.c
@@ -0,0 +1,19 @@
+/* Test the `vnegs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vneg_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegs8.c
new file mode 100644
index 000000000..242174cc1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vnegs8.c
@@ -0,0 +1,19 @@
+/* Test the `vnegs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vnegs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vneg_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQs16.c
new file mode 100644
index 000000000..3a5a97fad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vornQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vornq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQs32.c
new file mode 100644
index 000000000..ade713492
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vornQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vornq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQs64.c
new file mode 100644
index 000000000..da1e06233
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vornQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vornq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQs8.c
new file mode 100644
index 000000000..d585a1f95
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vornQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vornq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQu16.c
new file mode 100644
index 000000000..b6f38e407
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vornQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vornq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQu32.c
new file mode 100644
index 000000000..5904f8f99
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vornQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vornq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQu64.c
new file mode 100644
index 000000000..ff977d64f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vornQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vornq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQu8.c
new file mode 100644
index 000000000..f60434ba0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vornQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vornq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorns16.c
new file mode 100644
index 000000000..eb26f74b0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorns16.c
@@ -0,0 +1,20 @@
+/* Test the `vorns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vorn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorns32.c
new file mode 100644
index 000000000..de81c7976
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorns32.c
@@ -0,0 +1,20 @@
+/* Test the `vorns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vorn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorns64.c
new file mode 100644
index 000000000..6e8b8e3ca
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorns64.c
@@ -0,0 +1,20 @@
+/* Test the `vorns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorns8.c
new file mode 100644
index 000000000..dfb773070
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorns8.c
@@ -0,0 +1,20 @@
+/* Test the `vorns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vorn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornu16.c
new file mode 100644
index 000000000..8575f9bee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornu16.c
@@ -0,0 +1,20 @@
+/* Test the `vornu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vorn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornu32.c
new file mode 100644
index 000000000..02bac35fc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornu32.c
@@ -0,0 +1,20 @@
+/* Test the `vornu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vorn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornu64.c
new file mode 100644
index 000000000..ce666533c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornu64.c
@@ -0,0 +1,20 @@
+/* Test the `vornu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornu8.c
new file mode 100644
index 000000000..4e3c59393
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vornu8.c
@@ -0,0 +1,20 @@
+/* Test the `vornu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vornu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vorn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c
new file mode 100644
index 000000000..428f30c68
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vorrq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c
new file mode 100644
index 000000000..787a61814
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vorrq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c
new file mode 100644
index 000000000..73ff15f52
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vorrq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c
new file mode 100644
index 000000000..223419925
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vorrq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c
new file mode 100644
index 000000000..5b074abce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vorrq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c
new file mode 100644
index 000000000..55434037a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vorrq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c
new file mode 100644
index 000000000..4b0997999
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vorrq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c
new file mode 100644
index 000000000..679556309
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vorrQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vorrq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrs16.c
new file mode 100644
index 000000000..6f5d139ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrs16.c
@@ -0,0 +1,20 @@
+/* Test the `vorrs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vorr_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrs32.c
new file mode 100644
index 000000000..3410bc2f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrs32.c
@@ -0,0 +1,20 @@
+/* Test the `vorrs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vorr_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrs64.c
new file mode 100644
index 000000000..53725423a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrs64.c
@@ -0,0 +1,20 @@
+/* Test the `vorrs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrs8.c
new file mode 100644
index 000000000..be6136cbc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorrs8.c
@@ -0,0 +1,20 @@
+/* Test the `vorrs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorrs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vorr_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorru16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorru16.c
new file mode 100644
index 000000000..ffd2b40d9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorru16.c
@@ -0,0 +1,20 @@
+/* Test the `vorru16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorru16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vorr_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorru32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorru32.c
new file mode 100644
index 000000000..f7688ea9d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorru32.c
@@ -0,0 +1,20 @@
+/* Test the `vorru32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorru32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vorr_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorru64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorru64.c
new file mode 100644
index 000000000..cf8352fac
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorru64.c
@@ -0,0 +1,20 @@
+/* Test the `vorru64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorru64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorru8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorru8.c
new file mode 100644
index 000000000..c80b2e25d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vorru8.c
@@ -0,0 +1,20 @@
+/* Test the `vorru8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vorru8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vorr_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c
new file mode 100644
index 000000000..c7cc96f2d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQs16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int32x4_t = vpadalq_s16 (arg0_int32x4_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c
new file mode 100644
index 000000000..5051917a2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQs32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int64x2_t = vpadalq_s32 (arg0_int64x2_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c
new file mode 100644
index 000000000..631e3155c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQs8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int16x8_t = vpadalq_s8 (arg0_int16x8_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c
new file mode 100644
index 000000000..dbe27b50a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint32x4_t = vpadalq_u16 (arg0_uint32x4_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c
new file mode 100644
index 000000000..fb13006d2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint64x2_t = vpadalq_u32 (arg0_uint64x2_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c
new file mode 100644
index 000000000..044ac0420
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalQu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint16x8_t = vpadalq_u8 (arg0_uint16x8_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadals16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadals16.c
new file mode 100644
index 000000000..130c63c1f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadals16.c
@@ -0,0 +1,20 @@
+/* Test the `vpadals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadals16 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x2_t = vpadal_s16 (arg0_int32x2_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadals32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadals32.c
new file mode 100644
index 000000000..73f8d1ffc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadals32.c
@@ -0,0 +1,20 @@
+/* Test the `vpadals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadals32 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x1_t = vpadal_s32 (arg0_int64x1_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadals8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadals8.c
new file mode 100644
index 000000000..54f04c8ac
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadals8.c
@@ -0,0 +1,20 @@
+/* Test the `vpadals8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadals8 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x4_t = vpadal_s8 (arg0_int16x4_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c
new file mode 100644
index 000000000..e1e186e4d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalu16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x2_t = vpadal_u16 (arg0_uint32x2_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c
new file mode 100644
index 000000000..44f1f267d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalu32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x1_t = vpadal_u32 (arg0_uint64x1_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c
new file mode 100644
index 000000000..e4a4a18bf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpadalu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadalu8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x4_t = vpadal_u8 (arg0_uint16x4_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c
new file mode 100644
index 000000000..7e999ddf8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vpadd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c
new file mode 100644
index 000000000..ee4590be6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQs16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int32x4_t = vpaddlq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c
new file mode 100644
index 000000000..63f2f007c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQs32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int64x2_t = vpaddlq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c
new file mode 100644
index 000000000..fde7218c7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQs8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int16x8_t = vpaddlq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c
new file mode 100644
index 000000000..7bbff2021
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint32x4_t = vpaddlq_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c
new file mode 100644
index 000000000..0d707a1af
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint64x2_t = vpaddlq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c
new file mode 100644
index 000000000..7ec49a5a7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint16x8_t = vpaddlq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c
new file mode 100644
index 000000000..2cf1f207c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddls16 (void)
+{
+  int32x2_t out_int32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x2_t = vpaddl_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c
new file mode 100644
index 000000000..990f9ad8d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddls32 (void)
+{
+  int64x1_t out_int64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x1_t = vpaddl_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c
new file mode 100644
index 000000000..31aaec3d9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddls8 (void)
+{
+  int16x4_t out_int16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x4_t = vpaddl_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c
new file mode 100644
index 000000000..eda1abd3f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlu16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x2_t = vpaddl_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c
new file mode 100644
index 000000000..dfd53c063
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlu32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x1_t = vpaddl_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c
new file mode 100644
index 000000000..405b00f34
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c
@@ -0,0 +1,19 @@
+/* Test the `vpaddlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddlu8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x4_t = vpaddl_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadds16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadds16.c
new file mode 100644
index 000000000..008762d03
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadds16.c
@@ -0,0 +1,20 @@
+/* Test the `vpadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vpadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadds32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadds32.c
new file mode 100644
index 000000000..03deb9d13
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadds32.c
@@ -0,0 +1,20 @@
+/* Test the `vpadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vpadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadds8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadds8.c
new file mode 100644
index 000000000..49a470057
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpadds8.c
@@ -0,0 +1,20 @@
+/* Test the `vpadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vpadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c
new file mode 100644
index 000000000..d9e9b804d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vpadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c
new file mode 100644
index 000000000..5452e6497
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vpadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c
new file mode 100644
index 000000000..fe967a172
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vpadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c
new file mode 100644
index 000000000..fe8c16728
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vpmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c
new file mode 100644
index 000000000..26effea76
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vpmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c
new file mode 100644
index 000000000..ca26deec0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vpmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c
new file mode 100644
index 000000000..6b6fab5e5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vpmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c
new file mode 100644
index 000000000..c498274bf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vpmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c
new file mode 100644
index 000000000..e2218c347
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vpmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c
new file mode 100644
index 000000000..20da6295a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpmaxu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmaxu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vpmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpminf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpminf32.c
new file mode 100644
index 000000000..0952bdbf3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpminf32.c
@@ -0,0 +1,20 @@
+/* Test the `vpminf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpminf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vpmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmins16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmins16.c
new file mode 100644
index 000000000..fcf8e1eae
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmins16.c
@@ -0,0 +1,20 @@
+/* Test the `vpmins16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmins16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vpmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmins32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmins32.c
new file mode 100644
index 000000000..0ca2213e5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmins32.c
@@ -0,0 +1,20 @@
+/* Test the `vpmins32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmins32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vpmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmins8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmins8.c
new file mode 100644
index 000000000..b103cb901
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpmins8.c
@@ -0,0 +1,20 @@
+/* Test the `vpmins8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpmins8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vpmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpminu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpminu16.c
new file mode 100644
index 000000000..f21479125
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpminu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpminu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpminu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vpmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpminu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpminu32.c
new file mode 100644
index 000000000..5dcc5a573
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpminu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpminu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpminu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vpmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpminu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpminu8.c
new file mode 100644
index 000000000..f2627fa65
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vpminu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpminu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vpminu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vpmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
new file mode 100644
index 000000000..e0a48afd0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vqrdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
new file mode 100644
index 000000000..c82b8a5c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vqrdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
new file mode 100644
index 000000000..410d2918c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16_t arg1_int16_t;
+
+  out_int16x8_t = vqrdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
new file mode 100644
index 000000000..512a64313
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32_t arg1_int32_t;
+
+  out_int32x4_t = vqrdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c
new file mode 100644
index 000000000..e841e0e08
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqrdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c
new file mode 100644
index 000000000..e694c4f2a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqrdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
new file mode 100644
index 000000000..57aa08555
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulh_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqrdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
new file mode 100644
index 000000000..910b08280
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulh_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqrdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
new file mode 100644
index 000000000..f2e1c2c2d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulh_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int16x4_t = vqrdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
new file mode 100644
index 000000000..736e3d622
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulh_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int32x2_t = vqrdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c
new file mode 100644
index 000000000..ce7542a5d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqrdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c
new file mode 100644
index 000000000..00b054c07
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRdmulhs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqrdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c
new file mode 100644
index 000000000..daa4f3b59
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c
new file mode 100644
index 000000000..08afba1f3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c
new file mode 100644
index 000000000..af2a3668f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c
new file mode 100644
index 000000000..92cb8f211
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c
new file mode 100644
index 000000000..534d6ffc1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vqrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c
new file mode 100644
index 000000000..fa084993a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vqrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c
new file mode 100644
index 000000000..8f5d5fb93
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vqrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c
new file mode 100644
index 000000000..4c2b7d286
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vqrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c
new file mode 100644
index 000000000..c6fa26ec6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c
new file mode 100644
index 000000000..3d5e0135c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c
new file mode 100644
index 000000000..ea48f7a15
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c
new file mode 100644
index 000000000..f2fdc51c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c
new file mode 100644
index 000000000..49c6ffde9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vqrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c
new file mode 100644
index 000000000..7475bf1e9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vqrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c
new file mode 100644
index 000000000..20064fdbe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vqrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c
new file mode 100644
index 000000000..24fd9de4c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vqrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c
new file mode 100644
index 000000000..740c885c2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vqrshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c
new file mode 100644
index 000000000..1fc90b709
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vqrshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c
new file mode 100644
index 000000000..4b3412730
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vqrshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c
new file mode 100644
index 000000000..be40d437c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vqrshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c
new file mode 100644
index 000000000..887085593
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vqrshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c
new file mode 100644
index 000000000..41898b425
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vqrshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c
new file mode 100644
index 000000000..85a7e10c9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrun_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x8_t = vqrshrun_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c
new file mode 100644
index 000000000..ffd2053c9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrun_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x4_t = vqrshrun_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
new file mode 100644
index 000000000..bb47b08b9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqRshrun_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x2_t = vqrshrun_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c
new file mode 100644
index 000000000..5d230ed88
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vqabsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vqabsq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c
new file mode 100644
index 000000000..a5ef813ee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vqabsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vqabsq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c
new file mode 100644
index 000000000..9f3a4c7f8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vqabsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vqabsq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabss16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabss16.c
new file mode 100644
index 000000000..597e20f26
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabss16.c
@@ -0,0 +1,19 @@
+/* Test the `vqabss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vqabs_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabss32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabss32.c
new file mode 100644
index 000000000..958587461
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabss32.c
@@ -0,0 +1,19 @@
+/* Test the `vqabss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vqabs_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabss8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabss8.c
new file mode 100644
index 000000000..086ff4902
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqabss8.c
@@ -0,0 +1,19 @@
+/* Test the `vqabss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqabss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vqabs_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c
new file mode 100644
index 000000000..649a7047d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c
new file mode 100644
index 000000000..3c80d27b8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c
new file mode 100644
index 000000000..fd4655196
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqaddq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c
new file mode 100644
index 000000000..583439e4a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c
new file mode 100644
index 000000000..3b1a87437
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vqaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c
new file mode 100644
index 000000000..c4e22fabc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vqaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c
new file mode 100644
index 000000000..80ad826bd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vqaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c
new file mode 100644
index 000000000..c9ec1a762
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vqaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqadds16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqadds16.c
new file mode 100644
index 000000000..b8d9e8dd4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqadds16.c
@@ -0,0 +1,20 @@
+/* Test the `vqadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqadds32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqadds32.c
new file mode 100644
index 000000000..1cb7d2ba4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqadds32.c
@@ -0,0 +1,20 @@
+/* Test the `vqadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqadds64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqadds64.c
new file mode 100644
index 000000000..fd0a4013e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqadds64.c
@@ -0,0 +1,20 @@
+/* Test the `vqadds64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqadds64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqadds8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqadds8.c
new file mode 100644
index 000000000..b64cbf081
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqadds8.c
@@ -0,0 +1,20 @@
+/* Test the `vqadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c
new file mode 100644
index 000000000..41664ecaf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vqadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c
new file mode 100644
index 000000000..3fdeebada
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vqadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c
new file mode 100644
index 000000000..7a4809216
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vqadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c
new file mode 100644
index 000000000..ceb70e2cc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vqadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
new file mode 100644
index 000000000..02e5b0ac2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlal_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
new file mode 100644
index 000000000..925622449
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlal_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
new file mode 100644
index 000000000..24ce9838c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlal_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vqdmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
new file mode 100644
index 000000000..885fecc74
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlal_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vqdmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c
new file mode 100644
index 000000000..a1bdf951d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlals16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c
new file mode 100644
index 000000000..ac858e31c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlals32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
new file mode 100644
index 000000000..bba7153eb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsl_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
new file mode 100644
index 000000000..2c1181470
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsl_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
new file mode 100644
index 000000000..56da4c2e8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vqdmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
new file mode 100644
index 000000000..dad599dd5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vqdmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c
new file mode 100644
index 000000000..80ea5abdd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c
new file mode 100644
index 000000000..daf9a6e17
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmlsls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
new file mode 100644
index 000000000..9c5651266
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vqdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
new file mode 100644
index 000000000..e5a0bf1d3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vqdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
new file mode 100644
index 000000000..7ae3a222a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16_t arg1_int16_t;
+
+  out_int16x8_t = vqdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
new file mode 100644
index 000000000..e742ff540
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32_t arg1_int32_t;
+
+  out_int32x4_t = vqdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c
new file mode 100644
index 000000000..75b7951a6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c
new file mode 100644
index 000000000..b9a19abb4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
new file mode 100644
index 000000000..597032f6b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulh_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
new file mode 100644
index 000000000..1314664f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulh_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
new file mode 100644
index 000000000..537be4eb6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulh_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int16x4_t = vqdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
new file mode 100644
index 000000000..407e61649
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulh_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int32x2_t = vqdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c
new file mode 100644
index 000000000..20c1611ea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c
new file mode 100644
index 000000000..3e76e8ec4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulhs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
new file mode 100644
index 000000000..69309b1f4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmull_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vqdmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
new file mode 100644
index 000000000..ffa26d805
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmull_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vqdmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
new file mode 100644
index 000000000..032a9a6f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmull_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int32x4_t = vqdmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
new file mode 100644
index 000000000..02eec1e8f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmull_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int64x2_t = vqdmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c
new file mode 100644
index 000000000..e3224c596
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vqdmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c
new file mode 100644
index 000000000..7c306985b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c
@@ -0,0 +1,20 @@
+/* Test the `vqdmulls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqdmulls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vqdmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c
new file mode 100644
index 000000000..49d103a3f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vqmovn_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c
new file mode 100644
index 000000000..ed48f200b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vqmovn_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c
new file mode 100644
index 000000000..f3e23481f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vqmovn_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c
new file mode 100644
index 000000000..5ee9b9cd3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vqmovn_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c
new file mode 100644
index 000000000..7bdfb5d6f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vqmovn_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c
new file mode 100644
index 000000000..93c6eb850
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vqmovn_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c
new file mode 100644
index 000000000..3a92133d4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovuns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovuns16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x8_t = vqmovun_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqmovun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c
new file mode 100644
index 000000000..be303c92d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovuns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovuns32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x4_t = vqmovun_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqmovun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c
new file mode 100644
index 000000000..660ac6bd3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqmovuns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqmovuns64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x2_t = vqmovun_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqmovun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
new file mode 100644
index 000000000..eb5ac374b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vqnegq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
new file mode 100644
index 000000000..d84a5fe06
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vqnegq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
new file mode 100644
index 000000000..3907ccdd6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vqnegq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c
new file mode 100644
index 000000000..2d9d99bc1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vqneg_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c
new file mode 100644
index 000000000..e68a827ea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vqneg_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c
new file mode 100644
index 000000000..70312003b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c
@@ -0,0 +1,19 @@
+/* Test the `vqnegs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqnegs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vqneg_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c
new file mode 100644
index 000000000..75e9cc377
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vqshlq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c
new file mode 100644
index 000000000..4b5933ad4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vqshlq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c
new file mode 100644
index 000000000..1b5628037
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vqshlq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c
new file mode 100644
index 000000000..31cf319b5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vqshlq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c
new file mode 100644
index 000000000..56101c239
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vqshlq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c
new file mode 100644
index 000000000..107756673
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vqshlq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c
new file mode 100644
index 000000000..d199c1d9b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vqshlq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c
new file mode 100644
index 000000000..55510f52c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vqshlq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c
new file mode 100644
index 000000000..b4e8a5e84
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c
new file mode 100644
index 000000000..200e2c4e2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c
new file mode 100644
index 000000000..8379c254b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c
new file mode 100644
index 000000000..1804b81f7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c
new file mode 100644
index 000000000..14f5362a1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vqshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c
new file mode 100644
index 000000000..344e654b1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vqshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c
new file mode 100644
index 000000000..bbc4efec5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vqshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c
new file mode 100644
index 000000000..69eb05f08
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vqshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c
new file mode 100644
index 000000000..7992aaf57
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vqshl_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c
new file mode 100644
index 000000000..c7e5b8e72
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vqshl_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c
new file mode 100644
index 000000000..f5de9108c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vqshl_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c
new file mode 100644
index 000000000..70d06838f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vqshl_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c
new file mode 100644
index 000000000..9a0610890
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vqshl_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c
new file mode 100644
index 000000000..85f231cab
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vqshl_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c
new file mode 100644
index 000000000..b91be64f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vqshl_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c
new file mode 100644
index 000000000..71b86c75d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshl_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vqshl_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshls16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshls16.c
new file mode 100644
index 000000000..45ff5de39
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshls16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshls32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshls32.c
new file mode 100644
index 000000000..f4ee413ef
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshls32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshls64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshls64.c
new file mode 100644
index 000000000..590aa7fc2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshls64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshls8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshls8.c
new file mode 100644
index 000000000..a42fe1532
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshls8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c
new file mode 100644
index 000000000..ca5c1a44a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vqshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c
new file mode 100644
index 000000000..0ad2e7297
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vqshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c
new file mode 100644
index 000000000..18b5a794b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vqshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c
new file mode 100644
index 000000000..ac6a2fb9c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vqshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c
new file mode 100644
index 000000000..2cb5910d4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshluQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint16x8_t = vqshluq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c
new file mode 100644
index 000000000..d27c3e830
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshluQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint32x4_t = vqshluq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c
new file mode 100644
index 000000000..c8d397292
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshluQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint64x2_t = vqshluq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c
new file mode 100644
index 000000000..7edcd394c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshluQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint8x16_t = vqshluq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c
new file mode 100644
index 000000000..bf439bae7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlu_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint16x4_t = vqshlu_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c
new file mode 100644
index 000000000..e91e9fc70
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlu_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint32x2_t = vqshlu_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c
new file mode 100644
index 000000000..10ff898ec
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlu_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint64x1_t = vqshlu_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c
new file mode 100644
index 000000000..0bcb6046f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vqshlu_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint8x8_t = vqshlu_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c
new file mode 100644
index 000000000..545397922
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vqshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c
new file mode 100644
index 000000000..69c17e6b9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vqshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c
new file mode 100644
index 000000000..71f1cf1ef
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vqshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c
new file mode 100644
index 000000000..59da1e5d5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vqshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c
new file mode 100644
index 000000000..23b03ca68
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vqshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c
new file mode 100644
index 000000000..7cf626a9e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vqshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c
new file mode 100644
index 000000000..18943f9dd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrun_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrun_ns16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x8_t = vqshrun_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c
new file mode 100644
index 000000000..705b31491
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrun_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrun_ns32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x4_t = vqshrun_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c
new file mode 100644
index 000000000..097d4d32a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vqshrun_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqshrun_ns64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x2_t = vqshrun_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c
new file mode 100644
index 000000000..c270c666b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c
new file mode 100644
index 000000000..e319ba2d4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c
new file mode 100644
index 000000000..0b718f67d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c
new file mode 100644
index 000000000..fc1aba499
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c
new file mode 100644
index 000000000..0e1201973
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vqsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c
new file mode 100644
index 000000000..30c5aeca9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vqsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c
new file mode 100644
index 000000000..ee0953594
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vqsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c
new file mode 100644
index 000000000..506c4448b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vqsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c
new file mode 100644
index 000000000..f6b70bd06
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c
new file mode 100644
index 000000000..0ddfe5a80
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c
new file mode 100644
index 000000000..ad2c75f76
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c
new file mode 100644
index 000000000..b39ed08c6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c
new file mode 100644
index 000000000..d19df3ea0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vqsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c
new file mode 100644
index 000000000..50c298f46
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vqsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c
new file mode 100644
index 000000000..77faa60d1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vqsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c
new file mode 100644
index 000000000..a3cdcc671
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqsubu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vqsubu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vqsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c
new file mode 100644
index 000000000..d1010bca5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrecpeQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpeQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrecpeq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c
new file mode 100644
index 000000000..35a258856
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c
@@ -0,0 +1,19 @@
+/* Test the `vrecpeQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpeQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrecpeq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c
new file mode 100644
index 000000000..f296b9553
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c
@@ -0,0 +1,19 @@
+/* Test the `vrecpef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrecpe_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c
new file mode 100644
index 000000000..3e57d3503
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c
@@ -0,0 +1,19 @@
+/* Test the `vrecpeu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpeu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrecpe_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c
new file mode 100644
index 000000000..213021c69
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrecpsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vrecpsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrecps\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c
new file mode 100644
index 000000000..6e7e41945
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrecpsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrecpsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vrecps_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrecps\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c
new file mode 100644
index 000000000..998c3f0ce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p16 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_float32x4_t = vreinterpretq_f32_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c
new file mode 100644
index 000000000..c68861c11
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p8 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_float32x4_t = vreinterpretq_f32_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c
new file mode 100644
index 000000000..99548c85e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s16 (void)
+{
+  float32x4_t out_float32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_float32x4_t = vreinterpretq_f32_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c
new file mode 100644
index 000000000..13ce5b5c4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s32 (void)
+{
+  float32x4_t out_float32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_float32x4_t = vreinterpretq_f32_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c
new file mode 100644
index 000000000..6cb0d85d1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s64 (void)
+{
+  float32x4_t out_float32x4_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_float32x4_t = vreinterpretq_f32_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c
new file mode 100644
index 000000000..a0b01cfdc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s8 (void)
+{
+  float32x4_t out_float32x4_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_float32x4_t = vreinterpretq_f32_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c
new file mode 100644
index 000000000..b1ef77da8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u16 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_float32x4_t = vreinterpretq_f32_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c
new file mode 100644
index 000000000..bde7baf0d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_float32x4_t = vreinterpretq_f32_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c
new file mode 100644
index 000000000..a72ed95da
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u64 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_float32x4_t = vreinterpretq_f32_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c
new file mode 100644
index 000000000..e77bb9817
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQf32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u8 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_float32x4_t = vreinterpretq_f32_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c
new file mode 100644
index 000000000..019cf583b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_f32 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly16x8_t = vreinterpretq_p16_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c
new file mode 100644
index 000000000..1b51eecb2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_p8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly16x8_t = vreinterpretq_p16_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c
new file mode 100644
index 000000000..8ae9b9dfc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c
new file mode 100644
index 000000000..09f2264e9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s32 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c
new file mode 100644
index 000000000..f7c7af0a4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s64 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c
new file mode 100644
index 000000000..1727461bf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c
new file mode 100644
index 000000000..23c0f9926
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c
new file mode 100644
index 000000000..ad218958c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u32 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c
new file mode 100644
index 000000000..72b5f2559
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u64 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c
new file mode 100644
index 000000000..ce056f527
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c
new file mode 100644
index 000000000..ffe9956cd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_f32 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly8x16_t = vreinterpretq_p8_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c
new file mode 100644
index 000000000..f02d2820c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_p16 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly8x16_t = vreinterpretq_p8_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c
new file mode 100644
index 000000000..dbbf983b5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s16 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c
new file mode 100644
index 000000000..2881005b7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s32 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c
new file mode 100644
index 000000000..2e0242328
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s64 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c
new file mode 100644
index 000000000..61bbc8558
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c
new file mode 100644
index 000000000..0b98d6af1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u16 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c
new file mode 100644
index 000000000..aab2dc1b2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u32 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c
new file mode 100644
index 000000000..9c1a59add
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u64 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c
new file mode 100644
index 000000000..8674e986e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQp8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c
new file mode 100644
index 000000000..8f0667825
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_f32 (void)
+{
+  int16x8_t out_int16x8_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int16x8_t = vreinterpretq_s16_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c
new file mode 100644
index 000000000..8a7a8f03e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p16 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int16x8_t = vreinterpretq_s16_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c
new file mode 100644
index 000000000..e14288d6b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p8 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int16x8_t = vreinterpretq_s16_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c
new file mode 100644
index 000000000..911c95e09
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_s32 (void)
+{
+  int16x8_t out_int16x8_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x8_t = vreinterpretq_s16_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c
new file mode 100644
index 000000000..86eaf663b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_s64 (void)
+{
+  int16x8_t out_int16x8_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int16x8_t = vreinterpretq_s16_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c
new file mode 100644
index 000000000..baa8ee2a9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_s8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int16x8_t = vreinterpretq_s16_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c
new file mode 100644
index 000000000..436f9e6f9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u16 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int16x8_t = vreinterpretq_s16_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c
new file mode 100644
index 000000000..a7bd6f35e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u32 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int16x8_t = vreinterpretq_s16_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c
new file mode 100644
index 000000000..7d0a8a609
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u64 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int16x8_t = vreinterpretq_s16_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c
new file mode 100644
index 000000000..feb8a5528
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u8 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int16x8_t = vreinterpretq_s16_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c
new file mode 100644
index 000000000..366893d16
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_f32 (void)
+{
+  int32x4_t out_int32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int32x4_t = vreinterpretq_s32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c
new file mode 100644
index 000000000..85dca2f74
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p16 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int32x4_t = vreinterpretq_s32_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c
new file mode 100644
index 000000000..19fff80c6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p8 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int32x4_t = vreinterpretq_s32_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c
new file mode 100644
index 000000000..52bf8e5f4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_s16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int32x4_t = vreinterpretq_s32_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c
new file mode 100644
index 000000000..4f8df90dd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_s64 (void)
+{
+  int32x4_t out_int32x4_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x4_t = vreinterpretq_s32_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c
new file mode 100644
index 000000000..a955553a4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_s8 (void)
+{
+  int32x4_t out_int32x4_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int32x4_t = vreinterpretq_s32_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c
new file mode 100644
index 000000000..36f7a3ce8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u16 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int32x4_t = vreinterpretq_s32_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c
new file mode 100644
index 000000000..b3200bf20
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u32 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int32x4_t = vreinterpretq_s32_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c
new file mode 100644
index 000000000..009c9311d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u64 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int32x4_t = vreinterpretq_s32_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c
new file mode 100644
index 000000000..59b13bf4d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u8 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int32x4_t = vreinterpretq_s32_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c
new file mode 100644
index 000000000..27c6c5a88
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_f32 (void)
+{
+  int64x2_t out_int64x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int64x2_t = vreinterpretq_s64_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c
new file mode 100644
index 000000000..ad92c9caf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p16 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int64x2_t = vreinterpretq_s64_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c
new file mode 100644
index 000000000..3850ba2cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p8 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int64x2_t = vreinterpretq_s64_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c
new file mode 100644
index 000000000..b929cd3ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_s16 (void)
+{
+  int64x2_t out_int64x2_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int64x2_t = vreinterpretq_s64_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c
new file mode 100644
index 000000000..f095c80df
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_s32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int64x2_t = vreinterpretq_s64_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c
new file mode 100644
index 000000000..48cda7b3a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_s8 (void)
+{
+  int64x2_t out_int64x2_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int64x2_t = vreinterpretq_s64_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c
new file mode 100644
index 000000000..175f18c4e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u16 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int64x2_t = vreinterpretq_s64_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c
new file mode 100644
index 000000000..4ad87457b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u32 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int64x2_t = vreinterpretq_s64_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c
new file mode 100644
index 000000000..5a5218805
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u64 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int64x2_t = vreinterpretq_s64_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c
new file mode 100644
index 000000000..82d075779
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u8 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int64x2_t = vreinterpretq_s64_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c
new file mode 100644
index 000000000..851500f98
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_f32 (void)
+{
+  int8x16_t out_int8x16_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int8x16_t = vreinterpretq_s8_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c
new file mode 100644
index 000000000..9f4b632b8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p16 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int8x16_t = vreinterpretq_s8_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c
new file mode 100644
index 000000000..79d860c14
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p8 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int8x16_t = vreinterpretq_s8_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c
new file mode 100644
index 000000000..84349328d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_s16 (void)
+{
+  int8x16_t out_int8x16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x16_t = vreinterpretq_s8_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c
new file mode 100644
index 000000000..c16a14290
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_s32 (void)
+{
+  int8x16_t out_int8x16_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int8x16_t = vreinterpretq_s8_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c
new file mode 100644
index 000000000..f38396315
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_s64 (void)
+{
+  int8x16_t out_int8x16_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int8x16_t = vreinterpretq_s8_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c
new file mode 100644
index 000000000..19278ff6c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u16 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int8x16_t = vreinterpretq_s8_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c
new file mode 100644
index 000000000..d5943f25c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u32 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int8x16_t = vreinterpretq_s8_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c
new file mode 100644
index 000000000..6e066376c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u64 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int8x16_t = vreinterpretq_s8_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c
new file mode 100644
index 000000000..1e95d1955
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQs8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u8 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int8x16_t = vreinterpretq_s8_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c
new file mode 100644
index 000000000..6068d0c5c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_f32 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint16x8_t = vreinterpretq_u16_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c
new file mode 100644
index 000000000..6ee38c3d5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c
new file mode 100644
index 000000000..feea098d4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c
new file mode 100644
index 000000000..59e49b312
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c
new file mode 100644
index 000000000..38c292406
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s32 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c
new file mode 100644
index 000000000..5fe8ddafd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s64 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c
new file mode 100644
index 000000000..1afbd474b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c
new file mode 100644
index 000000000..59c5b9765
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_u32 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x8_t = vreinterpretq_u16_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c
new file mode 100644
index 000000000..61d2b7bd0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_u64 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint16x8_t = vreinterpretq_u16_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c
new file mode 100644
index 000000000..243b99140
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_u8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint16x8_t = vreinterpretq_u16_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c
new file mode 100644
index 000000000..c6d318fd2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_f32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint32x4_t = vreinterpretq_u32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c
new file mode 100644
index 000000000..288654a92
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c
new file mode 100644
index 000000000..cc8eec4c4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p8 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c
new file mode 100644
index 000000000..9418c2f02
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c
new file mode 100644
index 000000000..69719d8fb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c
new file mode 100644
index 000000000..5b70d30c1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s64 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c
new file mode 100644
index 000000000..90a2c7d91
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s8 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c
new file mode 100644
index 000000000..a331c9f00
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_u16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint32x4_t = vreinterpretq_u32_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c
new file mode 100644
index 000000000..5c0e26c34
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_u64 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x4_t = vreinterpretq_u32_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c
new file mode 100644
index 000000000..4b3378393
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_u8 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint32x4_t = vreinterpretq_u32_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c
new file mode 100644
index 000000000..17f89d0e9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_f32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint64x2_t = vreinterpretq_u64_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c
new file mode 100644
index 000000000..50fbbdef0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p16 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c
new file mode 100644
index 000000000..cc1d1e1a1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p8 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c
new file mode 100644
index 000000000..c17c80057
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s16 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c
new file mode 100644
index 000000000..dc8208b75
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c
new file mode 100644
index 000000000..a4a08b211
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c
new file mode 100644
index 000000000..357ceabbf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s8 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c
new file mode 100644
index 000000000..62f933748
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_u16 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint64x2_t = vreinterpretq_u64_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c
new file mode 100644
index 000000000..5d3a874f6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_u32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint64x2_t = vreinterpretq_u64_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c
new file mode 100644
index 000000000..7618eb166
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_u8 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint64x2_t = vreinterpretq_u64_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c
new file mode 100644
index 000000000..4a21da5aa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_f32 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint8x16_t = vreinterpretq_u8_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c
new file mode 100644
index 000000000..297736953
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p16 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c
new file mode 100644
index 000000000..d8dd6de39
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c
new file mode 100644
index 000000000..362a7766a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s16 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c
new file mode 100644
index 000000000..f864b1b5c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s32 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c
new file mode 100644
index 000000000..7cb682c07
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s64 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c
new file mode 100644
index 000000000..8d803c5f0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c
new file mode 100644
index 000000000..14d94dea7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_u16 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x16_t = vreinterpretq_u8_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c
new file mode 100644
index 000000000..0d8b46987
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_u32 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint8x16_t = vreinterpretq_u8_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c
new file mode 100644
index 000000000..8afdabf39
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretQu8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_u64 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint8x16_t = vreinterpretq_u8_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c
new file mode 100644
index 000000000..e05ef3108
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_p16 (void)
+{
+  float32x2_t out_float32x2_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_float32x2_t = vreinterpret_f32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c
new file mode 100644
index 000000000..6a807751c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_p8 (void)
+{
+  float32x2_t out_float32x2_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_float32x2_t = vreinterpret_f32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c
new file mode 100644
index 000000000..d86ee6511
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s16 (void)
+{
+  float32x2_t out_float32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_float32x2_t = vreinterpret_f32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c
new file mode 100644
index 000000000..10d230bc3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s32 (void)
+{
+  float32x2_t out_float32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_float32x2_t = vreinterpret_f32_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c
new file mode 100644
index 000000000..c78cb7853
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s64 (void)
+{
+  float32x2_t out_float32x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_float32x2_t = vreinterpret_f32_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c
new file mode 100644
index 000000000..bf130bdb7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s8 (void)
+{
+  float32x2_t out_float32x2_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_float32x2_t = vreinterpret_f32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c
new file mode 100644
index 000000000..29f83cfdc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u16 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_float32x2_t = vreinterpret_f32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c
new file mode 100644
index 000000000..4da99af1c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_float32x2_t = vreinterpret_f32_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c
new file mode 100644
index 000000000..5bc91f647
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u64 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_float32x2_t = vreinterpret_f32_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c
new file mode 100644
index 000000000..655ed88a2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretf32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u8 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_float32x2_t = vreinterpret_f32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c
new file mode 100644
index 000000000..78a6dc8ff
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_f32 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_poly16x4_t = vreinterpret_p16_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c
new file mode 100644
index 000000000..cd8c7921e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_p8 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly16x4_t = vreinterpret_p16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c
new file mode 100644
index 000000000..3638a18d5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_poly16x4_t = vreinterpret_p16_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c
new file mode 100644
index 000000000..4d131a377
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s32 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_poly16x4_t = vreinterpret_p16_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c
new file mode 100644
index 000000000..3d7e5d6d1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s64 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_poly16x4_t = vreinterpret_p16_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c
new file mode 100644
index 000000000..f72f660db
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s8 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_poly16x4_t = vreinterpret_p16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c
new file mode 100644
index 000000000..f4b36ec84
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_poly16x4_t = vreinterpret_p16_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c
new file mode 100644
index 000000000..627eeef72
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u32 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_poly16x4_t = vreinterpret_p16_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c
new file mode 100644
index 000000000..e7dbf8305
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u64 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_poly16x4_t = vreinterpret_p16_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c
new file mode 100644
index 000000000..c00b7264f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u8 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_poly16x4_t = vreinterpret_p16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c
new file mode 100644
index 000000000..c486793ba
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_f32 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_poly8x8_t = vreinterpret_p8_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c
new file mode 100644
index 000000000..c8ff231d5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_p16 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly8x8_t = vreinterpret_p8_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c
new file mode 100644
index 000000000..d179eaec7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s16 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_poly8x8_t = vreinterpret_p8_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c
new file mode 100644
index 000000000..54deb03b8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s32 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_poly8x8_t = vreinterpret_p8_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c
new file mode 100644
index 000000000..0788af995
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s64 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_poly8x8_t = vreinterpret_p8_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c
new file mode 100644
index 000000000..e201471c6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_poly8x8_t = vreinterpret_p8_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c
new file mode 100644
index 000000000..34bc38d0f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u16 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_poly8x8_t = vreinterpret_p8_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c
new file mode 100644
index 000000000..103963d37
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u32 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_poly8x8_t = vreinterpret_p8_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c
new file mode 100644
index 000000000..4521146b6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u64 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_poly8x8_t = vreinterpret_p8_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c
new file mode 100644
index 000000000..52321f279
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretp8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_poly8x8_t = vreinterpret_p8_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c
new file mode 100644
index 000000000..7cbe159c9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_f32 (void)
+{
+  int16x4_t out_int16x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int16x4_t = vreinterpret_s16_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c
new file mode 100644
index 000000000..42533bf94
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_p16 (void)
+{
+  int16x4_t out_int16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int16x4_t = vreinterpret_s16_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c
new file mode 100644
index 000000000..6d2e15e5f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_p8 (void)
+{
+  int16x4_t out_int16x4_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int16x4_t = vreinterpret_s16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c
new file mode 100644
index 000000000..019eb9b57
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_s32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int16x4_t = vreinterpret_s16_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c
new file mode 100644
index 000000000..56cdaede7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_s64 (void)
+{
+  int16x4_t out_int16x4_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int16x4_t = vreinterpret_s16_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c
new file mode 100644
index 000000000..f94745e9a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_s8 (void)
+{
+  int16x4_t out_int16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x4_t = vreinterpret_s16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c
new file mode 100644
index 000000000..4dc4f80eb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u16 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int16x4_t = vreinterpret_s16_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c
new file mode 100644
index 000000000..bf5442eb4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u32 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int16x4_t = vreinterpret_s16_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c
new file mode 100644
index 000000000..42cc2c5d8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u64 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int16x4_t = vreinterpret_s16_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c
new file mode 100644
index 000000000..5f4baaf02
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u8 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int16x4_t = vreinterpret_s16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c
new file mode 100644
index 000000000..5d646cf8a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_f32 (void)
+{
+  int32x2_t out_int32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int32x2_t = vreinterpret_s32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c
new file mode 100644
index 000000000..7be758c46
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_p16 (void)
+{
+  int32x2_t out_int32x2_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int32x2_t = vreinterpret_s32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c
new file mode 100644
index 000000000..3b3e34ac6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_p8 (void)
+{
+  int32x2_t out_int32x2_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int32x2_t = vreinterpret_s32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c
new file mode 100644
index 000000000..deb72ba85
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_s16 (void)
+{
+  int32x2_t out_int32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x2_t = vreinterpret_s32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c
new file mode 100644
index 000000000..9a1799d7f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_s64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int32x2_t = vreinterpret_s32_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c
new file mode 100644
index 000000000..f8a6db98d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_s8 (void)
+{
+  int32x2_t out_int32x2_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int32x2_t = vreinterpret_s32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c
new file mode 100644
index 000000000..3a1457d59
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u16 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int32x2_t = vreinterpret_s32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c
new file mode 100644
index 000000000..5c0cf56cc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u32 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int32x2_t = vreinterpret_s32_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c
new file mode 100644
index 000000000..7ce200dcf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u64 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int32x2_t = vreinterpret_s32_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c
new file mode 100644
index 000000000..9c1ebc18e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u8 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int32x2_t = vreinterpret_s32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c
new file mode 100644
index 000000000..b852607a5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_f32 (void)
+{
+  int64x1_t out_int64x1_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int64x1_t = vreinterpret_s64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c
new file mode 100644
index 000000000..aa49ee775
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_p16 (void)
+{
+  int64x1_t out_int64x1_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int64x1_t = vreinterpret_s64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c
new file mode 100644
index 000000000..0a9ff26cc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_p8 (void)
+{
+  int64x1_t out_int64x1_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int64x1_t = vreinterpret_s64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c
new file mode 100644
index 000000000..beedbf451
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_s16 (void)
+{
+  int64x1_t out_int64x1_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int64x1_t = vreinterpret_s64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c
new file mode 100644
index 000000000..7d9060dc1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_s32 (void)
+{
+  int64x1_t out_int64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x1_t = vreinterpret_s64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c
new file mode 100644
index 000000000..98401192a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_s8 (void)
+{
+  int64x1_t out_int64x1_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int64x1_t = vreinterpret_s64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c
new file mode 100644
index 000000000..66313a494
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u16 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int64x1_t = vreinterpret_s64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c
new file mode 100644
index 000000000..a993b5813
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u32 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int64x1_t = vreinterpret_s64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c
new file mode 100644
index 000000000..67497a24e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u64 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int64x1_t = vreinterpret_s64_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c
new file mode 100644
index 000000000..16ba5dae1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u8 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int64x1_t = vreinterpret_s64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c
new file mode 100644
index 000000000..b2f535bc5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_f32 (void)
+{
+  int8x8_t out_int8x8_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int8x8_t = vreinterpret_s8_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c
new file mode 100644
index 000000000..0ddbbbfa9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_p16 (void)
+{
+  int8x8_t out_int8x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int8x8_t = vreinterpret_s8_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c
new file mode 100644
index 000000000..282fc9394
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_p8 (void)
+{
+  int8x8_t out_int8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int8x8_t = vreinterpret_s8_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c
new file mode 100644
index 000000000..a23cdd5e3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_s16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int8x8_t = vreinterpret_s8_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c
new file mode 100644
index 000000000..e9299291a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_s32 (void)
+{
+  int8x8_t out_int8x8_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int8x8_t = vreinterpret_s8_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c
new file mode 100644
index 000000000..3288e02f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_s64 (void)
+{
+  int8x8_t out_int8x8_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int8x8_t = vreinterpret_s8_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c
new file mode 100644
index 000000000..d24bd11bf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u16 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int8x8_t = vreinterpret_s8_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c
new file mode 100644
index 000000000..7665a3081
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u32 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int8x8_t = vreinterpret_s8_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c
new file mode 100644
index 000000000..e0fcde95d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u64 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int8x8_t = vreinterpret_s8_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c
new file mode 100644
index 000000000..a4da614d3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterprets8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u8 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int8x8_t = vreinterpret_s8_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c
new file mode 100644
index 000000000..462d41b34
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_f32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint16x4_t = vreinterpret_u16_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c
new file mode 100644
index 000000000..2d901d611
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_p16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint16x4_t = vreinterpret_u16_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c
new file mode 100644
index 000000000..b49141b75
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_p8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint16x4_t = vreinterpret_u16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c
new file mode 100644
index 000000000..553deb1e8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint16x4_t = vreinterpret_u16_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c
new file mode 100644
index 000000000..97ddbe39f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint16x4_t = vreinterpret_u16_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c
new file mode 100644
index 000000000..901288b98
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s64 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint16x4_t = vreinterpret_u16_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c
new file mode 100644
index 000000000..10fec133e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint16x4_t = vreinterpret_u16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c
new file mode 100644
index 000000000..3cc777d92
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_u32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint16x4_t = vreinterpret_u16_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c
new file mode 100644
index 000000000..67ea82edb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_u64 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint16x4_t = vreinterpret_u16_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c
new file mode 100644
index 000000000..b548558ad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_u8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x4_t = vreinterpret_u16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c
new file mode 100644
index 000000000..5a0bd3615
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_f32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint32x2_t = vreinterpret_u32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c
new file mode 100644
index 000000000..23e885c40
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_p16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint32x2_t = vreinterpret_u32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c
new file mode 100644
index 000000000..24df01f90
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_p8 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint32x2_t = vreinterpret_u32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c
new file mode 100644
index 000000000..8e4baeb5f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint32x2_t = vreinterpret_u32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c
new file mode 100644
index 000000000..5251786ae
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint32x2_t = vreinterpret_u32_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c
new file mode 100644
index 000000000..0f0b4894c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint32x2_t = vreinterpret_u32_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c
new file mode 100644
index 000000000..f2ca01dc7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s8 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint32x2_t = vreinterpret_u32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c
new file mode 100644
index 000000000..9ff8649d6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_u16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x2_t = vreinterpret_u32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c
new file mode 100644
index 000000000..a7ab80893
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_u64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint32x2_t = vreinterpret_u32_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c
new file mode 100644
index 000000000..6dc3a30f0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_u8 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint32x2_t = vreinterpret_u32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c
new file mode 100644
index 000000000..9d079aa57
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_f32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint64x1_t = vreinterpret_u64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c
new file mode 100644
index 000000000..50a89b7a3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_p16 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint64x1_t = vreinterpret_u64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c
new file mode 100644
index 000000000..4d47d2505
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_p8 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint64x1_t = vreinterpret_u64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c
new file mode 100644
index 000000000..f55f9ea39
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s16 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint64x1_t = vreinterpret_u64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c
new file mode 100644
index 000000000..6ff562a54
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint64x1_t = vreinterpret_u64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c
new file mode 100644
index 000000000..1e705d00a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint64x1_t = vreinterpret_u64_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c
new file mode 100644
index 000000000..d80646728
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s8 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint64x1_t = vreinterpret_u64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c
new file mode 100644
index 000000000..97826c238
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_u16 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint64x1_t = vreinterpret_u64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c
new file mode 100644
index 000000000..10a6b550f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_u32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x1_t = vreinterpret_u64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c
new file mode 100644
index 000000000..d577d5657
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_u8 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint64x1_t = vreinterpret_u64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c
new file mode 100644
index 000000000..e0e6a594a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_f32 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint8x8_t = vreinterpret_u8_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c
new file mode 100644
index 000000000..d4e9852c4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_p16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint8x8_t = vreinterpret_u8_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c
new file mode 100644
index 000000000..ac17dd9a3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_p8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint8x8_t = vreinterpret_u8_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c
new file mode 100644
index 000000000..9182d4efc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint8x8_t = vreinterpret_u8_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c
new file mode 100644
index 000000000..3eee2f886
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s32 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint8x8_t = vreinterpret_u8_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c
new file mode 100644
index 000000000..46c65b2b7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s64 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint8x8_t = vreinterpret_u8_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c
new file mode 100644
index 000000000..c309adfe5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint8x8_t = vreinterpret_u8_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c
new file mode 100644
index 000000000..e0c0bbe97
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_u16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint8x8_t = vreinterpret_u8_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c
new file mode 100644
index 000000000..4f61486de
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_u32 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint8x8_t = vreinterpret_u8_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c
new file mode 100644
index 000000000..a9df64a74
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c
@@ -0,0 +1,18 @@
+/* Test the `vreinterpretu8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_u64 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint8x8_t = vreinterpret_u8_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c
new file mode 100644
index 000000000..36af44e1a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vrev16q_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c
new file mode 100644
index 000000000..3a6b903e4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrev16q_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c
new file mode 100644
index 000000000..859b1f11d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrev16q_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c
new file mode 100644
index 000000000..842519275
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vrev16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c
new file mode 100644
index 000000000..c236a4875
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrev16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c
new file mode 100644
index 000000000..9d640b60e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev16u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev16u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrev16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c
new file mode 100644
index 000000000..108571340
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x8_t = vrev32q_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c
new file mode 100644
index 000000000..4d28282ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vrev32q_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c
new file mode 100644
index 000000000..d8af7a485
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vrev32q_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c
new file mode 100644
index 000000000..85fe2b29b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrev32q_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c
new file mode 100644
index 000000000..8e26466dc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vrev32q_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c
new file mode 100644
index 000000000..4cd1024bf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrev32q_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c
new file mode 100644
index 000000000..41f4cf7de
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32p16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x4_t = vrev32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c
new file mode 100644
index 000000000..e1d714333
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vrev32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c
new file mode 100644
index 000000000..f01317218
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32s16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vrev32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c
new file mode 100644
index 000000000..8d14e6ae6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrev32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c
new file mode 100644
index 000000000..abc5cdeb8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32u16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vrev32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c
new file mode 100644
index 000000000..716a546f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev32u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev32u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrev32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c
new file mode 100644
index 000000000..a75d7dad5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrev64q_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c
new file mode 100644
index 000000000..bbee8de17
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x8_t = vrev64q_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c
new file mode 100644
index 000000000..f0f162801
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vrev64q_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c
new file mode 100644
index 000000000..0e24cc0ec
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vrev64q_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c
new file mode 100644
index 000000000..1c7c89274
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vrev64q_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c
new file mode 100644
index 000000000..e492a4e3b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrev64q_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c
new file mode 100644
index 000000000..1ed83305a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vrev64q_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c
new file mode 100644
index 000000000..723a1340d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrev64q_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c
new file mode 100644
index 000000000..4a6df7770
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrev64q_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c
new file mode 100644
index 000000000..3a7c21e9c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64f32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrev64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c
new file mode 100644
index 000000000..03c7e9029
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64p16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x4_t = vrev64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c
new file mode 100644
index 000000000..91f1ea4f9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vrev64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c
new file mode 100644
index 000000000..c5e49d770
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64s16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vrev64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c
new file mode 100644
index 000000000..952365c1f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64s32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vrev64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c
new file mode 100644
index 000000000..8b4dc987f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrev64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c
new file mode 100644
index 000000000..6d9291638
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64u16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vrev64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c
new file mode 100644
index 000000000..3759bb985
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64u32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrev64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c
new file mode 100644
index 000000000..3328ec0e3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c
@@ -0,0 +1,19 @@
+/* Test the `vrev64u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrev64u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrev64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c
new file mode 100644
index 000000000..a8ba1fb2e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c
@@ -0,0 +1,19 @@
+/* Test the `vrsqrteQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrteQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrsqrteq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c
new file mode 100644
index 000000000..609d78976
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c
@@ -0,0 +1,19 @@
+/* Test the `vrsqrteQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrteQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrsqrteq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c
new file mode 100644
index 000000000..1a2b771f6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c
@@ -0,0 +1,19 @@
+/* Test the `vrsqrtef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrtef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrsqrte_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c
new file mode 100644
index 000000000..6f4138d8b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c
@@ -0,0 +1,19 @@
+/* Test the `vrsqrteu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrteu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrsqrte_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c
new file mode 100644
index 000000000..28d300e90
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrsqrtsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrtsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vrsqrtsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c
new file mode 100644
index 000000000..f02c99ee7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrsqrtsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vrsqrtsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vrsqrts_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
new file mode 100644
index 000000000..c52ebb160
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32_t arg0_float32_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vsetq_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
new file mode 100644
index 000000000..0ce862292
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16_t arg0_poly16_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vsetq_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
new file mode 100644
index 000000000..f8ef936a8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8_t arg0_poly8_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vsetq_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
new file mode 100644
index 000000000..823bbfc90
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16_t arg0_int16_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsetq_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
new file mode 100644
index 000000000..003e16922
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32_t arg0_int32_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsetq_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c
new file mode 100644
index 000000000..16b1bc4e1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64_t arg0_int64_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsetq_lane_s64 (arg0_int64_t, arg1_int64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
new file mode 100644
index 000000000..9c784cbe8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8_t arg0_int8_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsetq_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
new file mode 100644
index 000000000..8ff74a26e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16_t arg0_uint16_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsetq_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
new file mode 100644
index 000000000..9a2272276
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32_t arg0_uint32_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsetq_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c
new file mode 100644
index 000000000..447f078ec
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64_t arg0_uint64_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsetq_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
new file mode 100644
index 000000000..c22690b04
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsetQ_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8_t arg0_uint8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsetq_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
new file mode 100644
index 000000000..c044b54a5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32_t arg0_float32_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vset_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
new file mode 100644
index 000000000..49d09040d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16_t arg0_poly16_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vset_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
new file mode 100644
index 000000000..c41b330e7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8_t arg0_poly8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vset_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
new file mode 100644
index 000000000..76d164266
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16_t arg0_int16_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vset_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
new file mode 100644
index 000000000..8f8c9e87e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32_t arg0_int32_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vset_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c
new file mode 100644
index 000000000..57cb6f6dc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64_t arg0_int64_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
new file mode 100644
index 000000000..45725c2ce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8_t arg0_int8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vset_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
new file mode 100644
index 000000000..6f699c693
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vset_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16_t arg0_uint16_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vset_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
new file mode 100644
index 000000000..663960298
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vset_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32_t arg0_uint32_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vset_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c
new file mode 100644
index 000000000..e22621ae9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c
@@ -0,0 +1,20 @@
+/* Test the `vset_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
new file mode 100644
index 000000000..7bcfb67ce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vset_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8_t arg0_uint8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vset_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c
new file mode 100644
index 000000000..7c50d641f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vshlq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c
new file mode 100644
index 000000000..e98bc6e88
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vshlq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c
new file mode 100644
index 000000000..b4eeae627
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vshlq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c
new file mode 100644
index 000000000..aacac035f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vshlq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c
new file mode 100644
index 000000000..01e3cfbe9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vshlq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c
new file mode 100644
index 000000000..828bcdf33
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vshlq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c
new file mode 100644
index 000000000..9e51c60d9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vshlq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c
new file mode 100644
index 000000000..37fc479f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vshlQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vshlq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c
new file mode 100644
index 000000000..eca26b5bc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c
new file mode 100644
index 000000000..8d20024ef
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c
new file mode 100644
index 000000000..2d6a12416
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c
new file mode 100644
index 000000000..c74b1ad8b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c
new file mode 100644
index 000000000..1cd61e27c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c
new file mode 100644
index 000000000..6601481ba
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c
new file mode 100644
index 000000000..845cb5d84
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c
new file mode 100644
index 000000000..1994c0787
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c
new file mode 100644
index 000000000..caacaa32d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vshl_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c
new file mode 100644
index 000000000..553cd0423
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vshl_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c
new file mode 100644
index 000000000..b9081d15e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vshl_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c
new file mode 100644
index 000000000..ae26970e0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vshl_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c
new file mode 100644
index 000000000..dbe74e173
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vshl_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c
new file mode 100644
index 000000000..271cc2a88
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vshl_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c
new file mode 100644
index 000000000..fdec91913
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vshl_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c
new file mode 100644
index 000000000..3c196122c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vshl_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vshl_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c
new file mode 100644
index 000000000..fb68e3288
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x4_t = vshll_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c
new file mode 100644
index 000000000..ebd7ceff0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x2_t = vshll_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c
new file mode 100644
index 000000000..1b1fba40a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_ns8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x8_t = vshll_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c
new file mode 100644
index 000000000..7bc3b1077
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x4_t = vshll_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c
new file mode 100644
index 000000000..20bf36382
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x2_t = vshll_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c
new file mode 100644
index 000000000..a4a141cb2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vshll_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshll_nu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x8_t = vshll_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshls16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshls16.c
new file mode 100644
index 000000000..80ab6f45b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshls16.c
@@ -0,0 +1,20 @@
+/* Test the `vshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshls32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshls32.c
new file mode 100644
index 000000000..f2cd655b1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshls32.c
@@ -0,0 +1,20 @@
+/* Test the `vshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshls64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshls64.c
new file mode 100644
index 000000000..23c910f7f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshls64.c
@@ -0,0 +1,20 @@
+/* Test the `vshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshls8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshls8.c
new file mode 100644
index 000000000..798a23f5d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshls8.c
@@ -0,0 +1,20 @@
+/* Test the `vshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlu16.c
new file mode 100644
index 000000000..6d7fbea47
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlu32.c
new file mode 100644
index 000000000..be05c003a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlu64.c
new file mode 100644
index 000000000..687cae2ef
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlu64.c
@@ -0,0 +1,20 @@
+/* Test the `vshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlu8.c
new file mode 100644
index 000000000..cb0070544
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c
new file mode 100644
index 000000000..9bd0a8040
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vshrq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c
new file mode 100644
index 000000000..65c41a625
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vshrq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c
new file mode 100644
index 000000000..9ee9e483d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vshrq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c
new file mode 100644
index 000000000..f8de705db
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vshrq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c
new file mode 100644
index 000000000..588ffb2f3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vshrq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c
new file mode 100644
index 000000000..5044cbf5e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vshrq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c
new file mode 100644
index 000000000..89d2c4dc0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vshrq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c
new file mode 100644
index 000000000..80ee3f559
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vshrQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vshrq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c
new file mode 100644
index 000000000..7576615b8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vshr_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c
new file mode 100644
index 000000000..7b3c4fa31
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vshr_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c
new file mode 100644
index 000000000..96ace08a7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vshr_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c
new file mode 100644
index 000000000..f8649d7c7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vshr_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c
new file mode 100644
index 000000000..4ea2a5317
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vshr_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c
new file mode 100644
index 000000000..86ab08c84
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vshr_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c
new file mode 100644
index 000000000..331a99707
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vshr_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c
new file mode 100644
index 000000000..6c94eaff4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c
@@ -0,0 +1,19 @@
+/* Test the `vshr_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vshr_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c
new file mode 100644
index 000000000..6ba1e4f21
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c
new file mode 100644
index 000000000..b84ddc78d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c
new file mode 100644
index 000000000..6cb52f521
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c
new file mode 100644
index 000000000..458698cec
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c
new file mode 100644
index 000000000..b797205b3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c
new file mode 100644
index 000000000..f8368410a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c
new file mode 100644
index 000000000..d15239f1b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vsliq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c
new file mode 100644
index 000000000..9151aba8f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vsliq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c
new file mode 100644
index 000000000..82c1f6a48
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsliq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c
new file mode 100644
index 000000000..2496254b0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsliq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c
new file mode 100644
index 000000000..30139f29e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsliq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c
new file mode 100644
index 000000000..abbe0c39d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsliq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c
new file mode 100644
index 000000000..00e7cfab2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsliq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c
new file mode 100644
index 000000000..155c70515
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsliq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c
new file mode 100644
index 000000000..19570e22a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsliq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c
new file mode 100644
index 000000000..85a77b862
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsliQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsliq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c
new file mode 100644
index 000000000..d0395f9a3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vsli_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c
new file mode 100644
index 000000000..22eef0f3f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vsli_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c
new file mode 100644
index 000000000..12ba95508
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsli_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c
new file mode 100644
index 000000000..7cb9804ee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsli_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c
new file mode 100644
index 000000000..822b05da3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsli_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c
new file mode 100644
index 000000000..dc01f5051
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsli_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c
new file mode 100644
index 000000000..5bd43815b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsli_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c
new file mode 100644
index 000000000..ba4236343
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsli_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c
new file mode 100644
index 000000000..84ef9f338
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsli_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c
new file mode 100644
index 000000000..c62744d9e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsli_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsli_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c
new file mode 100644
index 000000000..7e6796961
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c
new file mode 100644
index 000000000..db0869a10
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c
new file mode 100644
index 000000000..f5ff91d21
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c
new file mode 100644
index 000000000..909c73bad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c
new file mode 100644
index 000000000..f437b338c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c
new file mode 100644
index 000000000..41e1b54d2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c
new file mode 100644
index 000000000..b70347f4d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c
new file mode 100644
index 000000000..62afb6158
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsraQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c
new file mode 100644
index 000000000..6a19cd7e8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c
new file mode 100644
index 000000000..3ed528cb0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c
new file mode 100644
index 000000000..9a5ce9676
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c
new file mode 100644
index 000000000..f1de791ab
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c
new file mode 100644
index 000000000..0143526c3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c
new file mode 100644
index 000000000..d7e3bc52c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c
new file mode 100644
index 000000000..bf9e1df59
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c
new file mode 100644
index 000000000..bc05cc552
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsra_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c
new file mode 100644
index 000000000..efa39e31a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vsriq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c
new file mode 100644
index 000000000..376e8d7c1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vsriq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c
new file mode 100644
index 000000000..f69c52b6a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsriq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c
new file mode 100644
index 000000000..6108d3641
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsriq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c
new file mode 100644
index 000000000..d78710f8a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsriq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c
new file mode 100644
index 000000000..ba4bd196d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsriq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c
new file mode 100644
index 000000000..c15a1f6e8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsriq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c
new file mode 100644
index 000000000..634be975f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsriq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c
new file mode 100644
index 000000000..85812e59d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsriq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c
new file mode 100644
index 000000000..d83121f23
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsriQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsriq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c
new file mode 100644
index 000000000..7080997ec
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vsri_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c
new file mode 100644
index 000000000..abb742f9d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vsri_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c
new file mode 100644
index 000000000..5eaee7861
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsri_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c
new file mode 100644
index 000000000..c813765e5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsri_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c
new file mode 100644
index 000000000..552c5db77
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsri_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c
new file mode 100644
index 000000000..9bec2eabd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsri_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c
new file mode 100644
index 000000000..001bc33cf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsri_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c
new file mode 100644
index 000000000..8bb73bf35
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsri_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c
new file mode 100644
index 000000000..bad5816d0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsri_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c
new file mode 100644
index 000000000..c2cc93dcb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsri_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsri_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
new file mode 100644
index 000000000..e1de667c4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4_t arg1_float32x4_t;
+
+  vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
new file mode 100644
index 000000000..f2a4f5969
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
new file mode 100644
index 000000000..f4a56b14e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
new file mode 100644
index 000000000..0a7de3e10
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8_t arg1_int16x8_t;
+
+  vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
new file mode 100644
index 000000000..5211c9ab6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4_t arg1_int32x4_t;
+
+  vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
new file mode 100644
index 000000000..ab1bda9d4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x2_t arg1_int64x2_t;
+
+  vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
new file mode 100644
index 000000000..215c5af52
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16_t arg1_int8x16_t;
+
+  vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
new file mode 100644
index 000000000..4e88d26e7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
new file mode 100644
index 000000000..2d416c0ef
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
new file mode 100644
index 000000000..46fe4c345
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
new file mode 100644
index 000000000..9536e3742
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Q_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
new file mode 100644
index 000000000..e8bab5ae2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4_t arg1_float32x4_t;
+
+  vst1q_f32 (arg0_float32_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
new file mode 100644
index 000000000..b83669507
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
new file mode 100644
index 000000000..bdbf4b078
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
new file mode 100644
index 000000000..c3c04aaea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8_t arg1_int16x8_t;
+
+  vst1q_s16 (arg0_int16_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
new file mode 100644
index 000000000..54fc0bb4b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4_t arg1_int32x4_t;
+
+  vst1q_s32 (arg0_int32_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
new file mode 100644
index 000000000..696b4ce5d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x2_t arg1_int64x2_t;
+
+  vst1q_s64 (arg0_int64_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
new file mode 100644
index 000000000..6de3700a3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16_t arg1_int8x16_t;
+
+  vst1q_s8 (arg0_int8_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
new file mode 100644
index 000000000..b0667fb9a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
new file mode 100644
index 000000000..88456cf99
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
new file mode 100644
index 000000000..8a390f79f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
new file mode 100644
index 000000000..0e815e36e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
new file mode 100644
index 000000000..03fe37db9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2_t arg1_float32x2_t;
+
+  vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
new file mode 100644
index 000000000..793b8a159
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
new file mode 100644
index 000000000..50de02d2e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
new file mode 100644
index 000000000..e8d31d3f2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4_t arg1_int16x4_t;
+
+  vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
new file mode 100644
index 000000000..73bbe63c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2_t arg1_int32x2_t;
+
+  vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
new file mode 100644
index 000000000..61b08a901
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1_t arg1_int64x1_t;
+
+  vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
new file mode 100644
index 000000000..263113b8a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8_t arg1_int8x8_t;
+
+  vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
new file mode 100644
index 000000000..8fe92a508
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
new file mode 100644
index 000000000..65785ee99
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
new file mode 100644
index 000000000..6f54cc106
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
new file mode 100644
index 000000000..2e96ddfb9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
new file mode 100644
index 000000000..fc6829b88
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2_t arg1_float32x2_t;
+
+  vst1_f32 (arg0_float32_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
new file mode 100644
index 000000000..138b7f806
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  vst1_p16 (arg0_poly16_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
new file mode 100644
index 000000000..ae57e3b06
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  vst1_p8 (arg0_poly8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
new file mode 100644
index 000000000..7c2931200
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4_t arg1_int16x4_t;
+
+  vst1_s16 (arg0_int16_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
new file mode 100644
index 000000000..968447a32
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2_t arg1_int32x2_t;
+
+  vst1_s32 (arg0_int32_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
new file mode 100644
index 000000000..2e694366b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1_t arg1_int64x1_t;
+
+  vst1_s64 (arg0_int64_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
new file mode 100644
index 000000000..ab8daca15
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8_t arg1_int8x8_t;
+
+  vst1_s8 (arg0_int8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
new file mode 100644
index 000000000..77265c490
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
@@ -0,0 +1,19 @@
+/* Test the `vst1u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  vst1_u16 (arg0_uint16_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
new file mode 100644
index 000000000..ef9268460
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
@@ -0,0 +1,19 @@
+/* Test the `vst1u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  vst1_u32 (arg0_uint32_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
new file mode 100644
index 000000000..6cc6d2ee4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
@@ -0,0 +1,19 @@
+/* Test the `vst1u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  vst1_u64 (arg0_uint64_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
new file mode 100644
index 000000000..92a37cdab
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
@@ -0,0 +1,19 @@
+/* Test the `vst1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst1u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  vst1_u8 (arg0_uint8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
new file mode 100644
index 000000000..4d36a80b5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x2_t arg1_float32x4x2_t;
+
+  vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
new file mode 100644
index 000000000..c3247d075
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x2_t arg1_poly16x8x2_t;
+
+  vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
new file mode 100644
index 000000000..60c0c14d9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x2_t arg1_int16x8x2_t;
+
+  vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
new file mode 100644
index 000000000..82c309489
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x2_t arg1_int32x4x2_t;
+
+  vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
new file mode 100644
index 000000000..f966f8fcf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x2_t arg1_uint16x8x2_t;
+
+  vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
new file mode 100644
index 000000000..936009256
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x2_t arg1_uint32x4x2_t;
+
+  vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
new file mode 100644
index 000000000..5109dc217
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x2_t arg1_float32x4x2_t;
+
+  vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
new file mode 100644
index 000000000..dba266d77
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x2_t arg1_poly16x8x2_t;
+
+  vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
new file mode 100644
index 000000000..1de005241
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16x2_t arg1_poly8x16x2_t;
+
+  vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
new file mode 100644
index 000000000..83fe85290
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x2_t arg1_int16x8x2_t;
+
+  vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
new file mode 100644
index 000000000..ea8411f0c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x2_t arg1_int32x4x2_t;
+
+  vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
new file mode 100644
index 000000000..1eb70b24a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16x2_t arg1_int8x16x2_t;
+
+  vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
new file mode 100644
index 000000000..61dfaeebd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x2_t arg1_uint16x8x2_t;
+
+  vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
new file mode 100644
index 000000000..ec8556039
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x2_t arg1_uint32x4x2_t;
+
+  vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
new file mode 100644
index 000000000..c3e5c5db3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16x2_t arg1_uint8x16x2_t;
+
+  vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
new file mode 100644
index 000000000..4dc5258f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x2_t arg1_float32x2x2_t;
+
+  vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
new file mode 100644
index 000000000..dedaec7fe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x2_t arg1_poly16x4x2_t;
+
+  vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
new file mode 100644
index 000000000..ff88aebef
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+
+  vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
new file mode 100644
index 000000000..80aedbaf1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x2_t arg1_int16x4x2_t;
+
+  vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
new file mode 100644
index 000000000..150686d80
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x2_t arg1_int32x2x2_t;
+
+  vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
new file mode 100644
index 000000000..a71f186b3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x2_t arg1_int8x8x2_t;
+
+  vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
new file mode 100644
index 000000000..303b8ecf5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x2_t arg1_uint16x4x2_t;
+
+  vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
new file mode 100644
index 000000000..e1402fcc8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x2_t arg1_uint32x2x2_t;
+
+  vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
new file mode 100644
index 000000000..37f320b02
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+
+  vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
new file mode 100644
index 000000000..4b1d03d63
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x2_t arg1_float32x2x2_t;
+
+  vst2_f32 (arg0_float32_t, arg1_float32x2x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
new file mode 100644
index 000000000..9e788b259
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x2_t arg1_poly16x4x2_t;
+
+  vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
new file mode 100644
index 000000000..d40ca694e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+
+  vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
new file mode 100644
index 000000000..56cdbf811
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x2_t arg1_int16x4x2_t;
+
+  vst2_s16 (arg0_int16_t, arg1_int16x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
new file mode 100644
index 000000000..9519eec9b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x2_t arg1_int32x2x2_t;
+
+  vst2_s32 (arg0_int32_t, arg1_int32x2x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
new file mode 100644
index 000000000..e4fda8dc5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
@@ -0,0 +1,19 @@
+/* Test the `vst2s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1x2_t arg1_int64x1x2_t;
+
+  vst2_s64 (arg0_int64_t, arg1_int64x1x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
new file mode 100644
index 000000000..9553e4f5a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x2_t arg1_int8x8x2_t;
+
+  vst2_s8 (arg0_int8_t, arg1_int8x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
new file mode 100644
index 000000000..c0af478d2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
@@ -0,0 +1,19 @@
+/* Test the `vst2u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x2_t arg1_uint16x4x2_t;
+
+  vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
new file mode 100644
index 000000000..dbde9a6b5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
@@ -0,0 +1,19 @@
+/* Test the `vst2u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x2_t arg1_uint32x2x2_t;
+
+  vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
new file mode 100644
index 000000000..2487ff238
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
@@ -0,0 +1,19 @@
+/* Test the `vst2u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1x2_t arg1_uint64x1x2_t;
+
+  vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
new file mode 100644
index 000000000..e35a3ccd1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
@@ -0,0 +1,19 @@
+/* Test the `vst2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst2u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+
+  vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
new file mode 100644
index 000000000..c8409af83
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x3_t arg1_float32x4x3_t;
+
+  vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
new file mode 100644
index 000000000..1c058b487
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x3_t arg1_poly16x8x3_t;
+
+  vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
new file mode 100644
index 000000000..a6c0c1ae3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x3_t arg1_int16x8x3_t;
+
+  vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
new file mode 100644
index 000000000..982d4de45
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x3_t arg1_int32x4x3_t;
+
+  vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
new file mode 100644
index 000000000..c44b1a6d5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x3_t arg1_uint16x8x3_t;
+
+  vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
new file mode 100644
index 000000000..7ddf8887e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x3_t arg1_uint32x4x3_t;
+
+  vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
new file mode 100644
index 000000000..c8d5d220f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x3_t arg1_float32x4x3_t;
+
+  vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
new file mode 100644
index 000000000..6b416bd94
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x3_t arg1_poly16x8x3_t;
+
+  vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
new file mode 100644
index 000000000..7b034fd4a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16x3_t arg1_poly8x16x3_t;
+
+  vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
new file mode 100644
index 000000000..c191ea011
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x3_t arg1_int16x8x3_t;
+
+  vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
new file mode 100644
index 000000000..5fad79bc2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x3_t arg1_int32x4x3_t;
+
+  vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
new file mode 100644
index 000000000..ba5807e94
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16x3_t arg1_int8x16x3_t;
+
+  vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
new file mode 100644
index 000000000..7d23e10b6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x3_t arg1_uint16x8x3_t;
+
+  vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
new file mode 100644
index 000000000..c6233c087
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x3_t arg1_uint32x4x3_t;
+
+  vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
new file mode 100644
index 000000000..a72a4a822
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16x3_t arg1_uint8x16x3_t;
+
+  vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
new file mode 100644
index 000000000..f4e4a4806
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x3_t arg1_float32x2x3_t;
+
+  vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
new file mode 100644
index 000000000..af61dcdbb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x3_t arg1_poly16x4x3_t;
+
+  vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
new file mode 100644
index 000000000..b5d21c1a3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+
+  vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
new file mode 100644
index 000000000..0f5d9d5a1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x3_t arg1_int16x4x3_t;
+
+  vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
new file mode 100644
index 000000000..9bd76f2e3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x3_t arg1_int32x2x3_t;
+
+  vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
new file mode 100644
index 000000000..b7f5996eb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x3_t arg1_int8x8x3_t;
+
+  vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
new file mode 100644
index 000000000..d00856247
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x3_t arg1_uint16x4x3_t;
+
+  vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
new file mode 100644
index 000000000..2e4bf4f68
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x3_t arg1_uint32x2x3_t;
+
+  vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
new file mode 100644
index 000000000..c001b0921
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+
+  vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
new file mode 100644
index 000000000..6cd851817
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x3_t arg1_float32x2x3_t;
+
+  vst3_f32 (arg0_float32_t, arg1_float32x2x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
new file mode 100644
index 000000000..d3deb3b26
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x3_t arg1_poly16x4x3_t;
+
+  vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
new file mode 100644
index 000000000..41f9608c7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+
+  vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
new file mode 100644
index 000000000..73cb6932b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x3_t arg1_int16x4x3_t;
+
+  vst3_s16 (arg0_int16_t, arg1_int16x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
new file mode 100644
index 000000000..46feb60a8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x3_t arg1_int32x2x3_t;
+
+  vst3_s32 (arg0_int32_t, arg1_int32x2x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
new file mode 100644
index 000000000..93834d6dd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
@@ -0,0 +1,19 @@
+/* Test the `vst3s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1x3_t arg1_int64x1x3_t;
+
+  vst3_s64 (arg0_int64_t, arg1_int64x1x3_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
new file mode 100644
index 000000000..f093584f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x3_t arg1_int8x8x3_t;
+
+  vst3_s8 (arg0_int8_t, arg1_int8x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
new file mode 100644
index 000000000..dc634f00a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
@@ -0,0 +1,19 @@
+/* Test the `vst3u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x3_t arg1_uint16x4x3_t;
+
+  vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
new file mode 100644
index 000000000..a7eeef402
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
@@ -0,0 +1,19 @@
+/* Test the `vst3u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x3_t arg1_uint32x2x3_t;
+
+  vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
new file mode 100644
index 000000000..4cd844068
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
@@ -0,0 +1,19 @@
+/* Test the `vst3u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1x3_t arg1_uint64x1x3_t;
+
+  vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
new file mode 100644
index 000000000..83c6155cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
@@ -0,0 +1,19 @@
+/* Test the `vst3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst3u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+
+  vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
new file mode 100644
index 000000000..937168e8b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x4_t arg1_float32x4x4_t;
+
+  vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
new file mode 100644
index 000000000..549360c88
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x4_t arg1_poly16x8x4_t;
+
+  vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
new file mode 100644
index 000000000..b9b25fbfd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x4_t arg1_int16x8x4_t;
+
+  vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
new file mode 100644
index 000000000..cab45ab99
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x4_t arg1_int32x4x4_t;
+
+  vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
new file mode 100644
index 000000000..61aba31c0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x4_t arg1_uint16x8x4_t;
+
+  vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
new file mode 100644
index 000000000..98144c11d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x4_t arg1_uint32x4x4_t;
+
+  vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
new file mode 100644
index 000000000..ad51afdcb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x4_t arg1_float32x4x4_t;
+
+  vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
new file mode 100644
index 000000000..1ab633799
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x4_t arg1_poly16x8x4_t;
+
+  vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
new file mode 100644
index 000000000..3e32382d9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16x4_t arg1_poly8x16x4_t;
+
+  vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
new file mode 100644
index 000000000..8581c41d9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x4_t arg1_int16x8x4_t;
+
+  vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
new file mode 100644
index 000000000..8a66e9647
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x4_t arg1_int32x4x4_t;
+
+  vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
new file mode 100644
index 000000000..14e8ab8ff
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16x4_t arg1_int8x16x4_t;
+
+  vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
new file mode 100644
index 000000000..5f14fa80d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x4_t arg1_uint16x8x4_t;
+
+  vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
new file mode 100644
index 000000000..e42744648
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x4_t arg1_uint32x4x4_t;
+
+  vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
new file mode 100644
index 000000000..b67bb19ff
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16x4_t arg1_uint8x16x4_t;
+
+  vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
new file mode 100644
index 000000000..8d0eab5bb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x4_t arg1_float32x2x4_t;
+
+  vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
new file mode 100644
index 000000000..7dbddf3c1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x4_t arg1_poly16x4x4_t;
+
+  vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
new file mode 100644
index 000000000..1791964da
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+
+  vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
new file mode 100644
index 000000000..46a4c92f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x4_t arg1_int16x4x4_t;
+
+  vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
new file mode 100644
index 000000000..1a9491c10
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x4_t arg1_int32x2x4_t;
+
+  vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
new file mode 100644
index 000000000..15cbab1f8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x4_t arg1_int8x8x4_t;
+
+  vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
new file mode 100644
index 000000000..96a0182ac
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x4_t arg1_uint16x4x4_t;
+
+  vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
new file mode 100644
index 000000000..c8b19220e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x4_t arg1_uint32x2x4_t;
+
+  vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
new file mode 100644
index 000000000..0dbcd5483
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+
+  vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4f32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
new file mode 100644
index 000000000..9e37af218
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x4_t arg1_float32x2x4_t;
+
+  vst4_f32 (arg0_float32_t, arg1_float32x2x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4p16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
new file mode 100644
index 000000000..f07d43524
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x4_t arg1_poly16x4x4_t;
+
+  vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
new file mode 100644
index 000000000..ddee22802
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+
+  vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4s16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
new file mode 100644
index 000000000..8ca806078
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x4_t arg1_int16x4x4_t;
+
+  vst4_s16 (arg0_int16_t, arg1_int16x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4s32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
new file mode 100644
index 000000000..9619e4b50
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x4_t arg1_int32x2x4_t;
+
+  vst4_s32 (arg0_int32_t, arg1_int32x2x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4s64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
new file mode 100644
index 000000000..0b470ad84
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
@@ -0,0 +1,19 @@
+/* Test the `vst4s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1x4_t arg1_int64x1x4_t;
+
+  vst4_s64 (arg0_int64_t, arg1_int64x1x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
new file mode 100644
index 000000000..796c44663
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x4_t arg1_int8x8x4_t;
+
+  vst4_s8 (arg0_int8_t, arg1_int8x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4u16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
new file mode 100644
index 000000000..3ce82b70c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
@@ -0,0 +1,19 @@
+/* Test the `vst4u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x4_t arg1_uint16x4x4_t;
+
+  vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4u32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
new file mode 100644
index 000000000..36df64969
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
@@ -0,0 +1,19 @@
+/* Test the `vst4u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x4_t arg1_uint32x2x4_t;
+
+  vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4u64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
new file mode 100644
index 000000000..3d11dd06d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
@@ -0,0 +1,19 @@
+/* Test the `vst4u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1x4_t arg1_uint64x1x4_t;
+
+  vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
new file mode 100644
index 000000000..4d4dde14e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
@@ -0,0 +1,19 @@
+/* Test the `vst4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vst4u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+
+  vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
new file mode 100644
index 000000000..bacf30471
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vsubq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c
new file mode 100644
index 000000000..01b4f6d97
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c
new file mode 100644
index 000000000..1de3a942a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c
new file mode 100644
index 000000000..1ac90a0e5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c
new file mode 100644
index 000000000..e3b819b8c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c
new file mode 100644
index 000000000..46ad52bf2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c
new file mode 100644
index 000000000..391f54c56
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c
new file mode 100644
index 000000000..f542d37e5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c
new file mode 100644
index 000000000..1f8ec0f5b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubf32.c
new file mode 100644
index 000000000..ee29262a8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubf32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vsub_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c
new file mode 100644
index 000000000..034e87a8b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c
new file mode 100644
index 000000000..5c5d0bdce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c
new file mode 100644
index 000000000..2e7e5ca7f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c
new file mode 100644
index 000000000..91f6aa0b4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c
new file mode 100644
index 000000000..36ce23e67
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c
new file mode 100644
index 000000000..bde5a7a34
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubls16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubls16.c
new file mode 100644
index 000000000..f346d0047
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubls16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vsubl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubls32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubls32.c
new file mode 100644
index 000000000..db6189018
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubls32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vsubl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubls8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubls8.c
new file mode 100644
index 000000000..e3cad6fb5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubls8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vsubl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsublu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsublu16.c
new file mode 100644
index 000000000..cb3012922
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsublu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsublu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsublu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vsubl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsublu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsublu32.c
new file mode 100644
index 000000000..e9541f92e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsublu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsublu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsublu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vsubl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsublu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsublu8.c
new file mode 100644
index 000000000..51f68dcfe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsublu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsublu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsublu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vsubl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubs16.c
new file mode 100644
index 000000000..1b97aef20
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubs16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubs32.c
new file mode 100644
index 000000000..11e1a373c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubs32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubs64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubs64.c
new file mode 100644
index 000000000..85074fb94
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubs64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubs8.c
new file mode 100644
index 000000000..4cfe5db3e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubs8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubu16.c
new file mode 100644
index 000000000..d1039ac17
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubu32.c
new file mode 100644
index 000000000..eca7e86af
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubu64.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubu64.c
new file mode 100644
index 000000000..e6307c231
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubu8.c
new file mode 100644
index 000000000..02b945c61
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubws16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubws16.c
new file mode 100644
index 000000000..a821ae65a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubws16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubws16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubws16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vsubw_s16 (arg0_int32x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubws32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubws32.c
new file mode 100644
index 000000000..4e1e7ddb7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubws32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubws32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubws32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vsubw_s32 (arg0_int64x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubws8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubws8.c
new file mode 100644
index 000000000..223050899
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubws8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubws8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubws8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vsubw_s8 (arg0_int16x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c
new file mode 100644
index 000000000..e35073ba2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c
@@ -0,0 +1,20 @@
+/* Test the `vsubwu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubwu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vsubw_u16 (arg0_uint32x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c
new file mode 100644
index 000000000..e4270aa2f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c
@@ -0,0 +1,20 @@
+/* Test the `vsubwu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubwu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vsubw_u32 (arg0_uint64x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c
new file mode 100644
index 000000000..5d8aa55cd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c
@@ -0,0 +1,20 @@
+/* Test the `vsubwu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vsubwu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vsubw_u8 (arg0_uint16x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c
new file mode 100644
index 000000000..177db25a9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl1p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl1_p8 (arg0_poly8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c
new file mode 100644
index 000000000..1e77e3078
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl1s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl1_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c
new file mode 100644
index 000000000..8719c2854
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl1u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl1_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c
new file mode 100644
index 000000000..07bdc05d3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl2p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8x2_t arg0_poly8x8x2_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl2_p8 (arg0_poly8x8x2_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c
new file mode 100644
index 000000000..04a824d84
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl2s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8x2_t arg0_int8x8x2_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl2_s8 (arg0_int8x8x2_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c
new file mode 100644
index 000000000..ce29a23a0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl2u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8x2_t arg0_uint8x8x2_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl2_u8 (arg0_uint8x8x2_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c
new file mode 100644
index 000000000..dce7bbb04
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl3p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8x3_t arg0_poly8x8x3_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl3_p8 (arg0_poly8x8x3_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c
new file mode 100644
index 000000000..1b62f6d29
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl3s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8x3_t arg0_int8x8x3_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl3_s8 (arg0_int8x8x3_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c
new file mode 100644
index 000000000..9837e5320
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl3u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8x3_t arg0_uint8x8x3_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl3_u8 (arg0_uint8x8x3_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c
new file mode 100644
index 000000000..c60e2dcc0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl4p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8x4_t arg0_poly8x8x4_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl4_p8 (arg0_poly8x8x4_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c
new file mode 100644
index 000000000..c89d2b101
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl4s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8x4_t arg0_int8x8x4_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl4_s8 (arg0_int8x8x4_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c
new file mode 100644
index 000000000..1e98a31eb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c
@@ -0,0 +1,20 @@
+/* Test the `vtbl4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbl4u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8x4_t arg0_uint8x8x4_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl4_u8 (arg0_uint8x8x4_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c
new file mode 100644
index 000000000..136d80e64
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx1p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx1_p8 (arg0_poly8x8_t, arg1_poly8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c
new file mode 100644
index 000000000..23e59836e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx1s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx1_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c
new file mode 100644
index 000000000..46320636a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx1u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx1_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c
new file mode 100644
index 000000000..2b46e7ea9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx2p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx2_p8 (arg0_poly8x8_t, arg1_poly8x8x2_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c
new file mode 100644
index 000000000..6efb84ffe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx2s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8x2_t arg1_int8x8x2_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx2_s8 (arg0_int8x8_t, arg1_int8x8x2_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c
new file mode 100644
index 000000000..a74568942
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx2u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx2_u8 (arg0_uint8x8_t, arg1_uint8x8x2_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c
new file mode 100644
index 000000000..a8f9a2910
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx3p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx3_p8 (arg0_poly8x8_t, arg1_poly8x8x3_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c
new file mode 100644
index 000000000..9de0184cd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx3s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8x3_t arg1_int8x8x3_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx3_s8 (arg0_int8x8_t, arg1_int8x8x3_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c
new file mode 100644
index 000000000..45e7e05d1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx3u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx3_u8 (arg0_uint8x8_t, arg1_uint8x8x3_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c
new file mode 100644
index 000000000..a283be7bc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx4p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx4_p8 (arg0_poly8x8_t, arg1_poly8x8x4_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c
new file mode 100644
index 000000000..f64198c9f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx4s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8x4_t arg1_int8x8x4_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx4_s8 (arg0_int8x8_t, arg1_int8x8x4_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c
new file mode 100644
index 000000000..de5ebd706
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbx4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtbx4u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx4_u8 (arg0_uint8x8_t, arg1_uint8x8x4_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c
new file mode 100644
index 000000000..c011dc9a6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4x2_t = vtrnq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c
new file mode 100644
index 000000000..3f86f8ad8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8x2_t = vtrnq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c
new file mode 100644
index 000000000..2406d8852
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16x2_t = vtrnq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c
new file mode 100644
index 000000000..971977af4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8x2_t = vtrnq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c
new file mode 100644
index 000000000..b89558668
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4x2_t = vtrnq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c
new file mode 100644
index 000000000..c7a62b6e1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16x2_t = vtrnq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c
new file mode 100644
index 000000000..e36b18d76
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8x2_t = vtrnq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c
new file mode 100644
index 000000000..dee79ce16
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4x2_t = vtrnq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c
new file mode 100644
index 000000000..7fbffd9e6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnQu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16x2_t = vtrnq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c
new file mode 100644
index 000000000..c31e250c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2x2_t = vtrn_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c
new file mode 100644
index 000000000..f2d0357ae
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4x2_t = vtrn_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c
new file mode 100644
index 000000000..97eb848e8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8x2_t = vtrn_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrns16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrns16.c
new file mode 100644
index 000000000..98ddc529c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrns16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrns16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4x2_t = vtrn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrns32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrns32.c
new file mode 100644
index 000000000..ae02e6a1e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrns32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrns32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2x2_t = vtrn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrns8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrns8.c
new file mode 100644
index 000000000..6d45572b6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrns8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrns8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8x2_t = vtrn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c
new file mode 100644
index 000000000..4f7a6dae2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4x2_t = vtrn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c
new file mode 100644
index 000000000..b9a9dbcdf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2x2_t = vtrn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c
new file mode 100644
index 000000000..4de249665
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c
@@ -0,0 +1,20 @@
+/* Test the `vtrnu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtrnu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8x2_t = vtrn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c
new file mode 100644
index 000000000..38f8a4b7a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQp8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_uint8x16_t = vtstq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c
new file mode 100644
index 000000000..607a01ef6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vtstq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c
new file mode 100644
index 000000000..b2b3def48
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vtstq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c
new file mode 100644
index 000000000..d5faf9a9e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vtstq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c
new file mode 100644
index 000000000..8dfa203e9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vtstq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c
new file mode 100644
index 000000000..024e57859
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vtstq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c
new file mode 100644
index 000000000..0d7f3b255
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vtstQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vtstq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstp8.c
new file mode 100644
index 000000000..93327b9d7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstp8.c
@@ -0,0 +1,20 @@
+/* Test the `vtstp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstp8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_uint8x8_t = vtst_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtsts16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtsts16.c
new file mode 100644
index 000000000..30b788470
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtsts16.c
@@ -0,0 +1,20 @@
+/* Test the `vtsts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtsts16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vtst_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtsts32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtsts32.c
new file mode 100644
index 000000000..f5dafb227
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtsts32.c
@@ -0,0 +1,20 @@
+/* Test the `vtsts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtsts32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vtst_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtsts8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtsts8.c
new file mode 100644
index 000000000..f4c416214
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtsts8.c
@@ -0,0 +1,20 @@
+/* Test the `vtsts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtsts8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vtst_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstu16.c
new file mode 100644
index 000000000..6f8005cea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstu16.c
@@ -0,0 +1,20 @@
+/* Test the `vtstu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vtst_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstu32.c
new file mode 100644
index 000000000..b98e12c32
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstu32.c
@@ -0,0 +1,20 @@
+/* Test the `vtstu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vtst_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstu8.c
new file mode 100644
index 000000000..0c7f38043
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vtstu8.c
@@ -0,0 +1,20 @@
+/* Test the `vtstu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vtstu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtst_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c
new file mode 100644
index 000000000..29339566c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4x2_t = vuzpq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c
new file mode 100644
index 000000000..51a90d337
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8x2_t = vuzpq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c
new file mode 100644
index 000000000..f9765651a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16x2_t = vuzpq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c
new file mode 100644
index 000000000..aeb29673d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8x2_t = vuzpq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c
new file mode 100644
index 000000000..3bf1ad938
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4x2_t = vuzpq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c
new file mode 100644
index 000000000..194b596b8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16x2_t = vuzpq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c
new file mode 100644
index 000000000..6312ca702
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8x2_t = vuzpq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c
new file mode 100644
index 000000000..f7d854c3d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4x2_t = vuzpq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c
new file mode 100644
index 000000000..eef40e53f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpQu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16x2_t = vuzpq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c
new file mode 100644
index 000000000..056795eac
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2x2_t = vuzp_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c
new file mode 100644
index 000000000..d198675cc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4x2_t = vuzp_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c
new file mode 100644
index 000000000..292a22899
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8x2_t = vuzp_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzps16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzps16.c
new file mode 100644
index 000000000..3d6590341
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzps16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzps16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzps16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4x2_t = vuzp_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzps32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzps32.c
new file mode 100644
index 000000000..68767dc8a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzps32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzps32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzps32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2x2_t = vuzp_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzps8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzps8.c
new file mode 100644
index 000000000..ef9704c36
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzps8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzps8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzps8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8x2_t = vuzp_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c
new file mode 100644
index 000000000..f6d463630
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4x2_t = vuzp_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c
new file mode 100644
index 000000000..33b75c55e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2x2_t = vuzp_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c
new file mode 100644
index 000000000..99fec5c19
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c
@@ -0,0 +1,20 @@
+/* Test the `vuzpu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vuzpu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8x2_t = vuzp_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c
new file mode 100644
index 000000000..f1d0393fb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4x2_t = vzipq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c
new file mode 100644
index 000000000..d378c5166
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8x2_t = vzipq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c
new file mode 100644
index 000000000..ce557b78a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16x2_t = vzipq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c
new file mode 100644
index 000000000..b629a40c6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8x2_t = vzipq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c
new file mode 100644
index 000000000..09c0ef6a7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4x2_t = vzipq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c
new file mode 100644
index 000000000..6bc9461c4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16x2_t = vzipq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c
new file mode 100644
index 000000000..743929027
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8x2_t = vzipq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c
new file mode 100644
index 000000000..d499070e6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4x2_t = vzipq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c
new file mode 100644
index 000000000..35d0ef6a1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vzipQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipQu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16x2_t = vzipq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipf32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipf32.c
new file mode 100644
index 000000000..e1f7ff1d7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipf32.c
@@ -0,0 +1,20 @@
+/* Test the `vzipf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2x2_t = vzip_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipp16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipp16.c
new file mode 100644
index 000000000..e8a62b107
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipp16.c
@@ -0,0 +1,20 @@
+/* Test the `vzipp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4x2_t = vzip_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipp8.c
new file mode 100644
index 000000000..553b69127
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipp8.c
@@ -0,0 +1,20 @@
+/* Test the `vzipp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8x2_t = vzip_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzips16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzips16.c
new file mode 100644
index 000000000..0693ee7af
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzips16.c
@@ -0,0 +1,20 @@
+/* Test the `vzips16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzips16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4x2_t = vzip_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzips32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzips32.c
new file mode 100644
index 000000000..29990f3ac
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzips32.c
@@ -0,0 +1,20 @@
+/* Test the `vzips32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzips32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2x2_t = vzip_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzips8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzips8.c
new file mode 100644
index 000000000..9546ad88d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzips8.c
@@ -0,0 +1,20 @@
+/* Test the `vzips8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzips8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8x2_t = vzip_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipu16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipu16.c
new file mode 100644
index 000000000..ebcb9f23c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipu16.c
@@ -0,0 +1,20 @@
+/* Test the `vzipu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4x2_t = vzip_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipu32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipu32.c
new file mode 100644
index 000000000..6ba6c32aa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipu32.c
@@ -0,0 +1,20 @@
+/* Test the `vzipu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2x2_t = vzip_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipu8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipu8.c
new file mode 100644
index 000000000..94a280cd4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/neon/vzipu8.c
@@ -0,0 +1,20 @@
+/* Test the `vzipu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0 -mfpu=neon -mfloat-abi=softfp" } */
+
+#include "arm_neon.h"
+
+void test_vzipu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8x2_t = vzip_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/pr40482.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/pr40482.c
new file mode 100644
index 000000000..4303a4f2e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/pr40482.c
@@ -0,0 +1,7 @@
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-final { scan-assembler-not "ldr" } } */
+
+unsigned int foo (unsigned int i )
+{
+  return i | 0xff000000;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/pr40670.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/pr40670.c
new file mode 100644
index 000000000..24786385d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/pr40670.c
@@ -0,0 +1,8 @@
+/* { dg-options "-mthumb -O2" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-final { scan-assembler-not "ldr" } } */
+
+float foo (void)
+{
+  return 2.0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/pr40835.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/pr40835.c
new file mode 100644
index 000000000..76ad509eb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/pr40835.c
@@ -0,0 +1,56 @@
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-final { scan-assembler-not "cmp" } } */
+
+int bar();
+void goo(int, int);
+
+void eq()
+{
+  int v = bar();
+  if (v == 0)
+    return;
+  goo(1, v);
+}
+
+void ge()
+{
+  int v = bar();
+  if (v >= 0)
+    return;
+  goo(1, v);
+}
+
+void gt()
+{
+  int v = bar();
+  if (v > 0)
+    return;
+  goo(1, v);
+}
+
+void lt()
+{
+  int v = bar();
+  if (v < 0)
+    return;
+  goo(1, v);
+}
+
+void le()
+{
+  int v = bar();
+  if (v <= 0)
+    return;
+  goo(1, v);
+}
+
+unsigned int foo();
+
+void leu()
+{
+  unsigned int v = foo();
+  if (v <= 0)
+    return;
+  goo(1, v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/pr42496.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/pr42496.c
new file mode 100644
index 000000000..c6d8a1f39
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/pr42496.c
@@ -0,0 +1,16 @@
+/* { dg-options "-O2" }  */
+
+void foo(int i)
+{
+    extern int j;
+
+    if (i) {
+         j = 10;
+    }
+    else {
+          j = 20;
+    }
+}
+
+/* { dg-final { scan-assembler-not "strne" } } */
+/* { dg-final { scan-assembler-not "streq" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/pr42879.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/pr42879.c
new file mode 100644
index 000000000..02af72c18
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/pr42879.c
@@ -0,0 +1,15 @@
+/* { dg-options "-march=armv7-a -mthumb -Os" }  */
+/* { dg-final { scan-assembler "lsls" } } */
+
+struct A
+{
+  int v:1;
+};
+
+int bar();
+int foo(struct A* p)
+{
+  if (p->v)
+    return 1;
+  return bar();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/register-variables.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/register-variables.c
new file mode 100644
index 000000000..8c874b22e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/register-variables.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-options "-O" } */
+
+#include <stdlib.h>
+
+void __attribute__((noinline)) 
+bar(int a, int b)
+{
+  if (a != 43 || b != 42)
+    abort();
+}
+
+int main(void)
+{
+    register int r0 asm("r0") = 42;
+    register int r1 asm("r1") = 43;
+    asm volatile("": "+r" (r0), "+r" (r1));
+    bar(r1, r0);
+    return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/scd42-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/scd42-1.c
new file mode 100644
index 000000000..e02a898e6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/scd42-1.c
@@ -0,0 +1,15 @@
+/* Verify that mov is preferred on XScale for loading a 1 byte constant. */
+/* { dg-do compile } */
+/* { dg-options "-mcpu=xscale -O" } */
+
+unsigned load1(void) __attribute__ ((naked));
+unsigned load1(void)
+{
+    /* Best code would be:
+       mov r0, =17
+       mov pc, lr */
+
+    return 17;
+}
+
+/* { dg-final { scan-assembler "mov\[ 	].*17" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/scd42-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/scd42-2.c
new file mode 100644
index 000000000..0c372983a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/scd42-2.c
@@ -0,0 +1,18 @@
+/* Verify that mov is preferred on XScale for loading a 2 byte constant. */
+/* { dg-do compile } */
+/* { dg-options "-mcpu=xscale -O" } */
+/* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-march=*" } { "-march=xscale" } } */
+/* { dg-require-effective-target arm32 } */
+
+unsigned load2(void) __attribute__ ((naked));
+unsigned load2(void)
+{
+    /* Best code would be:
+       mov r0, =272
+       add r0, r0, =1
+       mov pc, lr */
+
+    return 273;
+}
+
+/* { dg-final { scan-assembler "mov\[ 	].*272" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/scd42-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/scd42-3.c
new file mode 100644
index 000000000..b2e66662c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/scd42-3.c
@@ -0,0 +1,15 @@
+/* Verify that ldr is preferred on XScale for loading a 3 or 4 byte constant. */
+/* { dg-do compile } */
+/* { dg-options "-mcpu=xscale -O" } */
+
+unsigned load4(void) __attribute__ ((naked));
+unsigned load4(void)
+{
+    /* Best code would be:
+       ldr r0, =65809
+       mov pc, lr */
+
+    return 65809;
+}
+
+/* { dg-final { scan-assembler "ldr\[ 	].*" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/sibcall-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/sibcall-1.c
new file mode 100644
index 000000000..77c94fdd0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/sibcall-1.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target { arm32 } } } */
+/* { dg-options "-O2" } */
+
+#define noinline __attribute__((noinline))
+
+typedef struct {
+  int data[4];
+} arr16_t;
+
+int result = 0;
+
+void noinline func2 (int i, int j, arr16_t arr)
+{
+  result = (arr.data[0] != 1
+	    || arr.data[1] != 2
+	    || arr.data[2] != 3
+	    || arr.data[3] != 4);
+}
+
+void func1 (int i, int j, int k, int l, int m, int n, arr16_t a)
+{
+  func2(i, j, a);
+}
+
+int main(int argc, const char *argv[])
+{
+  arr16_t arr = {{1, 2, 3, 4}};
+    
+  func1(0, 0, 0, 0, 0, 0, arr);
+  return result;
+}
+
+/* { dg-final { scan-assembler "\tb\tfunc2\n" } } */
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/stack-corruption.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/stack-corruption.c
new file mode 100644
index 000000000..3a63950cc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/stack-corruption.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mthumb -fno-omit-frame-pointer" } */
+
+int main() {
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "\tadd\tr7, sp, #8\n" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/symbian1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/symbian1.c
new file mode 100644
index 000000000..25e812816
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/symbian1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target arm*-*-symbianelf* } } */
+/* Symbian OS requires that all defined symbols with external linkage
+   have the ELF STV_HIDDEN attribute set by default.  */
+/* { dg-final { scan-assembler ".hidden.*i" } } */
+/* { dg-final { scan-assembler ".hidden.*j" } } */
+/* { dg-final { scan-assembler ".hidden.*f" } } */
+
+int i;
+int j = 3;
+void f() {}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/symbian2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/symbian2.c
new file mode 100644
index 000000000..987016368
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/symbian2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target arm*-*-symbianelf* } } */
+/* { dg-options "-O2" } */
+
+/* Symbian OS requires that builtins not be expanded by default.  Make
+   sure that a reference to "strlen" is emitted.  */
+/* { dg-final { scan-assembler "strlen" } } */
+
+int f() {
+  return strlen("abc");
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/symbian3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/symbian3.c
new file mode 100644
index 000000000..2f11d355b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/symbian3.c
@@ -0,0 +1,7 @@
+/* { dg-do compile { target arm*-*-symbianelf* } } */
+/* Check that enumeration types are 4-byte types.  */
+
+enum e { e_1 };
+
+extern int i[sizeof (enum e)];
+int i[4];
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/symbian4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/symbian4.c
new file mode 100644
index 000000000..aede7f5c6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/symbian4.c
@@ -0,0 +1,5 @@
+/* { dg-do compile { target arm*-*-symbianelf* } } */
+/* Check that wchar_t is a 2-byte type.  */
+
+extern int i[sizeof (L'a')];
+int i[2];
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/symbian5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/symbian5.c
new file mode 100644
index 000000000..0bde6b0cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/symbian5.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target arm*-*-symbianelf* } } */
+/* { dg-options "-fno-short-wchar" } */
+/* Check that wchar_t is a 4-byte type when -fno-short-wchar is
+   used.  */
+
+extern int i[sizeof (L'a')];
+int i[4];
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/synchronize.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/synchronize.c
new file mode 100644
index 000000000..81ed84811
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/synchronize.c
@@ -0,0 +1,6 @@
+/* { dg-final { scan-assembler "__sync_synchronize" { target arm*-*-linux-*eabi } } } */
+
+void *foo (void)
+{
+  __sync_synchronize();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/thumb-andsi.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/thumb-andsi.c
new file mode 100644
index 000000000..992d437c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/thumb-andsi.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+
+unsigned get_least_bits(unsigned value)
+{
+  return value << 9 >> 9;
+}
+
+/* { dg-final { scan-assembler "lsl" } } */
+/* { dg-final { scan-assembler "lsr" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c
new file mode 100644
index 000000000..64423e818
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+
+int ldrb(unsigned char* p)
+{
+  if (p[8] <= 0x7F)
+    return 2;
+  else
+    return 5;
+}
+
+
+/* { dg-final { scan-assembler "127" } } */
+/* { dg-final { scan-assembler "ldrb" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/va_list.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/va_list.c
new file mode 100644
index 000000000..b988a0d33
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/va_list.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_eabi } */
+
+#include <stdarg.h>
+#include <stddef.h>
+
+/* AAPCS \S 7.1.4 requires that va_list match the structure shown
+   here */
+typedef struct my_va_list 
+{
+  void *ap;
+} my_va_list;
+
+int 
+main () {
+  if (sizeof (va_list) != sizeof (my_va_list))
+    return 1;
+  /* This check confirms both that "va_list" has a member named "__ap"
+     and that it is located at the correct position.  */
+  if (offsetof (va_list, __ap) 
+      != offsetof (my_va_list, ap))
+    return 2;
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/arm/vfp-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/vfp-1.c
new file mode 100644
index 000000000..bbf914098
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/arm/vfp-1.c
@@ -0,0 +1,127 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_vfp_ok } */
+
+extern float fabsf (float);
+extern float sqrtf (float);
+extern double fabs (double);
+extern double sqrt (double);
+
+volatile float f1, f2, f3;
+
+void test_sf() {
+  /* abssf2_vfp */
+  /* { dg-final { scan-assembler "fabss" } } */
+  f1 = fabsf (f1);
+  /* negsf2_vfp */
+  /* { dg-final { scan-assembler "fnegs" } } */
+  f1 = -f1;
+  /* addsf3_vfp */
+  /* { dg-final { scan-assembler "fadds" } } */
+  f1 = f2 + f3;
+  /* subsf3_vfp */
+  /* { dg-final { scan-assembler "fsubs" } } */
+  f1 = f2 - f3;
+  /* divsf3_vfp */
+  /* { dg-final { scan-assembler "fdivs" } } */
+  f1 = f2 / f3;
+  /* mulsf3_vfp */
+  /* { dg-final { scan-assembler "fmuls" } } */
+  f1 = f2 * f3;
+  /* mulsf3negsf_vfp */
+  /* { dg-final { scan-assembler "fnmuls" } } */
+  f1 = -f2 * f3;
+  /* mulsf3addsf_vfp */
+  /* { dg-final { scan-assembler "fmacs" } } */
+  f1 = f2 * f3 + f1;
+  /* mulsf3subsf_vfp */
+  /* { dg-final { scan-assembler "fmscs" } } */
+  f1 = f2 * f3 - f1;
+  /* mulsf3negsfaddsf_vfp */
+  /* { dg-final { scan-assembler "fnmacs" } } */
+  f1 = f2 - f3 * f1;
+  /* mulsf3negsfsubsf_vfp */
+  /* { dg-final { scan-assembler "fnmscs" } } */
+  f1 = -f2 * f3 - f1;
+  /* sqrtsf2_vfp */
+  /* { dg-final { scan-assembler "fsqrts" } } */
+  f1 = sqrtf (f1);
+}
+
+volatile double d1, d2, d3;
+
+void test_df() {
+  /* absdf2_vfp */
+  /* { dg-final { scan-assembler "fabsd" } } */
+  d1 = fabs (d1);
+  /* negdf2_vfp */
+  /* { dg-final { scan-assembler "fnegd" } } */
+  d1 = -d1;
+  /* adddf3_vfp */
+  /* { dg-final { scan-assembler "faddd" } } */
+  d1 = d2 + d3;
+  /* subdf3_vfp */
+  /* { dg-final { scan-assembler "fsubd" } } */
+  d1 = d2 - d3;
+  /* divdf3_vfp */
+  /* { dg-final { scan-assembler "fdivd" } } */
+  d1 = d2 / d3;
+  /* muldf3_vfp */
+  /* { dg-final { scan-assembler "fmuld" } } */
+  d1 = d2 * d3;
+  /* muldf3negdf_vfp */
+  /* { dg-final { scan-assembler "fnmuld" } } */
+  d1 = -d2 * d3;
+  /* muldf3adddf_vfp */
+  /* { dg-final { scan-assembler "fmacd" } } */
+  d1 = d2 * d3 + d1;
+  /* muldf3subdf_vfp */
+  /* { dg-final { scan-assembler "fmscd" } } */
+  d1 = d2 * d3 - d1;
+  /* muldf3negdfadddf_vfp */
+  /* { dg-final { scan-assembler "fnmacd" } } */
+  d1 = d2 - d3 * d1;
+  /* muldf3negdfsubdf_vfp */
+  /* { dg-final { scan-assembler "fnmscd" } } */
+  d1 = -d2 * d3 - d1;
+  /* sqrtdf2_vfp */
+  /* { dg-final { scan-assembler "fsqrtd" } } */
+  d1 = sqrt (d1);
+}
+
+volatile int i1;
+volatile unsigned int u1;
+
+void test_convert () {
+  /* extendsfdf2_vfp */
+  /* { dg-final { scan-assembler "fcvtds" } } */
+  d1 = f1;
+  /* truncdfsf2_vfp */
+  /* { dg-final { scan-assembler "fcvtsd" } } */
+  f1 = d1;
+  /* truncsisf2_vfp */
+  /* { dg-final { scan-assembler "ftosizs" } } */
+  i1 = f1;
+  /* truncsidf2_vfp */
+  /* { dg-final { scan-assembler "ftosizd" } } */
+  i1 = d1;
+  /* fixuns_truncsfsi2 */
+  /* { dg-final { scan-assembler "ftouizs" } } */
+  u1 = f1;
+  /* fixuns_truncdfsi2 */
+  /* { dg-final { scan-assembler "ftouizd" } } */
+  u1 = d1;
+  /* floatsisf2_vfp */
+  /* { dg-final { scan-assembler "fsitos" } } */
+  f1 = i1;
+  /* floatsidf2_vfp */
+  /* { dg-final { scan-assembler "fsitod" } } */
+  d1 = i1;
+  /* floatunssisf2 */
+  /* { dg-final { scan-assembler "fuitos" } } */
+  f1 = u1;
+  /* floatunssidf2 */
+  /* { dg-final { scan-assembler "fuitod" } } */
+  d1 = u1;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/avr/avr.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/avr/avr.exp
new file mode 100644
index 000000000..90aeed41e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/avr/avr.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 2008 Free Software Foundation, Inc.

+

+# This program is free software; you can redistribute it and/or modify

+# it under the terms of the GNU General Public License as published by

+# the Free Software Foundation; either version 3 of the License, or

+# (at your option) any later version.

+# 

+# This program is distributed in the hope that it will be useful,

+# but WITHOUT ANY WARRANTY; without even the implied warranty of

+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+# GNU General Public License for more details.

+# 

+# You should have received a copy of the GNU General Public License

+# along with GCC; see the file COPYING3.  If not see

+# <http://www.gnu.org/licenses/>.

+

+# GCC testsuite that uses the `dg.exp' driver.

+

+# Exit immediately if this isn't an AVR target.

+if ![istarget avr-*-*] then {

+  return

+}

+

+# Load support procs.

+load_lib gcc-dg.exp

+

+# If a testcase doesn't have special options, use these.

+global DEFAULT_CFLAGS

+if ![info exists DEFAULT_CFLAGS] then {

+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"

+}

+

+# Initialize `dg'.

+dg-init

+

+# Main loop.

+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \

+	"" $DEFAULT_CFLAGS

+

+# All done.

+dg-finish

diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/avr/torture/avr-torture.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/avr/torture/avr-torture.exp
new file mode 100644
index 000000000..355b3ad88
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/avr/torture/avr-torture.exp
@@ -0,0 +1,61 @@
+#   Copyright (C) 2008 Free Software Foundation, Inc.

+

+# This program is free software; you can redistribute it and/or modify

+# it under the terms of the GNU General Public License as published by

+# the Free Software Foundation; either version 3 of the License, or

+# (at your option) any later version.

+# 

+# This program is distributed in the hope that it will be useful,

+# but WITHOUT ANY WARRANTY; without even the implied warranty of

+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+# GNU General Public License for more details.

+# 

+# You should have received a copy of the GNU General Public License

+# along with GCC; see the file COPYING3.  If not see

+# <http://www.gnu.org/licenses/>.

+

+# GCC testsuite that uses the `gcc-dg.exp' driver, looping over

+# optimization options.

+

+# Exit immediately if this isn't a AVR target.

+if { ![istarget avr-*-*] } then {

+  return

+}

+

+# Load support procs.

+load_lib gcc-dg.exp

+

+# If a testcase doesn't have special options, use these.

+global DEFAULT_CFLAGS

+if ![info exists DEFAULT_CFLAGS] then {

+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"

+}

+

+# Initialize `dg'.

+dg-init

+

+    set AVR_TORTURE_OPTIONS [list \

+	{ -O0 } \

+	{ -O1 } \

+	{ -O2 } \

+	{ -O2 -mcall-prologues } \

+	{ -Os -fomit-frame-pointer } \

+	{ -Os -fomit-frame-pointer -finline-functions } \

+	{ -O3 -g } \

+	{ -Os -mcall-prologues} ]

+

+

+#Initialize use of torture lists. 

+torture-init

+

+set-torture-options $AVR_TORTURE_OPTIONS

+

+

+# Main loop.

+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] $DEFAULT_CFLAGS

+

+# Finalize use of torture lists.

+torture-finish

+

+# All done.

+dg-finish

diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/avr/torture/trivial.c b/gcc-4.4.3/gcc/testsuite/gcc.target/avr/torture/trivial.c
new file mode 100644
index 000000000..91163f922
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/avr/torture/trivial.c
@@ -0,0 +1,14 @@
+/* { dg-do run } */

+#include <stdio.h>

+

+#define __ATTR_PROGMEM__ __attribute__((__progmem__))

+

+#define PROGMEM __ATTR_PROGMEM__

+char PROGMEM a1 = 0x12; 

+int PROGMEM a2 = 0x2345; 

+long PROGMEM a3 = 0x12345678; 

+int main(void)

+{

+  printf("Hello World\n");

+  return 0;

+}

diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/avr/trivial.c b/gcc-4.4.3/gcc/testsuite/gcc.target/avr/trivial.c
new file mode 100644
index 000000000..91163f922
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/avr/trivial.c
@@ -0,0 +1,14 @@
+/* { dg-do run } */

+#include <stdio.h>

+

+#define __ATTR_PROGMEM__ __attribute__((__progmem__))

+

+#define PROGMEM __ATTR_PROGMEM__

+char PROGMEM a1 = 0x12; 

+int PROGMEM a2 = 0x2345; 

+long PROGMEM a3 = 0x12345678; 

+int main(void)

+{

+  printf("Hello World\n");

+  return 0;

+}

diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/arith.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/arith.c
new file mode 100644
index 000000000..35029ed32
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/arith.c
@@ -0,0 +1,48 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, c, d;
+  fract16 t1, t2;
+  a = __builtin_bfin_compose_2x16 (0x3000, 0x2000);
+  b = __builtin_bfin_compose_2x16 (0x7000, 0x5000);
+  c = __builtin_bfin_compose_2x16 (0x7000, 0xc000);
+
+  d = __builtin_bfin_add_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != 0x7000 || t2 != 0x7fff)
+    abort ();
+
+  d = __builtin_bfin_sub_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != -0x3000 || t2 != -0x4000)
+    abort ();
+
+  d = __builtin_bfin_negate_fr2x16 (c);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != 0x4000 || t2 != -0x7000)
+    abort ();
+  
+  if (__builtin_bfin_add_fr1x32 (0x7fffffff, 1) != 0x7fffffff)
+    abort ();
+
+  if (__builtin_bfin_add_fr1x32 (0x80000000, -1) != 0x80000000)
+    abort ();
+    
+  if (__builtin_bfin_add_fr1x32 (0x80000001, -1) != 0x80000000)
+    abort ();
+    
+  if (__builtin_bfin_add_fr1x32 (0xFEDCBA98, 0x11111111) != 0x0FEDCBA9)
+    abort ();
+    
+  exit (0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/bfin.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/bfin.exp
new file mode 100644
index 000000000..854713e2f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/bfin.exp
@@ -0,0 +1,63 @@
+# Copyright (C) 2007 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an BFIN target.
+if ![istarget bfin-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Like dg-options, but treats certain Blackfin-specific options specially:
+#
+#    -mcpu=*
+#	Select the target cpu. Skip the test if the multilib flags force
+#	a different cpu.
+proc dg-bfin-options {args} {
+    upvar dg-extra-tool-flags extra_tool_flags
+    upvar dg-do-what do_what
+
+    set multilib_cpu ""
+    set cpu ""
+
+    foreach flag [target_info multilib_flags] {
+	regexp "^-mcpu=(.*)" $flag dummy multilib_cpu
+    }
+
+    set flags [lindex $args 1]
+
+    foreach flag $flags {
+	regexp "^-mcpu=(.*)" $flag dummy cpu
+    }
+
+    if {$multilib_cpu == "" || $multilib_cpu == $cpu} {
+	set extra_tool_flags $flags
+    } else {
+	set do_what [list [lindex $do_what 0] "N" "P"]
+    }
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]]	"" ""
+
+# All done.
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/frmul.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/frmul.c
new file mode 100644
index 000000000..61930bae5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/frmul.c
@@ -0,0 +1,149 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+#define GETVECT(HILO1,HILO2,IN1,IN2)					\
+  __builtin_bfin_compose_2x16 ((HILO2) ? __builtin_bfin_extract_hi (IN1) : __builtin_bfin_extract_lo (IN1), \
+			  (HILO1) ? __builtin_bfin_extract_hi (IN2) : __builtin_bfin_extract_lo (IN2))
+#define DOTEST(IN1, IN2, HL1, HL2, HL3, HL4)					\
+  __builtin_bfin_multr_fr2x16 (GETVECT (HL1, HL2, IN1, IN1), \
+			  GETVECT (HL3, HL4, IN2, IN2))
+
+#define FUNC(HL1, HL2, HL3, HL4) \
+  fract2x16 foo ## HL1 ## HL2 ## HL3 ## HL4 (fract2x16 a, fract2x16 b)\
+  { \
+    return DOTEST(a, b, HL1, HL2, HL3, HL4);\
+  }
+
+FUNC (0, 0, 0, 0)
+FUNC (1, 0, 0, 0)
+FUNC (0, 1, 0, 0)
+FUNC (1, 1, 0, 0)
+FUNC (0, 0, 1, 0)
+FUNC (1, 0, 1, 0)
+FUNC (0, 1, 1, 0)
+FUNC (1, 1, 1, 0)
+FUNC (0, 0, 0, 1)
+FUNC (1, 0, 0, 1)
+FUNC (0, 1, 0, 1)
+FUNC (1, 1, 0, 1)
+FUNC (0, 0, 1, 1)
+FUNC (1, 0, 1, 1)
+FUNC (0, 1, 1, 1)
+FUNC (1, 1, 1, 1)
+
+#define RES1 0x1400
+#define RES2 0x1e00
+#define RES3 0x1c00
+#define RES4 0x2a00
+
+
+int main ()
+{
+  fract2x16 a, b, c;
+  fract16 t1, t2;
+  a = __builtin_bfin_compose_2x16 (0x3000, 0x2000);
+  b = __builtin_bfin_compose_2x16 (0x7000, 0x5000);
+
+  c = foo0000 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES1 || t2 != RES1)
+    abort ();
+
+  c = foo1000 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES2 || t2 != RES1)
+    abort ();
+
+  c = foo0100 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES1 || t2 != RES2)
+    abort ();
+
+  c = foo1100 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES2 || t2 != RES2)
+    abort ();
+
+  c = foo0010 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES3 || t2 != RES1)
+    abort ();
+
+  c = foo1010 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES4 || t2 != RES1)
+    abort ();
+
+  c = foo0110 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES3 || t2 != RES2)
+    abort ();
+
+  c = foo1110 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES4 || t2 != RES2)
+    abort ();
+
+  c = foo0001 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES1 || t2 != RES3)
+    abort ();
+
+  c = foo1001 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES2 || t2 != RES3)
+    abort ();
+
+  c = foo0101 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES1 || t2 != RES4)
+    abort ();
+
+  c = foo1101 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES2 || t2 != RES4)
+    abort ();
+
+  c = foo0011 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES3 || t2 != RES3)
+    abort ();
+
+  c = foo1011 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES4 || t2 != RES3)
+    abort ();
+
+  c = foo0111 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES3 || t2 != RES4)
+    abort ();
+
+  c = foo1111 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES4 || t2 != RES4)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/hisilh-O0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/hisilh-O0.c
new file mode 100644
index 000000000..50786b8be
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/hisilh-O0.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target bfin*-*-* } } */
+/* { dg-options "-O0" } */
+#include <stdlib.h>
+typedef short raw2x16 __attribute__ ((vector_size(4)));
+
+int x;
+
+int ll(raw2x16 a, raw2x16 b)
+{
+    x = __builtin_bfin_mulhisill(a, b);
+    return x;
+}
+
+int lh(raw2x16 a, raw2x16 b)
+{
+    x = __builtin_bfin_mulhisilh(a, b);
+    return x;
+}
+
+int hl(raw2x16 a, raw2x16 b)
+{
+    x = __builtin_bfin_mulhisihl(a, b);
+    return x;
+}
+
+int hh(raw2x16 a, raw2x16 b)
+{
+    x = __builtin_bfin_mulhisihh(a, b);
+    return x;
+}
+
+int main ()
+{
+    raw2x16 a = __builtin_bfin_compose_2x16 (0x1234, 0x5678);
+    raw2x16 b = __builtin_bfin_compose_2x16 (0xFEDC, 0xBA98);
+    if (ll (a, b) != 0xe88e8740)
+	abort ();
+    if (lh (a, b) != 0xff9d5f20)
+	abort ();
+    if (hl (a, b) != 0xfb1096e0)
+	abort ();
+    if (hh (a, b) != 0xffeb3cb0)
+	abort ();
+    
+    return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/hisilh.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/hisilh.c
new file mode 100644
index 000000000..4efbfd449
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/hisilh.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target bfin*-*-* } } */
+/* { dg-options "-O2" } */
+#include <stdlib.h>
+typedef short raw2x16 __attribute__ ((vector_size(4)));
+
+int x;
+
+int ll(raw2x16 a, raw2x16 b)
+{
+    x = __builtin_bfin_mulhisill(a, b);
+    return x;
+}
+
+int lh(raw2x16 a, raw2x16 b)
+{
+    x = __builtin_bfin_mulhisilh(a, b);
+    return x;
+}
+
+int hl(raw2x16 a, raw2x16 b)
+{
+    x = __builtin_bfin_mulhisihl(a, b);
+    return x;
+}
+
+int hh(raw2x16 a, raw2x16 b)
+{
+    x = __builtin_bfin_mulhisihh(a, b);
+    return x;
+}
+
+int main ()
+{
+    raw2x16 a = __builtin_bfin_compose_2x16 (0x1234, 0x5678);
+    raw2x16 b = __builtin_bfin_compose_2x16 (0xFEDC, 0xBA98);
+    if (ll (a, b) != 0xe88e8740)
+	abort ();
+    if (lh (a, b) != 0xff9d5f20)
+	abort ();
+    if (hl (a, b) != 0xfb1096e0)
+	abort ();
+    if (hh (a, b) != 0xffeb3cb0)
+	abort ();
+    
+    return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/longcall-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/longcall-1.c
new file mode 100644
index 000000000..138707e9e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/longcall-1.c
@@ -0,0 +1,33 @@
+/* { dg-do compile { target bfin-*-* } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "call\[^\\n\]*foo" } } */
+/* { dg-final { scan-assembler-not "jump\[^\\n\]*foo" } } */
+/* { dg-final { scan-assembler "call\[^\\n\]*baz" } } */
+/* { dg-final { scan-assembler "jump\[^\\n\]*baz" } } */
+/* { dg-final { scan-assembler "call\[^\\n\]*bar" } } */
+/* { dg-final { scan-assembler "jump\[^\\n\]*bar" } } */
+
+extern void foo () __attribute__((longcall));
+extern void bar () __attribute__((shortcall));
+extern void baz ();
+
+int t1 ()
+{
+    foo ();
+    bar ();
+    baz ();
+    return 4;
+}
+
+void t2 ()
+{
+    foo ();
+}
+void t3 ()
+{
+    bar ();
+}
+void t4 ()
+{
+    baz ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/longcall-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/longcall-2.c
new file mode 100644
index 000000000..33189b01f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/longcall-2.c
@@ -0,0 +1,33 @@
+/* { dg-do compile { target bfin-*-* } } */
+/* { dg-options "-O2 -mlong-calls" } */
+/* { dg-final { scan-assembler-not "call\[^\\n\]*foo" } } */
+/* { dg-final { scan-assembler-not "jump\[^\\n\]*foo" } } */
+/* { dg-final { scan-assembler-not "call\[^\\n\]*baz" } } */
+/* { dg-final { scan-assembler-not "jump\[^\\n\]*baz" } } */
+/* { dg-final { scan-assembler "call\[^\\n\]*bar" } } */
+/* { dg-final { scan-assembler "jump\[^\\n\]*bar" } } */
+
+extern void foo () __attribute__((longcall));
+extern void bar () __attribute__((shortcall));
+extern void baz ();
+
+int t1 ()
+{
+    foo ();
+    bar ();
+    baz ();
+    return 4;
+}
+
+void t2 ()
+{
+    foo ();
+}
+void t3 ()
+{
+    bar ();
+}
+void t4 ()
+{
+    baz ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf512.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf512.c
new file mode 100644
index 000000000..71fbcf38d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf512.c
@@ -0,0 +1,62 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf512" } */
+
+#ifndef __ADSPBF512__
+#error "__ADSPBF512__ is not defined"
+#endif
+
+#ifndef __ADSPBF51x__
+#error "__ADSPBF51x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0000
+#error "__SILICON_REVISION__ is not 0x0000"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf512" } */
+
+#ifndef __ADSPBF512__
+#error "__ADSPBF512__ is not defined"
+#endif
+
+#ifndef __ADSPBF51x__
+#error "__ADSPBF51x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0000
+#error "__SILICON_REVISION__ is not 0x0000"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf514.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf514.c
new file mode 100644
index 000000000..b1ae2a2ce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf514.c
@@ -0,0 +1,62 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf514" } */
+
+#ifndef __ADSPBF514__
+#error "__ADSPBF514__ is not defined"
+#endif
+
+#ifndef __ADSPBF51x__
+#error "__ADSPBF51x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0000
+#error "__SILICON_REVISION__ is not 0x0000"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf514" } */
+
+#ifndef __ADSPBF514__
+#error "__ADSPBF514__ is not defined"
+#endif
+
+#ifndef __ADSPBF51x__
+#error "__ADSPBF51x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0000
+#error "__SILICON_REVISION__ is not 0x0000"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf516.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf516.c
new file mode 100644
index 000000000..675d2659d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf516.c
@@ -0,0 +1,62 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf516" } */
+
+#ifndef __ADSPBF516__
+#error "__ADSPBF516__ is not defined"
+#endif
+
+#ifndef __ADSPBF51x__
+#error "__ADSPBF51x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0000
+#error "__SILICON_REVISION__ is not 0x0000"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf516" } */
+
+#ifndef __ADSPBF516__
+#error "__ADSPBF516__ is not defined"
+#endif
+
+#ifndef __ADSPBF51x__
+#error "__ADSPBF51x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0000
+#error "__SILICON_REVISION__ is not 0x0000"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf518.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf518.c
new file mode 100644
index 000000000..d0675783b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf518.c
@@ -0,0 +1,62 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf518" } */
+
+#ifndef __ADSPBF518__
+#error "__ADSPBF518__ is not defined"
+#endif
+
+#ifndef __ADSPBF51x__
+#error "__ADSPBF51x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0000
+#error "__SILICON_REVISION__ is not 0x0000"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf518" } */
+
+#ifndef __ADSPBF518__
+#error "__ADSPBF518__ is not defined"
+#endif
+
+#ifndef __ADSPBF51x__
+#error "__ADSPBF51x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0000
+#error "__SILICON_REVISION__ is not 0x0000"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf522.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf522.c
new file mode 100644
index 000000000..58c325e0c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf522.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf522" } */
+
+#ifndef __ADSPBF522__
+#error "__ADSPBF522__ is not defined"
+#endif
+
+#ifndef __ADSPBF52x__
+#error "__ADSPBF52x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf523.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf523.c
new file mode 100644
index 000000000..10f71eddb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf523.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf523" } */
+
+#ifndef __ADSPBF523__
+#error "__ADSPBF523__ is not defined"
+#endif
+
+#ifndef __ADSPBF52x__
+#error "__ADSPBF52x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf524.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf524.c
new file mode 100644
index 000000000..d8e30c4f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf524.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf524" } */
+
+#ifndef __ADSPBF524__
+#error "__ADSPBF524__ is not defined"
+#endif
+
+#ifndef __ADSPBF52x__
+#error "__ADSPBF52x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf525.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf525.c
new file mode 100644
index 000000000..0e021e46f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf525.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf525" } */
+
+#ifndef __ADSPBF525__
+#error "__ADSPBF525__ is not defined"
+#endif
+
+#ifndef __ADSPBF52x__
+#error "__ADSPBF52x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf526.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf526.c
new file mode 100644
index 000000000..e3e248a9b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf526.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf526" } */
+
+#ifndef __ADSPBF526__
+#error "__ADSPBF526__ is not defined"
+#endif
+
+#ifndef __ADSPBF52x__
+#error "__ADSPBF52x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf527.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf527.c
new file mode 100644
index 000000000..41f493114
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf527.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf527" } */
+
+#ifndef __ADSPBF527__
+#error "__ADSPBF527__ is not defined"
+#endif
+
+#ifndef __ADSPBF52x__
+#error "__ADSPBF52x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf531.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf531.c
new file mode 100644
index 000000000..ebcf39822
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf531.c
@@ -0,0 +1,33 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf531" } */
+
+#ifndef __ADSPBF531__
+#error "__ADSPBF531__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0006
+#error "__SILICON_REVISION__ is not 0x0006"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0005
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf532.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf532.c
new file mode 100644
index 000000000..18ff74a4c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf532.c
@@ -0,0 +1,33 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf532" } */
+
+#ifndef __ADSPBF532__
+#error "__ADSPBF532__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0006
+#error "__SILICON_REVISION__ is not 0x0006"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0005
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf533.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf533.c
new file mode 100644
index 000000000..d961d7a72
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf533.c
@@ -0,0 +1,33 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf533" } */
+
+#ifndef __ADSPBF533__
+#error "__ADSPBF533__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0006
+#error "__SILICON_REVISION__ is not 0x0006"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0005
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf534.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf534.c
new file mode 100644
index 000000000..cd354596d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf534.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf534" } */
+
+#ifndef __ADSPBF534__
+#error "__ADSPBF534__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0003
+#error "__SILICON_REVISION__ is not 0x0003"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf536.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf536.c
new file mode 100644
index 000000000..0ac9ebf9a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf536.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf536" } */
+
+#ifndef __ADSPBF536__
+#error "__ADSPBF536__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0003
+#error "__SILICON_REVISION__ is not 0x0003"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf537.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf537.c
new file mode 100644
index 000000000..66a87c045
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf537.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf537" } */
+
+#ifndef __ADSPBF537__
+#error "__ADSPBF537__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0003
+#error "__SILICON_REVISION__ is not 0x0003"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf538.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf538.c
new file mode 100644
index 000000000..188f8708c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf538.c
@@ -0,0 +1,33 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf538" } */
+
+#ifndef __ADSPBF538__
+#error "__ADSPBF538__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0005
+#error "__SILICON_REVISION__ is not 0x0005"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0004
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf539.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf539.c
new file mode 100644
index 000000000..acb0d8936
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf539.c
@@ -0,0 +1,33 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf539" } */
+
+#ifndef __ADSPBF539__
+#error "__ADSPBF539__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0005
+#error "__SILICON_REVISION__ is not 0x0005"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0004
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c
new file mode 100644
index 000000000..4d95d65de
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf542" } */
+
+#ifndef __ADSPBF542__
+#error "__ADSPBF542__ is not defined"
+#endif
+
+#ifndef __ADSPBF54x__
+#error "__ADSPBF54x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c
new file mode 100644
index 000000000..39314b008
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf544" } */
+
+#ifndef __ADSPBF544__
+#error "__ADSPBF544__ is not defined"
+#endif
+
+#ifndef __ADSPBF54x__
+#error "__ADSPBF54x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c
new file mode 100644
index 000000000..4036c02f4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf547" } */
+
+#ifndef __ADSPBF547__
+#error "__ADSPBF547__ is not defined"
+#endif
+
+#ifndef __ADSPBF54x__
+#error "__ADSPBF54x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c
new file mode 100644
index 000000000..71d3bb87b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf548" } */
+
+#ifndef __ADSPBF548__
+#error "__ADSPBF548__ is not defined"
+#endif
+
+#ifndef __ADSPBF54x__
+#error "__ADSPBF54x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c
new file mode 100644
index 000000000..201b1019b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf549" } */
+
+#ifndef __ADSPBF549__
+#error "__ADSPBF549__ is not defined"
+#endif
+
+#ifndef __ADSPBF54x__
+#error "__ADSPBF54x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf561.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf561.c
new file mode 100644
index 000000000..e2eab3ba3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-bf561.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf561" } */
+
+#ifndef __ADSPBF561__
+#error "__ADSPBF561__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0005
+#error "__SILICON_REVISION__ is not 0x0005"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-default.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-default.c
new file mode 100644
index 000000000..9109701cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mcpu-default.c
@@ -0,0 +1,93 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "" } */
+
+#ifdef __ADSPBF522__
+#error "__ADSPBF522__ is defined"
+#endif
+#ifdef __ADSPBF523__
+#error "__ADSPBF523__ is defined"
+#endif
+#ifdef __ADSPBF524__
+#error "__ADSPBF524__ is defined"
+#endif
+#ifdef __ADSPBF525__
+#error "__ADSPBF525__ is defined"
+#endif
+#ifdef __ADSPBF526__
+#error "__ADSPBF526__ is defined"
+#endif
+#ifdef __ADSPBF527__
+#error "__ADSPBF527__ is defined"
+#endif
+
+
+#ifdef __ADSPBF531__
+#error "__ADSPBF531__ is defined"
+#endif
+#ifdef __ADSPBF532__
+#error "__ADSPBF532__ is defined"
+#endif
+#ifdef __ADSPBF533__
+#error "__ADSPBF533__ is defined"
+#endif
+#ifdef __ADSPBF534__
+#error "__ADSPBF534__ is defined"
+#endif
+#ifdef __ADSPBF536__
+#error "__ADSPBF536__ is defined"
+#endif
+#ifdef __ADSPBF537__
+#error "__ADSPBF537__ is defined"
+#endif
+#ifdef __ADSPBF538__
+#error "__ADSPBF538__ is defined"
+#endif
+#ifdef __ADSPBF539__
+#error "__ADSPBF539__ is defined"
+#endif
+
+#ifdef __ADSPBF542__
+#error "__ADSPBF542__ is defined"
+#endif
+#ifdef __ADSPBF544__
+#error "__ADSPBF544__ is defined"
+#endif
+#ifdef __ADSPBF547__
+#error "__ADSPBF547__ is defined"
+#endif
+#ifdef __ADSPBF548__
+#error "__ADSPBF548__ is defined"
+#endif
+#ifdef __ADSPBF549__
+#error "__ADSPBF548__ is defined"
+#endif
+
+#ifdef __ADSPBF561__
+#error "__ADSPBF561__ is defined"
+#endif
+
+
+#ifndef __SILICON_REVISION__
+#error "__SILICON_REVISION__ is not defined"
+#else
+#if __SILICON_REVISION__ != 0xffff
+#error "__SILICON_REVISION__ is not 0xFFFF"
+#endif
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is not defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mul-combine.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mul-combine.c
new file mode 100644
index 000000000..2a811b332
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/mul-combine.c
@@ -0,0 +1,45 @@
+/* Make sure combine eliminates all unnecessary instructions for the
+   sixteen cases of hi/lo multiplications.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-not "<<" } } */
+/* { dg-final { scan-assembler-not "PACK" } } */
+
+extern void abort (void);
+extern void exit (int);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+#define GETVECT(HILO1,HILO2,IN1,IN2)					\
+  __builtin_bfin_compose_2x16 ((HILO2) ? __builtin_bfin_extract_hi (IN1) : __builtin_bfin_extract_lo (IN1), \
+			  (HILO1) ? __builtin_bfin_extract_hi (IN2) : __builtin_bfin_extract_lo (IN2))
+#define DOTEST(IN1, IN2, HL1, HL2, HL3, HL4)					\
+  __builtin_bfin_multr_fr2x16 (GETVECT (HL1, HL2, IN1, IN1), \
+			  GETVECT (HL3, HL4, IN2, IN2))
+
+#define FUNC(HL1, HL2, HL3, HL4) \
+  fract2x16 foo ## HL1 ## HL2 ## HL3 ## HL4 (fract2x16 a, fract2x16 b)\
+  { \
+    return DOTEST(a, b, HL1, HL2, HL3, HL4);\
+  }
+
+FUNC (0, 0, 0, 0)
+FUNC (1, 0, 0, 0)
+FUNC (0, 1, 0, 0)
+FUNC (1, 1, 0, 0)
+FUNC (0, 0, 1, 0)
+FUNC (1, 0, 1, 0)
+FUNC (0, 1, 1, 0)
+FUNC (1, 1, 1, 0)
+FUNC (0, 0, 0, 1)
+FUNC (1, 0, 0, 1)
+FUNC (0, 1, 0, 1)
+FUNC (1, 1, 0, 1)
+FUNC (0, 0, 1, 1)
+FUNC (1, 0, 1, 1)
+FUNC (0, 1, 1, 1)
+FUNC (1, 1, 1, 1)
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/shift.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/shift.c
new file mode 100644
index 000000000..4a0e9175c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/shift.c
@@ -0,0 +1,73 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, c, d;
+  fract16 t1, t2;
+  a = __builtin_bfin_compose_2x16 (0xe005, 0x1000);
+  b = __builtin_bfin_compose_2x16 (0x7000, 0x5000);
+  c = __builtin_bfin_compose_2x16 (0x7000, 0xc000);
+
+  d = __builtin_bfin_shl_fr2x16 (c, 2);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if ((unsigned short)t1 != 0x8000 || t2 != 0x7fff)
+    abort ();
+
+  d = __builtin_bfin_shl_fr2x16 (c, -2);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if ((unsigned short)t1 != 0xf000 || t2 != 0x1c00)
+    abort ();
+
+  d = __builtin_bfin_shl_fr2x16 (a, 2);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != 0x4000 || (unsigned short)t2 != 0x8014)
+    abort ();
+
+  d = __builtin_bfin_shl_fr2x16 (c, -4);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if ((unsigned short)t1 != 0xfc00 || t2 != 0x0700)
+    abort ();
+
+  d = __builtin_bfin_shl_fr2x16 (c, 2);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if ((unsigned short)t1 != 0x8000 || t2 != 0x7fff)
+    abort ();
+
+  d = __builtin_bfin_shl_fr2x16 (a, -2);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != 0x0400 || (unsigned short)t2 != 0xf801)
+    abort ();
+
+  /* lsh */
+  d = __builtin_bfin_lshl_fr2x16 (c, -4);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != 0x0c00 || t2 != 0x0700)
+    abort ();
+
+  d = __builtin_bfin_lshl_fr2x16 (c, 2);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != 0x0000 || t2 != -0x4000)
+    abort ();
+
+  d = __builtin_bfin_lshl_fr2x16 (a, -2);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != 0x0400 || (unsigned short)t2 != 0x3801)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-1.c
new file mode 100644
index 000000000..53ca1d7b7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-1.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcsync-anomaly -mcpu=bf537" } */
+
+#ifndef __ADSPBF537__
+#error "__ADSPBF537__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0003
+#error "__SILICON_REVISION__ is not 0x0003"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-2.c
new file mode 100644
index 000000000..c639a204e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-2.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mno-specld-anomaly -mcpu=bf537" } */
+
+#ifndef __ADSPBF537__
+#error "__ADSPBF537__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0003
+#error "__SILICON_REVISION__ is not 0x0003"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-3.c
new file mode 100644
index 000000000..3209f2348
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-3.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf537-none" } */
+
+#ifndef __ADSPBF537__
+#error "__ADSPBF537__ is not defined"
+#endif
+
+#ifdef __SILICON_REVISION__
+#error "__SILICON_REVISION__ is defined"
+#endif
+
+#ifdef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-4.c
new file mode 100644
index 000000000..62bd382b7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-4.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf537-any" } */
+
+#ifndef __ADSPBF537__
+#error "__ADSPBF537__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0xffff
+#error "__SILICON_REVISION__ is not 0xffff"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-any.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-any.c
new file mode 100644
index 000000000..62bd382b7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-any.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf537-any" } */
+
+#ifndef __ADSPBF537__
+#error "__ADSPBF537__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0xffff
+#error "__SILICON_REVISION__ is not 0xffff"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-none.c b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-none.c
new file mode 100644
index 000000000..3209f2348
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/bfin/workarounds-none.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf537-none" } */
+
+#ifndef __ADSPBF537__
+#error "__ADSPBF537__ is not defined"
+#endif
+
+#ifdef __SILICON_REVISION__
+#error "__SILICON_REVISION__ is defined"
+#endif
+
+#ifdef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/20011127-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/20011127-1.c
new file mode 100644
index 000000000..0e448f8b0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/20011127-1.c
@@ -0,0 +1,30 @@
+/* Copyright (C) 2001, 2007  Free Software Foundation.
+   by Hans-Peter Nilsson  <hp@axis.com>
+
+   Making sure that invalid asm operand modifiers don't cause an ICE.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-message "reg:SI|const_double:DF" "prune debug_rtx output" { target *-*-* } 0 } */
+
+void
+foo (void)
+{
+  /* The first case symbolizes the default case for CRIS.  */
+  asm ("\n;# %w0" : : "r" (0));	/* { dg-error "modifier" } */
+
+  /* These are explicit cases.  Luckily, a register is invalid in most of
+     them.  */
+  asm ("\n;# %b0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %v0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %P0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %p0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %z0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %H0" : : "F" (0.5));	/* { dg-error "modifier" } */
+  asm ("\n;# %e0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %m0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %A0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %D0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %T0" : : "r" (0));		/* { dg-error "modifier" } */
+  /* Add more must-not-ICE asm errors here as we find them ICEing.  */
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/asm-b-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/asm-b-1.c
new file mode 100644
index 000000000..5417c047d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/asm-b-1.c
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2" } */
+
+/* Checking that the "b" constraint is accepted, for all target variants.  */
+
+long sys_ipc (void)
+{
+  long __gu_err = -14;
+  long dummy_for_get_user_asm_64_;
+  __asm__ __volatile__( "move.d [%1+],%0\n"
+			: "=r" (__gu_err), "=b" (dummy_for_get_user_asm_64_)
+			: "0" (__gu_err));
+
+  return __gu_err;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/asmreg-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/asmreg-1.c
new file mode 100644
index 000000000..f430fafbe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/asmreg-1.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "\\\.ifnc \\\$r9-\\\$r10-\\\$r11-\\\$r12" } } */
+
+/* Sanity check for asm register operands in syscall failed for
+   cris-axis-linux-gnu due to regmove bug.
+   Hans-Peter Nilsson <hp@axis.com>.  */
+
+extern void lseek64 (int, long long, int);
+extern int *__errno_location (void);
+struct dirent64
+{
+  long long d_off;
+  unsigned short int d_reclen;
+  char d_name[256];
+};
+struct kernel_dirent64
+{   
+  long long d_off;
+  unsigned short d_reclen;
+  char d_name[256];
+};
+
+static inline int __attribute__ ((__always_inline__))
+__syscall_getdents64 (int fd, char * dirp, unsigned count)
+{
+  register unsigned long __sys_res asm ("r10");
+  register unsigned long __r10 __asm__ ("r10") = (unsigned long) fd;
+  register unsigned long __r11 __asm__ ("r11") = (unsigned long) dirp;
+  register unsigned long __r12 __asm__ ("r12") = (unsigned long) count;
+  register unsigned long __callno asm ("r9") = (220);
+  asm volatile (".ifnc %1-%0-%3-%4,$r9-$r10-$r11-$r12\n\t"
+		".err\n\t"
+		".endif\n\t"
+		"break 13"
+		: "=r" (__sys_res)
+		: "r" (__callno), "0" (__r10), "r" (__r11), "r" (__r12)
+		: "memory");
+  if (__sys_res >= (unsigned long) -4096)
+    {
+      (*__errno_location ()) = - __sys_res;
+      __sys_res = -1;
+    }
+  return __sys_res;
+}
+
+int
+__getdents64 (int fd, char *buf, unsigned nbytes)
+{   
+  struct dirent64 *dp;
+  long long last_offset = -1;
+  int retval;
+  struct kernel_dirent64 *skdp, *kdp;
+  dp = (struct dirent64 *) buf;
+  skdp = kdp = __builtin_alloca (nbytes);
+  retval = __syscall_getdents64(fd, (char *)kdp, nbytes);
+  if (retval == -1)
+    return -1;
+  while ((char *) kdp < (char *) skdp + retval)
+    {
+      if ((char *) dp > buf + nbytes)
+	{
+	  lseek64(fd, last_offset, 0);
+	  break;
+	}
+      last_offset = kdp->d_off;
+      __builtin_memcpy (dp->d_name, kdp->d_name, kdp->d_reclen - 10);
+      dp = (struct dirent64 *) ((char *) dp + sizeof (*dp));
+      kdp = (struct kernel_dirent64 *) (((char *) kdp) + kdp->d_reclen);
+    }
+
+  return (char *) dp - buf;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/biap.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/biap.c
new file mode 100644
index 000000000..1f3b4368a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/biap.c
@@ -0,0 +1,11 @@
+/* Make sure ADDI is combined and emitted successfully.
+   See also PR37939.  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "addi" } } */
+/* { dg-final { scan-assembler-not "lsl" } } */
+
+int xyzzy (int r10, int r11)
+{
+  return r11 * 4 + r10;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_bswap_v3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_bswap_v3.c
new file mode 100644
index 000000000..1230d4b59
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_bswap_v3.c
@@ -0,0 +1,12 @@
+/* Check that we don't use the swap insn for bswap by checking assembler 
+   output.  The swap instruction was added in v8.  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
+/* { dg-options "-O2 -march=v3" } */
+/* { dg-final { scan-assembler-not "\[ \t\]swapwb\[ \t\]" } } */
+
+int
+f (int a)
+{
+	return __builtin_bswap32(a);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_bswap_v8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_bswap_v8.c
new file mode 100644
index 000000000..b7a8d2684
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_bswap_v8.c
@@ -0,0 +1,12 @@
+/* Check that we use the swap insn for bswap by checking assembler
+   output.  The swap instruction was added in v8.  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
+/* { dg-options "-O2 -march=v8" } */
+/* { dg-final { scan-assembler "\[ \t\]swapwb\[ \t\]" } } */
+
+int
+f (int a)
+{
+	return __builtin_bswap32(a);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_clz_v0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_clz_v0.c
new file mode 100644
index 000000000..318402faa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_clz_v0.c
@@ -0,0 +1,12 @@
+/* Check that we don't use the lz insn for clz by checking assembler output.
+   The lz insn was implemented in CRIS v3 (ETRAX 4).  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
+/* { dg-options "-O2 -march=v0" } */
+/* { dg-final { scan-assembler-not "\[ \t\]lz\[ \t\]" } } */
+
+int
+f (int a)
+{
+	return __builtin_clz(a);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_clz_v3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_clz_v3.c
new file mode 100644
index 000000000..ecf039048
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_clz_v3.c
@@ -0,0 +1,12 @@
+/* Check that we use the lz insn for clz by checking assembler output.
+   The lz insn was implemented in CRIS v3 (ETRAX 4).  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
+/* { dg-options "-O2 -march=v3" } */
+/* { dg-final { scan-assembler "\[ \t\]lz\[ \t\]" } } */
+
+int
+f (int a)
+{
+	return __builtin_clz(a);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_ctz_v3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_ctz_v3.c
new file mode 100644
index 000000000..8971a47a0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_ctz_v3.c
@@ -0,0 +1,12 @@
+/* Check that we don't use the swap insn for ctz by checking
+   assembler output.  The swap instruction was implemented in v8.  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
+/* { dg-options "-O2 -march=v3" } */
+/* { dg-final { scan-assembler-not "\[ \t\]swapwbr\[ \t\]" } } */
+
+int
+f (int a)
+{
+	return __builtin_ctz(a);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_ctz_v8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_ctz_v8.c
new file mode 100644
index 000000000..853b1740a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/builtin_ctz_v8.c
@@ -0,0 +1,12 @@
+/* Check that we use the swap insn for ctz by checking assembler output.
+   The swap instruction was implemented in v8.  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
+/* { dg-options "-O2 -march=v8" } */
+/* { dg-final { scan-assembler "\[ \t\]swapwbr\[ \t\]" } } */
+
+int
+f (int a)
+{
+	return __builtin_ctz(a);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/cris.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/cris.exp
new file mode 100644
index 000000000..769052a28
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/cris.exp
@@ -0,0 +1,41 @@
+#   Copyright (C) 2005, 2007 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `gcc-dg.exp' driver, just a single option, no
+# looping over tests.
+
+# Exit immediately if this isn't a CRIS target.
+if { ![istarget cris-*-*] && ![istarget crisv32-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] "" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/peep2-andu1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/peep2-andu1.c
new file mode 100644
index 000000000..3b54c3295
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/peep2-andu1.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler-not "and.d " } } */
+/* { dg-final { scan-assembler-not "move.d " } } */
+/* { dg-final { scan-assembler "cLear.b" } } */
+/* { dg-final { scan-assembler "movu.b" } } */
+/* { dg-final { scan-assembler "and.b" } } */
+/* { dg-final { scan-assembler "movu.w" } } */
+/* { dg-final { scan-assembler "and.w" } } */
+/* { dg-final { scan-assembler "andq" } } */
+/* { dg-options "-O2" } */
+
+/* Test the "andu" peephole2 trivially, memory operand.  */
+
+int
+clearb (int x, int *y)
+{
+  return *y & 0xff00;
+}
+
+int
+andb (int x, int *y)
+{
+  return *y & 0x3f;
+}
+
+int
+andw (int x, int *y)
+{
+  return *y & 0xfff;
+}
+
+int
+andq (int x, int *y)
+{
+  return *y & 0xf0;
+}
+
+int
+andq2 (int x, int *y)
+{
+  return *y & 0xfff0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/peep2-andu2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/peep2-andu2.c
new file mode 100644
index 000000000..55f638cdb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/peep2-andu2.c
@@ -0,0 +1,32 @@
+/* { dg-do assemble } */
+/* { dg-final { scan-assembler "movu.w \\\$r10,\\\$" } } */
+/* { dg-final { scan-assembler "and.w 2047,\\\$" } } */
+/* { dg-final { scan-assembler-not "move.d \\\$r10,\\\$" } } */
+/* { dg-final { scan-assembler "movu.b \\\$r10,\\\$" } } */
+/* { dg-final { scan-assembler "and.b 95,\\\$" } } */
+/* { dg-final { scan-assembler "andq -2,\\\$" } } */
+/* { dg-options "-O2 -save-temps" } */
+
+/* Test the "andu" peephole2 trivially, register operand.  */
+
+unsigned int
+and_peep2_hi (unsigned int y, unsigned int *x)
+{
+  *x = y & 0x7ff;
+  return y;
+}
+
+unsigned int
+and_peep2_qi (unsigned int y, unsigned int *x)
+{
+  *x = y & 0x5f;
+  return y;
+}
+
+
+unsigned int
+and_peep2_q (unsigned int y, unsigned int *x)
+{
+  *x = y & 0xfe;
+  return y;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/peep2-xsrand.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/peep2-xsrand.c
new file mode 100644
index 000000000..df0e76886
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/peep2-xsrand.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "and.w " } } */
+/* { dg-final { scan-assembler "and.b " } } */
+/* { dg-final { scan-assembler-not "and.d" } } */
+/* { dg-options "-O2" } */
+
+/* Test the "asrandb", "asrandw", "lsrandb" and "lsrandw" peephole2:s
+   trivially.  */
+
+unsigned int
+andwlsr (unsigned int x)
+{
+  return (x >> 17) & 0x7ff;
+}
+
+unsigned int
+andblsr (unsigned int x)
+{
+  return (x >> 25) & 0x5f;
+}
+
+int
+andwasr (int x)
+{
+  return (x >> 17) & 0x7ff;
+}
+
+int
+andbasr (int x)
+{
+  return (x >> 25) & 0x5f;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/peep2-xsrand2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/peep2-xsrand2.c
new file mode 100644
index 000000000..5d6ca788d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/peep2-xsrand2.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "and.w -137," } } */
+/* { dg-final { scan-assembler "and.b -64," } } */
+/* { dg-final { scan-assembler "and.w -139," } } */
+/* { dg-final { scan-assembler "and.b -63," } } */
+/* { dg-final { scan-assembler-not "and.d" } } */
+/* { dg-options "-O2" } */
+
+/* PR target/17984.  Test-case based on
+   testsuite/gcc.dg/cris-peep2-xsrand.c.  */
+
+unsigned int
+andwlsr (unsigned int x)
+{
+  return (x >> 16) & 0xff77;
+}
+
+unsigned int
+andblsr (unsigned int x)
+{
+  return (x >> 24) & 0xc0;
+}
+
+int
+andwasr (int x)
+{
+  return (x >> 16) & 0xff75;
+}
+
+int
+andbasr (int x)
+{
+  return (x >> 24) & 0xc1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/rld-legit1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/rld-legit1.c
new file mode 100644
index 000000000..53a38af2c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/rld-legit1.c
@@ -0,0 +1,21 @@
+/* Check that we don't get unnecessary insns due to reload using more
+   insns than needed due to reloading of more locations than
+   needed.  */
+/* { dg-options -O2 } */
+/* { dg-final { scan-assembler-not "movs.w" } } */
+/* { dg-final { scan-assembler-not "move.w" } } */
+
+/* As torture/pr24750-2.c, except we need to clobber R8 for thorough
+   testing and know we can do, since we replace the frame-pointer.  */
+
+int
+f (short *a, char *y)
+{
+  __asm__ ("" : : :
+#ifndef __PIC__
+	   "r0",
+#endif
+	   "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8",
+	   "r9", "r10", "r11", "r12", "r13");
+  return y[*a];
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/rld-legit2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/rld-legit2.c
new file mode 100644
index 000000000..0add3e2b5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/rld-legit2.c
@@ -0,0 +1,16 @@
+/* A variant of rld-legit1.c only for full code coverage of the
+   initial version of cris_reload_address_legitimized.  */
+/* { dg-options -O2 } */
+
+short *
+g (short *a, char *y)
+{
+  __asm__ ("" : : :
+#ifndef __PIC__
+	   "r0",
+#endif
+	   "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8",
+	   "r9", "r10", "r11", "r12", "r13");
+  y[*a++] = 0;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/torture/cris-torture.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/torture/cris-torture.exp
new file mode 100644
index 000000000..a0b294fcd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/torture/cris-torture.exp
@@ -0,0 +1,41 @@
+#   Copyright (C) 2005, 2007 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `gcc-dg.exp' driver, looping over
+# optimization options.
+
+# Exit immediately if this isn't a CRIS target.
+if { ![istarget cris-*-*] && ![istarget crisv32-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/torture/no-pro-epi-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/torture/no-pro-epi-1.c
new file mode 100644
index 000000000..728a34c23
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/torture/no-pro-epi-1.c
@@ -0,0 +1,4 @@
+/* { dg-options -mno-prologue-epilogue } */
+void f (void)
+{
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/torture/pr24750-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/torture/pr24750-2.c
new file mode 100644
index 000000000..281fb47b7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/torture/pr24750-2.c
@@ -0,0 +1,20 @@
+/* As the invalid insn in this test got as far as to the target output
+   code and was "near enough" to output invalid assembly-code, we need
+   to pass it through the assembler as well.
+   { dg-do assemble } */
+
+int
+f (short *a, char *y)
+{
+  __asm__ ("" : : :
+#ifndef __PIC__
+	   "r0",
+#endif
+	   "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+	   /* Register R8 is frame-pointer, and we don't have a means
+	      to not clobber it for the test-runs that don't eliminate
+	      it.  But that's ok; we have enough general-register
+	      pressure to repeat the bug without that.  */
+	   "r9", "r10", "r11", "r12", "r13");
+  return y[*a];
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/cris/torture/pr34773.c b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/torture/pr34773.c
new file mode 100644
index 000000000..d3723e38f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/cris/torture/pr34773.c
@@ -0,0 +1,74 @@
+/* { dg-do run } */
+union double_union
+{
+  double d;
+  int i[2];
+};
+void _dtoa_r (double) __attribute__ ((__noinline__));
+void _vfprintf_r (double) __attribute__ ((__noinline__));
+void
+__sprint_r(int);
+void
+_vfprintf_r(double da)
+{
+ double ffp = da;
+ double value = ffp;
+ union double_union tmp;
+
+ tmp.d = value;
+
+ if ((tmp.i[1]) & ((unsigned)0x80000000L)) {
+   value = -value;
+ }
+
+ _dtoa_r (value);
+
+ if (ffp != 0)
+   __sprint_r(value == 0);
+ __asm__ ("");
+}
+
+
+double dd = -.012;
+double ff = .012;
+
+void exit (int) __attribute__ ((__noreturn__));
+void abort (void) __attribute__ ((__noreturn__));
+void *memset(void *s, int c, __SIZE_TYPE__ n);
+void _dtoa_r (double d)
+{
+  if (d != ff)
+    abort ();
+  __asm__ ("");
+}
+
+void __sprint_r (int i)
+{
+  if (i != 0)
+    abort ();
+  __asm__ ("");
+}
+
+int clearstack (void) __attribute__ ((__noinline__));
+int clearstack (void)
+{
+  char doodle[128];
+  memset (doodle, 0, sizeof doodle);
+  __asm__ volatile ("" : : "g" (doodle) : "memory");
+  return doodle[127];
+}
+
+void doit (void) __attribute__ ((__noinline__));
+void doit (void)
+{
+  _vfprintf_r (dd);
+  _vfprintf_r (ff);
+  __asm__ ("");
+}
+
+int main(void)
+{
+  clearstack ();
+  doit ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-accs-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-accs-1.c
new file mode 100644
index 000000000..cb4232b3c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-accs-1.c
@@ -0,0 +1,65 @@
+/* Check that ACCs and ACCGs are treated as global variables even if
+   media.h isn't included.  */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+void
+set ()
+{
+#define SET(X) __MWTACC (X, (X) | 0x100), __MWTACCG (X, X)
+  SET (0);
+  SET (1);
+  SET (2);
+  SET (3);
+#if defined (__CPU_FR450__)
+  SET (8);
+  SET (9);
+  SET (10);
+  SET (11);
+#elif __FRV_ACC__ > 4
+  SET (4);
+  SET (5);
+  SET (6);
+  SET (7);
+#endif
+#undef SET
+}
+
+void
+check ()
+{
+  int diff1, diff2;
+
+  diff1 = diff2 = 0;
+
+#define CHECK(X) \
+	(diff1 |= (__MRDACC (X) ^ (X | 0x100)), \
+	 diff2 |= (__MRDACCG (X) ^ X))
+  CHECK (0);
+  CHECK (1);
+  CHECK (2);
+  CHECK (3);
+#if defined (__CPU_FR450__)
+  CHECK (8);
+  CHECK (9);
+  CHECK (10);
+  CHECK (11);
+#elif __FRV_ACC__ > 4
+  CHECK (4);
+  CHECK (5);
+  CHECK (6);
+  CHECK (7);
+#endif
+#undef CHECK
+  if ((diff1 | diff2) != 0)
+    abort ();
+}
+
+int
+main ()
+{
+  set ();
+  check ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-mclracca-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-mclracca-1.c
new file mode 100644
index 000000000..28ab497ca
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-mclracca-1.c
@@ -0,0 +1,24 @@
+/* GCSE used to reuse the value of __MRDACC.  */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+void foo (int *z)
+{
+  __MWTACC (3, 1);
+  if (__MRDACC (3) != 1)
+    *z = 1;
+  __MCLRACCA ();
+  if (__MRDACC (3) != 1)
+    *z = 2;
+}
+
+int main ()
+{
+  int z = 3;
+
+  foo (&z);
+  if (z != 2)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-mdpackh-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-mdpackh-1.c
new file mode 100644
index 000000000..837423773
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-mdpackh-1.c
@@ -0,0 +1,16 @@
+/* Test the new (Fujitsu-compatible) __MDPACKH() interface.  */
+/* { dg-do run } */
+extern void exit (int);
+extern void abort (void);
+
+unsigned short x[] = { 0x8765, 0x1234, 0x2222, 0xeeee };
+
+int
+main ()
+{
+  if (__MDPACKH (x[0], x[1], x[2], x[3]) != 0x876522221234eeeeULL)
+    abort ();
+  if (__MDPACKH (0x1111, 0x8001, 0xeeee, 0x7002) != 0x1111eeee80017002ULL)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-read-write-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-read-write-1.c
new file mode 100644
index 000000000..8496a58ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-read-write-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+volatile unsigned long long x[2];
+
+int main ()
+{
+  volatile char *addr = (volatile char *) &x[0];
+
+  x[0] = ~0ULL;
+  x[1] = ~0ULL;
+  __builtin_write64 (addr, 0x1122334455667788ULL);
+  __builtin_write32 (addr + 8, 0x12345678);
+  __builtin_write16 (addr + 12, 0xaabb);
+  __builtin_write8 (addr + 14, 0xcc);
+
+  if (x[0] != 0x1122334455667788ULL
+      || x[1] != 0x12345678aabbccffULL
+      || __builtin_read8 (addr) != 0x11
+      || __builtin_read16 (addr + 2) != 0x3344
+      || __builtin_read32 (addr + 4) != 0x55667788
+      || __builtin_read64 (addr + 8) != 0x12345678aabbccffULL)
+    abort ();
+
+  __builtin_write64 (addr, 0);
+  __builtin_write32 (addr + 8, 0);
+  __builtin_write16 (addr + 12, 0);
+  __builtin_write8 (addr + 14, 0);
+  if (x[0] != 0 || x[1] != 0xff)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-global-dynamic.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-global-dynamic.c
new file mode 100644
index 000000000..2135090f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-global-dynamic.c
@@ -0,0 +1,12 @@
+/* { dg-options "-ftls-model=global-dynamic -fpic -mfdpic -mno-inline-plt" } */
+/* { dg-do compile } */
+extern __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler "call #gettlsoff.x." } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-initial-exec-pic.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-initial-exec-pic.c
new file mode 100644
index 000000000..b51e34df6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-initial-exec-pic.c
@@ -0,0 +1,12 @@
+/* { dg-options "-ftls-model=initial-exec -fpic -mfdpic" } */
+/* { dg-do compile } */
+extern __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler "ld.*#gottlsoff12" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-initial-exec.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-initial-exec.c
new file mode 100644
index 000000000..fa755a299
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-initial-exec.c
@@ -0,0 +1,12 @@
+/* { dg-options "-ftls-model=initial-exec -mfdpic" } */
+/* { dg-do compile } */
+extern __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler "ld.*#tlsoff.x.@" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic-plt-pic.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic-plt-pic.c
new file mode 100644
index 000000000..3eabe1c6b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic-plt-pic.c
@@ -0,0 +1,13 @@
+/* { dg-options "-ftls-model=local-dynamic -minline-plt -fpic -mfdpic" } */
+/* { dg-do compile } */
+static __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler "lddi.*gottlsdesc12" } } */
+/* { dg-final { scan-assembler "calll.*#gettlsoff\\(0\\)" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic-plt.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic-plt.c
new file mode 100644
index 000000000..5c2de9384
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic-plt.c
@@ -0,0 +1,12 @@
+/* { dg-options "-ftls-model=local-dynamic -minline-plt -fPIC -mfdpic" } */
+/* { dg-do compile } */
+static __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler "ldd.*tlsdesc\\(0\\)@" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic.c
new file mode 100644
index 000000000..4680a98f4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic.c
@@ -0,0 +1,13 @@
+/* { dg-options "-ftls-model=local-dynamic -fpic -mfdpic" } */
+/* { dg-do compile } */
+static __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler "gettlsoff\\(0\\)" } } */
+/* { dg-final { scan-assembler "tlsmoff12" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-local-exec-TLS.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-local-exec-TLS.c
new file mode 100644
index 000000000..83f78de4e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-local-exec-TLS.c
@@ -0,0 +1,12 @@
+/* { dg-options "-ftls-model=local-exec -mfdpic -mTLS" } */
+/* { dg-do compile } */
+static __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler "sethi.*tlsmoffhi\\(x\\)," } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-local-exec.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-local-exec.c
new file mode 100644
index 000000000..dd1b86a05
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/all-tls-local-exec.c
@@ -0,0 +1,12 @@
+/* { dg-options "-ftls-model=local-exec -mfdpic" } */
+/* { dg-do compile } */
+static __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler ".*tlsmoff12" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr400-builtins-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr400-builtins-1.c
new file mode 100644
index 000000000..85ca7cfbf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr400-builtins-1.c
@@ -0,0 +1,28 @@
+/* Test prefetch support.  */
+/* { dg-options "-mcpu=fr400" } */
+/* { dg-do run } */
+
+unsigned char global[64];
+
+int foo (unsigned int *x, int n)
+{
+  unsigned short local[16];
+
+  __data_prefetch0 (x);
+  __data_prefetch0 (&x[8]);
+  __data_prefetch0 (&x[n]);
+  __data_prefetch0 (local);
+  __data_prefetch0 (&local[16]);
+  __data_prefetch0 (&local[n]);
+  __data_prefetch0 (global);
+  __data_prefetch0 (&global[32]);
+  __data_prefetch0 (&global[n]);
+}
+
+int main ()
+{
+  unsigned int i[16];
+
+  foo (i, 2);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr400-builtins-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr400-builtins-2.c
new file mode 100644
index 000000000..66f30055e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr400-builtins-2.c
@@ -0,0 +1,10 @@
+/* Test prefetch support.  */
+/* { dg-options "-mcpu=fr400" } */
+/* { dg-do compile } */
+
+void foo (void *x)
+{
+  __data_prefetch0 (x);
+}
+
+/* { dg-final { scan-assembler "\tdcpl " } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr405-builtins-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr405-builtins-1.c
new file mode 100644
index 000000000..98e304e27
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr405-builtins-1.c
@@ -0,0 +1,39 @@
+/* Test the IACC multiply/accumulate instructions.  Also test the IACC
+   read/write functions.  */
+/* { dg-options "-mcpu=fr405" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  long long res, res1, res2, res3;
+
+  __SMU (0x12345678, 0x40004000);
+  __SMASS (0x12000000, 0x11223344);
+  __SMSSS (0x01020304, 0x54321000);
+
+  res = __IACCreadll (0);
+  res1 = 0x12345678LL * 0x40004000LL;
+  res2 = 0x12000000LL * 0x11223344LL;
+  res3 = 0x01020304LL * 0x54321000LL;
+  if (res != res1 + res2 - res3)
+    abort ();
+
+  __IACCsetll (0, 0x7ffffffffffffff0LL);
+  __SMASS (0x100, 0x100);
+  if (__IACCreadll (0) != 0x7fffffffffffffffLL)
+    abort ();
+
+  __IACCsetl (0, -0x7ffffffe);
+  __IACCsetl (1, 0);
+  __SMSSS (0x10001, 0x10000);
+  if (__IACCreadl (0) != -0x7fffffff - 1 || __IACCreadl (1) != -0x10000)
+    abort ();
+
+  __SMSSS (0x10001, 0x10000);
+  if (__IACCreadl (0) != -0x7fffffff - 1 || __IACCreadl (1) != 0)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr405-builtins-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr405-builtins-2.c
new file mode 100644
index 000000000..778547c4d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr405-builtins-2.c
@@ -0,0 +1,69 @@
+/* Test the SCUTSS instruction.  */
+/* { dg-options "-mcpu=fr405" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  struct {
+    long long value;
+    int cut_point;
+    int result;
+  } values[] = {
+    /* Non-saturating values */
+
+    { +0x0000000000001234LL, 44, +0x01234000 },
+    { ~0x0000000000001234LL, 44, ~0x01234fff },
+
+    { +0x0000011223300fffLL, 20, +0x11223301 },
+    { ~0x0000011223300fffLL, 20, ~0x11223300 },
+    { +0x0000011223300800LL, 20, +0x11223301 },
+    { ~0x0000011223300800LL, 20, ~0x11223300 },
+    { +0x00000112233007ffLL, 20, +0x11223300 },
+    { ~0x00000112233007ffLL, 20, ~0x112232ff },
+    { +0x0000011223300000LL, 20, +0x11223300 },
+    { ~0x0000011223300000LL, 20, ~0x112232ff },
+
+    { +0x1234567fffffffffLL, -4, +0x01234568 },
+    { ~0x1234567fffffffffLL, -4, ~0x01234567 },
+    { +0x1234567800000000LL, -4, +0x01234568 },
+    { ~0x1234567800000000LL, -4, ~0x01234567 },
+    { +0x12345677ffffffffLL, -4, +0x01234567 },
+    { ~0x12345677ffffffffLL, -4, ~0x01234566 },
+    { +0x1234567000000000LL, -4, +0x01234567 },
+    { ~0x1234567000000000LL, -4, ~0x01234566 },
+
+    /* Saturation tests */
+
+    { +0x4000000000000000LL, 44, +0x7fffffff },
+    { ~0x4000000000000000LL, 44, ~0x7fffffff },
+    { +0x0000000000080000LL, 44, +0x7fffffff },
+    { ~0x0000000000080000LL, 44, ~0x7fffffff },
+    { +0x000000000007ffffLL, 44, +0x7ffff000 },
+    { ~0x000000000007ffffLL, 44, ~0x7fffffff },
+    { +0x000000000007fffeLL, 44, +0x7fffe000 },
+    { ~0x000000000007fffeLL, 44, ~0x7fffefff },
+
+    { +0x4000000000000000LL, 20, +0x7fffffff },
+    { ~0x4000000000000000LL, 20, ~0x7fffffff },
+    { +0x0000080000000000LL, 20, +0x7fffffff },
+    { ~0x0000080000000000LL, 20, ~0x7fffffff },
+    { +0x000007ffffffffffLL, 20, +0x7fffffff },
+    { ~0x000007ffffffffffLL, 20, ~0x7fffffff },
+    { +0x000007fffffff000LL, 20, +0x7fffffff },
+    { ~0x000007fffffff000LL, 20, ~0x7ffffffe },
+    { +0x000007ffffffe000LL, 20, +0x7ffffffe },
+    { ~0x000007ffffffefffLL, 20, ~0x7ffffffe }
+  };
+
+  unsigned int i;
+
+  for (i = 0; i < sizeof (values) / sizeof (values[0]); i++)
+    {
+      __IACCsetll (0, values[i].value);
+      if (__SCUTSS (values[i].cut_point) != values[i].result)
+	abort ();
+    }
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr405-builtins-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr405-builtins-3.c
new file mode 100644
index 000000000..91fd96d7f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr405-builtins-3.c
@@ -0,0 +1,58 @@
+/* Test the remaining integer instructions.  */
+/* { dg-options "-mcpu=fr405" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  if (__SLASS (0x112233, 4) != 0x1122330)
+    abort ();
+
+  if (__SLASS (0x7ffff, 12) != 0x7ffff000)
+    abort ();
+
+  if (__SLASS (0x80000, 12) != 0x7fffffff)
+    abort ();
+
+  if (__SLASS (-0x7ffff, 12) != -0x7ffff000)
+    abort ();
+
+  if (__SLASS (-0x80000, 12) != -0x7fffffff - 1)
+    abort ();
+
+  if (__SLASS (-0x80001, 12) != -0x7fffffff - 1)
+    abort ();
+
+  if (__ADDSS (0x7fffffff, 1) != 0x7fffffff)
+    abort ();
+
+  if (__ADDSS (0x7ffffffd, 1) != 0x7ffffffe)
+    abort ();
+
+  if (__ADDSS (-0x7fffffff, -2) != -0x7fffffff - 1)
+    abort ();
+
+  if (__ADDSS (-0x7ffffffd, -2) != -0x7fffffff)
+    abort ();
+
+  if (__SUBSS (0x7fffffff, -1) != 0x7fffffff)
+    abort ();
+
+  if (__SUBSS (0x7ffffffd, -1) != 0x7ffffffe)
+    abort ();
+
+  if (__SUBSS (-0x7fffffff, 2) != -0x7fffffff - 1)
+    abort ();
+
+  if (__SUBSS (-0x7ffffffd, 2) != -0x7fffffff)
+    abort ();
+
+  if (__SCAN (0x12345678, 0) != 3)
+    abort ();
+
+  if (__SCAN (0x12345678, 0x24680000) != 17)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-1.c
new file mode 100644
index 000000000..cb7986ddb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-1.c
@@ -0,0 +1,27 @@
+/* Test __MQLCLRHS.  */
+/* { dg-options "-mcpu=fr450" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  struct { unsigned long long a, b, c; } entries[] = {
+    { 0x10002000e800d800ULL, 0x0800080008000800ULL, 0x10002000e800d800ULL },
+    { 0x10002000e800d800ULL, 0xf800f800f800f800ULL, 0xf000e00018002800ULL },
+    { 0x1000100010001000ULL, 0xf000f80008001000ULL, 0x0000f00010000000ULL },
+    { 0xf000f000f000f000ULL, 0xf000f80008001000ULL, 0x00001000f0000000ULL },
+    { 0x8000800080008000ULL, 0x80007fff80010000ULL, 0x000080007fff8000ULL },
+    { 0x7fff7fff7fff7fffULL, 0x80007fff80010000ULL, 0x0000000000007fffULL },
+    { 0x8001800180018001ULL, 0x80007fff80010000ULL, 0x0000000000008001ULL },
+    { 0x800080000001ffffULL, 0x0001ffff80008000ULL, 0x80007fff00000000ULL }
+  };
+
+  unsigned int i;
+
+  for (i = 0; i < sizeof (entries) / sizeof (entries[0]); i++)
+    if (__MQLCLRHS (entries[i].a, entries[i].b) != entries[i].c)
+      abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-2.c
new file mode 100644
index 000000000..663d735cf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-2.c
@@ -0,0 +1,27 @@
+/* Test __MLMTHS.  */
+/* { dg-options "-mcpu=fr450" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  struct { unsigned long long a, b, c; } entries[] = {
+    { 0x10002000e800d800ULL, 0x0800080008000800ULL, 0x08000800f800f800ULL },
+    { 0x10002000e800d800ULL, 0xf800f800f800f800ULL, 0xf800f80008000800ULL },
+    { 0x1000100010001000ULL, 0xe800f80008001800ULL, 0x1000f80008001000ULL },
+    { 0xf000f000f000f000ULL, 0xe800f80008001800ULL, 0xf0000800f800f000ULL },
+    { 0x8000800080008000ULL, 0x80007fff80010000ULL, 0x7fff80017fff0000ULL },
+    { 0x7fff7fff7fff7fffULL, 0x80007fff80010000ULL, 0x7fff7fff80010000ULL },
+    { 0x8001800180018001ULL, 0x80007fff80010000ULL, 0x800180017fff0000ULL },
+    { 0x800080000001ffffULL, 0x0001ffff80008000ULL, 0xffff00010001ffffULL }
+  };
+
+  unsigned int i;
+
+  for (i = 0; i < sizeof (entries) / sizeof (entries[0]); i++)
+    if (__MQLMTHS (entries[i].a, entries[i].b) != entries[i].c)
+      abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-3.c
new file mode 100644
index 000000000..00478a4ae
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-3.c
@@ -0,0 +1,25 @@
+/* Test __MQSLLHI.  */
+/* { dg-options "-mcpu=fr450" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  if (__MQSLLHI (0x0001000200030004ULL, 1) != 0x0002000400060008ULL)
+    abort ();
+
+  if (__MQSLLHI (0xfffffffefffcfff8ULL, 1) != 0xfffefffcfff8fff0ULL)
+    abort ();
+
+  if (__MQSLLHI (0xfffffffefffcfff8ULL, 12) != 0xf000e000c0008000ULL)
+    abort ();
+
+  if (__MQSLLHI (0x123456789abcdef0ULL, 12) != 0x40008000c0000000ULL)
+    abort ();
+
+  if (__MQSLLHI (0x123456789abcdef0ULL, 16) != 0x123456789abcdef0ULL)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-4.c
new file mode 100644
index 000000000..1eee1861a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-4.c
@@ -0,0 +1,25 @@
+/* Test __MQSRAHI.  */
+/* { dg-options "-mcpu=fr450" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  if (__MQSRAHI (0x0001000200030004ULL, 1) != 0x0000000100010002ULL)
+    abort ();
+
+  if (__MQSRAHI (0xfffffffefffcfff8ULL, 1) != 0xfffffffffffefffcULL)
+    abort ();
+
+  if (__MQSRAHI (0x8000c000e000f000ULL, 12) != 0xfff8fffcfffeffffULL)
+    abort ();
+
+  if (__MQSRAHI (0x123456789abcdef0ULL, 12) != 0x00010005fff9fffdULL)
+    abort ();
+
+  if (__MQSRAHI (0x123456789abcdef0ULL, 16) != 0x123456789abcdef0ULL)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-5.c
new file mode 100644
index 000000000..c94e8ff80
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-5.c
@@ -0,0 +1,35 @@
+/* Test that all accumulator registers are accessible.  */
+/* { dg-options "-mcpu=fr450" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+#define TEST_ACC(X) \
+  (__MWTACC (X, 0x11220000 | X), __MRDACC (X) ^ (0x11220000 | X))
+
+#define TEST_ACCG(X) \
+  (__MWTACCG (X, X), __MRDACCG (X) ^ X)
+
+#define ZERO_ACC(X) \
+  (__MRDACC (X) | __MRDACCG (X))
+
+int
+main ()
+{
+  if (TEST_ACC (0) | TEST_ACC (1) | TEST_ACC (2) | TEST_ACC (3))
+    abort ();
+  if (TEST_ACC (8) | TEST_ACC (9) | TEST_ACC (10) | TEST_ACC (11))
+    abort ();
+  if (TEST_ACCG (0) | TEST_ACCG (1) | TEST_ACCG (2) | TEST_ACCG (3))
+    abort ();
+  if (TEST_ACCG (8) | TEST_ACCG (9) | TEST_ACCG (10) | TEST_ACCG (11))
+    abort ();
+
+  __MCLRACCA ();
+  if (ZERO_ACC (0) | ZERO_ACC (1) | ZERO_ACC (2) | ZERO_ACC (3))
+    abort ();
+  if (ZERO_ACC (8) | ZERO_ACC (9) | ZERO_ACC (10) | ZERO_ACC (11))
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-6.c
new file mode 100644
index 000000000..0624eb1f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-6.c
@@ -0,0 +1,23 @@
+/* Test a situation in which an M5 instruction (mrdacc) and M4 instruction
+   (mqmulhu) can be issued together.  */
+/* { dg-options "-mcpu=fr450" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int
+main ()
+{
+  __MQMULHU (0, 0x0011002200330044ULL, 0x0002000300040001ULL);
+  __MQMULHU (8, 0x0100020003000400ULL, 0x0001000200030004ULL);
+
+  /* 0x22 + 0x66 + 0xcc + 0x44 = 0x198 */
+  /* 0x100 + 0x400 + 0x900 + 0x1000 = 0x1e00 */
+  if (__MRDACC (0) + __MRDACC (1)
+      + __MRDACC (2) + __MRDACC (3)
+      + __MRDACC (8) + __MRDACC (9)
+      + __MRDACC (10) + __MRDACC (11) != 0x1f98)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-7.c
new file mode 100644
index 000000000..dbba44a85
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-7.c
@@ -0,0 +1,24 @@
+/* Test that the code from fr450-builtins-6.c packs together an
+   M4 and M5 instruction.  */
+/* { dg-options "-O2 -mcpu=fr450" } */
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "mqmulhu.p\[^\t\]*\t*mrdacc" } } */
+extern void abort (void);
+extern void exit (int);
+
+int
+main ()
+{
+  __MQMULHU (0, 0x0011002200330044ULL, 0x0002000300040001ULL);
+  __MQMULHU (8, 0x0100020003000400ULL, 0x0001000200030004ULL);
+
+  /* 0x22 + 0x66 + 0xcc + 0x44 = 0x198 */
+  /* 0x100 + 0x400 + 0x900 + 0x1000 = 0x1e00 */
+  if (__MRDACC (0) + __MRDACC (1)
+      + __MRDACC (2) + __MRDACC (3)
+      + __MRDACC (8) + __MRDACC (9)
+      + __MRDACC (10) + __MRDACC (11) != 0x1f98)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-8.c
new file mode 100644
index 000000000..2c23f8cd8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-8.c
@@ -0,0 +1,22 @@
+/* Test a situation in which an M6 instruction (mdcutssi) and M4 instruction
+   (mqmulhu) can be issued together.  */
+/* { dg-options "-mcpu=fr450" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int
+main ()
+{
+  __MQMULHU (0, 0x0001001101111111ULL, 0x0001000200030004ULL);
+  __MQMULHU (8, 0x0002002202222222ULL, 0x0004000400040004ULL);
+  if (__MDCUTSSI (0, 8)
+      + __MDCUTSSI (2, 8)
+      + __MDCUTSSI (8, 8)
+      + __MDCUTSSI (10, 8)
+      != (0x0000000100000022ULL + 0x0000033300004444ULL
+	  + 0x0000000800000088ULL + 0x0000088800008888ULL))
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-9.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-9.c
new file mode 100644
index 000000000..5f32ba281
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr450-builtins-9.c
@@ -0,0 +1,23 @@
+/* Test a situation in which an M6 instruction (mdcutssi) and M4 instruction
+   (mqmulhu) can be issued together.  */
+/* { dg-options "-O2 -mcpu=fr450" } */
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "mqmulhu.p\[^\t\]*\t*mdcutssi" } } */
+extern void abort (void);
+extern void exit (int);
+
+int
+main ()
+{
+  __MQMULHU (0, 0x0001001101111111ULL, 0x0001000200030004ULL);
+  __MQMULHU (8, 0x0002002202222222ULL, 0x0004000400040004ULL);
+  if (__MDCUTSSI (0, 8)
+      + __MDCUTSSI (2, 8)
+      + __MDCUTSSI (8, 8)
+      + __MDCUTSSI (10, 8)
+      != (0x0000000100000022ULL + 0x0000033300004444ULL
+	  + 0x0000000800000088ULL + 0x0000088800008888ULL))
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr550-builtins-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr550-builtins-1.c
new file mode 100644
index 000000000..d728f12a4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr550-builtins-1.c
@@ -0,0 +1,42 @@
+/* Test prefetch support.  */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+unsigned char global[64];
+
+void
+foo (unsigned int *x, int n)
+{
+  unsigned short local[16];
+
+  __data_prefetch0 (x);
+  __data_prefetch0 (&x[8]);
+  __data_prefetch0 (&x[n]);
+  __data_prefetch0 (local);
+  __data_prefetch0 (&local[16]);
+  __data_prefetch0 (&local[n]);
+  __data_prefetch0 (global);
+  __data_prefetch0 (&global[32]);
+  __data_prefetch0 (&global[n]);
+
+#if __FRV_VLIW__ > 1
+  __data_prefetch (x);
+  __data_prefetch (&x[8]);
+  __data_prefetch (&x[n]);
+  __data_prefetch (local);
+  __data_prefetch (&local[16]);
+  __data_prefetch (&local[n]);
+  __data_prefetch (global);
+  __data_prefetch (&global[32]);
+  __data_prefetch (&global[n]);
+#endif
+}
+
+int main ()
+{
+  unsigned int i[16];
+
+  foo (i, 2);
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr550-builtins-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr550-builtins-2.c
new file mode 100644
index 000000000..ce39f462c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr550-builtins-2.c
@@ -0,0 +1,9 @@
+/* Test prefetch support.  */
+/* { dg-do compile } */
+
+void foo (void *x)
+{
+  __data_prefetch0 (x);
+}
+
+/* { dg-final { scan-assembler "\tdcpl " } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr550-builtins-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr550-builtins-3.c
new file mode 100644
index 000000000..b5347de74
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr550-builtins-3.c
@@ -0,0 +1,13 @@
+/* Test prefetch support.  */
+/* { dg-do compile } */
+
+#if __FRV_VLIW__ > 1
+void foo (void *x)
+{
+  __data_prefetch (x);
+}
+#else
+asm (";\tnop.p\n;\tnldub ");
+#endif
+
+/* { dg-final { scan-assembler "\tnop.p.*\tnldub " } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr550-builtins-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr550-builtins-4.c
new file mode 100644
index 000000000..801dfee20
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr550-builtins-4.c
@@ -0,0 +1,48 @@
+/* Test the __M{,D}{ADD,SUB}ACC functions.  */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int
+main ()
+{
+  __MWTACC (6, 10);
+  __MWTACC (7, 25);
+  __MADDACCS (5, 6);
+  if (__MRDACC (5) != 35)
+    abort ();
+  __MSUBACCS (4, 6);
+  if (__MRDACC (4) != -15)
+    abort ();
+  __MASACCS (4, 6);
+  if (__MRDACC (4) != 35 || __MRDACC (5) != -15)
+    abort ();
+
+  __MWTACC (0, 100);
+  __MWTACC (1, 150);
+  __MWTACC (2, 1000);
+  __MWTACC (3, 1500);
+  __MDADDACCS (2, 0);
+  if (__MRDACC (2) != 250 || __MRDACC (3) != 2500)
+    abort ();
+
+  __MWTACC (0, 100);
+  __MWTACC (1, 150);
+  __MWTACC (2, 1000);
+  __MWTACC (3, 1500);
+  __MDSUBACCS (2, 0);
+  if (__MRDACC (2) != -50 || __MRDACC (3) != -500)
+    abort ();
+
+  __MWTACC (0, 100);
+  __MWTACC (1, 150);
+  __MWTACC (2, 1000);
+  __MWTACC (3, 1500);
+  __MDASACCS (0, 0);
+  if (__MRDACC (0) != 250 || __MRDACC (1) != -50)
+    abort ();
+  if (__MRDACC (2) != 2500 || __MRDACC (3) != -500)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr550-builtins-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr550-builtins-5.c
new file mode 100644
index 000000000..ff75ea17d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/fr550-builtins-5.c
@@ -0,0 +1,25 @@
+/* Test that __MADDACC only changes the registers it's supposed to.  */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int
+main ()
+{
+  __MWTACC (0, 1);
+  __MWTACC (1, 1);
+  __MWTACC (2, 1);
+  __MWTACC (3, 1);
+  __MWTACC (4, 1);
+  __MWTACC (5, 1);
+  __MWTACC (6, 1);
+  __MWTACC (7, 1);
+  __MADDACCS (0, 2);
+  __MADDACCS (4, 6);
+  if ((__MRDACC (0) - 2)
+      | (__MRDACC (1) - 1)
+      | (__MRDACC (4) - 2)
+      | (__MRDACC (5) - 1))
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/frv/frv.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/frv.exp
new file mode 100644
index 000000000..f2c4359b4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/frv/frv.exp
@@ -0,0 +1,35 @@
+# The name of each test starts with the architecture it requires.  Tests that
+# work on all variants start with "all".
+
+if {![istarget frv-*-*]} {
+    return 0
+}
+
+load_lib gcc-dg.exp
+
+# Find out which architecture is used by default.
+set mainarch "fr500"
+foreach flag [target_info multilib_flags] {
+    regexp "^-mcpu=(.*)" $flag dummy mainarch
+    if {$flag == "-mno-pack"} {
+	# -mno-pack disables media intrinsics.
+	return 0
+    }
+}
+
+# Set $archs to "all" plus the list of architectures we can test.
+set archs [list "all" $mainarch]
+switch $mainarch {
+    fr405 { lappend archs fr400 }
+    fr450 { lappend archs fr405 fr400 }
+}
+
+# Set $files to the list of files we can test.
+set files ""
+foreach arch $archs {
+    lappend files [lsort [glob -nocomplain $srcdir/$subdir/${arch}*.c]]
+}
+
+dg-init
+gcc-dg-runtest [eval concat $files] ""
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000609-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000609-1.c
new file mode 100644
index 000000000..e094bba55
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000609-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O1 -ffast-math -march=i686" } */
+
+
+/* Sanity check for fp_jcc_* with TARGET_CMOVE.  */
+
+extern void abort (void);
+
+static int test(double a)
+{
+  if (a)
+    return 0;
+}
+
+static double zero = 0.0;
+
+int main ()
+{
+  test (zero);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000614-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000614-1.c
new file mode 100644
index 000000000..5e86f02e4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000614-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+void bar(char *p)
+{
+}
+
+static inline void foo (unsigned long base, unsigned char val)
+{
+  val ^= (1<<2);
+  bar (val & (1<<5) ? "1" : "2");
+  bar (val & (1<<4) ? "1" : "2");
+  bar (val & (1<<3) ? "1" : "2");
+  bar (val & (1<<2) ? "1" : "2");
+  bar (val & (1<<1) ? "1" : "2");
+  bar (val & (1<<0) ? "1" : "2");
+  asm volatile ("": :"a" (val), "d" (base));
+}
+
+int main (void)
+{
+  foo (23, 1);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000614-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000614-2.c
new file mode 100644
index 000000000..5b0490707
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000614-2.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+extern void exit (int);
+
+char buf[8];
+
+void bar(char *p)
+{
+}
+
+int main()
+{
+  union {
+    unsigned int val;
+    unsigned char p[4];
+  } serial;
+
+  int i;
+  serial.val = 0;
+  bar(buf);
+  for(i = 0; i < 8; i += 4)
+    {
+      serial.p [0] += buf [i + 0];
+      serial.p [1] += buf [i + 1];
+      serial.p [2] += buf [i + 2];
+      serial.p [3] += buf [i + 3];
+    }
+  if (serial.val)
+    abort();
+  exit(0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000720-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000720-1.c
new file mode 100644
index 000000000..076a22bad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000720-1.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-mpreferred-stack-boundary=2 -march=i586 -O2 -fomit-frame-pointer" } */
+
+extern void *foo(void *a, const void *b, unsigned c);
+
+extern inline void *
+bar(void *a, const void *b, unsigned c)
+{
+  int d0, d1, d2;
+  __asm__ __volatile__(
+    "" :
+    "=&c" (d0), "=&D" (d1), "=&S" (d2) :
+    "0" (c/4), "q" (c), "1" (a), "2" (b) :
+    "memory");
+  return a;
+}
+
+typedef struct {
+  unsigned char a;
+  unsigned b : 2;
+  unsigned c : 4;
+  unsigned d : 2;
+} *baz;
+
+static int
+dead(unsigned short *v, char *w, unsigned char *x, int y, int z)
+{
+  int i = 0;
+  unsigned short j = *v;
+
+  while (y > 0) {
+    ((baz)x)->a = j;
+    ((baz)x)->b = 0;
+    ((baz)x)->c = 0;
+    ((baz)x)->d = 0;
+    __builtin_constant_p(i) ? foo(x, w, i) : bar(x, w, i);
+  }
+  return z - y;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000724-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000724-1.c
new file mode 100644
index 000000000..b3be437b5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000724-1.c
@@ -0,0 +1,72 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+
+extern void abort (void);
+extern void exit (int);
+
+struct s {
+  struct { int a; } a;
+  int b;
+  struct { struct { int a; } a; struct t { struct t *a, *b; } b; } c;
+};
+
+int bar(int (*fn)(void *), void *arg, unsigned long flags)
+{
+  return 0;
+}
+
+int baz(void *x)
+{
+  return 0;
+}
+
+void do_check (struct s *) asm ("do_check") __attribute__((regparm(1)));
+
+void __attribute__((regparm(1))) do_check(struct s *x)
+{
+  if (x->a.a || x->b || x->c.a.a)
+    abort();
+  if (x->c.b.a != &x->c.b || x->c.b.b != &x->c.b)
+    abort();
+}
+
+#define NT "\n\t"
+
+asm ("\n"
+"___checkme:"
+NT	"pushl %eax; pushl %ebx; pushl %ecx; pushl %edx; pushl %esi; pushl %edi"
+
+NT	"pushl $0; pushl $0; pushl $0; pushl $0; pushl $0"
+NT	"pushl $0; pushl $0; pushl $0; pushl $0; pushl $0"
+
+NT	"movl %ecx, %eax"
+NT	"call do_check"
+
+NT	"popl %eax; popl %eax; popl %eax; popl %eax; popl %eax"
+NT	"popl %eax; popl %eax; popl %eax; popl %eax; popl %eax"
+
+NT	"popl %edi; popl %esi; popl %edx; popl %ecx; popl %ebx;	popl %eax"
+NT	"ret"
+);
+
+extern inline void do_asm(struct s * x)
+{
+  asm volatile("call ___checkme" : : "c" (x) : "memory");
+}
+
+int foo(void)
+{
+  struct s x = { { 0 }, 0, { { 0 }, { &x.c.b, &x.c.b } } };
+  bar(baz, &x, 1);
+  do_asm(&x);
+  bar(baz, &x, 1);
+  do_asm(&x);
+  return 0;
+}
+
+int main()
+{
+  foo();
+  exit(0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000807-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000807-1.c
new file mode 100644
index 000000000..efdf97b14
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000807-1.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-Os -fpic" } */
+
+#include <string.h>
+
+typedef struct
+{
+  char *a;
+  char *b;
+} *foo;
+
+void
+bar (foo x)
+{
+  char *c = x->b;
+  char *d = (void *)0;
+  unsigned int e = 0, f = 0, g;
+  while (*c != ':')
+    if (*c == '%')
+      {
+        ++c;
+        switch (*c++)
+          {
+          case 'N':
+            g = strlen (x->a);
+            if (e + g >= f) {
+		char *h = d;
+		f += 256 + g;
+		d = (char *) __builtin_alloca (f);
+		memcpy (d, h, e);
+	    };
+            memcpy (&d[e], x->a, g);
+            e += g;
+            break;
+	  }
+      }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000904-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000904-1.c
new file mode 100644
index 000000000..0fbce57e1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20000904-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O0 -fpic" } */
+
+static struct {
+  unsigned short a, b, c, d;
+} x[10];
+
+int foo(int i)
+{
+  return ((*((char *)&x[i] + i)) | (*((char *)&x[i] + i)));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20001127-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20001127-1.c
new file mode 100644
index 000000000..b62c6f979
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20001127-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+extern inline float bar (float x)
+{
+  register long double value;
+  asm volatile ("frndint" : "=t" (value) : "0" (x));
+  return value;
+}
+
+float a;
+
+float foo (float b)
+{
+  return a + bar (b);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20010520-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20010520-1.c
new file mode 100644
index 000000000..ab4ed16ce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20010520-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-w" } */
+
+void f ()
+{
+  int i __asm__ ("%eax");
+  __asm__ volatile ("" : "=a" (i));
+}
+
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20011009-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20011009-1.c
new file mode 100644
index 000000000..99173a109
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20011009-1.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  int x;
+
+  asm ("movl $26, %0 # 26 |-> reg \n\t"
+       "movl $28, %0" : "=r" (x));
+  if (x != 28)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20011029-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20011029-2.c
new file mode 100644
index 000000000..c1068de6e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20011029-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int foo (int s)
+{
+  for (;;)
+    {
+      int a[32];
+      int y, z;
+      __asm__ __volatile__ ("" : "=c" (y), "=D" (z)
+			    : "a" (0), "0" (32), "1" (a) : "memory");
+      if (({ register char r;
+	     __asm__ __volatile__ ("" : "=q" (r)
+				   : "r" (s % 32), "m" (a[s / 32])
+				   : "cc"); r; }))
+        continue;
+      else if (({ register char r;
+		  __asm__ __volatile__ ("" : "=q" (r)
+					: "r" (0), "m" (a[0])
+					: "cc"); r; }))
+        continue;
+    }
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20011107-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20011107-1.c
new file mode 100644
index 000000000..3bf84e5ba
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20011107-1.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mtune=k6" } */
+
+void
+foo (unsigned char *x, const unsigned char *y)
+{
+  int a = 6;
+  unsigned char *b;
+  for (;;)
+    {
+      unsigned char *c = x;
+
+      while (1)
+	{
+	  if (c + 2 < y)
+	    c += 3;
+	  else
+	    break;
+	}
+      b = x + a;
+      if (*c == 4 || *c == 5)
+	{
+	  unsigned char d = c[2];
+
+	  if (b[3] == 7 || b[3] == 8)
+	    {
+	      int e = b[3] == 8;
+	      if (d < b[4] * 8 && b[5 + d / 8] & (1 << (d % 8)))
+		e = !e;
+	      if (!e)
+		x[-3] = 26;
+	    }
+	}
+      else if (*c == 7 && b[3] == 8)
+	{
+	  int f;
+	  for (f = 0; f < (int) c[1]; f++)
+	    if (!(c[2 + f] == 0))
+	      break;
+	  if (f == c[1])
+	    x[-3] = 26;
+	}
+      x -= 2;
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20011119-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20011119-1.c
new file mode 100644
index 000000000..4dd657ef7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20011119-1.c
@@ -0,0 +1,82 @@
+/* Test for reload failing to eliminate from argp to sp.  */
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+
+static int ustrsize (const char *s);
+static int (*ucwidth) (int c);
+static int (*ugetxc) (const char **s);
+static int (*usetc) (char *s, int c);
+
+char *ustrzcat(char *dest, int size, const char *src)
+{
+   int pos = ustrsize(dest);
+   int c;
+
+   size -= pos + ucwidth(0);
+
+   while ((c = ugetxc(&src)) != 0) {
+      size -= ucwidth(c);
+      if (size < 0)
+         break;
+
+      pos += usetc(dest+pos, c);
+   }
+
+   usetc(dest+pos, 0);
+
+   return dest;
+}
+
+static int __attribute__((noinline))
+ustrsize (const char *s)
+{
+  return 0;
+}
+
+static int
+ucwidth_ (int c)
+{
+  return 1;
+}
+
+static int
+ugetxc_ (const char **s)
+{
+  return '\0';
+}
+
+static int
+usetc_ (char *s, int c)
+{
+  return 1;
+}
+
+int
+main()
+{
+  ucwidth = ucwidth_;
+  ugetxc = ugetxc_;
+  usetc = usetc_;
+
+  /* ??? It is impossible to explicitly modify the hard frame pointer.
+     This will run afoul of code in flow.c that declines to mark regs
+     in eliminate_regs in regs_ever_used.  Apparently, we have to wait
+     for reload to decide that it won't need a frame pointer before a
+     variable can be allocated to %ebp.
+
+     So save, restore, and clobber %ebp by hand.  */
+
+  asm ("pushl %%ebp\n\t"
+       "movl $-1, %%ebp\n\t"
+       "pushl $0\n\t"
+       "pushl $0\n\t"
+       "pushl $0\n\t"
+       "call %P0\n\t"
+       "addl $12, %%esp\n\t"
+       "popl %%ebp"
+       : : "i"(ustrzcat) : "memory" );
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020201-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020201-3.c
new file mode 100644
index 000000000..da700c192
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020201-3.c
@@ -0,0 +1,16 @@
+/* This testcase ICEd because a SFmode variable was given a MMX register
+   for which there is no movsf exists.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=i686 -mmmx -fno-strict-aliasing" } */
+
+struct A { unsigned int a, b; };
+
+void foo (struct A *x, int y, int z)
+{
+   const float d = 1.0;
+   float e = (float) y + z;
+
+   x->a = *(unsigned int *) &d;
+   x->b = *(unsigned int *) &e;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020218-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020218-1.c
new file mode 100644
index 000000000..13a835ed0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020218-1.c
@@ -0,0 +1,35 @@
+/* Verify that X86-64 only SSE registers aren't restored on IA-32.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-final { scan-assembler-not "xmm8" } } */
+
+extern void abort (void);
+extern void exit (int);
+
+void *bar (void *p, void *q)
+{
+  if (p != (void *) 26 || q != (void *) 35)
+    abort ();
+  return (void *) 76;
+}
+
+void *foo (void **args)
+{
+  void *argcookie = &args[1];
+
+  __builtin_return (__builtin_apply (args[0], &argcookie,
+				     2 * sizeof (void *)));
+}
+
+int main (void)
+{
+  void *args[3];
+
+  args[0] = (void *) bar;
+  args[1] = (void *) 26;
+  args[2] = (void *) 35;
+  if (foo (args) != (void *) 76)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020224-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020224-1.c
new file mode 100644
index 000000000..2905719fa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020224-1.c
@@ -0,0 +1,41 @@
+/* PR target/5755
+   This testcase failed because the caller of a function returning struct
+   expected the callee to pop up the hidden return structure pointer,
+   while callee was actually not poping it up (as the hidden argument
+   was passed in register).  */
+/* { dg-do run } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+
+extern void abort (void);
+extern void exit (int);
+
+typedef struct {
+   int a1, a2;
+} A;
+
+A a;
+
+A __attribute__ ((regparm (2)))
+foo (int x)
+{
+  return a;
+}
+
+int __attribute__ ((regparm (2)))
+bar (int x)
+{
+  int r = foo(0).a2;
+  return r;
+}
+
+int
+main ()
+{
+  int f;
+  a.a1 = 530;
+  a.a2 = 980;
+  f = bar (0);
+  if (f != 980)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020426-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020426-1.c
new file mode 100644
index 000000000..57690f1d3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020426-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-msoft-float -mfp-ret-in-387" } */
+
+void f() {
+  __builtin_apply(0, 0, 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020523.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020523.c
new file mode 100644
index 000000000..7c3490f78
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020523.c
@@ -0,0 +1,40 @@
+/* PR target/6753
+   This testcase was miscompiled because sse_mov?fcc_const0*
+   patterns were missing earlyclobber.  */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -msse -mfpmath=sse -ffast-math" } */
+
+#include "sse-check.h"
+
+float one = 1.f;
+
+void bar (float f)
+{
+  if (__builtin_memcmp (&one, &f, sizeof (float)))
+    abort ();
+}
+
+float foo (void)
+{
+  return 1.f;
+}
+
+typedef struct
+{
+  float t;
+} T;
+
+static void
+sse_test (void)
+{
+  int i;
+  T x[1];
+
+  for (i = 0; i < 1; i++)
+    {
+      x[i].t = foo ();
+      x[i].t = 0.f > x[i].t ? 0.f : x[i].t;
+      bar (x[i].t);
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020531-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020531-1.c
new file mode 100644
index 000000000..cd7cac347
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020531-1.c
@@ -0,0 +1,21 @@
+/* PR optimization/6842
+   This testcase caused ICE when trying to optimize V8QI subreg of VOIDmode
+   CONST_DOUBLE.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmmx" } */
+
+typedef char __v8qi __attribute__ ((vector_size (8)));
+extern void abort (void);
+extern void exit (int);
+
+void foo (void)
+{
+  unsigned long long a = 0x0102030405060708LL;
+  unsigned long long b = 0x1020304050607080LL;
+  unsigned long long c;
+
+  c = (unsigned long long) __builtin_ia32_paddusb ((__v8qi) a, (__v8qi) b);
+  __builtin_ia32_emms ();
+  if (c != 0x1122334455667788LL)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020616-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020616-1.c
new file mode 100644
index 000000000..5641826b4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020616-1.c
@@ -0,0 +1,35 @@
+/* PR opt/6722 */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#if !__PIC__
+register int k asm("%ebx");
+#elif __amd64
+register int k asm("%r12");
+#else
+register int k asm("%esi");
+#endif
+
+void __attribute__((noinline))
+foo()
+{
+  k = 1;
+}
+
+void test()
+{
+  int i;
+  for (i = 0; i < 10; i += k)
+    {
+      k = 0;
+      foo();
+    }
+}
+
+int main()
+{
+  int old = k;
+  test();
+  k = old;
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020729-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020729-1.c
new file mode 100644
index 000000000..d4ef9bfcd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20020729-1.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=k6" } */
+
+static inline void *
+baz (void *s, unsigned long c, unsigned int count)
+{
+  int d0, d1;
+  __asm__ __volatile__ (""
+			: "=&c" (d0), "=&D" (d1)
+			:"a" (c), "q" (count), "0" (count / 4), "1" ((long) s)
+			:"memory");
+  return s;
+}
+
+struct A
+{
+  unsigned long *a;
+};
+
+inline static void *
+bar (struct A *x, int y)
+{
+  char *ptr;
+
+  ptr = (void *) x->a[y >> 12];
+  ptr += y % (1UL << 12);
+  return (void *) ptr;
+}
+
+int
+foo (struct A *x, unsigned int *y, int z, int u)
+{
+  int a, b, c, d, e;
+
+  z += *y;
+  c = z + u;
+  a = (z >> 12) + 1;
+  do
+    {
+      b = (a << 12);
+      d = b - z;
+      e = c - z;
+      if (e < d)
+	d = e;
+      baz (bar (x, z), 0, d);
+      z = b;
+      a++;
+    }
+  while (z < c);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20030217-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20030217-1.c
new file mode 100644
index 000000000..f19fd27fe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20030217-1.c
@@ -0,0 +1,18 @@
+/* Test whether denormal floating point constants in hexadecimal notation
+   are parsed correctly.  */
+/* { dg-do run } */
+/* { dg-options "-std=c99" } */
+
+long double d = 0x0.0000003ffffffff00000p-16357L;
+long double e = 0x0.0000003ffffffff00000p-16356L;
+
+extern void abort (void);
+extern void exit (int);
+
+int
+main (void)
+{
+  if (d != e / 2.0)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20030926-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20030926-1.c
new file mode 100644
index 000000000..0425f2456
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20030926-1.c
@@ -0,0 +1,18 @@
+/* PR optimization/11741  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -minline-all-stringops" } */
+/* { dg-options "-O2 -minline-all-stringops -march=pentium4" { target ilp32 } } */
+
+extern void *memcpy (void *, const void *, __SIZE_TYPE__);
+extern __SIZE_TYPE__ strlen (const char *);
+
+void
+foo (char *p)
+{
+  for (;;)
+    {
+      memcpy (p, p + 1, strlen (p));
+      p++;
+    }
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20040112-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20040112-1.c
new file mode 100644
index 000000000..168fd2f0b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20040112-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "testb" } } */
+ftn (char *sp)
+{
+  char status;
+
+  while (1)
+    {
+      *sp = 0xE8;
+      status = *(volatile char *) sp;
+      if (status & 0x80)
+	break;
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20050113-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20050113-1.c
new file mode 100644
index 000000000..44deb30cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20050113-1.c
@@ -0,0 +1,6 @@
+/* PR middle-end/19164 */
+/* { dg-do compile } */
+/* { dg-options "-mmmx" } */
+
+typedef short int V __attribute__ ((vector_size (8)));
+static V v = (V) 0x00FF00FF00FF00FFLL;
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060125-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060125-1.c
new file mode 100644
index 000000000..f445b7e99
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060125-1.c
@@ -0,0 +1,30 @@
+/* PR rtl-optimization/25703 */
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mtune=i486" } */
+
+extern void abort (void);
+
+struct a
+{
+        int a;
+        char b,c,d,e;
+};
+
+__attribute__ ((noinline))
+__attribute__ ((regparm(1))) t(struct a a)
+{
+        if (a.a!=1 || a.b!=1 || a.c!=1)
+                        abort();
+}
+
+int main()
+{
+        struct a a;
+        a.c=1;
+        a.a=1;
+        a.b=1;
+        t(a);
+        return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060125-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060125-2.c
new file mode 100644
index 000000000..55ef83955
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060125-2.c
@@ -0,0 +1,30 @@
+/* PR rtl-optimization/25703 */
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mtune=pentiumpro" } */
+
+extern void abort (void);
+
+struct a
+{
+        int a;
+        char b,c,d,e;
+};
+
+__attribute__ ((noinline))
+__attribute__ ((regparm(1))) t(struct a a)
+{
+        if (a.a!=1 || a.b!=1 || a.c!=1)
+                        abort();
+}
+
+int main()
+{
+        struct a a;
+        a.c=1;
+        a.a=1;
+        a.b=1;
+        t(a);
+        return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060218-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060218-1.c
new file mode 100644
index 000000000..b94cbd8c9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060218-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+
+void
+foo (void)
+{
+  register int cc __asm ("cc"); /* { dg-error "invalid register name" } */
+  __asm ("" : : "r" (cc) : "cc");
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060512-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060512-1.c
new file mode 100644
index 000000000..8109f94b7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060512-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-std=gnu99 -msse2 -mpreferred-stack-boundary=4" } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+__m128i __attribute__ ((__noinline__))
+vector_using_function ()
+{
+  volatile __m128i vx;	/* We want to force a vector-aligned store into the stack.  */
+  vx = _mm_xor_si128 (vx, vx);
+  return vx;
+}
+int __attribute__ ((__noinline__, __force_align_arg_pointer__))
+self_aligning_function (int x, int y)
+{
+  __m128i ignored = vector_using_function ();
+  return (x + y);
+}
+int g_1 = 20;
+int g_2 = 22;
+
+static void
+sse2_test (void)
+{
+  int result;
+  asm ("pushl %esi");		/* Disalign runtime stack.  */
+  result = self_aligning_function (g_1, g_2);
+  if (result != 42)
+    abort ();
+  asm ("popl %esi");
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060512-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060512-2.c
new file mode 100644
index 000000000..fe1af5635
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060512-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-std=gnu99 -mpreferred-stack-boundary=4" } */
+int
+outer_function (int x, int y)
+{
+  int __attribute__ ((__noinline__, __force_align_arg_pointer__))
+  nested_function (int x, int y)
+    {
+      return (x + y);
+    }
+  return (3 + nested_function (x, y));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060512-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060512-3.c
new file mode 100644
index 000000000..847f0eb6d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060512-3.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-std=gnu99 -msse2 -mstackrealign -mpreferred-stack-boundary=4" } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+__m128i __attribute__ ((__noinline__))
+vector_using_function ()
+{
+  volatile __m128i vx;	/* We want to force a vector-aligned store into the stack.  */
+  vx = _mm_xor_si128 (vx, vx);
+  return vx;
+}
+int __attribute__ ((__noinline__))
+self_aligning_function (int x, int y)
+{
+  __m128i ignored = vector_using_function ();
+  return (x + y);
+}
+int g_1 = 20;
+int g_2 = 22;
+
+static void
+sse2_test (void)
+{
+  int result;
+  asm ("pushl %esi");		/* Disalign runtime stack.  */
+  result = self_aligning_function (g_1, g_2);
+  if (result != 42)
+    abort ();
+  asm ("popl %esi");
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060512-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060512-4.c
new file mode 100644
index 000000000..ee7b8a4ad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060512-4.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-mstackrealign -mpreferred-stack-boundary=4" } */
+int
+outer_function (int x, int y)
+{
+  int __attribute__ ((__noinline__))
+  nested_function (int x, int y)
+    {
+      return (x + y);
+    }
+  return (3 + nested_function (x, y));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060821-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060821-1.c
new file mode 100644
index 000000000..56e980fdd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20060821-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse3 -S" } */
+/* { dg-final { scan-assembler-not "%mm" } } */
+/* PR 28825 */
+#include <pmmintrin.h>
+__m128 ggg(float* m)
+{
+  return (__m128) {m[0], m[5], m[10], m[10]};
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20080723-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20080723-1.c
new file mode 100644
index 000000000..a2ed5bf86
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/20080723-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+extern void exit (int);
+
+static inline __attribute__((always_inline))
+void
+prefetch (void *x)
+{
+  asm volatile("prefetcht0 %0" : : "m" (*(unsigned long *)x));
+}
+
+struct hlist_head
+{
+  struct hlist_node *first;
+};
+
+struct hlist_node
+{
+  struct hlist_node *next;
+  unsigned long i_ino;
+};
+
+struct hlist_node * find_inode_fast(struct hlist_head *head, unsigned long ino)
+{
+  struct hlist_node *node;
+
+  for (node = head->first;
+       node && (prefetch (node->next), 1);
+       node = node->next)
+    {
+      if (node->i_ino == ino)
+	break;
+    }
+  return node ? node : 0;
+}
+
+struct hlist_node g2;
+struct hlist_node g1 = { &g2 };
+struct hlist_head h = { &g1 };
+
+int
+main()
+{
+  if (find_inode_fast (&h, 1) != 0)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-1.c
new file mode 100644
index 000000000..2b3ca0b06
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-1.c
@@ -0,0 +1,21 @@
+/* Verify that -mno-fancy-math-387 works.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O -ffast-math -mfpmath=387 -mno-fancy-math-387 -march=i386" } */
+/* { dg-final { scan-assembler "call\t(.*)sin" } } */
+/* { dg-final { scan-assembler "call\t(.*)cos" } } */
+/* { dg-final { scan-assembler "call\t(.*)sqrt" } } */
+/* { dg-final { scan-assembler "call\t(.*)atan2" } } */
+/* { dg-final { scan-assembler "call\t(.*)log" } } */
+/* { dg-final { scan-assembler "call\t(.*)exp" } } */
+/* { dg-final { scan-assembler "call\t(.*)tan" } } */
+/* { dg-final { scan-assembler "call\t(.*)fmod" } } */
+
+double f1(double x) { return __builtin_sin(x); }
+double f2(double x) { return __builtin_cos(x); }
+double f3(double x) { return __builtin_sqrt(x); }
+double f4(double x, double y) { return __builtin_atan2(x,y); }
+double f5(double x) { return __builtin_log(x); }
+double f6(double x) { return __builtin_exp(x); }
+double f7(double x) { return __builtin_tan(x); }
+double f8(double x, double y) { return __builtin_fmod(x,y); }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-10.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-10.c
new file mode 100644
index 000000000..565f0196e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-10.c
@@ -0,0 +1,20 @@
+/* PR tree-optimization/24964 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfpmath=387" } */
+
+double fabs(double x);
+
+double test1(double x)
+{
+  double t = fabs(x);
+  return t*t;
+}
+
+double test2(double x)
+{
+  double t = -x;
+  return t*t;
+}
+
+/* { dg-final { scan-assembler-not "fchs" } } */
+/* { dg-final { scan-assembler-not "fabs" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-11.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-11.c
new file mode 100644
index 000000000..03020f64f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-11.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfpmath=387" } */
+
+double foo(double x, double y)
+{
+  double t = -x * y;
+  return -t;
+}
+
+/* { dg-final { scan-assembler-not "fchs" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-12.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-12.c
new file mode 100644
index 000000000..6b3ce2405
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-12.c
@@ -0,0 +1,17 @@
+/* PR target/26915 */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O" } */
+
+double testm0(void)
+{
+	return -0.0;
+}
+
+double testm1(void)
+{
+	return -1.0;
+}
+
+/* { dg-final { scan-assembler "fldz" } } */
+/* { dg-final { scan-assembler "fld1" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-2.c
new file mode 100644
index 000000000..5a317efea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-2.c
@@ -0,0 +1,21 @@
+/* Verify that -march overrides -mno-fancy-math-387.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O -ffast-math -mfpmath=387 -march=i686 -mno-fancy-math-387" } */
+/* { dg-final { scan-assembler "fsin" } } */
+/* { dg-final { scan-assembler "fcos" } } */
+/* { dg-final { scan-assembler "fsqrt" } } */
+/* { dg-final { scan-assembler "fpatan" } } */
+/* { dg-final { scan-assembler "fyl2x" } } */
+/* { dg-final { scan-assembler "f2xm1" } } */
+/* { dg-final { scan-assembler "fptan" } } */
+/* { dg-final { scan-assembler "fprem" } } */
+
+double f1(double x) { return __builtin_sin(x); }
+double f2(double x) { return __builtin_cos(x); }
+double f3(double x) { return __builtin_sqrt(x); }
+double f4(double x, double y) { return __builtin_atan2(x,y); }
+double f5(double x) { return __builtin_log(x); }
+double f6(double x) { return __builtin_exp(x); }
+double f7(double x) { return __builtin_tan(x); }
+double f8(double x, double y) { return __builtin_fmod(x,y); }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-3.c
new file mode 100644
index 000000000..ce11faa8f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-3.c
@@ -0,0 +1,11 @@
+/* Verify that 387 mathematical constants are recognized.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=i686" } */
+/* { dg-final { scan-assembler "fldpi" } } */
+
+long double add_pi(long double x)
+{
+  return x + 3.1415926535897932385128089594061862044L;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-4.c
new file mode 100644
index 000000000..5617636da
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=i686" } */
+/* { dg-final { scan-assembler "fldpi" } } */
+
+long double atanl (long double);
+
+long double pi()
+{
+  return 4.0 * atanl (1.0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-5.c
new file mode 100644
index 000000000..0a0500817
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-5.c
@@ -0,0 +1,11 @@
+/* Verify that -mno-fancy-math-387 works.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O -ffast-math -mfpmath=387 -mno-fancy-math-387 -march=i386" } */
+/* { dg-final { scan-assembler "call\t(.*)atan" } } */
+/* { dg-final { scan-assembler "call\t(.*)log1p" } } */
+/* { dg-final { scan-assembler "call\t(.*)drem" } } */
+
+double f1(double x) { return __builtin_atan(x); }
+double f2(double x) { return __builtin_log1p(x); }
+double f3(double x, double y) { return __builtin_drem(x,y); }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-6.c
new file mode 100644
index 000000000..bfef46ae5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-6.c
@@ -0,0 +1,11 @@
+/* Verify that -march overrides -mno-fancy-math-387.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O -ffast-math -mfpmath=387 -march=i686 -mno-fancy-math-387" } */
+/* { dg-final { scan-assembler "fpatan" } } */
+/* { dg-final { scan-assembler "fyl2xp1" } } */
+/* { dg-final { scan-assembler "fprem1" } } */
+
+double f1(double x) { return __builtin_atan(x); }
+double f2(double x) { return __builtin_log1p(x); }
+double f3(double x, double y) { return __builtin_drem(x,y); }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-7.c
new file mode 100644
index 000000000..61c82c95e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-7.c
@@ -0,0 +1,14 @@
+/* Verify that 387 fsincos instruction is generated.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O -ffast-math -march=i686" } */
+/* { dg-final { scan-assembler "fsincos" } } */
+
+extern double sin (double);
+extern double cos (double);
+
+double f1(double x)
+{
+  return sin(x) + cos (x);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-8.c
new file mode 100644
index 000000000..3293f560c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-8.c
@@ -0,0 +1,16 @@
+/* Verify that 387 fptan instruction is generated. Also check that
+   inherent load of 1.0 is used in further calculations.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -ffast-math -march=i686" } */
+/* { dg-final { scan-assembler "fptan" } } */
+/* { dg-final { scan-assembler-not "fld1" } } */
+
+extern double tan (double);
+
+double f1(double x)
+{
+  return 1.0 / tan(x);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-9.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-9.c
new file mode 100644
index 000000000..9d126aff8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/387-9.c
@@ -0,0 +1,36 @@
+/* Verify that 387 fsincos instruction is generated.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O -funsafe-math-optimizations -march=i686" } */
+
+extern double sin (double);
+extern double cos (double);
+extern void sincos (double, double *, double *);
+
+double f1(double x)
+{
+  double s, c;
+  sincos (x, &s, &c);
+  return s + c;
+}
+
+double f2(double x)
+{
+  double s, c, tmp;
+  sincos (x, &s, &tmp);
+  c = cos (x);
+  return s + c;
+}
+
+double f3(double x)
+{
+  double s, c, tmp;
+  sincos (x, &tmp, &c);
+  s = sin (x);
+  return s + c;
+}
+
+/* { dg-final { scan-assembler "fsincos" } } */
+/* { dg-final { scan-assembler-not "fsin " } } */
+/* { dg-final { scan-assembler-not "fcos" } } */
+/* { dg-final { scan-assembler-not "call" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/3dnow-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/3dnow-1.c
new file mode 100644
index 000000000..de5a2c3f9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/3dnow-1.c
@@ -0,0 +1,12 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -m3dnow" } */
+
+/* Test that the intrinsics compile with optimization.  All of them are
+   defined as inline functions in mmintrin.h that reference the proper
+   builtin functions.  Defining away "extern" and "__inline" results in
+   all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+#include <mm3dnow.h>
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/3dnow-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/3dnow-2.c
new file mode 100644
index 000000000..4b4d74722
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/3dnow-2.c
@@ -0,0 +1,12 @@
+/* { dg-do assemble } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -m3dnow" } */
+
+/* Test that the intrinsics compile without optimization.  All of them are
+   defined as inline functions in mmintrin.h that reference the proper
+   builtin functions.  Defining away "extern" and "__inline" results in
+   all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+#include <mm3dnow.h>
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/3dnowA-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/3dnowA-1.c
new file mode 100644
index 000000000..6d4f32532
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/3dnowA-1.c
@@ -0,0 +1,12 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow" } */
+
+/* Test that the intrinsics compile with optimization.  All of them are
+   defined as inline functions in mmintrin.h that reference the proper
+   builtin functions.  Defining away "extern" and "__inline" results in
+   all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+#include <mm3dnow.h>
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/3dnowA-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/3dnowA-2.c
new file mode 100644
index 000000000..0a30d61c9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/3dnowA-2.c
@@ -0,0 +1,12 @@
+/* { dg-do assemble } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow" } */
+
+/* Test that the intrinsics compile without optimization.  All of them are
+   defined as inline functions in mmintrin.h that reference the proper
+   builtin functions.  Defining away "extern" and "__inline" results in
+   all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+#include <mm3dnow.h>
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980211-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980211-1.c
new file mode 100644
index 000000000..ad6312b37
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980211-1.c
@@ -0,0 +1,29 @@
+/* Test long double on x86 and x86-64. */
+
+/* { dg-do run } */
+/* { dg-options -O2 } */
+
+extern void abort (void);
+
+__inline int
+__signbitl0 (long double __x)
+{
+  union { long double __l; int __i[3]; } __u = { __l: __x };
+
+  return (__u.__i[2] & 0x8000) != 0;
+}
+
+void
+foo (long double x, long double y)
+{
+  long double z = x / y;
+  if (__signbitl0 (x) && __signbitl0 (z))
+    abort ();
+}
+
+int main()
+{
+  if (sizeof (long double) > sizeof (double))
+    foo (-0.0, -1.0);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980226-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980226-1.c
new file mode 100644
index 000000000..d5587c71b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980226-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options -O2 } */
+
+extern int printf (const char *, ...);
+extern double bar (double);
+
+int
+baz (double d)
+{
+  double e = bar (d);
+  asm volatile ("" : : : "st");
+  return printf ("%lg\n", e);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980312-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980312-1.c
new file mode 100644
index 000000000..72cdd5e3f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980312-1.c
@@ -0,0 +1,25 @@
+/* { dg-do link } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=pentiumpro" } */
+
+extern __inline  double
+__expm1 (double __x)
+{
+  double __temp;
+  __temp = 1.0;
+  return __temp;
+}
+extern __inline  double
+__sgn1 (double __x)
+{
+  return __x >= 0.0 ? 1.0 : -1.0;
+}
+double
+tanh (double __x)
+{
+  return  __expm1 (__x) * __sgn1 (-__x);
+}
+main ()
+{
+  return tanh (3.45) != 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980313-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980313-1.c
new file mode 100644
index 000000000..3b5263cd5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980313-1.c
@@ -0,0 +1,26 @@
+/* { dg-do link } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=pentiumpro" } */
+
+extern __inline  double
+__expm1 (double __x)
+{
+  double __temp;
+  __temp -= 1.0;
+  return __temp;
+}
+extern __inline  double
+__sgn1 (double __x)
+{
+  return __x >= 0.0 ? 1.0 : -1.0;
+}
+double
+tanh (double __x)
+{
+  register double __exm1 = __expm1 (__x);
+  return __exm1 / (__exm1 + 2.0) * __sgn1 (-__x);
+}
+main ()
+{
+  return tanh (3.45) != 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980414-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980414-1.c
new file mode 100644
index 000000000..6a2130a59
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980414-1.c
@@ -0,0 +1,78 @@
+/* Test double on x86. */
+
+/* { dg-do run } */
+/* { dg-options -O2 } */
+
+extern void abort (void);
+
+static __inline  double
+mypow (double __x, double __y)
+{
+  register double __value, __exponent;
+  long __p = (long) __y;
+  if (__y == (double) __p)
+    {
+      double __r = 1.0;
+      if (__p == 0)
+	return 1.0;
+      if (__p < 0)
+	{
+	  __p = -__p;
+	  __x = 1.0 / __x;
+	}
+      while (1)
+	{
+	  if (__p & 1)
+	    __r *= __x;
+	  __p >>= 1;
+	  if (__p == 0)
+	    return __r;
+	  __x *= __x;
+	}
+    }
+  __asm __volatile__
+    ("fmul	%%st(1),%%st\n\t"	/* y * log2(x) */
+     "fst	%%st(1)\n\t"
+     "frndint\n\t"			/* int(y * log2(x)) */
+     "fxch  %%st(1)\n\t"
+     "fsub	%%st(1),%%st\n\t"	/* fract(y * log2(x)) */
+     "f2xm1\n\t"			/* 2^(fract(y * log2(x))) - 1 */
+     : "=t" (__value), "=u" (__exponent) :  "0" (__x), "1" (__y));
+  __value += 1.0;
+  __asm __volatile__
+    ("fscale"
+     : "=t" (__value) : "0" (__value), "u" (__exponent));
+  return __value;
+}
+
+const double E1 = 2.71828182845904523536028747135;
+
+double fact (double x)
+{
+  double corr;
+  corr = 1.0;
+  return corr * mypow(x/E1, x);
+}
+
+int main ()
+{
+  double y, z;
+
+  y = fact (46.2);
+  z = mypow (46.2/E1, 46.2);
+
+#if 0
+  printf ("%26.19e, %26.19e\n", y, z);
+#endif
+
+  if (y > z)
+    y -= z;
+  else
+    y = z - y;
+
+  y /= z;
+  if (y > 0.1)
+    abort ();
+ 
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980520-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980520-1.c
new file mode 100644
index 000000000..f4393307c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980520-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options -O2 } */
+
+int bug(void)
+{
+        unsigned long a, b;
+   
+        __asm__(""
+                : "=d" (a)
+                :
+                : "memory");
+        __asm__ __volatile__(""
+                             :
+                             : "g" (b)
+                             : "memory");
+        return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980709-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980709-1.c
new file mode 100644
index 000000000..595b7cbaa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/980709-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options -O2 } */
+
+extern __inline__ int test_and_set_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+	__asm__ __volatile__( "" 
+		"btsl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit),"=m" (addr)
+		:"ir" (nr));
+	return oldbit;
+}
+struct buffer_head {
+	unsigned long b_state;		 
+};
+extern void lock_buffer(struct buffer_head * bh)
+{
+	while (test_and_set_bit(2 , &bh->b_state))
+		__wait_on_buffer(bh);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990117-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990117-1.c
new file mode 100644
index 000000000..3a40e7fdf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990117-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=pentiumpro" } */
+
+extern __inline  double
+fabs (double __x)
+{
+  register double __value;
+  __asm __volatile__
+    ("fabs"
+     : "=t" (__value) : "0" (__x));
+  return __value;
+}
+int
+foo ()
+{
+  int i, j, k;
+  double x = 0, y = ((i == j) ? 1 : 0);
+  for (i = 0; i < 10; i++)
+    ;
+  fabs (x - y);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990130-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990130-1.c
new file mode 100644
index 000000000..b2754fb08
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990130-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options -O0 } */
+
+typedef 	 int SItype	__attribute__ ((mode (SI)));
+typedef		 int DItype	__attribute__ ((mode (DI)));
+typedef unsigned int USItype	__attribute__ ((mode (SI)));
+  struct DIstruct {SItype low, high;};
+typedef union
+{
+  struct DIstruct s;
+  DItype ll;
+} DIunion;
+DItype
+__muldi3 (DItype u, DItype v)
+{
+  DIunion w;
+  DIunion uu, vv;
+  uu.ll = u,
+  vv.ll = v;
+  w.ll = ({DIunion __w;	__asm__ ("mull %3"	: "=a" ((USItype) (  __w.s.low )),	"=d" ((USItype) ( __w.s.high ))	: "%0" ((USItype) (   uu.s.low  )),	"rm" ((USItype) (    vv.s.low  ))) ;	__w.ll; }) ;
+  w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
+	       + (USItype) uu.s.high * (USItype) vv.s.low);
+  return w.ll;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990213-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990213-2.c
new file mode 100644
index 000000000..21392bfca
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990213-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-fPIC" } */
+
+struct normal_encoding {};
+struct unknown_encoding {};
+static const struct normal_encoding latin1_encoding = {};
+
+struct encoding*
+XmlInitUnknownEncoding(void *mem)
+{
+  int i;
+  struct unknown_encoding *e = mem;
+  for (i = 0; i < sizeof(struct normal_encoding); i++)
+    ((char *)mem)[i] = ((char *)&latin1_encoding)[i];
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990214-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990214-1.c
new file mode 100644
index 000000000..3c203e9f7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990214-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-fPIC" } */
+
+typedef int int64_t __attribute__ ((__mode__ (  __DI__ ))) ;
+unsigned *
+bar (int64_t which)
+{
+	switch (which & 15 ) {
+	case 0 :
+		break;
+	case 1 :
+	case 5 :
+	case 2 : ;
+	}
+
+	return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990424-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990424-1.c
new file mode 100644
index 000000000..95628e12f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990424-1.c
@@ -0,0 +1,30 @@
+/* Test that stack alignment is preserved with pending_stack_adjust
+   with stdcall functions.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options -mpreferred-stack-boundary=4 } */
+
+void __attribute__((stdcall)) foo(int a, int b, int c);
+
+extern void abort (void);
+extern void exit (int);
+
+int
+main ()
+{
+  foo(1, 2, 3);
+  foo(1, 2, 3);
+  exit (0);
+}
+
+void __attribute__((stdcall))
+foo(int a, int b, int c)
+{
+  static int last_align = -1;
+  int dummy, align = (int)&dummy & 15;
+  if (last_align < 0)
+    last_align = align;
+  else if (align != last_align)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990524-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990524-1.c
new file mode 100644
index 000000000..7d8205cd0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/990524-1.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=pentiumpro" } */
+
+typedef struct t_anim_info {
+   char        *new_filename;
+   long         first_frame_nr; 
+} t_anim_info;
+static int
+p_frames_to_multilayer(t_anim_info *ainfo_ptr,
+                      long range_from, long range_to)
+{
+  long    l_cur_frame_nr;
+  long    l_step, l_begin, l_end;
+  int  l_tmp_image_id;
+  int  l_new_image_id;
+  if(range_from > range_to)
+  {
+    l_step  = -1;      
+    if(range_to < ainfo_ptr->first_frame_nr)
+    { l_begin = ainfo_ptr->first_frame_nr; 
+     }
+  }
+  else
+  {
+    l_step  = 1;       
+  }
+  l_cur_frame_nr = l_begin;
+  while(1)
+  {
+    if(ainfo_ptr->new_filename == ((void *)0) )
+    if(l_tmp_image_id < 0)
+      gimp_image_delete(l_tmp_image_id);
+    if(l_cur_frame_nr == l_end)
+       break;
+    l_cur_frame_nr += l_step;
+  }
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/991129-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/991129-1.c
new file mode 100644
index 000000000..d0d58e8f9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/991129-1.c
@@ -0,0 +1,16 @@
+/* Test against a problem in push_reload.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2" } */
+
+unsigned long foo (unsigned long long x, unsigned long y)
+{
+    unsigned long a;
+
+    x += y;
+
+    asm ("" : "=a" (a) : "A" (x), "rm" (y));
+
+    return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/991209-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/991209-1.c
new file mode 100644
index 000000000..15a46cfc4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/991209-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-ansi -pedantic" } */
+
+int foo ()
+{
+  return 1;
+}
+
+register char *stack_ptr __asm ("%esp"); /* { dg-warning "file-scope declaration of 'stack_ptr' specifies 'register'" } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/991214-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/991214-1.c
new file mode 100644
index 000000000..3d9a72ed0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/991214-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2" } */
+
+/* Test against a problem with the combiner substituting explicit hard reg
+   references when it shouldn't.  */
+void foo (int, int) __attribute__ ((regparm (3)));
+void __attribute__((regparm(3))) foo (int x, int y)
+{
+  __asm__ __volatile__("" : : "d" (x), "r" (y));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/991230-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/991230-1.c
new file mode 100644
index 000000000..a57cc98ea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/991230-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O -ffast-math -mtune=i486" } */
+
+/* Test that floating point greater-than tests are compiled correctly with
+   -ffast-math.  */
+
+extern void abort (void);
+
+static int gt (double a, double b)
+{
+  if (a > b)
+    return 4;
+  return 0;
+}
+
+static double zero = 0.0;
+
+int main ()
+{
+  if (gt (zero, zero))
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/abi-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/abi-1.c
new file mode 100644
index 000000000..62b80ef40
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/abi-1.c
@@ -0,0 +1,8 @@
+/* Make certain that we pass V2DF in the correct register for SSE1.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse -mno-sse2" } */
+
+typedef double v2df __attribute__((vector_size (16)));
+v2df foo (void) { return (v2df){ 1.0, 2.0 }; }
+
+/* { dg-final { scan-assembler-times "xmm0" 1 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/abi-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/abi-2.c
new file mode 100644
index 000000000..5ed6b4a56
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/abi-2.c
@@ -0,0 +1,8 @@
+/* Make certain that we pass __m256i in the correct register for AVX.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -mavx" } */
+
+typedef long long __m256i __attribute__ ((__vector_size__ (32)));
+__m256i foo (void) { return (__m256i){ 1, 2, 3, 4 }; }
+
+/* { dg-final { scan-assembler-times "ymm0" 1 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/addr-sel-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/addr-sel-1.c
new file mode 100644
index 000000000..9cc820fee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/addr-sel-1.c
@@ -0,0 +1,17 @@
+/* PR rtl-optimization/28940 */
+/* Origin: Lev Makhlis <lmakhlis@bmc.com> */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -mtune=i686" } */
+
+char a[10], b[10];
+
+int f(int i)
+{
+  return a[i+1] + b[i+1];
+}
+
+/* { dg-final { scan-assembler "a\\+1" } } */
+/* { dg-final { scan-assembler "b\\+1" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aes-avx-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aes-avx-check.h
new file mode 100644
index 000000000..e73e36eab
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aes-avx-check.h
@@ -0,0 +1,31 @@
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+#include <stdlib.h>
+#include "cpuid.h"
+
+static void aes_avx_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run AES + AVX test only if host has AES + AVX support.  */
+  if ((ecx & (bit_AVX | bit_AES)) == (bit_AVX | bit_AES))
+    {
+      aes_avx_test ();
+#ifdef DEBUG
+      printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aes-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aes-check.h
new file mode 100644
index 000000000..f56f1adeb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aes-check.h
@@ -0,0 +1,30 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void aes_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run AES test only if host has AES support.  */
+  if (ecx & bit_AES)
+    {
+      aes_test ();
+#ifdef DEBUG
+    printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aesdec.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aesdec.c
new file mode 100644
index 000000000..affe3d19c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aesdec.c
@@ -0,0 +1,75 @@
+/* { dg-do run } */
+/* { dg-require-effective-target aes } */
+/* { dg-options "-O2 -maes" } */
+
+#ifndef CHECK_H
+#define CHECK_H "aes-check.h"
+#endif
+
+#ifndef TEST
+#define TEST aes_test
+#endif
+
+#include CHECK_H
+
+#include <wmmintrin.h>
+#include <string.h>
+
+extern void abort (void);
+
+#define NUM 1024
+
+static __m128i src1[NUM];
+static __m128i src2[NUM];
+static __m128i edst[NUM];
+
+static __m128i resdst[NUM];
+
+/* Initialize input/output vectors.  (Currently, there is only one set
+   of input/output vectors).  */
+static void
+init_data (__m128i *s1, __m128i *s2, __m128i *d)
+{
+  int i;
+  for (i = 0; i < NUM; i++)
+    {
+      s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72,
+			      0x73745665, 0x7b5b5465);
+      s2[i] = _mm_setr_epi32 (0x726f6e5d, 0x5b477565,
+			      0x68617929, 0x48692853);
+      d[i]  = _mm_setr_epi32 (0xb730392a, 0xb58eb95e,
+			      0xfaea2787, 0x138ac342);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+
+  init_data (src1, src2, edst);
+
+  for (i = 0; i < NUM; i += 16)
+    {
+      resdst[i] = _mm_aesdec_si128 (src1[i], src2[i]);
+      resdst[i + 1] = _mm_aesdec_si128 (src1[i + 1], src2[i + 1]);
+      resdst[i + 2] = _mm_aesdec_si128 (src1[i + 2], src2[i + 2]);
+      resdst[i + 3] = _mm_aesdec_si128 (src1[i + 3], src2[i + 3]);
+      resdst[i + 4] = _mm_aesdec_si128 (src1[i + 4], src2[i + 4]);
+      resdst[i + 5] = _mm_aesdec_si128 (src1[i + 5], src2[i + 5]);
+      resdst[i + 6] = _mm_aesdec_si128 (src1[i + 6], src2[i + 6]);
+      resdst[i + 7] = _mm_aesdec_si128 (src1[i + 7], src2[i + 7]);
+      resdst[i + 8] = _mm_aesdec_si128 (src1[i + 8], src2[i + 8]);
+      resdst[i + 9] = _mm_aesdec_si128 (src1[i + 9], src2[i + 9]);
+      resdst[i + 10] = _mm_aesdec_si128 (src1[i + 10], src2[i + 10]);
+      resdst[i + 11] = _mm_aesdec_si128 (src1[i + 11], src2[i + 11]);
+      resdst[i + 12] = _mm_aesdec_si128 (src1[i + 12], src2[i + 12]);
+      resdst[i + 13] = _mm_aesdec_si128 (src1[i + 13], src2[i + 13]);
+      resdst[i + 14] = _mm_aesdec_si128 (src1[i + 14], src2[i + 14]);
+      resdst[i + 15] = _mm_aesdec_si128 (src1[i + 15], src2[i + 15]);
+    }
+
+  for (i = 0; i < NUM; i++)
+    if (memcmp (edst + i, resdst + i, sizeof (__m128i)))
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aesdeclast.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aesdeclast.c
new file mode 100644
index 000000000..417264a13
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aesdeclast.c
@@ -0,0 +1,77 @@
+/* { dg-do run } */
+/* { dg-require-effective-target aes } */
+/* { dg-options "-O2 -maes" } */
+
+#ifndef CHECK_H
+#define CHECK_H "aes-check.h"
+#endif
+
+#ifndef TEST
+#define TEST aes_test
+#endif
+
+#include CHECK_H
+
+#include <wmmintrin.h>
+#include <string.h>
+
+extern void abort (void);
+
+#define NUM 1024
+
+static __m128i src1[NUM];
+static __m128i src2[NUM];
+static __m128i edst[NUM];
+
+static __m128i resdst[NUM];
+
+/* Initialize input/output vectors.  (Currently, there is only one set of
+   input/output vectors).  */
+
+static void
+init_data (__m128i *s1, __m128i *s2, __m128i *d)
+{
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72,
+			      0x73745665, 0x7b5b5465);
+      s2[i] = _mm_setr_epi32 (0x726f6e5d, 0x5b477565,
+			      0x68617929, 0x48692853);
+      d[i] = _mm_setr_epi32 (0x72a593d0, 0xd410637b,
+			     0x6b317f95, 0xc5a391ef);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+
+  init_data (src1, src2, edst);
+
+  for (i = 0; i < NUM; i += 16)
+    {
+      resdst[i] = _mm_aesdeclast_si128 (src1[i], src2[i]);
+      resdst[i + 1] = _mm_aesdeclast_si128 (src1[i + 1], src2[i + 1]);
+      resdst[i + 2] = _mm_aesdeclast_si128 (src1[i + 2], src2[i + 2]);
+      resdst[i + 3] = _mm_aesdeclast_si128 (src1[i + 3], src2[i + 3]);
+      resdst[i + 4] = _mm_aesdeclast_si128 (src1[i + 4], src2[i + 4]);
+      resdst[i + 5] = _mm_aesdeclast_si128 (src1[i + 5], src2[i + 5]);
+      resdst[i + 6] = _mm_aesdeclast_si128 (src1[i + 6], src2[i + 6]);
+      resdst[i + 7] = _mm_aesdeclast_si128 (src1[i + 7], src2[i + 7]);
+      resdst[i + 8] = _mm_aesdeclast_si128 (src1[i + 8], src2[i + 8]);
+      resdst[i + 9] = _mm_aesdeclast_si128 (src1[i + 9], src2[i + 9]);
+      resdst[i + 10] = _mm_aesdeclast_si128 (src1[i + 10], src2[i + 10]);
+      resdst[i + 11] = _mm_aesdeclast_si128 (src1[i + 11], src2[i + 11]);
+      resdst[i + 12] = _mm_aesdeclast_si128 (src1[i + 12], src2[i + 12]);
+      resdst[i + 13] = _mm_aesdeclast_si128 (src1[i + 13], src2[i + 13]);
+      resdst[i + 14] = _mm_aesdeclast_si128 (src1[i + 14], src2[i + 14]);
+      resdst[i + 15] = _mm_aesdeclast_si128 (src1[i + 15], src2[i + 15]);
+    }
+
+  for (i = 0; i < NUM; i++)
+    if (memcmp (edst + i, resdst + i, sizeof (__m128i)))
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aesenc.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aesenc.c
new file mode 100644
index 000000000..d2a8b6031
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aesenc.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-require-effective-target aes } */
+/* { dg-options "-O2 -maes" } */
+
+#ifndef CHECK_H
+#define CHECK_H "aes-check.h"
+#endif
+
+#ifndef TEST
+#define TEST aes_test
+#endif
+
+#include CHECK_H
+
+#include <wmmintrin.h>
+#include <string.h>
+
+extern void abort (void);
+
+#define NUM 1024
+
+static __m128i src1[NUM];
+static __m128i src2[NUM];
+static __m128i edst[NUM];
+
+static __m128i resdst[NUM];
+
+/* Initialize input/output vectors.  (Currently, there is only one set
+   of input/output vectors).  */
+
+static void
+init_data (__m128i *s1, __m128i *s2, __m128i *d)
+{
+  int i;
+  for (i = 0; i < NUM; i++)
+    {
+      s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72,
+			      0x73745665, 0x7b5b5465);
+      s2[i] = _mm_setr_epi32 (0x726f6e5d, 0x5b477565,
+			      0x68617929, 0x48692853);
+      d[i] = _mm_setr_epi32 (0xded7e595, 0x8b104b58,
+			     0x9fdba3c5, 0xa8311c2f);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+
+  init_data (src1, src2, edst);
+
+  for (i = 0; i < NUM; i += 16)
+    {
+      resdst[i] = _mm_aesenc_si128 (src1[i], src2[i]);
+      resdst[i + 1] = _mm_aesenc_si128 (src1[i + 1], src2[i + 1]);
+      resdst[i + 2] = _mm_aesenc_si128 (src1[i + 2], src2[i + 2]);
+      resdst[i + 3] = _mm_aesenc_si128 (src1[i + 3], src2[i + 3]);
+      resdst[i + 4] = _mm_aesenc_si128 (src1[i + 4], src2[i + 4]);
+      resdst[i + 5] = _mm_aesenc_si128 (src1[i + 5], src2[i + 5]);
+      resdst[i + 6] = _mm_aesenc_si128 (src1[i + 6], src2[i + 6]);
+      resdst[i + 7] = _mm_aesenc_si128 (src1[i + 7], src2[i + 7]);
+      resdst[i + 8] = _mm_aesenc_si128 (src1[i + 8], src2[i + 8]);
+      resdst[i + 9] = _mm_aesenc_si128 (src1[i + 9], src2[i + 9]);
+      resdst[i + 10] = _mm_aesenc_si128 (src1[i + 10], src2[i + 10]);
+      resdst[i + 11] = _mm_aesenc_si128 (src1[i + 11], src2[i + 11]);
+      resdst[i + 12] = _mm_aesenc_si128 (src1[i + 12], src2[i + 12]);
+      resdst[i + 13] = _mm_aesenc_si128 (src1[i + 13], src2[i + 13]);
+      resdst[i + 14] = _mm_aesenc_si128 (src1[i + 14], src2[i + 14]);
+      resdst[i + 15] = _mm_aesenc_si128 (src1[i + 15], src2[i + 15]);
+    }
+
+  for (i = 0; i < NUM; i++)
+    if (memcmp (edst + i, resdst + i, sizeof (__m128i)))
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aesenclast.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aesenclast.c
new file mode 100644
index 000000000..fd72597e9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aesenclast.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-require-effective-target aes } */
+/* { dg-options "-O2 -maes" } */
+
+#ifndef CHECK_H
+#define CHECK_H "aes-check.h"
+#endif
+
+#ifndef TEST
+#define TEST aes_test
+#endif
+
+#include CHECK_H
+
+#include <wmmintrin.h>
+#include <string.h>
+
+extern void abort (void);
+
+#define NUM 1024
+
+static __m128i src1[NUM];
+static __m128i src2[NUM];
+static __m128i edst[NUM];
+
+static __m128i resdst[NUM];
+
+/* Initialize input/output vectors.  (Currently, there is only one
+   set of input/output vectors).  */
+
+static void
+init_data (__m128i *s1, __m128i *s2, __m128i *d)
+{
+  int i;
+  for (i = 0; i < NUM; i++)
+    {
+      s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72,
+			      0x73745665, 0x7b5b5465);
+      s2[i] = _mm_setr_epi32 (0x726f6e5d, 0x5b477565,
+			      0x68617929, 0x48692853);
+      d[i] = _mm_setr_epi32 (0x53fdc611, 0x177ec425,
+			     0x938c5964, 0xc7fb881e);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+
+  init_data (src1, src2, edst);
+
+  for (i = 0; i < NUM; i += 16)
+    {
+      resdst[i] = _mm_aesenclast_si128 (src1[i], src2[i]);
+      resdst[i + 1] = _mm_aesenclast_si128 (src1[i + 1], src2[i + 1]);
+      resdst[i + 2] = _mm_aesenclast_si128 (src1[i + 2], src2[i + 2]);
+      resdst[i + 3] = _mm_aesenclast_si128 (src1[i + 3], src2[i + 3]);
+      resdst[i + 4] = _mm_aesenclast_si128 (src1[i + 4], src2[i + 4]);
+      resdst[i + 5] = _mm_aesenclast_si128 (src1[i + 5], src2[i + 5]);
+      resdst[i + 6] = _mm_aesenclast_si128 (src1[i + 6], src2[i + 6]);
+      resdst[i + 7] = _mm_aesenclast_si128 (src1[i + 7], src2[i + 7]);
+      resdst[i + 8] = _mm_aesenclast_si128 (src1[i + 8], src2[i + 8]);
+      resdst[i + 9] = _mm_aesenclast_si128 (src1[i + 9], src2[i + 9]);
+      resdst[i + 10] = _mm_aesenclast_si128 (src1[i + 10], src2[i + 10]);
+      resdst[i + 11] = _mm_aesenclast_si128 (src1[i + 11], src2[i + 11]);
+      resdst[i + 12] = _mm_aesenclast_si128 (src1[i + 12], src2[i + 12]);
+      resdst[i + 13] = _mm_aesenclast_si128 (src1[i + 13], src2[i + 13]);
+      resdst[i + 14] = _mm_aesenclast_si128 (src1[i + 14], src2[i + 14]);
+      resdst[i + 15] = _mm_aesenclast_si128 (src1[i + 15], src2[i + 15]);
+    }
+
+  for (i = 0; i < NUM; i++)
+    if (memcmp(edst + i, resdst + i, sizeof (__m128i)))
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aesimc.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aesimc.c
new file mode 100644
index 000000000..676f919f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aesimc.c
@@ -0,0 +1,74 @@
+/* { dg-do run } */
+/* { dg-require-effective-target aes } */
+/* { dg-options "-O2 -maes" } */
+
+#ifndef CHECK_H
+#define CHECK_H "aes-check.h"
+#endif
+
+#ifndef TEST
+#define TEST aes_test
+#endif
+
+#include CHECK_H
+
+#include <wmmintrin.h>
+#include <string.h>
+
+extern void abort (void);
+
+#define NUM 1024
+
+static __m128i src1[NUM];
+static __m128i edst[NUM];
+
+static __m128i resdst[NUM];
+
+/* Initialize input/output vectors.  (Currently, there is only one set
+   of input/output vectors).   */
+
+static void
+init_data (__m128i *s1, __m128i *d)
+{
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72,
+			      0x73745665, 0x7b5b5465);
+      d[i] = _mm_setr_epi32 (0x81c3b3e5, 0x2b18330a,
+			     0x44b109c8, 0x627a6f66);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+
+  init_data (src1, edst);
+
+  for (i = 0; i < NUM; i += 16)
+    {
+      resdst[i] = _mm_aesimc_si128 (src1[i]);
+      resdst[i + 1] = _mm_aesimc_si128 (src1[i + 1]);
+      resdst[i + 2] = _mm_aesimc_si128 (src1[i + 2]);
+      resdst[i + 3] = _mm_aesimc_si128 (src1[i + 3]);
+      resdst[i + 4] = _mm_aesimc_si128 (src1[i + 4]);
+      resdst[i + 5] = _mm_aesimc_si128 (src1[i + 5]);
+      resdst[i + 6] = _mm_aesimc_si128 (src1[i + 6]);
+      resdst[i + 7] = _mm_aesimc_si128 (src1[i + 7]);
+      resdst[i + 8] = _mm_aesimc_si128 (src1[i + 8]);
+      resdst[i + 9] = _mm_aesimc_si128 (src1[i + 9]);
+      resdst[i + 10] = _mm_aesimc_si128 (src1[i + 10]);
+      resdst[i + 11] = _mm_aesimc_si128 (src1[i + 11]);
+      resdst[i + 12] = _mm_aesimc_si128 (src1[i + 12]);
+      resdst[i + 13] = _mm_aesimc_si128 (src1[i + 13]);
+      resdst[i + 14] = _mm_aesimc_si128 (src1[i + 14]);
+      resdst[i + 15] = _mm_aesimc_si128 (src1[i + 15]);
+    }
+
+  for (i = 0; i < NUM; i++)
+    if (memcmp(edst + i, resdst + i, sizeof (__m128i)))
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aeskeygenassist.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aeskeygenassist.c
new file mode 100644
index 000000000..f033bd6a0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/aeskeygenassist.c
@@ -0,0 +1,74 @@
+/* { dg-do run } */
+/* { dg-require-effective-target aes } */
+/* { dg-options "-O2 -maes" } */
+
+#ifndef CHECK_H
+#define CHECK_H "aes-check.h"
+#endif
+
+#ifndef TEST
+#define TEST aes_test
+#endif
+
+#include CHECK_H
+
+#include <wmmintrin.h>
+#include <string.h>
+
+extern void abort (void);
+
+#define NUM 1024
+#define IMM8 1
+
+static __m128i src1[NUM];
+static __m128i edst[NUM];
+
+static __m128i resdst[NUM];
+
+/* Initialize input/output vectors.  (Currently, there is only one set
+   of input/output vectors).  */
+
+static void
+init_data (__m128i *s1, __m128i *d)
+{
+  int i;
+  for (i = 0; i < NUM; i++)
+    {
+      s1[i] = _mm_setr_epi32 (0x16157e2b, 0xa6d2ae28,
+			      0x8815f7ab, 0x3c4fcf09);
+      d[i] = _mm_setr_epi32 (0x24b5e434, 0x3424b5e5,
+			     0xeb848a01, 0x01eb848b);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+
+  init_data (src1, edst);
+
+  for (i = 0; i < NUM; i += 16)
+    {
+      resdst[i]  = _mm_aeskeygenassist_si128 (src1[i], IMM8);
+      resdst[i + 1] = _mm_aeskeygenassist_si128 (src1[i + 1], IMM8);
+      resdst[i + 2] = _mm_aeskeygenassist_si128 (src1[i + 2], IMM8);
+      resdst[i + 3] = _mm_aeskeygenassist_si128 (src1[i + 3], IMM8);
+      resdst[i + 4] = _mm_aeskeygenassist_si128 (src1[i + 4], IMM8);
+      resdst[i + 5] = _mm_aeskeygenassist_si128 (src1[i + 5], IMM8);
+      resdst[i + 6] = _mm_aeskeygenassist_si128 (src1[i + 6], IMM8);
+      resdst[i + 7] = _mm_aeskeygenassist_si128 (src1[i + 7], IMM8);
+      resdst[i + 8] = _mm_aeskeygenassist_si128 (src1[i + 8], IMM8);
+      resdst[i + 9] = _mm_aeskeygenassist_si128 (src1[i + 9], IMM8);
+      resdst[i + 10] = _mm_aeskeygenassist_si128 (src1[i + 10], IMM8);
+      resdst[i + 11] = _mm_aeskeygenassist_si128 (src1[i + 11], IMM8);
+      resdst[i + 12] = _mm_aeskeygenassist_si128 (src1[i + 12], IMM8);
+      resdst[i + 13] = _mm_aeskeygenassist_si128 (src1[i + 13], IMM8);
+      resdst[i + 14] = _mm_aeskeygenassist_si128 (src1[i + 14], IMM8);
+      resdst[i + 15] = _mm_aeskeygenassist_si128 (src1[i + 15], IMM8);
+    }
+
+  for (i = 0; i < NUM; i++)
+    if (memcmp(edst + i, resdst + i, sizeof (__m128i)))
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/align-main-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/align-main-1.c
new file mode 100644
index 000000000..5bbc101c0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/align-main-1.c
@@ -0,0 +1,25 @@
+/* Test for stack alignment when PREFERRED_STACK_BOUNDARY < alignment
+   of local variable.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=6" } */
+/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-128,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
+
+#include <stddef.h>
+
+#define ALIGNMENT 128
+typedef int aligned __attribute__((aligned(ALIGNMENT)));
+extern void abort(void);
+
+void check(void * a)
+{
+  if (((ptrdiff_t)a & (ALIGNMENT-1)) != 0)
+    abort();
+}
+
+int main()
+{
+  aligned a = 1;
+  check(&a);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/align-main-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/align-main-2.c
new file mode 100644
index 000000000..df45f0e51
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/align-main-2.c
@@ -0,0 +1,25 @@
+/* Test for stack alignment when PREFERRED_STACK_BOUNDARY > alignment
+   of local variable.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=6" } */
+/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-128,\[\\t \]*%\[re\]?sp" } } */
+
+#include <stddef.h>
+
+#define ALIGNMENT 32
+typedef int aligned __attribute__((aligned(ALIGNMENT)));
+extern void abort(void);
+
+void check(void * a)
+{
+  if (((ptrdiff_t)a & (ALIGNMENT-1)) != 0)
+    abort();
+}
+
+int main()
+{
+  aligned a = 1;
+  check(&a);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/align-main-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/align-main-3.c
new file mode 100644
index 000000000..d2f88d859
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/align-main-3.c
@@ -0,0 +1,14 @@
+/* Test for stack alignment with sibcall optimization.  */
+/* { dg-do compile { target { *-*-linux* && ilp32 } } } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=4 -mincoming-stack-boundary=2" } */
+/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-final { scan-assembler "call\[\\t \]*foo" } } */
+/* { dg-final { scan-assembler-not "jmp\[\\t \]*foo" } } */
+
+extern int foo (void);
+
+int
+main ()
+{
+  return foo ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-1.c
new file mode 100644
index 000000000..d3df77a49
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mno-sse" } */
+
+double foo(void) { return 0; }	/* { dg-error "SSE disabled" } */
+void bar(double x) { }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-2.c
new file mode 100644
index 000000000..fefc88a4e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-2.c
@@ -0,0 +1,7 @@
+/* PR target/26223 */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mno-80387" } */
+long double foo(long double x) { return x; } /* { dg-error "x87 disabled" } */
+long double bar(long double x) { return x; }
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-3.c
new file mode 100644
index 000000000..8db7f13b1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-3.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -fomit-frame-pointer -mno-sse" } */
+/* { dg-final { scan-assembler "subq\[\\t \]*\\\$88,\[\\t \]*%rsp" } } */
+/* { dg-final { scan-assembler-not "subq\[\\t \]*\\\$216,\[\\t \]*%rsp" } } */
+
+#include <stdarg.h>
+
+void foo (va_list va_arglist);
+
+void
+test (int a1, ...)
+{
+  va_list va_arglist;
+  va_start (va_arglist, a1);
+  foo (va_arglist);
+  va_end (va_arglist);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-4.c
new file mode 100644
index 000000000..8f3202966
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-4.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mno-sse" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+int n1 = 30;
+int n2 = 324;
+void *n3 = (void *) &n2;
+int n4 = 407;
+
+int e1;
+int e2;
+void *e3;
+int e4;
+
+static void
+__attribute__((noinline))
+foo (va_list va_arglist)
+{
+  e2 = va_arg (va_arglist, int);
+  e3 = va_arg (va_arglist, void *);
+  e4 = va_arg (va_arglist, int);
+}
+
+static void
+__attribute__((noinline))
+test (int a1, ...)
+{
+  e1 = a1;
+  va_list va_arglist;
+  va_start (va_arglist, a1);
+  foo (va_arglist);
+  va_end (va_arglist);
+}
+
+int
+main ()
+{
+  test (n1, n2, n3, n4);
+  assert (n1 == e1);
+  assert (n2 == e2);
+  assert (n3 == e3);
+  assert (n4 == e4);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-5.c
new file mode 100644
index 000000000..e4ba1fd5d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-5.c
@@ -0,0 +1,64 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+int n1 = 30;
+double n2 = 324;
+double n3 = 39494.94;
+double n4 = 407;
+double n5 = 32.304;
+double n6 = 394.14;
+double n7 = 4.07;
+double n8 = 32.4;
+double n9 = 314.194;
+double n10 = 0.1407;
+
+int e1;
+double e2;
+double e3;
+double e4;
+double e5;
+double e6;
+double e7;
+double e8;
+double e9;
+double e10;
+
+static void
+__attribute__((noinline))
+test (int a1, ...)
+{
+  e1 = a1;
+  va_list va_arglist;
+  va_start (va_arglist, a1);
+  e2 = va_arg (va_arglist, double);
+  e3 = va_arg (va_arglist, double);
+  e4 = va_arg (va_arglist, double);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, double);
+  e7 = va_arg (va_arglist, double);
+  e8 = va_arg (va_arglist, double);
+  e9 = va_arg (va_arglist, double);
+  e10 = va_arg (va_arglist, double);
+  va_end (va_arglist);
+}
+
+int
+main ()
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10);
+  assert (n1 == e1);
+  assert (n2 == e2);
+  assert (n3 == e3);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (n6 == e6);
+  assert (n7 == e7);
+  assert (n8 == e8);
+  assert (n9 == e9);
+  assert (n10 == e10);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-6.c
new file mode 100644
index 000000000..255b5479e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/amd64-abi-6.c
@@ -0,0 +1,71 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+int n1 = 30;
+double n2 = 324;
+double n3 = 39494.94;
+double n4 = 407;
+double n5 = 32.304;
+double n6 = 394.14;
+double n7 = 4.07;
+double n8 = 32.4;
+double n9 = 314.194;
+double n10 = 0.1407;
+
+int e1;
+double e2;
+double e3;
+double e4;
+double e5;
+double e6;
+double e7;
+double e8;
+double e9;
+double e10;
+
+static void
+__attribute__((noinline))
+foo (va_list va_arglist)
+{
+  e2 = va_arg (va_arglist, double);
+  e3 = va_arg (va_arglist, double);
+  e4 = va_arg (va_arglist, double);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, double);
+  e7 = va_arg (va_arglist, double);
+  e8 = va_arg (va_arglist, double);
+  e9 = va_arg (va_arglist, double);
+  e10 = va_arg (va_arglist, double);
+}
+
+static void
+__attribute__((noinline))
+test (int a1, ...)
+{
+  va_list va_arglist;
+  e1 = a1;
+  va_start (va_arglist, a1);
+  foo (va_arglist);
+  va_end (va_arglist);
+}
+
+int
+main ()
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10);
+  assert (n1 == e1);
+  assert (n2 == e2);
+  assert (n3 == e3);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (n6 == e6);
+  assert (n7 == e7);
+  assert (n8 == e8);
+  assert (n9 == e9);
+  assert (n10 == e10);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/andor-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/andor-1.c
new file mode 100644
index 000000000..6cc12b348
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/andor-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "andl" } } */
+
+unsigned int foo(unsigned int x)
+{
+  unsigned int t = x & ~1;
+  return t | 1;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/andor-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/andor-2.c
new file mode 100644
index 000000000..88118aab5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/andor-2.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=i686" } */
+
+int h(int x, int y)
+{
+  if ((x >= 0 && x <= 1) && (y >= 0 && y <= 1))
+    return x && y;
+  else
+    return -1;
+}
+
+int g(int x, int y)
+{
+  if ((x >= 0 && x <= 1) && (y >= 0 && y <= 1))
+    return x || y;
+  else
+    return -1;
+}
+
+int f(int x, int y)
+{
+  if (x != 0 && x != 1)
+    return -2;
+
+  else
+    return !x;
+}
+
+/* { dg-final { scan-assembler-not "setne" } } */
+/* { dg-final { scan-assembler-not "sete" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/asm-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/asm-1.c
new file mode 100644
index 000000000..348dc32dd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/asm-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-m32" } */
+
+register unsigned int EAX asm ("r14"); /* { dg-error "register name" } */
+
+void foo ()
+{
+  EAX = 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/asm-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/asm-2.c
new file mode 100644
index 000000000..09a545517
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/asm-2.c
@@ -0,0 +1,62 @@
+/* PR opt/13862 */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O" } */
+
+typedef struct _fame_syntax_t_ {
+} fame_syntax_t;
+
+typedef struct _fame_bitbuffer_t_
+{
+  unsigned char * base;
+  unsigned char * data;
+  unsigned long shift;
+} fame_bitbuffer_t;
+
+#define fast_bitbuffer_write(data, shift, c, l)				\
+{									\
+  int d;								\
+									\
+  asm("add %1, %%ecx\n"            /* ecx = shift + length */		\
+      "shrd %%cl, %2, %3\n"        /* adjust code to fit in */		\
+      "shr %%cl, %2\n"             /* adjust code to fit in */		\
+      "mov %%ecx, %1\n"            /* shift += length */		\
+      "bswap %2\n"                 /* reverse byte order of code */	\
+      "shr $5, %%ecx\n"            /* get dword increment */            \
+      "or %2, (%0)\n"              /* put first 32 bits */		\
+      "bswap %3\n"                 /* reverse byte order of code */	\
+      "lea   (%0, %%ecx, 4), %0\n" /* data += (ecx>32) */		\
+      "andl $31, %1\n"             /* mask shift */			\
+      "orl %3, (%0)\n"             /* put last 32 bits */		\
+      : "=r"(data), "=r"(shift), "=a"(d), "=d"(d), "=c"(d)		\
+      : "0"(data), "1"(shift), "2"((unsigned long) c), "3"(0),		\
+	"c"((unsigned long) l)						\
+      : "memory");							\
+}
+
+#define bitbuffer_write(bb, c, l) \
+  fast_bitbuffer_write((bb)->data, (bb)->shift, c, l)
+
+typedef enum { frame_type_I, frame_type_P } frame_type_t;
+
+typedef struct _fame_syntax_mpeg1_t_ {
+  fame_bitbuffer_t buffer;
+  frame_type_t frame_type;
+} fame_syntax_mpeg1_t;
+
+#define FAME_SYNTAX_MPEG1(x) ((fame_syntax_mpeg1_t *) x)
+
+void mpeg1_start_picture(fame_syntax_t *syntax)
+{
+  fame_syntax_mpeg1_t *syntax_mpeg1 = FAME_SYNTAX_MPEG1(syntax);
+  bitbuffer_write(&syntax_mpeg1->buffer, 0xFFFF, 16); 
+
+  switch(syntax_mpeg1->frame_type) {
+    case frame_type_I:
+      bitbuffer_write(&syntax_mpeg1->buffer, 0, 1);  
+    break;
+    case frame_type_P:
+      bitbuffer_write(&syntax_mpeg1->buffer, 0, 1);
+    break;
+  }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/asm-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/asm-3.c
new file mode 100644
index 000000000..6c23237de
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/asm-3.c
@@ -0,0 +1,35 @@
+/* PR inline-asm/6806 */
+/* { dg-do run } */
+/* { dg-skip-if "" { ilp32 && { ! nonpic } } { "*" } { "" } } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+volatile int out = 1;
+volatile int a = 2;
+volatile int b = 4;
+volatile int c = 8;
+volatile int d = 16;
+volatile int e = 32;
+volatile int f = 64;
+
+int
+main ()
+{
+  asm volatile ("xorl %%eax, %%eax	\n\t"
+		"xorl %%esi, %%esi	\n\t"
+		"addl %1, %0		\n\t"
+		"addl %2, %0		\n\t"
+		"addl %3, %0		\n\t"
+		"addl %4, %0		\n\t"
+		"addl %5, %0		\n\t"
+		"addl %6, %0"
+		: "+r" (out)
+		: "r" (a), "r" (b), "r" (c), "g" (d), "g" (e), "g" (f)
+		: "%eax", "%esi");
+
+  if (out != 127)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/asm-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/asm-4.c
new file mode 100644
index 000000000..b86801032
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/asm-4.c
@@ -0,0 +1,47 @@
+/* Test if functions marked __attribute__((used)), but with address never
+   taken in C code, don't use alternate calling convention for local
+   functions on IA-32.  */
+/* { dg-do run } */
+/* The asm in this test uses an absolute address.  */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+static int foo (int, int, int, int) __asm ("foo");
+static __attribute__((noinline, used)) int
+foo (int i, int j, int k, int l)
+{
+  return i + j + k + l;
+}
+
+void
+bar (void)
+{
+  if (foo (1, 2, 3, 4) != 10)
+    abort ();
+}
+
+int (*fn) (int, int, int, int);
+
+void
+baz (void)
+{
+  /* Darwin loads 64-bit regions above the 4GB boundary so
+     we need to use this instead.  */
+#if defined (__LP64__) && defined (__MACH__)
+  __asm ("leaq foo(%%rip), %0" : "=r" (fn));
+#else
+  __asm ("movl $foo, %k0" : "=r" (fn));
+#endif
+  if (fn (2, 3, 4, 5) != 14)
+    abort ();
+}
+
+int
+main (void)
+{
+  bar ();
+  baz ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/asm-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/asm-5.c
new file mode 100644
index 000000000..966a824b3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/asm-5.c
@@ -0,0 +1,26 @@
+/* PR inline-asm/11676 */
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+static int bar(int x) __asm__("bar") __attribute__((regparm(1)));
+static int __attribute__((regparm(1), noinline, used))
+bar(int x)
+{
+  if (x != 0)
+    abort ();
+}
+
+static int __attribute__((regparm(1), noinline))
+foo(int x)
+{
+  x = 0;
+  __asm__ __volatile__("call bar" : "=a"(x) : "a"(x));
+}
+
+int main()
+{
+  foo(1);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/attr-returns_twice-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/attr-returns_twice-1.c
new file mode 100644
index 000000000..cd820d276
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/attr-returns_twice-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-Wclobbered" } */
+
+int newsetjmp(void) __attribute__((returns_twice));
+void g(int);
+
+int
+main (void)
+{
+  register int reg asm ("esi") = 1; /* { dg-warning "might be clobbered" "" } */
+
+  if (!newsetjmp ())
+    {
+      reg = 2;
+      g (reg);
+    }
+  else
+    {
+      g (reg);
+    }
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/attributes-error.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/attributes-error.c
new file mode 100644
index 000000000..1a5b0eade
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/attributes-error.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+
+void foo1(int i, int j) __attribute__((fastcall, cdecl)); /* { dg-error "not compatible" } */
+void foo2(int i, int j) __attribute__((fastcall, stdcall)); /* { dg-error "not compatible" } */
+void foo3(int i, int j) __attribute__((fastcall, regparm(2))); /* { dg-error "not compatible" } */
+void foo4(int i, int j) __attribute__((stdcall, cdecl)); /* { dg-error "not compatible" } */
+void foo5(int i, int j) __attribute__((stdcall, fastcall)); /* { dg-error "not compatible" } */
+void foo6(int i, int j) __attribute__((cdecl, fastcall)); /* { dg-error "not compatible" } */
+void foo7(int i, int j) __attribute__((cdecl, stdcall)); /* { dg-error "not compatible" } */
+void foo8(int i, int j) __attribute__((regparm(2), fastcall)); /* { dg-error "not compatible" } */
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-1.c
new file mode 100644
index 000000000..d093d6c1c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-1.c
@@ -0,0 +1,139 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -msse5 -maes -mpclmul" } */
+
+#include <mm_malloc.h>
+
+/* Test that the intrinsics compile with optimization.  All of them are
+   defined as inline functions in {,x,e,p,t,s,w,g,a,b}mmintrin.h and
+   mm3dnow.h that reference the proper builtin functions.  Defining away
+   "extern" and "__inline" results in all of them being compiled as proper
+   functions.  */
+
+#define extern
+#define __inline
+
+/* Following intrinsics require immediate arguments. */
+
+/* ammintrin.h */
+#define __builtin_ia32_extrqi(X, I, L)  __builtin_ia32_extrqi(X, 1, 1)
+#define __builtin_ia32_insertqi(X, Y, I, L) __builtin_ia32_insertqi(X, Y, 1, 1)
+
+/* immintrin.h */
+#define __builtin_ia32_blendpd256(X, Y, M) __builtin_ia32_blendpd256(X, Y, 1)
+#define __builtin_ia32_blendps256(X, Y, M) __builtin_ia32_blendps256(X, Y, 1)
+#define __builtin_ia32_dpps256(X, Y, M) __builtin_ia32_dpps256(X, Y, 1)
+#define __builtin_ia32_shufpd256(X, Y, M) __builtin_ia32_shufpd256(X, Y, 1)
+#define __builtin_ia32_shufps256(X, Y, M) __builtin_ia32_shufps256(X, Y, 1)
+#define __builtin_ia32_cmpsd(X, Y, O) __builtin_ia32_cmpsd(X, Y, 1)
+#define __builtin_ia32_cmpss(X, Y, O) __builtin_ia32_cmpss(X, Y, 1)
+#define __builtin_ia32_cmppd(X, Y, O) __builtin_ia32_cmppd(X, Y, 1)
+#define __builtin_ia32_cmpps(X, Y, O) __builtin_ia32_cmpps(X, Y, 1)
+#define __builtin_ia32_cmppd256(X, Y, O) __builtin_ia32_cmppd256(X, Y, 1)
+#define __builtin_ia32_cmpps256(X, Y, O) __builtin_ia32_cmpps256(X, Y, 1)
+#define __builtin_ia32_vextractf128_pd256(X, N) __builtin_ia32_vextractf128_pd256(X, 1)
+#define __builtin_ia32_vextractf128_ps256(X, N) __builtin_ia32_vextractf128_ps256(X, 1)
+#define __builtin_ia32_vextractf128_si256(X, N) __builtin_ia32_vextractf128_si256(X, 1)
+#define __builtin_ia32_vpermilpd(X, N) __builtin_ia32_vpermilpd(X, 1)
+#define __builtin_ia32_vpermilpd256(X, N) __builtin_ia32_vpermilpd256(X, 1)
+#define __builtin_ia32_vpermilps(X, N) __builtin_ia32_vpermilps(X, 1)
+#define __builtin_ia32_vpermilps256(X, N) __builtin_ia32_vpermilps256(X, 1)
+#define __builtin_ia32_vpermil2pd(X, Y, C, I) __builtin_ia32_vpermil2pd(X, Y, C, 1)
+#define __builtin_ia32_vpermil2pd256(X, Y, C, I) __builtin_ia32_vpermil2pd256(X, Y, C, 1)
+#define __builtin_ia32_vpermil2ps(X, Y, C, I) __builtin_ia32_vpermil2ps(X, Y, C, 1)
+#define __builtin_ia32_vpermil2ps256(X, Y, C, I) __builtin_ia32_vpermil2ps256(X, Y, C, 1)
+#define __builtin_ia32_vperm2f128_pd256(X, Y, C) __builtin_ia32_vperm2f128_pd256(X, Y, 1)
+#define __builtin_ia32_vperm2f128_ps256(X, Y, C) __builtin_ia32_vperm2f128_ps256(X, Y, 1)
+#define __builtin_ia32_vperm2f128_si256(X, Y, C) __builtin_ia32_vperm2f128_si256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_pd256(X, Y, C) __builtin_ia32_vinsertf128_pd256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_ps256(X, Y, C) __builtin_ia32_vinsertf128_ps256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_si256(X, Y, C) __builtin_ia32_vinsertf128_si256(X, Y, 1)
+#define __builtin_ia32_roundpd256(V, M) __builtin_ia32_roundpd256(V, 1)
+#define __builtin_ia32_roundps256(V, M) __builtin_ia32_roundps256(V, 1)
+
+/* wmmintrin.h */
+#define __builtin_ia32_aeskeygenassist128(X, C) __builtin_ia32_aeskeygenassist128(X, 1)
+#define __builtin_ia32_pclmulqdq128(X, Y, I) __builtin_ia32_pclmulqdq128(X, Y, 1)
+
+/* mmintrin-common.h */
+#define __builtin_ia32_roundpd(V, M) __builtin_ia32_roundpd(V, 1)
+#define __builtin_ia32_roundsd(D, V, M) __builtin_ia32_roundsd(D, V, 1)
+#define __builtin_ia32_roundps(V, M) __builtin_ia32_roundps(V, 1)
+#define __builtin_ia32_roundss(D, V, M) __builtin_ia32_roundss(D, V, 1)
+
+/* smmintrin.h */
+#define __builtin_ia32_pblendw128(X, Y, M) __builtin_ia32_pblendw128 (X, Y, 1)
+#define __builtin_ia32_blendps(X, Y, M) __builtin_ia32_blendps(X, Y, 1)
+#define __builtin_ia32_blendpd(X, Y, M) __builtin_ia32_blendpd(X, Y, 1)
+#define __builtin_ia32_dpps(X, Y, M) __builtin_ia32_dpps(X, Y, 1)
+#define __builtin_ia32_dppd(X, Y, M) __builtin_ia32_dppd(X, Y, 1)
+#define __builtin_ia32_insertps128(D, S, N) __builtin_ia32_insertps128(D, S, 1)
+#define __builtin_ia32_vec_ext_v4sf(X, N) __builtin_ia32_vec_ext_v4sf(X, 1)
+#define __builtin_ia32_vec_set_v16qi(D, S, N) __builtin_ia32_vec_set_v16qi(D, S, 1)
+#define __builtin_ia32_vec_set_v4si(D, S, N) __builtin_ia32_vec_set_v4si(D, S, 1)
+#define __builtin_ia32_vec_set_v2di(D, S, N) __builtin_ia32_vec_set_v2di(D, S, 1)
+#define __builtin_ia32_vec_ext_v16qi(X, N) __builtin_ia32_vec_ext_v16qi(X, 1)
+#define __builtin_ia32_vec_ext_v4si(X, N) __builtin_ia32_vec_ext_v4si(X, 1)
+#define __builtin_ia32_vec_ext_v2di(X, N) __builtin_ia32_vec_ext_v2di(X, 1)
+#define __builtin_ia32_mpsadbw128(X, Y, M) __builtin_ia32_mpsadbw128(X, Y, 1)
+#define __builtin_ia32_pcmpistrm128(X, Y, M) \
+  __builtin_ia32_pcmpistrm128(X, Y, 1)
+#define __builtin_ia32_pcmpistri128(X, Y, M) \
+  __builtin_ia32_pcmpistri128(X, Y, 1)
+#define __builtin_ia32_pcmpestrm128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestrm128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestri128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestri128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpistria128(X, Y, M) \
+  __builtin_ia32_pcmpistria128(X, Y, 1)
+#define __builtin_ia32_pcmpistric128(X, Y, M) \
+  __builtin_ia32_pcmpistric128(X, Y, 1)
+#define __builtin_ia32_pcmpistrio128(X, Y, M) \
+  __builtin_ia32_pcmpistrio128(X, Y, 1)
+#define __builtin_ia32_pcmpistris128(X, Y, M) \
+  __builtin_ia32_pcmpistris128(X, Y, 1)
+#define __builtin_ia32_pcmpistriz128(X, Y, M) \
+  __builtin_ia32_pcmpistriz128(X, Y, 1)
+#define __builtin_ia32_pcmpestria128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestria128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestric128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestric128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestrio128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestrio128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestris128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestris128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestriz128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestriz128(X, LX, Y, LY, 1)
+
+/* tmmintrin.h */
+#define __builtin_ia32_palignr128(X, Y, N) __builtin_ia32_palignr128(X, Y, 8)
+#define __builtin_ia32_palignr(X, Y, N) __builtin_ia32_palignr(X, Y, 8)
+
+/* emmintrin.h */
+#define __builtin_ia32_psrldqi128(A, B) __builtin_ia32_psrldqi128(A, 8)
+#define __builtin_ia32_pslldqi128(A, B) __builtin_ia32_pslldqi128(A, 8)
+#define __builtin_ia32_pshufhw(A, N) __builtin_ia32_pshufhw(A, 0)
+#define __builtin_ia32_pshuflw(A, N) __builtin_ia32_pshuflw(A, 0)
+#define __builtin_ia32_pshufd(A, N) __builtin_ia32_pshufd(A, 0)
+#define __builtin_ia32_vec_set_v8hi(A, D, N) \
+  __builtin_ia32_vec_set_v8hi(A, D, 0)
+#define __builtin_ia32_vec_ext_v8hi(A, N) __builtin_ia32_vec_ext_v8hi(A, 0)
+#define __builtin_ia32_shufpd(A, B, N) __builtin_ia32_shufpd(A, B, 0)
+
+/* xmmintrin.h */
+#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, A, _MM_HINT_NTA)
+#define __builtin_ia32_pshufw(A, N) __builtin_ia32_pshufw(A, 0)
+#define __builtin_ia32_vec_set_v4hi(A, D, N) \
+  __builtin_ia32_vec_set_v4hi(A, D, 0)
+#define __builtin_ia32_vec_ext_v4hi(A, N) __builtin_ia32_vec_ext_v4hi(A, 0)
+#define __builtin_ia32_shufps(A, B, N) __builtin_ia32_shufps(A, B, 0)
+
+/* bmmintrin.h */
+#define __builtin_ia32_protbi(A, B) __builtin_ia32_protbi(A,1)
+#define __builtin_ia32_protwi(A, B) __builtin_ia32_protwi(A,1)
+#define __builtin_ia32_protdi(A, B) __builtin_ia32_protdi(A,1)
+#define __builtin_ia32_protqi(A, B) __builtin_ia32_protqi(A,1)
+
+#include <wmmintrin.h>
+#include <bmmintrin.h>
+#include <immintrin.h>
+#include <mm3dnow.h>
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-2.c
new file mode 100644
index 000000000..e0d9c811f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-2.c
@@ -0,0 +1,168 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -msse5 -maes -mpclmul" } */
+
+#include <mm_malloc.h>
+
+/* Test that the intrinsics compile without optimization.  All of them are
+   defined as inline functions in {,x,e,p,t,s,w,g,a,b}mmintrin.h and
+   mm3dnow.h that reference the proper builtin functions.  Defining away
+   "extern" and "__inline" results in all of them being compiled as proper
+   functions.  */
+
+#define extern
+#define __inline
+
+#include <wmmintrin.h>
+#include <bmmintrin.h>
+#include <immintrin.h>
+#include <mm3dnow.h>
+
+#define _CONCAT(x,y) x ## y
+
+#define test_1(func, type, op1_type, imm)				\
+  type _CONCAT(_,func) (op1_type A, int const I)			\
+  { return func (A, imm); }
+
+#define test_1x(func, type, op1_type, imm1, imm2)			\
+  type _CONCAT(_,func) (op1_type A, int const I, int const L)		\
+  { return func (A, imm1, imm2); }
+
+#define test_2(func, type, op1_type, op2_type, imm)			\
+  type _CONCAT(_,func) (op1_type A, op2_type B, int const I)		\
+  { return func (A, B, imm); }
+
+#define test_2x(func, type, op1_type, op2_type, imm1, imm2)		\
+  type _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L) \
+  { return func (A, B, imm1, imm2); }
+
+#define test_3(func, type, op1_type, op2_type, op3_type, imm)	\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, int const I)		\
+  { return func (A, B, C, imm); }
+
+#define test_4(func, type, op1_type, op2_type, op3_type, op4_type, imm)	\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, op4_type D, int const I)		\
+  { return func (A, B, C, D, imm); }
+
+
+/* Following intrinsics require immediate arguments.  They
+   are defined as macros for non-optimized compilations. */
+
+/* ammintrin.h */
+test_1x (_mm_extracti_si64, __m128i, __m128i, 1, 1)
+test_2x (_mm_inserti_si64, __m128i, __m128i, __m128i, 1, 1)
+
+/* immintrin.h */
+test_2 (_mm256_blend_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_blend_ps, __m256, __m256, __m256, 1)
+test_2 (_mm256_dp_ps, __m256, __m256, __m256, 1)
+test_2 (_mm256_shuffle_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_shuffle_ps, __m256, __m256, __m256, 1)
+test_2 (_mm_cmp_sd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_cmp_ss, __m128, __m128, __m128, 1)
+test_2 (_mm_cmp_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_cmp_ps, __m128, __m128, __m128, 1)
+test_2 (_mm256_cmp_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_cmp_ps, __m256, __m256, __m256, 1)
+test_1 (_mm256_extractf128_pd, __m128d, __m256d, 1)
+test_1 (_mm256_extractf128_ps, __m128, __m256, 1)
+test_1 (_mm256_extractf128_si256, __m128i, __m256i, 1)
+test_1 (_mm256_extract_epi8, int, __m256i, 20)
+test_1 (_mm256_extract_epi16, int, __m256i, 13)
+test_1 (_mm256_extract_epi32, int, __m256i, 6)
+#ifdef __x86_64__
+test_1 (_mm256_extract_epi64, long long, __m256i, 2)
+#endif
+test_1 (_mm_permute_pd, __m128d, __m128d, 1)
+test_1 (_mm256_permute_pd, __m256d, __m256d, 1)
+test_1 (_mm_permute_ps, __m128, __m128, 1)
+test_1 (_mm256_permute_ps, __m256, __m256, 1)
+test_2 (_mm256_permute2f128_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_permute2f128_ps, __m256, __m256, __m256, 1)
+test_2 (_mm256_permute2f128_si256, __m256i, __m256i, __m256i, 1)
+test_2 (_mm256_insertf128_pd, __m256d, __m256d, __m128d, 1)
+test_2 (_mm256_insertf128_ps, __m256, __m256, __m128, 1)
+test_2 (_mm256_insertf128_si256, __m256i, __m256i, __m128i, 1)
+test_2 (_mm256_insert_epi8, __m256i, __m256i, int, 30)
+test_2 (_mm256_insert_epi16, __m256i, __m256i, int, 7)
+test_2 (_mm256_insert_epi32, __m256i, __m256i, int, 3)
+#ifdef __x86_64__
+test_2 (_mm256_insert_epi64, __m256i, __m256i, long long, 1)
+#endif
+test_1 (_mm256_round_pd, __m256d, __m256d, 1)
+test_1 (_mm256_round_ps, __m256, __m256, 1)
+
+/* wmmintrin.h */
+test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1)
+test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1)
+
+/* mmintrin-common.h */
+test_1 (_mm_round_pd, __m128d, __m128d, 1)
+test_1 (_mm_round_ps, __m128, __m128, 1)
+test_2 (_mm_round_sd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_round_ss, __m128, __m128, __m128, 1)
+
+/* smmintrin.h */
+test_2 (_mm_blend_epi16, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_blend_ps, __m128, __m128, __m128, 1)
+test_2 (_mm_blend_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_dp_ps, __m128, __m128, __m128, 1)
+test_2 (_mm_dp_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_insert_ps, __m128, __m128, __m128, 1)
+test_1 (_mm_extract_ps, int, __m128, 1)
+test_2 (_mm_insert_epi8, __m128i, __m128i, int, 1)
+test_2 (_mm_insert_epi32, __m128i, __m128i, int, 1)
+#ifdef __x86_64__
+test_2 (_mm_insert_epi64, __m128i, __m128i, long long, 1)
+#endif
+test_1 (_mm_extract_epi8, int, __m128i, 1)
+test_1 (_mm_extract_epi32, int, __m128i, 1)
+#ifdef __x86_64__
+test_1 (_mm_extract_epi64, long long, __m128i, 1)
+#endif
+test_2 (_mm_mpsadbw_epu8, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrm, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_cmpistri, int, __m128i, __m128i, 1)
+test_4 (_mm_cmpestrm, __m128i, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestri, int, __m128i, int, __m128i, int, 1)
+test_2 (_mm_cmpistra, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrc, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistro, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrs, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrz, int, __m128i, __m128i, 1)
+test_4 (_mm_cmpestra, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrc, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestro, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrs, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
+
+/* tmmintrin.h */
+test_2 (_mm_alignr_epi8, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_alignr_pi8, __m64, __m64, __m64, 1)
+
+/* emmintrin.h */
+test_2 (_mm_shuffle_pd, __m128d, __m128d, __m128d, 1)
+test_1 (_mm_srli_si128, __m128i, __m128i, 1)
+test_1 (_mm_slli_si128, __m128i, __m128i, 1)
+test_1 (_mm_extract_epi16, int, __m128i, 1)
+test_2 (_mm_insert_epi16, __m128i, __m128i, int, 1)
+test_1 (_mm_shufflehi_epi16, __m128i, __m128i, 1)
+test_1 (_mm_shufflelo_epi16, __m128i, __m128i, 1)
+test_1 (_mm_shuffle_epi32, __m128i, __m128i, 1)
+
+/* xmmintrin.h */
+test_2 (_mm_shuffle_ps, __m128, __m128, __m128, 1)
+test_1 (_mm_extract_pi16, int, __m64, 1)
+test_1 (_m_pextrw, int, __m64, 1)
+test_2 (_mm_insert_pi16, __m64, __m64, int, 1)
+test_2 (_m_pinsrw, __m64, __m64, int, 1)
+test_1 (_mm_shuffle_pi16, __m64, __m64, 1)
+test_1 (_m_pshufw, __m64, __m64, 1)
+test_1 (_mm_prefetch, void, void *, _MM_HINT_NTA)
+
+/* bmmintrin.h */
+test_1 (_mm_roti_epi8, __m128i, __m128i, 1)
+test_1 (_mm_roti_epi16, __m128i, __m128i, 1)
+test_1 (_mm_roti_epi32, __m128i, __m128i, 1)
+test_1 (_mm_roti_epi64, __m128i, __m128i, 1)
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-3.c
new file mode 100644
index 000000000..6a180fa88
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-O2 -mavx -std=gnu99" } */
+
+_Decimal128
+foo128 (_Decimal128 z)
+{
+  return z + 1.0dl;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-check.h
new file mode 100644
index 000000000..8db55a103
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-check.h
@@ -0,0 +1,29 @@
+#include <stdlib.h>
+#include "cpuid.h"
+#include "m256-check.h"
+
+static void avx_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run AVX test only if host has AVX support.  */
+  if (ecx & bit_AVX)
+    {
+      avx_test ();
+#ifdef DEBUG
+      printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v16hi-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v16hi-1.c
new file mode 100644
index 000000000..e85784890
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v16hi-1.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (short *v)
+{
+  return _mm256_set_epi16 (v[15], v[14], v[13], v[12],
+			   v[11], v[10], v[9], v[8],
+			   v[7], v[6], v[5], v[4],
+			   v[3], v[2], v[1], v[0]);
+}
+
+static void
+avx_test (void)
+{
+  short v[16] =
+    { 
+      -3, 60, 48, 104, -90, 37, -48, 78,
+      4, 33, 81, 4, -89, 17, 8, 68
+    };
+  union256i_w u;
+
+  u.x = foo (v);
+  if (check_union256i_w (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v16hi-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v16hi-2.c
new file mode 100644
index 000000000..ac1fc458b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v16hi-2.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (short x1, short x2, short x3, short x4,
+     short x5, short x6, short x7, short x8,
+     short x9, short x10, short x11, short x12,
+     short x13, short x14, short x15, short x16)
+{
+  return _mm256_set_epi16 (x1, x2, x3, x4, x5, x6, x7, x8,
+			   x9, x10, x11, x12, x13, x14, x15, x16);
+}
+
+static void
+avx_test (void)
+{
+  short v[16] =
+    { 
+      -3, 60, 48, 104, -90, 37, -48, 78,
+      4, 33, 81, 4, -89, 17, 8, 68
+    };
+  union256i_w u;
+
+  u.x = foo (v[15], v[14], v[13], v[12],
+	     v[11], v[10], v[9], v[8],
+	     v[7], v[6], v[5], v[4],
+	     v[3], v[2], v[1], v[0]);
+  if (check_union256i_w (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v16hi-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v16hi-3.c
new file mode 100644
index 000000000..c215d5675
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v16hi-3.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (short x)
+{
+  return _mm256_set_epi16 (x, x, x, x, x, x, x, x,
+			   x, x, x, x, x, x, x, x);
+}
+
+static void
+avx_test (void)
+{
+  short e = 345;
+  short v[16];
+  union256i_w u;
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    v[i] = e;
+  u.x = foo (e);
+  if (check_union256i_w (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v16hi-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v16hi-4.c
new file mode 100644
index 000000000..a707fc8dc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v16hi-4.c
@@ -0,0 +1,83 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (short x, int i)
+{
+  switch (i)
+    {
+    case 15:
+      return _mm256_set_epi16 (x, 0, 0, 0, 0, 0, 0, 0,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 14:
+      return _mm256_set_epi16 (0, x, 0, 0, 0, 0, 0, 0,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 13:
+      return _mm256_set_epi16 (0, 0, x, 0, 0, 0, 0, 0,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 12:
+      return _mm256_set_epi16 (0, 0, 0, x, 0, 0, 0, 0,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 11:
+      return _mm256_set_epi16 (0, 0, 0, 0, x, 0, 0, 0,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 10:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, x, 0, 0,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 9:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, x, 0,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 8:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, x,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 7:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       x, 0, 0, 0, 0, 0, 0, 0);
+    case 6:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       0, x, 0, 0, 0, 0, 0, 0);
+    case 5:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       0, 0, x, 0, 0, 0, 0, 0);
+    case 4:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       0, 0, 0, x, 0, 0, 0, 0);
+    case 3:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       0, 0, 0, 0, x, 0, 0, 0);
+    case 2:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       0, 0, 0, 0, 0, x, 0, 0);
+    case 1:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       0, 0, 0, 0, 0, 0, x, 0);
+    case 0:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  short e = 0xbeef;
+  short v[16];
+  union256i_w u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 0;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_w (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v16hi-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v16hi-5.c
new file mode 100644
index 000000000..ad77eda29
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v16hi-5.c
@@ -0,0 +1,83 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (short x, int i)
+{
+  switch (i)
+    {
+    case 15:
+      return _mm256_set_epi16 (x, 1, 1, 1, 1, 1, 1, 1,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 14:
+      return _mm256_set_epi16 (1, x, 1, 1, 1, 1, 1, 1,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 13:
+      return _mm256_set_epi16 (1, 1, x, 1, 1, 1, 1, 1,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 12:
+      return _mm256_set_epi16 (1, 1, 1, x, 1, 1, 1, 1,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 11:
+      return _mm256_set_epi16 (1, 1, 1, 1, x, 1, 1, 1,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 10:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, x, 1, 1,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 9:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, x, 1,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 8:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, x,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 7:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       x, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       1, x, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       1, 1, x, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       1, 1, 1, x, 1, 1, 1, 1);
+    case 3:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       1, 1, 1, 1, x, 1, 1, 1);
+    case 2:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       1, 1, 1, 1, 1, x, 1, 1);
+    case 1:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       1, 1, 1, 1, 1, 1, x, 1);
+    case 0:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  short e = 0xbeef;
+  short v[16];
+  union256i_w u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 1;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_w (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v32qi-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v32qi-1.c
new file mode 100644
index 000000000..9d9381578
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v32qi-1.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (char *v)
+{
+  return _mm256_set_epi8 (v[31], v[30], v[29], v[28],
+			  v[27], v[26], v[25], v[24],
+			  v[23], v[22], v[21], v[20],
+			  v[19], v[18], v[17], v[16],
+			  v[15], v[14], v[13], v[12],
+			  v[11], v[10], v[9], v[8],
+			  v[7], v[6], v[5], v[4],
+			  v[3], v[2], v[1], v[0]);
+}
+
+static void
+avx_test (void)
+{
+  char v[32] =
+    { 
+      -3, 60, 48, 104, -90, 37, -48, 78,
+      4, 33, 81, 4, -89, 17, 8, 68,
+      -13, 30, 78, 149, -70, -37, 98, 38,
+      41, 73, 89, 14, 80, 117, 108, 8
+    };
+  union256i_b u;
+
+  u.x = foo (v);
+  if (check_union256i_b (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v32qi-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v32qi-2.c
new file mode 100644
index 000000000..508ed51a8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v32qi-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (char x1, char x2, char x3, char x4,
+     char x5, char x6, char x7, char x8,
+     char x9, char x10, char x11, char x12,
+     char x13, char x14, char x15, char x16,
+     char x17, char x18, char x19, char x20,
+     char x21, char x22, char x23, char x24,
+     char x25, char x26, char x27, char x28,
+     char x29, char x30, char x31, char x32)
+{
+  return _mm256_set_epi8 (x1, x2, x3, x4, x5, x6, x7, x8,
+			  x9, x10, x11, x12, x13, x14, x15, x16,
+			  x17, x18, x19, x20, x21, x22, x23, x24,
+			  x25, x26, x27, x28, x29, x30, x31, x32);
+}
+
+static void
+avx_test (void)
+{
+  char v[32] =
+    { 
+      -3, 60, 48, 104, -90, 37, -48, 78,
+      4, 33, 81, 4, -89, 17, 8, 68,
+      -13, 30, 78, 149, -70, -37, 98, 38,
+      41, 73, 89, 14, 80, 117, 108, 8
+    };
+  union256i_b u;
+
+  u.x = foo (v[31], v[30], v[29], v[28],
+	     v[27], v[26], v[25], v[24],
+	     v[23], v[22], v[21], v[20],
+	     v[19], v[18], v[17], v[16],
+	     v[15], v[14], v[13], v[12],
+	     v[11], v[10], v[9], v[8],
+	     v[7], v[6], v[5], v[4],
+	     v[3], v[2], v[1], v[0]);
+  if (check_union256i_b (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v32qi-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v32qi-3.c
new file mode 100644
index 000000000..da92c8e2c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v32qi-3.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (char x)
+{
+  return _mm256_set_epi8 (x, x, x, x, x, x, x, x,
+			  x, x, x, x, x, x, x, x,
+			  x, x, x, x, x, x, x, x,
+			  x, x, x, x, x, x, x, x);
+}
+
+static void
+avx_test (void)
+{
+  char e = -45;
+  char v[32];
+  union256i_b u;
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    v[i] = e;
+  u.x = foo (e);
+  if (check_union256i_b (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v32qi-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v32qi-4.c
new file mode 100644
index 000000000..7220695ba
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v32qi-4.c
@@ -0,0 +1,131 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (char x, int i)
+{
+  switch (i)
+    {
+    case 31:
+      return _mm256_set_epi8 (x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 30:
+      return _mm256_set_epi8 (0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 29:
+      return _mm256_set_epi8 (0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 28:
+      return _mm256_set_epi8 (0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 27:
+      return _mm256_set_epi8 (0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 26:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 25:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 24:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 23:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 22:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 21:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 20:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 19:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 18:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 17:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 16:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 15:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 14:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 13:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 12:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 11:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 10:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 9:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 8:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 7:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0);
+    case 6:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0);
+    case 5:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0);
+    case 4:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0);
+    case 3:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0);
+    case 2:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0);
+    case 1:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0);
+    case 0:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  char e = 0xa1;
+  char v[32];
+  union256i_b u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 0;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_b (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v32qi-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v32qi-5.c
new file mode 100644
index 000000000..0fcadda91
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v32qi-5.c
@@ -0,0 +1,131 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (char x, int i)
+{
+  switch (i)
+    {
+    case 31:
+      return _mm256_set_epi8 (x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 30:
+      return _mm256_set_epi8 (1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 29:
+      return _mm256_set_epi8 (1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 28:
+      return _mm256_set_epi8 (1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 27:
+      return _mm256_set_epi8 (1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 26:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 25:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 24:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 23:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 22:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 21:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 20:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 19:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 18:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 17:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 16:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 15:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 14:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 13:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 12:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 11:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 10:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 9:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 8:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 7:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1);
+    case 3:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1);
+    case 2:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1);
+    case 1:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1);
+    case 0:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  char e = 0xa1;
+  char v[32];
+  union256i_b u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 1;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_b (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4df-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4df-1.c
new file mode 100644
index 000000000..89e6ec2f3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4df-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256d
+__attribute__((noinline))
+foo (double *v)
+{
+  return _mm256_set_pd (v[3], v[2], v[1], v[0]);
+}
+
+static void
+avx_test (void)
+{
+  double v[4] = { -3, 2, 1, 9 };
+  union256d u;
+
+  u.x = foo (v);
+  if (check_union256d (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4df-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4df-2.c
new file mode 100644
index 000000000..51df025ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4df-2.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256d
+__attribute__((noinline))
+foo (double x1, double x2, double x3, double x4)
+{
+  return _mm256_set_pd (x1, x2, x3, x4);
+}
+
+static void
+avx_test (void)
+{
+  double v[4] = { -3, 2, 1, 9 };
+  union256d u;
+
+  u.x = foo (v[3], v[2], v[1], v[0]);
+  if (check_union256d (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4df-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4df-3.c
new file mode 100644
index 000000000..01b2ff51d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4df-3.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256d
+__attribute__((noinline))
+foo (double x)
+{
+  return _mm256_set_pd (x, x, x, x);
+}
+
+static void
+avx_test (void)
+{
+  double e = 34.5;
+  double v[4];
+  union256d u;
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    v[i] = e;
+  u.x = foo (e);
+  if (check_union256d (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4df-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4df-4.c
new file mode 100644
index 000000000..e2f6300a3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4df-4.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256d
+__attribute__((noinline))
+foo (double x, int i)
+{
+  switch (i)
+    {
+    case 3:
+      return _mm256_set_pd (x, 0, 0, 0);
+    case 2:
+      return _mm256_set_pd (0, x, 0, 0);
+    case 1:
+      return _mm256_set_pd (0, 0, x, 0);
+    case 0:
+      return _mm256_set_pd (0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  double e = -3.234;
+  double v[4];
+  union256d u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 0;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256d (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4df-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4df-5.c
new file mode 100644
index 000000000..6f418a668
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4df-5.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256d
+__attribute__((noinline))
+foo (double x, int i)
+{
+  switch (i)
+    {
+    case 3:
+      return _mm256_set_pd (x, 1, 1, 1);
+    case 2:
+      return _mm256_set_pd (1, x, 1, 1);
+    case 1:
+      return _mm256_set_pd (1, 1, x, 1);
+    case 0:
+      return _mm256_set_pd (1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  double e = -3.234;
+  double v[4];
+  union256d u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 1;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256d (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4di-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4di-1.c
new file mode 100644
index 000000000..84b6278a3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4di-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (long long *v)
+{
+  return _mm256_set_epi64x (v[3], v[2], v[1], v[0]);
+}
+
+static void
+avx_test (void)
+{
+  long long v[4]
+    = { 0x12e9e94645ad8LL, 0x851c0b39446LL,
+	0x786784645245LL, 0x9487731234LL };
+  union256i_q u;
+
+  u.x = foo (v);
+  if (check_union256i_q (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4di-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4di-2.c
new file mode 100644
index 000000000..f3dc138a8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4di-2.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (long long x1, long long x2, long long x3, long long x4)
+{
+  return _mm256_set_epi64x (x1, x2, x3, x4);
+}
+
+static void
+avx_test (void)
+{
+  long long v[4]
+    = { 0x12e9e94645ad8LL, 0x851c0b39446LL,
+	0x786784645245LL, 0x9487731234LL };
+  union256i_q u;
+
+  u.x = foo (v[3], v[2], v[1], v[0]);
+  if (check_union256i_q (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4di-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4di-3.c
new file mode 100644
index 000000000..95710d822
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4di-3.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (long long x)
+{
+  return _mm256_set_epi64x (x, x, x, x);
+}
+
+static void
+avx_test (void)
+{
+  long long e = 0xfed178ab134badf1LL;
+  long long v[4];
+  union256i_q u;
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    v[i] = e;
+  u.x = foo (e);
+  if (check_union256i_q (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4di-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4di-4.c
new file mode 100644
index 000000000..83f8c15fa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4di-4.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (long long x, int i)
+{
+  switch (i)
+    {
+    case 3:
+      return _mm256_set_epi64x (x, 0, 0, 0);
+    case 2:
+      return _mm256_set_epi64x (0, x, 0, 0);
+    case 1:
+      return _mm256_set_epi64x (0, 0, x, 0);
+    case 0:
+      return _mm256_set_epi64x (0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  long long e = 0xabadbeef01234567LL;
+  long long v[4];
+  union256i_q u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 0;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_q (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4di-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4di-5.c
new file mode 100644
index 000000000..7bc260c7b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v4di-5.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (long long x, int i)
+{
+  switch (i)
+    {
+    case 3:
+      return _mm256_set_epi64x (x, 1, 1, 1);
+    case 2:
+      return _mm256_set_epi64x (1, x, 1, 1);
+    case 1:
+      return _mm256_set_epi64x (1, 1, x, 1);
+    case 0:
+      return _mm256_set_epi64x (1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  long long e = 0xabadbeef01234567LL;
+  long long v[4];
+  union256i_q u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 1;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_q (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8sf-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8sf-1.c
new file mode 100644
index 000000000..6f1ba7101
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8sf-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256 
+__attribute__((noinline))
+foo (float *v)
+{
+  return _mm256_set_ps (v[7], v[6], v[5], v[4],
+			v[3], v[2], v[1], v[0]);
+}
+
+static void
+avx_test (void)
+{
+  float v[8] = { -3, 2, 1, 9, 23, -173, -13, 69 };
+  union256 u;
+
+  u.x = foo (v);
+  if (check_union256 (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8sf-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8sf-2.c
new file mode 100644
index 000000000..4d809d7ca
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8sf-2.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+__m256
+__attribute__((noinline))
+foo (float x1, float x2, float x3, float x4,
+     float x5, float x6, float x7, float x8)
+{
+  return _mm256_set_ps (x1, x2, x3, x4, x5, x6, x7, x8);
+}
+
+void
+avx_test (void)
+{
+  float v[8] = { -3, 2, 1, 9, 23, -173, -13, 69 };
+  union256 u;
+
+  u.x = foo (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+
+  if (check_union256 (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8sf-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8sf-3.c
new file mode 100644
index 000000000..96f5e3318
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8sf-3.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256
+__attribute__((noinline))
+foo (float x)
+{
+  return _mm256_set_ps (x, x, x, x, x, x, x, x);
+}
+
+static void
+avx_test (void)
+{
+  float e = 34.5;
+  float v[8];
+  union256 u;
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    v[i] = e;
+  u.x = foo (e);
+  if (check_union256 (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8sf-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8sf-4.c
new file mode 100644
index 000000000..73be30369
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8sf-4.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256
+__attribute__((noinline))
+foo (float x, int i)
+{
+  switch (i)
+    {
+    case 7:
+      return _mm256_set_ps (x, 0, 0, 0, 0, 0, 0, 0);
+    case 6:
+      return _mm256_set_ps (0, x, 0, 0, 0, 0, 0, 0);
+    case 5:
+      return _mm256_set_ps (0, 0, x, 0, 0, 0, 0, 0);
+    case 4:
+      return _mm256_set_ps (0, 0, 0, x, 0, 0, 0, 0);
+    case 3:
+      return _mm256_set_ps (0, 0, 0, 0, x, 0, 0, 0);
+    case 2:
+      return _mm256_set_ps (0, 0, 0, 0, 0, x, 0, 0);
+    case 1:
+      return _mm256_set_ps (0, 0, 0, 0, 0, 0, x, 0);
+    case 0:
+      return _mm256_set_ps (0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  float e = -3.234;
+  float v[8];
+  union256 u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 0;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256 (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8sf-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8sf-5.c
new file mode 100644
index 000000000..80dc156d5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8sf-5.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256
+__attribute__((noinline))
+foo (float x, int i)
+{
+  switch (i)
+    {
+    case 7:
+      return _mm256_set_ps (x, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm256_set_ps (1, x, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm256_set_ps (1, 1, x, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm256_set_ps (1, 1, 1, x, 1, 1, 1, 1);
+    case 3:
+      return _mm256_set_ps (1, 1, 1, 1, x, 1, 1, 1);
+    case 2:
+      return _mm256_set_ps (1, 1, 1, 1, 1, x, 1, 1);
+    case 1:
+      return _mm256_set_ps (1, 1, 1, 1, 1, 1, x, 1);
+    case 0:
+      return _mm256_set_ps (1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  float e = -3.234;
+  float v[8];
+  union256 u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 1;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256 (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8si-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8si-1.c
new file mode 100644
index 000000000..7aa029ea5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8si-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (int *v)
+{
+  return _mm256_set_epi32 (v[7], v[6], v[5], v[4],
+			   v[3], v[2], v[1], v[0]);
+}
+
+static void
+avx_test (void)
+{
+  int v[8]
+    = { 19832468, 6576856, 8723467, 234566,
+	786784, 645245, 948773, 1234 };
+  union256i_d u;
+
+  u.x = foo (v);
+  if (check_union256i_d (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8si-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8si-2.c
new file mode 100644
index 000000000..e822c785b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8si-2.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+__m256i
+__attribute__((noinline))
+foo (int x1, int x2, int x3, int x4,
+     int x5, int x6, int x7, int x8)
+{
+  return _mm256_set_epi32 (x1, x2, x3, x4, x5, x6, x7, x8);
+}
+
+static void
+avx_test (void)
+{
+  int v[8] = { -3, 2, 1, 9, 23, -173, -13, 69 };
+  union256i_d u;
+
+  u.x = foo (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+
+  if (check_union256i_d (u, v))
+     abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8si-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8si-3.c
new file mode 100644
index 000000000..594436b37
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8si-3.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (int x)
+{
+  return _mm256_set_epi32 (x, x, x, x, x, x, x, x);
+}
+
+static void
+avx_test (void)
+{
+  int e = 0xabadbeef;
+  int v[8];
+  union256i_d u;
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    v[i] = e;
+  u.x = foo (e);
+  if (check_union256i_d (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8si-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8si-4.c
new file mode 100644
index 000000000..2cad62769
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8si-4.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (int x, int i)
+{
+  switch (i)
+    {
+    case 7:
+      return _mm256_set_epi32 (x, 0, 0, 0, 0, 0, 0, 0);
+    case 6:
+      return _mm256_set_epi32 (0, x, 0, 0, 0, 0, 0, 0);
+    case 5:
+      return _mm256_set_epi32 (0, 0, x, 0, 0, 0, 0, 0);
+    case 4:
+      return _mm256_set_epi32 (0, 0, 0, x, 0, 0, 0, 0);
+    case 3:
+      return _mm256_set_epi32 (0, 0, 0, 0, x, 0, 0, 0);
+    case 2:
+      return _mm256_set_epi32 (0, 0, 0, 0, 0, x, 0, 0);
+    case 1:
+      return _mm256_set_epi32 (0, 0, 0, 0, 0, 0, x, 0);
+    case 0:
+      return _mm256_set_epi32 (0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  int e = 0xabadbeef;
+  int v[8];
+  union256i_d u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 0;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_d (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8si-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8si-5.c
new file mode 100644
index 000000000..456e87772
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set-v8si-5.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (int x, int i)
+{
+  switch (i)
+    {
+    case 7:
+      return _mm256_set_epi32 (x, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm256_set_epi32 (1, x, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm256_set_epi32 (1, 1, x, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm256_set_epi32 (1, 1, 1, x, 1, 1, 1, 1);
+    case 3:
+      return _mm256_set_epi32 (1, 1, 1, 1, x, 1, 1, 1);
+    case 2:
+      return _mm256_set_epi32 (1, 1, 1, 1, 1, x, 1, 1);
+    case 1:
+      return _mm256_set_epi32 (1, 1, 1, 1, 1, 1, x, 1);
+    case 0:
+      return _mm256_set_epi32 (1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  int e = 0xabadbeef;
+  int v[8];
+  union256i_d u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 1;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_d (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set1-epi32-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set1-epi32-1.c
new file mode 100644
index 000000000..2d774aef3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set1-epi32-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256i_d u;
+  int e [8];
+  int source[1] = {1234};
+
+  u.x = _mm256_set1_epi32 (source[0]);
+
+  for (i = 0; i < 8; i++)
+    e[i] = source[0];
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set1-pd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set1-pd-256-1.c
new file mode 100644
index 000000000..21aea2940
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set1-pd-256-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u;
+  double e [4];
+  double source[1] = {26156.643};
+
+  u.x = _mm256_set1_pd (source[0]);
+
+  for (i = 0; i < 4; i++)
+    e[i] = source[0];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set1-ps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set1-ps-256-1.c
new file mode 100644
index 000000000..c5f2d1023
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-set1-ps-256-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u;
+  float e [8];
+  float	 source[1] = {1234.234f};
+
+  u.x = _mm256_set1_ps (source[0]);
+
+  for (i = 0; i < 8; i++)
+    e[i] = source[0];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-setzero-pd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-setzero-pd-256-1.c
new file mode 100644
index 000000000..43656cf81
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-setzero-pd-256-1.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u;
+  double e [4];
+
+  u.x = _mm256_setzero_pd ();
+
+  for (i = 0; i < 4; i++)
+    e[i] = 0.0;
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-setzero-ps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-setzero-ps-256-1.c
new file mode 100644
index 000000000..ffbf431fc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-setzero-ps-256-1.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u;
+  float e [8];
+
+  u.x = _mm256_setzero_ps ();
+
+  for (i = 0; i < 8; i++)
+    e[i] = 0.0;
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-setzero-si256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-setzero-si256-1.c
new file mode 100644
index 000000000..01eef2a4e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-setzero-si256-1.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256i_q u;
+  long long e [4];
+
+  u.x = _mm256_setzero_si256 ();
+
+  for (i = 0; i < 4; i++)
+    e[i] = 0;
+
+  if (check_union256i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddpd-1.c
new file mode 100644
index 000000000..afed3d035
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-addpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddpd-256-1.c
new file mode 100644
index 000000000..2d0394354
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddpd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_add_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddps-1.c
new file mode 100644
index 000000000..ba905097f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-addps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddps-256-1.c
new file mode 100644
index 000000000..363a4dedb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddps-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_add_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddsd-1.c
new file mode 100644
index 000000000..5c562a01d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-addsd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddss-1.c
new file mode 100644
index 000000000..093f61b63
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-addss-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-1.c
new file mode 100644
index 000000000..7c0fc2fdf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -mfpmath=sse" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-addsubpd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-256-1.c
new file mode 100644
index 000000000..7f431ec36
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-256-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_addsub_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    if (i % 2)
+      e[i] = s1.a[i] + s2.a[i];
+    else 
+      e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddsubps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddsubps-1.c
new file mode 100644
index 000000000..1dbe3f353
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddsubps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -mfpmath=sse" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-addsubps.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddsubps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddsubps-256-1.c
new file mode 100644
index 000000000..e6977f9b9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaddsubps-256-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_addsub_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    if (i % 2)
+      e[i] = s1.a[i] + s2.a[i];
+    else 
+      e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaesdec-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaesdec-1.c
new file mode 100644
index 000000000..c926dd197
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaesdec-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vaes } */
+/* { dg-options "-O2 -maes -mavx" } */
+
+#define CHECK_H "aes-avx-check.h"
+#define TEST aes_avx_test
+
+#include "aesdec.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaesdeclast-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaesdeclast-1.c
new file mode 100644
index 000000000..467462606
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaesdeclast-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vaes } */
+/* { dg-options "-O2 -maes -mavx" } */
+
+#define CHECK_H "aes-avx-check.h"
+#define TEST aes_avx_test
+
+#include "aesdeclast.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaesenc-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaesenc-1.c
new file mode 100644
index 000000000..313f10105
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaesenc-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vaes } */
+/* { dg-options "-O2 -maes -mavx" } */
+
+#define CHECK_H "aes-avx-check.h"
+#define TEST aes_avx_test
+
+#include "aesenc.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaesenclast-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaesenclast-1.c
new file mode 100644
index 000000000..0df9130ad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaesenclast-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vaes } */
+/* { dg-options "-O2 -maes -mavx" } */
+
+#define CHECK_H "aes-avx-check.h"
+#define TEST aes_avx_test
+
+#include "aesenclast.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaesimc-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaesimc-1.c
new file mode 100644
index 000000000..29f910a47
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaesimc-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vaes } */
+/* { dg-options "-O2 -maes -mavx" } */
+
+#define CHECK_H "aes-avx-check.h"
+#define TEST aes_avx_test
+
+#include "aesimc.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaeskeygenassist-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaeskeygenassist-1.c
new file mode 100644
index 000000000..7c0d564a3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vaeskeygenassist-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vaes } */
+/* { dg-options "-O2 -maes -mavx" } */
+
+#define CHECK_H "aes-avx-check.h"
+#define TEST aes_avx_test
+
+#include "aeskeygenassist.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandnpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandnpd-1.c
new file mode 100644
index 000000000..c5f3c1d38
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandnpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-andnpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandnpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandnpd-256-1.c
new file mode 100644
index 000000000..27e4ccdd1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandnpd-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  long long source1[4]={34545, 95567, 23443, 5675};
+  long long source2[4]={674, 57897, 93459, 45624};
+  long long d[4];
+  long long e[4];
+
+  s1.x = _mm256_loadu_pd ((double *)source1);
+  s2.x = _mm256_loadu_pd ((double *)source2);
+  u.x = _mm256_andnot_pd (s1.x, s2.x);
+
+  _mm256_storeu_pd ((double *)d, u.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (~source1[i]) & source2[i];
+
+  if (checkVl (d, e, 4))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandnps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandnps-1.c
new file mode 100644
index 000000000..357db7e8d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandnps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-andnps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandnps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandnps-256-1.c
new file mode 100644
index 000000000..7b5a3dbe8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandnps-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  int source1[8]={34545, 95567, 23443, 5675, 2323, 67, 2345, 45667};
+  int source2[8]={674, 57897, 93459, 45624, 54674, 1237, 67436, 79608};
+  int d[8];
+  int e[8];
+
+  s1.x = _mm256_loadu_ps ((float *)source1);
+  s2.x = _mm256_loadu_ps ((float *)source2);
+  u.x = _mm256_andnot_ps (s1.x, s2.x);
+
+  _mm256_storeu_ps ((float *)d, u.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = (~source1[i]) & source2[i];
+
+  if (checkVi (d, e, 8))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandpd-1.c
new file mode 100644
index 000000000..0a9532d5d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-andpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandpd-256-1.c
new file mode 100644
index 000000000..b0675ec65
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandpd-256-1.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+
+  union
+  {
+     double d[4];
+     long long ll[4];
+  }source1, source2, e;
+
+  s1.x = _mm256_set_pd (345.45, 95567, 2344.3, 567.5);
+  s2.x = _mm256_set_pd (674, 57.897, 934.59, 4562.4);
+
+  _mm256_storeu_pd (source1.d, s1.x);
+  _mm256_storeu_pd (source2.d, s2.x);
+
+  u.x = _mm256_and_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e.ll[i] = source1.ll[i] & source2.ll[i];
+
+  if (check_union256d (u, e.d))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandps-1.c
new file mode 100644
index 000000000..54bba79ab
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-andps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandps-256-1.c
new file mode 100644
index 000000000..4dc123bf3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vandps-256-1.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  
+  union
+  {
+    float f[8];
+    int   i[8];
+  }source1, source2, e;
+
+  s1.x = _mm256_set_ps (34545, 95567, 23443, 5675, 2323, 67, 2345, 45667);
+  s2.x = _mm256_set_ps (674, 57897, 93459, 45624, 54674, 1237, 67436, 79608);
+  
+  _mm256_storeu_ps (source1.f, s1.x);
+  _mm256_storeu_ps (source2.f, s2.x);
+
+  u.x = _mm256_and_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e.i[i] = source1.i[i] & source2.i[i];
+
+  if (check_union256 (u, e.f))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vblendpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vblendpd-1.c
new file mode 100644
index 000000000..0a9031f44
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vblendpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-blendpd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vblendpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vblendpd-256-1.c
new file mode 100644
index 000000000..39e7c1bd5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vblendpd-256-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 12
+#endif
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (34545, 95567, 23443, 5675);
+  s2.x = _mm256_set_pd (674, 57897, 93459, 45624);
+  u.x = _mm256_blend_pd (s1.x, s2.x, MASK);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (MASK & (0x01 << i)) ? s2.a[i] : s1.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vblendps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vblendps-256-1.c
new file mode 100644
index 000000000..9f5dde29f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vblendps-256-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 114
+#endif
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (34545, 95567, 23443, 5675, 2323, 67, 2345, 45667);
+  s2.x = _mm256_set_ps (674, 57897, 93459, 45624, 54674, 1237, 67436, 79608);
+  u.x = _mm256_blend_ps (s1.x, s2.x, MASK);
+
+  for (i = 0; i < 8; i++)
+    e[i] = (MASK & (0x01 << i)) ? s2.a[i] : s1.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vblendvpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vblendvpd-256-1.c
new file mode 100644
index 000000000..2f668c22e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vblendvpd-256-1.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 6
+#endif
+
+#define mask_v(pos) (((MASK >> (pos)) & 1ULL) << 63)
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, mask, s1, s2;
+  long long m[4]={mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
+  double e [4];
+
+  s1.x = _mm256_set_pd (34545, 95567, 23443, 5675);
+  s2.x = _mm256_set_pd (674, 57897, 93459, 45624);
+  mask.x = _mm256_set_pd (m[0], m[1], m[2], m[3]);
+
+  u.x = _mm256_blendv_pd (s1.x, s2.x, mask.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (m[i] & (1ULL << 63)) ? s2.a[i] : s1.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vblendvps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vblendvps-256-1.c
new file mode 100644
index 000000000..0e48d690e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vblendvps-256-1.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 214
+#endif
+
+#define mask_v(pos) (((MASK >> (pos)) & 1U) << 31)
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, mask, s1, s2;
+  int m[8]={mask_v(0), mask_v(1), mask_v(2), mask_v(3), 
+            mask_v(4), mask_v(5), mask_v(6), mask_v(7)};
+  float e [8];
+
+  s1.x = _mm256_set_ps (34545, 95567, 23443, 5675, 2323, 67, 2345, 45667);
+  s2.x = _mm256_set_ps (674, 57897, 93459, 45624, 54674, 1237, 67436, 79608);
+  mask.x = _mm256_loadu_ps ((float *)m);
+
+  u.x = _mm256_blendv_ps (s1.x, s2.x, mask.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = (m[i] & (1ULL << 31)) ? s2.a[i] : s1.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-1.c
new file mode 100644
index 000000000..e0cddd1a9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u;
+  union128 s;
+  float e [8];
+
+  s.x = _mm_set_ps(24.43, 68.346, 43.35, 546.46);
+  u.x = _mm256_broadcast_ps (&s.x);
+
+  for (i = 0; i < 4; i++)
+    e[i+4] = e[i] = s.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-2.c
new file mode 100644
index 000000000..eb4ec579b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-2.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u;
+  union128d s;
+  double e [4];
+
+  s.x = _mm_set_pd(24.43, 68.346);
+  u.x = _mm256_broadcast_pd (&s.x);
+
+  e[0] = e[2] = s.a[0];
+  e[1] = e[3] = s.a[1];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vbroadcastsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vbroadcastsd-1.c
new file mode 100644
index 000000000..329405f31
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vbroadcastsd-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  double s = 39678;
+  union256d u;
+  double e [4];
+
+  u.x = _mm256_broadcast_sd (&s);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s;
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-1.c
new file mode 100644
index 000000000..d6bf2ce61
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  float s = 39678.3452;
+  union256 u;
+  float e [8];
+
+  u.x = _mm256_broadcast_ss (&s);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s;
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-2.c
new file mode 100644
index 000000000..56723cb28
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-2.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  float s = 39678.3452;
+  union128 u;
+  float e [4];
+
+  u.x = _mm_broadcast_ss (&s);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s;
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmppd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmppd-1.c
new file mode 100644
index 000000000..be69d47e8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmppd-1.c
@@ -0,0 +1,78 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -std=c99" } */
+
+#include "avx-check.h"
+#include <math.h>
+
+double s1[2]={2134.3343,6678.346};
+double s2[2]={41124.234,6678.346};
+long long  e[2];
+
+union
+{
+  double d[2];
+  long long ll[2];
+}d;
+
+void check(unsigned imm, char *id)
+{
+    if(checkVl(d.ll, e, 2)){
+	printf("mm_cmp_pd(%s: 0x%x) FAILED\n", id, imm);
+    }
+}
+
+#define CMP(imm, rel)					\
+    for (i = 0; i < 2; i++) e[i] = rel ? -1 : 0;	\
+    source1 = _mm_loadu_pd(s1);				\
+    source2 = _mm_loadu_pd(s2);				\
+    dest = _mm_cmp_pd(source1, source2, imm);		\
+    _mm_storeu_pd(d.d, dest);			\
+    check(imm, "" #imm "");
+
+static void
+avx_test ()
+{
+    __m128d source1, source2, dest;
+    int i;
+
+    d.ll[0] = e[0] = 222;
+    d.ll[1] = e[1] = -33;
+    
+    CMP(_CMP_EQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OS, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OS, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_US, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_US, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[i], s2[i]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_US, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_US, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OS, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OS, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_S, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_US, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_S, !isunordered(s1[i], s2[i]));
+    CMP(_CMP_EQ_US, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_US, 1);
+    
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmppd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmppd-256-1.c
new file mode 100644
index 000000000..7000bb07f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmppd-256-1.c
@@ -0,0 +1,75 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -std=c99" } */
+
+#include "avx-check.h"
+#include <math.h>
+
+double s1[4]={2134.3343,6678.346,453.345635,54646.464356};
+double s2[4]={41124.234,6678.346,8653.65635,856.43576};
+long long e[4];
+
+union
+{
+  double d[4];
+  long long ll[4];
+}d;
+
+void check(unsigned imm, char *id)
+{
+    if(checkVl(d.ll, e, 4)){
+	printf("mm256_cmp_pd(%s: 0x%x) FAILED\n", id, imm);
+    }
+}
+
+#define CMP(imm, rel)					\
+    for (i = 0; i < 4; i++) e[i] = rel ? -1 : 0;	\
+    source1 = _mm256_loadu_pd(s1);			\
+    source2 = _mm256_loadu_pd(s2);			\
+    dest = _mm256_cmp_pd(source1, source2, imm);	\
+    _mm256_storeu_pd(d.d, dest);		\
+    check(imm, "" #imm "");
+
+static void
+avx_test ()
+{
+    __m256d source1, source2, dest;
+    int i;
+    
+    CMP(_CMP_EQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OS, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OS, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_US, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_US, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[i], s2[i]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_US, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_US, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OS, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OS, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_S, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_US, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_S, !isunordered(s1[i], s2[i]));
+    CMP(_CMP_EQ_US, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_US, 1);
+
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmpps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmpps-1.c
new file mode 100644
index 000000000..753f2ce64
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmpps-1.c
@@ -0,0 +1,74 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -std=c99" } */
+
+#include "avx-check.h"
+#include <math.h>
+
+float s1[4]={2134.3343,6678.346,453.345635,54646.464356};
+float s2[4]={41124.234,6678.346,8653.65635,856.43576};
+int e[4];
+
+union
+{
+  float f[4];
+  int   i[4];
+}d;
+
+void check(unsigned imm, char *id)
+{
+    if(checkVi(d.i, e, 4)){
+	printf("mm_cmp_ps(0x%x, %s) FAILED\n", imm, id);
+    }
+}
+
+static void
+avx_test ()
+{
+    __m128 source1, source2, dest;
+    int i;
+
+#define CMP(imm, rel)					\
+    for (i = 0; i < 4; i++) e[i] = rel ? -1 : 0;	\
+    source1 = _mm_loadu_ps(s1);				\
+    source2 = _mm_loadu_ps(s2);				\
+    dest = _mm_cmp_ps(source1, source2, imm);		\
+    _mm_storeu_ps(d.f, dest);			\
+    check(imm, "" #imm "");
+
+    CMP(_CMP_EQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OS, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OS, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_US, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_US, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[i], s2[i]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_US, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_US, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OS, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OS, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_S, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_US, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_S, !isunordered(s1[i], s2[i]));
+    CMP(_CMP_EQ_US, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_US, 1);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmpps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmpps-256-1.c
new file mode 100644
index 000000000..c1292a255
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmpps-256-1.c
@@ -0,0 +1,74 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -std=c99" } */
+
+#include "avx-check.h"
+#include <math.h>
+
+float s1[8]={2134.3343,6678.346,453.345635,54646.464356,456,678567,123,2346};
+float s2[8]={41124.234,6678.346,8653.65635,856.43576,7456,134,539,54674};
+int e[8];
+
+union
+{
+  float f[8];
+  int   i[8];
+}d;
+
+void check(unsigned imm, char *id)
+{
+    if(checkVi(d.i, e, 8)){
+	printf("mm256_cmp_ps(0x%x, %s) FAILED\n", imm, id);
+    }
+}
+
+static void
+avx_test ()
+{
+    __m256 source1, source2, dest;
+    int i;
+
+#define CMP(imm, rel)					\
+    for (i = 0; i < 8; i++) e[i] = rel ? -1 : 0;	\
+    source1 = _mm256_loadu_ps(s1);			\
+    source2 = _mm256_loadu_ps(s2);			\
+    dest = _mm256_cmp_ps(source1, source2, imm);	\
+    _mm256_storeu_ps(d.f, dest);		        \
+    check(imm, "" #imm "");
+
+    CMP(_CMP_EQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OS, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OS, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_US, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_US, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[i], s2[i]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_US, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_US, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OS, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OS, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_S, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_US, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_S, !isunordered(s1[i], s2[i]));
+    CMP(_CMP_EQ_US, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_US, 1);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmpsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmpsd-1.c
new file mode 100644
index 000000000..97ca6e6c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmpsd-1.c
@@ -0,0 +1,71 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -std=c99" } */
+
+#include "avx-check.h"
+#include <math.h>
+
+double s1[] = {2134.3343, 6678.346};
+double s2[] = {41124.234, 6678.346};
+long long dd[] =  {1, 2}, d[2];
+union{long long l[2]; double d[2];} e;
+
+void check(unsigned imm, char *id)
+{
+    if(checkVl(d, e.l, 2)){
+	printf("mm_cmp_sd(%s: 0x%x) FAILED\n", id, imm);
+    }
+}
+
+#define CMP(imm, rel)					\
+    e.l[0] = rel ? -1 : 0;	                        \
+    dest = _mm_loadu_pd((double*)dd);	      		\
+    source1 = _mm_loadu_pd(s1);				\
+    source2 = _mm_loadu_pd(s2);				\
+    dest = _mm_cmp_sd(source1, source2, imm);		\
+    _mm_storeu_pd((double*) d, dest);			\
+    check(imm, "" #imm "");
+
+static void
+avx_test ()
+{
+    __m128d source1, source2, dest;
+
+    e.d[1] = s1[1];
+    
+    CMP(_CMP_EQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]);
+    CMP(_CMP_LT_OS, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(_CMP_LE_OS, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[0], s2[0]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[0], s2[0]) || s1[0] != s2[0]);
+    CMP(_CMP_NLT_US, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(_CMP_NLE_US, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[0], s2[0]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[0], s2[0]) || s1[0] == s2[0]);
+    CMP(_CMP_NGE_US, isunordered(s1[0], s2[0]) || s1[0] < s2[0]);
+    CMP(_CMP_NGT_US, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]);
+    CMP(_CMP_GE_OS, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]);
+    CMP(_CMP_GT_OS, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+    CMP(_CMP_UNORD_S, isunordered(s1[0], s2[0]));
+    CMP(_CMP_NEQ_US, isunordered(s1[0], s2[0]) || s1[0] != s2[0]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(_CMP_ORD_S, !isunordered(s1[0], s2[0]));
+    CMP(_CMP_EQ_US, isunordered(s1[0], s2[0]) || s1[0] == s2[0]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[0], s2[0]) || s1[0] < s2[0]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]);
+    CMP(_CMP_TRUE_US, 1);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmpss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmpss-1.c
new file mode 100644
index 000000000..627333a86
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcmpss-1.c
@@ -0,0 +1,73 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -std=c99" } */
+
+#include "avx-check.h"
+#include <math.h>
+
+float s1[]={2134.3343, 6678.346, 453.345635, 54646.464356};
+float s2[]={41124.234, 6678.346, 8653.65635, 856.43576};
+int dd[] = {1, 2, 3, 4};
+float d[4];
+union{int i[4]; float f[4];} e;
+
+void check(unsigned imm, char *id)
+{
+    if(checkVi((int*)d, e.i, 4)){
+	printf("mm_cmp_ss(0x%x, %s) FAILED\n", imm, id);
+    }
+}
+
+static void
+avx_test ()
+{
+    __m128 source1, source2, dest;
+    int i;
+
+#define CMP(imm, rel)					\
+    e.i[0] = rel ? -1 : 0;	                        \
+    dest = _mm_loadu_ps((float*)dd);			\
+    source1 = _mm_loadu_ps(s1);				\
+    source2 = _mm_loadu_ps(s2);				\
+    dest = _mm_cmp_ss(source1, source2, imm);		\
+    _mm_storeu_ps(d, dest);			        \
+    check(imm, "" #imm "");
+
+    for(i = 1; i < 4; i++) e.f[i] = s1[i];
+    
+    CMP(_CMP_EQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]);
+    CMP(_CMP_LT_OS, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(_CMP_LE_OS, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[0], s2[0]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[0], s2[0]) || s1[0] != s2[0]);
+    CMP(_CMP_NLT_US, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(_CMP_NLE_US, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[0], s2[0]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[0], s2[0]) || s1[0] == s2[0]);
+    CMP(_CMP_NGE_US, isunordered(s1[0], s2[0]) || s1[0] < s2[0]);
+    CMP(_CMP_NGT_US, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]);
+    CMP(_CMP_GE_OS, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]);
+    CMP(_CMP_GT_OS, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+    CMP(_CMP_UNORD_S, isunordered(s1[0], s2[0]));
+    CMP(_CMP_NEQ_US, isunordered(s1[0], s2[0]) || s1[0] != s2[0]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(_CMP_ORD_S, !isunordered(s1[0], s2[0]));
+    CMP(_CMP_EQ_US, isunordered(s1[0], s2[0]) || s1[0] == s2[0]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[0], s2[0]) || s1[0] < s2[0]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]);
+    CMP(_CMP_TRUE_US, 1);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-1.c
new file mode 100644
index 000000000..419249b46
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-comisd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-2.c
new file mode 100644
index 000000000..9f757ef04
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-comisd-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-3.c
new file mode 100644
index 000000000..3bb5453c2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-comisd-3.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-4.c
new file mode 100644
index 000000000..f5c7a5d3b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-4.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-comisd-4.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-5.c
new file mode 100644
index 000000000..314cb09ee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-5.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-comisd-5.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-6.c
new file mode 100644
index 000000000..72f54138f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomisd-6.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-comisd-6.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-1.c
new file mode 100644
index 000000000..6b214fd11
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-comiss-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-2.c
new file mode 100644
index 000000000..f83b977a4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-comiss-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-3.c
new file mode 100644
index 000000000..a2db9e91c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-comiss-3.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-4.c
new file mode 100644
index 000000000..530dfc0c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-4.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-comiss-4.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-5.c
new file mode 100644
index 000000000..b149736b3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-5.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-comiss-5.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-6.c
new file mode 100644
index 000000000..45e94daf3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcomiss-6.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-comiss-6.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-1.c
new file mode 100644
index 000000000..5d08be902
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtdq2pd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-256-1.c
new file mode 100644
index 000000000..4b39ffe9a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union128i_d s1;
+  union256d u;
+  double e [4];
+
+  s1.x = _mm_set_epi32 (2134.3343,1234.635654,453.345635,54646.464356);
+  u.x = _mm256_cvtepi32_pd (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (double)s1.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtdq2ps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtdq2ps-1.c
new file mode 100644
index 000000000..1e2ad6254
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtdq2ps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtdq2ps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-1.c
new file mode 100644
index 000000000..752497514
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtpd2dq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-256-1.c
new file mode 100644
index 000000000..30e93af92
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d s1;
+  union128i_d u;
+  int e [4];
+
+  s1.x = _mm256_set_pd (2.78, 7777768.82, 23.67, 536.46);
+  u.x = _mm256_cvtpd_epi32 (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (int)(s1.a[i] + 0.5);
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-1.c
new file mode 100644
index 000000000..5bc43d561
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtpd2ps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-256-1.c
new file mode 100644
index 000000000..987f2b263
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d s1;
+  union128 u;
+  float e [4];
+
+  s1.x = _mm256_set_pd (2.43, 68.46, 23.35, 536.46);
+  u.x = _mm256_cvtpd_ps (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (float)s1.a[i];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-1.c
new file mode 100644
index 000000000..36d90a265
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtps2dq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-256-1.c
new file mode 100644
index 000000000..47ec12b8d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 s1;
+  union256i_d u;
+  int e [8];
+
+  s1.x = _mm256_set_ps (2.78, 77768.82, 23.67, 536.46, 4564.6575, 568.1263, 9889.2422, 7352.4563);
+  u.x = _mm256_cvtps_epi32 (s1.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = (int)(s1.a[i] + 0.5);
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-1.c
new file mode 100644
index 000000000..114a71976
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtps2pd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-256-1.c
new file mode 100644
index 000000000..9d48998a3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union128 s1;
+  union256d u;
+  double e [4];
+
+  s1.x = _mm_set_ps (2.43, 68.46, 23.35, 536.46);
+  u.x = _mm256_cvtps_pd (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (double)s1.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-1.c
new file mode 100644
index 000000000..53c61a2ea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtsd2si-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-2.c
new file mode 100644
index 000000000..a5b04fa5e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-2.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtsd2si-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsd2ss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsd2ss-1.c
new file mode 100644
index 000000000..c0e224d06
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsd2ss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtsd2ss-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-1.c
new file mode 100644
index 000000000..35da346d6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtsi2sd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-2.c
new file mode 100644
index 000000000..49096cfce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-2.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtsi2sd-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-1.c
new file mode 100644
index 000000000..12ac36c72
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-cvtsi2ss-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-2.c
new file mode 100644
index 000000000..765c455f8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-2.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-cvtsi2ss-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtss2sd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtss2sd-1.c
new file mode 100644
index 000000000..0f6365c35
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtss2sd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtss2sd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-1.c
new file mode 100644
index 000000000..3a51ff168
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-cvtss2si-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-2.c
new file mode 100644
index 000000000..5160b8de1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-2.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-cvtss2si-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-1.c
new file mode 100644
index 000000000..f27160a6b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvttpd2dq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-256-1.c
new file mode 100644
index 000000000..16edf8ac7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d s1;
+  union128i_d u;
+  int e [4];
+
+  s1.x = _mm256_set_pd (2.43, 68.78, 23.61, 536.46);
+  u.x = _mm256_cvttpd_epi32 (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (int)s1.a[i];
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-1.c
new file mode 100644
index 000000000..f8ab025db
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvttps2dq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-256-1.c
new file mode 100644
index 000000000..0a580f015
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 s1;
+  union256i_d u;
+  int e [8];
+
+  s1.x = _mm256_set_ps (45.64, 4564.56, 2.3, 5.5, 57.57, 89.34, 54.12, 954.67);
+  u.x = _mm256_cvttps_epi32 (s1.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = (int)s1.a[i];
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-1.c
new file mode 100644
index 000000000..b9963d4ab
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvttsd2si-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-2.c
new file mode 100644
index 000000000..dcf487afb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-2.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvttsd2si-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-1.c
new file mode 100644
index 000000000..94c94c1d6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-cvttss2si-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-2.c
new file mode 100644
index 000000000..14b072146
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-2.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-cvttss2si-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivpd-1.c
new file mode 100644
index 000000000..57ddfd1f7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-divpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivpd-256-1.c
new file mode 100644
index 000000000..1840e3d56
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivpd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_div_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] / s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivps-1.c
new file mode 100644
index 000000000..d4fcaebdf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-divps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivps-256-1.c
new file mode 100644
index 000000000..3ff4c7ee2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivps-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e[8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_div_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i] / s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivsd-1.c
new file mode 100644
index 000000000..faca3ed1c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-divsd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivss-1.c
new file mode 100644
index 000000000..f5740eba4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdivss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-divss-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdppd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdppd-1.c
new file mode 100644
index 000000000..7d04cc4bc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdppd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-dppd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdppd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdppd-2.c
new file mode 100644
index 000000000..6e30faf45
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdppd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-dppd-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdpps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdpps-1.c
new file mode 100644
index 000000000..75ba0be5f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdpps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-dpps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdpps-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdpps-2.c
new file mode 100644
index 000000000..b54b90969
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vdpps-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-dpps-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-1.c
new file mode 100644
index 000000000..4919d640f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-1.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef OFFSET
+#define OFFSET 1
+#endif
+
+#if OFFSET < 0 || OFFSET > 1
+#error OFFSET must be within [0..1]
+#endif
+
+void static
+avx_test (void)
+{
+  union256d s1;
+  union128d u;
+  double e [2];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  u.x = _mm256_extractf128_pd (s1.x, OFFSET);
+
+  __builtin_memcpy (e, s1.a + OFFSET * 2, sizeof e);
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-2.c
new file mode 100644
index 000000000..db26e181c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-2.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef OFFSET
+#define OFFSET 1
+#endif
+
+#if OFFSET < 0 || OFFSET > 1
+#error OFFSET must be within [0..1]
+#endif
+
+void static
+avx_test (void)
+{
+  union256 s1;
+  union128 u;
+  float e [4];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  u.x = _mm256_extractf128_ps (s1.x, OFFSET);
+
+  __builtin_memcpy (e, s1.a + OFFSET * 4, sizeof e);
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vextractps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vextractps-1.c
new file mode 100644
index 000000000..4215c34dc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vextractps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-extractps.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhaddpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhaddpd-1.c
new file mode 100644
index 000000000..7809c850c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhaddpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-haddpd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhaddpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhaddpd-256-1.c
new file mode 100644
index 000000000..b9245a368
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhaddpd-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_hadd_pd (s1.x, s2.x);
+
+  e[0] = s1.a[0] + s1.a[1];
+  e[1] = s2.a[0] + s2.a[1];
+  e[2] = s1.a[2] + s1.a[3];
+  e[3] = s2.a[2] + s2.a[3];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhaddps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhaddps-1.c
new file mode 100644
index 000000000..73dcfb6c4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhaddps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-haddps.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhaddps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhaddps-256-1.c
new file mode 100644
index 000000000..fbc58238a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhaddps-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_hadd_ps (s1.x, s2.x);
+
+  e[0] = s1.a[0] + s1.a[1];
+  e[1] = s1.a[2] + s1.a[3];
+  e[2] = s2.a[0] + s2.a[1];
+  e[3] = s2.a[2] + s2.a[3];
+  e[4] = s1.a[4] + s1.a[5];
+  e[5] = s1.a[6] + s1.a[7];
+  e[6] = s2.a[4] + s2.a[5];
+  e[7] = s2.a[6] + s2.a[7];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhsubpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhsubpd-1.c
new file mode 100644
index 000000000..68d14327a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhsubpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-hsubpd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhsubpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhsubpd-256-1.c
new file mode 100644
index 000000000..df710d7f0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhsubpd-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_hsub_pd (s1.x, s2.x);
+
+  e[0] = s1.a[0] - s1.a[1];
+  e[1] = s2.a[0] - s2.a[1];
+  e[2] = s1.a[2] - s1.a[3];
+  e[3] = s2.a[2] - s2.a[3];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhsubps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhsubps-1.c
new file mode 100644
index 000000000..2ddd2c0c8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhsubps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-hsubps.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhsubps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhsubps-256-1.c
new file mode 100644
index 000000000..aa601c8a7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vhsubps-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_hsub_ps (s1.x, s2.x);
+
+  e[0] = s1.a[0] - s1.a[1];
+  e[1] = s1.a[2] - s1.a[3];
+  e[2] = s2.a[0] - s2.a[1];
+  e[3] = s2.a[2] - s2.a[3];
+  e[4] = s1.a[4] - s1.a[5];
+  e[5] = s1.a[6] - s1.a[7];
+  e[6] = s2.a[4] - s2.a[5];
+  e[7] = s2.a[6] - s2.a[7];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-1.c
new file mode 100644
index 000000000..2390e5c7e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-1.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef OFFSET
+#define OFFSET 1
+#endif
+
+#if OFFSET < 0 || OFFSET > 1
+#error OFFSET must be within [0..1]
+#endif
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1;
+  union128d s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm_set_pd (68543.731254, 3452.578238);
+  u.x = _mm256_insertf128_pd (s1.x, s2.x, OFFSET);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i];
+
+  for (i=0; i < 2; i++)
+    e[i + (OFFSET * 2)] = s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-2.c
new file mode 100644
index 000000000..ce0b23bbf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-2.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef OFFSET
+#define OFFSET 0
+#endif
+
+#if OFFSET < 0 || OFFSET > 1
+#error OFFSET must be within [0..1]
+#endif
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1;
+  union128 s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (39.467, 45.789, 78.342, 67.892, 76.678, 12.963, 29.746, 24.753);
+  s2.x = _mm_set_ps (57.493, 38.395, 22.479, 31.614);
+  u.x = _mm256_insertf128_ps (s1.x, s2.x, OFFSET);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i];
+
+  for (i=0; i < 4; i++)
+    e[i + (OFFSET * 4)] = s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-3.c
new file mode 100644
index 000000000..89834d554
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-3.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef OFFSET
+#define OFFSET 0
+#endif
+
+#if OFFSET < 0 || OFFSET > 1
+#error OFFSET must be within [0..1]
+#endif
+
+void static
+avx_test (void)
+{
+  int i;
+  union256i_d u, s1;
+  union128i_d s2;
+  int e [8];
+
+  s1.x = _mm256_set_epi32 (39467, 45789, 78342, 67892, 76678, 12963, 29746, 24753);
+  s2.x = _mm_set_epi32 (57493, 38395, 22479, 31614);
+  u.x = _mm256_insertf128_si256 (s1.x, s2.x, OFFSET);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i];
+
+  for (i=0; i < 4; i++)
+    e[i + (OFFSET * 4)] = s2.a[i];
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vinsertps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vinsertps-1.c
new file mode 100644
index 000000000..ad1f33308
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vinsertps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-insertps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vinsertps-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vinsertps-2.c
new file mode 100644
index 000000000..7b93174aa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vinsertps-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-insertps-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vlddqu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vlddqu-1.c
new file mode 100644
index 000000000..7ecea79e8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vlddqu-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-lddqu.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vlddqu-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vlddqu-256-1.c
new file mode 100644
index 000000000..82c0ed580
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vlddqu-256-1.c
@@ -0,0 +1,17 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int e[8]={ 23, 67, 53, 6, 4, 6, 85, 234};
+  union256i_d u;
+
+  u.x = _mm256_lddqu_si256 ((__m256i *) e);
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c
new file mode 100644
index 000000000..f29826bbb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 7
+#endif
+
+#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63)
+
+void static
+avx_test (void)
+{
+  int i;
+  long long m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
+  double s[4] = {1.1, 2.2, 3.3, 4.4};
+  union256d u, mask;
+  double e [4] = {0.0};
+
+  mask.x = _mm256_loadu_pd ((double*)m);
+  u.x = _mm256_maskload_pd (s, mask.x);
+
+  for (i = 0 ; i < 4; i++) 
+    e[i] = m[i] ? s[i] : 0;
+   
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c
new file mode 100644
index 000000000..1e574b699
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 6
+#endif
+
+#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63)
+
+void static
+avx_test (void)
+{
+  int i;
+  long long m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
+  double s[4] = {1.1, 2.2, 3.3, 4.4};
+  double e [4] = {0.0};
+  double d [4] = {0.0};
+  union256d src, mask;
+  
+  src.x = _mm256_loadu_pd (s);
+  mask.x = _mm256_loadu_pd ((double*)m);
+  _mm256_maskstore_pd (d, mask.x, src.x);
+
+  for (i = 0 ; i < 4; i++) 
+    e[i] = m[i] ? s[i] : 0;
+   
+  if (checkVd (d, e, 4))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c
new file mode 100644
index 000000000..9e6c7f91d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 134
+#endif
+
+#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31)
+
+void static
+avx_test (void)
+{
+  int i;
+  int m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3), mask_v(4), mask_v(5), mask_v(6), mask_v(7)};
+  float s[8] = {1,2,3,4,5,6,7,8};
+  union256 u, mask;
+  float e [8] = {0.0};
+
+  mask.x = _mm256_loadu_ps ((float*)m);
+  u.x = _mm256_maskload_ps (s, mask.x);
+
+  for (i = 0 ; i < 8; i++) 
+    e[i] = m[i] ? s[i] : 0;
+   
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c
new file mode 100644
index 000000000..90d91a06a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 214
+#endif
+
+#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31)
+
+void static
+avx_test (void)
+{
+  int i;
+  int m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3), mask_v(4), mask_v(5), mask_v(6), mask_v(7)};
+  float s[8] = {1,2,3,4,5,6,7,8};
+  union256 src, mask;
+  float e [8] = {0.0};
+  float d [8] = {0.0};
+
+  src.x = _mm256_loadu_ps (s);
+  mask.x = _mm256_loadu_ps ((float *)m);
+  _mm256_maskstore_ps (d, mask.x, src.x);
+
+  for (i = 0 ; i < 8; i++) 
+    e[i] = m[i] ? s[i] : 0;
+   
+  if (checkVf (d, e, 8))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxpd-1.c
new file mode 100644
index 000000000..981e2a5b6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-maxpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxpd-256-1.c
new file mode 100644
index 000000000..7b9c91c03
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxpd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_max_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] > s2.a[i] ? s1.a[i] : s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxps-1.c
new file mode 100644
index 000000000..e4c41450d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-maxps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxps-256-1.c
new file mode 100644
index 000000000..44bb7ed9c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxps-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 24567.16, 3.15, 4567.14, 5.13, 65467.12, 788.11, 8.9);
+  u.x = _mm256_max_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i] > s2.a[i] ? s1.a[i] : s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxsd-1.c
new file mode 100644
index 000000000..e24410cd1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-maxsd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxss-1.c
new file mode 100644
index 000000000..afe5d0adb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmaxss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-maxss-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminpd-1.c
new file mode 100644
index 000000000..a7eb64972
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-minpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminpd-256-1.c
new file mode 100644
index 000000000..555e029bd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminpd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_min_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] < s2.a[i] ? s1.a[i] : s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminps-1.c
new file mode 100644
index 000000000..dfb07ba23
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-minps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminps-256-1.c
new file mode 100644
index 000000000..19ac83a72
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminps-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 24567.16, 3.15, 4567.14, 5.13, 65467.12, 788.11, 8.9);
+  u.x = _mm256_min_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i] < s2.a[i] ? s1.a[i] : s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminsd-1.c
new file mode 100644
index 000000000..5aa1d9aa0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-minsd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminss-1.c
new file mode 100644
index 000000000..c2e6f2799
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vminss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-minss-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovapd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovapd-1.c
new file mode 100644
index 000000000..5d97a5d2f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovapd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movapd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovapd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovapd-2.c
new file mode 100644
index 000000000..9856d2907
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovapd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movapd-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c
new file mode 100644
index 000000000..d91212283
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256d
+__attribute__((noinline, unused))
+test (double *e)
+{
+  return _mm256_load_pd (e);
+}
+
+void static
+avx_test (void)
+{
+  union256d u;
+  double e [4] __attribute__ ((aligned (8)))  = {41124.234,2344.2354,8653.65635,856.43576};
+
+  u.x = test (e);
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c
new file mode 100644
index 000000000..96a664ac1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void
+__attribute__((noinline, unused))
+test (double *e, __m256d a)
+{
+  return _mm256_store_pd (e, a);
+}
+
+void static
+avx_test (void)
+{
+  union256d u;
+  double e [4] __attribute__ ((aligned (8))) = {0.0};
+
+  u.x = _mm256_set_pd (39578.467285, 7856.342941, 85632.783567, 47563.234215);
+
+  test (e, u.x);
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovaps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovaps-1.c
new file mode 100644
index 000000000..a10894c35
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovaps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movaps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovaps-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovaps-2.c
new file mode 100644
index 000000000..ad0cf47c4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovaps-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movaps-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-1.c
new file mode 100644
index 000000000..74681c326
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256
+__attribute__((noinline, unused))
+test (float *e)
+{
+  return _mm256_load_ps (e);
+}
+
+void static
+avx_test (void)
+{
+  union256 u;
+  float e [8] __attribute__ ((aligned (32)))  = {24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4};
+
+  u.x = test (e);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-2.c
new file mode 100644
index 000000000..dbd5227c0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-2.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void
+__attribute__((noinline, unused))
+test (float *e, __m256 a)
+{
+  return _mm256_store_ps (e, a);
+}
+
+void static
+avx_test (void)
+{
+  union256 u;
+  float e [8] __attribute__ ((aligned (32))) = {0.0};
+
+  u.x = _mm256_set_ps (1.17, 24567.16, 3.15, 4567.14, 5.13, 65467.12, 788.11, 8.9);
+
+  test (e, u.x);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovd-1.c
new file mode 100644
index 000000000..cdaec13cf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovd-2.c
new file mode 100644
index 000000000..3c3732baf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovd-2.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movd-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovddup-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovddup-1.c
new file mode 100644
index 000000000..4db42e137
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovddup-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -mfpmath=sse" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-movddup.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovddup-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovddup-256-1.c
new file mode 100644
index 000000000..a971dbf4f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovddup-256-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1;
+  double e [4];
+
+  s1.x = _mm256_set_pd (39578.467285, 7856.342941, 85632.783567, 47563.234215);
+  u.x = _mm256_movedup_pd (s1.x);
+
+  for (i = 0; i < 2; i++)
+    e[2*i] = e[2*i+1] = s1.a[2*i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqa-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqa-1.c
new file mode 100644
index 000000000..b14aeaff9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqa-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movdqa-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqa-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqa-2.c
new file mode 100644
index 000000000..94a758d2e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqa-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movdqa-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-1.c
new file mode 100644
index 000000000..abe62880e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__ ((noinline, unused))
+test (__m256i *p)
+{
+  return _mm256_load_si256 (p);
+}
+
+void static
+avx_test (void)
+{
+  union256i_d u;
+  int e [8] __attribute__ ((aligned (32))) = {23, 67, 53, 6, 4, 6, 85, 234};
+
+  u.x = test ((__m256i *)e);
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-2.c
new file mode 100644
index 000000000..41f3ed0e6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256i_d u;
+  int e [8] __attribute__ ((aligned (32))) = {0};
+
+  u.x = _mm256_set_epi32(23, 67, 53, 6, 4, 6, 85, 234);
+  _mm256_store_si256 ((__m256i *)e, u.x);
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqu-1.c
new file mode 100644
index 000000000..7785b40ab
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqu-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movdqu-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqu-2.c
new file mode 100644
index 000000000..f0eead700
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqu-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movdqu-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-1.c
new file mode 100644
index 000000000..849df7bc3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-1.c
@@ -0,0 +1,17 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256i_d u;
+  int e [8] = {23, 67, 53, 6, 4, 6, 85, 234};
+
+  u.x = _mm256_loadu_si256 ((__m256i *) e); 
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-2.c
new file mode 100644
index 000000000..eb0af202c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256i_d u;
+  int e [8] = {0};
+
+  u.x = _mm256_set_epi32(23, 67, 53, 6, 4, 6, 85, 234);
+  _mm256_storeu_si256 ((__m256i *)e, u.x);
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovhlps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovhlps-1.c
new file mode 100644
index 000000000..25beca971
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovhlps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movhlps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovhpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovhpd-1.c
new file mode 100644
index 000000000..246275cd2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovhpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movhpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovhpd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovhpd-2.c
new file mode 100644
index 000000000..1cfdf59c2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovhpd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movhpd-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovhps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovhps-1.c
new file mode 100644
index 000000000..8cf1eec8d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovhps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movhps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovhps-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovhps-2.c
new file mode 100644
index 000000000..c835f1512
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovhps-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movhps-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovlhps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovlhps-1.c
new file mode 100644
index 000000000..8f8234b31
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovlhps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movlhps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovlpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovlpd-1.c
new file mode 100644
index 000000000..64d90c6cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovlpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movlpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovlpd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovlpd-2.c
new file mode 100644
index 000000000..081956a9d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovlpd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movlpd-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-1.c
new file mode 100644
index 000000000..07eb85185
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movmskpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-256-1.c
new file mode 100644
index 000000000..71353c44d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-256-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  int d;
+  union256d s1;
+  double source[4] = {-45, -3, -34.56, 35};
+  int e = 0;
+
+  s1.x = _mm256_loadu_pd (source);
+  d = _mm256_movemask_pd (s1.x);
+  
+  for (i = 0; i < 4; i++)
+    if (source[i] < 0)
+      e |= (1 << i);
+
+  if (checkVi (&d, &e, 1))
+    abort ();  
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovmskps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovmskps-1.c
new file mode 100644
index 000000000..df4d1e78d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovmskps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movmskps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovmskps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovmskps-256-1.c
new file mode 100644
index 000000000..4b81d0413
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovmskps-256-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  int d;
+  union256 s1;
+  float source[8] = {-45, -3, -34.56, 35, 5.46,46, -464.3, 56};
+  int e = 0;
+
+  s1.x = _mm256_loadu_ps (source);
+  d = _mm256_movemask_ps (s1.x);
+  
+  for (i = 0; i < 8; i++)
+    if (source[i] < 0)
+      e |= (1 << i);
+
+  if (checkVi (&d, &e, 1))
+    abort ();  
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntdq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntdq-1.c
new file mode 100644
index 000000000..166d46f20
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntdq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movntdq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntdq-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntdq-256-1.c
new file mode 100644
index 000000000..5caf34e6d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntdq-256-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void
+__attribute__((noinline))
+test (__m256i *p, __m256i s)
+{
+  return _mm256_stream_si256 (p, s); 
+}
+
+static void
+avx_test (void)
+{
+  union256i_d u;
+  int e[8] __attribute__ ((aligned(32))) = {1,1,1,1,1,1,1,1};
+
+  u.x = _mm256_set_epi32 (2434, 6845, 3789, 4683,
+			  4623, 2236, 8295, 1084);
+
+  test ((__m256i *)e, u.x);
+  
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntdqa-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntdqa-1.c
new file mode 100644
index 000000000..c884d1e5e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntdqa-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-movntdqa.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntpd-1.c
new file mode 100644
index 000000000..d547a2a9e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntpd-1.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movntpd-1.c"
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntpd-256-1.c
new file mode 100644
index 000000000..f17deafaf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntpd-256-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void 
+__attribute__((noinline))
+test (double *p, __m256d s)
+{
+  return _mm256_stream_pd (p, s); 
+}
+
+static void
+avx_test (void)
+{
+  union256d u;
+  double e[4] __attribute__ ((aligned(32))) = {1,1,1,1};
+   
+  u.x = _mm256_set_pd (2134.3343, 1234.635654, -13443.35, 43.35345);
+  test (e, u.x); 
+   
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntps-1.c
new file mode 100644
index 000000000..b9732f26d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movntps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntps-256-1.c
new file mode 100644
index 000000000..9f79403f4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovntps-256-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void 
+__attribute__((noinline))
+test (float *p, __m256 s)
+{
+  return _mm256_stream_ps (p, s); 
+}
+
+static void
+avx_test (void)
+{
+  union256 u;
+  float e[8] __attribute__ ((aligned(32)));
+
+  u.x = _mm256_set_ps (24.43, 68.346, -43.35, 546.46,
+		       46.9, -2.78, 82.9, -0.4);
+  test (e, u.x); 
+  
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovq-1.c
new file mode 100644
index 000000000..44d202308
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovq-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovq-2.c
new file mode 100644
index 000000000..cf0f4eb69
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovq-2.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movq-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovq-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovq-3.c
new file mode 100644
index 000000000..26944d118
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovq-3.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movq-3.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovsd-1.c
new file mode 100644
index 000000000..185784419
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movsd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovsd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovsd-2.c
new file mode 100644
index 000000000..672b25bfd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovsd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movsd-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovshdup-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovshdup-1.c
new file mode 100644
index 000000000..ee995e3a7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovshdup-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -mfpmath=sse" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-movshdup.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovshdup-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovshdup-256-1.c
new file mode 100644
index 000000000..a4b57a0c4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovshdup-256-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1;
+  float e[8];
+
+  s1.x = _mm256_set_ps (134.3, 1234.54, 45.335, 646.456, 43.54, 473.34, 78, 89.54);
+  u.x = _mm256_movehdup_ps (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[2*i] = e[2*i+1] = s1.a[2*i+1];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovsldup-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovsldup-1.c
new file mode 100644
index 000000000..67ea717ad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovsldup-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -mfpmath=sse" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-movsldup.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovsldup-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovsldup-256-1.c
new file mode 100644
index 000000000..52127bec2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovsldup-256-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1;
+  float e[8];
+
+  s1.x = _mm256_set_ps (134.3, 1234.54, 45.335, 646.456, 43.54, 473.34, 78, 89.54);
+  u.x = _mm256_moveldup_ps (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[2*i] = e[2*i+1] = s1.a[2*i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovss-1.c
new file mode 100644
index 000000000..ff983e6b3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movss-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovss-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovss-2.c
new file mode 100644
index 000000000..e9a8bdc59
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovss-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movss-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovss-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovss-3.c
new file mode 100644
index 000000000..b73e2af06
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovss-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movss-3.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovupd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovupd-1.c
new file mode 100644
index 000000000..67f08744a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovupd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movupd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovupd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovupd-2.c
new file mode 100644
index 000000000..cb6f27763
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovupd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movupd-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-1.c
new file mode 100644
index 000000000..8683a78da
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256d
+__attribute__((noinline, unused))
+test (double *e)
+{
+  return _mm256_loadu_pd (e);
+}
+
+void static
+avx_test (void)
+{
+  union256d u;
+  double e [4]  = {41124.234,2344.2354,8653.65635,856.43576};
+
+  u.x = test (e);
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-2.c
new file mode 100644
index 000000000..4cbd0e7e2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-2.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void
+__attribute__((noinline, unused))
+test (double *e, __m256d a)
+{
+  return _mm256_storeu_pd (e, a);
+}
+
+void static
+avx_test (void)
+{
+  union256d u;
+  double e [4] = {0.0};
+
+  u.x = _mm256_set_pd (39578.467285, 7856.342941, 85632.783567, 47563.234215);
+
+  test (e, u.x);
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovups-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovups-1.c
new file mode 100644
index 000000000..5b9a98b05
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovups-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movups-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovups-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovups-2.c
new file mode 100644
index 000000000..e5668a29a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovups-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movups-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovups-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovups-256-1.c
new file mode 100644
index 000000000..87d840998
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovups-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256
+__attribute__((noinline, unused))
+test (float *e)
+{
+  return _mm256_loadu_ps (e);
+}
+
+void static
+avx_test (void)
+{
+  union256 u;
+  float e [8]  = {24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4};
+
+  u.x = test (e);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovups-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovups-256-2.c
new file mode 100644
index 000000000..c1781979a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmovups-256-2.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void
+__attribute__((noinline, unused))
+test (float *e, __m256 a)
+{
+  return _mm256_storeu_ps (e, a);
+}
+
+void static
+avx_test (void)
+{
+  union256 u;
+  float e [8]  = {0.0};
+
+  u.x = _mm256_set_ps (1.17, 24567.16, 3.15, 4567.14, 5.13, 65467.12, 788.11, 8.9);
+
+  test (e, u.x);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmpsadbw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmpsadbw-1.c
new file mode 100644
index 000000000..403423e66
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmpsadbw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-mpsadbw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulpd-1.c
new file mode 100644
index 000000000..0fa0f1ad7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-mulpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulpd-256-1.c
new file mode 100644
index 000000000..c6d9c4770
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulpd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_mul_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] * s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulps-1.c
new file mode 100644
index 000000000..bb29e1945
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-mulps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulps-256-1.c
new file mode 100644
index 000000000..518a9477d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulps-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_mul_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i] * s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulsd-1.c
new file mode 100644
index 000000000..16adcde80
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-mulsd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulss-1.c
new file mode 100644
index 000000000..9ff6e3d14
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vmulss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-mulss-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vorpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vorpd-1.c
new file mode 100644
index 000000000..221849ff1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vorpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-orpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vorpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vorpd-256-1.c
new file mode 100644
index 000000000..ca60e24fc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vorpd-256-1.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+
+  union
+  {
+    double d[4];
+    long long ll[4];
+  }source1, source2, e;
+
+  s1.x = _mm256_set_pd (34545, 95567, 23443, 5675);
+  s2.x = _mm256_set_pd (674, 57897, 93459, 45624);
+
+  _mm256_storeu_pd (source1.d, s1.x);
+  _mm256_storeu_pd (source2.d, s2.x);
+
+  u.x = _mm256_or_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e.ll[i] = source1.ll[i] | source2.ll[i];
+
+  if (check_union256d (u, e.d))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vorps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vorps-1.c
new file mode 100644
index 000000000..fd501dd15
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vorps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-orps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vorps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vorps-256-1.c
new file mode 100644
index 000000000..ef1c51b1d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vorps-256-1.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+
+  union256 u, s1, s2;
+
+  union
+  {
+    float f[8];
+    int   i[8];
+  }source1, source2, e;
+
+  s1.x = _mm256_set_ps (34545, 95567, 23443, 5675, 2323, 67, 2345, 45667);
+  s2.x = _mm256_set_ps (674, 57897, 93459, 45624, 54674, 1237, 67436, 79608);
+
+  _mm256_storeu_ps (source1.f, s1.x);
+  _mm256_storeu_ps (source2.f, s2.x);
+
+  u.x = _mm256_or_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e.i[i] = source1.i[i] | source2.i[i];
+
+  if (check_union256 (u, e.f))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpabsb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpabsb-1.c
new file mode 100644
index 000000000..bd5b1fbe9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpabsb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-pabsb.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpabsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpabsd-1.c
new file mode 100644
index 000000000..3ea84d808
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpabsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-pabsd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpabsw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpabsw-1.c
new file mode 100644
index 000000000..6de79a5b6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpabsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-pabsw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpackssdw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpackssdw-1.c
new file mode 100644
index 000000000..f302ce716
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpackssdw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-packssdw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpacksswb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpacksswb-1.c
new file mode 100644
index 000000000..14fd680a5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpacksswb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-packsswb-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpackusdw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpackusdw-1.c
new file mode 100644
index 000000000..81991d951
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpackusdw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-packusdw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpackuswb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpackuswb-1.c
new file mode 100644
index 000000000..d06f3c779
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpackuswb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-packuswb-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddb-1.c
new file mode 100644
index 000000000..fa06c1e30
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddb-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddd-1.c
new file mode 100644
index 000000000..fc2ee2932
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddq-1.c
new file mode 100644
index 000000000..bb913be9d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddsb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddsb-1.c
new file mode 100644
index 000000000..56dc00b73
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddsb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddsb-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddsw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddsw-1.c
new file mode 100644
index 000000000..c326420e6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddsw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddusb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddusb-1.c
new file mode 100644
index 000000000..a83bf6b7e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddusb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddusb-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddusw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddusw-1.c
new file mode 100644
index 000000000..8cbf06092
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddusw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddusw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddw-1.c
new file mode 100644
index 000000000..caaa46666
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpaddw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpalignr-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpalignr-1.c
new file mode 100644
index 000000000..1a60b467f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpalignr-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-palignr.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpand-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpand-1.c
new file mode 100644
index 000000000..22e05701c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpand-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pand-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpandn-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpandn-1.c
new file mode 100644
index 000000000..fbd7e25ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpandn-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pandn-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpavgb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpavgb-1.c
new file mode 100644
index 000000000..1474d2b1f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpavgb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pavgb-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpavgw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpavgw-1.c
new file mode 100644
index 000000000..1c7c3c89d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpavgw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pavgw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpblendvb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpblendvb-1.c
new file mode 100644
index 000000000..001799776
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpblendvb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pblendvb.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpblendw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpblendw-1.c
new file mode 100644
index 000000000..241dbcc6a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpblendw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pblendw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpclmulqdq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpclmulqdq.c
new file mode 100644
index 000000000..9b015abcd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpclmulqdq.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vpclmul } */
+/* { dg-options "-O2 -mpclmul -mavx" } */
+
+#define CHECK_H "pclmul-avx-check.h"
+#define TEST pclmul_avx_test
+
+#include "pclmulqdq.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpeqb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpeqb-1.c
new file mode 100644
index 000000000..9cd2bbcc1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpeqb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pcmpeqb-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpeqd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpeqd-1.c
new file mode 100644
index 000000000..b1d1dd2d6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpeqd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pcmpeqd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpeqq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpeqq-1.c
new file mode 100644
index 000000000..541b52c4b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpeqq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pcmpeqq.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpeqw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpeqw-1.c
new file mode 100644
index 000000000..0e0397abd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpeqw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pcmpeqw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-1.c
new file mode 100644
index 000000000..806000f9f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpestri-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-2.c
new file mode 100644
index 000000000..6d683ef89
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpestri-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-1.c
new file mode 100644
index 000000000..95b2bdc0c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpestrm-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-2.c
new file mode 100644
index 000000000..b2f6ad33d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpestrm-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpgtb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpgtb-1.c
new file mode 100644
index 000000000..ed9fd4d21
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpgtb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pcmpgtb-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpgtd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpgtd-1.c
new file mode 100644
index 000000000..344741eef
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpgtd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pcmpgtd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpgtq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpgtq-1.c
new file mode 100644
index 000000000..1332215a9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpgtq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpgtq.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpgtw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpgtw-1.c
new file mode 100644
index 000000000..c4f2007e0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpgtw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pcmpgtw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-1.c
new file mode 100644
index 000000000..4cb13535d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpistri-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-2.c
new file mode 100644
index 000000000..ec2af713d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpistri-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-1.c
new file mode 100644
index 000000000..7a6a4d4d1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpistrm-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-2.c
new file mode 100644
index 000000000..82857d813
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpistrm-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-1.c
new file mode 100644
index 000000000..99abca189
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-1.c
@@ -0,0 +1,63 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#define CONTROL 0xCC
+
+void static
+avx_test (void)
+{
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (1, 2, 3, 4, 5, 6, 7, 8);
+  s2.x = _mm256_set_ps (9, 10, 11, 12, 13, 14, 15, 16);
+  u.x = _mm256_permute2f128_ps (s1.x, s2.x, CONTROL);
+
+  switch (CONTROL & 0x3)
+    {
+      case 0:
+        __builtin_memcpy (e, s1.a, 16);
+        break;
+      case 1: 
+        __builtin_memcpy (e, s1.a+4, 16);
+        break;
+      case 2:
+        __builtin_memcpy (e, s2.a, 16);
+        break;
+      case 3:
+        __builtin_memcpy (e, s2.a+4, 16);
+        break;
+      default:
+        abort ();
+    }
+
+ switch ((CONTROL & 0xc)>>2)
+    {
+      case 0:
+        __builtin_memcpy (e+4, s1.a, 16);
+        break;
+      case 1: 
+        __builtin_memcpy (e+4, s1.a+4, 16);
+        break;
+      case 2:
+        __builtin_memcpy (e+4, s2.a, 16);
+        break;
+      case 3:
+        __builtin_memcpy (e+4, s2.a+4, 16);
+        break;
+      default:
+        abort ();
+    }
+
+  if (CONTROL & (1<<3))
+    __builtin_memset (e, 0, 16);
+
+  if (CONTROL & (1<<7))
+    __builtin_memset (e+4, 0, 16);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-2.c
new file mode 100644
index 000000000..db9c65bce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-2.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef IMM8
+#  define IMM8 99
+#endif
+
+
+void static
+avx_test ()
+{
+    union256d source1, source2, u;
+    double  s1[4]={1, 2, 3, 4};
+    double  s2[4]={5, 6, 7, 8};
+    double   e[4];
+
+    source1.x = _mm256_loadu_pd(s1);
+    source2.x = _mm256_loadu_pd(s2);
+    u.x = _mm256_permute2f128_pd(source1.x, source2.x, IMM8);
+
+    if(IMM8 & 8) e[0] = e[1] = 0;
+    else{
+        e[0] = (IMM8 & 2 ? s2 : s1)[(IMM8 & 1) * 2];
+        e[1] = (IMM8 & 2 ? s2 : s1)[(IMM8 & 1) * 2 + 1];
+    }
+    if(IMM8 & 128) e[3] = e[3] = 0;
+    else{
+        unsigned m = (IMM8 >> 4) & 3;
+        e[2] = (m & 2 ? s2 : s1)[(m & 1) * 2];
+        e[3] = (m & 2 ? s2 : s1)[(m & 1) * 2 + 1];
+    }
+  
+   if (check_union256d (u, e))
+     abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-3.c
new file mode 100644
index 000000000..7b00c4b76
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-3.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef IMM8
+#  define IMM8 100
+#endif
+
+void static
+avx_test ()
+{
+    union256i_q source1, source2, u;
+    long long  s1[4]={1, 2, 3, 4};
+    long long  s2[4]={5, 6, 7, 8};
+    long long   e[4];
+
+    source1.x = _mm256_loadu_si256((__m256i*)s1);
+    source2.x = _mm256_loadu_si256((__m256i*)s2);
+    u.x = _mm256_permute2f128_si256(source1.x, source2.x, IMM8);
+
+    if(IMM8 & 8) e[0] = e[1] = 0;
+    else{
+        e[0] = (IMM8 & 2 ? s2 : s1)[(IMM8 & 1) * 2];
+        e[1] = (IMM8 & 2 ? s2 : s1)[(IMM8 & 1) * 2 + 1];
+    }
+    if(IMM8 & 128) e[3] = e[3] = 0;
+    else{
+        unsigned m = (IMM8 >> 4) & 3;
+        e[2] = (m & 2 ? s2 : s1)[(m & 1) * 2];
+        e[3] = (m & 2 ? s2 : s1)[(m & 1) * 2 + 1];
+    }
+   
+   if (check_union256i_q (u, e))
+     abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilpd-1.c
new file mode 100644
index 000000000..6379cdb4a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilpd-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef CTRL
+#define CTRL 1
+#endif
+
+void static
+avx_test ()
+{
+    union128d u, src;
+    double s[2] = {9674.67456, 13543.9788};
+    double e[2];
+
+    src.x=_mm_loadu_pd(s);
+    u.x=_mm_permute_pd(src.x, CTRL);
+
+    e[0] = s[ (CTRL & 0x01)];
+    e[1] = s[((CTRL & 0x02) >> 1)];
+
+    if (check_union128d (u, e))
+      abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilpd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilpd-2.c
new file mode 100644
index 000000000..a6d7a0d67
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilpd-2.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef CTRL
+#define CTRL 2
+#endif
+
+#define mask_v(pos) (((CTRL & (1ULL << (pos))) >> (pos)) << 1)
+
+void static
+avx_test ()
+{
+    union128d u, src;
+    union128i_q ctl;
+ 
+    double  s[2] = {9674.67456, 13543.9788};
+    long long m[2] = {mask_v(0), mask_v(1)};
+    double  e[2];
+
+    src.x = _mm_loadu_pd(s);
+    ctl.x = _mm_loadu_si128((__m128i*) m);
+    u.x = _mm_permutevar_pd(src.x, ctl.x);
+
+    e[0] = s[((m[0] & 0x02) >> 1)];
+    e[1] = s[((m[1] & 0x02) >> 1)];
+
+    if (check_union128d (u, e))
+      abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-1.c
new file mode 100644
index 000000000..ca93474b5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#define CONTROL 5
+
+void static
+avx_test (void)
+{
+  union256d u, s1;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  u.x = _mm256_permute_pd (s1.x, CONTROL);
+
+  e[0] = (CONTROL&0x01) ? s1.a[1] : s1.a[0];
+  e[1] = (CONTROL&0x02) ? s1.a[1] : s1.a[0];
+  e[2] = (CONTROL&0x04) ? s1.a[3] : s1.a[2];
+  e[3] = (CONTROL&0x08) ? s1.a[3] : s1.a[2];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-2.c
new file mode 100644
index 000000000..1cd5c3a62
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef CTRL
+#define CTRL 6
+#endif
+
+#define mask_v(pos) (((CTRL & (1ULL << (pos))) >> (pos)) << 1)
+
+void static
+avx_test ()
+{
+    union256d u, src; 
+    union256i_q ctl;
+
+    double  s[4] = {39578.467285, 7856.342941, 9674.67456, 13543.9788};
+    long long m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
+    double  e[4] = {0.0};
+
+    src.x = _mm256_loadu_pd(s);
+    ctl.x  = _mm256_loadu_si256((__m256i*) m);
+    u.x = _mm256_permutevar_pd(src.x, ctl.x);
+
+    e[0] = s[0 + ((m[0] & 0x02) >> 1)];
+    e[1] = s[0 + ((m[1] & 0x02) >> 1)];
+    e[2] = s[2 + ((m[2] & 0x02) >> 1)];
+    e[3] = s[2 + ((m[3] & 0x02) >> 1)];
+
+    if (check_union256d (u, e))
+      abort ();
+}
+
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilps-1.c
new file mode 100644
index 000000000..146f55567
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilps-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef CTRL
+#define CTRL 11
+#endif
+
+void static
+avx_test ()
+{
+  union128 u, s;
+  float e[4];
+
+  s.x = _mm_set_ps (1, 2, 3, 4);
+  u.x = _mm_permute_ps(s.x, CTRL);
+
+  e[0] = s.a[ (CTRL & 0x03)];
+  e[1] = s.a[((CTRL & 0x0c) >> 2)];
+  e[2] = s.a[((CTRL & 0x30) >> 4)];
+  e[3] = s.a[((CTRL & 0xc0) >> 6)];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilps-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilps-2.c
new file mode 100644
index 000000000..ca0fbae4a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilps-2.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef CTRL
+#define CTRL 233
+#endif
+
+#define mask_v(pos) ((CTRL & (0x3 << (pos))) >> (pos))
+
+void static
+avx_test ()
+{
+    union128 u, s;
+    union128i_q ctl;
+    int m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
+    float e[4];
+
+    s.x = _mm_set_ps (1, 2, 3, 4);
+    ctl.x = _mm_loadu_si128((__m128i*) m);
+    u.x = _mm_permutevar_ps(s.x, ctl.x);
+
+    e[0] = s.a[0 + (m[0] & 0x03)];
+    e[1] = s.a[0 + (m[1] & 0x03)];
+    e[2] = s.a[0 + (m[2] & 0x03)];
+    e[3] = s.a[0 + (m[3] & 0x03)];
+
+    if (check_union128 (u, e))
+      abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-1.c
new file mode 100644
index 000000000..b9291498d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef CTRL
+#define CTRL 129
+#endif
+
+void static
+avx_test ()
+{
+    union256 src, u;
+    float e[8] = {0.0};
+
+    src.x = _mm256_set_ps (1, 2, 3, 4, 5, 6, 7, 8);
+    u.x = _mm256_permute_ps(src.x, CTRL);
+
+    e[0] = src.a[0 +  (CTRL & 0x03)];
+    e[1] = src.a[0 + ((CTRL & 0x0c) >> 2)];
+    e[2] = src.a[0 + ((CTRL & 0x30) >> 4)];
+    e[3] = src.a[0 + ((CTRL & 0xc0) >> 6)];
+    e[4] = src.a[4 +  (CTRL & 0x03)];
+    e[5] = src.a[4 + ((CTRL & 0x0c) >> 2)];
+    e[6] = src.a[4 + ((CTRL & 0x30) >> 4)];
+    e[7] = src.a[4 + ((CTRL & 0xc0) >> 6)];
+
+    if (check_union256 (u, e))
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-2.c
new file mode 100644
index 000000000..9890410b4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef CTRL
+#define CTRL 233
+#endif
+
+#define mask_v(pos) ((CTRL & (0x3 << (pos))) >> (pos))
+
+void static
+avx_test ()
+{
+    union256 u, s;
+    union256i_q ctl;
+    int m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3), mask_v(4), mask_v(5), mask_v(6), mask_v(7)};
+    float e[8];
+
+    s.x = _mm256_set_ps (1, 2, 3, 4, 5, 6, 7, 8);
+    ctl.x = _mm256_loadu_si256((__m256i*) m);
+    u.x = _mm256_permutevar_ps(s.x, ctl.x);
+
+    e[0] = s.a[0 + (m[0] & 0x03)];
+    e[1] = s.a[0 + (m[1] & 0x03)];
+    e[2] = s.a[0 + (m[2] & 0x03)];
+    e[3] = s.a[0 + (m[3] & 0x03)];
+    e[4] = s.a[4 + (m[4] & 0x03)];
+    e[5] = s.a[4 + (m[5] & 0x03)];
+    e[6] = s.a[4 + (m[6] & 0x03)];
+    e[7] = s.a[4 + (m[7] & 0x03)];
+
+    if (check_union256 (u, e))
+      abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpextrb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpextrb-1.c
new file mode 100644
index 000000000..4e1c64428
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpextrb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pextrb.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpextrd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpextrd-1.c
new file mode 100644
index 000000000..bc67a2845
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpextrd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pextrd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpextrq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpextrq-1.c
new file mode 100644
index 000000000..1ffe007a1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpextrq-1.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pextrq.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpextrw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpextrw-1.c
new file mode 100644
index 000000000..7751ded98
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpextrw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pextrw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphaddd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphaddd-1.c
new file mode 100644
index 000000000..d0aee2139
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphaddd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-phaddd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphaddsw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphaddsw-1.c
new file mode 100644
index 000000000..b58978aeb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphaddsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-phaddsw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphaddw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphaddw-1.c
new file mode 100644
index 000000000..cdf17f694
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphaddw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-phaddw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphminposuw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphminposuw-1.c
new file mode 100644
index 000000000..288651c95
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphminposuw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-phminposuw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphsubd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphsubd-1.c
new file mode 100644
index 000000000..b1be419cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphsubd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-phsubd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphsubsw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphsubsw-1.c
new file mode 100644
index 000000000..477523e30
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphsubsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-phsubsw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphsubw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphsubw-1.c
new file mode 100644
index 000000000..55893a672
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vphsubw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-phsubw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpinsrb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpinsrb-1.c
new file mode 100644
index 000000000..b3b63581d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpinsrb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pinsrb.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpinsrd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpinsrd-1.c
new file mode 100644
index 000000000..69c9bef3c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpinsrd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pinsrd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpinsrq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpinsrq-1.c
new file mode 100644
index 000000000..3b9d26a29
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpinsrq-1.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pinsrq.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaddubsw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaddubsw-1.c
new file mode 100644
index 000000000..adc476300
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaddubsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-pmaddubsw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxsb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxsb-1.c
new file mode 100644
index 000000000..74b5a331f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxsb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmaxsb.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxsd-1.c
new file mode 100644
index 000000000..832e25e7f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmaxsd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxsw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxsw-1.c
new file mode 100644
index 000000000..55e362e69
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pmaxsw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxub-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxub-1.c
new file mode 100644
index 000000000..0f647cbe1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxub-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pmaxub-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxud-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxud-1.c
new file mode 100644
index 000000000..afd29dbb4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxud-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmaxud.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxuw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxuw-1.c
new file mode 100644
index 000000000..74b4177ca
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmaxuw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmaxuw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminsb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminsb-1.c
new file mode 100644
index 000000000..e44ca611f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminsb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pminsb.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminsd-1.c
new file mode 100644
index 000000000..54e18ed53
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pminsd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminsw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminsw-1.c
new file mode 100644
index 000000000..ce65712f4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pminsw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminub-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminub-1.c
new file mode 100644
index 000000000..d7b77bc62
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminub-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pminub-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminud-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminud-1.c
new file mode 100644
index 000000000..bbc069e78
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminud-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pminud.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminuw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminuw-1.c
new file mode 100644
index 000000000..9b253555e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpminuw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pminuw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovmskb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovmskb-1.c
new file mode 100644
index 000000000..0b3e8aaee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovmskb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pmovmskb-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxbd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxbd-1.c
new file mode 100644
index 000000000..b3a57b044
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxbd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovsxbd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxbq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxbq-1.c
new file mode 100644
index 000000000..a9aba16bd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxbq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovsxbq.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxbw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxbw-1.c
new file mode 100644
index 000000000..a3f2efe36
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxbw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovsxbw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxdq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxdq-1.c
new file mode 100644
index 000000000..6f2940533
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxdq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovsxdq.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxwd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxwd-1.c
new file mode 100644
index 000000000..8e186e382
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxwd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovsxwd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxwq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxwq-1.c
new file mode 100644
index 000000000..90c2d1d5e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovsxwq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovsxwq.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxbd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxbd-1.c
new file mode 100644
index 000000000..3f4556ce8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxbd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovzxbd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxbq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxbq-1.c
new file mode 100644
index 000000000..719c7271e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxbq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovzxbq.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxbw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxbw-1.c
new file mode 100644
index 000000000..ad5fe4e7d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxbw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovzxbw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxdq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxdq-1.c
new file mode 100644
index 000000000..7490902b8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxdq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovzxdq.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxwd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxwd-1.c
new file mode 100644
index 000000000..5447155d5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxwd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovzxwd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxwq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxwq-1.c
new file mode 100644
index 000000000..b8239f221
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmovzxwq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovzxwq.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmuldq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmuldq-1.c
new file mode 100644
index 000000000..527d3cbdb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmuldq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmuldq.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmulhrsw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmulhrsw-1.c
new file mode 100644
index 000000000..121252ec6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmulhrsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-pmulhrsw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmulhuw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmulhuw-1.c
new file mode 100644
index 000000000..f3127a9db
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmulhuw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pmulhuw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmulhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmulhw-1.c
new file mode 100644
index 000000000..c36b489c7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmulhw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pmulhw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmulld-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmulld-1.c
new file mode 100644
index 000000000..63df55d79
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmulld-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmulld.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmullw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmullw-1.c
new file mode 100644
index 000000000..649dcad62
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmullw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pmullw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmuludq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmuludq-1.c
new file mode 100644
index 000000000..e7c1cebdc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpmuludq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pmuludq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpor-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpor-1.c
new file mode 100644
index 000000000..cda694f00
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpor-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-por-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsadbw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsadbw-1.c
new file mode 100644
index 000000000..6f76c9632
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsadbw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psadbw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpshufb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpshufb-1.c
new file mode 100644
index 000000000..5ab106c3f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpshufb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-pshufb.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpshufd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpshufd-1.c
new file mode 100644
index 000000000..543bcdfcb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpshufd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pshufd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpshufhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpshufhw-1.c
new file mode 100644
index 000000000..23b79c653
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpshufhw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pshufhw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpshuflw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpshuflw-1.c
new file mode 100644
index 000000000..268b5d244
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpshuflw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pshuflw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsignb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsignb-1.c
new file mode 100644
index 000000000..9677c6834
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsignb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-psignb.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsignd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsignd-1.c
new file mode 100644
index 000000000..84b16b73a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsignd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-psignd.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsignw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsignw-1.c
new file mode 100644
index 000000000..daf47e601
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsignw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-psignw.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpslld-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpslld-1.c
new file mode 100644
index 000000000..778662dbd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpslld-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pslld-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpslld-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpslld-2.c
new file mode 100644
index 000000000..12754ed78
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpslld-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pslld-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpslldq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpslldq-1.c
new file mode 100644
index 000000000..aea5b7865
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpslldq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pslldq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsllq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsllq-1.c
new file mode 100644
index 000000000..37c152649
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsllq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psllq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsllq-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsllq-2.c
new file mode 100644
index 000000000..0cc298df9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsllq-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psllq-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsllw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsllw-1.c
new file mode 100644
index 000000000..ebb610c31
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsllw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psllw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsllw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsllw-2.c
new file mode 100644
index 000000000..62a989dc9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsllw-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psllw-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrad-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrad-1.c
new file mode 100644
index 000000000..2293c42b5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrad-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrad-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrad-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrad-2.c
new file mode 100644
index 000000000..53f4f09c2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrad-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrad-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsraw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsraw-1.c
new file mode 100644
index 000000000..525163fcc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsraw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psraw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsraw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsraw-2.c
new file mode 100644
index 000000000..90c8df0f2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsraw-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psraw-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrld-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrld-1.c
new file mode 100644
index 000000000..a143a65c4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrld-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrld-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrld-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrld-2.c
new file mode 100644
index 000000000..e9e1e3f2a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrld-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrld-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrldq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrldq-1.c
new file mode 100644
index 000000000..a8cec081e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrldq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrldq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrlq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrlq-1.c
new file mode 100644
index 000000000..d7a57bff7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrlq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrlq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrlq-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrlq-2.c
new file mode 100644
index 000000000..efa870818
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrlq-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrlq-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrlw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrlw-1.c
new file mode 100644
index 000000000..e132c2da1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrlw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrlw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrlw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrlw-2.c
new file mode 100644
index 000000000..ec4a85dce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsrlw-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrlw-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubb-1.c
new file mode 100644
index 000000000..e66624f22
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psubb-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubd-1.c
new file mode 100644
index 000000000..1e9214dbd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psubd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubq-1.c
new file mode 100644
index 000000000..b7c22be7c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psubq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubsb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubsb-1.c
new file mode 100644
index 000000000..fa71d6112
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubsb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psubsb-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubsw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubsw-1.c
new file mode 100644
index 000000000..b3fbad0ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psubsw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubw-1.c
new file mode 100644
index 000000000..a83140e19
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpsubw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psubw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-1.c
new file mode 100644
index 000000000..c70752d36
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-ptest-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-2.c
new file mode 100644
index 000000000..cb6b5520b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-ptest-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-256-1.c
new file mode 100644
index 000000000..ebc2673a4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int s1i[8] = {0, 5463, 86456, 0, 1234, 0, 62445, 34352};
+  int s2i[8] = {0, 1223, 0,     0, 0,    1, 0,     0};
+  int d;
+  int e;
+  int i;
+  union256i_d s1, s2;
+
+  s1.x = _mm256_loadu_si256 ((__m256i*)s1i);
+  s2.x = _mm256_loadu_si256 ((__m256i*)s2i);
+  d = _mm256_testz_si256 (s1.x, s2.x);
+
+  e = 1;
+  for (i = 0; i < 8; i++)
+    if ((s1i[i] & s2i[i]) != 0)
+      e = 0;
+
+  if (d != e)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-256-2.c
new file mode 100644
index 000000000..f85344a9a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-256-2.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int s1i[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int s2i[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+  int d;
+  int e;
+  int i;
+  union256i_d s1, s2;
+
+  s1.x = _mm256_loadu_si256 ((__m256i*)s1i);
+  s2.x = _mm256_loadu_si256 ((__m256i*)s2i);
+  d = _mm256_testc_si256 (s1.x, s2.x);
+
+  e = 1;
+  for (i = 0; i < 8; i++)
+    if ((~s1i[i] & s2i[i]) != 0)
+      e = 0;
+
+  if (d != e)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-256-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-256-3.c
new file mode 100644
index 000000000..cccbbef4e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-256-3.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int s1i[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int s2i[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+  int d;
+  int c = 1, z = 1, e = 0xf;
+  int i;
+  union256i_d s1, s2;
+
+  s1.x = _mm256_loadu_si256 ((__m256i*)s1i);
+  s2.x = _mm256_loadu_si256 ((__m256i*)s2i);
+  d = _mm256_testnzc_si256 (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    {
+      if ((s1.a[i] & s2.a[i]))
+        z = 0;
+      if ((~s1.a[i] & s2.a[i]))
+        c = 0;
+    }
+
+   e = (z == 0 && c == 0) ? 1 : 0;
+
+  if (d != e)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-3.c
new file mode 100644
index 000000000..1b875a75f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vptest-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-ptest-3.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpckhbw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpckhbw-1.c
new file mode 100644
index 000000000..3c76aa3f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpckhbw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpckhbw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpckhdq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpckhdq-1.c
new file mode 100644
index 000000000..a853d7014
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpckhdq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpckhdq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpckhqdq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpckhqdq-1.c
new file mode 100644
index 000000000..8b86c7649
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpckhqdq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpckhqdq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpckhwd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpckhwd-1.c
new file mode 100644
index 000000000..0e4e051d4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpckhwd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpckhwd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpcklbw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpcklbw-1.c
new file mode 100644
index 000000000..ad856cf6a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpcklbw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpcklbw-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpckldq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpckldq-1.c
new file mode 100644
index 000000000..2acd87929
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpckldq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpckldq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpcklqdq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpcklqdq-1.c
new file mode 100644
index 000000000..bd378a34f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpcklqdq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpcklqdq-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpcklwd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpcklwd-1.c
new file mode 100644
index 000000000..07f2be177
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpunpcklwd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpcklwd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpxor-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpxor-1.c
new file mode 100644
index 000000000..dfc46537b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vpxor-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pxor-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vrcpps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vrcpps-1.c
new file mode 100644
index 000000000..45673de43
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vrcpps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-rcpps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vrcpps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vrcpps-256-1.c
new file mode 100644
index 000000000..16b3051b0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vrcpps-256-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256 u, s1;
+    float e[8] = {0.0};
+
+    s1.x = _mm256_set_ps (1.0, 2.0, 13.0, 14.0, 56.89, 73.3, 4.78, 45.64);
+    u.x = _mm256_rcp_ps (s1.x);
+
+    for (i = 0; i < 8; i++) {
+      __m128 tmp = _mm_load_ss (&s1.a[i]);
+      tmp = _mm_rcp_ss (tmp);
+      _mm_store_ss (&e[i], tmp);
+    }
+
+    if (check_union256 (u, e))
+      abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-1.c
new file mode 100644
index 000000000..c8b0ec1ef
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-roundpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-2.c
new file mode 100644
index 000000000..e29ac5562
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-roundpd-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-1.c
new file mode 100644
index 000000000..71da7523a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-1.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#define iRoundMode 0x7
+
+void static
+avx_test (void)
+{
+  union256d u, s1;
+  double source [4] = {2134.3343,1234.635654,453.345635,54646.464356};
+  double e[4] = {0.0};
+  int i;
+
+  s1.x = _mm256_loadu_pd (source);
+  u.x = _mm256_round_pd (s1.x, iRoundMode);
+
+  for (i = 0; i < 4; i++)
+    {
+      __m128d tmp = _mm_load_sd (&s1.a[i]);
+      tmp = _mm_round_sd (tmp, tmp, iRoundMode);
+      _mm_store_sd (&e[i], tmp);
+    }
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-2.c
new file mode 100644
index 000000000..a61d7730c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u, s1;
+  double source [4] = {2134.3343,1234.635654,453.345635,54646.464356};
+  double e[4] = {0.0};
+  int i;
+
+  s1.x = _mm256_loadu_pd (source);
+  u.x = _mm256_floor_pd (s1.x);
+
+  for (i = 0; i < 4; i++)
+    {
+      __m128d tmp = _mm_load_sd (&s1.a[i]);
+      tmp = _mm_floor_sd (tmp, tmp);
+      _mm_store_sd (&e[i], tmp);
+    }
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-3.c
new file mode 100644
index 000000000..f4f3e77dd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-3.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u, s1;
+  double source [4] = {2134.3343,1234.635654,453.345635,54646.464356};
+  double e[4] = {0.0};
+  int i;
+
+  s1.x = _mm256_loadu_pd (source);
+  u.x = _mm256_ceil_pd (s1.x);
+
+  for (i = 0; i < 4; i++)
+    {
+      __m128d tmp = _mm_load_sd (&s1.a[i]);
+      tmp = _mm_ceil_sd (tmp, tmp);
+      _mm_store_sd (&e[i], tmp);
+    }
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-3.c
new file mode 100644
index 000000000..6d9326f6a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundpd-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-roundpd-3.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundps-256-1.c
new file mode 100644
index 000000000..d33248e24
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vroundps-256-1.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256 u, s1;
+  float source [8] = {2134.3343,1234.635654,453.345635,54646.464356,895833.346347,56343,234234.34563,2345434.67832};
+  float e [8] = {2134.0,1234.0,453.0,54646.0,895833.0,56343,234234.0,2345434.0};
+
+  s1.x = _mm256_loadu_ps (source);
+  u.x = _mm256_round_ps (s1.x, 1);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-1.c
new file mode 100644
index 000000000..2db1650dd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-rsqrtps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-256-1.c
new file mode 100644
index 000000000..19a933c5d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-256-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256 u, s1;
+    float e[8] = {0.0};
+
+    s1.x = _mm256_set_ps (1.0, 2.0, 13.0, 14.0, 56.89, 73.3, 4.78, 45.64);
+    u.x = _mm256_rsqrt_ps (s1.x);
+
+    for (i = 0; i < 8; i++) {
+      __m128 tmp = _mm_load_ss (&s1.a[i]);
+      tmp = _mm_rsqrt_ss (tmp);
+      _mm_store_ss (&e[i], tmp);
+    }
+
+    if (check_union256 (u, e))
+      abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vshufpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vshufpd-1.c
new file mode 100644
index 000000000..a6f00ea8b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vshufpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-shufpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vshufpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vshufpd-256-1.c
new file mode 100644
index 000000000..828f6804f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vshufpd-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 10
+#endif
+
+void static
+avx_test (void)
+{
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_shuffle_pd (s1.x, s2.x, MASK);
+
+  e[0] = (MASK & (1 << 0)) ? s1.a[1] : s1.a[0];
+  e[1] = (MASK & (1 << 1)) ? s2.a[1] : s2.a[0];
+  e[2] = (MASK & (1 << 2)) ? s1.a[3] : s1.a[2];
+  e[3] = (MASK & (1 << 3)) ? s2.a[3] : s2.a[2];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vshufps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vshufps-1.c
new file mode 100644
index 000000000..97d85706d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vshufps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-shufps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vshufps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vshufps-256-1.c
new file mode 100644
index 000000000..f939357d4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vshufps-256-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 203
+#endif
+
+float select4(const float *src, unsigned int control)
+{
+    switch(control) {
+    case 0:
+        return src[0];
+    case 1:
+        return src[1];
+    case 2:
+        return src[2];
+    case 3:
+        return src[3];
+    }
+    return -1;
+}
+
+
+void static
+avx_test (void)
+{
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8);
+  s2.x = _mm256_set_ps (2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8);
+  u.x = _mm256_shuffle_ps (s1.x, s2.x, MASK);
+
+
+  e[0] = select4(s1.a,   (MASK >> 0) & 0x3);
+  e[1] = select4(s1.a,   (MASK >> 2) & 0x3);
+  e[2] = select4(s2.a,   (MASK >> 4) & 0x3);
+  e[3] = select4(s2.a,   (MASK >> 6) & 0x3);
+  e[4] = select4(s1.a+4, (MASK >> 0) & 0x3);
+  e[5] = select4(s1.a+4, (MASK >> 2) & 0x3);
+  e[6] = select4(s2.a+4, (MASK >> 4) & 0x3);
+  e[7] = select4(s2.a+4, (MASK >> 6) & 0x3);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-1.c
new file mode 100644
index 000000000..dc098c910
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-sqrtpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-256-1.c
new file mode 100644
index 000000000..d611bbd12
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-256-1.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u, s1;
+  double e [4] = {0x1.d3881b2c32ed7p+7, 0x1.54abaed51711cp+4, 0x1.19195c08a8d23p+5, 0x1.719741d6c0b0bp+5};
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  u.x = _mm256_sqrt_pd (s1.x);
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsqrtps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsqrtps-1.c
new file mode 100644
index 000000000..deb88947f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsqrtps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-sqrtps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsqrtps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsqrtps-256-1.c
new file mode 100644
index 000000000..d5cd77f5d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsqrtps-256-1.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256 u, s1;
+  float e[8] = {0x1.7edeccp+10, 0x1.e3fa46p+8, 0x1.dabbcep+7, 0x1.d93e0cp+9,\
+                0x1.d3881cp+7, 0x1.54abbp+4, 0x1.19195cp+5, 0x1.719742p+5};
+
+  s1.x = _mm256_set_ps (2134.3343,1234.635654,453.345635,54646.464356, \
+                        895833.346347,56343,234234.34563,2345434.67832);
+  u.x = _mm256_sqrt_ps (s1.x);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubpd-1.c
new file mode 100644
index 000000000..2af33fc6a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-subpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubpd-256-1.c
new file mode 100644
index 000000000..ce4ddcaa1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubpd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_sub_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubps-1.c
new file mode 100644
index 000000000..59aa92847
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-subps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubps-256-1.c
new file mode 100644
index 000000000..de4337cb6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubps-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_sub_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubsd-1.c
new file mode 100644
index 000000000..58cf4cb32
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-subsd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubss-1.c
new file mode 100644
index 000000000..719aa6f15
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vsubss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-subss-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-1.c
new file mode 100644
index 000000000..6b52d786b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union128d source1, source2;
+
+    double s1[2] = {30, -5463};
+    double s2[2] = {20, 1223};
+    int    d[1];
+    int    e[1];
+  
+    source1.x = _mm_loadu_pd(s1);
+    source2.x = _mm_loadu_pd(s2);
+
+    d[0] = _mm_testz_pd(source1.x, source2.x);
+    
+    e[0] = 1;
+    for (i = 0; i < 2; i++)
+      {
+	union ieee754_double u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+        if (u1.bits.sign && u2.bits.sign) {
+            e[0] = 0;
+        }
+    }
+
+    if (checkVi(d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-2.c
new file mode 100644
index 000000000..57dfeeb7d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union128d source1, source2;
+
+    double s1[2] = {0, -5463};
+    double s2[2] = {0, -1223};
+    int    d[1];
+    int    e[1];
+  
+    source1.x = _mm_loadu_pd(s1);
+    source2.x = _mm_loadu_pd(s2);
+
+    d[0] = _mm_testc_pd(source1.x, source2.x);
+    
+    e[0] = 1;
+    for (i = 0; i < 2; i++) {
+	union ieee754_double u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+        if (!u1.bits.sign && u2.bits.sign)
+            e[0] = 0;
+    }
+
+    if (checkVi(d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-1.c
new file mode 100644
index 000000000..050f140f7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-1.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256d source1, source2;
+   
+    double s1[4] = {0, -5463, 86456, 0};
+    double s2[4] = {0, -1223, 0,     1};
+    int    d[1];
+    int    e[1];
+
+    source1.x = _mm256_loadu_pd(s1);
+    source2.x = _mm256_loadu_pd(s2);
+    d[0] = _mm256_testz_pd(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 4; i++) {
+	union ieee754_double u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+        if (u1.bits.sign && u2.bits.sign) {
+            e[0] = 0;
+        }
+    }
+    
+   if (checkVi(d, e, 1))
+     abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-2.c
new file mode 100644
index 000000000..0954f1dd8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256d source1, source2;
+   
+    double s1[4] = {0, -5463, 86456, 0};
+    double s2[4] = {0, -1223, 0,     1};
+    int    d[1];
+    int    e[1];
+
+    source1.x = _mm256_loadu_pd(s1);
+    source2.x = _mm256_loadu_pd(s2);
+    d[0] = _mm256_testc_pd(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 4; i++) {
+	union ieee754_double u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+        if (!u1.bits.sign && u2.bits.sign) {
+            e[0] = 0;
+        }
+    }
+    
+  if (checkVi(d, e, 1))
+    abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-3.c
new file mode 100644
index 000000000..8a6e32e41
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-3.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256d source1, source2;
+   
+    double s1[4] = {0, -5463, 86456, 0};
+    double s2[4] = {0, -1223, 0,     1};
+    int    d[1];
+    int    e[1];
+    int c=1;
+    int z=1;
+
+    source1.x = _mm256_loadu_pd(s1);
+    source2.x = _mm256_loadu_pd(s2);
+    d[0] = _mm256_testnzc_pd(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 4; i++) {
+	union ieee754_double u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+        if (u1.bits.sign && u2.bits.sign)
+            z = 0;
+        
+        if (!u1.bits.sign && u2.bits.sign)
+            c = 0;
+    }
+    e[0] = (c==0 && z==0) ? 1:0;
+    
+   if (checkVi(d, e, 1))
+     abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-3.c
new file mode 100644
index 000000000..74c5dc868
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestpd-3.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union128d source1, source2;
+
+    double s1[2] = {0, -5463};
+    double s2[2] = {0, -1223};
+    int    d[1];
+    int    e[1];
+    int c = 1;
+    int z = 1;
+  
+    source1.x = _mm_loadu_pd(s1);
+    source2.x = _mm_loadu_pd(s2);
+
+    d[0] = _mm_testnzc_pd(source1.x, source2.x);
+    
+    e[0] = 1;
+    for (i = 0; i < 2; i++) {
+	union ieee754_double u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+        if (u1.bits.sign && u2.bits.sign)
+            z = 0;
+        if (!u1.bits.sign && u2.bits.sign)
+            c = 0;
+        
+    }
+
+    e[0] = (c==0 && z==0) ? 1:0;
+
+    if (checkVi(d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-1.c
new file mode 100644
index 000000000..fb0c802fb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-1.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union128 source1, source2;
+    float s1[4] = {0, -5463, 86456, 0};
+    float s2[4] = {0, -1223, 0,     0};
+    int   d[1];
+    int   e[1];
+
+    source1.x = _mm_loadu_ps(s1);
+    source2.x = _mm_loadu_ps(s2);
+    d[0] = _mm_testz_ps(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 4; i++) {
+	union ieee754_float u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+	if (u1.bits.sign && u2.bits.sign)
+            e[0] = 0;
+    }
+
+    if (checkVi (d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-2.c
new file mode 100644
index 000000000..7482dae4e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-2.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union128 source1, source2;
+    float s1[4] = {0, -5463, 86456, 0};
+    float s2[4] = {0, -1223, 0,     0};
+    int   d[1];
+    int   e[1];
+
+    source1.x = _mm_loadu_ps(s1);
+    source2.x = _mm_loadu_ps(s2);
+    d[0] = _mm_testc_ps(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 4; i++) {
+	union ieee754_float u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+	if (!u1.bits.sign && u2.bits.sign)
+            e[0] = 0;
+    }
+
+    if (checkVi (d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-256-1.c
new file mode 100644
index 000000000..6362c4183
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-256-1.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256 source1, source2;
+
+    float s1[8] = {0, -5463, 86456, 0, 1234, 0, 62445, 34352};
+    float s2[8] = {0, -1223, 0,     0, 0,    1, 0,     0};
+    int   d[1];
+    int   e[1];
+
+    source1.x = _mm256_loadu_ps(s1);
+    source2.x = _mm256_loadu_ps(s2);
+    d[0] = _mm256_testz_ps(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 8; i++) {
+	union ieee754_float u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+	if (u1.bits.sign && u2.bits.sign)
+            e[0] = 0;
+    }
+
+    if (checkVi (d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-256-2.c
new file mode 100644
index 000000000..de23ab2e9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-256-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256 source1, source2;
+
+    float s1[8] = {0, -5463, 86456, 0, 1234, 0, 62445, 34352};
+    float s2[8] = {0, -1223, 0,     0, 0,    1, 0,     0};
+    int   d[1];
+    int   e[1];
+
+    source1.x = _mm256_loadu_ps(s1);
+    source2.x = _mm256_loadu_ps(s2);
+    d[0] = _mm256_testc_ps(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 8; i++) {
+	union ieee754_float u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+	if (!u1.bits.sign && u2.bits.sign)
+            e[0] = 0;
+    }
+
+    if (checkVi (d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-256-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-256-3.c
new file mode 100644
index 000000000..717e5bb28
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-256-3.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256 source1, source2;
+    int c = 1;
+    int z = 1;
+
+    float s1[8] = {0, -5463, 86456, 0, 1234, 0, 62445, 34352};
+    float s2[8] = {0, -1223, 0,     0, 0,    1, 0,     0};
+    int   d[1];
+    int   e[1];
+
+    source1.x = _mm256_loadu_ps(s1);
+    source2.x = _mm256_loadu_ps(s2);
+    d[0] = _mm256_testnzc_ps(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 8; i++) {
+	union ieee754_float u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+	if (!u1.bits.sign && u2.bits.sign)
+            c = 0;
+	if (u1.bits.sign && u2.bits.sign)
+            z = 0;
+        }
+    e[0] = (c==0 && z==0)?1:0;
+
+    if (checkVi (d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-3.c
new file mode 100644
index 000000000..61f58a6b3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vtestps-3.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union128 source1, source2;
+    float s1[4] = {0, -5463, 86456, 0};
+    float s2[4] = {0, -1223, 0,     0};
+    int   d[1];
+    int   e[1];
+    int c=1;
+    int z=1;
+
+    source1.x = _mm_loadu_ps(s1);
+    source2.x = _mm_loadu_ps(s2);
+    d[0] = _mm_testnzc_ps(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 4; i++) {
+	union ieee754_float u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+	if (!u1.bits.sign && u2.bits.sign)
+            c = 0;
+	if (u1.bits.sign && u2.bits.sign)
+            z = 0;
+        
+    }
+    e[0] = (c == 0 && z == 0) ? 1:0;
+
+    if (checkVi (d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-1.c
new file mode 100644
index 000000000..d4efd212d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-ucomisd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-2.c
new file mode 100644
index 000000000..d55f31007
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-ucomisd-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-3.c
new file mode 100644
index 000000000..e2ba869ff
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-ucomisd-3.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-4.c
new file mode 100644
index 000000000..961759909
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-4.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-ucomisd-4.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-5.c
new file mode 100644
index 000000000..9034519af
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-5.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-ucomisd-5.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-6.c
new file mode 100644
index 000000000..cc9d0e925
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomisd-6.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-ucomisd-6.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-1.c
new file mode 100644
index 000000000..c0ba7a3a6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-ucomiss-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-2.c
new file mode 100644
index 000000000..ea4b80e10
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-ucomiss-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-3.c
new file mode 100644
index 000000000..bd82bb92a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-ucomiss-3.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-4.c
new file mode 100644
index 000000000..a58395a12
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-4.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-ucomiss-4.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-5.c
new file mode 100644
index 000000000..198933cd5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-5.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-ucomiss-5.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-6.c
new file mode 100644
index 000000000..db48b7a30
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vucomiss-6.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-ucomiss-6.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-1.c
new file mode 100644
index 000000000..4b7191ce0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-unpckhpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-256-1.c
new file mode 100644
index 000000000..5da332d45
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_unpackhi_pd (s1.x, s2.x);
+
+  e[0] = s1.a[1];
+  e[1] = s2.a[1];
+  e[2] = s1.a[3];
+  e[3] = s2.a[3];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpckhps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpckhps-1.c
new file mode 100644
index 000000000..e5a0f3e1e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpckhps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-unpckhps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpckhps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpckhps-256-1.c
new file mode 100644
index 000000000..be6fbb6f9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpckhps-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_unpackhi_ps (s1.x, s2.x);
+
+  e[0] = s1.a[2];
+  e[1] = s2.a[2];
+  e[2] = s1.a[3];
+  e[3] = s2.a[3];
+  e[4] = s1.a[6];
+  e[5] = s2.a[6];
+  e[6] = s1.a[7];
+  e[7] = s2.a[7];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-1.c
new file mode 100644
index 000000000..9e0cb05ad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-unpcklpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-256-1.c
new file mode 100644
index 000000000..0f7e390cf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_unpacklo_pd (s1.x, s2.x);
+
+  e[0] = s1.a[0];
+  e[1] = s2.a[0];
+  e[2] = s1.a[2];
+  e[3] = s2.a[2];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpcklps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpcklps-1.c
new file mode 100644
index 000000000..c2380a47e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpcklps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-unpcklps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpcklps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpcklps-256-1.c
new file mode 100644
index 000000000..bf0e31892
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vunpcklps-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_unpacklo_ps (s1.x, s2.x);
+
+  e[0] = s1.a[0];
+  e[1] = s2.a[0];
+  e[2] = s1.a[1];
+  e[3] = s2.a[1];
+  e[4] = s1.a[4];
+  e[5] = s2.a[4];
+  e[6] = s1.a[5];
+  e[7] = s2.a[5];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vxorpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vxorpd-1.c
new file mode 100644
index 000000000..435bf042a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vxorpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-xorpd-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vxorpd-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vxorpd-256-1.c
new file mode 100644
index 000000000..4896ee01e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vxorpd-256-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union
+  {
+    double d[4];
+    long long l[4];
+  }source1, source2, e;
+
+  int i;
+  union256d u, s1, s2;
+
+  s1.x = _mm256_set_pd (34545.123, 95567.456, 23443.09876, 5675.543);
+  s2.x = _mm256_set_pd (674, 57897.332187, 93459, 45624.112);
+  _mm256_storeu_pd (source1.d, s1.x);
+  _mm256_storeu_pd (source2.d, s2.x);
+
+  u.x = _mm256_xor_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e.l[i] = source1.l[i] ^ source2.l[i];
+
+  if (check_union256d (u, e.d))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vxorps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vxorps-1.c
new file mode 100644
index 000000000..e203a7f57
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vxorps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-xorps-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vxorps-256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vxorps-256-1.c
new file mode 100644
index 000000000..007704846
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vxorps-256-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union {
+    float f[8];
+    int   i[8];
+  }source1, source2, e;
+  
+  int i;
+  union256 u, s1, s2;
+
+  s1.x = _mm256_set_ps (34545, 95567, 23443, 5675, 2323, 67, 2345, 45667);
+  s2.x = _mm256_set_ps (674, 57897, 93459, 45624, 54674, 1237, 67436, 79608);
+  
+  _mm256_storeu_ps (source1.f, s1.x);
+  _mm256_storeu_ps (source2.f, s2.x);
+
+  u.x = _mm256_xor_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e.i[i] = source1.i[i] ^ source2.i[i];
+
+  if (check_union256 (u, e.f))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vzeroall-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vzeroall-1.c
new file mode 100644
index 000000000..996357a7e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vzeroall-1.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void
+avx_test (void)
+{
+  __m256i src;
+#ifdef __x86_64__
+  char reg_save[16][32];
+  char d[16][32];
+#else
+  char reg_save[8][32];
+  char d[8][32];
+#endif  
+
+  int s[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+
+  __builtin_memset (d, 0, sizeof d);
+  __builtin_memset (reg_save, -1, sizeof reg_save);
+
+  src = _mm256_loadu_si256 ((__m256i*) s);
+
+  _mm256_zeroall (); 
+
+  __asm__ __volatile__ ("vmovdqu %%ymm0,%0":"=m"(reg_save[0]));
+  __asm__ __volatile__ ("vmovdqu %%ymm1,%0":"=m"(reg_save[1]));
+  __asm__ __volatile__ ("vmovdqu %%ymm2,%0":"=m"(reg_save[2]));
+  __asm__ __volatile__ ("vmovdqu %%ymm3,%0":"=m"(reg_save[3]));
+  __asm__ __volatile__ ("vmovdqu %%ymm4,%0":"=m"(reg_save[4]));
+  __asm__ __volatile__ ("vmovdqu %%ymm5,%0":"=m"(reg_save[5]));
+  __asm__ __volatile__ ("vmovdqu %%ymm6,%0":"=m"(reg_save[6]));
+  __asm__ __volatile__ ("vmovdqu %%ymm7,%0":"=m"(reg_save[7]));
+#ifdef __x86_64__
+  __asm__ __volatile__ ("vmovdqu %%ymm8,%0":"=m"(reg_save[8]));
+  __asm__ __volatile__ ("vmovdqu %%ymm9,%0":"=m"(reg_save[9]));
+  __asm__ __volatile__ ("vmovdqu %%ymm10,%0":"=m"(reg_save[10]));
+  __asm__ __volatile__ ("vmovdqu %%ymm11,%0":"=m"(reg_save[11]));
+  __asm__ __volatile__ ("vmovdqu %%ymm12,%0":"=m"(reg_save[12]));
+  __asm__ __volatile__ ("vmovdqu %%ymm13,%0":"=m"(reg_save[13]));
+  __asm__ __volatile__ ("vmovdqu %%ymm14,%0":"=m"(reg_save[14]));
+  __asm__ __volatile__ ("vmovdqu %%ymm15,%0":"=m"(reg_save[15]));
+#endif
+
+  if (__builtin_memcmp (reg_save, d, sizeof d))
+    abort ();
+
+  _mm256_storeu_si256 ((__m256i*) d, src);
+
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vzeroall-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vzeroall-2.c
new file mode 100644
index 000000000..f49a0da42
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vzeroall-2.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static int s[4] = {234566, 8723467, 6576856, 19832468};
+static int d[4] = {1,1,1,1};
+
+static void
+avx_test (void)
+{
+  __m128i src;
+
+  src = _mm_loadu_si128 ((__m128i*) s);
+  _mm256_zeroall ();
+  _mm_storeu_si128 ((__m128i*) d, src);
+
+  if (__builtin_memcmp (d, s, sizeof (d)))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vzeroupper-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vzeroupper-1.c
new file mode 100644
index 000000000..2137c25ba
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vzeroupper-1.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifdef __x86_64__
+#define LEN 16
+#else
+#define LEN 8
+#endif
+
+static void
+avx_test (void)
+{
+  __m256i src;
+
+  char reg_save[LEN][32];
+  int i, j;
+
+  int s[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+  int d[8] = {11, 22, 33, 44, 55, 66, 77, 88};
+
+  __builtin_memset (reg_save, -1, sizeof reg_save);
+
+  src = _mm256_loadu_si256 ((__m256i*) s);
+
+  _mm256_zeroupper (); 
+
+  __asm__ __volatile__ ("vmovdqu %%ymm0,%0":"=m"(reg_save[0]));
+  __asm__ __volatile__ ("vmovdqu %%ymm1,%0":"=m"(reg_save[1]));
+  __asm__ __volatile__ ("vmovdqu %%ymm2,%0":"=m"(reg_save[2]));
+  __asm__ __volatile__ ("vmovdqu %%ymm3,%0":"=m"(reg_save[3]));
+  __asm__ __volatile__ ("vmovdqu %%ymm4,%0":"=m"(reg_save[4]));
+  __asm__ __volatile__ ("vmovdqu %%ymm5,%0":"=m"(reg_save[5]));
+  __asm__ __volatile__ ("vmovdqu %%ymm6,%0":"=m"(reg_save[6]));
+  __asm__ __volatile__ ("vmovdqu %%ymm7,%0":"=m"(reg_save[7]));
+#ifdef __x86_64__
+  __asm__ __volatile__ ("vmovdqu %%ymm8,%0":"=m"(reg_save[8]));
+  __asm__ __volatile__ ("vmovdqu %%ymm9,%0":"=m"(reg_save[9]));
+  __asm__ __volatile__ ("vmovdqu %%ymm10,%0":"=m"(reg_save[10]));
+  __asm__ __volatile__ ("vmovdqu %%ymm11,%0":"=m"(reg_save[11]));
+  __asm__ __volatile__ ("vmovdqu %%ymm12,%0":"=m"(reg_save[12]));
+  __asm__ __volatile__ ("vmovdqu %%ymm13,%0":"=m"(reg_save[13]));
+  __asm__ __volatile__ ("vmovdqu %%ymm14,%0":"=m"(reg_save[14]));
+  __asm__ __volatile__ ("vmovdqu %%ymm15,%0":"=m"(reg_save[15]));
+#endif
+
+  for (i = 0; i < LEN; i++)
+    for (j = 16; j < 32; j++)
+      if (reg_save[i][j])
+        abort ();
+
+  _mm256_storeu_si256 ((__m256i*) d, src);
+
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vzeroupper-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vzeroupper-2.c
new file mode 100644
index 000000000..9771e6c07
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/avx-vzeroupper-2.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static int s[4] = {234566, 8723467, 6576856, 19832468};
+static int d[4] = {1,1,1,1};
+
+static void
+avx_test (void)
+{
+  __m128i src;
+
+  src = _mm_loadu_si128 ((__m128i*) s);
+  _mm256_zeroupper ();
+  _mm_storeu_si128 ((__m128i*) d, src);
+
+  if (__builtin_memcmp (d, s, sizeof (d)))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bitfield1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bitfield1.c
new file mode 100644
index 000000000..1590396c2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bitfield1.c
@@ -0,0 +1,55 @@
+// Test for bitfield alignment in structs on IA-32
+// { dg-do run }
+// { dg-require-effective-target ilp32 }
+// { dg-options "-O2" }
+// { dg-options "-mno-align-double -mno-ms-bitfields" { target i?86-*-interix* i?86-*-cygwin* i?86-*-mingw*} }
+
+extern void abort (void);
+extern void exit (int);
+
+struct A
+{
+  char a;
+  long long b : 61;
+  char c;
+} a, a4[4];
+
+struct B
+{
+  char d;
+  struct A e;
+  char f;
+} b;
+
+struct C
+{
+  char g;
+  union U
+  {
+    char u1;
+    long long u2;
+    long long u3 : 64;
+  } h;
+  char i;
+} c;
+
+int main (void)
+{
+  if (&a.c - &a.a != 12)
+    abort ();
+  if (sizeof (a) != 16)
+    abort ();
+  if (sizeof (a4) != 4 * 16)
+    abort ();
+  if (sizeof (b) != 2 * 4 + 16)
+    abort ();
+  if (__alignof__ (b.e) != 4)
+    abort ();
+  if (&c.i - &c.g != 12)
+    abort ();
+  if (sizeof (c) != 16)
+    abort ();
+  if (__alignof__ (c.h) != 4)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bitfield2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bitfield2.c
new file mode 100644
index 000000000..d665fcb13
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bitfield2.c
@@ -0,0 +1,23 @@
+// Test for bitfield alignment in structs on IA-32
+// { dg-do run }
+// { dg-require-effective-target ilp32 }
+// { dg-options "-O2" }
+// { dg-options "-mno-align-double -mno-ms-bitfields" { target i?86-*-interix* i?86-*-cygwin* i?86-*-mingw* } }
+
+extern void abort (void);
+extern void exit (int);
+
+struct X {
+  char a;
+  long long : 0;
+  char b;
+} x;
+
+int main () {
+  if (&x.b - &x.a != 4)
+    abort ();
+  if (sizeof (x) != 5)
+    abort ();
+  
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bitfield3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bitfield3.c
new file mode 100644
index 000000000..139f4d461
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bitfield3.c
@@ -0,0 +1,24 @@
+// Test for bitfield alignment in structs on IA-32
+// { dg-do run }
+// { dg-options "-O2" }
+// { dg-options "-mno-align-double -mno-ms-bitfields" { target *-*-interix* } }
+
+extern void abort (void);
+extern void exit (int);
+
+struct X {
+  int : 32;
+};
+
+struct Y {
+  int i : 32;
+};
+
+int main () {
+  if (__alignof__(struct X) != 1)
+    abort ();
+  if (__alignof__(struct Y) != 4)
+    abort ();
+  
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bt-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bt-1.c
new file mode 100644
index 000000000..3727155d6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bt-1.c
@@ -0,0 +1,15 @@
+/* PR target/36473 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=core2" } */
+
+extern void foo (void);
+
+int test(int x, int n)
+{
+  if (x & ( 0x01 << n ))
+    foo ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "btl\[ \t\]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bt-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bt-2.c
new file mode 100644
index 000000000..34fa829e4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bt-2.c
@@ -0,0 +1,16 @@
+/* PR target/36473 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=core2" } */
+
+extern void foo (void);
+
+int test(long x, long n)
+{
+  if (x & ( (long)0x01 << n ))
+    foo ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "btl\[ \t\]" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "btq\[ \t\]" { target lp64 } } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bt-mask-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bt-mask-1.c
new file mode 100644
index 000000000..bdcfd558a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bt-mask-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=core2" } */
+
+void foo (void);
+
+int test (int x, int n)
+{
+  n &= 0x1f;
+
+  if (x & (0x01 << n))
+    foo ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "and\[lq\]\[ \t\]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bt-mask-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bt-mask-2.c
new file mode 100644
index 000000000..babfc2bcd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/bt-mask-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=core2" } */
+
+void foo (void);
+
+int test (long x, long n)
+{
+  n &= 0x3f;
+
+  if (x & ((long)0x01 << n))
+    foo ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "and\[lq\]\[ \t\]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/builtin-apply-mmx.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/builtin-apply-mmx.c
new file mode 100644
index 000000000..f6477e264
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/builtin-apply-mmx.c
@@ -0,0 +1,42 @@
+/* __builtin_apply_args () and __builtin_return () built-in functions does
+   not function properly when -mmmx is used in compile flags.
+   __builtin_apply_args () saves all registers that pass arguments to a
+   function, including %mm0-%mm3, to a memory block, and __builtin_return ()
+   restores %mm0, from a return memory block, as it can be used as a
+   function return register.  Unfortunatelly, when MMX registers are touched,
+   i387 FPU switches to MMX mode, and no FP operation is possible until emms
+   instruction is issued.  */
+
+/* This test case is adapted from gcc.dg/builtin-apply4.c.  */
+ 
+/* { dg-do run { xfail { ! *-*-darwin* } } } */
+/* { dg-options "-O2 -mmmx" } */
+/* { dg-require-effective-target ilp32 } */
+
+#include "mmx-check.h"
+
+extern void abort (void);
+
+double
+foo (double arg)
+{
+  if (arg != 116.0)
+    abort ();
+
+  return arg + 1.0;
+}
+
+inline double
+bar (double arg)
+{
+  foo (arg);
+  __builtin_return (__builtin_apply ((void (*)()) foo,
+				     __builtin_apply_args (), 16));
+}
+
+static void
+mmx_test (void)
+{
+  if (bar (116.0) != 117.0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/builtin-bswap-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/builtin-bswap-1.c
new file mode 100644
index 000000000..0f94025c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/builtin-bswap-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "builtin_bswap" } } */
+
+long foo (long a)
+{
+  long b;
+
+#if __LP64__
+  b = __builtin_bswap64 (a);
+#else
+  b = __builtin_bswap32 (a);
+#endif
+
+  return b;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/builtin-bswap-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/builtin-bswap-2.c
new file mode 100644
index 000000000..818aa76b9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/builtin-bswap-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=nocona" } */
+/* { dg-final { scan-assembler-not "bswap\[ \t\]" } } */
+
+int foo(int x)
+{
+  int t = __builtin_bswap32 (x);
+  return __builtin_bswap32 (t);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/builtin-bswap-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/builtin-bswap-3.c
new file mode 100644
index 000000000..d5d612f60
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/builtin-bswap-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "bswapdi2" } } */
+
+long long foo (long long x)
+{
+  return __builtin_bswap64 (x);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/builtin-copysign.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/builtin-copysign.c
new file mode 100644
index 000000000..c20a0b6cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/builtin-copysign.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define TEST_SET(MODE, CEXT)						\
+MODE test1##CEXT(MODE a) { return -a; }					\
+MODE test2##CEXT(MODE a) { return __builtin_fabs##CEXT(a); }		\
+MODE test3##CEXT(MODE a) { return __builtin_copysign##CEXT(a, 0.0); }	\
+MODE test4##CEXT(MODE a) { return __builtin_copysign##CEXT(a, -1.0); }	\
+MODE test5##CEXT(MODE a, MODE b) { return __builtin_copysign##CEXT(a, b); }
+
+TEST_SET (float, f)
+TEST_SET (double, )
+TEST_SET (long double, l)
+#if defined (__LP64__)
+TEST_SET (__float128, q)
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cadd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cadd.c
new file mode 100644
index 000000000..7a39c67ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cadd.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "sbb" } } */
+
+extern void abort (void);
+
+/* Conditional increment is best done using sbb $-1, val.  */
+int t[]={0,0,0,0,1,1,1,1,1,1};
+q()
+{
+  int sum=0;
+  int i;
+  for (i=0;i<10;i++)
+    if (t[i])
+       sum++;
+  if (sum != 6)
+    abort ();
+}
+main()
+{
+  int i;
+  for (i=0;i<10000000;i++)
+    q();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/call-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/call-1.c
new file mode 100644
index 000000000..bd7c569c6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/call-1.c
@@ -0,0 +1,39 @@
+/* PR optimization/11304 */
+/* Originator: <manuel.serrano@sophia.inria.fr> */
+/* { dg-do run } */
+/* { dg-options "-O -fomit-frame-pointer" } */
+
+/* Verify that %eax is always restored after a call.  */
+
+extern void abort(void);
+
+volatile int r;
+
+void set_eax(int val)
+{
+  __asm__ __volatile__ ("mov %0, %%eax" : : "m" (val));
+}
+
+void foo(int val)
+{
+  r = val;
+}
+
+int bar(int x)
+{
+  if (x)
+  {
+    set_eax(0);
+    return x;
+  }
+
+  foo(x);
+}
+
+int main(void)
+{
+  if (bar(1) != 1)
+    abort();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cleanup-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cleanup-1.c
new file mode 100644
index 000000000..1a47fcb03
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cleanup-1.c
@@ -0,0 +1,240 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-options "-fexceptions -fnon-call-exceptions -fasynchronous-unwind-tables -O2" } */
+/* Test complex CFA value expressions.  */
+
+#include <unwind.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include <unistd.h>
+
+static _Unwind_Reason_Code
+force_unwind_stop (int version, _Unwind_Action actions,
+		   _Unwind_Exception_Class exc_class,
+		   struct _Unwind_Exception *exc_obj,
+		   struct _Unwind_Context *context,
+		   void *stop_parameter)
+{
+  if (actions & _UA_END_OF_STACK)
+    abort ();
+  return _URC_NO_REASON;
+}
+
+static void
+force_unwind ()
+{
+  struct _Unwind_Exception *exc = malloc (sizeof (*exc));
+  memset (&exc->exception_class, 0, sizeof (exc->exception_class));
+  exc->exception_cleanup = 0;
+
+  _Unwind_ForcedUnwind (exc, force_unwind_stop, 0);
+  abort ();
+}
+
+int count;
+
+static void
+counter (void *p __attribute__((unused)))
+{
+  ++count;
+}
+
+static void
+handler (void *p __attribute__((unused)))
+{
+  if (count != 2)
+    abort ();
+  _exit (0);
+}
+
+static int __attribute__((noinline))
+fn5 (void)
+{
+  char dummy __attribute__((cleanup (counter)));
+  force_unwind ();
+  return 0;
+}
+
+void
+bar (void)
+{
+  char dummy __attribute__((cleanup (counter)));
+  fn5 ();
+}
+
+void __attribute__((noinline))
+foo (int x)
+{
+  char buf[256];
+#ifdef __i386__
+  __asm (
+	"testl	%0, %0\n\t"
+	"jnz	1f\n\t"
+	".subsection 1\n\t"
+	".type	_L_mutex_lock_%=, @function\n"
+"_L_mutex_lock_%=:\n"
+"1:\t"	"leal	%1, %%ecx\n"
+"2:\t"	"call	bar\n"
+"3:\t"	"jmp	18f\n"
+"4:\t"	".size _L_mutex_lock_%=, .-_L_mutex_lock_%=\n\t"
+	".previous\n\t"
+	".section	.eh_frame,\"a\",@progbits\n"
+"5:\t"	".long	7f-6f	# Length of Common Information Entry\n"
+"6:\t"	".long	0x0	# CIE Identifier Tag\n\t"
+	".byte	0x1	# CIE Version\n\t"
+	".ascii \"zR\\0\"	# CIE Augmentation\n\t"
+	".uleb128 0x1	# CIE Code Alignment Factor\n\t"
+	".sleb128 -4	# CIE Data Alignment Factor\n\t"
+	".byte	0x8	# CIE RA Column\n\t"
+	".uleb128 0x1	# Augmentation size\n\t"
+	".byte	0x1b	# FDE Encoding (pcrel sdata4)\n\t"
+	".byte	0xc	# DW_CFA_def_cfa\n\t"
+	".uleb128 0x4\n\t"
+	".uleb128 0x0\n\t"
+	".align 4\n"
+"7:\t"	".long	17f-8f	# FDE Length\n"
+"8:\t"	".long	8b-5b	# FDE CIE offset\n\t"
+	".long	1b-.	# FDE initial location\n\t"
+	".long	4b-1b	# FDE address range\n\t"
+	".uleb128 0x0	# Augmentation size\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x8\n\t"
+	".uleb128 10f-9f\n"
+"9:\t"	".byte	0x78	# DW_OP_breg8\n\t"
+	".sleb128 3b-1b\n"
+"10:\t"	".byte	0x40 + (2b-1b) # DW_CFA_advance_loc\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x8\n\t"
+	".uleb128 12f-11f\n"
+"11:\t"	".byte	0x78	# DW_OP_breg8\n\t"
+	".sleb128 3b-2b\n"
+"12:\t"	".byte	0x40 + (3b-2b-1) # DW_CFA_advance_loc\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x8\n\t"
+	".uleb128 16f-13f\n"
+"13:\t"	".byte	0x78	# DW_OP_breg8\n\t"
+	".sleb128 15f-14f\n\t"
+	".byte	0x0d	# DW_OP_const4s\n"
+"14:\t"	".4byte	3b-.\n\t"
+	".byte	0x1c	# DW_OP_minus\n\t"
+	".byte	0x0d	# DW_OP_const4s\n"
+"15:\t"	".4byte	18f-.\n\t"
+	".byte	0x22	# DW_OP_plus\n"
+"16:\t"	".align 4\n"
+"17:\t"	".previous\n"
+"18:"
+	: : "r" (x), "m" (x), "r" (buf)
+	: "memory", "eax", "edx", "ecx");
+#elif defined __x86_64__
+  __asm (
+	"testl	%0, %0\n\t"
+	"jnz	1f\n\t"
+	".subsection 1\n\t"
+	".type	_L_mutex_lock_%=, @function\n"
+"_L_mutex_lock_%=:\n"
+"1:\t"	"leaq	%1, %%rdi\n"
+"2:\t"	"subq	$128, %%rsp\n"
+"3:\t"	"call	bar\n"
+"4:\t"	"addq	$128, %%rsp\n"
+"5:\t"	"jmp	24f\n"
+"6:\t"	".size _L_mutex_lock_%=, .-_L_mutex_lock_%=\n\t"
+	".previous\n\t"
+	".section	.eh_frame,\"a\",@progbits\n"
+"7:\t"	".long	9f-8f	# Length of Common Information Entry\n"
+"8:\t"	".long	0x0	# CIE Identifier Tag\n\t"
+	".byte	0x1	# CIE Version\n\t"
+	".ascii \"zR\\0\"	# CIE Augmentation\n\t"
+	".uleb128 0x1	# CIE Code Alignment Factor\n\t"
+	".sleb128 -8	# CIE Data Alignment Factor\n\t"
+	".byte	0x10	# CIE RA Column\n\t"
+	".uleb128 0x1	# Augmentation size\n\t"
+	".byte	0x1b	# FDE Encoding (pcrel sdata4)\n\t"
+	".byte	0x12	# DW_CFA_def_cfa_sf\n\t"
+	".uleb128 0x7\n\t"
+	".sleb128 16\n\t"
+	".align 8\n"
+"9:\t"	".long	23f-10f	# FDE Length\n"
+"10:\t"	".long	10b-7b	# FDE CIE offset\n\t"
+	".long	1b-.	# FDE initial location\n\t"
+	".long	6b-1b	# FDE address range\n\t"
+	".uleb128 0x0	# Augmentation size\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 12f-11f\n"
+"11:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 4b-1b\n"
+"12:\t"	".byte	0x40 + (2b-1b) # DW_CFA_advance_loc\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 14f-13f\n"
+"13:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 4b-2b\n"
+"14:\t"	".byte	0x40 + (3b-2b) # DW_CFA_advance_loc\n\t"
+	".byte	0x0e	# DW_CFA_def_cfa_offset\n\t"
+	".uleb128 0\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 16f-15f\n"
+"15:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 4b-3b\n"
+"16:\t"	".byte	0x40 + (4b-3b-1) # DW_CFA_advance_loc\n\t"
+	".byte	0x0e	# DW_CFA_def_cfa_offset\n\t"
+	".uleb128 128\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 20f-17f\n"
+"17:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 19f-18f\n\t"
+	".byte	0x0d	# DW_OP_const4s\n"
+"18:\t"	".4byte	4b-.\n\t"
+	".byte	0x1c	# DW_OP_minus\n\t"
+	".byte	0x0d	# DW_OP_const4s\n"
+"19:\t"	".4byte	24f-.\n\t"
+	".byte	0x22	# DW_OP_plus\n"
+"20:\t"	".byte	0x40 + (5b-4b+1) # DW_CFA_advance_loc\n\t"
+	".byte	0x13	# DW_CFA_def_cfa_offset_sf\n\t"
+	".sleb128 16\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 22f-21f\n"
+"21:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 4b-5b\n"
+"22:\t"	".align 8\n"
+"23:\t"	".previous\n"
+"24:"
+	: : "r" (x), "m" (x), "r" (buf)
+	: "memory", "rax", "rdx", "rcx", "rsi", "rdi",
+	  "r8", "r9", "r10", "r11");
+#else
+# error Unsupported test architecture
+#endif
+}
+
+static int __attribute__((noinline))
+fn2 (void)
+{
+  foo (3);
+  return 0;
+}
+
+static int __attribute__((noinline))
+fn1 (void)
+{
+  fn2 ();
+  return 0;
+}
+
+static void *
+fn0 (void)
+{
+  char dummy __attribute__((cleanup (handler)));
+  fn1 ();
+  return 0;
+}
+
+int
+main (void)
+{
+  fn0 ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cleanup-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cleanup-2.c
new file mode 100644
index 000000000..2bd18025f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cleanup-2.c
@@ -0,0 +1,206 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-fexceptions -fnon-call-exceptions -fasynchronous-unwind-tables -O2" } */
+/* Test complex CFA value expressions.  */
+
+#include <unwind.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include <unistd.h>
+
+static _Unwind_Reason_Code
+force_unwind_stop (int version, _Unwind_Action actions,
+		   _Unwind_Exception_Class exc_class,
+		   struct _Unwind_Exception *exc_obj,
+		   struct _Unwind_Context *context,
+		   void *stop_parameter)
+{
+  if (actions & _UA_END_OF_STACK)
+    abort ();
+  return _URC_NO_REASON;
+}
+
+static void
+force_unwind ()
+{
+  struct _Unwind_Exception *exc = malloc (sizeof (*exc));
+  memset (&exc->exception_class, 0, sizeof (exc->exception_class));
+  exc->exception_cleanup = 0;
+
+  _Unwind_ForcedUnwind (exc, force_unwind_stop, 0);
+  abort ();
+}
+
+int count;
+
+static void
+counter (void *p __attribute__((unused)))
+{
+  ++count;
+}
+
+static void
+handler (void *p __attribute__((unused)))
+{
+  if (count != 2)
+    abort ();
+  _exit (0);
+}
+
+static int __attribute__((noinline))
+fn5 (void)
+{
+  char dummy __attribute__((cleanup (counter)));
+  force_unwind ();
+  return 0;
+}
+
+void
+bar (void)
+{
+  char dummy __attribute__((cleanup (counter)));
+  fn5 ();
+}
+
+void __attribute__((noinline))
+foo (int x)
+{
+  char buf[256];
+#ifdef __x86_64__
+  __asm (
+	"testl	%0, %0\n\t"
+	"jnz	1f\n\t"
+	".subsection 1\n\t"
+	".type	_L_mutex_lock_%=, @function\n"
+"_L_mutex_lock_%=:\n"
+"1:\t"	"leaq	%1, %%rdi\n"
+"2:\t"	"subq	$128, %%rsp\n"
+"3:\t"	"call	bar\n"
+"4:\t"	"addq	$128, %%rsp\n"
+"5:\t"	"jmp	21f\n"
+"6:\t"	".size _L_mutex_lock_%=, .-_L_mutex_lock_%=\n\t"
+	".previous\n\t"
+	".section	.eh_frame,\"a\",@progbits\n"
+"7:\t"	".long	9f-8f	# Length of Common Information Entry\n"
+"8:\t"	".long	0x0	# CIE Identifier Tag\n\t"
+	".byte	0x1	# CIE Version\n\t"
+	".ascii \"zR\\0\"	# CIE Augmentation\n\t"
+	".uleb128 0x1	# CIE Code Alignment Factor\n\t"
+	".sleb128 -8	# CIE Data Alignment Factor\n\t"
+	".byte	0x10	# CIE RA Column\n\t"
+	".uleb128 0x1	# Augmentation size\n\t"
+	".byte	0x1b	# FDE Encoding (pcrel sdata4)\n\t"
+	".byte	0xc	# DW_CFA_def_cfa\n\t"
+	".uleb128 0x7\n\t"
+	".uleb128 0x0\n\t"
+	".align 8\n"
+"9:\t"	".long	20f-10f	# FDE Length\n"
+"10:\t"	".long	10b-7b	# FDE CIE offset\n\t"
+	".long	1b-.	# FDE initial location\n\t"
+	".long	6b-1b	# FDE address range\n\t"
+	".uleb128 0x0	# Augmentation size\n\t"
+	/* This CFA expression computes the address right
+	   past the jnz instruction above, from %rip somewhere
+	   within the _L_mutex_lock_%= subsection.  */
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 19f-11f\n"
+"11:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 0\n"
+"12:\t"	".byte	0x12	# DW_OP_dup\n\t"
+	".byte	0x94	# DW_OP_deref_size\n\t"
+	".byte	1\n\t"
+	".byte	0x12	# DW_OP_dup\n\t"
+	".byte	0x08	# DW_OP_const1u\n\t"
+	".byte	0x48\n\t"
+	".byte	0x2e	# DW_OP_ne\n\t"
+	".byte	0x28	# DW_OP_bra\n\t"
+	".2byte	16f-13f\n"
+"13:\t"	".byte	0x13	# DW_OP_drop\n\t"
+	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 1\n\t"
+	".byte	0x12	# DW_OP_dup\n\t"
+	".byte	0x94	# DW_OP_deref_size\n\t"
+	".byte	1\n\t"
+	".byte	0x08	# DW_OP_const1u\n\t"
+	".byte	0x81\n\t"
+	".byte	0x2e	# DW_OP_ne\n\t"
+	".byte	0x28	# DW_OP_bra\n\t"
+	".2byte	15f-14f\n"
+"14:\t"	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 3b-2b-1\n\t"
+	".byte	0x2f	# DW_OP_skip\n\t"
+	".2byte	12b-15f\n"
+"15:\t"	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 2b-1b-1\n\t"
+	".byte	0x2f	# DW_OP_skip\n\t"
+	".2byte	12b-16f\n"
+"16:\t"	".byte	0x08	# DW_OP_const1u\n\t"
+	".byte	0xe8\n\t"
+	".byte	0x2e	# DW_OP_ne\n\t"
+	".byte	0x28	# DW_OP_bra\n\t"
+	".2byte	18f-17f\n"
+"17:\t"	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 4b-3b\n\t"
+	".byte	0x2f	# DW_OP_skip\n\t"
+	".2byte	12b-18f\n"
+"18:\t"	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 1\n\t"
+	".byte	0x12	# DW_OP_dup\n\t"
+	".byte	0x94	# DW_OP_deref_size\n\t"
+	".byte	4\n\t"
+	".byte	0x08	# DW_OP_const1u\n\t"
+	".byte	72 - (6b-5b) * 8 # (6b-5b) == 5 ? 32 : 56\n\t"
+	".byte	0x24	# DW_OP_shl\n\t"
+	".byte	0x08	# DW_OP_const1u\n\t"
+	".byte	72 - (6b-5b) * 8 # (6b-5b) == 5 ? 32 : 56\n\t"
+	".byte	0x26	# DW_OP_shra\n\t"
+	".byte	0x22	# DW_OP_plus\n\t"
+	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 6b-5b-1\n"
+"19:\t"	".byte	0x40 + (3b-1b) # DW_CFA_advance_loc\n\t"
+	".byte	0xe	# DW_CFA_def_cfa_offset\n\t"
+	".uleb128 128\n\t"
+	".byte	0x40 + (5b-3b) # DW_CFA_advance_loc\n\t"
+	".byte	0xe	# DW_CFA_def_cfa_offset\n\t"
+	".uleb128 0\n\t"
+	".align 8\n"
+"20:\t"	".previous\n"
+"21:"
+	: : "r" (x), "m" (x), "r" (buf)
+	: "memory", "rax", "rdx", "rcx", "rsi", "rdi",
+	  "r8", "r9", "r10", "r11");
+#else
+# error Unsupported test architecture
+#endif
+}
+
+static int __attribute__((noinline))
+fn2 (void)
+{
+  foo (3);
+  return 0;
+}
+
+static int __attribute__((noinline))
+fn1 (void)
+{
+  fn2 ();
+  return 0;
+}
+
+static void *
+fn0 (void)
+{
+  char dummy __attribute__((cleanup (handler)));
+  fn1 ();
+  return 0;
+}
+
+int
+main (void)
+{
+  fn0 ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/clobbers.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/clobbers.c
new file mode 100644
index 000000000..7e8b200c6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/clobbers.c
@@ -0,0 +1,35 @@
+/* Test asm clobbers on x86. */
+
+/* { dg-do run } */
+/* { dg-skip-if "" { ilp32 } { "-fpic" "-fPIC" } { "" } } */
+
+extern void abort (void);
+
+int main ()
+{
+        int i;
+        __asm__ ("movl $1,%0\n\txorl %%eax,%%eax" : "=r" (i) : : "eax");
+        if (i != 1)
+                abort ();
+	/* On darwin you can't call external functions from non-pic code,
+	   however, clobbering ebx isn't valid in pic code. Instead of
+	   disabling the whole test, just disable the ebx clobbering part.  */
+#if !(defined (__MACH__))
+        __asm__ ("movl $1,%0\n\txorl %%ebx,%%ebx" : "=r" (i) : : "ebx");
+        if (i != 1)
+                abort ();
+#endif
+        __asm__ ("movl $1,%0\n\txorl %%ecx,%%ecx" : "=r" (i) : : "ecx");
+        if (i != 1)
+                abort ();
+        __asm__ ("movl $1,%0\n\txorl %%edx,%%edx" : "=r" (i) : : "edx");
+        if (i != 1)
+                abort ();
+        __asm__ ("movl $1,%0\n\txorl %%esi,%%esi" : "=r" (i) : : "esi");
+        if (i != 1)
+                abort ();
+        __asm__ ("movl $1,%0\n\txorl %%edi,%%edi" : "=r" (i) : : "edi");
+        if (i != 1)
+                abort ();
+        return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov1.c
new file mode 100644
index 000000000..edbbda584
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov1.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* This test checks for absolute memory operands.  */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "sar\[^\\n\]*magic_namea" } } */
+/* { dg-final { scan-assembler "sar\[^\\n\]*magic_nameb" } } */
+/* { dg-final { scan-assembler "sar\[^\\n\]*magic_namec" } } */
+/* { dg-final { scan-assembler "shr\[^\\n\]*magic_named" } } */
+/* { dg-final { scan-assembler "shr\[^\\n\]*magic_namee" } } */
+/* { dg-final { scan-assembler "shr\[^\\n\]*magic_namef" } } */
+
+/* Check code generation for several conditional moves doable by single arithmetics.  */
+
+static int magic_namea;
+static char magic_nameb;
+static short magic_namec;
+static int magic_named;
+static char magic_namee;
+static short magic_namef;
+
+unsigned int gen;
+void m(void)
+{
+  magic_namec=magic_namec>=0?0:-1;
+  magic_namea=magic_namea>=0?0:-1;
+  magic_nameb=magic_nameb>=0?0:-1;
+  magic_named=magic_named>=0?0:1;
+  magic_namee=magic_namee>=0?0:1;
+  magic_namef=magic_namef>=0?0:1;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov2.c
new file mode 100644
index 000000000..2b7c696bb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "sbb" } } */
+
+/* This conditional move is fastest to be done using sbb.  */
+t(unsigned int a, unsigned int b)
+{
+  return (a<=b?5:-5);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov3.c
new file mode 100644
index 000000000..34df0aab7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "cmov\[^3\]" } } */
+
+/* This conditional move is fastest to be done using cmov.  */
+t(int a, int b)
+{
+  return (a<=b?5:-5);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov4.c
new file mode 100644
index 000000000..6a955eaeb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "cmov\[^4\]" } } */
+
+/* Verify that if conversion happends for memory references.  */
+int ARCHnodes;
+int *nodekind;
+float *nodekindf;
+t()
+{
+int i;
+/* Redefine nodekind to be 1 for all surface nodes */
+
+  for (i = 0; i < ARCHnodes; i++) {
+    nodekind[i] = (int) nodekindf[i];
+    if (nodekind[i] == 3)
+      nodekind[i] = 1;
+  }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov5.c
new file mode 100644
index 000000000..898323b44
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov5.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "sbb" } } */
+
+int
+t(float a, float b)
+{
+	return a<=b?0:-1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov6.c
new file mode 100644
index 000000000..535326e4c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov6.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "cmov\[^6\]" } } */
+
+/* Verify that blocks are converted to conditional moves.  */
+extern int bar (int, int);
+int foo (int c, int d, int e)
+{
+  int a, b;
+
+  if (c)
+    {
+      a = 10;
+      b = d;
+    }
+  else
+    {
+      a = e;
+      b = 20;
+    }
+  return bar (a, b);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov7.c
new file mode 100644
index 000000000..31b481654
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov7.c
@@ -0,0 +1,15 @@
+/* PR middle-end/33187 */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -march=k8 -mbranch-cost=5 -mfpmath=387" } */
+/* { dg-final { scan-assembler "fcmov" } } */
+
+/* compress_float_constant generates load + float_extend
+   sequence which combine pass failed to combine into
+   (set (reg:DF) (float_extend:DF (mem:SF (symbol_ref...)))).  */
+
+double
+sgn (double __x)
+{
+  return __x >= 0.0 ? 1.0 : -1.0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov8.c
new file mode 100644
index 000000000..639fb62b0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmov8.c
@@ -0,0 +1,13 @@
+/* PR target/36936 */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=i686" } */
+/* { dg-final { scan-assembler "cmov\[^8\]" } } */
+
+int
+foo (int x)
+{
+  if (x < 0)
+    x = 1;
+  return x;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmpxchg16b-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmpxchg16b-1.c
new file mode 100644
index 000000000..fd266f5a0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cmpxchg16b-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mcx16" } */
+
+typedef int TItype __attribute__ ((mode (TI)));
+
+TItype m_128;
+
+void test(TItype x_128)
+{
+  m_128 = __sync_val_compare_and_swap (&m_128, x_128, m_128);
+}
+
+/* { dg-final { scan-assembler "cmpxchg16b" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cold-attribute-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cold-attribute-1.c
new file mode 100644
index 000000000..db81ee837
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cold-attribute-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+#include <string.h>
+static inline
+__attribute__ ((cold))
+my_cold_memset (void *a, int b,int c)
+{
+  memset (a,b,c);
+}
+t(void *a,int b,int c)
+{
+  if (a)
+    my_cold_memset (a,b,40);
+}
+
+/* The IF conditional should be predicted as cold and my_cold_memset inlined
+   for size expanding memset as rep; stosb.  */
+/* { dg-final { scan-assembler "stosb" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cold-attribute-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cold-attribute-2.c
new file mode 100644
index 000000000..93ea90661
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cold-attribute-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+#include <string.h>
+t(int c)
+{
+  if (__builtin_expect (c, 0))
+    {
+      cold_hint ();
+      return c * 11;
+    }
+  return c;
+}
+
+/* { dg-final { scan-assembler "imul" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cold-attribute-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cold-attribute-3.c
new file mode 100644
index 000000000..5225428c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cold-attribute-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+#include <string.h>
+
+int
+__attribute__ ((cold))
+t(int c)
+{
+  return c * 11;
+}
+
+/* { dg-final { scan-assembler "imul" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cold-attribute-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cold-attribute-4.c
new file mode 100644
index 000000000..37a41e954
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cold-attribute-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+#include <string.h>
+
+int
+__attribute__ ((cold))
+t(int c)
+{
+  return -1;
+}
+
+/* { dg-final { scan-assembler "orl" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cold-attribute-4.s b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cold-attribute-4.s
new file mode 100644
index 000000000..68d05d09d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cold-attribute-4.s
@@ -0,0 +1,41 @@
+	.file	"cold-attribute-4.c"
+	.text
+	.p2align 4,,15
+.globl t
+	.type	t, @function
+t:
+.LFB14:
+	movl	$-1, %eax
+	ret
+.LFE14:
+	.size	t, .-t
+	.section	.eh_frame,"a",@progbits
+.Lframe1:
+	.long	.LECIE1-.LSCIE1
+.LSCIE1:
+	.long	0x0
+	.byte	0x1
+	.string	"zR"
+	.uleb128 0x1
+	.sleb128 -8
+	.byte	0x10
+	.uleb128 0x1
+	.byte	0x3
+	.byte	0xc
+	.uleb128 0x7
+	.uleb128 0x8
+	.byte	0x90
+	.uleb128 0x1
+	.align 8
+.LECIE1:
+.LSFDE1:
+	.long	.LEFDE1-.LASFDE1
+.LASFDE1:
+	.long	.LASFDE1-.Lframe1
+	.long	.LFB14
+	.long	.LFE14-.LFB14
+	.uleb128 0x0
+	.align 8
+.LEFDE1:
+	.ident	"GCC: (GNU) 4.1.2 20061115 (prerelease) (Debian 4.1.1-21)"
+	.section	.note.GNU-stack,"",@progbits
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/compress-float-387-pic.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/compress-float-387-pic.c
new file mode 100644
index 000000000..fa69eedaa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/compress-float-387-pic.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=387 -fpic" } */
+double foo (double x) {
+  return x + 1.75;
+}
+/* { dg-final { scan-assembler "flds" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/compress-float-387.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/compress-float-387.c
new file mode 100644
index 000000000..bed2986bc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/compress-float-387.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=387" } */
+double foo (double x) {
+  return x + 1.75;
+}
+/* { dg-final { scan-assembler "flds" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/compress-float-sse-pic.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/compress-float-sse-pic.c
new file mode 100644
index 000000000..2c9be7cd9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/compress-float-sse-pic.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=sse -fpic" } */
+double foo (double x) {
+  return x + 1.75;
+}
+/* { dg-final { scan-assembler "movsd" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/compress-float-sse.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/compress-float-sse.c
new file mode 100644
index 000000000..48db61111
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/compress-float-sse.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=sse" } */
+double foo (double x) {
+  return x + 1.75;
+}
+/* { dg-final { scan-assembler "movsd" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cvt-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cvt-1.c
new file mode 100644
index 000000000..9535725e5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/cvt-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8 -mfpmath=sse" } */
+/* { dg-final { scan-assembler "cvttsd2si" } } */
+/* { dg-final { scan-assembler "cvttss2si" } } */
+int a,a1;
+double b;
+float b1;
+t()
+{
+	a=b;
+	a1=b1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/darwin-fpmath.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/darwin-fpmath.c
new file mode 100644
index 000000000..7db694670
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/darwin-fpmath.c
@@ -0,0 +1,9 @@
+/* { dg-do compile { target i?86-*-darwin* } } */
+/* { dg-final { scan-assembler "addsd" } } */
+/* Do not add -msse or -msse2 or -mfpmath=sse to the options.  GCC is
+   supposed to use SSE math on Darwin by default, and libm won't work
+   right if it doesn't.  */
+double foo(double x, double y)
+{
+  return x + y;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/defines-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/defines-1.c
new file mode 100644
index 000000000..acc39f3f6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/defines-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=nocona -mno-sse" } */
+
+#if defined(__SSE__) || defined(__SSE2__) || defined(__SSE3__)
+#error
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/defines-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/defines-2.c
new file mode 100644
index 000000000..4383a059b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/defines-2.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=athlon64 -mno-mmx" } */
+
+#if defined(__MMX__) || defined(__3dNOW__) || defined(__3dNOW_A__)
+#error
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fastcall-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fastcall-1.c
new file mode 100644
index 000000000..9d7012391
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fastcall-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target i?86-*-mingw32* i?86-*-cygwin* } } */
+/* { dg-options "-std=gnu89" } */
+
+void
+__attribute__ ((fastcall))
+f1() { }
+
+void
+_fastcall
+f2() { }
+
+void
+__fastcall
+f3() { }
+
+void
+__attribute__ ((fastcall))
+f4(int x, int y, int z) { }
+
+/* Scan for global label with correct prefix and suffix.  */
+/* { dg-final { scan-assembler "\.globl\[ \t\]@f4@12" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c
new file mode 100644
index 000000000..bdfae5b3b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-options "-mpreferred-stack-boundary=4 -msse" } */
+/* { dg-require-effective-target ilp32 } */
+
+#include "sse-check.h"
+
+extern void abort(void);
+
+void __attribute__((fastcall, sseregparm)) foo(int i, int j, float x)
+{
+  static int last_align = -1;
+  int dummy, align = (int)&dummy & 15;
+  if (last_align < 0)
+    last_align = align;
+  else if (align != last_align)
+    abort ();
+}
+
+static void
+sse_test (void)
+{
+	foo(0,0,0.0);
+	foo(0,0,0.0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/float128-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/float128-1.c
new file mode 100644
index 000000000..9c6d22745
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/float128-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+extern void abort (void);
+
+typedef _Complex float __attribute__((mode(TC))) _Complex128;
+
+_Complex128 __attribute__ ((noinline))
+foo (_Complex128 x, _Complex128 y)
+{
+  return x * y;
+}
+
+static void
+sse2_test (void)
+{
+  _Complex128 a = 1.3q + 3.4qi, b = 5.6q + 7.8qi, c;
+
+  c = foo (a, b);
+  if (__real__(c) == 0.0q || __imag__ (c) == 0.0q)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/float128-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/float128-2.c
new file mode 100644
index 000000000..94408d2ef
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/float128-2.c
@@ -0,0 +1,17 @@
+/* PR target/36710 */
+
+/* { dg-do run { target *-*-linux* *-*-darwin* } } */
+/* { dg-options "-Os -msse2" } */
+
+#include "sse2-check.h"
+
+extern void abort (void);
+
+static void
+sse2_test (void)
+{
+  static volatile __float128 a = 123.0q;
+
+  if ((int) a != 123)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fpcvt-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fpcvt-1.c
new file mode 100644
index 000000000..1c3b9b834
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fpcvt-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler-not "cvtss2sd" } } */
+float a,b;
+main()
+{
+  a=b*3.0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fpcvt-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fpcvt-2.c
new file mode 100644
index 000000000..066d84365
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fpcvt-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler-not "cvtss2sd" } } */
+float a,b;
+main()
+{
+	return a<0.0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fpcvt-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fpcvt-3.c
new file mode 100644
index 000000000..569d21a5a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fpcvt-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler-not "cvtss2sd" } } */
+extern double fabs (double);
+float a,b;
+main()
+{
+	a=fabs(b)+1.0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fpcvt-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fpcvt-4.c
new file mode 100644
index 000000000..8257f6520
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fpcvt-4.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8 -mfpmath=sse" } */
+/* { dg-final { scan-assembler "cvtsi2sd" } } */
+/* Check that conversions will get folded.  */
+double
+t(short a)
+{
+  float b=a;
+  return b;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fpprec-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fpprec-1.c
new file mode 100644
index 000000000..0174e7c6c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/fpprec-1.c
@@ -0,0 +1,79 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-math-errno -fno-trapping-math -msse2 -mfpmath=sse" } */
+
+#include "sse2-check.h"
+
+double x[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(),
+	-0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023,  /* +-DBL_MAX */
+	-0x1p-52, 0x1p-52,				    /* +-DBL_EPSILON */
+	/* nextafter/before 0.5, 1.0 and 1.5 */
+	0x1.0000000000001p-1, 0x1.fffffffffffffp-2,
+	0x1.0000000000001p+0, 0x1.fffffffffffffp-1,
+	0x1.8000000000001p+0, 0x1.7ffffffffffffp+0,
+	-0.0, 0.0, -0.5, 0.5, -1.0, 1.0, -1.5, 1.5, -2.0, 2.0,
+	-2.5, 2.5 };
+#define NUM (sizeof(x)/sizeof(double))
+
+double expect_round[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(),
+	-0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023,
+	-0.0, 0.0,
+	1.0, 0.0, 1.0, 1.0, 2.0, 1.0,
+	-0.0, 0.0, -1.0, 1.0, -1.0, 1.0, -2.0, 2.0, -2.0, 2.0,
+	-3.0, 3.0 };
+
+double expect_rint[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(),
+        -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023,
+        -0.0, 0.0,
+        1.0, 0.0, 1.0, 1.0, 2.0, 1.0,
+        -0.0, 0.0, -0.0, 0.0, -1.0, 1.0, -2.0, 2.0, -2.0, 2.0,
+        -2.0, 2.0 };
+
+double expect_floor[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(),
+        -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023,
+        -1.0, 0.0,
+        0.0, 0.0, 1.0, 0.0, 1.0, 1.0,
+        -0.0, 0.0, -1.0, 0.0, -1.0, 1.0, -2.0, 1.0, -2.0, 2.0,
+        -3.0, 2.0 };
+
+double expect_ceil[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(),
+        -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023,
+        -0.0, 1.0,
+        1.0, 1.0, 2.0, 1.0, 2.0, 2.0,
+        -0.0, 0.0, -0.0, 1.0, -1.0, 1.0, -1.0, 2.0, -2.0, 2.0,
+        -2.0, 3.0 };
+
+double expect_trunc[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(),
+        -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023,
+        -0.0, 0.0,
+        0.0, 0.0, 1.0, 0.0, 1.0, 1.0,
+        -0.0, 0.0, -0.0, 0.0, -1.0, 1.0, -1.0, 1.0, -2.0, 2.0,
+        -2.0, 2.0 };
+
+
+#define CHECK(fn) \
+void check_ ## fn (void) \
+{ \
+  int i; \
+  for (i = 0; i < NUM; ++i) \
+    { \
+      double res = __builtin_ ## fn (x[i]); \
+      if (__builtin_memcmp (&res, &expect_ ## fn [i], sizeof(double)) != 0) \
+        printf( # fn " [%i]: %.18e %.18e\n", i, expect_ ## fn [i], res), abort (); \
+    } \
+}
+
+CHECK(round)
+CHECK(rint)
+CHECK(floor)
+CHECK(ceil)
+CHECK(trunc)
+
+static void
+sse2_test (void)
+{
+  check_round ();
+  check_rint ();
+  check_floor ();
+  check_ceil ();
+  check_trunc ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-1.c
new file mode 100644
index 000000000..1416c75f3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-1.c
@@ -0,0 +1,34 @@
+/* Test whether using target specific options, we can generate SSE2 code on
+   32-bit, which does not generate SSE2 by default, but still generate 387 code
+   for a function that doesn't use attribute((option)).  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O3 -ftree-vectorize -march=i386" } */
+/* { dg-final { scan-assembler "addps\[ \t\]" } } */
+/* { dg-final { scan-assembler "fsubs\[ \t\]" } } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+static float a[SIZE] __attribute__((__aligned__(16)));
+static float b[SIZE] __attribute__((__aligned__(16)));
+static float c[SIZE] __attribute__((__aligned__(16)));
+
+void sse_addnums (void) __attribute__ ((__target__ ("sse2")));
+
+void
+sse_addnums (void)
+{
+  int i = 0;
+  for (; i < SIZE; ++i)
+    a[i] = b[i] + c[i];
+}
+
+void
+i387_subnums (void)
+{
+  int i = 0;
+  for (; i < SIZE; ++i)
+    a[i] = b[i] - c[i];
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-10.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-10.c
new file mode 100644
index 000000000..9526e7df2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-10.c
@@ -0,0 +1,15 @@
+/* PR target/36936 */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=i686" } */
+/* { dg-final { scan-assembler-not "cmov" } } */
+
+extern int foo (int) __attribute__((__target__("arch=i386")));
+
+int
+foo (int x)
+{
+  if (x < 0)
+    x = 1;
+  return x;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-11.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-11.c
new file mode 100644
index 000000000..065ca3cca
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-11.c
@@ -0,0 +1,15 @@
+/* PR target/36936 */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=i386" } */
+/* { dg-final { scan-assembler "cmov" } } */
+
+extern int foo (int) __attribute__((__target__("arch=i686")));
+
+int
+foo (int x)
+{
+  if (x < 0)
+    x = 1;
+  return x;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-2.c
new file mode 100644
index 000000000..e3628e302
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-2.c
@@ -0,0 +1,99 @@
+/* Test whether using target specific options, we can generate SSE5 code.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -march=k8" } */
+
+extern void exit (int);
+
+#define SSE5_ATTR __attribute__((__target__("sse5,fused-madd")))
+extern float  flt_mul_add     (float a, float b, float c) SSE5_ATTR;
+extern float  flt_mul_sub     (float a, float b, float c) SSE5_ATTR;
+extern float  flt_neg_mul_add (float a, float b, float c) SSE5_ATTR;
+extern float  flt_neg_mul_sub (float a, float b, float c) SSE5_ATTR;
+
+extern double dbl_mul_add     (double a, double b, double c) SSE5_ATTR;
+extern double dbl_mul_sub     (double a, double b, double c) SSE5_ATTR;
+extern double dbl_neg_mul_add (double a, double b, double c) SSE5_ATTR;
+extern double dbl_neg_mul_sub (double a, double b, double c) SSE5_ATTR;
+
+float
+flt_mul_add (float a, float b, float c)
+{
+  return (a * b) + c;
+}
+
+double
+dbl_mul_add (double a, double b, double c)
+{
+  return (a * b) + c;
+}
+
+float
+flt_mul_sub (float a, float b, float c)
+{
+  return (a * b) - c;
+}
+
+double
+dbl_mul_sub (double a, double b, double c)
+{
+  return (a * b) - c;
+}
+
+float
+flt_neg_mul_add (float a, float b, float c)
+{
+  return (-(a * b)) + c;
+}
+
+double
+dbl_neg_mul_add (double a, double b, double c)
+{
+  return (-(a * b)) + c;
+}
+
+float
+flt_neg_mul_sub (float a, float b, float c)
+{
+  return (-(a * b)) - c;
+}
+
+double
+dbl_neg_mul_sub (double a, double b, double c)
+{
+  return (-(a * b)) - c;
+}
+
+float  f[10] = { 2, 3, 4 };
+double d[10] = { 2, 3, 4 };
+
+int main ()
+{
+  f[3] = flt_mul_add (f[0], f[1], f[2]);
+  f[4] = flt_mul_sub (f[0], f[1], f[2]);
+  f[5] = flt_neg_mul_add (f[0], f[1], f[2]);
+  f[6] = flt_neg_mul_sub (f[0], f[1], f[2]);
+
+  d[3] = dbl_mul_add (d[0], d[1], d[2]);
+  d[4] = dbl_mul_sub (d[0], d[1], d[2]);
+  d[5] = dbl_neg_mul_add (d[0], d[1], d[2]);
+  d[6] = dbl_neg_mul_sub (d[0], d[1], d[2]);
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "fmaddss" } } */
+/* { dg-final { scan-assembler "fmaddsd" } } */
+/* { dg-final { scan-assembler "fmsubss" } } */
+/* { dg-final { scan-assembler "fmsubsd" } } */
+/* { dg-final { scan-assembler "fnmaddss" } } */
+/* { dg-final { scan-assembler "fnmaddsd" } } */
+/* { dg-final { scan-assembler "fnmsubss" } } */
+/* { dg-final { scan-assembler "fnmsubsd" } } */
+/* { dg-final { scan-assembler "call\t(.*)flt_mul_add" } } */
+/* { dg-final { scan-assembler "call\t(.*)flt_mul_sub" } } */
+/* { dg-final { scan-assembler "call\t(.*)flt_neg_mul_add" } } */
+/* { dg-final { scan-assembler "call\t(.*)flt_neg_mul_sub" } } */
+/* { dg-final { scan-assembler "call\t(.*)dbl_mul_add" } } */
+/* { dg-final { scan-assembler "call\t(.*)dbl_mul_sub" } } */
+/* { dg-final { scan-assembler "call\t(.*)dbl_neg_mul_add" } } */
+/* { dg-final { scan-assembler "call\t(.*)dbl_neg_mul_sub" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-3.c
new file mode 100644
index 000000000..01c7e4ca0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-3.c
@@ -0,0 +1,67 @@
+/* Test whether using target specific options, we can generate popcnt by
+   setting the architecture.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -march=k8" } */
+
+extern void exit (int);
+extern void abort (void);
+
+#define SSE4A_ATTR __attribute__((__target__("arch=amdfam10")))
+#define SSE42_ATTR __attribute__((__target__("sse4.2")))
+
+static int sse4a_pop_i (int a) SSE4A_ATTR;
+static long sse42_pop_l (long a) SSE42_ATTR;
+static int generic_pop_i (int a);
+static long generic_pop_l (long a);
+
+static
+int sse4a_pop_i (int a)
+{
+  return __builtin_popcount (a);
+}
+
+static
+long sse42_pop_l (long a)
+{
+  return __builtin_popcountl (a);
+}
+
+static
+int generic_pop_i (int a)
+{
+  return __builtin_popcount (a);
+}
+
+static
+long generic_pop_l (long a)
+{
+  return __builtin_popcountl (a);
+}
+
+int five = 5;
+long seven = 7;
+
+int main ()
+{
+  if (sse4a_pop_i (five) != 2)
+    abort ();
+
+  if (sse42_pop_l (seven) != 3L)
+    abort ();
+
+  if (generic_pop_i (five) != 2)
+    abort ();
+
+  if (generic_pop_l (seven) != 3L)
+    abort ();
+
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "popcntl" { target { ! *-*-darwin* } } } } */
+/* { dg-final { scan-assembler "popcntq" { target { ! *-*-darwin* } } } } */
+/* { dg-final { scan-assembler-times "popcnt" 2 { target *-*-darwin* } } } */
+/* { dg-final { scan-assembler "call\t(.*)sse4a_pop_i" } } */
+/* { dg-final { scan-assembler "call\t(.*)sse42_pop_l" } } */
+/* { dg-final { scan-assembler "call\t(.*)popcountdi2" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-4.c
new file mode 100644
index 000000000..98f545a1c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-4.c
@@ -0,0 +1,14 @@
+/* Test some error conditions with function specific options.  */
+/* { dg-do compile } */
+
+/* no sse500 switch */
+extern void error1 (void) __attribute__((__target__("sse500"))); /* { dg-error "unknown" } */
+
+/* Multiple arch switches */
+extern void error2 (void) __attribute__((__target__("arch=core2,arch=k8"))); /* { dg-error "already specified" } */
+
+/* Unknown tune target */
+extern void error3 (void) __attribute__((__target__("tune=foobar"))); /* { dg-error "bad value" } */
+
+/* option on a variable */
+extern int error4 __attribute__((__target__("sse2"))); /* { dg-warning "ignored" } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-5.c
new file mode 100644
index 000000000..378dca5f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-5.c
@@ -0,0 +1,125 @@
+/* Test whether all of the 32-bit function specific options are accepted
+   without error.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+
+extern void test_abm (void)			__attribute__((__target__("abm")));
+extern void test_aes (void)			__attribute__((__target__("aes")));
+extern void test_fused_madd (void)		__attribute__((__target__("fused-madd")));
+extern void test_mmx (void)			__attribute__((__target__("mmx")));
+extern void test_pclmul (void)			__attribute__((__target__("pclmul")));
+extern void test_popcnt (void)			__attribute__((__target__("popcnt")));
+extern void test_recip (void)			__attribute__((__target__("recip")));
+extern void test_sse (void)			__attribute__((__target__("sse")));
+extern void test_sse2 (void)			__attribute__((__target__("sse2")));
+extern void test_sse3 (void)			__attribute__((__target__("sse3")));
+extern void test_sse4 (void)			__attribute__((__target__("sse4")));
+extern void test_sse4_1 (void)			__attribute__((__target__("sse4.1")));
+extern void test_sse4_2 (void)			__attribute__((__target__("sse4.2")));
+extern void test_sse4a (void)			__attribute__((__target__("sse4a")));
+extern void test_sse5 (void)			__attribute__((__target__("sse5")));
+extern void test_ssse3 (void)			__attribute__((__target__("ssse3")));
+
+extern void test_no_abm (void)			__attribute__((__target__("no-abm")));
+extern void test_no_aes (void)			__attribute__((__target__("no-aes")));
+extern void test_no_fused_madd (void)		__attribute__((__target__("no-fused-madd")));
+extern void test_no_mmx (void)			__attribute__((__target__("no-mmx")));
+extern void test_no_pclmul (void)		__attribute__((__target__("no-pclmul")));
+extern void test_no_popcnt (void)		__attribute__((__target__("no-popcnt")));
+extern void test_no_recip (void)		__attribute__((__target__("no-recip")));
+extern void test_no_sse (void)			__attribute__((__target__("no-sse")));
+extern void test_no_sse2 (void)			__attribute__((__target__("no-sse2")));
+extern void test_no_sse3 (void)			__attribute__((__target__("no-sse3")));
+extern void test_no_sse4 (void)			__attribute__((__target__("no-sse4")));
+extern void test_no_sse4_1 (void)		__attribute__((__target__("no-sse4.1")));
+extern void test_no_sse4_2 (void)		__attribute__((__target__("no-sse4.2")));
+extern void test_no_sse4a (void)		__attribute__((__target__("no-sse4a")));
+extern void test_no_sse5 (void)			__attribute__((__target__("no-sse5")));
+extern void test_no_ssse3 (void)		__attribute__((__target__("no-ssse3")));
+
+extern void test_arch_i386 (void)		__attribute__((__target__("arch=i386")));
+extern void test_arch_i486 (void)		__attribute__((__target__("arch=i486")));
+extern void test_arch_i586 (void)		__attribute__((__target__("arch=i586")));
+extern void test_arch_pentium (void)		__attribute__((__target__("arch=pentium")));
+extern void test_arch_pentium_mmx (void)	__attribute__((__target__("arch=pentium-mmx")));
+extern void test_arch_winchip_c6 (void)		__attribute__((__target__("arch=winchip-c6")));
+extern void test_arch_winchip2 (void)		__attribute__((__target__("arch=winchip2")));
+extern void test_arch_c3 (void)			__attribute__((__target__("arch=c3")));
+extern void test_arch_c3_2 (void)		__attribute__((__target__("arch=c3-2")));
+extern void test_arch_i686 (void)		__attribute__((__target__("arch=i686")));
+extern void test_arch_pentiumpro (void)		__attribute__((__target__("arch=pentiumpro")));
+extern void test_arch_pentium2 (void)		__attribute__((__target__("arch=pentium2")));
+extern void test_arch_pentium3 (void)		__attribute__((__target__("arch=pentium3")));
+extern void test_arch_pentium3m (void)		__attribute__((__target__("arch=pentium3m")));
+extern void test_arch_pentium_m (void)		__attribute__((__target__("arch=pentium-m")));
+extern void test_arch_pentium4 (void)		__attribute__((__target__("arch=pentium4")));
+extern void test_arch_pentium4m (void)		__attribute__((__target__("arch=pentium4m")));
+extern void test_arch_prescott (void)		__attribute__((__target__("arch=prescott")));
+extern void test_arch_nocona (void)		__attribute__((__target__("arch=nocona")));
+extern void test_arch_core2 (void)		__attribute__((__target__("arch=core2")));
+extern void test_arch_geode (void)		__attribute__((__target__("arch=geode")));
+extern void test_arch_k6 (void)			__attribute__((__target__("arch=k6")));
+extern void test_arch_k6_2 (void)		__attribute__((__target__("arch=k6-2")));
+extern void test_arch_k6_3 (void)		__attribute__((__target__("arch=k6-3")));
+extern void test_arch_athlon (void)		__attribute__((__target__("arch=athlon")));
+extern void test_arch_athlon_tbird (void)	__attribute__((__target__("arch=athlon-tbird")));
+extern void test_arch_athlon_4 (void)		__attribute__((__target__("arch=athlon-4")));
+extern void test_arch_athlon_xp (void)		__attribute__((__target__("arch=athlon-xp")));
+extern void test_arch_athlon_mp (void)		__attribute__((__target__("arch=athlon-mp")));
+extern void test_arch_k8 (void)			__attribute__((__target__("arch=k8")));
+extern void test_arch_k8_sse3 (void)		__attribute__((__target__("arch=k8-sse3")));
+extern void test_arch_opteron (void)		__attribute__((__target__("arch=opteron")));
+extern void test_arch_opteron_sse3 (void)	__attribute__((__target__("arch=opteron-sse3")));
+extern void test_arch_athlon64 (void)		__attribute__((__target__("arch=athlon64")));
+extern void test_arch_athlon64_sse3 (void)	__attribute__((__target__("arch=athlon64-sse3")));
+extern void test_arch_athlon_fx (void)		__attribute__((__target__("arch=athlon-fx")));
+extern void test_arch_amdfam10 (void)		__attribute__((__target__("arch=amdfam10")));
+extern void test_arch_barcelona (void)		__attribute__((__target__("arch=barcelona")));
+extern void test_arch_foo (void)		__attribute__((__target__("arch=foo"))); /* { dg-error "bad value" } */
+
+extern void test_tune_i386 (void)		__attribute__((__target__("tune=i386")));
+extern void test_tune_i486 (void)		__attribute__((__target__("tune=i486")));
+extern void test_tune_i586 (void)		__attribute__((__target__("tune=i586")));
+extern void test_tune_pentium (void)		__attribute__((__target__("tune=pentium")));
+extern void test_tune_pentium_mmx (void)	__attribute__((__target__("tune=pentium-mmx")));
+extern void test_tune_winchip_c6 (void)		__attribute__((__target__("tune=winchip-c6")));
+extern void test_tune_winchip2 (void)		__attribute__((__target__("tune=winchip2")));
+extern void test_tune_c3 (void)			__attribute__((__target__("tune=c3")));
+extern void test_tune_c3_2 (void)		__attribute__((__target__("tune=c3-2")));
+extern void test_tune_i686 (void)		__attribute__((__target__("tune=i686")));
+extern void test_tune_pentiumpro (void)		__attribute__((__target__("tune=pentiumpro")));
+extern void test_tune_pentium2 (void)		__attribute__((__target__("tune=pentium2")));
+extern void test_tune_pentium3 (void)		__attribute__((__target__("tune=pentium3")));
+extern void test_tune_pentium3m (void)		__attribute__((__target__("tune=pentium3m")));
+extern void test_tune_pentium_m (void)		__attribute__((__target__("tune=pentium-m")));
+extern void test_tune_pentium4 (void)		__attribute__((__target__("tune=pentium4")));
+extern void test_tune_pentium4m (void)		__attribute__((__target__("tune=pentium4m")));
+extern void test_tune_prescott (void)		__attribute__((__target__("tune=prescott")));
+extern void test_tune_nocona (void)		__attribute__((__target__("tune=nocona")));
+extern void test_tune_core2 (void)		__attribute__((__target__("tune=core2")));
+extern void test_tune_geode (void)		__attribute__((__target__("tune=geode")));
+extern void test_tune_k6 (void)			__attribute__((__target__("tune=k6")));
+extern void test_tune_k6_2 (void)		__attribute__((__target__("tune=k6-2")));
+extern void test_tune_k6_3 (void)		__attribute__((__target__("tune=k6-3")));
+extern void test_tune_athlon (void)		__attribute__((__target__("tune=athlon")));
+extern void test_tune_athlon_tbird (void)	__attribute__((__target__("tune=athlon-tbird")));
+extern void test_tune_athlon_4 (void)		__attribute__((__target__("tune=athlon-4")));
+extern void test_tune_athlon_xp (void)		__attribute__((__target__("tune=athlon-xp")));
+extern void test_tune_athlon_mp (void)		__attribute__((__target__("tune=athlon-mp")));
+extern void test_tune_k8 (void)			__attribute__((__target__("tune=k8")));
+extern void test_tune_k8_sse3 (void)		__attribute__((__target__("tune=k8-sse3")));
+extern void test_tune_opteron (void)		__attribute__((__target__("tune=opteron")));
+extern void test_tune_opteron_sse3 (void)	__attribute__((__target__("tune=opteron-sse3")));
+extern void test_tune_athlon64 (void)		__attribute__((__target__("tune=athlon64")));
+extern void test_tune_athlon64_sse3 (void)	__attribute__((__target__("tune=athlon64-sse3")));
+extern void test_tune_athlon_fx (void)		__attribute__((__target__("tune=athlon-fx")));
+extern void test_tune_amdfam10 (void)		__attribute__((__target__("tune=amdfam10")));
+extern void test_tune_barcelona (void)		__attribute__((__target__("tune=barcelona")));
+extern void test_tune_generic (void)		__attribute__((__target__("tune=generic")));
+extern void test_tune_foo (void)		__attribute__((__target__("tune=foo"))); /* { dg-error "bad value" } */
+
+extern void test_fpmath_sse (void)		__attribute__((__target__("sse2,fpmath=sse")));
+extern void test_fpmath_387 (void)		__attribute__((__target__("sse2,fpmath=387")));
+extern void test_fpmath_sse_387 (void)		__attribute__((__target__("sse2,fpmath=sse+387")));
+extern void test_fpmath_387_sse (void)		__attribute__((__target__("sse2,fpmath=387+sse")));
+extern void test_fpmath_both (void)		__attribute__((__target__("sse2,fpmath=both")));
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-6.c
new file mode 100644
index 000000000..6b526c2dc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-6.c
@@ -0,0 +1,71 @@
+/* Test whether all of the 64-bit function specific options are accepted
+   without error.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+
+extern void test_abm (void)			__attribute__((__target__("abm")));
+extern void test_aes (void)			__attribute__((__target__("aes")));
+extern void test_fused_madd (void)		__attribute__((__target__("fused-madd")));
+extern void test_mmx (void)			__attribute__((__target__("mmx")));
+extern void test_pclmul (void)			__attribute__((__target__("pclmul")));
+extern void test_popcnt (void)			__attribute__((__target__("popcnt")));
+extern void test_recip (void)			__attribute__((__target__("recip")));
+extern void test_sse (void)			__attribute__((__target__("sse")));
+extern void test_sse2 (void)			__attribute__((__target__("sse2")));
+extern void test_sse3 (void)			__attribute__((__target__("sse3")));
+extern void test_sse4 (void)			__attribute__((__target__("sse4")));
+extern void test_sse4_1 (void)			__attribute__((__target__("sse4.1")));
+extern void test_sse4_2 (void)			__attribute__((__target__("sse4.2")));
+extern void test_sse4a (void)			__attribute__((__target__("sse4a")));
+extern void test_sse5 (void)			__attribute__((__target__("sse5")));
+extern void test_ssse3 (void)			__attribute__((__target__("ssse3")));
+
+extern void test_no_abm (void)			__attribute__((__target__("no-abm")));
+extern void test_no_aes (void)			__attribute__((__target__("no-aes")));
+extern void test_no_fused_madd (void)		__attribute__((__target__("no-fused-madd")));
+extern void test_no_mmx (void)			__attribute__((__target__("no-mmx")));
+extern void test_no_pclmul (void)		__attribute__((__target__("no-pclmul")));
+extern void test_no_popcnt (void)		__attribute__((__target__("no-popcnt")));
+extern void test_no_recip (void)		__attribute__((__target__("no-recip")));
+extern void test_no_sse (void)			__attribute__((__target__("no-sse")));
+extern void test_no_sse2 (void)			__attribute__((__target__("no-sse2")));
+extern void test_no_sse3 (void)			__attribute__((__target__("no-sse3")));
+extern void test_no_sse4 (void)			__attribute__((__target__("no-sse4")));
+extern void test_no_sse4_1 (void)		__attribute__((__target__("no-sse4.1")));
+extern void test_no_sse4_2 (void)		__attribute__((__target__("no-sse4.2")));
+extern void test_no_sse4a (void)		__attribute__((__target__("no-sse4a")));
+extern void test_no_sse5 (void)			__attribute__((__target__("no-sse5")));
+extern void test_no_ssse3 (void)		__attribute__((__target__("no-ssse3")));
+
+extern void test_arch_nocona (void)		__attribute__((__target__("arch=nocona")));
+extern void test_arch_core2 (void)		__attribute__((__target__("arch=core2")));
+extern void test_arch_k8 (void)			__attribute__((__target__("arch=k8")));
+extern void test_arch_k8_sse3 (void)		__attribute__((__target__("arch=k8-sse3")));
+extern void test_arch_opteron (void)		__attribute__((__target__("arch=opteron")));
+extern void test_arch_opteron_sse3 (void)	__attribute__((__target__("arch=opteron-sse3")));
+extern void test_arch_athlon64 (void)		__attribute__((__target__("arch=athlon64")));
+extern void test_arch_athlon64_sse3 (void)	__attribute__((__target__("arch=athlon64-sse3")));
+extern void test_arch_athlon_fx (void)		__attribute__((__target__("arch=athlon-fx")));
+extern void test_arch_amdfam10 (void)		__attribute__((__target__("arch=amdfam10")));
+extern void test_arch_barcelona (void)		__attribute__((__target__("arch=barcelona")));
+extern void test_arch_foo (void)		__attribute__((__target__("arch=foo"))); /* { dg-error "bad value" } */
+
+extern void test_tune_nocona (void)		__attribute__((__target__("tune=nocona")));
+extern void test_tune_core2 (void)		__attribute__((__target__("tune=core2")));
+extern void test_tune_k8 (void)			__attribute__((__target__("tune=k8")));
+extern void test_tune_k8_sse3 (void)		__attribute__((__target__("tune=k8-sse3")));
+extern void test_tune_opteron (void)		__attribute__((__target__("tune=opteron")));
+extern void test_tune_opteron_sse3 (void)	__attribute__((__target__("tune=opteron-sse3")));
+extern void test_tune_athlon64 (void)		__attribute__((__target__("tune=athlon64")));
+extern void test_tune_athlon64_sse3 (void)	__attribute__((__target__("tune=athlon64-sse3")));
+extern void test_tune_athlon_fx (void)		__attribute__((__target__("tune=athlon-fx")));
+extern void test_tune_amdfam10 (void)		__attribute__((__target__("tune=amdfam10")));
+extern void test_tune_barcelona (void)		__attribute__((__target__("tune=barcelona")));
+extern void test_tune_generic (void)		__attribute__((__target__("tune=generic")));
+extern void test_tune_foo (void)		__attribute__((__target__("tune=foo"))); /* { dg-error "bad value" } */
+
+extern void test_fpmath_sse (void)		__attribute__((__target__("sse2,fpmath=sse")));
+extern void test_fpmath_387 (void)		__attribute__((__target__("sse2,fpmath=387")));
+extern void test_fpmath_sse_387 (void)		__attribute__((__target__("sse2,fpmath=sse+387")));
+extern void test_fpmath_387_sse (void)		__attribute__((__target__("sse2,fpmath=387+sse")));
+extern void test_fpmath_both (void)		__attribute__((__target__("sse2,fpmath=both")));
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-7.c
new file mode 100644
index 000000000..56b549050
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-7.c
@@ -0,0 +1,13 @@
+/* Test whether using target specific options, we can generate the reciprocal
+   square root instruction.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8 -mno-recip -mfpmath=sse -ffast-math" } */
+
+float do_recip  (float a) __attribute__((__target__("recip")));
+float do_normal (float a);
+
+float do_recip  (float a) { return 1.0f / __builtin_sqrtf (a); }
+float do_normal (float a) { return 1.0f / __builtin_sqrtf (a); }
+
+/* { dg-final { scan-assembler "sqrtss" } } */
+/* { dg-final { scan-assembler "rsqrtss" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-8.c
new file mode 100644
index 000000000..2478c672d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-8.c
@@ -0,0 +1,161 @@
+/* Test whether using target specific options, we can use the x86 builtin
+   functions in functions with the appropriate function specific options.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8 -mfpmath=sse" } */
+
+typedef float     __m128  __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef double    __m128d __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef int	  __m128w __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#ifdef __SSE3__
+#error "-msse3 should not be set for this test"
+#endif
+
+__m128d sse3_hsubpd (__m128d a, __m128d b) __attribute__((__target__("sse3")));
+__m128d generic_hsubpd (__m128d a, __m128d b);
+
+__m128d
+sse3_hsubpd (__m128d a, __m128d b)
+{
+  return __builtin_ia32_hsubpd (a, b);
+}
+
+__m128d
+generic_hsubpd (__m128d a, __m128d b)
+{
+  return __builtin_ia32_hsubpd (a, b);			/* { dg-error "needs isa option" } */
+}
+
+#ifdef __SSSE3__
+#error "-mssse3 should not be set for this test"
+#endif
+
+__m128w ssse3_psignd128 (__m128w a, __m128w b) __attribute__((__target__("ssse3")));
+__m128w generic_psignd (__m128w ab, __m128w b);
+
+__m128w
+ssse3_psignd128 (__m128w a, __m128w b)
+{
+  return __builtin_ia32_psignd128 (a, b);
+}
+
+__m128w
+generic_psignd128 (__m128w a, __m128w b)
+{
+  return __builtin_ia32_psignd128 (a, b);		/* { dg-error "needs isa option" } */
+}
+
+#ifdef __SSE4_1__
+#error "-msse4.1 should not be set for this test"
+#endif
+
+__m128d sse4_1_blendvpd (__m128d a, __m128d b, __m128d c) __attribute__((__target__("sse4.1")));
+__m128d generic_blendvpd (__m128d a, __m128d b, __m128d c);
+
+__m128d
+sse4_1_blendvpd  (__m128d a, __m128d b, __m128d c)
+{
+  return __builtin_ia32_blendvpd (a, b, c);
+}
+
+__m128d
+generic_blendvpd  (__m128d a, __m128d b, __m128d c)
+{
+  return __builtin_ia32_blendvpd (a, b, c);		/* { dg-error "needs isa option" } */
+}
+
+#ifdef __SSE4_2__
+#error "-msse4.2 should not be set for this test"
+#endif
+
+__m128i sse4_2_pcmpgtq (__m128i a, __m128i b) __attribute__((__target__("sse4.2")));
+__m128i generic_pcmpgtq (__m128i ab, __m128i b);
+
+__m128i
+sse4_2_pcmpgtq (__m128i a, __m128i b)
+{
+  return __builtin_ia32_pcmpgtq (a, b);
+}
+
+__m128i
+generic_pcmpgtq (__m128i a, __m128i b)
+{
+  return __builtin_ia32_pcmpgtq (a, b);			/* { dg-error "needs isa option" } */
+}
+
+#ifdef __SSE4A__
+#error "-msse4a should not be set for this test"
+#endif
+
+__m128i sse4_2_insertq (__m128i a, __m128i b) __attribute__((__target__("sse4a")));
+__m128i generic_insertq (__m128i ab, __m128i b);
+
+__m128i
+sse4_2_insertq (__m128i a, __m128i b)
+{
+  return __builtin_ia32_insertq (a, b);
+}
+
+__m128i
+generic_insertq (__m128i a, __m128i b)
+{
+  return __builtin_ia32_insertq (a, b);			/* { dg-error "needs isa option" } */
+}
+
+#ifdef __SSE5__
+#error "-msse5 should not be set for this test"
+#endif
+
+__m128d sse5_fmaddpd (__m128d a, __m128d b, __m128d c) __attribute__((__target__("sse5")));
+__m128d generic_fmaddpd (__m128d a, __m128d b, __m128d c);
+
+__m128d
+sse5_fmaddpd  (__m128d a, __m128d b, __m128d c)
+{
+  return __builtin_ia32_fmaddpd (a, b, c);
+}
+
+__m128d
+generic_fmaddpd  (__m128d a, __m128d b, __m128d c)
+{
+  return __builtin_ia32_fmaddpd (a, b, c);		/* { dg-error "needs isa option" } */
+}
+
+#ifdef __AES__
+#error "-maes should not be set for this test"
+#endif
+
+__m128i aes_aesimc128 (__m128i a) __attribute__((__target__("aes")));
+__m128i generic_aesimc128 (__m128i a);
+
+__m128i
+aes_aesimc128 (__m128i a)
+{
+  return __builtin_ia32_aesimc128 (a);
+}
+
+__m128i
+generic_aesimc128 (__m128i a)
+{
+  return __builtin_ia32_aesimc128 (a);			/* { dg-error "needs isa option" } */
+}
+
+#ifdef __PCLMUL__
+#error "-mpclmul should not be set for this test"
+#endif
+
+__m128i pclmul_pclmulqdq128 (__m128i a, __m128i b) __attribute__((__target__("pclmul")));
+__m128i generic_pclmulqdq128 (__m128i a, __m128i b);
+
+__m128i
+pclmul_pclmulqdq128 (__m128i a, __m128i b)
+{
+  return __builtin_ia32_pclmulqdq128 (a, b, 5);
+}
+
+__m128i
+generic_pclmulqdq128 (__m128i a, __m128i b)
+{
+  return __builtin_ia32_pclmulqdq128 (a, b, 5);		/* { dg-error "needs isa option" } */
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-9.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-9.c
new file mode 100644
index 000000000..1a7fc1b58
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/funcspec-9.c
@@ -0,0 +1,36 @@
+/* Test whether using target specific options, we can generate SSE5 code.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8 -mfpmath=sse -msse2" } */
+
+extern void exit (int);
+
+#ifdef __SSE5__
+#warning "__SSE5__ should not be defined before #pragma GCC target."
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("sse5,fused-madd")
+
+#ifndef __SSE5__
+#warning "__SSE5__ should have be defined after #pragma GCC target."
+#endif
+
+float
+flt_mul_add (float a, float b, float c)
+{
+  return (a * b) + c;
+}
+
+#pragma GCC pop_options
+#ifdef __SSE5__
+#warning "__SSE5__ should not be defined after #pragma GCC pop target."
+#endif
+
+double
+dbl_mul_add (double a, double b, double c)
+{
+  return (a * b) + c;
+}
+
+/* { dg-final { scan-assembler "fmaddss" } } */
+/* { dg-final { scan-assembler "addsd" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-1.c
new file mode 100644
index 000000000..598f2ddbc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-1.c
@@ -0,0 +1,23 @@
+/* { dg-do preprocess } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-march=i386" } */
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-2.c
new file mode 100644
index 000000000..fa6e7c654
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-2.c
@@ -0,0 +1,24 @@
+/* { dg-do preprocess } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-march=i486" } */
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-3.c
new file mode 100644
index 000000000..bc5a55989
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-3.c
@@ -0,0 +1,23 @@
+/* { dg-do preprocess } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-march=i586" } */
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-4.c
new file mode 100644
index 000000000..27928699f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-4.c
@@ -0,0 +1,23 @@
+/* { dg-do preprocess } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mcx16" } */
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/i386.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/i386.exp
new file mode 100644
index 000000000..f70c81f33
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/i386.exp
@@ -0,0 +1,165 @@
+# Copyright (C) 1997, 2004, 2007, 2008, 2009 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a x86 target.
+if { ![istarget i?86*-*-*] && ![istarget x86_64-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Return 1 if ssse3 instructions can be compiled.
+proc check_effective_target_ssse3 { } {
+    return [check_no_compiler_messages ssse3 object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef int __v4si __attribute__ ((__vector_size__ (16)));
+
+	__m128i _mm_abs_epi32 (__m128i __X)
+	{
+	    return (__m128i) __builtin_ia32_pabsd128 ((__v4si)__X);
+	}
+    } "-O2 -mssse3" ]
+}
+
+# Return 1 if sse4 instructions can be compiled.
+proc check_effective_target_sse4 { } {
+    return [check_no_compiler_messages sse4.1 object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef int __v4si __attribute__ ((__vector_size__ (16)));
+
+	__m128i _mm_mullo_epi32 (__m128i __X, __m128i __Y)
+	{
+	    return (__m128i) __builtin_ia32_pmulld128 ((__v4si)__X,
+						       (__v4si)__Y);
+	}
+    } "-O2 -msse4.1" ]
+}
+
+# Return 1 if aes instructions can be compiled.
+proc check_effective_target_aes { } {
+    return [check_no_compiler_messages aes object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+
+	__m128i _mm_aesimc_si128 (__m128i __X)
+	{
+	    return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X);
+	}
+    } "-O2 -maes" ]
+}
+
+# Return 1 if vaes instructions can be compiled.
+proc check_effective_target_vaes { } {
+    return [check_no_compiler_messages vaes object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+
+	__m128i _mm_aesimc_si128 (__m128i __X)
+	{
+	    return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X);
+	}
+    } "-O2 -maes -mavx" ]
+}
+
+# Return 1 if pclmul instructions can be compiled.
+proc check_effective_target_pclmul { } {
+    return [check_no_compiler_messages pclmul object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+
+	__m128i pclmulqdq_test (__m128i __X, __m128i __Y)
+	{
+	    return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
+							  (__v2di)__Y,
+							  1);
+	}
+    } "-O2 -mpclmul" ]
+}
+
+# Return 1 if vpclmul instructions can be compiled.
+proc check_effective_target_vpclmul { } {
+    return [check_no_compiler_messages vpclmul object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+
+	__m128i pclmulqdq_test (__m128i __X, __m128i __Y)
+	{
+	    return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
+							  (__v2di)__Y,
+							  1);
+	}
+    } "-O2 -mpclmul -mavx" ]
+}
+
+# Return 1 if sse4a instructions can be compiled.
+proc check_effective_target_sse4a { } {
+    return [check_no_compiler_messages sse4a object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+
+	__m128i _mm_insert_si64 (__m128i __X,__m128i __Y)
+	{
+	    return (__m128i) __builtin_ia32_insertq ((__v2di)__X, (__v2di)__Y);
+	}
+    } "-O2 -msse4a" ]
+}
+
+# Return 1 if sse5 instructions can be compiled.
+proc check_effective_target_sse5 { } {
+    return [check_no_compiler_messages sse5 object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef short __v8hi __attribute__ ((__vector_size__ (16)));
+
+	__m128i _mm_maccs_epi16(__m128i __A, __m128i __B, __m128i __C)
+	{
+	    return (__m128i) __builtin_ia32_pmacssww ((__v8hi)__A,
+						      (__v8hi)__B,
+						      (__v8hi)__C);
+	}
+    } "-O2 -msse5" ]
+}
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Special case compilation of vect-args.c so we don't have to
+# replicate it 10 times.
+foreach type { "" -mmmx -m3dnow -msse -msse2 } {
+  foreach level { "" -O } {
+    set flags "$type $level"
+    verbose -log "Testing vect-args, $flags" 1
+    dg-test $srcdir/$subdir/vect-args.c $flags ""
+  }
+}
+
+# Everything else.
+set tests [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]]
+set tests [prune $tests $srcdir/$subdir/vect-args.c]
+
+# Main loop.
+dg-runtest $tests "" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ifcvt-onecmpl-abs-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ifcvt-onecmpl-abs-1.c
new file mode 100644
index 000000000..c8caab5f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ifcvt-onecmpl-abs-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* This test checks for if-conversion of one's complement
+ * abs function.  */
+/* { dg-options "-O -mtune=generic" } */
+/* { dg-final { scan-assembler "sar" } } */
+/* { dg-final { scan-assembler "xor" } } */
+
+/* Check code generation for one's complement version of abs */
+
+int onecmplabs(int x)
+{
+  if (x < 0)
+    x = ~x;
+  return x;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/incoming-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/incoming-1.c
new file mode 100644
index 000000000..86e98a79b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/incoming-1.c
@@ -0,0 +1,19 @@
+/* PR middle-end/37009 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */
+/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */
+
+#include <emmintrin.h>
+
+extern void bar (int *);
+
+int
+foo(__m128 x, __m128 y, __m128 z, int size)
+{
+  int __attribute((aligned(16))) xxx;
+
+  xxx = 2;
+  bar (&xxx);
+  return size;
+}
+
+/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/incoming-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/incoming-2.c
new file mode 100644
index 000000000..2947d3347
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/incoming-2.c
@@ -0,0 +1,19 @@
+/* PR middle-end/37009 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */
+/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */
+
+#include <emmintrin.h>
+
+extern void bar (int *);
+
+int
+foo(__m128 x, __m128 y, __m128 z, __m128 a, int size)
+{
+  int __attribute((aligned(16))) xxx;
+
+  xxx = 2;
+  bar (&xxx);
+  return size;
+}
+
+/* { dg-final { scan-assembler-not "and\[l\]\[ \t\]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/incoming-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/incoming-3.c
new file mode 100644
index 000000000..1edbfda0b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/incoming-3.c
@@ -0,0 +1,19 @@
+/* PR middle-end/37009 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */
+/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */
+
+#include <emmintrin.h>
+
+extern void bar (int *);
+
+int
+foo(__m128 y, int size, ...)
+{
+  int __attribute((aligned(16))) xxx;
+
+  xxx = 2;
+  bar (&xxx);
+  return size;
+}
+
+/* { dg-final { scan-assembler-not "and\[l\]\[ \t\]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/incoming-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/incoming-4.c
new file mode 100644
index 000000000..80c169c24
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/incoming-4.c
@@ -0,0 +1,20 @@
+/* PR middle-end/37009 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */
+/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */
+
+#include <stdarg.h>
+#include <emmintrin.h>
+
+extern void bar (int *);
+
+__m128
+foo(va_list arg) 
+{
+  int __attribute((aligned(16))) xxx;
+
+  xxx = 2;
+  bar (&xxx);
+  return va_arg (arg, __m128);
+}
+
+/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/incoming-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/incoming-5.c
new file mode 100644
index 000000000..f083d4031
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/incoming-5.c
@@ -0,0 +1,16 @@
+/* PR middle-end/37009 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ilp32 } } } */
+/* { dg-options "-m32 -mincoming-stack-boundary=2 -mpreferred-stack-boundary=2" } */
+
+extern void bar (double *);
+
+double
+foo(double x)
+{
+  double xxx = x + 13.0;
+
+  bar (&xxx);
+  return xxx;
+}
+
+/* { dg-final { scan-assembler "andl\[\\t \]*\\$-8,\[\\t \]*%esp" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/inline-mcpy.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/inline-mcpy.c
new file mode 100644
index 000000000..7eacb5f98
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/inline-mcpy.c
@@ -0,0 +1,11 @@
+/* Test if we inline memcpy even with -Os, when the user requested it.  */
+/* Don't name this test with memcpy in its name, otherwise the scan-assembler
+   would be confused.  */
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-options "-Os -minline-all-stringops" } */
+/* { dg-final { scan-assembler-not "memcpy" } } */
+char f(int i)
+{
+  char *ram_split[] = { "5:3", "3:1", "1:1", "3:5" };
+  return ram_split[i][0];
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-1.c
new file mode 100644
index 000000000..ad4e7ed17
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -msse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if !defined __SSSE3__
+  abort ();
+#endif
+#if !defined __SSE4_1__
+  abort ();
+#endif
+#if !defined __SSE4_2__
+  abort ();
+#endif
+#if defined __SSE4A__
+  abort ();
+#endif
+#if defined __SSE5__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-10.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-10.c
new file mode 100644
index 000000000..76fe35593
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-10.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -msse5 -mno-sse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if !defined __SSE5__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-11.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-11.c
new file mode 100644
index 000000000..29688d5a7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-11.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -msse5 -mno-ssse3" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if !defined __SSE5__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-12.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-12.c
new file mode 100644
index 000000000..4b7e2e230
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-12.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -msse5 -mno-sse3" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if defined __SSE3__
+  abort ();
+#endif
+#if defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if defined __SSE4A__
+  abort ();
+#endif
+#if defined __SSE5__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-13.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-13.c
new file mode 100644
index 000000000..ab623c4b1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-13.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -msse5 -mno-sse2" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if defined __SSE2__
+  abort ();
+#endif
+#if defined __SSE3__
+  abort ();
+#endif
+#if defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if defined __SSE4A__
+  abort ();
+#endif
+#if defined __SSE5__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-14.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-14.c
new file mode 100644
index 000000000..09b421c37
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-14.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -msse5 -mno-sse" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if defined __SSE__
+  abort ();
+#endif
+#if defined __SSE2__
+  abort ();
+#endif
+#if defined __SSE3__
+  abort ();
+#endif
+#if defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if defined __SSE4A__
+  abort ();
+#endif
+#if defined __SSE5__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-2.c
new file mode 100644
index 000000000..ebbef772d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-2.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -msse4 -msse5" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if !defined __SSSE3__
+  abort ();
+#endif
+#if !defined __SSE4_1__
+  abort ();
+#endif
+#if !defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if !defined __SSE5__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-3.c
new file mode 100644
index 000000000..c22954406
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-3.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -msse4 -msse5 -msse4a" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if !defined __SSSE3__
+  abort ();
+#endif
+#if !defined __SSE4_1__
+  abort ();
+#endif
+#if !defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if !defined __SSE5__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-4.c
new file mode 100644
index 000000000..620369075
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-4.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=core2 -msse5 -mno-sse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if !defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if !defined __SSE5__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-5.c
new file mode 100644
index 000000000..9cd071ad5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-5.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=core2 -msse4a -mno-sse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if !defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if defined __SSE5__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-6.c
new file mode 100644
index 000000000..ec1fbeaa4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-6.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=amdfam10 -mno-sse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if defined __SSE5__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-7.c
new file mode 100644
index 000000000..76ea31ed2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-7.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=amdfam10 -msse5 -mno-sse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if !defined __SSE5__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-8.c
new file mode 100644
index 000000000..fb37669dc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-8.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=amdfam10 -msse5 -mno-sse4a" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if defined __SSE4A__
+  abort ();
+#endif
+#if defined __SSE5__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-9.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-9.c
new file mode 100644
index 000000000..fefdef6a0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/isa-9.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=amdfam10 -mno-sse5" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if defined __SSE5__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/large-size-array-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/large-size-array-3.c
new file mode 100644
index 000000000..07c877a93
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/large-size-array-3.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mcmodel=medium" } */
+/* { dg-final { scan-assembler "8589934588" } } */
+int bigarray[2147483647];
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/lea.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/lea.c
new file mode 100644
index 000000000..afbbfa4fb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/lea.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=pentiumpro" } */
+/* { dg-final { scan-assembler "leal" } } */
+typedef struct {
+  char **visbuf;
+  char **allbuf;
+} TScreen;
+
+void
+VTallocbuf(TScreen *screen, unsigned long savelines)
+{
+  screen->visbuf = &screen->allbuf[savelines];
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/local.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/local.c
new file mode 100644
index 000000000..eca16f106
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/local.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -funit-at-a-time" } */
+/* { dg-final { scan-assembler "magic\[^\\n\]*eax" { target ilp32 } } } */
+/* { dg-final { scan-assembler "magic\[^\\n\]*edi" { target lp64 } } } */
+
+/* Verify that local calling convention is used.  */
+static t(int) __attribute__ ((noinline));
+m()
+{
+	t(1);
+}
+static t(int a)
+{
+	asm("magic %0"::"g"(a));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/loop-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/loop-1.c
new file mode 100644
index 000000000..30cfd68f6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/loop-1.c
@@ -0,0 +1,106 @@
+/* PR optimization/9888 */
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-mtune=k6 -O3" } */
+
+/* Verify that GCC doesn't emit out of range 'loop' instructions.  */
+
+extern void abort (void);
+extern void exit (int);
+
+   
+f1 (a)
+     long a;
+{
+  int i;
+  for (i = 0; i < 10; i++)
+    {
+      if (--a == -1)
+	return i;
+    }
+  return -1;
+}
+
+f2 (a)
+     long a;
+{
+  int i;
+  for (i = 0; i < 10; i++)
+    {
+      if (--a != -1)
+	return i;
+    }
+  return -1;
+}
+
+f3 (a)
+     long a;
+{
+  int i;
+  for (i = 0; i < 10; i++)
+    {
+      if (--a == 0)
+	return i;
+    }
+  return -1;
+}
+
+f4 (a)
+     long a;
+{
+  int i;
+  for (i = 0; i < 10; i++)
+    {
+      if (--a != 0)
+	return i;
+    }
+  return -1;
+}
+
+f5 (a)
+     long a;
+{
+  int i;
+  for (i = 0; i < 10; i++)
+    {
+      if (++a == 0)
+	return i;
+    }
+  return -1;
+}
+
+f6 (a)
+     long a;
+{
+  int i;
+  for (i = 0; i < 10; i++)
+    {
+      if (++a != 0)
+	return i;
+    }
+  return -1;
+}
+
+
+int main()
+{
+  if (f1 (5L) != 5)
+    abort ();
+  if (f2 (1L) != 0)
+    abort ();
+  if (f2 (0L) != 1)
+    abort ();
+  if (f3 (5L) != 4)
+    abort ();
+  if (f4 (1L) != 1)
+    abort ();
+  if (f4 (0L) != 0)
+    abort ();
+  if (f5 (-5L) != 4)
+    abort ();
+  if (f6 (-1L) != 1)
+    abort ();
+  if (f6 (0L) != 0)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/loop-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/loop-2.c
new file mode 100644
index 000000000..cf44d3027
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/loop-2.c
@@ -0,0 +1,81 @@
+/* PR optimization/9888 */
+/* Originator: Jim Bray <jb@as220.org> */
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-mtune=k6 -Os" } */
+
+enum reload_type
+{
+  RELOAD_FOR_INPUT, RELOAD_FOR_OUTPUT, RELOAD_FOR_INSN,
+  RELOAD_FOR_INPUT_ADDRESS, RELOAD_FOR_INPADDR_ADDRESS,
+  RELOAD_FOR_OUTPUT_ADDRESS, RELOAD_FOR_OUTADDR_ADDRESS,
+  RELOAD_FOR_OPERAND_ADDRESS, RELOAD_FOR_OPADDR_ADDR,
+  RELOAD_OTHER, RELOAD_FOR_OTHER_ADDRESS
+};
+
+#define FOO_SIZE 3
+
+/* My results, varying with FOO_SIZE:
+   30: asm error "value of ..fff77 too large:
+   3 to 29: ....ff7d...
+   1 to 2: no error.  */
+
+struct reload
+{
+   int foo[FOO_SIZE];
+   int opnum; 
+   enum reload_type when_needed;
+   unsigned int optional:1; 
+   unsigned int secondary_p:1;
+};
+
+#define N_RELOADS  2
+
+struct reload rld[N_RELOADS];
+int n_reloads = N_RELOADS;
+
+int main(void)
+{
+  int i;
+
+  enum reload_type operand_type[1];
+
+  enum reload_type address_type[1];
+
+  int operand_reloadnum[1];
+  int goal_alternative_matches[1];
+
+  for (i = 0; i < n_reloads; i++)
+    {
+      if (rld[i].secondary_p
+          && rld[i].when_needed == operand_type[rld[i].opnum])
+        rld[i].when_needed = address_type[rld[i].opnum];
+
+      if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
+           || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS
+           || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS
+           || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
+          && (operand_reloadnum[rld[i].opnum] < 0
+              || rld[operand_reloadnum[rld[i].opnum]].optional))
+        {
+
+          if (rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS
+              || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
+            rld[i].when_needed = RELOAD_FOR_OPADDR_ADDR;
+          else
+            rld[i].when_needed = RELOAD_FOR_OPERAND_ADDRESS;
+        }
+
+      if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
+           || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
+          && operand_reloadnum[rld[i].opnum] >= 0
+          && (rld[operand_reloadnum[rld[i].opnum]].when_needed
+              == RELOAD_OTHER))
+        rld[i].when_needed = RELOAD_FOR_OTHER_ADDRESS;
+
+      if (goal_alternative_matches[rld[i].opnum] >= 0)
+        rld[i].opnum = goal_alternative_matches[rld[i].opnum];
+    }
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/loop-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/loop-3.c
new file mode 100644
index 000000000..782512f4c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/loop-3.c
@@ -0,0 +1,80 @@
+/* PR target/11044 */
+/* Originator: Tim McGrath <misty-@charter.net> */
+/* Testcase contributed by Eric Botcazou <ebotcazou@libertysurf.fr> */
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-mtune=k6 -O3 -ffast-math -funroll-loops" } */
+
+extern void *memset (void *, int, __SIZE_TYPE__);
+extern void abort (void);
+
+typedef struct
+{
+        unsigned char colormod;
+} entity_state_t;
+
+typedef struct
+{
+        int num_entities;
+        entity_state_t *entities;
+} packet_entities_t;
+
+typedef struct
+{
+        double senttime;
+        float ping_time;
+        packet_entities_t entities;
+} client_frame_t;
+
+typedef enum
+{
+        cs_free,
+        cs_server,
+        cs_zombie,
+        cs_connected,
+        cs_spawned
+} sv_client_state_t;
+
+typedef struct client_s
+{
+        sv_client_state_t state;
+        int ping;
+        client_frame_t frames[64];
+} client_t;
+
+int CalcPing (client_t *cl)
+{
+        float ping;
+        int count, i;
+        register client_frame_t *frame;
+
+        if (cl->state == cs_server)
+                return cl->ping;
+        ping = 0;
+        count = 0;
+        for (frame = cl->frames, i = 0; i < 64; i++, frame++) {
+                if (frame->ping_time > 0) {
+                        ping += frame->ping_time;
+                        count++;
+                }
+        }
+        if (!count)
+                return 9999;
+        ping /= count;
+
+        return ping * 1000;
+}
+
+int main(void)
+{
+   client_t cl;
+
+   memset(&cl, 0, sizeof(cl));
+
+   cl.frames[0].ping_time = 1.0f;
+
+   if (CalcPing(&cl) != 1000)
+     abort();
+
+   return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/m128-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/m128-check.h
new file mode 100644
index 000000000..4e2deecb1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/m128-check.h
@@ -0,0 +1,166 @@
+#include <stdio.h>
+#include <xmmintrin.h>
+
+#ifdef __SSE2__
+#include <emmintrin.h>
+
+typedef union
+{
+  __m128i x;
+  char a[16];
+} union128i_b;
+
+typedef union
+{
+  __m128i x;
+  unsigned char a[16];
+} union128i_ub;
+
+typedef union
+{
+  __m128i x;
+  short a[8];
+} union128i_w;
+
+typedef union
+{
+  __m128i x;
+  unsigned short a[8];
+} union128i_uw;
+
+typedef union
+{
+  __m128i x;
+  int a[4];
+} union128i_d;
+
+typedef union
+{
+  __m128i x;
+  long long a[2];
+} union128i_q;
+
+typedef union
+{
+  __m128d x;
+  double a[2];
+} union128d;
+#endif
+
+typedef union
+{
+  __m128  x;
+  float a[4];
+} union128;
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(A) (sizeof (A) / sizeof ((A)[0]))
+#endif
+
+#ifdef DEBUG
+#define PRINTF printf
+#else
+#define PRINTF(...)	
+#endif
+
+#define CHECK_EXP(UINON_TYPE, VALUE_TYPE, FMT)		\
+static int						\
+__attribute__((noinline, unused))			\
+check_##UINON_TYPE (UINON_TYPE u, const VALUE_TYPE *v)	\
+{							\
+  int i;						\
+  int err = 0;						\
+							\
+  for (i = 0; i < ARRAY_SIZE (u.a); i++)		\
+    if (u.a[i] != v[i])					\
+      {							\
+	err++;						\
+	PRINTF ("%i: " FMT " != " FMT "\n",		\
+		i, v[i], u.a[i]);			\
+      }							\
+  return err;						\
+}
+
+#ifdef __SSE2__
+CHECK_EXP (union128i_b, char, "%d")
+CHECK_EXP (union128i_ub, unsigned char, "%d")
+CHECK_EXP (union128i_w, short, "%d")
+CHECK_EXP (union128i_uw, unsigned short, "%d")
+CHECK_EXP (union128i_d, int, "0x%x")
+CHECK_EXP (union128i_q, long long, "0x%llx")
+CHECK_EXP (union128d, double, "%f")
+#endif
+
+CHECK_EXP (union128, float, "%f")
+
+#define ESP_FLOAT 0.000001
+#define ESP_DOUBLE 0.000001
+#define CHECK_ARRAY(ARRAY, TYPE, FMT)                   \
+static int                                              \
+__attribute__((noinline, unused))                       \
+checkV##ARRAY (const TYPE *v, const TYPE *e, int n)     \
+{                                                       \
+  int i;                                                \
+  int err = 0;                                          \
+                                                        \
+  for (i = 0; i < n; i++)                               \
+    if (v[i] != e[i])                                   \
+      {                                                 \
+        err++;                                          \
+        PRINTF ("%i: " FMT " != " FMT "\n",             \
+                i, v[i], e[i]);                 \
+      }                                                 \
+  return err;                                           \
+}
+
+CHECK_ARRAY(i, int, "0x%x")
+CHECK_ARRAY(l, long long, "0x%llx")
+
+#define CHECK_FP_ARRAY(ARRAY, TYPE, ESP, FMT)                   \
+static int                                              \
+__attribute__((noinline, unused))                       \
+checkV##ARRAY (const TYPE *v, const TYPE *e, int n)     \
+{                                                       \
+  int i;                                                \
+  int err = 0;                                          \
+                                                        \
+  for (i = 0; i < n; i++)                               \
+    if (v[i] > (e[i] + (ESP)) || v[i] < (e[i] - (ESP))) \
+    if (e[i] != v[i])                                   \
+      {                                                 \
+        err++;                                          \
+        PRINTF ("%i: " FMT " != " FMT "\n",             \
+                i, v[i], e[i]);                 \
+      }                                                 \
+  return err;                                           \
+}
+
+CHECK_FP_ARRAY (d, double, ESP_DOUBLE, "%f")
+CHECK_FP_ARRAY (f, float, ESP_FLOAT, "%f")
+
+#ifdef NEED_IEEE754_FLOAT
+union ieee754_float
+{
+   float d;
+   struct 
+   {
+      unsigned long frac : 23;
+      unsigned exp : 8;
+      unsigned sign : 1;
+   } bits __attribute__((packed));
+};
+#endif
+
+#ifdef NEED_IEEE754_DOUBLE
+union ieee754_double
+{
+   double d;
+   struct 
+   {
+      unsigned long frac1 : 32;
+      unsigned long frac0 : 20;
+      unsigned exp : 11;
+      unsigned sign : 1;
+   } bits __attribute__((packed));
+};
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/m256-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/m256-1.c
new file mode 100644
index 000000000..a40b9e88f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/m256-1.c
@@ -0,0 +1,63 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-mavx" } */
+
+#include <assert.h>
+#include "avx-check.h"
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+__m256d n2 = { -93.83, 893.318, 3884.34, -3134.3 };
+__m256i n3 = { 893, -3180, 3334, -3984 };
+int n4 = -30;
+double n5 = 40.3;
+__m128i n6 = { 8931, -13984 };
+__m128d n7 = { 1893.318, -31134.3 };
+__m256 n8 =
+{
+  -913.87, 8193.518, 312884.34, -9134.9,
+  -19093.83, 89312.318, 7884.84, -4134.3
+};
+__m128 n9 = { -1283.3, -213.3, 3213.4, 81119.03 };
+__m128i n10 = { 28131, -313684 };
+int n11 = 103;
+double n12 = -3004.3;
+__m256d n13 = { 913.73, -93.38, 84.34, -734.3 };
+__m128d n14 = { -73.378, 934.31 };
+__m256 n15 =
+{
+  13.73, -8193.318, 384.74, 734.9,
+  193.83, 312.78, 7884.34, -8134.3
+};
+__m128i n16 = { 831, -3849 };
+
+void
+__attribute__((noinline))
+m256_test (__m128 a1, __m256d a2, __m256i a3, int a4, double a5,
+	   __m128i a6, __m128d a7, __m256 a8, __m128 a9, __m128i a10,
+	   int a11, double a12, __m256d a13, __m128d a14, __m256 a15,
+	   __m128i a16)
+{
+  assert (__builtin_memcmp (&a1, &n1, sizeof (a1)) == 0);
+  assert (__builtin_memcmp (&a2, &n2, sizeof (a2)) == 0);
+  assert (__builtin_memcmp (&a3, &n3, sizeof (a3)) == 0);
+  assert (a4 == n4);
+  assert (a5 == n5);
+  assert (__builtin_memcmp (&a6, &n6, sizeof (a6)) == 0);
+  assert (__builtin_memcmp (&a7, &n7, sizeof (a7)) == 0);
+  assert (__builtin_memcmp (&a8, &n8, sizeof (a8)) == 0);
+  assert (__builtin_memcmp (&a9, &n9, sizeof (a9)) == 0);
+  assert (__builtin_memcmp (&a10, &n10, sizeof (a10)) == 0);
+  assert (a11 == n11);
+  assert (a12 == n12);
+  assert (__builtin_memcmp (&a13, &n13, sizeof (a13)) == 0);
+  assert (__builtin_memcmp (&a14, &n14, sizeof (a14)) == 0);
+  assert (__builtin_memcmp (&a15, &n15, sizeof (a15)) == 0);
+  assert (__builtin_memcmp (&a16, &n16, sizeof (a16)) == 0);
+}
+
+static void
+avx_test (void)
+{
+  m256_test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
+	     n13, n14, n15, n16);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/m256-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/m256-2.c
new file mode 100644
index 000000000..64e38527d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/m256-2.c
@@ -0,0 +1,73 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-mavx" } */
+
+#include <assert.h>
+#include "avx-check.h"
+
+struct m128
+{
+  __m128 v;
+};
+
+struct m256d
+{
+  __m256d v;
+};
+
+struct m128 n1 = { { -283.3, -23.3, 213.4, 1119.03 } };
+struct m256d n2 = { { -93.83, 893.318, 3884.34, -3134.3 } };
+__m256i n3 = { 893, -3180, 3334, -3984 };
+int n4 = -30;
+double n5 = 40.3;
+__m128i n6 = { 8931, -13984 };
+__m128d n7 = { 1893.318, -31134.3 };
+__m256 n8 =
+{
+  -913.87, 8193.518, 312884.34, -9134.9,
+  -19093.83, 89312.318, 7884.84, -4134.3
+};
+__m128 n9 = { -1283.3, -213.3, 3213.4, 81119.03 };
+__m128i n10 = { 28131, -313684 };
+int n11 = 103;
+double n12 = -3004.3;
+struct m256d n13 =  { { 913.73, -93.38, 84.34, -734.3 } };
+__m128d n14 = { -73.378, 934.31 };
+__m256 n15 =
+{
+  13.73, -8193.318, 384.74, 734.9,
+  193.83, 312.78, 7884.34, -8134.3
+};
+__m128i n16 = { 831, -3849 };
+
+void
+__attribute__((noinline))
+m256_test (struct m128 a1, struct m256d a2, __m256i a3, int a4, double a5,
+	   __m128i a6, __m128d a7, __m256 a8, __m128 a9, __m128i a10,
+	   int a11, double a12, struct m256d a13, __m128d a14, __m256 a15,
+	   __m128i a16)
+{
+  assert (__builtin_memcmp (&a1, &n1, sizeof (a1)) == 0);
+  assert (__builtin_memcmp (&a2, &n2, sizeof (a2)) == 0);
+  assert (__builtin_memcmp (&a3, &n3, sizeof (a3)) == 0);
+  assert (a4 == n4);
+  assert (a5 == n5);
+  assert (__builtin_memcmp (&a6, &n6, sizeof (a6)) == 0);
+  assert (__builtin_memcmp (&a7, &n7, sizeof (a7)) == 0);
+  assert (__builtin_memcmp (&a8, &n8, sizeof (a8)) == 0);
+  assert (__builtin_memcmp (&a9, &n9, sizeof (a9)) == 0);
+  assert (__builtin_memcmp (&a10, &n10, sizeof (a10)) == 0);
+  assert (a11 == n11);
+  assert (a12 == n12);
+  assert (__builtin_memcmp (&a13, &n13, sizeof (a13)) == 0);
+  assert (__builtin_memcmp (&a14, &n14, sizeof (a14)) == 0);
+  assert (__builtin_memcmp (&a15, &n15, sizeof (a15)) == 0);
+  assert (__builtin_memcmp (&a16, &n16, sizeof (a16)) == 0);
+}
+
+static void
+avx_test (void)
+{
+  m256_test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
+	     n13, n14, n15, n16);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/m256-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/m256-check.h
new file mode 100644
index 000000000..e1843550e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/m256-check.h
@@ -0,0 +1,73 @@
+#include <immintrin.h>
+#include "m128-check.h"
+
+#ifndef max
+#define max(a, b) (((a) > (b)) ? (a):(b))
+#endif
+#ifndef min
+#define min(a, b) (((a) < (b)) ? (a):(b))
+#endif
+
+typedef union
+{
+  __m256i x;
+  char a[32];
+} union256i_b;
+
+typedef union
+{
+  __m256i x;
+  short a[16];
+} union256i_w;
+
+typedef union
+{
+  __m256i x;
+  int a[8];
+} union256i_d;
+
+typedef union
+{
+  __m256i x;
+  long long a[4];
+} union256i_q;
+
+typedef union
+{
+  __m256 x;
+  float a[8];
+} union256;
+
+typedef union
+{
+  __m256d x;
+  double a[4];
+} union256d;
+
+CHECK_EXP (union256i_b, char, "%d")
+CHECK_EXP (union256i_w, short, "%d")
+CHECK_EXP (union256i_d, int, "0x%x")
+CHECK_EXP (union256i_q, long long, "0x%llx")
+CHECK_EXP (union256, float, "%f")
+CHECK_EXP (union256d, double, "%f")
+
+#define CHECK_FP_EXP(UINON_TYPE, VALUE_TYPE, ESP, FMT)		\
+static int							\
+__attribute__((noinline, unused))				\
+check_fp_##UINON_TYPE (UINON_TYPE u, const VALUE_TYPE *v)	\
+{								\
+  int i;							\
+  int err = 0;							\
+								\
+  for (i = 0; i < ARRAY_SIZE (u.a); i++)			\
+    if (u.a[i] > (v[i] + (ESP)) || u.a[i] < (v[i] - (ESP)))	\
+      {								\
+	err++;							\
+	PRINTF ("%i: " FMT " != " FMT "\n",			\
+		i, v[i], u.a[i]);				\
+      }								\
+  return err;							\
+}
+
+CHECK_FP_EXP (union256, float, ESP_FLOAT, "%f")
+CHECK_FP_EXP (union256d, double, ESP_DOUBLE, "%f")
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/ceil.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/ceil.c
new file mode 100644
index 000000000..dfccd7af4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/ceil.c
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+
+float testlf (float x)
+{
+  return __builtin_ceilf (x);
+}
+double testl (double x)
+{
+  return __builtin_ceil (x);
+}
+long double testll (long double x)
+{
+  return __builtin_ceill (x);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/floor.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/floor.c
new file mode 100644
index 000000000..0c3aa9156
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/floor.c
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+
+float testlf (float x)
+{
+  return __builtin_floorf (x);
+}
+double testl (double x)
+{
+  return __builtin_floor (x);
+}
+long double testll (long double x)
+{
+  return __builtin_floorl (x);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/lceil.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/lceil.c
new file mode 100644
index 000000000..d09847904
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/lceil.c
@@ -0,0 +1,26 @@
+/* { dg-do assemble } */
+
+long testlf (float x)
+{
+  return __builtin_lceilf (x);
+}
+long testl (double x)
+{
+  return __builtin_lceil (x);
+}
+long testll (long double x)
+{
+  return __builtin_lceill (x);
+}
+long long testllf (float x)
+{
+  return __builtin_llceilf (x);
+}
+long long testll_ (double x)
+{
+  return __builtin_llceil (x);
+}
+long long testlll (long double x)
+{
+  return __builtin_llceill (x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/lfloor.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/lfloor.c
new file mode 100644
index 000000000..2c2e96f2e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/lfloor.c
@@ -0,0 +1,26 @@
+/* { dg-do assemble } */
+
+long testlf (float x)
+{
+  return __builtin_lfloorf (x);
+}
+long testl (double x)
+{
+  return __builtin_lfloor (x);
+}
+long testll (long double x)
+{
+  return __builtin_lfloorl (x);
+}
+long long testllf (float x)
+{
+  return __builtin_llfloorf (x);
+}
+long long testll_ (double x)
+{
+  return __builtin_llfloor (x);
+}
+long long testlll (long double x)
+{
+  return __builtin_llfloorl (x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/lrint.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/lrint.c
new file mode 100644
index 000000000..73b75b7ad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/lrint.c
@@ -0,0 +1,26 @@
+/* { dg-do assemble } */
+
+long testlf (float x)
+{
+  return __builtin_lrintf (x);
+}
+long testl (double x)
+{
+  return __builtin_lrint (x);
+}
+long testll (long double x)
+{
+  return __builtin_lrintl (x);
+}
+long long testllf (float x)
+{
+  return __builtin_llrintf (x);
+}
+long long testll_ (double x)
+{
+  return __builtin_llrint (x);
+}
+long long testlll (long double x)
+{
+  return __builtin_llrintl (x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/lround.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/lround.c
new file mode 100644
index 000000000..756356d62
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/lround.c
@@ -0,0 +1,26 @@
+/* { dg-do assemble } */
+
+long testlf (float x)
+{
+  return __builtin_lroundf (x);
+}
+long testl (double x)
+{
+  return __builtin_lround (x);
+}
+long testll (long double x)
+{
+  return __builtin_lroundl (x);
+}
+long long testllf (float x)
+{
+  return __builtin_llroundf (x);
+}
+long long testll_ (double x)
+{
+  return __builtin_llround (x);
+}
+long long testlll (long double x)
+{
+  return __builtin_llroundl (x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/math-torture.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/math-torture.exp
new file mode 100644
index 000000000..43ea6ea2f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/math-torture.exp
@@ -0,0 +1,42 @@
+# This harness is for tests that should be run at all optimisation levels.
+
+# Exit immediately if this isn't a x86 target.
+if { ![istarget i?86*-*-*] && ![istarget x86_64-*-*] } then {
+  return
+}
+
+set MATH_TORTURE_OPTIONS [list \
+        { -O0 } \
+        { -O0 -mfpmath=387 } \
+        { -O0 -msse -mno-sse2 -mfpmath=sse } \
+        { -O0 -msse -msse2 -mfpmath=sse } \
+        { -O0 -msse -mno-sse2 -mfpmath=sse,387 } \
+        { -O0 -msse -msse2 -mfpmath=sse,387 } \
+        { -O0 -mfpmath=387 -ffast-math } \
+        { -O0 -msse -mno-sse2 -mfpmath=sse -ffast-math } \
+        { -O0 -msse -msse2 -mfpmath=sse -ffast-math } \
+        { -O0 -msse -mno-sse2 -mfpmath=sse,387 -ffast-math } \
+        { -O0 -msse -msse2 -mfpmath=sse,387 -ffast-math } \
+        { -O2 } \
+        { -O2 -mfpmath=387 } \
+        { -O2 -msse -mno-sse2 -mfpmath=sse } \
+        { -O2 -msse -msse2 -mfpmath=sse } \
+        { -O2 -msse -mno-sse2 -mfpmath=sse,387 } \
+        { -O2 -msse -msse2 -mfpmath=sse,387 } \
+        { -O2 -mfpmath=387 -ffast-math } \
+        { -O2 -msse -mno-sse2 -mfpmath=sse -ffast-math } \
+        { -O2 -msse -msse2 -mfpmath=sse -ffast-math } \
+        { -O2 -msse -mno-sse2 -mfpmath=sse,387 -ffast-math } \
+        { -O2 -msse -msse2 -mfpmath=sse,387 -ffast-math } \
+]
+
+load_lib gcc-dg.exp
+load_lib torture-options.exp
+
+torture-init
+set-torture-options $MATH_TORTURE_OPTIONS
+
+dg-init
+gcc-dg-runtest [lsort [glob $srcdir/$subdir/*.c]] ""
+torture-finish
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/nearbyint.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/nearbyint.c
new file mode 100644
index 000000000..dd646f012
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/nearbyint.c
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+
+float testlf (float x)
+{
+  return __builtin_nearbyintf (x);
+}
+double testl (double x)
+{
+  return __builtin_nearbyint (x);
+}
+long double testll (long double x)
+{
+  return __builtin_nearbyintl (x);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/rint.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/rint.c
new file mode 100644
index 000000000..f9dfff7ca
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/rint.c
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+
+float testlf (float x)
+{
+  return __builtin_rintf (x);
+}
+double testl (double x)
+{
+  return __builtin_rint (x);
+}
+long double testll (long double x)
+{
+  return __builtin_rintl (x);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/round.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/round.c
new file mode 100644
index 000000000..fddac7abb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/round.c
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+
+float testlf (float x)
+{
+  return __builtin_roundf (x);
+}
+double testl (double x)
+{
+  return __builtin_round (x);
+}
+long double testll (long double x)
+{
+  return __builtin_roundl (x);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/trunc.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/trunc.c
new file mode 100644
index 000000000..a71e026c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/math-torture/trunc.c
@@ -0,0 +1,14 @@
+/* { dg-do assemble } */
+
+float testlf (float x)
+{
+  return __builtin_truncf (x);
+}
+double testl (double x)
+{
+  return __builtin_trunc (x);
+}
+long double testll (long double x)
+{
+  return __builtin_truncl (x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/memcpy-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/memcpy-1.c
new file mode 100644
index 000000000..51797e189
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/memcpy-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=pentiumpro -minline-all-stringops" } */
+/* { dg-final { scan-assembler "rep" } } */
+/* { dg-final { scan-assembler "movs" } } */
+/* { dg-final { scan-assembler-not "test" } } */
+/* { dg-final { scan-assembler "\.L?:" } } */
+
+/* A and B are aligned, but we used to lose track of it.
+   Ensure that memcpy is inlined and alignment prologue is missing.  */
+
+char a[2048];
+char b[2048];
+t()
+{
+  __builtin_memcpy (a,b,2048);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/memset-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/memset-1.c
new file mode 100644
index 000000000..eaf3230ec
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/memset-1.c
@@ -0,0 +1,104 @@
+/* Copyright (C) 2002, 2005  Free Software Foundation.
+
+   Test -minline-all-stringops memset with various combinations of pointer
+   alignments and lengths to make sure builtin optimizations are correct.
+   PR target/6456.
+
+   Written by Michael Meissner, March 9, 2002.
+   Target by Roger Sayle, April 25, 2002.  */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -minline-all-stringops" } */
+
+extern void *memset (void *, int, __SIZE_TYPE__);
+extern void abort (void);
+extern void exit (int);
+
+#ifndef MAX_OFFSET
+#define MAX_OFFSET (sizeof (long long))
+#endif
+
+#ifndef MAX_COPY
+#define MAX_COPY (8 * sizeof (long long))
+#endif
+
+#ifndef MAX_EXTRA
+#define MAX_EXTRA (sizeof (long long))
+#endif
+
+#define MAX_LENGTH (MAX_OFFSET + MAX_COPY + MAX_EXTRA)
+
+static union {
+  char buf[MAX_LENGTH];
+  long long align_int;
+  long double align_fp;
+} u;
+
+char A = 'A';
+
+main ()
+{
+  int off, len, i;
+  char *p, *q;
+
+  for (off = 0; off < MAX_OFFSET; off++)
+    for (len = 1; len < MAX_COPY; len++)
+      {
+	for (i = 0; i < MAX_LENGTH; i++)
+	  u.buf[i] = 'a';
+
+	p = memset (u.buf + off, '\0', len);
+	if (p != u.buf + off)
+	  abort ();
+
+	q = u.buf;
+	for (i = 0; i < off; i++, q++)
+	  if (*q != 'a')
+	    abort ();
+
+	for (i = 0; i < len; i++, q++)
+	  if (*q != '\0')
+	    abort ();
+
+	for (i = 0; i < MAX_EXTRA; i++, q++)
+	  if (*q != 'a')
+	    abort ();
+
+	p = memset (u.buf + off, A, len);
+	if (p != u.buf + off)
+	  abort ();
+
+	q = u.buf;
+	for (i = 0; i < off; i++, q++)
+	  if (*q != 'a')
+	    abort ();
+
+	for (i = 0; i < len; i++, q++)
+	  if (*q != 'A')
+	    abort ();
+
+	for (i = 0; i < MAX_EXTRA; i++, q++)
+	  if (*q != 'a')
+	    abort ();
+
+	p = memset (u.buf + off, 'B', len);
+	if (p != u.buf + off)
+	  abort ();
+
+	q = u.buf;
+	for (i = 0; i < off; i++, q++)
+	  if (*q != 'a')
+	    abort ();
+
+	for (i = 0; i < len; i++, q++)
+	  if (*q != 'B')
+	    abort ();
+
+	for (i = 0; i < MAX_EXTRA; i++, q++)
+	  if (*q != 'a')
+	    abort ();
+      }
+
+  exit(0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/minmax-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/minmax-1.c
new file mode 100644
index 000000000..ca7fb6a91
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/minmax-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=opteron" } */
+/* { dg-final { scan-assembler "test" } } */
+/* { dg-final { scan-assembler-not "cmp" } } */
+#define max(a,b) (((a) > (b))? (a) : (b))
+t(int a)
+{
+  return (max(a,1));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/minmax-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/minmax-2.c
new file mode 100644
index 000000000..2021aaa07
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/minmax-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "test" } } */
+/* { dg-final { scan-assembler-not "cmp" } } */
+#define max(a,b) (((a) > (b))? (a) : (b))
+t(unsigned int a)
+{
+  return (max(a,1));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-1.c
new file mode 100644
index 000000000..0b31a531a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -mmmx" } */
+
+/* Test that the intrinsics compile with optimization.  All of them are
+   defined as inline functions in mmintrin.h that reference the proper
+   builtin functions.  Defining away "extern" and "__inline" results in
+   all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+#include <mmintrin.h>
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-2.c
new file mode 100644
index 000000000..d15ceb185
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -mmmx" } */
+
+/* Test that the intrinsics compile without optimization.  All of them are
+   defined as inline functions in mmintrin.h that reference the proper
+   builtin functions.  Defining away "extern" and "__inline" results in
+   all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+#include <mmintrin.h>
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-3.c
new file mode 100644
index 000000000..6022d5294
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-3.c
@@ -0,0 +1,17 @@
+/* PR target/8870 */
+/* Originator: otaylor@redhat.com */
+/* { dg-do compile } */
+/* { dg-options "-O1 -mmmx -march=k8" } */
+
+typedef short v4hi __attribute__ ((vector_size (8)));
+
+static inline v4hi cvtsi_v4hi (int i)
+{
+  long long tmp = i;
+  return (v4hi) tmp;
+}
+
+v4hi bar (unsigned short a)
+{
+  return cvtsi_v4hi (a);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-3dnow-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-3dnow-check.h
new file mode 100644
index 000000000..458e7cda8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-3dnow-check.h
@@ -0,0 +1,21 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void mmx_3dnow_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run 3DNow! test only if host has 3DNow! support.  */
+  if (edx & bit_3DNOW)
+    mmx_3dnow_test ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-4.c
new file mode 100644
index 000000000..05d2b553b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-4.c
@@ -0,0 +1,236 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mmmx" } */
+
+#include "mmx-check.h"
+
+#include <mmintrin.h>
+#include <string.h>
+
+#define SHIFT (4)
+
+typedef union {
+  __m64 v;
+  unsigned char c[8];
+  unsigned short int s[4];
+  unsigned long long t;
+  unsigned int u[2];
+}vecInWord;
+
+void mmx_tests (void) __attribute__((noinline));
+void dump64_16 (char *, char *, vecInWord);
+void dump64_32 (char *, char *, vecInWord);
+void dump64_64 (char *, char *, vecInWord);
+int check (const char *, const char *[]);
+
+char buf[8000];
+char comparison[8000];
+static int errors = 0;
+
+vecInWord a64, b64, c64, d64, e64;
+__m64 m64_16, s64, m64_32, m64_64;
+
+const char *reference_mmx[] = {
+  "_mm_srai_pi16 0012 0012 0012 0012 \n",
+  "_mm_sra_pi16 0012 0012 0012 0012 \n",
+  "_mm_srai_pi32 00123456 00123456 \n",
+  "_mm_sra_pi32 00123456 00123456 \n",
+  "_mm_srli_pi16 0012 0012 0012 0012 \n",
+  "_mm_srl_pi16 0012 0012 0012 0012 \n",
+  "_mm_srli_pi32 00123456 00123456 \n",
+  "_mm_srl_pi32 00123456 00123456 \n",
+  "_mm_srli_si64 00123456789abcde\n",
+  "_mm_srl_si64 00123456789abcde\n",
+  "_mm_slli_pi16 1230 1230 1230 1230 \n",
+  "_mm_sll_pi16 1230 1230 1230 1230 \n",
+  "_mm_slli_pi32 12345670 12345670 \n",
+  "_mm_sll_pi32 12345670 12345670 \n",
+  "_mm_slli_si64 123456789abcdef0\n",
+  "_mm_sll_si64 123456789abcdef0\n",
+  ""
+};
+
+
+static void
+mmx_test (void)
+{
+  d64.u[0]  = 0x01234567;
+  d64.u[1]  = 0x01234567;
+
+  m64_32 = d64.v;
+
+  e64.t  = 0x0123456789abcdefULL;
+
+  m64_64 = e64.v;
+
+  a64.s[0] = 0x0123;
+  a64.s[1] = 0x0123;
+  a64.s[2] = 0x0123;
+  a64.s[3] = 0x0123;
+
+  m64_16 = a64.v;
+
+  b64.s[0] = SHIFT;
+  b64.s[1] = 0;
+  b64.s[2] = 0;
+  b64.s[3] = 0;
+
+  s64 = b64.v;
+
+  mmx_tests();
+  check (buf, reference_mmx);
+#ifdef DEBUG
+  printf ("mmx testing:\n");
+  printf (buf);
+  printf ("\ncomparison:\n");
+  printf (comparison);
+#endif
+  buf[0] = '\0';
+
+  if (errors != 0)
+    abort ();
+}
+
+void __attribute__((noinline))
+mmx_tests (void)
+{
+  /* psraw */
+  c64.v = _mm_srai_pi16 (m64_16, SHIFT);
+  dump64_16 (buf, "_mm_srai_pi16", c64);
+  c64.v  = _mm_sra_pi16 (m64_16, s64);
+  dump64_16 (buf, "_mm_sra_pi16", c64);
+
+  /* psrad */
+  c64.v  = _mm_srai_pi32 (m64_32, SHIFT);
+  dump64_32 (buf, "_mm_srai_pi32", c64);
+  c64.v = _mm_sra_pi32 (m64_32, s64);
+  dump64_32 (buf, "_mm_sra_pi32", c64);
+
+  /* psrlw */
+  c64.v = _mm_srli_pi16 (m64_16, SHIFT);
+  dump64_16 (buf, "_mm_srli_pi16", c64);
+  c64.v = _mm_srl_pi16 (m64_16, s64);
+  dump64_16 (buf, "_mm_srl_pi16", c64);
+
+  /* psrld */
+  c64.v = _mm_srli_pi32 (m64_32, SHIFT);
+  dump64_32 (buf, "_mm_srli_pi32", c64);
+  c64.v = _mm_srl_pi32 (m64_32, s64);
+  dump64_32 (buf, "_mm_srl_pi32", c64);
+
+  /* psrlq */
+  c64.v = _mm_srli_si64 (m64_64, SHIFT);
+  dump64_64 (buf, "_mm_srli_si64", c64);
+  c64.v = _mm_srl_si64 (m64_64, s64);
+  dump64_64 (buf, "_mm_srl_si64", c64);
+
+  /* psllw */
+  c64.v = _mm_slli_pi16 (m64_16, SHIFT);
+  dump64_16 (buf, "_mm_slli_pi16", c64);
+  c64.v = _mm_sll_pi16 (m64_16, s64);
+  dump64_16 (buf, "_mm_sll_pi16", c64);
+
+  /* pslld */
+  c64.v = _mm_slli_pi32 (m64_32, SHIFT);
+  dump64_32 (buf, "_mm_slli_pi32", c64);
+  c64.v = _mm_sll_pi32 (m64_32, s64);
+  dump64_32 (buf, "_mm_sll_pi32", c64);
+
+  /* psllq */
+  c64.v = _mm_slli_si64 (m64_64, SHIFT);
+  dump64_64 (buf, "_mm_slli_si64", c64);
+  c64.v = _mm_sll_si64 (m64_64, s64);
+  dump64_64 (buf, "_mm_sll_si64", c64);
+}
+
+void
+dump64_16 (char *buf, char *name, vecInWord x)
+{
+  int i;
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+  for (i=0; i<4; i++)
+    {
+      sprintf (p, "%4.4x ", x.s[i]);
+      p += strlen (p);
+    }
+  strcat (p, "\n");
+}
+
+void
+dump64_32 (char *buf, char *name, vecInWord x)
+{
+  int i;
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+  for (i=0; i<2; i++)
+    {
+      sprintf (p, "%8.8x ", x.u[i]);
+      p += strlen (p);
+    }
+  strcat (p, "\n");
+}
+
+void
+dump64_64 (char *buf, char *name, vecInWord x)
+{
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+#if defined(_WIN32) && !defined(__CYGWIN__)
+  sprintf (p, "%16.16I64x\n", x.t);
+#else
+  sprintf (p, "%16.16llx\n", x.t);
+#endif
+}
+
+int
+check (const char *input, const char *reference[])
+{
+  int broken, i, j, len;
+  const char *p_input;
+  char *p_comparison;
+  int new_errors = 0;
+
+  p_comparison = &comparison[0];
+  p_input = input;
+
+  for (i = 0; *reference[i] != '\0'; i++)
+    {
+      broken = 0;
+      len = strlen (reference[i]);
+      for (j = 0; j < len; j++)
+	{
+	  /* Ignore the terminating NUL characters at the end of every string in 'reference[]'.  */
+	  if (!broken && *p_input != reference[i][j])
+	    {
+	      *p_comparison = '\0';
+	      strcat (p_comparison, " >>> ");
+	      p_comparison += strlen (p_comparison);
+	      new_errors++;
+	      broken = 1;
+	    }
+	  *p_comparison = *p_input;
+	  p_comparison++;
+	  p_input++;
+	}
+      if (broken)
+	{
+	  *p_comparison = '\0';
+	  strcat (p_comparison, "expected:\n");
+	  strcat (p_comparison, reference[i]);
+	  p_comparison += strlen (p_comparison);
+	}
+    }
+  *p_comparison = '\0';
+  strcat (p_comparison, new_errors ? "failure\n\n" : "O.K.\n\n") ;
+  errors += new_errors;
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-5.c
new file mode 100644
index 000000000..a58fbb7b1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-5.c
@@ -0,0 +1,18 @@
+/* PR rtl-optimization/17853 */
+/* Contributed by Stuart Hastings <stuart@apple.com> */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmmx" } */
+#include <mmintrin.h>
+#include <stdlib.h>
+
+__m64 global_mask;
+
+int main()
+{
+    __m64 zero = _mm_setzero_si64();
+    __m64 mask = _mm_cmpeq_pi8( zero, zero );
+    mask = _mm_unpacklo_pi8( mask, zero );
+    global_mask = mask;
+    return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-6.c
new file mode 100644
index 000000000..e0bc6bdd3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-6.c
@@ -0,0 +1,17 @@
+/* PR middle-end/17767 */
+/* Contributed by Volker Reichelt <reichelt@igpm.rwth-aachen.de> */
+/* { dg-do compile } */
+/* { dg-options "-O -mmmx" } */
+typedef int __m64 __attribute__ ((vector_size (8)));
+typedef short __v4hi __attribute__ ((vector_size (8)));
+
+__m64 foo ()
+{
+  int i;
+  __m64 m;
+
+  for (i = 0; i < 2; i++)
+    m = (__m64) __builtin_ia32_pcmpeqw ((__v4hi) m, (__v4hi) m);
+
+  return m;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-7.c
new file mode 100644
index 000000000..683ca102d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-7.c
@@ -0,0 +1,18 @@
+/* PR middle-end/26379 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmmx" } */
+
+#include <mmintrin.h>
+
+void
+foo (__m64 *p)
+{
+  __m64 m;
+
+  m = p[0];
+  m = _mm_srli_pi16(m, 2);
+  m = _mm_slli_pi16(m, 8);
+
+  p[0] = m;
+  _mm_empty();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-8.c
new file mode 100644
index 000000000..c90083bab
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-8.c
@@ -0,0 +1,137 @@
+/* PR middle-end/37809 */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -mmmx" } */
+
+#include <mmintrin.h>
+
+#include "mmx-check.h"
+
+// Various tests of cases where it is incorrect to optimise vectors as if they
+// were integers of the same width.
+
+extern void abort (void);
+
+void __attribute__ ((noinline))
+Sshift()
+{
+    volatile __m64 y = (__m64) 0xffffffffll;
+    __m64 x = y & (__m64) 0xffffffffll;
+    x = _m_psradi (x, 1);
+    x &= (__m64) 0x80000000ll;
+    if (0 == (long long) x)
+        abort();
+}
+
+#define SHIFTU(F,B,S,T)                         \
+    void F()                                    \
+    {                                           \
+        volatile __m64 y = (__m64) 0ll;         \
+        __m64 x = y | (__m64) (1llu << B);      \
+        if (S > 0)                              \
+            x = _m_pslldi (x, S);               \
+        else                                    \
+            x = _m_psrldi (x, -S);              \
+        if (T > 0)                              \
+            x = _m_pslldi (x, T);               \
+        else                                    \
+            x = _m_psrldi (x, -T);              \
+        x &= (__m64) (1llu << (B + S + T));     \
+        if ((long long) x)                      \
+            abort();                            \
+    }
+
+SHIFTU (shiftU1, 31, 1, -1)
+SHIFTU (shiftU2, 32, -1, 1)
+SHIFTU (shiftU3, 31, 1, 0)
+SHIFTU (shiftU4, 32, -1, 0)
+
+void __attribute__ ((noinline))
+add_1()
+{
+    volatile long long ONE = 1;
+    long long one = ONE;
+
+    __m64 a = (__m64) one;
+    __m64 b = (__m64) -one;
+    __m64 c = a + b;
+    if (0 == (long long) c)
+        abort();
+}
+
+void __attribute__ ((noinline))
+add_2()
+{
+    volatile long long ONE = 1;
+    long long one = ONE;
+
+    __m64 a = (__m64) one;
+    __m64 b = (__m64) -one;
+    __m64 c = _m_paddd (a, b);
+    if (0 == (long long) c)
+        abort();
+}
+
+void __attribute__ ((noinline))
+mult_1()
+{
+    volatile __m64 y = (__m64) 0ll;
+    __m64 x = y | (__m64) (1ll << 32);
+    x = x * (__m64) 1ll;
+    x &= (__m64) (1ll << 32);
+    if (0 != (long long) x)
+        abort();
+}
+
+void __attribute__ ((noinline))
+mult_2()
+{
+    volatile int foo = 1;
+    unsigned long long one = foo & 1;
+
+    __m64 x = (__m64) (one << 16);
+    x *= x;
+    x &= (__m64) (1ll << 32);
+    if (0 != (long long) x)
+        abort();
+}
+
+void __attribute__ ((noinline))
+mult_3()
+{
+    volatile __m64 y = (__m64) (1ll << 32);
+    __m64 a = y;
+    __m64 b = y * (__m64) 1ll;
+    if (((long long) a) == (long long) b)
+        abort();
+}
+
+void __attribute__ ((noinline))
+div_1()
+{
+    volatile __m64 y = (__m64) 0ll;
+    __m64 x = y | (__m64) (1ull << 32);
+    x |= (__m64) 1ull;
+    x = x / x;
+    if (1ll == (long long) x)
+        abort();
+}
+
+
+void mmx_test (void)
+{
+    Sshift();
+    shiftU1();
+    shiftU2();
+    shiftU3();
+    shiftU4();
+
+    add_1();
+    add_2();
+
+    mult_1();
+    mult_2();
+    mult_3();
+
+    div_1();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-check.h
new file mode 100644
index 000000000..aefdc4e87
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mmx-check.h
@@ -0,0 +1,21 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void mmx_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run MMX test only if host has MMX support.  */
+  if (edx & bit_MMX)
+    mmx_test ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/monitor.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/monitor.c
new file mode 100644
index 000000000..939969f79
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/monitor.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse3" } */
+
+/* Verify that they work in both 32bit and 64bit.  */
+
+#include <pmmintrin.h>
+
+void
+foo (char *p, int x, int y, int z)
+{
+   _mm_monitor (p, y, x);
+   _mm_mwait (z, y);
+}
+
+void
+bar (char *p, long x, long y, long z)
+{
+   _mm_monitor (p, y, x);
+   _mm_mwait (z, y);
+}
+
+void
+foo1 (char *p)
+{
+   _mm_monitor (p, 0, 0);
+   _mm_mwait (0, 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/movq-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/movq-2.c
new file mode 100644
index 000000000..4a1accb58
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/movq-2.c
@@ -0,0 +1,26 @@
+/* PR target/25199 */
+/* { dg-do compile } */
+/* { dg-options "-Os -mtune=pentium4" } */
+/* { dg-require-effective-target ilp32 } */
+
+struct S
+{
+  void *p[30];
+  unsigned char c[4];
+};
+
+unsigned char d;
+
+void
+foo (struct S *x)
+{
+  register unsigned char e __asm ("esi");
+  e = x->c[3];
+  __asm __volatile ("" : : "r" (e));
+  e = x->c[0];
+  __asm __volatile ("" : : "r" (e));
+}
+
+/* { dg-final { scan-assembler-not "movl\[ \t\]*123" } } */
+/* { dg-final { scan-assembler "movzbl\[ \t\]*123" } } */
+/* { dg-final { scan-assembler "mov(zb)?l\[ \t\]*120" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/movq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/movq.c
new file mode 100644
index 000000000..ac0dfa2d9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/movq.c
@@ -0,0 +1,10 @@
+/* { dg-do compile }
+/* { dg-options "-Os -march=pentium4 -mtune=prescott" } */
+/* { dg-require-effective-target ilp32 } */
+
+register char foo asm("edi");
+char x;
+int bar() {
+  foo = x;
+}
+/* { dg-final { scan-assembler "movz" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/movsi-sm-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/movsi-sm-1.c
new file mode 100644
index 000000000..35941405d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/movsi-sm-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fgcse-sm -minline-all-stringops" } */
+
+/* Store motion used to fail to recognize killed expressions within
+   parallels such as those generated for memory copying.  */
+
+static const char s[1024] __attribute__ ((__aligned__ (32)))
+  = "This is what we should get!";
+
+int bug (int arg) {
+  char str[sizeof(s) > 4 ? sizeof(s) : 4] __attribute__ ((__aligned__ (32)));
+
+  __builtin_memcpy (str, "Bug", 4);
+
+  if (arg <= 2)
+    __builtin_memcpy (str, s, sizeof (s));
+
+  if (arg <= 1)
+    __builtin_memcpy (str, "Err", 4);
+
+  __builtin_puts (str);
+
+  return str[0] != s[0];
+}
+
+int main () {
+  if (bug (2))
+    __builtin_abort ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/movti.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/movti.c
new file mode 100644
index 000000000..e306c1e3f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/movti.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-O -std=gnu99" } */
+
+_Decimal128 test (void)
+{
+  return 1234123412341234.123412341234dl;
+}
+
+/* { dg-final { scan-assembler-not "movabs" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mul.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mul.c
new file mode 100644
index 000000000..94f0b8dc8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/mul.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* This test checks for absolute memory operands.  */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "and\[^\\n\]*magic" } } */
+
+/* Should be done as "andw $32767, magic".  */
+static unsigned short magic;
+void t(void)
+{
+	magic%=(unsigned short)0x8000U;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/nrv1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/nrv1.c
new file mode 100644
index 000000000..5cd8b066d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/nrv1.c
@@ -0,0 +1,12 @@
+/* Verify that gimple-level NRV is occurring even for SSA_NAMEs.  *./
+/* { dg-do compile } */
+/* { dg-options "-O -fdump-tree-optimized" } */
+/* { dg-require-effective-target ilp32 } */
+
+_Complex double foo (_Complex double x)
+{
+  return __builtin_cexp (x);
+}
+
+/* { dg-final { scan-tree-dump-times "return slot optimization" 1 "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/opt-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/opt-1.c
new file mode 100644
index 000000000..7eb37e8fb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/opt-1.c
@@ -0,0 +1,34 @@
+/* Test the attribute((optimize)) really works.  Do this test by checking
+   whether we vectorize a simple loop.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse2 -mfpmath=sse -march=k8" } */
+/* { dg-final { scan-assembler "addps" } } */
+/* { dg-final { scan-assembler "subss" } } */
+
+#define SIZE 10240
+float a[SIZE] __attribute__((__aligned__(32)));
+float b[SIZE] __attribute__((__aligned__(32)));
+float c[SIZE] __attribute__((__aligned__(32)));
+
+/* This should vectorize.  */
+void opt3 (void) __attribute__((__optimize__(3,"unroll-all-loops")));
+
+void
+opt3 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] + c[i];
+}
+
+/* This should not vectorize.  */
+void
+not_opt3 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] - c[i];
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/opt-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/opt-2.c
new file mode 100644
index 000000000..15c0d2d57
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/opt-2.c
@@ -0,0 +1,37 @@
+/* Test the attribute((optimize)) really works.  Do this test by checking
+   whether we vectorize a simple loop.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse2 -mfpmath=sse -march=k8" } */
+/* { dg-final { scan-assembler "addps" } } */
+/* { dg-final { scan-assembler "subss" } } */
+
+#define SIZE 10240
+float a[SIZE] __attribute__((__aligned__(32)));
+float b[SIZE] __attribute__((__aligned__(32)));
+float c[SIZE] __attribute__((__aligned__(32)));
+
+/* This should vectorize.  */
+#pragma GCC push_options
+#pragma GCC optimize (3, "unroll-all-loops")
+
+void
+opt3 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] + c[i];
+}
+
+#pragma GCC pop_options
+
+/* This should not vectorize.  */
+void
+not_opt3 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] - c[i];
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ordcmp-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ordcmp-1.c
new file mode 100644
index 000000000..a136182ac
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ordcmp-1.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-final { scan-assembler "cmpordss" } } */
+/* { dg-final { scan-assembler "cmpordps" } } */
+/* { dg-final { scan-assembler "cmpordsd" } } */
+/* { dg-final { scan-assembler "cmpordpd" } } */
+/* { dg-final { scan-assembler-not "cmpunordss" } } */
+/* { dg-final { scan-assembler-not "cmpunordps" } } */
+/* { dg-final { scan-assembler-not "cmpunordsd" } } */
+/* { dg-final { scan-assembler-not "cmpunordpd" } } */
+
+#include <emmintrin.h>
+
+__m128
+f1 (__m128 x, __m128 y)
+{
+  return _mm_cmpord_ss (x, y);
+}
+
+__m128
+f2 (__m128 x, __m128 y)
+{
+  return _mm_cmpord_ps (x, y);
+}
+
+__m128d
+f3 (__m128d x, __m128d y)
+{
+  return _mm_cmpord_sd (x, y);
+}
+
+__m128d
+f4 (__m128d x, __m128d y)
+{
+  return _mm_cmpord_pd (x, y);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/parity-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/parity-1.c
new file mode 100644
index 000000000..0094b5bce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/parity-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "setnp" } } */
+
+int foo(unsigned int x)
+{
+  return __builtin_parity(x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/parity-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/parity-2.c
new file mode 100644
index 000000000..a4c238e0b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/parity-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "setnp" } } */
+
+int foo(unsigned long long int x)
+{
+  return __builtin_parityll(x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pclmul-avx-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pclmul-avx-check.h
new file mode 100644
index 000000000..de6333361
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pclmul-avx-check.h
@@ -0,0 +1,31 @@
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+#include <stdlib.h>
+#include "cpuid.h"
+
+static void pclmul_avx_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run PCLMUL + AVX test only if host has PCLMUL + AVX support.  */
+  if ((ecx & (bit_AVX | bit_PCLMUL)) == (bit_AVX | bit_PCLMUL))
+    {
+      pclmul_avx_test ();
+#ifdef DEBUG
+      printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pclmul-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pclmul-check.h
new file mode 100644
index 000000000..706fd6400
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pclmul-check.h
@@ -0,0 +1,30 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void pclmul_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run PCLMULQDQ test only if host has PCLMULQDQ support.  */
+  if (ecx & bit_PCLMUL)
+    {
+      pclmul_test ();
+#ifdef DEBUG
+      printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pclmulqdq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pclmulqdq.c
new file mode 100644
index 000000000..1c1d2aabe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pclmulqdq.c
@@ -0,0 +1,95 @@
+/* { dg-do run } */
+/* { dg-require-effective-target pclmul } */
+/* { dg-options "-O2 -mpclmul" } */
+
+#ifndef CHECK_H
+#define CHECK_H "pclmul-check.h"
+#endif
+
+#ifndef TEST
+#define TEST pclmul_test
+#endif
+
+#include CHECK_H
+
+#include <wmmintrin.h>
+#include <string.h>
+
+extern void abort (void);
+
+#define NUM 1024
+
+static __m128i s1[NUM];
+static __m128i s2[NUM];
+/* We need this array to generate mem form of inst */
+static __m128i s2m[NUM];
+
+static __m128i e_00[NUM];
+static __m128i e_01[NUM];
+static __m128i e_10[NUM];
+static __m128i e_11[NUM];
+
+static __m128i d_00[NUM];
+static __m128i d_01[NUM];
+static __m128i d_10[NUM];
+static __m128i d_11[NUM];
+
+/* Initialize input/output vectors.  (Currently, there is only one set
+   of input/output vectors).  */
+static void
+init_data (__m128i *ls1,   __m128i *ls2, __m128i *le_00, __m128i *le_01,
+	   __m128i *le_10, __m128i *le_11)
+{
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      ls1[i] = _mm_set_epi32 (0x7B5B5465, 0x73745665,
+			      0x63746F72, 0x5D53475D);
+      ls2[i] = _mm_set_epi32 (0x48692853, 0x68617929,
+			      0x5B477565, 0x726F6E5D);
+      s2m[i] = _mm_set_epi32 (0x48692853, 0x68617929,
+			      0x5B477565, 0x726F6E5D);
+      le_00[i] = _mm_set_epi32 (0x1D4D84C8, 0x5C3440C0,
+				0x929633D5, 0xD36F0451);
+      le_01[i] = _mm_set_epi32 (0x1A2BF6DB, 0x3A30862F,
+				0xBABF262D, 0xF4B7D5C9);
+      le_10[i] = _mm_set_epi32 (0x1BD17C8D, 0x556AB5A1,
+				0x7FA540AC, 0x2A281315);
+      le_11[i] = _mm_set_epi32 (0x1D1E1F2C, 0x592E7C45,
+				0xD66EE03E, 0x410FD4ED);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+
+  init_data (s1, s2, e_00, e_01, e_10, e_11);
+
+  for (i = 0; i < NUM; i += 2)
+    {
+      d_00[i] = _mm_clmulepi64_si128 (s1[i], s2m[i], 0x00);
+      d_01[i] = _mm_clmulepi64_si128 (s1[i], s2[i], 0x01);
+      d_10[i] = _mm_clmulepi64_si128 (s1[i], s2[i], 0x10);
+      d_11[i] = _mm_clmulepi64_si128 (s1[i], s2[i], 0x11);
+
+      d_11[i + 1] = _mm_clmulepi64_si128 (s1[i + 1], s2[i + 1], 0x11);
+      d_00[i + 1] = _mm_clmulepi64_si128 (s1[i + 1], s2[i + 1], 0x00);
+      d_10[i + 1] = _mm_clmulepi64_si128 (s1[i + 1], s2m[i + 1], 0x10);
+      d_01[i + 1] = _mm_clmulepi64_si128 (s1[i + 1], s2[i + 1], 0x01);
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      if (memcmp (d_00 + i, e_00 + i, sizeof (__m128i)))
+	abort ();
+      if (memcmp (d_01 + i, e_01 + i, sizeof (__m128i)))
+	abort ();
+      if (memcmp (d_10 + i, e_10 + i, sizeof (__m128i)))
+	abort ();
+      if (memcmp(d_11 + i, e_11 + i, sizeof (__m128i)))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pentium4-not-mull.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pentium4-not-mull.c
new file mode 100644
index 000000000..be48185a8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pentium4-not-mull.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=pentium4" } */
+/* { dg-final { scan-assembler-not "imull" } } */
+
+/* Should be done not using imull.  */
+int t(int x)
+{
+  return x*29;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pic-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pic-1.c
new file mode 100644
index 000000000..bc11de90b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pic-1.c
@@ -0,0 +1,20 @@
+/* PR target/8340 */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-fPIC" } */
+
+int foo ()
+{
+  static int a;
+
+  __asm__ __volatile__ (  /* { dg-error "PIC register" } */
+    "xorl %%ebx, %%ebx\n"
+    "movl %%ebx, %0\n"
+    : "=m" (a)
+    :
+    : "%ebx"
+  );
+
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pow-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pow-1.c
new file mode 100644
index 000000000..2e1ac61bd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pow-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O -ffast-math" } */
+
+double test1 (double x)
+{
+  return __builtin_pow (x, 1./2.);
+}
+
+double test2 (double x)
+{
+  return __builtin_pow (x, 3./2.);
+}
+
+double test3 (double x)
+{
+  return __builtin_pow (x, 5./2.);
+}
+
+double test4 (double x)
+{
+  return __builtin_pow (x, -5./2.);
+}
+
+/* { dg-final { scan-assembler-not "call\[ \t\]*pow" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memcpy-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memcpy-1.c
new file mode 100644
index 000000000..c63f84869
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memcpy-1.c
@@ -0,0 +1,23 @@
+/* Ensure that we don't use 'rep movX' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-Os -w" } */
+
+extern void *memcpy (void *, const void *, __SIZE_TYPE__);
+
+register int regvar asm("%esi");
+
+int foo[10];
+int bar[10];
+
+char baz[15];
+char quux[15];
+
+void
+do_copy ()
+{
+  memcpy (foo, bar, sizeof foo);
+  memcpy (baz, quux, sizeof baz);
+}
+
+/* { dg-final { scan-assembler-not "rep movsl" } } */
+/* { dg-final { scan-assembler-not "rep movsb" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memcpy-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memcpy-2.c
new file mode 100644
index 000000000..ae1c3a886
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memcpy-2.c
@@ -0,0 +1,23 @@
+/* Ensure that we don't use 'rep movX' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-Os -w" } */
+
+extern void *memcpy (void *, const void *, __SIZE_TYPE__);
+
+register int regvar asm("%edi");
+
+int foo[10];
+int bar[10];
+
+char baz[15];
+char quux[15];
+
+void
+do_copy ()
+{
+  memcpy (foo, bar, sizeof foo);
+  memcpy (baz, quux, sizeof baz);
+}
+
+/* { dg-final { scan-assembler-not "rep movsl" } } */
+/* { dg-final { scan-assembler-not "rep movsb" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memcpy-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memcpy-3.c
new file mode 100644
index 000000000..0f5bd561d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memcpy-3.c
@@ -0,0 +1,23 @@
+/* Ensure that we don't use 'rep movX' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-Os -w" } */
+
+extern void *memcpy (void *, const void *, __SIZE_TYPE__);
+
+register int regvar asm("%ecx");
+
+int foo[10];
+int bar[10];
+
+char baz[15];
+char quux[15];
+
+void
+do_copy ()
+{
+  memcpy (foo, bar, sizeof foo);
+  memcpy (baz, quux, sizeof baz);
+}
+
+/* { dg-final { scan-assembler-not "rep movsl" } } */
+/* { dg-final { scan-assembler-not "rep movsb" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memset-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memset-1.c
new file mode 100644
index 000000000..e44d32fb4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memset-1.c
@@ -0,0 +1,23 @@
+/* Ensure that we don't use 'rep stoX' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-Os -w" } */
+
+extern void *memset (void *, int, __SIZE_TYPE__);
+
+register int regvar asm("%eax");
+
+int foo[10];
+int bar[10];
+
+char baz[15];
+char quux[15];
+
+void
+do_copy ()
+{
+  memset (foo, 0, sizeof foo);
+  memset (baz, 0, sizeof baz);
+}
+
+/* { dg-final { scan-assembler-not "rep stosl" } } */
+/* { dg-final { scan-assembler-not "rep stosb" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memset-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memset-2.c
new file mode 100644
index 000000000..02fc8d319
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memset-2.c
@@ -0,0 +1,23 @@
+/* Ensure that we don't use 'rep stoX' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-Os -w" } */
+
+extern void *memset (void *, int, __SIZE_TYPE__);
+
+register int regvar asm("%ecx");
+
+int foo[10];
+int bar[10];
+
+char baz[15];
+char quux[15];
+
+void
+do_copy ()
+{
+  memset (foo, 0, sizeof foo);
+  memset (baz, 0, sizeof baz);
+}
+
+/* { dg-final { scan-assembler-not "rep stosl" } } */
+/* { dg-final { scan-assembler-not "rep stosb" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memset-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memset-3.c
new file mode 100644
index 000000000..1bdfb8656
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-memset-3.c
@@ -0,0 +1,23 @@
+/* Ensure that we don't use 'rep stoX' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-Os -w" } */
+
+extern void *memset (void *, int, __SIZE_TYPE__);
+
+register int regvar asm("%edi");
+
+int foo[10];
+int bar[10];
+
+char baz[15];
+char quux[15];
+
+void
+do_copy ()
+{
+  memset (foo, 0, sizeof foo);
+  memset (baz, 0, sizeof baz);
+}
+
+/* { dg-final { scan-assembler-not "rep stosl" } } */
+/* { dg-final { scan-assembler-not "rep stosb" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-strlen-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-strlen-1.c
new file mode 100644
index 000000000..6e159e445
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-strlen-1.c
@@ -0,0 +1,16 @@
+/* Ensure that we don't use 'repnz scasb' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -w" } */
+
+extern __SIZE_TYPE__ strlen (const char *);
+extern void *malloc (__SIZE_TYPE__);
+
+register int regvar asm("%edi");
+
+char *
+do_copy (char *str)
+{
+  return malloc (strlen (str) + 1);
+}
+
+/* { dg-final { scan-assembler-not "repnz scasb" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-strlen-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-strlen-2.c
new file mode 100644
index 000000000..e03adb25f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-strlen-2.c
@@ -0,0 +1,16 @@
+/* Ensure that we don't use 'repnz scasb' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -w" } */
+
+extern __SIZE_TYPE__ strlen (const char *);
+extern void *malloc (__SIZE_TYPE__);
+
+register int regvar asm("%eax");
+
+char *
+do_copy (char *str)
+{
+  return malloc (strlen (str) + 1);
+}
+
+/* { dg-final { scan-assembler-not "repnz scasb" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-strlen-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-strlen-3.c
new file mode 100644
index 000000000..c7a379ae0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr11001-strlen-3.c
@@ -0,0 +1,16 @@
+/* Ensure that we don't use 'repnz scasb' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -w" } */
+
+extern __SIZE_TYPE__ strlen (const char *);
+extern void *malloc (__SIZE_TYPE__);
+
+register int regvar asm("%ecx");
+
+char *
+do_copy (char *str)
+{
+  return malloc (strlen (str) + 1);
+}
+
+/* { dg-final { scan-assembler-not "repnz scasb" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr12092-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr12092-1.c
new file mode 100644
index 000000000..d85807e8d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr12092-1.c
@@ -0,0 +1,13 @@
+/* PR rtl-optimization/12092  */
+/* Test case reduced by Andrew Pinski <pinskia@physics.uc.edu> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mtune=i486 -march=pentium4 -fprefetch-loop-arrays" } */
+
+void DecodeAC(int index,int *matrix)
+{
+  int *mptr;
+
+  for(mptr=matrix+index;mptr<matrix+64;mptr++) {*mptr = 0;}
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr12329.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr12329.c
new file mode 100644
index 000000000..21d2c6580
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr12329.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+int test_nested (int i)
+{
+  int __attribute__ ((__noinline__, __regparm__(3))) foo(int j, int k, int l) /* { dg-error "nested functions are limited to 2 register parameters" } */
+  {
+    return i + j + k + l;
+  }
+
+  return foo (i, i+1, i+2);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr13366.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr13366.c
new file mode 100644
index 000000000..f0dce0b24
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr13366.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O -msse" } */
+
+#include <xmmintrin.h>
+
+typedef unsigned short v4hi __attribute__ ((vector_size (8)));
+
+int f(unsigned short n)
+{
+   __m64 vec = (__m64)(v4hi){ 0, 0, 1, n };
+   __m64 hw = _mm_mulhi_pi16 (vec, vec);
+   return _mm_extract_pi16 (hw, 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr13685.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr13685.c
new file mode 100644
index 000000000..159112d16
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr13685.c
@@ -0,0 +1,31 @@
+/* PR target/13685 */
+/* { dg-do run } */
+/* { dg-options "-Os -msse" } */
+
+#include "sse-check.h"
+
+#include <xmmintrin.h>
+
+void foo (__m128 *, __m64 *, int);
+
+__m128 xmm0 = { 0 };
+__m64 mm0 = { 0 };
+
+static void
+sse_test (void)
+{
+  foo (&xmm0, &mm0, 4);
+}
+
+void
+foo (__m128 *dst, __m64 *src, int n)
+{
+  __m128 xmm0 = { 0 };
+  while (n > 64)
+    {
+      puts ("");
+      xmm0 = _mm_cvtpi32_ps (xmm0, *src);
+      *dst = xmm0;
+      n--;
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr14289-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr14289-1.c
new file mode 100644
index 000000000..e427b2d0c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr14289-1.c
@@ -0,0 +1,12 @@
+/* PR middle-end/14289 */
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+
+register int a[2] asm("ebx");
+
+void Nase(void)
+{
+  int i=6;
+  a[i]=5;  /* { dg-error "address of global" } */
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr14552.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr14552.c
new file mode 100644
index 000000000..659257c32
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr14552.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmmx" } */
+
+typedef short mmxw  __attribute__ ((vector_size (8)));
+typedef int   mmxdw __attribute__ ((vector_size (8)));
+
+mmxdw dw;
+mmxw w;
+
+void test()
+{
+  w+=w;
+  dw= (mmxdw)w;
+}
+
+/* { dg-final { scan-assembler-not "%mm" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr17390.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr17390.c
new file mode 100644
index 000000000..9a3d61fcd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr17390.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -mfpmath=387" } */
+
+double sgn (double __x)
+{
+  return __x == 0.0 ? 0.0 : (__x > 0.0 ? 1.0 : -1.0);
+}
+
+/* { dg-final { scan-assembler-times "fcom|ftst" 1 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr17692.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr17692.c
new file mode 100644
index 000000000..a837386a3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr17692.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mfpmath=sse -msse2" } */
+/* The fact that t1 and t2 are uninitialized is critical.  With them
+   uninitialized, the register allocator is free to put them in the same
+   hard register, which results in
+
+	xmm0 = xmm0 >= xmm0 ? xmm0 : xmm0
+
+   Which is of course a nop, but one for which we would ICE splitting the
+   pattern.  */
+   
+double out;
+
+static void foo(void)
+{
+    double t1, t2, t3, t4;
+    
+    t4 = t1 >= t2 ? t1 : t2;
+    t4 = t4 >= t3 ? t4 : t3;
+    out = t4;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr18614-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr18614-1.c
new file mode 100644
index 000000000..1a4997537
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr18614-1.c
@@ -0,0 +1,15 @@
+/* PR rtl-optimization/18614 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef double v2df __attribute__ ((vector_size (16)));
+
+v2df foo (void)
+{
+  v2df yd = { 1.0, 4.0 };
+  v2df xd;
+
+  xd = __builtin_ia32_cvtps2pd (__builtin_ia32_rsqrtps
+				(__builtin_ia32_cvtpd2ps (yd)));
+  return xd;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr19236-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr19236-1.c
new file mode 100644
index 000000000..38db79812
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr19236-1.c
@@ -0,0 +1,14 @@
+/* PR target/19236 */
+/* { dg-do compile } */
+/* { dg-options "-ffast-math" } */
+
+extern float log1pf (float);
+extern double log1p (double);  
+
+float testf (float __x) { 
+  return log1pf(1.0); 
+}
+
+double test (double __x) { 
+  return log1p(1.0); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr20204.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr20204.c
new file mode 100644
index 000000000..ca97a3ae9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr20204.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+void *x (void *pdst, const void *psrc, unsigned int pn)
+{
+  register void *return_dst = pdst;
+  register unsigned char *dst = pdst;
+  register unsigned const char *src = psrc;
+  register int n __asm__ ("ebx") = pn;
+
+  if (src < dst && dst < src + n)
+    {
+      src += n;
+      dst += n;
+      while (n--)
+        *--dst = *--src;
+      return return_dst;
+    }
+
+  while (n >= 16) n--;
+
+  return return_dst;
+}
+extern void abort ();
+extern void exit (int);
+char xx[30] = "abc";
+int main (void)
+{
+  char yy[30] = "aab";
+
+  if (x (xx + 1, xx, 2) != xx + 1 || memcmp (xx, yy, sizeof (yy)) != 0)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr21101.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr21101.c
new file mode 100644
index 000000000..104b08cd2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr21101.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -funroll-loops -march=nocona" } */
+
+#include <mmintrin.h>
+
+int W;
+void f()
+{
+  int j;
+  int B, C;
+  unsigned char* S;
+  __m64 *T = (__m64 *) &W;
+
+  for (j = 0; j < 16; j++, T++)
+  {
+    T[0] = T[1] = _mm_set1_pi8(*S);
+    S += W;
+  }
+
+  C = 3 * B;
+
+  __m64 E = _mm_set_pi16(3 * B, 3 * B, 3 * B, 5 * B);
+  __m64 G = _mm_set1_pi16(3 * B);
+
+  for (j = 0; j < 16; j++)
+  {
+    __m64 R = _mm_set1_pi16(B + j * C);
+    R = _m_paddw(R, E);
+    R = _m_paddw(R, G);
+    T[0] = _mm_srai_pi16(R, 3);
+  }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr21291.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr21291.c
new file mode 100644
index 000000000..b59750985
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr21291.c
@@ -0,0 +1,36 @@
+/* The asm has 2 "r" in/out operands, 1 earlyclobber "r" output, 1 "r"
+   input and 2 fixed "r" clobbers (eax and edx), so there are a total of
+   6 registers that must not conflict.  Add to that the PIC register,
+   the frame pointer, and the stack pointer, and we've run out of
+   registers on 32-bit targets.  */
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+typedef unsigned long bngdigit;
+typedef bngdigit *bng;
+typedef unsigned int bngcarry;
+typedef unsigned long bngsize;
+
+bngdigit
+bng_ia32_mult_sub_digit (bng a, bngsize alen, bng b, bngsize blen, bngdigit d)
+{
+  bngdigit out, tmp;
+  bngcarry carry;
+  bngdigit a11;
+
+  alen -= blen;
+  out = 0;
+  asm (""
+       : "+r" (a), "+r" (b), "+mr" (blen), "+mr" (out), "=&r" (tmp)
+       : "mr" (d)
+       : "eax", "edx");
+  if (alen == 0)
+    {
+      a11 = out;
+      goto t;
+    }
+
+  a11 = 1;
+ t:
+  return a11;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr21518.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr21518.c
new file mode 100644
index 000000000..b42d9c9f0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr21518.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fPIC -fno-tree-pre" } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target fpic } */
+
+extern void __attribute__ ((regparm (3)))
+drawPointsLines (char type, int first, int *dd);
+
+int
+do_locator (int *call)
+{
+  char prephitmp5;
+  int type;
+  int i;
+
+  if (call == 0)
+    prephitmp5 = 1;
+  else
+    {
+      type = *call;
+      i = 0;
+      do
+	{
+	  if (i != type)
+	    drawPointsLines ((int) (char) type, 0, call);
+	  i = i + 1;
+	}
+      while (i != 2);
+      prephitmp5 = (char) type;
+    }
+  drawPointsLines ((int) prephitmp5, 0, call);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22076.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22076.c
new file mode 100644
index 000000000..5195f361c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22076.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fomit-frame-pointer -flax-vector-conversions -mmmx" } */
+
+#include <mmintrin.h>
+
+__v8qi test ()
+{
+  __v8qi mm0 = {1,2,3,4,5,6,7,8};
+  __v8qi mm1 = {11,22,33,44,55,66,77,88};
+  volatile __m64 x;
+
+  x = _mm_add_pi8 (mm0, mm1);
+
+  return x;
+}
+
+/* { dg-final { scan-assembler-times "movq" 3 } } */
+/* { dg-final { scan-assembler-not "movl" { target nonpic } } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22152.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22152.c
new file mode 100644
index 000000000..d12597703
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22152.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <mmintrin.h>
+
+__m64
+unsigned_add3 (const __m64 * a, const __m64 * b, unsigned long count)
+{
+  __m64 sum;
+  unsigned int i;
+
+  for (i = 1; i < count; i++)
+    sum = _mm_add_si64 (a[i], b[i]);
+
+  return sum;
+}
+
+/* { dg-final { scan-assembler-times "movq\[ \\t\]+.*%mm" 1 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22362.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22362.c
new file mode 100644
index 000000000..a7c78b12f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22362.c
@@ -0,0 +1,25 @@
+/* PR target/22362 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target ilp32 } */
+
+register unsigned int reg0 __asm__ ("esi");
+register unsigned int reg1 __asm__ ("edi");
+register unsigned int reg2 __asm__ ("ebx");
+
+static unsigned int
+__attribute__((noinline))
+foo (unsigned long *x, void *y, void *z)
+{
+  int i;
+
+  for (i = 5; i > 0; i--)
+    x[i] = (unsigned long) foo ((unsigned long *) x[i], y, z);
+  return 0;
+}
+
+unsigned int
+bar (void)
+{
+  return foo (0, 0, 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22432.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22432.c
new file mode 100644
index 000000000..86ae4b28f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22432.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmmx" } */
+/* { dg-final { scan-assembler-not "paddb" } } */
+
+typedef int v2si __attribute__ ((__vector_size__ (8)));
+typedef short v4hi __attribute__ ((__vector_size__ (8)));
+typedef char v8qi __attribute__ ((__vector_size__ (8)));
+
+int
+foo (unsigned int *a, unsigned int *b)
+{
+  long long i, j, k;
+
+  i = (long long) __builtin_ia32_vec_init_v2si (*a, 0);
+  j = (long long) __builtin_ia32_vec_init_v2si (*b, 0);
+  i = (long long) __builtin_ia32_punpcklbw ((v8qi) i, (v8qi) 0ll);
+  j = (long long) __builtin_ia32_punpcklbw ((v8qi) j, (v8qi) 0ll);
+  k = (long long) __builtin_ia32_paddw ((v4hi) i, (v4hi) j);
+  return __builtin_ia32_vec_ext_v2si ((v2si) k, 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22576.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22576.c
new file mode 100644
index 000000000..083fbf648
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22576.c
@@ -0,0 +1,10 @@
+/* PR target/22576 */
+/* Testcase reduced by Volker Reichelt */
+/* { dg-do compile } */
+/* { dg-options "-ffast-math" } */
+
+int
+foo (long double d)
+{
+  return d == 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22585.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22585.c
new file mode 100644
index 000000000..9ba2da537
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr22585.c
@@ -0,0 +1,12 @@
+/* PR target/22585 */
+/* Testcase reduced by Volker Reichelt */
+/* { dg-do compile } */
+/* { dg-options "-march=i386 -O -ffast-math" } */
+/* { dg-require-effective-target ilp32 } */
+
+int
+foo (long double d, int i)
+{
+  if (d == (long double) i)
+    return 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23098.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23098.c
new file mode 100644
index 000000000..d91bf2a5f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23098.c
@@ -0,0 +1,26 @@
+/* PR rtl-optimization/23098 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fPIC" } */
+/* { dg-final { scan-assembler-not "\.LC\[0-9\]" { xfail *-*-vxworks* } } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target fpic } */
+
+double foo (float);
+
+double
+f1 (void)
+{
+  return foo (1.0);
+}
+
+double
+f2 (void)
+{
+  return foo (0.0);
+}
+
+void
+f3 (float *x, float t)
+{
+  *x = 0.0 + t;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23268.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23268.c
new file mode 100644
index 000000000..b5645b297
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23268.c
@@ -0,0 +1,13 @@
+/* PR target/23268 */
+/* Testcase reduced by Andrew Pinski */
+/* { dg-do compile } */
+/* { dg-options "-O1 -ffast-math" } */
+
+int
+f (float x)
+{
+  int a, b;
+  a = __builtin_log (2.f);
+  b = __builtin_lrint (x);
+  return (a + b);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23376.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23376.c
new file mode 100644
index 000000000..0dee77f6b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23376.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -mmmx -funroll-loops -fvariable-expansion-in-unroller" } */
+
+typedef int __m64 __attribute__ ((__vector_size__ (8)));
+typedef int __v2si __attribute__ ((__vector_size__ (8)));
+
+static __inline __m64 __attribute__((__always_inline__))
+_mm_add_pi32 (__m64 __m1, __m64 __m2)
+{
+  return (__m64) __builtin_ia32_paddd ((__v2si)__m1, (__v2si)__m2);
+}
+
+__m64
+simple_block_diff_up_mmx_4 (const int width, __m64 ref1)
+{
+  __m64 sum;
+  int count = width >>1;
+  while (count--)
+    sum = _mm_add_pi32 (sum, ref1);
+  return sum;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23570.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23570.c
new file mode 100644
index 000000000..1542663fa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23570.c
@@ -0,0 +1,92 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef float __v4sf __attribute__ ((__vector_size__ (16)));
+typedef float __m128 __attribute__ ((__vector_size__ (16)));
+typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+
+static __inline __m128
+_mm_cmpeq_ps (__m128 __A, __m128 __B)
+{
+  return (__m128) __builtin_ia32_cmpeqps ((__v4sf)__A, (__v4sf)__B);
+}
+
+static __inline __m128
+_mm_setr_ps (float __Z, float __Y, float __X, float __W)
+{
+  return __extension__ (__m128)(__v4sf){__Z, __Y, __X, __W };
+}
+
+static __inline __m128
+_mm_and_si128 (__m128 __A, __m128 __B)
+{
+  return (__m128)__builtin_ia32_pand128 ((__v2di)__A, (__v2di)__B);
+}
+
+static __inline __m128
+_mm_or_si128 (__m128 __A, __m128 __B)
+{
+  return (__m128)__builtin_ia32_por128 ((__v2di)__A, (__v2di)__B);
+}
+
+typedef union
+{
+  __m128 xmmi;
+  int si[4];
+}
+__attribute__ ((aligned (16))) um128;
+
+um128 u;
+
+static inline int
+sse_max_abs_indexf (float *v, int step, int n)
+{
+  __m128 m1, mm;
+  __m128 mim, mi, msk;
+  um128 u, ui;
+  int n4, step2, step3;
+  mm = __builtin_ia32_andps ((__m128) (__v4sf)
+			     { 0.0, v[step], v[step2], v[step3] }
+			     , u.xmmi);
+  if (n4)
+    {
+      int i;
+      for (i = 0; i < n4; ++i);
+      msk = (__m128) _mm_cmpeq_ps (m1, mm);
+      mim = _mm_or_si128 (_mm_and_si128 (msk, mi), mim);
+    }
+  ui.xmmi = (__m128) mim;
+  return ui.si[n];
+}
+
+static void
+sse_swap_rowf (float *r1, float *r2, int n)
+{
+  int n4 = (n / 4) * 4;
+  float *r14end = r1 + n4;
+  while (r1 < r14end)
+    {
+      *r1 = *r2;
+      r1++;
+    }
+}
+
+void
+ludcompf (float *m, int nw, int *prow, int n)
+{
+  int i, s = 0;
+  float *pm;
+  for (i = 0, pm = m; i < n - 1; ++i, pm += nw)
+    {
+      int vi = sse_max_abs_indexf (pm + i, nw, n - i);
+      float *pt;
+      int j;
+      if (vi != 0)
+	{
+	  sse_swap_rowf (pm, pm + vi * nw, nw);
+	  swap_index (prow, i, i + vi);
+	}
+      for (j = i + 1, pt = pm + nw; j < n; ++j, pt += nw)
+	sse_add_rowf (pt + i + 1, pm + i + 1, -1.0, n - i - 1);
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23575.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23575.c
new file mode 100644
index 000000000..522226ef7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23575.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2 -O2" } */
+
+/* We used to ICE because of a bogous pattern.  */
+
+typedef double __v2df __attribute__ ((__vector_size__ (16)));
+typedef __v2df __m128d;
+static __inline __m128d __attribute__((__always_inline__)) _mm_set1_pd (double __F) {
+  return __extension__ (__m128d){__F, __F};
+}
+static __inline __m128d __attribute__((__always_inline__)) _mm_move_sd (__m128d __A, __m128d __B) {
+  return (__m128d) __builtin_ia32_movsd ((__v2df)__A, (__v2df)__B);
+}
+void g(__m128d b);
+__m128d cross(__m128d tmp9)
+{
+  __m128d t1 = _mm_set1_pd(1.0);
+  __m128d tmp10 = _mm_move_sd(t1, tmp9);
+  return tmp10;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23943.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23943.c
new file mode 100644
index 000000000..9e14036ec
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr23943.c
@@ -0,0 +1,21 @@
+/* This used to ICE in side_effects_p, due to a problem in cse.c.
+   Origin: marcus at jet dot franken dot de.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -fPIC" } */
+
+typedef long unsigned int size_t;
+
+extern size_t strlen (__const char *__s)
+    __attribute__ ((__nothrow__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1)));
+
+static char savecallsin[256] = "";
+
+int read_agent_config(void)
+{
+  savecallsin[0] = '\0';
+
+  if (savecallsin[strlen(savecallsin) - 1] != '/')
+    __builtin___strncat_chk (savecallsin, "/", sizeof(savecallsin) - strlen(savecallsin) - 1, __builtin_object_size (savecallsin, 2 > 1)) ;
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr24055.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr24055.c
new file mode 100644
index 000000000..5190ec4b9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr24055.c
@@ -0,0 +1,26 @@
+/* PR target/24055 */
+/* Testcase reduced by Serge Belyshev */
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math" } */
+
+extern double rint(double);
+
+void foo_1 (int *p, double x)
+{
+  *p = rint (x);
+}
+
+void foo_2 (long long *p, double x)
+{
+  *p = rint (x);
+}
+
+int foo_3 (double x)
+{
+  return rint (x);
+}
+
+long long foo_4 (double x)
+{
+  return rint (x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr24306.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr24306.c
new file mode 100644
index 000000000..c578475bb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr24306.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-msse" } */
+
+#include "sse-check.h"
+
+extern void abort(void);
+typedef int __attribute__ ((vector_size (16))) foo_t;
+
+struct s
+{
+  foo_t f[0];
+} s1;
+
+void
+check (int x, ...) __attribute__((noinline));
+void
+check (int x, ...)
+{
+  int y;
+  __builtin_va_list ap;
+
+  __builtin_va_start (ap, x);
+  __builtin_va_arg (ap, struct s);
+  y = __builtin_va_arg (ap, int);
+
+  if (y != 7)
+    abort ();
+}
+
+static void
+sse_test (void)
+{
+  check (3, s1, 7);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr24315.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr24315.c
new file mode 100644
index 000000000..dc6133eb9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr24315.c
@@ -0,0 +1,9 @@
+/* PR target/24315 */
+/* { dg-do compile } */
+/* { dg-options "-O0 -fpeephole2" } */
+
+void s48_double_to_bignum (int exponent)
+{
+  long length = ((((exponent) + ((((sizeof (long)) * 8) - 2) - 1)) /
+		  (((sizeof (long)) * 8) - 2)));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr25196.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr25196.c
new file mode 100644
index 000000000..c3b69b87a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr25196.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-march=i386 -O3 -fomit-frame-pointer" } */
+
+/* For this test case, we used to do an invalid load motion after
+   reload, because we missed autoincrements of the stack pointer.  */
+
+extern void abort (void);
+
+static int j;
+
+static void __attribute__((noinline))
+f1 (int a, int b, int c, int d, int e)
+{
+  j = a;
+}
+
+int __attribute__((noinline))
+f2 (int a, int b, int c, int d, int e)
+{
+  if ((b & 0x1111) != 1)
+    f1 (a, b, c, d, e);
+  return 0;
+}
+
+int
+main (void)
+{
+  f2 (123, 0, 0, 0, 0);
+  if (j != 123)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr25254.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr25254.c
new file mode 100644
index 000000000..ad602024c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr25254.c
@@ -0,0 +1,12 @@
+/* PR target/25254 */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mcmodel=medium -mlarge-data-threshold=1" } */
+
+const struct { int i; int j; } c = { 2, 6 };
+
+const char *
+foo (void)
+{
+  return "OK";
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr25293.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr25293.c
new file mode 100644
index 000000000..6217da2a0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr25293.c
@@ -0,0 +1,51 @@
+/* PR target/25293 */
+/* { dg-do compile } */
+/* { dg-options "-mpreferred-stack-boundary=2 -mtune=i586 -O2 -fomit-frame-pointer -g" } */
+/* { dg-require-effective-target ilp32 } */
+
+struct T { unsigned short t1, t2, t3, t4, t5, t6, t7; };
+struct S { struct T s1; unsigned short s2, s3; };
+unsigned short v1;
+int f1 (void);
+int f2 (struct T);
+int f3 (const char *);
+
+int
+foo (struct S *x, struct T y)
+{
+  unsigned short a, b, c;
+  unsigned long d, e;
+  int f = 0;
+  y.t6 = 6;
+  a = y.t7;
+  b = y.t6;
+  c = y.t7;
+  switch (a)
+    {
+    case 8:
+    case 7:
+      c = 9;
+      break;
+    case 1:
+    case 6:
+    case 3:
+      b = 16;
+      c = 9;
+      break;
+    }
+  if ((f = f1 ()))
+    goto error;
+  if ((f = f2 (y)))
+    goto error;
+  d = (long) &y;
+  e = (long) &x->s1;
+  __asm __volatile ("" : "+D" (e), "+S" (d) :: "memory");
+  x->s2 = b;
+  x->s3 = c;
+  f3 ("foo");
+  return 0;
+error:
+  if (v1 >= 1)
+    f3 ("bar");
+  return f;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr25654.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr25654.c
new file mode 100644
index 000000000..2d7ef221f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr25654.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=2 -march=i686 -frename-registers" } */
+
+extern void abort (void) __attribute__((noreturn));
+
+struct wrapper {
+union setconflict
+{
+  short a[20];
+  int b[10];
+} a;
+};
+
+int
+main ()
+{
+  int sum = 0;
+  {
+    struct wrapper a;
+    short *c;
+    c = a.a.a;
+    asm ("": "=r" (c):"0" (c));
+    *c = 0;
+    asm ("": "=r" (c):"0" (c));
+    sum += *c;
+  }
+  {
+    struct wrapper a;
+    int *c;
+    c = a.a.b;
+    asm ("": "=r" (c):"0" (c));
+    *c = 1;
+    asm ("": "=r" (c):"0" (c));
+    sum += *c;
+  }
+
+  if (sum != 1)
+    abort();
+  return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr25993.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr25993.c
new file mode 100644
index 000000000..38d0e0f35
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr25993.c
@@ -0,0 +1,14 @@
+/* { dg-do assemble } */
+/* { dg-skip-if "" { "*-*-darwin*" "*-*-mingw*" } { "*" } { "" } } */
+/* { dg-options "-std=c99 -x assembler-with-cpp" } */
+
+#ifndef __ASSEMBLER__
+extern int func(void);
+#else
+.global func
+.type func,%function
+.align 4
+func:
+        ret
+.size func,.-func
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr26449-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr26449-1.c
new file mode 100644
index 000000000..b4ef78048
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr26449-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mtune=k8" } */
+
+typedef short __v8hi __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+
+void sse2_test (void)
+{
+  union
+  {
+    __m128i x;
+  } val1, res[8], tmp;
+  short ins[8] = { 8, 5, 9, 4, 2, 6, 1, 20 };
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      tmp.x = val1.x;
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+        (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi) val1.x, ins[i], 0);
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr26449.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr26449.c
new file mode 100644
index 000000000..7a6129684
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr26449.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O1 -ftree-vectorize -march=pentium4 -std=c99" } */
+
+void matmul_i4 (int bbase_yn, int xcount)
+{
+  int x;
+  int * restrict dest_y;
+  const int * abase_n;
+
+  for (x = 0;  x < xcount;  x++)
+    {
+      dest_y[x] += abase_n[x] * bbase_yn;
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr26600.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr26600.c
new file mode 100644
index 000000000..bbe0663da
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr26600.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O -ftree-vectorize -msse2" } */
+
+void foo(int *p, int N)
+{
+    int i;
+    for (i=0; i<8; ++i, ++p)
+    {
+        int j = N+2*(N+p[0]), k = 2*N+p[0];
+        p[0] = j+N;
+        p[5] = j+k;
+    }
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr26778.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr26778.c
new file mode 100644
index 000000000..6f6f27725
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr26778.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=pentium3" } */
+
+typedef union {
+  long long l;
+  double d;
+} db_number;
+
+double test(double x[3]) {
+  double th = x[1] + x[2];
+  if (x[2] != th - x[1]) {
+    db_number thdb;
+    thdb.d = th;
+    thdb.l++;
+    th = thdb.d;
+  }
+  return x[0] + th;
+}
+
+/* { dg-final { scan-assembler-not "mov.ps" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr26826.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr26826.c
new file mode 100644
index 000000000..8adab3a36
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr26826.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O -fomit-frame-pointer -march=i586" } */
+
+void foo(char* p, char c, int i)
+{
+    char a[2], *q=a+1;
+    if (p && i)
+        *p = q-a+bar(i);
+    if (c)
+        bar(i);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr27266.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr27266.c
new file mode 100644
index 000000000..73e7c596f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr27266.c
@@ -0,0 +1,14 @@
+/* PR target/27266.
+   The testcase below used to trigger an ICE.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-march=pentium" } */
+
+signed long long sll;
+
+void
+foo (void)
+{
+  __sync_fetch_and_add (&sll, 1);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr27696.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr27696.c
new file mode 100644
index 000000000..2f281e3f7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr27696.c
@@ -0,0 +1,11 @@
+/* PR target/27696
+   The testcase below uses to trigger an ICE.  */
+
+/* { dg-do compile } */
+/* { dg-options "-msse3" } */
+
+void
+foo (void const * P, unsigned int E, unsigned int H)
+{
+  __builtin_ia32_monitor (P, E, H);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr27790.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr27790.c
new file mode 100644
index 000000000..e8986c415
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr27790.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O -ftree-vectorize -msse2" } */
+
+void binarize (int npixels, unsigned char *b)
+{
+  int i;
+  for (i = 0; i < npixels; i++)
+    b[i] = (b[i] > 225 ? 0xff : 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr27827.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr27827.c
new file mode 100644
index 000000000..3b337444a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr27827.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mfpmath=387" } */
+
+double a, b;
+double f(double c)
+{
+  double x = a * b;
+  return x + c * a;
+}
+
+/* { dg-final { scan-assembler-not "fld\[ \t\]*%st" } } */
+/* { dg-final { scan-assembler "fmul\[ \t\]*%st" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr27971.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr27971.c
new file mode 100644
index 000000000..8c706adda
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr27971.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned array[4];
+
+unsigned foo(unsigned long x)
+{
+          return array[(x>>2)&3ul];
+}
+
+/* { dg-final { scan-assembler-not "shr\[^\\n\]*2" } } */
+/* { dg-final { scan-assembler "and\[^\\n\]*12" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr28839.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr28839.c
new file mode 100644
index 000000000..6a215164c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr28839.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -ftree-vectorize -funswitch-loops" } */
+
+static int ready[10];
+void abort (void);
+void test_once (int t,int t1)
+{
+  int i, repeat;
+  for (i = 0; i < 10; i++)
+    {
+      ready[i] = 0;
+      if (t1)
+	if (b())
+	  abort ();
+    }
+  if (t)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr28946.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr28946.c
new file mode 100644
index 000000000..bdc2fd15f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr28946.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+/* { dg-final { scan-assembler-not "test" } } */
+
+int fct1 (void);
+int fct2 (void);
+
+int
+fct (unsigned nb)
+{
+  if ((nb >> 5) != 0)
+    return fct1 ();
+  else
+    return fct2 ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr29978.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr29978.c
new file mode 100644
index 000000000..8c0bf9f5e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr29978.c
@@ -0,0 +1,16 @@
+/* PR target/29978 */
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+void g ();
+
+void
+f (long long v)
+{
+  if (v > 0xfffffffffLL)
+    g ();
+  g ();
+}
+
+/* Verify there are no redundant jumps jl .L2; jle .L2 */
+/* { dg-final { scan-assembler-not "jl\[^e\]*\\.L" { target ilp32 } } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30120.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30120.c
new file mode 100644
index 000000000..22fd843a7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30120.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math" } */
+
+extern void abort (void);
+
+static void
+foo (double a, double weight, const double *ring, double *phase)
+{
+  *phase = *ring * weight;
+}
+
+void
+foo2 (void)
+{
+  foo (0, 1, (double *) 0, (double *) 0);
+}
+
+int
+main (void)
+{
+  double t1 = 1, c1;
+  foo (0, 1, &t1, &c1);
+  if (c1 < 0.5)
+    abort();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30315.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30315.c
new file mode 100644
index 000000000..998d5071e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30315.c
@@ -0,0 +1,97 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "cmp" 4 } } */
+
+extern void abort (void);
+int c;
+
+#define PLUSCC1(T, t, C)	\
+T pluscc##t##C (T a, T b)	\
+{	\
+  T sum = a + b;	\
+  if (sum < C)		\
+    abort ();		\
+  return sum;		\
+}
+#define PLUSCC(T, t) PLUSCC1(T, t, a) PLUSCC1(T, t, b)
+
+#define INCCC1(T, t, C)	\
+T inccc##t##C (T a, T b)	\
+{	\
+  T sum = a + b;	\
+  if (sum < C)		\
+    c ++;		\
+  return sum;		\
+}
+#define INCCC(T, t) INCCC1(T, t, a) INCCC1(T, t, b)
+
+#define PLUSCCONLY1(T, t, C)	\
+void pluscconly##t##C (T a, T b)	\
+{	\
+  T sum = a + b;	\
+  if (sum < C)		\
+    abort ();		\
+}
+#define PLUSCCONLY(T, t) PLUSCCONLY1(T, t, a) PLUSCCONLY1(T, t, b)
+
+#define MINUSCC(T, t)	\
+T minuscc##t (T a, T b)	\
+{	\
+  T difference = a - b;	\
+  if (difference > a)	\
+    abort ();		\
+  return difference;	\
+}
+
+#define DECCC(T, t)	\
+T deccc##t (T a, T b)	\
+{	\
+  T difference = a - b;	\
+  if (difference > a)	\
+    c --;		\
+  return difference;	\
+}
+
+#define MINUSCCONLY(T, t)	\
+void minuscconly##t (T a, T b)	\
+{	\
+  T difference = a - b;	\
+  if (difference > a)	\
+    abort ();		\
+}
+
+#define TEST(T, t)	\
+  PLUSCC(T, t)		\
+  PLUSCCONLY(T, t)	\
+  INCCC(T, t)		\
+  MINUSCC(T, t)		\
+  MINUSCCONLY(T, t)	\
+  DECCC(T, t)
+
+TEST (unsigned long,  l)
+TEST (unsigned int,   i)
+TEST (unsigned short, s) 
+TEST (unsigned char,  c)
+
+#define PLUSCCZEXT(C)	\
+unsigned long pluscczext##C (unsigned int a, unsigned int b)	\
+{	\
+  unsigned int sum = a + b;	\
+  if (sum < C)		\
+    abort ();		\
+  return sum;		\
+}
+
+PLUSCCZEXT(a)
+PLUSCCZEXT(b)
+
+#define MINUSCCZEXT	\
+unsigned long minuscczext (unsigned int a, unsigned int b)	\
+{	\
+  unsigned int difference = a - b;	\
+  if (difference > a)		\
+    abort ();			\
+  return difference;		\
+}
+
+MINUSCCZEXT
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30413.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30413.c
new file mode 100644
index 000000000..1d3a94f97
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30413.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+int test() {
+  char a, b = -1;
+  asm volatile ("mov%z0 %1, %0" : "=q"(a) : "m"(b));
+  return a;
+}
+
+int main()
+{
+  if (test() != -1)
+    abort();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30505.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30505.c
new file mode 100644
index 000000000..9f8fc4267
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30505.c
@@ -0,0 +1,20 @@
+/* PR inline-asm/30505 */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2" } */
+
+unsigned long long a, c;
+unsigned int b, d;
+
+void
+test ()
+{
+  unsigned int e, f;
+
+  __asm__ ("divl %5;movl %1, %0;movl %4, %1;divl %5"
+	   : "=&rm" (e), "=a" (f), "=d" (d)
+	   : "1" ((unsigned int) (a >> 32)), "g" ((unsigned int) a),
+	     "rm" (b), "2" (0)
+	   : "cc");
+  c = (unsigned long long) e << 32 | f;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30848.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30848.c
new file mode 100644
index 000000000..2a9285151
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30848.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+
+void foo(double d)
+{
+  __asm__ ("" : "=u" (d));  /* { dg-error "output regs" } */
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30961-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30961-1.c
new file mode 100644
index 000000000..c22594335
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30961-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2" } */
+
+double
+convert (long long in)
+{
+  double f;
+  __builtin_memcpy( &f, &in, sizeof( in ) );
+  return f;
+}
+
+/* { dg-final { scan-assembler-not "movapd" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30970.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30970.c
new file mode 100644
index 000000000..96d64e5a9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr30970.c
@@ -0,0 +1,15 @@
+/* { dg-do compile }
+/* { dg-options "-msse2 -O2 -ftree-vectorize" } */
+
+#define N 256
+int b[N];
+
+void test()
+{  
+  int i;
+
+  for (i = 0; i < N; i++)
+    b[i] = 0;
+}
+
+/* { dg-final { scan-assembler-times "pxor" 1 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr31167.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr31167.c
new file mode 100644
index 000000000..aca12130c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr31167.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O" } */
+
+typedef int int32_t;
+
+int32_t round32hi (const __int128_t arg)
+{
+  const int SHIFT = 96;
+  const int mshift = 96;
+  const __int128_t M = (~(__int128_t) 0) << mshift;
+  const __int128_t L = (~M) + 1;
+  const __int128_t L1 = ((__int128_t) L) >> 1;
+  const __int128_t Mlo = ((__int128_t) (~M)) >> 1;
+  __int128_t vv = arg & M;
+
+  if ((arg & (L1)) && ((arg & Mlo) || (arg & L)))
+    vv += L;
+
+  return (int32_t) (vv >> SHIFT);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr31486.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr31486.c
new file mode 100644
index 000000000..7082d3de9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr31486.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-msse -mno-sse2" } */
+
+typedef double __v2df __attribute__ ((vector_size (16)));
+
+__v2df b = { 1.1, 1.2 };
+
+extern __v2df a2 (__v2df a, __v2df b);
+
+void test2 ()
+{
+  b = a2 (b, b);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr31628.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr31628.c
new file mode 100644
index 000000000..121d9c636
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr31628.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fPIC" } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target fpic } */
+
+typedef int tt, *lptt;
+
+int __attribute__((__stdcall__)) bar(lptt);
+
+int __attribute__((__stdcall__)) bar(tt *x)
+{
+  return 0;
+}
+
+int
+foo (void)
+{
+  return bar (0);
+}
+
+int
+main()
+{
+  return foo ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr31854.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr31854.c
new file mode 100644
index 000000000..6fcd20ef0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr31854.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-O -std=gnu99" } */
+
+_Decimal128 d128;
+long double tf;
+
+void foo (void)
+{
+  d128 = tf;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32000-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32000-1.c
new file mode 100644
index 000000000..483d24a76
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32000-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-O -msse2 -std=gnu99" } */
+
+#include "sse2-check.h"
+
+typedef struct { _Decimal128 f __attribute__((packed)); } packed;
+
+_Decimal128 __attribute__((noinline))
+foo (_Decimal128 a1, _Decimal128 a2, _Decimal128 a3, _Decimal128 a4,
+     _Decimal128 a5, _Decimal128 a6, _Decimal128 a7, _Decimal128 a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y)
+{
+  return y.f;
+}
+
+void
+sse2_test (void)
+{
+  packed x;
+  _Decimal128 y = -1;
+  x.f = y;
+  y = foo (0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x.f, sizeof (y)))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32000-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32000-2.c
new file mode 100644
index 000000000..639b121dc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32000-2.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-skip-if "" { ! { ilp32 && dfp } } } */
+/* { dg-options "-O -msse2 -std=gnu99 -mpreferred-stack-boundary=2" } */
+
+#include "sse2-check.h"
+
+typedef struct { _Decimal128 f __attribute__((packed)); } packed;
+
+_Decimal128 __attribute__((noinline))
+foo (_Decimal128 a1, _Decimal128 a2, _Decimal128 a3, _Decimal128 a4,
+     _Decimal128 a5, _Decimal128 a6, _Decimal128 a7, _Decimal128 a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y)
+{
+  return y.f;
+}
+
+void
+sse2_test (void)
+{
+  packed x;
+  _Decimal128 y = -1;
+  x.f = y;
+  y = foo (0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x.f, sizeof (y)))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32065-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32065-1.c
new file mode 100644
index 000000000..eefea27f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32065-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-msse -std=gnu99" } */
+
+_Decimal128 test (void)
+{
+  return 1234123412341234.123412341234dl;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32065-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32065-2.c
new file mode 100644
index 000000000..e1a88592d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32065-2.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-Os -msse -std=gnu99" } */
+
+#include "sse-check.h"
+
+extern void abort (void);
+
+static void
+sse_test (void)
+{
+  if (7.999999999999999999999999999999999E6144dl + 3.0E6144dl
+      != __builtin_infd32 ())
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32191.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32191.c
new file mode 100644
index 000000000..f5238b01d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32191.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-std=c99" } */
+
+typedef _Complex float __attribute__((mode(TC))) _Complex128;
+
+_Complex128 foo (_Complex128 x, _Complex128 y)
+{
+  return x * y;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32268.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32268.c
new file mode 100644
index 000000000..a5d673ad9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32268.c
@@ -0,0 +1,34 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-options "-O2" } */
+
+extern void abort(void);
+
+int __attribute__ ((__noinline__))
+test_lt(__float128 x, __float128 y)
+{
+  return x < y;
+}
+
+int __attribute__ ((__noinline__))
+test_gt (__float128 x, __float128 y)
+{
+  return x > y;
+}
+
+int main()
+{
+  __float128 a = 0.0;
+  __float128 b = 1.0;
+
+  int r;
+
+  r = test_lt (a, b);
+  if (r != ((double) a < (double) b))
+    abort();
+
+  r = test_gt (a, b);
+  if (r != ((double) a > (double) b))
+    abort();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32280.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32280.c
new file mode 100644
index 000000000..d48a635a4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32280.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+
+__m128i foo1(__m128i __a)
+{
+ return (__m128i)__builtin_ia32_pslldqi128 (__a, 8);
+}
+
+__m128i foo2(__m128i __a)
+{
+ return (__m128i)__builtin_ia32_psrldqi128 (__a, 8);
+}
+
+/* { dg-final { scan-assembler "psrldq" } } */
+/* { dg-final { scan-assembler "pslldq" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32389.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32389.c
new file mode 100644
index 000000000..24c27674c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32389.c
@@ -0,0 +1,11 @@
+/* Testcase by Mike Frysinger <vapier@gentoo.org>  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-msse" } */
+
+double f1();
+int f2() {
+  __builtin_ia32_stmxcsr();
+  return f1();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32661-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32661-1.c
new file mode 100644
index 000000000..9411c2887
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32661-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+
+long long foo_0(__m128i* val)
+{
+  return __builtin_ia32_vec_ext_v2di(*val, 0);
+}
+
+long long foo_1(__m128i* val)
+{
+  return __builtin_ia32_vec_ext_v2di(*val, 1);
+}
+
+/* { dg-final { scan-assembler-times "mov" 2 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32661.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32661.c
new file mode 100644
index 000000000..247ae1319
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32661.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef int __v4si __attribute__ ((__vector_size__ (16)));
+typedef float __v4sf __attribute__ ((__vector_size__ (16)));
+
+int fooSI_1(__v4si *val)
+{
+  return __builtin_ia32_vec_ext_v4si(*val, 1);
+}
+/* { dg-final { scan-assembler-not "pshufd" } } */
+
+int fooSI_2(__v4si *val)
+{
+  return __builtin_ia32_vec_ext_v4si(*val, 2);
+}
+/* { dg-final { scan-assembler-not "punpckhdq" } } */
+
+float fooSF_2(__v4sf *val)
+{
+  return __builtin_ia32_vec_ext_v4sf(*val, 2);
+}
+/* { dg-final { scan-assembler-not "unpckhps" } } */
+
+float fooSF_3(__v4sf *val)
+{
+  return __builtin_ia32_vec_ext_v4sf(*val, 3);
+}
+/* { dg-final { scan-assembler-not "shufps" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32708-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32708-1.c
new file mode 100644
index 000000000..c5308937b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32708-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+
+static __inline __m128i __attribute__((__always_inline__))
+_mm_set_epi64x (long long __q1, long long __q0)
+{
+  return __extension__ (__m128i)(__v2di){ __q0, __q1 };
+}
+
+__m128i long2vector(long long __i)
+{
+  return _mm_set_epi64x (0, __i);
+}
+
+/* { dg-final { scan-assembler-not "movq2dq" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32708-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32708-2.c
new file mode 100644
index 000000000..dc31c42a7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32708-2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mtune=k8" } */
+
+typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+
+static __inline __m128i __attribute__((__always_inline__))
+_mm_set_epi64x (long long __q1, long long __q0)
+{
+  return __extension__ (__m128i)(__v2di){ __q0, __q1 };
+}
+
+__m128i long2vector(long long __i)
+{
+  return _mm_set_epi64x (0, __i);
+}
+
+/* { dg-final { scan-assembler-not "movq2dq" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32708-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32708-3.c
new file mode 100644
index 000000000..dae9a52d1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32708-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mtune=core2" } */
+
+typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+
+static __inline __m128i __attribute__((__always_inline__))
+_mm_set_epi64x (long long __q1, long long __q0)
+{
+  return __extension__ (__m128i)(__v2di){ __q0, __q1 };
+}
+
+__m128i long2vector(long long __i)
+{
+  return _mm_set_epi64x (0, __i);
+}
+
+/* { dg-final { scan-assembler-not "movq2dq" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32961.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32961.c
new file mode 100644
index 000000000..a2326289a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr32961.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -msse2" } */
+
+#include <xmmintrin.h>
+
+void x (int n)
+{
+  __m128i a;
+  a = _mm_slli_epi32 (a, n);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33329.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33329.c
new file mode 100644
index 000000000..bb589ee27
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33329.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -msse2" } */
+
+extern void g (int *);
+
+void f (void)
+{
+  int tabs[8], tabcount;
+
+  for (tabcount = 1; tabcount <= 8; tabcount += 7)
+    {
+      int i;
+      for (i = 0; i < 8; i++)
+	tabs[i] = i * 2;
+      g (tabs);
+    }
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33483.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33483.c
new file mode 100644
index 000000000..8fe2a946b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33483.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+long double f1 (long double x)
+{
+  return __builtin_fmodl (x, x);
+}
+
+long double f2 (long double x)
+{
+  return __builtin_remainderl (x, x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33524.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33524.c
new file mode 100644
index 000000000..5b484a207
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33524.c
@@ -0,0 +1,25 @@
+/* Test that the compiler properly optimizes vector SI->DI conversions.  This
+   was a bug in the initial SSE5 code.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
+
+typedef long long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+union {
+  signed   int   si[SIZE];
+  signed   long  sl[SIZE];
+  __m128i        align;
+} a, b;
+
+void conv_sign_int_sign_long (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.sl[i] = b.si[i];
+}
+
+/* { dg-final { scan-assembler "pperm" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33552.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33552.c
new file mode 100644
index 000000000..68a81222e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33552.c
@@ -0,0 +1,41 @@
+/* PR rtl-optimization/33552 */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+void
+__attribute__((noinline))
+foo (unsigned long *wp, unsigned long *up, long un, unsigned long *vp)
+{
+  long j;
+  unsigned long prod_low, prod_high;
+  unsigned long cy_dig;
+  unsigned long v_limb;
+  v_limb = vp[0];
+  cy_dig = 64;
+  for (j = un; j > 0; j--)
+    {
+      unsigned long u_limb, w_limb;
+      u_limb = *up++;
+      __asm__ (""
+               : "=r" (prod_low), "=r" (prod_high)
+               : "0" (u_limb), "1" (v_limb));
+      __asm__ ("mov %5, %1; add %5, %0"
+               : "=r" (cy_dig), "=&r" (w_limb)
+               : "0" (prod_high), "rm" (0), "1" (prod_low), "rm" (cy_dig));
+      *wp++ = w_limb;
+    }
+}
+
+int
+main (void)
+{
+  unsigned long wp[4];
+  unsigned long up[4] = { 0x1248, 0x248a, 0x1745, 0x1853 };
+  unsigned long vp = 0xdead;
+  foo (wp, up, 4, &vp);
+  if (wp[0] != 0x40 || wp[1] != 0xdeed || wp[2] != 0x1bd9a || wp[3] != 0x29c47)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33555.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33555.c
new file mode 100644
index 000000000..21c56b7bd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33555.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "sbbl" } } */
+
+int test(unsigned long a, unsigned long b)
+{
+  return -(a < b);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33600.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33600.c
new file mode 100644
index 000000000..a2ab91e57
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr33600.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+int f(int n)
+{
+        int x;
+
+        asm("" : "=&c"(n), "=r"(x) : "1"(n), "0"(n));
+
+        return n;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34012.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34012.c
new file mode 100644
index 000000000..00b1240d1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34012.c
@@ -0,0 +1,25 @@
+/* PR rtl-optimization/34012 */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2" } */
+
+void bar (long int *);
+void
+foo (void)
+{
+  long int buf[10];
+  buf[0] = 0x0808080808080808;
+  buf[1] = 0x0808080808080808;
+  buf[2] = 0x0808080808080808;
+  buf[3] = 0x0808080808080808;
+  buf[4] = 0x0808080808080808;
+  buf[5] = 0x0808080808080808;
+  buf[6] = 0x0808080808080808;
+  buf[7] = 0x0808080808080808;
+  buf[8] = 0x0808080808080808;
+  buf[9] = 0x0808080808080808;
+  bar (buf);
+}
+
+/* Check that CSE did its job and fwprop hasn't undone it.  */
+/* { dg-final { scan-assembler-times "578721382704613384|0808080808080808" 1 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34077.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34077.c
new file mode 100644
index 000000000..a2ec5d12b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34077.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -minline-all-stringops -minline-stringops-dynamically" } */
+
+#include <string.h>
+
+extern double ran(void);
+
+struct spec_fd_t {
+  int limit;
+  int len;
+  int pos;
+  unsigned char *buf;
+} spec_fd[3];
+
+int spec_random_load (int fd) {
+  int i, j;
+  char random_text[(32)][(128*1024)];
+
+  for (j = 0; j < (128*1024); j++) {
+    random_text[i][j] = (int)(ran()*256);
+  }
+
+  for (i = 0 ; i < spec_fd[fd].limit; i+= (128*1024)) {
+    memcpy(spec_fd[fd].buf + i, random_text[(int)(ran()*(32))],
+	   (128*1024));
+  }
+
+  spec_fd[fd].len = 1024*1024;
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34215.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34215.c
new file mode 100644
index 000000000..9e194ff44
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34215.c
@@ -0,0 +1,19 @@
+/* Testcase by Martin Michlmayr <tbm@cyrius.com> */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2" } */
+
+double pow (double, double);
+
+void calc_score_dist (int mxdlen, long double d, long double **dist)
+{
+  unsigned long i, scr2;
+  for (i = 1; i <= mxdlen; i++)
+    {
+      for (scr2 = mxdlen; scr2 <= mxdlen + 10; scr2++)
+	{
+	}
+      dist[i][scr2] *= pow (1.0 / d, i);
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34256.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34256.c
new file mode 100644
index 000000000..e207ecef7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34256.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -fomit-frame-pointer -march=core2" } */
+
+#include <mmintrin.h>
+
+__m64 x;
+__m64 y;
+
+unsigned long long  foo(__m64 m) {
+  return _mm_cvtm64_si64(_mm_add_pi32(x, y));
+}
+
+/* { dg-final { scan-assembler-times "mov" 2 { target nonpic } } } */
+/* { dg-final { scan-assembler-times "mov" 4 { target { ! nonpic } } } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34312.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34312.c
new file mode 100644
index 000000000..846c28537
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34312.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -march=pentium-m -fpic" } */
+
+typedef struct
+{
+  unsigned char seq[3];
+} JamoNormMap;
+
+static const JamoNormMap *
+JamoClusterSearch (JamoNormMap aKey, const JamoNormMap * aClusters,
+		   short aClustersSize)
+{
+  unsigned short l = 0, u = aClustersSize - 1;
+  unsigned short h = (l + u) / 2;
+
+  if ((aKey.seq[1] - aClusters[h].seq[1]) < 0)
+    return JamoClusterSearch (aKey, &(aClusters[l]), h - l);
+}
+
+short
+JamoSrchReplace (const JamoNormMap * aClusters, unsigned short aClustersSize,
+		 unsigned short * aIn, unsigned int * aLength,
+		 unsigned short aOffset)
+{
+  JamoNormMap key;
+
+  key.seq[0] = 0;
+  key.seq[1] = 1;
+  key.seq[2] = 2;
+
+  JamoClusterSearch (key, aClusters, aClustersSize);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34522.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34522.c
new file mode 100644
index 000000000..c79745bd7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr34522.c
@@ -0,0 +1,13 @@
+/* { dg-options "-O2" } */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+
+int test(long long a, long long b)
+{
+        return a * b;
+}
+
+/* Check that we did not spill anything.  This is all that is needed
+   to qualify the generated code as "decent"...  */
+
+/* { dg-final { scan-assembler-not "%e\[sd\]i" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35083.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35083.c
new file mode 100644
index 000000000..c765d3254
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35083.c
@@ -0,0 +1,8 @@
+/* { dg-options "-O2 -mno-80387" } */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+
+float test (unsigned int x)
+{
+  return (float) x;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35160.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35160.c
new file mode 100644
index 000000000..12394ec6d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35160.c
@@ -0,0 +1,32 @@
+/* PR inline-asm/35160 */
+/* { dg-do run } */
+/* { dg-skip-if "" { ilp32 && { ! nonpic } } { "*" } { "" } } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+void
+__attribute__((noinline))
+foo (unsigned int *y)
+{
+   unsigned int c0, c1, c2, d0, d1, d2;
+   d0 = 0; d1 = 0; d2 = 0; c0 = c1 = c2 = 0;
+
+   __asm__ ("movl $7, %k0; movl $8, %k1; movl $9, %k2"
+	    : "+r" (d0), "+r" (d1), "+r" (d2));
+   __asm__ ("movl %3, %0; movl %4, %1; movl %5, %2"
+	    : "+r" (c0), "+r" (c1), "+r" (c2), "+r" (d0), "+r" (d1), "+r" (d2));
+   y[0] = c0;
+   y[1] = c1;
+   y[2] = c2;
+}
+
+int
+main (void)
+{
+  unsigned int y[3];
+  foo (y);
+  if (y[0] != 7 || y[1] != 8 || y[2] != 9)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35281.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35281.c
new file mode 100644
index 000000000..70e93cbea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35281.c
@@ -0,0 +1,19 @@
+/* { dg-options "-O2" } */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+
+unsigned long long a;
+unsigned int b;
+unsigned short c;
+
+unsigned long long mul32()
+{
+  return a * b;
+}
+
+unsigned long long mul16()
+{
+  return a * c;
+}
+
+/* { dg-final { scan-assembler-not "xor" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35540.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35540.c
new file mode 100644
index 000000000..00af637d0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35540.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+int __attribute__ ((noinline))
+test (unsigned int *a, int b)
+{
+  return b ? 1 : __builtin_parity (*a);
+}
+
+int __attribute__ ((noinline))
+testl (unsigned long *a, int b)
+{
+  return b ? 1 : __builtin_parityl (*a);
+}
+
+int __attribute__ ((noinline))
+testll (unsigned long long *a, int b)
+{
+  return b ? 1 : __builtin_parityll (*a);
+}
+
+int
+main ()
+{
+  unsigned int a = 0;
+  unsigned long al;
+  unsigned long long all;
+
+  a = 0x12345670;
+  if (test (&a, 0))
+    abort ();
+
+  al = 0x12345670ul;
+  if (testl (&al, 0))
+    abort();
+
+#if 1
+  all = 0x12345678abcdef0ull;
+  if (testll (&all, 0))
+    abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35714.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35714.c
new file mode 100644
index 000000000..13ca47c23
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35714.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <emmintrin.h>
+
+extern __m128i a;
+
+__m128i madd (__m128i b)
+{
+  return _mm_madd_epi16(a, b);
+}
+
+__m128i madd_swapped (__m128i b)
+{
+    return _mm_madd_epi16(b, a);
+}
+
+/* { dg-final { scan-assembler-not "movaps" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-1.c
new file mode 100644
index 000000000..5ed5b8588
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+typedef struct { __m128 f __attribute__((packed)); } packed;
+
+__m128  __attribute__((noinline))
+foo (__m128 a1, __m128 a2, __m128 a3, __m128 a4,
+     __m128 a5, __m128 a6, __m128 a7, __m128 a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y)
+{
+  return y.f;
+}
+
+void
+sse2_test (void)
+{
+  packed x;
+  __m128 y = { 0 };
+  x.f = y; 
+  y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x.f, sizeof (y)) != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-1d.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-1d.c
new file mode 100644
index 000000000..cdf17fa61
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-1d.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+typedef struct { __m128d f __attribute__((packed)); } packed;
+
+__m128d  __attribute__((noinline))
+foo (__m128d a1, __m128d a2, __m128d a3, __m128d a4,
+     __m128d a5, __m128d a6, __m128d a7, __m128d a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y)
+{
+  return y.f;
+}
+
+void
+sse2_test (void)
+{
+  packed x;
+  __m128d y = { 0 };
+  x.f = y; 
+  y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x.f, sizeof (y)) != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-1i.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-1i.c
new file mode 100644
index 000000000..188e8e737
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-1i.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+typedef struct { __m128i f __attribute__((packed)); } packed;
+
+__m128i  __attribute__((noinline))
+foo (__m128i a1, __m128i a2, __m128i a3, __m128i a4,
+     __m128i a5, __m128i a6, __m128i a7, __m128i a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y)
+{
+  return y.f;
+}
+
+void
+sse2_test (void)
+{
+  packed x;
+  __m128i y = { 0 };
+  x.f = y; 
+  y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x.f, sizeof (y)) != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-2.c
new file mode 100644
index 000000000..82062ff9e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-2.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+typedef  __m128 __attribute__((aligned(1))) unaligned;
+
+__m128  __attribute__((noinline))
+foo (__m128 a1, __m128 a2, __m128 a3, __m128 a4,
+     __m128 a5, __m128 a6, __m128 a7, __m128 a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, unaligned y)
+{
+  return y;
+}
+
+void
+sse2_test (void)
+{
+  unaligned x;
+  __m128 y = { 0 };
+  x = y; 
+  y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x, sizeof (y)) != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-2d.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-2d.c
new file mode 100644
index 000000000..ae96cd852
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-2d.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+typedef  __m128d __attribute__((aligned(1))) unaligned;
+
+__m128d  __attribute__((noinline))
+foo (__m128d a1, __m128d a2, __m128d a3, __m128d a4,
+     __m128d a5, __m128d a6, __m128d a7, __m128d a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, unaligned y)
+{
+  return y;
+}
+
+void
+sse2_test (void)
+{
+  unaligned x;
+  __m128d y = { 0 };
+  x = y; 
+  y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x, sizeof (y)) != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-2i.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-2i.c
new file mode 100644
index 000000000..d241644b6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-2i.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+typedef  __m128i __attribute__((aligned(1))) unaligned;
+
+__m128i  __attribute__((noinline))
+foo (__m128i a1, __m128i a2, __m128i a3, __m128i a4,
+     __m128i a5, __m128i a6, __m128i a7, __m128i a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, unaligned y)
+{
+  return y;
+}
+
+void
+sse2_test (void)
+{
+  unaligned x;
+  __m128i y = { 0 };
+  x = y; 
+  y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x, sizeof (y)) != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-3.c
new file mode 100644
index 000000000..e7592ff7b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-3.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-O -msse2 -std=gnu99" } */
+
+#include "sse2-check.h"
+
+typedef _Decimal128 unaligned __attribute__((aligned(1)));
+
+_Decimal128 __attribute__((noinline))
+foo (_Decimal128 a1, _Decimal128 a2, _Decimal128 a3, _Decimal128 a4,
+     _Decimal128 a5, _Decimal128 a6, _Decimal128 a7, _Decimal128 a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, unaligned y)
+{
+  return y;
+}
+
+void
+sse2_test (void)
+{
+  unaligned x;
+  _Decimal128 y = -1;
+  x = y;
+  y = foo (0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x, sizeof (y)))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-4.c
new file mode 100644
index 000000000..e12f64ffe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-4.c
@@ -0,0 +1,14 @@
+/* Test that we generate aligned load when memory is aligned.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-O -march=x86-64 -mtune=generic -std=gnu99" } */
+/* { dg-final { scan-assembler-not "movdqu" } } */
+/* { dg-final { scan-assembler "movdqa" } } */
+
+extern _Decimal128 foo (_Decimal128, _Decimal128, _Decimal128);
+
+void
+bar (void)
+{
+  foo (0, 0, 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-5.c
new file mode 100644
index 000000000..4372d2e57
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr35767-5.c
@@ -0,0 +1,17 @@
+/* Test that we generate aligned load when memory is aligned.  */
+/* { dg-do compile } */
+/* { dg-options "-O -msse2 -mtune=generic" } */
+/* { dg-final { scan-assembler-not "movups" } } */
+/* { dg-final { scan-assembler "movaps" } } */
+
+typedef float v4sf __attribute__ ((__vector_size__ (16)));
+
+extern void foo(v4sf, v4sf, v4sf, v4sf, v4sf, v4sf, v4sf, v4sf, v4sf);
+
+int test(void)
+{
+  v4sf x = { 0.0, 1.0, 2.0, 3.0 };
+
+  foo (x, x, x, x, x, x, x, x, x);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36064.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36064.c
new file mode 100644
index 000000000..7964f280c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36064.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O1 -march=core2" } */
+
+typedef long long ogg_int64_t;
+
+typedef struct vorbis_info
+{
+  long rate;
+} vorbis_info;
+
+typedef struct OggVorbis_File
+{
+  int seekable;
+  int links;
+  ogg_int64_t *pcmlengths;
+  vorbis_info *vi;
+  int ready_state;
+} OggVorbis_File;
+
+extern double ov_time_total (OggVorbis_File * vf, int i);
+extern int ov_pcm_seek_page (OggVorbis_File * vf, ogg_int64_t pos);
+
+int
+ov_time_seek_page (OggVorbis_File * vf, double seconds)
+{
+  int link = -1;
+  ogg_int64_t pcm_total = 0;
+  double time_total = 0.;
+
+  if (vf->ready_state < 2)
+    return (-131);
+  if (!vf->seekable)
+    return (-138);
+  if (seconds < 0)
+    return (-131);
+
+  for (link = 0; link < vf->links; link++)
+    {
+      double addsec = ov_time_total (vf, link);
+      if (seconds < time_total + addsec)
+	break;
+      time_total += addsec;
+      pcm_total += vf->pcmlengths[link * 2 + 1];
+    }
+
+  if (link == vf->links)
+    return (-131);
+
+  {
+    ogg_int64_t target =
+      pcm_total + (seconds - time_total) * vf->vi[link].rate;
+    return (ov_pcm_seek_page (vf, target));
+  }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36073.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36073.c
new file mode 100644
index 000000000..b1587579e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36073.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O -march=core2 -mfpmath=sse,387 -ffast-math" } */
+
+extern double log (double x);
+extern int f (void);
+
+double cached_value;
+
+void g (void)
+{
+  cached_value = log (f ());
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36222-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36222-1.c
new file mode 100644
index 000000000..2d4c5b9b7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36222-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef int __v4si __attribute__ ((__vector_size__ (16)));
+
+__m128i _mm_set_epi32 (int __q3, int __q2, int __q1, int __q0)
+{
+  return (__m128i)(__v4si){ __q0, __q1, __q2, __q3 };
+}
+
+/* { dg-final { scan-assembler-not "movdqa" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36246.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36246.c
new file mode 100644
index 000000000..4f3e155cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36246.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -fomit-frame-pointer -mtune=generic" } */
+
+typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef int __v4si __attribute__ ((__vector_size__ (16)));
+
+__m128i
+_mm_set_epi32 (int __q3, int __q2, int __q1, int __q0)
+{
+  return (__m128i)(__v4si){ __q0, __q1, __q2, __q3 };
+}
+
+/* { dg-final { scan-assembler-not "movq" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36438.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36438.c
new file mode 100644
index 000000000..38376b8c9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36438.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmmx" } */
+
+#include <mmintrin.h>
+
+extern __m64 SetS16 (unsigned short, unsigned short,
+		     unsigned short, unsigned short);
+
+void foo(__m64* dest)
+{
+  __m64 mask = SetS16 (0x00FF, 0xFF00, 0x0000, 0x00FF);
+
+  mask = _mm_slli_si64(mask, 8);
+  mask = _mm_slli_si64(mask, 8);
+
+  *dest = mask;
+
+  _mm_empty ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36533.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36533.c
new file mode 100644
index 000000000..a271fea1c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36533.c
@@ -0,0 +1,174 @@
+/* PR target/36533 */
+/* { dg-do run { target { { i?86-*-linux* x86_64-*-linux* } && ilp32 } } } */
+/* { dg-options "-Os" } */
+#include <string.h>
+#include <sys/mman.h>
+#ifndef MAP_ANONYMOUS
+#define MAP_ANONYMOUS MAP_ANON
+#endif
+
+typedef struct S1
+{
+  unsigned long s1;
+  struct S1 *s2;
+  char *s3;
+} S1;
+
+typedef struct
+{
+  unsigned int s4;
+  unsigned int s5;
+  int s6;
+  unsigned int *s7;
+} S2;
+
+typedef struct
+{
+  unsigned int s8;
+  unsigned short s9;
+  unsigned char s10;
+  unsigned char s11;
+  char s12[255];
+} S3;
+
+typedef struct
+{
+  unsigned int s4;
+  unsigned short s13;
+  unsigned short s14;
+} S4;
+
+typedef struct
+{
+  char s15[16];
+  unsigned long s16;
+} S5;
+
+typedef struct
+{
+  char s15[48];
+  S5 *s17;
+} S6;
+
+typedef struct
+{
+  S1 *s18;
+} S7;
+
+__attribute__((regparm (3), noinline)) int
+fn1 (const char *x, void *y, S1 *z)
+{
+  asm volatile ("" : : : "memory");
+  return *x + (y != 0);
+}
+
+__attribute__((regparm (3), noinline)) int
+fn2 (const char *x, int y, S2 *z)
+{
+  asm volatile ("" : : : "memory");
+  return 0;
+}
+
+static inline __attribute__ ((always_inline)) unsigned int
+fn4 (unsigned short x)
+{
+  unsigned len = x;
+  if (len == ((1 << 16) - 1))
+    return 1 << 16;
+  return len;
+}
+
+static inline __attribute__ ((always_inline)) S3 *
+fn3 (S3 *p)
+{
+  return (S3 *) ((char *) p + fn4 (p->s9));
+}
+
+__attribute__((regparm (3), noinline)) int
+fn5 (void)
+{
+  asm volatile ("" : : : "memory");
+  return 0;
+}
+
+static inline __attribute__ ((always_inline)) int
+fn6 (S3 *w, int x, S2 *y, S4 *z)
+{
+  int a = 2;
+  char *b = (char *) w;
+  S2 c = *y;
+
+  while ((char *) w < b + x - 2 * sizeof (S4))
+    {
+      if (w->s10 && w->s8)
+	{
+	  fn2 (w->s12, w->s10, &c);
+	  z--;
+	  z->s4 = c.s4;
+	  z->s13 = (unsigned short) ((char *) w - b);
+	  z->s14 = w->s9;
+	  a++;
+	  fn5 ();
+	}
+
+      w = fn3 (w);
+    }
+  return a;
+}
+
+__attribute__((regparm (3), noinline)) unsigned int
+test (void *u, S6 *v, S1 **w, S7 *x, S2 *y, S1 *z)
+{
+  unsigned b = v->s17->s16;
+  unsigned a;
+  S4 *c;
+  unsigned d, e, f, i;
+
+  fn1 (__func__, u, x->s18);
+  c = (S4 *) (z->s3 + b);
+  a = fn6 ((S3 *) (*w)->s3, b, y, c);
+  c -= a;
+  f = 0;
+  e = 2;
+  for (i = a - 1; ; i--)
+    {
+      if (f + (unsigned short) (c[i].s14 / 2) > b / 2)
+	break;
+      f += c[i].s14;
+      e++;
+    }
+  d = a - e;
+  return c[d].s4;
+}
+
+int main (void)
+{
+  char *p = mmap (NULL, 131072, PROT_READ | PROT_WRITE,
+		  MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+  S1 wb, z, *w;
+  S6 v;
+  S7 x;
+  S2 y;
+  S5 vb;
+  S4 s4;
+  if (p == MAP_FAILED)
+    return 0;
+  if (munmap (p + 65536, 65536) < 0)
+    return 0;
+  memset (&wb, 0, sizeof (wb));
+  memset (&z, 0, sizeof (z));
+  memset (&v, 0, sizeof (v));
+  memset (&x, 0, sizeof (x));
+  memset (&y, 0, sizeof (y));
+  memset (&vb, 0, sizeof (vb));
+  memset (&s4, 0, sizeof (s4));
+  s4.s14 = 254;
+  z.s3 = p + 65536 - 2 * sizeof (S4);
+  w = &wb;
+  v.s17 = &vb;
+  vb.s16 = 2 * sizeof (S4);
+  memcpy (z.s3, &s4, sizeof (s4));
+  memcpy (z.s3 + sizeof (s4), &s4, sizeof (s4));
+  test ((void *) 0, &v, &w, &x, &y, &z);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36578-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36578-1.c
new file mode 100644
index 000000000..cae0d7088
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36578-1.c
@@ -0,0 +1,22 @@
+/* Test for unsafe floating-point conversions.  PR 36578.  */
+/* { dg-do run } */
+/* { dg-options "-msse2 -mfpmath=sse" } */
+
+#include "sse2-check.h"
+
+extern void abort (void);
+extern void exit (int);
+extern int printf(const char *, ...);
+
+volatile double d1 = 1.0;
+volatile double d2 = 0x1.00001p-53;
+volatile double d3;
+
+static void
+sse2_test (void)
+{
+  d3 = (double)((long double)d1 + (long double)d2);
+  if (d3 != d1)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36578-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36578-2.c
new file mode 100644
index 000000000..19143cfe5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36578-2.c
@@ -0,0 +1,23 @@
+/* Test for unsafe floating-point conversions.  */
+/* { dg-do run } */
+/* { dg-options "-msse2 -mfpmath=sse" } */
+
+#include "sse2-check.h"
+
+extern void abort (void);
+extern void exit (int);
+extern int printf(const char *, ...);
+
+volatile double d1 = 0x1.000001p0;
+volatile double d2 = 0x1p-54;
+volatile float f = 0x1.000002p0f;
+volatile float f2;
+
+static void
+sse2_test (void)
+{
+  f2 = (float)((long double)d1 + (long double)d2);
+  if (f != f2)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36613.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36613.c
new file mode 100644
index 000000000..e9d7d11ce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36613.c
@@ -0,0 +1,44 @@
+/* { dg-do run { target { { i?86-*-linux* x86_64-*-linux* } && ilp32 } } } */
+/* { dg-options "-Os" } */
+/* PR target/36613 */
+
+extern void abort (void);
+
+static inline int
+lshifts (int val, int cnt)
+{
+  if (val < 0)
+    return val;
+  return val << cnt;
+}
+
+static inline unsigned int
+lshiftu (unsigned int val, unsigned int cnt)
+{
+  if (cnt >= sizeof (unsigned int) * __CHAR_BIT__
+      || val > ((__INT_MAX__ * 2U) >> cnt))
+    return val;
+  return val << cnt;
+}
+
+static inline int
+rshifts (int val, unsigned int cnt)
+{
+  if (val < 0 || cnt >= sizeof (int) * __CHAR_BIT__)
+    return val;
+  return val >> cnt;
+}
+
+int
+foo (unsigned int val)
+{
+  return rshifts (1 + val, lshifts (lshiftu (val, val), 1));
+}
+
+int
+main (void)
+{
+  if (foo (1) != 0)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36753.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36753.c
new file mode 100644
index 000000000..2d43d42a0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36753.c
@@ -0,0 +1,31 @@
+/* { dg-options "-O2" } */
+/* { dg-do run } */
+
+#if defined __i386__
+#define REG "edi"
+#else
+#define REG "r14"
+#endif
+
+register unsigned long *ds asm(REG);
+
+extern void abort (void);
+
+__attribute__ ((noinline)) void
+test (void)
+{
+  *++ds = 31337;
+}
+
+int
+main ()
+{
+  unsigned long stack[2];
+  stack[0] = 0;
+  stack[1] = 0;
+  ds = stack;
+  test ();
+  if (ds != stack + 1 || *ds != 31337)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36786.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36786.c
new file mode 100644
index 000000000..692518e1b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36786.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+
+typedef int DItype __attribute__ ((mode (DI)));
+typedef unsigned int UDItype __attribute__ ((mode (DI)));
+typedef int TItype __attribute__ ((mode (TI)));
+
+__floattisf (TItype u)
+{
+  DItype hi = u >> (8 * 8);
+  UDItype count, shift;
+  hi = u >> shift;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36992-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36992-1.c
new file mode 100644
index 000000000..7cd24cccf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36992-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile }
+/* { dg-options "-O2 -msse2" } */
+
+#include <emmintrin.h>
+
+__m128i
+test (__m128i b)
+{
+  return _mm_move_epi64 (b);
+}
+
+/* { dg-final { scan-assembler-times "movq\[ \\t\]+.*%xmm" 1 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36992-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36992-2.c
new file mode 100644
index 000000000..17696a5b2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr36992-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile }
+/* { dg-options "-O2 -msse4" } */
+
+#include <emmintrin.h>
+
+__m128i
+test (__m128i b)
+{
+  return _mm_move_epi64 (b);
+}
+
+/* { dg-final { scan-assembler-times "movq\[ \\t\]+.*%xmm" 1 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37101.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37101.c
new file mode 100644
index 000000000..8fd3bfc5f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37101.c
@@ -0,0 +1,64 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -ftree-vectorize -march=nocona" } */
+
+typedef __SIZE_TYPE__ size_t;
+extern void *malloc (size_t);
+extern void free (void *);
+
+typedef struct _Resource
+{
+  struct _Resource *next;
+  unsigned int id;
+} ResourceRec, *ResourcePtr;
+
+typedef struct _ClientResource
+{
+  ResourcePtr *resources;
+  int elements;
+  int buckets;
+  int hashsize;
+} ClientResourceRec;
+
+static ClientResourceRec clientTable[256];
+
+void
+RebuildTable (int client)
+{
+  int j;
+  ResourcePtr res, next;
+  ResourcePtr **tails, *resources;
+  ResourcePtr **tptr, *rptr;
+
+  j = 2 * clientTable[client].buckets;
+
+  tails =
+    (ResourcePtr **) malloc ((unsigned long) (j * sizeof (ResourcePtr *)));
+  resources =
+    (ResourcePtr *) malloc ((unsigned long) (j * sizeof (ResourcePtr)));
+
+  for (rptr = resources, tptr = tails; --j >= 0; rptr++, tptr++)
+    {
+      *rptr = ((ResourcePtr) ((void *) 0));
+      *tptr = rptr;
+    }
+
+  clientTable[client].hashsize++;
+  for (j = clientTable[client].buckets,
+       rptr = clientTable[client].resources; --j >= 0; rptr++)
+    {
+      for (res = *rptr; res; res = next)
+	{
+	  next = res->next;
+	  res->next = ((ResourcePtr) ((void *) 0));
+	  tptr = &tails[Hash (client, res->id)];
+	  **tptr = res;
+	  *tptr = &res->next;
+	}
+    }
+  free ((void *) tails);
+  clientTable[client].buckets *= 2;
+  free ((void *) clientTable[client].resources);
+  clientTable[client].resources = resources;
+}
+
+/* { dg-final { scan-assembler-not "movlps" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37184.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37184.c
new file mode 100644
index 000000000..14e11f707
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37184.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O1" } */
+
+static inline unsigned int
+rshift_u_s (unsigned int left, int right)
+{
+  return left >> right;
+}
+
+unsigned int g_15;
+
+int func_29 (int p_30)
+{
+  unsigned int l_31;
+  unsigned long long int l_35 = 0x7736EAE11771B705LL;
+  unsigned int l_36 = 0xEDB553A8L;
+
+  l_31 = g_15;
+  if ((l_31 <
+       (rshift_u_s ((g_15 - (g_15 >= l_35)), (l_36 <= 1)))) + mod_rhs (1))
+    return 1;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37191.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37191.c
new file mode 100644
index 000000000..b7b65df12
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37191.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -mmmx" } */
+
+#include <mmintrin.h>
+#include <stddef.h>
+#include <stdint.h>
+
+extern const uint64_t ff_bone;
+
+static inline void transpose4x4(uint8_t *dst, uint8_t *src, ptrdiff_t dst_stride, ptrdiff_t src_stride) {
+    __m64 row0 = _mm_cvtsi32_si64(*(unsigned*)(src + (0 * src_stride)));
+    __m64 row1 = _mm_cvtsi32_si64(*(unsigned*)(src + (1 * src_stride)));
+    __m64 row2 = _mm_cvtsi32_si64(*(unsigned*)(src + (2 * src_stride)));
+    __m64 row3 = _mm_cvtsi32_si64(*(unsigned*)(src + (3 * src_stride)));
+    __m64 tmp0 = _mm_unpacklo_pi8(row0, row1);
+    __m64 tmp1 = _mm_unpacklo_pi8(row2, row3);
+    __m64 row01 = _mm_unpacklo_pi16(tmp0, tmp1);
+    __m64 row23 = _mm_unpackhi_pi16(tmp0, tmp1);
+    *((unsigned*)(dst + (0 * dst_stride))) = _mm_cvtsi64_si32(row01);
+    *((unsigned*)(dst + (1 * dst_stride))) = _mm_cvtsi64_si32(_mm_unpackhi_pi32(row01, row01));
+    *((unsigned*)(dst + (2 * dst_stride))) = _mm_cvtsi64_si32(row23);
+    *((unsigned*)(dst + (3 * dst_stride))) = _mm_cvtsi64_si32(_mm_unpackhi_pi32(row23, row23));
+}
+
+static inline void h264_loop_filter_chroma_intra_mmx2(uint8_t *pix, int stride, int alpha1, int beta1)
+{
+    asm volatile(
+        ""
+        :: "r"(pix-2*stride), "r"(pix), "r"((long)stride),
+           "m"(alpha1), "m"(beta1), "m"(ff_bone)
+    );
+}
+
+void h264_h_loop_filter_chroma_intra_mmx2(uint8_t *pix, int stride, int alpha, int beta)
+{
+
+    uint8_t trans[8*4] __attribute__ ((aligned (8)));
+    transpose4x4(trans, pix-2, 8, stride);
+    transpose4x4(trans+4, pix-2+4*stride, 8, stride);
+    h264_loop_filter_chroma_intra_mmx2(trans+2*8, 8, alpha-1, beta-1);
+    transpose4x4(pix-2, trans, stride, 8);
+    transpose4x4(pix-2+4*stride, trans+4, stride, 8);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37197.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37197.c
new file mode 100644
index 000000000..95565e802
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37197.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse4" } */
+
+int testl (unsigned long *a, int b)
+{
+  return b ? 1 : __builtin_parityl (*a);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37248-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37248-1.c
new file mode 100644
index 000000000..c87379508
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37248-1.c
@@ -0,0 +1,19 @@
+/* PR middle-end/37248 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-optimized" } */
+
+struct S
+{
+  unsigned char a : 1;
+  unsigned char b : 1;
+  unsigned char c : 1;
+} s;
+
+int
+foo (struct S x)
+{
+  return x.a && x.b && x.c;
+}
+
+/* { dg-final { scan-tree-dump "& 7\[^\n\t\]*== 7" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37248-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37248-2.c
new file mode 100644
index 000000000..ba50e96bc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37248-2.c
@@ -0,0 +1,23 @@
+/* PR middle-end/37248 */
+/* { dg-do compile { target { ! default_packed } } } */
+/* { dg-options "-O2 -fdump-tree-optimized" } */
+
+struct S
+{
+  unsigned char a : 1;
+  unsigned char b : 1;
+  unsigned char c : 1;
+  unsigned int d : 26;
+  unsigned char e : 1;
+  unsigned char f : 1;
+  unsigned char g : 1;
+} s;
+
+int
+foo (struct S x)
+{
+  return x.a && x.g && x.b && x.f && x.c && x.e;
+}
+
+/* { dg-final { scan-tree-dump "& (3758096391|0x0e0000007)\[^\n\t\]*== (3758096391|0x0e0000007)" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37248-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37248-3.c
new file mode 100644
index 000000000..b757855c8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37248-3.c
@@ -0,0 +1,25 @@
+/* PR middle-end/37248 */
+/* { dg-do compile { target { ! default_packed } } } */
+/* { dg-options "-O2 -fdump-tree-optimized -mno-ms-bitfields" } */
+
+struct S
+{
+  unsigned char a : 1;
+  unsigned char b : 1;
+  unsigned char c : 1;
+  unsigned int d : 6;
+  unsigned int e : 14;
+  unsigned int f : 6;
+  unsigned char g : 1;
+  unsigned char h : 1;
+  unsigned char i : 1;
+} s;
+
+int
+foo (struct S x)
+{
+  return x.a && x.i && x.b && x.h && x.c && x.g && x.e == 131;
+}
+
+/* { dg-final { scan-tree-dump "& (3766484487|0x0e07ffe07)\[^\n\t\]*== (3758163463|0x0e0010607)" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37275.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37275.c
new file mode 100644
index 000000000..ca9612bba
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37275.c
@@ -0,0 +1,137 @@
+/* PR middle-end/37275 */
+/* { dg-do compile { target ilp32 } } */
+/* { dg-options "-g -dA -O2 -march=i686 -fstack-protector" } */
+
+typedef __SIZE_TYPE__ size_t;
+extern void *memcpy (void *, const void *, size_t);
+extern void *malloc (size_t);
+
+typedef int A;
+
+struct B
+{
+  int x;
+};
+
+struct C
+{
+  struct F *c1;
+  void *c2;
+};
+
+enum D
+{
+  D0,
+  D1
+};
+
+struct E
+{
+  struct E *e1;
+  struct E *e2;
+  struct B e3;
+  void (*fn) (void *);
+  void *fn_data;
+  enum D e4;
+  _Bool e5;
+  _Bool e6;
+};
+
+struct F
+{
+  unsigned f1;
+  A f2;
+  int f3;
+};
+
+struct G
+{
+  void (*fn) (void *data);
+  void *data;
+  struct C g1;
+  struct E *t;
+};
+
+extern void fn1 (A * m);
+static inline void
+fn2 (A *x)
+{
+  if (!__sync_bool_compare_and_swap (x, 0, 1))
+    fn1 (x);
+}
+
+extern __thread struct G thr __attribute__ ((visibility ("hidden")));
+static inline struct G *
+fn3 (void)
+{
+  return &thr;
+}
+
+extern struct B *fn4 (void);
+extern struct B a;
+
+static inline struct B *
+fn5 (_Bool x)
+{
+  struct E *t = fn3 ()->t;
+  if (t)
+    return &t->e3;
+  else if (x)
+    return fn4 ();
+  else
+    return &a;
+}
+
+void
+fn6 (struct E *t, struct E *e1_t,
+		struct B *prev_e3)
+{
+  t->e1 = e1_t;
+  t->e3 = *prev_e3;
+  t->e4 = D0;
+  t->e5 = 0;
+  t->e6 = 0;
+  t->e2 = ((void *) 0);
+}
+
+void
+test (void (*fn) (void *), void *data, void (*cpyfn) (void *, void *), long x, long y, _Bool z)
+{
+  struct G *thr = fn3 ();
+  struct F *c1 = thr->g1.c1;
+  if (!z || c1 == 0 || (unsigned) c1->f3 > 64 * c1->f1)
+    {
+      struct E t;
+
+      fn6 (&t, thr->t, fn5 (0));
+      if (thr->t)
+	t.e6 = thr->t->e6;
+      thr->t = &t;
+      if (__builtin_expect (cpyfn != ((void *) 0), 0))
+	{
+	  char buf[x + y - 1];
+	  char *arg = (char *) (((unsigned long) buf + y - 1)
+				& ~(unsigned long) (y - 1));
+	  cpyfn (arg, data);
+	  fn (arg);
+	}
+    }
+  else
+    {
+      struct E *t;
+      struct E *e1 = thr->t;
+      char *arg;
+
+      t = malloc (sizeof (*t) + x + y - 1);
+      arg = (char *) (((unsigned long) (t + 1) + y - 1)
+		      & ~(unsigned long) (y - 1));
+      fn6 (t, e1, fn5 (0));
+      thr->t = t;
+      if (cpyfn)
+	cpyfn (arg, data);
+      else
+	memcpy (arg, data, x);
+      thr->t = e1;
+      fn2 (&c1->f2);
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37434-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37434-1.c
new file mode 100644
index 000000000..b556bf084
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37434-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef short __v8hi __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+__m128i Set_AC4R_SETUP_I( const short *val ) {
+  short D2073 = *val;
+  short D2076 = *(val + 2);
+  short D2079 = *(val + 4);
+  __v8hi D2094 = {D2073, D2076, D2079, 0, D2073, D2076, D2079, 0};
+  return (__m128i)D2094;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37434-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37434-2.c
new file mode 100644
index 000000000..00ff9fd2e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37434-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=core2 -msse2" } */
+
+typedef short __v8hi __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+__m128i Set_AC4R_SETUP_I( const short *val ) {
+  short D2073 = *val;
+  short D2076 = *(val + 2);
+  short D2079 = *(val + 4);
+  __v8hi D2094 = {D2073, D2076, D2079, 0, D2073, D2076, D2079, 0};
+  return (__m128i)D2094;
+}
+
+/* { dg-final { scan-assembler "pinsrw" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37434-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37434-3.c
new file mode 100644
index 000000000..916c99fe0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37434-3.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+typedef char __v16qi __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+__m128i Set_AC4R_SETUP_I( const char *val ) {
+  char D2073 = *val;
+  char D2074 = *(val + 1);
+  char D2075 = *(val + 2);
+  char D2076 = *(val + 3);
+  char D2077 = *(val + 4);
+  char D2078 = *(val + 5);
+  char D2079 = *(val + 6);
+  __v16qi D2094 = {D2073, D2074, D2075, D2076,  D2077, D2078, D2079, 0,
+  D2073, D2074, D2075, D2076,  D2077, D2078, D2079, 0};
+  return (__m128i)D2094;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37434-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37434-4.c
new file mode 100644
index 000000000..15f8292b0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37434-4.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -mtune=core2 -msse4.1" } */
+
+typedef char __v16qi __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+__m128i Set_AC4R_SETUP_I( const char *val ) {
+  char D2073 = *val;
+  char D2074 = *(val + 1);
+  char D2075 = *(val + 2);
+  char D2076 = *(val + 3);
+  char D2077 = *(val + 4);
+  char D2078 = *(val + 5);
+  char D2079 = *(val + 6);
+  __v16qi D2094 = {D2073, D2074, D2075, D2076,  D2077, D2078, D2079, 0,
+  D2073, D2074, D2075, D2076,  D2077, D2078, D2079, 0};
+  return (__m128i)D2094;
+}
+
+/* { dg-final { scan-assembler "pinsrb" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37843-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37843-1.c
new file mode 100644
index 000000000..e37ea9df2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37843-1.c
@@ -0,0 +1,13 @@
+/* Test for stack alignment with sibcall optimization.  */
+/* { dg-do compile { target nonpic } } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=5" } */
+/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-final { scan-assembler "call\[\\t \]*foo" } } */
+/* { dg-final { scan-assembler-not "jmp\[\\t \]*foo" } } */
+
+extern int foo (void);
+
+int bar (void)
+{
+    return foo();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37843-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37843-2.c
new file mode 100644
index 000000000..e36cb0d95
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37843-2.c
@@ -0,0 +1,13 @@
+/* Test for stack alignment with sibcall optimization.  */
+/* { dg-do compile { target nonpic } } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=6" } */
+/* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*foo" } } */
+/* { dg-final { scan-assembler "jmp\[\\t \]*foo" } } */
+
+extern int foo (void);
+
+int bar (void)
+{
+    return foo();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37843-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37843-3.c
new file mode 100644
index 000000000..a475e4143
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37843-3.c
@@ -0,0 +1,15 @@
+/* Test for stack alignment with sibcall optimization.  */
+/* { dg-do compile { target { ilp32 && nonpic } } } */
+/* { dg-options "-O2 -msse2 -mpreferred-stack-boundary=4 -mstackrealign" } */
+/* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*foo" } } */
+/* { dg-final { scan-assembler "jmp\[\\t \]*foo" } } */
+
+#include <emmintrin.h>
+
+extern int foo (__m128, __m128, __m128, __m128);
+
+int bar (__m128 x1, __m128 x2, __m128 x3, __m128 x4)
+{
+    return foo (x1, x2, x3, x4);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37870.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37870.c
new file mode 100644
index 000000000..19cfb2058
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr37870.c
@@ -0,0 +1,29 @@
+/* PR middle-end/37870 */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+unsigned int
+foo (long double x)
+{
+  struct { char a[8]; unsigned int b:7; } c;
+  __builtin_memcpy (&c, &x, sizeof (c));
+  return c.b;
+}
+
+unsigned int
+bar (long double x)
+{
+  union { struct { char a[8]; unsigned int b:7; } c; long double d; } u;
+  u.d = x;
+  return u.c.b;
+}
+
+int
+main (void)
+{
+  if (foo (1.245L) != bar (1.245L)
+      || foo (245.67L) != bar (245.67L)
+      || foo (0.00567L) != bar (0.00567L))
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr38151-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr38151-1.c
new file mode 100644
index 000000000..6500a5029
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr38151-1.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+void abort (void);
+
+struct S2848
+{
+  unsigned int a;
+  _Complex int b;
+};
+
+struct S2848 s2848;
+
+void __attribute__((noinline))
+check2848 (struct S2848 arg0)
+{
+  if (arg0.b != s2848.b)
+    abort ();
+}
+
+int main()
+{
+  s2848.a = 4027477739U;
+  s2848.b = (723419448 + -218144346 * __extension__ 1i);
+
+  check2848 (s2848);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr38240.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr38240.c
new file mode 100644
index 000000000..6a3568754
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr38240.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+
+typedef float V
+  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+V __attribute__((target("sse"))) f(const V *ptr) { return *ptr; }
+
+V g(const V *ptr) { return *ptr; }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr38824.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr38824.c
new file mode 100644
index 000000000..637abfde8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr38824.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse" } */
+
+typedef float v4sf __attribute__ ((__vector_size__ (16)));
+
+void bench_1(float * out, float * in, float f, unsigned int n)
+{
+    n /= 4;
+    v4sf scalar = { f, f, f, f };
+    do
+    {
+        v4sf arg = *(v4sf *)in;
+        v4sf result = arg + scalar;
+        *(v4sf *) out = result;
+        in += 4;
+        out += 4;
+    }
+    while (--n);
+}
+
+/* { dg-final { scan-assembler-not "addps\[^\\n\]*%\[er\]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr38931.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr38931.c
new file mode 100644
index 000000000..dd35dec75
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr38931.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse" } */
+
+typedef int __m64 __attribute__ ((__vector_size__ (8)));
+
+extern __m64 foo () ;
+
+void bar (const int input_bpl, const unsigned char *input,
+	  unsigned char *output, unsigned long x1)
+{
+  unsigned char *pix_end_ptr = output + x1 * 4;
+  __m64 m_original = { 0, 0 };
+  __m64 m_base_addr = __builtin_ia32_vec_init_v2si (0, input_bpl);
+  __m64 m_addr = __builtin_ia32_paddd (m_original, m_base_addr);
+  __m64 *a0 = (__m64 *) input;
+
+  for (; output < pix_end_ptr; output += 4)
+    {
+      a0 = (__m64 *) (input + __builtin_ia32_vec_ext_v2si (m_addr, 0));
+      m_addr = foo ();
+      __builtin_prefetch (a0, 0);
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr38988.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr38988.c
new file mode 100644
index 000000000..8e2c8eaa6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr38988.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -fpic -mcmodel=large" } */
+
+typedef long unsigned int size_t;
+typedef void (*func_ptr) (void);
+
+static func_ptr __DTOR_LIST__[1] = { (func_ptr) (-1) };
+
+void
+__do_global_dtors_aux (void)
+{
+  extern func_ptr __DTOR_END__[];
+  size_t dtor_idx = 0;
+  const size_t max_idx = __DTOR_END__ - __DTOR_LIST__ - 1;
+  func_ptr f;
+
+  while (dtor_idx < max_idx)
+    {
+      f = __DTOR_LIST__[++dtor_idx];
+      f ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39013-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39013-1.c
new file mode 100644
index 000000000..25f02fcdb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39013-1.c
@@ -0,0 +1,15 @@
+/* PR target/39013 */
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-options "-O2 -fpie -std=gnu89" } */
+
+inline int foo (void);
+extern inline int bar (void);
+
+int
+main (void)
+{
+  return foo () + bar ();
+}
+
+/* { dg-final { scan-assembler "foo@PLT" } } */
+/* { dg-final { scan-assembler "bar@PLT" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39013-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39013-2.c
new file mode 100644
index 000000000..615d54900
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39013-2.c
@@ -0,0 +1,15 @@
+/* PR target/39013 */
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-options "-O2 -fpie -std=gnu99" } */
+
+inline int foo (void);		/* { dg-warning "declared but never defined" } */
+extern inline int bar (void);	/* { dg-warning "declared but never defined" } */
+
+int
+main (void)
+{
+  return foo () + bar ();
+}
+
+/* { dg-final { scan-assembler "foo@PLT" } } */
+/* { dg-final { scan-assembler "bar@PLT" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39058.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39058.c
new file mode 100644
index 000000000..2982e8d14
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39058.c
@@ -0,0 +1,34 @@
+/* PR inline-asm/39058 */
+/* { dg-options "-O2" } */
+
+double
+f1 ()
+{
+  double x;
+  asm ("" : "=r,r" (x) : "0,0" (x));
+  return x;
+}
+
+double
+f2 ()
+{
+  double x;
+  asm ("" : "=r" (x) : "0" (x));
+  return x;
+}
+
+double
+f3 ()
+{
+  double x, y;
+  asm ("" : "=r,r" (x), "=r,r" (y) : "%0,0" (x), "r,r" (0));
+  return x;
+}
+
+double
+f4 ()
+{
+  double x, y;
+  asm ("" : "=r" (x), "=r" (y) : "0" (x), "r" (0));
+  return x;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39082-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39082-1.c
new file mode 100644
index 000000000..4c4e2547a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39082-1.c
@@ -0,0 +1,35 @@
+/* PR target/39082 */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2" } */
+
+union un
+{
+  long double x;
+  int i;
+};
+
+extern int bar1 (union un);
+extern union un bar2 (int);
+
+int
+foo1 (union un u) /* { dg-message "note: The ABI of passing union with long double has changed in GCC 4.4" } */
+{
+  bar1 (u);
+  return u.i;
+}
+
+int
+foo2 (void)
+{
+  union un u;
+  u.i = 1;
+  return foo1 (u) + bar1 (u);
+}
+
+int
+foo3 (int x)
+{
+  union un u = bar2 (x);
+  return u.i;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39139.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39139.c
new file mode 100644
index 000000000..95ea7fda9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39139.c
@@ -0,0 +1,39 @@
+/* PR target/39139 */
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+#ifdef __x86_64__
+# define AX_REG asm ("rax")
+# define DI_REG asm ("rdi")
+# define SI_REG asm ("rsi")
+#else
+# define AX_REG asm ("eax")
+# define DI_REG asm ("edi")
+# define SI_REG asm ("esi")
+#endif
+
+static inline int
+foo (unsigned int x, void *y)
+{
+  register unsigned long r AX_REG;
+  register unsigned long a1 DI_REG;
+  register unsigned long a2 SI_REG;
+  a1 = (unsigned long) x;
+  a2 = (unsigned long) y;
+  asm volatile ("" : "=r" (r), "+r" (a1), "+r" (a2) : : "memory");
+  return (int) r;
+}
+
+struct T { unsigned long t1, t2; unsigned int t3, t4, t5; };
+
+int
+bar (unsigned long x, unsigned int y, unsigned long u, unsigned int v)
+{
+  long r;
+  struct T e = { .t1 = x, .t2 = u };
+
+  if (x << y != u << v)
+    return 5;
+  r = foo (11, &e);
+  return e.t3 == x;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39162.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39162.c
new file mode 100644
index 000000000..2d114b8fd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39162.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mno-avx" } */
+
+typedef long long __m256i __attribute__ ((__vector_size__ (32), __may_alias__));
+
+__m256i
+bar (__m256i x) /* { dg-warning "AVX" "" } */
+{
+  return x;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39431.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39431.c
new file mode 100644
index 000000000..756bdb9eb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39431.c
@@ -0,0 +1,15 @@
+/* PR target/39431 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-options "-O2 -march=i686 -fpic" { target { ilp32 && fpic } } } */
+
+extern void bar (char *, int);
+
+int
+foo (long long *p, long long oldv, long long *q, int n)
+{
+  char buf[n];
+  bar (buf, n);
+  p[256 + n] = __sync_val_compare_and_swap (p + n, oldv, oldv + 6);
+  return __sync_bool_compare_and_swap (q + n, oldv, oldv + 8);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39445.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39445.c
new file mode 100644
index 000000000..6f0295bc1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39445.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-Os -msse2" } */
+
+#include "sse2-check.h"
+
+typedef struct { __m128 f __attribute__((packed)); } packed;
+
+__m128  __attribute__((noinline))
+foo (__m128 a1, __m128 a2, __m128 a3, __m128 a4,
+     __m128 a5, __m128 a6, __m128 a7, __m128 a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y)
+{
+  return y.f;
+}
+
+void
+sse2_test (void)
+{
+  packed x;
+  __m128 y = { 0 };
+  x.f = y; 
+  y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x.f, sizeof (y)) != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39482.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39482.c
new file mode 100644
index 000000000..4e2dfa724
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39482.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-sse2" } */
+
+extern double log (double __x);
+
+double foo (unsigned long int m_liOutputBufferLen)
+{
+  return log ((double) m_liOutputBufferLen);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39496.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39496.c
new file mode 100644
index 000000000..e4132a116
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39496.c
@@ -0,0 +1,35 @@
+/* PR target/39496 */
+/* { dg-do compile { target { { i?86-*-linux* x86_64-*-linux* } && ilp32 } } } */
+/* { dg-options "-O0 -fverbose-asm -fno-omit-frame-pointer -mtune=i686 -msse2 -mfpmath=sse" } */
+/* Verify that {foo,bar}{,2}param are all passed on the stack, using
+   normal calling conventions, when not optimizing.  */
+/* { dg-final { scan-assembler "\[^0-9-\]8\\(%ebp\\),\[^\n\]*fooparam," } } */
+/* { dg-final { scan-assembler "\[^0-9-\]8\\(%ebp\\),\[^\n\]*barparam," } } */
+/* { dg-final { scan-assembler "\[^0-9-\]8\\(%ebp\\),\[^\n\]*foo2param," } } */
+/* { dg-final { scan-assembler "\[^0-9-\]8\\(%ebp\\),\[^\n\]*bar2param," } } */
+
+static inline int foo (int fooparam)
+{
+  return fooparam;
+}
+
+static int bar (int barparam)
+{
+  return foo (barparam);
+}
+
+static inline double foo2 (double foo2param)
+{
+  return foo2param;
+}
+
+static double bar2 (double bar2param)
+{
+  return foo2 (bar2param);
+}
+
+int
+main ()
+{
+  return bar (0) + bar2 (0.0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39543-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39543-1.c
new file mode 100644
index 000000000..a8442b2e6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39543-1.c
@@ -0,0 +1,52 @@
+/* PR inline-asm/39543 */
+/* { dg-do compile } */
+/* { dg-options "-O3 -fomit-frame-pointer" } */
+
+float __attribute__ ((aligned (16))) s0[128];
+const float s1 = 0.707;
+float s2[8] __attribute__ ((aligned (16)));
+float s3[8] __attribute__ ((aligned (16)));
+float s4[16] __attribute__ ((aligned (16)));
+float s5[16] __attribute__ ((aligned (16)));
+
+void
+foo (int k, float *x, float *y, const float *d, const float *z)
+{
+  float *a, *b, *c, *e;
+
+  a = x + 2 * k;
+  b = a + 2 * k;
+  c = b + 2 * k;
+  e = y + 2 * k;
+  __asm__ volatile (""
+		    : "=m" (x[0]), "=m" (b[0]), "=m" (a[0]), "=m" (c[0])
+		    : "m" (y[0]), "m" (y[k * 2]), "m" (x[0]), "m" (a[0])
+		    : "memory");
+  for (;;)
+    {
+      __asm__ volatile (""
+			:
+			: "m" (y[2]), "m" (d[2]), "m" (e[2]), "m" (z[2])
+			: "memory");
+      if (!--k)
+	break;
+    }
+  __asm__ volatile (""
+		    : "=m" (x[2]), "=m" (x[10]), "=m" (x[6]), "=m" (x[14])
+		    : "m" (y[2]), "m" (y[6]), "m" (x[2]), "m" (x[6]),
+		      "m" (y[18]), "m" (s1)
+		    : "memory");
+}
+
+void
+bar (float *a)
+{
+  foo (4, a, a + 16, s2, s3);
+  foo (8, a, a + 32, s4, s5);
+}
+
+void
+baz (void)
+{
+  bar (s0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39543-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39543-2.c
new file mode 100644
index 000000000..04e980efa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39543-2.c
@@ -0,0 +1,52 @@
+/* PR inline-asm/39543 */
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+/* { dg-skip-if "" { ilp32 && { ! nonpic } } { "*" } { "" } } */
+
+float __attribute__ ((aligned (16))) s0[128];
+const float s1 = 0.707;
+float s2[8] __attribute__ ((aligned (16)));
+float s3[8] __attribute__ ((aligned (16)));
+float s4[16] __attribute__ ((aligned (16)));
+float s5[16] __attribute__ ((aligned (16)));
+
+void
+foo (int k, float *x, float *y, const float *d, const float *z)
+{
+  float *a, *b, *c, *e;
+
+  a = x + 2 * k;
+  b = a + 2 * k;
+  c = b + 2 * k;
+  e = y + 2 * k;
+  __asm__ volatile (""
+		    : "=m" (x[0]), "=m" (b[0]), "=m" (a[0]), "=m" (c[0])
+		    : "m" (y[0]), "m" (y[k * 2]), "m" (x[0]), "m" (a[0])
+		    : "memory");
+  for (;;)
+    {
+      __asm__ volatile (""
+			:
+			: "m" (y[2]), "m" (d[2]), "m" (e[2]), "m" (z[2])
+			: "memory");
+      if (!--k)
+	break;
+    }
+  __asm__ volatile (""
+		    : "=m" (x[2]), "=m" (x[10]), "=m" (x[6]), "=m" (x[14])
+		    : "m" (y[2]), "m" (y[6]), "m" (x[2]), "m" (x[6]), "m" (s1)
+		    : "memory");
+}
+
+void
+bar (float *a)
+{
+  foo (4, a, a + 16, s2, s3);
+  foo (8, a, a + 32, s4, s5);
+}
+
+void
+baz (void)
+{
+  bar (s0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39543-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39543-3.c
new file mode 100644
index 000000000..4e103e671
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39543-3.c
@@ -0,0 +1,42 @@
+/* PR inline-asm/39543 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int s[128];
+
+void
+f1 (void)
+{
+  int i;
+  asm volatile ("# %0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16 %17"
+		: "=r" (i)
+		: "m" (s[0]), "m" (s[2]), "m" (s[4]), "m" (s[6]), "m" (s[8]),
+		  "m" (s[10]), "m" (s[12]), "m" (s[14]), "m" (s[16]), "m" (s[18]),
+		  "m" (s[20]), "m" (s[22]), "m" (s[24]), "m" (s[26]), "m" (s[28]),
+		  "m" (s[30]), "m" (s[32]));
+  asm volatile ("# %0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16 %17"
+		: "=r" (i)
+		: "m" (s[0]), "m" (s[2]), "m" (s[4]), "m" (s[6]), "m" (s[8]),
+		  "m" (s[10]), "m" (s[12]), "m" (s[14]), "m" (s[16]), "m" (s[18]),
+		  "m" (s[20]), "m" (s[22]), "m" (s[24]), "m" (s[26]), "m" (s[28]),
+		  "m" (s[30]), "m" (s[32]));
+}
+
+void
+f2 (int *q)
+{
+  int i;
+  int *p = q + 32;
+  asm volatile ("# %0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16 %17"
+		: "=r" (i)
+		: "m" (p[0]), "m" (p[2]), "m" (p[4]), "m" (p[6]), "m" (p[8]),
+		  "m" (p[10]), "m" (p[12]), "m" (p[14]), "m" (p[16]), "m" (p[18]),
+		  "m" (p[20]), "m" (p[22]), "m" (p[24]), "m" (p[26]), "m" (p[28]),
+		  "m" (p[30]), "m" (p[32]));
+  asm volatile ("# %0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16 %17"
+		: "=r" (i)
+		: "m" (p[0]), "m" (p[2]), "m" (p[4]), "m" (p[6]), "m" (p[8]),
+		  "m" (p[10]), "m" (p[12]), "m" (p[14]), "m" (p[16]), "m" (p[18]),
+		  "m" (p[20]), "m" (p[22]), "m" (p[24]), "m" (p[26]), "m" (p[28]),
+		  "m" (p[30]), "m" (p[32]));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39545-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39545-1.c
new file mode 100644
index 000000000..62bc33fa2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39545-1.c
@@ -0,0 +1,24 @@
+/* PR target/39545 */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2" } */
+
+struct flex
+{
+  int i;
+  int flex [];
+};
+
+int
+foo (struct flex s) /* { dg-message "note: The ABI of passing struct with a flexible array member has changed in GCC 4.4" } */
+{
+  return s.i;
+}
+
+struct flex
+bar (int x)
+{
+  struct flex s;
+  s.i = x;
+  return s;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39545-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39545-2.c
new file mode 100644
index 000000000..143c3827f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39545-2.c
@@ -0,0 +1,18 @@
+/* PR target/39545 */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2" } */
+
+struct flex
+{
+  int i;
+  int flex [];
+};
+
+struct flex
+foo (int x)
+{ /* { dg-message "note: The ABI of passing struct with a flexible array member has changed in GCC 4.4" } */
+  struct flex s;
+  s.i = x;
+  return s;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39592-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39592-1.c
new file mode 100644
index 000000000..a7f37043b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39592-1.c
@@ -0,0 +1,10 @@
+/* Test for ICE with C99-conforming excess precision and -msse.  PR
+   39592.  */
+/* { dg-do compile } */
+/* { dg-options "-ansi -msse" } */
+
+double
+foo (unsigned long var)
+{
+  return var;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39678.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39678.c
new file mode 100644
index 000000000..70e8ff497
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39678.c
@@ -0,0 +1,19 @@
+/* PR target/39678 */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2" } */
+
+struct X {
+  char c;
+  __complex__ float val;
+};
+
+struct X
+foo (float *p)
+{ /* { dg-message "note: The ABI of passing structure with complex float member has changed in GCC 4.4" } */
+  struct X x;
+  x.c = -3;
+  __real x.val = p[0];
+  __imag x.val = p[1];
+  return x;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39804.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39804.c
new file mode 100644
index 000000000..3ff247908
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr39804.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O" } */
+
+typedef unsigned char u8;
+struct __large_struct { unsigned long buf[100]; };
+static inline __attribute__((always_inline)) unsigned long
+__copy_from_user_inatomic(void *to, const void *from, unsigned long n)
+{
+  unsigned long ret = 0;
+  asm volatile("1:	mov""b"" %2,%""b""1\n" "2:\n"
+	       ".section .fixup,\"ax\"\n"
+	       "3:	mov %3,%0\n"
+	       "	xor""b"" %""b""1,%""b""1\n"
+	       "	jmp 2b\n"
+	       ".previous\n"
+	       " .section __ex_table,\"a\"\n"
+	       " " ".balign 4" " " "\n"
+	       " " ".long" " " "1b" "," "3b" "\n"
+	       " .previous\n"
+	       : "=r" (ret), "=q"(*(u8 *)to)
+	       : "m" ((*(struct __large_struct *)(from))), "i" (1), "0" (ret));
+  return ret;
+}
+void romchecksum(const unsigned char *rom, unsigned char c)
+{
+  unsigned char sum;
+  for (sum = 0;
+       !__copy_from_user_inatomic(&(c), ( typeof(c) *)(rom++), sizeof(c));)
+    sum += c;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40718.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40718.c
new file mode 100644
index 000000000..f6029ed98
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40718.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O1 -foptimize-sibling-calls" } */
+
+void abort (void);
+
+struct S
+{
+  void (__attribute__((__stdcall__)) *f) (struct S *);
+  int i;
+};
+
+void __attribute__((__stdcall__))
+foo (struct S *s)
+{
+  s->i++;
+}
+
+void __attribute__((__stdcall__))
+bar (struct S *s)
+{
+  foo(s);
+  s->f(s);
+}
+
+int main (void)
+{
+  struct S s = { foo, 0 };
+
+  bar (&s);
+  if (s.i != 2)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40809.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40809.c
new file mode 100644
index 000000000..979b53154
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40809.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -msse2" } */
+
+#include "sse2-check.h"
+
+#define N 8
+
+unsigned int u4[N] = { 4000000000u, 4000000000u, 4000000000u, 4000000000u, 4000000000u, 4000000000u, 4000000000u, 4000000000u };
+float f4[N];
+
+static void
+sse2_test (void)
+{
+  int j;
+
+  for (j = 0; j < N; j++)
+    f4[j] = u4[j];
+
+  /* check results:  */
+  for (j = 0; j < N; j++)
+    if (f4[j] != 4000000000.0)
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40906-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40906-1.c
new file mode 100644
index 000000000..c14bbfa3a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40906-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -fomit-frame-pointer -mpush-args -mno-accumulate-outgoing-args" } */
+
+void abort (void);
+
+void __attribute__((noinline))
+f (long double a)
+{
+  if (a != 1.23L)
+    abort ();
+}
+
+int __attribute__((noinline))
+g (long double b)
+{
+  f (b);
+  return 0;
+}
+
+int
+main (void)
+{
+  g (1.23L);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40906-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40906-2.c
new file mode 100644
index 000000000..66e146b0c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40906-2.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -fomit-frame-pointer -mpush-args -mno-accumulate-outgoing-args -m128bit-long-double" } */
+
+void abort (void);
+
+void __attribute__((noinline))
+f (long double a)
+{
+  if (a != 1.23L)
+    abort ();
+}
+
+int __attribute__((noinline))
+g (long double b)
+{
+  f (b);
+  return 0;
+}
+
+int
+main (void)
+{
+  g (1.23L);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40906-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40906-3.c
new file mode 100644
index 000000000..b639b6299
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40906-3.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -fomit-frame-pointer -msse2 -mpush-args -mno-accumulate-outgoing-args" } */
+
+#include "sse2-check.h"
+
+void __attribute__((noinline))
+f (__float128 a)
+{
+  if (a != 1.23Q)
+    abort ();
+}
+
+int __attribute__((noinline))
+g (__float128 b)
+{
+  f (b);
+  return 0;
+}
+
+static void
+sse2_test (void)
+{
+  g (1.23Q);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40934.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40934.c
new file mode 100644
index 000000000..41f46f881
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40934.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -march=i586 -ffast-math" } */
+
+extern double host_frametime;
+extern float pitchvel;
+V_DriftPitch (float delta, float move)
+{
+  if (!delta)
+    move = host_frametime;
+  if (delta > 0)
+    ;
+  else if (delta < 0 && move > -delta)
+    pitchvel = 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40957.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40957.c
new file mode 100644
index 000000000..56762d7e8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr40957.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+typedef int __v8si __attribute__((__vector_size__(32)));
+typedef long long __m256i __attribute__((__vector_size__(32), __may_alias__));
+
+static __m256i
+_mm256_set1_epi32 (int __A)
+{
+  return __extension__ (__m256i)(__v8si){ __A, __A, __A, __A,
+					  __A, __A, __A, __A };
+}
+__m256i
+foo ()
+{
+  return _mm256_set1_epi32 (-1);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr41019.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr41019.c
new file mode 100644
index 000000000..c0021c6a4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr41019.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2 -ftree-vectorize" } */
+
+#include "sse2-check.h"
+
+long long int a[64];
+
+void
+sse2_test (void)
+{
+  int k;
+
+  for (k = 0; k < 64; k++)
+    a[k] = a[k] != 5 ? 12 : 10;
+
+  for (k = 0; k < 64; k++)
+    if (a[k] != 12)
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr41442.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr41442.c
new file mode 100644
index 000000000..feae791bd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr41442.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef struct LINK link;
+struct LINK
+{
+    link* next;
+};
+
+int haha(link* p1, link* p2)
+{
+  if ((p1->next && !p2->next) || p2->next)
+    return 0;
+
+  return 1;
+}
+
+/* { dg-final { scan-assembler-times "test|cmp" 2 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr41900.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr41900.c
new file mode 100644
index 000000000..55f712d1f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr41900.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -fomit-frame-pointer -mpreferred-stack-boundary=2" } */
+
+int main ()
+{
+  volatile unsigned code = 0xc3;
+
+  ((void (*)(void)) &code) ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "call\[ \\t\]+\\*%esp" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr41963.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr41963.c
new file mode 100644
index 000000000..3eeffeea1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr41963.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -mrecip" } */
+#include <math.h>
+
+extern float sqrtf(float);
+
+static __attribute__((noinline)) void f (float *dst, float *src)
+{
+  int i, j;
+  for (i = 0; i < 2; i++)
+    {
+      float len;
+      dst[0] = src[0];
+      dst[1] = src[1];
+      len = sqrtf (dst[0] * dst[0] + dst[1] * dst[1]);
+      if (len > 0.5f)
+	{
+	  len = 1.0f / len;
+	  dst[0] *= len;
+	  dst[1] *= len;
+	}
+    }
+}
+
+extern void abort (void);
+
+int main()
+{
+  float dst[2], src[2];
+  src[0] = 2.0f;
+  src[1] = 5.0f;
+  f (dst, src);
+  if (fabsf (dst[0] * dst[0] + dst[1] * dst[1] - 1.0f) > 0.01f)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-1.c
new file mode 100644
index 000000000..60da8ee15
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-1.c
@@ -0,0 +1,77 @@
+/* { dg-do run } */
+/* { dg-options "-O1 -msse2 -ftree-vectorize" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+unsigned int v1[] __attribute__ ((aligned(16))) =
+{
+  0x80000000, 1, 0xa0000000, 2,
+  3, 0xd0000000, 0xf0000000, 0xe0000000
+};
+unsigned int v2[] __attribute__ ((aligned(16))) =
+{
+  4, 0xb0000000, 5, 0xc0000000,
+  0xd0000000, 6, 7, 8
+};
+
+unsigned int max[] =
+{
+  0x80000000, 0xb0000000, 0xa0000000, 0xc0000000,
+  0xd0000000, 0xd0000000, 0xf0000000, 0xe0000000
+};
+
+unsigned int min[] =
+{
+  4, 1, 5, 2,
+  3, 6, 7, 8
+};
+
+unsigned int res[8] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 8; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 8; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-1a.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-1a.c
new file mode 100644
index 000000000..cd77175f6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-1a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O1 -msse4.1 -ftree-vectorize" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "pr42542-1.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-1b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-1b.c
new file mode 100644
index 000000000..7651f07a6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-1b.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse4.1 -ftree-vectorize" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "pr42542-1.c"
+
+/* { dg-final { scan-assembler "pmaxud" } } */
+/* { dg-final { scan-assembler "pminud" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-2.c
new file mode 100644
index 000000000..fc59534d9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-2.c
@@ -0,0 +1,77 @@
+/* { dg-do run } */
+/* { dg-options "-O1 -msse2 -ftree-vectorize" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+unsigned short v1[] __attribute__ ((aligned(16))) =
+{
+  0x8000, 0x9000, 1, 10, 0xa000, 0xb000, 2, 20,
+  3, 30, 0xd000, 0xe000, 0xf000, 0xe000, 25, 30
+};
+unsigned short v2[] __attribute__ ((aligned(16))) =
+{
+  4, 40, 0xb000, 0x8000, 5, 50, 0xc000, 0xf000,
+  0xd000, 0xa000, 6, 65, 7, 75, 0xe000, 0xc000
+};
+
+unsigned short max[] =
+{
+  0x8000, 0x9000, 0xb000, 0x8000, 0xa000, 0xb000, 0xc000, 0xf000,
+  0xd000, 0xa000, 0xd000, 0xe000, 0xf000, 0xe000, 0xe000, 0xc000
+};
+
+unsigned short min[] =
+{
+  4, 40, 1, 10, 5, 50, 2, 20,
+  3, 30, 6, 65, 7, 75, 25, 30
+};
+
+unsigned short res[16] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 16; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 16; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-2a.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-2a.c
new file mode 100644
index 000000000..bcefa9cfe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-2a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O1 -msse4.1 -ftree-vectorize" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "pr42542-2.c"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-2b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-2b.c
new file mode 100644
index 000000000..ddb539bf7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-2b.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse4.1 -ftree-vectorize" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "pr42542-2.c"
+
+/* { dg-final { scan-assembler "pmaxuw" } } */
+/* { dg-final { scan-assembler "pminuw" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-3.c
new file mode 100644
index 000000000..028d2f899
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-3.c
@@ -0,0 +1,85 @@
+/* { dg-do run } */
+/* { dg-options "-O1 -msse2 -ftree-vectorize" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+unsigned char v1[] __attribute__ ((aligned(16))) =
+{
+  0x80, 0xd0, 0x90, 0xa0, 1, 15, 10, 15,
+  0xa0, 0xc0, 0xb0, 0xf0, 2, 25, 20, 35,
+  3, 34, 30, 36, 0xd0, 0x80, 0xe0, 0xb0,
+  0xf0, 0xe0, 0xe0, 0x80, 25, 34, 30, 40
+};
+unsigned char v2[] __attribute__ ((aligned(16))) =
+{
+  4, 44, 40, 48, 0xb0, 0x80, 0x80, 0x90,
+  5, 55, 50, 51, 0xc0, 0xb0, 0xf0, 0xd0,
+  0xd0, 0x80, 0xa0, 0xf0, 6, 61, 65, 68,
+  7, 76, 75, 81, 0xe0, 0xf0, 0xc0, 0x90
+};
+
+unsigned char max[] =
+{
+  0x80, 0xd0, 0x90, 0xa0, 0xb0, 0x80, 0x80, 0x90,
+  0xa0, 0xc0, 0xb0, 0xf0, 0xc0, 0xb0, 0xf0, 0xd0,
+  0xd0, 0x80, 0xa0, 0xf0, 0xd0, 0x80, 0xe0, 0xb0,
+  0xf0, 0xe0, 0xe0, 0x80, 0xe0, 0xf0, 0xc0, 0x90
+};
+
+unsigned char min[] =
+{
+  4, 44, 40, 48, 1, 15, 10, 15,
+  5, 55, 50, 51, 2, 25, 20, 35,
+  3, 34, 30, 36, 6, 61, 65, 68,
+  7, 76, 75, 81, 25, 34, 30, 40
+};
+
+unsigned char res[32] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 32; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 32; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-3a.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-3a.c
new file mode 100644
index 000000000..754e59e84
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42542-3a.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse2 -ftree-vectorize" } */
+
+#include "pr42542-3.c"
+
+/* { dg-final { scan-assembler "pmaxub" } } */
+/* { dg-final { scan-assembler "pminub" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42549.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42549.c
new file mode 100644
index 000000000..0a9bfa84f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr42549.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -m3dnow" } */
+
+#include "mmx-3dnow-check.h"
+
+#include <mm3dnow.h>
+
+typedef union {
+  float f[2];
+  __m64 v;
+} vec_t;
+
+void __attribute__ ((noinline))
+Butterfly_3 (__m64 * D, __m64 SC)
+{
+  __m64 T, T1;
+
+  T = _m_pfmul (D[1], SC);
+  T1 = D[0];
+  D[0] = _m_pfadd (T1, T);
+  D[1] = _m_pfsub (T1, T);
+}
+
+static void
+mmx_3dnow_test (void)
+{
+  vec_t D[2] = { { .f = { 2.0f, 3.0f } },
+		 { .f = { 4.0f, 5.0f } } };
+
+  const vec_t SC = { .f = { 1.0f, 1.0f } };
+
+  Butterfly_3 (&D[0].v, SC.v);
+  _m_femms ();
+
+  if (D[1].f[0] != -2.0f || D[1].f[1] != -2.0f)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr9771-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr9771-1.c
new file mode 100644
index 000000000..01f2f2975
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/pr9771-1.c
@@ -0,0 +1,44 @@
+/* PR rtl-optimization/9771 */
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -fomit-frame-pointer -ffixed-ebp" } */
+
+extern void abort(void);
+extern void exit(int);
+
+register long *B asm ("ebp");
+
+long x = 10;
+long y = 20;
+
+void bar(void)
+{
+  B = &y;
+}
+
+void foo()
+{
+  long *adr = B;
+  long save = *adr;
+
+  *adr = 123;
+
+  bar();
+
+  *adr = save;
+}
+
+int main()
+{
+  B = &x;
+
+  foo();
+
+  if (x != 10 || y != 20)
+    abort();
+
+  /* We can't return, as our caller may assume %ebp is preserved!  */
+  /* We could save/restore it (like foo), but its easier to exit.  */
+  exit(0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/push-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/push-1.c
new file mode 100644
index 000000000..da9b39ec9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/push-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
+/* { dg-options "-w -msse2 -Os" } */
+
+typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
+
+extern void foo (__m128 x, __m128 y ,__m128 z ,__m128 a, int size);
+
+void
+bar (void)
+{
+  __m128 x = { 1.0 };
+  foo (x, x, x, x, 5);
+}
+
+/* { dg-final { scan-assembler-not "movups" { xfail *-*-* } } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/quad-sse.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/quad-sse.c
new file mode 100644
index 000000000..4b6fe7925
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/quad-sse.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+__float128 x, y;
+
+__float128 test_1(void)
+{
+  return -x;
+}
+
+__float128 test_2(void)
+{
+  return __builtin_fabsq (x);
+}
+
+__float128 test_3(void)
+{
+  return __builtin_copysignq (x, y);
+}
+
+/* { dg-final { scan-assembler-not "call.*(neg|fabs|copysign)" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/recip-divf.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/recip-divf.c
new file mode 100644
index 000000000..b4447d33a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/recip-divf.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -msse -mfpmath=sse -mrecip" } */
+
+float t1(float a, float b)
+{
+  return a / b;
+}
+
+/* { dg-final { scan-assembler "rcpss" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/recip-sqrtf.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/recip-sqrtf.c
new file mode 100644
index 000000000..859d2180a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/recip-sqrtf.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -msse -mfpmath=sse -mrecip" } */
+
+extern float sqrtf (float);
+
+float t1(float a, float b)
+{
+  return a/sqrtf(b);
+}
+
+float t2(float a, float b)
+{
+  return sqrtf(a/b);
+}
+
+float t3(float a)
+{
+  return sqrtf(a);
+}
+
+/* { dg-final { scan-assembler-times "rsqrtss" 3 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/recip-vec-divf.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/recip-vec-divf.c
new file mode 100644
index 000000000..4bdbba79f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/recip-vec-divf.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse -mfpmath=sse -mrecip" } */
+
+float a[16];
+float b[16];
+float r[16];
+
+void t1(void)
+{
+ int i;
+
+ for (i = 0; i < 16; i++)
+   r[i] = a[i] / b[i];
+}
+
+/* { dg-final { scan-assembler "rcpps" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf.c
new file mode 100644
index 000000000..bcef700ec
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse -mfpmath=sse -mrecip" } */
+
+float a[16];
+float b[16];
+float r[16];
+
+extern float sqrtf (float);
+
+void t1(void)
+{
+ int i;
+
+ for (i = 0; i < 16; i++)
+   r[i] = a[i] / sqrtf (b[i]);
+}
+
+void t2(void)
+{
+ int i;
+
+ for (i = 0; i < 16; i++)
+   r[i] = sqrtf (a[i] / b[i]);
+}
+
+void t3(void)
+{
+ int i;
+
+ for (i = 0; i < 16; i++)
+   r[i] = sqrtf (a[i]);
+}
+
+/* { dg-final { scan-assembler-times "rsqrtps" 3 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/regparm-stdcall.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/regparm-stdcall.c
new file mode 100644
index 000000000..144f5f99e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/regparm-stdcall.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-options -mpreferred-stack-boundary=4 } */
+/* { dg-require-effective-target ilp32 } */
+
+extern void abort(void);
+
+void __attribute__((regparm(2), stdcall)) foo(int i, int j, float x)
+{
+  static int last_align = -1;
+  int dummy, align = (int)&dummy & 15;
+  if (last_align < 0)
+    last_align = align;
+  else if (align != last_align)
+    abort ();
+}
+
+int main()
+{
+	foo(0,0,0.0);
+	foo(0,0,0.0);
+	return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/regparm.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/regparm.c
new file mode 100644
index 000000000..9db191c72
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/regparm.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-W -Wall" } */
+
+/* Verify that GCC correctly detects non-matching regparm attributes.  */
+int __attribute__((regparm(3))) f (void);  /* { dg-message "note: previous" } */
+
+int __attribute__((regparm(2))) f (void) { /* { dg-error "conflicting" } */
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/reload-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/reload-1.c
new file mode 100644
index 000000000..8ccfcb55d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/reload-1.c
@@ -0,0 +1,114 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O3 -msse2 -fdump-rtl-csa" } */
+
+#include <emmintrin.h>
+#include <stdint.h>
+
+typedef __SIZE_TYPE__ size_t;
+typedef float vFloat __attribute__ ((__vector_size__ (16)));
+typedef double vDouble __attribute__ ((__vector_size__ (16)));
+typedef struct buf
+{
+  void *data;
+  unsigned long h;
+  unsigned long  w;
+  size_t bytes;
+} buf;
+
+typedef struct job
+{
+  struct Job *next;
+  void * info;
+  long (*func)(struct Job *job);
+  long error;
+} job;
+
+typedef struct fj
+{
+    job hd;
+    buf src;
+    buf dest;
+    float g;
+    unsigned int flags;
+} fj;
+
+static const double r[256], t[256];
+
+long bar (const buf *src, const buf *dest, float g, unsigned int flags)
+{
+  float *d0 = (float*) src->data;
+  float *d1 = (float*) dest->data;
+  uintptr_t w = dest->w;
+  uintptr_t idx;
+  vFloat p0;
+  static const vFloat m0;
+  static const vDouble p[3], m, b;
+  float *sr = d0;
+  float *dr = d1;
+  for( idx = 0; idx + 8 <= w; idx += 8 )
+  {
+    vFloat f0 = _mm_loadu_ps (sr);
+    vFloat f1 = _mm_loadu_ps (sr + 4);
+    sr += 8;
+    vFloat fa0 = _mm_andnot_ps (m0, f0);
+    vFloat fa1 = _mm_andnot_ps (m0, f1);
+    vDouble v0 = _mm_cvtps_pd (fa0);
+    vDouble v1 = _mm_cvtps_pd (_mm_movehl_ps (fa0, fa0));
+    vDouble v2 = _mm_cvtps_pd (fa1);
+    vDouble v3 = _mm_cvtps_pd (_mm_movehl_ps (fa1, fa1));
+    vDouble  vi0, vi1, vi2, vi3;
+    __m128i b0, b1, b2, b3;
+    b0 = _mm_packs_epi32 (_mm_packs_epi32 (b0, b1), _mm_packs_epi32 (b2, b3));
+    b1 = _mm_srli_epi64 (b0, 32);
+    unsigned int i0 = _mm_cvtsi128_si32 (b0); 
+    unsigned int i2 = _mm_cvtsi128_si32 (b1);
+    v0 -= _mm_loadh_pd (_mm_load_sd (r + (i0 & 0xff)), r + (i0 >> 16));
+    v1 -= _mm_loadh_pd (_mm_load_sd (r + (i2 & 0xff)), r + (i2 >> 16));
+    b0 = _mm_unpackhi_epi64 (b0, b0);
+    b1 = _mm_unpackhi_epi64 (b1, b1);
+    unsigned int i4 = _mm_cvtsi128_si32 (b0);
+    unsigned int i6 = _mm_cvtsi128_si32 (b1);
+    v2 -= _mm_loadh_pd (_mm_load_sd (r + (i4 & 0xff)), r + (i4 >> 16));
+    v3 -= _mm_loadh_pd (_mm_load_sd (r + (i6 & 0xff)), r + (i6 >> 16));
+    v0 = p[0] + (p[1] + p[2] * v0) * v0;
+    v1 = p[0] + (p[1] + p[2] * v1) * v1;
+    v2 = p[0] + (p[1] + p[2] * v2) * v2;
+    v3 = p[0] + (p[1] + p[2] * v3) * v3;
+    vi0 = (vDouble) _mm_slli_epi64 ((__m128i)((vi0 + b) + m), 52);
+    vi1 = (vDouble) _mm_slli_epi64 ((__m128i)((vi1 + b) + m), 52);
+    vi2 = (vDouble) _mm_slli_epi64 ((__m128i)((vi2 + b) + m), 52);
+    vi3 = (vDouble) _mm_slli_epi64 ((__m128i)((vi3 + b) + m), 52);
+    vi0 *= _mm_loadh_pd (_mm_load_sd (t + (i0 & 0xff)), t + (i0 >> 16));
+    vi1 *= _mm_loadh_pd (_mm_load_sd (t + (i2 & 0xff)), t + (i2 >> 16));
+    vi2 *= _mm_loadh_pd (_mm_load_sd (t + (i4 & 0xff)), t + (i4 >> 16));
+    vi3 *= _mm_loadh_pd (_mm_load_sd (t + (i6 & 0xff)), t + (i6 >> 16));
+    v0 *= vi0;
+    v1 *= vi1;
+    v2 *= vi2;
+    v3 *= vi3;
+    vFloat r0 = _mm_movelh_ps (_mm_cvtpd_ps( v0 ), _mm_cvtpd_ps (v1));
+    vFloat r1 = _mm_movelh_ps (_mm_cvtpd_ps( v2 ), _mm_cvtpd_ps (v3));
+    vFloat z0 = _mm_cmpeq_ps (f0, _mm_setzero_ps());
+    vFloat z1 = _mm_cmpeq_ps (f1, _mm_setzero_ps());
+    r0 = _mm_andnot_ps (z0, r0);
+    r1 = _mm_andnot_ps (z1, r1);
+    z0 = _mm_and_ps (z0, p0);
+    z1 = _mm_and_ps (z1, p0);
+    r0 = _mm_or_ps (r0, z0);
+    r1 = _mm_or_ps (r1, z1);
+    _mm_storeu_ps (dr, r0);
+    _mm_storeu_ps (dr + 4, r1);
+    dr += 8;
+  }
+  return 0;
+}
+
+long foo (job *j )
+{
+  fj *jd = (fj*) j;
+  return bar (&jd->src, &jd->dest, jd->g, jd->flags);
+}
+
+/* { dg-final { scan-rtl-dump-not "deleted 1 dead insns" "csa" } } */
+/* { dg-final { cleanup-rtl-dump "csa" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/rotate-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/rotate-1.c
new file mode 100644
index 000000000..23dc2ee67
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/rotate-1.c
@@ -0,0 +1,16 @@
+/* Verify that rolb instruction is emitted on IA-32/x86-64.  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void foo (unsigned char *);
+
+int
+main (void)
+{
+  unsigned char c = 0;
+  foo (&c);
+  c = c >> 1 | c << 7;
+  return c;
+}
+
+/* { dg-final { scan-assembler "rolb" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/set-v16qi-1.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/set-v16qi-1.h
new file mode 100644
index 000000000..79556e874
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/set-v16qi-1.h
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include CHECK_H
+
+static __m128i
+__attribute__((noinline))
+foo (char *v)
+{
+  return _mm_set_epi8 (v[15], v[14], v[13], v[12],
+		       v[11], v[10], v[9], v[8],
+		       v[7], v[6], v[5], v[4],
+		       v[3], v[2], v[1], v[0]);
+}
+
+static void
+TEST (void)
+{
+  char v[16] =
+    { 
+      -3, 60, 48, 104, -90, 37, -48, 78,
+      4, 33, 81, 4, -89, 17, 8, 68
+    };
+  union128i_b u;
+
+  u.x = foo (v);
+  if (check_union128i_b (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/set-v16qi-2.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/set-v16qi-2.h
new file mode 100644
index 000000000..9768806c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/set-v16qi-2.h
@@ -0,0 +1,30 @@
+#include CHECK_H
+
+static __m128i
+__attribute__((noinline))
+foo (char x1, char x2, char x3, char x4,
+     char x5, char x6, char x7, char x8,
+     char x9, char x10, char x11, char x12,
+     char x13, char x14, char x15, char x16)
+{
+  return _mm_set_epi8 (x1, x2, x3, x4, x5, x6, x7, x8,
+		       x9, x10, x11, x12, x13, x14, x15, x16);
+}
+
+static void
+TEST (void)
+{
+  char v[16] =
+    { 
+      -3, 60, 48, 104, -90, 37, -48, 78,
+      4, 33, 81, 4, -89, 17, 8, 68
+    };
+  union128i_b u;
+
+  u.x = foo (v[15], v[14], v[13], v[12],
+	     v[11], v[10], v[9], v[8],
+	     v[7], v[6], v[5], v[4],
+	     v[3], v[2], v[1], v[0]);
+  if (check_union128i_b (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/set-v16qi-3.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/set-v16qi-3.h
new file mode 100644
index 000000000..faf3cd344
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/set-v16qi-3.h
@@ -0,0 +1,63 @@
+#include CHECK_H
+
+static __m128i
+__attribute__((noinline))
+foo (char x, int i)
+{
+  switch (i)
+    {
+    case 15:
+      return _mm_set_epi8 (x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 14:
+      return _mm_set_epi8 (1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 13:
+      return _mm_set_epi8 (1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 12:
+      return _mm_set_epi8 (1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 11:
+      return _mm_set_epi8 (1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 10:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 9:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 8:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 7:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1);
+    case 3:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1);
+    case 2:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1);
+    case 1:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1);
+    case 0:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+TEST (void)
+{
+  char e = 0x13;
+  char v[16];
+  union128i_b u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 1;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union128i_b (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/set-v8hi-1.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/set-v8hi-1.h
new file mode 100644
index 000000000..87762b82e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/set-v8hi-1.h
@@ -0,0 +1,19 @@
+#include CHECK_H
+
+static __m128i
+__attribute__((noinline))
+foo (short *v)
+{
+  return _mm_set_epi16 (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+}
+
+static void
+TEST (void)
+{
+  short v[8] = { -3, 6000, 48, 104, -90, 34567, -1248, 34678 };
+  union128i_w u;
+
+  u.x = foo (v);
+  if (check_union128i_w (u, v))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/set-v8hi-2.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/set-v8hi-2.h
new file mode 100644
index 000000000..835e7b4d6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/set-v8hi-2.h
@@ -0,0 +1,21 @@
+#include CHECK_H
+
+__m128i
+__attribute__((noinline))
+foo (short x1, short x2, short x3, short x4,
+     short x5, short x6, short x7, short x8)
+{
+  return _mm_set_epi16 (x1, x2, x3, x4, x5, x6, x7, x8);
+}
+
+static void
+TEST (void)
+{
+  short v[8] = { -3, 2, 1, 9, 23, -173, -13, 69 };
+  union128i_w u;
+
+  u.x = foo (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+
+  if (check_union128i_w (u, v))
+     abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sibcall-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sibcall-5.c
new file mode 100644
index 000000000..f4127b975
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sibcall-5.c
@@ -0,0 +1,44 @@
+/* Check that indirect sibcalls understand regparm.  */
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+int (*f)(int, int) __attribute__((regparm(2)));
+int (*g)(int, int, int) __attribute__((regparm(3)));
+
+int __attribute__((noinline))
+foo(void)
+{
+  return f(1, 2);
+}
+
+int __attribute__((noinline))
+bar(void)
+{
+  return g(1, 2, 3);
+}
+
+int __attribute__((regparm(2)))
+f1(int x, int y)
+{
+  return x*3 + y;
+}
+
+int __attribute__((regparm(3)))
+g1(int x, int y, int z)
+{
+  return x*9 + y*3 + z;
+}
+
+int main()
+{
+  f = f1;
+  g = g1;
+  if (foo() != 1*3 + 2)
+    abort ();
+  if (bar() != 1*9 + 2*3 + 3)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/signbit-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/signbit-1.c
new file mode 100644
index 000000000..745796d70
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/signbit-1.c
@@ -0,0 +1,29 @@
+/* PR optimization/8746 */
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O1 -mtune=i586" } */
+
+extern void abort (void);
+
+unsigned char r0;
+
+int foo(int x)
+{
+  unsigned char r = x&0xf0;
+
+  if (!(r&0x80))
+  {
+    r0 = r;
+    return 0;
+  }
+  else
+    return 1;
+}
+
+int main(void)
+{
+  if (foo(0x80) != 1)
+    abort();
+
+   return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/signbit-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/signbit-2.c
new file mode 100644
index 000000000..c09bba3b8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/signbit-2.c
@@ -0,0 +1,29 @@
+/* PR optimization/8746 */
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O1 -mtune=i586" } */
+
+extern void abort (void);
+
+unsigned short r0;
+
+int foo(int x)
+{
+  unsigned short r = x&0xf000;
+
+  if (!(r&0x8000))
+  {
+    r0 = r;
+    return 0;
+  }
+  else
+    return 1;
+}
+
+int main(void)
+{
+  if (foo(0x8000) != 1)
+    abort();
+
+   return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/signbit-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/signbit-3.c
new file mode 100644
index 000000000..dcd56b636
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/signbit-3.c
@@ -0,0 +1,33 @@
+/* PR optimization/8746 */
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O1 -mtune=i586" } */
+
+extern void abort (void);
+
+volatile int j;
+
+void f0() { j=0; }
+void f1() { j=1; }
+
+int foo(int x)
+{
+  if ((short int)(x&0x8000) > (short int)0)
+  {
+    f0();
+    return 0;
+  }
+  else
+  {
+    f1();
+    return 1;
+  }
+}
+
+int main(void)
+{
+  if (foo(0x8000) != 1)
+    abort();
+
+   return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-1.c
new file mode 100644
index 000000000..afae22d37
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-1.c
@@ -0,0 +1,25 @@
+/* PR 12902 */
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse" } */
+
+#include <xmmintrin.h>
+
+typedef union
+{
+  int i[4];
+  float f[4];
+  __m128 v;
+} vector4_t;
+
+void
+swizzle (const void *a, vector4_t * b, vector4_t * c)
+{
+  b->v = _mm_loadl_pi (b->v, (__m64 *) a);
+  c->v = _mm_loadl_pi (c->v, ((__m64 *) a) + 1);
+}
+
+/* While one legal rendering of each statement would be movaps;movlps;movaps,
+   we can implmenent this with just movlps;movlps.  Since we do now, anything
+   less would be a regression.  */
+/* { dg-final { scan-assembler-not "movaps" } } */
+/* { dg-final { scan-assembler "movlps" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-10.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-10.c
new file mode 100644
index 000000000..5cf0714f0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-10.c
@@ -0,0 +1,31 @@
+/* PR 17930 */
+/* { dg-do run } */
+/* { dg-options "-O1 -msse2 -mfpmath=sse -mno-accumulate-outgoing-args -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer" } */
+/* { dg-options "-O1 -msse2 -mfpmath=sse -fno-omit-frame-pointer" { target *-*-mingw* *-*-cygwin* } } */
+
+#include "sse2-check.h"
+
+typedef _Complex double complex_16;
+
+void __attribute__((noinline))
+test (complex_16 a[5][5])
+{
+  int i, j, k;
+  complex_16 x;
+
+  for (j = 0; j < 5; j++)
+    for (i = 0; i < 5; i++)
+      {
+        for (k = 0; k < j - 1; ++k)
+	  x = a[k][i] * ~a[k][j];
+	a[j][i] = x;
+      }
+}
+
+static void
+sse2_test (void)
+{
+  static complex_16 work[5][5];
+
+  test (work); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-11.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-11.c
new file mode 100644
index 000000000..3745dbf7f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-11.c
@@ -0,0 +1,74 @@
+/* PR rtl-optimization/21239 */
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+void
+foo (unsigned int x, double *y, const double *z)
+{
+  __m128d tmp;
+  while (x)
+    {
+      tmp = _mm_load_sd (z);
+      _mm_store_sd (y, tmp);
+      --x; ++z; ++y;
+    }
+}
+
+void
+bar (unsigned int x, float *y, const float *z)
+{
+  __m128 tmp;
+  unsigned int i;
+  for (i = 0; i < x; ++i)
+    {
+      tmp = (__m128) { *z, 0, 0, 0 };
+      *y = __builtin_ia32_vec_ext_v4sf (tmp, 0);
+      ++z; ++y;
+    }
+  for (i = 0; i < x; ++i)
+    {
+      tmp = (__m128) { 0, *z, 0, 0 };
+      *y = __builtin_ia32_vec_ext_v4sf (tmp, 1);
+      ++z; ++y;
+    }
+  for (i = 0; i < x; ++i)
+    {
+      tmp = (__m128) { 0, 0, *z, 0 };
+      *y = __builtin_ia32_vec_ext_v4sf (tmp, 2);
+      ++z; ++y;
+    }
+  for (i = 0; i < x; ++i)
+    {
+      tmp = (__m128) { 0, 0, 0, *z };
+      *y = __builtin_ia32_vec_ext_v4sf (tmp, 3);
+      ++z; ++y;
+    }
+}
+
+static void
+sse2_test (void)
+{
+  unsigned int i;
+  double a[16], b[16];
+  float c[16], d[16];
+  for (i = 0; i < 16; ++i)
+    {
+      a[i] = 1;
+      b[i] = 2;
+      c[i] = 3;
+      d[i] = 4;
+    }
+  foo (16, a, b);
+  bar (4, c, d);
+  for (i = 0; i < 16; ++i)
+    {
+      if (a[i] != 2)
+	abort ();
+      if (c[i] != 4)
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-12.c
new file mode 100644
index 000000000..5e2173a8f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-12.c
@@ -0,0 +1,8 @@
+/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h and mm_malloc.h are
+   usable with -O -std=c89 -pedantic-errors.  */
+/* { dg-do compile } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -m3dnow -mavx -msse5 -maes -mpclmul" } */
+
+#include <x86intrin.h>
+
+int dummy;
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-13.c
new file mode 100644
index 000000000..8bfb9f866
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -0,0 +1,135 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -msse5 -maes -mpclmul" } */
+
+#include <mm_malloc.h>
+
+/* Test that the intrinsics compile with optimization.  All of them are
+   defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h and mm3dnow.h
+   that reference the proper builtin functions.  Defining away "extern" and
+   "__inline" results in all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+/* Following intrinsics require immediate arguments. */
+
+/* ammintrin.h */
+#define __builtin_ia32_extrqi(X, I, L)  __builtin_ia32_extrqi(X, 1, 1)
+#define __builtin_ia32_insertqi(X, Y, I, L) __builtin_ia32_insertqi(X, Y, 1, 1)
+
+/* immintrin.h */
+#define __builtin_ia32_blendpd256(X, Y, M) __builtin_ia32_blendpd256(X, Y, 1)
+#define __builtin_ia32_blendps256(X, Y, M) __builtin_ia32_blendps256(X, Y, 1)
+#define __builtin_ia32_dpps256(X, Y, M) __builtin_ia32_dpps256(X, Y, 1)
+#define __builtin_ia32_shufpd256(X, Y, M) __builtin_ia32_shufpd256(X, Y, 1)
+#define __builtin_ia32_shufps256(X, Y, M) __builtin_ia32_shufps256(X, Y, 1)
+#define __builtin_ia32_cmpsd(X, Y, O) __builtin_ia32_cmpsd(X, Y, 1)
+#define __builtin_ia32_cmpss(X, Y, O) __builtin_ia32_cmpss(X, Y, 1)
+#define __builtin_ia32_cmppd(X, Y, O) __builtin_ia32_cmppd(X, Y, 1)
+#define __builtin_ia32_cmpps(X, Y, O) __builtin_ia32_cmpps(X, Y, 1)
+#define __builtin_ia32_cmppd256(X, Y, O) __builtin_ia32_cmppd256(X, Y, 1)
+#define __builtin_ia32_cmpps256(X, Y, O) __builtin_ia32_cmpps256(X, Y, 1)
+#define __builtin_ia32_vextractf128_pd256(X, N) __builtin_ia32_vextractf128_pd256(X, 1)
+#define __builtin_ia32_vextractf128_ps256(X, N) __builtin_ia32_vextractf128_ps256(X, 1)
+#define __builtin_ia32_vextractf128_si256(X, N) __builtin_ia32_vextractf128_si256(X, 1)
+#define __builtin_ia32_vpermilpd(X, N) __builtin_ia32_vpermilpd(X, 1)
+#define __builtin_ia32_vpermilpd256(X, N) __builtin_ia32_vpermilpd256(X, 1)
+#define __builtin_ia32_vpermilps(X, N) __builtin_ia32_vpermilps(X, 1)
+#define __builtin_ia32_vpermilps256(X, N) __builtin_ia32_vpermilps256(X, 1)
+#define __builtin_ia32_vpermil2pd(X, Y, C, I) __builtin_ia32_vpermil2pd(X, Y, C, 1)
+#define __builtin_ia32_vpermil2pd256(X, Y, C, I) __builtin_ia32_vpermil2pd256(X, Y, C, 1)
+#define __builtin_ia32_vpermil2ps(X, Y, C, I) __builtin_ia32_vpermil2ps(X, Y, C, 1)
+#define __builtin_ia32_vpermil2ps256(X, Y, C, I) __builtin_ia32_vpermil2ps256(X, Y, C, 1)
+#define __builtin_ia32_vperm2f128_pd256(X, Y, C) __builtin_ia32_vperm2f128_pd256(X, Y, 1)
+#define __builtin_ia32_vperm2f128_ps256(X, Y, C) __builtin_ia32_vperm2f128_ps256(X, Y, 1)
+#define __builtin_ia32_vperm2f128_si256(X, Y, C) __builtin_ia32_vperm2f128_si256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_pd256(X, Y, C) __builtin_ia32_vinsertf128_pd256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_ps256(X, Y, C) __builtin_ia32_vinsertf128_ps256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_si256(X, Y, C) __builtin_ia32_vinsertf128_si256(X, Y, 1)
+#define __builtin_ia32_roundpd256(V, M) __builtin_ia32_roundpd256(V, 1)
+#define __builtin_ia32_roundps256(V, M) __builtin_ia32_roundps256(V, 1)
+
+/* wmmintrin.h */
+#define __builtin_ia32_aeskeygenassist128(X, C) __builtin_ia32_aeskeygenassist128(X, 1)
+#define __builtin_ia32_pclmulqdq128(X, Y, I) __builtin_ia32_pclmulqdq128(X, Y, 1)
+
+/* mmintrin-common.h */
+#define __builtin_ia32_roundpd(V, M) __builtin_ia32_roundpd(V, 1)
+#define __builtin_ia32_roundsd(D, V, M) __builtin_ia32_roundsd(D, V, 1)
+#define __builtin_ia32_roundps(V, M) __builtin_ia32_roundps(V, 1)
+#define __builtin_ia32_roundss(D, V, M) __builtin_ia32_roundss(D, V, 1)
+
+/* smmintrin.h */
+#define __builtin_ia32_pblendw128(X, Y, M) __builtin_ia32_pblendw128 (X, Y, 1)
+#define __builtin_ia32_blendps(X, Y, M) __builtin_ia32_blendps(X, Y, 1)
+#define __builtin_ia32_blendpd(X, Y, M) __builtin_ia32_blendpd(X, Y, 1)
+#define __builtin_ia32_dpps(X, Y, M) __builtin_ia32_dpps(X, Y, 1)
+#define __builtin_ia32_dppd(X, Y, M) __builtin_ia32_dppd(X, Y, 1)
+#define __builtin_ia32_insertps128(D, S, N) __builtin_ia32_insertps128(D, S, 1)
+#define __builtin_ia32_vec_ext_v4sf(X, N) __builtin_ia32_vec_ext_v4sf(X, 1)
+#define __builtin_ia32_vec_set_v16qi(D, S, N) __builtin_ia32_vec_set_v16qi(D, S, 1)
+#define __builtin_ia32_vec_set_v4si(D, S, N) __builtin_ia32_vec_set_v4si(D, S, 1)
+#define __builtin_ia32_vec_set_v2di(D, S, N) __builtin_ia32_vec_set_v2di(D, S, 1)
+#define __builtin_ia32_vec_ext_v16qi(X, N) __builtin_ia32_vec_ext_v16qi(X, 1)
+#define __builtin_ia32_vec_ext_v4si(X, N) __builtin_ia32_vec_ext_v4si(X, 1)
+#define __builtin_ia32_vec_ext_v2di(X, N) __builtin_ia32_vec_ext_v2di(X, 1)
+#define __builtin_ia32_mpsadbw128(X, Y, M) __builtin_ia32_mpsadbw128(X, Y, 1)
+#define __builtin_ia32_pcmpistrm128(X, Y, M) \
+  __builtin_ia32_pcmpistrm128(X, Y, 1)
+#define __builtin_ia32_pcmpistri128(X, Y, M) \
+  __builtin_ia32_pcmpistri128(X, Y, 1)
+#define __builtin_ia32_pcmpestrm128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestrm128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestri128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestri128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpistria128(X, Y, M) \
+  __builtin_ia32_pcmpistria128(X, Y, 1)
+#define __builtin_ia32_pcmpistric128(X, Y, M) \
+  __builtin_ia32_pcmpistric128(X, Y, 1)
+#define __builtin_ia32_pcmpistrio128(X, Y, M) \
+  __builtin_ia32_pcmpistrio128(X, Y, 1)
+#define __builtin_ia32_pcmpistris128(X, Y, M) \
+  __builtin_ia32_pcmpistris128(X, Y, 1)
+#define __builtin_ia32_pcmpistriz128(X, Y, M) \
+  __builtin_ia32_pcmpistriz128(X, Y, 1)
+#define __builtin_ia32_pcmpestria128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestria128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestric128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestric128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestrio128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestrio128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestris128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestris128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestriz128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestriz128(X, LX, Y, LY, 1)
+
+/* tmmintrin.h */
+#define __builtin_ia32_palignr128(X, Y, N) __builtin_ia32_palignr128(X, Y, 8)
+#define __builtin_ia32_palignr(X, Y, N) __builtin_ia32_palignr(X, Y, 8)
+
+/* emmintrin.h */
+#define __builtin_ia32_psrldqi128(A, B) __builtin_ia32_psrldqi128(A, 8)
+#define __builtin_ia32_pslldqi128(A, B) __builtin_ia32_pslldqi128(A, 8)
+#define __builtin_ia32_pshufhw(A, N) __builtin_ia32_pshufhw(A, 0)
+#define __builtin_ia32_pshuflw(A, N) __builtin_ia32_pshuflw(A, 0)
+#define __builtin_ia32_pshufd(A, N) __builtin_ia32_pshufd(A, 0)
+#define __builtin_ia32_vec_set_v8hi(A, D, N) \
+  __builtin_ia32_vec_set_v8hi(A, D, 0)
+#define __builtin_ia32_vec_ext_v8hi(A, N) __builtin_ia32_vec_ext_v8hi(A, 0)
+#define __builtin_ia32_shufpd(A, B, N) __builtin_ia32_shufpd(A, B, 0)
+
+/* xmmintrin.h */
+#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, A, _MM_HINT_NTA)
+#define __builtin_ia32_pshufw(A, N) __builtin_ia32_pshufw(A, 0)
+#define __builtin_ia32_vec_set_v4hi(A, D, N) \
+  __builtin_ia32_vec_set_v4hi(A, D, 0)
+#define __builtin_ia32_vec_ext_v4hi(A, N) __builtin_ia32_vec_ext_v4hi(A, 0)
+#define __builtin_ia32_shufps(A, B, N) __builtin_ia32_shufps(A, B, 0)
+
+/* bmmintrin.h */
+#define __builtin_ia32_protbi(A, B) __builtin_ia32_protbi(A,1)
+#define __builtin_ia32_protwi(A, B) __builtin_ia32_protwi(A,1)
+#define __builtin_ia32_protdi(A, B) __builtin_ia32_protdi(A,1)
+#define __builtin_ia32_protqi(A, B) __builtin_ia32_protqi(A,1)
+
+#include <x86intrin.h>
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-14.c
new file mode 100644
index 000000000..67da6608a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-14.c
@@ -0,0 +1,164 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -msse5 -maes -mpclmul" } */
+
+#include <mm_malloc.h>
+
+/* Test that the intrinsics compile without optimization.  All of them are
+   defined as inline functions in {,x,e,p,t,s,w,a,b}mmintrin.h  and mm3dnow.h
+   that reference the proper builtin functions.  Defining away "extern" and
+   "__inline" results in all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+#include <x86intrin.h>
+
+#define _CONCAT(x,y) x ## y
+
+#define test_1(func, type, op1_type, imm)				\
+  type _CONCAT(_,func) (op1_type A, int const I)			\
+  { return func (A, imm); }
+
+#define test_1x(func, type, op1_type, imm1, imm2)			\
+  type _CONCAT(_,func) (op1_type A, int const I, int const L)		\
+  { return func (A, imm1, imm2); }
+
+#define test_2(func, type, op1_type, op2_type, imm)			\
+  type _CONCAT(_,func) (op1_type A, op2_type B, int const I)		\
+  { return func (A, B, imm); }
+
+#define test_2x(func, type, op1_type, op2_type, imm1, imm2)		\
+  type _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L) \
+  { return func (A, B, imm1, imm2); }
+
+#define test_3(func, type, op1_type, op2_type, op3_type, imm)		\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, int const I)			\
+  { return func (A, B, C, imm); }
+
+#define test_4(func, type, op1_type, op2_type, op3_type, op4_type, imm)	\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, op4_type D, int const I)		\
+  { return func (A, B, C, D, imm); }
+
+
+/* Following intrinsics require immediate arguments.  They
+   are defined as macros for non-optimized compilations. */
+
+/* ammintrin.h */
+test_1x (_mm_extracti_si64, __m128i, __m128i, 1, 1)
+test_2x (_mm_inserti_si64, __m128i, __m128i, __m128i, 1, 1)
+
+/* immintrin.h */
+test_2 (_mm256_blend_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_blend_ps, __m256, __m256, __m256, 1)
+test_2 (_mm256_dp_ps, __m256, __m256, __m256, 1)
+test_2 (_mm256_shuffle_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_shuffle_ps, __m256, __m256, __m256, 1)
+test_2 (_mm_cmp_sd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_cmp_ss, __m128, __m128, __m128, 1)
+test_2 (_mm_cmp_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_cmp_ps, __m128, __m128, __m128, 1)
+test_2 (_mm256_cmp_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_cmp_ps, __m256, __m256, __m256, 1)
+test_1 (_mm256_extractf128_pd, __m128d, __m256d, 1)
+test_1 (_mm256_extractf128_ps, __m128, __m256, 1)
+test_1 (_mm256_extractf128_si256, __m128i, __m256i, 1)
+test_1 (_mm256_extract_epi8, int, __m256i, 20)
+test_1 (_mm256_extract_epi16, int, __m256i, 13)
+test_1 (_mm256_extract_epi32, int, __m256i, 6)
+#ifdef __x86_64__
+test_1 (_mm256_extract_epi64, long long, __m256i, 2)
+#endif
+test_1 (_mm_permute_pd, __m128d, __m128d, 1)
+test_1 (_mm256_permute_pd, __m256d, __m256d, 1)
+test_1 (_mm_permute_ps, __m128, __m128, 1)
+test_1 (_mm256_permute_ps, __m256, __m256, 1)
+test_2 (_mm256_permute2f128_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_permute2f128_ps, __m256, __m256, __m256, 1)
+test_2 (_mm256_permute2f128_si256, __m256i, __m256i, __m256i, 1)
+test_2 (_mm256_insertf128_pd, __m256d, __m256d, __m128d, 1)
+test_2 (_mm256_insertf128_ps, __m256, __m256, __m128, 1)
+test_2 (_mm256_insertf128_si256, __m256i, __m256i, __m128i, 1)
+test_2 (_mm256_insert_epi8, __m256i, __m256i, int, 30)
+test_2 (_mm256_insert_epi16, __m256i, __m256i, int, 7)
+test_2 (_mm256_insert_epi32, __m256i, __m256i, int, 3)
+#ifdef __x86_64__
+test_2 (_mm256_insert_epi64, __m256i, __m256i, long long, 1)
+#endif
+test_1 (_mm256_round_pd, __m256d, __m256d, 1)
+test_1 (_mm256_round_ps, __m256, __m256, 1)
+
+/* wmmintrin.h */
+test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1)
+test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1)
+
+/* mmintrin-common.h */
+test_1 (_mm_round_pd, __m128d, __m128d, 1)
+test_1 (_mm_round_ps, __m128, __m128, 1)
+test_2 (_mm_round_sd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_round_ss, __m128, __m128, __m128, 1)
+
+/* smmintrin.h */
+test_2 (_mm_blend_epi16, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_blend_ps, __m128, __m128, __m128, 1)
+test_2 (_mm_blend_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_dp_ps, __m128, __m128, __m128, 1)
+test_2 (_mm_dp_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_insert_ps, __m128, __m128, __m128, 1)
+test_1 (_mm_extract_ps, int, __m128, 1)
+test_2 (_mm_insert_epi8, __m128i, __m128i, int, 1)
+test_2 (_mm_insert_epi32, __m128i, __m128i, int, 1)
+#ifdef __x86_64__
+test_2 (_mm_insert_epi64, __m128i, __m128i, long long, 1)
+#endif
+test_1 (_mm_extract_epi8, int, __m128i, 1)
+test_1 (_mm_extract_epi32, int, __m128i, 1)
+#ifdef __x86_64__
+test_1 (_mm_extract_epi64, long long, __m128i, 1)
+#endif
+test_2 (_mm_mpsadbw_epu8, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrm, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_cmpistri, int, __m128i, __m128i, 1)
+test_4 (_mm_cmpestrm, __m128i, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestri, int, __m128i, int, __m128i, int, 1)
+test_2 (_mm_cmpistra, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrc, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistro, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrs, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrz, int, __m128i, __m128i, 1)
+test_4 (_mm_cmpestra, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrc, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestro, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrs, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
+
+/* tmmintrin.h */
+test_2 (_mm_alignr_epi8, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_alignr_pi8, __m64, __m64, __m64, 1)
+
+/* emmintrin.h */
+test_2 (_mm_shuffle_pd, __m128d, __m128d, __m128d, 1)
+test_1 (_mm_srli_si128, __m128i, __m128i, 1)
+test_1 (_mm_slli_si128, __m128i, __m128i, 1)
+test_1 (_mm_extract_epi16, int, __m128i, 1)
+test_2 (_mm_insert_epi16, __m128i, __m128i, int, 1)
+test_1 (_mm_shufflehi_epi16, __m128i, __m128i, 1)
+test_1 (_mm_shufflelo_epi16, __m128i, __m128i, 1)
+test_1 (_mm_shuffle_epi32, __m128i, __m128i, 1)
+
+/* xmmintrin.h */
+test_2 (_mm_shuffle_ps, __m128, __m128, __m128, 1)
+test_1 (_mm_extract_pi16, int, __m64, 1)
+test_1 (_m_pextrw, int, __m64, 1)
+test_2 (_mm_insert_pi16, __m64, __m64, int, 1)
+test_2 (_m_pinsrw, __m64, __m64, int, 1)
+test_1 (_mm_shuffle_pi16, __m64, __m64, 1)
+test_1 (_m_pshufw, __m64, __m64, 1)
+test_1 (_mm_prefetch, void, void *, _MM_HINT_NTA)
+
+/* bmmintrin.h */
+test_1 (_mm_roti_epi8, __m128i, __m128i, 1)
+test_1 (_mm_roti_epi16, __m128i, __m128i, 1)
+test_1 (_mm_roti_epi32, __m128i, __m128i, 1)
+test_1 (_mm_roti_epi64, __m128i, __m128i, 1)
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-15.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-15.c
new file mode 100644
index 000000000..5a1da7a75
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-15.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse -msse2" } */
+
+/* Test that the intrinsics compile with optimization.  These were not
+   tested in i386-sse-[12].c because these builtins require immediate
+   operands.  */
+
+#include <xmmintrin.h>
+
+__m128
+test_shuf (void)
+{
+  __m128 a = _mm_set1_ps (1.0);
+  __m128 b = _mm_set1_ps (2.0);
+  return _mm_shuffle_ps (a, b, _MM_SHUFFLE (0,1,2,3));
+}
+
+__m64
+test_ins_ext (__m64 a)
+{
+  return _mm_insert_pi16 (a, _mm_extract_pi16 (a, 0), 3);
+}
+
+__m64
+test_shuf2 (__m64 a)
+{
+  return _mm_shuffle_pi16 (a, 0xA5);
+}
+
+void
+test_prefetch (char *p)
+{
+  _mm_prefetch (p, _MM_HINT_T0);
+  _mm_prefetch (p+4, _MM_HINT_T1);
+  _mm_prefetch (p+8, _MM_HINT_T2);
+  _mm_prefetch (p+12, _MM_HINT_NTA);
+}
+
+__m128i
+test__slli_si128 (__m128i a)
+{
+  return _mm_slli_si128 (a, 3);
+}
+
+__m128i
+test__srli_si128 (__m128i a)
+{
+  return _mm_srli_si128 (a, 3);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-16.c
new file mode 100644
index 000000000..e429630cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-16.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -msse" } */
+
+typedef float __vr __attribute__ ((vector_size (16)));
+
+struct vector
+{
+  union
+  {
+    __vr v;
+    float f[4];
+  };
+};
+
+void
+doit ()
+{
+  float f[4];
+  struct vector v;
+
+  f[0] = 0;
+  f[1] = 1;
+  f[2] = 2;
+  f[3] = 3;
+
+  v.v = __builtin_ia32_loadups (f);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-17.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-17.c
new file mode 100644
index 000000000..f7b3d0d1c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-17.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+#include "sse2-check.h"
+#include <xmmintrin.h>
+extern void abort();
+int untrue = 0;
+typedef union {
+  __v4sf v;
+  float f[4];
+} u;
+void foo (u, u) __attribute__((noinline));
+void foo (u a, u b) {
+  if (b.f[0] != 7.0 || b.f[1] != 8.0 || b.f[2] != 3.0 || b.f[3] != 4.0)
+    abort();
+}
+void bar (__v4sf, __v4sf) __attribute__((noinline));
+void bar (__v4sf a __attribute((unused)), __v4sf b __attribute((unused))) { untrue = 0;}
+__v4sf setupa () __attribute((noinline));
+__v4sf setupa () { __v4sf t = { 1.0, 2.0, 3.0, 4.0 }; return t; }
+__v4sf setupb () __attribute((noinline));
+__v4sf setupb () { __v4sf t = { 5.0, 6.0, 7.0, 8.0 }; return t; }
+void __attribute__((noinline))
+sse2_test(void) {
+  u a, b;
+  a.v = setupa ();
+  b.v = setupb ();
+  if (untrue)
+    bar(a.v, b.v);
+  b.v = (__v4sf) _mm_movehl_ps ((__m128)a.v, (__m128)b.v);
+  foo (a, b);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-18.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-18.c
new file mode 100644
index 000000000..fc0224f8f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-18.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -msse2" } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+__m128i foo (char) __attribute__((noinline));
+__m128i foo (char x) {
+  return _mm_set1_epi8(x);
+}
+__m128i bar (char) __attribute__((noinline));
+__m128i bar (char x) {
+  return _mm_set_epi8 (x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x);
+}
+
+static void
+sse2_test (void) {
+  int i, j;
+  union u { __m128i v; char c[16]; };
+  union u x, y;
+
+  for (i = -128; i <= 127; i++)
+    {
+      x.v = foo ((char)i);
+      y.v = bar ((char)i);
+      for (j=0; j<16; j++)
+	if (x.c[j] != y.c[j])
+	  abort();
+    }
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-19.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-19.c
new file mode 100644
index 000000000..43c090bd4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-19.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -msse2" } */
+/* { dg-final { scan-assembler "punpcklbw" } } */
+extern void abort();
+#include <emmintrin.h>
+__m128i foo (char) __attribute__((noinline));
+__m128i foo (char x) {
+  return _mm_set1_epi8(x);
+}
+__m128i bar (char) __attribute__((noinline));
+__m128i bar (char x) {
+  return _mm_set_epi8 (x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x);
+}
+
+main() {
+  int i, j;
+  union u { __m128i v; char c[16]; };
+  union u x, y;
+  for (i = -128; i <= 127; i++)
+    {
+      x.v = foo ((char)i);
+      y.v = bar ((char)i);
+      for (j=0; j<16; j++)
+	if (x.c[j] != y.c[j])
+	  abort();
+    }
+  return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-2.c
new file mode 100644
index 000000000..cbaa5e6a3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -msse" } */
+#include <xmmintrin.h>
+static const __m128 v_sign = {-.0f, -.0f, -.0f, -.0f};
+static const __m128 v_half = {0.5f, 0.5f, 0.5f, 0.5f};
+static const __m128 v_one  = {1.0f, 1.0f, 1.0f, 1.0f};
+static inline __m128 insn_ABS (__m128 a)
+{
+  return _mm_andnot_ps (v_sign, a);
+}
+__m128 voodoo (__m128 a)
+{
+  __m128 x = insn_ABS (a), y = _mm_rsqrt_ps (x);
+  y = _mm_add_ps (_mm_mul_ps (_mm_sub_ps (_mm_setzero_ps(), _mm_sub_ps (_mm_mul_ps (x, _mm_add_ps (_mm_mul_ps (y, y), _mm_setzero_ps())), v_one)), _mm_add_ps (_mm_mul_ps (y, v_half), _mm_setzero_ps())), y);
+  return y;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-20.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-20.c
new file mode 100644
index 000000000..5aa8f7a28
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-20.c
@@ -0,0 +1,26 @@
+/* PR target/13685 */
+/* { dg-options "-Os -msse" } */
+
+typedef float __m128 __attribute__ ((vector_size (16)));
+typedef int __m64 __attribute__ ((vector_size (8)));
+
+int puts (const char *s);
+void foo (__m128 *, __m64 *, int);
+
+int main (void)
+{
+  foo (0, 0, 0);
+  return 0;
+}
+
+void foo (__m128 *dst, __m64 *src, int n)
+{
+  __m128 xmm0 = { 0 };
+  while (n > 64)
+    {
+      puts ("");
+      xmm0 = __builtin_ia32_cvtpi2ps (xmm0, *src);
+      *dst = xmm0;
+      n --;
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-21.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-21.c
new file mode 100644
index 000000000..ca4c114d8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-21.c
@@ -0,0 +1,24 @@
+/* Test that we don't generate a fisttp instruction when -mno-sse3.  */
+/* { dg-do compile } */
+/* { dg-options "-O -mfpmath=387 -march=nocona -mno-sse3" } */
+/* { dg-final { scan-assembler-not "fisttp" } } */
+struct foo
+{
+ long a;
+ long b;
+};
+
+extern double c;
+
+extern unsigned long long baz (void);
+
+int
+walrus (const struct foo *input)
+{
+    unsigned long long d;
+
+    d = baz ()
+      + (unsigned long long) (((double) input->a * 1000000000
+			      + (double) input->b) * c);
+    return (d ? 1 : 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-22.c
new file mode 100644
index 000000000..f530e54ec
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-22.c
@@ -0,0 +1,171 @@
+/* Same as sse-14, except converted to use #pragma GCC option.  */
+/* { dg-do compile } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration" } */
+
+#include <mm_malloc.h>
+
+/* Test that the intrinsics compile without optimization.  All of them are
+   defined as inline functions in {,x,e,p,t,s,w,a,b}mmintrin.h  and mm3dnow.h
+   that reference the proper builtin functions.  Defining away "extern" and
+   "__inline" results in all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+#define _CONCAT(x,y) x ## y
+
+#define test_1(func, type, op1_type, imm)				\
+  type _CONCAT(_,func) (op1_type A, int const I)			\
+  { return func (A, imm); }
+
+#define test_1x(func, type, op1_type, imm1, imm2)			\
+  type _CONCAT(_,func) (op1_type A, int const I, int const L)		\
+  { return func (A, imm1, imm2); }
+
+#define test_2(func, type, op1_type, op2_type, imm)			\
+  type _CONCAT(_,func) (op1_type A, op2_type B, int const I)		\
+  { return func (A, B, imm); }
+
+#define test_2x(func, type, op1_type, op2_type, imm1, imm2)		\
+  type _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L) \
+  { return func (A, B, imm1, imm2); }
+
+#define test_4(func, type, op1_type, op2_type, op3_type, op4_type, imm)	\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, op4_type D, int const I)		\
+  { return func (A, B, C, D, imm); }
+
+
+#ifndef DIFFERENT_PRAGMAS
+#pragma GCC target ("mmx,3dnow,sse,sse2,sse3,ssse3,sse4.1,sse4.2,sse5,aes,pclmul")
+#endif
+
+/* Following intrinsics require immediate arguments.  They
+   are defined as macros for non-optimized compilations. */
+
+/* mmintrin.h (MMX).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("mmx")
+#endif
+#include <mmintrin.h>
+
+/* mm3dnow.h (3DNOW).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("3dnow")
+#endif
+#include <mm3dnow.h>
+
+/* xmmintrin.h (SSE).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("sse")
+#endif
+#include <xmmintrin.h>
+test_2 (_mm_shuffle_ps, __m128, __m128, __m128, 1)
+test_1 (_mm_extract_pi16, int, __m64, 1)
+test_1 (_m_pextrw, int, __m64, 1)
+test_2 (_mm_insert_pi16, __m64, __m64, int, 1)
+test_2 (_m_pinsrw, __m64, __m64, int, 1)
+test_1 (_mm_shuffle_pi16, __m64, __m64, 1)
+test_1 (_m_pshufw, __m64, __m64, 1)
+test_1 (_mm_prefetch, void, void *, _MM_HINT_NTA)
+
+/* emmintrin.h (SSE2).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("sse2")
+#endif
+#include <emmintrin.h>
+test_2 (_mm_shuffle_pd, __m128d, __m128d, __m128d, 1)
+test_1 (_mm_srli_si128, __m128i, __m128i, 1)
+test_1 (_mm_slli_si128, __m128i, __m128i, 1)
+test_1 (_mm_extract_epi16, int, __m128i, 1)
+test_2 (_mm_insert_epi16, __m128i, __m128i, int, 1)
+test_1 (_mm_shufflehi_epi16, __m128i, __m128i, 1)
+test_1 (_mm_shufflelo_epi16, __m128i, __m128i, 1)
+test_1 (_mm_shuffle_epi32, __m128i, __m128i, 1)
+
+/* pmmintrin.h (SSE3).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("sse3")
+#endif
+#include <pmmintrin.h>
+
+/* tmmintrin.h (SSSE3).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("ssse3")
+#endif
+#include <tmmintrin.h>
+test_2 (_mm_alignr_epi8, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_alignr_pi8, __m64, __m64, __m64, 1)
+
+/* ammintrin.h (SSE4A).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("sse4a")
+#endif
+#include <ammintrin.h>
+test_1x (_mm_extracti_si64, __m128i, __m128i, 1, 1)
+test_2x (_mm_inserti_si64, __m128i, __m128i, __m128i, 1, 1)
+
+/* smmintrin.h (SSE4.1).  */
+/* nmmintrin.h (SSE4.2).  */
+/* Note, nmmintrin.h includes smmintrin.h, and smmintrin.h checks for the
+   #ifdef.  So just set the option to SSE4.2.  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("sse4.2")
+#endif
+#include <nmmintrin.h>
+test_2 (_mm_blend_epi16, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_blend_ps, __m128, __m128, __m128, 1)
+test_2 (_mm_blend_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_dp_ps, __m128, __m128, __m128, 1)
+test_2 (_mm_dp_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_insert_ps, __m128, __m128, __m128, 1)
+test_1 (_mm_extract_ps, int, __m128, 1)
+test_2 (_mm_insert_epi8, __m128i, __m128i, int, 1)
+test_2 (_mm_insert_epi32, __m128i, __m128i, int, 1)
+#ifdef __x86_64__
+test_2 (_mm_insert_epi64, __m128i, __m128i, long long, 1)
+#endif
+test_1 (_mm_extract_epi8, int, __m128i, 1)
+test_1 (_mm_extract_epi32, int, __m128i, 1)
+#ifdef __x86_64__
+test_1 (_mm_extract_epi64, long long, __m128i, 1)
+#endif
+test_2 (_mm_mpsadbw_epu8, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrm, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_cmpistri, int, __m128i, __m128i, 1)
+test_4 (_mm_cmpestrm, __m128i, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestri, int, __m128i, int, __m128i, int, 1)
+test_2 (_mm_cmpistra, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrc, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistro, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrs, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrz, int, __m128i, __m128i, 1)
+test_4 (_mm_cmpestra, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrc, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestro, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrs, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
+
+/* bmmintrin.h (SSE5).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("sse5")
+#endif
+#include <bmmintrin.h>
+test_1 (_mm_roti_epi8, __m128i, __m128i, 1)
+test_1 (_mm_roti_epi16, __m128i, __m128i, 1)
+test_1 (_mm_roti_epi32, __m128i, __m128i, 1)
+test_1 (_mm_roti_epi64, __m128i, __m128i, 1)
+
+/* wmmintrin.h (AES/PCLMUL).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("aes,pclmul")
+#endif
+#include <wmmintrin.h>
+test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1)
+test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1)
+
+/* mmintrin-common.h */
+test_1 (_mm_round_pd, __m128d, __m128d, 1)
+test_1 (_mm_round_ps, __m128, __m128, 1)
+test_2 (_mm_round_sd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_round_ss, __m128, __m128, __m128, 1)
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-23.c
new file mode 100644
index 000000000..4488568f4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -0,0 +1,108 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8" } */
+
+#include <mm_malloc.h>
+
+/* Test that the intrinsics compile with optimization.  All of them are
+   defined as inline functions in {,x,e,p,t,s,w,a,b}mmintrin.h and mm3dnow.h
+   that reference the proper builtin functions.  Defining away "extern" and
+   "__inline" results in all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+/* Following intrinsics require immediate arguments. */
+
+/* ammintrin.h */
+#define __builtin_ia32_extrqi(X, I, L)  __builtin_ia32_extrqi(X, 1, 1)
+#define __builtin_ia32_insertqi(X, Y, I, L) __builtin_ia32_insertqi(X, Y, 1, 1)
+
+/* wmmintrin.h */
+#define __builtin_ia32_aeskeygenassist128(X, C) __builtin_ia32_aeskeygenassist128(X, 1)
+#define __builtin_ia32_pclmulqdq128(X, Y, I) __builtin_ia32_pclmulqdq128(X, Y, 1)
+
+/* mmintrin-common.h */
+#define __builtin_ia32_roundpd(V, M) __builtin_ia32_roundpd(V, 1)
+#define __builtin_ia32_roundsd(D, V, M) __builtin_ia32_roundsd(D, V, 1)
+#define __builtin_ia32_roundps(V, M) __builtin_ia32_roundps(V, 1)
+#define __builtin_ia32_roundss(D, V, M) __builtin_ia32_roundss(D, V, 1)
+
+/* smmintrin.h */
+#define __builtin_ia32_pblendw128(X, Y, M) __builtin_ia32_pblendw128 (X, Y, 1)
+#define __builtin_ia32_blendps(X, Y, M) __builtin_ia32_blendps(X, Y, 1)
+#define __builtin_ia32_blendpd(X, Y, M) __builtin_ia32_blendpd(X, Y, 1)
+#define __builtin_ia32_dpps(X, Y, M) __builtin_ia32_dpps(X, Y, 1)
+#define __builtin_ia32_dppd(X, Y, M) __builtin_ia32_dppd(X, Y, 1)
+#define __builtin_ia32_insertps128(D, S, N) __builtin_ia32_insertps128(D, S, 1)
+#define __builtin_ia32_vec_ext_v4sf(X, N) __builtin_ia32_vec_ext_v4sf(X, 1)
+#define __builtin_ia32_vec_set_v16qi(D, S, N) __builtin_ia32_vec_set_v16qi(D, S, 1)
+#define __builtin_ia32_vec_set_v4si(D, S, N) __builtin_ia32_vec_set_v4si(D, S, 1)
+#define __builtin_ia32_vec_set_v2di(D, S, N) __builtin_ia32_vec_set_v2di(D, S, 1)
+#define __builtin_ia32_vec_ext_v16qi(X, N) __builtin_ia32_vec_ext_v16qi(X, 1)
+#define __builtin_ia32_vec_ext_v4si(X, N) __builtin_ia32_vec_ext_v4si(X, 1)
+#define __builtin_ia32_vec_ext_v2di(X, N) __builtin_ia32_vec_ext_v2di(X, 1)
+#define __builtin_ia32_mpsadbw128(X, Y, M) __builtin_ia32_mpsadbw128(X, Y, 1)
+#define __builtin_ia32_pcmpistrm128(X, Y, M) \
+  __builtin_ia32_pcmpistrm128(X, Y, 1)
+#define __builtin_ia32_pcmpistri128(X, Y, M) \
+  __builtin_ia32_pcmpistri128(X, Y, 1)
+#define __builtin_ia32_pcmpestrm128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestrm128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestri128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestri128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpistria128(X, Y, M) \
+  __builtin_ia32_pcmpistria128(X, Y, 1)
+#define __builtin_ia32_pcmpistric128(X, Y, M) \
+  __builtin_ia32_pcmpistric128(X, Y, 1)
+#define __builtin_ia32_pcmpistrio128(X, Y, M) \
+  __builtin_ia32_pcmpistrio128(X, Y, 1)
+#define __builtin_ia32_pcmpistris128(X, Y, M) \
+  __builtin_ia32_pcmpistris128(X, Y, 1)
+#define __builtin_ia32_pcmpistriz128(X, Y, M) \
+  __builtin_ia32_pcmpistriz128(X, Y, 1)
+#define __builtin_ia32_pcmpestria128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestria128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestric128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestric128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestrio128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestrio128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestris128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestris128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestriz128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestriz128(X, LX, Y, LY, 1)
+
+/* tmmintrin.h */
+#define __builtin_ia32_palignr128(X, Y, N) __builtin_ia32_palignr128(X, Y, 8)
+#define __builtin_ia32_palignr(X, Y, N) __builtin_ia32_palignr(X, Y, 8)
+
+/* emmintrin.h */
+#define __builtin_ia32_psrldqi128(A, B) __builtin_ia32_psrldqi128(A, 8)
+#define __builtin_ia32_pslldqi128(A, B) __builtin_ia32_pslldqi128(A, 8)
+#define __builtin_ia32_pshufhw(A, N) __builtin_ia32_pshufhw(A, 0)
+#define __builtin_ia32_pshuflw(A, N) __builtin_ia32_pshuflw(A, 0)
+#define __builtin_ia32_pshufd(A, N) __builtin_ia32_pshufd(A, 0)
+#define __builtin_ia32_vec_set_v8hi(A, D, N) \
+  __builtin_ia32_vec_set_v8hi(A, D, 0)
+#define __builtin_ia32_vec_ext_v8hi(A, N) __builtin_ia32_vec_ext_v8hi(A, 0)
+#define __builtin_ia32_shufpd(A, B, N) __builtin_ia32_shufpd(A, B, 0)
+
+/* xmmintrin.h */
+#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, A, _MM_HINT_NTA)
+#define __builtin_ia32_pshufw(A, N) __builtin_ia32_pshufw(A, 0)
+#define __builtin_ia32_vec_set_v4hi(A, D, N) \
+  __builtin_ia32_vec_set_v4hi(A, D, 0)
+#define __builtin_ia32_vec_ext_v4hi(A, N) __builtin_ia32_vec_ext_v4hi(A, 0)
+#define __builtin_ia32_shufps(A, B, N) __builtin_ia32_shufps(A, B, 0)
+
+/* bmmintrin.h */
+#define __builtin_ia32_protbi(A, B) __builtin_ia32_protbi(A,1)
+#define __builtin_ia32_protwi(A, B) __builtin_ia32_protwi(A,1)
+#define __builtin_ia32_protdi(A, B) __builtin_ia32_protdi(A,1)
+#define __builtin_ia32_protqi(A, B) __builtin_ia32_protqi(A,1)
+
+
+#pragma GCC target ("3dnow,sse4,sse5,aes,pclmul")
+#include <wmmintrin.h>
+#include <bmmintrin.h>
+#include <smmintrin.h>
+#include <mm3dnow.h>
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-3.c
new file mode 100644
index 000000000..338b7c60b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-3.c
@@ -0,0 +1,36 @@
+/* PR target/21149 */
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#include "sse-check.h"
+
+#include <xmmintrin.h>
+
+void
+__attribute__((noinline))
+check (__m128 x, float a, float b, float c, float d)
+{
+  union { __m128 m; float f[4]; } u;
+  u.m = x;
+  if (u.f[0] != a || u.f[1] != b || u.f[2] != c || u.f[3] != d)
+    abort ();
+}
+
+static inline
+void
+foo (__m128 *x)
+{
+  __m128 y = _mm_setzero_ps ();
+  __m128 v = _mm_movehl_ps (y, *x);
+  __m128 w = _mm_movehl_ps (*x, y);
+  check (*x, 9, 1, 2, -3);
+  check (v, 2, -3, 0, 0);
+  check (w, 0, 0, 2, -3);
+}
+
+static void
+sse_test (void)
+{
+  __m128 y = _mm_set_ps (-3, 2, 1, 9);
+  foo (&y);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-4.c
new file mode 100644
index 000000000..394ad9d7e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-4.c
@@ -0,0 +1,10 @@
+/* This testcase caused a buffer overflow in simplify_immed_subreg.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <emmintrin.h>
+
+__m128i foo (__m128i x)
+{
+  return _mm_min_epu8 (x, _mm_set1_epi8 (10));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-5.c
new file mode 100644
index 000000000..c3ed8f267
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-5.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Winline -O2 -march=i386" } */
+
+typedef double v2df __attribute__ ((vector_size (16)));
+v2df p;
+q(v2df t) /* { dg-warning "SSE" "" } */
+{
+	p=t;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-6.c
new file mode 100644
index 000000000..930b23f1f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-6.c
@@ -0,0 +1,304 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+#include <string.h>
+
+#define SHIFT (4)
+
+typedef union {
+  __m128i v;
+  unsigned int s[4];
+  unsigned short int t[8];
+  unsigned long long u[2];
+  unsigned char c[16];
+}vecInLong;
+
+void sse2_tests (void) __attribute__((noinline));
+void dump128_16 (char *, char *, vecInLong);
+void dump128_32 (char *, char *, vecInLong);
+void dump128_64 (char *, char *, vecInLong);
+void dump128_128 (char *, char *, vecInLong);
+int check (const char *, const char *[]);
+
+char buf[8000];
+char comparison[8000];
+static int errors = 0;
+
+vecInLong a128, b128, c128, d128, e128, f128;
+__m128i m128_16, m128_32, s128, m128_64, m128_128;
+__m64 m64_16, s64, m64_32, m64_64;
+
+const char *reference_sse2[] = {
+  "_mm_srai_epi16 0012 0012 0012 0012 0012 0012 0012 0012 \n",
+  "_mm_sra_epi16 0012 0012 0012 0012 0012 0012 0012 0012 \n",
+  "_mm_srai_epi32 00123456 00123456 00123456 00123456 \n",
+  "_mm_sra_epi32 00123456 00123456 00123456 00123456 \n",
+  "_mm_srli_epi16 0012 0012 0012 0012 0012 0012 0012 0012 \n",
+  "_mm_srl_epi16 0012 0012 0012 0012 0012 0012 0012 0012 \n",
+  "_mm_srli_epi32 00123456 00123456 00123456 00123456 \n",
+  "_mm_srl_epi32 00123456 00123456 00123456 00123456 \n",
+  "_mm_srli_epi64 00123456789abcde 00123456789abcde \n",
+  "_mm_srl_epi64 00123456789abcde 00123456789abcde \n",
+  "_mm_srli_si128 (byte shift)  00000000ffeeddccbbaa998877665544\n",
+  "_mm_slli_epi16 1230 1230 1230 1230 1230 1230 1230 1230 \n",
+  "_mm_sll_epi16 1230 1230 1230 1230 1230 1230 1230 1230 \n",
+  "_mm_slli_epi32 12345670 12345670 12345670 12345670 \n",
+  "_mm_sll_epi32 12345670 12345670 12345670 12345670 \n",
+  "_mm_slli_epi64 123456789abcdef0 123456789abcdef0 \n",
+  "_mm_sll_epi64 123456789abcdef0 123456789abcdef0 \n",
+  "_mm_sll_si128 (byte shift) bbaa9988776655443322110000000000\n",
+  "_mm_shuffle_epi32 ffeeddcc bbaa9988 77665544 33221100 \n",
+  "_mm_shuffelo_epi16 7766 5544 3322 1100 9988 bbaa ddcc ffee \n",
+  "_mm_shuffehi_epi16 1100 3322 5544 7766 ffee ddcc bbaa 9988 \n",
+  ""
+};
+
+static void
+sse2_test (void)
+{
+  a128.s[0] = 0x01234567;
+  a128.s[1] = 0x01234567;
+  a128.s[2] = 0x01234567;
+  a128.s[3] = 0x01234567;
+
+  m128_32 = a128.v;
+
+  d128.u[0] = 0x0123456789abcdefULL;
+  d128.u[1] = 0x0123456789abcdefULL;
+
+  m128_64 = d128.v;
+
+  /* This is the 128-bit constant 0x00112233445566778899aabbccddeeff,
+     expressed as two little-endian 64-bit words.  */
+  e128.u[0] = 0x7766554433221100ULL;
+  e128.u[1] = 0xffeeddccbbaa9988ULL;
+
+  f128.t[0] = 0x0123;
+  f128.t[1] = 0x0123;
+  f128.t[2] = 0x0123;
+  f128.t[3] = 0x0123;
+  f128.t[4] = 0x0123;
+  f128.t[5] = 0x0123;
+  f128.t[6] = 0x0123;
+  f128.t[7] = 0x0123;
+
+  m128_16 = f128.v;
+
+  m128_128 = e128.v;
+
+  b128.s[0] = SHIFT;
+  b128.s[1] = 0;
+  b128.s[2] = 0;
+  b128.s[3] = 0;
+
+  s128 = b128.v;
+
+  sse2_tests();
+  check (buf, reference_sse2);
+#ifdef DEBUG
+  printf ("sse2 testing:\n");
+  printf (buf);
+  printf ("\ncomparison:\n");
+  printf (comparison);
+#endif
+  buf[0] = '\0';
+
+  if (errors != 0)
+    abort ();
+}
+
+void __attribute__((noinline))
+sse2_tests (void)
+{
+  /* psraw */
+  c128.v = _mm_srai_epi16 (m128_16, SHIFT);
+  dump128_16 (buf, "_mm_srai_epi16", c128);
+  c128.v = _mm_sra_epi16 (m128_16, s128);
+  dump128_16 (buf, "_mm_sra_epi16", c128);
+
+  /* psrad */
+  c128.v = _mm_srai_epi32 (m128_32, SHIFT);
+  dump128_32 (buf, "_mm_srai_epi32", c128);
+  c128.v = _mm_sra_epi32 (m128_32, s128);
+  dump128_32 (buf, "_mm_sra_epi32", c128);
+
+  /* psrlw */
+  c128.v = _mm_srli_epi16 (m128_16, SHIFT);
+  dump128_16 (buf, "_mm_srli_epi16", c128);
+  c128.v = _mm_srl_epi16 (m128_16, s128);
+  dump128_16 (buf, "_mm_srl_epi16", c128);
+
+  /* psrld */
+  c128.v = _mm_srli_epi32 (m128_32, SHIFT);
+  dump128_32 (buf, "_mm_srli_epi32", c128);
+  c128.v = _mm_srl_epi32 (m128_32, s128);
+  dump128_32 (buf, "_mm_srl_epi32", c128);
+
+  /* psrlq */
+  c128.v = _mm_srli_epi64 (m128_64, SHIFT);
+  dump128_64 (buf, "_mm_srli_epi64", c128);
+  c128.v = _mm_srl_epi64 (m128_64, s128);
+  dump128_64 (buf, "_mm_srl_epi64", c128);
+
+  /* psrldq */
+  c128.v = _mm_srli_si128 (m128_128, SHIFT);
+  dump128_128 (buf, "_mm_srli_si128 (byte shift) ", c128);
+
+  /* psllw */
+  c128.v = _mm_slli_epi16 (m128_16, SHIFT);
+  dump128_16 (buf, "_mm_slli_epi16", c128);
+  c128.v = _mm_sll_epi16 (m128_16, s128);
+  dump128_16 (buf, "_mm_sll_epi16", c128);
+
+  /* pslld */
+  c128.v = _mm_slli_epi32 (m128_32, SHIFT);
+  dump128_32 (buf, "_mm_slli_epi32", c128);
+  c128.v = _mm_sll_epi32 (m128_32, s128);
+  dump128_32 (buf, "_mm_sll_epi32", c128);
+
+  /* psllq */
+  c128.v = _mm_slli_epi64 (m128_64, SHIFT);
+  dump128_64 (buf, "_mm_slli_epi64", c128);
+  c128.v = _mm_sll_epi64 (m128_64, s128);
+  dump128_64 (buf, "_mm_sll_epi64", c128);
+
+  /* pslldq */
+  c128.v = _mm_slli_si128 (m128_128, SHIFT);
+  dump128_128 (buf, "_mm_sll_si128 (byte shift)", c128);
+
+  /* Shuffle constant 0x1b == 0b_00_01_10_11, e.g. swap words: ABCD => DCBA.  */
+
+  /* pshufd */
+  c128.v = _mm_shuffle_epi32 (m128_128, 0x1b);
+  dump128_32 (buf, "_mm_shuffle_epi32", c128);
+
+  /* pshuflw */
+  c128.v = _mm_shufflelo_epi16 (m128_128, 0x1b);
+  dump128_16 (buf, "_mm_shuffelo_epi16", c128);
+
+  /* pshufhw */
+  c128.v = _mm_shufflehi_epi16 (m128_128, 0x1b);
+  dump128_16 (buf, "_mm_shuffehi_epi16", c128);
+}
+
+void
+dump128_16 (char *buf, char *name, vecInLong x)
+{
+  int i;
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+  for (i=0; i<8; i++)
+    {
+      sprintf (p, "%4.4x ", x.t[i]);
+      p += strlen (p);
+    }
+  strcat (p, "\n");
+}
+
+void
+dump128_32 (char *buf, char *name, vecInLong x)
+{
+  int i;
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+  for (i=0; i<4; i++)
+    {
+      sprintf (p, "%8.8x ", x.s[i]);
+      p += strlen (p);
+    }
+  strcat (p, "\n");
+}
+
+void
+dump128_64 (char *buf, char *name, vecInLong x)
+{
+  int i;
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+  for (i=0; i<2; i++)
+    {
+#if defined(_WIN32) && !defined(__CYGWIN__)
+      sprintf (p, "%16.16I64x ", x.u[i]);
+#else
+      sprintf (p, "%16.16llx ", x.u[i]);
+#endif
+      p += strlen (p);
+    }
+  strcat (p, "\n");
+}
+
+void
+dump128_128 (char *buf, char *name, vecInLong x)
+{
+  int i;
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+  for (i=15; i>=0; i--)
+    {
+      /* This is cheating; we don't have a 128-bit int format code.
+	 Running the loop backwards to compensate for the
+	 little-endian layout. */
+      sprintf (p, "%2.2x", x.c[i]);
+      p += strlen (p);
+    }
+  strcat (p, "\n");
+}
+
+int
+check (const char *input, const char *reference[])
+{
+  int broken, i, j, len;
+  const char *p_input;
+  char *p_comparison;
+  int new_errors = 0;
+
+  p_comparison = &comparison[0];
+  p_input = input;
+
+  for (i = 0; *reference[i] != '\0'; i++)
+    {
+      broken = 0;
+      len = strlen (reference[i]);
+      for (j = 0; j < len; j++)
+	{
+	  /* Ignore the terminating NUL characters at the end of every string in 'reference[]'.  */
+	  if (!broken && *p_input != reference[i][j])
+	    {
+	      *p_comparison = '\0';
+	      strcat (p_comparison, " >>> ");
+	      p_comparison += strlen (p_comparison);
+	      new_errors++;
+	      broken = 1;
+	    }
+	  *p_comparison = *p_input;
+	  p_comparison++;
+	  p_input++;
+	}
+      if (broken)
+	{
+	  *p_comparison = '\0';
+	  strcat (p_comparison, "expected:\n");
+	  strcat (p_comparison, reference[i]);
+	  p_comparison += strlen (p_comparison);
+	}
+    }
+  *p_comparison = '\0';
+  strcat (p_comparison, new_errors ? "failure\n\n" : "O.K.\n\n") ;
+  errors += new_errors;
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-7.c
new file mode 100644
index 000000000..12b88ca53
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-7.c
@@ -0,0 +1,123 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#include "sse-check.h"
+
+#include <xmmintrin.h>
+#include <string.h>
+
+#define SHIFT (4)
+
+typedef union {
+  __m64 v;
+  unsigned char c[8];
+  unsigned short int s[4];
+  unsigned long long t;
+  unsigned int u[2];
+}vecInWord;
+
+void sse_tests (void) __attribute__((noinline));
+void dump64_16 (char *, char *, vecInWord);
+int check (const char *, const char *[]);
+
+char buf[8000];
+char comparison[8000];
+static int errors = 0;
+
+vecInWord c64, e64;
+__m64 m64_64;
+
+const char *reference_sse[] = {
+  "_mm_shuffle_pi16 0123 4567 89ab cdef \n",
+  ""
+};
+
+static void
+sse_test (void)
+{
+  e64.t  = 0x0123456789abcdefULL;
+
+  m64_64 = e64.v;
+
+  sse_tests();
+  check (buf, reference_sse);
+#ifdef DEBUG
+  printf ("sse testing:\n");
+  printf (buf);
+  printf ("\ncomparison:\n");
+  printf (comparison);
+#endif
+  buf[0] = '\0';
+
+  if (errors != 0)
+    abort ();
+}
+
+void __attribute__((noinline))
+sse_tests (void)
+{
+  /* pshufw */
+  c64.v = _mm_shuffle_pi16 (m64_64, 0x1b);
+  dump64_16 (buf, "_mm_shuffle_pi16", c64);
+}
+
+void
+dump64_16 (char *buf, char *name, vecInWord x)
+{
+  int i;
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+  for (i=0; i<4; i++)
+    {
+      sprintf (p, "%4.4x ", x.s[i]);
+      p += strlen (p);
+    }
+  strcat (p, "\n");
+}
+
+int
+check (const char *input, const char *reference[])
+{
+  int broken, i, j, len;
+  const char *p_input;
+  char *p_comparison;
+  int new_errors = 0;
+
+  p_comparison = &comparison[0];
+  p_input = input;
+
+  for (i = 0; *reference[i] != '\0'; i++)
+    {
+      broken = 0;
+      len = strlen (reference[i]);
+      for (j = 0; j < len; j++)
+	{
+	  /* Ignore the terminating NUL characters at the end of every string in 'reference[]'.  */
+	  if (!broken && *p_input != reference[i][j])
+	    {
+	      *p_comparison = '\0';
+	      strcat (p_comparison, " >>> ");
+	      p_comparison += strlen (p_comparison);
+	      new_errors++;
+	      broken = 1;
+	    }
+	  *p_comparison = *p_input;
+	  p_comparison++;
+	  p_input++;
+	}
+      if (broken)
+	{
+	  *p_comparison = '\0';
+	  strcat (p_comparison, "expected:\n");
+	  strcat (p_comparison, reference[i]);
+	  p_comparison += strlen (p_comparison);
+	}
+    }
+  *p_comparison = '\0';
+  strcat (p_comparison, new_errors ? "failure\n\n" : "O.K.\n\n") ;
+  errors += new_errors;
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-8.c
new file mode 100644
index 000000000..b6cb5c824
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-8.c
@@ -0,0 +1,14 @@
+/* PR target/14343 */
+/* Origin: <Pawe Sikora <pluto@ds14.agh.edu.pl> */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-march=pentium3" } */
+
+int main() 
+{ 
+  typedef long long int v __attribute__ ((vector_size (16))); 
+  v a, b; 
+  a = b; 
+  return 0; 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-9.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-9.c
new file mode 100644
index 000000000..0106cb52f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-9.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#include "sse-check.h"
+
+#include <xmmintrin.h>
+#include <stddef.h>
+#include <string.h>
+
+static void
+sse_test (void)
+{
+  int alignment, n;
+  void *ptr;
+  int errors = 0;
+  const char test [] = "This is a test.";
+
+  for (alignment = 1; alignment <= (1 << 20); alignment += alignment)
+    {
+      ptr = _mm_malloc (alignment, alignment);
+      if (((ptrdiff_t) ptr) & (alignment - 1))
+	abort ();
+      if (ptr)
+	{
+	  n = alignment > sizeof test ? sizeof test : alignment;
+	  memcpy (ptr, test, n);
+	  if (memcmp (ptr, test, n) != 0)
+	    errors++;
+	  _mm_free (ptr);
+	}
+      else
+	errors++;
+    }
+   
+  if (errors != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-addps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-addps-1.c
new file mode 100644
index 000000000..2aa1cfa41
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-addps-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_add_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = test (s1.x, s2.x); 
+  
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] + s2.a[i];   
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-addss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-addss-1.c
new file mode 100644
index 000000000..911a6cd91
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-addss-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_add_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = test (s1.x, s2.x); 
+
+  e[0] = s1.a[0] + s2.a[0];
+  e[1] = s1.a[1];
+  e[2] = s1.a[2];
+  e[3] = s1.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-andnps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-andnps-1.c
new file mode 100644
index 000000000..06d1e07dd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-andnps-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_andnot_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  int source1[4]={34, 545, 955, 67};
+  int source2[4]={67, 4, 57, 897};
+  int e[4];
+   
+  s1.x = _mm_loadu_ps ((float *)source1);
+  s2.x = _mm_loadu_ps ((float *)source2);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = (~source1[0]) & source2[0];
+  e[1] = (~source1[1]) & source2[1];
+  e[2] = (~source1[2]) & source2[2];
+  e[3] = (~source1[3]) & source2[3];
+
+  if (check_union128 (u, (float *)e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-andps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-andps-1.c
new file mode 100644
index 000000000..aa46b8a28
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-andps-1.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_and_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  union
+  {
+    float f[4];
+    int   i[4];
+  }source1, source2, e;
+
+  s1.x = _mm_set_ps (34, 545, 955, 67);
+  s2.x = _mm_set_ps (67, 4, 57, 897);
+
+  _mm_storeu_ps (source1.f, s1.x);
+  _mm_storeu_ps (source2.f, s2.x);
+
+  u.x = test (s1.x, s2.x); 
+   
+  e.i[0] = source1.i[0] & source2.i[0];
+  e.i[1] = source1.i[1] & source2.i[1];
+  e.i[2] = source1.i[2] & source2.i[2];
+  e.i[3] = source1.i[3] & source2.i[3];
+
+  if (check_union128 (u, e.f))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-check.h
new file mode 100644
index 000000000..79ea48155
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-check.h
@@ -0,0 +1,22 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include "m128-check.h"
+
+#include "cpuid.h"
+
+static void sse_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run SSE test only if host has SSE support.  */
+  if (edx & bit_SSE)
+    sse_test ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-1.c
new file mode 100644
index 000000000..2892a70a6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-1.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_comieq_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] == s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-2.c
new file mode 100644
index 000000000..63b6d6d11
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_comilt_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] < s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-3.c
new file mode 100644
index 000000000..75ac4e4fa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-3.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_comile_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] <= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-4.c
new file mode 100644
index 000000000..ceeeca794
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-4.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_comigt_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] > s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-5.c
new file mode 100644
index 000000000..8f503512f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-5.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_comige_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] >= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-6.c
new file mode 100644
index 000000000..38df9b8e4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-comiss-6.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_comineq_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] != s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-1.c
new file mode 100644
index 000000000..e5435b6b7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-1.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 p, int b)
+{
+  return _mm_cvtsi32_ss (p, b); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1;
+  int b = 498;
+  float e[4] = { 24.43, 68.346, 43.35, 546.46 };
+   
+  s1.x = _mm_set_ps (e[3], e[2], e[1], e[0]);
+  u.x = test (s1.x, b); 
+  e[0] = (float)b;  
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c
new file mode 100644
index 000000000..aa74e11ec
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 p, long long b)
+{
+  return _mm_cvtsi64_ss (p, b); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1;
+  long long b = 4294967295133LL;
+  float e[4] = { 24.43, 68.346, 43.35, 546.46 };
+   
+  s1.x = _mm_set_ps (e[3], e[2], e[1], e[0]);
+  u.x = test (s1.x, b); 
+  e[0] = (float)b;  
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvtss2si-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvtss2si-1.c
new file mode 100644
index 000000000..574062665
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvtss2si-1.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int
+__attribute__((noinline, unused))
+test (__m128 p)
+{
+  return _mm_cvtss_si32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128 s1;
+  int d;
+  int e;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  d = test (s1.x); 
+  e = (int)s1.a[0];  
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c
new file mode 100644
index 000000000..e136b7198
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static long long
+__attribute__((noinline, unused))
+test (__m128 p)
+{
+  return _mm_cvtss_si64 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128 s1;
+  long long d;
+  long long e;
+   
+  s1.x = _mm_set_ps (344.4, 68.346, 43.35, 429496729501.4);
+  d = test (s1.x); 
+  e = (long long)s1.a[0];  
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvttss2si-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvttss2si-1.c
new file mode 100644
index 000000000..8edc197ea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvttss2si-1.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int
+__attribute__((noinline, unused))
+test (__m128 p)
+{
+  return _mm_cvttss_si32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128 s1;
+  int d;
+  int e;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  d = test (s1.x); 
+  e = (int)s1.a[0];  
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c
new file mode 100644
index 000000000..94e831e78
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static long long
+__attribute__((noinline, unused))
+test (__m128 p)
+{
+  return _mm_cvttss_si64 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128 s1;
+  long long d;
+  long long e;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 429496729501.4);
+  d = test (s1.x); 
+  e = (long long)s1.a[0];  
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-divps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-divps-1.c
new file mode 100644
index 000000000..d4d441aeb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-divps-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_div_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] / s2.a[0];
+  e[1] = s1.a[1] / s2.a[1];
+  e[2] = s1.a[2] / s2.a[2];
+  e[3] = s1.a[3] / s2.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-divss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-divss-1.c
new file mode 100644
index 000000000..e7449496e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-divss-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_div_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] / s2.a[0];
+  e[1] = s1.a[1];
+  e[2] = s1.a[2];
+  e[3] = s1.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-init-v4hi-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-init-v4hi-1.c
new file mode 100644
index 000000000..5c2547727
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-init-v4hi-1.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#include "sse-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <mmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m64 x, unsigned short *v, int j)
+{
+  union
+    {
+      __m64 x;
+      unsigned short i[8];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned short *v)
+{
+  __m64 x;
+
+  x = _mm_set_pi16 (0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_pi16 (0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_pi16 (0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_pi16 (v[3], 0, 0, 0);
+  check (x, v, 3);
+}
+
+static void
+sse_test (void)
+{
+  unsigned short v[4]
+    = { 0x7B5B, 0x5465, 0x7374, 0x5665};
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-init-v4sf-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-init-v4sf-1.c
new file mode 100644
index 000000000..4cb1f337e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-init-v4sf-1.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#include "sse-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <xmmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128 x, float *v, int j)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.f[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: %f != %f\n", i, v[i], u.f[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.f[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: %f != 0\n", i, u.f[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (float *v)
+{
+  __m128 x;
+
+  x = _mm_set_ps (0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_ps (0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_ps (0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_ps (v[3], 0, 0, 0);
+  check (x, v, 3);
+}
+
+static void
+sse_test (void)
+{
+  float v[4] = { -3, 2, 1, 9 };
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-maxps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-maxps-1.c
new file mode 100644
index 000000000..5e6fcd654
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-maxps-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_max_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = test (s1.x, s2.x); 
+  
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] > s2.a[i] ? s1.a[i]:s2.a[i];   
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-maxss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-maxss-1.c
new file mode 100644
index 000000000..5b5215a57
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-maxss-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_max_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = test (s1.x, s2.x); 
+  
+  e[0] = s1.a[0] > s2.a[0] ? s1.a[0]:s2.a[0];   
+  e[1] = s1.a[1]; 
+  e[2] = s1.a[2];
+  e[3] = s1.a[3]; 
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-minps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-minps-1.c
new file mode 100644
index 000000000..a41139f8b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-minps-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_min_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = test (s1.x, s2.x); 
+  
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] < s2.a[i] ? s1.a[i]:s2.a[i];   
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-minss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-minss-1.c
new file mode 100644
index 000000000..9280b0705
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-minss-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_min_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = test (s1.x, s2.x); 
+  
+  e[0] = s1.a[0] < s2.a[0] ? s1.a[0]:s2.a[0];   
+  e[1] = s1.a[1];
+  e[2] = s1.a[2];
+  e[3] = s1.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movaps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movaps-1.c
new file mode 100644
index 000000000..3677ac442
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movaps-1.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (float *e)
+{
+  return _mm_load_ps (e); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float e[4] __attribute__ ((aligned (16))) = {2134.3343,1234.635654, 1.2234, 876.8976};
+
+  u.x = test (e);   
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movaps-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movaps-2.c
new file mode 100644
index 000000000..46b971a9d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movaps-2.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (float *e, __m128 a)
+{
+  _mm_store_ps (e, a); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float e[4] __attribute__ ((aligned (16))) = {0.0};
+
+  u.x = _mm_set_ps (2134.3343,1234.635654, 1.414, 3.3421);
+
+  test (e, u.x);
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movhlps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movhlps-1.c
new file mode 100644
index 000000000..7023bf95d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movhlps-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_movehl_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = test (s1.x, s2.x); 
+
+  e[0] = s2.a[2];
+  e[1] = s2.a[3];
+  e[2] = s1.a[2];
+  e[3] = s1.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movhps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movhps-1.c
new file mode 100644
index 000000000..9f28927a8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movhps-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 a, __m64 *p)
+{
+  return _mm_loadh_pi (a, p); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1;
+  float d[2] = {24.43, 68.346};
+  float e[4] = {1.17, 2.16, 3.15, 4.14};
+
+  s1.x = _mm_set_ps (5.13, 6.12, 7.11, 8.9);
+  u.x = _mm_loadu_ps (e);
+ 
+  u.x = test (s1.x, (__m64 *)d);
+
+  e[0] = s1.a[0];
+  e[1] = s1.a[1];
+  e[2] = d[0];
+  e[3] = d[1];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movhps-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movhps-2.c
new file mode 100644
index 000000000..023937b66
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movhps-2.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (__m64 *p, __m128 a)
+{
+  return _mm_storeh_pi (p, a); 
+}
+
+static void
+TEST (void)
+{
+  union128 s1;
+  float e[2];
+  float d[2];
+
+  s1.x = _mm_set_ps (5.13, 6.12, 7.11, 8.9);
+ 
+  test ((__m64 *)d, s1.x);
+
+  e[0] = s1.a[2];
+  e[1] = s1.a[3];
+
+  if (checkVf (d, e, 2))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movlhps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movlhps-1.c
new file mode 100644
index 000000000..aba9a9aa4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movlhps-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 a, __m128 b)
+{
+  return _mm_movelh_ps (a, b); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4]; 
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = _mm_set1_ps (0.0);
+
+  u.x = test (s1.x, s2.x);
+
+  e[0] = s1.a[0];
+  e[1] = s1.a[1];
+  e[2] = s2.a[0];
+  e[3] = s2.a[1];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movmskps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movmskps-1.c
new file mode 100644
index 000000000..f1f0d7ed5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movmskps-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int
+__attribute__((noinline, unused))
+test (__m128 a)
+{
+  return _mm_movemask_ps (a); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float s[4] = {2134.3343,1234.635654, 1.2234, 876.8976};
+  int d;
+  int e = 0;
+  int i;
+
+  u.x = _mm_loadu_ps (s);   
+  d = test (u.x);
+
+  for (i = 0; i < 4; i++)
+    if (s[i] < 0)
+      e |= (1 << i);
+
+  if (checkVi (&d, &e, 1))
+    abort ();
+
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movntps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movntps-1.c
new file mode 100644
index 000000000..8c45da31d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movntps-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static void 
+__attribute__((noinline, unused))
+test (float *p, __m128 s)
+{
+  return _mm_stream_ps (p, s); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float e[4] __attribute__ ((aligned(16)));
+
+  u.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  test (e, u.x); 
+  
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movss-1.c
new file mode 100644
index 000000000..eccdf5af9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movss-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (float *e)
+{
+  return _mm_load_ss (e); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float e[4] = {1.1, 2.2, 3.3, 4.4};
+ 
+  u.x = _mm_set_ps (2134.3343,1234.635654, 1.2234, 876.8976);
+
+  u.x = test (e);
+
+  e[1] = u.a[1];
+  e[2] = u.a[2];
+  e[3] = u.a[3];   
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movss-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movss-2.c
new file mode 100644
index 000000000..f64fa4db6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movss-2.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (float *e, __m128 a)
+{
+  return _mm_store_ss (e, a); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float d[1];
+  float e[1];
+ 
+  u.x = _mm_set_ps (2134.3343,1234.635654, 1.2234, 876.8976);
+
+  test (d, u.x);
+
+  e[0] = u.a[0];
+
+  if (checkVf (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movss-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movss-3.c
new file mode 100644
index 000000000..1212622b7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movss-3.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 a, __m128 b)
+{
+  return _mm_move_ss (a, b); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+ 
+  s1.x = _mm_set_ps (2134.3343,1234.635654, 1.2234, 876.8976);
+  s2.x = _mm_set_ps (1.1, 2.2, 3.3, 4.4);
+  u.x = _mm_set_ps (5.5, 6.6, 7.7, 8.8);
+  u.x = test (s1.x, s2.x);
+  
+  e[0] = s2.a[0];
+  e[1] = s1.a[1];
+  e[2] = s1.a[2];
+  e[3] = s1.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movups-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movups-1.c
new file mode 100644
index 000000000..222da79d9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movups-1.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (float *e)
+{
+  return _mm_loadu_ps (e); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float e[4] = {2134.3343,1234.635654, 1.2234, 876.8976};
+
+  u.x = test (e);   
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movups-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movups-2.c
new file mode 100644
index 000000000..41657239c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-movups-2.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (float *e, __m128 a)
+{
+  _mm_storeu_ps (e, a); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float e[4] = {0.0};
+
+  u.x = _mm_set_ps (2134.3343,1234.635654, 1.414, 3.3421);
+
+  test (e, u.x);
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-mulps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-mulps-1.c
new file mode 100644
index 000000000..a07b5abf6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-mulps-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_mul_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] * s2.a[0];
+  e[1] = s1.a[1] * s2.a[1];
+  e[2] = s1.a[2] * s2.a[2];
+  e[3] = s1.a[3] * s2.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-mulss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-mulss-1.c
new file mode 100644
index 000000000..7b4506350
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-mulss-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_mul_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] * s2.a[0];
+  e[1] = s1.a[1];
+  e[2] = s1.a[2];
+  e[3] = s1.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-orps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-orps-1.c
new file mode 100644
index 000000000..6c8dac5cc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-orps-1.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_or_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union {
+    float f[4];
+    int   i[4];
+  }source1, source2, e;
+
+  union128 u, s1, s2;
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 168.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (10.17, 2.16, 3.15, 4.14);
+
+  _mm_storeu_ps (source1.f, s1.x);
+  _mm_storeu_ps (source2.f, s2.x);
+
+  u.x = test (s1.x, s2.x); 
+  
+  for (i = 0; i < 4; i++)
+    e.i[i] = source1.i[i] | source2.i[i];   
+
+  if (check_union128 (u, e.f))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-rcpps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-rcpps-1.c
new file mode 100644
index 000000000..7a1a8fa73
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-rcpps-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1)
+{
+  return _mm_rcp_ps (s1); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1;
+  float e[4];
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  u.x = test (s1.x); 
+  
+  for (i = 0; i < 4; i++)
+    {
+      __m128 tmp = _mm_load_ss (&s1.a[i]);
+      tmp = _mm_rcp_ss (tmp);
+      _mm_store_ss (&e[i], tmp);
+    }
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-recip-vec.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-recip-vec.c
new file mode 100644
index 000000000..2f90ec8ae
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-recip-vec.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse -mfpmath=sse -mrecip" } */
+
+#include "sse-check.h"
+
+extern float sqrtf (float);
+
+#define N 8
+
+float a[N] = { 0.f, 18.f, 108.f, 324.f, 720.f, 1944.f, 3087.f, 5832.f };
+float b[N] = { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f };
+float r[N];
+
+float rc[N] = { 0.f, 3.f, 6.f, 9.f, 12.f, 18.f, 21.f, 27.f };
+
+static void
+sse_test (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    {
+      r[i] = sqrtf (a[i] / b[i]);
+    }
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (r[i] != rc[i])
+	abort();
+    }   
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-recip.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-recip.c
new file mode 100644
index 000000000..b673f400b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-recip.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -msse -mfpmath=sse -mrecip" } */
+
+#include "sse-check.h"
+
+extern float sqrtf (float);
+
+#define N 8
+
+static void
+sse_test (void)
+{
+  float a[N] = { 0.f, 18.f, 108.f, 324.f, 720.f, 1944.f, 3087.f, 5832.f };
+  float b[N] = { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f };
+  float r[N];
+
+  float rc[N] = { 0.f, 3.f, 6.f, 9.f, 12.f, 18.f, 21.f, 27.f };
+
+  int i;
+
+  for (i = 0; i < N; i++)
+    {
+      r[i] = sqrtf (a[i] / b[i]);
+    }
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (r[i] != rc[i])
+	abort();
+    }   
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-rsqrtps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-rsqrtps-1.c
new file mode 100644
index 000000000..4052c21f0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-rsqrtps-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1)
+{
+  return _mm_rsqrt_ps (s1); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1;
+  float e[4];
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  u.x = test (s1.x); 
+  
+  for (i = 0; i < 4; i++)
+    {
+      __m128 tmp = _mm_load_ss (&s1.a[i]);
+      tmp = _mm_rsqrt_ss (tmp);
+      _mm_store_ss (&e[i], tmp);
+    }
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-set-ps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-set-ps-1.c
new file mode 100644
index 000000000..8232c7229
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-set-ps-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#include "sse-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <xmmintrin.h>
+
+static void
+__attribute__((noinline))
+test (float *v)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } u;
+  unsigned int i;
+  
+  u.x = _mm_set_ps (v[3], v[2], v[1], v[0]);
+
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (v[i] != u.f[i])
+      {
+#ifdef DEBUG
+	printf ("%i: %f != %f\n", i, v[i], u.f[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+sse_test (void)
+{
+  float v[4] = { -3, 2, 1, 9 };
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-sqrtps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-sqrtps-1.c
new file mode 100644
index 000000000..9f0658d0e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-sqrtps-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1)
+{
+  return _mm_sqrt_ps (s1); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1;
+  float e[4];
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  u.x = test (s1.x); 
+  
+  for (i = 0; i < 4; i++) {
+    __m128 tmp = _mm_load_ss (&s1.a[i]);
+    tmp = _mm_sqrt_ss (tmp);
+    _mm_store_ss (&e[i], tmp);
+    }
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-subps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-subps-1.c
new file mode 100644
index 000000000..2e7e8d502
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-subps-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_sub_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] - s2.a[0];
+  e[1] = s1.a[1] - s2.a[1];
+  e[2] = s1.a[2] - s2.a[2];
+  e[3] = s1.a[3] - s2.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-subss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-subss-1.c
new file mode 100644
index 000000000..5b3ef26bd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-subss-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_sub_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] - s2.a[0];
+  e[1] = s1.a[1];
+  e[2] = s1.a[2];
+  e[3] = s1.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-1.c
new file mode 100644
index 000000000..b38b1fd42
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-1.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_ucomieq_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] == s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-2.c
new file mode 100644
index 000000000..e0212a4e3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_ucomilt_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] < s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-3.c
new file mode 100644
index 000000000..dc728fb50
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-3.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_ucomile_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] <= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-4.c
new file mode 100644
index 000000000..3251c0b8f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-4.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_ucomigt_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] > s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-5.c
new file mode 100644
index 000000000..ad34f01d9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-5.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_ucomige_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] >= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-6.c
new file mode 100644
index 000000000..b9b2f4b28
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-ucomiss-6.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_ucomineq_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] != s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-unpckhps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-unpckhps-1.c
new file mode 100644
index 000000000..be4ab3659
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-unpckhps-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_unpackhi_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[2];
+  e[1] = s2.a[2];
+  e[2] = s1.a[3];
+  e[3] = s2.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-unpcklps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-unpcklps-1.c
new file mode 100644
index 000000000..5a5da2064
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-unpcklps-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_unpacklo_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0];
+  e[1] = s2.a[0];
+  e[2] = s1.a[1];
+  e[3] = s2.a[1];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-vect-types.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-vect-types.c
new file mode 100644
index 000000000..9cb6f3e07
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-vect-types.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -msse2" } */
+
+#include <xmmintrin.h>
+
+__m128d foo1(__m128d z, __m128d  a, int N) { 
+  int i;
+  for (i=0; i<N; i++) {
+    a = _mm_add_ps(z, a); /* { dg-error "incompatible type" } */
+  }
+  return a;
+}
+/* { dg-message "note: expected '\[^'\n\]*' but argument is of type '\[^'\n\]*'" "note: expected" { target *-*-* } 0 } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-xorps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-xorps-1.c
new file mode 100644
index 000000000..6f96e6910
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse-xorps-1.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_xor_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union {
+    float f[4];
+    int   i[4];
+  }source1, source2, e;
+
+  union128 u, s1, s2;
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+
+  _mm_storeu_ps (source1.f, s1.x);
+  _mm_storeu_ps (source2.f, s2.x);
+
+  u.x = test (s1.x, s2.x); 
+  
+  for (i = 0; i < 4; i++)
+    e.i[i] = source1.i[i] ^ source2.i[i];   
+
+  if (check_union128 (u, e.f))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-addpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-addpd-1.c
new file mode 100644
index 000000000..2c1e81d85
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-addpd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_add_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] + s2.a[0];
+  e[1] = s1.a[1] + s2.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-addsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-addsd-1.c
new file mode 100644
index 000000000..d81b1bb92
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-addsd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_add_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] + s2.a[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-andnpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-andnpd-1.c
new file mode 100644
index 000000000..36b3c3194
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-andnpd-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_andnot_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  long long source1[2]={34545, 95567};
+  long long source2[2]={674, 57897};
+  long long e[2];
+   
+  s1.x = _mm_loadu_pd ((double *)source1);
+  s2.x = _mm_loadu_pd ((double *)source2);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = (~source1[0]) & source2[0];
+  e[1] = (~source1[1]) & source2[1];
+
+  if (check_union128d (u, (double *)e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-andpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-andpd-1.c
new file mode 100644
index 000000000..90902bfcd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-andpd-1.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_and_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  
+  union
+  {
+    double d[2];
+    long long ll[2];
+  }source1, source2, e;
+   
+  s1.x = _mm_set_pd (34545, 95567);
+  s2.x = _mm_set_pd (674, 57897);
+
+  _mm_storeu_pd (source1.d, s1.x);
+  _mm_storeu_pd (source2.d, s2.x);
+
+  u.x = test (s1.x, s2.x); 
+   
+  e.ll[0] = source1.ll[0] & source2.ll[0];
+  e.ll[1] = source1.ll[1] & source2.ll[1];
+
+  if (check_union128d (u, e.d))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-check.h
new file mode 100644
index 000000000..a69333e39
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-check.h
@@ -0,0 +1,20 @@
+#include <stdlib.h>
+#include "cpuid.h"
+#include "m128-check.h"
+
+static void sse2_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run SSE2 test only if host has SSE2 support.  */
+  if (edx & bit_SSE2)
+    sse2_test ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-1.c
new file mode 100644
index 000000000..e8478d9ad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-1.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_comieq_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,2344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] == s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-2.c
new file mode 100644
index 000000000..f18cf1617
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_comilt_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,2344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] < s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-3.c
new file mode 100644
index 000000000..6bd885527
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-3.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_comile_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,2344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] <= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-4.c
new file mode 100644
index 000000000..cf377c490
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-4.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_comigt_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,12344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] > s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-5.c
new file mode 100644
index 000000000..dd2127bc3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-5.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_comige_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,2344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] >= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-6.c
new file mode 100644
index 000000000..13371172a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-comisd-6.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_comineq_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,2344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] != s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtdq2pd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtdq2pd-1.c
new file mode 100644
index 000000000..5640e398f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtdq2pd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128i p)
+{
+  return _mm_cvtepi32_pd (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  union128i_d s;
+  double e[2];
+
+  s.x = _mm_set_epi32 (123, 321, 456, 987);
+
+  u.x = test (s.x);
+
+  e[0] = (double)s.a[0]; 
+  e[1] = (double)s.a[1]; 
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtdq2ps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtdq2ps-1.c
new file mode 100644
index 000000000..a8839a4c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtdq2ps-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128i p)
+{
+  return _mm_cvtepi32_ps (p); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  union128i_d s;
+  float e[4];
+
+  s.x = _mm_set_epi32 (123, 321, 456, 987);
+
+  u.x = test (s.x);
+
+  e[0] = (float)s.a[0]; 
+  e[1] = (float)s.a[1]; 
+  e[2] = (float)s.a[2]; 
+  e[3] = (float)s.a[3]; 
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtpd2dq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtpd2dq-1.c
new file mode 100644
index 000000000..f25290c2e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtpd2dq-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_cvtpd_epi32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  union128d s;
+  int e[4] = {0};
+
+  s.x = _mm_set_pd (2.78, 7777768.82);
+
+  u.x = test (s.x);
+
+  e[0] = (int)(s.a[0] + 0.5); 
+  e[1] = (int)(s.a[1] + 0.5); 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtpd2ps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtpd2ps-1.c
new file mode 100644
index 000000000..365d5e704
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtpd2ps-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_cvtpd_ps (p); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  union128d s;
+  float e[4] = {0};
+
+  s.x = _mm_set_pd (123.321, 456.987);
+
+  u.x = test (s.x);
+
+  e[0] = (float)s.a[0]; 
+  e[1] = (float)s.a[1]; 
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtps2dq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtps2dq-1.c
new file mode 100644
index 000000000..68c2a996d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtps2dq-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128 p)
+{
+  return _mm_cvtps_epi32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  union128 s;
+  int e[4] = {0};
+
+  s.x = _mm_set_ps (2.78, 7777768.82, 2.331, 3.456);
+
+  u.x = test (s.x);
+
+  e[0] = (int)(s.a[0] + 0.5); 
+  e[1] = (int)(s.a[1] + 0.5); 
+  e[2] = (int)(s.a[2] + 0.5); 
+  e[3] = (int)(s.a[3] + 0.5); 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtps2pd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtps2pd-1.c
new file mode 100644
index 000000000..16093ef4f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtps2pd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128 p)
+{
+  return _mm_cvtps_pd (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  union128 s;
+  double e[2];
+
+  s.x = _mm_set_ps (2.78, 7777768.82, 2.331, 3.456);
+
+  u.x = test (s.x);
+
+  e[0] = (double)s.a[0]; 
+  e[1] = (double)s.a[1]; 
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-1.c
new file mode 100644
index 000000000..75770eeb1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_cvtsd_si32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d s;
+  int e;
+  int d;
+
+  s.x = _mm_set_pd (123.321, 456.987);
+
+  d = test (s.x);
+
+  e = (int)(s.a[0] + 0.5);
+
+  if (d != e)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-2.c
new file mode 100644
index 000000000..dfc543f19
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-2.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static long long
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_cvtsd_si64 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d s;
+  long long e;
+  long long d;
+
+  s.x = _mm_set_pd (829496729501.4, 429496729501.4);
+
+  d = test (s.x);
+
+  e = (long long)(s.a[0] + 0.5);
+
+  if (d != e)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtsd2ss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtsd2ss-1.c
new file mode 100644
index 000000000..ae0b2c353
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtsd2ss-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+
+static __m128 
+__attribute__((noinline, unused))
+test (__m128 p1, __m128d p2)
+{
+  return _mm_cvtsd_ss (p1, p2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1;
+  union128 u, s2;
+  double source1[2] = {123.345, 67.3321};
+  float  e[4] = {5633.098, 93.21, 3.34, 4555.2};
+
+  s1.x = _mm_loadu_pd (source1);
+  s2.x = _mm_loadu_ps (e);
+
+  u.x = test(s2.x, s1.x);
+
+  e[0] = (float)source1[0];
+
+  if (check_union128(u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-1.c
new file mode 100644
index 000000000..12ca895fc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-1.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d 
+__attribute__((noinline, unused))
+test (__m128d p, int b)
+{
+  return _mm_cvtsi32_sd (p, b); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s;
+  int b = 128;
+  double e[2];
+
+  s.x = _mm_set_pd (123.321, 456.987);
+
+  u.x = test (s.x, b);
+  e[0] = (double)b;
+  e[1] = s.a[1];
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-2.c
new file mode 100644
index 000000000..29d6d86a6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-2.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d 
+__attribute__((noinline, unused))
+test (__m128d p, long long b)
+{
+  return _mm_cvtsi64_sd (p, b); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s;
+  long long b = 42949672951333LL;
+  double e[2];
+
+  s.x = _mm_set_pd (123.321, 456.987);
+
+  u.x = test (s.x, b);
+  e[0] = (double)b;
+  e[1] = s.a[1];
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtss2sd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtss2sd-1.c
new file mode 100644
index 000000000..e8172d38e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvtss2sd-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d 
+__attribute__((noinline, unused))
+test (__m128d a, __m128 b)
+{
+  return _mm_cvtss_sd (a, b); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1;
+  union128 s2;
+  double e[2];
+
+  s1.x = _mm_set_pd (123.321, 456.987);
+  s2.x = _mm_set_ps (123.321, 456.987, 666.45, 231.987);
+
+  u.x = test (s1.x, s2.x);
+
+  e[0] = (double)s2.a[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvttpd2dq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvttpd2dq-1.c
new file mode 100644
index 000000000..93dd62493
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvttpd2dq-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_cvttpd_epi32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d s;
+  union128i_d u;
+  int e[4] = {0};
+
+  s.x = _mm_set_pd (123.321, 456.987);
+
+  u.x = test (s.x);
+
+  e[0] = (int)s.a[0]; 
+  e[1] = (int)s.a[1]; 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvttps2dq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvttps2dq-1.c
new file mode 100644
index 000000000..1c963a10e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvttps2dq-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128 p)
+{
+  return _mm_cvttps_epi32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128 s;
+  union128i_d u;
+  int e[4] = {0};
+
+  s.x = _mm_set_ps (123.321, 456.987, 33.56, 7765.321);
+
+  u.x = test (s.x);
+
+  e[0] = (int)s.a[0]; 
+  e[1] = (int)s.a[1]; 
+  e[2] = (int)s.a[2]; 
+  e[3] = (int)s.a[3]; 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-1.c
new file mode 100644
index 000000000..a87ec1a13
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-1.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_cvttsd_si32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d s;
+  int e;
+  int d;
+
+  s.x = _mm_set_pd (123.321, 456.987);
+
+  d = test (s.x);
+  e = (int)(s.a[0]);
+
+  if (d != e)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-2.c
new file mode 100644
index 000000000..ec0fe20ee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-2.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static long long
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_cvttsd_si64 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d s;
+  long long e;
+  long long d;
+
+  s.x = _mm_set_pd (123.321, 42949672339501.4);
+
+  d = test (s.x);
+  e = (long long)(s.a[0]);
+
+  if (d != e)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-divpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-divpd-1.c
new file mode 100644
index 000000000..cc4f9d116
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-divpd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_div_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] / s2.a[0];
+  e[1] = s1.a[1] / s2.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-divsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-divsd-1.c
new file mode 100644
index 000000000..e8b9e8c4c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-divsd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_div_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] / s2.a[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-init-v16qi-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-init-v16qi-1.c
new file mode 100644
index 000000000..903a5ad74
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-init-v16qi-1.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128i x, unsigned char *v, int j)
+{
+  union
+    {
+      __m128i x;
+      unsigned char i[16];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned char *v)
+{
+  __m128i x;
+
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[3], 0, 0, 0);
+  check (x, v, 3);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[4], 0, 0, 0, 0);
+  check (x, v, 4);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[5], 0, 0, 0, 0, 0);
+  check (x, v, 5);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, v[6], 0, 0, 0, 0, 0, 0);
+  check (x, v, 6);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, v[7], 0, 0, 0, 0, 0, 0, 0);
+  check (x, v, 7);
+}
+
+static void
+sse2_test (void)
+{
+  unsigned char v[16]
+    = { 0x7B, 0x5B, 0x54, 0x65, 0x73, 0x74, 0x56, 0x65,
+	0x63, 0x74, 0x6F, 0x72, 0x5D, 0x53, 0x47, 0x5D };
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-init-v2di-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-init-v2di-1.c
new file mode 100644
index 000000000..7dc80a320
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-init-v2di-1.c
@@ -0,0 +1,63 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128i x, unsigned long long *v, int j)
+{
+  union
+    {
+      __m128i x;
+      unsigned long long i[2];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%llx != 0x%llx\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%llx != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned long long *v)
+{
+  __m128i x;
+
+  x = _mm_set_epi64x (0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_epi64x (v[1], 0);
+  check (x, v, 1);
+}
+
+static void
+sse2_test (void)
+{
+  unsigned long long v[2]
+    = { 0x7B5B546573745665LL, 0x63746F725D53475DLL };
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c
new file mode 100644
index 000000000..da36efa1d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse4 -march=core2" } */
+
+#include <emmintrin.h>
+
+__m128i
+test (long long b)
+{
+  return _mm_cvtsi64_si128 (b); 
+}
+
+/* { dg-final { scan-assembler "movq" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-init-v4si-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-init-v4si-1.c
new file mode 100644
index 000000000..71e27be60
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-init-v4si-1.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128i x, unsigned int *v, int j)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned int *v)
+{
+  __m128i x;
+
+  x = _mm_set_epi32 (0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_epi32 (0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_epi32 (0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_epi32 (v[3], 0, 0, 0);
+  check (x, v, 3);
+}
+
+static void
+sse2_test (void)
+{
+  unsigned int v[4]
+    = { 0x7B5B5465, 0x73745665, 0x63746F72, 0x5D53475D };
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-init-v8hi-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-init-v8hi-1.c
new file mode 100644
index 000000000..3874b2ed5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-init-v8hi-1.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128i x, unsigned short *v, int j)
+{
+  union
+    {
+      __m128i x;
+      unsigned short i[8];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned short *v)
+{
+  __m128i x;
+
+  x = _mm_set_epi16 (0, 0, 0, 0, 0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_epi16 (0, 0, 0, 0, 0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_epi16 (0, 0, 0, 0, 0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_epi16 (0, 0, 0, 0, v[3], 0, 0, 0);
+  check (x, v, 3);
+  x = _mm_set_epi16 (0, 0, 0, v[4], 0, 0, 0, 0);
+  check (x, v, 4);
+  x = _mm_set_epi16 (0, 0, v[5], 0, 0, 0, 0, 0);
+  check (x, v, 5);
+  x = _mm_set_epi16 (0, v[6], 0, 0, 0, 0, 0, 0);
+  check (x, v, 6);
+  x = _mm_set_epi16 (v[7], 0, 0, 0, 0, 0, 0, 0);
+  check (x, v, 7);
+}
+
+static void
+sse2_test (void)
+{
+  unsigned short v[8]
+    = { 0x7B5B, 0x5465, 0x7374, 0x5665,
+	0x6374, 0x6F72, 0x5D53, 0x475D };
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-lrint-vec.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-lrint-vec.c
new file mode 100644
index 000000000..5276c7edd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-lrint-vec.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2" } */
+
+#include "sse2-check.h"
+
+extern long lrint (double);
+
+#define N 32
+
+double a[N] = {0.4,3.5,6.6,9.4,12.5,15.6,18.4,21.5,24.6,27.4,30.5,33.6,36.4,39.5,42.6,45.4,0.5,3.6,6.4,9.5,12.6,15.4,18.5,21.6,24.4,27.5,30.6,33.4,36.5,39.6,42.4,45.5};
+long r[N];
+
+static void
+sse2_test (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    {
+      r[i] = lrint (a[i]);
+    }
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (r[i] != lrint (a[i]))
+	abort();
+    }   
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-lrintf-vec.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-lrintf-vec.c
new file mode 100644
index 000000000..43037a577
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-lrintf-vec.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2" } */
+
+#include "sse2-check.h"
+
+extern long lrintf (float);
+
+#define N 32
+
+float a[N] = {0.4,3.5,6.6,9.4,12.5,15.6,18.4,21.5,24.6,27.4,30.5,33.6,36.4,39.5,42.6,45.4,0.5,3.6,6.4,9.5,12.6,15.4,18.5,21.6,24.4,27.5,30.6,33.4,36.5,39.6,42.4,45.5};
+long r[N];
+
+static void
+sse2_test (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    {
+      r[i] = lrintf (a[i]);
+    }
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (r[i] != lrintf (a[i]))
+	abort();
+    }   
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-maxpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-maxpd-1.c
new file mode 100644
index 000000000..3ca51a2c3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-maxpd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_max_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] > s2.a[0] ? s1.a[0]:s2.a[0];
+  e[1] = s1.a[1] > s2.a[1] ? s1.a[1]:s2.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-maxsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-maxsd-1.c
new file mode 100644
index 000000000..e2c6829f2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-maxsd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_max_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] > s2.a[0] ? s1.a[0]:s2.a[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-minpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-minpd-1.c
new file mode 100644
index 000000000..9ec53e22c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-minpd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_min_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] < s2.a[0] ? s1.a[0]:s2.a[0];
+  e[1] = s1.a[1] < s2.a[1] ? s1.a[1]:s2.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-minsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-minsd-1.c
new file mode 100644
index 000000000..50dc124b4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-minsd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_min_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] < s2.a[0] ? s1.a[0]:s2.a[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-mmx.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-mmx.c
new file mode 100644
index 000000000..ca375cb90
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-mmx.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#include <mmintrin.h>
+
+#define N 4
+
+unsigned long long a[N], b[N], result[N];
+
+unsigned long long check[N] =
+  { 0x101010101010100full,
+    0x1010101010101010ull,
+    0x1010101010101010ull,
+    0x1010101010101010ull };
+
+__m64
+unsigned_add3 (const __m64 * a, const __m64 * b,
+	       __m64 * result, unsigned int count)
+{
+  __m64 _a, _b, one, sum, carry, onesCarry;
+
+  unsigned int i;
+
+  carry = _mm_setzero_si64 ();
+
+  one = _mm_cmpeq_pi8 (carry, carry);
+  one = _mm_sub_si64 (carry, one);
+
+  for (i = 0; i < count; i++)
+    {
+      _a = a[i];
+      _b = b[i];
+
+      sum = _mm_add_si64 (_a, _b);
+      sum = _mm_add_si64 (sum, carry);
+
+      result[i] = sum;
+
+      onesCarry = _mm_and_si64 (_mm_xor_si64 (_a, _b), carry);
+      onesCarry = _mm_or_si64 (_mm_and_si64 (_a, _b), onesCarry);
+      onesCarry = _mm_and_si64 (onesCarry, one);
+
+      _a = _mm_srli_si64 (_a, 1);
+      _b = _mm_srli_si64 (_b, 1);
+
+      carry = _mm_add_si64 (_mm_add_si64 (_a, _b), onesCarry);
+      carry = _mm_srli_si64 (carry, 63);
+    }
+
+  return carry;
+}
+
+void __attribute__((noinline))
+sse2_test (void)
+{
+  unsigned long long carry;
+  int i;
+
+  /* Really long numbers.  */
+  a[3] = a[2] = a[1] = a[0] = 0xd3d3d3d3d3d3d3d3ull;
+  b[3] = b[2] = b[1] = b[0] = 0x3c3c3c3c3c3c3c3cull;
+
+  carry = (unsigned long long) unsigned_add3
+    ((__m64 *)a, (__m64 *)b, (__m64 *)result, N);
+
+  _mm_empty ();
+
+  if (carry != 1)
+    abort ();
+
+  for (i = 0; i < N; i++)
+    if (result [i] != check[i])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movapd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movapd-1.c
new file mode 100644
index 000000000..0a047dd93
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movapd-1.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (double *e)
+{
+  return _mm_load_pd (e); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double e[2] __attribute__ ((aligned (8))) = {2134.3343,1234.635654};
+
+  u.x = test (e);   
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movapd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movapd-2.c
new file mode 100644
index 000000000..decfd22b5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movapd-2.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (double *e, __m128d a)
+{
+  _mm_store_pd (e, a); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double e[2] __attribute__ ((aligned (8))) = {0.0};
+
+  u.x = _mm_set_pd (2134.3343,1234.635654);
+
+  test (e, u.x);
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movd-1.c
new file mode 100644
index 000000000..2475bbc35
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movd-1.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (int b)
+{
+  return _mm_cvtsi32_si128 (b); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  int b = 128;
+  int e[4] = {0};
+
+  u.x = test (b);
+
+  e[0] = b;
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movd-2.c
new file mode 100644
index 000000000..f986e6e25
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movd-2.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int
+__attribute__((noinline, unused))
+test (__m128i b)
+{
+  return _mm_cvtsi128_si32 (b); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  int e;
+
+  u.x = _mm_set_epi32 (2134, -128, 655366, 9999);
+  e = test (u.x);
+  if (e != u.a[0])
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movdqa-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movdqa-1.c
new file mode 100644
index 000000000..cf95b629b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movdqa-1.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i *p)
+{
+  return _mm_load_si128 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  int e[4] __attribute__ ((aligned(16))) = {1, 2, 3, 4};
+   
+  u.x = test ((__m128i *)e); 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movdqa-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movdqa-2.c
new file mode 100644
index 000000000..7bf49dcff
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movdqa-2.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (__m128i *p, __m128i a)
+{
+  return _mm_store_si128 (p, a); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  int e[4] __attribute__ ((aligned(16))) = {0};
+
+  u.x = _mm_set_epi32 (1, 2, 3, 4);
+   
+  test ((__m128i *)e, u.x); 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movdqu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movdqu-1.c
new file mode 100644
index 000000000..c24e128f4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movdqu-1.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i *p)
+{
+  return _mm_loadu_si128 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  int e[4]  = {1, 2, 3, 4};
+   
+  u.x = test ((__m128i *)e); 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movdqu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movdqu-2.c
new file mode 100644
index 000000000..9ab0195e5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movdqu-2.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (__m128i *p, __m128i a)
+{
+  return _mm_storeu_si128 (p, a); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  int e[4]  = {0};
+
+  u.x = _mm_set_epi32 (1, 2, 3, 4);
+   
+  test ((__m128i *)e, u.x); 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movhpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movhpd-1.c
new file mode 100644
index 000000000..82e7671bc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movhpd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mfpmath=sse -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, double *p)
+{
+  return _mm_loadh_pd (s1, p); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1;
+  double s2[2] = {41124.234,2344.2354};
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  u.x = test (s1.x, s2); 
+
+  e[0] = s1.a[0];
+  e[1] = s2[0];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movhpd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movhpd-2.c
new file mode 100644
index 000000000..335c89810
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movhpd-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mfpmath=sse -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (double *p, __m128d a)
+{
+  return _mm_storeh_pd (p, a); 
+}
+
+static void
+TEST (void)
+{
+  union128d s;
+  double d[1];
+  double e[1];
+   
+  s.x = _mm_set_pd (2134.3343,1234.635654);
+  test (d, s.x);
+
+  e[0] = s.a[1];
+
+  if (e[0] != d[0])
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movlpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movlpd-1.c
new file mode 100644
index 000000000..548f2e625
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movlpd-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d a, double *e)
+{
+  return _mm_loadl_pd (a, e); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1;
+  double d[2] = {2134.3343,1234.635654};
+  double e[2];
+
+  s1.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = _mm_loadu_pd (d);
+
+  u.x = test (s1.x, d);  
+
+  e[0] = d[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movlpd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movlpd-2.c
new file mode 100644
index 000000000..d63aedf06
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movlpd-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (double *e, __m128d a)
+{
+  return _mm_storel_pd (e, a); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double e[2];
+
+  u.x = _mm_set_pd (41124.234,2344.2354);
+
+  test (e, u.x);  
+
+  e[1] = u.a[1];
+  
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movmskpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movmskpd-1.c
new file mode 100644
index 000000000..cef6f8d72
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movmskpd-1.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_movemask_pd (p); 
+}
+
+static void
+TEST (void)
+{
+  double source[2] = {1.234, -2234.23};
+  union128d s1;
+  int d;
+  int e;
+
+  s1.x = _mm_loadu_pd (source);
+
+  d = test (s1.x);
+
+  e = 0;
+  if (source[0] < 0)
+    e |= 1;
+  
+  if (source[1] < 0)
+    e |= 1 << 1;
+
+  if (checkVi (&d, &e, 1))
+    abort ();  
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movntdq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movntdq-1.c
new file mode 100644
index 000000000..d36eaef48
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movntdq-1.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (__m128i *p, __m128i s)
+{
+  return _mm_stream_si128 (p, s); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  int e[4] __attribute__ ((aligned(16)));
+
+  u.x = _mm_set_epi32 (21, 34, 334, 8567);
+
+  test ((__m128i *)e, u.x);
+  
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movntpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movntpd-1.c
new file mode 100644
index 000000000..edcb90c7b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movntpd-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void 
+__attribute__((noinline, unused))
+test (double *p, __m128d s)
+{
+  return _mm_stream_pd (p, s); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double e[2] __attribute__ ((aligned(16)));
+   
+  u.x = _mm_set_pd (2134.3343,1234.635654);
+  test (e, u.x); 
+   
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movq-1.c
new file mode 100644
index 000000000..9d22df957
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movq-1.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i b)
+{
+  return _mm_move_epi64 (b); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s1;
+  long long e[2] = {0};
+
+  s1.x = _mm_set_epi64x(12876, 3376590);
+  u.x = test (s1.x);
+  e[0] = s1.a[0];
+
+  if (check_union128i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movq-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movq-2.c
new file mode 100644
index 000000000..1b4c02a9c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movq-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (long long b)
+{
+  return _mm_cvtsi64_si128 (b); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u;
+  long long b = 4294967295133LL;
+  long long e[2] = {0};
+
+  u.x = test (b);
+
+  e[0] = b;
+
+  if (check_union128i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movq-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movq-3.c
new file mode 100644
index 000000000..3538bd3ad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movq-3.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static long long
+__attribute__((noinline, unused))
+test (__m128i b)
+{
+  return _mm_cvtsi128_si64 (b); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u;
+  long long e;
+
+  u.x = _mm_set_epi64x (4294967295133LL, 3844294967295133LL);
+  e = test (u.x);
+  if (e != u.a[0])
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movsd-1.c
new file mode 100644
index 000000000..98f9987cf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movsd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (double *p)
+{
+  return _mm_load_sd (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double d[2] = {128.023, 3345.1234};
+  double e[2];
+
+  u.x = _mm_loadu_pd (e);
+  u.x = test (d);
+
+  e[0] = d[0];
+  e[1] = 0.0;
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movsd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movsd-2.c
new file mode 100644
index 000000000..e6e83d10b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movsd-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void 
+__attribute__((noinline, unused))
+test (double *p, __m128d a)
+{
+  _mm_store_sd (p, a); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double d[1];
+  double e[1];
+
+  u.x = _mm_set_pd (128.023, 3345.1234);
+  test (d, u.x);
+
+  e[0] = u.a[0];
+
+  if (checkVd (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movupd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movupd-1.c
new file mode 100644
index 000000000..f9bf5851f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movupd-1.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (double *e)
+{
+  return _mm_loadu_pd (e); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double e[2] = {2134.3343,1234.635654};
+
+  u.x = test (e);   
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movupd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movupd-2.c
new file mode 100644
index 000000000..b5c59b8c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-movupd-2.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (double *e, __m128d a)
+{
+  _mm_storeu_pd (e, a); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double e[2] = {0.0};
+
+  u.x = _mm_set_pd (2134.3343,1234.635654);
+
+  test (e, u.x);
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-mulpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-mulpd-1.c
new file mode 100644
index 000000000..c87e9e20d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-mulpd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_mul_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] * s2.a[0];
+  e[1] = s1.a[1] * s2.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-mulsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-mulsd-1.c
new file mode 100644
index 000000000..1b665733e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-mulsd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_mul_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] * s2.a[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-orpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-orpd-1.c
new file mode 100644
index 000000000..4eaa70a76
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-orpd-1.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_or_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+
+  union
+  {
+     double d[2];
+     long long ll[2];
+  }d1, d2, e;
+
+  s1.x = _mm_set_pd (1234, 44386);
+  s2.x = _mm_set_pd (5198, 23098);
+
+  _mm_storeu_pd (d1.d, s1.x);
+  _mm_storeu_pd (d2.d, s2.x);
+
+  u.x = test (s1.x, s2.x);
+  
+  e.ll[0] = d1.ll[0] | d2.ll[0];
+  e.ll[1] = d1.ll[1] | d2.ll[1];
+
+  if (check_union128d (u, e.d))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-packssdw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-packssdw-1.c
new file mode 100644
index 000000000..a6103261d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-packssdw-1.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_packs_epi32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d s1, s2;
+  union128i_w u;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi32 (2134, -128, 655366, 9999);
+  s2.x = _mm_set_epi32 (41124, 234, 2, -800900);
+  u.x = test (s1.x, s2.x); 
+
+  for (i = 0; i < 4; i++)
+    {
+      if (s1.a[i] > 32767)
+        e[i] = 32767;
+      else if (s1.a[i] < -32768)
+        e[i] = -32768;
+      else
+        e[i] = s1.a[i];
+    }
+  
+  for (i = 0; i < 4; i++)
+   {
+      if (s2.a[i] > 32767)
+        e[i+4] = 32767;
+      else if (s2.a[i] < -32768)
+        e[i+4] = -32768;
+      else
+        e[i+4] = s2.a[i];
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-packsswb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-packsswb-1.c
new file mode 100644
index 000000000..76532fb32
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-packsswb-1.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_packs_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w s1, s2;
+  union128i_b u;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi16 (2134, -128, 1234, 6354, 1002, 3004, 4050, 9999);
+  s2.x = _mm_set_epi16 (41124, 234, 2344, 2354, 607, 1, 2, -8009);
+  u.x = test (s1.x, s2.x); 
+
+  for (i = 0; i < 8; i++)
+    {
+      if (s1.a[i] > 127)
+        e[i] = 127;
+      else if (s1.a[i] < -128)
+        e[i] = -128;
+      else
+        e[i] = s1.a[i];
+    }
+  
+  for (i = 0; i < 8; i++)
+   {
+      if (s2.a[i] > 127)
+        e[i+8] = 127;
+      else if (s2.a[i] < -128)
+        e[i+8] = -128;
+      else
+        e[i+8] = s2.a[i];
+    }
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-packuswb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-packuswb-1.c
new file mode 100644
index 000000000..d176ac0a6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-packuswb-1.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_packus_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w s1, s2;
+  union128i_ub u;
+  unsigned char e[16];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi16 (1, 2, 3, 4, -5, -6, -7, -8);
+  s2.x = _mm_set_epi16 (-9, -10, -11, -12, 13, 14, 15, 16);
+  u.x = test (s1.x, s2.x); 
+
+  for (i=0; i<8; i++)
+    {
+      tmp = s1.a[i]<0 ? 0 : s1.a[i];
+      tmp = tmp>255 ? 255 : tmp;
+      e[i] = tmp;
+
+      tmp = s2.a[i]<0 ? 0 : s2.a[i];
+      tmp = tmp>255 ? 255 : tmp;
+      e[i+8] = tmp;
+    }
+
+  if (check_union128i_ub (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddb-1.c
new file mode 100644
index 000000000..d9414ca07
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddb-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_add_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+     e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddd-1.c
new file mode 100644
index 000000000..c2d9b048a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_add_epi32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s1, s2;
+  int e[4];
+  int i;
+   
+  s1.x = _mm_set_epi32 (30,90,-80,-40);
+  s2.x = _mm_set_epi32 (76, -100, -34, -78);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 4; i++)
+     e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddq-1.c
new file mode 100644
index 000000000..4867cb42e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddq-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_add_epi64 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s1, s2;
+  long long e[2];
+  int i;
+   
+  s1.x = _mm_set_epi64x (90,-80);
+  s2.x = _mm_set_epi64x (76, -100);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 2; i++)
+     e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union128i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddsb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddsb-1.c
new file mode 100644
index 000000000..bb3bafcf5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddsb-1.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_adds_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+    {
+      tmp = s1.a[i] + s2.a[i];
+
+      if (tmp > 127)
+        tmp = 127;
+      if (tmp < -128)
+        tmp = -128;
+
+      e[i] = tmp;
+    }
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddsw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddsw-1.c
new file mode 100644
index 000000000..885ed2609
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddsw-1.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_adds_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15);
+  s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      tmp = s1.a[i] + s2.a[i];
+      
+      if (tmp > 32767)
+        tmp = 32767;
+      if (tmp < -32768)
+        tmp = -32768;
+      
+      e[i] = tmp;
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddusb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddusb-1.c
new file mode 100644
index 000000000..ee1f03869
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddusb-1.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_adds_epu8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16] = {0};
+  int i, tmp;
+   
+  s1.x = _mm_set_epi8 (30, 2,  3,  4,  10, 20, 30, 90,   80, 40, 100, 15, 98, 25, 98, 7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, 100,  34, 78, 39,   6,  3,  4,  5,  119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+    {
+      tmp = s1.a[i] + s2.a[i];
+
+      if (tmp > 255)
+        tmp = -1;
+      if (tmp < 0)
+        tmp = 0; 
+
+      e[i] = tmp; 
+    }
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddusw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddusw-1.c
new file mode 100644
index 000000000..449d14156
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddusw-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_adds_epu16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,80,40,100,15);
+  s2.x = _mm_set_epi16 (11, 98, 76, 100, 34, 78, 39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      tmp = s1.a[i] + s2.a[i];
+      
+      if (tmp > 65535)
+        tmp = -1;
+
+      if (tmp < 0)
+        tmp = 0;
+      
+      e[i] = tmp;
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddw-1.c
new file mode 100644
index 000000000..db1664fbe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-paddw-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_add_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15);
+  s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+     e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pand-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pand-1.c
new file mode 100644
index 000000000..cab3c1fc9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pand-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_and_si128 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+     e[i] = s1.a[i] & s2.a[i];
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pandn-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pandn-1.c
new file mode 100644
index 000000000..5a300c198
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pandn-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_andnot_si128 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+     e[i] = (~s1.a[i]) & s2.a[i];
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pavgb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pavgb-1.c
new file mode 100644
index 000000000..cb80431c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pavgb-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_avg_epu8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_ub u, s1, s2;
+  unsigned char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,80,40,100,15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, 100, 34, 78, 39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+     e[i] = (s1.a[i] + s2.a[i]+1)>>1;
+
+  if (check_union128i_ub (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pavgw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pavgw-1.c
new file mode 100644
index 000000000..341e5afac
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pavgw-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_avg_epu16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_uw u, s1, s2;
+  unsigned short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,80,40,100,15);
+  s2.x = _mm_set_epi16 (11, 98, 76, 100, 34, 78, 39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+     e[i] = (s1.a[i] + s2.a[i]+1)>>1;
+
+  if (check_union128i_uw (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpeqb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpeqb-1.c
new file mode 100644
index 000000000..240fa0dc1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpeqb-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_cmpeq_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,80,40,100,15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, 100, 34, 78, 39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+     e[i] = (s1.a[i] == s2.a[i]) ? -1:0;
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpeqd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpeqd-1.c
new file mode 100644
index 000000000..cb18d1119
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpeqd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_cmpeq_epi32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s1, s2;
+  int e[4];
+  int i;
+   
+  s1.x = _mm_set_epi32 (98, 25, 98,7);
+  s2.x = _mm_set_epi32 (88, 44, 33, 229);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 4; i++)
+     e[i] = (s1.a[i] == s2.a[i]) ? -1:0;
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpeqw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpeqw-1.c
new file mode 100644
index 000000000..e87e9b113
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpeqw-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_cmpeq_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (20,30,90,80,40,100,15,98);
+  s2.x = _mm_set_epi16 (34, 78, 39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+     e[i] = (s1.a[i] == s2.a[i]) ? -1:0;
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpgtb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpgtb-1.c
new file mode 100644
index 000000000..916ec3c33
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpgtb-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_cmpgt_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,80,40,100,15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, 100, 34, 78, 39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+     e[i] = (s1.a[i] > s2.a[i]) ? -1:0;
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpgtd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpgtd-1.c
new file mode 100644
index 000000000..bba5eae01
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpgtd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_cmpgt_epi32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s1, s2;
+  int e[4];
+  int i;
+   
+  s1.x = _mm_set_epi32 (98, 25, 98,7);
+  s2.x = _mm_set_epi32 (88, 44, 33, 229);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 4; i++)
+     e[i] = (s1.a[i] > s2.a[i]) ? -1:0;
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpgtw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpgtw-1.c
new file mode 100644
index 000000000..bfa58a9b7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pcmpgtw-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_cmpgt_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (20,30,90,80,40,100,15,98);
+  s2.x = _mm_set_epi16 (34, 78, 39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+     e[i] = (s1.a[i] > s2.a[i]) ? -1:0;
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmaddwd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmaddwd-1.c
new file mode 100644
index 000000000..df1907a34
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmaddwd-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_madd_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w  s1, s2;
+  union128i_d u;
+  int e[4]; 
+  int i; 
+ 
+  s1.x = _mm_set_epi16 (2134,3343,1234,6354, 1, 3, 4, 5);
+  s2.x = _mm_set_epi16 (41124,234,2344,2354,9, -1, -8, -10);
+  u.x = test (s1.x, s2.x); 
+
+  for (i = 0; i < 4; i++)
+    e[i] = (s1.a[i*2] * s2.a[i*2])+(s1.a[(i*2) + 1] * s2.a[(i*2) + 1]);   
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmaxsw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmaxsw-1.c
new file mode 100644
index 000000000..b07fcb6b9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmaxsw-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_max_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (1,2,3,4,5,6,7,8);
+  s2.x = _mm_set_epi16 (8,7,6,5,4,3,2,1);
+  u.x = test (s1.x, s2.x);
+
+  for (i=0; i<8; i++)
+    e[i] = s1.a[i]>s2.a[i]?s1.a[i]:s2.a[i]; 
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmaxub-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmaxub-1.c
new file mode 100644
index 000000000..e5eafc132
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmaxub-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_max_epu8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_ub u, s1, s2;
+  unsigned char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16);
+  s2.x = _mm_set_epi8 (16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1);
+  u.x = test (s1.x, s2.x);
+
+  for (i=0; i<16; i++)
+    e[i] = s1.a[i]>s2.a[i]?s1.a[i]:s2.a[i]; 
+
+  if (check_union128i_ub (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pminsw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pminsw-1.c
new file mode 100644
index 000000000..ad26ca957
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pminsw-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_min_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (1,2,3,4,5,6,7,8);
+  s2.x = _mm_set_epi16 (8,7,6,5,4,3,2,1);
+  u.x = test (s1.x, s2.x);
+
+  for (i=0; i<8; i++)
+    e[i] = s1.a[i]<s2.a[i]?s1.a[i]:s2.a[i]; 
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pminub-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pminub-1.c
new file mode 100644
index 000000000..953f8dd8a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pminub-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_min_epu8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_ub u, s1, s2;
+  unsigned char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16);
+  s2.x = _mm_set_epi8 (16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1);
+  u.x = test (s1.x, s2.x);
+
+  for (i=0; i<16; i++)
+    e[i] = s1.a[i]<s2.a[i]?s1.a[i]:s2.a[i]; 
+
+  if (check_union128i_ub (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmovmskb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmovmskb-1.c
new file mode 100644
index 000000000..f1f5ff756
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmovmskb-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_movemask_epi8 (s1); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b s1;
+  int i, u, e=0;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  u = test (s1.x); 
+  
+  for (i = 0; i < 16; i++)
+    if (s1.a[i] & (1<<7))
+      e = e | (1<<i);
+
+  if (checkVi (&u, &e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmulhuw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmulhuw-1.c
new file mode 100644
index 000000000..fd6a3d245
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmulhuw-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_mulhi_epu16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_uw u, s1, s2;
+  unsigned short e[8];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi16 (10,2067,3033,90,80,40,1000,15);
+  s2.x = _mm_set_epi16 (11, 9834, 7444, 10222, 34, 7833, 39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      tmp = s1.a[i] * s2.a[i];
+    
+      e[i] = (tmp & 0xffff0000)>>16;
+    }
+
+  if (check_union128i_uw (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmulhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmulhw-1.c
new file mode 100644
index 000000000..447b5ca29
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmulhw-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_mulhi_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi16 (10,2067,-3033,90,80,40,-1000,15);
+  s2.x = _mm_set_epi16 (11, 9834, 7444, -10222, 34, -7833, 39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      tmp = s1.a[i] * s2.a[i];
+    
+      e[i] = (tmp & 0xffff0000)>>16;
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmullw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmullw-1.c
new file mode 100644
index 000000000..a68d0659d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmullw-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_mullo_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi16 (10,2067,-3033,90,80,40,-1000,15);
+  s2.x = _mm_set_epi16 (11, 9834, 7444, -10222, 34, -7833, 39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      tmp = s1.a[i] * s2.a[i];
+    
+      e[i] = tmp;
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmuludq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmuludq-1.c
new file mode 100644
index 000000000..dac14ef5c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pmuludq-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_mul_epu32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d s1, s2;
+  union128i_q u;
+  long long e[2];
+   
+  s1.x = _mm_set_epi32 (10,2067,3033,905);
+  s2.x = _mm_set_epi32 (11, 9834, 7444, 10222);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] * s2.a[0];
+  e[1] = s1.a[2] * s2.a[2];
+
+  if (check_union128i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-por-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-por-1.c
new file mode 100644
index 000000000..7c332ed9c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-por-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_or_si128 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15);
+  s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      e[i] = s1.a[i] | s2.a[i];
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psadbw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psadbw-1.c
new file mode 100644
index 000000000..c5fa0b226
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psadbw-1.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_sad_epu8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_ub s1, s2;
+  union128i_w u;
+  short e[8] = {0};
+  unsigned char tmp[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16);
+  s2.x = _mm_set_epi8 (16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1);
+  u.x = test (s1.x, s2.x);
+
+  for (i = 0; i < 16; i++)
+    tmp [i] = __builtin_abs (s1.a[i] - s2.a[i]);
+
+  for (i = 0; i < 8; i++)
+    e[0] += tmp[i];
+
+  for (i = 8; i < 16; i++)
+    e[4] += tmp[i]; 
+
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pshufd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pshufd-1.c
new file mode 100644
index 000000000..b106283aa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pshufd-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xec
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_shuffle_epi32 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s1;
+  int e[4] = {0};
+  int i;
+   
+  s1.x = _mm_set_epi32 (16,15,14,13);
+  u.x = test (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[((N & (0x3<<(2*i)))>>(2*i))];
+
+  if (check_union128i_d(u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pshufhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pshufhw-1.c
new file mode 100644
index 000000000..4eec55d04
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pshufhw-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xec
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_shufflehi_epi16 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q s1;
+  union128i_w u;
+  short  e[8] = {0};
+  int i;
+  int m1[4] = {0x3, 0x3<<2, 0x3<<4, 0x3<<6};
+  int m2[4];
+  
+  s1.x = _mm_set_epi64x (0xabcde,0xef58a234);
+  u.x = test (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (s1.a[0]>>(16 * i)) & 0xffff;
+
+  for (i = 0; i < 4; i++)
+    m2[i] = (N & m1[i])>>(2*i);
+
+  for (i = 0; i < 4; i++)
+    e[i+4] = (s1.a[1] >> (16 * m2[i])) & 0xffff;
+
+  if (check_union128i_w(u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pshuflw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pshuflw-1.c
new file mode 100644
index 000000000..37496251c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pshuflw-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xec
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_shufflelo_epi16 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q s1;
+  union128i_w u;
+  short  e[8] = {0};
+  int i;
+  int m1[4] = {0x3, 0x3<<2, 0x3<<4, 0x3<<6};
+  int m2[4];
+  
+  s1.x = _mm_set_epi64x (0xabcde,0xef58a234);
+  u.x = test (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i+4] = (s1.a[1]>>(16 * i)) & 0xffff;
+
+  for (i = 0; i < 4; i++)
+    m2[i] = (N & m1[i])>>(2*i);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (s1.a[0] >> (16 * m2[i])) & 0xffff;
+
+  if (check_union128i_w(u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pslld-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pslld-1.c
new file mode 100644
index 000000000..4fbde24a5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pslld-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xf
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_slli_epi32 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s;
+  int e[4] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi32 (1, -2, 3, 4);
+
+  u.x = test (s.x);
+
+  if (N < 32)
+    for (i = 0; i < 4; i++)
+      e[i] = s.a[i] << N; 
+
+  if (check_union128i_d (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pslld-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pslld-2.c
new file mode 100644
index 000000000..adef576e1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pslld-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i c)
+{
+  return _mm_sll_epi32 (s1, c); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s;
+  union128i_q c;
+  int e[4] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi32 (2, -3, 0x7000, 0x9000);
+  c.x = _mm_set_epi64x (12, 23);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 32)
+    for (i = 0; i < 4; i++)
+      e[i] = s.a[i] << c.a[0]; 
+
+  if (check_union128i_d (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pslldq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pslldq-1.c
new file mode 100644
index 000000000..3189106a4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pslldq-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0x5
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_slli_si128 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s;
+  char src[16] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16};
+  char e[16] = {0};
+  int i;
+   
+  s.x = _mm_loadu_si128 ((__m128i *)src);
+
+  u.x = test (s.x);
+
+  for (i = 0; i < 16-N; i++)
+    e[i+N] = src[i];
+
+  if (check_union128i_b (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psllq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psllq-1.c
new file mode 100644
index 000000000..cd916ebf3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psllq-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 60
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_slli_epi64 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s;
+  long long e[2] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi64x (-1, 0xf);
+
+  u.x = test (s.x);
+
+  if (N < 64)
+    for (i = 0; i < 2; i++)
+      e[i] = s.a[i] << N; 
+
+  if (check_union128i_q (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psllq-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psllq-2.c
new file mode 100644
index 000000000..b20e872ff
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psllq-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i c)
+{
+  return _mm_sll_epi64 (s1, c); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s, c;
+  long long e[2] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi64x (-1, 0xf);
+  c.x = _mm_set_epi64x (60,50);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 64)
+    for (i = 0; i < 2; i++)
+      e[i] = s.a[i] << c.a[0]; 
+
+  if (check_union128i_q (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psllw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psllw-1.c
new file mode 100644
index 000000000..1fc5aa406
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psllw-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xb
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_slli_epi16 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s;
+  short e[8] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi16 (1, 2, 3, 4, 5, 6, 0x7000, 0x9000);
+
+  u.x = test (s.x);
+
+  if (N < 16)
+    for (i = 0; i < 8; i++)
+      e[i] = s.a[i] << N; 
+
+  if (check_union128i_w (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psllw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psllw-2.c
new file mode 100644
index 000000000..22a54b6a9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psllw-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i c)
+{
+  return _mm_sll_epi16 (s1, c); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s;
+  union128i_q c;
+  short e[8] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi16 (1, 2, 3, 4, 5, 6, 0x7000, 0x9000);
+  c.x = _mm_set_epi64x (12, 13);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 16)
+    for (i = 0; i < 8; i++)
+      e[i] = s.a[i] << c.a[0]; 
+
+  if (check_union128i_w (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrad-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrad-1.c
new file mode 100644
index 000000000..37091ba84
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrad-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xf
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_srai_epi32 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s;
+  int e[4] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi32 (1, -2, 3, 4);
+
+  u.x = test (s.x);
+
+  if (N < 32)
+    for (i = 0; i < 4; i++)
+      e[i] = s.a[i] >> N; 
+
+  if (check_union128i_d (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrad-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrad-2.c
new file mode 100644
index 000000000..dc24a0f27
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrad-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i count)
+{
+  return _mm_sra_epi32 (s1, count); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s;
+  union128i_q c;
+  int e[4] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi32 (1, -2, 3, 4);
+  c.x = _mm_set_epi64x (16, 29);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 32)
+    for (i = 0; i < 4; i++)
+      e[i] = s.a[i] >> c.a[0]; 
+
+  if (check_union128i_d (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psraw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psraw-1.c
new file mode 100644
index 000000000..3e0d88f16
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psraw-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xb
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_srai_epi16 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s;
+  short e[8] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi16 (1, -2, 3, 4, -5, 6, 0x7000, 0x9000);
+
+  u.x = test (s.x);
+
+  if (N < 16)
+    for (i = 0; i < 8; i++)
+      e[i] = s.a[i] >> N; 
+
+  if (check_union128i_w (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psraw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psraw-2.c
new file mode 100644
index 000000000..c3823ebee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psraw-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i c)
+{
+  return _mm_sra_epi16 (s1, c); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s;
+  union128i_q c;
+  short e[8] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi16 (1, -2, 3, 4, 5, 6, -0x7000, 0x9000);
+  c.x = _mm_set_epi64x (12, 13);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 16)
+    for (i = 0; i < 8; i++)
+      e[i] = s.a[i] >> c.a[0]; 
+
+  if (check_union128i_w (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrld-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrld-1.c
new file mode 100644
index 000000000..0e5773167
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrld-1.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xf
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_srli_epi32 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s;
+  int e[4] = {0};
+  unsigned int tmp;
+  int i;
+ 
+  s.x = _mm_set_epi32 (1, -2, 3, 4);
+
+  u.x = test (s.x);
+
+  if (N < 32)
+    for (i = 0; i < 4; i++) {
+      tmp  = s.a[i];
+      e[i] = tmp >> N; 
+    }
+
+  if (check_union128i_d (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrld-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrld-2.c
new file mode 100644
index 000000000..0270d9274
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrld-2.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i c)
+{
+  return _mm_srl_epi32 (s1, c); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s;
+  union128i_q c;
+  int e[4] = {0};
+  unsigned int tmp;
+  int i;
+ 
+  s.x = _mm_set_epi32 (2, -3, 0x7000, 0x9000);
+  c.x = _mm_set_epi64x (12, 23);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 32)
+    for (i = 0; i < 4; i++) {
+      tmp = s.a[i];
+      e[i] = tmp >> c.a[0];
+    } 
+
+  if (check_union128i_d (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrldq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrldq-1.c
new file mode 100644
index 000000000..751319164
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrldq-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0x5
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_srli_si128 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s;
+  char src[16] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16};
+  char e[16] = {0};
+  int i;
+   
+  s.x = _mm_loadu_si128 ((__m128i *)src);
+
+  u.x = test (s.x);
+
+  for (i = 0; i < 16-N; i++)
+    e[i] = src[i+N];
+
+  if (check_union128i_b (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrlq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrlq-1.c
new file mode 100644
index 000000000..9c1ce5e87
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrlq-1.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 60
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_srli_epi64 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s;
+  long long e[2] = {0};
+  unsigned long long tmp;
+  int i;
+ 
+  s.x = _mm_set_epi64x (-1, 0xf);
+
+  u.x = test (s.x);
+
+  if (N < 64)
+    for (i = 0; i < 2; i++) {
+      tmp = s.a[i]; 
+      e[i] = tmp >> N;
+    }
+
+  if (check_union128i_q (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrlq-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrlq-2.c
new file mode 100644
index 000000000..8c6594079
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrlq-2.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i c)
+{
+  return _mm_srl_epi64 (s1, c); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s, c;
+  long long e[2] = {0};
+  unsigned long long tmp;
+  int i;
+ 
+  s.x = _mm_set_epi64x (-1, 0xf);
+  c.x = _mm_set_epi64x (60,50);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 64)
+    for (i = 0; i < 2; i++){
+      tmp = s.a[i];
+      e[i] =tmp >> c.a[0];
+    } 
+
+  if (check_union128i_q (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrlw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrlw-1.c
new file mode 100644
index 000000000..e5375f735
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrlw-1.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xb
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_srli_epi16 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s;
+  short e[8] = {0};
+  unsigned short tmp;
+  int i;
+ 
+  s.x = _mm_set_epi16 (1, -2, 3, -4, 5, 6, 0x7000, 0x9000);
+
+  u.x = test (s.x);
+
+  if (N < 16)
+    for (i = 0; i < 8; i++)
+      {
+        tmp = s.a[i];
+        e[i] = tmp >> N;
+      }
+
+  if (check_union128i_w (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrlw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrlw-2.c
new file mode 100644
index 000000000..dbe6a68e1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psrlw-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i c)
+{
+  return _mm_srl_epi16 (s1, c); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s;
+  union128i_q c;
+  short e[8] = {0};
+  unsigned short tmp;
+  int i;
+ 
+  s.x = _mm_set_epi16 (1, -2, 3, 4, 5, 6, -0x7000, 0x9000);
+  c.x = _mm_set_epi64x (12, 13);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 16)
+    for (i = 0; i < 8; i++)
+      {
+        tmp = s.a[i];
+        e[i] = tmp >> c.a[0];
+      }
+
+  if (check_union128i_w (u, e))
+    abort (); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubb-1.c
new file mode 100644
index 000000000..a8d5b67dd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubb-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_sub_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+     e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubd-1.c
new file mode 100644
index 000000000..296a261d3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_sub_epi32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s1, s2;
+  int e[4];
+  int i;
+   
+  s1.x = _mm_set_epi32 (30,90,-80,-40);
+  s2.x = _mm_set_epi32 (76, -100, -34, -78);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 4; i++)
+     e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubq-1.c
new file mode 100644
index 000000000..fe8c0f431
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubq-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_sub_epi64 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s1, s2;
+  long long e[2];
+  int i;
+   
+  s1.x = _mm_set_epi64x (90,-80);
+  s2.x = _mm_set_epi64x (76, -100);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 2; i++)
+     e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union128i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubsb-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubsb-1.c
new file mode 100644
index 000000000..d9cb1af5f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubsb-1.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_subs_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+    {
+      tmp = s1.a[i] - s2.a[i];
+
+      if (tmp > 127)
+        tmp = 127;
+      if (tmp < -128)
+        tmp = -128;
+
+      e[i] = tmp;
+    }
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubsw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubsw-1.c
new file mode 100644
index 000000000..85fdbeb42
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubsw-1.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_subs_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15);
+  s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      tmp = s1.a[i] - s2.a[i];
+      
+      if (tmp > 32767)
+        tmp = 32767;
+      if (tmp < -32768)
+        tmp = -32768;
+      
+      e[i] = tmp;
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubw-1.c
new file mode 100644
index 000000000..e2d8be50c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-psubw-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_sub_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15);
+  s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+     e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpckhbw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpckhbw-1.c
new file mode 100644
index 000000000..f673b0b9d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpckhbw-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpackhi_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      e[2*i] = s1.a[8+i];
+      e[2*i + 1] = s2.a[8+i];
+    }
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpckhdq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpckhdq-1.c
new file mode 100644
index 000000000..7fcef7784
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpckhdq-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpackhi_epi32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s1, s2;
+  int e[4];
+  int i;
+   
+  s1.x = _mm_set_epi32 (10,20,-80,-40);
+  s2.x = _mm_set_epi32 (11, -34, -78, -39);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 2; i++)
+    {
+      e[2*i] = s1.a[2+i];
+      e[2*i+1] = s2.a[2+i];
+    }
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpckhqdq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpckhqdq-1.c
new file mode 100644
index 000000000..4cb60d719
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpckhqdq-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpackhi_epi64 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s1, s2;
+  long long  e[2];
+   
+  s1.x = _mm_set_epi64x (10,-40);
+  s2.x = _mm_set_epi64x (1134, -7839);
+  u.x = test (s1.x, s2.x); 
+  
+  e[0] = s1.a[1];
+  e[1] = s2.a[1];
+
+  if (check_union128i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpckhwd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpckhwd-1.c
new file mode 100644
index 000000000..1ba04e162
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpckhwd-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpackhi_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15);
+  s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 4; i++)
+    {
+      e[2*i] = s1.a[4+i];
+      e[2*i+1] = s2.a[4+i];
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpcklbw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpcklbw-1.c
new file mode 100644
index 000000000..4e63885e3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpcklbw-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpacklo_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      e[2*i] = s1.a[i];
+      e[2*i + 1] = s2.a[i];
+    }
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpckldq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpckldq-1.c
new file mode 100644
index 000000000..1e7b44f15
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpckldq-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpacklo_epi32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s1, s2;
+  int e[4];
+  int i;
+   
+  s1.x = _mm_set_epi32 (10,20,-80,-40);
+  s2.x = _mm_set_epi32 (11, -34, -78, -39);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 2; i++)
+    {
+      e[2*i] = s1.a[i];
+      e[2*i+1] = s2.a[i];
+    }
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpcklqdq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpcklqdq-1.c
new file mode 100644
index 000000000..4f84ca10d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpcklqdq-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpacklo_epi64 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s1, s2;
+  long long  e[2];
+   
+  s1.x = _mm_set_epi64x (10,-40);
+  s2.x = _mm_set_epi64x (1134, -7839);
+  u.x = test (s1.x, s2.x); 
+  
+  e[0] = s1.a[0];
+  e[1] = s2.a[0];
+
+  if (check_union128i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpcklwd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpcklwd-1.c
new file mode 100644
index 000000000..8ba26b348
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-punpcklwd-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpacklo_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15);
+  s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 4; i++)
+    {
+      e[2*i] = s1.a[i];
+      e[2*i+1] = s2.a[i];
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pxor-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pxor-1.c
new file mode 100644
index 000000000..7e06440a1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-pxor-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_xor_si128 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_ub u, s1, s2;
+  unsigned char e[16] = {0};
+  int i; 
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,80,40,100,15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, 100, 34, 78, 39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+ 
+  for (i = 0; i < 16; i++)
+    e[i] = s1.a[i] ^ s2.a[i];
+
+  if (check_union128i_ub (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-epi32-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-epi32-1.c
new file mode 100644
index 000000000..f4dac40fc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-epi32-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+test (unsigned int *v)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } u;
+  unsigned int i;
+  
+  u.x = _mm_set_epi32 (v[3], v[2], v[1], v[0]);
+
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (v[i] != u.i[i])
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+sse2_test (void)
+{
+  unsigned int v[4]
+    = { 0x7B5B5465, 0x73745665, 0x63746F72, 0x5D53475D };
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-epi64x-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-epi64x-1.c
new file mode 100644
index 000000000..67510b59c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-epi64x-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+test (unsigned long long *v)
+{
+  union
+    {
+      __m128i x;
+      unsigned long long i[2];
+    } u;
+  unsigned int i;
+  
+  u.x = _mm_set_epi64x (v[1], v[0]);
+
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (v[i] != u.i[i])
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%llx != 0x%llx\n", i, v[i], u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+sse2_test (void)
+{
+  unsigned long long v[2]
+    = { 0x7B5B546573745665LL, 0x63746F725D53475DLL };
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-1.c
new file mode 100644
index 000000000..61f19cb2b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-1.c
@@ -0,0 +1,7 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v16qi-1.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-2.c
new file mode 100644
index 000000000..918fa5c91
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-2.c
@@ -0,0 +1,7 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v16qi-2.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-3.c
new file mode 100644
index 000000000..2c0227dd7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-3.c
@@ -0,0 +1,7 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v16qi-3.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1.c
new file mode 100644
index 000000000..cab461e3e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1.c
@@ -0,0 +1,7 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v8hi-1.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c
new file mode 100644
index 000000000..816c19e20
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c
@@ -0,0 +1,7 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mtune=core2 -msse2" } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v8hi-1.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2.c
new file mode 100644
index 000000000..2b4a8be72
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2.c
@@ -0,0 +1,7 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v8hi-2.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c
new file mode 100644
index 000000000..b5103ac1d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c
@@ -0,0 +1,7 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mtune=core2 -msse2" } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v8hi-2.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-shufpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-shufpd-1.c
new file mode 100644
index 000000000..cffa4695c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-shufpd-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xab
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_shuffle_pd (s1, s2, N); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2] = {0.0};
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (453.345635,54646.464356);
+  u.x = test (s1.x, s2.x);
+
+  e[0] = (N & (1 << 0)) ? s1.a[1] : s1.a[0];
+  e[1] = (N & (1 << 1)) ? s2.a[1] : s2.a[0];
+
+  if (check_union128d(u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-shufps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-shufps-1.c
new file mode 100644
index 000000000..f1ef34761
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-shufps-1.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define MASK 0xab
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+float select4(const float *src, unsigned int control)
+{
+    switch(control) {
+    case 0:
+        return src[0];
+    case 1:
+        return src[1];
+    case 2:
+        return src[2];
+    case 3:
+        return src[3];
+    }
+    return -1;
+}
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_shuffle_ps (s1, s2, MASK); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4] = {0.0};
+   
+  s1.x = _mm_set_ps (1.1, 1.2, 1.3, 1.4);
+  s2.x = _mm_set_ps (2.1, 2.2, 2.3, 2.4);
+  u.x = test (s1.x, s2.x);
+
+  e[0] = select4(s1.a,   (MASK >> 0) & 0x3);
+  e[1] = select4(s1.a,   (MASK >> 2) & 0x3);
+  e[2] = select4(s2.a,   (MASK >> 4) & 0x3);
+  e[3] = select4(s2.a,   (MASK >> 6) & 0x3);
+
+  if (check_union128(u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-sqrtpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-sqrtpd-1.c
new file mode 100644
index 000000000..3a476cfa3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-sqrtpd-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+#include <math.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1)
+{
+  return _mm_sqrt_pd (s1); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1;
+  double e[2];
+  int i;
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  u.x = test (s1.x); 
+
+  for (i = 0; i < 2; i++)
+    {
+      __m128d tmp = _mm_load_sd (&s1.a[i]);
+      tmp = _mm_sqrt_sd (tmp, tmp);
+      _mm_store_sd (&e[i], tmp);
+    }
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-subpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-subpd-1.c
new file mode 100644
index 000000000..e8ac1b820
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-subpd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_sub_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] - s2.a[0];
+  e[1] = s1.a[1] - s2.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-subsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-subsd-1.c
new file mode 100644
index 000000000..d70c3f855
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-subsd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_sub_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] - s2.a[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-1.c
new file mode 100644
index 000000000..deae8e70f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-1.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_ucomieq_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,2344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] == s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-2.c
new file mode 100644
index 000000000..110f7cd4b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_ucomilt_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,12344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] < s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-3.c
new file mode 100644
index 000000000..1e3a1a60a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-3.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_ucomile_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1] = {0};
+  int e[1] = {0};
+ 
+  s1.x = _mm_set_pd (2134.3343,12344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] <= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-4.c
new file mode 100644
index 000000000..99c9aa2ad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-4.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_ucomigt_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,12344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] > s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-5.c
new file mode 100644
index 000000000..19a730a97
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-5.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_ucomige_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,12344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] >= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-6.c
new file mode 100644
index 000000000..dd5ed70e2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-ucomisd-6.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_ucomineq_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,12344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] != s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-unpack-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-unpack-1.c
new file mode 100644
index 000000000..a2676396c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-unpack-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <emmintrin.h>
+
+__m128i
+foo1 (__m128i s1, __m128i s2)
+{
+  return _mm_unpackhi_epi64 (s1, s2); 
+}
+
+__m128i
+foo2 (__m128i s1, __m128i s2)
+{
+  return _mm_unpacklo_epi64 (s1, s2); 
+}
+
+/* { dg-final { scan-assembler "punpcklqdq" } } */
+/* { dg-final { scan-assembler "punpckhqdq" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-unpckhpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-unpckhpd-1.c
new file mode 100644
index 000000000..a682725d1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-unpckhpd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_unpackhi_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[1];
+  e[1] = s2.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-unpcklpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-unpcklpd-1.c
new file mode 100644
index 000000000..0e4a5cce9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-unpcklpd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_unpacklo_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0];
+  e[1] = s2.a[0];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-1.c
new file mode 100644
index 000000000..ba7e2e895
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-1.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+#define msk0   0
+#define msk1   1
+
+static void
+sse2_test (void)
+{
+  union
+    {
+      __m128d x;
+      double d[2];
+    } val1;
+  double res[2];
+  int masks[2];
+  int i;
+
+  val1.d[0] = 23.;
+  val1.d[1] = 45;
+
+  res[0] = __builtin_ia32_vec_ext_v2df ((__v2df)val1.x, msk0);
+  res[1] = __builtin_ia32_vec_ext_v2df ((__v2df)val1.x, msk1);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+
+  for (i = 0; i < 2; i++)
+    if (res[i] != val1.d [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-2.c
new file mode 100644
index 000000000..c7586e14b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-2.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+static void
+sse2_test (void)
+{
+  union
+    {
+      __m128i x;
+      char c[16];
+      short s[8];
+      int i[4];
+      long long ll[2];
+    } val1;
+  long long res[2];
+  int masks[2];
+  int i;
+
+  for (i = 0; i < 16; i++)
+    val1.c[i] = i;
+
+  res[0] = __builtin_ia32_vec_ext_v2di ((__v2di)val1.x, 0);
+  res[1] = __builtin_ia32_vec_ext_v2di ((__v2di)val1.x, 1);
+
+  for (i = 0; i < 2; i++)
+    masks[i] = i;
+
+  for (i = 0; i < 2; i++)
+    if (res[i] != val1.ll [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-3.c
new file mode 100644
index 000000000..545dbe0ba
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-3.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+static void
+sse2_test (void)
+{
+  union
+    {
+      __m128i x;
+      char c[16];
+      short s[8];
+      int i[4];
+      long long ll[2];
+    } val1;
+  int res[4];
+  int masks[4];
+  int i;
+
+  for (i = 0; i < 16; i++)
+    val1.c[i] = i;
+
+  res[0] = __builtin_ia32_vec_ext_v4si ((__v4si)val1.x, 0);
+  res[1] = __builtin_ia32_vec_ext_v4si ((__v4si)val1.x, 1);
+  res[2] = __builtin_ia32_vec_ext_v4si ((__v4si)val1.x, 2);
+  res[3] = __builtin_ia32_vec_ext_v4si ((__v4si)val1.x, 3);
+
+  for (i = 0; i < 4; i++)
+    masks[i] = i;
+
+  for (i = 0; i < 4; i++)
+    if (res[i] != val1.i [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-4.c
new file mode 100644
index 000000000..31e480659
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-4.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+static void
+sse2_test (void)
+{
+  union
+    {
+      __m128i x;
+      char c[16];
+      short s[8];
+      int i[4];
+      long long ll[2];
+    } val1;
+  short res[8];
+  int masks[8];
+  int i;
+
+  for (i = 0; i < 16; i++)
+    val1.c[i] = i;
+
+  res[0] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 0);
+  res[1] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 1);
+  res[2] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 2);
+  res[3] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 3);
+  res[4] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 4);
+  res[5] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 5);
+  res[6] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 6);
+  res[7] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 7);
+
+  for (i = 0; i < 8; i++)
+    masks[i] = i;
+
+  for (i = 0; i < 8; i++)
+    if (res[i] != val1.s [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-5.c
new file mode 100644
index 000000000..7ca45baa2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-5.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+static void
+sse2_test (void)
+{
+  union
+    {
+      __m128i x;
+      char c[16];
+      short s[8];
+      int i[4];
+      long long ll[2];
+    } val1;
+  char res[16];
+  int masks[16];
+  int i;
+
+  for (i = 0; i < 16; i++)
+    val1.c[i] = i;
+
+  res[0] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 0);
+  res[1] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 1);
+  res[2] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 2);
+  res[3] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 3);
+  res[4] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 4);
+  res[5] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 5);
+  res[6] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 6);
+  res[7] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 7);
+  res[8] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 8);
+  res[9] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 9);
+  res[10] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 10);
+  res[11] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 11);
+  res[12] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 12);
+  res[13] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 13);
+  res[14] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 14);
+  res[15] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 15);
+
+  for (i = 0; i < 16; i++)
+    masks[i] = i;
+
+  for (i = 0; i < 16; i++)
+    if (res[i] != val1.c [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-6.c
new file mode 100644
index 000000000..ecd0b331d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-vec-6.c
@@ -0,0 +1,69 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+#include <string.h>
+
+static void
+sse2_test (void)
+{
+  union
+    {
+      __m128i x;
+      char c[16];
+      short s[8];
+      int i[4];
+      long long ll[2];
+    } val1, res[16], tmp;
+  short ins[8] = { 8, 5, 9, 4, 2, 6, 1, 20 };
+  int masks[8];
+  int i;
+
+  for (i = 0; i < 16; i++)
+    val1.c[i] = i;
+
+  res[0].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 0);
+  res[1].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 1);
+  res[2].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 2);
+  res[3].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 3);
+  res[4].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 4);
+  res[5].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 5);
+  res[6].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 6);
+  res[7].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 7);
+
+  for (i = 0; i < 8; i++)
+    masks[i] = i;
+
+  for (i = 0; i < 8; i++)
+    {
+      tmp.x = val1.x;
+      tmp.s[masks[i]] = ins[0];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+
+  for (i = 0; i < 8; i++)
+    {
+      res[i].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+							ins[i], 0);
+      masks[i] = 0;
+    }
+
+  for (i = 0; i < 8; i++)
+    {
+      tmp.x = val1.x;
+      tmp.s[masks[i]] = ins[i];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-xorpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-xorpd-1.c
new file mode 100644
index 000000000..88cf0d379
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse2-xorpd-1.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_xor_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      double d[2];
+      long long l[2];
+    }source1, source2, e;
+
+  union128d u, s1, s2;
+  int i; 
+   
+  s1.x = _mm_set_pd (11.1321456, 2.287332);
+  s2.x = _mm_set_pd (3.37768, 4.43222234);
+
+  _mm_storeu_pd (source1.d, s1.x);
+  _mm_storeu_pd (source2.d, s2.x);
+
+  u.x = test (s1.x, s2.x); 
+ 
+  for (i = 0; i < 2; i++)
+    e.l[i] = source1.l[i] ^ source2.l[i];
+
+  if (check_union128d (u, e.d))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-addsubpd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-addsubpd.c
new file mode 100644
index 000000000..e82fa76c5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-addsubpd.c
@@ -0,0 +1,98 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+
+#include <pmmintrin.h>
+
+static void
+sse3_test_addsubpd (double *i1, double *i2, double *r)
+{
+  __m128d t1 = _mm_loadu_pd (i1);
+  __m128d t2 = _mm_loadu_pd (i2);
+
+  t1 = _mm_addsub_pd (t1, t2);
+
+  _mm_storeu_pd (r, t1);
+}
+
+static void
+sse3_test_addsubpd_subsume (double *i1, double *i2, double *r)
+{
+  __m128d t1 = _mm_load_pd (i1);
+  __m128d t2 = _mm_load_pd (i2);
+
+  t1 = _mm_addsub_pd (t1, t2);
+
+  _mm_storeu_pd (r, t1);
+}
+
+static int
+chk_pd (double *v1, double *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 2; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static double p1[2] __attribute__ ((aligned(16)));
+static double p2[2] __attribute__ ((aligned(16)));
+static double p3[2];
+static double ck[2];
+
+double vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 4)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = vals[i+1];
+
+      p2[0] = vals[i+2];
+      p2[1] = vals[i+3];
+
+      ck[0] = p1[0] - p2[0];
+      ck[1] = p1[1] + p2[1];
+
+      sse3_test_addsubpd (p1, p2, p3);
+
+      fail += chk_pd (ck, p3);
+
+      sse3_test_addsubpd_subsume (p1, p2, p3);
+
+      fail += chk_pd (ck, p3);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-addsubps.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-addsubps.c
new file mode 100644
index 000000000..091b58c84
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-addsubps.c
@@ -0,0 +1,104 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+
+#include <pmmintrin.h>
+
+static void
+sse3_test_addsubps (float *i1, float *i2, float *r)
+{
+  __m128 t1 = _mm_loadu_ps (i1);
+  __m128 t2 = _mm_loadu_ps (i2);
+
+  t1 = _mm_addsub_ps (t1, t2);
+
+  _mm_storeu_ps (r, t1);
+}
+
+static void
+sse3_test_addsubps_subsume (float *i1, float *i2, float *r)
+{
+  __m128 t1 = _mm_load_ps (i1);
+  __m128 t2 = _mm_load_ps (i2);
+
+  t1 = _mm_addsub_ps (t1, t2);
+
+  _mm_storeu_ps (r, t1);
+}
+
+static int
+chk_ps (float *v1, float *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 4; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static float p1[4] __attribute__ ((aligned(16)));
+static float p2[4] __attribute__ ((aligned(16)));
+static float p3[4];
+static float ck[4];
+
+static float vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 8)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = vals[i+1];
+      p1[2] = vals[i+2];
+      p1[3] = vals[i+3];
+
+      p2[0] = vals[i+4];
+      p2[1] = vals[i+5];
+      p2[2] = vals[i+6];
+      p2[3] = vals[i+7];
+
+      ck[0] = p1[0] - p2[0];
+      ck[1] = p1[1] + p2[1];
+      ck[2] = p1[2] - p2[2];
+      ck[3] = p1[3] + p2[3];
+
+      sse3_test_addsubps (p1, p2, p3);
+
+      fail += chk_ps (ck, p3);
+
+      sse3_test_addsubps_subsume (p1, p2, p3);
+
+      fail += chk_ps (ck, p3);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-check.h
new file mode 100644
index 000000000..92930d10a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-check.h
@@ -0,0 +1,21 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void sse3_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+ 
+  /* Run SSE3 test only if host has SSE3 support.  */
+  if (ecx & bit_SSE3)
+    sse3_test ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-haddpd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-haddpd.c
new file mode 100644
index 000000000..8750ddfe2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-haddpd.c
@@ -0,0 +1,97 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+#include <pmmintrin.h>
+
+static void
+sse3_test_haddpd (double *i1, double *i2, double *r)
+{
+  __m128d t1 = _mm_loadu_pd (i1);
+  __m128d t2 = _mm_loadu_pd (i2);
+
+  t1 = _mm_hadd_pd (t1, t2);
+
+  _mm_storeu_pd (r, t1);
+}
+
+static void
+sse3_test_haddpd_subsume (double *i1, double *i2, double *r)
+{
+  __m128d t1 = _mm_load_pd (i1);
+  __m128d t2 = _mm_load_pd (i2);
+
+  t1 = _mm_hadd_pd (t1, t2);
+
+  _mm_storeu_pd (r, t1);
+}
+
+static int
+chk_pd (double *v1, double *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 2; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static double p1[2] __attribute__ ((aligned(16)));
+static double p2[2] __attribute__ ((aligned(16)));
+static double p3[2];
+static double ck[2];
+
+static double vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 4)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = vals[i+1];
+
+      p2[0] = vals[i+2];
+      p2[1] = vals[i+3];
+
+      ck[0] = p1[0] + p1[1];
+      ck[1] = p2[0] + p2[1];
+
+      sse3_test_haddpd (p1, p2, p3);
+
+      fail += chk_pd (ck, p3);
+
+      sse3_test_haddpd_subsume (p1, p2, p3);
+
+      fail += chk_pd (ck, p3);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-haddps.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-haddps.c
new file mode 100644
index 000000000..dcb0a7c58
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-haddps.c
@@ -0,0 +1,104 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+
+#include <pmmintrin.h>
+
+static void
+sse3_test_haddps (float *i1, float *i2, float *r)
+{
+  __m128 t1 = _mm_loadu_ps (i1);
+  __m128 t2 = _mm_loadu_ps (i2);
+
+  t1 = _mm_hadd_ps (t1, t2);
+
+  _mm_storeu_ps (r, t1);
+}
+
+static void
+sse3_test_haddps_subsume (float *i1, float *i2, float *r)
+{
+  __m128 t1 = _mm_load_ps (i1);
+  __m128 t2 = _mm_load_ps (i2);
+
+  t1 = _mm_hadd_ps (t1, t2);
+
+  _mm_storeu_ps (r, t1);
+}
+
+static int
+chk_ps(float *v1, float *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 4; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static float p1[4] __attribute__ ((aligned(16)));
+static float p2[4] __attribute__ ((aligned(16)));
+static float p3[4];
+static float ck[4];
+
+static float vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST ()
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 8)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = vals[i+1];
+      p1[2] = vals[i+2];
+      p1[3] = vals[i+3];
+
+      p2[0] = vals[i+4];
+      p2[1] = vals[i+5];
+      p2[2] = vals[i+6];
+      p2[3] = vals[i+7];
+
+      ck[0] = p1[0] + p1[1];
+      ck[1] = p1[2] + p1[3];
+      ck[2] = p2[0] + p2[1];
+      ck[3] = p2[2] + p2[3];
+
+      sse3_test_haddps (p1, p2, p3);
+
+      fail += chk_ps (ck, p3);
+
+      sse3_test_haddps_subsume (p1, p2, p3);
+
+      fail += chk_ps (ck, p3);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-hsubpd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-hsubpd.c
new file mode 100644
index 000000000..77018f574
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-hsubpd.c
@@ -0,0 +1,97 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+#include <pmmintrin.h>
+
+static void
+sse3_test_hsubpd (double *i1, double *i2, double *r)
+{
+  __m128d t1 = _mm_loadu_pd (i1);
+  __m128d t2 = _mm_loadu_pd (i2);
+
+  t1 = _mm_hsub_pd (t1, t2);
+
+  _mm_storeu_pd (r, t1);
+}
+
+static void
+sse3_test_hsubpd_subsume (double *i1, double *i2, double *r)
+{
+  __m128d t1 = _mm_load_pd (i1);
+  __m128d t2 = _mm_load_pd (i2);
+
+  t1 = _mm_hsub_pd (t1, t2);
+
+  _mm_storeu_pd (r, t1);
+}
+
+static int
+chk_pd (double *v1, double *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 2; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static double p1[2] __attribute__ ((aligned(16)));
+static double p2[2] __attribute__ ((aligned(16)));
+static double p3[2];
+static double ck[2];
+
+static double vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 4)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = vals[i+1];
+
+      p2[0] = vals[i+2];
+      p2[1] = vals[i+3];
+
+      ck[0] = p1[0] - p1[1];
+      ck[1] = p2[0] - p2[1];
+
+      sse3_test_hsubpd (p1, p2, p3);
+
+      fail += chk_pd (ck, p3);
+
+      sse3_test_hsubpd_subsume (p1, p2, p3);
+
+      fail += chk_pd (ck, p3);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-hsubps.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-hsubps.c
new file mode 100644
index 000000000..326adfd04
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-hsubps.c
@@ -0,0 +1,105 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+#include <pmmintrin.h>
+
+static void
+sse3_test_hsubps (float *i1, float *i2, float *r)
+{
+  __m128 t1 = _mm_loadu_ps (i1);
+  __m128 t2 = _mm_loadu_ps (i2);
+
+  t1 = _mm_hsub_ps (t1, t2);
+
+  _mm_storeu_ps (r, t1);
+}
+
+static void
+sse3_test_hsubps_subsume (float *i1, float *i2, float *r)
+{
+  __m128 t1 = _mm_load_ps (i1);
+  __m128 t2 = _mm_load_ps (i2);
+
+  t1 = _mm_hsub_ps (t1, t2);
+
+  _mm_storeu_ps (r, t1);
+}
+
+static int
+chk_ps (float *v1, float *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 4; i++) {
+    if (v1[i] != v2[i]) {
+      n_fails += 1;
+    }
+  }
+
+  return n_fails;
+}
+
+static float p1[4] __attribute__ ((aligned(16)));
+static float p2[4] __attribute__ ((aligned(16)));
+static float p3[4];
+static float ck[4];
+
+static float vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 8)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = vals[i+1];
+      p1[2] = vals[i+2];
+      p1[3] = vals[i+3];
+
+      p2[0] = vals[i+4];
+      p2[1] = vals[i+5];
+      p2[2] = vals[i+6];
+      p2[3] = vals[i+7];
+
+      ck[0] = p1[0] - p1[1];
+      ck[1] = p1[2] - p1[3];
+      ck[2] = p2[0] - p2[1];
+      ck[3] = p2[2] - p2[3];
+
+      sse3_test_hsubps (p1, p2, p3);
+
+      fail += chk_ps (ck, p3);
+
+      sse3_test_hsubps_subsume (p1, p2, p3);
+
+      fail += chk_ps (ck, p3);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-lddqu.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-lddqu.c
new file mode 100644
index 000000000..5df19a62a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-lddqu.c
@@ -0,0 +1,75 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+#include <pmmintrin.h>
+
+static void
+sse3_test_lddqu (double *i1, double *r)
+{
+  __m128i t1 = _mm_lddqu_si128 ((__m128i *) i1);
+
+  _mm_storeu_si128 ((__m128i *) r, t1);
+}
+
+static int
+chk_pd (double *v1, double *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 2; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static double p1[2];
+static double p2[2];
+static double ck[2];
+
+static double vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 2)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = vals[i+1];
+
+      sse3_test_lddqu (p1, p2);
+
+      ck[0] = p1[0];
+      ck[1] = p1[1];
+
+      fail += chk_pd (ck, p2);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-movddup.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-movddup.c
new file mode 100644
index 000000000..2eb33ad49
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-movddup.c
@@ -0,0 +1,132 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+
+#include <pmmintrin.h>
+
+static void
+sse3_test_movddup_mem (double *i1, double *r)
+{
+  __m128d t1 = _mm_loaddup_pd (i1);
+
+  _mm_storeu_pd (r, t1);
+}
+
+static double cnst1 [2] = {1.0, 1.0};
+
+static void
+sse3_test_movddup_reg (double *i1, double *r)
+{
+  __m128d t1 = _mm_loadu_pd (i1);
+  __m128d t2 = _mm_loadu_pd (&cnst1[0]);
+
+  t1  = _mm_mul_pd (t1, t2);
+  t2  = _mm_movedup_pd (t1);
+
+  _mm_storeu_pd (r, t2);
+}
+
+static void
+sse3_test_movddup_reg_subsume_unaligned (double *i1, double *r)
+{
+  __m128d t1 = _mm_loadu_pd (i1);
+  __m128d t2 = _mm_movedup_pd (t1);
+
+  _mm_storeu_pd (r, t2);
+}
+
+static void
+sse3_test_movddup_reg_subsume_ldsd (double *i1, double *r)
+{
+  __m128d t1 = _mm_load_sd (i1);
+  __m128d t2 = _mm_movedup_pd (t1);
+
+  _mm_storeu_pd (r, t2);
+}
+
+static void
+sse3_test_movddup_reg_subsume (double *i1, double *r)
+{
+  __m128d t1 = _mm_load_pd (i1);
+  __m128d t2 = _mm_movedup_pd (t1);
+
+  _mm_storeu_pd (r, t2);
+}
+
+static int
+chk_pd (double *v1, double *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 2; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static double p1[2] __attribute__ ((aligned(16)));
+static double p2[2];
+static double ck[2];
+
+static double vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 1)
+    {
+      p1[0] = vals[i+0];
+
+      ck[0] = p1[0];
+      ck[1] = p1[0];
+
+      sse3_test_movddup_mem (p1, p2);
+
+      fail += chk_pd (ck, p2);
+
+      sse3_test_movddup_reg (p1, p2);
+
+      fail += chk_pd (ck, p2);
+
+      sse3_test_movddup_reg_subsume (p1, p2);
+
+      fail += chk_pd (ck, p2);
+
+      sse3_test_movddup_reg_subsume_unaligned (p1, p2);
+
+      fail += chk_pd (ck, p2);
+
+      sse3_test_movddup_reg_subsume_ldsd (p1, p2);
+
+      fail += chk_pd (ck, p2);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-movshdup.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-movshdup.c
new file mode 100644
index 000000000..8f6706cf9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-movshdup.c
@@ -0,0 +1,94 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+
+#include <pmmintrin.h>
+
+static void
+sse3_test_movshdup_reg (float *i1, float *r)
+{
+  __m128 t1 = _mm_loadu_ps (i1);
+  __m128 t2 = _mm_movehdup_ps (t1);
+
+  _mm_storeu_ps (r, t2);
+}
+
+static void
+sse3_test_movshdup_reg_subsume (float *i1, float *r)
+{
+  __m128 t1 = _mm_load_ps (i1);
+  __m128 t2 = _mm_movehdup_ps (t1);
+
+  _mm_storeu_ps (r, t2);
+}
+
+static int
+chk_ps (float *v1, float *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 4; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static float p1[4] __attribute__ ((aligned(16)));
+static float p2[4];
+static float ck[4];
+
+static float vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 2)
+    {
+      p1[0] = 0.0;
+      p1[1] = vals[i+0];
+      p1[2] = 1.0;
+      p1[3] = vals[i+1];
+
+      ck[0] = p1[1];
+      ck[1] = p1[1];
+      ck[2] = p1[3];
+      ck[3] = p1[3];
+
+      sse3_test_movshdup_reg (p1, p2);
+
+      fail += chk_ps (ck, p2);
+
+      sse3_test_movshdup_reg_subsume (p1, p2);
+
+      fail += chk_ps (ck, p2);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-movsldup.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-movsldup.c
new file mode 100644
index 000000000..9ae8454e0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse3-movsldup.c
@@ -0,0 +1,94 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+
+#include <pmmintrin.h>
+
+static void
+sse3_test_movsldup_reg (float *i1, float *r)
+{
+  __m128 t1 = _mm_loadu_ps (i1);
+  __m128 t2 = _mm_moveldup_ps (t1);
+
+  _mm_storeu_ps (r, t2);
+}
+
+static void
+sse3_test_movsldup_reg_subsume (float *i1, float *r)
+{
+  __m128 t1 = _mm_load_ps (i1);
+  __m128 t2 = _mm_moveldup_ps (t1);
+
+  _mm_storeu_ps (r, t2);
+}
+
+static int
+chk_ps (float *v1, float *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 4; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static float p1[4] __attribute__ ((aligned(16)));
+static float p2[4];
+static float ck[4];
+
+static float vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 2)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = 0.0;
+      p1[2] = vals[i+1];
+      p1[3] = 1.0;
+
+      ck[0] = p1[0];
+      ck[1] = p1[0];
+      ck[2] = p1[2];
+      ck[3] = p1[2];
+
+      sse3_test_movsldup_reg (p1, p2);
+
+      fail += chk_ps (ck, p2);
+
+      sse3_test_movsldup_reg_subsume (p1, p2);
+
+      fail += chk_ps (ck, p2);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-blendpd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-blendpd.c
new file mode 100644
index 000000000..aff188c63
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-blendpd.c
@@ -0,0 +1,89 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+#ifndef MASK
+#define MASK 0x03
+#endif
+
+static void
+init_blendpd (double *src1, double *src2)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < NUM * 2; i++)
+    {
+      src1[i] = i * i * sign;
+      src2[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+}
+
+static int
+check_blendpd (__m128d *dst, double *src1, double *src2)
+{
+  double tmp[2];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+
+  for(j = 0; j < 2; j++)
+    if ((MASK & (1 << j)))
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+TEST (void)
+{
+  __m128d x, y;
+  union
+    {
+      __m128d x[NUM];
+      double d[NUM * 2];
+    } dst, src1, src2;
+  union
+    {
+      __m128d x;
+      double d[2];
+    } src3;
+  int i;
+
+  init_blendpd (src1.d, src2.d);
+
+  /* Check blendpd imm8, m128, xmm */
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blend_pd (src1.x[i], src2.x[i], MASK);
+      if (check_blendpd (&dst.x[i], &src1.d[i * 2], &src2.d[i * 2]))
+	abort ();
+    }
+    
+  /* Check blendpd imm8, xmm, xmm */
+  src3.x = _mm_setzero_pd ();
+
+  x = _mm_blend_pd (dst.x[2], src3.x, MASK);
+  y = _mm_blend_pd (src3.x, dst.x[2], MASK);
+
+  if (check_blendpd (&x, &dst.d[4], &src3.d[0]))
+    abort ();
+
+  if (check_blendpd (&y, &src3.d[0], &dst.d[4]))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-blendps-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-blendps-2.c
new file mode 100644
index 000000000..b66bbfd3b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-blendps-2.c
@@ -0,0 +1,77 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+#undef MASK
+#define MASK 0xe
+
+static void
+init_blendps (float *src1, float *src2)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1[i] = i * i * sign;
+      src2[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+}
+
+static int
+check_blendps (__m128 *dst, float *src1, float *src2)
+{
+  float tmp[4];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+  for (j = 0; j < 4; j++)
+    if ((MASK & (1 << j)))
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+sse4_1_test (void)
+{
+  __m128 x, y;
+  union
+    {
+      __m128 x[NUM];
+      float f[NUM * 4];
+    } dst, src1, src2;
+  union
+    {
+      __m128 x;
+      float f[4];
+    } src3;
+  int i;
+
+  init_blendps (src1.f, src2.f);
+
+  /* Check blendps imm8, m128, xmm */
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blend_ps (src1.x[i], src2.x[i], MASK); 
+      if (check_blendps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4]))
+	abort ();
+    }
+    
+   /* Check blendps imm8, xmm, xmm */
+  x = _mm_blend_ps (dst.x[2], src3.x, MASK);
+  y = _mm_blend_ps (src3.x, dst.x[2], MASK);
+
+  if (check_blendps (&x, &dst.f[8], &src3.f[0]))
+    abort ();
+
+  if (check_blendps (&y, &src3.f[0], &dst.f[8]))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-blendps.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-blendps.c
new file mode 100644
index 000000000..b4d8e8ee1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-blendps.c
@@ -0,0 +1,86 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+#ifndef MASK
+#define MASK 0x0f
+#endif
+
+static void
+init_blendps (float *src1, float *src2)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1[i] = i * i * sign;
+      src2[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+}
+
+static int
+check_blendps (__m128 *dst, float *src1, float *src2)
+{
+  float tmp[4];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+  for (j = 0; j < 4; j++)
+    if ((MASK & (1 << j)))
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+TEST (void)
+{
+  __m128 x, y;
+  union
+    {
+      __m128 x[NUM];
+      float f[NUM * 4];
+    } dst, src1, src2;
+  union
+    {
+      __m128 x;
+      float f[4];
+    } src3;
+  int i;
+
+  init_blendps (src1.f, src2.f);
+
+  /* Check blendps imm8, m128, xmm */
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blend_ps (src1.x[i], src2.x[i], MASK); 
+      if (check_blendps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4]))
+	abort ();
+    }
+    
+   /* Check blendps imm8, xmm, xmm */
+  x = _mm_blend_ps (dst.x[2], src3.x, MASK);
+  y = _mm_blend_ps (src3.x, dst.x[2], MASK);
+
+  if (check_blendps (&x, &dst.f[8], &src3.f[0]))
+    abort ();
+
+  if (check_blendps (&y, &src3.f[0], &dst.f[8]))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-blendvpd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-blendvpd.c
new file mode 100644
index 000000000..8478234e2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-blendvpd.c
@@ -0,0 +1,65 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+static void
+init_blendvpd (double *src1, double *src2, double *mask)
+{
+  int i, msk, sign = 1; 
+
+  msk = -1;
+  for (i = 0; i < NUM * 2; i++)
+    {
+      if((i % 2) == 0)
+	msk++;
+      src1[i] = i* (i + 1) * sign;
+      src2[i] = (i + 20) * sign;
+      mask[i] = (i + 120) * i;
+      if( (msk & (1 << (i % 2))))
+	mask[i] = -mask[i];
+      sign = -sign;
+    }
+}
+
+static int
+check_blendvpd (__m128d *dst, double *src1, double *src2,
+		double *mask)
+{
+  double tmp[2];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+  for (j = 0; j < 2; j++)
+    if (mask [j] < 0.0)
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+sse4_1_test (void)
+{
+  union
+    {
+      __m128d x[NUM];
+      double d[NUM * 2];
+    } dst, src1, src2, mask;
+  int i;
+
+  init_blendvpd (src1.d, src2.d, mask.d);
+
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blendv_pd (src1.x[i], src2.x[i], mask.x[i]);
+      if (check_blendvpd (&dst.x[i], &src1.d[i * 2], &src2.d[i * 2],
+			  &mask.d[i * 2]))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-blendvps.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-blendvps.c
new file mode 100644
index 000000000..7ff464900
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-blendvps.c
@@ -0,0 +1,65 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+static void
+init_blendvps (float *src1, float *src2, float *mask)
+{
+  int i, msk, sign = 1; 
+
+  msk = -1;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      if((i % 4) == 0)
+	msk++;
+      src1[i] = i* (i + 1) * sign;
+      src2[i] = (i + 20) * sign;
+      mask[i] = (i + 120) * i;
+      if( (msk & (1 << (i % 4))))
+	mask[i] = -mask[i];
+      sign = -sign;
+    }
+}
+
+static int
+check_blendvps (__m128 *dst, float *src1, float *src2,
+		float *mask)
+{
+  float tmp[4];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+  for (j = 0; j < 4; j++)
+    if (mask [j] < 0.0)
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+sse4_1_test (void)
+{
+  union
+    {
+      __m128 x[NUM];
+      float f[NUM * 4];
+    } dst, src1, src2, mask;
+  int i;
+
+  init_blendvps (src1.f, src2.f, mask.f);
+
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blendv_ps (src1.x[i], src2.x[i], mask.x[i]);
+      if (check_blendvps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4],
+			  &mask.f[i * 4]))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-check.h
new file mode 100644
index 000000000..2d1c4e835
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-check.h
@@ -0,0 +1,23 @@
+#include <stdlib.h>
+
+#include "cpuid.h"
+#include "m128-check.h"
+
+static void sse4_1_test (void);
+
+#define MASK 0x2
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run SSE4.1 test only if host has SSE4.1 support.  */
+  if (ecx & bit_SSE4_1)
+    sse4_1_test ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-dppd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-dppd-1.c
new file mode 100644
index 000000000..b8e58d47a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-dppd-1.c
@@ -0,0 +1,71 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define lmskN  0x00
+#define lmsk0  0x01
+#define lmsk1  0x02
+#define lmsk01 0x03
+
+#define hmskA  0x30
+#define hmsk0  0x10
+#define hmsk1  0x20
+#define hmsk01 0x30
+#define hmskN  0x00
+
+#ifndef HIMASK
+#define HIMASK hmskA
+#endif
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128d x;
+      double d[2];
+    } val1, val2, res[4];
+  int masks[4];
+  int i, j;
+
+  val1.d[0] = 2.;
+  val1.d[1] = 3.;
+
+  val2.d[0] = 10.;
+  val2.d[1] = 100.;
+
+  res[0].x = _mm_dp_pd (val1.x, val2.x, HIMASK | lmskN);
+  res[1].x = _mm_dp_pd (val1.x, val2.x, HIMASK | lmsk0);
+  res[2].x = _mm_dp_pd (val1.x, val2.x, HIMASK | lmsk1);
+  res[3].x = _mm_dp_pd (val1.x, val2.x, HIMASK | lmsk01);
+
+  masks[0] = HIMASK | lmskN;
+  masks[1] = HIMASK | lmsk0;
+  masks[2] = HIMASK | lmsk1;
+  masks[3] = HIMASK | lmsk01; 
+
+  for (i = 0; i < 4; i++)
+    {
+      double tmp = 0.;
+
+      for (j = 0; j < 2; j++)
+	if (HIMASK & (0x10 << j))
+	  tmp = tmp + (val1.d[j] * val2.d[j]);
+
+      for (j = 0; j < 2; j++)
+	if ((masks[i] & (1 << j)) && res[i].d[j] != tmp)
+	  abort ();
+   }
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-dppd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-dppd-2.c
new file mode 100644
index 000000000..6dc328c05
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-dppd-2.c
@@ -0,0 +1,73 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#include <string.h>
+
+#define lmskN  0x00
+#define lmsk0  0x01
+#define lmsk1  0x02
+#define lmsk01 0x03
+
+#define hmskA  0x30
+#define hmsk0  0x10
+#define hmsk1  0x20
+#define hmsk01 0x30
+#define hmskN  0x00
+
+#ifndef HIMASK
+#define HIMASK hmskA
+#endif
+
+#ifndef LOMASK
+#define LOMASK lmsk01
+#endif
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128d x;
+      double d[2];
+    } val1[4], val2[4], res[4], chk[4];
+  int i, j;
+  double tmp;
+
+  for (i = 0; i < 4; i++)
+    {
+      val1[i].d [0] = 2.;
+      val1[i].d [1] = 3.;
+
+      val2[i].d [0] = 10.;
+      val2[i].d [1] = 100.;
+
+      tmp = 0.;
+      for (j = 0; j < 2; j++)
+	if ((HIMASK & (0x10 << j)))
+	  tmp += val1[i].d [j] * val2[i].d [j];
+
+      for (j = 0; j < 2; j++)
+        if ((LOMASK & (1 << j)))
+	  chk[i].d[j] = tmp;
+    }
+
+  for (i = 0; i < 4; i++)
+    {
+      res[i].x = _mm_dp_pd (val1[i].x, val2[i].x, HIMASK | LOMASK); 
+      if (memcmp (&res[i], &chk[i], sizeof (chk[i])))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-dpps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-dpps-1.c
new file mode 100644
index 000000000..77232567c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-dpps-1.c
@@ -0,0 +1,114 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define lmskN  0x00
+#define lmsk0  0x01
+#define lmsk1  0x02
+#define lmsk2  0x04
+#define lmsk3  0x08
+#define lmsk01 0x03
+#define lmsk02 0x05
+#define lmsk03 0x09
+#define lmsk12 0x06
+#define lmsk13 0x0A
+#define lmsk23 0x0C
+#define lmskA  0x0F
+
+#define hmskN  0x00
+#define hmskA  0xF0
+#define hmsk0  0x10
+#define hmsk1  0x20
+#define hmsk2  0x40
+#define hmsk3  0x80
+#define hmsk01 0x30
+#define hmsk02 0x50
+#define hmsk03 0x90
+#define hmsk12 0x60
+#define hmsk13 0xA0
+#define hmsk23 0xC0
+
+#ifndef HIMASK
+#define HIMASK hmskA
+#endif
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } val1, val2, res[16];
+  int masks[16];
+  int i, j;
+
+  val1.f[0] = 2.;
+  val1.f[1] = 3.;
+  val1.f[2] = 4.;
+  val1.f[3] = 5.;
+
+  val2.f[0] = 10.;
+  val2.f[1] = 100.;
+  val2.f[2] = 1000.;
+  val2.f[3] = 10000.;
+
+  res[0].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk0); 
+  res[1].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk1); 
+  res[2].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk2); 
+  res[3].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk3); 
+  res[4].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk01); 
+  res[5].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk02); 
+  res[6].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk03); 
+  res[7].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk12); 
+  res[8].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk13); 
+  res[9].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk23); 
+  res[10].x = _mm_dp_ps (val1.x, val2.x, HIMASK | (0x0F & ~lmsk0)); 
+  res[11].x = _mm_dp_ps (val1.x, val2.x, HIMASK | (0x0F & ~lmsk1)); 
+  res[12].x = _mm_dp_ps (val1.x, val2.x, HIMASK | (0x0F & ~lmsk2)); 
+  res[13].x = _mm_dp_ps (val1.x, val2.x, HIMASK | (0x0F & ~lmsk3)); 
+  res[14].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmskN); 
+  res[15].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmskA); 
+
+  masks[0] = HIMASK | lmsk0; 
+  masks[1] = HIMASK | lmsk1; 
+  masks[2] = HIMASK | lmsk2; 
+  masks[3] = HIMASK | lmsk3; 
+  masks[4] = HIMASK | lmsk01; 
+  masks[5] = HIMASK | lmsk02; 
+  masks[6] = HIMASK | lmsk03; 
+  masks[7] = HIMASK | lmsk12; 
+  masks[8] = HIMASK | lmsk13; 
+  masks[9] = HIMASK | lmsk23; 
+  masks[10] = HIMASK | (0x0F & ~lmsk0); 
+  masks[11] = HIMASK | (0x0F & ~lmsk1); 
+  masks[12] = HIMASK | (0x0F & ~lmsk2); 
+  masks[13] = HIMASK | (0x0F & ~lmsk3); 
+  masks[14] = HIMASK | lmskN; 
+  masks[15] = HIMASK | lmskA; 
+
+  for (i = 0; i <= 15; i++)
+    {
+      float tmp = 0.;
+
+      for (j = 0; j < 4; j++)
+	if ((HIMASK & (0x10 << j)))
+	  tmp += val1.f[j] * val2.f[j];
+
+      for (j = 0; j < 4; j++)
+	if ((masks[i] & (1 << j)) && res[i].f[j] != tmp)
+	  abort ();
+   }
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-dpps-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-dpps-2.c
new file mode 100644
index 000000000..48483b6c8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-dpps-2.c
@@ -0,0 +1,92 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#include <string.h>
+
+#define lmskN  0x00
+#define lmsk0  0x01
+#define lmsk1  0x02
+#define lmsk2  0x04
+#define lmsk3  0x08
+#define lmsk01 0x03
+#define lmsk02 0x05
+#define lmsk03 0x09
+#define lmsk12 0x06
+#define lmsk13 0x0A
+#define lmsk23 0x0C
+#define lmskA  0x0F
+
+#define hmskN  0x00
+#define hmskA  0xF0
+#define hmsk0  0x10
+#define hmsk1  0x20
+#define hmsk2  0x40
+#define hmsk3  0x80
+#define hmsk01 0x30
+#define hmsk02 0x50
+#define hmsk03 0x90
+#define hmsk12 0x60
+#define hmsk13 0xA0
+#define hmsk23 0xC0
+
+#ifndef HIMASK
+#define HIMASK hmskA
+#endif
+
+#ifndef LOMASK
+#define LOMASK lmskA
+#endif
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } val1[16], val2[16], res[16], chk[16];
+  int i,j;
+  float tmp;
+
+  for (i = 0; i < 16; i++)
+    {
+      val1[i].f[0] = 2.;
+      val1[i].f[1] = 3.;
+      val1[i].f[2] = 4.;
+      val1[i].f[3] = 5.;
+
+      val2[i].f[0] = 10.;
+      val2[i].f[1] = 100.;
+      val2[i].f[2] = 1000.;
+      val2[i].f[3] = 10000.;
+
+      tmp = 0.;
+      for (j = 0; j < 4; j++)
+        if ((HIMASK & (0x10 << j)))
+	  tmp += val1[i].f [j] * val2[i].f [j];
+
+      for (j = 0; j < 4; j++)
+	if ((LOMASK & (1 << j)))
+	  chk[i].f[j] = tmp;
+    }
+
+   for (i = 0; i < 16; i++)
+     {
+       res[i].x = _mm_dp_ps (val1[i].x, val2[i].x, HIMASK | LOMASK);
+       if (memcmp (&res[i], &chk[i], sizeof (chk[i])))
+	 abort ();
+     }
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-extractps.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-extractps.c
new file mode 100644
index 000000000..d63296fe2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-extractps.c
@@ -0,0 +1,72 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+int masks[4];
+
+#define msk0 0x00
+#define msk1 0x01
+#define msk2 0x02
+#define msk3 0x03
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } val1, val2;
+  union
+    {
+      int i;
+      float f;
+    } res[4];
+  float resm[4];
+  int i;
+
+  val1.f[0] = 10.;
+  val1.f[1] = 2.;
+  val1.f[2] = 3.;
+  val1.f[3] = 40.;
+
+  val2.f[0] = 77.;
+  val2.f[1] = 21.;
+  val2.f[2] = 34.;
+  val2.f[3] = 49.;
+
+  res[0].i = _mm_extract_ps (val1.x, msk0);
+  res[1].i = _mm_extract_ps (val1.x, msk1);
+  res[2].i = _mm_extract_ps (val1.x, msk2);
+  res[3].i = _mm_extract_ps (val1.x, msk3);
+
+  _MM_EXTRACT_FLOAT (resm[0], val2.x, msk0);
+  _MM_EXTRACT_FLOAT (resm[1], val2.x, msk1);
+  _MM_EXTRACT_FLOAT (resm[2], val2.x, msk2);
+  _MM_EXTRACT_FLOAT (resm[3], val2.x, msk3);
+  
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+
+  for( i=0; i < 4; i++ )
+    {
+      if (res[i].f != val1.f[masks[i]])
+	abort ();
+      if (resm[i] != val2.f[masks[i]])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-init-v16qi-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-init-v16qi-1.c
new file mode 100644
index 000000000..6a3ccee58
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-init-v16qi-1.c
@@ -0,0 +1,77 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128i x, unsigned char *v, int j)
+{
+  union
+    {
+      __m128i x;
+      unsigned char i[16];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned char *v)
+{
+  __m128i x;
+
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[3], 0, 0, 0);
+  check (x, v, 3);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[4], 0, 0, 0, 0);
+  check (x, v, 4);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[5], 0, 0, 0, 0, 0);
+  check (x, v, 5);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, v[6], 0, 0, 0, 0, 0, 0);
+  check (x, v, 6);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, v[7], 0, 0, 0, 0, 0, 0, 0);
+  check (x, v, 7);
+}
+
+static void
+sse4_1_test (void)
+{
+  unsigned char v[16]
+    = { 0x7B, 0x5B, 0x54, 0x65, 0x73, 0x74, 0x56, 0x65,
+	0x63, 0x74, 0x6F, 0x72, 0x5D, 0x53, 0x47, 0x5D };
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-init-v2di-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-init-v2di-1.c
new file mode 100644
index 000000000..cd9fa7978
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-init-v2di-1.c
@@ -0,0 +1,64 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128i x, unsigned long long *v, int j)
+{
+  union
+    {
+      __m128i x;
+      unsigned long long i[2];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%llx != 0x%llx\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%llx != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned long long *v)
+{
+  __m128i x;
+
+  x = _mm_set_epi64x (0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_epi64x (v[1], 0);
+  check (x, v, 1);
+}
+
+static void
+sse4_1_test (void)
+{
+  unsigned long long v[2]
+    = { 0x7B5B546573745665LL, 0x63746F725D53475DLL };
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-init-v4sf-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-init-v4sf-1.c
new file mode 100644
index 000000000..f97604235
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-init-v4sf-1.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128 x, float *v, int j)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.f[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: %f != %f\n", i, v[i], u.f[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.f[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: %f != 0\n", i, u.f[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (float *v)
+{
+  __m128 x;
+
+  x = _mm_set_ps (0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_ps (0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_ps (0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_ps (v[3], 0, 0, 0);
+  check (x, v, 3);
+}
+
+static void
+sse4_1_test (void)
+{
+  float v[4] = { -3, 2, 1, 9 };
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-init-v4si-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-init-v4si-1.c
new file mode 100644
index 000000000..63501b7ee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-init-v4si-1.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128i x, unsigned int *v, int j)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned int *v)
+{
+  __m128i x;
+
+  x = _mm_set_epi32 (0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_epi32 (0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_epi32 (0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_epi32 (v[3], 0, 0, 0);
+  check (x, v, 3);
+}
+
+static void
+sse4_1_test (void)
+{
+  unsigned int v[4]
+    = { 0x7B5B5465, 0x73745665, 0x63746F72, 0x5D53475D };
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-insertps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-insertps-1.c
new file mode 100644
index 000000000..2f5741288
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-insertps-1.c
@@ -0,0 +1,79 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define msk0 0x01
+#define msk1 0x10
+#define msk2 0x29
+#define msk3 0x30
+
+#define msk4 0xFC
+#define msk5 0x05
+#define msk6 0x0A
+#define msk7 0x0F
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } res[8], val1, val2, tmp;
+  int masks[8];
+  int i, j;
+
+  val2.f[0] = 55.0;
+  val2.f[1] = 55.0;
+  val2.f[2] = 55.0;
+  val2.f[3] = 55.0;
+
+  val1.f[0] = 1.;
+  val1.f[1] = 2.;
+  val1.f[2] = 3.;
+  val1.f[3] = 4.;
+
+  res[0].x = _mm_insert_ps (val2.x, val1.x, msk0);
+  res[1].x = _mm_insert_ps (val2.x, val1.x, msk1);
+  res[2].x = _mm_insert_ps (val2.x, val1.x, msk2);
+  res[3].x = _mm_insert_ps (val2.x, val1.x, msk3);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+
+  for (i = 0; i < 4; i++)
+    res[i + 4].x = _mm_insert_ps (val2.x, val1.x, msk4);
+
+  masks[4] = msk4;
+  masks[5] = msk4;
+  masks[6] = msk4;
+  masks[7] = msk4;
+
+  for (i=0; i < 8; i++)
+    {
+      tmp = val2;
+      tmp.f[(masks[i] & 0x30) >> 4] = val1.f[(masks[i] & 0xC0) >> 6];
+
+      for (j = 0; j < 4; j++)
+	if (masks[i] & (0x1 << j))
+	  tmp.f[j] = 0.f;
+
+      if (memcmp (&res[i], &tmp, sizeof (tmp)))
+	abort ();
+    }
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-insertps-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-insertps-2.c
new file mode 100644
index 000000000..fbb96ca50
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-insertps-2.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+static void
+TEST (void)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } vals[4], val;
+  int i, j;
+
+  val.f[0]= 1.;
+  val.f[1]= 2.;
+  val.f[2]= 3.;
+  val.f[3]= 4.;
+
+  vals[0].x = _MM_PICK_OUT_PS (val.x, 0);
+  vals[1].x = _MM_PICK_OUT_PS (val.x, 1);
+  vals[2].x = _MM_PICK_OUT_PS (val.x, 2);
+  vals[3].x = _MM_PICK_OUT_PS (val.x, 3);
+
+  for (i = 0; i < 4; i++)
+    for (j = 0; j < 4; j++)
+      if ((j != 0 && vals[i].f[j] != 0)
+	  || (j == 0 && vals[i].f[j] != val.f[i]))
+	abort ();
+
+  if (_MM_MK_INSERTPS_NDX(0, 0, 0x1) != 0x01
+      || _MM_MK_INSERTPS_NDX(0, 1, 0x2) != 0x12
+      || _MM_MK_INSERTPS_NDX(0, 2, 0x3) != 0x23
+      || _MM_MK_INSERTPS_NDX(0, 3, 0x4) != 0x34
+      || _MM_MK_INSERTPS_NDX(1, 0, 0x5) != 0x45
+      || _MM_MK_INSERTPS_NDX(1, 1, 0x6) != 0x56
+      || _MM_MK_INSERTPS_NDX(2, 2, 0x7) != 0xA7
+      || _MM_MK_INSERTPS_NDX(3, 3, 0x8) != 0xF8)
+    abort ();
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-movntdqa.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-movntdqa.c
new file mode 100644
index 000000000..bc5cf2383
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-movntdqa.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+static void
+init_movntdqa (int *src)
+{
+  int i, j, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    for (j = 0; j < 4; j++)
+      {
+	src[i * 4 + j] = j * i * i * sign;
+	sign = -sign;
+      }
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      int i[NUM * 4];
+    } dst, src;
+  int i;
+
+  init_movntdqa (src.i);
+
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_stream_load_si128 (&src.x[i]);
+
+  for (i = 0; i < NUM; i++)
+    if (memcmp (&dst.x[i], &src.x[i], sizeof(src.x[i])))
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-mpsadbw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-mpsadbw.c
new file mode 100644
index 000000000..0fc24e861
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-mpsadbw.c
@@ -0,0 +1,130 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define msk0 0xC0
+#define msk1 0x01
+#define msk2 0xF2
+#define msk3 0x03
+#define msk4 0x84
+#define msk5 0x05
+#define msk6 0xE6
+#define msk7 0x67
+
+static __m128i
+compute_mpsadbw (unsigned char *v1, unsigned char *v2, int mask)
+{
+  union
+    {
+      __m128i x;
+      unsigned short s[8];
+    } ret;
+  unsigned char s[4];
+  int i, j;
+  int offs1, offs2;
+
+  offs2 = 4 * (mask & 3);
+  for (i = 0; i < 4; i++)
+    s[i] = v2[offs2 + i];
+
+  offs1 = 4 * ((mask & 4) >> 2);
+  for (j = 0; j < 8; j++)
+    {
+      ret.s[j] = 0;
+      for (i = 0; i < 4; i++)
+	ret.s[j] += abs (v1[offs1 + j + i] - s[i]);
+    }
+
+  return ret.x;
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+      unsigned char c[16];
+    } val1, val2, val3 [8];
+  __m128i res[8], tmp;
+  unsigned char masks[8];
+  int i;
+
+  val1.i[0] = 0x35251505;
+  val1.i[1] = 0x75655545;
+  val1.i[2] = 0xB5A59585;
+  val1.i[3] = 0xF5E5D5C5;
+
+  val2.i[0] = 0x31211101;
+  val2.i[1] = 0x71615141;
+  val2.i[2] = 0xB1A19181;
+  val2.i[3] = 0xF1E1D1C1;
+
+  for (i=0; i < 8; i++)
+    switch (i % 3)
+      {
+      case 1:
+	val3[i].i[0] = 0xF1E1D1C1;
+	val3[i].i[1] = 0xB1A19181;
+	val3[i].i[2] = 0x71615141;
+	val3[i].i[3] = 0x31211101;
+	break;
+      default:
+	val3[i].x = val2.x;
+	break;
+      }
+
+  /* Check mpsadbw imm8, xmm, xmm.  */
+  res[0] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk0);
+  res[1] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk1);
+  res[2] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk2);
+  res[3] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk3);
+  res[4] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk4);
+  res[5] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk5);
+  res[6] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk6);
+  res[7] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk7);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+  masks[4] = msk4;
+  masks[5] = msk5;
+  masks[6] = msk6;
+  masks[7] = msk7;
+
+  for (i=0; i < 8; i++)
+    {
+      tmp = compute_mpsadbw (val1.c, val2.c, masks[i]);
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+    
+  /* Check mpsadbw imm8, m128, xmm.  */
+  for (i=0; i < 8; i++)
+    {
+      res[i] = _mm_mpsadbw_epu8 (val1.x, val3[i].x, msk4);
+      masks[i] = msk4;
+    }
+
+  for (i=0; i < 8; i++)
+    {
+      tmp = compute_mpsadbw (val1.c, val3[i].c, masks[i]);
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-packusdw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-packusdw.c
new file mode 100644
index 000000000..f98157794
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-packusdw.c
@@ -0,0 +1,73 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static unsigned short
+int_to_ushort (int iVal)
+{
+  unsigned short sVal;
+
+  if (iVal < 0)
+    sVal = 0;
+  else if (iVal > 0xffff)
+    sVal = 0xffff;
+  else sVal = iVal;
+
+  return sVal;
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      int i[NUM];
+    } src1, src2;
+  union
+    {
+      __m128i x[NUM / 4];
+      unsigned short s[NUM * 2];
+    } dst;
+  int i, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i * sign;
+      src2.i[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x[i / 4] = _mm_packus_epi32 (src1.x [i / 4], src2.x [i / 4]);
+
+  for (i = 0; i < NUM; i ++)
+    {
+      int dstIndex;
+      unsigned short sVal;
+
+      sVal = int_to_ushort (src1.i[i]);
+      dstIndex = (i % 4) + (i / 4) * 8;
+      if (sVal != dst.s[dstIndex])
+	abort ();
+
+      sVal = int_to_ushort (src2.i[i]);
+      dstIndex += 4;
+      if (sVal != dst.s[dstIndex])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pblendvb.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pblendvb.c
new file mode 100644
index 000000000..58e94471e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pblendvb.c
@@ -0,0 +1,70 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+static void
+init_pblendvb (unsigned char *src1, unsigned char *src2,
+	       unsigned char *mask)
+{
+  int i, sign = 1; 
+
+  for (i = 0; i < NUM * 16; i++)
+    {
+      src1[i] = i* i * sign;
+      src2[i] = (i + 20) * sign;
+      mask[i] = (i % 3) + ((i * (14 + sign))
+			   ^ (src1[i] | src2[i] | (i*3)));
+      sign = -sign;
+    }
+}
+
+static int
+check_pblendvb (__m128i *dst, unsigned char *src1,
+		unsigned char *src2, unsigned char *mask)
+{
+  unsigned char tmp[16];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+  for (j = 0; j < 16; j++)
+    if (mask [j] & 0x80)
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      unsigned char c[NUM * 16];
+    } dst, src1, src2, mask;
+  int i;
+
+  init_pblendvb (src1.c, src2.c, mask.c);
+
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blendv_epi8 (src1.x[i], src2.x[i], mask.x[i]);
+      if (check_pblendvb (&dst.x[i], &src1.c[i * 16], &src2.c[i * 16],
+			  &mask.c[i * 16]))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pblendw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pblendw-2.c
new file mode 100644
index 000000000..eecc6edf6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pblendw-2.c
@@ -0,0 +1,79 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+#undef MASK
+#define MASK 0xfe
+
+static void
+init_pblendw (short *src1, short *src2)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < NUM * 8; i++)
+    {
+      src1[i] = i * i * sign;
+      src2[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+}
+
+static int
+check_pblendw (__m128i *dst, short *src1, short *src2)
+{
+  short tmp[8];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+  for (j = 0; j < 8; j++)
+    if ((MASK & (1 << j)))
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+sse4_1_test (void)
+{
+  __m128i x, y;
+  union
+    {
+      __m128i x[NUM];
+      short s[NUM * 8];
+    } dst, src1, src2;
+  union
+    {
+      __m128i x;
+      short s[8];
+    } src3;
+  int i;
+
+  init_pblendw (src1.s, src2.s);
+
+  /* Check pblendw imm8, m128, xmm */
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blend_epi16 (src1.x[i], src2.x[i], MASK); 
+      if (check_pblendw (&dst.x[i], &src1.s[i * 8], &src2.s[i * 8]))
+	abort ();
+    }
+    
+   /* Check pblendw imm8, xmm, xmm */
+  src3.x = _mm_setzero_si128 ();
+
+  x = _mm_blend_epi16 (dst.x[2], src3.x, MASK);
+  y = _mm_blend_epi16 (src3.x, dst.x[2], MASK);
+
+  if (check_pblendw (&x, &dst.s[16], &src3.s[0]))
+    abort ();
+
+  if (check_pblendw (&y, &src3.s[0], &dst.s[16]))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pblendw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pblendw.c
new file mode 100644
index 000000000..5f5a25353
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pblendw.c
@@ -0,0 +1,88 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+#ifndef MASK
+#define MASK 0x0f
+#endif
+
+static void
+init_pblendw (short *src1, short *src2)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < NUM * 8; i++)
+    {
+      src1[i] = i * i * sign;
+      src2[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+}
+
+static int
+check_pblendw (__m128i *dst, short *src1, short *src2)
+{
+  short tmp[8];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+  for (j = 0; j < 8; j++)
+    if ((MASK & (1 << j)))
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+TEST (void)
+{
+  __m128i x, y;
+  union
+    {
+      __m128i x[NUM];
+      short s[NUM * 8];
+    } dst, src1, src2;
+  union
+    {
+      __m128i x;
+      short s[8];
+    } src3;
+  int i;
+
+  init_pblendw (src1.s, src2.s);
+
+  /* Check pblendw imm8, m128, xmm */
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blend_epi16 (src1.x[i], src2.x[i], MASK); 
+      if (check_pblendw (&dst.x[i], &src1.s[i * 8], &src2.s[i * 8]))
+	abort ();
+    }
+    
+   /* Check pblendw imm8, xmm, xmm */
+  src3.x = _mm_setzero_si128 ();
+
+  x = _mm_blend_epi16 (dst.x[2], src3.x, MASK);
+  y = _mm_blend_epi16 (src3.x, dst.x[2], MASK);
+
+  if (check_pblendw (&x, &dst.s[16], &src3.s[0]))
+    abort ();
+
+  if (check_pblendw (&y, &src3.s[0], &dst.s[16]))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pcmpeqq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pcmpeqq.c
new file mode 100644
index 000000000..8611b8248
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pcmpeqq.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      long long ll[NUM];
+    } dst, src1, src2;
+  int i, sign=1;
+  long long is_eq;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.ll[i] = i * i * sign;
+      src2.ll[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x [i / 2] = _mm_cmpeq_epi64(src1.x [i / 2], src2.x [i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      is_eq = src1.ll[i] == src2.ll[i] ? 0xffffffffffffffffLL : 0LL;
+      if (is_eq != dst.ll[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pextrb.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pextrb.c
new file mode 100644
index 000000000..bef4d2d16
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pextrb.c
@@ -0,0 +1,87 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+#include <smmintrin.h>
+
+#define msk0   0
+#define msk1   1
+#define msk2   2
+#define msk3   3
+#define msk4   4
+#define msk5   5
+#define msk6   6
+#define msk7   7
+#define msk8   8
+#define msk9   9
+#define msk10 10
+#define msk11 11
+#define msk12 12
+#define msk13 13
+#define msk14 14
+#define msk15 15
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      int i[4];
+      char c[16];
+    } val1;
+  int res[16], masks[16];
+  int i;
+
+  val1.i[0] = 0x04030201;
+  val1.i[1] = 0x08070605;
+  val1.i[2] = 0x0C0B0A09;
+  val1.i[3] = 0x100F0E0D;
+
+  res[0] = _mm_extract_epi8 (val1.x, msk0);
+  res[1] = _mm_extract_epi8 (val1.x, msk1);
+  res[2] = _mm_extract_epi8 (val1.x, msk2);
+  res[3] = _mm_extract_epi8 (val1.x, msk3);
+  res[4] = _mm_extract_epi8 (val1.x, msk4);
+  res[5] = _mm_extract_epi8 (val1.x, msk5);
+  res[6] = _mm_extract_epi8 (val1.x, msk6);
+  res[7] = _mm_extract_epi8 (val1.x, msk7);
+  res[8] = _mm_extract_epi8 (val1.x, msk8);
+  res[9] = _mm_extract_epi8 (val1.x, msk9);
+  res[10] = _mm_extract_epi8 (val1.x, msk10);
+  res[11] = _mm_extract_epi8 (val1.x, msk11);
+  res[12] = _mm_extract_epi8 (val1.x, msk12);
+  res[13] = _mm_extract_epi8 (val1.x, msk13);
+  res[14] = _mm_extract_epi8 (val1.x, msk14);
+  res[15] = _mm_extract_epi8 (val1.x, msk15);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+  masks[4] = msk4;
+  masks[5] = msk5;
+  masks[6] = msk6;
+  masks[7] = msk7;
+  masks[8] = msk8;
+  masks[9] = msk9;
+  masks[10] = msk10;
+  masks[11] = msk11;
+  masks[12] = msk12;
+  masks[13] = msk13;
+  masks[14] = msk14;
+  masks[15] = msk15;
+
+  for (i = 0; i < 16; i++)
+    if (res[i] != val1.c [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pextrd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pextrd.c
new file mode 100644
index 000000000..3091e5a05
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pextrd.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+#include <smmintrin.h>
+
+
+#define msk0   0
+#define msk1   1
+#define msk2   2
+#define msk3   3
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      int i[4];
+    } val1;
+  int res[4], masks[4];
+  int i;
+
+  val1.i[0] = 0x04030201;
+  val1.i[1] = 0x08070605;
+  val1.i[2] = 0x0C0B0A09;
+  val1.i[3] = 0x100F0E0D;
+
+  res[0] = _mm_extract_epi32 (val1.x, msk0);
+  res[1] = _mm_extract_epi32 (val1.x, msk1);
+  res[2] = _mm_extract_epi32 (val1.x, msk2);
+  res[3] = _mm_extract_epi32 (val1.x, msk3);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+
+  for (i = 0; i < 4; i++)
+    if (res[i] != val1.i [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pextrq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pextrq.c
new file mode 100644
index 000000000..b90f4e2f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pextrq.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define msk0   0
+#define msk1   1
+
+static void
+__attribute__((noinline))
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      long long ll[2];
+    } val1;
+  long long res[2];
+  int masks[2];
+  int i;
+
+  val1.ll[0] = 0x0807060504030201LL;
+  val1.ll[1] = 0x100F0E0D0C0B0A09LL;
+
+  res[0] = _mm_extract_epi64 (val1.x, msk0);
+  res[1] = _mm_extract_epi64 (val1.x, msk1);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+
+  for (i = 0; i < 2; i++)
+    if (res[i] != val1.ll [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pextrw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pextrw.c
new file mode 100644
index 000000000..2a0f03c07
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pextrw.c
@@ -0,0 +1,64 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define msk0   0
+#define msk1   1
+#define msk2   2
+#define msk3   3
+#define msk4   4
+#define msk5   5
+#define msk6   6
+#define msk7   7
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      int i[4];
+      short s[8];
+    } val1;
+  int res[8], masks[8];
+  int i;
+
+  val1.i[0] = 0x04030201;
+  val1.i[1] = 0x08070605;
+  val1.i[2] = 0x0C0B0A09;
+  val1.i[3] = 0x100F0E0D;
+
+  res[0] = _mm_extract_epi16 (val1.x, msk0);
+  res[1] = _mm_extract_epi16 (val1.x, msk1);
+  res[2] = _mm_extract_epi16 (val1.x, msk2);
+  res[3] = _mm_extract_epi16 (val1.x, msk3);
+  res[4] = _mm_extract_epi16 (val1.x, msk4);
+  res[5] = _mm_extract_epi16 (val1.x, msk5);
+  res[6] = _mm_extract_epi16 (val1.x, msk6);
+  res[7] = _mm_extract_epi16 (val1.x, msk7);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+  masks[4] = msk4;
+  masks[5] = msk5;
+  masks[6] = msk6;
+  masks[7] = msk7;
+
+  for (i = 0; i < 8; i++)
+    if (res[i] != val1.s [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw.c
new file mode 100644
index 000000000..ab4683401
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM/8];
+      unsigned short s[NUM];
+    } src;
+  unsigned short minVal[NUM/8];
+  int minInd[NUM/8];
+  unsigned short minValScalar, minIndScalar;
+  int i, j, res;
+
+  for (i = 0; i < NUM; i++)
+    src.s[i] = i * i / (i + i / 3.14 + 1.0);
+
+  for (i = 0, j = 0; i < NUM; i += 8, j++)
+    {
+      res = _mm_cvtsi128_si32 (_mm_minpos_epu16 (src.x [i/8]));
+      minVal[j] = res & 0xffff;
+      minInd[j] = (res >> 16) & 0x3;
+    }
+
+  for (i = 0; i < NUM; i += 8)
+    {
+      minValScalar = src.s[i];
+      minIndScalar = 0;
+
+      for (j = i + 1; j < i + 8; j++)
+	if (minValScalar > src.s[j])
+	  {
+	    minValScalar = src.s[j];
+	    minIndScalar = j - i;
+	  }
+
+      if (minValScalar != minVal[i/8] && minIndScalar != minInd[i/8])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pinsrb.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pinsrb.c
new file mode 100644
index 000000000..18427360f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pinsrb.c
@@ -0,0 +1,110 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define msk0 0x00
+#define msk1 0x01
+#define msk2 0x02
+#define msk3 0x03
+#define msk4 0x04
+#define msk5 0x05
+#define msk6 0x06
+#define msk7 0x07
+#define msk8 0x08
+#define msk9 0x09
+#define mskA 0x0A
+#define mskB 0x0B
+#define mskC 0x0C
+#define mskD 0x0D
+#define mskE 0x0E
+#define mskF 0x0F
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+      unsigned char c[16];
+    } res [16], val, tmp;
+  int masks[16];
+  unsigned char ins[4] = { 3, 4, 5, 6 };
+  int i;
+
+  val.i[0] = 0x35251505;
+  val.i[1] = 0x75655545;
+  val.i[2] = 0xB5A59585;
+  val.i[3] = 0xF5E5D5C5;
+
+  /* Check pinsrb imm8, r32, xmm.  */
+  res[0].x = _mm_insert_epi8 (val.x, ins[0], msk0);
+  res[1].x = _mm_insert_epi8 (val.x, ins[0], msk1);
+  res[2].x = _mm_insert_epi8 (val.x, ins[0], msk2);
+  res[3].x = _mm_insert_epi8 (val.x, ins[0], msk3);
+  res[4].x = _mm_insert_epi8 (val.x, ins[0], msk4);
+  res[5].x = _mm_insert_epi8 (val.x, ins[0], msk5);
+  res[6].x = _mm_insert_epi8 (val.x, ins[0], msk6);
+  res[7].x = _mm_insert_epi8 (val.x, ins[0], msk7);
+  res[8].x = _mm_insert_epi8 (val.x, ins[0], msk8);
+  res[9].x = _mm_insert_epi8 (val.x, ins[0], msk9);
+  res[10].x = _mm_insert_epi8 (val.x, ins[0], mskA);
+  res[11].x = _mm_insert_epi8 (val.x, ins[0], mskB);
+  res[12].x = _mm_insert_epi8 (val.x, ins[0], mskC);
+  res[13].x = _mm_insert_epi8 (val.x, ins[0], mskD);
+  res[14].x = _mm_insert_epi8 (val.x, ins[0], mskE);
+  res[15].x = _mm_insert_epi8 (val.x, ins[0], mskF);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+  masks[4] = msk4;
+  masks[5] = msk5;
+  masks[6] = msk6;
+  masks[7] = msk7;
+  masks[8] = msk8;
+  masks[9] = msk9;
+  masks[10] = mskA;
+  masks[11] = mskB;
+  masks[12] = mskC;
+  masks[13] = mskD;
+  masks[14] = mskE;
+  masks[15] = mskF;
+
+  for (i = 0; i < 16; i++)
+    {
+      tmp.x = val.x;
+      tmp.c[masks[i]] = ins[0];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+    
+  /* Check pinsrb imm8, m8, xmm.  */
+  for (i = 0; i < 16; i++)
+    {
+      res[i].x = _mm_insert_epi8 (val.x, ins[i % 4], msk0);
+      masks[i] = msk0;
+    }
+
+  for (i = 0; i < 16; i++)
+    {
+      tmp.x = val.x;
+      tmp.c[masks[i]] = ins[i % 4];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pinsrd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pinsrd.c
new file mode 100644
index 000000000..7a5d5fbc9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pinsrd.c
@@ -0,0 +1,73 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define msk0 0x00
+#define msk1 0x01
+#define msk2 0x02
+#define msk3 0x03
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } res [4], val, tmp;
+  static unsigned int ins[4] = { 3, 4, 5, 6 };
+  int masks[4];
+  int i;
+
+  val.i[0] = 55;
+  val.i[1] = 55;
+  val.i[2] = 55;
+  val.i[3] = 55;
+
+  /* Check pinsrd imm8, r32, xmm.  */
+  res[0].x = _mm_insert_epi32 (val.x, ins[0], msk0);
+  res[1].x = _mm_insert_epi32 (val.x, ins[0], msk1);
+  res[2].x = _mm_insert_epi32 (val.x, ins[0], msk2);
+  res[3].x = _mm_insert_epi32 (val.x, ins[0], msk3);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+
+  for (i = 0; i < 4; i++)
+    {
+      tmp.x = val.x;
+      tmp.i[masks[i]] = ins[0];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+    
+  /* Check pinsrd imm8, m32, xmm.  */
+  for (i = 0; i < 4; i++)
+    {
+      res[i].x = _mm_insert_epi32 (val.x, ins[i], msk0);
+      masks[i] = msk0;
+    }
+
+  for (i = 0; i < 4; i++)
+    {
+      tmp.x = val.x;
+      tmp.i[masks[i]] = ins[i];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pinsrq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pinsrq.c
new file mode 100644
index 000000000..1640439e5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pinsrq.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define msk0 0x00
+#define msk1 0x01
+
+static void
+__attribute__((noinline))
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned long long ll[2];
+    } res [4], val, tmp;
+  int masks[4];
+  static unsigned long long ins[2] =
+    { 0xAABBAABBAABBAABBLL, 0xCCDDCCDDCCDDCCDDLL };
+  int i;
+
+  val.ll[0] = 0x0807060504030201LL;
+  val.ll[1] = 0x100F0E0D0C0B0A09LL;
+
+  /* Check pinsrq imm8, r64, xmm.  */
+  res[0].x = _mm_insert_epi64 (val.x, ins[0], msk0);
+  res[1].x = _mm_insert_epi64 (val.x, ins[0], msk1);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+
+  for (i = 0; i < 2; i++)
+    {
+      tmp.x = val.x;
+      tmp.ll[masks[i]] = ins[0];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+    
+  /* Check pinsrq imm8, m64, xmm.  */
+  for (i = 0; i < 2; i++)
+    {
+      res[i].x = _mm_insert_epi64 (val.x, ins[i], msk0);
+      masks[i] = msk0;
+    }
+
+  for (i = 0; i < 2; i++)
+    {
+      tmp.x = val.x;
+      tmp.ll[masks[i]] = ins[i];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsb.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsb.c
new file mode 100644
index 000000000..ab445eefd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsb.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 1024
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 16];
+      char i[NUM];
+    } dst, src1, src2;
+  int i, sign = 1;
+  char max;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i * sign;
+      src2.i[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 16)
+    dst.x[i / 16] = _mm_max_epi8 (src1.x[i / 16], src2.x[i / 16]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (max != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsd.c
new file mode 100644
index 000000000..37c77aef5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsd.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      int i[NUM];
+    } dst, src1, src2;
+  int i, sign = 1;
+  int max;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i * sign;
+      src2.i[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x[i / 4] = _mm_max_epi32 (src1.x[i / 4], src2.x[i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (max != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmaxud.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmaxud.c
new file mode 100644
index 000000000..693c078fe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmaxud.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      unsigned int i[NUM];
+    } dst, src1, src2;
+  int i;
+  unsigned int max;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i;
+      src2.i[i] = i + 20;
+      if ((i % 4))
+	src2.i[i] |= 0x80000000;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x[i / 4] = _mm_max_epu32 (src1.x[i / 4], src2.x[i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (max != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmaxuw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmaxuw.c
new file mode 100644
index 000000000..7b5cfcd8f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmaxuw.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 8];
+      unsigned short i[NUM];
+    } dst, src1, src2;
+  int i;
+  unsigned short max;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i;
+      src2.i[i] = i + 20;
+      if ((i % 8))
+	src2.i[i] |= 0x8000;
+    }
+
+  for (i = 0; i < NUM; i += 8)
+    dst.x[i / 8] = _mm_max_epu16 (src1.x[i / 8], src2.x[i / 8]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (max != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pminsb.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pminsb.c
new file mode 100644
index 000000000..6f32d8b83
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pminsb.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 1024
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 16];
+      char i[NUM];
+    } dst, src1, src2;
+  int i, sign = 1;
+  char min;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i * sign;
+      src2.i[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 16)
+    dst.x[i / 16] = _mm_min_epi8 (src1.x[i / 16], src2.x[i / 16]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (min != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pminsd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pminsd.c
new file mode 100644
index 000000000..a3de148a0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pminsd.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      int i[NUM];
+    } dst, src1, src2;
+  int i, sign = 1;
+  int min;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i * sign;
+      src2.i[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x[i / 4] = _mm_min_epi32 (src1.x[i / 4], src2.x[i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (min != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pminud.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pminud.c
new file mode 100644
index 000000000..9daffc070
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pminud.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      unsigned int i[NUM];
+    } dst, src1, src2;
+  int i;
+  unsigned int min;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i;
+      src2.i[i] = i + 20;
+      if ((i % 4))
+	src2.i[i] |= 0x80000000;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x[i / 4] = _mm_min_epu32 (src1.x[i / 4], src2.x[i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (min != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pminuw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pminuw.c
new file mode 100644
index 000000000..6ed5d9e2e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pminuw.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 8];
+      unsigned short i[NUM];
+    } dst, src1, src2;
+  int i;
+  unsigned short min;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i;
+      src2.i[i] = i + 20;
+      if ((i % 8))
+	src2.i[i] |= 0x8000;
+    }
+
+  for (i = 0; i < NUM; i += 8)
+    dst.x[i / 8] = _mm_min_epu16 (src1.x[i / 8], src2.x[i / 8]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (min != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbd.c
new file mode 100644
index 000000000..00ce3ef77
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbd.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      int i[NUM];
+      char c[NUM * 4];
+    } dst, src;
+  int i, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.c[(i % 4) + (i / 4) * 16] = i * i * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x [i / 4] = _mm_cvtepi8_epi32 (src.x [i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.c[(i % 4) + (i / 4) * 16] != dst.i[i])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbq.c
new file mode 100644
index 000000000..0df6a61c7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbq.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      long long ll[NUM];
+      char c[NUM * 8];
+    } dst, src;
+  int i, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.c[(i % 2) + (i / 2) * 16] = i * i * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x [i / 2] = _mm_cvtepi8_epi64 (src.x [i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.c[(i % 2) + (i / 2) * 16] != dst.ll[i])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbw.c
new file mode 100644
index 000000000..36accff4c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbw.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 8];
+      short s[NUM];
+      char c[NUM * 2];
+    } dst, src;
+  int i, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.c[(i % 8) + (i / 8) * 16] = i * i * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 8)
+    dst.x [i / 8] = _mm_cvtepi8_epi16 (src.x [i / 8]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.c[(i % 8) + (i / 8) * 16] != dst.s[i])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxdq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxdq.c
new file mode 100644
index 000000000..e46ba1961
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxdq.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      long long ll[NUM];
+      int i[NUM * 2];
+    } dst, src;
+  int i, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.i[(i % 2) + (i / 2) * 4] = i * i * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x [i / 2] = _mm_cvtepi32_epi64 (src.x [i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.i[(i % 2) + (i / 2) * 4] != dst.ll[i])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwd.c
new file mode 100644
index 000000000..61d9d3c2e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwd.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      int i[NUM];
+      short s[NUM * 2];
+    } dst, src;
+  int i, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.s[(i % 4) + (i / 4) * 8] = i * i * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x [i / 4] = _mm_cvtepi16_epi32 (src.x [i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.s[(i % 4) + (i / 4) * 8] != dst.i[i])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwq.c
new file mode 100644
index 000000000..160d6467d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwq.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      long long ll[NUM];
+      short s[NUM * 4];
+    } dst, src;
+  int i, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.s[(i % 2) + (i / 2) * 8] = i * i * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x [i / 2] = _mm_cvtepi16_epi64 (src.x [i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.s[(i % 2) + (i / 2) * 8] != dst.ll[i])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbd.c
new file mode 100644
index 000000000..6ebd6cf4e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbd.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      unsigned int i[NUM];
+      unsigned char c[NUM * 4];
+    } dst, src;
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.c[(i % 4) + (i / 4) * 16] = i * i;
+      if ((i % 4))
+	src.c[(i % 4) + (i / 4) * 16] |= 0x80;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x [i / 4] = _mm_cvtepu8_epi32 (src.x [i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.c[(i % 4) + (i / 4) * 16] != dst.i[i])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbq.c
new file mode 100644
index 000000000..8b2f18a22
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbq.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      unsigned long long ll[NUM];
+      unsigned char c[NUM * 8];
+    } dst, src;
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.c[(i % 2) + (i / 2) * 16] = i * i;
+      if ((i % 2))
+	src.c[(i % 2) + (i / 2) * 16] |= 0x80;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x [i / 2] = _mm_cvtepu8_epi64 (src.x [i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.c[(i % 2) + (i / 2) * 16] != dst.ll[i])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbw.c
new file mode 100644
index 000000000..8e1452bf7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbw.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 8];
+      unsigned short s[NUM];
+      unsigned char c[NUM * 2];
+    } dst, src;
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.c[(i % 8) + (i / 8) * 16] = i * i;
+      if ((i % 4))
+	src.c[(i % 8) + (i / 8) * 16] |= 0x80;
+    }
+
+  for (i = 0; i < NUM; i += 8)
+    dst.x [i / 8] = _mm_cvtepu8_epi16 (src.x [i / 8]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.c[(i % 8) + (i / 8) * 16] != dst.s[i])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxdq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxdq.c
new file mode 100644
index 000000000..cb2a4383e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxdq.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      unsigned long long ll[NUM];
+      unsigned int i[NUM * 2];
+    } dst, src;
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.i[(i % 2) + (i / 2) * 4] = i * i;
+      if ((i % 2))
+        src.i[(i % 2) + (i / 2) * 4] |= 0x80000000;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x [i / 2] = _mm_cvtepu32_epi64 (src.x [i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.i[(i % 2) + (i / 2) * 4] != dst.ll[i])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwd.c
new file mode 100644
index 000000000..b525f4c6a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwd.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      unsigned int i[NUM];
+      unsigned short s[NUM * 2];
+    } dst, src;
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.s[(i % 4) + (i / 4) * 8] = i * i;
+      if ((i % 4))
+	src.s[(i % 4) + (i / 4) * 8] |= 0x8000;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x [i / 4] = _mm_cvtepu16_epi32 (src.x [i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.s[(i % 4) + (i / 4) * 8] != dst.i[i])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwq.c
new file mode 100644
index 000000000..98f552aac
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwq.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      unsigned long long ll[NUM];
+      unsigned short s[NUM * 4];
+    } dst, src;
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.s[(i % 2) + (i / 2) * 8] = i * i;
+      if ((i % 2))
+	src.s[(i % 2) + (i / 2) * 8] |= 0x8000;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x [i / 2] = _mm_cvtepu16_epi64 (src.x [i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.s[(i % 2) + (i / 2) * 8] != dst.ll[i])
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmuldq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmuldq.c
new file mode 100644
index 000000000..dda1ba3c1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmuldq.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      long long ll[NUM];
+    } dst;
+  union
+    {
+      __m128i x[NUM / 2];
+      int i[NUM * 2];
+    } src1, src2;
+  int i, sign = 1;
+  long long value;
+
+  for (i = 0; i < NUM; i += 2)
+    {
+      src1.i[i] = i * i * sign;
+      src2.i[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x[i / 2] = _mm_mul_epi32 (src1.x[i / 2], src2.x[i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      value = (long long) src1.i[i * 2] * (long long) src2.i[i * 2];
+      if (value != dst.ll[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmulld.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmulld.c
new file mode 100644
index 000000000..9fb77d0ac
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-pmulld.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      int i[NUM];
+    } dst, src1, src2;
+  int i, sign = 1;
+  int value;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i * sign;
+      src2.i[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x[i / 4] = _mm_mullo_epi32 (src1.x[i / 4], src2.x[i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      value = src1.i[i] * src2.i[i];
+      if (value != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-ptest-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-ptest-1.c
new file mode 100644
index 000000000..8b57a2111
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-ptest-1.c
@@ -0,0 +1,117 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+static int
+make_ptestz (__m128i m, __m128i v)
+{
+  union
+    {
+      __m128i x;
+      unsigned char c[16];
+    } val, mask;
+  int i, z;
+
+  mask.x = m;
+  val.x = v;
+
+  z = 1;
+  for (i = 0; i < 16; i++)
+    if ((mask.c[i] & val.c[i]))
+      {
+	z = 0;
+	break;
+      }
+  return z;
+}
+
+static int
+make_ptestc (__m128i m, __m128i v)
+{
+  union
+    {
+      __m128i x;
+      unsigned char c[16];
+    } val, mask;
+  int i, c;
+
+  mask.x = m;
+  val.x = v;
+
+  c = 1;
+  for (i = 0; i < 16; i++)
+    if ((val.c[i] & ~mask.c[i]))
+      {
+	c = 0;
+	break;
+      }
+  return c;
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } val[4];
+  int i, j, l;
+  int res[32];
+
+  val[0].i[0] = 0x11111111;
+  val[0].i[1] = 0x00000000;
+  val[0].i[2] = 0x00000000;
+  val[0].i[3] = 0x11111111;
+    
+  val[1].i[0] = 0x00000000;
+  val[1].i[1] = 0x11111111;
+  val[1].i[2] = 0x11111111;
+  val[1].i[3] = 0x00000000;
+
+  val[2].i[0] = 0;
+  val[2].i[1] = 0;
+  val[2].i[2] = 0;
+  val[2].i[3] = 0;
+
+  val[3].i[0] = 0xffffffff;
+  val[3].i[1] = 0xffffffff;
+  val[3].i[2] = 0xffffffff;
+  val[3].i[3] = 0xffffffff;
+
+  l = 0;
+  for(i = 0; i < 4; i++)
+    for(j = 0; j < 4; j++)
+      {
+	res[l++] = _mm_testz_si128 (val[j].x, val[i].x);
+	res[l++] = _mm_testc_si128 (val[j].x, val[i].x);
+      }
+
+  l = 0;
+  for(i = 0; i < 4; i++)
+    for(j = 0; j < 4; j++)
+      {
+	if (res[l++] != make_ptestz (val[j].x, val[i].x))
+	  abort ();
+	if (res[l++] != make_ptestc (val[j].x, val[i].x))
+	  abort ();
+      }
+
+  if (res[2] != _mm_testz_si128 (val[1].x, val[0].x))
+    abort ();
+
+  if (res[3] != _mm_testc_si128 (val[1].x, val[0].x))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-ptest-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-ptest-2.c
new file mode 100644
index 000000000..2e6df9538
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-ptest-2.c
@@ -0,0 +1,96 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+static int
+make_ptestnzc (__m128i m, __m128i v)
+{
+  union
+    {
+      __m128i x;
+      unsigned char c[16];
+    } val, mask;
+  int i, z, c;
+
+  mask.x = m;
+  val.x = v;
+
+  z = c = 1;
+  for (i = 0; i < 16; i++)
+    {
+      if ((mask.c[i] & val.c[i]))
+	z = 0;
+      if ((~mask.c[i] & val.c[i]))
+	c = 0;
+    }
+
+  return (z == 0 && c == 0) ? 1 : 0;
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } val[4];
+  int i, j, l;
+  int res[32];
+
+  val[0].i[0] = 0x11111111;
+  val[0].i[1] = 0x00000000;
+  val[0].i[2] = 0x00000000;
+  val[0].i[3] = 0x11111111;
+    
+  val[1].i[0] = 0x00000000;
+  val[1].i[1] = 0x11111111;
+  val[1].i[2] = 0x11111111;
+  val[1].i[3] = 0x00000000;
+
+  val[2].i[0] = 0;
+  val[2].i[1] = 0;
+  val[2].i[2] = 0;
+  val[2].i[3] = 0;
+
+  val[3].i[0] = 0xffffffff;
+  val[3].i[1] = 0xffffffff;
+  val[3].i[2] = 0xffffffff;
+  val[3].i[3] = 0xffffffff;
+
+  l = 0;
+  for(i = 0; i < 4; i++)
+    for(j = 0; j < 4; j++)
+      {
+	res[l++] = _mm_testnzc_si128 (val[j].x, val[i].x);
+	res[l++] = _mm_testnzc_si128 (val[j].x, val[i].x);
+      }
+
+  l = 0;
+  for(i = 0; i < 4; i++)
+    for(j = 0; j < 4; j++)
+      {
+	if (res[l++] != make_ptestnzc (val[j].x, val[i].x))
+	  abort ();
+	if (res[l++] != make_ptestnzc (val[j].x, val[i].x))
+	  abort ();
+      }
+
+  if (res[2] != _mm_testnzc_si128 (val[1].x, val[0].x))
+    abort ();
+
+  if (res[3] != _mm_testnzc_si128 (val[1].x, val[0].x))
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-ptest-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-ptest-3.c
new file mode 100644
index 000000000..bf2df320e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-ptest-3.c
@@ -0,0 +1,85 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } val[4];
+  int correct_zeros[4];
+  int correct_ones[4];
+  int correct_mixed[4];
+  int zeros[4];
+  int ones[4];
+  int mixed[4];
+  int i;
+  __m128i v;
+
+  val[0].i[0] = 0x11111111;
+  val[0].i[1] = 0x00000000;
+  val[0].i[2] = 0x00000000;
+  val[0].i[3] = 0x11111111;
+  correct_zeros[0] = 0;
+  correct_ones[0] = 0;
+  correct_mixed[0] = 1;
+    
+  val[1].i[0] = 0x00000000;
+  val[1].i[1] = 0x11111111;
+  val[1].i[2] = 0x11111111;
+  val[1].i[3] = 0x00000000;
+  correct_zeros[1] = 0;
+  correct_ones[1] = 0;
+  correct_mixed[1] = 1;
+
+  val[2].i[0] = 0;
+  val[2].i[1] = 0;
+  val[2].i[2] = 0;
+  val[2].i[3] = 0;
+  correct_zeros[2] = 1;
+  correct_ones[2] = 0;
+  correct_mixed[2] = 0;
+
+  val[3].i[0] = 0xffffffff;
+  val[3].i[1] = 0xffffffff;
+  val[3].i[2] = 0xffffffff;
+  val[3].i[3] = 0xffffffff;
+  correct_zeros[3] = 0;
+  correct_ones[3] = 1;
+  correct_mixed[3] = 0;
+
+  for (i=0; i < 4; i++)
+    zeros[i] = _mm_test_all_zeros (val[i].x, val[i].x);
+
+  for( i=0; i < 4; i++ )
+    ones[i] = _mm_test_all_ones (val[i].x);
+
+  v = _mm_cmpeq_epi32 (val[0].x, val[0].x);
+  for( i=0; i < 4; i++ )
+    mixed[i] = _mm_test_mix_ones_zeros (val[i].x, v);
+
+  for( i=0; i < 4; i++ )
+    {
+      if (zeros[i] != correct_zeros[i])
+	abort ();
+      if (ones[i] != correct_ones[i])
+	abort ();
+      if (mixed[i] != correct_mixed[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-round.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-round.h
new file mode 100644
index 000000000..0210ac130
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-round.h
@@ -0,0 +1,95 @@
+#include <smmintrin.h>
+#include <math.h>
+
+#define NUM 64
+
+static void
+init_round (FP_T *src)
+{
+  int i, sign = 1;
+  FP_T f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1)* f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI *sign);
+      sign = -sign;
+    }
+}
+
+static FP_T
+do_round (FP_T f, int type)
+{
+  short saved_cw, new_cw, clr_mask;
+  FP_T ret;
+
+  if ((type & 4))
+    {
+      type = 0;
+      clr_mask = 0xFFFF;
+    }
+  else
+    {
+      type = 0x003F | ((type & 3) << 10);
+      clr_mask = ~0x0C3F;
+    }
+
+  __asm__ ("fld" ASM_SUFFIX " %0" : : "m" (*&f));
+
+  __asm__ ("fstcw %0" : "=m" (*&saved_cw));
+  new_cw = saved_cw & clr_mask;
+  new_cw |= type;
+  __asm__ ("fldcw %0" : : "m" (*&new_cw));
+
+  __asm__ ("frndint\n"
+	   "fstp" ASM_SUFFIX " %0\n" : "=m" (*&ret));
+  __asm__ ("fldcw %0" : : "m" (*&saved_cw));
+  return ret;
+}
+
+static void
+sse4_1_test (void)
+{
+  int i;
+  FP_T f;
+  union
+    {
+      VEC_T x[NUM / LOOP_INCREMENT];
+      FP_T f[NUM];
+    } dst, src;
+
+  init_round (src.f);
+
+  for (i = 0; i < NUM / LOOP_INCREMENT; i++)
+    dst.x[i] =  ROUND_INTRIN (src.x[i], ROUND_MODE);
+
+  for (i = 0; i < NUM; i += CHECK_LOOP_INCREMENT)
+    {
+      f = do_round (src.f[i], CHECK_ROUND_MODE);
+     if (f != dst.f[i])
+       abort ();
+    }
+
+  if (_MM_FROUND_TO_NEAREST_INT != 0x00
+      || _MM_FROUND_TO_NEG_INF != 0x01
+      || _MM_FROUND_TO_POS_INF != 0x02
+      || _MM_FROUND_TO_ZERO != 0x03
+      || _MM_FROUND_CUR_DIRECTION != 0x04
+      || _MM_FROUND_RAISE_EXC != 0x00
+      || _MM_FROUND_NO_EXC != 0x08
+      || _MM_FROUND_NINT != 0x00
+      || _MM_FROUND_FLOOR != 0x01
+      || _MM_FROUND_CEIL != 0x02
+      || _MM_FROUND_TRUNC != 0x03
+      || _MM_FROUND_RINT != 0x04
+      || _MM_FROUND_NEARBYINT != 0x0C)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-1.c
new file mode 100644
index 000000000..37f20285f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define iRoundMode 0x2
+
+static void
+TEST (void)
+{
+  union128d u, s;
+  double e[2] = {0.0};
+  int i;
+
+  s.x = _mm_set_pd (1.1234, -2.3478);
+  u.x = _mm_round_pd (s.x, iRoundMode);
+
+  for (i = 0; i < 2; i++)
+    {
+      __m128d tmp = _mm_load_sd (&s.a[i]);
+      tmp = _mm_round_sd (tmp, tmp, iRoundMode);
+      _mm_store_sd (&e[i], tmp);
+    }
+  
+  if (check_union128d (u, e))
+    abort ();
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-2.c
new file mode 100644
index 000000000..7f0475f75
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+static void
+TEST (void)
+{
+  union128d u, s;
+  double e[2] = {0.0};
+  int i;
+
+  s.x = _mm_set_pd (1.1234, -2.3478);
+  u.x = _mm_floor_pd (s.x);
+
+  for (i = 0; i < 2; i++)
+    {
+      __m128d tmp = _mm_load_sd (&s.a[i]);
+      tmp = _mm_floor_sd (tmp, tmp);
+      _mm_store_sd (&e[i], tmp);
+    }
+  
+  if (check_union128d (u, e))
+    abort ();
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-3.c
new file mode 100644
index 000000000..4a1f81026
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-3.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+static void
+TEST (void)
+{
+  union128d u, s;
+  double e[2] = {0.0};
+  int i;
+
+  s.x = _mm_set_pd (1.1234, -2.3478);
+  u.x = _mm_ceil_pd (s.x);
+
+  for (i = 0; i < 2; i++)
+    {
+      __m128d tmp = _mm_load_sd (&s.a[i]);
+      tmp = _mm_ceil_sd (tmp, tmp);
+      _mm_store_sd (&e[i], tmp);
+    }
+  
+  if (check_union128d (u, e))
+    abort ();
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundps-1.c
new file mode 100644
index 000000000..65b891c14
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundps-1.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128
+#define FP_T float
+#define ASM_SUFFIX "s"
+
+#define ROUND_INTRIN(x, mode) _mm_ceil_ps(x)
+#define ROUND_MODE _MM_FROUND_CEIL
+#define CHECK_ROUND_MODE 0x02
+
+#define LOOP_INCREMENT 4
+#define CHECK_LOOP_INCREMENT 1
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundps-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundps-2.c
new file mode 100644
index 000000000..44b778f31
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundps-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128
+#define FP_T float
+#define ASM_SUFFIX "s"
+
+#define ROUND_INTRIN _mm_round_ps
+#define ROUND_MODE _MM_FROUND_NINT
+#define CHECK_ROUND_MODE 0x00
+
+#define LOOP_INCREMENT 4
+#define CHECK_LOOP_INCREMENT 1
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundps-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundps-3.c
new file mode 100644
index 000000000..3f166b712
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundps-3.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128
+#define FP_T float
+#define ASM_SUFFIX "s"
+
+#define ROUND_INTRIN(x, mode) _mm_floor_ps(x)
+#define ROUND_MODE _MM_FROUND_FLOOR
+#define CHECK_ROUND_MODE 0x01
+
+#define LOOP_INCREMENT 4
+#define CHECK_LOOP_INCREMENT 1
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-1.c
new file mode 100644
index 000000000..33500d361
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128d
+#define FP_T double
+#define ASM_SUFFIX "l"
+
+#define ROUND_INTRIN(x, mode) _mm_ceil_sd(x, x)
+#define ROUND_MODE _MM_FROUND_CEIL
+#define CHECK_ROUND_MODE 0x02
+
+#define LOOP_INCREMENT 2
+#define CHECK_LOOP_INCREMENT 2
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-2.c
new file mode 100644
index 000000000..f6a51db61
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128d
+#define FP_T double
+#define ASM_SUFFIX "l"
+
+#define ROUND_INTRIN(x, mode) _mm_round_sd(x, x, mode)
+#define ROUND_MODE _MM_FROUND_NINT
+#define CHECK_ROUND_MODE 0x00
+
+#define LOOP_INCREMENT 2
+#define CHECK_LOOP_INCREMENT 2
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-3.c
new file mode 100644
index 000000000..1e4196443
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-3.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128d
+#define FP_T double
+#define ASM_SUFFIX "l"
+
+#define ROUND_INTRIN(x, mode) _mm_floor_sd(x, x)
+#define ROUND_MODE _MM_FROUND_FLOOR
+#define CHECK_ROUND_MODE 0x01
+
+#define LOOP_INCREMENT 2
+#define CHECK_LOOP_INCREMENT 2
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-4.c
new file mode 100644
index 000000000..dca97789f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-4.c
@@ -0,0 +1,91 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#include <smmintrin.h>
+#include <math.h>
+#include <string.h>
+
+#define NUM 64
+
+static void
+init_round (double *src)
+{
+  int i, sign = 1;
+  double d = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1)* d * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    d = d * src[i];
+        }
+      else if (i == (NUM / 2))
+	d = rand ();
+      else if ((i % 6) == 0)
+	d = 1 / (d * (i + 1) * src[i] * M_PI *sign);
+      sign = -sign;
+    }
+}
+
+static double
+do_round (double f, int type)
+{
+  short saved_cw, new_cw, clr_mask;
+  double ret;
+
+  if ((type & 4))
+    {
+      type = 0;
+      clr_mask = 0xFFFF;
+    }
+  else
+    {
+      type = 0x003F | ((type & 3) << 10);
+      clr_mask = ~0x0C3F;
+    }
+
+  __asm__ ("fldl %0" : : "m" (*&f));
+
+  __asm__ ("fstcw %0" : "=m" (*&saved_cw));
+  new_cw = saved_cw & clr_mask;
+  new_cw |= type;
+  __asm__ ("fldcw %0" : : "m" (*&new_cw));
+
+  __asm__ ("frndint\n"
+	   "fstpl %0\n" : "=m" (*&ret));
+  __asm__ ("fldcw %0" : : "m" (*&saved_cw));
+  return ret;
+}
+
+static void
+sse4_1_test (void)
+{
+  int i;
+  double f;
+  union
+    {
+      __m128d x[NUM / 2];
+      double d[NUM];
+    } dst, src;
+
+  init_round (src.d);
+  memset (&dst, 0, NUM * sizeof(double));
+
+  for (i = 0; i < NUM / 2 ; i++)
+    dst.x[i] =  _mm_round_sd (dst.x[i], src.x[i], _MM_FROUND_TRUNC);
+
+  for (i = 0; i < NUM; i += 2)
+    {
+      if (dst.d[i + 1] != 0.0)
+	abort ();
+
+      f = do_round (src.d[i], 0x03);
+      if (f != dst.d[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundss-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundss-1.c
new file mode 100644
index 000000000..d79657811
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundss-1.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128
+#define FP_T float
+#define ASM_SUFFIX "s"
+
+#define ROUND_INTRIN(x, mode) _mm_ceil_ss(x, x)
+#define ROUND_MODE _MM_FROUND_CEIL
+#define CHECK_ROUND_MODE 0x02
+
+#define LOOP_INCREMENT 4
+#define CHECK_LOOP_INCREMENT 4
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundss-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundss-2.c
new file mode 100644
index 000000000..019f21344
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundss-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128
+#define FP_T float
+#define ASM_SUFFIX "s"
+
+#define ROUND_INTRIN(x, mode) _mm_round_ss(x, x, mode)
+#define ROUND_MODE _MM_FROUND_NINT
+#define CHECK_ROUND_MODE 0x00
+
+#define LOOP_INCREMENT 4
+#define CHECK_LOOP_INCREMENT 4
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundss-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundss-3.c
new file mode 100644
index 000000000..2adac1a60
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundss-3.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128
+#define FP_T float
+#define ASM_SUFFIX "s"
+
+#define ROUND_INTRIN(x, mode) _mm_floor_ss(x, x)
+#define ROUND_MODE _MM_FROUND_FLOOR
+#define CHECK_ROUND_MODE 0x01
+
+#define LOOP_INCREMENT 4
+#define CHECK_LOOP_INCREMENT 4
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundss-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundss-4.c
new file mode 100644
index 000000000..dc7f34edb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-roundss-4.c
@@ -0,0 +1,106 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#include <smmintrin.h>
+#include <math.h>
+#include <string.h>
+
+#define NUM 64
+
+static void
+init_round (float *src)
+{
+  int i, sign = 1;
+  float f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1)* f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI *sign);
+      sign = -sign;
+    }
+}
+
+static float
+do_round (float f, int type)
+{
+  short saved_cw, new_cw, clr_mask;
+  float ret;
+
+  if ((type & 4))
+    {
+      type = 0;
+      clr_mask = 0xFFFF;
+    }
+  else
+    {
+      type = 0x003F | ((type & 3) << 10);
+      clr_mask = ~0x0C3F;
+    }
+
+  __asm__ ("flds %0" : : "m" (*&f));
+
+  __asm__ ("fstcw %0" : "=m" (*&saved_cw));
+  new_cw = saved_cw & clr_mask;
+  new_cw |= type;
+  __asm__ ("fldcw %0" : : "m" (*&new_cw));
+
+  __asm__ ("frndint\n"
+	   "fstps %0\n" : "=m" (*&ret));
+  __asm__ ("fldcw %0" : : "m" (*&saved_cw));
+  return ret;
+}
+
+static void
+sse4_1_test (void)
+{
+  int i, j;
+  float f;
+  union
+    {
+      __m128 x[NUM / 4];
+      float f[NUM];
+    } dst, src;
+
+  init_round (src.f);
+  memset (&dst, 0, NUM * sizeof(float));
+
+  for (i = 0; i < NUM / 4 ; i++)
+    dst.x[i] =  _mm_round_ss (dst.x[i], src.x[i], _MM_FROUND_RINT);
+
+  for (i = 0; i < NUM; i += 4)
+    {
+      for (j = 0; j < 3; j++)
+	if (dst.f[i + j + 1] != 0.0)
+	  abort ();
+
+      f = do_round (src.f[i], 0x04);
+      if (f != dst.f[i])
+	abort ();
+    }
+
+  for (i = 0; i < NUM / 4 ; i++)
+    dst.x[i] =  _mm_round_ss (dst.x[i], src.x[i], _MM_FROUND_NEARBYINT);
+
+  for (i = 0; i < NUM; i += 4)
+    {
+      for (j = 0; j < 3; j++)
+	if (dst.f[i + j + 1] != 0.0)
+	  abort ();
+
+      f = do_round (src.f[i], 0x0c);
+      if (f != dst.f[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-epi32-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-epi32-1.c
new file mode 100644
index 000000000..989e4f708
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-epi32-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+test (unsigned int *v)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } u;
+  unsigned int i;
+  
+  u.x = _mm_set_epi32 (v[3], v[2], v[1], v[0]);
+
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (v[i] != u.i[i])
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+sse4_1_test (void)
+{
+  unsigned int v[4]
+    = { 0x7B5B5465, 0x73745665, 0x63746F72, 0x5D53475D };
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-epi64x-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-epi64x-1.c
new file mode 100644
index 000000000..8679f5286
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-epi64x-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+test (unsigned long long *v)
+{
+  union
+    {
+      __m128i x;
+      unsigned long long i[2];
+    } u;
+  unsigned int i;
+  
+  u.x = _mm_set_epi64x (v[1], v[0]);
+
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (v[i] != u.i[i])
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%llx != 0x%llx\n", i, v[i], u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+sse4_1_test (void)
+{
+  unsigned long long v[2]
+    = { 0x7B5B546573745665LL, 0x63746F725D53475DLL };
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-ps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-ps-1.c
new file mode 100644
index 000000000..fe77d94ad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-ps-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <xmmintrin.h>
+
+static void
+__attribute__((noinline))
+test (float *v)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } u;
+  unsigned int i;
+  
+  u.x = _mm_set_ps (v[3], v[2], v[1], v[0]);
+
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (v[i] != u.f[i])
+      {
+#ifdef DEBUG
+	printf ("%i: %f != %f\n", i, v[i], u.f[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+sse4_1_test (void)
+{
+  float v[4] = { -3, 2, 1, 9 };
+  test (v);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1.c
new file mode 100644
index 000000000..23c090330
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "set-v16qi-1.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c
new file mode 100644
index 000000000..b8612962d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -mtune=core2 -msse4.1" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "set-v16qi-1.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2.c
new file mode 100644
index 000000000..524587082
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "set-v16qi-2.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c
new file mode 100644
index 000000000..21f1692cd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -mtune=core2 -msse4.1" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "set-v16qi-2.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3.c
new file mode 100644
index 000000000..99f563ab1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "set-v16qi-3.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c
new file mode 100644
index 000000000..1065a843a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -mtune=core2 -msse4.1" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "set-v16qi-3.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-check.h
new file mode 100644
index 000000000..2a397e886
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-check.h
@@ -0,0 +1,21 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void sse4_2_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run SSE4.2 test only if host has SSE4.2 support.  */
+  if (ecx & bit_SSE4_2)
+    sse4_2_test ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-crc32.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-crc32.h
new file mode 100644
index 000000000..c0bcd16cc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-crc32.h
@@ -0,0 +1,163 @@
+#include "sse4_2-check.h"
+
+#include <nmmintrin.h>
+#include <string.h>
+
+#define POLYNOMIAL 0x11EDC6F41LL
+
+#define MAX_BUF 16
+
+static void
+shift_mem_by1 (unsigned char* buf, int len)
+{
+  int i;
+
+  for (i = len - 1; i >= 0; i--)
+    {
+      buf[i] = buf[i] << 1;
+      if (i > 0 && (buf[i-1] & 0x80))
+	buf[i] |= 1;
+   }
+}
+
+static void
+do_div (unsigned char* buf, unsigned char* div) 
+{
+  int i;
+  for (i = 0; i < 5; i++)
+    buf[i] ^= div[i];
+}
+
+static unsigned int
+calc_rem (unsigned char* buf, int len)
+{
+  union
+    {
+      unsigned long long ll;
+      unsigned char c[8];
+    } divisor;
+  union
+    {
+      unsigned int i;
+      unsigned char c[4];
+    } ret;
+  unsigned char *div_buf;
+  unsigned char divident[MAX_BUF];
+  int disp = len / 8;
+  int i;
+
+  divisor.ll = POLYNOMIAL << 7LL;
+
+  memcpy (divident, buf, disp);
+
+  div_buf = divident + disp - 5;
+
+  for (i = 0; i < len - 32; i++)
+    {
+      if ((div_buf[4] & 0x80)) 
+	do_div (div_buf, divisor.c);
+      shift_mem_by1 (divident, disp);
+   }
+
+  memcpy (ret.c, div_buf + 1, sizeof (ret));
+  return ret.i;
+}
+
+static void 
+reverse_bits (unsigned char *src, int len)
+{
+  unsigned char buf[MAX_BUF];
+  unsigned char *tmp = buf + len - 1;
+  unsigned char ch;
+  int i, j;
+
+  for (i = 0; i < len; i++)
+    {
+      ch = 0;
+      for (j = 0; j < 8; j++)
+	if ((src[i] & (1 << j)))
+	  ch |= 1 << (7 - j);
+      *tmp-- = ch;
+    }
+
+  for (i = 0; i < len; i++)
+    src[i] = buf[i];
+}
+
+static void 
+shift_mem ( unsigned char *src, unsigned char *dst, int len, int shft)
+{
+  int disp = shft / 8;
+  int i;
+   
+  memset (dst, 0, len + disp);
+  for (i = 0; i < len; i++)
+    dst[i + disp] = src[i];
+}
+
+static void 
+xor_mem (unsigned char *src, unsigned char *dst, int len)
+{
+  int disp = len / 8;
+  int i;
+   
+  for (i = 0; i < disp; i++)
+    dst[i] ^= src[i];
+}
+
+static DST_T
+compute_crc32 (DST_T crc, SRC_T inp)
+{
+  unsigned char crcbuf[sizeof (DST_T)];
+  unsigned char inbuf[sizeof (SRC_T)];
+  unsigned char tmp1[MAX_BUF], tmp2[MAX_BUF];
+  int crc_sh, xor_sz;
+  union
+    {
+      unsigned int i;
+      unsigned char c[4];
+    } ret;
+
+  crc_sh = sizeof (SRC_T) * 8;
+  xor_sz = 32 + crc_sh;
+  memcpy (crcbuf, &crc, sizeof (DST_T));
+  memcpy (inbuf, &inp, sizeof (SRC_T));
+   
+  reverse_bits (crcbuf, 4);
+  reverse_bits (inbuf, sizeof (SRC_T));
+
+  shift_mem (inbuf, tmp1, sizeof (SRC_T), 32);
+  shift_mem (crcbuf, tmp2, 4, crc_sh);
+
+  xor_mem (tmp1, tmp2, xor_sz);
+
+  ret.i = calc_rem (tmp2, xor_sz);
+  
+  reverse_bits (ret.c, 4);
+
+  return (DST_T)ret.i;
+}
+
+#define NUM 1024
+
+static void
+sse4_2_test (void)
+{
+  DST_T dst[NUM]; 
+  SRC_T src[NUM];
+  int i;
+
+ for (i = 0; i < NUM; i++)
+   {
+     dst[i] = rand ();
+     if (sizeof (DST_T) > 4)
+       dst[i] |= (DST_T)rand () << (DST_T)(sizeof (DST_T) * 4);
+     src[i] = rand ();
+     if (sizeof (SRC_T) > 4)
+       src[i] |= (SRC_T)rand () << (SRC_T)(sizeof (DST_T) * 4);
+   }
+
+  for (i = 0; i < NUM; i++)
+    if (CRC32 (dst[i], src[i]) != compute_crc32 (dst[i], src[i]))
+      abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-crc32b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-crc32b.c
new file mode 100644
index 000000000..05a609cd1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-crc32b.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#define CRC32 _mm_crc32_u8
+#define DST_T unsigned int
+#define SRC_T unsigned char
+
+#include "sse4_2-crc32.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-crc32l.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-crc32l.c
new file mode 100644
index 000000000..00cdf6ad3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-crc32l.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#define CRC32 _mm_crc32_u32
+#define DST_T unsigned int
+#define SRC_T unsigned int
+
+#include "sse4_2-crc32.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-crc32q.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-crc32q.c
new file mode 100644
index 000000000..8209e9935
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-crc32q.c
@@ -0,0 +1,10 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#define CRC32 _mm_crc32_u64
+#define DST_T unsigned long long
+#define SRC_T unsigned long long
+
+#include "sse4_2-crc32.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-crc32w.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-crc32w.c
new file mode 100644
index 000000000..03991e553
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-crc32w.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#define CRC32 _mm_crc32_u16
+#define DST_T unsigned int
+#define SRC_T unsigned short
+
+#include "sse4_2-crc32.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-1.c
new file mode 100644
index 000000000..5b7f3ad77
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-1.c
@@ -0,0 +1,83 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+ (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+  | _SIDD_MOST_SIGNIFICANT)
+#define IMM_VAL2 \
+ (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_LEAST_SIGNIFICANT)
+
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  int res, correct, l1, l2;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      l1 = rand () % 18;
+      l2 = rand () % 18;
+
+      switch ((rand () % 4))
+	{
+	case 0:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL0,
+			    NULL);
+	  break;
+
+	case 1:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL1,
+			    NULL);
+	  break;
+
+	case 2:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL2,
+			    NULL);
+	  break;
+
+	default:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL3,
+			    NULL);
+	  break;
+        }
+
+      if (correct != res)
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-2.c
new file mode 100644
index 000000000..800084ff6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-2.c
@@ -0,0 +1,119 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+ (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+  | _SIDD_MOST_SIGNIFICANT)
+#define IMM_VAL2 \
+ (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_LEAST_SIGNIFICANT)
+
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  int res, correct, correct_flags, l1, l2;
+  int flags, cf, zf, sf, of, af;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      l1 = rand () % 18;
+      l2 = rand () % 18;
+
+      switch ((rand () % 4))
+	{
+	case 0:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL0,
+			    &correct_flags);
+	  break;
+
+	case 1:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL1,
+			    &correct_flags);
+	  break;
+
+	case 2:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL2,
+			    &correct_flags);
+	  break;
+
+	default:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL3,
+			    &correct_flags);
+	  break;
+	}
+      
+      if (correct != res)
+	abort ();
+
+      flags = 0;
+      if (cf)
+	flags |= CFLAG;
+      if (zf)
+	flags |= ZFLAG;
+      if (sf)
+	flags |= SFLAG;
+      if (of)
+	flags |= OFLAG;
+      
+      if (flags != correct_flags
+	  || (af && (cf || zf))
+	  || (!af && !(cf || zf)))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-1.c
new file mode 100644
index 000000000..f02bb7e69
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-1.c
@@ -0,0 +1,84 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+  (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+   | _SIDD_BIT_MASK)
+#define IMM_VAL2 \
+  (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_UNIT_MASK)
+
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  __m128i res, correct;
+  int l1, l2;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      l1 = rand () % 18;
+      l2 = rand () % 18;
+
+      switch((rand() % 4))
+	{
+	case 0:
+	  res  = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL0,
+			    NULL);
+	  break;
+
+	case 1:
+	  res  = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL1,
+			    NULL);
+	  break;
+
+	case 2:
+	  res  = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL2,
+			    NULL);
+	  break;
+
+	default:
+	  res  = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL3,
+			    NULL);
+	  break;
+        }
+
+      if (memcmp (&correct, &res, sizeof (res)))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-2.c
new file mode 100644
index 000000000..845471f0b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-2.c
@@ -0,0 +1,119 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+  (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+   | _SIDD_BIT_MASK)
+#define IMM_VAL2 \
+  (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_UNIT_MASK)
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  __m128i res, correct;
+  int correct_flags, l1, l2;
+  int flags, cf, zf, sf, of, af;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      l1 = rand () % 18;
+      l2 = rand () % 18;
+
+      switch ((rand () % 4))
+	{
+	case 0:
+	  res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL0,
+			    &correct_flags);
+	  break;
+
+	case 1:
+	  res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL1,
+			    &correct_flags);
+	  break;
+
+	case 2:
+	  res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL2,
+			    &correct_flags);
+	  break;
+
+	default:	
+	  res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL3,
+			    &correct_flags);
+	  break;
+	}
+      
+      if (memcmp (&correct, &res, sizeof (res)))
+	abort ();
+
+      flags = 0;
+      if (cf)
+	flags |= CFLAG;
+      if (zf)
+	flags |= ZFLAG;
+      if (sf)
+	flags |= SFLAG;
+      if (of)
+	flags |= OFLAG;
+      
+      if (flags != correct_flags
+	  || (af && (cf || zf))
+	  || (!af && !(cf || zf)))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpgtq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpgtq.c
new file mode 100644
index 000000000..e2ef66f2a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpgtq.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include <nmmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      long long ll[NUM];
+    } dst, src1, src2;
+  int i, sign = 1;
+  long long is_eq;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.ll[i] = i * i * sign;
+      src2.ll[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x[i / 2] = _mm_cmpgt_epi64 (src1.x[i / 2], src2.x[i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      is_eq = src1.ll[i] > src2.ll[i] ? 0xFFFFFFFFFFFFFFFFLL : 0LL;
+      if (is_eq != dst.ll[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-1.c
new file mode 100644
index 000000000..b74df024d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-1.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+ (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+  | _SIDD_MOST_SIGNIFICANT)
+#define IMM_VAL2 \
+ (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_MOST_SIGNIFICANT)
+
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  int res, correct;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      switch ((rand () % 4))
+	{
+	case 0:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL0);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL0, NULL);
+	  break;
+
+	case 1:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL1);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL1, NULL);
+	  break;
+
+	case 2:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL2);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL2, NULL);
+	  break;
+
+	default:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL3);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL3, NULL);
+	  break;
+        }
+
+      if (correct != res)
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-2.c
new file mode 100644
index 000000000..5aea655ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-2.c
@@ -0,0 +1,116 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+ (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+  | _SIDD_MOST_SIGNIFICANT)
+#define IMM_VAL2 \
+ (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_MOST_SIGNIFICANT)
+
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  int res, correct, correct_flags;
+  int flags, cf, zf, sf, of, af;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      switch ((rand () % 4))
+	{
+	case 0:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL0);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL0);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL0);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL0);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL0);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL0);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL0,
+			    &correct_flags);
+	  break;
+
+	case 1:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL1);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL1);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL1);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL1);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL1);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL1);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL1,
+			    &correct_flags);
+	  break;
+
+	case 2:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL2);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL2);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL2);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL2);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL2);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL2);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL2,
+			    &correct_flags);
+	  break;
+
+	default:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL3);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL3);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL3);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL3);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL3);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL3);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL3,
+			    &correct_flags);
+	  break;
+	}
+      
+      if (correct != res)
+	abort ();
+
+      flags = 0;
+      if (cf)
+	flags |= CFLAG;
+      if (zf)
+	flags |= ZFLAG;
+      if (sf)
+	flags |= SFLAG;
+      if (of)
+	flags |= OFLAG;
+      
+      if (flags != correct_flags
+	  || (af && (cf || zf))
+	  || (!af && !(cf || zf)))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-1.c
new file mode 100644
index 000000000..b8ec890cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-1.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+  (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+   | _SIDD_BIT_MASK)
+#define IMM_VAL2 \
+  (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_UNIT_MASK)
+
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  __m128i res, correct;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      switch((rand() % 4))
+	{
+	case 0:
+	  res  = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL0);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL0, NULL);
+	  break;
+
+	case 1:
+	  res  = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL1);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL1, NULL);
+	  break;
+
+	case 2:
+	  res  = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL2);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL2, NULL);
+	  break;
+
+	default:
+	  res  = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL3);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL3, NULL);
+	  break;
+        }
+
+      if (memcmp (&correct, &res, sizeof (res)))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-2.c
new file mode 100644
index 000000000..c6896ee61
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-2.c
@@ -0,0 +1,116 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+  (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+   | _SIDD_BIT_MASK)
+#define IMM_VAL2 \
+  (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_POSITIVE_POLARITY | _SIDD_UNIT_MASK)
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  __m128i res, correct;
+  int correct_flags;
+  int flags, cf, zf, sf, of, af;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      switch ((rand () % 4))
+	{
+	case 0:
+	  res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL0);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL0);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL0);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL0);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL0);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL0);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL0,
+			    &correct_flags);
+	  break;
+
+	case 1:
+	  res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL1);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL1);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL1);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL1);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL1);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL1);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL1,
+			    &correct_flags);
+	  break;
+
+	case 2:
+	  res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL2);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL2);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL2);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL2);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL2);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL2);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL2,
+			    &correct_flags);
+	  break;
+
+	default:	
+	  res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL3);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL3);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL3);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL3);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL3);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL3);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL3,
+			    &correct_flags);
+	  break;
+	}
+      
+      if (memcmp (&correct, &res, sizeof (res)))
+	abort ();
+
+      flags = 0;
+      if (cf)
+	flags |= CFLAG;
+      if (zf)
+	flags |= ZFLAG;
+      if (sf)
+	flags |= SFLAG;
+      if (of)
+	flags |= OFLAG;
+      
+      if (flags != correct_flags
+	  || (af && (cf || zf))
+	  || (!af && !(cf || zf)))
+	abort ();
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpstr.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpstr.h
new file mode 100644
index 000000000..999b5c8ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-pcmpstr.h
@@ -0,0 +1,447 @@
+#include <nmmintrin.h>
+#include <string.h>
+
+#define CFLAG 0x00000001
+#define ZFLAG 0x00000002
+#define SFLAG 0x00000004
+#define OFLAG 0x00000008
+#define AFLAG 0x00000010
+#define PFLAG 0x00000020
+
+#define PCMPSTR_EQ(X, Y, RES) \
+  {							\
+    int __size = (sizeof (*X) ^ 3) * 8;			\
+    int __i, __j;					\
+    for (__i = 0; __i < __size; __i++)			\
+      for (__j = 0; __j < __size; __j++)		\
+        RES[__j][__i] = (X[__i] == Y[__j]);		\
+  }
+
+#define PCMPSTR_RNG(X, Y, RES) \
+  {							\
+    int __size = (sizeof (*X) ^ 3) * 8;			\
+    int __i, __j;					\
+    for (__j = 0; __j < __size; __j++)			\
+      for (__i = 0; __i < __size - 1; __i += 2)		\
+	{						\
+	  RES[__j][__i] = (Y[__j] >= X[__i]);		\
+	  RES[__j][__i+1] = (Y[__j] <= X[__i + 1]);	\
+	}						\
+  }
+
+static void
+override_invalid (unsigned char res[16][16], int la, int lb,
+		  const int mode, int dim)
+{
+  int i, j;
+
+  for (j = 0; j < dim; j++)
+    for (i = 0; i < dim; i++)
+      if (i < la && j >= lb)
+	res[j][i] = 0;
+      else if (i >= la)
+	switch ((mode & 0x0C))
+	  {
+	  case _SIDD_CMP_EQUAL_ANY:
+	  case _SIDD_CMP_RANGES:
+	    res[j][i] = 0;
+	    break;
+	  case _SIDD_CMP_EQUAL_EACH:
+	    res[j][i] = (j >= lb) ? 1: 0;
+	    break;
+	  case _SIDD_CMP_EQUAL_ORDERED:
+	    res[j][i] = 1;
+	    break;
+          }
+}
+
+static void  
+calc_matrix (__m128i a, int la, __m128i b, int lb, const int mode,
+	     unsigned char res[16][16])
+{
+  union
+    {
+      __m128i x;
+      signed char sc[16];
+      unsigned char uc[16];
+      signed short ss[8];
+      unsigned short us[8];
+    } d, s;
+
+  d.x = a;
+  s.x = b;
+
+  switch ((mode & 3))
+    {
+    case _SIDD_UBYTE_OPS:
+      if ((mode & 0x0C) == _SIDD_CMP_RANGES)
+	{
+	  PCMPSTR_RNG (d.uc, s.uc, res);
+	}
+      else
+	{
+	  PCMPSTR_EQ (d.uc, s.uc, res);
+	}
+      break;
+    case _SIDD_UWORD_OPS:
+      if ((mode & 0x0C) == _SIDD_CMP_RANGES)
+	{
+	  PCMPSTR_RNG (d.us, s.us, res);
+	}
+      else
+	{
+	  PCMPSTR_EQ (d.us, s.us, res);
+	}
+      break;
+    case _SIDD_SBYTE_OPS:
+      if ((mode & 0x0C) == _SIDD_CMP_RANGES)
+	{
+	  PCMPSTR_RNG (d.sc, s.sc, res);
+	}
+      else
+	{
+	  PCMPSTR_EQ (d.sc, s.sc, res);
+	}
+      break;
+    case _SIDD_SWORD_OPS:
+      if ((mode & 0x0C) == _SIDD_CMP_RANGES)
+	{
+	  PCMPSTR_RNG (d.ss, s.ss, res);
+	}
+      else
+	{
+	  PCMPSTR_EQ (d.ss, s.ss, res);
+	}
+      break;
+    }
+
+  override_invalid (res, la, lb, mode, (mode & 1) == 0 ? 16 : 8);
+}
+
+static int 
+calc_res (__m128i a, int la, __m128i b, int lb, const int mode)
+{
+  unsigned char mtx[16][16];
+  int i, j, k, dim, res = 0;
+
+  memset (mtx, 0, sizeof (mtx));
+
+  dim = (mode & 1) == 0 ? 16 : 8;
+
+  if (la < 0)
+    la = -la;
+
+  if (lb < 0)
+    lb = -lb;
+
+  if (la > dim)
+    la = dim;
+ 
+  if (lb > dim)
+    lb = dim;
+
+  calc_matrix (a, la, b, lb, mode, mtx);
+
+  switch ((mode & 0x0C))
+    {
+    case _SIDD_CMP_EQUAL_ANY:
+      for (i = 0; i < dim; i++)
+	for (j = 0; j < dim; j++)
+	  if (mtx[i][j])
+	    res |= (1 << i);
+      break;
+
+     case _SIDD_CMP_RANGES:
+      for (i = 0; i < dim; i += 2)
+	for(j = 0; j < dim; j++)
+	  if (mtx[j][i] && mtx[j][i+1])
+	    res |= (1 << j);
+      break;
+
+     case _SIDD_CMP_EQUAL_EACH:
+      for(i = 0; i < dim; i++)
+	if (mtx[i][i])
+	  res |= (1 << i);
+      break;
+
+     case _SIDD_CMP_EQUAL_ORDERED:
+      for(i = 0; i < dim; i++)
+	{
+	  unsigned char val = 1;
+
+	  for (j = 0, k = i; j < dim - i && k < dim; j++, k++)
+	    val &= mtx[k][j];
+	  
+	  if (val)
+	    res |= (1 << i);
+	  else
+	    res &= ~(1 << i);
+	}
+      break;
+    }
+
+  switch ((mode & 0x30))
+    {
+    case _SIDD_POSITIVE_POLARITY:
+    case _SIDD_MASKED_POSITIVE_POLARITY:
+      break;
+
+    case _SIDD_NEGATIVE_POLARITY:
+      res ^= -1;
+      break;
+
+    case _SIDD_MASKED_NEGATIVE_POLARITY:
+      for (i = 0; i < lb; i++)
+	if (res & (1 << i))
+	  res &= ~(1 << i);
+	else
+	  res |= (1 << i);
+      break;
+    }
+
+  return res & ((dim == 8) ? 0xFF : 0xFFFF);
+}
+
+static int
+cmp_flags (__m128i a, int la, __m128i b, int lb,
+	   int mode, int res2, int is_implicit)
+{
+  int i;
+  int flags = 0;
+  int is_bytes_mode = (mode & 1) == 0;
+  union
+    {
+      __m128i x;
+      unsigned char uc[16];
+      unsigned short us[8];
+    } d, s;
+
+  d.x = a;
+  s.x = b;
+
+  /* CF: reset if (RES2 == 0), set otherwise.  */
+  if (res2 != 0)
+    flags |= CFLAG;
+
+  if (is_implicit)
+    {
+      /* ZF: set if any byte/word of src xmm operand is null, reset
+	 otherwise.
+	 SF: set if any byte/word of dst xmm operand is null, reset
+	 otherwise.  */
+
+      if (is_bytes_mode)
+	{
+	  for (i = 0; i < 16; i++)
+	    {
+	      if (s.uc[i] == 0)
+		flags |= ZFLAG;
+	      if (d.uc[i] == 0)
+		flags |= SFLAG;
+            }
+	}
+      else
+	{
+	  for (i = 0; i < 8; i++)
+	    {
+	      if (s.us[i] == 0)
+		flags |= ZFLAG;
+	      if (d.us[i] == 0)
+		flags |= SFLAG;
+            }
+        }
+    }
+  else
+    {
+      /* ZF: set if abs value of EDX/RDX < 16 (8), reset otherwise.
+	 SF: set if abs value of EAX/RAX < 16 (8), reset otherwise.  */
+      int max_ind = is_bytes_mode ? 16 : 8;
+
+      if (la < 0)
+	la = -la;
+      if (lb < 0)
+	lb = -lb;
+
+      if (lb < max_ind)
+	flags |= ZFLAG;
+      if (la < max_ind)
+	flags |= SFLAG;
+    }
+
+  /* OF: equal to RES2[0].  */
+  if ((res2 & 0x1))
+    flags |= OFLAG;
+
+  /* AF: Reset.
+     PF: Reset.  */
+  return flags;
+}
+
+static int
+cmp_indexed (__m128i a, int la, __m128i b, int lb,
+	     const int mode, int *res2)
+{
+  int i, ndx;
+  int dim = (mode & 1) == 0 ? 16 : 8;
+  int r2;
+  
+  r2 = calc_res (a, la, b, lb, mode);
+
+  ndx = dim;
+  if ((mode & 0x40))
+    {
+      for (i = dim - 1; i >= 0; i--)
+	if (r2 & (1 << i))
+	  {
+	    ndx = i;
+	    break;
+	  }
+    }
+  else
+    {
+      for (i = 0; i < dim; i++)
+	if ((r2 & (1 << i)))
+	  {
+	    ndx = i;
+	    break;
+	  }
+    }
+
+   *res2 = r2;
+   return ndx;
+}
+
+static __m128i 
+cmp_masked (__m128i a, int la, __m128i b, int lb,
+	    const int mode, int *res2)
+{
+  union
+    {
+      __m128i x;
+      char c[16];
+      short s[8];
+    } ret;
+  int i;
+  int dim = (mode & 1) == 0 ? 16 : 8;
+  union
+    {
+      int i;
+      char c[4];
+      short s[2];
+    } r2;
+
+  r2.i = calc_res (a, la, b, lb, mode);
+
+  memset (&ret, 0, sizeof (ret));
+
+  if (mode & 0x40)
+    {
+      for (i = 0; i < dim; i++)
+	if (dim == 8)
+	  ret.s [i] = (r2.i & (1 << i)) ? -1 : 0;
+	else
+	  ret.c [i] = (r2.i & (1 << i)) ? -1 : 0;
+    }
+  else
+    {
+      if (dim == 16)
+	ret.s[0] = r2.s[0];
+      else
+	ret.c[0] = r2.c[0];
+    }
+
+   *res2 = r2.i;
+
+   return ret.x;
+}
+
+static int 
+calc_str_len (__m128i a, const int mode)
+{
+  union
+    {
+      __m128i x;
+      char c[16];
+      short s[8];
+    } s;
+  int i;
+  int dim  = (mode & 1) == 0 ? 16 : 8;
+
+  s.x = a;
+
+  if ((mode & 1))
+    {
+      for (i = 0; i < dim; i++)
+	if (s.s[i] == 0)
+	  break;
+    }
+  else
+    {
+      for (i = 0; i < dim; i++)
+       if (s.c[i] == 0)
+	 break;
+    }
+
+  return i;
+}
+
+static inline int
+cmp_ei (__m128i *a, int la, __m128i *b, int lb,
+	const int mode, int *flags)
+{
+  int res2;
+  int index = cmp_indexed (*a, la, *b, lb, mode, &res2);
+
+  if (flags != NULL)
+    *flags = cmp_flags (*a, la, *b, lb, mode, res2, 0);
+
+  return index;
+}
+
+static inline int
+cmp_ii (__m128i *a, __m128i *b, const int mode, int *flags)
+{
+  int la, lb;
+  int res2;
+  int index;
+
+  la = calc_str_len (*a, mode);
+  lb = calc_str_len (*b, mode);
+
+  index = cmp_indexed (*a, la, *b, lb, mode, &res2);
+
+  if (flags != NULL) 
+    *flags = cmp_flags (*a, la, *b, lb, mode, res2, 1);
+
+  return index;
+}
+
+static inline __m128i
+cmp_em (__m128i *a, int la, __m128i *b, int lb,
+	const int mode, int *flags )
+{
+  int res2;
+  __m128i mask = cmp_masked (*a, la, *b, lb, mode, &res2);
+
+  if (flags != NULL)
+    *flags = cmp_flags (*a, la, *b, lb, mode, res2, 0);
+
+  return mask;
+}
+
+static inline __m128i
+cmp_im (__m128i *a, __m128i *b, const int mode, int *flags)
+{
+  int la, lb;
+  int res2;
+  __m128i mask;
+
+  la = calc_str_len (*a, mode);
+  lb = calc_str_len (*b, mode);
+
+  mask = cmp_masked (*a, la, *b, lb, mode, &res2);
+  if (flags != NULL)
+    *flags = cmp_flags (*a, la, *b, lb, mode, res2, 1);
+
+  return mask;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-popcnt.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-popcnt.h
new file mode 100644
index 000000000..ce06ba1b8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-popcnt.h
@@ -0,0 +1,41 @@
+#include "sse4_2-check.h"
+
+#include <nmmintrin.h>
+
+#define NUM 1024
+
+static int
+compute_popcnt (TYPE v)
+{
+  int ret;
+  int i;
+
+ ret = 0;
+ for (i = 0; i < sizeof(v) * 8; i++)
+   if ((v & ((TYPE)1 << (TYPE) i)))
+     ret++;
+
+ return ret;
+}
+
+static void
+sse4_2_test (void)
+{
+  int i;
+  TYPE vals[NUM];
+  TYPE res;
+
+ for (i = 0; i < NUM; i++)
+   {
+     vals[i] = rand ();
+     if (sizeof (TYPE) > 4)
+       vals[i] |= (TYPE)rand() << (TYPE)(sizeof (TYPE) * 4);
+   }
+
+ for (i=0; i < NUM; i++)
+   { 
+     res = POPCNT (vals[i]);
+     if (res != compute_popcnt (vals[i]))
+       abort ();
+   }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-popcntl.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-popcntl.c
new file mode 100644
index 000000000..30da548d9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-popcntl.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#define TYPE unsigned int
+#define POPCNT _mm_popcnt_u32
+
+#include "sse4_2-popcnt.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-popcntq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-popcntq.c
new file mode 100644
index 000000000..aa4d8a917
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4_2-popcntq.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#define TYPE unsigned long long
+#define POPCNT _mm_popcnt_u64
+
+#include "sse4_2-popcnt.h"
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4a-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4a-check.h
new file mode 100644
index 000000000..d6140e896
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4a-check.h
@@ -0,0 +1,21 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void sse4a_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run SSE4a test only if host has SSE4a support.  */
+  if (ecx & bit_SSE4a)
+    sse4a_test ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4a-extract.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4a-extract.c
new file mode 100644
index 000000000..5fb190e44
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4a-extract.c
@@ -0,0 +1,84 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4a } */
+/* { dg-options "-O2 -msse4a" } */
+
+#include "sse4a-check.h"
+
+#include <ammintrin.h>
+
+typedef union
+{
+  long long i[2];
+  __m128i vec;
+} LI;
+
+static long long 
+sse4a_test_extrq (long long in)
+{
+  __m128i v1, v2;
+  long long index_length, pad;
+  LI v_out;
+  index_length = 0x0000000000000810LL; 
+  pad = 0x0;
+  v1 = _mm_set_epi64x (pad, in);
+  v2 = _mm_set_epi64x (pad, index_length); 
+  v_out.vec = _mm_extract_si64 (v1, v2);
+  return (v_out.i[0]); 
+}
+
+static long long 
+sse4a_test_extrqi (long long in)
+{
+  __m128i v1;
+  long long pad =0x0;
+  LI v_out;
+  v1 = _mm_set_epi64x (pad, in);
+  v_out.vec = _mm_extracti_si64 (v1, (unsigned int) 0x10,(unsigned int) 0x08);
+  return (v_out.i[0]);
+}
+
+static chk (long long i1, long long i2)
+{
+  int n_fails =0;
+  if (i1 != i2) 
+    n_fails +=1;
+  return n_fails;
+}
+
+long long vals_in[5] =
+  {
+    0x1234567887654321LL,
+    0x1456782093002490LL,
+    0x2340909123990390LL,
+    0x9595959599595999LL,
+    0x9099038798000029LL
+  };
+
+long long vals_out[5] =
+  {
+    0x0000000000006543LL,
+    0x0000000000000024LL,
+    0x0000000000009903LL,
+    0x0000000000005959LL,
+    0x0000000000000000LL
+  };
+
+static void
+sse4a_test (void)
+{
+  int i;
+  int fail = 0;
+  long long out;
+
+  for (i = 0; i < 5; i += 1)
+    {
+      out = sse4a_test_extrq (vals_in[i]);
+      fail += chk(out, vals_out[i]);
+
+      out = sse4a_test_extrqi (vals_in[i]);
+      fail += chk(out, vals_out[i]);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4a-insert.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4a-insert.c
new file mode 100644
index 000000000..c1bd1006d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4a-insert.c
@@ -0,0 +1,94 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4a } */
+/* { dg-options "-O2 -msse4a" } */
+
+#include "sse4a-check.h"
+
+#include <ammintrin.h>
+
+typedef union
+{
+  long long i[2];
+  __m128i vec;
+} LI;
+
+static long long
+sse4a_test_insert (long long in1, long long in2)
+{
+  __m128i v1,v2;
+  long long index_length, pad;
+  LI v_out;
+  index_length = 0x0000000000000810LL;
+  pad = 0x0;
+  v1 = _mm_set_epi64x (pad, in1);
+  v2 = _mm_set_epi64x (index_length, in2); 
+  v_out.vec = _mm_insert_si64 (v1, v2);
+  return (v_out.i[0]);
+}
+
+static long long
+sse4a_test_inserti (long long in1, long long in2)
+{
+  __m128i v1,v2;
+  long long pad = 0x0;
+  LI v_out;
+  v1 = _mm_set_epi64x (pad, in1);
+  v2 = _mm_set_epi64x (pad, in2); 
+  v_out.vec = _mm_inserti_si64 (v1, v2, (unsigned int) 0x10, (unsigned int) 0x08);
+  return (v_out.i[0]);  
+}
+
+static chk (long long i1, long long i2)
+{
+  int n_fails =0;
+  if (i1 != i2) 
+    n_fails +=1;
+  return n_fails;
+}
+
+long long vals_in1[5] =
+  {
+    0x1234567887654321LL,
+    0x1456782093002490LL,
+    0x2340909123990390LL,
+    0x9595959599595999LL,
+    0x9099038798000029LL
+  };
+
+long long vals_in2[5] =
+  {
+    0x9ABCDEF00FEDCBA9LL,
+    0x234567097289672ALL,
+    0x45476453097BD342LL,
+    0x23569012AE586FF0LL,
+    0x432567ABCDEF765DLL
+  };
+
+long long vals_out[5] =
+  {
+    0x1234567887CBA921LL,
+    0x1456782093672A90LL,
+    0x2340909123D34290LL,
+    0x95959595996FF099LL,
+    0x9099038798765D29LL
+  };
+
+static void
+sse4a_test (void)
+{
+  int i;
+  int fail = 0;
+  long long out;
+
+  for (i = 0; i < 5; i += 1)
+    {
+      out = sse4a_test_insert (vals_in1[i], vals_in2[i]);
+      fail += chk(out, vals_out[i]);
+
+      out = sse4a_test_inserti (vals_in1[i], vals_in2[i]);
+      fail += chk(out, vals_out[i]);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4a-montsd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4a-montsd.c
new file mode 100644
index 000000000..1cc067db6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4a-montsd.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4a } */
+/* { dg-options "-O2 -msse4a" } */
+
+#include "sse4a-check.h"
+
+#include <ammintrin.h>
+
+static void 
+sse4a_test_movntsd (double *out, double *in)
+{
+  __m128d in_v2df = _mm_load_sd (in);
+  _mm_stream_sd (out, in_v2df);
+}
+
+static int 
+chk_sd (double *v1, double *v2)
+{
+  int n_fails = 0;
+  if (v1[0] != v2[0])
+    n_fails += 1;
+  return n_fails;
+}
+
+double vals[10] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, 
+    -1.0, .345, -21.5, 9.32,  8.41
+  };
+
+static void
+sse4a_test (void)
+{
+  int i;
+  int fail = 0;
+  double *out;
+
+  out = (double *) malloc (sizeof (double));
+  for (i = 0; i < 10; i += 1)
+    {
+      sse4a_test_movntsd (out, &vals[i]);
+      
+      fail += chk_sd (out, &vals[i]);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4a-montss.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4a-montss.c
new file mode 100644
index 000000000..41e80e83d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse4a-montss.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4a } */
+/* { dg-options "-O2 -msse4a" } */
+
+#include "sse4a-check.h"
+
+#include <ammintrin.h>
+
+static void 
+sse4a_test_movntss (float *out, float *in)
+{
+  __m128 in_v4sf = _mm_load_ss (in);
+  _mm_stream_ss (out, in_v4sf);
+}
+
+static int 
+chk_ss (float *v1, float *v2)
+{
+  int n_fails = 0;
+  if (v1[0] != v2[0])
+    n_fails += 1;
+  return n_fails;
+}
+
+float vals[10] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, 
+    -1.0, .345, -21.5, 9.32,  8.41
+  };
+
+static void
+sse4a_test (void)
+{
+  int i;
+  int fail = 0;
+  float *out;
+
+  out = (float *) malloc (sizeof (float));
+  for (i = 0; i < 10; i += 1)
+    {
+      sse4a_test_movntss (out, &vals[i]);
+      
+      fail += chk_ss (out, &vals[i]);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-check.h
new file mode 100644
index 000000000..e133ed884
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-check.h
@@ -0,0 +1,20 @@
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void sse5_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run SSE5 test only if host has SSE5 support.  */
+  if (ecx & bit_SSE5)
+    sse5_test ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-fma-vector.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-fma-vector.c
new file mode 100644
index 000000000..ec6388f5a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-fma-vector.c
@@ -0,0 +1,93 @@
+/* Test that the compiler properly optimizes floating point multiply and add
+   instructions vector into fmaddps on SSE5 systems.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse5 -mfused-madd -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef float     __m128  __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef double    __m128d __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128 f_align;
+  __m128d d_align;
+  float f[SIZE];
+  double d[SIZE];
+} a, b, c, d;
+
+void
+flt_mul_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.f[i] = (b.f[i] * c.f[i]) + d.f[i];
+}
+
+void
+dbl_mul_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.d[i] = (b.d[i] * c.d[i]) + d.d[i];
+}
+
+void
+flt_mul_sub (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.f[i] = (b.f[i] * c.f[i]) - d.f[i];
+}
+
+void
+dbl_mul_sub (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.d[i] = (b.d[i] * c.d[i]) - d.d[i];
+}
+
+void
+flt_neg_mul_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.f[i] = (-(b.f[i] * c.f[i])) + d.f[i];
+}
+
+void
+dbl_neg_mul_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.d[i] = (-(b.d[i] * c.d[i])) + d.d[i];
+}
+
+int main ()
+{
+  flt_mul_add ();
+  flt_mul_sub ();
+  flt_neg_mul_add ();
+
+  dbl_mul_add ();
+  dbl_mul_sub ();
+  dbl_neg_mul_add ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "fmaddps" } } */
+/* { dg-final { scan-assembler "fmaddpd" } } */
+/* { dg-final { scan-assembler "fmsubps" } } */
+/* { dg-final { scan-assembler "fmsubpd" } } */
+/* { dg-final { scan-assembler "fnmaddps" } } */
+/* { dg-final { scan-assembler "fnmaddpd" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-fma.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-fma.c
new file mode 100644
index 000000000..d30e3166e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-fma.c
@@ -0,0 +1,82 @@
+/* Test that the compiler properly optimizes floating point multiply and add
+   instructions into fmaddss, fmsubss, fnmaddss, fnmsubss on SSE5 systems.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse5 -mfused-madd" } */
+
+extern void exit (int);
+
+float
+flt_mul_add (float a, float b, float c)
+{
+  return (a * b) + c;
+}
+
+double
+dbl_mul_add (double a, double b, double c)
+{
+  return (a * b) + c;
+}
+
+float
+flt_mul_sub (float a, float b, float c)
+{
+  return (a * b) - c;
+}
+
+double
+dbl_mul_sub (double a, double b, double c)
+{
+  return (a * b) - c;
+}
+
+float
+flt_neg_mul_add (float a, float b, float c)
+{
+  return (-(a * b)) + c;
+}
+
+double
+dbl_neg_mul_add (double a, double b, double c)
+{
+  return (-(a * b)) + c;
+}
+
+float
+flt_neg_mul_sub (float a, float b, float c)
+{
+  return (-(a * b)) - c;
+}
+
+double
+dbl_neg_mul_sub (double a, double b, double c)
+{
+  return (-(a * b)) - c;
+}
+
+float  f[10] = { 2, 3, 4 };
+double d[10] = { 2, 3, 4 };
+
+int main ()
+{
+  f[3] = flt_mul_add (f[0], f[1], f[2]);
+  f[4] = flt_mul_sub (f[0], f[1], f[2]);
+  f[5] = flt_neg_mul_add (f[0], f[1], f[2]);
+  f[6] = flt_neg_mul_sub (f[0], f[1], f[2]);
+
+  d[3] = dbl_mul_add (d[0], d[1], d[2]);
+  d[4] = dbl_mul_sub (d[0], d[1], d[2]);
+  d[5] = dbl_neg_mul_add (d[0], d[1], d[2]);
+  d[6] = dbl_neg_mul_sub (d[0], d[1], d[2]);
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "fmaddss" } } */
+/* { dg-final { scan-assembler "fmaddsd" } } */
+/* { dg-final { scan-assembler "fmsubss" } } */
+/* { dg-final { scan-assembler "fmsubsd" } } */
+/* { dg-final { scan-assembler "fnmaddss" } } */
+/* { dg-final { scan-assembler "fnmaddsd" } } */
+/* { dg-final { scan-assembler "fnmsubss" } } */
+/* { dg-final { scan-assembler "fnmsubsd" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-haddX.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-haddX.c
new file mode 100644
index 000000000..ff1f7fcc7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-haddX.c
@@ -0,0 +1,208 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse5 } */
+/* { dg-options "-O2 -msse5" } */
+
+#include "sse5-check.h"
+
+#include <bmmintrin.h>
+#include <string.h>
+
+#define NUM 10
+
+union
+{
+  __m128i x[NUM];
+  signed char ssi[NUM * 16];
+  short si[NUM * 8];
+  int li[NUM * 4];
+  long long lli[NUM * 2];
+} dst, res, src1;
+
+static void
+init_sbyte ()
+{
+  int i;
+  for (i=0; i < NUM * 16; i++)
+    src1.ssi[i] = i;
+}
+
+static void
+init_sword ()
+{
+  int i;
+  for (i=0; i < NUM * 8; i++)
+    src1.si[i] = i;
+}
+
+
+static void
+init_sdword ()
+{
+  int i;
+  for (i=0; i < NUM * 4; i++)
+    src1.li[i] = i;
+}
+
+static int 
+check_sbyte2word ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 16; i = i + 16)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.si[s] = src1.ssi[t] + src1.ssi[t + 1] ;
+	  if (res.si[s] != dst.si[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static int 
+check_sbyte2dword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 16; i = i + 16)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  t = i + (4 * j);
+	  s = (i / 4) + j;
+	  res.li[s] = (src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2]
+	              + src1.ssi[t + 3]); 
+	  if (res.li[s] != dst.li[s]) 
+	    check_fails++;
+	}
+    }
+  return check_fails++;
+}
+
+static int
+check_sbyte2qword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 16; i = i + 16)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  t = i + (8 * j);
+	  s = (i / 8) + j;
+	  res.lli[s] = ((src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2] 
+		       + src1.ssi[t + 3])) + ((src1.ssi[t + 4] + src1.ssi[t +5])
+	               + (src1.ssi[t + 6] + src1.ssi[t + 7])); 
+	  if (res.lli[s] != dst.lli[s]) 
+	    check_fails++;
+	}
+    }
+  return check_fails++;
+}
+
+static int
+check_sword2dword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < (NUM * 8); i = i + 8)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.li[s] = src1.si[t] + src1.si[t + 1] ;
+	  if (res.li[s] != dst.li[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static int 
+check_sword2qword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 8; i = i + 8)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  t = i + (4 * j);
+	  s = (i / 4) + j;
+	  res.lli[s] = (src1.si[t] + src1.si[t + 1]) + (src1.si[t + 2]
+	               + src1.si[t + 3]); 
+	  if (res.lli[s] != dst.lli[s]) 
+	    check_fails++;
+	}
+    }
+  return check_fails++;
+}
+
+static int
+check_dword2qword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < (NUM * 4); i = i + 4)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.lli[s] = src1.li[t] + src1.li[t + 1] ;
+	  if (res.lli[s] != dst.lli[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static void
+sse5_test (void)
+{
+  int i;
+  
+  /* Check haddbw */
+  init_sbyte ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddw_epi8 (src1.x[i]);
+  
+  if (check_sbyte2word())
+  abort ();
+  
+  /* Check haddbd */
+  for (i = 0; i < (NUM ); i++)
+    dst.x[i] = _mm_haddd_epi8 (src1.x[i]);
+  
+  if (check_sbyte2dword())
+    abort (); 
+  
+  /* Check haddbq */
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddq_epi8 (src1.x[i]);
+  
+  if (check_sbyte2qword())
+    abort ();
+
+  /* Check haddwd */
+  init_sword ();
+
+  for (i = 0; i < (NUM ); i++)
+    dst.x[i] = _mm_haddd_epi16 (src1.x[i]);
+  
+  if (check_sword2dword())
+    abort (); 
+   
+  /* Check haddbwq */
+ 
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddq_epi16 (src1.x[i]);
+  
+  if (check_sword2qword())
+    abort ();
+ 
+  /* Check haddq */
+  init_sdword ();
+
+    for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddq_epi32 (src1.x[i]);
+  
+  if (check_dword2qword())
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-hadduX.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-hadduX.c
new file mode 100644
index 000000000..f2697443e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-hadduX.c
@@ -0,0 +1,207 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse5 } */
+/* { dg-options "-O2 -msse5" } */
+
+#include "sse5-check.h"
+
+#include <bmmintrin.h>
+#include <string.h>
+
+#define NUM 10
+
+union
+{
+  __m128i x[NUM];
+  unsigned char  ssi[NUM * 16];
+  unsigned short si[NUM * 8];
+  unsigned int li[NUM * 4];
+  unsigned long long  lli[NUM * 2];
+} dst, res, src1;
+
+static void
+init_byte ()
+{
+  int i;
+  for (i=0; i < NUM * 16; i++)
+    src1.ssi[i] = i;
+}
+
+static void
+init_word ()
+{
+  int i;
+  for (i=0; i < NUM * 8; i++)
+    src1.si[i] = i;
+}
+
+
+static void
+init_dword ()
+{
+  int i;
+  for (i=0; i < NUM * 4; i++)
+    src1.li[i] = i;
+}
+
+static int 
+check_byte2word ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 16; i = i + 16)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.si[s] = src1.ssi[t] + src1.ssi[t + 1] ;
+	  if (res.si[s] != dst.si[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static int 
+check_byte2dword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 16; i = i + 16)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  t = i + (4 * j);
+	  s = (i / 4) + j;
+	  res.li[s] = (src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2]
+	              + src1.ssi[t + 3]); 
+	  if (res.li[s] != dst.li[s]) 
+	    check_fails++;
+	}
+    }
+  return check_fails++;
+}
+
+static int
+check_byte2qword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 16; i = i + 16)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  t = i + (8 * j);
+	  s = (i / 8) + j;
+	  res.lli[s] = ((src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2] 
+		       + src1.ssi[t + 3])) + ((src1.ssi[t + 4] + src1.ssi[t +5])
+	               + (src1.ssi[t + 6] + src1.ssi[t + 7])); 
+	  if (res.lli[s] != dst.lli[s]) 
+	    check_fails++;
+	}
+    }
+  return check_fails++;
+}
+
+static int
+check_word2dword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < (NUM * 8); i = i + 8)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.li[s] = src1.si[t] + src1.si[t + 1] ;
+	  if (res.li[s] != dst.li[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static int 
+check_word2qword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 8; i = i + 8)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  t = i + (4 * j);
+	  s = (i / 4) + j;
+	  res.lli[s] = (src1.si[t] + src1.si[t + 1]) + (src1.si[t + 2]
+	               + src1.si[t + 3]); 
+	  if (res.lli[s] != dst.lli[s]) 
+	    check_fails++;
+	}
+    }
+  return check_fails++;
+}
+
+static int
+check_dword2qword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < (NUM * 4); i = i + 4)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.lli[s] = src1.li[t] + src1.li[t + 1] ;
+	  if (res.lli[s] != dst.lli[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static void
+sse5_test (void)
+{
+  int i;
+  
+  /* Check haddubw */
+  init_byte ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddw_epu8 (src1.x[i]);
+  
+  if (check_byte2word())
+  abort ();
+  
+  /* Check haddubd */
+  for (i = 0; i < (NUM ); i++)
+    dst.x[i] = _mm_haddd_epu8 (src1.x[i]);
+  
+  if (check_byte2dword())
+    abort (); 
+  
+  /* Check haddubq */
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddq_epu8 (src1.x[i]);
+  
+  if (check_byte2qword())
+    abort ();
+
+  /* Check hadduwd */
+  init_word ();
+
+  for (i = 0; i < (NUM ); i++)
+    dst.x[i] = _mm_haddd_epu16 (src1.x[i]);
+  
+  if (check_word2dword())
+    abort (); 
+   
+  /* Check haddbuwq */
+ 
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddq_epu16 (src1.x[i]);
+  
+  if (check_word2qword())
+    abort ();
+ 
+  /* Check hadudq */
+  init_dword ();
+    for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddq_epu32 (src1.x[i]);
+  
+  if (check_dword2qword())
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-hsubX.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-hsubX.c
new file mode 100644
index 000000000..4e2979e9c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-hsubX.c
@@ -0,0 +1,128 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse5 } */
+/* { dg-options "-O2 -msse5" } */
+
+#include "sse5-check.h"
+
+#include <bmmintrin.h>
+#include <string.h>
+
+#define NUM 10
+
+union
+{
+  __m128i x[NUM];
+  signed char ssi[NUM * 16];
+  short si[NUM * 8];
+  int li[NUM * 4];
+  long long lli[NUM * 2];
+} dst, res, src1;
+
+static void
+init_sbyte ()
+{
+  int i;
+  for (i=0; i < NUM * 16; i++)
+    src1.ssi[i] = i;
+}
+
+static void
+init_sword ()
+{
+  int i;
+  for (i=0; i < NUM * 8; i++)
+    src1.si[i] = i;
+}
+
+
+static void
+init_sdword ()
+{
+  int i;
+  for (i=0; i < NUM * 4; i++)
+    src1.li[i] = i;
+}
+
+static int 
+check_sbyte2word ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 16; i = i + 16)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.si[s] = src1.ssi[t] - src1.ssi[t + 1] ;
+	  if (res.si[s] != dst.si[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static int
+check_sword2dword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < (NUM * 8); i = i + 8)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.li[s] = src1.si[t] - src1.si[t + 1] ;
+	  if (res.li[s] != dst.li[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static int
+check_dword2qword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < (NUM * 4); i = i + 4)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.lli[s] = src1.li[t] - src1.li[t + 1] ;
+	  if (res.lli[s] != dst.lli[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static void
+sse5_test (void)
+{
+  int i;
+  
+  /* Check hsubbw */
+  init_sbyte ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_hsubw_epi8 (src1.x[i]);
+  
+  if (check_sbyte2word())
+  abort ();
+  
+
+  /* Check hsubwd */
+  init_sword ();
+
+  for (i = 0; i < (NUM ); i++)
+    dst.x[i] = _mm_hsubd_epi16 (src1.x[i]);
+  
+  if (check_sword2dword())
+    abort (); 
+   
+   /* Check hsubdq */
+  init_sdword ();
+    for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_hsubq_epi32 (src1.x[i]);
+  
+  if (check_dword2qword())
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-ima-vector.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-ima-vector.c
new file mode 100644
index 000000000..f32b0a13d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-ima-vector.c
@@ -0,0 +1,34 @@
+/* Test that the compiler properly optimizes vector 32-bit integer point
+   multiply and add instructions vector into pmacsdd on SSE5 systems.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i align;
+  int i[SIZE];
+} a, b, c, d;
+
+void
+int_mul_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.i[i] = (b.i[i] * c.i[i]) + d.i[i];
+}
+
+int main ()
+{
+  int_mul_add ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "pmacsdd" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-imul32widen-vector.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-imul32widen-vector.c
new file mode 100644
index 000000000..ef29d0814
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-imul32widen-vector.c
@@ -0,0 +1,36 @@
+/* Test that the compiler properly optimizes floating point multiply and add
+   instructions vector into pmacsdd/etc. on SSE5 systems.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  int i32[SIZE];
+  long i64[SIZE];
+} a, b, c, d;
+
+void
+imul32_to_64 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.i64[i] = ((long)b.i32[i]) * ((long)c.i32[i]);
+}
+
+int main ()
+{
+  imul32_to_64 ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "pmacsdql" } } */
+/* { dg-final { scan-assembler "pmacsdqh" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-imul64-vector.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-imul64-vector.c
new file mode 100644
index 000000000..06ad1d2e9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-imul64-vector.c
@@ -0,0 +1,36 @@
+/* Test that the compiler properly optimizes floating point multiply and add
+   instructions vector into pmacsdd/etc. on SSE5 systems.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  long i64[SIZE];
+} a, b, c, d;
+
+void
+imul64 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.i64[i] = b.i64[i] * c.i64[i];
+}
+
+int main ()
+{
+  imul64 ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "pmacsdd" } } */
+/* { dg-final { scan-assembler "phadddq" } } */
+/* { dg-final { scan-assembler "pmacsdql" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-maccXX.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-maccXX.c
new file mode 100644
index 000000000..c7bc5fe5f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-maccXX.c
@@ -0,0 +1,140 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse5 } */
+/* { dg-options "-O2 -msse5" } */
+
+#include "sse5-check.h"
+
+#include <bmmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+union
+{
+  __m128 x[NUM];
+  float f[NUM * 4];
+  __m128d y[NUM];
+  double d[NUM * 2];
+} dst, res, src1, src2, src3;
+
+
+/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate 
+   product is not rounded, only the addition is rounded. */
+
+static void
+init_maccps ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.f[i] = i;
+      src2.f[i] = i + 10;
+      src3.f[i] = i + 20;
+    }
+}
+
+static void
+init_maccpd ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.d[i] = i;
+      src2.d[i] = i + 10;
+      src3.d[i] = i + 20;
+    }
+}
+
+static int
+check_maccps ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    for (j = 0; j < 4; j++)
+      {
+	res.f[i + j] = (src1.f[i + j] * src2.f[i + j]) + src3.f[i + j];
+	if (dst.f[i + j] != res.f[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static int
+check_maccpd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    for (j = 0; j < 2; j++)
+      {
+	res.d[i + j] = (src1.d[i + j] * src2.d[i + j]) + src3.d[i + j];
+	if (dst.d[i + j] != res.d[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+
+static int
+check_maccss ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i= i + 4)
+    {
+      res.f[i] = (src1.f[i] * src2.f[i]) + src3.f[i];
+      if (dst.f[i] != res.f[i]) 
+	check_fails++;
+    }	
+  return check_fails++;
+}
+
+static int
+check_maccsd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    {
+      res.d[i] = (src1.d[i] * src2.d[i]) + src3.d[i];
+      if (dst.d[i] != res.d[i]) 
+	check_fails++;
+    }
+  return check_fails++;
+}
+
+static void
+sse5_test (void)
+{
+  int i;
+  
+  /* Check maccps */
+  init_maccps ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_macc_ps (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_maccps ()) 
+    abort ();
+  
+  /* check maccss */
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_macc_ss (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_maccss ()) 
+    abort ();
+  
+  /* Check maccpd */
+  init_maccpd ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_macc_pd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_maccpd ()) 
+    abort ();
+  
+  /* Check maccps */
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_macc_sd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_maccsd ()) 
+    abort ();
+  
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-msubXX.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-msubXX.c
new file mode 100644
index 000000000..22c34c7fd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-msubXX.c
@@ -0,0 +1,139 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse5 } */
+/* { dg-options "-O2 -msse5" } */
+
+#include "sse5-check.h"
+
+#include <bmmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+union
+{
+  __m128 x[NUM];
+  float f[NUM * 4];
+  __m128d y[NUM];
+  double d[NUM * 2];
+} dst, res, src1, src2, src3;
+
+/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate 
+   product is not rounded, only the addition is rounded. */
+
+static void
+init_msubps ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.f[i] = i;
+      src2.f[i] = i + 10;
+      src3.f[i] = i + 20;
+    }
+}
+
+static void
+init_msubpd ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.d[i] = i;
+      src2.d[i] = i + 10;
+      src3.d[i] = i + 20;
+    }
+}
+
+static int
+check_msubps ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    for (j = 0; j < 4; j++)
+      {
+	res.f[i + j] = (src1.f[i + j] * src2.f[i + j]) - src3.f[i + j];
+	if (dst.f[i + j] != res.f[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static int
+check_msubpd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    for (j = 0; j < 2; j++)
+      {
+	res.d[i + j] = (src1.d[i + j] * src2.d[i + j]) - src3.d[i + j];
+	if (dst.d[i + j] != res.d[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+
+static int
+check_msubss ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    {
+      res.f[i] = (src1.f[i] * src2.f[i]) - src3.f[i];
+      if (dst.f[i] != res.f[i]) 
+	check_fails++;
+    }	
+  return check_fails++;
+}
+
+static int
+check_msubsd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    {
+      res.d[i] = (src1.d[i] * src2.d[i]) - src3.d[i];
+      if (dst.d[i] != res.d[i]) 
+	check_fails++;
+    }
+  return check_fails++;
+}
+
+static void
+sse5_test (void)
+{
+  int i;
+  
+  /* Check msubps */
+  init_msubps ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_msub_ps (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_msubps ()) 
+    abort ();
+  
+  /* check msubss */
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_msub_ss (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_msubss ()) 
+    abort ();
+  
+  /* Check msubpd */
+  init_msubpd ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_msub_pd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_msubpd ()) 
+    abort ();
+  
+  /* Check msubps */
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_msub_sd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_msubsd ()) 
+    abort ();
+  
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-nmaccXX.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-nmaccXX.c
new file mode 100644
index 000000000..061497736
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-nmaccXX.c
@@ -0,0 +1,139 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse5 } */
+/* { dg-options "-O2 -msse5" } */
+
+#include "sse5-check.h"
+
+#include <bmmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+union
+{
+  __m128 x[NUM];
+  float f[NUM * 4];
+  __m128d y[NUM];
+  double d[NUM * 2];
+} dst, res, src1, src2, src3;
+
+/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate 
+   product is not rounded, only the addition is rounded. */
+
+static void
+init_nmaccps ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.f[i] = i;
+      src2.f[i] = i + 10;
+      src3.f[i] = i + 20;
+    }
+}
+
+static void
+init_nmaccpd ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.d[i] = i;
+      src2.d[i] = i + 10;
+      src3.d[i] = i + 20;
+    }
+}
+
+static int
+check_nmaccps ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    for (j = 0; j < 4; j++)
+      {
+	res.f[i + j] = - (src1.f[i + j] * src2.f[i + j]) + src3.f[i + j];
+	if (dst.f[i + j] != res.f[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static int
+check_nmaccpd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    for (j = 0; j < 2; j++)
+      {
+	res.d[i + j] = - (src1.d[i + j] * src2.d[i + j]) + src3.d[i + j];
+	if (dst.d[i + j] != res.d[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+
+static int
+check_nmaccss ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    {
+      res.f[i] = - (src1.f[i] * src2.f[i]) + src3.f[i];
+      if (dst.f[i] != res.f[i]) 
+	check_fails++;
+    }	
+  return check_fails++;
+}
+
+static int
+check_nmaccsd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    {
+      res.d[i] = - (src1.d[i] * src2.d[i]) + src3.d[i];
+      if (dst.d[i] != res.d[i]) 
+	check_fails++;
+    }
+  return check_fails++;
+}
+
+static void
+sse5_test (void)
+{
+  int i;
+  
+  /* Check nmaccps */
+  init_nmaccps ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_nmacc_ps (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_nmaccps ()) 
+    abort ();
+  
+  /* check nmaccss */
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_nmacc_ss (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_nmaccss ()) 
+    abort ();
+  
+  /* Check nmaccpd */
+  init_nmaccpd ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_nmacc_pd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_nmaccpd ()) 
+    abort ();
+  
+  /* Check nmaccps */
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_nmacc_sd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_nmaccsd ()) 
+    abort ();
+  
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-nmsubXX.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-nmsubXX.c
new file mode 100644
index 000000000..b22684c6a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-nmsubXX.c
@@ -0,0 +1,139 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse5 } */
+/* { dg-options "-O2 -msse5" } */
+
+#include "sse5-check.h"
+
+#include <bmmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+union
+{
+  __m128 x[NUM];
+  float f[NUM * 4];
+  __m128d y[NUM];
+  double d[NUM * 2];
+} dst, res, src1, src2, src3;
+
+/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate 
+   product is not rounded, only the addition is rounded. */
+
+static void
+init_nmsubps ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.f[i] = i;
+      src2.f[i] = i + 10;
+      src3.f[i] = i + 20;
+    }
+}
+
+static void
+init_nmsubpd ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.d[i] = i;
+      src2.d[i] = i + 10;
+      src3.d[i] = i + 20;
+    }
+}
+
+static int
+check_nmsubps ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    for (j = 0; j < 4; j++)
+      {
+	res.f[i + j] = - (src1.f[i + j] * src2.f[i + j]) - src3.f[i + j];
+	if (dst.f[i + j] != res.f[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static int
+check_nmsubpd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    for (j = 0; j < 2; j++)
+      {
+	res.d[i + j] = - (src1.d[i + j] * src2.d[i + j]) - src3.d[i + j];
+	if (dst.d[i + j] != res.d[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+
+static int
+check_nmsubss ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    {
+      res.f[i] = - (src1.f[i] * src2.f[i]) - src3.f[i];
+      if (dst.f[i] != res.f[i]) 
+	check_fails++;
+    }	
+  return check_fails++;
+}
+
+static int
+check_nmsubsd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    {
+      res.d[i] = - (src1.d[i] * src2.d[i]) - src3.d[i];
+      if (dst.d[i] != res.d[i]) 
+	check_fails++;
+    }
+  return check_fails++;
+}
+
+static void
+sse5_test (void)
+{
+  int i;
+  
+  /* Check nmsubps */
+  init_nmsubps ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_nmsub_ps (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_nmsubps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4], &src3.f[i * 4])) 
+    abort ();
+  
+  /* check nmsubss */
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_nmsub_ss (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_nmsubss (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4], &src3.f[i * 4])) 
+    abort ();
+  
+  /* Check nmsubpd */
+  init_nmsubpd ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_nmsub_pd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_nmsubpd (&dst.y[i], &src1.d[i * 2], &src2.d[i * 2], &src3.d[i * 2])) 
+    abort ();
+  
+  /* Check nmsubps */
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_nmsub_sd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_nmsubsd (&dst.y[i], &src1.d[i * 2], &src2.d[i * 2], &src3.d[i * 2])) 
+    abort ();
+  
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-pcmov.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-pcmov.c
new file mode 100644
index 000000000..f83b06b33
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-pcmov.c
@@ -0,0 +1,23 @@
+/* Test that the compiler properly optimizes conditional floating point moves
+   into the pcmov instruction on SSE5 systems.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse5" } */
+
+extern void exit (int);
+
+double dbl_test (double a, double b, double c, double d)
+{
+  return (a > b) ? c : d;
+}
+
+double dbl_a = 1, dbl_b = 2, dbl_c = 3, dbl_d = 4, dbl_e;
+
+int main()
+{
+  dbl_e = dbl_test (dbl_a, dbl_b, dbl_c, dbl_d);
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "pcmov" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-pcmov2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-pcmov2.c
new file mode 100644
index 000000000..6b174d666
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-pcmov2.c
@@ -0,0 +1,23 @@
+/* Test that the compiler properly optimizes conditional floating point moves
+   into the pcmov instruction on SSE5 systems.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse5" } */
+
+extern void exit (int);
+
+float flt_test (float a, float b, float c, float d)
+{
+  return (a > b) ? c : d;
+}
+
+float flt_a = 1, flt_b = 2, flt_c = 3, flt_d = 4, flt_e;
+
+int main()
+{
+  flt_e = flt_test (flt_a, flt_b, flt_c, flt_d);
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "pcmov" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-permpX.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-permpX.c
new file mode 100644
index 000000000..cae307725
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-permpX.c
@@ -0,0 +1,120 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse5 } */
+/* { dg-options "-O2 -msse5" } */
+
+#include "sse5-check.h"
+
+#include <bmmintrin.h>
+#include <string.h>
+
+union
+{
+  __m128 x[2];
+  __m128d y[2];
+  __m128i z[2];
+  float f[8];
+  double d[4];
+  int i[8];
+  long li[4];
+} dst, res, src1, src2, src3;
+
+
+static void
+init_ddata ()
+{
+  int i;
+  for (i = 0; i < 4; i++)
+    {
+      src1.d[i] = i;
+      src2.d[i] = i + 2;
+    }
+ 
+  src3.li[0] = 3;
+  src3.li[1] = 0;
+  src3.li[2] = 1;
+  src3.li[3] = 2;
+
+  res.d[0] = 3.0;
+  res.d[1] = 0.0;
+  res.d[2] = 3.0;
+  res.d[3] = 4.0;
+}
+
+
+static void 
+init_fdata ()
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    {
+      src1.f[i] = i;
+      src2.f[i] = i + 2;
+    }
+
+  src3.i[0] = 7;
+  src3.i[1] = 5;
+  src3.i[2] = 1;
+  src3.i[3] = 2;
+  src3.i[4] = 0;
+  src3.i[5] = 4;
+  src3.i[6] = 3;
+  src3.i[7] = 6; 
+
+  res.f[0] = 5.0;
+  res.f[1] = 3.0;
+  res.f[2] = 1.0;
+  res.f[3] = 2.0;
+  res.f[4] = 4.0;
+  res.f[5] = 6.0;
+  res.f[6] = 7.0;
+  res.f[7] = 8.0;
+}
+
+static int
+check_permpd ()
+{
+  int i, check_fails = 0;
+
+  for (i = 0; i < 4; i++)
+    {
+      if (res.d[i] != dst.d[i])
+	check_fails++;
+    }
+  return check_fails++;
+}
+
+static int
+check_permps ()
+{
+  int i, check_fails = 0;
+
+  for (i = 0; i < 8; i++)
+    {
+      if (res.f[i] != dst.f[i])
+	check_fails++;
+    }
+  return check_fails++;
+}
+
+static void
+sse5_test (void)
+{
+  int i;
+  init_ddata();
+
+  for (i = 0; i < 2; i++)
+    dst.y[i] = _mm_perm_pd (src1.y[i], src2.y[i], src3.z[i]);
+  
+  if (check_permpd ())
+    abort ();
+  
+  init_fdata();
+  
+  for (i = 0; i < 2; i++)
+    dst.x[i] = _mm_perm_ps (src1.x[i], src2.x[i], src3.z[i]);
+   
+  if (check_permps ())
+    abort (); 
+}
+
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-rotate1-vector.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-rotate1-vector.c
new file mode 100644
index 000000000..0db9b9f79
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-rotate1-vector.c
@@ -0,0 +1,35 @@
+/* Test that the compiler properly optimizes vector rotate instructions vector
+   into prot on SSE5 systems.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  unsigned u32[SIZE];
+} a, b, c;
+
+void
+left_rotate32 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.u32[i] = (b.u32[i] << ((sizeof (int) * 8) - 4)) | (b.u32[i] >> 4);
+}
+
+int
+main ()
+{
+  left_rotate32 ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "protd" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-rotate2-vector.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-rotate2-vector.c
new file mode 100644
index 000000000..4ea762a20
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-rotate2-vector.c
@@ -0,0 +1,35 @@
+/* Test that the compiler properly optimizes vector rotate instructions vector
+   into prot on SSE5 systems.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  unsigned u32[SIZE];
+} a, b, c;
+
+void
+right_rotate32_b (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.u32[i] = (b.u32[i] >> ((sizeof (int) * 8) - 4)) | (b.u32[i] << 4);
+}
+
+int
+main ()
+{
+  right_rotate ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "prot" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-rotate3-vector.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-rotate3-vector.c
new file mode 100644
index 000000000..de7272439
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-rotate3-vector.c
@@ -0,0 +1,34 @@
+/* Test that the compiler properly optimizes vector rotate instructions vector
+   into prot on SSE5 systems.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  unsigned u32[SIZE];
+} a, b, c;
+
+void
+vector_rotate32 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.u32[i] = (b.u32[i] >> ((sizeof (int) * 8) - c.u32[i])) | (b.u32[i] << c.u32[i]);
+}
+
+int main ()
+{
+  vector_rotate32 ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "protd" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-shift1-vector.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-shift1-vector.c
new file mode 100644
index 000000000..c1ce02326
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-shift1-vector.c
@@ -0,0 +1,35 @@
+/* Test that the compiler properly optimizes vector shift instructions into
+   psha/pshl on SSE5 systems.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  int i32[SIZE];
+  unsigned u32[SIZE];
+} a, b, c;
+
+void
+left_shift32 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.i32[i] = b.i32[i] << c.i32[i];
+}
+
+int main ()
+{
+  left_shfit32 ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "pshad" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-shift2-vector.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-shift2-vector.c
new file mode 100644
index 000000000..c0d97bc3d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-shift2-vector.c
@@ -0,0 +1,35 @@
+/* Test that the compiler properly optimizes vector shift instructions into
+   psha/pshl on SSE5 systems.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  int i32[SIZE];
+  unsigned u32[SIZE];
+} a, b, c;
+
+void
+right_sign_shift32 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.i32[i] = b.i32[i] >> c.i32[i];
+}
+
+int main ()
+{
+  right_sign_shfit32 ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "pshad" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-shift3-vector.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-shift3-vector.c
new file mode 100644
index 000000000..0027457e3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sse5-shift3-vector.c
@@ -0,0 +1,35 @@
+/* Test that the compiler properly optimizes vector shift instructions into
+   psha/pshl on SSE5 systems.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  int i32[SIZE];
+  unsigned u32[SIZE];
+} a, b, c;
+
+void
+right_uns_shift32 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.u32[i] = b.u32[i] >> c.i32[i];
+}
+
+int main ()
+{
+  right_uns_shfit32 ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "pshld" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefn-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefn-1.c
new file mode 100644
index 000000000..0279a5533
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefn-1.c
@@ -0,0 +1,30 @@
+/* Test argument passing with SSE and local functions
+   Written by Paolo Bonzini, 25 January 2005 */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-final { scan-assembler "movss" } } */
+/* { dg-final { scan-assembler "mulss" } } */
+/* { dg-final { scan-assembler-not "movsd" } } */
+/* { dg-final { scan-assembler-not "mulsd" } } */
+/* { dg-options "-O2 -march=i386 -msse -mfpmath=sse -fno-inline" } */
+
+static float xs (void)
+{
+  return 3.14159265;
+}
+
+float ys (float a)
+{
+  return xs () * a;
+}
+
+static double xd (void)
+{
+  return 3.1415926535;
+}
+
+double yd (double a)
+{
+  return xd () * a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefn-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefn-2.c
new file mode 100644
index 000000000..09b920ea7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefn-2.c
@@ -0,0 +1,31 @@
+/* Test argument passing with SSE2 and local functions
+   Written by Paolo Bonzini, 25 January 2005 */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-final { scan-assembler "movss" } } */
+/* { dg-final { scan-assembler "mulss" } } */
+/* { dg-final { scan-assembler "movsd" } } */
+/* { dg-final { scan-assembler "mulsd" } } */
+/* { dg-options "-O2 -msse2 -mfpmath=sse -fno-inline" } */
+
+static float xs (void)
+{
+  return 3.14159265;
+}
+
+float ys (float a)
+{
+  return xs () * a;
+}
+
+static double xd (void)
+{
+  return 3.1415926535;
+}
+
+double yd (double a)
+{
+  return xd () * a;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefn-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefn-3.c
new file mode 100644
index 000000000..adf72cce1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefn-3.c
@@ -0,0 +1,38 @@
+/* Execution test for argument passing with SSE and local functions
+   Written by Paolo Bonzini, 25 January 2005 */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -msse -mfpmath=sse" } */
+
+#include "sse-check.h"
+
+#include <assert.h>
+
+static float xs (void)
+{
+  return 3.14159265;
+}
+
+float ys (float a)
+{
+  return xs () * a;
+}
+
+static double xd (void)
+{
+  return 3.1415926535;
+}
+
+double yd (double a)
+{
+  return xd () * a;
+}
+
+static void
+sse_test (void)
+{
+  assert (ys (1) == xs ());
+  assert (ys (2) == xs () * 2);
+  assert (yd (1) == xd ());
+  assert (yd (2) == xd () * 2);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefn-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefn-4.c
new file mode 100644
index 000000000..eacdfa793
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefn-4.c
@@ -0,0 +1,38 @@
+/* Execution test for argument passing with SSE2 and local functions
+   Written by Paolo Bonzini, 25 January 2005 */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2 -mfpmath=sse" } */
+
+#include "sse2-check.h"
+
+#include <assert.h>
+
+static float xs (void)
+{
+  return 3.14159265;
+}
+
+float ys (float a)
+{
+  return xs () * a;
+}
+
+static double xd (void)
+{
+  return 3.1415926535;
+}
+
+double yd (double a)
+{
+  return xd () * a;
+}
+
+static void
+sse2_test (void)
+{
+  assert (ys (1) == xs ());
+  assert (ys (2) == xs () * 2);
+  assert (yd (1) == xd ());
+  assert (yd (2) == xd () * 2);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefp-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefp-1.c
new file mode 100644
index 000000000..621e362f4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefp-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -march=k8 -mfpmath=sse" } */
+/* { dg-final { scan-assembler "maxsd" } } */
+/* { dg-final { scan-assembler "minsd" } } */
+double x;
+t()
+{
+  x=x>5?x:5;
+}
+
+double x;
+q()
+{
+  x=x<5?x:5;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefp-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefp-2.c
new file mode 100644
index 000000000..a6caee398
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssefp-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -march=k8 -mfpmath=sse" } */
+/* { dg-final { scan-assembler "maxsd" } } */
+/* { dg-final { scan-assembler "minsd" } } */
+double x;
+q()
+{
+  x=x<5?5:x;
+}
+
+double x;
+q1()
+{
+  x=x>5?5:x;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-1.c
new file mode 100644
index 000000000..9d426b842
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target ilp32 } */
+
+float essef(float) __attribute__((sseregparm));
+double essed(double) __attribute__((sseregparm));
+float __attribute__((sseregparm, noinline)) ssef(float f) { return f; }
+double __attribute__((sseregparm, noinline)) ssed(double d) { return d; }
+extern double d;
+extern float f;
+void test(void)
+{
+  f = essef(f);
+  d = essed(d);
+  f = ssef(f);
+  d = ssed(d);
+}
+
+/* { dg-final { scan-assembler-not "fldl" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-2.c
new file mode 100644
index 000000000..cca98ca82
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-sse" } */
+/* { dg-require-effective-target ilp32 } */
+
+float essef(float) __attribute__((sseregparm));
+double essed(double) __attribute__((sseregparm));
+float __attribute__((sseregparm, noinline)) ssef(float f) { return f; } /* { dg-error "SSE" } */
+double __attribute__((sseregparm, noinline)) ssed(double d) { return d; } /* { dg-error "SSE" } */
+extern double d;
+extern float f;
+void test(void)
+{
+  f = essef(f);
+  d = essed(d);
+  f = ssef(f);
+  d = ssed(d);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-3.c
new file mode 100644
index 000000000..9ee82af44
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2 -O2" } */
+/* { dg-require-effective-target ilp32 } */
+
+/* Make sure we know that mysinfp returns in %xmm0.  */
+
+double __attribute__((sseregparm)) mysin(double x);
+double __attribute__((sseregparm)) (*mysinfp)(double) = mysin;
+double bar(double x)
+{
+  return 1.0+mysinfp(x);
+}
+
+/* { dg-final { scan-assembler "fldl" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-4.c
new file mode 100644
index 000000000..a29cf06bf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-4.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2 -O2" } */
+/* { dg-require-effective-target ilp32 } */
+
+/* Make sure we know that mysinfp returns in %xmm0.  */
+
+double __attribute__((sseregparm)) mysin(double x);
+double __attribute__((sseregparm)) (*mysinfp)(double) = mysin;
+double bar(double x)
+{
+  return mysinfp(x);
+}
+
+/* { dg-final { scan-assembler "fldl" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-5.c
new file mode 100644
index 000000000..7423722d6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-5.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2 -O2" } */
+/* { dg-require-effective-target ilp32 } */
+
+/* Make sure we know that mysinfp returns in %xmm0.  */
+
+double __attribute__((sseregparm)) mysin(void);
+double __attribute__((sseregparm)) (*mysinfp)(void) = mysin;
+double bar(double x)
+{
+  return mysinfp();
+}
+
+/* { dg-final { scan-assembler "fldl" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-6.c
new file mode 100644
index 000000000..6203b6b59
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-6.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2 -O2" } */
+/* { dg-require-effective-target ilp32 } */
+
+/* Make sure we know that mysinfp returns in %xmm0.  */
+
+double __attribute__((sseregparm)) mysin(double x);
+double bar(double x)
+{
+  return mysin(x);
+}
+
+/* { dg-final { scan-assembler "fldl" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-7.c
new file mode 100644
index 000000000..61267df98
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-7.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2 -O2" } */
+/* { dg-require-effective-target ilp32 } */
+
+/* Make sure we know that mysinfp returns in %xmm0.  */
+
+double __attribute__((sseregparm)) mysin(void);
+double bar(double x)
+{
+  return mysin();
+}
+
+/* { dg-final { scan-assembler "fldl" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-8.c
new file mode 100644
index 000000000..3a9d345a9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/sseregparm-8.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-sse" } */
+/* { dg-require-effective-target ilp32 } */
+
+float essef(float) __attribute__((sseregparm));
+double essed(double) __attribute__((sseregparm));
+float __attribute__((sseregparm)) ssef(float f);
+double __attribute__((sseregparm)) ssed(double d);
+extern double d;
+extern float f;
+void test(void)
+{
+  f = essef(f); /* { dg-error "SSE" } */
+  d = essed(d); /* { dg-error "SSE" } */
+  f = ssef(f); /* { dg-error "SSE" } */
+  d = ssed(d); /* { dg-error "SSE" } */
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssetype-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssetype-1.c
new file mode 100644
index 000000000..ef89059b8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssetype-1.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* This test checks for absolute memory operands.  */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "andpd\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "andnpd\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "xorpd\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "orpd\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler-not "movdqa" } } */
+/* { dg-final { scan-assembler "movapd\[^\\n\]*magic" } } */
+
+/* Verify that we generate proper instruction with memory operand.  */
+
+#include <xmmintrin.h>
+
+static __m128d magic_a, magic_b;
+
+__m128d
+t1(void)
+{
+return _mm_and_pd (magic_a,magic_b);
+}
+__m128d
+t2(void)
+{
+return _mm_andnot_pd (magic_a,magic_b);
+}
+__m128d
+t3(void)
+{
+return _mm_or_pd (magic_a,magic_b);
+}
+__m128d
+t4(void)
+{
+return _mm_xor_pd (magic_a,magic_b);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssetype-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssetype-2.c
new file mode 100644
index 000000000..b68a63923
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssetype-2.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "andpd" } } */
+/* { dg-final { scan-assembler "andnpd" } } */
+/* { dg-final { scan-assembler "xorpd" } } */
+/* { dg-final { scan-assembler "orpd" } } */
+/* { dg-final { scan-assembler-not "movdqa" } } */
+
+/* Verify that we generate proper instruction without memory operand.  */
+
+#include <xmmintrin.h>
+__m128d
+t1(__m128d a, __m128d b)
+{
+a=_mm_sqrt_pd(a);
+b=_mm_sqrt_pd(b);
+return _mm_and_pd (a,b);
+}
+__m128d
+t2(__m128d a, __m128d b)
+{
+a=_mm_sqrt_pd(a);
+b=_mm_sqrt_pd(b);
+return _mm_andnot_pd (a,b);
+}
+__m128d
+t3(__m128d a, __m128d b)
+{
+a=_mm_sqrt_pd(a);
+b=_mm_sqrt_pd(b);
+return _mm_or_pd (a,b);
+}
+__m128d
+t4(__m128d a, __m128d b)
+{
+a=_mm_sqrt_pd(a);
+b=_mm_sqrt_pd(b);
+return _mm_xor_pd (a,b);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssetype-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssetype-3.c
new file mode 100644
index 000000000..d6887d5cd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssetype-3.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* This test checks for absolute memory operands.  */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "andps\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "andnps\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "xorps\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "orps\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler-not "movdqa" } } */
+/* { dg-final { scan-assembler "movaps\[^\\n\]*magic" } } */
+
+/* Verify that we generate proper instruction with memory operand.  */
+
+#include <xmmintrin.h>
+
+static __m128 magic_a, magic_b;
+__m128
+t1(void)
+{
+return _mm_and_ps (magic_a,magic_b);
+}
+__m128
+t2(void)
+{
+return _mm_andnot_ps (magic_a,magic_b);
+}
+__m128
+t3(void)
+{
+return _mm_or_ps (magic_a,magic_b);
+}
+__m128
+t4(void)
+{
+return _mm_xor_ps (magic_a,magic_b);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssetype-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssetype-4.c
new file mode 100644
index 000000000..9994b07f2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssetype-4.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "andps" } } */
+/* { dg-final { scan-assembler "andnps" } } */
+/* { dg-final { scan-assembler "xorps" } } */
+/* { dg-final { scan-assembler "orps" } } */
+
+/* Verify that we generate proper instruction without memory operand.  */
+
+#include <xmmintrin.h>
+__m128
+t1(__m128 a, __m128 b)
+{
+a=_mm_sqrt_ps(a);
+b=_mm_sqrt_ps(b);
+return _mm_and_ps (a,b);
+}
+__m128
+t2(__m128 a, __m128 b)
+{
+a=_mm_sqrt_ps(a);
+b=_mm_sqrt_ps(b);
+return _mm_andnot_ps (a,b);
+}
+__m128
+t3(__m128 a, __m128 b)
+{
+a=_mm_sqrt_ps(a);
+b=_mm_sqrt_ps(b);
+return _mm_or_ps (a,b);
+}
+__m128
+t4(__m128 a, __m128 b)
+{
+a=_mm_sqrt_ps(a);
+b=_mm_sqrt_ps(b);
+return _mm_xor_ps (a,b);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssetype-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssetype-5.c
new file mode 100644
index 000000000..75133e9fa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssetype-5.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* This test checks for absolute memory operands.  */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "pand\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "pandn\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "pxor\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "por\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "movdqa" } } */
+/* { dg-final { scan-assembler-not "movaps\[^\\n\]*magic" } } */
+
+/* Verify that we generate proper instruction with memory operand.  */
+
+#include <xmmintrin.h>
+static __m128i magic_a, magic_b;
+__m128i
+t1(void)
+{
+return _mm_and_si128 (magic_a,magic_b);
+}
+__m128i
+t2(void)
+{
+return _mm_andnot_si128 (magic_a,magic_b);
+}
+__m128i
+t3(void)
+{
+return _mm_or_si128 (magic_a,magic_b);
+}
+__m128i
+t4(void)
+{
+return _mm_xor_si128 (magic_a,magic_b);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-check.h
new file mode 100644
index 000000000..78df15db7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-check.h
@@ -0,0 +1,21 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void ssse3_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run SSSE3 test only if host has SSSE3 support.  */
+  if (ecx & bit_SSSE3)
+    ssse3_test ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c
new file mode 100644
index 000000000..7caa1b6c3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c
@@ -0,0 +1,80 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_pabsb (int *i1, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  *(__m64 *) r = _mm_abs_pi8 (t1);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_pabsb128 (int *i1, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  *(__m128i *) r = _mm_abs_epi8 (t1);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *r)
+{
+  char *b1 = (char *) i1;
+  char *bout = (char *) r;
+  int i;
+
+  for (i = 0; i < 16; i++)
+    if (b1[i] < 0)
+      bout[i] = -b1[i];
+    else
+      bout[i] = b1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 4)
+    {
+      /* Manually compute the result */
+      compute_correct_result(&vals[i + 0], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_pabsb (&vals[i + 0], &r[0]);
+      ssse3_test_pabsb (&vals[i + 2], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_pabsb128 (&vals[i + 0], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pabsd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pabsd.c
new file mode 100644
index 000000000..3a73cf011
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pabsd.c
@@ -0,0 +1,79 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_pabsd (int *i1, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  *(__m64 *) r = _mm_abs_pi32 (t1);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_pabsd128 (int *i1, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  *(__m128i *) r = _mm_abs_epi32 (t1);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    if (i1[i] < 0)
+      r[i] = -i1[i];
+    else
+      r[i] = i1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 4)
+    {
+      /* Manually compute the result */
+      compute_correct_result(&vals[i + 0], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_pabsd (&vals[i + 0], &r[0]);
+      ssse3_test_pabsd (&vals[i + 2], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_pabsd128 (&vals[i + 0], r);
+      fail += chk_128(ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pabsw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pabsw.c
new file mode 100644
index 000000000..67e4721b8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pabsw.c
@@ -0,0 +1,81 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_pabsw (int *i1, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  *(__m64 *) r = _mm_abs_pi16 (t1);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_pabsw128 (int *i1, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  *(__m128i *) r = _mm_abs_epi16 (t1);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *r)
+{
+  short *s1 = (short *) i1;
+  short *sout = (short *) r;
+  int i;
+
+  for (i = 0; i < 8; i++)
+    if (s1[i] < 0)
+      sout[i] = -s1[i];
+    else
+      sout[i] = s1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 4)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_pabsw (&vals[i + 0], &r[0]);
+      ssse3_test_pabsw (&vals[i + 2], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_pabsw128 (&vals[i + 0], r);
+      fail += chk_128 (ck, r);
+    }
+  
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-palignr.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-palignr.c
new file mode 100644
index 000000000..dbee9bee4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-palignr.c
@@ -0,0 +1,279 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+#include <string.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_palignr (int *i1, int *i2, unsigned int imm, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+
+  switch (imm)
+    {
+    case 0:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 0);
+      break;
+    case 1:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 1);
+      break;
+    case 2:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 2);
+      break;
+    case 3:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 3);
+      break;
+    case 4:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 4);
+      break;
+    case 5:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 5);
+      break;
+    case 6:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 6);
+      break;
+    case 7:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 7);
+      break;
+    case 8:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 8);
+      break;
+    case 9:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 9);
+      break;
+    case 10:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 10);
+      break;
+    case 11:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 11);
+      break;
+    case 12:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 12);
+      break;
+    case 13:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 13);
+      break;
+    case 14:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 14);
+      break;
+    case 15:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 15);
+      break;
+    default:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 16);
+      break;
+    }
+
+   _mm_empty();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_palignr128 (int *i1, int *i2, unsigned int imm, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+
+  switch (imm)
+    {
+    case 0:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 0);
+      break;
+    case 1:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 1);
+      break;
+    case 2:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 2);
+      break;
+    case 3:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 3);
+      break;
+    case 4:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 4);
+      break;
+    case 5:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 5);
+      break;
+    case 6:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 6);
+      break;
+    case 7:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 7);
+      break;
+    case 8:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 8);
+      break;
+    case 9:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 9);
+      break;
+    case 10:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 10);
+      break;
+    case 11:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 11);
+      break;
+    case 12:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 12);
+      break;
+    case 13:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 13);
+      break;
+    case 14:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 14);
+      break;
+    case 15:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 15);
+      break;
+    case 16:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 16);
+      break;
+    case 17:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 17);
+      break;
+    case 18:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 18);
+      break;
+    case 19:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 19);
+      break;
+    case 20:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 20);
+      break;
+    case 21:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 21);
+      break;
+    case 22:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 22);
+      break;
+    case 23:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 23);
+      break;
+    case 24:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 24);
+      break;
+    case 25:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 25);
+      break;
+    case 26:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 26);
+      break;
+    case 27:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 27);
+      break;
+    case 28:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 28);
+      break;
+    case 29:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 29);
+      break;
+    case 30:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 30);
+      break;
+    case 31:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 31);
+      break;
+    default:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 32);
+      break;
+    }
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result_128 (int *i1, int *i2, unsigned int imm, int *r)
+{
+  char buf [32];
+  char *bout = (char *) r;
+  int i;
+
+  memcpy (&buf[0], i2, 16);
+  memcpy (&buf[16], i1, 16);
+
+  for (i = 0; i < 16; i++)
+    if (imm >= 32 || imm + i >= 32)
+      bout[i] = 0;
+    else
+      bout[i] = buf[imm + i];
+}
+
+#ifndef __AVX__
+static void
+compute_correct_result_64 (int *i1, int *i2, unsigned int imm, int *r)
+{
+  char buf [16];
+  char *bout = (char *)r;
+  int i;
+
+  /* Handle the first half */
+  memcpy (&buf[0], i2, 8);
+  memcpy (&buf[8], i1, 8);
+
+  for (i = 0; i < 8; i++)
+    if (imm >= 16 || imm + i >= 16)
+      bout[i] = 0;
+    else
+      bout[i] = buf[imm + i];
+
+  /* Handle the second half */
+  memcpy (&buf[0], &i2[2], 8);
+  memcpy (&buf[8], &i1[2], 8);
+
+  for (i = 0; i < 8; i++)
+    if (imm >= 16 || imm + i >= 16)
+      bout[i + 8] = 0;
+    else
+      bout[i + 8] = buf[imm + i];
+}
+#endif
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  unsigned int imm;
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    for (imm = 0; imm < 100; imm++)
+      {
+#ifndef __AVX__
+	/* Manually compute the result */
+	compute_correct_result_64 (&vals[i + 0], &vals[i + 4], imm, ck);
+
+	/* Run the 64-bit tests */
+	ssse3_test_palignr (&vals[i + 0], &vals[i + 4], imm, &r[0]);
+	ssse3_test_palignr (&vals[i + 2], &vals[i + 6], imm, &r[2]);
+	fail += chk_128 (ck, r);
+#endif
+
+	/* Recompute the results for 128-bits */
+	compute_correct_result_128 (&vals[i + 0], &vals[i + 4], imm, ck);
+
+	/* Run the 128-bit tests */
+	ssse3_test_palignr128 (&vals[i + 0], &vals[i + 4], imm, r);
+	fail += chk_128 (ck, r);
+      }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phaddd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phaddd.c
new file mode 100644
index 000000000..bef781686
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phaddd.c
@@ -0,0 +1,81 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_phaddd (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_hadd_pi32 (t1, t2);
+  _mm_empty();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_phaddd128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *) r = _mm_hadd_epi32 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result(int *i1, int *i2, int *r)
+{
+  int i;
+
+  for (i = 0; i < 2; i++)
+    r[i] = i1[2 * i] + i1[2 * i + 1];
+  for (i = 0; i < 2; i++)
+    r[i + 2] = i2[2 * i] + i2[2 * i + 1];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_phaddd (&vals[i + 0], &vals[i + 2], &r[0]);
+      ssse3_test_phaddd (&vals[i + 4], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_phaddd128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phaddsw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phaddsw.c
new file mode 100644
index 000000000..ff31fe5a5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phaddsw.c
@@ -0,0 +1,95 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_phaddsw (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_hadds_pi16 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_phaddsw128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+ *(__m128i *) r = _mm_hadds_epi16 (t1, t2);
+}
+
+static short
+signed_saturate_to_word (int x)
+{
+  if (x > (int) 0x7fff)
+    return 0x7fff;
+
+  if (x < (int) 0xffff8000)
+    return 0x8000;
+
+  return (short) x;
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  short *s1 = (short *) i1;
+  short *s2 = (short *) i2;
+  short *sout = (short *) r;
+  int i;
+
+  for (i = 0; i < 4; i++)
+    sout[i] = signed_saturate_to_word(s1[2 * i] + s1[2 * i + 1]);
+  for (i = 0; i < 4; i++)
+    sout[i + 4] = signed_saturate_to_word(s2[2 * i] + s2[2 * i + 1]);
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_phaddsw (&vals[i + 0], &vals[i + 2], &r[0]);
+      ssse3_test_phaddsw (&vals[i + 4], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_phaddsw128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phaddw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phaddw.c
new file mode 100644
index 000000000..05c0afd4f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phaddw.c
@@ -0,0 +1,84 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_phaddw (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_hadd_pi16 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_phaddw128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *) r = _mm_hadd_epi16 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result(int *i1, int *i2, int *r)
+{
+  short *s1 = (short *) i1;
+  short *s2 = (short *) i2;
+  short *sout = (short *) r;
+  int i;
+
+  for (i = 0; i < 4; i++)
+    sout[i] = s1[2 * i] + s1[2 * i + 1];
+
+  for (i = 0; i < 4; i++)
+    sout[i + 4] = s2[2 * i] + s2[2 * i + 1];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_phaddw (&vals[i + 0], &vals[i + 2], &r[0]);
+      ssse3_test_phaddw (&vals[i + 4], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_phaddw128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phsubd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phsubd.c
new file mode 100644
index 000000000..5884e5c12
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phsubd.c
@@ -0,0 +1,80 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_phsubd (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_hsub_pi32(t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_phsubd128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *) r = _mm_hsub_epi32 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  int i;
+
+  for (i = 0; i < 2; i++)
+    r[i] = i1[2 * i] - i1[2 * i + 1];
+  for (i = 0; i < 2; i++)
+    r[i + 2] = i2[2 * i] - i2[2 * i + 1];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_phsubd (&vals[i + 0], &vals[i + 2], &r[0]);
+      ssse3_test_phsubd (&vals[i + 4], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_phsubd128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phsubsw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phsubsw.c
new file mode 100644
index 000000000..371c8d112
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phsubsw.c
@@ -0,0 +1,98 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_phsubsw (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+
+  *(__m64 *) r = _mm_hsubs_pi16 (t1, t2);
+
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_phsubsw128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *) r = _mm_hsubs_epi16 (t1, t2);
+}
+
+static short
+signed_saturate_to_word (int x)
+{
+  if (x > (int )0x7fff)
+    return 0x7fff;
+
+  if (x < (int) 0xffff8000)
+    return 0x8000;
+
+  return (short)x;
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  short *s1 = (short *) i1;
+  short *s2 = (short *) i2;
+  short *sout = (short *) r;
+  int i;
+
+  for (i = 0; i < 4; i++)
+    sout[i] = signed_saturate_to_word (s1[2 * i] - s1[2 * i + 1]);
+
+  for (i = 0; i < 4; i++)
+    sout[i + 4] = signed_saturate_to_word (s2[2 * i] - s2[2 * i + 1]);
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_phsubsw (&vals[i + 0], &vals[i + 2], &r[0]);
+      ssse3_test_phsubsw (&vals[i + 4], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_phsubsw128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phsubw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phsubw.c
new file mode 100644
index 000000000..f3dbf9c98
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-phsubw.c
@@ -0,0 +1,83 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_phsubw (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_hsub_pi16 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_phsubw128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+
+  *(__m128i *) r = _mm_hsub_epi16 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  short *s1 = (short *) i1;
+  short *s2 = (short *) i2;
+  short *sout = (short *) r;
+  int i;
+
+  for (i = 0; i < 4; i++)
+    sout[i] = s1[2 * i] - s1[2 * i + 1];
+  for (i = 0; i < 4; i++)
+    sout[i + 4] = s2[2 * i] - s2[2 * i + 1];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_phsubw (&vals[i + 0], &vals[i + 2], &r[0]);
+      ssse3_test_phsubw (&vals[i + 4], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_phsubw128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pmaddubsw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pmaddubsw.c
new file mode 100644
index 000000000..00bfc844f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pmaddubsw.c
@@ -0,0 +1,98 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_pmaddubsw (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_maddubs_pi16 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_pmaddubsw128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *) r = _mm_maddubs_epi16 (t1, t2);
+}
+
+static short
+signed_saturate_to_word(int x)
+{
+  if (x > (int) 0x7fff)
+    return 0x7fff;
+
+  if (x < (int) 0xffff8000)
+    return 0x8000;
+
+  return (short) x;
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  unsigned char *ub1 = (unsigned char *) i1;
+  char *sb2 = (char *) i2;
+  short *sout = (short *) r;
+  int t0;
+  int i;
+
+  for (i = 0; i < 8; i++)
+    { 
+      t0 = ((int) ub1[2 * i] * (int) sb2[2 * i] +
+	    (int) ub1[2 * i + 1] * (int) sb2[2 * i + 1]);
+      sout[i] = signed_saturate_to_word (t0);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_pmaddubsw (&vals[i + 0], &vals[i + 4], &r[0]);
+      ssse3_test_pmaddubsw (&vals[i + 2], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_pmaddubsw128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pmulhrsw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pmulhrsw.c
new file mode 100644
index 000000000..24570b3bd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pmulhrsw.c
@@ -0,0 +1,85 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_pmulhrsw (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_mulhrs_pi16 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_pmulhrsw128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *) r = _mm_mulhrs_epi16 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  short *s1 = (short *) i1;
+  short *s2 = (short *) i2;
+  short *sout = (short *) r;
+  int t0;
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      t0 = (((int) s1[i] * (int) s2[i]) >> 14) + 1;
+      sout[i] = (short) (t0 >> 1);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_pmulhrsw (&vals[i + 0], &vals[i + 4], &r[0]);
+      ssse3_test_pmulhrsw (&vals[i + 2], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_pmulhrsw128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pshufb.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pshufb.c
new file mode 100644
index 000000000..b995456b6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-pshufb.c
@@ -0,0 +1,114 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_pshufb (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *)r = _mm_shuffle_pi8 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_pshufb128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *)r = _mm_shuffle_epi8 (t1, t2);
+}
+
+#ifndef __AVX__
+/* Routine to manually compute the results */
+static void
+compute_correct_result_64 (int *i1, int *i2, int *r)
+{
+  char *b1 = (char *) i1;
+  char *b2 = (char *) i2;
+  char *bout = (char *) r;
+  int i;
+  char select;
+
+  for (i = 0; i < 16; i++)
+    {
+      select = b2[i];
+      if (select & 0x80)
+	bout[i] = 0;
+      else if (i < 8)
+	bout[i] = b1[select & 0x7];
+      else
+	bout[i] = b1[8 + (select & 0x7)];
+    }
+}
+#endif
+
+static void
+compute_correct_result_128 (int *i1, int *i2, int *r)
+{
+  char *b1 = (char *) i1;
+  char *b2 = (char *) i2;
+  char *bout = (char *) r;
+  int i;
+  char select;
+
+  for (i = 0; i < 16; i++)
+    {
+      select = b2[i];
+      if (select & 0x80)
+	bout[i] = 0;
+      else
+	bout[i] = b1[select & 0xf];
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+#ifndef __AVX__
+      /* Manually compute the result */
+      compute_correct_result_64 (&vals[i + 0], &vals[i + 4], ck);
+
+      /* Run the 64-bit tests */
+      ssse3_test_pshufb (&vals[i + 0], &vals[i + 4], &r[0]);
+      ssse3_test_pshufb (&vals[i + 2], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Recompute the result for 128-bits */
+      compute_correct_result_128 (&vals[i + 0], &vals[i + 4], ck);
+
+      /* Run the 128-bit tests */
+      ssse3_test_pshufb128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-psignb.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-psignb.c
new file mode 100644
index 000000000..7462929aa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-psignb.c
@@ -0,0 +1,85 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_psignb (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_sign_pi8 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_psignb128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *) r = _mm_sign_epi8 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  char *b1 = (char *) i1;
+  char *b2 = (char *) i2;
+  char *bout = (char *) r;
+  int i;
+
+  for (i = 0; i < 16; i++)
+    if (b2[i] < 0)
+      bout[i] = -b1[i];
+    else if (b2[i] == 0)
+      bout[i] = 0;
+    else
+      bout[i] = b1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_psignb (&vals[i + 0], &vals[i + 4], &r[0]);
+      ssse3_test_psignb (&vals[i + 2], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_psignb128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-psignd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-psignd.c
new file mode 100644
index 000000000..eca0489f8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-psignd.c
@@ -0,0 +1,82 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_psignd (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_sign_pi32 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_psignd128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *)r = _mm_sign_epi32 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    if (i2[i] < 0)
+      r[i] = -i1[i];
+    else if (i2[i] == 0)
+      r[i] = 0;
+    else
+      r[i] = i1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_psignd (&vals[i + 0], &vals[i + 4], &r[0]);
+      ssse3_test_psignd (&vals[i + 2], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_psignd128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-psignw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-psignw.c
new file mode 100644
index 000000000..00a506fd8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-psignw.c
@@ -0,0 +1,85 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_psignw (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_sign_pi16 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_psignw128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+ *(__m128i *) r = _mm_sign_epi16 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  short *s1 = (short *) i1;
+  short *s2 = (short *) i2;
+  short *sout = (short *) r;
+  int i;
+
+  for (i = 0; i < 8; i++)
+    if (s2[i] < 0)
+      sout[i] = -s1[i];
+    else if (s2[i] == 0)
+      sout[i] = 0;
+    else
+      sout[i] = s1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_psignw (&vals[i + 0], &vals[i + 4], &r[0]);
+      ssse3_test_psignw (&vals[i + 2], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_psignw128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-vals.h b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-vals.h
new file mode 100644
index 000000000..048ca911c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/ssse3-vals.h
@@ -0,0 +1,60 @@
+/* Routine to check correctness of the results */
+static int
+chk_128 (int *v1, int *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 4; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static int vals [256] __attribute__ ((aligned(16))) =
+{
+  0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x5be800ee, 0x4f2d7b15,
+  0x409d9291, 0xdd95f27f, 0x423986e3, 0x21a4d2cd, 0xa7056d84, 0x4f4e5a3b,
+  0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+  0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+  0x73ef0244, 0xcd836329, 0x847f634f, 0xa7e3abcf, 0xb4c14764, 0x1ef42c06,
+  0x504f29ac, 0x4ae7ca73, 0xaddde3c9, 0xf63ded2e, 0xa5d3553d, 0xa52ae05f,
+  0x6fd3c83a, 0x7dc2b300, 0x76b05de7, 0xea8ebae5, 0x549568dd, 0x172f0358,
+  0x917eadf0, 0x796fb0a7, 0xb39381af, 0xd0591d61, 0x731d2f17, 0xbc4b6f5d,
+  0x8ec664c2, 0x3c199c19, 0x9c81db12, 0x6d85913b, 0x486107a9, 0xab6f4b26,
+  0x5630d37c, 0x20836e85, 0x40d4e746, 0xdfbaba36, 0xbeacaa69, 0xb3c84083,
+  0x8a688eb4, 0x08cde481, 0x66e7a190, 0x74ee1639, 0xb3942a19, 0xe0c40471,
+  0x9b789489, 0x9751207a, 0x543a1524, 0x41da7ad6, 0x614bb563, 0xf86f57b1,
+  0x69e62199, 0x2150cb12, 0x9ed74062, 0x429471f4, 0xad28502b, 0xf2e2d4d5,
+  0x45b6ce09, 0xaaa5e649, 0xb46da484, 0x0a637515, 0xae7a3212, 0x5afc784c,
+  0x776cfbbe, 0x9c542bb2, 0x64193aa8, 0x16e8a655, 0x4e3d2f92, 0xe05d7b72,
+  0x89854ebc, 0x8c318814, 0xb81e76e0, 0x3f2625f5, 0x61b44852, 0x5209d7ad,
+  0x842fe317, 0xd3cfcca1, 0x8d287cc7, 0x80f0c9a8, 0x4215f4e5, 0x563993d6,
+  0x5d627433, 0xc4449e35, 0x5b4fe009, 0x3ef92286, 0xacbc8927, 0x549ab870,
+  0x9ac5b959, 0xed8f1c91, 0x7ecf02cd, 0x989c0e8b, 0xa31d6918, 0x1dc2bcc1,
+  0x99d3f3cc, 0x6857acc8, 0x45d7324a, 0xaebdf2e6, 0x7af2f2ae, 0x09716f73,
+  0x7816e694, 0xc65493c0, 0x9f7e87bc, 0xaa96cd40, 0xbfb5bfc6, 0x01a2cce7,
+  0x5f1d8c46, 0x45303efb, 0xb24607c3, 0xef2009a7, 0xba873753, 0xbefb14bc,
+  0x74e53cd3, 0x70124708, 0x6eb4bdbd, 0xf3ba5e43, 0x4c94085f, 0x0c03e7e0,
+  0x9a084931, 0x62735424, 0xaeee77c5, 0xdb34f90f, 0x6860cbdd, 0xaf77cf9f,
+  0x95b28158, 0x23bd70d7, 0x9fbc3d88, 0x742e659e, 0x53bcfb48, 0xb8a63f6c,
+  0x4dcf3373, 0x2b168627, 0x4fe20745, 0xd0af5e94, 0x22514e6a, 0xb8ef25c2,
+  0x89ec781a, 0x13d9002b, 0x6d724500, 0x7fdbf63f, 0xb0e9ced5, 0xf919e0f3,
+  0x00fef203, 0x8905d47a, 0x434e7517, 0x4aef8e2c, 0x689f51e8, 0xe513b7c3,
+  0x72bbc5d2, 0x3a222f74, 0x05c3a0f9, 0xd5489d82, 0xb41fbe83, 0xec5d305f,
+  0x5ea02b0b, 0xb176065b, 0xa8eb404e, 0x80349117, 0x210fd49e, 0x43898d0e,
+  0x6c151b9c, 0x8742df18, 0x7b64de73, 0x1dbf52b2, 0x55c9cb19, 0xeb841f10,
+  0x10b8ae76, 0x0764ecb6, 0xb7479018, 0x2672cb3f, 0x7ac9ac90, 0x4be5332c,
+  0x8f1a0615, 0x4efb7a77, 0x16551a85, 0xdb2c3d66, 0x49179c07, 0x5dc4657e,
+  0x5e76907e, 0xd7486a9c, 0x445204a4, 0x65cdc426, 0x33f86ded, 0xcba95dda,
+  0x83351f16, 0xfedefad9, 0x639b620f, 0x86896a64, 0xba4099ba, 0x965f4a21,
+  0x1247154f, 0x25604c42, 0x5862d692, 0xb1e9149e, 0x612516a5, 0x02c49bf8,
+  0x631212bf, 0x9f69f54e, 0x168b63b0, 0x310a25ba, 0xa42a59cd, 0x084f0af9,
+  0x44a06cec, 0x5c0cda40, 0xb932d721, 0x7c42bb0d, 0x213cd3f0, 0xedc7f5a4,
+  0x7fb85859, 0x6b3da5ea, 0x61cd591e, 0xe8e9aa08, 0x4361fc34, 0x53d40d2a,
+  0x0511ad1b, 0xf996b44c, 0xb5ead756, 0xc022138d, 0x6172adf1, 0xa4a0a3b4,
+  0x8c2977b8, 0xa8e482ed, 0x04fcdd6b, 0x3f7b85d4, 0x4fca1e46, 0xa392ddca,
+  0x569fc791, 0x346a706c, 0x543bf3eb, 0x895b3cde, 0x2146bb80, 0x26b3c168,
+  0x929998db, 0x1ea472c9, 0x7207b36b, 0x6a8f10d4 
+};
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stack-prot-kernel.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stack-prot-kernel.c
new file mode 100644
index 000000000..4a93e333c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stack-prot-kernel.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -fstack-protector-all -mcmodel=kernel" } */
+
+void test1 (int x)
+{
+  char p[40];
+  int i;
+  for (i=0; i<40; i++)
+	p[i] = x;
+}
+
+/* { dg-final { scan-assembler-not "%fs" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stack-realign.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stack-realign.c
new file mode 100644
index 000000000..ab9360f49
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stack-realign.c
@@ -0,0 +1,17 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-mstackrealign -O2" } */
+
+extern void abort (void);
+
+__attribute__((noinline)) static void foo (int i1, int i2, int i3)
+{
+  if (i3 != 3)
+    abort ();
+}
+
+int main (int argc, char **argv)
+{
+  foo (1, 2, 3);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/asm-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/asm-1.c
new file mode 100644
index 000000000..e4d4f20bb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/asm-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-mpreferred-stack-boundary=2" } */
+
+/* This case is to detect a compile time regression introduced in stack
+   branch development. */
+f(){asm("%0"::"r"(1.5F));}g(){asm("%0"::"r"(1.5));}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/longlong-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/longlong-1.c
new file mode 100644
index 000000000..225d0c5e5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/longlong-1.c
@@ -0,0 +1,15 @@
+/* PR target/39137 */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=2" } */
+/* Make sure dynamic stack realignment isn't performed just because there
+   are long long variables.  */
+/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]*-8,\[^\\n\]*sp" } } */
+
+void fn (void *);
+
+void f1 (void)
+{
+  unsigned long long a;
+  fn (&a);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/longlong-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/longlong-2.c
new file mode 100644
index 000000000..ae7f3ee33
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/longlong-2.c
@@ -0,0 +1,33 @@
+/* { dg-do compile  { target { ! *-*-darwin* } } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=2" } */
+/* { dg-final { scan-assembler-times "and\[lq\]?\[^\\n\]*-8,\[^\\n\]*sp" 2 } } */ 
+/* { dg-final { scan-assembler-times "and\[lq\]?\[^\\n\]*-16,\[^\\n\]*sp" 2 } } */ 
+
+void fn (void *);
+
+void f2 (void)
+{
+  unsigned long long a __attribute__((aligned (8)));
+  fn (&a);
+}
+
+void f3 (void)
+{
+  typedef unsigned long long L __attribute__((aligned (8)));
+  L a;
+  fn (&a);
+}
+
+void f4 (void)
+{
+  unsigned long long a __attribute__((aligned (16)));
+  fn (&a);
+}
+
+void f5 (void)
+{
+  typedef unsigned long long L __attribute__((aligned (16)));
+  L a;
+  fn (&a);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-1.c
new file mode 100644
index 000000000..c5b32e5c4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-mpreferred-stack-boundary=2" } */
+
+/* This compile only test is to detect an assertion failure in stack branch
+   development.  */
+
+double
+foo (void)
+{
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-2.c
new file mode 100644
index 000000000..113e71b80
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-mpreferred-stack-boundary=2" } */
+
+/* This compile only test is to detect an assertion failure in stack branch
+   development.  */
+void baz (void);
+                       
+double foo (void)
+{
+  baz ();
+  return;
+}
+
+double bar (void)
+{
+  baz ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-3.c
new file mode 100644
index 000000000..8a682b8fc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! { ilp32 && dfp } } } */
+/* { dg-options "-msse -std=gnu99 -mpreferred-stack-boundary=2" } */
+
+/* This compile only test is to detect an assertion failure in stack branch
+   development.  */
+_Decimal128 test (void)
+{
+  return 1234123412341234.123412341234dl;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-4.c
new file mode 100644
index 000000000..a1e35dcc2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-4.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mpreferred-stack-boundary=4" } */
+/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]*-64,\[^\\n\]*sp" } } */
+
+/* This compile only test is to detect an assertion failure in stack branch
+   development.  */
+typedef int aligned __attribute__((aligned(64)));
+
+aligned
+foo (void) { }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-5.c
new file mode 100644
index 000000000..208bc0d8a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-5.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mpreferred-stack-boundary=4" } */
+/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]*-64,\[^\\n\]*sp" } } */
+
+/* This compile only test is to detect an assertion failure in stack branch
+   development.  */
+struct bar
+{
+  int x;
+} __attribute__((aligned(64)));
+
+
+struct bar
+foo (void) { }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-6.c
new file mode 100644
index 000000000..b1aa1eac8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/return-6.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mpreferred-stack-boundary=4" } */
+/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]*-64,\[^\\n\]*sp" } } */
+
+/* This compile only test is to detect an assertion failure in stack branch
+   development.  */
+struct bar
+{
+  int x __attribute__((aligned(64)));
+};
+
+
+struct bar
+foo (void) { }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/stackalign.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/stackalign.exp
new file mode 100644
index 000000000..463ba612e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/stackalign/stackalign.exp
@@ -0,0 +1,47 @@
+# Copyright (C) 2008
+# Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# Exit immediately if this isn't a x86 target.
+if { ![istarget i?86*-*-*] && ![istarget x86_64-*-*] } then {
+  return
+}
+
+load_lib gcc-dg.exp
+
+# Only run on targets which support automatic stack alignment.
+if { ![check_effective_target_automatic_stack_alignment] } then {
+    return
+}
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS "-w"
+}
+
+# Initialize `dg'.
+dg-init
+
+set additional_flags "-mstackrealign"
+
+dg-runtest [lsort [glob $srcdir/$subdir/*.c]] $additional_flags $DEFAULT_CFLAGS
+
+set additional_flags "-mno-stackrealign"
+
+dg-runtest [lsort [glob $srcdir/$subdir/*.c]] $additional_flags $DEFAULT_CFLAGS
+
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/strinline.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/strinline.c
new file mode 100644
index 000000000..2fe671416
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/strinline.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -fPIC" } */
+typedef unsigned int size_t;
+ char *
+__mempcpy_by2 (char *__dest, __const char *__src, size_t __srclen)
+{
+  register char *__tmp = __dest;
+  register unsigned long int __d0, __d1;
+  __asm__ __volatile__
+    ("shrl      $1,%3\n\t"
+     "jz        2f\n"
+     "1:\n\t"
+     "movl      (%2),%0\n\t"
+     "leal      4(%2),%2\n\t"
+     "movl      %0,(%1)\n\t"
+     "leal      4(%1),%1\n\t"
+     "decl      %3\n\t"
+     "jnz       1b\n"
+     "2:\n\t"
+     "movw      (%2),%w0\n\t"
+     "movw      %w0,(%1)"
+     : "=&q" (__d0), "=r" (__tmp), "=&r" (__src), "=&r" (__d1),
+       "=m" ( *(struct { __extension__ char __x[__srclen]; } *)__dest)
+     : "1" (__tmp), "2" (__src), "3" (__srclen / 2),
+       "m" ( *(struct { __extension__ char __x[__srclen]; } *)__src)
+     : "cc");
+  return __tmp + 2;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/tailcall-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/tailcall-1.c
new file mode 100644
index 000000000..e6ae990a5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/tailcall-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2" } */
+
+typedef unsigned int Cardinal;
+typedef char *String;
+typedef struct _WidgetRec *Widget;
+
+typedef union _XEvent {
+        int type;
+ long pad[24];
+} XEvent;
+
+
+extern int SendMousePosition (Widget w, XEvent* event);
+
+
+void
+HandleIgnore(Widget w,
+      XEvent * event,
+      String * params ,
+      Cardinal *param_count )
+{
+
+    (void) SendMousePosition(w, event);
+}
+
+/* { dg-final { scan-assembler "jmp" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/unordcmp-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/unordcmp-1.c
new file mode 100644
index 000000000..49d4b8e07
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/unordcmp-1.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-final { scan-assembler "cmpunordss" } } */
+/* { dg-final { scan-assembler "cmpunordps" } } */
+/* { dg-final { scan-assembler "cmpunordsd" } } */
+/* { dg-final { scan-assembler "cmpunordpd" } } */
+/* { dg-final { scan-assembler-not "cmpordss" } } */
+/* { dg-final { scan-assembler-not "cmpordps" } } */
+/* { dg-final { scan-assembler-not "cmpordsd" } } */
+/* { dg-final { scan-assembler-not "cmpordpd" } } */
+
+#include <emmintrin.h>
+
+__m128
+f1 (__m128 x, __m128 y)
+{
+  return _mm_cmpunord_ss (x, y);
+}
+
+__m128
+f2 (__m128 x, __m128 y)
+{
+  return _mm_cmpunord_ps (x, y);
+}
+
+__m128d
+f3 (__m128d x, __m128d y)
+{
+  return _mm_cmpunord_sd (x, y);
+}
+
+__m128d
+f4 (__m128d x, __m128d y)
+{
+  return _mm_cmpunord_pd (x, y);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/unroll-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/unroll-1.c
new file mode 100644
index 000000000..8cf19c4be
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/unroll-1.c
@@ -0,0 +1,18 @@
+/* PR optimization/8599 */
+/* { dg-do run } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-mtune=k6 -O2 -funroll-loops" } */
+
+extern void exit (int);
+
+void *array[4];
+
+int main ()
+{
+  int i;
+ 
+  for (i = 0; i < 4; i++)
+    array[i] = 0;
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-1.c
new file mode 100644
index 000000000..1875e0a69
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-1.c
@@ -0,0 +1,32 @@
+/* PR middle-end/36858 */
+/* { dg-do run } */
+/* { dg-options "-w" { target { lp64 } } } */
+/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" { target { ilp32 } } } */
+
+#include "sse2-check.h"
+#include <stdarg.h>
+#include <emmintrin.h>
+
+int
+__attribute__((noinline))
+test (int a, ...)
+{
+  return a;
+}
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+
+int
+__attribute__((noinline))
+foo (void)
+{
+  return test (1, n1);
+}
+
+static void
+__attribute__((noinline))
+sse2_test (void)
+{
+  if (foo () != 1)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-10.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-10.c
new file mode 100644
index 000000000..053649877
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-10.c
@@ -0,0 +1,112 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-mavx" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "avx-check.h"
+
+struct m256d
+{
+  __m256d  v;
+};
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+struct m256d n2 = { { -93.83, 893.318, 3994.3, -39484.0 } };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+struct m256d n8 = { { -123.3, 2.3, 3.4, -10.03 } };
+__m128 n9 = { -123.3, 2.3, 3.4, -10.03 };
+__m128i n10 = { 1233, -100 };
+int n11 = 407;
+double n12 = 304.9;
+__m128i n13 = { 233, -110 };
+__m256i n14 = { -1233, 23, 34, -1003 };
+__m128i n15 = { -393, -180 };
+__m128d n16 = { 73.0, 63.18 };
+__m256 n17 = { -183.3, -22.3, 13.9, -119.3, 483.1, 122.3, -33.4, -9.37 };
+__m128 n18 = { -183.3, 22.3, 13.4, -19.03 };
+
+__m128 e1;
+struct m256d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+struct m256d e8;
+__m128 e9;
+__m128i e10;
+int e11;
+double e12;
+__m128i e13;
+__m256i e14;
+__m128i e15;
+__m128d e16;
+__m256 e17;
+__m128 e18;
+
+static void
+__attribute__((noinline))
+foo (va_list va_arglist)
+{
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, struct m256d);
+  e9 = va_arg (va_arglist, __m128);
+  e10 = va_arg (va_arglist, __m128i);
+  e11 = va_arg (va_arglist, int);
+  e12 = va_arg (va_arglist, double);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m256i);
+  e15 = va_arg (va_arglist, __m128i);
+  e16 = va_arg (va_arglist, __m128d);
+  e17 = va_arg (va_arglist, __m256);
+  e18 = va_arg (va_arglist, __m128);
+  va_end (va_arglist);
+}
+
+static void
+__attribute__((noinline))
+test (__m128 a1, struct m256d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  foo (va_arglist);
+  va_end (va_arglist);
+}
+
+static void
+avx_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
+	n13, n14, n15, n16, n17, n18);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (__builtin_memcmp (&e10, &n10, sizeof (e10)) == 0);
+  assert (n11 == e11);
+  assert (n12 == e12);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+  assert (__builtin_memcmp (&e16, &n16, sizeof (e16)) == 0);
+  assert (__builtin_memcmp (&e17, &n17, sizeof (e17)) == 0);
+  assert (__builtin_memcmp (&e18, &n18, sizeof (e18)) == 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-2.c
new file mode 100644
index 000000000..0534ac774
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-2.c
@@ -0,0 +1,40 @@
+/* PR middle-end/36859 */
+/* { dg-do run } */
+/* { dg-options "-w" { target { lp64 } } } */
+/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" { target { ilp32 } } } */
+
+#include "sse2-check.h"
+#include <stdarg.h>
+#include <emmintrin.h>
+
+__m128
+__attribute__((noinline))
+test (int a, ...)
+{
+  __m128 x;
+  va_list va_arglist;
+
+  va_start (va_arglist, a);
+  x = va_arg (va_arglist, __m128);
+  va_end (va_arglist);
+  return x;
+}
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+
+int
+__attribute__((noinline))
+foo (void)
+{
+  __m128 x = test (1, n1);
+  if (__builtin_memcmp (&x, &n1, sizeof (x)) != 0)
+    abort ();
+  return 0;
+}
+
+static void
+__attribute__((noinline))
+sse2_test (void)
+{
+  foo ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-3.c
new file mode 100644
index 000000000..a6b5876f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-3.c
@@ -0,0 +1,85 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "sse2-check.h"
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+__m128d n2 = { -93.83, 893.318 };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+__m128 n8 = { -123.3, 2.3, 3.4, -10.03 };
+__m128i n9 = { 1233, -100 };
+int n10 = 407;
+double n11 = 304.9;
+__m128i n12 = { 233, -110 };
+__m128i n13 = { -393, -180 };
+__m128d n14 = { 73.0, 63.18 };
+__m128 n15 = { -183.3, 22.3, 13.4, -19.03 };
+
+__m128 e1;
+__m128d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+__m128 e8;
+__m128i e9;
+int e10;
+double e11;
+__m128i e12;
+__m128i e13;
+__m128d e14;
+__m128 e15;
+
+static void
+__attribute__((noinline))
+test (__m128 a1, __m128d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, __m128);
+  e9 = va_arg (va_arglist, __m128i);
+  e10 = va_arg (va_arglist, int);
+  e11 = va_arg (va_arglist, double);
+  e12 = va_arg (va_arglist, __m128i);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m128d);
+  e15 = va_arg (va_arglist, __m128);
+  va_end (va_arglist);
+}
+
+static void
+sse2_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (n10 == e10);
+  assert (n11 == e11);
+  assert (__builtin_memcmp (&e12, &n12, sizeof (e12)) == 0);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-4.c
new file mode 100644
index 000000000..e2f83b0c4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-4.c
@@ -0,0 +1,92 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "sse2-check.h"
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+__m128d n2 = { -93.83, 893.318 };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+__m128 n8 = { -123.3, 2.3, 3.4, -10.03 };
+__m128i n9 = { 1233, -100 };
+int n10 = 407;
+double n11 = 304.9;
+__m128i n12 = { 233, -110 };
+__m128i n13 = { -393, -180 };
+__m128d n14 = { 73.0, 63.18 };
+__m128 n15 = { -183.3, 22.3, 13.4, -19.03 };
+
+__m128 e1;
+__m128d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+__m128 e8;
+__m128i e9;
+int e10;
+double e11;
+__m128i e12;
+__m128i e13;
+__m128d e14;
+__m128 e15;
+
+static void
+__attribute__((noinline))
+foo (va_list va_arglist)
+{
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, __m128);
+  e9 = va_arg (va_arglist, __m128i);
+  e10 = va_arg (va_arglist, int);
+  e11 = va_arg (va_arglist, double);
+  e12 = va_arg (va_arglist, __m128i);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m128d);
+  e15 = va_arg (va_arglist, __m128);
+}
+
+static void
+__attribute__((noinline))
+test (__m128 a1, __m128d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  foo (va_arglist);
+  va_end (va_arglist);
+}
+
+static void
+sse2_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (n10 == e10);
+  assert (n11 == e11);
+  assert (__builtin_memcmp (&e12, &n12, sizeof (e12)) == 0);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-5.c
new file mode 100644
index 000000000..03ff60cd7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-5.c
@@ -0,0 +1,99 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-mavx" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "avx-check.h"
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+__m256d n2 = { -93.83, 893.318, 3994.3, -39484.0 };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+__m256d n8 = { -123.3, 2.3, 3.4, -10.03 };
+__m128 n9 = { -123.3, 2.3, 3.4, -10.03 };
+__m128i n10 = { 1233, -100 };
+int n11 = 407;
+double n12 = 304.9;
+__m128i n13 = { 233, -110 };
+__m256i n14 = { -1233, 23, 34, -1003 };
+__m128i n15 = { -393, -180 };
+__m128d n16 = { 73.0, 63.18 };
+__m256 n17 = { -183.3, -22.3, 13.9, -119.3, 483.1, 122.3, -33.4, -9.37 };
+__m128 n18 = { -183.3, 22.3, 13.4, -19.03 };
+
+__m128 e1;
+__m256d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+__m256d e8;
+__m128 e9;
+__m128i e10;
+int e11;
+double e12;
+__m128i e13;
+__m256i e14;
+__m128i e15;
+__m128d e16;
+__m256 e17;
+__m128 e18;
+
+static void
+__attribute__((noinline))
+test (__m128 a1, __m256d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, __m256d);
+  e9 = va_arg (va_arglist, __m128);
+  e10 = va_arg (va_arglist, __m128i);
+  e11 = va_arg (va_arglist, int);
+  e12 = va_arg (va_arglist, double);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m256i);
+  e15 = va_arg (va_arglist, __m128i);
+  e16 = va_arg (va_arglist, __m128d);
+  e17 = va_arg (va_arglist, __m256);
+  e18 = va_arg (va_arglist, __m128);
+  va_end (va_arglist);
+}
+
+static void
+avx_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
+	n13, n14, n15, n16, n17, n18);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (__builtin_memcmp (&e10, &n10, sizeof (e10)) == 0);
+  assert (n11 == e11);
+  assert (n12 == e12);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+  assert (__builtin_memcmp (&e16, &n16, sizeof (e16)) == 0);
+  assert (__builtin_memcmp (&e17, &n17, sizeof (e17)) == 0);
+  assert (__builtin_memcmp (&e18, &n18, sizeof (e18)) == 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-6.c
new file mode 100644
index 000000000..5c645c41d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-6.c
@@ -0,0 +1,107 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-mavx" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "avx-check.h"
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+__m256d n2 = { -93.83, 893.318, 3994.3, -39484.0 };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+__m256d n8 = { -123.3, 2.3, 3.4, -10.03 };
+__m128 n9 = { -123.3, 2.3, 3.4, -10.03 };
+__m128i n10 = { 1233, -100 };
+int n11 = 407;
+double n12 = 304.9;
+__m128i n13 = { 233, -110 };
+__m256i n14 = { -1233, 23, 34, -1003 };
+__m128i n15 = { -393, -180 };
+__m128d n16 = { 73.0, 63.18 };
+__m256 n17 = { -183.3, -22.3, 13.9, -119.3, 483.1, 122.3, -33.4, -9.37 };
+__m128 n18 = { -183.3, 22.3, 13.4, -19.03 };
+
+__m128 e1;
+__m256d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+__m256d e8;
+__m128 e9;
+__m128i e10;
+int e11;
+double e12;
+__m128i e13;
+__m256i e14;
+__m128i e15;
+__m128d e16;
+__m256 e17;
+__m128 e18;
+
+static void
+__attribute__((noinline))
+foo (va_list va_arglist)
+{
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, __m256d);
+  e9 = va_arg (va_arglist, __m128);
+  e10 = va_arg (va_arglist, __m128i);
+  e11 = va_arg (va_arglist, int);
+  e12 = va_arg (va_arglist, double);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m256i);
+  e15 = va_arg (va_arglist, __m128i);
+  e16 = va_arg (va_arglist, __m128d);
+  e17 = va_arg (va_arglist, __m256);
+  e18 = va_arg (va_arglist, __m128);
+  va_end (va_arglist);
+}
+
+static void
+__attribute__((noinline))
+test (__m128 a1, __m256d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  foo (va_arglist);
+  va_end (va_arglist);
+}
+
+static void
+avx_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
+	n13, n14, n15, n16, n17, n18);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (__builtin_memcmp (&e10, &n10, sizeof (e10)) == 0);
+  assert (n11 == e11);
+  assert (n12 == e12);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+  assert (__builtin_memcmp (&e16, &n16, sizeof (e16)) == 0);
+  assert (__builtin_memcmp (&e17, &n17, sizeof (e17)) == 0);
+  assert (__builtin_memcmp (&e18, &n18, sizeof (e18)) == 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-7.c
new file mode 100644
index 000000000..bebf60924
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-7.c
@@ -0,0 +1,90 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "sse2-check.h"
+
+struct m128
+{
+  __m128 v;
+};
+
+struct m128 n1 = { { -283.3, -23.3, 213.4, 1119.03 } };
+__m128d n2 = { -93.83, 893.318 };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+struct m128 n8 = { { -123.3, 2.3, 3.4, -10.03 } };
+__m128i n9 = { 1233, -100 };
+int n10 = 407;
+double n11 = 304.9;
+__m128i n12 = { 233, -110 };
+__m128i n13 = { -393, -180 };
+__m128d n14 = { 73.0, 63.18 };
+struct m128 n15 = { { -183.3, 22.3, 13.4, -19.03 } };
+
+struct m128 e1;
+__m128d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+struct m128 e8;
+__m128i e9;
+int e10;
+double e11;
+__m128i e12;
+__m128i e13;
+__m128d e14;
+struct m128 e15;
+
+static void
+__attribute__((noinline))
+test (struct m128 a1, __m128d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, struct m128);
+  e9 = va_arg (va_arglist, __m128i);
+  e10 = va_arg (va_arglist, int);
+  e11 = va_arg (va_arglist, double);
+  e12 = va_arg (va_arglist, __m128i);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m128d);
+  e15 = va_arg (va_arglist, struct m128);
+  va_end (va_arglist);
+}
+
+static void
+sse2_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (n10 == e10);
+  assert (n11 == e11);
+  assert (__builtin_memcmp (&e12, &n12, sizeof (e12)) == 0);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-8.c
new file mode 100644
index 000000000..bf6d3b523
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-8.c
@@ -0,0 +1,97 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "sse2-check.h"
+
+struct m128
+{
+  __m128 v;
+};
+
+struct m128 n1 = { { -283.3, -23.3, 213.4, 1119.03 } };
+__m128d n2 = { -93.83, 893.318 };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+struct m128 n8 = { { -123.3, 2.3, 3.4, -10.03 } };
+__m128i n9 = { 1233, -100 };
+int n10 = 407;
+double n11 = 304.9;
+__m128i n12 = { 233, -110 };
+__m128i n13 = { -393, -180 };
+__m128d n14 = { 73.0, 63.18 };
+struct m128 n15 = { { -183.3, 22.3, 13.4, -19.03 } };
+
+struct m128 e1;
+__m128d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+struct m128 e8;
+__m128i e9;
+int e10;
+double e11;
+__m128i e12;
+__m128i e13;
+__m128d e14;
+struct m128 e15;
+
+static void
+__attribute__((noinline))
+foo (va_list va_arglist)
+{
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, struct m128);
+  e9 = va_arg (va_arglist, __m128i);
+  e10 = va_arg (va_arglist, int);
+  e11 = va_arg (va_arglist, double);
+  e12 = va_arg (va_arglist, __m128i);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m128d);
+  e15 = va_arg (va_arglist, struct m128);
+}
+
+static void
+__attribute__((noinline))
+test (struct m128 a1, __m128d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  foo (va_arglist);
+  va_end (va_arglist);
+}
+
+static void
+sse2_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (n10 == e10);
+  assert (n11 == e11);
+  assert (__builtin_memcmp (&e12, &n12, sizeof (e12)) == 0);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-9.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-9.c
new file mode 100644
index 000000000..581abb178
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vararg-9.c
@@ -0,0 +1,104 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-mavx" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "avx-check.h"
+
+struct m256d
+{
+  __m256d  v;
+};
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+struct m256d n2 = { { -93.83, 893.318, 3994.3, -39484.0 } };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+struct m256d n8 = { { -123.3, 2.3, 3.4, -10.03 } };
+__m128 n9 = { -123.3, 2.3, 3.4, -10.03 };
+__m128i n10 = { 1233, -100 };
+int n11 = 407;
+double n12 = 304.9;
+__m128i n13 = { 233, -110 };
+__m256i n14 = { -1233, 23, 34, -1003 };
+__m128i n15 = { -393, -180 };
+__m128d n16 = { 73.0, 63.18 };
+__m256 n17 = { -183.3, -22.3, 13.9, -119.3, 483.1, 122.3, -33.4, -9.37 };
+__m128 n18 = { -183.3, 22.3, 13.4, -19.03 };
+
+__m128 e1;
+struct m256d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+struct m256d e8;
+__m128 e9;
+__m128i e10;
+int e11;
+double e12;
+__m128i e13;
+__m256i e14;
+__m128i e15;
+__m128d e16;
+__m256 e17;
+__m128 e18;
+
+static void
+__attribute__((noinline))
+test (__m128 a1, struct m256d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, struct m256d);
+  e9 = va_arg (va_arglist, __m128);
+  e10 = va_arg (va_arglist, __m128i);
+  e11 = va_arg (va_arglist, int);
+  e12 = va_arg (va_arglist, double);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m256i);
+  e15 = va_arg (va_arglist, __m128i);
+  e16 = va_arg (va_arglist, __m128d);
+  e17 = va_arg (va_arglist, __m256);
+  e18 = va_arg (va_arglist, __m128);
+  va_end (va_arglist);
+}
+
+static void
+avx_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
+	n13, n14, n15, n16, n17, n18);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (__builtin_memcmp (&e10, &n10, sizeof (e10)) == 0);
+  assert (n11 == e11);
+  assert (n12 == e12);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+  assert (__builtin_memcmp (&e16, &n16, sizeof (e16)) == 0);
+  assert (__builtin_memcmp (&e17, &n17, sizeof (e17)) == 0);
+  assert (__builtin_memcmp (&e18, &n18, sizeof (e18)) == 0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-1.c
new file mode 100644
index 000000000..8553eb05e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+#define vector __attribute__((vector_size(16)))
+
+float a;
+vector float f1(void) { return (vector float){ a, 0.0, 0.0, 0.0}; }
+vector float f2(void) { return (vector float){ 0.0, a, 0.0, 0.0}; }
+vector float f3(void) { return (vector float){ 0.0, 0.0, a, 0.0}; }
+vector float f4(void) { return (vector float){ 0.0, 0.0, 0.0, a}; }
+/* { dg-final { scan-assembler-not "movaps" } } */
+/* { dg-final { scan-assembler-not "xor" } } */
+/* { dg-final { scan-assembler-not "%mm" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-2.c
new file mode 100644
index 000000000..d6c715fd4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+#define vector __attribute__((vector_size(16)))
+
+int a;
+vector int f1(void) { return (vector int){ a, 0, 0, 0}; }
+vector int f2(void) { return (vector int){ 0, a, 0, 0}; }
+vector int f3(void) { return (vector int){ 0, 0, a, 0}; }
+vector int f4(void) { return (vector int){ 0, 0, 0, a}; }
+/* { dg-final { scan-assembler-not "movaps" } } */
+/* { dg-final { scan-assembler-not "xor" } } */
+/* { dg-final { scan-assembler-not "%mm" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-3.c
new file mode 100644
index 000000000..053b566fb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+#define vector __attribute__((vector_size(16)))
+
+char a;
+vector char f(void) { return (vector char){ a, a, a, a, a, a, a, a,
+					    a, a, a, a, a, a, a, a }; }
+/* { dg-final { scan-assembler-not "sall" } } */
+/* { dg-final { scan-assembler-not "%mm" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-4.c
new file mode 100644
index 000000000..773a31600
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-4.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+#define vector __attribute__((vector_size(16)))
+
+short a;
+vector short f(void) { return (vector short){ a, a, a, a, a, a, a, a }; }
+/* { dg-final { scan-assembler-not "sall" } } */
+/* { dg-final { scan-assembler-not "%mm" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-5.c
new file mode 100644
index 000000000..576488973
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-5.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+#define vector __attribute__((vector_size(16)))
+
+float a, b;
+vector float f1(void) { return (vector float){ 0.0, 0.0, a, a}; }
+vector float f2(void) { return (vector float){ a, a, 0.0, 0.0}; }
+vector float f3(void) { return (vector float){ 0.0, a, 0.0, a}; }
+vector float f4(void) { return (vector float){ a, 0.0, a, 0.0}; }
+
+vector float f5(void) { return (vector float){ 1.0, 1.0, a, a}; }
+vector float f6(void) { return (vector float){ a, a, 1.0, 1.0}; }
+vector float f7(void) { return (vector float){ 1.0, a, 1.0, a}; }
+vector float f8(void) { return (vector float){ a, 1.0, a, 1.0}; }
+
+vector float fa(void) { return (vector float){ 1.0, 1.0, 0.0, 0.0}; }
+vector float fb(void) { return (vector float){ 1.0, 0.0, 1.0, 0.0}; }
+vector float fc(void) { return (vector float){ 0.0, 1.0, 0.0, 1.0}; }
+
+vector float fA(void) { return (vector float){ a, a, b, b}; }
+vector float fB(void) { return (vector float){ a, b, a, b}; }
+vector float fC(void) { return (vector float){ a, a, a, a}; }
+
+/* { dg-final { scan-assembler-not "%mm" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-6.c
new file mode 100644
index 000000000..ba58f1260
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vecinit-6.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+#define vector __attribute__((vector_size(16)))
+
+int a, b;
+vector int f1(void) { return (vector int){ 0, 0, a, a}; }
+vector int f2(void) { return (vector int){ a, a, 0, 0}; }
+vector int f3(void) { return (vector int){ 0, a, 0, a}; }
+vector int f4(void) { return (vector int){ a, 0, a, 0}; }
+
+vector int f5(void) { return (vector int){ 1, 1, a, a}; }
+vector int f6(void) { return (vector int){ a, a, 1, 1}; }
+vector int f7(void) { return (vector int){ 1, a, 1, a}; }
+vector int f8(void) { return (vector int){ a, 1, a, 1}; }
+
+vector int fa(void) { return (vector int){ 1, 1, 0, 0}; }
+vector int fb(void) { return (vector int){ 1, 0, 1, 0}; }
+vector int fc(void) { return (vector int){ 0, 1, 0, 1}; }
+
+vector int fA(void) { return (vector int){ a, a, b, b}; }
+vector int fB(void) { return (vector int){ a, b, a, b}; }
+vector int fC(void) { return (vector int){ a, a, a, a}; }
+
+/* { dg-final { scan-assembler-not "%mm" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vect-args.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vect-args.c
new file mode 100644
index 000000000..94b602d91
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vect-args.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-w" } */
+
+/* SSE1 and SSE2 modes.  */
+typedef unsigned char V16QImode __attribute__((vector_size(16)));
+typedef unsigned short V8HImode __attribute__((vector_size(16)));
+typedef unsigned int V4SImode __attribute__((vector_size(16)));
+typedef unsigned long long V2DImode __attribute__((vector_size(16)));
+typedef float V4SFmode __attribute__((vector_size(16)));
+typedef double V2DFmode __attribute__((vector_size(16)));
+
+/* MMX and 3DNOW modes.  */
+typedef unsigned char V8QImode __attribute__((vector_size(8)));
+typedef unsigned short V4HImode __attribute__((vector_size(8)));
+typedef unsigned int V2SImode __attribute__((vector_size(8)));
+typedef float V2SFmode __attribute__((vector_size(8)));
+
+/* Test argument loading and unloading of each.  */
+#define TEST(TYPE)					\
+extern TYPE data_##TYPE;				\
+void r_##TYPE (TYPE x) { data_##TYPE = x; }		\
+void s_##TYPE (void) { r_##TYPE (data_##TYPE); }
+
+TEST(V16QImode)
+TEST(V8HImode)
+TEST(V4SImode)
+TEST(V2DImode)
+TEST(V4SFmode)
+TEST(V2DFmode)
+TEST(V8QImode)
+TEST(V4HImode)
+TEST(V2SImode)
+TEST(V2SFmode)
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize1.c
new file mode 100644
index 000000000..7a5023aa9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize1.c
@@ -0,0 +1,19 @@
+/* PR middle-end/28915 */
+/* { dg-options "-msse -O2 -ftree-vectorize -fdump-tree-vect" } */
+
+extern char lanip[3][40];
+typedef struct
+{
+  char *t[8];
+}tx_typ;
+
+int set_names (void)
+{
+  static tx_typ tt1;
+  int ln;
+  for (ln = 0; ln < 8; ln++)
+      tt1.t[ln] = lanip[1];
+}
+
+/* { dg-final { scan-tree-dump "vect_cst" "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize2.c
new file mode 100644
index 000000000..419648719
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize2.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2 -mfpmath=sse" } */
+
+double a[256];
+int b[256];
+unsigned short c[256];
+
+extern long lrint (double);
+
+void foo(void)
+{
+  int i;
+
+  for (i=0; i<256; ++i)
+    b[i] = lrint (a[i]);
+}
+
+void bar(void)
+{
+  int i;
+
+  for (i=0; i<256; ++i)
+    {
+      b[i] = lrint (a[i]);
+      c[i] += c[i];
+    }
+}
+
+/* { dg-final { scan-assembler "cvtpd2dq" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize3.c
new file mode 100644
index 000000000..2947acbaf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize3.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2 -mfpmath=sse" } */
+
+float a[256];
+int b[256];
+unsigned short c[256];
+
+extern long lrintf (float);
+
+void foo(void)
+{
+  int i;
+
+  for (i=0; i<256; ++i)
+    b[i] = lrintf (a[i]);
+}
+
+void bar(void)
+{
+  int i;
+
+  for (i=0; i<256; ++i)
+    {
+      b[i] = lrintf (a[i]);
+      c[i] += c[i];
+    }
+}
+
+/* { dg-final { scan-assembler "cvtps2dq" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize4.c
new file mode 100644
index 000000000..f3d605e22
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize4.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2 --param ggc-min-expand=0 --param ggc-min-heapsize=0" } */
+/* This test, tests two thing, we vectorize square root and also we don't crash due to a GC issue.  */
+
+
+extern double sqrt (double __x);
+calc_freq (int *dest)
+{
+  float tmp_out[257];
+  int i;
+  for (i = 0; i < 256; i++)
+    dest[i] = sqrt (tmp_out[i]);
+}
+
+/* { dg-final { scan-assembler "sqrtpd" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize5.c
new file mode 100644
index 000000000..389424045
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize5.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -ftree-vectorize -mveclibabi=acml -ffast-math" } */
+
+double x[256];
+
+extern double sin(double);
+
+void foo(void)
+{
+  int i;
+
+  for (i=0; i<256; ++i)
+    x[i] = sin(x[i]);
+}
+
+/* { dg-final { scan-assembler "__vrd2_sin" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize6.c
new file mode 100644
index 000000000..78ec53d15
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/vectorize6.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -ftree-vectorize -mveclibabi=svml -ffast-math" } */
+
+double x[256];
+
+extern double sin(double);
+
+void foo(void)
+{
+  int i;
+
+  for (i=0; i<256; ++i)
+    x[i] = sin(x[i]);
+}
+
+/* { dg-final { scan-assembler "vmldSin2" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/volatile-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/volatile-1.c
new file mode 100644
index 000000000..714314cee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/volatile-1.c
@@ -0,0 +1,14 @@
+/* PR optimization/11381 */
+/* Originator: <tobias@ringstrom.mine.nu> */
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+/* Verify that the comparison is not optimized away. */
+
+void foo(volatile unsigned int *vaddr)
+{
+  while (*vaddr != *vaddr)
+    ;
+}
+
+/* { dg-final { scan-assembler "cmp" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/xchg-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/xchg-1.c
new file mode 100644
index 000000000..e81fe49cd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/xchg-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8" } */
+
+unsigned short good(unsigned short a)
+{
+       return (a >> 8 | a << 8);
+}
+
+/* { dg-final { scan-assembler "rol" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/xchg-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/xchg-2.c
new file mode 100644
index 000000000..f00fb0f21
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/xchg-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+unsigned short good(unsigned short a)
+{
+       return (a >> 8 | a << 8);
+}
+
+/* { dg-final { scan-assembler "xchgb" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/xorps-sse.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/xorps-sse.c
new file mode 100644
index 000000000..e9c0a2e73
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/xorps-sse.c
@@ -0,0 +1,14 @@
+/* Test that we generate xorps instruction when pxor is not available.  */
+/* { dg-do compile } */
+/* { dg-options "-O -msse -mno-sse2" } */
+/* { dg-final { scan-assembler "xorps\[ \t\]" } } */
+
+#define vector __attribute__ ((vector_size (16)))
+
+vector int i(vector int f)
+{
+  vector int g = { 0x80000000, 0, 0x80000000, 0 };
+  vector int f_int = (vector int) f;
+  return (f_int ^ g);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/xorps-sse2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/xorps-sse2.c
new file mode 100644
index 000000000..3c268b4cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/xorps-sse2.c
@@ -0,0 +1,15 @@
+/* Test that we generate xorps when the result is used in FP math.  */
+/* { dg-do compile } */
+/* { dg-options "-O -msse2 -mno-sse3" } */
+/* { dg-final { scan-assembler "xorps\[ \t\]" { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-not "pxor" { xfail *-*-* } } } */
+
+#define vector __attribute__ ((vector_size (16)))
+
+vector float i(vector float f, vector float h)
+{
+  vector int g = { 0x80000000, 0, 0x80000000, 0 };
+  vector int f_int = (vector int) f;
+  return ((vector float) (f_int ^ g)) + h;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/i386/xorps.c b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/xorps.c
new file mode 100644
index 000000000..6803a4d89
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/i386/xorps.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -msse2" } */
+
+typedef float __m128 __attribute__ ((vector_size (16)));
+
+static __inline __m128
+_mm_mul_ps (__m128 __A, __m128 __B)
+{
+  return __builtin_ia32_mulps (__A, __B);
+}
+
+static __inline __m128
+_mm_sub_ps (__m128 __A, __m128 __B)
+{
+  return  __builtin_ia32_subps (__A, __B);
+}
+
+__m128 POW_FUNC (__m128 x, __m128 y)
+{
+    __m128 xmm0 = x, xmm1 = y, xmm2;
+
+    xmm0 = __builtin_ia32_xorps (xmm1, xmm1);
+
+    xmm0 = _mm_mul_ps (xmm0, xmm1);
+
+    xmm0 = _mm_sub_ps (xmm0, xmm1);
+
+    xmm0 = _mm_mul_ps (xmm0, xmm1);
+
+    return xmm0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20010423-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20010423-1.c
new file mode 100644
index 000000000..4cec79370
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20010423-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int __sync_fetch_and_add_si (int *, int);
+
+inline unsigned int
+bar (volatile unsigned int *mem, unsigned int val)
+{
+  return __sync_fetch_and_add_si((int *)mem, (int)val);
+}
+
+volatile unsigned int x;
+
+void foo (unsigned short *a)
+{
+  *a = bar (&x, 1) + 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20020313-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20020313-1.c
new file mode 100644
index 000000000..bc134febf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20020313-1.c
@@ -0,0 +1,72 @@
+/* PR 5312 
+   The problem here is that the ia64 scheduler saw a sequence of L L M type
+   insns, and messed up its internal state on which slot it was issuing
+   to, and aborted.  */
+
+/* { dg-do compile } */
+/* In ILP32 mode, we get warnings about large integer constants.
+   Those cause spurious FAILs.  */
+/* { dg-options "-w -O2 -mconstant-gp" } */
+
+typedef unsigned long __u64;
+typedef unsigned int __u32;
+typedef struct { } spinlock_t;
+struct cpuinfo_ia64 {
+        union {
+                struct {
+                        __u32 irq_count;
+                        __u32 bh_count;
+                } f;
+                __u64 irq_and_bh_counts;
+        } irq_stat;
+        __u32 softirq_pending;
+} __attribute__ ((aligned ((1UL << 14)))) ;
+enum
+{
+        TCA_UNSPEC,
+        TCA_KIND,
+        TCA_OPTIONS,
+        TCA_STATS,
+        TCA_XSTATS,
+        TCA_RATE,
+};
+struct tc_stats
+{
+        __u64 bytes;
+        __u32 packets;
+        __u32 drops;
+        __u32 overlimits;
+        __u32 bps;
+        __u32 pps;
+        __u32 qlen;
+        __u32 backlog;
+        spinlock_t *lock;
+};
+struct sk_buff {
+        unsigned int data_len;
+        unsigned char *tail;
+        unsigned char *end;
+};
+static inline int skb_is_nonlinear(const struct sk_buff *skb)
+{
+        return skb->data_len;
+}
+static inline int skb_tailroom(const struct sk_buff *skb)
+{
+        return skb_is_nonlinear(skb) ? 0 : skb->end-skb->tail;
+}
+struct rtattr
+{
+        unsigned short rta_len;
+        unsigned short rta_type;
+};
+int qdisc_copy_stats(struct sk_buff *skb, struct tc_stats *st)
+{
+        do { do { (((struct cpuinfo_ia64 *) (0xa000000000000000 + 2*(1UL << 14)))->irq_stat.f.bh_count)++; __asm__ __volatile__("": : :"memory"); } while (0); (void)(st->lock); } while (0);
+        ({ if (skb_tailroom(skb) < (int)( (((( ((sizeof(struct rtattr))+4 -1) & ~(4 -1) ) + ((char*)&st->lock - (char*)st)))+4 -1) & ~(4 -1) )) goto rtattr_failure; __rta_fill(skb, TCA_STATS, (char*)&st->lock - (char*)st, st); });
+        do { do { } while(0); do { do { __asm__ __volatile__("": : :"memory"); (((struct cpuinfo_ia64 *) (0xa000000000000000 + 2*(1UL << 14)))->irq_stat.f.bh_count)--; } while (0); if (__builtin_expect((((struct cpuinfo_ia64 *) (0xa000000000000000 + 2*(1UL << 14)))->softirq_pending), 0) && (((struct cpuinfo_ia64 *) (0xa000000000000000 + 2*(1UL << 14)))->irq_stat.f.bh_count) == 0) do_softirq(); } while (0); } while (0);
+        return 0;
+rtattr_failure:
+        do { do { } while(0); do { do { __asm__ __volatile__("": : :"memory"); (((struct cpuinfo_ia64 *) (0xa000000000000000 + 2*(1UL << 14)))->irq_stat.f.bh_count)--; } while (0); if (__builtin_expect((((struct cpuinfo_ia64 *) (0xa000000000000000 + 2*(1UL << 14)))->softirq_pending), 0) && (((struct cpuinfo_ia64 *) (0xa000000000000000 + 2*(1UL << 14)))->irq_stat.f.bh_count) == 0) do_softirq(); } while (0); } while (0);
+        return -1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20020326-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20020326-1.c
new file mode 100644
index 000000000..16da750ba
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20020326-1.c
@@ -0,0 +1,11 @@
+/* PR target/6054 */
+/* { dg-do compile } */
+/* { dg-options "-O -mconstant-gp" } */
+/* { dg-final { scan-assembler "mov r1 =" } } */
+
+extern void direct (void);
+void foo(void (*indirect) (void))
+{
+  indirect ();
+  direct ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20030225-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20030225-2.c
new file mode 100644
index 000000000..278180777
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20030225-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+extern void abort (void);
+extern void exit (int);
+
+int __attribute__((noinline, const))
+ret4 (float value)
+{
+  return 4;
+}
+
+int __attribute__((noinline, const))
+ret0 (float value)
+{
+  return 0;
+}
+
+float __attribute__((noinline))
+test (float x, float y)
+{
+  int clsx = ret4 (x);
+  int clsy = ret0 (y);
+
+  if (clsx == 0 || clsy == 0
+      || (y < 0 && clsx == 1 && clsy == 1))
+    return x - y;
+
+  return x < y ? 0 : x - y;
+}
+
+float a = 0.0, b;
+
+int main (void)
+{
+  unsigned long e;
+  b = a / a;
+  __asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r" (e));
+  e &= ~0x7e000UL;
+  __asm__ __volatile__ ("mov.m ar.fpsr=%0" :: "r" (e) : "memory");
+  a = test (0, b);
+  __asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r" (e));
+  if (e & 0x2000)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20030405-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20030405-1.c
new file mode 100644
index 000000000..510638ce5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20030405-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+foo (int x, int y)
+{
+  if (y == 0)
+    {
+      register long r8 asm ("r8");
+      register long r15 asm ("r15") = 1;
+      long retval;
+      __asm __volatile ("foo" : "=r" (r8), "=r" (r15) : "1" (r15));
+      retval = r8;
+      y = retval;
+    }
+
+  {
+    register long r8 asm ("r8");
+    register long r15 asm ("r15") = 2;
+    long retval;
+    register long _out1 asm ("out1") = x;
+    register long _out0 asm ("out0") = y;
+    __asm __volatile ("foo"
+		      : "=r" (r8), "=r" (r15) , "=r" (_out0), "=r" (_out1)
+		      : "1" (r15) , "2" (_out0), "3" (_out1));
+    retval = r8;
+    return retval;
+  }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20030811-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20030811-1.c
new file mode 100644
index 000000000..45f78b361
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20030811-1.c
@@ -0,0 +1,59 @@
+/* Origin: PR target/11693 from Andreas Schwab <schwab@suse.de> */
+/* { dg-do compile } */
+/* { dg-options "-O2 -frename-registers" } */
+
+static inline unsigned long long
+foo (void)
+{
+  unsigned long long x;
+  __asm__ __volatile__ ("" : "=r" (x) :: "memory");
+  return x;
+}
+
+static inline void
+bar (unsigned long long x, unsigned long long y)
+{
+  __asm__ __volatile__ ("" :: "r"(x), "r"(y) : "memory");
+}
+
+static inline void
+baz (unsigned long long x, unsigned long long y, unsigned long long z,
+     unsigned long long p, unsigned long long q)
+{
+  __asm__ __volatile__ ("" :: "r" (q << 2) : "memory");
+  __asm__ __volatile__ ("" :: "r" (z) : "memory");
+  if (x & 0x1)
+    __asm__ __volatile__ ("" :: "r" (y), "r" (p) : "memory");
+  if (x & 0x2)
+    __asm__ __volatile__ ("" :: "r" (y), "r" (p) : "memory");
+}
+
+static inline unsigned long long
+ffz (unsigned long long x)
+{
+  unsigned long long r;
+  __asm__ ("" : "=r" (r) : "r" (x & (~x - 1)));
+  return r;
+}
+
+void die (const char *, ...) __attribute__ ((noreturn));
+
+void
+test (void *x)
+{
+  unsigned long long a, c;
+
+  a = foo ();
+  bar (0xc000000000000000LL, 0x660);
+  bar (0xa00000000000c000LL, 0x539);
+  baz (2, 1, 0xa000000000008000LL,
+       ({ unsigned long long b;
+	  b = ({ unsigned long long d; __asm__ ("" : "=r" (d) : "r" (x)); d; })
+	      + 0x10000000000661LL;
+	  b;
+	}),
+       14);
+  c = ffz (0x1fffffffffffffffLL);
+  if (c < 51 || c > 61)
+    die ("die", c - 1);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20040303-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20040303-1.c
new file mode 100644
index 000000000..60b5c528f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20040303-1.c
@@ -0,0 +1,20 @@
+/* Test floating point division on ia64.  There was a bug in the
+   max-throughput version of the inline division code.  Expecting an
+   exact value from a floating point expression is unwise but GCC
+   depends on it in allocno_compare.  */
+
+/* { dg-do run } */
+/* { dg-options "-minline-float-divide-max-throughput" } */
+
+extern void abort (void);
+
+volatile int i = 24;
+volatile int j = 30;
+volatile int k = 1;
+
+int main()
+{
+        int pri2 = (((double) i / j) * (10000 / 1000) * k);
+        if (pri2 != 8) abort();
+	return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20040709-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20040709-2.c
new file mode 100644
index 000000000..585ab06f0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20040709-2.c
@@ -0,0 +1,151 @@
+/* Check for ia64 data speculation failure with '-O2 -funroll-loops'.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -funroll-loops -Wno-overflow" } */
+
+extern void abort (void);
+extern void exit (int);
+
+unsigned int
+myrnd (void)
+{
+  static unsigned int s = 1388815473;
+  s *= 1103515245;
+  s += 12345;
+  return (s / 65536) % 2048;
+}
+
+#define T(S)					\
+struct S s##S;					\
+struct S retme##S (struct S x)			\
+{						\
+  return x;					\
+}						\
+						\
+unsigned int fn1##S (unsigned int x)		\
+{						\
+  struct S y = s##S;				\
+  y.k += x;					\
+  y = retme##S (y);				\
+  return y.k;					\
+}						\
+						\
+unsigned int fn2##S (unsigned int x)		\
+{						\
+  struct S y = s##S;				\
+  y.k += x;					\
+  y.k %= 15;					\
+  return y.k;					\
+}						\
+						\
+unsigned int retit##S (void)			\
+{						\
+  return s##S.k;				\
+}						\
+						\
+unsigned int fn3##S (unsigned int x)		\
+{						\
+  s##S.k += x;					\
+  return retit##S ();				\
+}						\
+						\
+void test##S (void)				\
+{						\
+  int i;					\
+  unsigned int mask, v, a, r;			\
+  struct S x;					\
+  char *p = (char *) &s##S;			\
+  for (i = 0; i < sizeof (s##S); ++i)		\
+    *p++ = myrnd ();				\
+  if (__builtin_classify_type (s##S.l) == 8)	\
+    s##S.l = 5.25;				\
+  s##S.k = -1;					\
+  mask = s##S.k;				\
+  v = myrnd ();					\
+  a = myrnd ();					\
+  s##S.k = v;					\
+  x = s##S;					\
+  r = fn1##S (a);				\
+  if (x.i != s##S.i || x.j != s##S.j		\
+      || x.k != s##S.k || x.l != s##S.l		\
+      || ((v + a) & mask) != r)			\
+    abort ();					\
+  v = myrnd ();					\
+  a = myrnd ();					\
+  s##S.k = v;					\
+  x = s##S;					\
+  r = fn2##S (a);				\
+  if (x.i != s##S.i || x.j != s##S.j		\
+      || x.k != s##S.k || x.l != s##S.l		\
+      || ((((v + a) & mask) % 15) & mask) != r)	\
+    abort ();					\
+  v = myrnd ();					\
+  a = myrnd ();					\
+  s##S.k = v;					\
+  x = s##S;					\
+  r = fn3##S (a);				\
+  if (x.i != s##S.i || x.j != s##S.j		\
+      || s##S.k != r || x.l != s##S.l		\
+      || ((v + a) & mask) != r)			\
+    abort ();					\
+}
+
+#define pck __attribute__((packed))
+struct pck A { unsigned short i : 1, l : 1, j : 3, k : 11; }; T(A)
+struct pck B { unsigned short i : 4, j : 1, k : 11; unsigned int l; }; T(B)
+struct pck C { unsigned int l; unsigned short i : 4, j : 1, k : 11; }; T(C)
+struct pck D { unsigned long long l : 6, i : 6, j : 23, k : 29; }; T(D)
+struct pck E { unsigned long long l, i : 12, j : 23, k : 29; }; T(E)
+struct pck F { unsigned long long i : 12, j : 23, k : 29, l; }; T(F)
+struct pck G { unsigned short i : 1, j : 1, k : 6; unsigned long long l; }; T(G)
+struct pck H { unsigned short i : 6, j : 2, k : 8; unsigned long long l; }; T(H)
+struct pck I { unsigned short i : 1, j : 6, k : 1; unsigned long long l; }; T(I)
+struct pck J { unsigned short i : 1, j : 8, k : 7; unsigned short l; }; T(J)
+struct pck K { unsigned int k : 6, l : 1, j : 10, i : 15; }; T(K)
+struct pck L { unsigned int k : 6, j : 11, i : 15; unsigned int l; }; T(L)
+struct pck M { unsigned int l; unsigned short k : 6, j : 11, i : 15; }; T(M)
+struct pck N { unsigned long long l : 6, k : 6, j : 23, i : 29; }; T(N)
+struct pck O { unsigned long long l, k : 12, j : 23, i : 29; }; T(O)
+struct pck P { unsigned long long k : 12, j : 23, i : 29, l; }; T(P)
+struct pck Q { unsigned short k : 12, j : 1, i : 3; unsigned long long l; }; T(Q)
+struct pck R { unsigned short k : 2, j : 11, i : 3; unsigned long long l; }; T(R)
+struct pck S { unsigned short k : 1, j : 6, i : 9; unsigned long long l; }; T(S)
+struct pck T { unsigned short k : 1, j : 8, i : 7; unsigned short l; }; T(T)
+struct pck U { unsigned short j : 6, k : 1, i : 9; unsigned long long l; }; T(U)
+struct pck V { unsigned short j : 8, k : 1, i : 7; unsigned short l; }; T(V)
+struct pck W { long double l; unsigned int k : 12, j : 13, i : 7; }; T(W)
+struct pck X { unsigned int k : 12, j : 13, i : 7; long double l; }; T(X)
+struct pck Y { unsigned int k : 12, j : 11, i : 9; long double l; }; T(Y)
+struct pck Z { long double l; unsigned int j : 13, i : 7, k : 12; }; T(Z)
+
+int
+main (void)
+{
+  testA ();
+  testB ();
+  testC ();
+  testD ();
+  testE ();
+  testF ();
+  testG ();
+  testH ();
+  testI ();
+  testJ ();
+  testK ();
+  testL ();
+  testM ();
+  testN ();
+  testO ();
+  testP ();
+  testQ ();
+  testR ();
+  testS ();
+  testT ();
+  testU ();
+  testV ();
+  testW ();
+  testX ();
+  testY ();
+  testZ ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20080802-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20080802-1.c
new file mode 100644
index 000000000..b689a5d8d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20080802-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msched-control-spec" } */
+
+struct cpp_reader;
+
+extern const char * parse_include (struct cpp_reader *, int *m, void *);
+extern int _cpp_compare_file_date (struct cpp_reader *, const char *, int);
+
+void
+_cpp_init_internal_pragmas (struct cpp_reader *pfile)
+{
+  const char *fname;
+  int angle_brackets, ordering;
+
+  fname = parse_include (pfile, &angle_brackets, (void *) 0);
+  if (!fname)
+    return;
+  ordering = _cpp_compare_file_date (pfile, fname, angle_brackets);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20090324-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20090324-1.c
new file mode 100644
index 000000000..d9aff6a18
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/20090324-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fmodulo-sched" } */
+
+static char *place_region_bounds_x, *place_region_bounds_y;
+static void read_place () {
+  char msg[300];
+  update_screen (msg);
+}
+static void alloc_and_load_placement_structs () {
+  int i, j;
+  for (j=0;
+      j<100;
+      j++) {
+    place_region_bounds_x[i] = place_region_bounds_x[i-1];
+    place_region_bounds_y[i] = place_region_bounds_y[i-1];
+  }
+}
+void place_and_route () {
+  read_place ();
+  alloc_and_load_placement_structs ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/asm-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/asm-1.c
new file mode 100644
index 000000000..0acfee589
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/asm-1.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-options } */
+
+extern void abort (void);
+
+/* Test that "=S" properly avoids the post-increment on the memory address.  */
+
+static void foo(int *x)
+{
+  long i;
+  for (i = 0; i < 100; ++i)
+    __asm__("st4 %0 = r0" : "=S"(x[i]));
+}
+
+int main()
+{
+  int array[100];
+  long i;
+
+  for (i = 0; i < 100; ++i)
+    array[i] = -1;
+
+  foo(array);
+
+  for (i = 0; i < 100; ++i)
+    if (array[i])
+      abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/builtin-bswap-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/builtin-bswap-1.c
new file mode 100644
index 000000000..381e3fe22
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/builtin-bswap-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "mux1" } } */
+
+long foo (long x)
+{
+  return __builtin_bswap64 (x);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/builtin-bswap-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/builtin-bswap-2.c
new file mode 100644
index 000000000..96f32c702
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/builtin-bswap-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "mux1" } } */
+
+int foo (int x)
+{
+  return __builtin_bswap32 (x);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/builtin-popcount-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/builtin-popcount-1.c
new file mode 100644
index 000000000..c9641d0e6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/builtin-popcount-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "popcnt" } } */
+
+int foo (int x)
+{
+  return __builtin_popcount (x);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/builtin-popcount-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/builtin-popcount-2.c
new file mode 100644
index 000000000..50ced72e7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/builtin-popcount-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "popcnt" } } */
+
+int foo (int x)
+{
+  return __builtin_popcount (x) == 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/float80-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/float80-1.c
new file mode 100644
index 000000000..38e9c870f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/float80-1.c
@@ -0,0 +1,12 @@
+/* Bug 14610 */
+/* { dg-do run } */
+
+extern void abort(void);
+volatile __float80 x = 30.0;
+
+int main(void)
+{
+  double d = x;
+  if (d != 30.0) abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/float80-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/float80-2.c
new file mode 100644
index 000000000..346daa7ba
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/float80-2.c
@@ -0,0 +1,13 @@
+/* Bug 14610 */
+/* { dg-do run } */
+/* { dg-options "-minline-int-divide-max-throughput" } */
+
+extern void abort(void);
+volatile int j = 30;
+
+int main(void)
+{
+  if (29 % j != 29) abort();
+  if (30 % j != 0)  abort();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/float80-varargs-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/float80-varargs-1.c
new file mode 100644
index 000000000..96524be6b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/float80-varargs-1.c
@@ -0,0 +1,33 @@
+/* Test for a bug with passing __float80 in varargs.  The __float80
+   value was wrongly passed, leading to an abort.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do run } */
+/* { dg-options "" } */
+
+#include <stdarg.h>
+
+extern void abort (void);
+extern void exit (int);
+
+__float80 s = 1.234L;
+__float80 d;
+
+void vf (int a0, ...);
+
+int
+main (void)
+{
+  vf (0, s);
+  if (d != s)
+    abort ();
+  exit (0);
+}
+
+void
+vf (int a0, ...)
+{
+  va_list ap;
+  va_start (ap, a0);
+  d = va_arg (ap, __float80);
+  va_end (ap);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/fpreg-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/fpreg-1.c
new file mode 100644
index 000000000..8c9e21d7c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/fpreg-1.c
@@ -0,0 +1,82 @@
+/* Test permitted and invalid uses of __fpreg.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+__float80 f80;
+double d;
+/* Default initialized __fpreg is OK.  */
+__fpreg fpreg, fpreg2;
+/* But explicitly zero-initialized is an invalid conversion.  */
+__fpreg fi = 0; /* { dg-error "invalid conversion to '__fpreg'" } */
+
+__fpreg f0 (__fpreg);
+int f1 (__float80);
+
+/* __fpreg in a structure is OK.  */
+struct s {
+  __float80 b;
+  __fpreg a;
+} x;
+
+void
+f (void)
+{
+  __fpreg *p;
+  /* Valid operations.  */
+  fpreg = fpreg2;
+  fpreg2 = (__fpreg) fpreg;
+  fpreg = f0 (fpreg2);
+  fpreg = +fpreg2;
+  p = &fpreg;
+  (void) fpreg;
+  fpreg = x.a;
+  fpreg2 = (struct s) { 0 }.a;
+  fpreg = (d ? fpreg : fpreg2);
+  d = sizeof (fpreg);
+  (void)(fpreg, fpreg);
+  /* Invalid operations.  */
+  ++fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  --fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg++; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg--; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = -fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = ~fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = !fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = *fpreg; /* { dg-error "invalid type argument" } */
+  if (fpreg) /* { dg-error "invalid operation on '__fpreg'" } */
+    return;
+  d = fpreg; /* { dg-error "invalid conversion from '__fpreg'" } */
+  d = (double) fpreg; /* { dg-error "invalid conversion from '__fpreg'" } */
+  fpreg = (__fpreg) d; /* { dg-error "invalid conversion to '__fpreg'" } */
+  fpreg = fpreg * fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = fpreg / fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = fpreg % fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = fpreg + fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = fpreg - fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = fpreg << fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = fpreg >> fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg < fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg > fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg <= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg >= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg == fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg != fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg & fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg ^ fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg | fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg && fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg || fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = (fpreg ? 1 : 2); /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = (d ? fpreg : d); /* { dg-error "invalid conversion to '__fpreg'" } */
+  fpreg *= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg /= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg %= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg += fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg -= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg <<= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg >>= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg &= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg ^= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg |= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/fpreg-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/fpreg-2.c
new file mode 100644
index 000000000..a21bd0fb2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/fpreg-2.c
@@ -0,0 +1,21 @@
+/* Test __fpreg ABI.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-options "" } */
+/* { dg-final { scan-assembler "ldf.fill" } } */
+/* { dg-final { scan-assembler "stf.spill" } } */
+
+__fpreg x;
+
+void f (void);
+
+void
+g (void)
+{
+  __fpreg b = x;
+  f ();
+  x = b;
+}
+
+char t1[(sizeof (__fpreg) == sizeof (__float80) ? 1 : -1)];
+char t2[(__alignof (__fpreg) == __alignof (__float80) ? 1 : -1)];
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/fptr-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/fptr-1.c
new file mode 100644
index 000000000..8dc2efa29
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/fptr-1.c
@@ -0,0 +1,37 @@
+/* { dg-do run { target ia64-*-linux* } } */
+/* { dg-options "-O2" } */
+
+/* Test function descriptor access.  */
+
+extern unsigned long *_GLOBAL_OFFSET_TABLE_;
+extern void abort(void);
+
+struct ia64_fdesc
+{
+  unsigned long func;
+  unsigned long gp;
+};
+
+void
+os_boot_rendez (void)
+{
+}
+
+static int
+check (unsigned long gp)
+{
+  return gp != (unsigned long) &_GLOBAL_OFFSET_TABLE_;
+}
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int res = 0;
+
+  for (i = 0; i < 1; i++)
+    res += check (((struct ia64_fdesc *) os_boot_rendez)->gp);
+  if (res)
+    abort ();
+  return res;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/got-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/got-1.c
new file mode 100644
index 000000000..7a12ebd02
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/got-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fPIC" } */
+
+/* { dg-final { scan-assembler "@ltoffx\\(object#\\)" } } */
+/* { dg-final { scan-assembler "@ltoffx\\(object#\[-+\]16384\\)" } } */
+/* { dg-final { scan-assembler-not "@ltoffx\\(object#\[-+\]1\\)" } } */
+/* { dg-final { scan-assembler-not "@ltoffx\\(object#\[-+\]8191\\)" } } */
+/* { dg-final { scan-assembler-not "@ltoffx\\(object#\[-+\]8192\\)" } } */
+/* { dg-final { scan-assembler-not "@ltoffx\\(object#\[-+\]8193\\)" } } */
+/* { dg-final { scan-assembler-not "@ltoffx\\(object#\[-+\]16383\\)" } } */
+/* { dg-final { scan-assembler-not "@ltoffx\\(object#\[-+\]16385\\)" } } */
+
+/* must not be in sdata */
+extern char object[];
+
+#define r(n) char *r_##n (void) { return &object[n]; }
+#define R(n) char *R_##n (void) { return &object[-n]; }
+
+#define t(n) r(n) R(n)
+
+t(0) t(1)
+t(8191) t(8192) t(8193)
+t(16383) t(16384) t(16385)
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/ia64.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/ia64.exp
new file mode 100644
index 000000000..2d917fa9a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/ia64.exp
@@ -0,0 +1,41 @@
+#   Copyright (C) 1997, 2007, 2007 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an IA-64 target.
+if ![istarget ia64*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/postinc-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/postinc-1.c
new file mode 100644
index 000000000..93c30d872
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/postinc-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-options "-O2 -mlp64" { target ia64-*-hpux* } } */
+
+void copy_loop_ldouble (void *xdest,
+                        const void *xsrc,
+                        long roff,
+                        long soff,
+                        long len,
+                        long shift)
+{ __float128 *dest = xdest;
+  const long double *src;
+  long i;
+  roff /= sizeof (__float128);
+  soff /= sizeof (__float128);
+  src = xsrc;
+  src += shift * soff;
+  for (i = 0; i < len - shift; ++i) {
+        *dest = *src;
+        dest += roff;
+        src += soff;
+  }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/pr29682.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/pr29682.c
new file mode 100644
index 000000000..ecca32392
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/pr29682.c
@@ -0,0 +1,51 @@
+/* { dg-do compile { target ia64-*-* } } */
+/* { dg-options "-O3 -msched-control-spec" } */
+typedef long unsigned int size_t;
+typedef unsigned char uint8_t;
+typedef unsigned int uint32_t;
+typedef uint8_t byte;
+typedef enum pgpArmor_e
+{
+  PGPARMOR_ERR_CRC_CHECK = -7, PGPARMOR_ERR_BODY_DECODE =
+    -3, PGPARMOR_ERR_UNKNOWN_ARMOR_TYPE = -2, PGPARMOR_ERR_NO_BEGIN_PGP =
+    -1, PGPARMOR_NONE = 0, PGPARMOR_MESSAGE = 1, PGPARMOR_PUBKEY =
+    5, PGPARMOR_PRIVKEY = 6, PGPARMOR_SECKEY = 7
+}
+pgpArmor;
+pgpCRC (const byte * octets, size_t len)
+{
+  unsigned int crc = 0xb704ce;
+  int i;
+  while (len--)
+    {
+      for (i = 0; i < 8; i++)
+	{
+	  crc <<= 1;
+	  if (crc & 0x1000000)
+	    crc ^= 0x1864cfb;
+	}
+    }
+}
+pgpReadPkts (const char *fn, const byte ** pkt, size_t * pktlen)
+{
+  const byte *b = ((void *) 0);
+  const char *enc = ((void *) 0);
+  byte *dec;
+  size_t declen;
+  uint32_t crcpkt, crc;
+  int pstate = 0;
+  pgpArmor ec = PGPARMOR_ERR_NO_BEGIN_PGP;
+    {
+      switch (pstate)
+	{
+	case 0:
+	  if (b64decode (enc, (void **) &dec, &declen) != 0)
+	    {
+	      goto exit;
+	    }
+	  crc = pgpCRC (dec, declen);
+	}
+    }
+exit:if (ec > PGPARMOR_NONE && pkt)
+    *pkt = b;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/pr42542-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/pr42542-1.c
new file mode 100644
index 000000000..9ce66f494
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/pr42542-1.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-options "-O1 -ftree-vectorize" } */
+
+unsigned int v1[] __attribute__ ((aligned(16))) =
+{
+  0x80000000, 1, 0xa0000000, 2,
+  3, 0xd0000000, 0xf0000000, 0xe0000000
+};
+unsigned int v2[] __attribute__ ((aligned(16))) =
+{
+  4, 0xb0000000, 5, 0xc0000000,
+  0xd0000000, 6, 7, 8
+};
+
+unsigned int max[] =
+{
+  0x80000000, 0xb0000000, 0xa0000000, 0xc0000000,
+  0xd0000000, 0xd0000000, 0xf0000000, 0xe0000000
+};
+
+unsigned int min[] =
+{
+  4, 1, 5, 2,
+  3, 6, 7, 8
+};
+
+unsigned int res[8] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+int main (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 8; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 8; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/pr42542-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/pr42542-2.c
new file mode 100644
index 000000000..d41eef383
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/pr42542-2.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-options "-O1 -ftree-vectorize" } */
+
+unsigned short v1[] __attribute__ ((aligned(16))) =
+{
+  0x8000, 0x9000, 1, 10, 0xa000, 0xb000, 2, 20,
+  3, 30, 0xd000, 0xe000, 0xf000, 0xe000, 25, 30
+};
+unsigned short v2[] __attribute__ ((aligned(16))) =
+{
+  4, 40, 0xb000, 0x8000, 5, 50, 0xc000, 0xf000,
+  0xd000, 0xa000, 6, 65, 7, 75, 0xe000, 0xc000
+};
+
+unsigned short max[] =
+{
+  0x8000, 0x9000, 0xb000, 0x8000, 0xa000, 0xb000, 0xc000, 0xf000,
+  0xd000, 0xa000, 0xd000, 0xe000, 0xf000, 0xe000, 0xe000, 0xc000
+};
+
+unsigned short min[] =
+{
+  4, 40, 1, 10, 5, 50, 2, 20,
+  3, 30, 6, 65, 7, 75, 25, 30
+};
+
+unsigned short res[16] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+int main (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 16; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 16; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/pr42542-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/pr42542-3.c
new file mode 100644
index 000000000..29e090883
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/pr42542-3.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-options "-O1 -ftree-vectorize" } */
+
+unsigned char v1[] __attribute__ ((aligned(16))) =
+{
+  0x80, 0xd0, 0x90, 0xa0, 1, 15, 10, 15,
+  0xa0, 0xc0, 0xb0, 0xf0, 2, 25, 20, 35,
+  3, 34, 30, 36, 0xd0, 0x80, 0xe0, 0xb0,
+  0xf0, 0xe0, 0xe0, 0x80, 25, 34, 30, 40
+};
+unsigned char v2[] __attribute__ ((aligned(16))) =
+{
+  4, 44, 40, 48, 0xb0, 0x80, 0x80, 0x90,
+  5, 55, 50, 51, 0xc0, 0xb0, 0xf0, 0xd0,
+  0xd0, 0x80, 0xa0, 0xf0, 6, 61, 65, 68,
+  7, 76, 75, 81, 0xe0, 0xf0, 0xc0, 0x90
+};
+
+unsigned char max[] =
+{
+  0x80, 0xd0, 0x90, 0xa0, 0xb0, 0x80, 0x80, 0x90,
+  0xa0, 0xc0, 0xb0, 0xf0, 0xc0, 0xb0, 0xf0, 0xd0,
+  0xd0, 0x80, 0xa0, 0xf0, 0xd0, 0x80, 0xe0, 0xb0,
+  0xf0, 0xe0, 0xe0, 0x80, 0xe0, 0xf0, 0xc0, 0x90
+};
+
+unsigned char min[] =
+{
+  4, 44, 40, 48, 1, 15, 10, 15,
+  5, 55, 50, 51, 2, 25, 20, 35,
+  3, 34, 30, 36, 6, 61, 65, 68,
+  7, 76, 75, 81, 25, 34, 30, 40
+};
+
+unsigned char res[32] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+int main (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 32; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 32; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/sibcall-opt-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/sibcall-opt-1.c
new file mode 100644
index 000000000..6e8d1a2fa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/sibcall-opt-1.c
@@ -0,0 +1,12 @@
+/* PR target/38056.  Do not do sibcall optimization across object file
+   boundery when -mconstant-gp is not used.  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "br.call.*bar" } } */
+
+int bar(int x);
+
+int foo(int x)
+{
+  return (bar(x + 1));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/sibcall-opt-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/sibcall-opt-2.c
new file mode 100644
index 000000000..d802b792d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/sibcall-opt-2.c
@@ -0,0 +1,12 @@
+/* PR target/38056.  Do sibcall optimization across object file
+   boundery when -mconstant-gp is used.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mconstant-gp" } */
+/* { dg-final { scan-assembler-not "br.call.*bar" } } */
+
+int bar(int x);
+
+int foo(int x)
+{
+  return (bar(x + 1));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/sibcall-unwind-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/sibcall-unwind-1.c
new file mode 100644
index 000000000..471179119
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/sibcall-unwind-1.c
@@ -0,0 +1,10 @@
+/* PR 13158.  Emit ".restore sp" for a sibcall.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -w" } */
+/* { dg-final { scan-assembler-times "\\.restore sp" 1 } } */
+
+static void do_date (char *);  
+void rfc822_date (char *date)  
+{  
+  do_date (date);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/sibcall-unwind-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/sibcall-unwind-2.c
new file mode 100644
index 000000000..0ae31ae5b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/sibcall-unwind-2.c
@@ -0,0 +1,11 @@
+/* PR 18987.  This caused an assembler error because we emitted ".restore sp"
+   twice.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -w" } */
+/* { dg-final { scan-assembler-times "\\.restore sp" 1 } } */
+
+static void do_date (char *);  
+void rfc822_date (char *date)  
+{  
+  do_date (date);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/small-addr-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/small-addr-1.c
new file mode 100644
index 000000000..846218623
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/small-addr-1.c
@@ -0,0 +1,23 @@
+/* PR target/21632 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct S
+{
+  void *s[256];
+};
+
+struct T
+{
+  long t[23];
+  struct S *u;
+};
+
+extern struct T __attribute__((model (small))) v;
+
+void *
+foo (void)
+{
+  return v.u->s[0];
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/types-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/types-1.c
new file mode 100644
index 000000000..ace49ebb3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/types-1.c
@@ -0,0 +1,41 @@
+/* { dg-do compile { target ia64*-hp-hpux* } } */
+
+/* Test that __fpreg is distinct from any other builtin type.  */
+
+extern float fr1; /* { dg-message "note: previous declaration of " } */
+extern __fpreg fr1; /* { dg-error "" } */
+extern double fr2; /* { dg-message "note: previous declaration of " } */
+extern __fpreg fr2; /* { dg-error "" } */
+extern long double fr3; /* { dg-message "note: previous declaration of " } */
+extern __fpreg fr3; /* { dg-error "" } */
+extern __float80 fr4; /* { dg-message "note: previous declaration of " } */
+extern __fpreg fr4; /* { dg-error "" } */
+extern __float128 fr5; /* { dg-message "note: previous declaration of " } */
+extern __fpreg fr5; /* { dg-error "" } */
+
+/* Test that __float80 is distinct from any other builtin type.  */
+
+extern float f801; /* { dg-message "note: previous declaration of " } */
+extern __float80 f801; /* { dg-error "" } */
+extern double f802; /* { dg-message "note: previous declaration of " } */
+extern __float80 f802; /* { dg-error "" } */
+extern long double f803; /* { dg-message "note: previous declaration of " } */
+extern __float80 f803; /* { dg-error "" } */
+extern __fpreg f804;  /* { dg-message "note: previous declaration of " } */
+extern __float80 f804; /* { dg-error "" } */
+extern __float128 f805; /* { dg-message "note: previous declaration of " } */
+extern __float80 f805; /* { dg-error "" } */
+
+/* Test that __float128 is distinct from any other builtin type --
+   except "long double", for which it is a synonym.  */
+
+extern float f1281; /* { dg-message "note: previous declaration of " } */
+extern __float128 f1281; /* { dg-error "" } */
+extern double f1282; /* { dg-message "note: previous declaration of " } */
+extern __float128 f1282; /* { dg-error "" } */
+extern long double f1283;
+extern __float128 f1283;
+extern __fpreg f1284; /* { dg-message "note: previous declaration of " } */
+extern __float128 f1284; /* { dg-error "" } */
+extern __float80 f1285; /* { dg-message "note: previous declaration of " } */
+extern __float128 f1285; /* { dg-error "" } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/types-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/types-2.c
new file mode 100644
index 000000000..30e4ddbf8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/types-2.c
@@ -0,0 +1,20 @@
+/* { dg-do run { target ia64*-hp-hpux* } } */
+/* { dg-options } */
+
+/* Test that the sizes and alignments of the extra floating-point
+   types are correct.  */
+
+int main () {
+  if (sizeof (__fpreg) != 16)
+    return 1;
+  if (__alignof__ (__fpreg) != 16)
+    return 2;
+
+  if (sizeof (__float80) != 16)
+    return 3;
+  if (__alignof__ (__float80) != 16)
+    return 4;
+
+  return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/versionid-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/versionid-1.c
new file mode 100644
index 000000000..4ee8224a7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/versionid-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target ia64-*-hpux* } } */
+
+extern int foo () __attribute__((version_id ("20040821")));
+
+int bar(int i)
+{
+	return (foo() + 1);
+}
+
+/* { dg-final { scan-assembler "alias.*foo.*foo\\\{20040821\\\}" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/versionid-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/versionid-2.c
new file mode 100644
index 000000000..258de0911
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/versionid-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target ia64-*-hpux* } } */
+
+extern int foo () __attribute__((version_id ("20040821")));
+
+int foo(int i)
+{
+	return (1);
+}
+
+/* { dg-final { scan-assembler "alias.*foo.*foo\\\{20040821\\\}" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/visibility-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/visibility-1.c
new file mode 100644
index 000000000..fdccab3c7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/visibility-1.c
@@ -0,0 +1,38 @@
+/* Test visibility attribute.  */
+/* { dg-do compile { target ia64*-*-linux* } } */
+/* { dg-options "-O2 -fpic" } */
+/* { dg-final { scan-assembler "\\.hidden.*variable_j" } } */
+/* { dg-final { scan-assembler "\\.hidden.*variable_m" } } */
+/* { dg-final { scan-assembler "\\.protected.*baz" } } */
+/* { dg-final { scan-assembler "gprel.*variable_i" } } */
+/* { dg-final { scan-assembler "gprel.*variable_j" } } */
+/* { dg-final { scan-assembler "ltoff.*variable_k" } } */
+/* { dg-final { scan-assembler "gprel.*variable_l" } } */
+/* { dg-final { scan-assembler "gprel.*variable_m" } } */
+/* { dg-final { scan-assembler "ltoff.*variable_n" } } */
+
+static int variable_i;
+int variable_j __attribute__((visibility ("hidden")));
+int variable_k;
+struct A { char a[64]; };
+static struct A variable_l __attribute__((section (".sbss")));
+struct A variable_m __attribute__((visibility ("hidden"), section(".sbss")));
+struct A variable_n __attribute__((section (".sbss")));
+
+void foo (void)
+{
+  variable_i = 0;
+  variable_j = 0;
+  variable_k = 0;
+}
+
+void bar (void)
+{
+  variable_l.a[10] = 0;
+  variable_m.a[10] = 0;
+  variable_n.a[10] = 0;
+}
+
+void __attribute__((visibility ("protected"))) baz (void)
+{
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/visibility-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/visibility-2.c
new file mode 100644
index 000000000..895ef6d91
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/ia64/visibility-2.c
@@ -0,0 +1,15 @@
+/* Test visibility attribute.  */
+/* { dg-do link { target ia64*-*-linux* } } */
+/* { dg-options "-O2 -fpic" } */
+
+int foo (int x);
+int bar (int x) __asm__ ("foo") __attribute__ ((visibility ("hidden")));
+int bar (int x)
+{
+  return x;
+}
+
+int main ()
+{
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/crash1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/crash1.c
new file mode 100644
index 000000000..fdd737ab2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/crash1.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -fomit-frame-pointer" } */
+
+/* Caused an ICE because of forgotten auto increment.  */
+
+register void *current __asm__("%a2");
+
+struct kernel_stat
+{
+ long long user;
+ long long nice;
+ long long system;
+ long long idle;
+ long long steal;
+ unsigned irqs[256];
+};
+extern struct kernel_stat per_cpu__kstat;
+
+void show_stat(void)
+{
+  int i;
+  long long user, nice, system, idle, steal;
+  long long sum = 0;
+
+  user = nice = system = idle = steal = 0;
+  for (i = 0; i < 1; i++)
+    {
+      int j;
+      user = user + per_cpu__kstat.user;
+      nice = nice + per_cpu__kstat.nice;
+      system = system + per_cpu__kstat.system;
+      idle = idle + per_cpu__kstat.idle;
+      steal = steal + per_cpu__kstat.steal;
+
+      for (j = 0 ; j < 256 ; j++)
+	sum += per_cpu__kstat.irqs[j];
+    }
+  seq_printf(user, nice, system, idle, steal);
+  seq_printf(sum);
+  for (i = 0; i < 256; i++)
+    seq_printf (i);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/interrupt-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/interrupt-1.c
new file mode 100644
index 000000000..443c13b46
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/interrupt-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "j(ra|mp)\[ \t\]*interrupt_sibcall" } } */
+/* { dg-final { scan-assembler "j(b|)sr\[ \t\]*interrupt_call" } } */
+/* { dg-final { scan-assembler "j(ra|mp)\[ \t\]*normal_sibcall" } } */
+
+void normal_sibcall (void);
+void interrupt_call (void);
+void __attribute ((interrupt)) interrupt_sibcall (void);
+
+void normal (void)
+{
+  normal_sibcall ();
+}
+
+void __attribute ((interrupt)) interrupt (void)
+{
+  interrupt_call ();
+}
+
+void __attribute ((interrupt)) interrupt_2 (void)
+{
+  interrupt_sibcall ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/interrupt-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/interrupt-2.c
new file mode 100644
index 000000000..7d4cb68c1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/interrupt-2.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+int x;
+volatile unsigned int y;
+
+#define REPEAT10(X, Y)					\
+  X(Y##0); X(Y##1); X(Y##2); X(Y##3); X(Y##4);		\
+  X(Y##5); X(Y##6); X(Y##7); X(Y##8); X(Y##9)
+
+#define REPEAT30(X) REPEAT10 (X, 0); REPEAT10 (X, 1); REPEAT10 (X, 2)
+#define IN(X) unsigned int x##X = y
+#define OUT(X) y = x##X
+
+void __attribute__ ((interrupt_handler)) f1 (void)
+{
+  x = y + 11;
+}
+
+void __attribute__ ((interrupt_handler)) f2 (void)
+{
+  REPEAT30 (IN);
+  REPEAT30 (OUT);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/interrupt_thread-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/interrupt_thread-1.c
new file mode 100644
index 000000000..ee7179cd4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/interrupt_thread-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=fidoa -O2 -fomit-frame-pointer" } */
+
+/* Check that interrupt_thread attribute works.  */
+
+#ifdef __mfido__
+extern void foo (void) __attribute__ ((interrupt_thread));
+
+int a, b, c, d;
+
+void bar (void);
+
+void
+foo (void)
+{
+  int w, x, y, z;
+
+  w = a;
+  x = b;
+  y = c;
+  z = d;
+
+  bar ();
+
+  a = w;
+  b = x;
+  c = y;
+  d = z;
+}
+#else
+/* If the current mutilib is, say, -mcpu=5485, the compiler gets
+   -mcpu=fidoa -mcpu=5485, where -mcpu=fidoa is overridden.  In that
+   case, we just print out "sleep" in the assembly file and pretend
+   that everything is all right.  */
+asm ("sleep");
+#endif
+
+/* "sleep" should be generated in place of "rts".  */
+/* { dg-final { scan-assembler-times "sleep" 1 } } */
+/* { dg-final { scan-assembler-times "rts" 0 } } */
+
+/* There should be no stack adjustment.  */
+/* { dg-final { scan-assembler-times "sp" 0 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/interrupt_thread-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/interrupt_thread-2.c
new file mode 100644
index 000000000..1518bece5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/interrupt_thread-2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=fidoa" } */
+
+/* Check that an error is issued for using more than one
+   interrupt_attribute at the same time.  */
+
+/* If the current mutilib is, say, -mcpu=5485, the compiler gets
+   -mcpu=fidoa -mcpu=5485, where -mcpu=fidoa is overridden.  In that
+   case, we just use two interrupt_handler attributes and expect the
+   same error.  */
+#ifdef __mfido___
+#define IH interrupt_thread
+#else
+#define IH interrupt_handler
+#endif
+
+extern void f1 (void) __attribute__((interrupt_handler, interrupt_handler)); /* { dg-error "multiple interrupt attributes not allowed" } */
+
+extern void f2 (void) __attribute__((interrupt_handler, IH)); /* { dg-error "multiple interrupt attributes not allowed" } */
+
+extern void f3 (void) __attribute__((IH, interrupt_handler)); /* { dg-error "multiple interrupt attributes not allowed" } */
+
+extern void f4 (void) __attribute__((IH, IH)); /* { dg-error "multiple interrupt attributes not allowed" } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/interrupt_thread-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/interrupt_thread-3.c
new file mode 100644
index 000000000..be83edb5f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/interrupt_thread-3.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=cpu32" } */
+
+/* Check that interrupt_thread is rejected on CPUs other than
+   fido.  */
+
+extern void foo (void) __attribute__((interrupt_thread)); /* { dg-error "interrupt_thread is available only on fido" } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/m68k.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/m68k.exp
new file mode 100644
index 000000000..4ac626440
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/m68k.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 1997, 2004, 2006, 2007 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an m68k target.
+if { ![istarget m68k*-*-*] && ![istarget fido*-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/pic-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/pic-1.c
new file mode 100644
index 000000000..b8d3fe81a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/pic-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target m68k-*-* fido-*-* } }  */
+/* { dg-options "-O2 -fpic" }  */
+
+extern void Foo (void *);
+
+char *ary[] = {"a", "b", "c", "d", "e"};
+
+void Bar (void)
+{
+  int cnt = 0;
+
+  for (cnt = 0; cnt < 4;  ++cnt)
+    {
+      char *ptr = ary[cnt];
+
+      Foo (&ptr);
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/pr35018.c b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/pr35018.c
new file mode 100644
index 000000000..fadea8620
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/pr35018.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -mcpu=5249" } */
+
+static inline void vect_add(int *x, int *y, int n)
+{
+    asm volatile ("nop;"
+                : [n] "+d" (n), [x] "+a" (x), [y] "+a" (y)
+                : : "%d0", "%d1", "%d2", "%d3", "%a0", "%a1", "%a2", "%a3",
+                    "cc", "memory");
+}
+
+extern void vect_copy (int *, int *, int);
+
+void vorbis_synthesis_blockin(int *blocksizes)
+{
+    int j, *pcm, *p;
+
+    int n=blocksizes[*p]/2;
+    int n0=blocksizes[0]/2;
+    int n1=blocksizes[1]/2;
+
+    for(j=0;j<*p;j++)
+    {
+        vect_add(p, pcm, n1);
+        vect_add(pcm, p, n0);
+        vect_add(p, pcm, n0);
+        vect_add(p, pcm, n0);
+        vect_copy(pcm, p, n);
+    }
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/pr36133.c b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/pr36133.c
new file mode 100644
index 000000000..25237a860
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/pr36133.c
@@ -0,0 +1,16 @@
+/* pr36133.c
+
+   This test ensures that conditional branches can use the condition codes
+   written by shift instructions, without the need for an extra TST.  */
+
+/* { dg-do compile }  */
+/* { dg-options "-O2" }  */
+/* { dg-final { scan-assembler-not "tst" } } */
+
+void
+f (unsigned int a)
+{
+  if (a >> 4)
+    asm volatile ("nop");
+  asm volatile ("nop");
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/pr36134.c b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/pr36134.c
new file mode 100644
index 000000000..d8d65c16c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/pr36134.c
@@ -0,0 +1,23 @@
+/* pr36134.c
+
+   This test ensures that the shorter LEA instruction is used in preference
+   to the longer ADD instruction.  */
+
+/* { dg-do compile }  */
+/* { dg-options "-O2" }  */
+/* { dg-final { scan-assembler "lea" } } */
+/* { dg-final { scan-assembler-not "add" } } */
+
+int *a, *b;
+
+void
+f ()
+{
+  while (a > b)
+    {
+      *a++ = *b++;
+      *a++ = *b++;
+      *a++ = *b++;
+      *a++ = *b++;
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/slp-ice.c b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/slp-ice.c
new file mode 100644
index 000000000..61c7f9df3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/slp-ice.c
@@ -0,0 +1,15 @@
+/* From PR 7872, test for optabs segfault when strict low part is present.  */
+/* { dg-do compile { target m68k-*-* } }  */
+/* { dg-options "-O0" }  */
+extern void (**table)(void);
+
+typedef unsigned short uw16;
+typedef unsigned int gshort;
+
+register uw16 *pc asm("%a4");
+register gshort code asm("%d6");
+
+void QMExecuteLoop(uw16 *oldPC)
+{
+  table[code=(*(uw16*)(pc++))]();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/xgot-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/xgot-1.c
new file mode 100644
index 000000000..6794241a8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/m68k/xgot-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fpic -mxgot -mcpu=5206" } */
+/* { dg-final { scan-assembler "foo@GOT,\%\[ad\]\[0-7\]" } } */
+
+extern int foo;
+
+int
+bar (void)
+{
+  return foo;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/20020620-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/20020620-1.c
new file mode 100644
index 000000000..1f2affe48
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/20020620-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong64" } */
+int foo (int *x, int i)
+{
+  return x[i] + i;
+}
+/* { dg-final { scan-assembler-not "move" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/args-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/args-1.c
new file mode 100644
index 000000000..56def9488
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/args-1.c
@@ -0,0 +1,35 @@
+/* Check that certain preprocessor macros are defined, and do some
+   consistency checks.  */
+/* { dg-do compile } */
+
+const char *compiled_for = _MIPS_ARCH;
+const char *optimized_for = _MIPS_TUNE;
+
+#if __mips_fpr != 32 && __mips_fpr != 64
+#error Bad __mips_fpr
+#endif
+
+/* Test complementary macro pairs: exactly one of each pair
+   must be defined.  */
+
+#if defined (_R3000) == defined (_R4000) && !defined (__sgi__)
+#error _R3000 / _R4000 mismatch
+#endif
+
+#if defined (__mips_hard_float) == defined (__mips_soft_float)
+#error __mips_hard_float / __mips_soft_float mismatch
+#endif
+
+#if defined (_MIPSEL) == defined (_MIPSEB)
+#error _MIPSEL / _MIPSEB mismatch
+#endif
+
+/* Check for __mips64 consistency.  */
+
+#if defined (__mips64) != defined (_R4000) && !defined (__sgi__)
+#error __mips64 / _R4000 mismatch
+#endif
+
+#if defined (__mips64) && __mips != 3 && __mips != 4 && __mips != 64
+#error __mips64 / __mips mismatch
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/args-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/args-2.c
new file mode 100644
index 000000000..192756525
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/args-2.c
@@ -0,0 +1,18 @@
+/* Check the _MIPSEB and _MIPSEL macros are accurate.  */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+short foo = 1;
+int main ()
+{
+  char *p = (char *) &foo;
+
+#ifdef _MIPSEB
+  if (p[0] != 0 || p[1] != 1)
+#else
+  if (p[0] != 1 || p[1] != 0)
+#endif
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/args-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/args-3.c
new file mode 100644
index 000000000..6a79ce674
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/args-3.c
@@ -0,0 +1,39 @@
+/* __mips, and related defines, guarantee that certain assembly
+   instructions can be used.  Check a few examples.  */
+/* { dg-do run } */
+/* { dg-skip-if "" { *-*-* } { "-mflip-mips16" } { "" } } */
+extern void abort (void);
+extern void exit (int);
+
+typedef int int32 __attribute__ ((mode (SI)));
+typedef int int64 __attribute__ ((mode (DI)));
+int foo (float inf, int64 in64, int32 in32)
+{
+  int64 res64;
+  int32 res32;
+
+#if __mips != 1 && defined (__mips_hard_float) && !defined (__mips16)
+  __asm__ ("trunc.w.s %0, %1" : "=f" (res32) : "f" (inf));
+  if (res32 != 11)
+    abort ();
+#endif
+
+#if defined (__mips64)
+  __asm__ ("daddu %0, %1, %1" : "=r" (res64) : "r" (in64));
+  if (res64 != 50)
+    abort ();
+#endif
+
+#if (__mips == 4 || __mips == 32 || __mips == 64) && !defined (__mips16)
+  __asm__ ("move %0,%.\n\tmovn %0,%1,%2"
+	   : "=&r" (res32) : "r" (in32), "r" (in64 != 0));
+  if (res32 != 60)
+    abort ();
+#endif
+}
+
+int main ()
+{
+  foo (11.4f, 25, 60);
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/asm-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/asm-1.c
new file mode 100644
index 000000000..9f9cb3a34
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/asm-1.c
@@ -0,0 +1,15 @@
+/* PR target/17565.  GCC used to put the asm into the delay slot
+   of the call.  */
+/* { dg-do assemble } */
+/* { dg-options "-O" } */
+
+NOMIPS16 int foo (int n)
+{
+  register int k asm ("$16") = n;
+  if (k > 0)
+    {
+      bar ();
+      asm ("li %0,0x12345678" : "=r" (k));
+    }
+  return k;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/atomic-memory-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/atomic-memory-1.c
new file mode 100644
index 000000000..b2316ee64
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/atomic-memory-1.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+
+/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
+
+extern void abort (void);
+extern void exit (int);
+
+NOMIPS16 int main ()
+{
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+  unsigned v = 0;
+  __sync_synchronize ();
+
+  if (!__sync_bool_compare_and_swap (&v, 0, 30000))
+    abort();
+  if (30000 != __sync_val_compare_and_swap (&v, 30000, 100001))
+    abort();
+  __sync_sub_and_fetch (&v, 0x8001);
+  __sync_sub_and_fetch (&v, 0x7fff);
+  if (v != 34465)
+    abort();
+  if (__sync_nand_and_fetch (&v, 0xff) != -162)
+    abort();
+  if (__sync_fetch_and_add (&v, 262) != -162)
+    abort();
+  if (v != 100)
+    abort();
+  if (__sync_or_and_fetch (&v, 0xf001) != 0xf065)
+    abort();
+  if (__sync_and_and_fetch (&v, 0x1000) != 0x1000)
+    abort();
+  if (__sync_xor_and_fetch (&v, 0xa51040) != 0xa50040)
+    abort();
+  __sync_and_and_fetch (&v, 7);
+  if (__sync_lock_test_and_set(&v, 1) != 0)
+    abort();
+  if (v != 1)
+    abort();
+  __sync_lock_release (&v);
+  if (v != 0)
+    abort();
+#endif
+  exit(0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/atomic-memory-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/atomic-memory-2.c
new file mode 100644
index 000000000..bc597ab2d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/atomic-memory-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 isa>=2 -mabi=32" } */
+/* { dg-final { scan-assembler "addiu" } } */
+/* { dg-final { scan-assembler-not "subu" } } */
+
+NOMIPS16 unsigned long
+f(unsigned long *p)
+{
+    return __sync_fetch_and_sub (p, 5);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/branch-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/branch-1.c
new file mode 100644
index 000000000..b70b2640f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/branch-1.c
@@ -0,0 +1,14 @@
+/* Octeon targets should use "bbit" instructions for these "if" statements,
+   but we test for "bbit" elsewhere.  On other targets, we should implement
+   the "if" statements using an "andi" instruction followed by a branch
+   on zero.  */
+/* { dg-options "-O2 isa=!octeon" } */
+
+void bar (void);
+NOMIPS16 void f1 (int x) { if (x & 4) bar (); }
+NOMIPS16 void f2 (int x) { if ((x >> 2) & 1) bar (); }
+NOMIPS16 void f3 (unsigned int x) { if (x & 0x10) bar (); }
+NOMIPS16 void f4 (unsigned int x) { if ((x >> 4) & 1) bar (); }
+/* { dg-final { scan-assembler "\tandi\t.*\tandi\t.*\tandi\t.*\tandi\t" } } */
+/* { dg-final { scan-assembler-not "\tsrl\t" } } */
+/* { dg-final { scan-assembler-not "\tsra\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/branch-cost-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/branch-cost-1.c
new file mode 100644
index 000000000..d825e0617
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/branch-cost-1.c
@@ -0,0 +1,8 @@
+/* { dg-options "-mbranch-cost=1 isa>=4 -O2" } */
+NOMIPS16 int
+foo (int x, int y, int z, int k)
+{
+  return x == k ? x + y : z - x;
+}
+/* { dg-final { scan-assembler-not "\t(movz|movn)\t" } } */
+/* { dg-final { scan-assembler "\t(bne|beq)\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/branch-cost-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/branch-cost-2.c
new file mode 100644
index 000000000..23f528ad6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/branch-cost-2.c
@@ -0,0 +1,8 @@
+/* { dg-options "-mbranch-cost=10 isa>=4 -O2" } */
+NOMIPS16 int
+foo (int x, int y, int z, int k)
+{
+  return x == k ? x + y : z - x;
+}
+/* { dg-final { scan-assembler "\t(movz|movn)\t" } } */
+/* { dg-final { scan-assembler-not "\t(bne|beq)\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/cache-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/cache-1.c
new file mode 100644
index 000000000..05cb40791
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/cache-1.c
@@ -0,0 +1,30 @@
+/* { dg-options "-O2 isa>=3" } */
+
+NOMIPS16 void
+f1 (int *area)
+{
+  __builtin_mips_cache (20, area);
+}
+
+NOMIPS16 void
+f2 (const short *area)
+{
+  __builtin_mips_cache (24, area + 10);
+}
+
+NOMIPS16 void
+f3 (volatile unsigned int *area, int offset)
+{
+  __builtin_mips_cache (0, area + offset);
+}
+
+NOMIPS16 void
+f4 (const volatile unsigned char *area)
+{
+  __builtin_mips_cache (4, area - 80);
+}
+
+/* { dg-final { scan-assembler "\tcache\t0x14,0\\(\\\$4\\)" } } */
+/* { dg-final { scan-assembler "\tcache\t0x18,20\\(\\\$4\\)" } } */
+/* { dg-final { scan-assembler "\tcache\t0x0,0\\(\\\$.\\)" } } */
+/* { dg-final { scan-assembler "\tcache\t0x4,-80\\(\\\$4\\)" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/call-saved-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/call-saved-1.c
new file mode 100644
index 000000000..5c86b6c8c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/call-saved-1.c
@@ -0,0 +1,21 @@
+/* Check that we save all call-saved GPRs in a MIPS16 __builtin_eh_return
+   function.  */
+/* { dg-options "(-mips16) isa_rev=0" } */
+
+void bar (void);
+
+MIPS16 void
+foo (int x)
+{
+  __builtin_unwind_init ();
+  __builtin_eh_return (x, bar);
+}
+/* { dg-final { scan-assembler "\\\$16" } } */
+/* { dg-final { scan-assembler "\\\$17" } } */
+/* { dg-final { scan-assembler "\\\$18" } } */
+/* { dg-final { scan-assembler "\\\$19" } } */
+/* { dg-final { scan-assembler "\\\$20" } } */
+/* { dg-final { scan-assembler "\\\$21" } } */
+/* { dg-final { scan-assembler "\\\$22" } } */
+/* { dg-final { scan-assembler "\\\$23" } } */
+/* { dg-final { scan-assembler "\\\$(30|fp)" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/call-saved-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/call-saved-2.c
new file mode 100644
index 000000000..9ac7a2735
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/call-saved-2.c
@@ -0,0 +1,18 @@
+/* Check that we save non-MIPS16 GPRs if they are explicitly clobbered.  */
+/* { dg-options "(-mips16) isa_rev=0 -O2" } */
+
+MIPS16 void
+foo (void)
+{
+  asm volatile ("" ::: "$19", "$23", "$24", "$30");
+}
+/* { dg-final { scan-assembler-not "\\\$16" } } */
+/* { dg-final { scan-assembler-not "\\\$17" } } */
+/* { dg-final { scan-assembler-not "\\\$18" } } */
+/* { dg-final { scan-assembler "\\\$19" } } */
+/* { dg-final { scan-assembler-not "\\\$20" } } */
+/* { dg-final { scan-assembler-not "\\\$21" } } */
+/* { dg-final { scan-assembler-not "\\\$22" } } */
+/* { dg-final { scan-assembler "\\\$23" } } */
+/* { dg-final { scan-assembler-not "\\\$24" } } */
+/* { dg-final { scan-assembler "\\\$(30|fp)" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/call-saved-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/call-saved-3.c
new file mode 100644
index 000000000..e178eb0f0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/call-saved-3.c
@@ -0,0 +1,22 @@
+/* Check that we save all call-saved GPRs in a MIPS16 __builtin_setjmp
+   function.  */
+/* { dg-options "(-mips16) isa_rev=0 -O2" } */
+
+void bar (void);
+extern int buf[];
+
+MIPS16 void
+foo (int x)
+{
+  if (__builtin_setjmp (buf) == 0)
+    bar();
+}
+/* { dg-final { scan-assembler "\\\$16" } } */
+/* { dg-final { scan-assembler "\\\$17" } } */
+/* { dg-final { scan-assembler "\\\$18" } } */
+/* { dg-final { scan-assembler "\\\$19" } } */
+/* { dg-final { scan-assembler "\\\$20" } } */
+/* { dg-final { scan-assembler "\\\$21" } } */
+/* { dg-final { scan-assembler "\\\$22" } } */
+/* { dg-final { scan-assembler "\\\$23" } } */
+/* { dg-final { scan-assembler "\\\$(30|fp)" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/clear-cache-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/clear-cache-1.c
new file mode 100644
index 000000000..60bbf9dfc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/clear-cache-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 isa_rev>=2" } */
+/* { dg-final { scan-assembler "synci" } } */
+/* { dg-final { scan-assembler "jr.hb" } } */
+/* { dg-final { scan-assembler-not "_flush_cache" } } */
+
+NOMIPS16 void f()
+{
+  int size = 40;
+  char *memory = __builtin_alloca(size);
+  __builtin___clear_cache(memory, memory + size);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/clear-cache-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/clear-cache-2.c
new file mode 100644
index 000000000..2c925b860
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/clear-cache-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mips32" } */
+/* { dg-final { scan-assembler-not "synci" } } */
+/* { dg-final { scan-assembler-not "jr.hb" } } */
+/* { dg-final { scan-assembler "_flush_cache" } } */
+
+void f()
+{
+  int size = 40;
+  char *memory = __builtin_alloca(size);
+  __builtin___clear_cache(memory, memory + size);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/code-readable-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/code-readable-1.c
new file mode 100644
index 000000000..ee239e1f8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/code-readable-1.c
@@ -0,0 +1,34 @@
+/* { dg-options "(-mips16) -mcode-readable=yes -mgp32 addressing=absolute" } */
+
+MIPS16 int
+foo (int i)
+{
+  switch (i)
+    {
+    case 1: return 40;
+    case 2: return 11;
+    case 3: return 29;
+    case 4: return 10;
+    case 5: return 12;
+    case 6: return 35;
+    case 7: return 23;
+    default: return 0;
+    }
+}
+
+extern int k[];
+
+MIPS16 int *
+bar (void)
+{
+  return k;
+}
+
+/* { dg-final { scan-assembler "\tla\t" } } */
+/* { dg-final { scan-assembler "\t\.half\t" } } */
+/* { dg-final { scan-assembler-not "%hi\\(\[^)\]*L" } } */
+/* { dg-final { scan-assembler-not "%lo\\(\[^)\]*L" } } */
+
+/* { dg-final { scan-assembler "\t\.word\tk\n" } } */
+/* { dg-final { scan-assembler-not "%hi\\(k\\)" } } */
+/* { dg-final { scan-assembler-not "%lo\\(k\\)" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/code-readable-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/code-readable-2.c
new file mode 100644
index 000000000..1aeecafe1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/code-readable-2.c
@@ -0,0 +1,34 @@
+/* { dg-options "(-mips16) -mcode-readable=pcrel -mgp32 addressing=absolute" } */
+
+MIPS16 int
+foo (int i)
+{
+  switch (i)
+    {
+    case 1: return 40;
+    case 2: return 11;
+    case 3: return 29;
+    case 4: return 10;
+    case 5: return 12;
+    case 6: return 35;
+    case 7: return 23;
+    default: return 0;
+    }
+}
+
+extern int k[];
+
+MIPS16 int *
+bar (void)
+{
+  return k;
+}
+
+/* { dg-final { scan-assembler-not "\tla\t" } } */
+/* { dg-final { scan-assembler-not "\t\.half\t" } } */
+/* { dg-final { scan-assembler "%hi\\(\[^)\]*L" } } */
+/* { dg-final { scan-assembler "%lo\\(\[^)\]*L" } } */
+
+/* { dg-final { scan-assembler "\t\.word\tk\n" } } */
+/* { dg-final { scan-assembler-not "%hi\\(k\\)" } } */
+/* { dg-final { scan-assembler-not "%lo\\(k\\)" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/code-readable-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/code-readable-3.c
new file mode 100644
index 000000000..21dc82be2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/code-readable-3.c
@@ -0,0 +1,34 @@
+/* { dg-options "(-mips16) -mcode-readable=no -mgp32 addressing=absolute" } */
+
+MIPS16 int
+foo (int i)
+{
+  switch (i)
+    {
+    case 1: return 40;
+    case 2: return 11;
+    case 3: return 29;
+    case 4: return 10;
+    case 5: return 12;
+    case 6: return 35;
+    case 7: return 23;
+    default: return 0;
+    }
+}
+
+extern int k[];
+
+MIPS16 int *
+bar (void)
+{
+  return k;
+}
+
+/* { dg-final { scan-assembler-not "\tla\t" } } */
+/* { dg-final { scan-assembler-not "\t\.half\t" } } */
+/* { dg-final { scan-assembler "%hi\\(\[^)\]*L" } } */
+/* { dg-final { scan-assembler "%lo\\(\[^)\]*L" } } */
+
+/* { dg-final { scan-assembler-not "\t\.word\tk\n" } } */
+/* { dg-final { scan-assembler "%hi\\(k\\)" } } */
+/* { dg-final { scan-assembler "%lo\\(k\\)" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dmult-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dmult-1.c
new file mode 100644
index 000000000..6d4120435
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dmult-1.c
@@ -0,0 +1,10 @@
+/* { dg-options "isa=64!octeon -mgp64" } */
+/* { dg-final { scan-assembler "\tdmult\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tdmul\t" } } */
+
+long long
+f (long long a, long long b)
+{
+  return a * b;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dpaq_sa_l_w.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dpaq_sa_l_w.c
new file mode 100644
index 000000000..87d1da98c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dpaq_sa_l_w.c
@@ -0,0 +1,49 @@
+/* { dg-do compile { target { fixed_point } } } */
+/* { dg-options "-O2 -mgp32 -mdsp" } */
+/* { dg-final { scan-assembler-times "\tdpaq_sa.l.w\t\\\$ac" 3 } } */
+
+NOMIPS16 _Sat long long _Fract
+f1 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z)
+{
+  return (_Sat long long _Fract) x * y + z;
+}
+
+NOMIPS16 _Sat long long _Fract
+f2 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z)
+{
+  return z + (_Sat long long _Fract) y * x;
+}
+
+NOMIPS16 _Sat long long _Fract
+f3 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z)
+{
+  _Sat long long _Fract t = (_Sat long long _Fract) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z = t + z; /* Need to put z at the end.  GCC does not swap operands to
+		  match the ssmadd pattern, because types are saturating.  */
+  return z;
+}
+
+long long _Fract
+f4 (long _Fract x, long _Fract y, long long _Fract z)
+{
+  return (long long _Fract) x * y + z;
+}
+
+long long _Fract
+f5 (long _Fract x, long _Fract y, long long _Fract z)
+{
+  return z + (long long _Fract) y * x;
+}
+
+long long _Fract
+f6 (long _Fract x, long _Fract y, long long _Fract z)
+{
+  long long _Fract t = (long long _Fract) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z = t + z; /* Need to put z at the end.  GCC does not swap operands to
+		  match the ssmadd pattern, because types are saturating.  */
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dpsq_sa_l_w.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dpsq_sa_l_w.c
new file mode 100644
index 000000000..9aeb5667a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dpsq_sa_l_w.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target { fixed_point } } } */
+/* { dg-options "-O2 -mgp32 -mdsp" } */
+/* { dg-final { scan-assembler-times "\tdpsq_sa.l.w\t\\\$ac" 2 } } */
+
+NOMIPS16 _Sat long long _Fract
+f1 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z)
+{
+  return z - (_Sat long long _Fract) x * y;
+}
+
+NOMIPS16 _Sat long long _Fract
+f2 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z)
+{
+  _Sat long long _Fract t = (_Sat long long _Fract) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
+
+long long _Fract
+f3 (long _Fract x, long _Fract y, long long _Fract z)
+{
+  return z - (long long _Fract) x * y;
+}
+
+long long _Fract
+f4 (long _Fract x, long _Fract y, long long _Fract z)
+{
+  long long _Fract t = (long long _Fract) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dse-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dse-1.c
new file mode 100644
index 000000000..6ef55cde2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dse-1.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-mgp64 -O" } */
+
+#define TEST(ID, TYPE1, TYPE2)					\
+  union u##ID {							\
+    TYPE1 m1[sizeof (TYPE2) / sizeof (TYPE1)];			\
+    TYPE2 m2;							\
+  };								\
+								\
+  /* The MIPS16 versions of the shifts we need are too		\
+     expensive.  */						\
+  TYPE1 __attribute__((nomips16))				\
+  f##ID (TYPE2 x, union u##ID *u)				\
+  {								\
+    u->m2 = x;							\
+    return (u->m1[0]						\
+	    + u->m1[sizeof (TYPE2) / sizeof (TYPE1) - 1]);	\
+  }								\
+								\
+  TYPE1 __attribute__((nomips16))				\
+  g##ID (union u##ID *u)					\
+  {								\
+    u->m2 = 0;							\
+    return (u->m1[0] | u->m1[1]);				\
+  }
+
+TEST (1, unsigned int, unsigned long long);
+TEST (2, int, long long);
+TEST (3, unsigned short, unsigned long long);
+TEST (4, short, long long);
+TEST (5, unsigned char, unsigned long long);
+TEST (6, signed char, long long);
+
+TEST (7, unsigned short, unsigned int);
+TEST (8, short, int);
+TEST (9, unsigned char, unsigned int);
+TEST (10, signed char, int);
+
+TEST (11, unsigned char, unsigned short);
+TEST (12, signed char, short);
+
+/* { dg-final { scan-assembler-not "\tlh\t" } } */
+/* { dg-final { scan-assembler-not "\tlhu\t" } } */
+/* { dg-final { scan-assembler-not "\tlw\t" } } */
+/* { dg-final { scan-assembler-not "\tlwu\t" } } */
+/* { dg-final { scan-assembler-not "\tlb\t" } } */
+/* { dg-final { scan-assembler-not "\tlbu\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dsp-ctrl.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dsp-ctrl.c
new file mode 100644
index 000000000..bb89e84f2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dsp-ctrl.c
@@ -0,0 +1,69 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mdsp -mgp32" } */
+
+extern void abort (void);
+extern void exit (int);
+
+NOMIPS16 void __attribute__ ((noinline))
+test1 (int i)
+{
+  __builtin_mips_wrdsp (i, 63);
+}
+
+NOMIPS16 void __attribute__ ((noinline))
+test2 ()
+{
+  long long a = 0;
+  __builtin_mips_extpdp (a, 3);
+}
+
+NOMIPS16 void __attribute__ ((noinline))
+test3 (int i)
+{
+  long long a = 0;
+  __builtin_mips_extpdp (a, i);
+}
+
+NOMIPS16 void __attribute__ ((noinline))
+test4 ()
+{
+  long long a = 0;
+  int i = 0;
+  __builtin_mips_mthlip (a, i);
+}
+
+NOMIPS16 int
+main ()
+{
+  int cntl;
+
+  /* Test 1: wrdsp */
+  __builtin_mips_wrdsp (0,63);
+  test1 (63);
+  cntl = __builtin_mips_rddsp (63);
+  if (cntl != 63)
+    abort ();
+
+  /* Test 2: extpdp */
+  __builtin_mips_wrdsp (63,63);
+  test2 ();
+  cntl = __builtin_mips_rddsp (63);
+  if (cntl != 59)
+    abort ();
+
+  /* Test 3: extpdpv */
+  __builtin_mips_wrdsp (63,63);
+  test3 (10);
+  cntl = __builtin_mips_rddsp (63);
+  if (cntl != 52)
+    abort ();
+
+  /* Test 4: mthlip */
+  __builtin_mips_wrdsp (8,63);
+  test4 ();
+  cntl = __builtin_mips_rddsp (63);
+  if (cntl != 40)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dsp-lhx.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dsp-lhx.c
new file mode 100644
index 000000000..416356f2a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dsp-lhx.c
@@ -0,0 +1,10 @@
+/* Test MIPS32 DSP LHX instruction */
+/* { dg-do compile } */
+/* { dg-options "-mgp32 -mdsp -O2" } */
+
+/* { dg-final { scan-assembler "\tlhx\t" } } */
+
+NOMIPS16 signed short test (signed short *a, int index)
+{
+  return a[index];
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dsp-no-lhx.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dsp-no-lhx.c
new file mode 100644
index 000000000..a37c42f1a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dsp-no-lhx.c
@@ -0,0 +1,10 @@
+/* Test MIPS32 DSP LHX instruction */
+/* { dg-do compile } */
+/* { dg-options "-mgp32 -mdsp -O2" } */
+
+/* { dg-final { scan-assembler-not "\tlhx\t" } } */
+
+NOMIPS16 unsigned short test (unsigned short *a, int index)
+{
+  return a[index];
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dspr2-MULT.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dspr2-MULT.c
new file mode 100644
index 000000000..ab2c28a73
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dspr2-MULT.c
@@ -0,0 +1,15 @@
+/* Test MIPS32 DSP REV 2 MULT instruction */
+/* { dg-do compile } */
+/* { dg-options "-mgp32 -mdspr2 -O2 -ffixed-hi -ffixed-lo" } */
+
+/* { dg-final { scan-assembler "\tmult\t" } } */
+/* { dg-final { scan-assembler "ac1" } } */
+/* { dg-final { scan-assembler "ac2" } } */
+
+typedef long long a64;
+
+NOMIPS16 a64 test (a64 *a, int *b, int *c)
+{
+  a[0] = (a64) b[0] * c[0];
+  a[1] = (a64) b[1] * c[1];
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c
new file mode 100644
index 000000000..312938ae5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c
@@ -0,0 +1,15 @@
+/* Test MIPS32 DSP REV 2 MULTU instruction */
+/* { dg-do compile } */
+/* { dg-options "-mgp32 -mdspr2 -O2 -ffixed-hi -ffixed-lo" } */
+
+/* { dg-final { scan-assembler "\tmultu\t" } } */
+/* { dg-final { scan-assembler "ac1" } } */
+/* { dg-final { scan-assembler "ac2" } } */
+
+typedef unsigned long long a64;
+
+NOMIPS16 a64 test (a64 *a, unsigned int *b, unsigned int *c)
+{
+  a[0] = (a64) b[0] * c[0];
+  a[1] = (a64) b[1] * c[1];
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/ext-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/ext-1.c
new file mode 100644
index 000000000..426cbb285
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/ext-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O isa_rev>=2 -mgp64" } */
+/* { dg-final { scan-assembler "\tdext\t" } } */
+/* { dg-final { scan-assembler-not "and" } } */
+
+struct
+{
+  unsigned long long a:9;
+  unsigned long long d:35;
+  unsigned long long e:10;
+  unsigned long long f:10;
+} t;
+
+NOMIPS16 unsigned long long
+f (void)
+{
+   return t.d;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/ext_ins.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/ext_ins.c
new file mode 100644
index 000000000..8186b84a2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/ext_ins.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "isa_rev>=2" } */
+/* { dg-final { scan-assembler "ext" } } */
+/* { dg-final { scan-assembler "ins" } } */
+
+struct A 
+{
+  unsigned int i : 2;
+  unsigned int j : 3;
+  unsigned int k : 4;
+  unsigned int l : 5;
+};
+
+void func (struct A);
+
+unsigned int f1 (struct A a)
+{
+  return a.j;
+}
+
+void f2 (int i)
+{
+  struct A c;
+  c.j = i;
+  func (c);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-1.c
new file mode 100644
index 000000000..76f3b86ec
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_fetch_and_add (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_fetch_and_add (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_fetch_and_add (z, 42);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-10.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-10.c
new file mode 100644
index 000000000..6ac908a71
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-10.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_and_and_fetch (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_and_and_fetch (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_and_and_fetch (z, 42);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-11.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-11.c
new file mode 100644
index 000000000..e1677b657
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-11.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_xor_and_fetch (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_xor_and_fetch (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_xor_and_fetch (z, 42);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-12.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-12.c
new file mode 100644
index 000000000..f767ae202
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-12.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_nand_and_fetch (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_nand_and_fetch (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_nand_and_fetch (z, 42);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-13.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-13.c
new file mode 100644
index 000000000..b0779e0ec
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-13.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_bool_compare_and_swap (z, 0, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_bool_compare_and_swap (z, 0, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_bool_compare_and_swap (z, 0, 42);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-14.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-14.c
new file mode 100644
index 000000000..4a690f59e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-14.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_val_compare_and_swap (z, 0, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_val_compare_and_swap (z, 0, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_val_compare_and_swap (z, 0, 42);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-15.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-15.c
new file mode 100644
index 000000000..bb5fd743a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-15.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  int result;
+
+  result = __sync_lock_test_and_set (z, 42);
+  __sync_lock_release (z);
+  return result;
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  short result;
+
+  result = __sync_lock_test_and_set (z, 42);
+  __sync_lock_release (z);
+  return result;
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  char result;
+
+  result = __sync_lock_test_and_set (z, 42);
+  __sync_lock_release (z);
+  return result;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-2.c
new file mode 100644
index 000000000..bac019134
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z, int amt)
+{
+  return __sync_fetch_and_sub (z, amt);
+}
+
+NOMIPS16 short
+f2 (short *z, short amt)
+{
+  return __sync_fetch_and_sub (z, amt);
+}
+
+NOMIPS16 char
+f3 (char *z, char amt)
+{
+  return __sync_fetch_and_sub (z, amt);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-3.c
new file mode 100644
index 000000000..bec7951c1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-3.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_fetch_and_or (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_fetch_and_or (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_fetch_and_or (z, 42);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-4.c
new file mode 100644
index 000000000..864ab8c1e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-4.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_fetch_and_and (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_fetch_and_and (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_fetch_and_and (z, 42);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-5.c
new file mode 100644
index 000000000..62fd70f5f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-5.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_fetch_and_xor (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_fetch_and_xor (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_fetch_and_xor (z, 42);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-6.c
new file mode 100644
index 000000000..d8bdb4516
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-6.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_fetch_and_nand (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_fetch_and_nand (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_fetch_and_nand (z, 42);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-7.c
new file mode 100644
index 000000000..d4b558e01
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-7.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_add_and_fetch (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_add_and_fetch (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_add_and_fetch (z, 42);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-8.c
new file mode 100644
index 000000000..d48ed263c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-8.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z, int amt)
+{
+  return __sync_sub_and_fetch (z, amt);
+}
+
+NOMIPS16 short
+f2 (short *z, short amt)
+{
+  return __sync_sub_and_fetch (z, amt);
+}
+
+NOMIPS16 char
+f3 (char *z, char amt)
+{
+  return __sync_sub_and_fetch (z, amt);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-9.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-9.c
new file mode 100644
index 000000000..88afad339
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r10000-9.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_or_and_fetch (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_or_and_fetch (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_or_and_fetch (z, 42);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-1.c
new file mode 100644
index 000000000..513fc6130
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-1.c
@@ -0,0 +1,6 @@
+/* { dg-options "-march=r4000 -mfix-r4000 -O2 -dp" } */
+typedef int int32_t;
+typedef int uint32_t;
+int32_t foo (int32_t x, int32_t y) { return x * y; }
+uint32_t bar (uint32_t x, uint32_t y) { return x * y; }
+/* { dg-final { scan-assembler-times "[concat {\tmult\t\$[45],\$[45][^\n]+mulsi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-10.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-10.c
new file mode 100644
index 000000000..ebf3ca305
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-10.c
@@ -0,0 +1,8 @@
+/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication
+   result to $2, which prevents the register allocators from storing the
+   multiplication result in $2.  */
+/* { dg-options "-mips3 -mfix-r4000 -mgp64 -O2 -fno-split-wide-types -dp -EL" } */
+typedef unsigned long long uint64_t;
+typedef unsigned int uint128_t __attribute__((mode(TI)));
+uint128_t foo (uint64_t x, uint64_t y) { return (uint128_t) x * y; }
+/* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-11.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-11.c
new file mode 100644
index 000000000..93f78134e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-11.c
@@ -0,0 +1,4 @@
+/* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */
+typedef long long int64_t;
+int64_t foo (int64_t x) { return x / 11993; }
+/* { dg-final { scan-assembler "[concat {\tdmult\t\$4,\$[0-9]+[^\n]+smuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-12.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-12.c
new file mode 100644
index 000000000..554975ccc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-12.c
@@ -0,0 +1,4 @@
+/* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */
+typedef unsigned long long uint64_t;
+uint64_t foo (uint64_t x) { return x / 11993; }
+/* { dg-final { scan-assembler "[concat {\tdmultu\t\$4,\$[0-9]+[^\n]+umuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-2.c
new file mode 100644
index 000000000..4f27041be
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-2.c
@@ -0,0 +1,7 @@
+/* { dg-options "-mips1 -mfix-r4000 -O2 -dp -EB" } */
+typedef int int32_t;
+typedef long long int64_t;
+int32_t foo (int32_t x, int32_t y) { return ((int64_t) x * y) >> 32; }
+/* ??? A highpart pattern would be a better choice, but we currently
+   don't use them.  */
+/* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-3.c
new file mode 100644
index 000000000..207fc66b0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-3.c
@@ -0,0 +1,7 @@
+/* { dg-options "-mips1 -mfix-r4000 -O2 -dp -EB" } */
+typedef unsigned int uint32_t;
+typedef unsigned long long uint64_t;
+uint32_t foo (uint32_t x, uint32_t y) { return ((uint64_t) x * y) >> 32; }
+/* ??? A highpart pattern would be a better choice, but we currently
+   don't use them.  */
+/* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-4.c
new file mode 100644
index 000000000..be32b57ae
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-4.c
@@ -0,0 +1,8 @@
+/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication
+   result to $2, which prevents the register allocators from storing the
+   multiplication result in $2.  */
+/* { dg-options "-mips1 -mfix-r4000 -O2 -fno-split-wide-types -dp -EL" } */
+typedef int int32_t;
+typedef long long int64_t;
+int64_t foo (int32_t x, int32_t y) { return (int64_t) x * y; }
+/* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-5.c
new file mode 100644
index 000000000..c14e949f2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-5.c
@@ -0,0 +1,8 @@
+/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication
+   result to $2, which prevents the register allocators from storing the
+   multiplication result in $2.  */
+/* { dg-options "-mips1 -mfix-r4000 -O2 -fno-split-wide-types -dp -EL" } */
+typedef unsigned int uint32_t;
+typedef unsigned long long uint64_t;
+uint64_t foo (uint32_t x, uint32_t y) { return (uint64_t) x * y; }
+/* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-6.c
new file mode 100644
index 000000000..32861f975
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-6.c
@@ -0,0 +1,6 @@
+/* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -O2 -dp" } */
+typedef long long int64_t;
+typedef unsigned long long uint64_t;
+int64_t foo (int64_t x, int64_t y) { return x * y; }
+uint64_t bar (uint64_t x, uint64_t y) { return x * y; }
+/* { dg-final { scan-assembler-times "[concat {\tdmult\t\$[45],\$[45][^\n]+muldi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-7.c
new file mode 100644
index 000000000..2555d5306
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-7.c
@@ -0,0 +1,7 @@
+/* { dg-options "-march=r4000 -mfix-r4000 -O2 -mgp64 -dp -EB" } */
+typedef long long int64_t;
+typedef int int128_t __attribute__((mode(TI)));
+int64_t foo (int64_t x, int64_t y) { return ((int128_t) x * y) >> 64; }
+/* ??? A highpart pattern would be a better choice, but we currently
+   don't use them.  */
+/* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-8.c
new file mode 100644
index 000000000..964dc2222
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-8.c
@@ -0,0 +1,7 @@
+/* { dg-options "-march=r4000 -mfix-r4000 -O2 -mgp64 -dp -EB" } */
+typedef unsigned long long uint64_t;
+typedef unsigned int uint128_t __attribute__((mode(TI)));
+uint64_t foo (uint64_t x, uint64_t y) { return ((uint128_t) x * y) >> 64; }
+/* ??? A highpart pattern would be a better choice, but we currently
+   don't use them.  */
+/* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-9.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-9.c
new file mode 100644
index 000000000..68724eb37
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-r4000-9.c
@@ -0,0 +1,8 @@
+/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication
+   result to $2, which prevents the register allocators from storing the
+   multiplication result in $2.  */
+/* { dg-options "-mips3 -mfix-r4000 -mgp64 -O2 -fno-split-wide-types -dp -EL" } */
+typedef long long int64_t;
+typedef int int128_t __attribute__((mode(TI)));
+int128_t foo (int64_t x, int64_t y) { return (int128_t) x * y; }
+/* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-vr4130-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-vr4130-1.c
new file mode 100644
index 000000000..f4eb492e4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-vr4130-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=vr4130 -mfix-vr4130" } */
+NOMIPS16 unsigned int
+foo (unsigned int x, unsigned int y)
+{
+  return x % y;
+}
+/* { dg-final { scan-assembler "\tmacchi\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-vr4130-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-vr4130-2.c
new file mode 100644
index 000000000..18708cb45
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-vr4130-2.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-march=vr4130 -mfix-vr4130" } */
+NOMIPS16 int foo (void) { int r; asm ("# foo" : "=l" (r)); return r; }
+/* { dg-final { scan-assembler "\tmacc\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-vr4130-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-vr4130-3.c
new file mode 100644
index 000000000..d3399d10c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-vr4130-3.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=vr4130 -mgp64 -mfix-vr4130" } */
+NOMIPS16 unsigned long long
+foo (unsigned long long x, unsigned long long y)
+{
+  return x % y;
+}
+/* { dg-final { scan-assembler "\tdmacchi\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-vr4130-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-vr4130-4.c
new file mode 100644
index 000000000..8b307c6e6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fix-vr4130-4.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=vr4130 -mgp64 -mfix-vr4130" } */
+NOMIPS16 long long
+foo (void)
+{
+  long long r;
+  asm ("# foo" : "=l" (r));
+  return r;
+}
+/* { dg-final { scan-assembler "\tdmacc\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fixed-scalar-type.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fixed-scalar-type.c
new file mode 100644
index 000000000..b4734f4d5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fixed-scalar-type.c
@@ -0,0 +1,217 @@
+/* Test scalar fixed-point instructions */
+/* { dg-do compile { target { fixed_point } } } */
+/* { dg-options "-mdspr2 -O2" } */
+/* { dg-final { scan-assembler-times "\taddu\t" 10 } } */
+/* { dg-final { scan-assembler-times "\tsubu\t" 10 } } */
+/* { dg-final { scan-assembler "\taddu_s.qb\t" } } */
+/* { dg-final { scan-assembler-times "\taddu_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\taddq_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\taddq_s.w\t" 2 } } */
+/* { dg-final { scan-assembler "\tsubu_s.qb\t" } } */
+/* { dg-final { scan-assembler-times "\tsubu_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tsubq_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tsubq_s.w\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmulq_rs.ph\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tmulq_rs.w\t" 1 } } */
+
+short _Fract non_sat_test1 (short _Fract a, short _Fract b)
+{
+  return a + b;
+}
+
+_Fract non_sat_test2 (_Fract a, _Fract b)
+{
+  return a + b;
+}
+
+long _Fract non_sat_test3 (long _Fract a, long _Fract b)
+{
+  return a + b;
+}
+
+unsigned short _Fract non_sat_test4 (unsigned short _Fract a,
+				     unsigned short _Fract b)
+{
+  return a + b;
+}
+
+unsigned _Fract non_sat_test5 (unsigned _Fract a, unsigned _Fract b)
+{
+  return a + b;
+}
+
+unsigned long _Fract non_sat_test6 (unsigned long _Fract a,
+				    unsigned long _Fract b)
+{
+  return a + b;
+}
+
+short _Accum non_sat_test7 (short _Accum a, short _Accum b)
+{
+  return a + b;
+}
+
+_Accum non_sat_test8 (_Accum a, _Accum b)
+{
+  return a + b;
+}
+
+unsigned short _Accum non_sat_test9 (unsigned short _Accum a,
+				     unsigned short _Accum b)
+{
+  return a + b;
+}
+
+unsigned _Accum non_sat_test10 (unsigned _Accum a, unsigned _Accum b)
+{
+  return a + b;
+}
+
+short _Fract non_sat_test11 (short _Fract a, short _Fract b)
+{
+  return a - b;
+}
+
+_Fract non_sat_test12 (_Fract a, _Fract b)
+{
+  return a - b;
+}
+
+long _Fract non_sat_test13 (long _Fract a, long _Fract b)
+{
+  return a - b;
+}
+
+unsigned short _Fract non_sat_test14 (unsigned short _Fract a,
+				      unsigned short _Fract b)
+{
+  return a - b;
+}
+
+unsigned _Fract non_sat_test15 (unsigned _Fract a, unsigned _Fract b)
+{
+  return a - b;
+}
+
+unsigned long _Fract non_sat_test16 (unsigned long _Fract a,
+				     unsigned long _Fract b)
+{
+  return a - b;
+}
+
+short _Accum non_sat_test17 (short _Accum a, short _Accum b)
+{
+  return a - b;
+}
+
+_Accum non_sat_test18 (_Accum a, _Accum b)
+{
+  return a - b;
+}
+
+unsigned short _Accum non_sat_test19 (unsigned short _Accum a,
+				      unsigned short _Accum b)
+{
+  return a - b;
+}
+
+unsigned _Accum non_sat_test20 (unsigned _Accum a, unsigned _Accum b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat unsigned short _Fract test1 (_Sat unsigned short _Fract a,
+					   _Sat unsigned short _Fract b)
+{
+  return a + b;
+}
+
+NOMIPS16 _Sat unsigned _Fract test2 (_Sat unsigned  _Fract a,
+				     _Sat unsigned _Fract b)
+{
+  return a + b;
+}
+
+NOMIPS16 _Sat unsigned short _Accum test3 (_Sat unsigned short _Accum a,
+					   _Sat unsigned short _Accum b)
+{
+  return a + b;
+}
+
+NOMIPS16 _Sat _Fract test4 (_Sat _Fract a, _Sat _Fract b)
+{
+  return a + b;
+}
+
+NOMIPS16 _Sat long _Fract test5 (_Sat long _Fract a, _Sat long _Fract b)
+{
+  return a + b;
+}
+
+NOMIPS16 _Sat short _Accum test6 (_Sat short _Accum a, _Sat short _Accum b)
+{
+  return a + b;
+}
+
+NOMIPS16 _Sat _Accum test7 (_Sat _Accum a, _Sat _Accum b)
+{
+  return a + b;
+}
+
+NOMIPS16 _Sat unsigned short _Fract test8 (_Sat unsigned short _Fract a,
+					   _Sat unsigned short _Fract b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat unsigned _Fract test9 (_Sat unsigned  _Fract a,
+				     _Sat unsigned _Fract b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat unsigned short _Accum test10 (_Sat unsigned short _Accum a,
+					    _Sat unsigned short _Accum b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat _Fract test11 (_Sat _Fract a, _Sat _Fract b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat long _Fract test12 (_Sat long _Fract a, _Sat long _Fract b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat short _Accum test13 (_Sat short _Accum a, _Sat short _Accum b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat _Accum test14 (_Sat _Accum a, _Sat _Accum b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat _Fract test15 (_Sat _Fract a, _Sat _Fract b)
+{
+  return a * b;
+}
+
+NOMIPS16 _Sat long _Fract test16 (_Sat long _Fract a, _Sat long _Fract b)
+{
+  return a * b;
+}
+
+NOMIPS16 _Fract test17 (_Fract a, _Fract b)
+{
+  return a * b;
+}
+
+NOMIPS16 long _Fract test18 (long _Fract a, long _Fract b)
+{
+  return a * b;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fixed-vector-type.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fixed-vector-type.c
new file mode 100644
index 000000000..9b6770479
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fixed-vector-type.c
@@ -0,0 +1,132 @@
+/* Test vector fixed-point instructions */
+/* { dg-do compile { target { fixed_point } } } */
+/* { dg-options "-mdspr2 -O2" } */
+/* { dg-final { scan-assembler-times "\taddq_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tsubq_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\taddu_s.qb\t" 1 } } */
+/* { dg-final { scan-assembler-times "\taddu_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tsubu_s.qb\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tsubu_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmulq_rs.ph\t" 1 } } */
+
+typedef _Sat unsigned short _Fract sat_v4uqq __attribute__ ((vector_size(4)));
+typedef _Sat unsigned _Fract sat_v2uhq __attribute__ ((vector_size(4)));
+typedef _Sat unsigned short _Accum sat_v2uha __attribute__ ((vector_size(4)));
+typedef _Sat _Fract sat_v2hq __attribute__ ((vector_size(4)));
+typedef _Sat short _Accum sat_v2ha __attribute__ ((vector_size(4)));
+
+typedef unsigned short _Fract v4uqq __attribute__ ((vector_size(4)));
+typedef unsigned _Fract v2uhq __attribute__ ((vector_size(4)));
+typedef unsigned short _Accum v2uha __attribute__ ((vector_size(4)));
+typedef _Fract v2hq __attribute__ ((vector_size(4)));
+typedef short _Accum v2ha __attribute__ ((vector_size(4)));
+
+NOMIPS16 sat_v2hq test1 (sat_v2hq a, sat_v2hq b)
+{
+  return a + b;
+}
+
+NOMIPS16 sat_v2ha test2 (sat_v2ha a, sat_v2ha b)
+{
+  return a + b;
+}
+
+NOMIPS16 sat_v2hq test3 (sat_v2hq a, sat_v2hq b)
+{
+  return a - b;
+}
+
+NOMIPS16 sat_v2ha test4 (sat_v2ha a, sat_v2ha b)
+{
+  return a - b;
+}
+
+NOMIPS16 sat_v4uqq test5 (sat_v4uqq a, sat_v4uqq b)
+{
+  return a + b;
+}
+
+NOMIPS16 sat_v2uhq test6 (sat_v2uhq a, sat_v2uhq b)
+{
+  return a + b;
+}
+
+NOMIPS16 sat_v2uha test7 (sat_v2uha a, sat_v2uha b)
+{
+  return a + b;
+}
+
+NOMIPS16 sat_v4uqq test8 (sat_v4uqq a, sat_v4uqq b)
+{
+  return a - b;
+}
+
+NOMIPS16 sat_v2uhq test9 (sat_v2uhq a, sat_v2uhq b)
+{
+  return a - b;
+}
+
+NOMIPS16 sat_v2uha test10 (sat_v2uha a, sat_v2uha b)
+{
+  return a - b;
+}
+
+NOMIPS16 sat_v2hq test11 (sat_v2hq a, sat_v2hq b)
+{
+  return a * b;
+}
+
+NOMIPS16 v2hq test12 (v2hq a, v2hq b)
+{
+  return a + b;
+}
+
+NOMIPS16 v2hq test13 (v2hq a, v2hq b)
+{
+  return a - b;
+}
+
+NOMIPS16 v2hq test14 (v2hq a, v2hq b)
+{
+  return a * b;
+}
+
+NOMIPS16 v2ha test15 (v2ha a, v2ha b)
+{
+  return a + b;
+}
+
+NOMIPS16 v2ha test16 (v2ha a, v2ha b)
+{
+  return a - b;
+}
+
+NOMIPS16 v4uqq test17 (v4uqq a, v4uqq b)
+{
+  return a + b;
+}
+
+NOMIPS16 v4uqq test18 (v4uqq a, v4uqq b)
+{
+  return a - b;
+}
+
+NOMIPS16 v2uhq test19 (v2uhq a, v2uhq b)
+{
+  return a + b;
+}
+
+NOMIPS16 v2uhq test20 (v2uhq a, v2uhq b)
+{
+  return a - b;
+}
+
+NOMIPS16 v2uha test21 (v2uha a, v2uha b)
+{
+  return a + b;
+}
+
+NOMIPS16 v2uha test22 (v2uha a, v2uha b)
+{
+  return a - b;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpcmp-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpcmp-1.c
new file mode 100644
index 000000000..cae48a0e9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpcmp-1.c
@@ -0,0 +1,6 @@
+/* We used to use c.lt.fmt instead of c.ule.fmt here.  */
+/* { dg-options "-mhard-float -O2" } */
+NOMIPS16 int f1 (float x, float y) { return __builtin_isless (x, y); }
+NOMIPS16 int f2 (double x, double y) { return __builtin_isless (x, y); }
+/* { dg-final { scan-assembler "c\\.ule\\.s" } } */
+/* { dg-final { scan-assembler "c\\.ule\\.d" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpcmp-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpcmp-2.c
new file mode 100644
index 000000000..3e1c259f8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpcmp-2.c
@@ -0,0 +1,6 @@
+/* We used to use c.le.fmt instead of c.ult.fmt here.  */
+/* { dg-options "-mhard-float -O2" } */
+NOMIPS16 int f1 (float x, float y) { return __builtin_islessequal (x, y); }
+NOMIPS16 int f2 (double x, double y) { return __builtin_islessequal (x, y); }
+/* { dg-final { scan-assembler "c\\.ult\\.s" } } */
+/* { dg-final { scan-assembler "c\\.ult\\.d" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-1.c
new file mode 100644
index 000000000..92977e04e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-1.c
@@ -0,0 +1,26 @@
+/* { dg-options "-mabi=32 -mhard-float -mips1 -O2 -EL" } */
+
+NOMIPS16 void
+foo (double d, double *x)
+{
+  *x = d;
+}
+
+NOMIPS16 double
+bar (double d)
+{
+  register double l1 asm ("$8") = d;
+  register double l2 asm ("$f20") = 0.0;
+  asm ("#foo" : "=d" (l1) : "d" (l1));
+  asm volatile ("#foo" :: "f" (l2));
+  return l1;
+}
+
+/* { dg-final { scan-assembler "\tswc1\t\\\$f12,0\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tswc1\t\\\$f13,4\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tmfc1\t\\\$8,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tmfc1\t\\\$9,\\\$f13\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f21\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$8,\\\$f0\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$9,\\\$f1\n" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-2.c
new file mode 100644
index 000000000..3f4f833ba
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-2.c
@@ -0,0 +1,26 @@
+/* { dg-options "-mabi=32 -mhard-float -mips1 -O2 -EB" } */
+
+NOMIPS16 void
+foo (double d, double *x)
+{
+  *x = d;
+}
+
+NOMIPS16 double
+bar (double d)
+{
+  register double l1 asm ("$8") = d;
+  register double l2 asm ("$f20") = 0.0;
+  asm ("#foo" : "=d" (l1) : "d" (l1));
+  asm volatile ("#foo" :: "f" (l2));
+  return l1;
+}
+
+/* { dg-final { scan-assembler "\tswc1\t\\\$f12,4\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tswc1\t\\\$f13,0\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tmfc1\t\\\$9,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tmfc1\t\\\$8,\\\$f13\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f21\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$9,\\\$f0\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$8,\\\$f1\n" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-3.c
new file mode 100644
index 000000000..34784d01c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-3.c
@@ -0,0 +1,18 @@
+/* { dg-options "-mabi=32 -mfp64 -O2 -EL" } */
+
+NOMIPS16 double
+foo (double d)
+{
+  register double l1 asm ("$8") = d;
+  register double l2 asm ("$f20") = 0.0;
+  asm ("#foo" : "=d" (l1) : "d" (l1));
+  asm volatile ("#foo" :: "f" (l2));
+  return l1;
+}
+
+/* { dg-final { scan-assembler "\tmfc1\t\\\$8,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tmfhc1\t\\\$9,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tmthc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$8,\\\$f0\n" } } */
+/* { dg-final { scan-assembler "\tmthc1\t\\\$9,\\\$f0\n" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-4.c
new file mode 100644
index 000000000..282cf761b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-4.c
@@ -0,0 +1,18 @@
+/* { dg-options "-mabi=32 -mfp64 -O2 -EB" } */
+
+NOMIPS16 double
+foo (double d)
+{
+  register double l1 asm ("$8") = d;
+  register double l2 asm ("$f20") = 0.0;
+  asm ("#foo" : "=d" (l1) : "d" (l1));
+  asm volatile ("#foo" :: "f" (l2));
+  return l1;
+}
+
+/* { dg-final { scan-assembler "\tmfc1\t\\\$9,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tmfhc1\t\\\$8,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tmthc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$9,\\\$f0\n" } } */
+/* { dg-final { scan-assembler "\tmthc1\t\\\$8,\\\$f0\n" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-5.c
new file mode 100644
index 000000000..848e5ea25
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-5.c
@@ -0,0 +1,33 @@
+/* { dg-options "-mabi=64 -mhard-float -O2 -EL" } */
+
+NOMIPS16 void
+foo (long double d, long double *x)
+{
+  *x = d;
+}
+
+NOMIPS16 long double
+bar (long double d, long double *x)
+{
+  register long double l1 asm ("$8") = d;
+  register long double l2 asm ("$10") = x[1];
+  register long double l3 asm ("$f20") = 0.0;
+  asm ("#foo" : "=d" (l1) : "d" (l1));
+  asm ("#foo" : "=d" (l2) : "d" (l2));
+  asm volatile ("#foo" :: "f" (l3));
+  x[1] = l1;
+  return l2;
+}
+
+/* { dg-final { scan-assembler "\tsdc1\t\\\$f12,0\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tsdc1\t\\\$f13,8\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tdmfc1\t\\\$8,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tdmfc1\t\\\$9,\\\$f13\n" } } */
+/* { dg-final { scan-assembler "\tld\t\\\$10,16\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tld\t\\\$11,24\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$0,\\\$f21\n" } } */
+/* { dg-final { scan-assembler "\tsd\t\\\$8,16\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tsd\t\\\$9,24\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$10,\\\$f0\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$11,\\\$f2\n" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-6.c
new file mode 100644
index 000000000..7f2611397
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-6.c
@@ -0,0 +1,33 @@
+/* { dg-options "-mabi=64 -mhard-float -O2 -EB" } */
+
+NOMIPS16 void
+foo (long double d, long double *x)
+{
+  *x = d;
+}
+
+NOMIPS16 long double
+bar (long double d, long double *x)
+{
+  register long double l1 asm ("$8") = d;
+  register long double l2 asm ("$10") = x[1];
+  register long double l3 asm ("$f20") = 0.0;
+  asm ("#foo" : "=d" (l1) : "d" (l1));
+  asm ("#foo" : "=d" (l2) : "d" (l2));
+  asm volatile ("#foo" :: "f" (l3));
+  x[1] = l1;
+  return l2;
+}
+
+/* { dg-final { scan-assembler "\tsdc1\t\\\$f12,0\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tsdc1\t\\\$f13,8\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tdmfc1\t\\\$8,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tdmfc1\t\\\$9,\\\$f13\n" } } */
+/* { dg-final { scan-assembler "\tld\t\\\$10,16\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tld\t\\\$11,24\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$0,\\\$f21\n" } } */
+/* { dg-final { scan-assembler "\tsd\t\\\$8,16\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tsd\t\\\$9,24\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$10,\\\$f0\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$11,\\\$f2\n" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-7.c
new file mode 100644
index 000000000..3abd10417
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-7.c
@@ -0,0 +1,36 @@
+/* { dg-options "(-mips16) -mabi=64 -O2 -EL" } */
+
+extern long double g[16];
+extern unsigned char gstuff[0x10000];
+
+NOMIPS16 long double
+foo (long double i1, long double i2, long double i3, long double i4,
+     long double *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = 1.0;
+  x[3] = g[4];
+  x[4] = *(long double *) (lstuff + 0x7fff);
+  return *(long double *) (gstuff + 0x7fff);
+}
+
+MIPS16 long double
+bar (long double i1, long double i2, long double i3, long double i4,
+     long double *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = 1.0;
+  x[3] = g[4];
+  x[4] = *(long double *) (lstuff + 0x7fff);
+  return *(long double *) (gstuff + 0x7fff);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-8.c
new file mode 100644
index 000000000..8b6901b7f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/fpr-moves-8.c
@@ -0,0 +1,36 @@
+/* { dg-options "(-mips16) -mabi=64 -O2 -EB" } */
+
+extern long double g[16];
+extern unsigned char gstuff[0x10000];
+
+NOMIPS16 long double
+foo (long double i1, long double i2, long double i3, long double i4,
+     long double *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = 1.0;
+  x[3] = g[4];
+  x[4] = *(long double *) (lstuff + 0x7fff);
+  return *(long double *) (gstuff + 0x7fff);
+}
+
+MIPS16 long double
+bar (long double i1, long double i2, long double i3, long double i4,
+     long double *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = 1.0;
+  x[3] = g[4];
+  x[4] = *(long double *) (lstuff + 0x7fff);
+  return *(long double *) (gstuff + 0x7fff);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-1.c
new file mode 100644
index 000000000..74df7de14
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-1.c
@@ -0,0 +1,22 @@
+/* { dg-do preprocess } */
+/* { dg-options "isa>=2 -mgp32" } */
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-2.c
new file mode 100644
index 000000000..3a03ba349
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-2.c
@@ -0,0 +1,22 @@
+/* { dg-do preprocess } */
+/* { dg-options "-mgp64" } */
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-3.c
new file mode 100644
index 000000000..b47a2ceb2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-3.c
@@ -0,0 +1,21 @@
+/* { dg-options "isa>=2 -mgp32 -mips16" } */
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-4.c
new file mode 100644
index 000000000..78a12440a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-4.c
@@ -0,0 +1,21 @@
+/* { dg-options "-mgp64 -mips16" } */
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/ins-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/ins-1.c
new file mode 100644
index 000000000..9e19354d1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/ins-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O isa_rev>=2 -mgp32" } */
+/* { dg-final { scan-assembler "\tins\t" } } */
+
+struct
+{
+  unsigned int i : 2;
+  unsigned int j : 3;
+  unsigned int k : 4;
+} s;
+
+NOMIPS16 void
+foo (void)
+{
+  s.j = 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/ins-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/ins-2.c
new file mode 100644
index 000000000..a71e6c053
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/ins-2.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O -meb isa_rev>=2 -mgp64" } */
+/* { dg-final { scan-assembler-times "\tins\t|\tdins\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tsll\t|\tins\t" 1 } } */
+
+/* When inserting something into the top bit of a 32-bit structure,
+   we must make sure that the register remains properly sign-extended.
+   There are two ways of doing this:
+ 
+     - use purely 32-bit bit manipulations (a single INS, matched twice here).
+     - use a 64-bit bit manipulation (DINS), and sign-extend the result.  We
+     check for this extension using SLL.  */
+
+struct s
+{
+  int a:3;
+  int b:29;
+};
+
+NOMIPS16 void
+f (int a)
+{
+  struct s s;
+  asm volatile ("" : "=r"(s));
+  s.a = a;
+  asm volatile ("" :: "r"(s));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/int-moves-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/int-moves-1.c
new file mode 100644
index 000000000..485555c39
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/int-moves-1.c
@@ -0,0 +1,38 @@
+/* { dg-options "(-mips16) -mgp64 -O2 -EL" } */
+
+typedef unsigned uint128_t __attribute__((mode(TI)));
+
+extern uint128_t g[16];
+extern unsigned char gstuff[0x10000];
+
+NOMIPS16 uint128_t
+foo (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4,
+     uint128_t *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL;
+  x[3] = g[4];
+  x[4] = *(uint128_t *) (lstuff + 0x7fff);
+  return *(uint128_t *) (gstuff + 0x7fff);
+}
+
+MIPS16 uint128_t
+bar (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4,
+     uint128_t *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL;
+  x[3] = g[4];
+  x[4] = *(uint128_t *) (lstuff + 0x7fff);
+  return *(uint128_t *) (gstuff + 0x7fff);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/int-moves-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/int-moves-2.c
new file mode 100644
index 000000000..eba798370
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/int-moves-2.c
@@ -0,0 +1,38 @@
+/* { dg-options "(-mips16) -mgp64 -O2 -EB" } */
+
+typedef unsigned uint128_t __attribute__((mode(TI)));
+
+extern uint128_t g[16];
+extern unsigned char gstuff[0x10000];
+
+NOMIPS16 uint128_t
+foo (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4,
+     uint128_t *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL;
+  x[3] = g[4];
+  x[4] = *(uint128_t *) (lstuff + 0x7fff);
+  return *(uint128_t *) (gstuff + 0x7fff);
+}
+
+MIPS16 uint128_t
+bar (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4,
+     uint128_t *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL;
+  x[3] = g[4];
+  x[4] = *(uint128_t *) (lstuff + 0x7fff);
+  return *(uint128_t *) (gstuff + 0x7fff);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/inter/mips16-inter.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/inter/mips16-inter.exp
new file mode 100644
index 000000000..45e0c5ebc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/inter/mips16-inter.exp
@@ -0,0 +1,54 @@
+# Run compatibility tests in which the "alt" compiler tries to force
+# MIPS16 mode.
+
+# We can only guarantee MIPS16 runtime support for certain targets.
+if { ![istarget mipsisa*-*-elf*] && ![istarget mips64vr*-*-elf*] } {
+    return
+}
+
+load_lib gcc-dg.exp
+
+# Check whether the flags are compatible with MIPS16 code generation.
+if { ![check_effective_target_mips16_attribute] } {
+    return
+}
+
+# Save the old value of CFLAGS_FOR_TARGET, if any.
+global saved_CFLAGS_FOR_TARGET
+if { [info exists CFLAGS_FOR_TARGET] } {
+    set saved_CFLAGS_FOR_TARGET $CFLAGS_FOR_TARGET
+} else {
+    unset -nocomplain saved_CFLAGS_FOR_TARGET
+}
+
+# The "alt" compiler is the normal compiler with an extra "-mips16" argument.
+proc compat-use-alt-compiler { } {
+    global saved_CFLAGS_FOR_TARGET CFLAGS_FOR_TARGET
+
+    if { [info exists saved_CFLAGS_FOR_TARGET] } {
+	set CFLAGS_FOR_TARGET [concat $saved_CFLAGS_FOR_TARGET "-mips16"]
+    } else {
+	set CFLAGS_FOR_TARGET "-mips16"
+    }
+}
+
+# Make the compiler under test the default.
+proc compat-use-tst-compiler { } {
+    global saved_CFLAGS_FOR_TARGET CFLAGS_FOR_TARGET
+
+    if { [info exists saved_CFLAGS_FOR_TARGET] } {
+	set CFLAGS_FOR_TARGET $saved_CFLAGS_FOR_TARGET
+    } else {
+	unset -nocomplain CFLAGS_FOR_TARGET
+    }
+}
+
+load_lib compat.exp
+
+gcc_init
+foreach src [lsort [find $srcdir/$subdir mips16_*_main.c]] {
+    if { [runtest_file_p $runtests $src] } {
+	compat-execute $src "mips16_inter" 1
+    }
+}
+compat-use-tst-compiler
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_main.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_main.c
new file mode 100644
index 000000000..df18c7670
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_main.c
@@ -0,0 +1,10 @@
+extern void init (void);
+extern void test (void);
+
+int
+main (void)
+{
+  init ();
+  test ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_x.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_x.c
new file mode 100644
index 000000000..076b399a3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_x.c
@@ -0,0 +1,176 @@
+#include <stdlib.h>
+
+/* All the function pointers are declared and initialized in
+   mips16-stubs-2.c.  */
+
+extern double the_result;
+
+extern void v0 (void);
+extern void v1 (float);
+extern void v5 (float, float);
+extern void v9 (float, double);
+extern void v2 (double);
+extern void v6 (double, float);
+extern void v10 (double, double);
+
+extern float f0 (void);
+extern float f1 (float);
+extern float f5 (float, float);
+extern float f9 (float, double);
+extern float f2 (double);
+extern float f6 (double, float);
+extern float f10 (double, double);
+
+extern double d0 (void);
+extern double d1 (float);
+extern double d5 (float, float);
+extern double d9 (float, double);
+extern double d2 (double);
+extern double d6 (double, float);
+extern double d10 (double, double);
+
+extern _Complex float cf0 (void);
+extern _Complex float cf1 (float);
+extern _Complex float cf5 (float, float);
+extern _Complex float cf9 (float, double);
+extern _Complex float cf2 (double);
+extern _Complex float cf6 (double, float);
+extern _Complex float cf10 (double, double);
+
+extern _Complex double cd0 (void);
+extern _Complex double cd1 (float);
+extern _Complex double cd5 (float, float);
+extern _Complex double cd9 (float, double);
+extern _Complex double cd2 (double);
+extern _Complex double cd6 (double, float);
+extern _Complex double cd10 (double, double);
+
+extern void (*pv0) (void);
+extern void (*pv1) (float);
+extern void (*pv5) (float, float);
+extern void (*pv9) (float, double);
+extern void (*pv2) (double);
+extern void (*pv6) (double, float);
+extern void (*pv10) (double, double);
+
+extern float (*pf0) (void);
+extern float (*pf1) (float);
+extern float (*pf5) (float, float);
+extern float (*pf9) (float, double);
+extern float (*pf2) (double);
+extern float (*pf6) (double, float);
+extern float (*pf10) (double, double);
+
+extern double (*pd0) (void);
+extern double (*pd1) (float);
+extern double (*pd5) (float, float);
+extern double (*pd9) (float, double);
+extern double (*pd2) (double);
+extern double (*pd6) (double, float);
+extern double (*pd10) (double, double);
+
+extern _Complex float (*pcf0) (void);
+extern _Complex float (*pcf1) (float);
+extern _Complex float (*pcf5) (float, float);
+extern _Complex float (*pcf9) (float, double);
+extern _Complex float (*pcf2) (double);
+extern _Complex float (*pcf6) (double, float);
+extern _Complex float (*pcf10) (double, double);
+
+extern _Complex double (*pcd0) (void);
+extern _Complex double (*pcd1) (float);
+extern _Complex double (*pcd5) (float, float);
+extern _Complex double (*pcd9) (float, double);
+extern _Complex double (*pcd2) (double);
+extern _Complex double (*pcd6) (double, float);
+extern _Complex double (*pcd10) (double, double);
+
+/* Macros for results checking.  */
+#define CHECK_RESULT(x, y) if ((x) != (y)) abort ()
+#define CHECK_VOID_RESULT(x, y)  CHECK_RESULT (((x), the_result), y)
+
+/* Call functions through pointers and and check against expected results.  */
+void
+test (void)
+{
+
+  CHECK_VOID_RESULT (v0 (), 1.0);
+  CHECK_VOID_RESULT (v1 (1.0), 2.0);
+  CHECK_VOID_RESULT (v5 (5.0, 6.0), 12.0);
+  CHECK_VOID_RESULT (v9 (9.0, 10.0), 20.0);
+  CHECK_VOID_RESULT (v2 (2.0), 3.0);
+  CHECK_VOID_RESULT (v6 (6.0, 7.0), 14.0);
+  CHECK_VOID_RESULT (v10 (10.0, 11.0), 22.0);
+
+  CHECK_RESULT (f0 (), 1.0);
+  CHECK_RESULT (f1 (1.0), 2.0);
+  CHECK_RESULT (f5 (5.0, 6.0), 12.0);
+  CHECK_RESULT (f9 (9.0, 10.0), 20.0);
+  CHECK_RESULT (f2 (2.0), 3.0);
+  CHECK_RESULT (f6 (6.0, 7.0), 14.0);
+  CHECK_RESULT (f10 (10.0, 11.0), 22.0);
+
+  CHECK_RESULT (d0 (), 1.0);
+  CHECK_RESULT (d1 (1.0), 2.0);
+  CHECK_RESULT (d5 (5.0, 6.0), 12.0);
+  CHECK_RESULT (d9 (9.0, 10.0), 20.0);
+  CHECK_RESULT (d2 (2.0), 3.0);
+  CHECK_RESULT (d6 (6.0, 7.0), 14.0);
+  CHECK_RESULT (d10 (10.0, 11.0), 22.0);
+
+  CHECK_RESULT (cf0 (), 1.0 + 0.0i);
+  CHECK_RESULT (cf1 (1.0), 2.0 + 1.0i);
+  CHECK_RESULT (cf5 (5.0, 6.0), 12.0 + 5.0i);
+  CHECK_RESULT (cf9 (9.0, 10.0), 20.0 + 9.0i);
+  CHECK_RESULT (cf2 (2.0), 3.0 + 2.0i);
+  CHECK_RESULT (cf6 (6.0, 7.0), 14.0 + 6.0i);
+  CHECK_RESULT (cf10 (10.0, 11.0), 22.0 + 10.0i);
+
+  CHECK_RESULT (cd0 (), 1.0 + 0.0i);
+  CHECK_RESULT (cd1 (1.0), 2.0 + 1.0i);
+  CHECK_RESULT (cd5 (5.0, 6.0), 12.0 + 5.0i);
+  CHECK_RESULT (cd9 (9.0, 10.0), 20.0 + 9.0i);
+  CHECK_RESULT (cd2 (2.0), 3.0 + 2.0i);
+  CHECK_RESULT (cd6 (6.0, 7.0), 14.0 + 6.0i);
+  CHECK_RESULT (cd10 (10.0, 11.0), 22.0 + 10.0i);
+
+  CHECK_VOID_RESULT ((*pv0) (), 1.0);
+  CHECK_VOID_RESULT ((*pv1) (1.0), 2.0);
+  CHECK_VOID_RESULT ((*pv5) (5.0, 6.0), 12.0);
+  CHECK_VOID_RESULT ((*pv9) (9.0, 10.0), 20.0);
+  CHECK_VOID_RESULT ((*pv2) (2.0), 3.0);
+  CHECK_VOID_RESULT ((*pv6) (6.0, 7.0), 14.0);
+  CHECK_VOID_RESULT ((*pv10) (10.0, 11.0), 22.0);
+
+  CHECK_RESULT ((*pf0) (), 1.0);
+  CHECK_RESULT ((*pf1) (1.0), 2.0);
+  CHECK_RESULT ((*pf5) (5.0, 6.0), 12.0);
+  CHECK_RESULT ((*pf9) (9.0, 10.0), 20.0);
+  CHECK_RESULT ((*pf2) (2.0), 3.0);
+  CHECK_RESULT ((*pf6) (6.0, 7.0), 14.0);
+  CHECK_RESULT ((*pf10) (10.0, 11.0), 22.0);
+
+  CHECK_RESULT ((*pd0) (), 1.0);
+  CHECK_RESULT ((*pd1) (1.0), 2.0);
+  CHECK_RESULT ((*pd5) (5.0, 6.0), 12.0);
+  CHECK_RESULT ((*pd9) (9.0, 10.0), 20.0);
+  CHECK_RESULT ((*pd2) (2.0), 3.0);
+  CHECK_RESULT ((*pd6) (6.0, 7.0), 14.0);
+  CHECK_RESULT ((*pd10) (10.0, 11.0), 22.0);
+
+  CHECK_RESULT ((*pcf0) (), 1.0 + 0.0i);
+  CHECK_RESULT ((*pcf1) (1.0), 2.0 + 1.0i);
+  CHECK_RESULT ((*pcf5) (5.0, 6.0), 12.0 + 5.0i);
+  CHECK_RESULT ((*pcf9) (9.0, 10.0), 20.0 + 9.0i);
+  CHECK_RESULT ((*pcf2) (2.0), 3.0 + 2.0i);
+  CHECK_RESULT ((*pcf6) (6.0, 7.0), 14.0 + 6.0i);
+  CHECK_RESULT ((*pcf10) (10.0, 11.0), 22.0 + 10.0i);
+
+  CHECK_RESULT ((*pcd0) (), 1.0 + 0.0i);
+  CHECK_RESULT ((*pcd1) (1.0), 2.0 + 1.0i);
+  CHECK_RESULT ((*pcd5) (5.0, 6.0), 12.0 + 5.0i);
+  CHECK_RESULT ((*pcd9) (9.0, 10.0), 20.0 + 9.0i);
+  CHECK_RESULT ((*pcd2) (2.0), 3.0 + 2.0i);
+  CHECK_RESULT ((*pcd6) (6.0, 7.0), 14.0 + 6.0i);
+  CHECK_RESULT ((*pcd10) (10.0, 11.0), 22.0 + 10.0i);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_y.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_y.c
new file mode 100644
index 000000000..b7a4d7f32
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_y.c
@@ -0,0 +1,133 @@
+/* All test functions return the sum of arguments, plus 1.
+   Void-returning functions put the result in the_result.
+   Complex-returning functions return their signature number as the
+   (constant) imaginary part of the result.  */
+
+double the_result;
+
+void v0 (void) 			{ the_result = 1.0; }
+void v1 (float x)		{ the_result = 1.0 + x; }
+void v5 (float x, float y) 	{ the_result = 1.0 + x + y; }
+void v9 (float x, double y) 	{ the_result = 1.0 + x + y; }
+void v2 (double x)		{ the_result = 1.0 + x; }
+void v6 (double x, float y)	{ the_result = 1.0 + x + y; }
+void v10 (double x, double y)  	{ the_result = 1.0 + x + y; }
+
+float f0 (void) 		{ return 1.0; }
+float f1 (float x)		{ return 1.0 + x; }
+float f5 (float x, float y) 	{ return 1.0 + x + y; }
+float f9 (float x, double y) 	{ return 1.0 + x + y; }
+float f2 (double x)		{ return 1.0 + x; }
+float f6 (double x, float y)	{ return 1.0 + x + y; }
+float f10 (double x, double y)	{ return 1.0 + x + y; }
+
+double d0 (void) 		{ return 1.0; }
+double d1 (float x)		{ return 1.0 + x; }
+double d5 (float x, float y) 	{ return 1.0 + x + y; }
+double d9 (float x, double y) 	{ return 1.0 + x + y; }
+double d2 (double x)		{ return 1.0 + x; }
+double d6 (double x, float y)	{ return 1.0 + x + y; }
+double d10 (double x, double y) { return 1.0 + x + y; }
+
+_Complex float cf0 (void) 			{ return 1.0 + 0.0i; }
+_Complex float cf1 (float x)			{ return 1.0 + x + 1.0i; }
+_Complex float cf5 (float x, float y) 		{ return 1.0 + x + y + 5.0i; }
+_Complex float cf9 (float x, double y) 		{ return 1.0 + x + y + 9.0i; }
+_Complex float cf2 (double x)			{ return 1.0 + x + 2.0i; }
+_Complex float cf6 (double x, float y)		{ return 1.0 + x + y + 6.0i; }
+_Complex float cf10 (double x, double y)	{ return 1.0 + x + y + 10.0i; }
+
+_Complex double cd0 (void) 			{ return 1.0 + 0.0i; }
+_Complex double cd1 (float x)			{ return 1.0 + x + 1.0i; }
+_Complex double cd5 (float x, float y) 		{ return 1.0 + x + y + 5.0i; }
+_Complex double cd9 (float x, double y) 	{ return 1.0 + x + y + 9.0i; }
+_Complex double cd2 (double x)			{ return 1.0 + x + 2.0i; }
+_Complex double cd6 (double x, float y)		{ return 1.0 + x + y + 6.0i; }
+_Complex double cd10 (double x, double y)	{ return 1.0 + x + y + 10.0i; }
+
+
+/* Declare and initialize all the pointer-to-function variables.  */
+
+void (*pv0) (void);
+void (*pv1) (float);
+void (*pv5) (float, float);
+void (*pv9) (float, double);
+void (*pv2) (double);
+void (*pv6) (double, float);
+void (*pv10) (double, double);
+
+float (*pf0) (void);
+float (*pf1) (float);
+float (*pf5) (float, float);
+float (*pf9) (float, double);
+float (*pf2) (double);
+float (*pf6) (double, float);
+float (*pf10) (double, double);
+
+double (*pd0) (void);
+double (*pd1) (float);
+double (*pd5) (float, float);
+double (*pd9) (float, double);
+double (*pd2) (double);
+double (*pd6) (double, float);
+double (*pd10) (double, double);
+
+_Complex float (*pcf0) (void);
+_Complex float (*pcf1) (float);
+_Complex float (*pcf5) (float, float);
+_Complex float (*pcf9) (float, double);
+_Complex float (*pcf2) (double);
+_Complex float (*pcf6) (double, float);
+_Complex float (*pcf10) (double, double);
+
+_Complex double (*pcd0) (void);
+_Complex double (*pcd1) (float);
+_Complex double (*pcd5) (float, float);
+_Complex double (*pcd9) (float, double);
+_Complex double (*pcd2) (double);
+_Complex double (*pcd6) (double, float);
+_Complex double (*pcd10) (double, double);
+
+void
+init (void)
+{
+  pv0 = v0;
+  pv1 = v1;
+  pv5 = v5;
+  pv9 = v9;
+  pv2 = v2;
+  pv6 = v6;
+  pv10 = v10;
+
+  pf0 = f0;
+  pf1 = f1;
+  pf5 = f5;
+  pf9 = f9;
+  pf2 = f2;
+  pf6 = f6;
+  pf10 = f10;
+
+  pd0 = d0;
+  pd1 = d1;
+  pd5 = d5;
+  pd9 = d9;
+  pd2 = d2;
+  pd6 = d6;
+  pd10 = d10;
+
+  pcf0 = cf0;
+  pcf1 = cf1;
+  pcf5 = cf5;
+  pcf9 = cf9;
+  pcf2 = cf2;
+  pcf6 = cf6;
+  pcf10 = cf10;
+
+  pcd0 = cd0;
+  pcd1 = cd1;
+  pcd5 = cd5;
+  pcd9 = cd9;
+  pcd2 = cd2;
+  pcd6 = cd6;
+  pcd10 = cd10;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/lazy-binding-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/lazy-binding-1.c
new file mode 100644
index 000000000..e85727c42
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/lazy-binding-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mabicalls -mshared -mexplicit-relocs -O2 -fno-delayed-branch" } */
+
+void bar (void);
+
+NOMIPS16 void
+foo (int n)
+{
+  while (n--)
+    {
+      bar ();
+      bar ();
+    }
+}
+
+/* There should be exactly five uses of $25: one to set up $gp, two to
+   load the address of bar (), and two to call it.  */
+/* { dg-final { scan-assembler-times "\tl.\t\\\$25,%call16\\\(bar\\\)" 2 } } */
+/* { dg-final { scan-assembler-times "\tjalr\t\\\$25" 2 } } */
+/* { dg-final { scan-assembler "(\\\$28,|\t.cpload\t)\\\$25" } } */
+/* { dg-final { scan-assembler-times "\\\$25" 5 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/long-calls-pg.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/long-calls-pg.c
new file mode 100644
index 000000000..5e554c497
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/long-calls-pg.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mabi=32 -pg -mno-abicalls -mlong-calls" } */
+/* { dg-final { scan-assembler-not "\tjal\t_mcount" } } */
+NOMIPS16 void
+foo (void)
+{
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/loongson-muldiv-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/loongson-muldiv-1.c
new file mode 100644
index 000000000..fd7289cea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/loongson-muldiv-1.c
@@ -0,0 +1,16 @@
+/* { dg-options "-O2 isa=loongson" } */
+
+typedef int st;
+typedef unsigned int ut;
+
+NOMIPS16 st smul (st x, st y) { return x * y; }
+NOMIPS16 st sdiv (st x, st y) { return x / y + x % y; }
+
+NOMIPS16 ut umul (ut x, ut y) { return x * y; }
+NOMIPS16 ut udiv (ut x, ut y) { return x / y + x % y; }
+
+/* { dg-final { scan-assembler-times "\tmultu.g\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tdivu.g\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tmodu.g\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tdiv.g\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tmod.g\t" 1 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/loongson-muldiv-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/loongson-muldiv-2.c
new file mode 100644
index 000000000..6f1f13875
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/loongson-muldiv-2.c
@@ -0,0 +1,16 @@
+/* { dg-options "-O2 isa=loongson -mgp64" } */
+
+typedef long long st;
+typedef unsigned long long ut;
+
+NOMIPS16 st smul (st x, st y) { return x * y; }
+NOMIPS16 st sdiv (st x, st y) { return x / y + x % y; }
+
+NOMIPS16 ut umul (ut x, ut y) { return x * y; }
+NOMIPS16 ut udiv (ut x, ut y) { return x / y + x % y; }
+
+/* { dg-final { scan-assembler-times "\tdmultu.g\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tddivu.g\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tdmodu.g\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tddiv.g\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tdmod.g\t" 1 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/loongson-simd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/loongson-simd.c
new file mode 100644
index 000000000..ae3565f47
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/loongson-simd.c
@@ -0,0 +1,1966 @@
+/* Test cases for ST Microelectronics Loongson-2E/2F SIMD intrinsics.
+   Copyright (C) 2008 Free Software Foundation, Inc.
+   Contributed by CodeSourcery.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+/* { dg-do run } */
+/* loongson.h does not handle or check for MIPS16ness.  There doesn't
+   seem any good reason for it to, given that the Loongson processors
+   do not support MIPS16.  */
+/* { dg-options "isa=loongson -mhard-float -mno-mips16 -flax-vector-conversions" } */
+
+#include "loongson.h"
+#include <stdio.h>
+#include <stdint.h>
+#include <assert.h>
+#include <limits.h>
+
+typedef union { int32x2_t v; int32_t a[2]; } int32x2_encap_t;
+typedef union { int16x4_t v; int16_t a[4]; } int16x4_encap_t;
+typedef union { int8x8_t v; int8_t a[8]; } int8x8_encap_t;
+typedef union { uint32x2_t v; uint32_t a[2]; } uint32x2_encap_t;
+typedef union { uint16x4_t v; uint16_t a[4]; } uint16x4_encap_t;
+typedef union { uint8x8_t v; uint8_t a[8]; } uint8x8_encap_t;
+
+#define UINT16x4_MAX USHRT_MAX
+#define UINT8x8_MAX UCHAR_MAX
+#define INT8x8_MAX SCHAR_MAX
+#define INT16x4_MAX SHRT_MAX
+#define INT32x2_MAX INT_MAX
+
+static void test_packsswh (void)
+{
+  int32x2_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = INT16x4_MAX - 2;
+  s.a[1] = INT16x4_MAX - 1;
+  t.a[0] = INT16x4_MAX;
+  t.a[1] = INT16x4_MAX + 1;
+  r.v = packsswh (s.v, t.v);
+  assert (r.a[0] == INT16x4_MAX - 2);
+  assert (r.a[1] == INT16x4_MAX - 1);
+  assert (r.a[2] == INT16x4_MAX);
+  assert (r.a[3] == INT16x4_MAX);
+}
+
+static void test_packsshb (void)
+{
+  int16x4_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = INT8x8_MAX - 6;
+  s.a[1] = INT8x8_MAX - 5;
+  s.a[2] = INT8x8_MAX - 4;
+  s.a[3] = INT8x8_MAX - 3;
+  t.a[0] = INT8x8_MAX - 2;
+  t.a[1] = INT8x8_MAX - 1;
+  t.a[2] = INT8x8_MAX;
+  t.a[3] = INT8x8_MAX + 1;
+  r.v = packsshb (s.v, t.v);
+  assert (r.a[0] == INT8x8_MAX - 6);
+  assert (r.a[1] == INT8x8_MAX - 5);
+  assert (r.a[2] == INT8x8_MAX - 4);
+  assert (r.a[3] == INT8x8_MAX - 3);
+  assert (r.a[4] == INT8x8_MAX - 2);
+  assert (r.a[5] == INT8x8_MAX - 1);
+  assert (r.a[6] == INT8x8_MAX);
+  assert (r.a[7] == INT8x8_MAX);
+}
+
+static void test_packushb (void)
+{
+  uint16x4_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = UINT8x8_MAX - 6;
+  s.a[1] = UINT8x8_MAX - 5;
+  s.a[2] = UINT8x8_MAX - 4;
+  s.a[3] = UINT8x8_MAX - 3;
+  t.a[0] = UINT8x8_MAX - 2;
+  t.a[1] = UINT8x8_MAX - 1;
+  t.a[2] = UINT8x8_MAX;
+  t.a[3] = UINT8x8_MAX + 1;
+  r.v = packushb (s.v, t.v);
+  assert (r.a[0] == UINT8x8_MAX - 6);
+  assert (r.a[1] == UINT8x8_MAX - 5);
+  assert (r.a[2] == UINT8x8_MAX - 4);
+  assert (r.a[3] == UINT8x8_MAX - 3);
+  assert (r.a[4] == UINT8x8_MAX - 2);
+  assert (r.a[5] == UINT8x8_MAX - 1);
+  assert (r.a[6] == UINT8x8_MAX);
+  assert (r.a[7] == UINT8x8_MAX);
+}
+
+static void test_paddw_u (void)
+{
+  uint32x2_encap_t s, t;
+  uint32x2_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 2;
+  t.a[0] = 3;
+  t.a[1] = 4;
+  r.v = paddw_u (s.v, t.v);
+  assert (r.a[0] == 4);
+  assert (r.a[1] == 6);
+}
+
+static void test_paddw_s (void)
+{
+  int32x2_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = -2;
+  s.a[1] = -1;
+  t.a[0] = 3;
+  t.a[1] = 4;
+  r.v = paddw_s (s.v, t.v);
+  assert (r.a[0] == 1);
+  assert (r.a[1] == 3);
+}
+
+static void test_paddh_u (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 2;
+  s.a[2] = 3;
+  s.a[3] = 4;
+  t.a[0] = 5;
+  t.a[1] = 6;
+  t.a[2] = 7;
+  t.a[3] = 8;
+  r.v = paddh_u (s.v, t.v);
+  assert (r.a[0] == 6);
+  assert (r.a[1] == 8);
+  assert (r.a[2] == 10);
+  assert (r.a[3] == 12);
+}
+
+static void test_paddh_s (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -10;
+  s.a[1] = -20;
+  s.a[2] = -30;
+  s.a[3] = -40;
+  t.a[0] = 1;
+  t.a[1] = 2;
+  t.a[2] = 3;
+  t.a[3] = 4;
+  r.v = paddh_s (s.v, t.v);
+  assert (r.a[0] == -9);
+  assert (r.a[1] == -18);
+  assert (r.a[2] == -27);
+  assert (r.a[3] == -36);
+}
+
+static void test_paddb_u (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 2;
+  s.a[2] = 3;
+  s.a[3] = 4;
+  s.a[4] = 5;
+  s.a[5] = 6;
+  s.a[6] = 7;
+  s.a[7] = 8;
+  t.a[0] = 9;
+  t.a[1] = 10;
+  t.a[2] = 11;
+  t.a[3] = 12;
+  t.a[4] = 13;
+  t.a[5] = 14;
+  t.a[6] = 15;
+  t.a[7] = 16;
+  r.v = paddb_u (s.v, t.v);
+  assert (r.a[0] == 10);
+  assert (r.a[1] == 12);
+  assert (r.a[2] == 14);
+  assert (r.a[3] == 16);
+  assert (r.a[4] == 18);
+  assert (r.a[5] == 20);
+  assert (r.a[6] == 22);
+  assert (r.a[7] == 24);
+}
+
+static void test_paddb_s (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -10;
+  s.a[1] = -20;
+  s.a[2] = -30;
+  s.a[3] = -40;
+  s.a[4] = -50;
+  s.a[5] = -60;
+  s.a[6] = -70;
+  s.a[7] = -80;
+  t.a[0] = 1;
+  t.a[1] = 2;
+  t.a[2] = 3;
+  t.a[3] = 4;
+  t.a[4] = 5;
+  t.a[5] = 6;
+  t.a[6] = 7;
+  t.a[7] = 8;
+  r.v = paddb_s (s.v, t.v);
+  assert (r.a[0] == -9);
+  assert (r.a[1] == -18);
+  assert (r.a[2] == -27);
+  assert (r.a[3] == -36);
+  assert (r.a[4] == -45);
+  assert (r.a[5] == -54);
+  assert (r.a[6] == -63);
+  assert (r.a[7] == -72);
+}
+
+static void test_paddd_u (void)
+{
+  uint64_t d = 123456;
+  uint64_t e = 789012;
+  uint64_t r;
+  r = paddd_u (d, e);
+  assert (r == 912468);
+}
+
+static void test_paddd_s (void)
+{
+  int64_t d = 123456;
+  int64_t e = -789012;
+  int64_t r;
+  r = paddd_s (d, e);
+  assert (r == -665556);
+}
+
+static void test_paddsh (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = 0;
+  s.a[2] = 1;
+  s.a[3] = 2;
+  t.a[0] = INT16x4_MAX;
+  t.a[1] = INT16x4_MAX;
+  t.a[2] = INT16x4_MAX;
+  t.a[3] = INT16x4_MAX;
+  r.v = paddsh (s.v, t.v);
+  assert (r.a[0] == INT16x4_MAX - 1);
+  assert (r.a[1] == INT16x4_MAX);
+  assert (r.a[2] == INT16x4_MAX);
+  assert (r.a[3] == INT16x4_MAX);
+}
+
+static void test_paddsb (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -6;
+  s.a[1] = -5;
+  s.a[2] = -4;
+  s.a[3] = -3;
+  s.a[4] = -2;
+  s.a[5] = -1;
+  s.a[6] = 0;
+  s.a[7] = 1;
+  t.a[0] = INT8x8_MAX;
+  t.a[1] = INT8x8_MAX;
+  t.a[2] = INT8x8_MAX;
+  t.a[3] = INT8x8_MAX;
+  t.a[4] = INT8x8_MAX;
+  t.a[5] = INT8x8_MAX;
+  t.a[6] = INT8x8_MAX;
+  t.a[7] = INT8x8_MAX;
+  r.v = paddsb (s.v, t.v);
+  assert (r.a[0] == INT8x8_MAX - 6);
+  assert (r.a[1] == INT8x8_MAX - 5);
+  assert (r.a[2] == INT8x8_MAX - 4);
+  assert (r.a[3] == INT8x8_MAX - 3);
+  assert (r.a[4] == INT8x8_MAX - 2);
+  assert (r.a[5] == INT8x8_MAX - 1);
+  assert (r.a[6] == INT8x8_MAX);
+  assert (r.a[7] == INT8x8_MAX);
+}
+
+static void test_paddush (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 0;
+  s.a[1] = 1;
+  s.a[2] = 0;
+  s.a[3] = 1;
+  t.a[0] = UINT16x4_MAX;
+  t.a[1] = UINT16x4_MAX;
+  t.a[2] = UINT16x4_MAX;
+  t.a[3] = UINT16x4_MAX;
+  r.v = paddush (s.v, t.v);
+  assert (r.a[0] == UINT16x4_MAX);
+  assert (r.a[1] == UINT16x4_MAX);
+  assert (r.a[2] == UINT16x4_MAX);
+  assert (r.a[3] == UINT16x4_MAX);
+}
+
+static void test_paddusb (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 0;
+  s.a[1] = 1;
+  s.a[2] = 0;
+  s.a[3] = 1;
+  s.a[4] = 0;
+  s.a[5] = 1;
+  s.a[6] = 0;
+  s.a[7] = 1;
+  t.a[0] = UINT8x8_MAX;
+  t.a[1] = UINT8x8_MAX;
+  t.a[2] = UINT8x8_MAX;
+  t.a[3] = UINT8x8_MAX;
+  t.a[4] = UINT8x8_MAX;
+  t.a[5] = UINT8x8_MAX;
+  t.a[6] = UINT8x8_MAX;
+  t.a[7] = UINT8x8_MAX;
+  r.v = paddusb (s.v, t.v);
+  assert (r.a[0] == UINT8x8_MAX);
+  assert (r.a[1] == UINT8x8_MAX);
+  assert (r.a[2] == UINT8x8_MAX);
+  assert (r.a[3] == UINT8x8_MAX);
+  assert (r.a[4] == UINT8x8_MAX);
+  assert (r.a[5] == UINT8x8_MAX);
+  assert (r.a[6] == UINT8x8_MAX);
+  assert (r.a[7] == UINT8x8_MAX);
+}
+
+static void test_pandn_ud (void)
+{
+  uint64_t d1 = 0x0000ffff0000ffffull;
+  uint64_t d2 = 0x0000ffff0000ffffull;
+  uint64_t r;
+  r = pandn_ud (d1, d2);
+  assert (r == 0);
+}
+
+static void test_pandn_sd (void)
+{
+  int64_t d1 = (int64_t) 0x0000000000000000ull;
+  int64_t d2 = (int64_t) 0xfffffffffffffffeull;
+  int64_t r;
+  r = pandn_sd (d1, d2);
+  assert (r == -2);
+}
+
+static void test_pandn_uw (void)
+{
+  uint32x2_encap_t s, t;
+  uint32x2_encap_t r;
+  s.a[0] = 0xffffffff;
+  s.a[1] = 0x00000000;
+  t.a[0] = 0x00000000;
+  t.a[1] = 0xffffffff;
+  r.v = pandn_uw (s.v, t.v);
+  assert (r.a[0] == 0x00000000);
+  assert (r.a[1] == 0xffffffff);
+}
+
+static void test_pandn_sw (void)
+{
+  int32x2_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = 0xffffffff;
+  s.a[1] = 0x00000000;
+  t.a[0] = 0xffffffff;
+  t.a[1] = 0xfffffffe;
+  r.v = pandn_sw (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == -2);
+}
+
+static void test_pandn_uh (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 0xffff;
+  s.a[1] = 0x0000;
+  s.a[2] = 0xffff;
+  s.a[3] = 0x0000;
+  t.a[0] = 0x0000;
+  t.a[1] = 0xffff;
+  t.a[2] = 0x0000;
+  t.a[3] = 0xffff;
+  r.v = pandn_uh (s.v, t.v);
+  assert (r.a[0] == 0x0000);
+  assert (r.a[1] == 0xffff);
+  assert (r.a[2] == 0x0000);
+  assert (r.a[3] == 0xffff);
+}
+
+static void test_pandn_sh (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = 0xffff;
+  s.a[1] = 0x0000;
+  s.a[2] = 0xffff;
+  s.a[3] = 0x0000;
+  t.a[0] = 0xffff;
+  t.a[1] = 0xfffe;
+  t.a[2] = 0xffff;
+  t.a[3] = 0xfffe;
+  r.v = pandn_sh (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == -2);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == -2);
+}
+
+static void test_pandn_ub (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 0xff;
+  s.a[1] = 0x00;
+  s.a[2] = 0xff;
+  s.a[3] = 0x00;
+  s.a[4] = 0xff;
+  s.a[5] = 0x00;
+  s.a[6] = 0xff;
+  s.a[7] = 0x00;
+  t.a[0] = 0x00;
+  t.a[1] = 0xff;
+  t.a[2] = 0x00;
+  t.a[3] = 0xff;
+  t.a[4] = 0x00;
+  t.a[5] = 0xff;
+  t.a[6] = 0x00;
+  t.a[7] = 0xff;
+  r.v = pandn_ub (s.v, t.v);
+  assert (r.a[0] == 0x00);
+  assert (r.a[1] == 0xff);
+  assert (r.a[2] == 0x00);
+  assert (r.a[3] == 0xff);
+  assert (r.a[4] == 0x00);
+  assert (r.a[5] == 0xff);
+  assert (r.a[6] == 0x00);
+  assert (r.a[7] == 0xff);
+}
+
+static void test_pandn_sb (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = 0xff;
+  s.a[1] = 0x00;
+  s.a[2] = 0xff;
+  s.a[3] = 0x00;
+  s.a[4] = 0xff;
+  s.a[5] = 0x00;
+  s.a[6] = 0xff;
+  s.a[7] = 0x00;
+  t.a[0] = 0xff;
+  t.a[1] = 0xfe;
+  t.a[2] = 0xff;
+  t.a[3] = 0xfe;
+  t.a[4] = 0xff;
+  t.a[5] = 0xfe;
+  t.a[6] = 0xff;
+  t.a[7] = 0xfe;
+  r.v = pandn_sb (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == -2);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == -2);
+  assert (r.a[4] == 0);
+  assert (r.a[5] == -2);
+  assert (r.a[6] == 0);
+  assert (r.a[7] == -2);
+}
+
+static void test_pavgh (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 2;
+  s.a[2] = 3;
+  s.a[3] = 4;
+  t.a[0] = 5;
+  t.a[1] = 6;
+  t.a[2] = 7;
+  t.a[3] = 8;
+  r.v = pavgh (s.v, t.v);
+  assert (r.a[0] == 3);
+  assert (r.a[1] == 4);
+  assert (r.a[2] == 5);
+  assert (r.a[3] == 6);
+}
+
+static void test_pavgb (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 2;
+  s.a[2] = 3;
+  s.a[3] = 4;
+  s.a[4] = 1;
+  s.a[5] = 2;
+  s.a[6] = 3;
+  s.a[7] = 4;
+  t.a[0] = 5;
+  t.a[1] = 6;
+  t.a[2] = 7;
+  t.a[3] = 8;
+  t.a[4] = 5;
+  t.a[5] = 6;
+  t.a[6] = 7;
+  t.a[7] = 8;
+  r.v = pavgb (s.v, t.v);
+  assert (r.a[0] == 3);
+  assert (r.a[1] == 4);
+  assert (r.a[2] == 5);
+  assert (r.a[3] == 6);
+  assert (r.a[4] == 3);
+  assert (r.a[5] == 4);
+  assert (r.a[6] == 5);
+  assert (r.a[7] == 6);
+}
+
+static void test_pcmpeqw_u (void)
+{
+  uint32x2_encap_t s, t;
+  uint32x2_encap_t r;
+  s.a[0] = 42;
+  s.a[1] = 43;
+  t.a[0] = 43;
+  t.a[1] = 43;
+  r.v = pcmpeqw_u (s.v, t.v);
+  assert (r.a[0] == 0x00000000);
+  assert (r.a[1] == 0xffffffff);
+}
+
+static void test_pcmpeqh_u (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 42;
+  s.a[1] = 43;
+  s.a[2] = 42;
+  s.a[3] = 43;
+  t.a[0] = 43;
+  t.a[1] = 43;
+  t.a[2] = 43;
+  t.a[3] = 43;
+  r.v = pcmpeqh_u (s.v, t.v);
+  assert (r.a[0] == 0x0000);
+  assert (r.a[1] == 0xffff);
+  assert (r.a[2] == 0x0000);
+  assert (r.a[3] == 0xffff);
+}
+
+static void test_pcmpeqb_u (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 42;
+  s.a[1] = 43;
+  s.a[2] = 42;
+  s.a[3] = 43;
+  s.a[4] = 42;
+  s.a[5] = 43;
+  s.a[6] = 42;
+  s.a[7] = 43;
+  t.a[0] = 43;
+  t.a[1] = 43;
+  t.a[2] = 43;
+  t.a[3] = 43;
+  t.a[4] = 43;
+  t.a[5] = 43;
+  t.a[6] = 43;
+  t.a[7] = 43;
+  r.v = pcmpeqb_u (s.v, t.v);
+  assert (r.a[0] == 0x00);
+  assert (r.a[1] == 0xff);
+  assert (r.a[2] == 0x00);
+  assert (r.a[3] == 0xff);
+  assert (r.a[4] == 0x00);
+  assert (r.a[5] == 0xff);
+  assert (r.a[6] == 0x00);
+  assert (r.a[7] == 0xff);
+}
+
+static void test_pcmpeqw_s (void)
+{
+  int32x2_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = -42;
+  s.a[1] = -42;
+  t.a[0] = 42;
+  t.a[1] = -42;
+  r.v = pcmpeqw_s (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == -1);
+}
+
+static void test_pcmpeqh_s (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -42;
+  s.a[1] = -42;
+  s.a[2] = -42;
+  s.a[3] = -42;
+  t.a[0] = 42;
+  t.a[1] = -42;
+  t.a[2] = 42;
+  t.a[3] = -42;
+  r.v = pcmpeqh_s (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == -1);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == -1);
+}
+
+static void test_pcmpeqb_s (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -42;
+  s.a[1] = -42;
+  s.a[2] = -42;
+  s.a[3] = -42;
+  s.a[4] = -42;
+  s.a[5] = -42;
+  s.a[6] = -42;
+  s.a[7] = -42;
+  t.a[0] = 42;
+  t.a[1] = -42;
+  t.a[2] = 42;
+  t.a[3] = -42;
+  t.a[4] = 42;
+  t.a[5] = -42;
+  t.a[6] = 42;
+  t.a[7] = -42;
+  r.v = pcmpeqb_s (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == -1);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == -1);
+  assert (r.a[4] == 0);
+  assert (r.a[5] == -1);
+  assert (r.a[6] == 0);
+  assert (r.a[7] == -1);
+}
+
+static void test_pcmpgtw_u (void)
+{
+  uint32x2_encap_t s, t;
+  uint32x2_encap_t r;
+  s.a[0] = 42;
+  s.a[1] = 43;
+  t.a[0] = 43;
+  t.a[1] = 42;
+  r.v = pcmpgtw_u (s.v, t.v);
+  assert (r.a[0] == 0x00000000);
+  assert (r.a[1] == 0xffffffff);
+}
+
+static void test_pcmpgth_u (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 40;
+  s.a[1] = 41;
+  s.a[2] = 42;
+  s.a[3] = 43;
+  t.a[0] = 40;
+  t.a[1] = 41;
+  t.a[2] = 43;
+  t.a[3] = 42;
+  r.v = pcmpgth_u (s.v, t.v);
+  assert (r.a[0] == 0x0000);
+  assert (r.a[1] == 0x0000);
+  assert (r.a[2] == 0x0000);
+  assert (r.a[3] == 0xffff);
+}
+
+static void test_pcmpgtb_u (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 40;
+  s.a[1] = 41;
+  s.a[2] = 42;
+  s.a[3] = 43;
+  s.a[4] = 44;
+  s.a[5] = 45;
+  s.a[6] = 46;
+  s.a[7] = 47;
+  t.a[0] = 48;
+  t.a[1] = 47;
+  t.a[2] = 46;
+  t.a[3] = 45;
+  t.a[4] = 44;
+  t.a[5] = 43;
+  t.a[6] = 42;
+  t.a[7] = 41;
+  r.v = pcmpgtb_u (s.v, t.v);
+  assert (r.a[0] == 0x00);
+  assert (r.a[1] == 0x00);
+  assert (r.a[2] == 0x00);
+  assert (r.a[3] == 0x00);
+  assert (r.a[4] == 0x00);
+  assert (r.a[5] == 0xff);
+  assert (r.a[6] == 0xff);
+  assert (r.a[7] == 0xff);
+}
+
+static void test_pcmpgtw_s (void)
+{
+  int32x2_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = 42;
+  s.a[1] = -42;
+  t.a[0] = -42;
+  t.a[1] = -42;
+  r.v = pcmpgtw_s (s.v, t.v);
+  assert (r.a[0] == -1);
+  assert (r.a[1] == 0);
+}
+
+static void test_pcmpgth_s (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -42;
+  s.a[1] = -42;
+  s.a[2] = -42;
+  s.a[3] = -42;
+  t.a[0] = 42;
+  t.a[1] = 43;
+  t.a[2] = 44;
+  t.a[3] = -43;
+  r.v = pcmpgth_s (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == -1);
+}
+
+static void test_pcmpgtb_s (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -42;
+  s.a[1] = -42;
+  s.a[2] = -42;
+  s.a[3] = -42;
+  s.a[4] = 42;
+  s.a[5] = 42;
+  s.a[6] = 42;
+  s.a[7] = 42;
+  t.a[0] = -45;
+  t.a[1] = -44;
+  t.a[2] = -43;
+  t.a[3] = -42;
+  t.a[4] = 42;
+  t.a[5] = 43;
+  t.a[6] = 41;
+  t.a[7] = 40;
+  r.v = pcmpgtb_s (s.v, t.v);
+  assert (r.a[0] == -1);
+  assert (r.a[1] == -1);
+  assert (r.a[2] == -1);
+  assert (r.a[3] == 0);
+  assert (r.a[4] == 0);
+  assert (r.a[5] == 0);
+  assert (r.a[6] == -1);
+  assert (r.a[7] == -1);
+}
+
+static void test_pextrh_u (void)
+{
+  uint16x4_encap_t s;
+  uint16x4_encap_t r;
+  s.a[0] = 40;
+  s.a[1] = 41;
+  s.a[2] = 42;
+  s.a[3] = 43;
+  r.v = pextrh_u (s.v, 1);
+  assert (r.a[0] == 41);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+}
+
+static void test_pextrh_s (void)
+{
+  int16x4_encap_t s;
+  int16x4_encap_t r;
+  s.a[0] = -40;
+  s.a[1] = -41;
+  s.a[2] = -42;
+  s.a[3] = -43;
+  r.v = pextrh_s (s.v, 2);
+  assert (r.a[0] == -42);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+}
+
+static void test_pinsrh_0123_u (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 42;
+  s.a[1] = 0;
+  s.a[2] = 0;
+  s.a[3] = 0;
+  t.a[0] = 0;
+  t.a[1] = 0;
+  t.a[2] = 0;
+  t.a[3] = 0;
+  r.v = pinsrh_0_u (t.v, s.v);
+  r.v = pinsrh_1_u (r.v, s.v);
+  r.v = pinsrh_2_u (r.v, s.v);
+  r.v = pinsrh_3_u (r.v, s.v);
+  assert (r.a[0] == 42);
+  assert (r.a[1] == 42);
+  assert (r.a[2] == 42);
+  assert (r.a[3] == 42);
+}
+
+static void test_pinsrh_0123_s (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -42;
+  s.a[1] = 0;
+  s.a[2] = 0;
+  s.a[3] = 0;
+  t.a[0] = 0;
+  t.a[1] = 0;
+  t.a[2] = 0;
+  t.a[3] = 0;
+  r.v = pinsrh_0_s (t.v, s.v);
+  r.v = pinsrh_1_s (r.v, s.v);
+  r.v = pinsrh_2_s (r.v, s.v);
+  r.v = pinsrh_3_s (r.v, s.v);
+  assert (r.a[0] == -42);
+  assert (r.a[1] == -42);
+  assert (r.a[2] == -42);
+  assert (r.a[3] == -42);
+}
+
+static void test_pmaddhw (void)
+{
+  int16x4_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = -5;
+  s.a[1] = -4;
+  s.a[2] = -3;
+  s.a[3] = -2;
+  t.a[0] = 10;
+  t.a[1] = 11;
+  t.a[2] = 12;
+  t.a[3] = 13;
+  r.v = pmaddhw (s.v, t.v);
+  assert (r.a[0] == (-5*10 + -4*11));
+  assert (r.a[1] == (-3*12 + -2*13));
+}
+
+static void test_pmaxsh (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -20;
+  s.a[1] = 40;
+  s.a[2] = -10;
+  s.a[3] = 50;
+  t.a[0] = 20;
+  t.a[1] = -40;
+  t.a[2] = 10;
+  t.a[3] = -50;
+  r.v = pmaxsh (s.v, t.v);
+  assert (r.a[0] == 20);
+  assert (r.a[1] == 40);
+  assert (r.a[2] == 10);
+  assert (r.a[3] == 50);
+}
+
+static void test_pmaxub (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 10;
+  s.a[1] = 20;
+  s.a[2] = 30;
+  s.a[3] = 40;
+  s.a[4] = 50;
+  s.a[5] = 60;
+  s.a[6] = 70;
+  s.a[7] = 80;
+  t.a[0] = 80;
+  t.a[1] = 70;
+  t.a[2] = 60;
+  t.a[3] = 50;
+  t.a[4] = 40;
+  t.a[5] = 30;
+  t.a[6] = 20;
+  t.a[7] = 10;
+  r.v = pmaxub (s.v, t.v);
+  assert (r.a[0] == 80);
+  assert (r.a[1] == 70);
+  assert (r.a[2] == 60);
+  assert (r.a[3] == 50);
+  assert (r.a[4] == 50);
+  assert (r.a[5] == 60);
+  assert (r.a[6] == 70);
+  assert (r.a[7] == 80);
+}
+
+static void test_pminsh (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -20;
+  s.a[1] = 40;
+  s.a[2] = -10;
+  s.a[3] = 50;
+  t.a[0] = 20;
+  t.a[1] = -40;
+  t.a[2] = 10;
+  t.a[3] = -50;
+  r.v = pminsh (s.v, t.v);
+  assert (r.a[0] == -20);
+  assert (r.a[1] == -40);
+  assert (r.a[2] == -10);
+  assert (r.a[3] == -50);
+}
+
+static void test_pminub (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 10;
+  s.a[1] = 20;
+  s.a[2] = 30;
+  s.a[3] = 40;
+  s.a[4] = 50;
+  s.a[5] = 60;
+  s.a[6] = 70;
+  s.a[7] = 80;
+  t.a[0] = 80;
+  t.a[1] = 70;
+  t.a[2] = 60;
+  t.a[3] = 50;
+  t.a[4] = 40;
+  t.a[5] = 30;
+  t.a[6] = 20;
+  t.a[7] = 10;
+  r.v = pminub (s.v, t.v);
+  assert (r.a[0] == 10);
+  assert (r.a[1] == 20);
+  assert (r.a[2] == 30);
+  assert (r.a[3] == 40);
+  assert (r.a[4] == 40);
+  assert (r.a[5] == 30);
+  assert (r.a[6] == 20);
+  assert (r.a[7] == 10);
+}
+
+static void test_pmovmskb_u (void)
+{
+  uint8x8_encap_t s;
+  uint8x8_encap_t r;
+  s.a[0] = 0xf0;
+  s.a[1] = 0x40;
+  s.a[2] = 0xf0;
+  s.a[3] = 0x40;
+  s.a[4] = 0xf0;
+  s.a[5] = 0x40;
+  s.a[6] = 0xf0;
+  s.a[7] = 0x40;
+  r.v = pmovmskb_u (s.v);
+  assert (r.a[0] == 0x55);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+  assert (r.a[4] == 0);
+  assert (r.a[5] == 0);
+  assert (r.a[6] == 0);
+  assert (r.a[7] == 0);
+}
+
+static void test_pmovmskb_s (void)
+{
+  int8x8_encap_t s;
+  int8x8_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = 1;
+  s.a[2] = -1;
+  s.a[3] = 1;
+  s.a[4] = -1;
+  s.a[5] = 1;
+  s.a[6] = -1;
+  s.a[7] = 1;
+  r.v = pmovmskb_s (s.v);
+  assert (r.a[0] == 0x55);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+  assert (r.a[4] == 0);
+  assert (r.a[5] == 0);
+  assert (r.a[6] == 0);
+  assert (r.a[7] == 0);
+}
+
+static void test_pmulhuh (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 0xff00;
+  s.a[1] = 0xff00;
+  s.a[2] = 0xff00;
+  s.a[3] = 0xff00;
+  t.a[0] = 16;
+  t.a[1] = 16;
+  t.a[2] = 16;
+  t.a[3] = 16;
+  r.v = pmulhuh (s.v, t.v);
+  assert (r.a[0] == 0x000f);
+  assert (r.a[1] == 0x000f);
+  assert (r.a[2] == 0x000f);
+  assert (r.a[3] == 0x000f);
+}
+
+static void test_pmulhh (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = 0x0ff0;
+  s.a[1] = 0x0ff0;
+  s.a[2] = 0x0ff0;
+  s.a[3] = 0x0ff0;
+  t.a[0] = -16*16;
+  t.a[1] = -16*16;
+  t.a[2] = -16*16;
+  t.a[3] = -16*16;
+  r.v = pmulhh (s.v, t.v);
+  assert (r.a[0] == -16);
+  assert (r.a[1] == -16);
+  assert (r.a[2] == -16);
+  assert (r.a[3] == -16);
+}
+
+static void test_pmullh (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = 0x0ff0;
+  s.a[1] = 0x0ff0;
+  s.a[2] = 0x0ff0;
+  s.a[3] = 0x0ff0;
+  t.a[0] = -16*16;
+  t.a[1] = -16*16;
+  t.a[2] = -16*16;
+  t.a[3] = -16*16;
+  r.v = pmullh (s.v, t.v);
+  assert (r.a[0] == 4096);
+  assert (r.a[1] == 4096);
+  assert (r.a[2] == 4096);
+  assert (r.a[3] == 4096);
+}
+
+static void test_pmuluw (void)
+{
+  uint32x2_encap_t s, t;
+  uint64_t r;
+  s.a[0] = 0xdeadbeef;
+  s.a[1] = 0;
+  t.a[0] = 0x0f00baaa;
+  t.a[1] = 0;
+  r = pmuluw (s.v, t.v);
+  assert (r == 0xd0cd08e1d1a70b6ull);
+}
+
+static void test_pasubub (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 10;
+  s.a[1] = 20;
+  s.a[2] = 30;
+  s.a[3] = 40;
+  s.a[4] = 50;
+  s.a[5] = 60;
+  s.a[6] = 70;
+  s.a[7] = 80;
+  t.a[0] = 80;
+  t.a[1] = 70;
+  t.a[2] = 60;
+  t.a[3] = 50;
+  t.a[4] = 40;
+  t.a[5] = 30;
+  t.a[6] = 20;
+  t.a[7] = 10;
+  r.v = pasubub (s.v, t.v);
+  assert (r.a[0] == 70);
+  assert (r.a[1] == 50);
+  assert (r.a[2] == 30);
+  assert (r.a[3] == 10);
+  assert (r.a[4] == 10);
+  assert (r.a[5] == 30);
+  assert (r.a[6] == 50);
+  assert (r.a[7] == 70);
+}
+
+static void test_biadd (void)
+{
+  uint8x8_encap_t s;
+  uint16x4_encap_t r;
+  s.a[0] = 10;
+  s.a[1] = 20;
+  s.a[2] = 30;
+  s.a[3] = 40;
+  s.a[4] = 50;
+  s.a[5] = 60;
+  s.a[6] = 70;
+  s.a[7] = 80;
+  r.v = biadd (s.v);
+  assert (r.a[0] == 360);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+}
+
+static void test_psadbh (void)
+{
+  uint8x8_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 10;
+  s.a[1] = 20;
+  s.a[2] = 30;
+  s.a[3] = 40;
+  s.a[4] = 50;
+  s.a[5] = 60;
+  s.a[6] = 70;
+  s.a[7] = 80;
+  t.a[0] = 80;
+  t.a[1] = 70;
+  t.a[2] = 60;
+  t.a[3] = 50;
+  t.a[4] = 40;
+  t.a[5] = 30;
+  t.a[6] = 20;
+  t.a[7] = 10;
+  r.v = psadbh (s.v, t.v);
+  assert (r.a[0] == 0x0140);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+}
+
+static void test_pshufh_u (void)
+{
+  uint16x4_encap_t s;
+  uint16x4_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 2;
+  s.a[2] = 3;
+  s.a[3] = 4;
+  r.a[0] = 0;
+  r.a[1] = 0;
+  r.a[2] = 0;
+  r.a[3] = 0;
+  r.v = pshufh_u (r.v, s.v, 0xe5);
+  assert (r.a[0] == 2);
+  assert (r.a[1] == 2);
+  assert (r.a[2] == 3);
+  assert (r.a[3] == 4);
+}
+
+static void test_pshufh_s (void)
+{
+  int16x4_encap_t s;
+  int16x4_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = 2;
+  s.a[2] = -3;
+  s.a[3] = 4;
+  r.a[0] = 0;
+  r.a[1] = 0;
+  r.a[2] = 0;
+  r.a[3] = 0;
+  r.v = pshufh_s (r.v, s.v, 0xe5);
+  assert (r.a[0] == 2);
+  assert (r.a[1] == 2);
+  assert (r.a[2] == -3);
+  assert (r.a[3] == 4);
+}
+
+static void test_psllh_u (void)
+{
+  uint16x4_encap_t s;
+  uint16x4_encap_t r;
+  s.a[0] = 0xffff;
+  s.a[1] = 0xffff;
+  s.a[2] = 0xffff;
+  s.a[3] = 0xffff;
+  r.v = psllh_u (s.v, 1);
+  assert (r.a[0] == 0xfffe);
+  assert (r.a[1] == 0xfffe);
+  assert (r.a[2] == 0xfffe);
+  assert (r.a[3] == 0xfffe);
+}
+
+static void test_psllw_u (void)
+{
+  uint32x2_encap_t s;
+  uint32x2_encap_t r;
+  s.a[0] = 0xffffffff;
+  s.a[1] = 0xffffffff;
+  r.v = psllw_u (s.v, 2);
+  assert (r.a[0] == 0xfffffffc);
+  assert (r.a[1] == 0xfffffffc);
+}
+
+static void test_psllh_s (void)
+{
+  int16x4_encap_t s;
+  int16x4_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = -1;
+  s.a[2] = -1;
+  s.a[3] = -1;
+  r.v = psllh_s (s.v, 1);
+  assert (r.a[0] == -2);
+  assert (r.a[1] == -2);
+  assert (r.a[2] == -2);
+  assert (r.a[3] == -2);
+}
+
+static void test_psllw_s (void)
+{
+  int32x2_encap_t s;
+  int32x2_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = -1;
+  r.v = psllw_s (s.v, 2);
+  assert (r.a[0] == -4);
+  assert (r.a[1] == -4);
+}
+
+static void test_psrah_u (void)
+{
+  uint16x4_encap_t s;
+  uint16x4_encap_t r;
+  s.a[0] = 0xffef;
+  s.a[1] = 0xffef;
+  s.a[2] = 0xffef;
+  s.a[3] = 0xffef;
+  r.v = psrah_u (s.v, 1);
+  assert (r.a[0] == 0xfff7);
+  assert (r.a[1] == 0xfff7);
+  assert (r.a[2] == 0xfff7);
+  assert (r.a[3] == 0xfff7);
+}
+
+static void test_psraw_u (void)
+{
+  uint32x2_encap_t s;
+  uint32x2_encap_t r;
+  s.a[0] = 0xffffffef;
+  s.a[1] = 0xffffffef;
+  r.v = psraw_u (s.v, 1);
+  assert (r.a[0] == 0xfffffff7);
+  assert (r.a[1] == 0xfffffff7);
+}
+
+static void test_psrah_s (void)
+{
+  int16x4_encap_t s;
+  int16x4_encap_t r;
+  s.a[0] = -2;
+  s.a[1] = -2;
+  s.a[2] = -2;
+  s.a[3] = -2;
+  r.v = psrah_s (s.v, 1);
+  assert (r.a[0] == -1);
+  assert (r.a[1] == -1);
+  assert (r.a[2] == -1);
+  assert (r.a[3] == -1);
+}
+
+static void test_psraw_s (void)
+{
+  int32x2_encap_t s;
+  int32x2_encap_t r;
+  s.a[0] = -2;
+  s.a[1] = -2;
+  r.v = psraw_s (s.v, 1);
+  assert (r.a[0] == -1);
+  assert (r.a[1] == -1);
+}
+
+static void test_psrlh_u (void)
+{
+  uint16x4_encap_t s;
+  uint16x4_encap_t r;
+  s.a[0] = 0xffef;
+  s.a[1] = 0xffef;
+  s.a[2] = 0xffef;
+  s.a[3] = 0xffef;
+  r.v = psrlh_u (s.v, 1);
+  assert (r.a[0] == 0x7ff7);
+  assert (r.a[1] == 0x7ff7);
+  assert (r.a[2] == 0x7ff7);
+  assert (r.a[3] == 0x7ff7);
+}
+
+static void test_psrlw_u (void)
+{
+  uint32x2_encap_t s;
+  uint32x2_encap_t r;
+  s.a[0] = 0xffffffef;
+  s.a[1] = 0xffffffef;
+  r.v = psrlw_u (s.v, 1);
+  assert (r.a[0] == 0x7ffffff7);
+  assert (r.a[1] == 0x7ffffff7);
+}
+
+static void test_psrlh_s (void)
+{
+  int16x4_encap_t s;
+  int16x4_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = -1;
+  s.a[2] = -1;
+  s.a[3] = -1;
+  r.v = psrlh_s (s.v, 1);
+  assert (r.a[0] == INT16x4_MAX);
+  assert (r.a[1] == INT16x4_MAX);
+  assert (r.a[2] == INT16x4_MAX);
+  assert (r.a[3] == INT16x4_MAX);
+}
+
+static void test_psrlw_s (void)
+{
+  int32x2_encap_t s;
+  int32x2_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = -1;
+  r.v = psrlw_s (s.v, 1);
+  assert (r.a[0] == INT32x2_MAX);
+  assert (r.a[1] == INT32x2_MAX);
+}
+
+static void test_psubw_u (void)
+{
+  uint32x2_encap_t s, t;
+  uint32x2_encap_t r;
+  s.a[0] = 3;
+  s.a[1] = 4;
+  t.a[0] = 2;
+  t.a[1] = 1;
+  r.v = psubw_u (s.v, t.v);
+  assert (r.a[0] == 1);
+  assert (r.a[1] == 3);
+}
+
+static void test_psubw_s (void)
+{
+  int32x2_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = -2;
+  s.a[1] = -1;
+  t.a[0] = 3;
+  t.a[1] = -4;
+  r.v = psubw_s (s.v, t.v);
+  assert (r.a[0] == -5);
+  assert (r.a[1] == 3);
+}
+
+static void test_psubh_u (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 5;
+  s.a[1] = 6;
+  s.a[2] = 7;
+  s.a[3] = 8;
+  t.a[0] = 1;
+  t.a[1] = 2;
+  t.a[2] = 3;
+  t.a[3] = 4;
+  r.v = psubh_u (s.v, t.v);
+  assert (r.a[0] == 4);
+  assert (r.a[1] == 4);
+  assert (r.a[2] == 4);
+  assert (r.a[3] == 4);
+}
+
+static void test_psubh_s (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -10;
+  s.a[1] = -20;
+  s.a[2] = -30;
+  s.a[3] = -40;
+  t.a[0] = 1;
+  t.a[1] = 2;
+  t.a[2] = 3;
+  t.a[3] = 4;
+  r.v = psubh_s (s.v, t.v);
+  assert (r.a[0] == -11);
+  assert (r.a[1] == -22);
+  assert (r.a[2] == -33);
+  assert (r.a[3] == -44);
+}
+
+static void test_psubb_u (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 10;
+  s.a[1] = 11;
+  s.a[2] = 12;
+  s.a[3] = 13;
+  s.a[4] = 14;
+  s.a[5] = 15;
+  s.a[6] = 16;
+  s.a[7] = 17;
+  t.a[0] = 1;
+  t.a[1] = 2;
+  t.a[2] = 3;
+  t.a[3] = 4;
+  t.a[4] = 5;
+  t.a[5] = 6;
+  t.a[6] = 7;
+  t.a[7] = 8;
+  r.v = psubb_u (s.v, t.v);
+  assert (r.a[0] == 9);
+  assert (r.a[1] == 9);
+  assert (r.a[2] == 9);
+  assert (r.a[3] == 9);
+  assert (r.a[4] == 9);
+  assert (r.a[5] == 9);
+  assert (r.a[6] == 9);
+  assert (r.a[7] == 9);
+}
+
+static void test_psubb_s (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -10;
+  s.a[1] = -20;
+  s.a[2] = -30;
+  s.a[3] = -40;
+  s.a[4] = -50;
+  s.a[5] = -60;
+  s.a[6] = -70;
+  s.a[7] = -80;
+  t.a[0] = 1;
+  t.a[1] = 2;
+  t.a[2] = 3;
+  t.a[3] = 4;
+  t.a[4] = 5;
+  t.a[5] = 6;
+  t.a[6] = 7;
+  t.a[7] = 8;
+  r.v = psubb_s (s.v, t.v);
+  assert (r.a[0] == -11);
+  assert (r.a[1] == -22);
+  assert (r.a[2] == -33);
+  assert (r.a[3] == -44);
+  assert (r.a[4] == -55);
+  assert (r.a[5] == -66);
+  assert (r.a[6] == -77);
+  assert (r.a[7] == -88);
+}
+
+static void test_psubd_u (void)
+{
+  uint64_t d = 789012;
+  uint64_t e = 123456;
+  uint64_t r;
+  r = psubd_u (d, e);
+  assert (r == 665556);
+}
+
+static void test_psubd_s (void)
+{
+  int64_t d = 123456;
+  int64_t e = -789012;
+  int64_t r;
+  r = psubd_s (d, e);
+  assert (r == 912468);
+}
+
+static void test_psubsh (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = 0;
+  s.a[2] = 1;
+  s.a[3] = 2;
+  t.a[0] = -INT16x4_MAX;
+  t.a[1] = -INT16x4_MAX;
+  t.a[2] = -INT16x4_MAX;
+  t.a[3] = -INT16x4_MAX;
+  r.v = psubsh (s.v, t.v);
+  assert (r.a[0] == INT16x4_MAX - 1);
+  assert (r.a[1] == INT16x4_MAX);
+  assert (r.a[2] == INT16x4_MAX);
+  assert (r.a[3] == INT16x4_MAX);
+}
+
+static void test_psubsb (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -6;
+  s.a[1] = -5;
+  s.a[2] = -4;
+  s.a[3] = -3;
+  s.a[4] = -2;
+  s.a[5] = -1;
+  s.a[6] = 0;
+  s.a[7] = 1;
+  t.a[0] = -INT8x8_MAX;
+  t.a[1] = -INT8x8_MAX;
+  t.a[2] = -INT8x8_MAX;
+  t.a[3] = -INT8x8_MAX;
+  t.a[4] = -INT8x8_MAX;
+  t.a[5] = -INT8x8_MAX;
+  t.a[6] = -INT8x8_MAX;
+  t.a[7] = -INT8x8_MAX;
+  r.v = psubsb (s.v, t.v);
+  assert (r.a[0] == INT8x8_MAX - 6);
+  assert (r.a[1] == INT8x8_MAX - 5);
+  assert (r.a[2] == INT8x8_MAX - 4);
+  assert (r.a[3] == INT8x8_MAX - 3);
+  assert (r.a[4] == INT8x8_MAX - 2);
+  assert (r.a[5] == INT8x8_MAX - 1);
+  assert (r.a[6] == INT8x8_MAX);
+  assert (r.a[7] == INT8x8_MAX);
+}
+
+static void test_psubush (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 0;
+  s.a[1] = 1;
+  s.a[2] = 2;
+  s.a[3] = 3;
+  t.a[0] = 1;
+  t.a[1] = 1;
+  t.a[2] = 3;
+  t.a[3] = 3;
+  r.v = psubush (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+}
+
+static void test_psubusb (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 0;
+  s.a[1] = 1;
+  s.a[2] = 2;
+  s.a[3] = 3;
+  s.a[4] = 4;
+  s.a[5] = 5;
+  s.a[6] = 6;
+  s.a[7] = 7;
+  t.a[0] = 1;
+  t.a[1] = 1;
+  t.a[2] = 3;
+  t.a[3] = 3;
+  t.a[4] = 5;
+  t.a[5] = 5;
+  t.a[6] = 7;
+  t.a[7] = 7;
+  r.v = psubusb (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+  assert (r.a[4] == 0);
+  assert (r.a[5] == 0);
+  assert (r.a[6] == 0);
+  assert (r.a[7] == 0);
+}
+
+static void test_punpckhbh_s (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = -3;
+  s.a[2] = -5;
+  s.a[3] = -7;
+  s.a[4] = -9;
+  s.a[5] = -11;
+  s.a[6] = -13;
+  s.a[7] = -15;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  t.a[2] = 6;
+  t.a[3] = 8;
+  t.a[4] = 10;
+  t.a[5] = 12;
+  t.a[6] = 14;
+  t.a[7] = 16;
+  r.v = punpckhbh_s (s.v, t.v);
+  assert (r.a[0] == -9);
+  assert (r.a[1] == 10);
+  assert (r.a[2] == -11);
+  assert (r.a[3] == 12);
+  assert (r.a[4] == -13);
+  assert (r.a[5] == 14);
+  assert (r.a[6] == -15);
+  assert (r.a[7] == 16);
+}
+
+static void test_punpckhbh_u (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  s.a[2] = 5;
+  s.a[3] = 7;
+  s.a[4] = 9;
+  s.a[5] = 11;
+  s.a[6] = 13;
+  s.a[7] = 15;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  t.a[2] = 6;
+  t.a[3] = 8;
+  t.a[4] = 10;
+  t.a[5] = 12;
+  t.a[6] = 14;
+  t.a[7] = 16;
+  r.v = punpckhbh_u (s.v, t.v);
+  assert (r.a[0] == 9);
+  assert (r.a[1] == 10);
+  assert (r.a[2] == 11);
+  assert (r.a[3] == 12);
+  assert (r.a[4] == 13);
+  assert (r.a[5] == 14);
+  assert (r.a[6] == 15);
+  assert (r.a[7] == 16);
+}
+
+static void test_punpckhhw_s (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = 3;
+  s.a[2] = -5;
+  s.a[3] = 7;
+  t.a[0] = -2;
+  t.a[1] = 4;
+  t.a[2] = -6;
+  t.a[3] = 8;
+  r.v = punpckhhw_s (s.v, t.v);
+  assert (r.a[0] == -5);
+  assert (r.a[1] == -6);
+  assert (r.a[2] == 7);
+  assert (r.a[3] == 8);
+}
+
+static void test_punpckhhw_u (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  s.a[2] = 5;
+  s.a[3] = 7;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  t.a[2] = 6;
+  t.a[3] = 8;
+  r.v = punpckhhw_u (s.v, t.v);
+  assert (r.a[0] == 5);
+  assert (r.a[1] == 6);
+  assert (r.a[2] == 7);
+  assert (r.a[3] == 8);
+}
+
+static void test_punpckhwd_s (void)
+{
+  int32x2_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  t.a[0] = 2;
+  t.a[1] = -4;
+  r.v = punpckhwd_s (s.v, t.v);
+  assert (r.a[0] == 3);
+  assert (r.a[1] == -4);
+}
+
+static void test_punpckhwd_u (void)
+{
+  uint32x2_encap_t s, t;
+  uint32x2_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  r.v = punpckhwd_u (s.v, t.v);
+  assert (r.a[0] == 3);
+  assert (r.a[1] == 4);
+}
+
+static void test_punpcklbh_s (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = -3;
+  s.a[2] = -5;
+  s.a[3] = -7;
+  s.a[4] = -9;
+  s.a[5] = -11;
+  s.a[6] = -13;
+  s.a[7] = -15;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  t.a[2] = 6;
+  t.a[3] = 8;
+  t.a[4] = 10;
+  t.a[5] = 12;
+  t.a[6] = 14;
+  t.a[7] = 16;
+  r.v = punpcklbh_s (s.v, t.v);
+  assert (r.a[0] == -1);
+  assert (r.a[1] == 2);
+  assert (r.a[2] == -3);
+  assert (r.a[3] == 4);
+  assert (r.a[4] == -5);
+  assert (r.a[5] == 6);
+  assert (r.a[6] == -7);
+  assert (r.a[7] == 8);
+}
+
+static void test_punpcklbh_u (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  s.a[2] = 5;
+  s.a[3] = 7;
+  s.a[4] = 9;
+  s.a[5] = 11;
+  s.a[6] = 13;
+  s.a[7] = 15;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  t.a[2] = 6;
+  t.a[3] = 8;
+  t.a[4] = 10;
+  t.a[5] = 12;
+  t.a[6] = 14;
+  t.a[7] = 16;
+  r.v = punpcklbh_u (s.v, t.v);
+  assert (r.a[0] == 1);
+  assert (r.a[1] == 2);
+  assert (r.a[2] == 3);
+  assert (r.a[3] == 4);
+  assert (r.a[4] == 5);
+  assert (r.a[5] == 6);
+  assert (r.a[6] == 7);
+  assert (r.a[7] == 8);
+}
+
+static void test_punpcklhw_s (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = 3;
+  s.a[2] = -5;
+  s.a[3] = 7;
+  t.a[0] = -2;
+  t.a[1] = 4;
+  t.a[2] = -6;
+  t.a[3] = 8;
+  r.v = punpcklhw_s (s.v, t.v);
+  assert (r.a[0] == -1);
+  assert (r.a[1] == -2);
+  assert (r.a[2] == 3);
+  assert (r.a[3] == 4);
+}
+
+static void test_punpcklhw_u (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  s.a[2] = 5;
+  s.a[3] = 7;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  t.a[2] = 6;
+  t.a[3] = 8;
+  r.v = punpcklhw_u (s.v, t.v);
+  assert (r.a[0] == 1);
+  assert (r.a[1] == 2);
+  assert (r.a[2] == 3);
+  assert (r.a[3] == 4);
+}
+
+static void test_punpcklwd_s (void)
+{
+  int32x2_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  t.a[0] = -2;
+  t.a[1] = 4;
+  r.v = punpcklwd_s (s.v, t.v);
+  assert (r.a[0] == 1);
+  assert (r.a[1] == -2);
+}
+
+static void test_punpcklwd_u (void)
+{
+  uint32x2_encap_t s, t;
+  uint32x2_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  r.v = punpcklwd_u (s.v, t.v);
+  assert (r.a[0] == 1);
+  assert (r.a[1] == 2);
+}
+
+int main (void)
+{
+  test_packsswh ();
+  test_packsshb ();
+  test_packushb ();
+  test_paddw_u ();
+  test_paddw_s ();
+  test_paddh_u ();
+  test_paddh_s ();
+  test_paddb_u ();
+  test_paddb_s ();
+  test_paddd_u ();
+  test_paddd_s ();
+  test_paddsh ();
+  test_paddsb ();
+  test_paddush ();
+  test_paddusb ();
+  test_pandn_ud ();
+  test_pandn_sd ();
+  test_pandn_uw ();
+  test_pandn_sw ();
+  test_pandn_uh ();
+  test_pandn_sh ();
+  test_pandn_ub ();
+  test_pandn_sb ();
+  test_pavgh ();
+  test_pavgb ();
+  test_pcmpeqw_u ();
+  test_pcmpeqh_u ();
+  test_pcmpeqb_u ();
+  test_pcmpeqw_s ();
+  test_pcmpeqh_s ();
+  test_pcmpeqb_s ();
+  test_pcmpgtw_u ();
+  test_pcmpgth_u ();
+  test_pcmpgtb_u ();
+  test_pcmpgtw_s ();
+  test_pcmpgth_s ();
+  test_pcmpgtb_s ();
+  test_pextrh_u ();
+  test_pextrh_s ();
+  test_pinsrh_0123_u ();
+  test_pinsrh_0123_s ();
+  test_pmaddhw ();
+  test_pmaxsh ();
+  test_pmaxub ();
+  test_pminsh ();
+  test_pminub ();
+  test_pmovmskb_u ();
+  test_pmovmskb_s ();
+  test_pmulhuh ();
+  test_pmulhh ();
+  test_pmullh ();
+  test_pmuluw ();
+  test_pasubub ();
+  test_biadd ();
+  test_psadbh ();
+  test_pshufh_u ();
+  test_pshufh_s ();
+  test_psllh_u ();
+  test_psllw_u ();
+  test_psllh_s ();
+  test_psllw_s ();
+  test_psrah_u ();
+  test_psraw_u ();
+  test_psrah_s ();
+  test_psraw_s ();
+  test_psrlh_u ();
+  test_psrlw_u ();
+  test_psrlh_s ();
+  test_psrlw_s ();
+  test_psubw_u ();
+  test_psubw_s ();
+  test_psubh_u ();
+  test_psubh_s ();
+  test_psubb_u ();
+  test_psubb_s ();
+  test_psubd_u ();
+  test_psubd_s ();
+  test_psubsh ();
+  test_psubsb ();
+  test_psubush ();
+  test_psubusb ();
+  test_punpckhbh_s ();
+  test_punpckhbh_u ();
+  test_punpckhhw_s ();
+  test_punpckhhw_u ();
+  test_punpckhwd_s ();
+  test_punpckhwd_u ();
+  test_punpcklbh_s ();
+  test_punpcklbh_u ();
+  test_punpcklhw_s ();
+  test_punpcklhw_u ();
+  test_punpcklwd_s ();
+  test_punpcklwd_u ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-1.c
new file mode 100644
index 000000000..53881a4b0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=vr4130 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmacc\t\\\$1," 3 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return (long long) x * y + z;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  return z + (long long) y * x;
+}
+
+NOMIPS16 long long
+f3 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-2.c
new file mode 100644
index 000000000..eab7a6845
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-2.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=vr5500 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmadd\t" 3 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return (long long) x * y + z;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  return z + (long long) y * x;
+}
+
+NOMIPS16 long long
+f3 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-3.c
new file mode 100644
index 000000000..6b479f59c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-3.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 isa_rev>=1 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmadd\t" 3 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return (long long) x * y + z;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  return z + (long long) y * x;
+}
+
+NOMIPS16 long long
+f3 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-4.c
new file mode 100644
index 000000000..f325af746
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-4.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdspr2 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmadd\t\\\$ac" 3 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return (long long) x * y + z;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  return z + (long long) y * x;
+}
+
+NOMIPS16 long long
+f3 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-5.c
new file mode 100644
index 000000000..1ad1c91f3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-5.c
@@ -0,0 +1,8 @@
+/* { dg-options "-O2 -march=5kc" } */
+/* { dg-final { scan-assembler-times "\tmadd\t" 4 } } */
+/* { dg-final { scan-assembler-not "\tmtlo\t" } } */
+/* { dg-final { scan-assembler-times "\tmflo\t" 3 } } */
+
+NOMIPS16 void f1 (int *a) { a[0] = a[0] * a[1] + a[2] * a[3]; }
+NOMIPS16 void f2 (int *a) { a[0] = a[0] * a[1] + a[2] * a[3] + a[4]; }
+NOMIPS16 void f3 (int *a) { a[0] = a[0] * a[1] + a[2] * a[3] + a[4] * a[5]; }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-6.c
new file mode 100644
index 000000000..4e5afadce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-6.c
@@ -0,0 +1,6 @@
+/* { dg-options "-O2 -march=5kc" } */
+/* { dg-final { scan-assembler-not "\tmadd\t" } } */
+/* { dg-final { scan-assembler "\tmul\t" } } */
+/* { dg-final { scan-assembler "\taddu\t" } } */
+
+NOMIPS16 void f1 (int *a) { a[0] = a[0] * a[1] + a[2]; }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-7.c
new file mode 100644
index 000000000..93ed0fc6f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-7.c
@@ -0,0 +1,15 @@
+/* -mlong32 added because of PR target/38598.  */
+/* { dg-options "-O2 -march=5kc -mlong32" } */
+/* { dg-final { scan-assembler-not "\tmul\t" } } */
+/* { dg-final { scan-assembler "\tmadd\t" } } */
+
+NOMIPS16 int
+f1 (int *a, int *b, int n)
+{
+  int x, i;
+
+  x = 0;
+  for (i = 0; i < n; i++)
+    x += a[i] * b[i];
+  return x;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-8.c
new file mode 100644
index 000000000..35092a8ad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/madd-8.c
@@ -0,0 +1,15 @@
+/* { dg-options "-O2 -march=5kc" } */
+/* { dg-final { scan-assembler "\tmul\t" } } */
+/* { dg-final { scan-assembler-not "\tmadd\t" } } */
+/* { dg-final { scan-assembler-not "\tmtlo\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+
+NOMIPS16 int
+f2 (int x, int y, int z)
+{
+  asm volatile ("" ::: "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9",
+		"$10", "$11", "$12", "$13", "$14", "$15", "$16", "$17",
+		"$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25",
+		"$31");
+  return x * y + z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/maddu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/maddu-1.c
new file mode 100644
index 000000000..04161ce3a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/maddu-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=vr4130 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmaccu\t\\\$1," 3 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return (ull) x * y + z;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  return z + (ull) y * x;
+}
+
+NOMIPS16 ull
+f3 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/maddu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/maddu-2.c
new file mode 100644
index 000000000..a9768f15b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/maddu-2.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=vr5500 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmaddu\t" 3 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return (ull) x * y + z;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  return z + (ull) y * x;
+}
+
+NOMIPS16 ull
+f3 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/maddu-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/maddu-3.c
new file mode 100644
index 000000000..b0b4817a4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/maddu-3.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 isa_rev>=1 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmaddu\t" 3 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return (ull) x * y + z;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  return z + (ull) y * x;
+}
+
+NOMIPS16 ull
+f3 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/maddu-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/maddu-4.c
new file mode 100644
index 000000000..9c1ccd5f9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/maddu-4.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdspr2 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmaddu\t\\\$ac" 3 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return (ull) x * y + z;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  return z + (ull) y * x;
+}
+
+NOMIPS16 ull
+f3 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/memcpy-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/memcpy-1.c
new file mode 100644
index 000000000..f3eda7500
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/memcpy-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "\tlbu\t" } } */
+
+#include <string.h>
+
+char c[10];
+
+void
+f1 ()
+{
+  memcpy (c, "123456", 6);
+}
+
+void
+f2 ()
+{
+  memcpy (c, &"12345678"[2], 6);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-1.c
new file mode 100644
index 000000000..eb3f8f9a8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-1.c
@@ -0,0 +1,127 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mips3d" } */
+
+/* Test MIPS-3D builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+NOMIPS16 int main ()
+{
+  int little_endian;
+  v2sf a, b, c, d;
+  float f1, f2, f3, f4, f5, f6;
+  double d1, d2, d3, d4, d5, d6, d7, d8, d9;
+  v2sf ps1, ps2, ps3, ps4, ps5, ps6;
+
+  union { long long ll; int i[2]; } endianness_test;
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  /* addr.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {45, 67};
+  c = __builtin_mips_addr_ps (a, b);
+  if (little_endian)
+    d = (v2sf) {112, 46};
+  else
+    d = (v2sf) {46, 112};
+
+  if (!__builtin_mips_all_c_eq_ps(c, d))
+     abort ();
+
+  /* mulr.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {45, 67};
+  c = __builtin_mips_mulr_ps (a, b);
+  if (little_endian)
+    d = (v2sf) {3015, 408};
+  else
+    d = (v2sf) {408, 3015};
+
+  if (!__builtin_mips_all_c_eq_ps(c, d))
+     abort ();
+
+  /* cvt.pw.ps */
+  a = (v2sf) {12345.34, 67890.45};
+  b = __builtin_mips_cvt_pw_ps (a);
+
+  /* cvt.ps.pw */
+  c = __builtin_mips_cvt_ps_pw (b);
+  d = (v2sf) {12345.0, 67890.0};
+
+  if (!__builtin_mips_all_c_eq_ps(c, d))
+     abort ();
+
+  /* recip1.s recip2.s */
+  f1 = 40;
+  f2 = __builtin_mips_recip1_s (f1);
+  f3 = __builtin_mips_recip2_s (f2, f1);
+  f4 = f2 + f2 * f3;
+  f5 = 0.025;
+
+  if (f4 != f5)
+    abort ();
+
+  /* recip1.d recip2.d */
+  d1 = 80;
+  d2 = __builtin_mips_recip1_d (d1);
+  d3 = __builtin_mips_recip2_d (d2, d1);
+  d4 = d2 + d2 * d3;
+  d5 = __builtin_mips_recip2_d (d4, d1);
+  d6 = d4 + d4 * d5;
+  d7 = 0.0125;
+
+  if (d6 != d7)
+    abort ();
+
+  /* recip1.ps recip2.ps */
+  ps1 = (v2sf) {100, 200};
+  ps2 = __builtin_mips_recip1_ps (ps1);
+  ps3 = __builtin_mips_recip2_ps (ps2, ps1);
+  ps4 = ps2 + ps2 * ps3;
+  ps5 = (v2sf) {0.01, 0.005};
+
+  if (!__builtin_mips_all_c_eq_ps(ps4, ps5))
+    abort ();
+
+  /* rsqrt1.s rsqrt2.s */
+  f1 = 400;
+  f2 = __builtin_mips_rsqrt1_s (f1);
+  f3 = f2 * f1;
+  f4 = __builtin_mips_rsqrt2_s (f3, f2);
+  f5 = f2 + f2 * f4;
+  f6 = 0.05;
+
+  if (f5 != f6)
+    abort ();
+
+  /* rsqrt1.d rsqrt2.d */
+  d1 = 1600;
+  d2 = __builtin_mips_rsqrt1_d (d1);
+  d3 = d2 * d1;
+  d4 = __builtin_mips_rsqrt2_d (d3, d2);
+  d5 = d2 + d2 * d4;
+  d6 = d1 * d5;
+  d7 = __builtin_mips_rsqrt2_d (d6, d5);
+  d8 = d5 + d5 * d7;
+  d9 = 0.025;
+
+  if (d8 != d9)
+    abort ();
+
+  /* rsqrt1.ps rsqrt2.ps */
+  ps1 = (v2sf) {400, 100};
+  ps2 = __builtin_mips_rsqrt1_ps (ps1);
+  ps3 = ps2 * ps1;
+  ps4 = __builtin_mips_rsqrt2_ps (ps3, ps2);
+  ps5 = ps2 + ps2 * ps4;
+  ps6 = (v2sf) {0.05, 0.1};
+
+  if (!__builtin_mips_all_c_eq_ps(ps5, ps6))
+     abort ();
+
+  printf ("Test Passes\n");
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-2.c
new file mode 100644
index 000000000..dc815748e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-2.c
@@ -0,0 +1,554 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mips3d" } */
+
+/* Test MIPS-3D branch-if-any-two builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+NOMIPS16 int test0 (v2sf a, v2sf b);
+NOMIPS16 int test1 (v2sf a, v2sf b);
+NOMIPS16 int test2 (v2sf a, v2sf b);
+NOMIPS16 int test3 (v2sf a, v2sf b);
+NOMIPS16 int test4 (v2sf a, v2sf b);
+NOMIPS16 int test5 (v2sf a, v2sf b);
+NOMIPS16 int test6 (v2sf a, v2sf b);
+NOMIPS16 int test7 (v2sf a, v2sf b);
+NOMIPS16 int test8 (v2sf a, v2sf b);
+NOMIPS16 int test9 (v2sf a, v2sf b);
+NOMIPS16 int test10 (v2sf a, v2sf b);
+NOMIPS16 int test11 (v2sf a, v2sf b);
+NOMIPS16 int test12 (v2sf a, v2sf b);
+NOMIPS16 int test13 (v2sf a, v2sf b);
+NOMIPS16 int test14 (v2sf a, v2sf b);
+NOMIPS16 int test15 (v2sf a, v2sf b);
+NOMIPS16 int test16 (v2sf a, v2sf b);
+NOMIPS16 int test17 (v2sf a, v2sf b);
+NOMIPS16 int test18 (v2sf a, v2sf b);
+NOMIPS16 int test19 (v2sf a, v2sf b);
+NOMIPS16 int test20 (v2sf a, v2sf b);
+NOMIPS16 int test21 (v2sf a, v2sf b);
+NOMIPS16 int test22 (v2sf a, v2sf b);
+NOMIPS16 int test23 (v2sf a, v2sf b);
+NOMIPS16 int test24 (v2sf a, v2sf b);
+NOMIPS16 int test25 (v2sf a, v2sf b);
+NOMIPS16 int test26 (v2sf a, v2sf b);
+NOMIPS16 int test27 (v2sf a, v2sf b);
+NOMIPS16 int test28 (v2sf a, v2sf b);
+NOMIPS16 int test29 (v2sf a, v2sf b);
+NOMIPS16 int test30 (v2sf a, v2sf b);
+NOMIPS16 int test31 (v2sf a, v2sf b);
+
+float qnan = 1.0f/0.0f - 1.0f/0.0f;
+
+NOMIPS16 int main ()
+{
+  v2sf a, b, c, d;
+  int i, j;
+
+  /* c.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {56, 78};
+  i = 0;
+  j = 0;
+  if (__builtin_mips_any_c_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_all_c_eq_ps(a, b) != j)
+     abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {12, 78};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_c_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_all_c_eq_ps(a, b) != j)
+     abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {56, 34};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_c_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_all_c_eq_ps(a, b) != j)
+     abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {12, 34};
+  i = 1;
+  j = 1;
+  if (__builtin_mips_any_c_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_all_c_eq_ps(a, b) != j)
+     abort ();
+
+  /* Test with 16 operators */
+  a = (v2sf) {10.58, 1984.0};
+  b = (v2sf) {567.345, 1984.0};
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b);
+  if (i != 0)
+    abort ();
+  i = test4 (a, b);
+  if (i != 1)
+    abort ();
+  i = test5 (a, b);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b);
+  if (i != 0)
+    abort ();
+  i = test8 (a, b);
+  if (i != 1)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b);
+  if (i != 0)
+    abort ();
+  i = test12 (a, b);
+  if (i != 1)
+    abort ();
+  i = test13 (a, b);
+  if (i != 1)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+  i = test16 (a, b);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b);
+  if (i != 0)
+    abort ();
+  i = test19 (a, b);
+  if (i != 0)
+    abort ();
+  i = test20 (a, b);
+  if (i != 1)
+    abort ();
+  i = test21 (a, b);
+  if (i != 0)
+    abort ();
+  i = test22 (a, b);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b);
+  if (i != 0)
+    abort ();
+  i = test24 (a, b);
+  if (i != 1)
+    abort ();
+  i = test25 (a, b);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b);
+  if (i != 0)
+    abort ();
+  i = test28 (a, b);
+  if (i != 1)
+    abort ();
+  i = test29 (a, b);
+  if (i != 1)
+    abort ();
+  i = test30 (a, b);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b);
+  if (i != 1)
+    abort ();
+
+  /* Reverse arguments */
+  i = test0 (b, a);
+  if (i != 0)
+    abort ();
+  i = test1 (b, a);
+  if (i != 0)
+    abort ();
+  i = test2 (b, a);
+  if (i != 0)
+    abort ();
+  i = test3 (b, a);
+  if (i != 0)
+    abort ();
+  i = test4 (b, a);
+  if (i != 1)
+    abort ();
+  i = test5 (b, a);
+  if (i != 0)
+    abort ();
+  i = test6 (b, a);
+  if (i != 1)
+    abort ();
+  i = test7 (b, a);
+  if (i != 0)
+    abort ();
+  i = test8 (b, a);
+  if (i != 0)
+    abort ();
+  i = test9 (b, a);
+  if (i != 0)
+    abort ();
+  i = test10 (b, a);
+  if (i != 0)
+    abort ();
+  i = test11 (b, a);
+  if (i != 0)
+    abort ();
+  i = test12 (b, a);
+  if (i != 1)
+    abort ();
+  i = test13 (b, a);
+  if (i != 0)
+    abort ();
+  i = test14 (b, a);
+  if (i != 1)
+    abort ();
+  i = test15 (b, a);
+  if (i != 0)
+    abort ();
+  i = test16 (b, a);
+  if (i != 0)
+    abort ();
+  i = test17 (b, a);
+  if (i != 0)
+    abort ();
+  i = test18 (b, a);
+  if (i != 0)
+    abort ();
+  i = test19 (b, a);
+  if (i != 0)
+    abort ();
+  i = test20 (b, a);
+  if (i != 1)
+    abort ();
+  i = test21 (b, a);
+  if (i != 0)
+    abort ();
+  i = test22 (b, a);
+  if (i != 1)
+    abort ();
+  i = test23 (b, a);
+  if (i != 0)
+    abort ();
+  i = test24 (b, a);
+  if (i != 0)
+    abort ();
+  i = test25 (b, a);
+  if (i != 0)
+    abort ();
+  i = test26 (b, a);
+  if (i != 0)
+    abort ();
+  i = test27 (b, a);
+  if (i != 0)
+    abort ();
+  i = test28 (b, a);
+  if (i != 1)
+    abort ();
+  i = test29 (b, a);
+  if (i != 0)
+    abort ();
+  i = test30 (b, a);
+  if (i != 1)
+    abort ();
+  i = test31 (b, a);
+  if (i != 0)
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test with 16 operators */
+  a = (v2sf) {qnan, qnan};
+  b = (v2sf) {567.345, 1984.0};
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 1)
+    abort ();
+  i = test3 (a, b);
+  if (i != 1)
+    abort ();
+  i = test4 (a, b);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b);
+  if (i != 1)
+    abort ();
+  i = test12 (a, b);
+  if (i != 0)
+    abort ();
+  i = test13 (a, b);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+  i = test16 (a, b);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b);
+  if (i != 1)
+    abort ();
+  i = test19 (a, b);
+  if (i != 1)
+    abort ();
+  i = test20 (a, b);
+  if (i != 0)
+    abort ();
+  i = test21 (a, b);
+  if (i != 0)
+    abort ();
+  i = test22 (a, b);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b);
+  if (i != 1)
+    abort ();
+  i = test24 (a, b);
+  if (i != 0)
+    abort ();
+  i = test25 (a, b);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b);
+  if (i != 1)
+    abort ();
+  i = test28 (a, b);
+  if (i != 0)
+    abort ();
+  i = test29 (a, b);
+  if (i != 0)
+    abort ();
+  i = test30 (a, b);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b);
+  if (i != 1)
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 int test0 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_f_ps (a, b);
+}
+
+NOMIPS16 int test1 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_f_ps (a, b);
+}
+
+NOMIPS16 int test2 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_un_ps (a, b);
+}
+
+NOMIPS16 int test3 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_un_ps (a, b);
+}
+
+NOMIPS16 int test4 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_eq_ps (a, b);
+}
+
+NOMIPS16 int test5 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_eq_ps (a, b);
+}
+
+NOMIPS16 int test6 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_ueq_ps (a, b);
+}
+
+NOMIPS16 int test7 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_ueq_ps (a, b);
+}
+
+NOMIPS16 int test8 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_olt_ps (a, b);
+}
+
+NOMIPS16 int test9 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_olt_ps (a, b);
+}
+
+NOMIPS16 int test10 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_ult_ps (a, b);
+}
+
+NOMIPS16 int test11 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_ult_ps (a, b);
+}
+
+NOMIPS16 int test12 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_ole_ps (a, b);
+}
+
+NOMIPS16 int test13 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_ole_ps (a, b);
+}
+
+NOMIPS16 int test14 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_ule_ps (a, b);
+}
+
+NOMIPS16 int test15 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_ule_ps (a, b);
+}
+
+NOMIPS16 int test16 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_sf_ps (a, b);
+}
+
+NOMIPS16 int test17 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_sf_ps (a, b);
+}
+
+NOMIPS16 int test18 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_ngle_ps (a, b);
+}
+
+NOMIPS16 int test19 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_ngle_ps (a, b);
+}
+
+NOMIPS16 int test20 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_seq_ps (a, b);
+}
+
+NOMIPS16 int test21 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_seq_ps (a, b);
+}
+
+NOMIPS16 int test22 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_ngl_ps (a, b);
+}
+
+NOMIPS16 int test23 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_ngl_ps (a, b);
+}
+
+NOMIPS16 int test24 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_lt_ps (a, b);
+}
+
+NOMIPS16 int test25 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_lt_ps (a, b);
+}
+
+NOMIPS16 int test26 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_nge_ps (a, b);
+}
+
+NOMIPS16 int test27 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_nge_ps (a, b);
+}
+
+NOMIPS16 int test28 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_le_ps (a, b);
+}
+
+NOMIPS16 int test29 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_le_ps (a, b);
+}
+
+NOMIPS16 int test30 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_ngt_ps (a, b);
+}
+
+NOMIPS16 int test31 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_ngt_ps (a, b);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-3.c
new file mode 100644
index 000000000..7df590f5c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-3.c
@@ -0,0 +1,1095 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mips3d" } */
+
+/* Test MIPS-3D absolute compare builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+NOMIPS16 int test0 (v2sf a, v2sf b);
+NOMIPS16 int test1 (v2sf a, v2sf b);
+NOMIPS16 int test2 (v2sf a, v2sf b);
+NOMIPS16 int test3 (v2sf a, v2sf b);
+NOMIPS16 int test4 (v2sf a, v2sf b);
+NOMIPS16 int test5 (v2sf a, v2sf b);
+NOMIPS16 int test6 (v2sf a, v2sf b);
+NOMIPS16 int test7 (v2sf a, v2sf b);
+NOMIPS16 int test8 (v2sf a, v2sf b);
+NOMIPS16 int test9 (v2sf a, v2sf b);
+NOMIPS16 int test10 (v2sf a, v2sf b);
+NOMIPS16 int test11 (v2sf a, v2sf b);
+NOMIPS16 int test12 (v2sf a, v2sf b);
+NOMIPS16 int test13 (v2sf a, v2sf b);
+NOMIPS16 int test14 (v2sf a, v2sf b);
+NOMIPS16 int test15 (v2sf a, v2sf b);
+NOMIPS16 int test16 (v2sf a, v2sf b);
+NOMIPS16 int test17 (v2sf a, v2sf b);
+NOMIPS16 int test18 (v2sf a, v2sf b);
+NOMIPS16 int test19 (v2sf a, v2sf b);
+NOMIPS16 int test20 (v2sf a, v2sf b);
+NOMIPS16 int test21 (v2sf a, v2sf b);
+NOMIPS16 int test22 (v2sf a, v2sf b);
+NOMIPS16 int test23 (v2sf a, v2sf b);
+NOMIPS16 int test24 (v2sf a, v2sf b);
+NOMIPS16 int test25 (v2sf a, v2sf b);
+NOMIPS16 int test26 (v2sf a, v2sf b);
+NOMIPS16 int test27 (v2sf a, v2sf b);
+NOMIPS16 int test28 (v2sf a, v2sf b);
+NOMIPS16 int test29 (v2sf a, v2sf b);
+NOMIPS16 int test30 (v2sf a, v2sf b);
+NOMIPS16 int test31 (v2sf a, v2sf b);
+NOMIPS16 int test32 (v2sf a, v2sf b);
+NOMIPS16 int test33 (v2sf a, v2sf b);
+NOMIPS16 int test34 (v2sf a, v2sf b);
+NOMIPS16 int test35 (v2sf a, v2sf b);
+NOMIPS16 int test36 (v2sf a, v2sf b);
+NOMIPS16 int test37 (v2sf a, v2sf b);
+NOMIPS16 int test38 (v2sf a, v2sf b);
+NOMIPS16 int test39 (v2sf a, v2sf b);
+NOMIPS16 int test40 (v2sf a, v2sf b);
+NOMIPS16 int test41 (v2sf a, v2sf b);
+NOMIPS16 int test42 (v2sf a, v2sf b);
+NOMIPS16 int test43 (v2sf a, v2sf b);
+NOMIPS16 int test44 (v2sf a, v2sf b);
+NOMIPS16 int test45 (v2sf a, v2sf b);
+NOMIPS16 int test46 (v2sf a, v2sf b);
+NOMIPS16 int test47 (v2sf a, v2sf b);
+NOMIPS16 int test48 (v2sf a, v2sf b);
+NOMIPS16 int test49 (v2sf a, v2sf b);
+NOMIPS16 int test50 (v2sf a, v2sf b);
+NOMIPS16 int test51 (v2sf a, v2sf b);
+NOMIPS16 int test52 (v2sf a, v2sf b);
+NOMIPS16 int test53 (v2sf a, v2sf b);
+NOMIPS16 int test54 (v2sf a, v2sf b);
+NOMIPS16 int test55 (v2sf a, v2sf b);
+NOMIPS16 int test56 (v2sf a, v2sf b);
+NOMIPS16 int test57 (v2sf a, v2sf b);
+NOMIPS16 int test58 (v2sf a, v2sf b);
+NOMIPS16 int test59 (v2sf a, v2sf b);
+NOMIPS16 int test60 (v2sf a, v2sf b);
+NOMIPS16 int test61 (v2sf a, v2sf b);
+NOMIPS16 int test62 (v2sf a, v2sf b);
+NOMIPS16 int test63 (v2sf a, v2sf b);
+
+float qnan = 1.0f/0.0f - 1.0f/0.0f;
+
+NOMIPS16 int main ()
+{
+  int little_endian;
+  v2sf a, b, c, d;
+  int i, j, k, l;
+
+  union { long long ll; int i[2]; } endianness_test;
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  /* cabs.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {-56, -78};
+  i = 0;
+  j = 0;
+  k = 0;
+  l = 0;
+  if (__builtin_mips_any_cabs_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_upper_cabs_eq_ps(a, b) != j)
+     abort ();
+  if (__builtin_mips_lower_cabs_eq_ps(a, b) != k)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_ps(a, b) != l)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {-12, -78};
+  i = 1;
+  if (little_endian)
+    {
+      j = 0;
+      k = 1;
+    }
+  else
+    {
+      j = 1;
+      k = 0;
+    }
+  l = 0;
+  if (__builtin_mips_any_cabs_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_upper_cabs_eq_ps(a, b) != j)
+     abort ();
+  if (__builtin_mips_lower_cabs_eq_ps(a, b) != k)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_ps(a, b) != l)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {-56, -34};
+  i = 1;
+  if (little_endian)
+    {
+      j = 1;
+      k = 0;
+    }
+  else
+    {
+      j = 0;
+      k = 1;
+    }
+  l = 0;
+  if (__builtin_mips_any_cabs_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_upper_cabs_eq_ps(a, b) != j)
+     abort ();
+  if (__builtin_mips_lower_cabs_eq_ps(a, b) != k)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_ps(a, b) != l)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {-12, -34};
+  i = 1;
+  j = 1;
+  k = 1;
+  l = 1;
+  if (__builtin_mips_any_cabs_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_upper_cabs_eq_ps(a, b) != j)
+     abort ();
+  if (__builtin_mips_lower_cabs_eq_ps(a, b) != k)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_ps(a, b) != l)
+     abort ();
+
+  /* Test all comparisons */
+  if (little_endian)
+    {
+      a = (v2sf) {1984.0, 10.58};
+      b = (v2sf) {-1984.0, -567.345};
+    }
+  else
+    {
+      a = (v2sf) {10.58, 1984.0};
+      b = (v2sf) {-567.345, -1984.0};
+    }
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b);
+  if (i != 0)
+    abort ();
+  i = test4 (a, b);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b);
+  if (i != 0)
+    abort ();
+  i = test7 (a, b);
+  if (i != 0)
+    abort ();
+  i = test8 (a, b);
+  if (i != 1)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b);
+  if (i != 0)
+    abort ();
+  i = test12 (a, b);
+  if (i != 1)
+    abort ();
+  i = test13 (a, b);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 0)
+    abort ();
+  i = test16 (a, b);
+  if (i != 1)
+    abort ();
+  i = test17 (a, b);
+  if (i != 1)
+    abort ();
+  i = test18 (a, b);
+  if (i != 0)
+    abort ();
+  i = test19 (a, b);
+  if (i != 0)
+    abort ();
+  i = test20 (a, b);
+  if (i != 1)
+    abort ();
+  i = test21 (a, b);
+  if (i != 1)
+    abort ();
+  i = test22 (a, b);
+  if (i != 0)
+    abort ();
+  i = test23 (a, b);
+  if (i != 0)
+    abort ();
+  i = test24 (a, b);
+  if (i != 1)
+    abort ();
+  i = test25 (a, b);
+  if (i != 1)
+    abort ();
+  i = test26 (a, b);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b);
+  if (i != 1)
+    abort ();
+  i = test28 (a, b);
+  if (i != 1)
+    abort ();
+  i = test29 (a, b);
+  if (i != 1)
+    abort ();
+  i = test30 (a, b);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b);
+  if (i != 1)
+    abort ();
+  i = test32 (a, b);
+  if (i != 0)
+    abort ();
+  i = test33 (a, b);
+  if (i != 0)
+    abort ();
+  i = test34 (a, b);
+  if (i != 0)
+    abort ();
+  i = test35 (a, b);
+  if (i != 0)
+    abort ();
+  i = test36 (a, b);
+  if (i != 0)
+    abort ();
+  i = test37 (a, b);
+  if (i != 0)
+    abort ();
+  i = test38 (a, b);
+  if (i != 0)
+    abort ();
+  i = test39 (a, b);
+  if (i != 0)
+    abort ();
+  i = test40 (a, b);
+  if (i != 1)
+    abort ();
+  i = test41 (a, b);
+  if (i != 0)
+    abort ();
+  i = test42 (a, b);
+  if (i != 1)
+    abort ();
+  i = test43 (a, b);
+  if (i != 0)
+    abort ();
+  i = test44 (a, b);
+  if (i != 1)
+    abort ();
+  i = test45 (a, b);
+  if (i != 0)
+    abort ();
+  i = test46 (a, b);
+  if (i != 1)
+    abort ();
+  i = test47 (a, b);
+  if (i != 0)
+    abort ();
+  i = test48 (a, b);
+  if (i != 1)
+    abort ();
+  i = test49 (a, b);
+  if (i != 1)
+    abort ();
+  i = test50 (a, b);
+  if (i != 0)
+    abort ();
+  i = test51 (a, b);
+  if (i != 0)
+    abort ();
+  i = test52 (a, b);
+  if (i != 1)
+    abort ();
+  i = test53 (a, b);
+  if (i != 1)
+    abort ();
+  i = test54 (a, b);
+  if (i != 0)
+    abort ();
+  i = test55 (a, b);
+  if (i != 0)
+    abort ();
+  i = test56 (a, b);
+  if (i != 1)
+    abort ();
+  i = test57 (a, b);
+  if (i != 1)
+    abort ();
+  i = test58 (a, b);
+  if (i != 1)
+    abort ();
+  i = test59 (a, b);
+  if (i != 1)
+    abort ();
+  i = test60 (a, b);
+  if (i != 1)
+    abort ();
+  i = test61 (a, b);
+  if (i != 1)
+    abort ();
+  i = test62 (a, b);
+  if (i != 1)
+    abort ();
+  i = test63 (a, b);
+  if (i != 1)
+    abort ();
+
+  /* Reverse arguments */
+  i = test0 (b, a);
+  if (i != 0)
+    abort ();
+  i = test1 (b, a);
+  if (i != 0)
+    abort ();
+  i = test2 (b, a);
+  if (i != 0)
+    abort ();
+  i = test3 (b, a);
+  if (i != 0)
+    abort ();
+  i = test4 (b, a);
+  if (i != 0)
+    abort ();
+  i = test5 (b, a);
+  if (i != 0)
+    abort ();
+  i = test6 (b, a);
+  if (i != 0)
+    abort ();
+  i = test7 (b, a);
+  if (i != 0)
+    abort ();
+  i = test8 (b, a);
+  if (i != 1)
+    abort ();
+  i = test9 (b, a);
+  if (i != 0)
+    abort ();
+  i = test10 (b, a);
+  if (i != 1)
+    abort ();
+  i = test11 (b, a);
+  if (i != 0)
+    abort ();
+  i = test12 (b, a);
+  if (i != 1)
+    abort ();
+  i = test13 (b, a);
+  if (i != 0)
+    abort ();
+  i = test14 (b, a);
+  if (i != 1)
+    abort ();
+  i = test15 (b, a);
+  if (i != 0)
+    abort ();
+  i = test16 (b, a);
+  if (i != 0)
+    abort ();
+  i = test17 (b, a);
+  if (i != 0)
+    abort ();
+  i = test18 (b, a);
+  if (i != 0)
+    abort ();
+  i = test19 (b, a);
+  if (i != 0)
+    abort ();
+  i = test20 (b, a);
+  if (i != 0)
+    abort ();
+  i = test21 (b, a);
+  if (i != 0)
+    abort ();
+  i = test22 (b, a);
+  if (i != 0)
+    abort ();
+  i = test23 (b, a);
+  if (i != 0)
+    abort ();
+  i = test24 (b, a);
+  if (i != 1)
+    abort ();
+  i = test25 (b, a);
+  if (i != 0)
+    abort ();
+  i = test26 (b, a);
+  if (i != 1)
+    abort ();
+  i = test27 (b, a);
+  if (i != 0)
+    abort ();
+  i = test28 (b, a);
+  if (i != 1)
+    abort ();
+  i = test29 (b, a);
+  if (i != 0)
+    abort ();
+  i = test30 (b, a);
+  if (i != 1)
+    abort ();
+  i = test31 (b, a);
+  if (i != 0)
+    abort ();
+  i = test32 (b, a);
+  if (i != 0)
+    abort ();
+  i = test33 (b, a);
+  if (i != 0)
+    abort ();
+  i = test34 (b, a);
+  if (i != 0)
+    abort ();
+  i = test35 (b, a);
+  if (i != 0)
+    abort ();
+  i = test36 (b, a);
+  if (i != 0)
+    abort ();
+  i = test37 (b, a);
+  if (i != 0)
+    abort ();
+  i = test38 (b, a);
+  if (i != 0)
+    abort ();
+  i = test39 (b, a);
+  if (i != 0)
+    abort ();
+  i = test40 (b, a);
+  if (i != 1)
+    abort ();
+  i = test41 (b, a);
+  if (i != 0)
+    abort ();
+  i = test42 (b, a);
+  if (i != 1)
+    abort ();
+  i = test43 (b, a);
+  if (i != 0)
+    abort ();
+  i = test44 (b, a);
+  if (i != 1)
+    abort ();
+  i = test45 (b, a);
+  if (i != 0)
+    abort ();
+  i = test46 (b, a);
+  if (i != 1)
+    abort ();
+  i = test47 (b, a);
+  if (i != 0)
+    abort ();
+  i = test48 (b, a);
+  if (i != 0)
+    abort ();
+  i = test49 (b, a);
+  if (i != 0)
+    abort ();
+  i = test50 (b, a);
+  if (i != 0)
+    abort ();
+  i = test51 (b, a);
+  if (i != 0)
+    abort ();
+  i = test52 (b, a);
+  if (i != 0)
+    abort ();
+  i = test53 (b, a);
+  if (i != 0)
+    abort ();
+  i = test54 (b, a);
+  if (i != 0)
+    abort ();
+  i = test55 (b, a);
+  if (i != 0)
+    abort ();
+  i = test56 (b, a);
+  if (i != 1)
+    abort ();
+  i = test57 (b, a);
+  if (i != 0)
+    abort ();
+  i = test58 (b, a);
+  if (i != 1)
+    abort ();
+  i = test59 (b, a);
+  if (i != 0)
+    abort ();
+  i = test60 (b, a);
+  if (i != 1)
+    abort ();
+  i = test61 (b, a);
+  if (i != 0)
+    abort ();
+  i = test62 (b, a);
+  if (i != 1)
+    abort ();
+  i = test63 (b, a);
+  if (i != 0)
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test all comparisons */
+  if (little_endian)
+    {
+      a = (v2sf) {qnan, qnan};
+      b = (v2sf) {-1984.0, -567.345};
+    }
+  else
+    {
+      a = (v2sf) {qnan, qnan};
+      b = (v2sf) {-567.345, -1984.0};
+    }
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b);
+  if (i != 0)
+    abort ();
+  i = test4 (a, b);
+  if (i != 1)
+    abort ();
+  i = test5 (a, b);
+  if (i != 1)
+    abort ();
+  i = test6 (a, b);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 0)
+    abort ();
+  i = test11 (a, b);
+  if (i != 0)
+    abort ();
+  i = test12 (a, b);
+  if (i != 1)
+    abort ();
+  i = test13 (a, b);
+  if (i != 1)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+  i = test16 (a, b);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b);
+  if (i != 0)
+    abort ();
+  i = test19 (a, b);
+  if (i != 0)
+    abort ();
+  i = test20 (a, b);
+  if (i != 1)
+    abort ();
+  i = test21 (a, b);
+  if (i != 1)
+    abort ();
+  i = test22 (a, b);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b);
+  if (i != 1)
+    abort ();
+  i = test24 (a, b);
+  if (i != 0)
+    abort ();
+  i = test25 (a, b);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b);
+  if (i != 0)
+    abort ();
+  i = test27 (a, b);
+  if (i != 0)
+    abort ();
+  i = test28 (a, b);
+  if (i != 1)
+    abort ();
+  i = test29 (a, b);
+  if (i != 1)
+    abort ();
+  i = test30 (a, b);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b);
+  if (i != 1)
+    abort ();
+  i = test32 (a, b);
+  if (i != 0)
+    abort ();
+  i = test33 (a, b);
+  if (i != 0)
+    abort ();
+  i = test34 (a, b);
+  if (i != 0)
+    abort ();
+  i = test35 (a, b);
+  if (i != 0)
+    abort ();
+  i = test36 (a, b);
+  if (i != 1)
+    abort ();
+  i = test37 (a, b);
+  if (i != 1)
+    abort ();
+  i = test38 (a, b);
+  if (i != 1)
+    abort ();
+  i = test39 (a, b);
+  if (i != 1)
+    abort ();
+  i = test40 (a, b);
+  if (i != 0)
+    abort ();
+  i = test41 (a, b);
+  if (i != 0)
+    abort ();
+  i = test42 (a, b);
+  if (i != 0)
+    abort ();
+  i = test43 (a, b);
+  if (i != 0)
+    abort ();
+  i = test44 (a, b);
+  if (i != 1)
+    abort ();
+  i = test45 (a, b);
+  if (i != 1)
+    abort ();
+  i = test46 (a, b);
+  if (i != 1)
+    abort ();
+  i = test47 (a, b);
+  if (i != 1)
+    abort ();
+  i = test48 (a, b);
+  if (i != 0)
+    abort ();
+  i = test49 (a, b);
+  if (i != 0)
+    abort ();
+  i = test50 (a, b);
+  if (i != 0)
+    abort ();
+  i = test51 (a, b);
+  if (i != 0)
+    abort ();
+  i = test52 (a, b);
+  if (i != 1)
+    abort ();
+  i = test53 (a, b);
+  if (i != 1)
+    abort ();
+  i = test54 (a, b);
+  if (i != 1)
+    abort ();
+  i = test55 (a, b);
+  if (i != 1)
+    abort ();
+  i = test56 (a, b);
+  if (i != 0)
+    abort ();
+  i = test57 (a, b);
+  if (i != 0)
+    abort ();
+  i = test58 (a, b);
+  if (i != 0)
+    abort ();
+  i = test59 (a, b);
+  if (i != 0)
+    abort ();
+  i = test60 (a, b);
+  if (i != 1)
+    abort ();
+  i = test61 (a, b);
+  if (i != 1)
+    abort ();
+  i = test62 (a, b);
+  if (i != 1)
+    abort ();
+  i = test63 (a, b);
+  if (i != 1)
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 int test0 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_f_ps (a, b);
+}
+
+NOMIPS16 int test1 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_f_ps (a, b);
+}
+
+NOMIPS16 int test2 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_f_ps (a, b);
+}
+
+NOMIPS16 int test3 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_f_ps (a, b);
+}
+
+NOMIPS16 int test4 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_un_ps (a, b);
+}
+
+NOMIPS16 int test5 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_un_ps (a, b);
+}
+
+NOMIPS16 int test6 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_un_ps (a, b);
+}
+
+NOMIPS16 int test7 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_un_ps (a, b);
+}
+
+NOMIPS16 int test8 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_eq_ps (a, b);
+}
+
+NOMIPS16 int test9 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_eq_ps (a, b);
+}
+
+NOMIPS16 int test10 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_eq_ps (a, b);
+}
+
+NOMIPS16 int test11 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_eq_ps (a, b);
+}
+
+NOMIPS16 int test12 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_ueq_ps (a, b);
+}
+
+NOMIPS16 int test13 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_ueq_ps (a, b);
+}
+
+NOMIPS16 int test14 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_ueq_ps (a, b);
+}
+
+NOMIPS16 int test15 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_ueq_ps (a, b);
+}
+
+NOMIPS16 int test16 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_olt_ps (a, b);
+}
+
+NOMIPS16 int test17 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_olt_ps (a, b);
+}
+
+NOMIPS16 int test18 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_olt_ps (a, b);
+}
+
+NOMIPS16 int test19 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_olt_ps (a, b);
+}
+
+NOMIPS16 int test20 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_ult_ps (a, b);
+}
+
+NOMIPS16 int test21 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_ult_ps (a, b);
+}
+
+NOMIPS16 int test22 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_ult_ps (a, b);
+}
+
+NOMIPS16 int test23 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_ult_ps (a, b);
+}
+
+NOMIPS16 int test24 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_ole_ps (a, b);
+}
+
+NOMIPS16 int test25 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_ole_ps (a, b);
+}
+
+NOMIPS16 int test26 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_ole_ps (a, b);
+}
+
+NOMIPS16 int test27 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_ole_ps (a, b);
+}
+
+NOMIPS16 int test28 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_ule_ps (a, b);
+}
+
+NOMIPS16 int test29 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_ule_ps (a, b);
+}
+
+NOMIPS16 int test30 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_ule_ps (a, b);
+}
+
+NOMIPS16 int test31 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_ule_ps (a, b);
+}
+
+NOMIPS16 int test32 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_sf_ps (a, b);
+}
+
+NOMIPS16 int test33 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_sf_ps (a, b);
+}
+
+NOMIPS16 int test34 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_sf_ps (a, b);
+}
+
+NOMIPS16 int test35 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_sf_ps (a, b);
+}
+
+NOMIPS16 int test36 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_ngle_ps (a, b);
+}
+
+NOMIPS16 int test37 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_ngle_ps (a, b);
+}
+
+NOMIPS16 int test38 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_ngle_ps (a, b);
+}
+
+NOMIPS16 int test39 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_ngle_ps (a, b);
+}
+
+NOMIPS16 int test40 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_seq_ps (a, b);
+}
+
+NOMIPS16 int test41 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_seq_ps (a, b);
+}
+
+NOMIPS16 int test42 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_seq_ps (a, b);
+}
+
+NOMIPS16 int test43 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_seq_ps (a, b);
+}
+
+NOMIPS16 int test44 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_ngl_ps (a, b);
+}
+
+NOMIPS16 int test45 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_ngl_ps (a, b);
+}
+
+NOMIPS16 int test46 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_ngl_ps (a, b);
+}
+
+NOMIPS16 int test47 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_ngl_ps (a, b);
+}
+
+NOMIPS16 int test48 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_lt_ps (a, b);
+}
+
+NOMIPS16 int test49 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_lt_ps (a, b);
+}
+
+NOMIPS16 int test50 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_lt_ps (a, b);
+}
+
+NOMIPS16 int test51 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_lt_ps (a, b);
+}
+
+NOMIPS16 int test52 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_nge_ps (a, b);
+}
+
+NOMIPS16 int test53 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_nge_ps (a, b);
+}
+
+NOMIPS16 int test54 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_nge_ps (a, b);
+}
+
+NOMIPS16 int test55 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_nge_ps (a, b);
+}
+
+NOMIPS16 int test56 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_le_ps (a, b);
+}
+
+NOMIPS16 int test57 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_le_ps (a, b);
+}
+
+NOMIPS16 int test58 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_le_ps (a, b);
+}
+
+NOMIPS16 int test59 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_le_ps (a, b);
+}
+
+NOMIPS16 int test60 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_ngt_ps (a, b);
+}
+
+NOMIPS16 int test61 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_ngt_ps (a, b);
+}
+
+NOMIPS16 int test62 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_ngt_ps (a, b);
+}
+
+NOMIPS16 int test63 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_ngt_ps (a, b);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-4.c
new file mode 100644
index 000000000..7f9cbdb1b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-4.c
@@ -0,0 +1,590 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mips3d" } */
+
+/* Test MIPS-3D branch-if-any-four builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d);
+
+float qnan = 1.0f/0.0f - 1.0f/0.0f;
+
+NOMIPS16 int main ()
+{
+  v2sf a, b, c, d;
+  int i, j;
+
+  /* c.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {33, 44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {77, 88};
+  i = 0;
+  j = 0;
+  if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i)
+    abort ();
+  if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j)
+    abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {11, 44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {77, 88};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i)
+    abort ();
+  if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j)
+    abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {33, 22};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {77, 88};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i)
+    abort ();
+  if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j)
+    abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {33, 44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {55, 88};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i)
+    abort ();
+  if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j)
+    abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {33, 44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {77, 66};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i)
+    abort ();
+  if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j)
+    abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {11, 22};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {55, 66};
+  i = 1;
+  j = 1;
+  if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i)
+    abort ();
+  if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j)
+    abort ();
+
+  /* Test all comparisons */
+  a = (v2sf) {11, 33};
+  b = (v2sf) {33, 11};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {55, 88};
+
+  i = test0 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test4 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test5 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test8 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test9 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test12 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test13 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test16 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test19 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test20 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test21 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test22 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test24 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test25 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test28 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test29 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test30 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b, c, d);
+  if (i != 0)
+    abort ();
+
+  /* Reversed arguments */
+  i = test0 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test1 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test2 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test3 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test4 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test5 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test6 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test7 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test8 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test9 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test10 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test11 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test12 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test13 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test14 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test15 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test16 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test17 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test18 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test19 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test20 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test21 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test22 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test23 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test24 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test25 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test26 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test27 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test28 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test29 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test30 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test31 (b, a, d, c);
+  if (i != 0)
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test all comparisons */
+  a = (v2sf) {qnan, qnan};
+  b = (v2sf) {33, 11};
+  c = (v2sf) {qnan, qnan};
+  d = (v2sf) {55, 88};
+
+  i = test0 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test3 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test4 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test12 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test13 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test16 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test19 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test20 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test21 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test22 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test24 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test25 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test28 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test29 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test30 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b, c, d);
+  if (i != 1)
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_f_4s (a, b, c, d);
+}
+
+NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_f_4s (a, b, c, d);
+}
+
+NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_un_4s (a, b, c, d);
+}
+
+NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_un_4s (a, b, c, d);
+}
+
+NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_eq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_eq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_ueq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_ueq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_olt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_olt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_ult_4s (a, b, c, d);
+}
+
+NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_ult_4s (a, b, c, d);
+}
+
+NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_ole_4s (a, b, c, d);
+}
+
+NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_ole_4s (a, b, c, d);
+}
+
+NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_ule_4s (a, b, c, d);
+}
+
+NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_ule_4s (a, b, c, d);
+}
+
+NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_sf_4s (a, b, c, d);
+}
+
+NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_sf_4s (a, b, c, d);
+}
+
+NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_ngle_4s (a, b, c, d);
+}
+
+NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_ngle_4s (a, b, c, d);
+}
+
+NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_seq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_seq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_ngl_4s (a, b, c, d);
+}
+
+NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_ngl_4s (a, b, c, d);
+}
+
+NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_lt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_lt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_nge_4s (a, b, c, d);
+}
+
+NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_nge_4s (a, b, c, d);
+}
+
+NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_le_4s (a, b, c, d);
+}
+
+NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_le_4s (a, b, c, d);
+}
+
+NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_ngt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_ngt_4s (a, b, c, d);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-5.c
new file mode 100644
index 000000000..c07dbe505
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-5.c
@@ -0,0 +1,590 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mips3d" } */
+
+/* Test MIPS-3D absolute-compare & branch-if-any-four builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d);
+
+float qnan = 1.0f/0.0f - 1.0f/0.0f;
+
+NOMIPS16 int main ()
+{
+  v2sf a, b, c, d;
+  int i, j;
+
+  /* cabs.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {-33, -44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {-77, -88};
+  i = 0;
+  j = 0;
+  if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {-11, -44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {-77, -88};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {-33, -22};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {-77, -88};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {-33, -44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {-55, -88};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {-33, -44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {-77, -66};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {-11, -22};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {-55, -66};
+  i = 1;
+  j = 1;
+  if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j)
+     abort ();
+
+  /* Test all comparisons */
+  a = (v2sf) {11, 33};
+  b = (v2sf) {-33, -11};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {-55, -88};
+
+  i = test0 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test4 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test5 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test8 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test9 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test12 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test13 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test16 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test19 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test20 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test21 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test22 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test24 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test25 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test28 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test29 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test30 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b, c, d);
+  if (i != 0)
+    abort ();
+
+  /* Reversed arguments */
+  i = test0 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test1 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test2 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test3 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test4 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test5 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test6 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test7 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test8 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test9 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test10 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test11 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test12 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test13 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test14 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test15 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test16 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test17 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test18 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test19 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test20 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test21 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test22 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test23 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test24 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test25 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test26 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test27 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test28 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test29 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test30 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test31 (b, a, d, c);
+  if (i != 0)
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test all comparisons */
+  a = (v2sf) {qnan, qnan};
+  b = (v2sf) {-33, -11};
+  c = (v2sf) {qnan, qnan};
+  d = (v2sf) {-55, -88};
+
+  i = test0 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test3 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test4 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test12 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test13 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test16 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test19 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test20 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test21 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test22 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test24 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test25 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test28 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test29 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test30 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b, c, d);
+  if (i != 1)
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_f_4s (a, b, c, d);
+}
+
+NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_f_4s (a, b, c, d);
+}
+
+NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_un_4s (a, b, c, d);
+}
+
+NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_un_4s (a, b, c, d);
+}
+
+NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_eq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_eq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_ueq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_ueq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_olt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_olt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_ult_4s (a, b, c, d);
+}
+
+NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_ult_4s (a, b, c, d);
+}
+
+NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_ole_4s (a, b, c, d);
+}
+
+NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_ole_4s (a, b, c, d);
+}
+
+NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_ule_4s (a, b, c, d);
+}
+
+NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_ule_4s (a, b, c, d);
+}
+
+NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_sf_4s (a, b, c, d);
+}
+
+NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_sf_4s (a, b, c, d);
+}
+
+NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_ngle_4s (a, b, c, d);
+}
+
+NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_ngle_4s (a, b, c, d);
+}
+
+NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_seq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_seq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_ngl_4s (a, b, c, d);
+}
+
+NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_ngl_4s (a, b, c, d);
+}
+
+NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_lt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_lt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_nge_4s (a, b, c, d);
+}
+
+NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_nge_4s (a, b, c, d);
+}
+
+NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_le_4s (a, b, c, d);
+}
+
+NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_le_4s (a, b, c, d);
+}
+
+NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_ngt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_ngt_4s (a, b, c, d);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-6.c
new file mode 100644
index 000000000..848414540
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-6.c
@@ -0,0 +1,284 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mips3d" } */
+
+/* Test MIPS-3D absolute compare (floats) builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+NOMIPS16 int test0 (float a, float b);
+NOMIPS16 int test1 (float a, float b);
+NOMIPS16 int test2 (float a, float b);
+NOMIPS16 int test3 (float a, float b);
+NOMIPS16 int test4 (float a, float b);
+NOMIPS16 int test5 (float a, float b);
+NOMIPS16 int test6 (float a, float b);
+NOMIPS16 int test7 (float a, float b);
+NOMIPS16 int test8 (float a, float b);
+NOMIPS16 int test9 (float a, float b);
+NOMIPS16 int test10 (float a, float b);
+NOMIPS16 int test11 (float a, float b);
+NOMIPS16 int test12 (float a, float b);
+NOMIPS16 int test13 (float a, float b);
+NOMIPS16 int test14 (float a, float b);
+NOMIPS16 int test15 (float a, float b);
+
+NOMIPS16 int main ()
+{
+  float a, b;
+  int i;
+
+  /* cabs.eq.s */
+  a = 12;
+  b = -56;
+  i = 0;
+  if (__builtin_mips_cabs_eq_s(a, b) != i)
+     abort ();
+
+  /* cabs.eq.s */
+  a = 12;
+  b = -12;
+  i = 1;
+  if (__builtin_mips_cabs_eq_s(a, b) != i)
+     abort ();
+
+  /* Test all comparisons */
+  a = 10.58;
+  b = 567.345;
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b);
+  if (i != 0)
+    abort ();
+  i = test4 (a, b);
+  if (i != 1)
+    abort ();
+  i = test5 (a, b);
+  if (i != 1)
+    abort ();
+  i = test6 (a, b);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 0)
+    abort ();
+  i = test11 (a, b);
+  if (i != 0)
+    abort ();
+  i = test12 (a, b);
+  if (i != 1)
+    abort ();
+  i = test13 (a, b);
+  if (i != 1)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+
+  /* Reversed arguments */
+  i = test0 (b, a);
+  if (i != 0)
+    abort ();
+  i = test1 (b, a);
+  if (i != 0)
+    abort ();
+  i = test2 (b, a);
+  if (i != 0)
+    abort ();
+  i = test3 (b, a);
+  if (i != 0)
+    abort ();
+  i = test4 (b, a);
+  if (i != 0)
+    abort ();
+  i = test5 (b, a);
+  if (i != 0)
+    abort ();
+  i = test6 (b, a);
+  if (i != 0)
+    abort ();
+  i = test7 (b, a);
+  if (i != 0)
+    abort ();
+  i = test8 (b, a);
+  if (i != 0)
+    abort ();
+  i = test9 (b, a);
+  if (i != 0)
+    abort ();
+  i = test10 (b, a);
+  if (i != 0)
+    abort ();
+  i = test11 (b, a);
+  if (i != 0)
+    abort ();
+  i = test12 (b, a);
+  if (i != 0)
+    abort ();
+  i = test13 (b, a);
+  if (i != 0)
+    abort ();
+  i = test14 (b, a);
+  if (i != 0)
+    abort ();
+  i = test15 (b, a);
+  if (i != 0)
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test all comparisons */
+  a = 1.0f/0.0f - 1.0f/0.0f; // QNaN
+  b = 567.345;
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 1)
+    abort ();
+  i = test2 (a, b);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b);
+  if (i != 1)
+    abort ();
+  i = test4 (a, b);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b);
+  if (i != 1)
+    abort ();
+  i = test6 (a, b);
+  if (i != 0)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b);
+  if (i != 1)
+    abort ();
+  i = test10 (a, b);
+  if (i != 0)
+    abort ();
+  i = test11 (a, b);
+  if (i != 1)
+    abort ();
+  i = test12 (a, b);
+  if (i != 0)
+    abort ();
+  i = test13 (a, b);
+  if (i != 1)
+    abort ();
+  i = test14 (a, b);
+  if (i != 0)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 int test0 (float a, float b)
+{
+  return __builtin_mips_cabs_f_s (a, b);
+}
+
+NOMIPS16 int test1 (float a, float b)
+{
+  return __builtin_mips_cabs_un_s (a, b);
+}
+
+NOMIPS16 int test2 (float a, float b)
+{
+  return __builtin_mips_cabs_eq_s (a, b);
+}
+
+NOMIPS16 int test3 (float a, float b)
+{
+  return __builtin_mips_cabs_ueq_s (a, b);
+}
+
+NOMIPS16 int test4 (float a, float b)
+{
+  return __builtin_mips_cabs_olt_s (a, b);
+}
+
+NOMIPS16 int test5 (float a, float b)
+{
+  return __builtin_mips_cabs_ult_s (a, b);
+}
+
+NOMIPS16 int test6 (float a, float b)
+{
+  return __builtin_mips_cabs_ole_s (a, b);
+}
+
+NOMIPS16 int test7 (float a, float b)
+{
+  return __builtin_mips_cabs_ule_s (a, b);
+}
+
+NOMIPS16 int test8 (float a, float b)
+{
+  return __builtin_mips_cabs_sf_s (a, b);
+}
+
+NOMIPS16 int test9 (float a, float b)
+{
+  return __builtin_mips_cabs_ngle_s (a, b);
+}
+
+NOMIPS16 int test10 (float a, float b)
+{
+  return __builtin_mips_cabs_seq_s (a, b);
+}
+
+NOMIPS16 int test11 (float a, float b)
+{
+  return __builtin_mips_cabs_ngl_s (a, b);
+}
+
+NOMIPS16 int test12 (float a, float b)
+{
+  return __builtin_mips_cabs_lt_s (a, b);
+}
+
+NOMIPS16 int test13 (float a, float b)
+{
+  return __builtin_mips_cabs_nge_s (a, b);
+}
+
+NOMIPS16 int test14 (float a, float b)
+{
+  return __builtin_mips_cabs_le_s (a, b);
+}
+
+NOMIPS16 int test15 (float a, float b)
+{
+  return __builtin_mips_cabs_ngt_s (a, b);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-7.c
new file mode 100644
index 000000000..d5d09f998
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-7.c
@@ -0,0 +1,284 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mips3d" } */
+
+/* Test MIPS-3D absolute compare (doubles) builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+NOMIPS16 int test0 (double a, double b);
+NOMIPS16 int test1 (double a, double b);
+NOMIPS16 int test2 (double a, double b);
+NOMIPS16 int test3 (double a, double b);
+NOMIPS16 int test4 (double a, double b);
+NOMIPS16 int test5 (double a, double b);
+NOMIPS16 int test6 (double a, double b);
+NOMIPS16 int test7 (double a, double b);
+NOMIPS16 int test8 (double a, double b);
+NOMIPS16 int test9 (double a, double b);
+NOMIPS16 int test10 (double a, double b);
+NOMIPS16 int test11 (double a, double b);
+NOMIPS16 int test12 (double a, double b);
+NOMIPS16 int test13 (double a, double b);
+NOMIPS16 int test14 (double a, double b);
+NOMIPS16 int test15 (double a, double b);
+
+NOMIPS16 int main ()
+{
+  double a, b;
+  int i;
+
+  /* cabs.eq.d */
+  a = 12;
+  b = -56;
+  i = 0;
+  if (__builtin_mips_cabs_eq_d(a, b) != i)
+     abort ();
+
+  /* cabs.eq.d */
+  a = 12;
+  b = -12;
+  i = 1;
+  if (__builtin_mips_cabs_eq_d(a, b) != i)
+     abort ();
+
+  /* Test all operators */
+  a = 1984.0;
+  b = 1984.0;
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 1)
+    abort ();
+  i = test3 (a, b);
+  if (i != 1)
+    abort ();
+  i = test4 (a, b);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b);
+  if (i != 1)
+    abort ();
+  i = test12 (a, b);
+  if (i != 0)
+    abort ();
+  i = test13 (a, b);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+
+  /* Reverse arguments */
+  i = test0 (b, a);
+  if (i != 0)
+    abort ();
+  i = test1 (b, a);
+  if (i != 0)
+    abort ();
+  i = test2 (b, a);
+  if (i != 1)
+    abort ();
+  i = test3 (b, a);
+  if (i != 1)
+    abort ();
+  i = test4 (b, a);
+  if (i != 0)
+    abort ();
+  i = test5 (b, a);
+  if (i != 0)
+    abort ();
+  i = test6 (b, a);
+  if (i != 1)
+    abort ();
+  i = test7 (b, a);
+  if (i != 1)
+    abort ();
+  i = test8 (b, a);
+  if (i != 0)
+    abort ();
+  i = test9 (b, a);
+  if (i != 0)
+    abort ();
+  i = test10 (b, a);
+  if (i != 1)
+    abort ();
+  i = test11 (b, a);
+  if (i != 1)
+    abort ();
+  i = test12 (b, a);
+  if (i != 0)
+    abort ();
+  i = test13 (b, a);
+  if (i != 0)
+    abort ();
+  i = test14 (b, a);
+  if (i != 1)
+    abort ();
+  i = test15 (b, a);
+  if (i != 1)
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test all operators */
+  a = 1.0/0.0 - 1.0/0.0; // QNaN
+  b = 1.0/0.0 - 1.0/0.0; // QNaN
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 1)
+    abort ();
+  i = test2 (a, b);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b);
+  if (i != 1)
+    abort ();
+  i = test4 (a, b);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b);
+  if (i != 1)
+    abort ();
+  i = test6 (a, b);
+  if (i != 0)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b);
+  if (i != 1)
+    abort ();
+  i = test10 (a, b);
+  if (i != 0)
+    abort ();
+  i = test11 (a, b);
+  if (i != 1)
+    abort ();
+  i = test12 (a, b);
+  if (i != 0)
+    abort ();
+  i = test13 (a, b);
+  if (i != 1)
+    abort ();
+  i = test14 (a, b);
+  if (i != 0)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 int test0 (double a, double b)
+{
+  return __builtin_mips_cabs_f_d (a, b);
+}
+
+NOMIPS16 int test1 (double a, double b)
+{
+  return __builtin_mips_cabs_un_d (a, b);
+}
+
+NOMIPS16 int test2 (double a, double b)
+{
+  return __builtin_mips_cabs_eq_d (a, b);
+}
+
+NOMIPS16 int test3 (double a, double b)
+{
+  return __builtin_mips_cabs_ueq_d (a, b);
+}
+
+NOMIPS16 int test4 (double a, double b)
+{
+  return __builtin_mips_cabs_olt_d (a, b);
+}
+
+NOMIPS16 int test5 (double a, double b)
+{
+  return __builtin_mips_cabs_ult_d (a, b);
+}
+
+NOMIPS16 int test6 (double a, double b)
+{
+  return __builtin_mips_cabs_ole_d (a, b);
+}
+
+NOMIPS16 int test7 (double a, double b)
+{
+  return __builtin_mips_cabs_ule_d (a, b);
+}
+
+NOMIPS16 int test8 (double a, double b)
+{
+  return __builtin_mips_cabs_sf_d (a, b);
+}
+
+NOMIPS16 int test9 (double a, double b)
+{
+  return __builtin_mips_cabs_ngle_d (a, b);
+}
+
+NOMIPS16 int test10 (double a, double b)
+{
+  return __builtin_mips_cabs_seq_d (a, b);
+}
+
+NOMIPS16 int test11 (double a, double b)
+{
+  return __builtin_mips_cabs_ngl_d (a, b);
+}
+
+NOMIPS16 int test12 (double a, double b)
+{
+  return __builtin_mips_cabs_lt_d (a, b);
+}
+
+NOMIPS16 int test13 (double a, double b)
+{
+  return __builtin_mips_cabs_nge_d (a, b);
+}
+
+NOMIPS16 int test14 (double a, double b)
+{
+  return __builtin_mips_cabs_le_d (a, b);
+}
+
+NOMIPS16 int test15 (double a, double b)
+{
+  return __builtin_mips_cabs_ngt_d (a, b);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-8.c
new file mode 100644
index 000000000..c80f2b9c8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-8.c
@@ -0,0 +1,630 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mips3d" } */
+
+/* Test MIPS-3D absolute compare and conditional move builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__((vector_size(8)));
+
+NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d);
+
+float qnan = 1.0f/0.0f - 1.0f/0.0f;
+
+NOMIPS16 int main ()
+{
+  v2sf a, b, c, d, e, f;
+
+  /* Case 1 {diff, diff} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {-7, -6};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 123};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 78};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* Case 2 {same, diff} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {-5, -6};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 123};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 78};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* Case 3 {diff, same} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {-9, -12};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 78};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 123};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* Case 4 {same, same} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {-5, -12};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 78};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 123};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* Test all 16 operators */
+  a = (v2sf) {-123, 123};
+  b = (v2sf) {1000, -1000};
+  c = (v2sf) {-33, 123};
+  d = (v2sf) {8, -78};
+
+  e = test0 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c))
+    abort ();
+  e = test1 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d))
+    abort ();
+
+  e = test2 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test3 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test4 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test5 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test6 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test7 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test8 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test9 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test10 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test11 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test12 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test13 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test14 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test15 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test16 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test17 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test18 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test19 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test20 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test21 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test22 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test23 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test24 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test25 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test26 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test27 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test28 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test29 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test30 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test31 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  /* Reversed arguments */
+  e = test0 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c))
+    abort ();
+  e = test1 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d))
+    abort ();
+
+  e = test2 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test3 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test4 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test5 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test6 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test7 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test8 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test9 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test10 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test11 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test12 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test13 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test14 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test15 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test16 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test17 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test18 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test19 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test20 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test21 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test22 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test23 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test24 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test25 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test26 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test27 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test28 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test29 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test30 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test31 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test all 16 operators */
+  a = (v2sf) {qnan, qnan};
+  b = (v2sf) {1000, -1000};
+  c = (v2sf) {8, -78};
+  d = (v2sf) {-33, 123};
+
+  e = test0 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c))
+    abort ();
+  e = test1 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d))
+    abort ();
+
+  e = test2 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test3 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test4 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test5 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test6 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test7 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test8 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test9 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test10 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test11 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test12 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test13 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test14 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test15 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test16 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test17 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test18 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test19 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test20 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test21 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test22 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test23 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test24 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test25 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test26 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test27 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test28 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test29 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test30 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test31 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_f_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_f_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_un_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_un_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_eq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_eq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_ueq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_ueq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_olt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_olt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_ult_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_ult_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_ole_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_ole_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_ule_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_ule_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_sf_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_sf_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_ngle_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_ngle_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_seq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_seq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_ngl_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_ngl_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_lt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_lt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_nge_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_nge_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_le_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_le_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_ngt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_ngt_ps (a, b, c, d);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-9.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-9.c
new file mode 100644
index 000000000..3875391b5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-3d-9.c
@@ -0,0 +1,158 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mips3d" } */
+
+/* Matrix Multiplications */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__((vector_size(8)));
+
+float a[4] = {1.1, 2.2, 3.3, 4.4};
+float b[4][4] = {{1, 2, 3, 4},
+                 {5, 6, 7, 8},
+                 {9, 10, 11, 12},
+                 {13, 14, 15, 16}};
+
+float c[4]; /* Result for matrix_multiply1() */
+float d[4]; /* Result for matrix_multiply2() */
+float e[4]; /* Result for matrix_multiply3() */
+float f[4]; /* Result for matrix_multiply4() */
+
+void matrix_multiply1();
+NOMIPS16 void matrix_multiply2();
+NOMIPS16 void matrix_multiply3();
+NOMIPS16 void matrix_multiply4();
+
+int main ()
+{
+  int i;
+
+  /* Version 1. Use float calculations */
+  matrix_multiply1();
+
+  /* Version 2. Use paired-single instructions inside the inner loop*/
+  matrix_multiply2();
+  for (i = 0; i < 4; i++)
+    if (d[i] != c[i])
+      abort();
+
+  /* Version 3. Use paired-single instructions and unroll the inner loop */
+  matrix_multiply3();
+  for (i = 0; i < 4; i++)
+    if (e[i] != c[i])
+      abort();
+
+  /* Version 4. Use paired-single instructions and unroll all loops */
+  matrix_multiply4();
+  for (i = 0; i < 4; i++)
+    if (f[i] != c[i])
+      abort();
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+void matrix_multiply1()
+{
+  int i, j;
+
+  for (i = 0; i < 4; i++)
+   {
+     c[i] = 0.0;
+
+     for (j = 0; j < 4; j ++)
+       c[i] += a[j] * b[j][i]; 
+   }
+}
+
+NOMIPS16 void matrix_multiply2()
+{
+  int i, j;
+  v2sf m1, m2;
+  v2sf result, temp;
+
+  for (i = 0; i < 4; i++)
+   {
+     result = (v2sf) {0.0, 0.0};
+
+     for (j = 0; j < 4; j+=2)
+     {
+       /* Load two float values into m1 */
+       m1 = (v2sf) {a[j], a[j+1]};
+       m2 = (v2sf) {b[j][i], b[j+1][i]};
+
+       /* Multiply and add */
+       result += m1 * m2;
+     }
+     
+     /* Reduction add at the end */
+     temp = __builtin_mips_addr_ps (result, result);
+     d[i] = __builtin_mips_cvt_s_pl (temp);
+   }
+}
+
+NOMIPS16 void matrix_multiply3()
+{
+  int i;
+  v2sf m1, m2, n1, n2;
+  v2sf result, temp;
+
+  m1 = (v2sf) {a[0], a[1]};
+  m2 = (v2sf) {a[2], a[3]};
+
+  for (i = 0; i < 4; i++)
+   {
+     n1 = (v2sf) {b[0][i], b[1][i]};
+     n2 = (v2sf) {b[2][i], b[3][i]};
+
+     /* Multiply and add */
+     result = m1 * n1 + m2 * n2;
+     
+     /* Reduction add at the end */
+     temp = __builtin_mips_addr_ps (result, result);
+     e[i] = __builtin_mips_cvt_s_pl (temp);
+   }
+}
+
+NOMIPS16 void matrix_multiply4()
+{
+  v2sf m1, m2;
+  v2sf n1, n2, n3, n4, n5, n6, n7, n8;
+  v2sf temp1, temp2, temp3, temp4;
+  v2sf result1, result2;
+
+  /* Load a[0] a[1] values into m1
+     Load a[2] a[3] values into m2 */
+  m1 = (v2sf) {a[0], a[1]};
+  m2 = (v2sf) {a[2], a[3]};
+
+  /* Load b[0][0] b[1][0] values into n1
+     Load b[2][0] b[3][0] values into n2
+     Load b[0][1] b[1][1] values into n3
+     Load b[2][1] b[3][1] values into n4
+     Load b[0][2] b[1][2] values into n5
+     Load b[2][2] b[3][2] values into n6
+     Load b[0][3] b[1][3] values into n7
+     Load b[2][3] b[3][3] values into n8 */
+  n1 = (v2sf) {b[0][0], b[1][0]};
+  n2 = (v2sf) {b[2][0], b[3][0]};
+  n3 = (v2sf) {b[0][1], b[1][1]};
+  n4 = (v2sf) {b[2][1], b[3][1]};
+  n5 = (v2sf) {b[0][2], b[1][2]};
+  n6 = (v2sf) {b[2][2], b[3][2]};
+  n7 = (v2sf) {b[0][3], b[1][3]};
+  n8 = (v2sf) {b[2][3], b[3][3]};
+
+  temp1 = m1 * n1 + m2 * n2;
+  temp2 = m1 * n3 + m2 * n4;
+  temp3 = m1 * n5 + m2 * n6;
+  temp4 = m1 * n7 + m2 * n8;
+
+  result1 = __builtin_mips_addr_ps (temp1, temp2);
+  result2 = __builtin_mips_addr_ps (temp3, temp4);
+  
+  f[0] = __builtin_mips_cvt_s_pu (result1);
+  f[1] = __builtin_mips_cvt_s_pl (result1);
+  f[2] = __builtin_mips_cvt_s_pu (result2);
+  f[3] = __builtin_mips_cvt_s_pl (result2);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/README b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/README
new file mode 100644
index 000000000..bdd62c193
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/README
@@ -0,0 +1,20 @@
+These tests are meant to test the interoperability of PIC and nonpic objects for mips.
+This table shows the various combinations and each case is tested by one of the nonpic tests.
+Test Case	The PIC code        	The non-PIC code        The result (stub and/or PLT)
+
+main-1.c	nothing           	nothing              	Neither (trivial)
+main-2.c	nothing           	call only		PLT entry
+main-3.c	nothing           	address taken only	Neither (* But creating a PLT entry is valid)
+main-4.c	nothing           	address and call	PLT entry
+main-5.c	call only           	nothing			.MIPS.stubs entry
+main-6.c	call only           	call only		.MIPS.stubs and PLT
+main-7.c	call only           	address taken only	.MIPS.stubs (* Also creating a PLT entry is valid)
+main-8.c	call only           	address and call	.MIPS.stubs and PLT entry
+main-9.c	address taken only	nothing			Neither
+main-10.c	address taken only	call only		PLT entry
+main-11.c	address taken only	address taken only	Neither (* But creating a PLT entry is valid)
+main-12.c	address taken only	address and call	PLT entry
+main-13.c	address and call	nothing			Neither
+main-14.c	address and call	call only		PLT entry
+main-15.c	address and call	address taken only	Neither (* But creating a PLT entry is valid)
+main-16.c	address and call	address and call	PLT entry
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-1.c
new file mode 100644
index 000000000..2f428717a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-1.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-nothing.o nonpic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_nothing ();
+  pic_nothing ();
+
+  if (hit_nonpic_nothing != 1)
+    abort ();
+
+  if (hit_pic_nothing != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-10.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-10.c
new file mode 100644
index 000000000..6c3601861
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-10.c
@@ -0,0 +1,18 @@
+/* { dg-options "nonpic-call.o pic-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_call ();
+  pic_addr ();
+
+  if (hit_nonpic_call != 1)
+    abort ();
+
+  if (hit_pic_addr != 2)
+    abort ();
+
+  exit (0);
+
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-11.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-11.c
new file mode 100644
index 000000000..1d8a6d20c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-11.c
@@ -0,0 +1,17 @@
+/* { dg-options "nonpic-addr.o pic-addr.o nonpic-receive-fn-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_addr ();
+  pic_addr ();
+
+  if (hit_nonpic_addr != 1)
+    abort ();
+
+  if (hit_pic_addr != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-12.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-12.c
new file mode 100644
index 000000000..f57b5ce17
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-12.c
@@ -0,0 +1,17 @@
+/* { dg-options "nonpic-addr-call.o pic-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_addr_call ();
+  pic_addr ();
+
+  if (hit_nonpic_addr_call != 1)
+    abort ();
+
+  if (hit_pic_addr != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-13.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-13.c
new file mode 100644
index 000000000..d2b88e1f3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-13.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-addr-call.o nonpic-receive-fn-addr.o nonpic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_nothing ();
+  pic_addr_call ();
+
+  if (hit_nonpic_nothing != 1)
+    abort ();
+
+  if (hit_pic_addr_call != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-14.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-14.c
new file mode 100644
index 000000000..6318a2240
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-14.c
@@ -0,0 +1,17 @@
+/* { dg-options "nonpic-call.o pic-addr.o pic-receive-fn-addr.o pic-addr-call.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_call ();
+  pic_addr_call ();
+
+  if (hit_nonpic_call != 1)
+    abort ();
+
+  if (hit_pic_addr_call != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-15.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-15.c
new file mode 100644
index 000000000..1c165043a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-15.c
@@ -0,0 +1,17 @@
+/* { dg-options "nonpic-addr.o pic-receive-fn-addr.o pic-addr-call.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_addr ();
+  pic_addr_call ();
+
+  if (hit_nonpic_addr != 1)
+    abort ();
+
+  if (hit_pic_addr_call != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-16.c
new file mode 100644
index 000000000..3119979d3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-16.c
@@ -0,0 +1,17 @@
+/* { dg-options "nonpic-addr-call.o pic-receive-fn-addr.o pic-addr-call.o nonpic-receive-fn-addr.o pic-nothing.o nonpic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_addr_call ();
+  pic_addr_call ();
+
+  if (hit_nonpic_addr_call != 1)
+    abort ();
+
+  if (hit_pic_addr_call != 1)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-2.c
new file mode 100644
index 000000000..8a66e7a7a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-2.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-addr.o nonpic-call.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_call ();
+  pic_nothing ();
+
+  if (hit_nonpic_call != 1)
+    abort ();
+
+  if (hit_pic_nothing != 2)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-3.c
new file mode 100644
index 000000000..c9c8dac70
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-3.c
@@ -0,0 +1,17 @@
+/* { dg-options "nonpic-addr.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_addr ();
+  pic_nothing ();
+
+  if (hit_nonpic_addr != 1)
+    abort ();
+
+  if (hit_pic_nothing != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-4.c
new file mode 100644
index 000000000..c10c213ac
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-4.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-addr.o pic-receive-fn-addr.o nonpic-addr-call.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_addr_call ();
+  pic_nothing ();
+
+  if (hit_nonpic_addr_call != 1)
+    abort ();
+
+  if (hit_pic_nothing != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-5.c
new file mode 100644
index 000000000..9b6dd8aff
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-5.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-addr.o pic-call.o nonpic-addr.o pic-receive-fn-addr.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_nothing ();
+  pic_call ();
+
+  if (hit_nonpic_nothing != 2)
+    abort ();
+
+  if (hit_pic_call != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-6.c
new file mode 100644
index 000000000..90b220f0f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-6.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-call.o nonpic-call.o nonpic-addr.o pic-addr.o nonpic-receive-fn-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  pic_call ();
+  nonpic_call ();
+
+  if (hit_pic_call != 1)
+    abort ();
+
+  if (hit_nonpic_call != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-7.c
new file mode 100644
index 000000000..8cef63f3c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-7.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-call.o nonpic-addr.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  pic_call ();
+  nonpic_addr ();
+
+  if (hit_pic_call != 1)
+    abort ();
+
+  if (hit_nonpic_addr != 2)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-8.c
new file mode 100644
index 000000000..0200bf2dd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-8.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-call.o nonpic-addr-call.o nonpic-addr.o nonpic-receive-fn-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  pic_call ();
+  nonpic_addr_call ();
+
+  if (hit_pic_call != 1)
+    abort ();
+
+  if (hit_nonpic_addr_call != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-9.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-9.c
new file mode 100644
index 000000000..4144172cc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/main-9.c
@@ -0,0 +1,10 @@
+/* { dg-options "pic-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  pic_addr ();
+  nonpic_nothing ();
+  exit (0);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.exp
new file mode 100644
index 000000000..47443acda
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.exp
@@ -0,0 +1,54 @@
+#   Copyright (C) 2008 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+load_lib gcc-dg.exp
+load_lib target-supports.exp
+
+# Exit immediately if this isn't a MIPS target.
+if ![istarget mips*-*-*] {
+  return
+}
+
+# Pic and nonpic are not link-compatible for VXWorks targets.
+if [istarget mips*-*-vxworks] {
+  return
+}
+
+if { ![check_effective_target_fpic] } {
+  return
+}
+
+dg-init
+
+set old-dg-do-what-default "${dg-do-what-default}"
+set dg-do-what-default "assemble"
+
+foreach testcase [lsort [glob -nocomplain $srcdir/$subdir/pic-*.c]] {
+    verbose "Compiling [file tail [file dirname $testcase]]/[file tail $testcase]"
+    dg-test -keep-output $testcase "-fpic" ""
+}
+
+foreach testcase [lsort [glob -nocomplain $srcdir/$subdir/nonpic-*.c]] {
+    verbose "Compiling [file tail [file dirname $testcase]]/[file tail $testcase]"
+    dg-test -keep-output $testcase "-fno-pic" ""
+}
+
+set dg-do-what-default "run"
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/main-*.c]] "-fno-pic" ""
+
+set dg-do-what-default "${old-dg-do-what-default}"
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.h b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.h
new file mode 100644
index 000000000..e9fe99218
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.h
@@ -0,0 +1,20 @@
+extern int hit_pic_addr;
+extern int hit_pic_addr_call;
+extern int hit_pic_nothing;
+extern int hit_pic_call;
+
+extern int hit_nonpic_addr;
+extern int hit_nonpic_addr_call;
+extern int hit_nonpic_call;
+extern int hit_nonpic_nothing;
+
+extern void nonpic_addr (void);
+extern void nonpic_nothing (void);
+extern void nonpic_receive_fn_addr (void *);
+
+extern void pic_addr (void);
+extern void pic_receive_fn_addr (void *);
+extern void pic_nothing (void);
+
+extern void abort (void);
+extern void exit (int);
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr-call.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr-call.c
new file mode 100644
index 000000000..19d0e4349
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr-call.c
@@ -0,0 +1,8 @@
+#include "mips-nonpic.h"
+int hit_nonpic_addr_call = 0;
+void
+nonpic_addr_call (void)
+{
+  hit_nonpic_addr_call++;
+  pic_receive_fn_addr (&pic_nothing);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr.c
new file mode 100644
index 000000000..c919e83b9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr.c
@@ -0,0 +1,8 @@
+#include "mips-nonpic.h"
+int hit_nonpic_addr = 0;
+void
+nonpic_addr ()
+{
+  nonpic_receive_fn_addr (&nonpic_nothing);
+  hit_nonpic_addr++;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-call.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-call.c
new file mode 100644
index 000000000..8d368b42e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-call.c
@@ -0,0 +1,9 @@
+#include "mips-nonpic.h"
+int hit_nonpic_call = 0;
+void
+nonpic_call ()
+{
+ pic_nothing ();
+ pic_addr ();
+ hit_nonpic_call++;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-nothing.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-nothing.c
new file mode 100644
index 000000000..90356fb24
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-nothing.c
@@ -0,0 +1,7 @@
+#include "mips-nonpic.h"
+int hit_nonpic_nothing = 0;
+void
+nonpic_nothing ()
+{
+  hit_nonpic_nothing++;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-receive-fn-addr.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-receive-fn-addr.c
new file mode 100644
index 000000000..8b548c9ef
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-receive-fn-addr.c
@@ -0,0 +1,7 @@
+#include "mips-nonpic.h"
+void
+nonpic_receive_fn_addr (void *x)
+{
+  if (x != &nonpic_nothing)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr-call.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr-call.c
new file mode 100644
index 000000000..2db729392
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr-call.c
@@ -0,0 +1,8 @@
+#include "mips-nonpic.h"
+int hit_pic_addr_call = 0;
+void
+pic_addr_call (void)
+{
+  hit_pic_addr_call++;
+  nonpic_receive_fn_addr (&nonpic_nothing);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr.c
new file mode 100644
index 000000000..a90739235
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr.c
@@ -0,0 +1,8 @@
+#include "mips-nonpic.h"
+int hit_pic_addr = 0;
+void
+pic_addr ()
+{
+  pic_receive_fn_addr (&pic_nothing);
+  hit_pic_addr++;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-call.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-call.c
new file mode 100644
index 000000000..0c73b9333
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-call.c
@@ -0,0 +1,9 @@
+#include "mips-nonpic.h"
+int hit_pic_call = 0;
+void
+pic_call ()
+{
+ nonpic_nothing ();
+ nonpic_addr ();
+ hit_pic_call++;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-nothing.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-nothing.c
new file mode 100644
index 000000000..3e4539081
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-nothing.c
@@ -0,0 +1,7 @@
+#include "mips-nonpic.h"
+int hit_pic_nothing = 0;
+void
+pic_nothing ()
+{
+  hit_pic_nothing++;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-receive-fn-addr.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-receive-fn-addr.c
new file mode 100644
index 000000000..4a40e0a18
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-receive-fn-addr.c
@@ -0,0 +1,7 @@
+#include "mips-nonpic.h"
+void
+pic_receive_fn_addr (void *x)
+{
+  if (x != &pic_nothing)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-1.c
new file mode 100644
index 000000000..9e6c66006
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-1.c
@@ -0,0 +1,271 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mpaired-single" } */
+
+/* Test v2sf calculations */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size (8)));
+
+v2sf A = {100, 200};
+
+/* Init from float */
+v2sf init (float a, float b)
+{
+  return (v2sf) {a, b};
+}
+
+/* Move between registers */
+v2sf move (v2sf a)
+{
+  return a;
+}
+
+/* Load from memory */
+v2sf load ()
+{
+  return A;
+}
+
+/* Store to memory */ 
+void store (v2sf a)
+{
+  A = a;
+}
+
+/* Add */ 
+v2sf add (v2sf a, v2sf b)
+{
+  return a + b;
+}
+
+/* Subtract */ 
+v2sf sub (v2sf a, v2sf b)
+{
+  return a - b;
+}
+
+/* Negate */
+v2sf neg (v2sf a)
+{
+  return - a;
+}
+
+/* Multiply */ 
+v2sf mul (v2sf a, v2sf b)
+{
+  return a * b;
+}
+
+/* Multiply and add */ 
+v2sf madd (v2sf a, v2sf b, v2sf c)
+{
+  return a * b + c;
+}
+
+/* Multiply and subtract */ 
+v2sf msub (v2sf a, v2sf b, v2sf c)
+{
+  return a * b - c;
+}
+
+/* Negate Multiply and add */ 
+v2sf nmadd (v2sf a, v2sf b, v2sf c)
+{
+  return - (a * b + c);
+}
+
+/* Negate Multiply and subtract */ 
+v2sf nmsub (v2sf a, v2sf b, v2sf c)
+{
+  return - (a * b - c);
+}
+
+/* Conditional Move */ 
+v2sf cond_move1 (v2sf a, v2sf b, long i)
+{
+  if (i > 0)
+    return a;
+  else
+    return b;
+}
+
+/* Conditional Move */ 
+v2sf cond_move2 (v2sf a, v2sf b, int i)
+{
+  if (i > 0)
+    return a;
+  else
+    return b;
+}
+
+/* Conditional Move */ 
+v2sf cond_move3 (v2sf a, v2sf b, float i)
+{
+  if (i > 0.0)
+    return a;
+  else
+    return b;
+}
+
+/* Conditional Move */ 
+v2sf cond_move4 (v2sf a, v2sf b, double i)
+{
+  if (i > 0.0)
+    return a;
+  else
+    return b;
+}
+
+NOMIPS16 int main()
+{
+  v2sf a, b, c, d, e, f;
+  float f1, f2;
+
+  f1 = 1.2;
+  f2 = 3.4;
+  a = init (f1, f2);
+  b = (v2sf) {1.2, 3.4};
+  if (!__builtin_mips_upper_c_eq_ps (a, b) ||
+      !__builtin_mips_lower_c_eq_ps (a, b))
+    abort ();
+
+  a = (v2sf) {1.2, 2.3};
+  b = (v2sf) {5.3, 6.1};
+  b = move (a);
+
+  if (!__builtin_mips_upper_c_eq_ps (a, b) ||
+      !__builtin_mips_lower_c_eq_ps (a, b))
+    abort ();
+
+  a = (v2sf) {1.2, 2.3};
+  b = (v2sf) {5.3, 6.1};
+  c = add (a, b);
+  d = (v2sf) {6.5, 8.4};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = sub (a, b);
+  d = (v2sf) {-4, 6};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = mul (a, b);
+  d = (v2sf) {5, 72};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = (v2sf) {5, 6};
+  d = madd (a, b, c);
+  e = (v2sf) {10, 78};
+  if (!__builtin_mips_upper_c_eq_ps (d, e) ||
+      !__builtin_mips_lower_c_eq_ps (d, e))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = (v2sf) {5, 6};
+  d = msub (a, b, c);
+  e = (v2sf) {0, 66};
+  if (!__builtin_mips_upper_c_eq_ps (d, e) ||
+      !__builtin_mips_lower_c_eq_ps (d, e))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = (v2sf) {5, 6};
+  d = nmadd (a, b, c);
+  e = (v2sf) {-10, -78};
+  if (!__builtin_mips_upper_c_eq_ps (d, e) ||
+      !__builtin_mips_lower_c_eq_ps (d, e))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = (v2sf) {5, 6};
+  d = nmsub (a, b, c);
+  e = (v2sf) {0, -66};
+  if (!__builtin_mips_upper_c_eq_ps (d, e) ||
+      !__builtin_mips_lower_c_eq_ps (d, e))
+    abort ();
+
+  a = (v2sf) {98, 12};
+  b = neg (a);
+  c = (v2sf) {-98, -12};
+  if (!__builtin_mips_upper_c_eq_ps (b, c) ||
+      !__builtin_mips_lower_c_eq_ps (b, c))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = cond_move1 (a, b, 1000);
+  if (!__builtin_mips_upper_c_eq_ps (c, a) ||
+      !__builtin_mips_lower_c_eq_ps (c, a))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = cond_move2 (a, b, -1000);
+  if (!__builtin_mips_upper_c_eq_ps (c, b) ||
+      !__builtin_mips_lower_c_eq_ps (c, b))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = cond_move3 (a, b, 9.0);
+  if (!__builtin_mips_upper_c_eq_ps (c, a) ||
+      !__builtin_mips_lower_c_eq_ps (c, a))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = cond_move4 (a, b, -10.0);
+  if (!__builtin_mips_upper_c_eq_ps (c, b) ||
+      !__builtin_mips_lower_c_eq_ps (c, b))
+    abort ();
+
+  a = (v2sf) {5, 12};
+  b = (v2sf) {5, 6};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_c_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 123};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  a = (v2sf) {5, 12};
+  b = (v2sf) {5, 6};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movf_c_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 78};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  a = load();
+  b = (v2sf) {100, 200};
+  if (!__builtin_mips_upper_c_eq_ps (a, b) ||
+      !__builtin_mips_lower_c_eq_ps (a, b))
+    abort ();
+
+  a = (v2sf) {123, 321};
+  store (a);
+  b = load();
+  if (!__builtin_mips_upper_c_eq_ps (a, b) ||
+      !__builtin_mips_lower_c_eq_ps (a, b))
+    abort ();
+
+  printf ("Test Passes\n");
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-2.c
new file mode 100644
index 000000000..baec12c1c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-2.c
@@ -0,0 +1,134 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mpaired-single" } */
+
+/* Test MIPS paired-single builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+NOMIPS16 int main ()
+{
+  int little_endian;
+  v2sf a, b, c, d;
+  float e,f;
+  int i;
+
+  union { long long ll; int i[2]; } endianness_test;
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  /* pll.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_pll_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {3, 1};
+  else // big endian
+    d = (v2sf) {2, 4};
+
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* pul.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_pul_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {3, 2};
+  else // big endian
+    d = (v2sf) {1, 4};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* plu.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_plu_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {4, 1};
+  else // big endian
+    d = (v2sf) {2, 3};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* puu.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_puu_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {4, 2};
+  else // big endian
+    d = (v2sf) {1, 3};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* cvt.ps.s */
+  e = 3.4;
+  f = 4.5; 
+  a = __builtin_mips_cvt_ps_s (e, f);
+  if (little_endian) // little endian
+    b = (v2sf) {4.5, 3.4};
+  else // big endian
+    b = (v2sf) {3.4, 4.5};
+  if (!__builtin_mips_upper_c_eq_ps (a, b) ||
+      !__builtin_mips_lower_c_eq_ps (a, b))
+    abort ();
+
+  /* cvt.s.pl */
+  a = (v2sf) {35.1, 120.2};
+  e = __builtin_mips_cvt_s_pl (a);
+  if (little_endian) // little endian
+    f = 35.1; 
+  else // big endian
+    f = 120.2;
+  if (e != f)
+    abort ();
+
+  /* cvt.s.pu */
+  a = (v2sf) {30.0, 100.0};
+  e = __builtin_mips_cvt_s_pu (a);
+  if (little_endian) // little endian
+    f = 100.0;
+  else // big endian
+    f = 30.0; 
+  if (e != f)
+    abort ();
+
+  /* abs.ps */
+  a = (v2sf) {-3.4, -5.8};
+  b = __builtin_mips_abs_ps (a);
+  c = (v2sf) {3.4, 5.8};
+  if (!__builtin_mips_upper_c_eq_ps (b, c) ||
+      !__builtin_mips_lower_c_eq_ps (b, c))
+    abort ();
+
+  /* alnv.ps with rs = 4*/
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  i = 4;
+  c = __builtin_mips_alnv_ps (a, b, i);
+  d = (v2sf) {2, 3};
+
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* alnv.ps with rs = 0 */
+  a = (v2sf) {5, 6};
+  b = (v2sf) {7, 8};
+  i = 0;
+  c = __builtin_mips_alnv_ps (a, b, i);
+  d = (v2sf) {5, 6};
+
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  printf ("Test Passes\n");
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-3.c
new file mode 100644
index 000000000..e9ed4c03f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-3.c
@@ -0,0 +1,737 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mpaired-single" } */
+
+/* Test MIPS paired-single conditional move */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__((vector_size(8)));
+
+NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d);
+
+float qnan = 1.0f/0.0f - 1.0f/0.0f;
+
+NOMIPS16 int main ()
+{
+  float f1;
+  v2sf a, b, c, d, e, f;
+
+  /* Case 1 {diff, diff} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {9, 6};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_c_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 123};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_c_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 78};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* Case 2 {same, diff} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {5, 6};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_c_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 123};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_c_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 78};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* Case 3 {diff, same} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {9, 12};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_c_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 78};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_c_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 123};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* Case 4 {same, same} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {5, 12};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_c_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 78};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_c_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 123};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* Test all 16 operators */
+  a = (v2sf) {123, 123};
+  b = (v2sf) {1000, 1000};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = test0 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test1 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test2 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test3 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test4 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test5 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test6 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test7 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test8 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test9 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test10 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test11 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test12 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test13 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test14 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test15 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test16 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test17 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test18 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test19 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test20 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test21 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test22 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test23 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test24 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test25 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test26 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test27 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test28 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test29 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test30 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test31 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  /* Test all 16 operators with (b, a) */
+  a = (v2sf) {123, 123};
+  b = (v2sf) {1000, 1000};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = test0 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test1 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test2 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test3 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test4 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test5 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test6 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test7 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test8 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test9 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test10 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test11 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test12 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test13 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test14 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test15 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test16 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test17 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test18 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test19 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test20 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test21 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test22 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test23 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test24 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test25 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test26 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test27 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test28 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test29 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test30 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test31 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test with NaN */
+  a = (v2sf) {qnan, qnan};
+  b = (v2sf) {1000, 1000};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = test0 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test1 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test2 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test3 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test4 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test5 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test6 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test7 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test8 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test9 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test10 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test11 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test12 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test13 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test14 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test15 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test16 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test17 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test18 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test19 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test20 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test21 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test22 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test23 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test24 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test25 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test26 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test27 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test28 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test29 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test30 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test31 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_f_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_f_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_un_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_un_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_eq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_eq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_ueq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_ueq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_olt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_olt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_ult_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_ult_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_ole_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_ole_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_ule_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_ule_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_sf_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_sf_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_ngle_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_ngle_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_seq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_seq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_ngl_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_ngl_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_lt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_lt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_nge_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_nge_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_le_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_le_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_ngt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_ngt_ps (a, b, c, d);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-4.c
new file mode 100644
index 000000000..b4452d091
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-4.c
@@ -0,0 +1,583 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mpaired-single" } */
+
+/* Test MIPS paired-single comparisons */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__((vector_size(8)));
+
+NOMIPS16 int test0 (v2sf a, v2sf b);
+NOMIPS16 int test1 (v2sf a, v2sf b);
+NOMIPS16 int test2 (v2sf a, v2sf b);
+NOMIPS16 int test3 (v2sf a, v2sf b);
+NOMIPS16 int test4 (v2sf a, v2sf b);
+NOMIPS16 int test5 (v2sf a, v2sf b);
+NOMIPS16 int test6 (v2sf a, v2sf b);
+NOMIPS16 int test7 (v2sf a, v2sf b);
+NOMIPS16 int test8 (v2sf a, v2sf b);
+NOMIPS16 int test9 (v2sf a, v2sf b);
+NOMIPS16 int test10 (v2sf a, v2sf b);
+NOMIPS16 int test11 (v2sf a, v2sf b);
+NOMIPS16 int test12 (v2sf a, v2sf b);
+NOMIPS16 int test13 (v2sf a, v2sf b);
+NOMIPS16 int test14 (v2sf a, v2sf b);
+NOMIPS16 int test15 (v2sf a, v2sf b);
+NOMIPS16 int test16 (v2sf a, v2sf b);
+NOMIPS16 int test17 (v2sf a, v2sf b);
+NOMIPS16 int test18 (v2sf a, v2sf b);
+NOMIPS16 int test19 (v2sf a, v2sf b);
+NOMIPS16 int test20 (v2sf a, v2sf b);
+NOMIPS16 int test21 (v2sf a, v2sf b);
+NOMIPS16 int test22 (v2sf a, v2sf b);
+NOMIPS16 int test23 (v2sf a, v2sf b);
+NOMIPS16 int test24 (v2sf a, v2sf b);
+NOMIPS16 int test25 (v2sf a, v2sf b);
+NOMIPS16 int test26 (v2sf a, v2sf b);
+NOMIPS16 int test27 (v2sf a, v2sf b);
+NOMIPS16 int test28 (v2sf a, v2sf b);
+NOMIPS16 int test29 (v2sf a, v2sf b);
+NOMIPS16 int test30 (v2sf a, v2sf b);
+NOMIPS16 int test31 (v2sf a, v2sf b);
+
+float qnan = 1.0f/0.0f - 1.0f/0.0f;
+
+NOMIPS16 int main()
+{
+  union { long long ll; int i[2]; } endianness_test;
+  int little_endian;
+  v2sf a, b;
+  int i, j;
+
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  /* Case 1 {diff, diff} */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  i = __builtin_mips_upper_c_eq_ps (a, b);
+  j = __builtin_mips_lower_c_eq_ps (a, b);
+  if (i != 0 || j != 0)
+    abort ();
+
+  /* Case 2 {same, diff} */
+  a = (v2sf) {1.0, 2.0};
+  b = (v2sf) {1.0, 4.0};
+  i = __builtin_mips_upper_c_eq_ps (a, b);
+  j = __builtin_mips_lower_c_eq_ps (a, b);
+  if (little_endian)
+    {
+      if (i != 0 || j != 1)
+        abort ();
+    }
+  else
+    {
+      if (i != 1 || j != 0)
+        abort ();
+    }
+
+  /* Case 3 {diff, same} */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 2};
+  i = __builtin_mips_upper_c_eq_ps (a, b);
+  j = __builtin_mips_lower_c_eq_ps (a, b);
+  if (little_endian)
+    {
+      if (i != 1 || j != 0)
+        abort ();
+    }
+  else
+    {
+      if (i != 0 || j != 1)
+        abort ();
+    }
+
+  /* Case 4 {same, same} */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {1, 2};
+  i = __builtin_mips_upper_c_eq_ps (a, b);
+  j = __builtin_mips_lower_c_eq_ps (a, b);
+  if (i != 1 || j != 1)
+    abort ();
+
+  /* Test upper/lower with 16 operators */
+  if (little_endian)
+   {
+     a = (v2sf) {1984.0, 10.58};
+     b = (v2sf) {1984.0, 567.345};
+   }
+  else
+   {
+     a = (v2sf) {10.58, 1984.0};
+     b = (v2sf) {567.345, 1984.0};
+   }
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b);
+  if (i != 0)
+    abort ();
+  i = test4 (a, b);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b);
+  if (i != 1)
+    abort ();
+  i = test6 (a, b);
+  if (i != 0)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 1)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b);
+  if (i != 0)
+    abort ();
+  i = test12 (a, b);
+  if (i != 1)
+    abort ();
+  i = test13 (a, b);
+  if (i != 1)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+  i = test16 (a, b);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b);
+  if (i != 0)
+    abort ();
+  i = test19 (a, b);
+  if (i != 0)
+    abort ();
+  i = test20 (a, b);
+  if (i != 0)
+    abort ();
+  i = test21 (a, b);
+  if (i != 1)
+    abort ();
+  i = test22 (a, b);
+  if (i != 0)
+    abort ();
+  i = test23 (a, b);
+  if (i != 1)
+    abort ();
+  i = test24 (a, b);
+  if (i != 1)
+    abort ();
+  i = test25 (a, b);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b);
+  if (i != 0)
+    abort ();
+  i = test28 (a, b);
+  if (i != 1)
+    abort ();
+  i = test29 (a, b);
+  if (i != 1)
+    abort ();
+  i = test30 (a, b);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b);
+  if (i != 1)
+    abort ();
+
+  /* Reverse arguments */
+  i = test0 (b, a);
+  if (i != 0)
+    abort ();
+  i = test1 (b, a);
+  if (i != 0)
+    abort ();
+  i = test2 (b, a);
+  if (i != 0)
+    abort ();
+  i = test3 (b, a);
+  if (i != 0)
+    abort ();
+  i = test4 (b, a);
+  if (i != 0)
+    abort ();
+  i = test5 (b, a);
+  if (i != 1)
+    abort ();
+  i = test6 (b, a);
+  if (i != 0)
+    abort ();
+  i = test7 (b, a);
+  if (i != 1)
+    abort ();
+  i = test8 (b, a);
+  if (i != 0)
+    abort ();
+  i = test9 (b, a);
+  if (i != 0)
+    abort ();
+  i = test10 (b, a);
+  if (i != 0)
+    abort ();
+  i = test11 (b, a);
+  if (i != 0)
+    abort ();
+  i = test12 (b, a);
+  if (i != 0)
+    abort ();
+  i = test13 (b, a);
+  if (i != 1)
+    abort ();
+  i = test14 (b, a);
+  if (i != 0)
+    abort ();
+  i = test15 (b, a);
+  if (i != 1)
+    abort ();
+  i = test16 (b, a);
+  if (i != 0)
+    abort ();
+  i = test17 (b, a);
+  if (i != 0)
+    abort ();
+  i = test18 (b, a);
+  if (i != 0)
+    abort ();
+  i = test19 (b, a);
+  if (i != 0)
+    abort ();
+  i = test20 (b, a);
+  if (i != 0)
+    abort ();
+  i = test21 (b, a);
+  if (i != 1)
+    abort ();
+  i = test22 (b, a);
+  if (i != 0)
+    abort ();
+  i = test23 (b, a);
+  if (i != 1)
+    abort ();
+  i = test24 (b, a);
+  if (i != 0)
+    abort ();
+  i = test25 (b, a);
+  if (i != 0)
+    abort ();
+  i = test26 (b, a);
+  if (i != 0)
+    abort ();
+  i = test27 (b, a);
+  if (i != 0)
+    abort ();
+  i = test28 (b, a);
+  if (i != 0)
+    abort ();
+  i = test29 (b, a);
+  if (i != 1)
+    abort ();
+  i = test30 (b, a);
+  if (i != 0)
+    abort ();
+  i = test31 (b, a);
+  if (i != 1)
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test upper/lower with 16 operators */
+  if (little_endian)
+   {
+     a = (v2sf) {qnan, qnan};
+     b = (v2sf) {1984.0, 567.345};
+   }
+  else
+   {
+     a = (v2sf) {qnan, qnan};
+     b = (v2sf) {567.345, 1984.0};
+   }
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 1)
+    abort ();
+  i = test3 (a, b);
+  if (i != 1)
+    abort ();
+  i = test4 (a, b);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b);
+  if (i != 1)
+    abort ();
+  i = test12 (a, b);
+  if (i != 0)
+    abort ();
+  i = test13 (a, b);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+  i = test16 (a, b);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b);
+  if (i != 1)
+    abort ();
+  i = test19 (a, b);
+  if (i != 1)
+    abort ();
+  i = test20 (a, b);
+  if (i != 0)
+    abort ();
+  i = test21 (a, b);
+  if (i != 0)
+    abort ();
+  i = test22 (a, b);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b);
+  if (i != 1)
+    abort ();
+  i = test24 (a, b);
+  if (i != 0)
+    abort ();
+  i = test25 (a, b);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b);
+  if (i != 1)
+    abort ();
+  i = test28 (a, b);
+  if (i != 0)
+    abort ();
+  i = test29 (a, b);
+  if (i != 0)
+    abort ();
+  i = test30 (a, b);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b);
+  if (i != 1)
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 int test0 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_f_ps (a, b);
+}
+
+NOMIPS16 int test1 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_f_ps (a, b);
+}
+
+NOMIPS16 int test2 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_un_ps (a, b);
+}
+
+NOMIPS16 int test3 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_un_ps (a, b);
+}
+
+NOMIPS16 int test4 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_eq_ps (a, b);
+}
+
+NOMIPS16 int test5 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_eq_ps (a, b);
+}
+
+NOMIPS16 int test6 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_ueq_ps (a, b);
+}
+
+NOMIPS16 int test7 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_ueq_ps (a, b);
+}
+
+NOMIPS16 int test8 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_olt_ps (a, b);
+}
+
+NOMIPS16 int test9 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_olt_ps (a, b);
+}
+
+NOMIPS16 int test10 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_ult_ps (a, b);
+}
+
+NOMIPS16 int test11 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_ult_ps (a, b);
+}
+
+NOMIPS16 int test12 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_ole_ps (a, b);
+}
+
+NOMIPS16 int test13 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_ole_ps (a, b);
+}
+
+NOMIPS16 int test14 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_ule_ps (a, b);
+}
+
+NOMIPS16 int test15 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_ule_ps (a, b);
+}
+
+NOMIPS16 int test16 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_sf_ps (a, b);
+}
+
+NOMIPS16 int test17 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_sf_ps (a, b);
+}
+
+NOMIPS16 int test18 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_ngle_ps (a, b);
+}
+
+NOMIPS16 int test19 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_ngle_ps (a, b);
+}
+
+NOMIPS16 int test20 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_seq_ps (a, b);
+}
+
+NOMIPS16 int test21 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_seq_ps (a, b);
+}
+
+NOMIPS16 int test22 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_ngl_ps (a, b);
+}
+
+NOMIPS16 int test23 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_ngl_ps (a, b);
+}
+
+NOMIPS16 int test24 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_lt_ps (a, b);
+}
+
+NOMIPS16 int test25 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_lt_ps (a, b);
+}
+
+NOMIPS16 int test26 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_nge_ps (a, b);
+}
+
+NOMIPS16 int test27 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_nge_ps (a, b);
+}
+
+NOMIPS16 int test28 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_le_ps (a, b);
+}
+
+NOMIPS16 int test29 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_le_ps (a, b);
+}
+
+NOMIPS16 int test30 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_ngt_ps (a, b);
+}
+
+NOMIPS16 int test31 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_ngt_ps (a, b);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-5.c
new file mode 100644
index 000000000..94d2f80ef
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-5.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mpaired-single -mgp64 -ftree-vectorize" } */
+
+extern float a[], b[], c[];
+
+NOMIPS16 void
+foo (void)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] = b[i] == c[i] + 1 ? b[i] : c[i];
+}
+
+/* { dg-final { scan-assembler "add\\.ps" } } */
+/* { dg-final { scan-assembler "c\\.eq\\.ps" } } */
+/* { dg-final { scan-assembler "mov\[tf\]\\.ps" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-6.c
new file mode 100644
index 000000000..5b8b25228
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-6.c
@@ -0,0 +1,136 @@
+/* mips-ps-2.c with an extra -ffinite-math-only option.  This option
+   changes the way that abs.ps is handled.  */
+/* { dg-do run } */
+/* { dg-options "-O2 -mpaired-single -ffinite-math-only" } */
+
+/* Test MIPS paired-single builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+NOMIPS16 int main ()
+{
+  int little_endian;
+  v2sf a, b, c, d;
+  float e,f;
+  int i;
+
+  union { long long ll; int i[2]; } endianness_test;
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  /* pll.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_pll_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {3, 1};
+  else // big endian
+    d = (v2sf) {2, 4};
+
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* pul.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_pul_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {3, 2};
+  else // big endian
+    d = (v2sf) {1, 4};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* plu.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_plu_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {4, 1};
+  else // big endian
+    d = (v2sf) {2, 3};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* puu.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_puu_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {4, 2};
+  else // big endian
+    d = (v2sf) {1, 3};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* cvt.ps.s */
+  e = 3.4;
+  f = 4.5; 
+  a = __builtin_mips_cvt_ps_s (e, f);
+  if (little_endian) // little endian
+    b = (v2sf) {4.5, 3.4};
+  else // big endian
+    b = (v2sf) {3.4, 4.5};
+  if (!__builtin_mips_upper_c_eq_ps (a, b) ||
+      !__builtin_mips_lower_c_eq_ps (a, b))
+    abort ();
+
+  /* cvt.s.pl */
+  a = (v2sf) {35.1, 120.2};
+  e = __builtin_mips_cvt_s_pl (a);
+  if (little_endian) // little endian
+    f = 35.1; 
+  else // big endian
+    f = 120.2;
+  if (e != f)
+    abort ();
+
+  /* cvt.s.pu */
+  a = (v2sf) {30.0, 100.0};
+  e = __builtin_mips_cvt_s_pu (a);
+  if (little_endian) // little endian
+    f = 100.0;
+  else // big endian
+    f = 30.0; 
+  if (e != f)
+    abort ();
+
+  /* abs.ps */
+  a = (v2sf) {-3.4, -5.8};
+  b = __builtin_mips_abs_ps (a);
+  c = (v2sf) {3.4, 5.8};
+  if (!__builtin_mips_upper_c_eq_ps (b, c) ||
+      !__builtin_mips_lower_c_eq_ps (b, c))
+    abort ();
+
+  /* alnv.ps with rs = 4*/
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  i = 4;
+  c = __builtin_mips_alnv_ps (a, b, i);
+  d = (v2sf) {2, 3};
+
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* alnv.ps with rs = 0 */
+  a = (v2sf) {5, 6};
+  b = (v2sf) {7, 8};
+  i = 0;
+  c = __builtin_mips_alnv_ps (a, b, i);
+  d = (v2sf) {5, 6};
+
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  printf ("Test Passes\n");
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-7.c
new file mode 100644
index 000000000..65a1104ba
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-7.c
@@ -0,0 +1,17 @@
+/* mips-ps-5.c with -mgp32 instead of -mgp64.  */
+/* { dg-do compile } */
+/* { dg-options "-mgp32 -O2 -mpaired-single -ftree-vectorize" } */
+
+extern float a[], b[], c[];
+
+NOMIPS16 void
+foo (void)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] = b[i] == c[i] + 1 ? b[i] : c[i];
+}
+
+/* { dg-final { scan-assembler "add\\.ps" } } */
+/* { dg-final { scan-assembler "c\\.eq\\.ps" } } */
+/* { dg-final { scan-assembler "mov\[tf\]\\.ps" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c
new file mode 100644
index 000000000..f79885533
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c
@@ -0,0 +1,111 @@
+/* Test v2sf calculations.  The nmadd and nmsub patterns need
+   -ffinite-math-only.  */
+/* { dg-do compile } */
+/* { dg-options "isa_rev>=2 -mgp32 -O2 -mpaired-single -ffinite-math-only" } */
+/* { dg-final { scan-assembler "cvt.ps.s" } } */
+/* { dg-final { scan-assembler "mov.ps" } } */
+/* { dg-final { scan-assembler "ldc1" } } */
+/* { dg-final { scan-assembler "sdc1" } } */
+/* { dg-final { scan-assembler "add.ps" } } */
+/* { dg-final { scan-assembler "sub.ps" } } */
+/* { dg-final { scan-assembler "neg.ps" } } */
+/* { dg-final { scan-assembler "mul.ps" } } */
+/* { dg-final { scan-assembler "madd.ps" } } */
+/* { dg-final { scan-assembler "msub.ps" } } */
+/* { dg-final { scan-assembler "nmadd.ps" } } */
+/* { dg-final { scan-assembler "nmsub.ps" } } */
+/* { dg-final { scan-assembler "movn.ps" } } */
+/* { dg-final { scan-assembler "movz.ps" } } */
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+void gobble (v2sf);
+
+v2sf A = {100, 200};
+
+/* Init from  floats */
+NOMIPS16 v2sf init (float a, float b)
+{
+  return (v2sf) {a, b};
+}
+
+/* Move between registers */
+NOMIPS16 v2sf move (v2sf a)
+{
+  return a;
+}
+
+/* Load from memory */
+NOMIPS16 v2sf load ()
+{
+  return A;
+}
+
+/* Store to memory */
+NOMIPS16 void store (v2sf a)
+{
+  A = a;
+}
+
+/* Add */
+NOMIPS16 v2sf add (v2sf a, v2sf b)
+{
+  return a + b;
+}
+
+/* Subtract */
+NOMIPS16 v2sf sub (v2sf a, v2sf b)
+{
+  return a - b;
+}
+
+/* Negate */
+NOMIPS16 v2sf neg (v2sf a)
+{
+  return - a;
+}
+
+/* Multiply */
+NOMIPS16 v2sf mul (v2sf a, v2sf b)
+{
+  return a * b;
+}
+
+/* Multiply and add */
+NOMIPS16 v2sf madd (v2sf a, v2sf b, v2sf c)
+{
+  return a * b + c;
+}
+
+/* Multiply and subtract */
+NOMIPS16 v2sf msub (v2sf a, v2sf b, v2sf c)
+{
+  return a * b - c;
+}
+
+/* Negate Multiply and add */
+NOMIPS16 v2sf nmadd (v2sf a, v2sf b, v2sf c)
+{
+  return - (a * b + c);
+}
+
+/* Negate Multiply and subtract */
+NOMIPS16 v2sf nmsub (v2sf a, v2sf b, v2sf c)
+{
+  return - (a * b - c);
+}
+
+/* Conditional Move */
+NOMIPS16 v2sf cond_move1 (v2sf a, v2sf b, int i)
+{
+  if (i == 0)
+    a = b;
+  gobble (a);
+}
+
+/* Conditional Move */
+NOMIPS16 v2sf cond_move2 (v2sf a, v2sf b, int i)
+{
+  if (i != 0)
+    a = b;
+  gobble (a);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-type.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-type.c
new file mode 100644
index 000000000..2a10f91bd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-ps-type.c
@@ -0,0 +1,111 @@
+/* Test v2sf calculations.  The nmadd and nmsub patterns need
+   -ffinite-math-only.  */
+/* { dg-do compile } */ 
+/* { dg-options "-O2 -mpaired-single -mgp64 -ffinite-math-only" } */
+/* { dg-final { scan-assembler "cvt.ps.s" } } */ 
+/* { dg-final { scan-assembler "mov.ps" } } */ 
+/* { dg-final { scan-assembler "ldc1" } } */ 
+/* { dg-final { scan-assembler "sdc1" } } */ 
+/* { dg-final { scan-assembler "add.ps" } } */ 
+/* { dg-final { scan-assembler "sub.ps" } } */ 
+/* { dg-final { scan-assembler "neg.ps" } } */ 
+/* { dg-final { scan-assembler "mul.ps" } } */ 
+/* { dg-final { scan-assembler "madd.ps" } } */ 
+/* { dg-final { scan-assembler "msub.ps" } } */ 
+/* { dg-final { scan-assembler "nmadd.ps" } } */ 
+/* { dg-final { scan-assembler "nmsub.ps" } } */ 
+/* { dg-final { scan-assembler "mov(n|z).ps" } } */ 
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+v2sf A = {100, 200};
+
+/* Init from  floats */
+NOMIPS16 v2sf init (float a, float b)
+{
+  return (v2sf) {a, b};
+}
+
+/* Move between registers */
+NOMIPS16 v2sf move (v2sf a)
+{
+  return a;
+}
+
+/* Load from memory */
+NOMIPS16 v2sf load ()
+{
+  return A;
+}
+
+/* Store to memory */ 
+NOMIPS16 void store (v2sf a)
+{
+  A = a;
+}
+
+/* Add */ 
+NOMIPS16 v2sf add (v2sf a, v2sf b)
+{
+  return a + b;
+}
+
+/* Subtract */ 
+NOMIPS16 v2sf sub (v2sf a, v2sf b)
+{
+  return a - b;
+}
+
+/* Negate */
+NOMIPS16 v2sf neg (v2sf a)
+{
+  return - a;
+}
+
+/* Multiply */ 
+NOMIPS16 v2sf mul (v2sf a, v2sf b)
+{
+  return a * b;
+}
+
+/* Multiply and add */ 
+NOMIPS16 v2sf madd (v2sf a, v2sf b, v2sf c)
+{
+  return a * b + c;
+}
+
+/* Multiply and subtract */ 
+NOMIPS16 v2sf msub (v2sf a, v2sf b, v2sf c)
+{
+  return a * b - c;
+}
+
+/* Negate Multiply and add */ 
+NOMIPS16 v2sf nmadd (v2sf a, v2sf b, v2sf c)
+{
+  return - (a * b + c);
+}
+
+/* Negate Multiply and subtract */ 
+NOMIPS16 v2sf nmsub (v2sf a, v2sf b, v2sf c)
+{
+  return - (a * b - c);
+}
+
+/* Conditional Move */ 
+NOMIPS16 v2sf cond_move1 (v2sf a, v2sf b, long i)
+{
+  if (i > 0)
+    return a;
+  else
+    return b;
+}
+
+/* Conditional Move */ 
+NOMIPS16 v2sf cond_move2 (v2sf a, v2sf b, int i)
+{
+  if (i > 0)
+    return a;
+  else
+    return b;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-sched-madd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-sched-madd.c
new file mode 100644
index 000000000..c0f9d332a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips-sched-madd.c
@@ -0,0 +1,19 @@
+/* Test for case where another independent multiply insn may interfere
+   with a macc chain.  */
+/* { dg-do compile } */
+/* { dg-options "-Os -march=24kf" } */
+
+NOMIPS16 int foo (int a, int b, int c, int d, int e, int f, int g)
+{
+  int temp;
+  int acc;
+
+  acc = a * b;
+  temp = a * c;
+  acc = d * e + acc;
+  acc = f * g + acc;
+  return acc > temp ? acc : temp;
+}
+
+/* { dg-final { scan-assembler "\tmult\t" } } */
+/* { dg-final { scan-assembler "\tmadd\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips.exp
new file mode 100644
index 000000000..7befff5a1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips.exp
@@ -0,0 +1,1156 @@
+# Copyright (C) 1997, 2007, 2008, 2009 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# A MIPS version of the GCC dg.exp driver.
+#
+# There are many MIPS features that we want to test, and many of those
+# features are specific to certain architectures, certain ABIs and so on.
+# There are therefore many cases in which we want to test something that
+# is incompatible with the user's chosen test options.
+#
+# In most dg testsuites, the options added by dg-options have a lower
+# priority than the options chosen by the user.  For example, if a test
+# specifies:
+#
+#    { dg-options "-mips1" }
+#
+# and the user passes the following option to runtest:
+#
+#    --target_board unix/-mips3
+#
+# the test would be compiled as MIPS III rather than MIPS I.  If the
+# test really wouldn't work with -mips3, normal practice would be to
+# have something like:
+#
+#    { dg-do compile { target can_force_mips1 } }
+#
+# so that the test is skipped when an option like -mips3 is passed.
+#
+# Sticking to the same approach here would cause us to skip many tests,
+# even though the toolchain can generate the required code.  For example,
+# there are 6 MIPS ABIs, plus variants.  Some configurations support
+# more than one ABI, so it is natural to use something like:
+#
+#    --target_board unix{-mabi=n32,-mabi=32,-mabi=64}
+#
+# when testing them.  But these -mabi=* options would normally prevent any
+# EABI and o64 tests from running.
+#
+# This testsuite therefore defines a local version of dg-options that
+# overrides any user options that are incompatible with the test options.
+# It tries to keep the other user options intact.
+#
+#
+# Most of the tests in this testsuite are scan-assembler tests, but
+# sometimes we need a link test instead.  In these cases, we must not
+# try to link code with options that are incompatible with the current
+# multilib, because xgcc is passed -L and -B options that are specific
+# to that multilib.
+#
+# Normal GCC practice would be to skip incompatible link tests as
+# unsupported, but in this particular case, it seems better to downgrade
+# them to an assemble test instead.  At least that way we get some
+# test-for-ICE and code-sanity coverage.
+#
+# The same problem applies to run tests.  If a test requires runtime
+# support for a particular feature, and if the current target does not
+# provide that support, normal practice would be to skip the test.
+# But in this case it seems better to downgrade it to a link test instead.
+# (We might then have to downgrade it to an assembler test according to
+# the constraints just mentioned.)
+#
+# The local dg-options therefore checks whether the new options are
+# link-compatiable with the user's options.  If not, it automatically
+# downgrades link tests to assemble tests.  It does the same for run
+# tests, but in addition, it downgrades run tests to link tests if the
+# target does not provide runtime support for a required feature or ASE.
+#
+#
+# Another problem is that many of the options we want to test require
+# certain other features.  For example, -mips3d requires both 64-bit
+# FPRs and a MIPS32 or MIPS64 target; -mfix-r10000 requires branch-
+# likely instructions; and so on.  We could handle this by specifying
+# a set of options that are guaranteed to give us what we want, such as:
+#
+#   dg-options "-mips3d -mpaired-single -mhard-float -mgp64 -mfp64 -mabi=n32 -march=mips64 -mips64"
+#
+# With the new dg-options semantics, this would override any troublesome
+# user options like -mips3, -march=vr4100, -mfp32, -mgp32, -msoft-float,
+# -mno-paired-single and so on.  But there are three major problems with
+# this:
+#
+#   - It is easy to forget options.
+#
+#   - If a new option is added, all tests that are incompatible with that
+#     option must be updated.
+#
+#   - We want to be able to test MIPS-3D with things like -march=mips32,
+#     -march=mips64r2, -march=sb1, and so on.
+#
+# The local version of dg-options therefore works out the requirements
+# of each test option.  As with the test options themselves, the local
+# dg-options overrides any user options that incompatible with these
+# requirements, but it keeps the other user options the same.
+#
+# For example, if the user passes -mips3, a MIPS-3D test will choose
+# a different architecture like -mips64 instead.  But if the user
+# passes -march=sb1, MIPS-3D tests will be run with that option.
+#
+#
+# Sometimes it is useful to say "I want an environment that is compatible
+# with option X, but I don't want to pass option X itself".  The main example
+# of this is -mips16: we want to be able to test __attribute__((mips16))
+# without requiring the test itself to be compiled as -mips16.  The local
+# version of dg-options lets you do this by putting X in parentheses.
+# For example:
+#
+#   { dg-options "(-mips16)" }
+#
+# selects a MIPS16-compatible target without passing -mips16 itself.
+#
+# It is also useful to say "any architecture within this ISA range is fine".
+# This can be done using special pseudo-options of the form:
+#
+#   PROP=VALUE PROP<=VALUE PROP>=VALUE
+#
+# where PROP can be:
+#
+#   isa:
+#	the value of the __mips macro.
+#
+#   isa_rev:
+#	the value of the __mips_isa_rev macro, or 0 if it isn't defined.
+#
+# For example, "isa_rev>=1" selects a MIPS32 or MIPS64 processor,
+# "isa=4" selects a MIPS IV processor, and so on.
+#
+# If certain processor-specific extensions are not applicable to the
+# test you can list them as !CPU in the isa or isa_rev options.  For
+# example, isa=64!octeon enforces MIPS64 while avoiding octeon.  You
+# can also use ! without an ISA value.  For example
+# isa=!octeon!loongson2e disables octeon and loongson2e if otherwise
+# you would compile for one of them.
+#
+# There are also the following special pseudo-options:
+#
+#   isa=loongson
+#	select a Loongson processor
+#
+#   addressing=absolute
+#	force absolute addresses to be used
+#
+#
+# In summary:
+#
+#   (1) Try to avoid { target ... } requirements wherever possible.
+#       Specify the requirements as dg-options instead.
+#
+#   (2) Don't worry about the consequences of (1) for link and run tests.
+#       If the test uses { dg-do link } or { dg-do run }, and its
+#       dg-options are incompatible with the current target, the
+#       testsuite will downgrade them where necessary.
+#
+#   (3) Try to use the bare minimum of options and leave dg-options
+#       to work out the dependencies.  For example, if you want
+#       a MIPS-3D test, you should generally just specify -mips3d.
+#       Don't specify an architecture option like -mips64 unless
+#       the test really doesn't work with -mips32r2, -mips64r2,
+#       -march=sb1, etc.
+#
+#   (4) If you want something compatible with a particular option,
+#       but don't want to pass the option itself, wrap that option
+#       in parentheses.  In particular, pass '(-mips16)' if you
+#       want to use "mips16" attributes.
+#
+#   (5) When testing a feature of a generic ISA (as opposed to a
+#	processor-specific extension), try to use the "isa" and
+#	"isa_rev" pseudo-options instead of specific architecture
+#	options.  For example, if the feature is present on revision 2
+#	processors and above, try to use "isa_rev>=2" instead of
+#	"-mips32r2" or "-mips64r2".
+#
+#   (6) If you need to disable processor-specific extensions use
+#	isa=!CPU instead of forcing a generic ISA.
+
+# Exit immediately if this isn't a MIPS target.
+if ![istarget mips*-*-*] {
+    return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# A list of GROUP REGEXP pairs.  Each GROUP represents a logical group of
+# options from which only option should be chosen.  REGEXP matches all the
+# options in that group; it is implicitly wrapped in "^(...)$".
+set mips_option_groups {
+    abi "-mabi=.*"
+    addressing "addressing=.*"
+    arch "-mips([1-5]|32.*|64.*)|-march=.*|isa(|_rev)(=|<=|>=).*"
+    dump_pattern "-dp"
+    endianness "-E(L|B)|-me(l|b)"
+    float "-m(hard|soft)-float"
+    fp "-mfp(32|64)"
+    gp "-mgp(32|64)"
+    long "-mlong(32|64)"
+    mips16 "-mips16|-mno-mips16"
+    mips3d "-mips3d|-mno-mips3d"
+    optimization "-O(|[0-3s])"
+    pic "-f(no-|)(pic|PIC)"
+    profiling "-pg"
+    small-data "-G[0-9]+"
+    warnings "-w"
+}
+
+# Add -mfoo/-mno-foo options to mips_option_groups.
+foreach option {
+    abicalls
+    branch-likely
+    dsp
+    dspr2
+    explicit-relocs
+    extern-sdata
+    fix-r4000
+    fix-r10000
+    fix-vr4130
+    gpopt
+    local-sdata
+    long-calls
+    paired-single
+    plt
+    shared
+    smartmips
+    sym32
+} {
+    lappend mips_option_groups $option "-m(no-|)$option"
+}
+
+# Add -mfoo= options to mips_option_groups.
+foreach option {
+    branch-cost
+    code-readable
+    r10k-cache-barrier
+} {
+    lappend mips_option_groups $option "-m$option=.*"
+}
+
+# Add -ffoo/-fno-foo options to mips_option_groups.
+foreach option {
+    delayed-branch
+    fast-math
+    finite-math-only
+    fixed-hi
+    fixed-lo
+    lax-vector-conversions
+    split-wide-types
+    tree-vectorize
+} {
+    lappend mips_option_groups $option "-f(no-|)$option"
+}
+
+# A list of option groups that have an impact on the ABI.
+set mips_abi_groups {
+    abi
+    abicalls
+    arch
+    endianness
+    float
+    fp
+    gp
+    gpopt
+    long
+    pic
+    small-data
+}
+
+# mips_option_tests(OPTION) is some assembly code that will run to completion
+# on a target that supports OPTION.
+set mips_option_tests(-mips16) {
+    move $2,$31
+    bal 1f
+    .set mips16
+    jr $31
+    .set nomips16
+    .align 2
+1:
+    ori $3,$31,1
+    jalr $3
+    move $31,$2
+}
+set mips_option_tests(-mpaired-single) {
+    .set mips64
+    lui $2,0x3f80
+    mtc1 $2,$f0
+    cvt.ps.s $f2,$f0,$f0
+}
+set mips_option_tests(-mips3d) {
+    .set mips64
+    .set mips3d
+    lui $2,0x3f80
+    mtc1 $2,$f0
+    cvt.ps.s $f2,$f0,$f0
+    mulr.ps $f2,$f2,$f2
+    rsqrt1.s $f2,$f0
+    mul.s $f4,$f2,$f0
+    rsqrt2.s $f4,$f4,$f2
+    madd.s $f4,$f2,$f2,$f4
+}
+set mips_option_tests(-mdsp) {
+    .set mips64r2
+    .set dsp
+    addsc $2,$2,$2
+}
+set mips_option_tests(-mdspr2) {
+    .set mips64r2
+    .set dspr2
+    prepend $2,$3,11
+}
+
+# Canonicalize command-line option OPTION.
+proc mips_canonicalize_option { option } {
+    regsub {^-mips([1-5]|32*|64*)$} $option {-march=mips\1} option
+
+    regsub {^-mel$} $option {-EL} option
+    regsub {^-meb$} $option {-EB} option
+
+    regsub {^-O$} $option {-O1} option
+
+    # MIPS doesn't use -fpic and -fPIC to distinguish between code models.
+    regsub {^-f(no-|)PIC} $option {-f\1pic} option
+
+    return $option
+}
+
+# Return true if OPTION1 and OPTION2 represent the same command-line option.
+proc mips_same_option_p { option1 option2 } {
+    return [string equal \
+		[mips_canonicalize_option $option1] \
+		[mips_canonicalize_option $option2]]
+}
+
+# Preprocess CODE using target_compile options OPTIONS.  Return the
+# compiler output.
+proc mips_preprocess { options code } {
+    global tool
+
+    set src dummy[pid].c
+    set f [open $src "w"]
+    puts $f $code
+    close $f
+    set output [${tool}_target_compile $src "" preprocess $options]
+    file delete $src
+
+    return $output
+}
+
+# Set the target board's command-line options to NEW_OPTIONS, storing the
+# old values in UPVAR.
+proc mips_push_test_options { upvar new_options } {
+    upvar $upvar var
+    global board_info
+
+    array unset var
+    set var(name) board_info([target_info name],multilib_flags)
+    if { [info exists $var(name)] } {
+	set var(old_options) [set $var(name)]
+	set $var(name) [join $new_options " "]
+    }
+}
+
+# Undo the effects of [mips_push_test_options UPVAR ...]
+proc mips_pop_test_options { upvar } {
+    upvar $upvar var
+    global board_info
+
+    if { [info exists var(old_options)] } {
+	set $var(name) $var(old_options)
+    }
+}
+
+# Return property PROP for architecture option ARCH (which belongs to
+# the "arch" group in mips_option_groups).  See the comment at the
+# top of the file for the valid property names.
+#
+# Cache the results in mips_arch_info (which can be reused between test
+# variants).
+proc mips_arch_info { arch prop } {
+    global mips_arch_info
+    global board_info
+
+    set arch [mips_canonicalize_option $arch]
+    if { ![info exists mips_arch_info($arch,$prop)] } {
+	mips_push_test_options saved_options {}
+	set output [mips_preprocess [list "additional_flags=$arch -mabi=32"] {
+	    int isa = __mips;
+	    #ifdef __mips_isa_rev
+	    int isa_rev = __mips_isa_rev;
+	    #else
+	    int isa_rev = 0;
+	    #endif
+	}]
+	foreach lhs { isa isa_rev } {
+	    regsub ".*$lhs = (\[^;\]*).*" $output {\1} rhs
+	    verbose -log "Architecture $arch has $lhs $rhs"
+	    set mips_arch_info($arch,$lhs) $rhs
+	}
+	mips_pop_test_options saved_options
+    }
+    return $mips_arch_info($arch,$prop)
+}
+
+# Return the option group associated with OPTION, or "" if none.
+proc mips_option_maybe_group { option } {
+    global mips_option_groups
+
+    foreach { group regexp } $mips_option_groups {
+	if { [regexp -- "^($regexp)\$" $option] } {
+	    return $group
+	}
+    }
+    return ""
+}
+
+# Return the option group associated with OPTION.  Raise an error if
+# there is none.
+proc mips_option_group { option } {
+    set group [mips_option_maybe_group $option]
+    if { [string equal $group ""] } {
+	error "Unrecognised option: $option"
+    }
+    return $group
+}
+
+# Return the option for option group GROUP, or "" if no option in that
+# group has been chosen.  UPSTATUS describes the option status.
+proc mips_option { upstatus group } {
+    upvar $upstatus status
+
+    return $status(option,$group)
+}
+
+# If the default options for this test run include an option in group GROUP,
+# return that option, otherwise return "".
+proc mips_original_option { group } {
+    global mips_base_options
+
+    return [mips_option mips_base_options $group]
+}
+
+# Return true if the test described up UPSTATUS requires a specific
+# option in group GROUP.
+proc mips_test_option_p { upstatus group } {
+    upvar $upstatus status
+
+    return $status(test_option_p,$group)
+}
+
+# If the test described by UPSTATUS requires a particular option in group
+# GROUP, return that option, otherwise return "".
+proc mips_test_option { upstatus group } {
+    upvar $upstatus status
+
+    if { [mips_test_option_p status $group] } {
+	return [mips_option status $group]
+    } else {
+	return ""
+    }
+}
+
+# Return true if the options described by UPSTATUS include OPTION.
+proc mips_have_option_p { upstatus option } {
+    upvar $upstatus status
+
+    return [mips_same_option_p \
+		[mips_option status [mips_option_group $option]] \
+		$option]
+}
+
+# Return true if the test described by UPSTATUS requires option OPTION.
+proc mips_have_test_option_p { upstatus option } {
+    upvar $upstatus status
+
+    set group [mips_option_group $option]
+    return [mips_same_option_p [mips_test_option status $group] $option]
+}
+
+# If the test described by UPSTATUS does not specify an option in
+# OPTION's group, act as though it had specified OPTION.
+#
+# The first optional argument indicates whether the option should be
+# treated as though it were wrapped in parentheses; see the comment at
+# the top of the file for details about this convention.  The default is 0.
+proc mips_make_test_option { upstatus option args } {
+    upvar $upstatus status
+
+    set group [mips_option_group $option]
+    if { ![mips_test_option_p status $group] } {
+	set status(option,$group) $option
+	set status(test_option_p,$group) 1
+	if { [llength $args] == 0 || ![lindex $args 0] } {
+	    set status(explicit_p,$group) 1
+	}
+    }
+}
+
+# If the test described by UPSTATUS requires option FROM, assume that
+# it implicitly requires option TO.
+proc mips_option_dependency { upstatus from to } {
+    upvar $upstatus status
+
+    if { [mips_have_test_option_p status $from] } {
+	mips_make_test_option status $to
+    }
+}
+
+# Return true if the given arch-group option specifies a 32-bit ISA.
+proc mips_32bit_arch_p { option } {
+    set isa [mips_arch_info $option isa]
+    return [expr { $isa < 3 || $isa == 32 }]
+}
+
+# Return true if the given arch-group option specifies a 64-bit ISA.
+proc mips_64bit_arch_p { option } {
+    return [expr { ![mips_32bit_arch_p $option] }]
+}
+
+# Return true if the given abi-group option implicitly requires -mgp32.
+proc mips_32bit_abi_p { option } {
+    switch -glob -- $option {
+	-mabi=32 {
+	    return 1
+	}
+    }
+    return 0
+}
+
+# Return true if the given abi-group option implicitly requires -mgp64.
+proc mips_64bit_abi_p { option } {
+    switch -glob -- $option {
+	-mabi=o64 -
+	-mabi=n32 -
+	-mabi=64 {
+	    return 1
+	}
+    }
+    return 0
+}
+
+# Check whether the current target supports all the options that the
+# current test requires.  Return "" if so, otherwise return one of
+# the incompatible options.  UPSTATUS describes the option status.
+proc mips_first_unsupported_option { upstatus } {
+    global mips_option_tests
+    upvar $upstatus status
+
+    foreach { option code } [array get mips_option_tests] {
+	if { [mips_have_test_option_p status $option] } {
+	    regsub -all "\n" $code "\\n\\\n" asm
+	    # Use check_runtime from target-supports.exp, which caches
+	    # the result for us.
+	    if { ![check_runtime mips_option_$option [subst {
+		__attribute__((nomips16)) int
+		main (void)
+		{
+		    asm (".set push\
+		    $asm\
+		    .set pop");
+		    return 0;
+		}
+	    }]] } {
+		return $option
+	    }
+	}
+    }
+    return ""
+}
+
+# Initialize this testsuite for a new test variant.
+proc mips-dg-init {} {
+    # Invariant information.
+    global mips_option_groups
+
+    # Internally-generated information about this run.
+    global mips_base_options
+    global mips_extra_options
+
+    # Override dg-options with our mips-dg-options routine.
+    rename dg-options mips-old-dg-options
+    rename mips-dg-options dg-options
+
+    # Start with a fresh option status.
+    array unset mips_base_options
+    foreach { group regexp } $mips_option_groups {
+	set mips_base_options(option,$group) ""
+	set mips_base_options(explicit_p,$group) 0
+	set mips_base_options(test_option_p,$group) 0
+    }
+
+    # Use preprocessor macros to work out as many implicit options as we can.
+    set output [mips_preprocess "" {
+	const char *options[] = {
+	    #if !defined _MIPS_SIM
+	    "-mabi=eabi",
+	    #elif _MIPS_SIM==_ABIO32
+	    "-mabi=32",
+	    #elif _MIPS_SIM==_ABIO64
+	    "-mabi=o64",
+	    #elif _MIPS_SIM==_ABIN32
+	    "-mabi=n32",
+	    #else
+	    "-mabi=64",
+	    #endif
+
+	    "-march=" _MIPS_ARCH,
+
+	    #ifdef _MIPSEB
+	    "-EB",
+	    #else
+	    "-EL",
+	    #endif
+
+	    #ifdef __mips_hard_float
+	    "-mhard-float",
+	    #else
+	    "-msoft-float",
+	    #endif
+
+	    #if __mips_fpr == 64
+	    "-mfp64",
+	    #else
+	    "-mfp32",
+	    #endif
+
+	    #ifdef __mips64
+	    "-mgp64",
+	    #else
+	    "-mgp32",
+	    #endif
+
+	    #if _MIPS_SZLONG == 64
+	    "-mlong64",
+	    #else
+	    "-mlong32",
+	    #endif
+
+	    #ifdef __mips16
+	    "-mips16",
+	    #else
+	    "-mno-mips16",
+	    #endif
+
+	    #ifdef __mips3d
+	    "-mips3d",
+	    #else
+	    "-mno-mips3d",
+	    #endif
+
+	    #ifdef __mips_paired_single_float
+	    "-mpaired-single",
+	    #else
+	    "-mno-paired-single",
+	    #endif
+
+	    #if __mips_abicalls
+	    "-mabicalls",
+	    #else
+	    "-mno-abicalls",
+	    #endif
+
+	    #if __mips_dsp_rev >= 2
+	    "-mdspr2",
+	    #else
+	    "-mno-dspr2",
+	    #endif
+
+	    #if __mips_dsp_rev >= 1
+	    "-mdsp",
+	    #else
+	    "-mno-dsp",
+	    #endif
+
+	    #ifndef __PIC__
+	    "addressing=absolute",
+	    #endif
+
+	    #ifdef __mips_smartmips
+	    "-msmartmips",
+	    #else
+	    "-mno-smartmips",
+	    #endif
+
+	    0
+	};
+    }]
+    foreach line [split $output "\r\n"] {
+	# Poor man's string concatenation.
+	regsub -all {" "} $line "" line
+	if { [regexp {"(.*)",} $line dummy option] } {
+	    set group [mips_option_group $option]
+	    set mips_base_options(option,$group) $option
+	}
+    }
+
+    # Process the target's multilib options, saving any unrecognized
+    # ones in mips_extra_options.
+    set mips_extra_options {}
+    foreach option [split [board_info target multilib_flags]] {
+	set group [mips_option_maybe_group $option]
+	if { ![string equal $group ""] } {
+	    set mips_base_options(option,$group) $option
+	    set mips_base_options(explicit_p,$group) 1
+	} else {
+	    lappend mips_extra_options $option
+	}
+    }
+}
+
+# Finish a test run started by mips-dg-init.
+proc mips-dg-finish {} {
+    rename dg-options mips-dg-options
+    rename mips-old-dg-options dg-options
+}
+
+# Override dg-options so that we can do some MIPS-specific processing.
+# All options used in this testsuite must appear in mips_option_groups.
+#
+# Test options override multilib options.  Certain test options can
+# also imply other test options, which also override multilib options.
+# These dependencies are ordered as follows:
+#
+#          START                        END
+#            |                           |
+#         -mips16                     -mno-mips16
+#            |                           |
+#         -mips3d                     -mno-mips3d
+#            |                           |
+#         -mpaired-single             -mno-paired-single
+#            |                           |
+#         -mfp64                      -mfp32
+#            |                           |
+#         -mhard-float                -msoft-float
+#            |                           |
+#         -mno-sym32                  -msym32
+#            |                           |
+#         -fpic                       -fno-pic
+#            |                           |
+#         -mshared                    -mno-shared
+#            |                           |
+#         -mno-plt                    -mplt
+#            |                           |
+#         addressing=unknown          addressing=absolute
+#            |                           |
+#         -mabicalls                  -mno-abicalls
+#            |                           |
+#         -G0                         <other value>
+#            |                           |
+#         <other value>               -mr10k-cache-barrier=none
+#            |                           |
+#         -mfix-r10000                -mno-fix-r10000
+#            |                           |
+#         -mbranch-likely             -mno-branch-likely
+#            |                           |
+#         -msmartmips                 -mno-smartmips
+#            |                           |
+#         -mno-gpopt                  -mgpopt
+#            |                           |
+#         -mexplicit-relocs           -mno-explicit-relocs
+#            |                           |
+#            +-- gp, abi & arch ---------+
+#
+# For these purposes, the "gp", "abi" & "arch" option groups are treated
+# as a single node.
+proc mips-dg-options { args } {
+    # dg.exp variables.
+    upvar dg-extra-tool-flags extra_tool_flags
+    upvar dg-do-what do_what
+
+    # Invariant information.
+    global mips_option_groups
+    global mips_abi_groups
+
+    # Information about this run.
+    global mips_base_options
+
+    # Start out with the default option state.
+    array set options [array get mips_base_options]
+
+    # Record the options that this test explicitly needs.
+    foreach option [lindex $args 1] {
+	set all_but_p [regexp {^\((.*)\)$} $option dummy option]
+	set group [mips_option_group $option]
+	if { [mips_test_option_p options $group] } {
+	    set old [mips_option options $group]
+	    error "Inconsistent $group option: $old vs. $option"
+	} else {
+	    mips_make_test_option options $option $all_but_p
+	}
+    }
+
+    # Handle dependencies between options on the left of the
+    # dependency diagram.
+    mips_option_dependency options "-mips3d" "-mpaired-single"
+    mips_option_dependency options "-mpaired-single" "-mfp64"
+    mips_option_dependency options "-mfp64" "-mhard-float"
+    mips_option_dependency options "-fpic" "-mshared"
+    mips_option_dependency options "-mshared" "-mno-plt"
+    mips_option_dependency options "-mno-plt" "addressing=unknown"
+    mips_option_dependency options "-mabicalls" "-G0"
+    mips_option_dependency options "-mno-gpopt" "-mexplicit-relocs"
+
+    # Work out information about the current ABI.
+    set abi_test_option_p [mips_test_option_p options abi]
+    set abi [mips_option options abi]
+    set eabi_p [mips_same_option_p $abi "-mabi=eabi"]
+
+    # If the test forces a particular ABI, set the register size
+    # accordingly.
+    if { $abi_test_option_p } {
+	if { [mips_32bit_abi_p $abi] } {
+	    mips_make_test_option options "-mgp32"
+	} elseif { [mips_64bit_abi_p $abi] } {
+	    mips_make_test_option options "-mgp64"
+	}
+    }
+
+    # Interpret the special "isa" and "isa_rev" options.  If we have
+    # a choice of a 32-bit or a 64-bit architecture, prefer to keep
+    # the -mgp setting the same.
+    set spec [mips_option options arch]
+    if { [regexp {^[^-]} $spec] } {
+	set arch [mips_option mips_base_options arch]
+	if { [string equal $spec "isa=loongson"] } {
+	    if { ![regexp {^-march=loongson} $arch] } {
+		set arch "-march=loongson2f"
+	    }
+	} else {
+	    # With ! and = the ISA value is optional.
+	    if { ![regexp {^(isa(?:|_rev))(=|<=|>=)([0-9]*)((?:![^!]+)*)$} \
+		       $spec dummy prop relation value nocpus]
+		 || ($value eq ""
+		     && ($relation ne "="
+			 || $nocpus eq ""))} {
+		error "Unrecognized isa specification: $spec"
+	    }
+	    if { $value ne "" } {
+		set current [mips_arch_info $arch $prop]
+		if { ($current < $value && ![string equal $relation "<="])
+		     || ($current > $value && ![string equal $relation ">="])
+		     || ([mips_have_test_option_p options "-mgp64"]
+			 && [mips_32bit_arch_p $arch]) } {
+		    # The current setting is out of range; it cannot
+		    # possibly be used.  Find a replacement that can.
+		    if { [string equal $prop "isa"] } {
+			set arch "-mips$value"
+		    } elseif { $value == 0 } {
+			set arch "-mips4"
+		    } else {
+			if { [mips_have_option_p options "-mgp32"] } {
+			    set arch "-mips32"
+			} else {
+			    set arch "-mips64"
+			}
+			if { $value > 1 } {
+			    append arch "r$value"
+			}
+		    }
+		}
+	    }
+	    # If we haven't switched to a generic ISA based on the
+	    # isa* value, do it here if the processor-specific
+	    # extension is not allowed.
+	    if { $nocpus ne ""
+		 && $arch eq [mips_option mips_base_options arch] } {
+		set cpu [regsub -- {-march=} $arch ""]
+		if { [regexp "!$cpu!" "$nocpus!"] } {
+		    set isa_rev [mips_arch_info $arch isa_rev]
+		    set arch "-mips[mips_arch_info $arch isa]"		
+		    if { $isa_rev > 1 } {
+			append arch "r$isa_rev"
+		    }
+		}
+	    }
+	}
+	set options(option,arch) $arch
+    }
+
+    # Work out information about the current architecture.
+    set arch_test_option_p [mips_test_option_p options arch]
+    set arch [mips_option options arch]
+    set isa [mips_arch_info $arch isa]
+    set isa_rev [mips_arch_info $arch isa_rev]
+
+    # If the test forces a 32-bit architecture, force -mgp32.
+    # Force the current -mgp setting otherwise; if we don't,
+    # some configurations would make a 64-bit architecture
+    # imply -mgp64.
+    if { $arch_test_option_p } {
+	if { [mips_32bit_arch_p $arch] } {
+	    mips_make_test_option options "-mgp32"
+	} else {
+	    mips_make_test_option options [mips_option options gp]
+	}
+    }
+
+    # We've now fixed the GP register size.  Make it easily available.
+    set gp_size [expr { [mips_have_option_p options "-mgp32"] ? 32 : 64 }]
+
+    # Handle dependencies between the pre-arch options and the arch option.
+    # This should mirror the arch and post-arch code below.
+    if { !$arch_test_option_p } {
+	# We need a revision 2 or better ISA for:
+	#
+	#   - the combination of -mgp32 -mfp64
+	#   - the DSP ASE
+	if { $isa_rev < 2
+	     && (($gp_size == 32 && [mips_have_test_option_p options "-mfp64"])
+		 || [mips_have_test_option_p options "-mdsp"]
+		 || [mips_have_test_option_p options "-mdspr2"]) } {
+	    if { $gp_size == 32 } {
+		mips_make_test_option options "-mips32r2"
+	    } else {
+		mips_make_test_option options "-mips64r2"
+	    }
+        # We need a MIPS32 or MIPS64 ISA for:
+	#
+        #   - paired-single instructions(*)
+        #
+	# (*) Note that we don't support MIPS V at the moment.
+	} elseif { $isa_rev < 1
+		   && [mips_have_test_option_p options "-mpaired-single"] } {
+	    if { $gp_size == 32 } {
+		mips_make_test_option options "-mips32"
+	    } else {
+		mips_make_test_option options "-mips64"
+	    }
+        # We need MIPS III or higher for:
+	#
+	#   - the "cache" instruction
+	} elseif { $isa < 3
+		   && ([mips_have_test_option_p options \
+			    "-mr10k-cache-barrier=load-store"]
+		       || [mips_have_test_option_p options \
+			       "-mr10k-cache-barrier=store"]) } {
+	    mips_make_test_option options "-mips3"
+        # We need MIPS II or higher for:
+	#
+	#   - branch-likely instructions(*)
+        #
+	# (*) needed by both -mbranch-likely and -mfix-r10000
+	} elseif { $isa < 2
+		   && ([mips_have_test_option_p options "-mbranch-likely"]
+		       || [mips_have_test_option_p options "-mfix-r10000"]) } {
+	    mips_make_test_option options "-mips2"
+	# Check whether we need to switch from a 32-bit processor to the
+	# "nearest" 64-bit processor.
+	} elseif { $gp_size == 64 && [mips_32bit_arch_p $arch] } {
+	    if { $isa_rev == 0 } {
+		mips_make_test_option options "-mips3"
+	    } elseif { $isa_rev == 1 } {
+		mips_make_test_option options "-mips64"
+	    } else {
+		mips_make_test_option options "-mips64r$isa_rev"
+	    }
+	}
+	unset arch
+	unset isa
+	unset isa_rev
+    }
+
+    # Set an appropriate ABI, handling dependencies between the pre-abi
+    # options and the abi options.  This should mirror the abi and post-abi
+    # code below.
+    if { !$abi_test_option_p } {
+	if { ($eabi_p
+	      && ([mips_have_option_p options "-mabicalls"]
+		  || ($gp_size == 32
+		      && [mips_have_option_p options "-mfp64"]))) } {
+	    # EABI doesn't support -mabicalls.
+	    # EABI doesn't support the combination -mgp32 -mfp64.
+	    set force_abi 1
+	} elseif { [mips_have_option_p options "-mips16"]
+		   && ![mips_same_option_p $abi "-mabi=32"]
+		   && ![mips_same_option_p $abi "-mabi=o64"]
+		   && (![mips_have_option_p options "addressing=absolute"]
+		       || [mips_have_option_p options "-mhard-float"]) } {
+	    # -mips16 -mhard-float requires o32 or o64.
+	    # -mips16 PIC requires o32 or o64.
+	    set force_abi 1
+	} else {
+	    set force_abi 0
+	}
+	if { $gp_size == 32 } {
+	    if { $force_abi || [mips_64bit_abi_p $abi] } {
+		mips_make_test_option options "-mabi=32"
+	    }
+	} else {
+	    if { $force_abi || [mips_32bit_abi_p $abi] } {
+		# All configurations should have an assembler that
+		# supports o64, since it requires the same BFD target
+		# vector as o32.  In contrast, many assembler
+		# configurations do not have n32 or n64 support.
+		mips_make_test_option options "-mabi=o64"
+	    }
+	}
+	unset abi
+	unset eabi_p
+    }
+
+    # Handle dependencies between the abi options and the post-abi options.
+    # This should mirror the abi and pre-abi code above.
+    if { $abi_test_option_p } {
+	if { $eabi_p } {
+	    mips_make_test_option options "-mno-abicalls"
+	    if { $gp_size == 32 } {
+		mips_make_test_option options "-mfp32"
+	    }
+	}
+	if { [mips_have_option_p options "-mips16"]
+	     && ![mips_same_option_p $abi "-mabi=32"]
+	     && ![mips_same_option_p $abi "-mabi=o64"]
+	     && (![mips_have_option_p options "addressing=absolute"]
+		 || [mips_have_option_p options "-mhard-float"]) } {
+	    if { [mips_test_option_p options mips16] } {
+		mips_make_test_option options "addressing=absolute"
+		mips_make_test_option options "-msoft-float"
+	    } else {
+		mips_make_test_option options "-mno-mips16"
+	    }
+	}
+	unset abi
+	unset eabi_p
+    }
+
+    # Handle dependencies between the arch option and the post-arch options.
+    # This should mirror the arch and pre-arch code above.
+    if { $arch_test_option_p } {
+	if { $isa < 2 } {
+	    mips_make_test_option options "-mno-branch-likely"
+	    mips_make_test_option options "-mno-fix-r10000"
+	}
+	if { $isa < 3 } {
+	    mips_make_test_option options "-mr10k-cache-barrier=none"
+	}
+	if { $isa_rev < 1 } {
+	    mips_make_test_option options "-mno-paired-single"
+	}
+	if { $isa_rev < 2 } {
+	    if { $gp_size == 32 } {
+		mips_make_test_option options "-mfp32"
+	    }
+	    mips_make_test_option options "-mno-dsp"
+	    mips_make_test_option options "-mno-dspr2"
+	}
+	unset arch
+	unset isa
+	unset isa_rev
+    }
+
+    # Handle dependencies between options on the right of the diagram.
+    mips_option_dependency options "-mno-explicit-relocs" "-mgpopt"
+    switch -- [mips_test_option options small-data] {
+	"" -
+	-G0 {}
+	default {
+	    mips_make_test_option options "-mno-abicalls"
+	}
+    }
+    if { [mips_have_option_p options "-mabicalls"] } {
+	mips_option_dependency options "addressing=absolute" "-mplt"
+    }
+    mips_option_dependency options "-mplt" "-msym32"
+    mips_option_dependency options "-mplt" "-mno-shared"
+    mips_option_dependency options "-mno-shared" "-fno-pic"
+    mips_option_dependency options "-mfp32" "-mno-paired-single"
+    mips_option_dependency options "-msoft-float" "-mno-paired-single"
+    mips_option_dependency options "-mno-paired-single" "-mno-mips3d"
+
+    # If the test requires an unsupported option, change run tests
+    # to link tests.
+
+    switch -- [lindex $do_what 0] {
+	run {
+	    set option [mips_first_unsupported_option options]
+	    if { ![string equal $option ""] } {
+		set do_what [lreplace $do_what 0 0 link]
+		verbose -log "Downgraded to a 'link' test due to unsupported option '$option'"
+	    }
+	}
+    }
+
+    # If the test has overridden a option that changes the ABI,
+    # downgrade a link or execution test to an assembler test.
+    foreach group $mips_abi_groups {
+	set old_option [mips_original_option $group]
+	set new_option [mips_option options $group]
+	if { ![mips_same_option_p $old_option $new_option] } {
+	    switch -- [lindex $do_what 0] {
+		link -
+		run {
+		    set do_what [lreplace $do_what 0 0 assemble]
+		    verbose -log "Downgraded to an 'assemble' test due to incompatible $group option ($old_option changed to $new_option)"
+		}
+	    }
+	    break
+	}
+    }
+
+    # Add all options to the dg variable.
+    set options(explicit_p,addressing) 0
+    foreach { group regexp } $mips_option_groups {
+	if { $options(explicit_p,$group) } {
+	    append extra_tool_flags " " $options(option,$group)
+	}
+    }
+
+    # If the test is MIPS16-compatible, provide a counterpart to the
+    # NOMIPS16 convenience macro.
+    if { [mips_have_test_option_p options "-mips16"] } {
+	append extra_tool_flags " -DMIPS16=__attribute__((mips16))"
+    }
+
+    # Use our version of gcc-dg-test for this test.
+    if { ![string equal [info procs "mips-gcc-dg-test"] ""] } {
+	rename gcc-dg-test mips-old-gcc-dg-test
+	rename mips-gcc-dg-test gcc-dg-test
+    }
+}
+
+# A version of gcc-dg-test that is used by dg-options tests.
+proc mips-gcc-dg-test { prog do_what extra_tool_flags } {
+    global board_info
+    global mips_extra_options
+
+    # Override the user's chosen test options with the combined test/user
+    # version.
+    mips_push_test_options saved_options $mips_extra_options
+    set result [gcc-dg-test-1 gcc_target_compile $prog \
+		    $do_what $extra_tool_flags]
+    mips_pop_test_options saved_options
+
+    # Restore the usual gcc-dg-test.
+    rename gcc-dg-test mips-gcc-dg-test
+    rename mips-old-gcc-dg-test gcc-dg-test
+
+    return $result
+}
+
+dg-init
+mips-dg-init
+# MIPS16 is defined by "-mips16" or "(-mips16)" in dg-options.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.c]] "" \
+    "-DNOMIPS16=__attribute__((nomips16))"
+mips-dg-finish
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips16-attributes-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips16-attributes-2.c
new file mode 100644
index 000000000..bc81cfa7e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips16-attributes-2.c
@@ -0,0 +1,16 @@
+/* { dg-skip-if "" { *-*-* } { "-mflip-mips16" } { "" } } */
+/* { dg-options "(-mips16)" } */
+
+void f1 (void);
+void __attribute__((mips16)) f1 (void) {} /* { dg-error "conflicting" } */
+
+void __attribute__((mips16)) f2 (void);
+void f2 (void) {} /* { dg-error "conflicting" } */
+
+void f3 (void);
+void __attribute__((nomips16)) f3 (void) {} /* { dg-error "conflicting" } */
+
+void __attribute__((nomips16)) f4 (void);
+void f4 (void) {} /* { dg-error "conflicting" } */
+
+void __attribute__((mips16, nomips16)) f5 (void) {} /* { dg-error "cannot have both" } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips16-attributes-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips16-attributes-3.c
new file mode 100644
index 000000000..747450390
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips16-attributes-3.c
@@ -0,0 +1,7 @@
+/* { dg-options "(-mips16)" } */
+/* We should be able to assign mips16 and nomips16 functions to a pointer.  */
+void __attribute__((mips16)) f1 (void);
+void (*ptr1) (void) = f1;
+
+void __attribute__((nomips16)) f2 (void);
+void (*ptr2) (void) = f2;
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips16-attributes.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips16-attributes.c
new file mode 100644
index 000000000..28bb9aae7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips16-attributes.c
@@ -0,0 +1,83 @@
+/* Verify that mips16 and nomips16 attributes work, checking all combinations
+   of calling a nomips16/mips16/default function from a nomips16/mips16/default
+   function.  */
+/* { dg-do run } */
+/* { dg-options "(-mips16)" } */
+
+#include <stdlib.h>
+
+#define ATTR1 __attribute__ ((nomips16))
+#define ATTR2 __attribute__ ((mips16))
+#define ATTR3
+
+double ATTR1
+f1 (int i, float f, double d)
+{
+  return i + f + d;
+}
+
+double ATTR2
+f2 (int i, float f, double d)
+{
+  return i + f + d;
+}
+
+double ATTR3
+f3 (int i, float f, double d)
+{
+  return i + f + d;
+}
+
+void ATTR1
+g1 (int i, float f, double d)
+{
+  double r = i + f + d;
+
+  if (f1 (i, f, d) != r)
+    abort ();
+  if (f2 (i+1, f+1, d+1) != r + 3)
+    abort ();
+  if (f3 (i+2, f+2, d+2) != r + 6)
+    abort ();
+}
+
+void ATTR2
+g2 (int i, float f, double d)
+{
+  double r = i + f + d;
+
+  if (f1 (i, f, d) != r)
+    abort ();
+  if (f2 (i+1, f+1, d+1) != r + 3)
+    abort ();
+  if (f3 (i+2, f+2, d+2) != r + 6)
+    abort ();
+}
+
+void ATTR3
+g3 (int i, float f, double d)
+{
+  double r = i + f + d;
+
+  if (f1 (i, f, d) != r)
+    abort ();
+  if (f2 (i+1, f+1, d+1) != r + 3)
+    abort ();
+  if (f3 (i+2, f+2, d+2) != r + 6)
+    abort ();
+}
+
+int ATTR3
+main (void)
+{
+  int i = 1;
+  float f = -2.0;
+  double d = 3.0;
+
+  g1 (i, f, d);
+  g2 (i, f, d);
+  g3 (i, f, d);
+
+  exit (0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips16e-extends.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips16e-extends.c
new file mode 100644
index 000000000..d077f2fae
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips16e-extends.c
@@ -0,0 +1,21 @@
+/* -mlong32 added because of PR target/38595.  */
+/* { dg-options "(-mips16) -Os isa_rev>=1 -mlong32" } */
+
+MIPS16 short cksum16 (unsigned long n)
+{
+  unsigned long l;
+  l = validate (n, (n >> 16) + (n & 0xffff));
+  return l;
+}
+
+MIPS16 signed char cksum8 (unsigned long n)
+{
+  unsigned long l;
+  l = validate (n, (n >> 8) + (n & 0xff));
+  return l;
+}
+
+/* { dg-final { scan-assembler "zeh" } } */
+/* { dg-final { scan-assembler "seh" } } */
+/* { dg-final { scan-assembler "zeb" } } */
+/* { dg-final { scan-assembler "seb" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32-dsp-run.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32-dsp-run.c
new file mode 100644
index 000000000..e6a271e24
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32-dsp-run.c
@@ -0,0 +1,1001 @@
+/* Test MIPS32 DSP instructions */
+/* { dg-do run } */
+/* { dg-options "-mdsp -O2" } */
+
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef signed char v4i8 __attribute__ ((vector_size(4)));
+typedef short v2q15 __attribute__ ((vector_size(4)));
+
+typedef int q31;
+typedef int i32;
+typedef long long a64;
+
+NOMIPS16 void test_MIPS_DSP (void);
+
+char array[100];
+int little_endian;
+
+int main ()
+{
+  int i;
+
+  union { long long ll; int i[2]; } endianness_test;
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  for (i = 0; i < 100; i++)
+    array[i] = i;
+
+  test_MIPS_DSP ();
+
+  exit (0);
+}
+
+NOMIPS16 v2q15 add_v2q15 (v2q15 a, v2q15 b)
+{
+  return __builtin_mips_addq_ph (a, b);
+}
+
+NOMIPS16 v4i8 add_v4i8 (v4i8 a, v4i8 b)
+{
+  return __builtin_mips_addu_qb (a, b);
+}
+
+NOMIPS16 v2q15 sub_v2q15 (v2q15 a, v2q15 b)
+{
+  return __builtin_mips_subq_ph (a, b);
+}
+
+NOMIPS16 v4i8 sub_v4i8 (v4i8 a, v4i8 b)
+{
+  return __builtin_mips_subu_qb (a, b);
+}
+
+NOMIPS16 void test_MIPS_DSP ()
+{
+  v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s;
+  v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s;
+  q31 q31_a,q31_b,q31_c,q31_r,q31_s;
+  i32 i32_a,i32_b,i32_c,i32_r,i32_s;
+  a64 a64_a,a64_b,a64_c,a64_r,a64_s;
+
+  void *ptr_a;
+  int r,s;
+  long long lr,ls;
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x81bd, 0x6789};
+  v2q15_r = add_v2q15 (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x7fff, 0x6789};
+  v2q15_r = __builtin_mips_addq_s_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_b = 0x71234567;
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_addq_s_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0xf1, 0xbd, 0x67, 0x89};
+  v4i8_r = add_v4i8 (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0xff, 0xbd, 0x67, 0x89};
+  v4i8_r = __builtin_mips_addu_s_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0xa2ab, 0x4567};
+  v2q15_r = sub_v2q15 (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x8000, 0x4567};
+  v2q15_r = __builtin_mips_subq_s_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_b = 0x71234567;
+  q31_s = 0xfedcba99;
+  q31_r = __builtin_mips_subq_s_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0xf3, 0xab, 0x45, 0x67};
+  v4i8_r = sub_v4i8 (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0x0, 0x0, 0x45, 0x67};
+  v4i8_r = __builtin_mips_subu_s_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0xf5678900;
+  i32_b = 0x7abcdef0;
+  i32_s = 0x702467f0;
+  i32_r = __builtin_mips_addsc (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x75678900;
+  i32_b = 0x7abcdef0;
+  i32_s = 0xf02467f1;
+  i32_r = __builtin_mips_addwc (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0;
+  i32_b = 0x00000901;
+  i32_s = 9;
+  i32_r = __builtin_mips_modsub (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  i32_s = 0x1f4;
+  i32_r = __builtin_mips_raddu_w_qb (v4i8_a);
+  if (i32_r != i32_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x8134};
+  v2q15_s = (v2q15) {0x7fff, 0x7ecc};
+  v2q15_r = __builtin_mips_absq_s_ph (v2q15_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = (q31) 0x80000000;
+  q31_s = (q31) 0x7fffffff;
+  q31_r = __builtin_mips_absq_s_w (q31_a);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x9999, 0x5612};
+  v2q15_b = (v2q15) {0x5612, 0x3333};
+  if (little_endian)
+    v4i8_s = (v4i8) {0x56, 0x33, 0x99, 0x56};
+  else
+    v4i8_s = (v4i8) {0x99, 0x56, 0x56, 0x33};
+  v4i8_r = __builtin_mips_precrq_qb_ph (v2q15_a, v2q15_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x12348678;
+  q31_b = 0x44445555;
+  if (little_endian)
+    v2q15_s = (v2q15) {0x4444, 0x1234};
+  else
+    v2q15_s = (v2q15) {0x1234, 0x4444};
+  v2q15_r = __builtin_mips_precrq_ph_w (q31_a, q31_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x12348678;
+  q31_b = 0x44445555;
+  if (little_endian)
+    v2q15_s = (v2q15) {0x4444, 0x1235};
+  else
+    v2q15_s = (v2q15) {0x1235, 0x4444};
+  v2q15_r = __builtin_mips_precrq_rs_ph_w (q31_a, q31_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x9999, 0x5612};
+  v2q15_b = (v2q15) {0x5612, 0x3333};
+  if (little_endian)
+    v4i8_s = (v4i8) {0xac, 0x66, 0x00, 0xac};
+  else
+    v4i8_s = (v4i8) {0x00, 0xac, 0xac, 0x66};
+  v4i8_r = __builtin_mips_precrqu_s_qb_ph (v2q15_a, v2q15_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3589, 0x4444};
+  if (little_endian)
+    q31_s = 0x44440000;
+  else
+    q31_s = 0x35890000;
+  q31_r = __builtin_mips_preceq_w_phl (v2q15_a);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3589, 0x4444};
+  if (little_endian)
+    q31_s = 0x35890000;
+  else
+    q31_s = 0x44440000;
+  q31_r = __builtin_mips_preceq_w_phr (v2q15_a);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  else
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  v2q15_r = __builtin_mips_precequ_ph_qbl (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  else
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  v2q15_r = __builtin_mips_precequ_ph_qbr (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  else
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  v2q15_r = __builtin_mips_precequ_ph_qbla (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  else
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  v2q15_r = __builtin_mips_precequ_ph_qbra (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x56, 0x33};
+  else
+    v2q15_s = (v2q15) {0x12, 0x56};
+  v2q15_r = __builtin_mips_preceu_ph_qbl (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x12, 0x56};
+  else
+    v2q15_s = (v2q15) {0x56, 0x33};
+  v2q15_r = __builtin_mips_preceu_ph_qbr (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x99, 0x33};
+  else
+    v2q15_s = (v2q15) {0x12, 0x56};
+  v2q15_r = __builtin_mips_preceu_ph_qbla (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x12, 0x56};
+  else
+    v2q15_s = (v2q15) {0x99, 0x33};
+  v2q15_r = __builtin_mips_preceu_ph_qbra (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_s = (v4i8) {0xc8, 0xd0, 0x58, 0xe0};
+  v4i8_r = __builtin_mips_shll_qb (v4i8_a, 2);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  i32_b = 1;
+  v4i8_s = (v4i8) {0xe4, 0x68, 0xac, 0xf0};
+  v4i8_r = __builtin_mips_shll_qb (v4i8_a, i32_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d0, 0x59e0};
+  v2q15_r = __builtin_mips_shll_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 1;
+  v2q15_s = (v2q15) {0x2468, 0xacf0};
+  v2q15_r = __builtin_mips_shll_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d0, 0x7fff};
+  v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 1;
+  v2q15_s = (v2q15) {0x2468, 0x7fff};
+  v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_shll_s_w (q31_a, 2);
+  if (q31_r != q31_s)
+    abort ();
+
+  q31_a = 0x70000000;
+  i32_b = 1;
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_shll_s_w (q31_a, i32_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_s = (v4i8) {0x3c, 0xd, 0x15, 0x1e};
+  v4i8_r = __builtin_mips_shrl_qb (v4i8_a, 2);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  i32_b = 1;
+  v4i8_s = (v4i8) {0x79, 0x1a, 0x2b, 0x3c};
+  v4i8_r = __builtin_mips_shrl_qb (v4i8_a, i32_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d, 0x159e};
+  v2q15_r = __builtin_mips_shra_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 1;
+  v2q15_s = (v2q15) {0x91a, 0x2b3c};
+  v2q15_r = __builtin_mips_shra_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d, 0x159e};
+  v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 3;
+  v2q15_s = (v2q15) {0x247, 0xacf};
+  v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_s = 0x1c000000;
+  q31_r = __builtin_mips_shra_r_w (q31_a, 2);
+  if (q31_r != q31_s)
+    abort ();
+
+  q31_a = 0x70000004;
+  i32_b = 3;
+  q31_s = 0x0e000001;
+  q31_r = __builtin_mips_shra_r_w (q31_a, i32_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  if (little_endian)
+    v2q15_s = (v2q15) {0xffff, 0x4444};
+  else
+    v2q15_s = (v2q15) {0x6f89, 0x2222};
+  v2q15_r = __builtin_mips_muleu_s_ph_qbl (v4i8_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x6f89, 0x2222};
+  else
+    v2q15_s = (v2q15) {0xffff, 0x4444};
+  v2q15_r = __builtin_mips_muleu_s_ph_qbr (v4i8_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x0fdd, 0x0b87};
+  v2q15_r = __builtin_mips_mulq_rs_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x8000};
+  v2q15_b = (v2q15) {0x8000, 0x8000};
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_muleq_s_w_phl (v2q15_a, v2q15_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x8000};
+  v2q15_b = (v2q15) {0x8000, 0x8000};
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_muleq_s_w_phr (v2q15_a, v2q15_b);
+  if (q31_r != q31_s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x22222f27;
+  else
+    a64_s = 0x222238d9;
+  a64_r = __builtin_mips_dpau_h_qbl (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x222238d9;
+  else
+    a64_s = 0x22222f27;
+  a64_r = __builtin_mips_dpau_h_qbr (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x2221f2fb;
+  else
+    a64_s = 0x2221e949;
+  a64_r = __builtin_mips_dpsu_h_qbl (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x2221e949;
+  else
+    a64_s = 0x2221f2fb;
+  a64_r = __builtin_mips_dpsu_h_qbr (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x5678};
+  v2q15_c = (v2q15) {0x8000, 0x1111};
+  a64_s = 0x8b877d00;
+  a64_r = __builtin_mips_dpaq_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x5678};
+  v2q15_c = (v2q15) {0x8000, 0x1111};
+  a64_s = 0xffffffff7478a522LL;
+  a64_r = __builtin_mips_dpsq_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x5678};
+  v2q15_c = (v2q15) {0x8000, 0x1111};
+  if (little_endian)
+    a64_s = 0xffffffff8b877d02LL;
+  else
+    a64_s = 0x7478a520;
+  a64_r = __builtin_mips_mulsaq_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  q31_b = 0x80000000;
+  q31_c = 0x80000000;
+  a64_s = 0x7fffffffffffffffLL;
+  a64_r = __builtin_mips_dpaq_sa_l_w (a64_a, q31_b, q31_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  q31_b = 0x80000000;
+  q31_c = 0x80000000;
+  a64_s = 0x8000000000001112LL;
+  a64_r = __builtin_mips_dpsq_sa_l_w (a64_a, q31_b, q31_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x1115;
+  else
+    a64_s = 0x80001110;
+  a64_r = __builtin_mips_maq_s_w_phl (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x80001110;
+  else
+    a64_s = 0x1115;
+  a64_r = __builtin_mips_maq_s_w_phr (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x1115;
+  else
+    a64_s = 0x7fffffff;
+  a64_r = __builtin_mips_maq_sa_w_phl (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x7fffffff;
+  else
+    a64_s = 0x1115;
+  a64_r = __builtin_mips_maq_sa_w_phr (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+  i32_a = 0x12345678;
+  i32_s = 0x00001e6a;
+  i32_r = __builtin_mips_bitrev (i32_a);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x00000208; // pos is 8, size is 4
+  __builtin_mips_wrdsp (i32_a, 31);
+  i32_a = 0x12345678;
+  i32_b = 0x87654321;
+  i32_s = 0x12345178;
+  i32_r = __builtin_mips_insv (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_s = (v4i8) {1, 1, 1, 1};
+  v4i8_r = __builtin_mips_repl_qb (1);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 99;
+  v4i8_s = (v4i8) {99, 99, 99, 99};
+  v4i8_r = __builtin_mips_repl_qb (i32_a);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_s = (v2q15) {30, 30};
+  v2q15_r = __builtin_mips_repl_ph (30);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x5612;
+  v2q15_s = (v2q15) {0x5612, 0x5612};
+  v2q15_r = __builtin_mips_repl_ph (i32_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x03000000;
+  else
+    i32_s = 0x0c000000;
+  __builtin_mips_cmpu_eq_qb (v4i8_a, v4i8_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x04000000;
+  else
+    i32_s = 0x02000000;
+  __builtin_mips_cmpu_lt_qb (v4i8_a, v4i8_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x07000000;
+  else
+    i32_s = 0x0e000000;
+  __builtin_mips_cmpu_le_qb (v4i8_a, v4i8_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x3;
+  else
+    i32_s = 0xc;
+  i32_r=__builtin_mips_cmpgu_eq_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x4;
+  else
+    i32_s = 0x2;
+  i32_r = __builtin_mips_cmpgu_lt_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x7;
+  else
+    i32_s = 0xe;
+  i32_r = __builtin_mips_cmpgu_le_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  __builtin_mips_wrdsp (0,31); // Clear all condition code bits.
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  if (little_endian)
+    i32_s = 0x01000000;
+  else
+    i32_s = 0x02000000;
+  __builtin_mips_cmp_eq_ph (v2q15_a, v2q15_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  if (little_endian)
+    i32_s = 0x02000000;
+  else
+    i32_s = 0x01000000;
+  __builtin_mips_cmp_lt_ph (v2q15_a, v2q15_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  i32_s = 0x03000000;
+  __builtin_mips_cmp_le_ph (v2q15_a, v2q15_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0a000000; // cc: 0000 1010
+  __builtin_mips_wrdsp (i32_a, 31);
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x21, 0x43, 0x65, 0x87};
+  if (little_endian)
+    v4i8_s = (v4i8) {0x21, 0x34, 0x65, 0x78};
+  else
+    v4i8_s = (v4i8) {0x12, 0x43, 0x56, 0x87};
+  v4i8_r = __builtin_mips_pick_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x02000000; // cc: 0000 0010
+  __builtin_mips_wrdsp (i32_a, 31);
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x2143, 0x6587};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x2143, 0x5678};
+  else
+    v2q15_s = (v2q15) {0x1234, 0x6587};
+  v2q15_r = __builtin_mips_pick_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x7856, 0x1234};
+  else
+    v2q15_s = (v2q15) {0x5678, 0x1234};
+  v2q15_r = __builtin_mips_packrl_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x1234567887654321LL;
+  i32_s = 0x88765432;
+  i32_r = __builtin_mips_extr_w (a64_a, 4);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887658321LL;
+  i32_s = 0x56788766;
+  i32_r = __builtin_mips_extr_r_w (a64_a, 16);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x12345677fffffff8LL;
+  i32_s = 0x7fffffff;
+  i32_r = __builtin_mips_extr_rs_w (a64_a, 4);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887658321LL;
+  i32_s = 0x7fff;
+  i32_r = __builtin_mips_extr_s_h (a64_a, 16);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x0000007887658321LL;
+  i32_b = 24;
+  i32_s = 0x7887;
+  i32_r = __builtin_mips_extr_s_h (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887654321LL;
+  i32_b = 4;
+  i32_s = 0x88765432;
+  i32_r = __builtin_mips_extr_w (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887658321LL;
+  i32_b = 16;
+  i32_s = 0x56788766;
+  i32_r = __builtin_mips_extr_r_w (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x12345677fffffff8LL;
+  i32_b = 4;
+  i32_s = 0x7fffffff;
+  i32_r = __builtin_mips_extr_rs_w (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_s = 8;
+  i32_r = __builtin_mips_extp (a64_a, 3); // extract 4 bits
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_b = 7; // size is 8. NOTE!! we should use 7
+  i32_s = 0x87;
+  i32_r = __builtin_mips_extp (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_s = 8;
+  i32_r = __builtin_mips_extpdp (a64_a, 3); // extract 4 bits
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_s = 0x0000021b; // pos is 27
+  i32_r = __builtin_mips_rddsp (31);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_b = 11; // size is 12. NOTE!!! We should use 11
+  i32_s = 0x876;
+  i32_r = __builtin_mips_extpdp (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_s = 0x00000213; // pos is 19
+  i32_r = __builtin_mips_rddsp (31);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887654321LL;
+  a64_s = 0x0012345678876543LL;
+  a64_r = __builtin_mips_shilo (a64_a, 8);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x1234567887654321LL;
+  i32_b = -16;
+  a64_s = 0x5678876543210000LL;
+  a64_r = __builtin_mips_shilo (a64_a, i32_b);
+  if (a64_r != a64_s)
+    abort ();
+
+  i32_a = 0x0;
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_b = 0x11112222;
+  a64_s = 0x8765432111112222LL;
+  a64_r = __builtin_mips_mthlip (a64_a, i32_b);
+  if (a64_r != a64_s)
+    abort ();
+  i32_s = 32;
+  i32_r = __builtin_mips_rddsp (31);
+  if (i32_r != i32_s)
+    abort ();
+#endif
+
+  i32_a = 0x1357a468;
+  __builtin_mips_wrdsp (i32_a, 63);
+  i32_s = 0x03572428;
+  i32_r = __builtin_mips_rddsp (63);
+  if (i32_r != i32_s)
+    abort ();
+
+  ptr_a = &array;
+  i32_b = 37;
+  i32_s = 37;
+  i32_r = __builtin_mips_lbux (ptr_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  ptr_a = &array;
+  i32_b = 38;
+  if (little_endian)
+    i32_s = 0x2726;
+  else
+    i32_s = 0x2627;
+  i32_r = __builtin_mips_lhx (ptr_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  ptr_a = &array;
+  i32_b = 40;
+  if (little_endian)
+    i32_s = 0x2b2a2928;
+  else
+    i32_s = 0x28292a2b;
+  i32_r = __builtin_mips_lwx (ptr_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x00000220; // pos is 32, size is 4
+  __builtin_mips_wrdsp (i32_a, 63);
+  i32_s = 1;
+  i32_r = __builtin_mips_bposge32 ();
+  if (i32_r != i32_s)
+    abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32-dsp-type.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32-dsp-type.c
new file mode 100644
index 000000000..cbf347b29
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32-dsp-type.c
@@ -0,0 +1,30 @@
+/* Test MIPS32 DSP instructions */
+/* { dg-do compile } */
+/* { dg-options "-mdsp" } */
+/* { dg-final { scan-assembler "addq.ph" } } */
+/* { dg-final { scan-assembler "addu.qb" } } */
+/* { dg-final { scan-assembler "subq.ph" } } */
+/* { dg-final { scan-assembler "subu.qb" } } */
+
+typedef char v4qi __attribute__ ((vector_size(4)));
+typedef short v2hi __attribute__ ((vector_size(4)));
+
+NOMIPS16 v2hi add_v2hi (v2hi a, v2hi b)
+{
+  return a + b;
+}
+
+NOMIPS16 v4qi add_v4qi (v4qi a, v4qi b)
+{
+  return a + b;
+}
+
+NOMIPS16 v2hi sub_v2hi (v2hi a, v2hi b)
+{
+  return a - b;
+}
+
+NOMIPS16 v4qi sub_v4qi (v4qi a, v4qi b)
+{
+  return a - b;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32-dsp.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32-dsp.c
new file mode 100644
index 000000000..c00ea3e0b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32-dsp.c
@@ -0,0 +1,1092 @@
+/* Test MIPS32 DSP instructions */
+/* { dg-do compile } */
+/* { dg-options "-mgp32 -mdsp" } */
+/* { dg-final { scan-assembler "addq.ph" } } */
+/* { dg-final { scan-assembler "addq_s.ph" } } */
+/* { dg-final { scan-assembler "addq_s.w" } } */
+/* { dg-final { scan-assembler "addu.qb" } } */
+/* { dg-final { scan-assembler "addu_s.qb" } } */
+/* { dg-final { scan-assembler "subq.ph" } } */
+/* { dg-final { scan-assembler "subq_s.ph" } } */
+/* { dg-final { scan-assembler "subq_s.w" } } */
+/* { dg-final { scan-assembler "subu.qb" } } */
+/* { dg-final { scan-assembler "subu_s.qb" } } */
+/* { dg-final { scan-assembler "addsc" } } */
+/* { dg-final { scan-assembler "addwc" } } */
+/* { dg-final { scan-assembler "modsub" } } */
+/* { dg-final { scan-assembler "raddu.w.qb" } } */
+/* { dg-final { scan-assembler "absq_s.ph" } } */
+/* { dg-final { scan-assembler "absq_s.w" } } */
+/* { dg-final { scan-assembler "precrq.qb.ph" } } */
+/* { dg-final { scan-assembler "precrq.ph.w" } } */
+/* { dg-final { scan-assembler "precrq_rs.ph.w" } } */
+/* { dg-final { scan-assembler "precrqu_s.qb.ph" } } */
+/* { dg-final { scan-assembler "preceq.w.phl" } } */
+/* { dg-final { scan-assembler "preceq.w.phr" } } */
+/* { dg-final { scan-assembler "precequ.ph.qbl" } } */
+/* { dg-final { scan-assembler "precequ.ph.qbr" } } */
+/* { dg-final { scan-assembler "precequ.ph.qbla" } } */
+/* { dg-final { scan-assembler "precequ.ph.qbra" } } */
+/* { dg-final { scan-assembler "preceu.ph.qbl" } } */
+/* { dg-final { scan-assembler "preceu.ph.qbr" } } */
+/* { dg-final { scan-assembler "preceu.ph.qbla" } } */
+/* { dg-final { scan-assembler "preceu.ph.qbra" } } */
+/* { dg-final { scan-assembler "shllv?.qb" } } */
+/* { dg-final { scan-assembler "shllv?.ph" } } */
+/* { dg-final { scan-assembler "shllv?_s.ph" } } */
+/* { dg-final { scan-assembler "shllv?_s.w" } } */
+/* { dg-final { scan-assembler "shrlv?.qb" } } */
+/* { dg-final { scan-assembler "shrav?.ph" } } */
+/* { dg-final { scan-assembler "shrav?_r.ph" } } */
+/* { dg-final { scan-assembler "shrav?_r.w" } } */
+/* { dg-final { scan-assembler "muleu_s.ph.qbl" } } */
+/* { dg-final { scan-assembler "muleu_s.ph.qbr" } } */
+/* { dg-final { scan-assembler "mulq_rs.ph" } } */
+/* { dg-final { scan-assembler "muleq_s.w.phl" } } */
+/* { dg-final { scan-assembler "muleq_s.w.phr" } } */
+/* { dg-final { scan-assembler "dpau.h.qbl" } } */
+/* { dg-final { scan-assembler "dpau.h.qbr" } } */
+/* { dg-final { scan-assembler "dpsu.h.qbl" } } */
+/* { dg-final { scan-assembler "dpsu.h.qbr" } } */
+/* { dg-final { scan-assembler "dpaq_s.w.ph" } } */
+/* { dg-final { scan-assembler "dpsq_s.w.ph" } } */
+/* { dg-final { scan-assembler "mulsaq_s.w.ph" } } */
+/* { dg-final { scan-assembler "dpaq_sa.l.w" } } */
+/* { dg-final { scan-assembler "dpsq_sa.l.w" } } */
+/* { dg-final { scan-assembler "maq_s.w.phl" } } */
+/* { dg-final { scan-assembler "maq_s.w.phr" } } */
+/* { dg-final { scan-assembler "maq_sa.w.phl" } } */
+/* { dg-final { scan-assembler "maq_sa.w.phr" } } */
+/* { dg-final { scan-assembler "bitrev" } } */
+/* { dg-final { scan-assembler "insv" } } */
+/* { dg-final { scan-assembler "replv?.qb" } } */
+/* { dg-final { scan-assembler "repl.ph" } } */
+/* { dg-final { scan-assembler "replv.ph" } } */
+/* { dg-final { scan-assembler "cmpu.eq.qb" } } */
+/* { dg-final { scan-assembler "cmpu.lt.qb" } } */
+/* { dg-final { scan-assembler "cmpu.le.qb" } } */
+/* { dg-final { scan-assembler "cmpgu.eq.qb" } } */
+/* { dg-final { scan-assembler "cmpgu.lt.qb" } } */
+/* { dg-final { scan-assembler "cmpgu.le.qb" } } */
+/* { dg-final { scan-assembler "cmp.eq.ph" } } */
+/* { dg-final { scan-assembler "cmp.lt.ph" } } */
+/* { dg-final { scan-assembler "cmp.le.ph" } } */
+/* { dg-final { scan-assembler "pick.qb" } } */
+/* { dg-final { scan-assembler "pick.ph" } } */
+/* { dg-final { scan-assembler "packrl.ph" } } */
+/* { dg-final { scan-assembler "extrv?.w" } } */
+/* { dg-final { scan-assembler "extrv?_s.h" } } */
+/* { dg-final { scan-assembler "extrv?_r.w" } } */
+/* { dg-final { scan-assembler "extrv?_rs.w" } } */
+/* { dg-final { scan-assembler "extpv?" } } */
+/* { dg-final { scan-assembler "extpdpv?" } } */
+/* { dg-final { scan-assembler "shilov?" } } */
+/* { dg-final { scan-assembler "mthlip" } } */
+/* { dg-final { scan-assembler "mfhi" } } */
+/* { dg-final { scan-assembler "mflo" } } */
+/* { dg-final { scan-assembler "mthi" } } */
+/* { dg-final { scan-assembler "mtlo" } } */
+/* { dg-final { scan-assembler "wrdsp" } } */
+/* { dg-final { scan-assembler "rddsp" } } */
+/* { dg-final { scan-assembler "lbux?" } } */
+/* { dg-final { scan-assembler "lhx?" } } */
+/* { dg-final { scan-assembler "lwx?" } } */
+/* { dg-final { scan-assembler "bposge32" } } */
+
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef signed char v4i8 __attribute__ ((vector_size(4)));
+typedef short v2q15 __attribute__ ((vector_size(4)));
+
+typedef int q31;
+typedef int i32;
+typedef long long a64;
+
+NOMIPS16 void test_MIPS_DSP (void);
+
+char array[100];
+int little_endian;
+
+int main ()
+{
+  int i;
+
+  union { long long ll; int i[2]; } endianness_test;
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  for (i = 0; i < 100; i++)
+    array[i] = i;
+
+  test_MIPS_DSP ();
+
+  exit (0);
+}
+
+NOMIPS16 v2q15 add_v2q15 (v2q15 a, v2q15 b)
+{
+  return __builtin_mips_addq_ph (a, b);
+}
+
+NOMIPS16 v4i8 add_v4i8 (v4i8 a, v4i8 b)
+{
+  return __builtin_mips_addu_qb (a, b);
+}
+
+NOMIPS16 v2q15 sub_v2q15 (v2q15 a, v2q15 b)
+{
+  return __builtin_mips_subq_ph (a, b);
+}
+
+NOMIPS16 v4i8 sub_v4i8 (v4i8 a, v4i8 b)
+{
+  return __builtin_mips_subu_qb (a, b);
+}
+
+NOMIPS16 void test_MIPS_DSP ()
+{
+  v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s;
+  v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s;
+  q31 q31_a,q31_b,q31_c,q31_r,q31_s;
+  i32 i32_a,i32_b,i32_c,i32_r,i32_s;
+  a64 a64_a,a64_b,a64_c,a64_r,a64_s;
+
+  void *ptr_a;
+  int r,s;
+  long long lr,ls;
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x81bd, 0x6789};
+  v2q15_r = add_v2q15 (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x7fff, 0x6789};
+  v2q15_r = __builtin_mips_addq_s_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_b = 0x71234567;
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_addq_s_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0xf1, 0xbd, 0x67, 0x89};
+  v4i8_r = add_v4i8 (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0xff, 0xbd, 0x67, 0x89};
+  v4i8_r = __builtin_mips_addu_s_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0xa2ab, 0x4567};
+  v2q15_r = sub_v2q15 (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x8000, 0x4567};
+  v2q15_r = __builtin_mips_subq_s_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_b = 0x71234567;
+  q31_s = 0xfedcba99;
+  q31_r = __builtin_mips_subq_s_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0xf3, 0xab, 0x45, 0x67};
+  v4i8_r = sub_v4i8 (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0x0, 0x0, 0x45, 0x67};
+  v4i8_r = __builtin_mips_subu_s_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0xf5678900;
+  i32_b = 0x7abcdef0;
+  i32_s = 0x702467f0;
+  i32_r = __builtin_mips_addsc (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x75678900;
+  i32_b = 0x7abcdef0;
+  i32_s = 0xf02467f1;
+  i32_r = __builtin_mips_addwc (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0;
+  i32_b = 0x00000901;
+  i32_s = 9;
+  i32_r = __builtin_mips_modsub (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  i32_s = 0x1f4;
+  i32_r = __builtin_mips_raddu_w_qb (v4i8_a);
+  if (i32_r != i32_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x8134};
+  v2q15_s = (v2q15) {0x7fff, 0x7ecc};
+  v2q15_r = __builtin_mips_absq_s_ph (v2q15_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = (q31) 0x80000000;
+  q31_s = (q31) 0x7fffffff;
+  q31_r = __builtin_mips_absq_s_w (q31_a);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x9999, 0x5612};
+  v2q15_b = (v2q15) {0x5612, 0x3333};
+  if (little_endian)
+    v4i8_s = (v4i8) {0x56, 0x33, 0x99, 0x56};
+  else
+    v4i8_s = (v4i8) {0x99, 0x56, 0x56, 0x33};
+  v4i8_r = __builtin_mips_precrq_qb_ph (v2q15_a, v2q15_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x12348678;
+  q31_b = 0x44445555;
+  if (little_endian)
+    v2q15_s = (v2q15) {0x4444, 0x1234};
+  else
+    v2q15_s = (v2q15) {0x1234, 0x4444};
+  v2q15_r = __builtin_mips_precrq_ph_w (q31_a, q31_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x12348678;
+  q31_b = 0x44445555;
+  if (little_endian)
+    v2q15_s = (v2q15) {0x4444, 0x1235};
+  else
+    v2q15_s = (v2q15) {0x1235, 0x4444};
+  v2q15_r = __builtin_mips_precrq_rs_ph_w (q31_a, q31_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x9999, 0x5612};
+  v2q15_b = (v2q15) {0x5612, 0x3333};
+  if (little_endian)
+    v4i8_s = (v4i8) {0xac, 0x66, 0x00, 0xac};
+  else
+    v4i8_s = (v4i8) {0x00, 0xac, 0xac, 0x66};
+  v4i8_r = __builtin_mips_precrqu_s_qb_ph (v2q15_a, v2q15_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3589, 0x4444};
+  if (little_endian)
+    q31_s = 0x44440000;
+  else
+    q31_s = 0x35890000;
+  q31_r = __builtin_mips_preceq_w_phl (v2q15_a);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3589, 0x4444};
+  if (little_endian)
+    q31_s = 0x35890000;
+  else
+    q31_s = 0x44440000;
+  q31_r = __builtin_mips_preceq_w_phr (v2q15_a);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  else
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  v2q15_r = __builtin_mips_precequ_ph_qbl (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  else
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  v2q15_r = __builtin_mips_precequ_ph_qbr (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  else
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  v2q15_r = __builtin_mips_precequ_ph_qbla (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  else
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  v2q15_r = __builtin_mips_precequ_ph_qbra (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x56, 0x33};
+  else
+    v2q15_s = (v2q15) {0x12, 0x56};
+  v2q15_r = __builtin_mips_preceu_ph_qbl (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x12, 0x56};
+  else
+    v2q15_s = (v2q15) {0x56, 0x33};
+  v2q15_r = __builtin_mips_preceu_ph_qbr (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x99, 0x33};
+  else
+    v2q15_s = (v2q15) {0x12, 0x56};
+  v2q15_r = __builtin_mips_preceu_ph_qbla (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x12, 0x56};
+  else
+    v2q15_s = (v2q15) {0x99, 0x33};
+  v2q15_r = __builtin_mips_preceu_ph_qbra (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_s = (v4i8) {0xc8, 0xd0, 0x58, 0xe0};
+  v4i8_r = __builtin_mips_shll_qb (v4i8_a, 2);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  i32_b = 1;
+  v4i8_s = (v4i8) {0xe4, 0x68, 0xac, 0xf0};
+  v4i8_r = __builtin_mips_shll_qb (v4i8_a, i32_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d0, 0x59e0};
+  v2q15_r = __builtin_mips_shll_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 1;
+  v2q15_s = (v2q15) {0x2468, 0xacf0};
+  v2q15_r = __builtin_mips_shll_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d0, 0x7fff};
+  v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 1;
+  v2q15_s = (v2q15) {0x2468, 0x7fff};
+  v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_shll_s_w (q31_a, 2);
+  if (q31_r != q31_s)
+    abort ();
+
+  q31_a = 0x70000000;
+  i32_b = 1;
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_shll_s_w (q31_a, i32_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_s = (v4i8) {0x3c, 0xd, 0x15, 0x1e};
+  v4i8_r = __builtin_mips_shrl_qb (v4i8_a, 2);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  i32_b = 1;
+  v4i8_s = (v4i8) {0x79, 0x1a, 0x2b, 0x3c};
+  v4i8_r = __builtin_mips_shrl_qb (v4i8_a, i32_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d, 0x159e};
+  v2q15_r = __builtin_mips_shra_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 1;
+  v2q15_s = (v2q15) {0x91a, 0x2b3c};
+  v2q15_r = __builtin_mips_shra_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d, 0x159e};
+  v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 3;
+  v2q15_s = (v2q15) {0x247, 0xacf};
+  v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_s = 0x1c000000;
+  q31_r = __builtin_mips_shra_r_w (q31_a, 2);
+  if (q31_r != q31_s)
+    abort ();
+
+  q31_a = 0x70000004;
+  i32_b = 3;
+  q31_s = 0x0e000001;
+  q31_r = __builtin_mips_shra_r_w (q31_a, i32_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  if (little_endian)
+    v2q15_s = (v2q15) {0xffff, 0x4444};
+  else
+    v2q15_s = (v2q15) {0x6f89, 0x2222};
+  v2q15_r = __builtin_mips_muleu_s_ph_qbl (v4i8_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x6f89, 0x2222};
+  else
+    v2q15_s = (v2q15) {0xffff, 0x4444};
+  v2q15_r = __builtin_mips_muleu_s_ph_qbr (v4i8_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x0fdd, 0x0b87};
+  v2q15_r = __builtin_mips_mulq_rs_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x8000};
+  v2q15_b = (v2q15) {0x8000, 0x8000};
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_muleq_s_w_phl (v2q15_a, v2q15_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x8000};
+  v2q15_b = (v2q15) {0x8000, 0x8000};
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_muleq_s_w_phr (v2q15_a, v2q15_b);
+  if (q31_r != q31_s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x22222f27;
+  else
+    a64_s = 0x222238d9;
+  a64_r = __builtin_mips_dpau_h_qbl (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x222238d9;
+  else
+    a64_s = 0x22222f27;
+  a64_r = __builtin_mips_dpau_h_qbr (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x2221f2fb;
+  else
+    a64_s = 0x2221e949;
+  a64_r = __builtin_mips_dpsu_h_qbl (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x2221e949;
+  else
+    a64_s = 0x2221f2fb;
+  a64_r = __builtin_mips_dpsu_h_qbr (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x5678};
+  v2q15_c = (v2q15) {0x8000, 0x1111};
+  a64_s = 0x8b877d00;
+  a64_r = __builtin_mips_dpaq_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x5678};
+  v2q15_c = (v2q15) {0x8000, 0x1111};
+  a64_s = 0xffffffff7478a522LL;
+  a64_r = __builtin_mips_dpsq_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x5678};
+  v2q15_c = (v2q15) {0x8000, 0x1111};
+  if (little_endian)
+    a64_s = 0xffffffff8b877d02LL;
+  else
+    a64_s = 0x7478a520;
+  a64_r = __builtin_mips_mulsaq_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  q31_b = 0x80000000;
+  q31_c = 0x80000000;
+  a64_s = 0x7fffffffffffffffLL;
+  a64_r = __builtin_mips_dpaq_sa_l_w (a64_a, q31_b, q31_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  q31_b = 0x80000000;
+  q31_c = 0x80000000;
+  a64_s = 0x8000000000001112LL;
+  a64_r = __builtin_mips_dpsq_sa_l_w (a64_a, q31_b, q31_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x1115;
+  else
+    a64_s = 0x80001110;
+  a64_r = __builtin_mips_maq_s_w_phl (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x80001110;
+  else
+    a64_s = 0x1115;
+  a64_r = __builtin_mips_maq_s_w_phr (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x1115;
+  else
+    a64_s = 0x7fffffff;
+  a64_r = __builtin_mips_maq_sa_w_phl (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x7fffffff;
+  else
+    a64_s = 0x1115;
+  a64_r = __builtin_mips_maq_sa_w_phr (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+  i32_a = 0x12345678;
+  i32_s = 0x00001e6a;
+  i32_r = __builtin_mips_bitrev (i32_a);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x00000208; // pos is 8, size is 4
+  __builtin_mips_wrdsp (i32_a, 31);
+  i32_a = 0x12345678;
+  i32_b = 0x87654321;
+  i32_s = 0x12345178;
+  i32_r = __builtin_mips_insv (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_s = (v4i8) {1, 1, 1, 1};
+  v4i8_r = __builtin_mips_repl_qb (1);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 99;
+  v4i8_s = (v4i8) {99, 99, 99, 99};
+  v4i8_r = __builtin_mips_repl_qb (i32_a);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_s = (v2q15) {30, 30};
+  v2q15_r = __builtin_mips_repl_ph (30);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x5612;
+  v2q15_s = (v2q15) {0x5612, 0x5612};
+  v2q15_r = __builtin_mips_repl_ph (i32_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x03000000;
+  else
+    i32_s = 0x0c000000;
+  __builtin_mips_cmpu_eq_qb (v4i8_a, v4i8_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x04000000;
+  else
+    i32_s = 0x02000000;
+  __builtin_mips_cmpu_lt_qb (v4i8_a, v4i8_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x07000000;
+  else
+    i32_s = 0x0e000000;
+  __builtin_mips_cmpu_le_qb (v4i8_a, v4i8_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x3;
+  else
+    i32_s = 0xc;
+  i32_r=__builtin_mips_cmpgu_eq_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x4;
+  else
+    i32_s = 0x2;
+  i32_r = __builtin_mips_cmpgu_lt_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x7;
+  else
+    i32_s = 0xe;
+  i32_r = __builtin_mips_cmpgu_le_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  __builtin_mips_wrdsp (0,31); // Clear all condition code bits.
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  if (little_endian)
+    i32_s = 0x01000000;
+  else
+    i32_s = 0x02000000;
+  __builtin_mips_cmp_eq_ph (v2q15_a, v2q15_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  if (little_endian)
+    i32_s = 0x02000000;
+  else
+    i32_s = 0x01000000;
+  __builtin_mips_cmp_lt_ph (v2q15_a, v2q15_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  i32_s = 0x03000000;
+  __builtin_mips_cmp_le_ph (v2q15_a, v2q15_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0a000000; // cc: 0000 1010
+  __builtin_mips_wrdsp (i32_a, 31);
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x21, 0x43, 0x65, 0x87};
+  if (little_endian)
+    v4i8_s = (v4i8) {0x21, 0x34, 0x65, 0x78};
+  else
+    v4i8_s = (v4i8) {0x12, 0x43, 0x56, 0x87};
+  v4i8_r = __builtin_mips_pick_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x02000000; // cc: 0000 0010
+  __builtin_mips_wrdsp (i32_a, 31);
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x2143, 0x6587};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x2143, 0x5678};
+  else
+    v2q15_s = (v2q15) {0x1234, 0x6587};
+  v2q15_r = __builtin_mips_pick_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x7856, 0x1234};
+  else
+    v2q15_s = (v2q15) {0x5678, 0x1234};
+  v2q15_r = __builtin_mips_packrl_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x1234567887654321LL;
+  i32_s = 0x88765432;
+  i32_r = __builtin_mips_extr_w (a64_a, 4);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887658321LL;
+  i32_s = 0x56788766;
+  i32_r = __builtin_mips_extr_r_w (a64_a, 16);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x12345677fffffff8LL;
+  i32_s = 0x7fffffff;
+  i32_r = __builtin_mips_extr_rs_w (a64_a, 4);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887658321LL;
+  i32_s = 0x7fff;
+  i32_r = __builtin_mips_extr_s_h (a64_a, 16);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x0000007887658321LL;
+  i32_b = 24;
+  i32_s = 0x7887;
+  i32_r = __builtin_mips_extr_s_h (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887654321LL;
+  i32_b = 4;
+  i32_s = 0x88765432;
+  i32_r = __builtin_mips_extr_w (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887658321LL;
+  i32_b = 16;
+  i32_s = 0x56788766;
+  i32_r = __builtin_mips_extr_r_w (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x12345677fffffff8LL;
+  i32_b = 4;
+  i32_s = 0x7fffffff;
+  i32_r = __builtin_mips_extr_rs_w (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_s = 8;
+  i32_r = __builtin_mips_extp (a64_a, 3); // extract 4 bits
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_b = 7; // size is 8. NOTE!! we should use 7
+  i32_s = 0x87;
+  i32_r = __builtin_mips_extp (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_s = 8;
+  i32_r = __builtin_mips_extpdp (a64_a, 3); // extract 4 bits
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_s = 0x0000021b; // pos is 27
+  i32_r = __builtin_mips_rddsp (31);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_b = 11; // size is 12. NOTE!!! We should use 11
+  i32_s = 0x876;
+  i32_r = __builtin_mips_extpdp (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_s = 0x00000213; // pos is 19
+  i32_r = __builtin_mips_rddsp (31);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887654321LL;
+  a64_s = 0x0012345678876543LL;
+  a64_r = __builtin_mips_shilo (a64_a, 8);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x1234567887654321LL;
+  i32_b = -16;
+  a64_s = 0x5678876543210000LL;
+  a64_r = __builtin_mips_shilo (a64_a, i32_b);
+  if (a64_r != a64_s)
+    abort ();
+
+  i32_a = 0x0;
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_b = 0x11112222;
+  a64_s = 0x8765432111112222LL;
+  a64_r = __builtin_mips_mthlip (a64_a, i32_b);
+  if (a64_r != a64_s)
+    abort ();
+  i32_s = 32;
+  i32_r = __builtin_mips_rddsp (31);
+  if (i32_r != i32_s)
+    abort ();
+#endif
+
+  i32_a = 0x1357a468;
+  __builtin_mips_wrdsp (i32_a, 63);
+  i32_s = 0x03572428;
+  i32_r = __builtin_mips_rddsp (63);
+  if (i32_r != i32_s)
+    abort ();
+
+  ptr_a = &array;
+  i32_b = 37;
+  i32_s = 37;
+  i32_r = __builtin_mips_lbux (ptr_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  ptr_a = &array;
+  i32_b = 38;
+  if (little_endian)
+    i32_s = 0x2726;
+  else
+    i32_s = 0x2627;
+  i32_r = __builtin_mips_lhx (ptr_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  ptr_a = &array;
+  i32_b = 40;
+  if (little_endian)
+    i32_s = 0x2b2a2928;
+  else
+    i32_s = 0x28292a2b;
+  i32_r = __builtin_mips_lwx (ptr_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x00000220; // pos is 32, size is 4
+  __builtin_mips_wrdsp (i32_a, 63);
+  i32_s = 1;
+  i32_r = __builtin_mips_bposge32 ();
+  if (i32_r != i32_s)
+    abort ();
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32-dspr2-type.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32-dspr2-type.c
new file mode 100644
index 000000000..9501e9cbe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32-dspr2-type.c
@@ -0,0 +1,12 @@
+/* Test MIPS32 DSP REV 2 instructions */
+/* { dg-do compile } */
+/* { dg-options "-mdspr2" } */
+/* { dg-final { scan-assembler "\tmul.ph\t" } } */
+
+typedef short v2hi __attribute__ ((vector_size(4)));
+
+NOMIPS16 v2hi mul_v2hi (v2hi a, v2hi b)
+{
+  return a * b;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32-dspr2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32-dspr2.c
new file mode 100644
index 000000000..1b3031ff1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32-dspr2.c
@@ -0,0 +1,541 @@
+/* Test MIPS32 DSP REV 2 instructions */
+/* { dg-do run } */
+/* { dg-options "-mdspr2 -O2" } */
+
+typedef signed char v4q7 __attribute__ ((vector_size(4)));
+typedef signed char v4i8 __attribute__ ((vector_size(4)));
+typedef short v2q15 __attribute__ ((vector_size(4)));
+typedef short v2i16 __attribute__ ((vector_size(4)));
+typedef int q31;
+typedef int i32;
+typedef unsigned int ui32;
+typedef long long a64;
+
+void abort (void);
+
+NOMIPS16 void test_MIPS_DSPR2 (void);
+
+int little_endian;
+
+int main ()
+{
+  union { long long ll; int i[2]; } endianness_test;
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  test_MIPS_DSPR2 ();
+
+  return 0;
+}
+
+NOMIPS16 void test_MIPS_DSPR2 ()
+{
+  v4q7 v4q7_a,v4q7_b,v4q7_c,v4q7_r,v4q7_s;
+  v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s;
+  v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s;
+  v2i16 v2i16_a,v2i16_b,v2i16_c,v2i16_r,v2i16_s;
+  q31 q31_a,q31_b,q31_c,q31_r,q31_s;
+  i32 i32_a,i32_b,i32_c,i32_r,i32_s;
+  ui32 ui32_a,ui32_b,ui32_c,ui32_r,ui32_s;
+  a64 a64_a,a64_b,a64_c,a64_r,a64_s;
+
+  int r,s;
+
+  v4q7_a = (v4i8) {0x81, 0xff, 0x80, 0x23};
+  v4q7_s = (v4i8) {0x7f, 0x01, 0x7f, 0x23};
+  v4q7_r = __builtin_mips_absq_s_qb (v4q7_a);
+  r = (int) v4q7_r;
+  s = (int) v4q7_s;
+  if (r != s)
+    abort ();
+
+  v2i16_a = (v2i16) {0xffff, 0x2468};
+  v2i16_b = (v2i16) {0x1234, 0x1111};
+  v2i16_s = (v2i16) {0x1233, 0x3579};
+  v2i16_r = __builtin_mips_addu_ph (v2i16_a, v2i16_b);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  v2i16_a = (v2i16) {0xffff, 0x2468};
+  v2i16_b = (v2i16) {0x1234, 0x1111};
+  v2i16_s = (v2i16) {0xffff, 0x3579};
+  v2i16_r = __builtin_mips_addu_s_ph (v2i16_a, v2i16_b);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0xff};
+  v4i8_b = (v4i8) {0x11, 0x33, 0x99, 0xff};
+  v4i8_s = (v4i8) {0x11, 0x2a, 0x66, 0xff};
+  v4i8_r = __builtin_mips_adduh_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0xff};
+  v4i8_b = (v4i8) {0x11, 0x33, 0x99, 0xff};
+  v4i8_s = (v4i8) {0x11, 0x2b, 0x66, 0xff};
+  v4i8_r = __builtin_mips_adduh_r_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x12345678;
+  i32_b = 0x87654321;
+  i32_s = 0x56784321;
+  i32_r = __builtin_mips_append (i32_a, i32_b, 16);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x12345678;
+  i32_b = 0x87654321;
+  i32_s = 0x78876543;
+  i32_r = __builtin_mips_balign (i32_a, i32_b, 3);
+  if (i32_r != i32_s)
+    abort ();
+
+  __builtin_mips_wrdsp (0, 63);
+  v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x44};
+  v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};
+  if (little_endian)
+    i32_s = 0xd;
+  else
+    i32_s = 0xb;
+  i32_r = __builtin_mips_cmpgdu_eq_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+  i32_r = __builtin_mips_rddsp (16);
+  if (little_endian)
+    i32_s = 0x0d000000;
+  else
+    i32_s = 0x0b000000;
+  if (i32_r != i32_s)
+    abort ();
+
+  __builtin_mips_wrdsp (0, 63);
+  v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x44};
+  v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};
+  if (little_endian)
+    i32_s = 0x2;
+  else
+    i32_s = 0x4;
+  i32_r = __builtin_mips_cmpgdu_lt_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+  i32_r = __builtin_mips_rddsp (16);
+  if (little_endian)
+    i32_s = 0x02000000;
+  else
+    i32_s = 0x04000000;
+  if (i32_r != i32_s)
+    abort ();
+
+  __builtin_mips_wrdsp (0, 63);
+  v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x54};
+  v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};
+  if (little_endian)
+    i32_s = 0x7;
+  else
+    i32_s = 0xe;
+  i32_r = __builtin_mips_cmpgdu_le_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+  i32_r = __builtin_mips_rddsp (16);
+  if (little_endian)
+    i32_s = 0x07000000;
+  else
+    i32_s = 0x0e000000;
+  if (i32_r != i32_s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  v2i16_b = (v2i16) {0xffff, 0x1555};
+  v2i16_c = (v2i16) {0x1234, 0x3322};
+  a64_s = 0x1677088e;
+  a64_r = __builtin_mips_dpa_w_ph (a64_a, v2i16_b, v2i16_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  v2i16_b = (v2i16) {0xffff, 0x1555};
+  v2i16_c = (v2i16) {0x1234, 0x3322};
+  a64_s = 0x0df1a462;
+  a64_r = __builtin_mips_dps_w_ph (a64_a, v2i16_b, v2i16_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  i32_b = 0x80000000;
+  i32_c = 0x11112222;
+  a64_s = 0xF7776EEF12345678LL;
+  a64_r = __builtin_mips_madd (a64_a, i32_b, i32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  ui32_b = 0x80000000;
+  ui32_c = 0x11112222;
+  a64_s = 0x0888911112345678LL;
+  a64_r = __builtin_mips_maddu (a64_a, ui32_b, ui32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  i32_b = 0x80000000;
+  i32_c = 0x11112222;
+  a64_s = 0x0888911112345678LL;
+  a64_r = __builtin_mips_msub (a64_a, i32_b, i32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  ui32_b = 0x80000000;
+  ui32_c = 0x11112222;
+  a64_s = 0xF7776EEF12345678LL;
+  a64_r = __builtin_mips_msubu (a64_a, ui32_b, ui32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+  v2i16_a = (v2i16) {0xffff, 0x2468};
+  v2i16_b = (v2i16) {0x1234, 0x1111};
+  v2i16_s = (v2i16) {0xedcc, 0x52e8};
+  v2i16_r = __builtin_mips_mul_ph (v2i16_a, v2i16_b);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  v2i16_a = (v2i16) {0x8000, 0x7fff};
+  v2i16_b = (v2i16) {0x1234, 0x1111};
+  v2i16_s = (v2i16) {0x8000, 0x7fff};
+  v2i16_r = __builtin_mips_mul_s_ph (v2i16_a, v2i16_b);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x80000000;
+  q31_b = 0x80000000; 
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_mulq_rs_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0xffff, 0x8000};
+  v2q15_b = (v2q15) {0x1111, 0x8000};
+  v2q15_s = (v2q15) {0xffff, 0x7fff};
+  v2q15_r = __builtin_mips_mulq_s_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x00000002;
+  q31_b = 0x80000000; 
+  q31_s = 0xfffffffe;
+  q31_r = __builtin_mips_mulq_s_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x19848419;
+  v2i16_b = (v2i16) {0xffff, 0x8000};
+  v2i16_c = (v2i16) {0x1111, 0x8000};
+  if (little_endian)
+    a64_s = 0x5984952a;
+  else
+    a64_s = 0xffffffffd9847308LL;
+  a64_r = __builtin_mips_mulsa_w_ph (a64_a, v2i16_b, v2i16_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  i32_a = 0x80000000;
+  i32_b = 0x11112222;
+  a64_s = 0xF7776EEF00000000LL;
+  a64_r = __builtin_mips_mult (i32_a, i32_b);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  ui32_a = 0x80000000;
+  ui32_b = 0x11112222;
+  a64_s = 0x888911100000000LL;
+  a64_r = __builtin_mips_multu (ui32_a, ui32_b);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+  v2i16_a = (v2i16) {0x1234, 0x5678};
+  v2i16_b = (v2i16) {0x2233, 0x5566};
+  if (little_endian)
+    v4i8_s = (v4i8) {0x33, 0x66, 0x34, 0x78};
+  else
+    v4i8_s = (v4i8) {0x34, 0x78, 0x33, 0x66};
+  v4i8_r = __builtin_mips_precr_qb_ph (v2i16_a, v2i16_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x12345678;
+  i32_b = 0x33334444;
+  if (little_endian)
+    v2i16_s = (v2i16) {0x3444, 0x4567};
+  else
+    v2i16_s = (v2i16) {0x4567, 0x3444};
+  v2i16_r = __builtin_mips_precr_sra_ph_w (i32_a, i32_b, 4);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x12345678;
+  i32_b = 0x33334444;
+  if (little_endian)
+    v2i16_s = (v2i16) {0x3444, 0x4568};
+  else
+    v2i16_s = (v2i16) {0x4568, 0x3444};
+  v2i16_r = __builtin_mips_precr_sra_r_ph_w (i32_a, i32_b, 4);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x12345678;
+  i32_b = 0x87654321;
+  i32_s = 0x43211234;
+  i32_r = __builtin_mips_prepend (i32_a, i32_b, 16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
+  v4i8_s = (v4i8) {0x9, 0x22, 0x3b, 0xcc};
+  v4i8_r = __builtin_mips_shra_qb (v4i8_a, 1);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
+  v4i8_s = (v4i8) {0x9, 0x23, 0x3c, 0xcd};
+  v4i8_r = __builtin_mips_shra_r_qb (v4i8_a, 1);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_b = 1;  
+  v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
+  v4i8_s = (v4i8) {0x9, 0x22, 0x3b, 0xcc};
+  v4i8_r = __builtin_mips_shra_qb (v4i8_a, i32_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_b = 1;  
+  v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
+  v4i8_s = (v4i8) {0x9, 0x23, 0x3c, 0xcd};
+  v4i8_r = __builtin_mips_shra_r_qb (v4i8_a, i32_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2i16_a = (v2i16) {0x1357, 0x2468};
+  v2i16_s = (v2i16) {0x0135, 0x0246};
+  v2i16_r = __builtin_mips_shrl_ph (v2i16_a, 4);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  i32_b = 8;
+  v2i16_a = (v2i16) {0x1357, 0x2468};
+  v2i16_s = (v2i16) {0x0013, 0x0024};
+  v2i16_r = __builtin_mips_shrl_ph (v2i16_a, i32_b);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  v2i16_a = (v2i16) {0x1357, 0x4455};
+  v2i16_b = (v2i16) {0x3333, 0x4444};
+  v2i16_s = (v2i16) {0xe024, 0x0011};
+  v2i16_r = __builtin_mips_subu_ph (v2i16_a, v2i16_b);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  v2i16_a = (v2i16) {0x1357, 0x4455};
+  v2i16_b = (v2i16) {0x3333, 0x4444};
+  v2i16_s = (v2i16) {0x0000, 0x0011};
+  v2i16_r = __builtin_mips_subu_s_ph (v2i16_a, v2i16_b);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x33 ,0x44, 0x55, 0x66};
+  v4i8_b = (v4i8) {0x99 ,0x15, 0x85, 0xff};
+  v4i8_s = (v4i8) {0xcd ,0x17, 0xe8, 0xb3};
+  v4i8_r = __builtin_mips_subuh_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x33 ,0x44, 0x55, 0x66};
+  v4i8_b = (v4i8) {0x99 ,0x15, 0x85, 0xff};
+  v4i8_s = (v4i8) {0xcd ,0x18, 0xe8, 0xb4};
+  v4i8_r = __builtin_mips_subuh_r_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3334, 0x4444};
+  v2q15_b = (v2q15) {0x1111, 0x2222};
+  v2q15_s = (v2q15) {0x2222, 0x3333};
+  v2q15_r = __builtin_mips_addqh_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3334, 0x4444};
+  v2q15_b = (v2q15) {0x1111, 0x2222};
+  v2q15_s = (v2q15) {0x2223, 0x3333};
+  v2q15_r = __builtin_mips_addqh_r_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x11111112;
+  q31_b = 0x99999999;
+  q31_s = 0xd5555555;
+  q31_r = __builtin_mips_addqh_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  q31_a = 0x11111112;
+  q31_b = 0x99999999;
+  q31_s = 0xd5555556;
+  q31_r = __builtin_mips_addqh_r_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3334, 0x4444};
+  v2q15_b = (v2q15) {0x1111, 0x2222};
+  v2q15_s = (v2q15) {0x1111, 0x1111};
+  v2q15_r = __builtin_mips_subqh_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3334, 0x4444};
+  v2q15_b = (v2q15) {0x1111, 0x2222};
+  v2q15_s = (v2q15) {0x1112, 0x1111};
+  v2q15_r = __builtin_mips_subqh_r_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x11111112;
+  q31_b = 0x99999999;
+  q31_s = 0x3bbbbbbc;
+  q31_r = __builtin_mips_subqh_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  q31_a = 0x11111112;
+  q31_b = 0x99999999;
+  q31_s = 0x3bbbbbbd;
+  q31_r = __builtin_mips_subqh_r_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x1111222212345678LL;
+  v2i16_b = (v2i16) {0x1, 0x2};
+  v2i16_c = (v2i16) {0x3, 0x4};
+  a64_s = 0x1111222212345682LL;
+  a64_r = __builtin_mips_dpax_w_ph (a64_a, v2i16_b, v2i16_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x9999111112345678LL;
+  v2i16_b = (v2i16) {0x1, 0x2};
+  v2i16_c = (v2i16) {0x3, 0x4};
+  a64_s = 0x999911111234566eLL;
+  a64_r = __builtin_mips_dpsx_w_ph (a64_a, v2i16_b, v2i16_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x70000000;
+  v2q15_b = (v2q15) {0x4000, 0x2000};
+  v2q15_c = (v2q15) {0x2000, 0x4000};
+  a64_s = 0x98000000;
+  a64_r = __builtin_mips_dpaqx_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x70000000;
+  v2q15_b = (v2q15) {0x4000, 0x2000};
+  v2q15_c = (v2q15) {0x2000, 0x4000};
+  a64_s = 0x7fffffff;
+  a64_r = __builtin_mips_dpaqx_sa_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x70000000;
+  v2q15_b = (v2q15) {0x4000, 0x2000};
+  v2q15_c = (v2q15) {0x2000, 0x4000};
+  a64_s = 0x48000000;
+  a64_r = __builtin_mips_dpsqx_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0xFFFFFFFF80000000LL;
+  v2q15_b = (v2q15) {0x4000, 0x2000};
+  v2q15_c = (v2q15) {0x2000, 0x4000};
+  a64_s = 0xFFFFFFFF80000000LL;
+  a64_r = __builtin_mips_dpsqx_sa_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32r2-mxhc1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32r2-mxhc1.c
new file mode 100644
index 000000000..cf57323db
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/mips32r2-mxhc1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mabi=32 -mfp64" } */
+/* { dg-final { scan-assembler "mthc1" } } */
+/* { dg-final { scan-assembler "mfhc1" } } */
+
+NOMIPS16 double func1 (long long a)
+{
+  return a;
+}
+
+NOMIPS16 long long func2 (double b)
+{
+  return b;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/movcc-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/movcc-1.c
new file mode 100644
index 000000000..1a930c9ac
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/movcc-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 isa>=4" } */
+/* { dg-final { scan-assembler "movz" } } */
+/* { dg-final { scan-assembler "movn" } } */
+
+void ext_int (int);
+
+NOMIPS16 int
+sub1 (int i, int j, int k)
+{
+  ext_int (k ? i : j);
+}
+
+NOMIPS16 int
+sub2 (int i, int j, long l)
+{
+  ext_int (!l ? i : j);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/movcc-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/movcc-2.c
new file mode 100644
index 000000000..d42acc1d7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/movcc-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 isa>=4" } */
+/* { dg-final { scan-assembler "movz" } } */
+/* { dg-final { scan-assembler "movn" } } */
+
+void ext_long (long);
+
+NOMIPS16 long
+sub4 (long i, long j, long k)
+{
+  ext_long (k ? i : j);
+}
+
+NOMIPS16 long
+sub5 (long i, long j, int k)
+{
+  ext_long (!k ? i : j);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/movcc-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/movcc-3.c
new file mode 100644
index 000000000..e6481777a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/movcc-3.c
@@ -0,0 +1,63 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 isa>=4 -mhard-float" } */
+/* { dg-final { scan-assembler "movt" } } */
+/* { dg-final { scan-assembler "movf" } } */
+/* { dg-final { scan-assembler "movz.s" } } */
+/* { dg-final { scan-assembler "movn.s" } } */
+/* { dg-final { scan-assembler "movt.s" } } */
+/* { dg-final { scan-assembler "movz.d" } } */
+/* { dg-final { scan-assembler "movn.d" } } */
+/* { dg-final { scan-assembler "movf.d" } } */
+
+void ext_int (int);
+void ext_long (long);
+void ext_float (float);
+void ext_double (double);
+
+NOMIPS16 int
+sub3 (int i, int j, float f)
+{
+  ext_int (f ? i : j);
+}
+
+NOMIPS16 long
+sub6 (long i, long j, float f)
+{
+  ext_long (!f ? i : j);
+}
+
+NOMIPS16 float
+sub7 (float f, float g, int i)
+{
+  ext_float (i ? f : g);
+}
+
+NOMIPS16 float
+sub8 (float f, float g, long l)
+{
+  ext_float (!l ? f : g);
+}
+
+NOMIPS16 float
+sub9 (float f, float g, float h)
+{
+  ext_float (h ? f : g);
+}
+
+NOMIPS16 double
+suba (double f, double g, int i)
+{
+  ext_double (i ? f : g);
+}
+
+NOMIPS16 double
+subb (double f, double g, long l)
+{
+  ext_double (!l ? f : g);
+}
+
+NOMIPS16 double
+subc (double f, double g, double h)
+{
+  ext_double (!h ? f : g);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-1.c
new file mode 100644
index 000000000..803ea77df
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=vr5400 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmsac\t\\\$0," 2 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return z - (long long) y * x;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-2.c
new file mode 100644
index 000000000..e6cdc2c1a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=vr5500 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmsub\t" 2 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return z - (long long) y * x;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-3.c
new file mode 100644
index 000000000..c44f34f4f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 isa_rev>=1 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmsub\t" 2 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return z - (long long) y * x;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-4.c
new file mode 100644
index 000000000..d41c31299
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdspr2 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmsub\t\\\$ac" 2 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return z - (long long) y * x;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-5.c
new file mode 100644
index 000000000..dcb124a71
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-5.c
@@ -0,0 +1,8 @@
+/* { dg-options "-O2 -march=5kc" } */
+/* { dg-final { scan-assembler-times "\tmsub\t" 4 } } */
+/* { dg-final { scan-assembler-not "\tmtlo\t" } } */
+/* { dg-final { scan-assembler-times "\tmflo\t" 3 } } */
+
+NOMIPS16 void f1 (int *a) { a[0] = a[0] * a[1] - a[2] * a[3]; }
+NOMIPS16 void f2 (int *a) { a[0] = a[0] * a[1] - a[2] * a[3] - a[4]; }
+NOMIPS16 void f3 (int *a) { a[0] = a[0] * a[1] - a[2] * a[3] - a[4] * a[5]; }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-6.c
new file mode 100644
index 000000000..ee4ca3d8d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-6.c
@@ -0,0 +1,6 @@
+/* { dg-options "-O2 -march=5kc" } */
+/* { dg-final { scan-assembler-not "\tmsub\t" } } */
+/* { dg-final { scan-assembler "\tmul\t" } } */
+/* { dg-final { scan-assembler "\tsubu\t" } } */
+
+NOMIPS16 void f1 (int *a) { a[0] = a[0] - a[1] * a[2]; }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-7.c
new file mode 100644
index 000000000..ca90cee9e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-7.c
@@ -0,0 +1,15 @@
+/* -mlong32 added because of PR target/38598.  */
+/* { dg-options "-O2 -march=5kc -mlong32" } */
+/* { dg-final { scan-assembler-not "\tmul\t" } } */
+/* { dg-final { scan-assembler "\tmsub\t" } } */
+
+NOMIPS16 int
+f1 (int *a, int *b, int n)
+{
+  int x, i;
+
+  x = 100;
+  for (i = 0; i < n; i++)
+    x -= a[i] * b[i];
+  return x;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-8.c
new file mode 100644
index 000000000..49d67f24a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msub-8.c
@@ -0,0 +1,15 @@
+/* { dg-options "-O2 -march=5kc" } */
+/* { dg-final { scan-assembler "\tmul\t" } } */
+/* { dg-final { scan-assembler-not "\tmsub\t" } } */
+/* { dg-final { scan-assembler-not "\tmtlo\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+
+NOMIPS16 int
+f2 (int x, int y, int z)
+{
+  asm volatile ("" ::: "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9",
+		"$10", "$11", "$12", "$13", "$14", "$15", "$16", "$17",
+		"$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25",
+		"$31");
+  return x - y * z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msubu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msubu-1.c
new file mode 100644
index 000000000..ae8040346
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msubu-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=vr5400 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmsacu\t\\\$0," 2 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return z - (ull) y * x;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msubu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msubu-2.c
new file mode 100644
index 000000000..186dc47d6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msubu-2.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=vr5500 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmsubu\t" 2 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return z - (ull) y * x;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msubu-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msubu-3.c
new file mode 100644
index 000000000..272c64818
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msubu-3.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 isa_rev>=1 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmsubu\t" 2 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return z - (ull) y * x;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msubu-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msubu-4.c
new file mode 100644
index 000000000..8f5fd647b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/msubu-4.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdspr2 -mgp32" } */
+/* { dg-final { scan-assembler-times "\tmsubu\t\\\$ac" 2 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return z - (ull) y * x;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/near-far-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/near-far-1.c
new file mode 100644
index 000000000..ac0cc1ef7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/near-far-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-mlong-calls addressing=absolute" } */
+
+extern int long_call_func () __attribute__((long_call));
+extern int far_func () __attribute__((far));
+extern int near_func () __attribute__((near));
+extern int normal_func ();
+
+int test ()
+{
+  return (long_call_func ()
+          + far_func ()
+          + near_func ()
+          + normal_func ());
+}
+
+/* { dg-final { scan-assembler-not "\tjal\tlong_call_func\n" } } */
+/* { dg-final { scan-assembler-not "\tjal\tfar_func\n" } } */
+/* { dg-final { scan-assembler     "\tjal\tnear_func\n" } } */
+/* { dg-final { scan-assembler-not "\tjal\tnormal_func\n" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/near-far-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/near-far-2.c
new file mode 100644
index 000000000..c954b444c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/near-far-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-long-calls addressing=absolute" } */
+
+extern int long_call_func () __attribute__((long_call));
+extern int far_func () __attribute__((far));
+extern int near_func () __attribute__((near));
+extern int normal_func ();
+
+int test ()
+{
+  return (long_call_func ()
+          + far_func ()
+          + near_func ()
+          + normal_func ());
+}
+
+/* { dg-final { scan-assembler-not "\tjal\tlong_call_func\n" } } */
+/* { dg-final { scan-assembler-not "\tjal\tfar_func\n" } } */
+/* { dg-final { scan-assembler     "\tjal\tnear_func\n" } } */
+/* { dg-final { scan-assembler     "\tjal\tnormal_func\n" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/near-far-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/near-far-3.c
new file mode 100644
index 000000000..f4ae791f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/near-far-3.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mlong-calls addressing=absolute -O2" } */
+
+NOMIPS16 extern int long_call_func () __attribute__((long_call));
+NOMIPS16 extern int far_func () __attribute__((far));
+NOMIPS16 extern int near_func () __attribute__((near));
+NOMIPS16 extern int normal_func ();
+
+NOMIPS16 int test1 () { return long_call_func (); }
+NOMIPS16 int test2 () { return far_func (); }
+NOMIPS16 int test3 () { return near_func (); }
+NOMIPS16 int test4 () { return normal_func (); }
+
+/* { dg-final { scan-assembler-not "\tj\tlong_call_func\n" } } */
+/* { dg-final { scan-assembler-not "\tj\tfar_func\n" } } */
+/* { dg-final { scan-assembler     "\tj\tnear_func\n" } } */
+/* { dg-final { scan-assembler-not "\tj\tnormal_func\n" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/near-far-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/near-far-4.c
new file mode 100644
index 000000000..b9aa21fe4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/near-far-4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-long-calls addressing=absolute -O2" } */
+
+NOMIPS16 extern int long_call_func () __attribute__((long_call));
+NOMIPS16 extern int far_func () __attribute__((far));
+NOMIPS16 extern int near_func () __attribute__((near));
+NOMIPS16 extern int normal_func ();
+
+NOMIPS16 int test1 () { return long_call_func (); }
+NOMIPS16 int test2 () { return far_func (); }
+NOMIPS16 int test3 () { return near_func (); }
+NOMIPS16 int test4 () { return normal_func (); }
+
+/* { dg-final { scan-assembler-not "\tj\tlong_call_func\n" } } */
+/* { dg-final { scan-assembler-not "\tj\tfar_func\n" } } */
+/* { dg-final { scan-assembler     "\tj\tnear_func\n" } } */
+/* { dg-final { scan-assembler     "\tj\tnormal_func\n" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/neg-abs-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/neg-abs-1.c
new file mode 100644
index 000000000..20691ff2c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/neg-abs-1.c
@@ -0,0 +1,13 @@
+/* Make sure that we use abs.fmt and neg.fmt when the signs of NaNs don't
+   matter.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mhard-float -ffinite-math-only" } */
+/* { dg-final { scan-assembler "neg.s" } } */
+/* { dg-final { scan-assembler "neg.d" } } */
+/* { dg-final { scan-assembler "abs.s" } } */
+/* { dg-final { scan-assembler "abs.d" } } */
+
+NOMIPS16 float f1 (float f) { return -f; }
+NOMIPS16 float f2 (float f) { return __builtin_fabsf (f); }
+NOMIPS16 double d1 (double d) { return -d; }
+NOMIPS16 double d2 (double d) { return __builtin_fabs (d); }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/neg-abs-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/neg-abs-2.c
new file mode 100644
index 000000000..67125f78a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/neg-abs-2.c
@@ -0,0 +1,13 @@
+/* Make sure that we avoid abs.fmt and neg.fmt when the signs of NaNs
+   matter.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mhard-float -fno-finite-math-only" } */
+/* { dg-final { scan-assembler-not "neg.s" } } */
+/* { dg-final { scan-assembler-not "neg.d" } } */
+/* { dg-final { scan-assembler-not "abs.s" } } */
+/* { dg-final { scan-assembler-not "abs.d" } } */
+
+float f1 (float f) { return -f; }
+float f2 (float f) { return __builtin_fabsf (f); }
+double d1 (double d) { return -d; }
+double d2 (double d) { return __builtin_fabs (d); }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/nmadd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/nmadd-1.c
new file mode 100644
index 000000000..123d48799
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/nmadd-1.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math isa=4 -mhard-float" } */
+/* { dg-final { scan-assembler "nmadd.s" } } */
+/* { dg-final { scan-assembler "nmadd.d" } } */
+/* { dg-final { scan-assembler "nmsub.s" } } */
+/* { dg-final { scan-assembler "nmsub.d" } } */
+
+NOMIPS16 float
+sub1 (float f, float g, float h)
+{
+  return -((f * g) + h);
+}
+
+NOMIPS16 double
+sub2 (double f, double g, double h)
+{
+  return -((f * g) + h);
+}
+
+NOMIPS16 float
+sub3 (float f, float g, float h)
+{
+  return -((f * g) - h);
+}
+
+NOMIPS16 double
+sub4 (double f, double g, double h)
+{
+  return -((f * g) - h);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/nmadd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/nmadd-2.c
new file mode 100644
index 000000000..90e4d838d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/nmadd-2.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-fast-math -ffinite-math-only isa=4 -mhard-float" } */
+/* { dg-final { scan-assembler "nmadd.s" } } */
+/* { dg-final { scan-assembler "nmadd.d" } } */
+/* { dg-final { scan-assembler "nmsub.s" } } */
+/* { dg-final { scan-assembler "nmsub.d" } } */
+
+NOMIPS16 float
+sub1 (float f, float g, float h)
+{
+  return -((f * g) + h);
+}
+
+NOMIPS16 double
+sub2 (double f, double g, double h)
+{
+  return -((f * g) + h);
+}
+
+NOMIPS16 float
+sub3 (float f, float g, float h)
+{
+  return -((f * g) - h);
+}
+
+NOMIPS16 double
+sub4 (double f, double g, double h)
+{
+  return -((f * g) - h);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/nmadd-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/nmadd-3.c
new file mode 100644
index 000000000..df7261861
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/nmadd-3.c
@@ -0,0 +1,32 @@
+/* The same code as nmadd-2.c, but compiled with -fno-finite-math-only.
+   We can't use nmadd and nmsub in that case.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-fast-math -fno-finite-math-only isa=4 -mhard-float" } */
+/* { dg-final { scan-assembler-not "nmadd.s" } } */
+/* { dg-final { scan-assembler-not "nmadd.d" } } */
+/* { dg-final { scan-assembler-not "nmsub.s" } } */
+/* { dg-final { scan-assembler-not "nmsub.d" } } */
+
+float
+sub1 (float f, float g, float h)
+{
+  return -((f * g) + h);
+}
+
+double
+sub2 (double f, double g, double h)
+{
+  return -((f * g) + h);
+}
+
+float
+sub3 (float f, float g, float h)
+{
+  return -((f * g) - h);
+}
+
+double
+sub4 (double f, double g, double h)
+{
+  return -((f * g) - h);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/no-smartmips-lwxs.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/no-smartmips-lwxs.c
new file mode 100644
index 000000000..ee7f3d54d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/no-smartmips-lwxs.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mno-smartmips" } */
+
+NOMIPS16 int scaled_indexed_word_load (int a[], int b)
+{
+  return a[b];
+}
+/* { dg-final { scan-assembler-not "\tlwxs\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/no-smartmips-ror-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/no-smartmips-ror-1.c
new file mode 100644
index 000000000..d1f50a8fb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/no-smartmips-ror-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mno-smartmips -march=mips32" } */
+
+NOMIPS16 int rotate_left (unsigned a, unsigned s)
+{
+  return (a << s) | (a >> (32 - s));
+}
+/* { dg-final { scan-assembler-not "\tror\t" } } */
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-baddu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-baddu-1.c
new file mode 100644
index 000000000..8dd5be167
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-baddu-1.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O -march=octeon" } */
+/* { dg-final { scan-assembler-times "\tbaddu\t" 4 } } */
+/* { dg-final { scan-assembler-not "\tandi\t" } } */
+
+NOMIPS16 unsigned char
+g (long long a, long long b)
+{
+  return a + b;
+}
+
+NOMIPS16 unsigned long long
+h (unsigned long long a, unsigned long long b)
+{
+  unsigned char c = a + b;
+  return c;
+}
+
+NOMIPS16 long long
+ff (long long a, long long b)
+{
+  unsigned char c = a + b;
+  return c;
+}
+
+NOMIPS16 int
+gg (int a, int b)
+{
+  return (a + b) & 0xff;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-bbit-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-bbit-1.c
new file mode 100644
index 000000000..6629dbb58
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-bbit-1.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=octeon" } */
+/* { dg-final { scan-assembler-times "\tbbit1\t" 4 } } */
+/* { dg-final { scan-assembler-times "\tbbit0\t" 2 } } */
+/* { dg-final { scan-assembler-not "andi\t" } } */
+
+NOMIPS16 void foo (void);
+
+NOMIPS16 void
+f1 (long long i)
+{
+  if (i & 0x80)
+    foo ();
+}
+
+NOMIPS16 void
+f2 (int i)
+{
+  if (!(i & 0x80))
+    foo ();
+}
+
+NOMIPS16 void
+f3 (int i)
+{
+  if (i % 2)
+    foo ();
+}
+
+NOMIPS16 void
+f4 (int i)
+{
+  if (i & 1)
+    foo ();
+}
+
+NOMIPS16 void
+f5 (long long i)
+{
+  if ((i >> 3) & 1)
+    foo ();
+}
+
+unsigned long long r;
+
+NOMIPS16 static inline __attribute__((always_inline)) int
+test_bit(unsigned long long nr, const unsigned long long *addr)
+{
+  return 1UL & (addr[nr >> 6] >> (nr & 63ULL));
+}
+
+NOMIPS16 void
+f6 ()
+{
+  if (!test_bit(0, &r))
+    foo ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-bbit-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-bbit-2.c
new file mode 100644
index 000000000..55bf23eae
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-bbit-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=octeon -mbranch-likely" } */
+/* { dg-final { scan-assembler "\tbbit\[01\]\t" } } */
+/* { dg-final { scan-assembler-not "\tbbit\[01\]l\t" } } */
+/* { dg-final { scan-assembler "\tbnel\t" } } */
+/* { dg-final { scan-assembler-not "\tbne\t" } } */
+
+NOMIPS16 int
+f (int n, int i)
+{
+  int s = 0;
+  for (; i & 1; i++)
+    s += i;
+  return s;
+}
+
+NOMIPS16 int
+g (int n, int i)
+{
+  int s = 0;
+  for (i = 0; i < n; i++)
+    s += i;
+  return s;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-bbit-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-bbit-3.c
new file mode 100644
index 000000000..bcc37d29e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-bbit-3.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+
+/* Force big-endian because for little-endian, combine generates this:
+
+ (if_then_else (ne (zero_extract:DI (subreg:DI (truncate:SI (reg:DI 196)) 0) 
+                 (const_int 1) 
+                 (const_int 0)) 
+             (const_int 0)) 
+         (label_ref 20) 
+         (pc))) 
+
+  which does not get recognized as a valid bbit pattern.  The
+  middle-end should be able to simplify this further.  */
+/* { dg-options "-O2 -march=octeon -meb" } */
+
+/* { dg-final { scan-assembler-times "\tbbit\[01\]\t|\tbgez\t" 2 } } */
+/* { dg-final { scan-assembler-not "ext\t" } } */
+
+void abort (void);
+void exit (int);
+
+typedef unsigned long long ulong64;
+
+typedef struct bitfield_s {
+  ulong64 a:1;
+  ulong64 b:29;
+  ulong64 c:1;
+  ulong64 d:15;
+  ulong64 f:18;
+} bitfield_t;
+
+bitfield_t bar;
+
+NOMIPS16 void
+f ()
+{
+  foo(&bar);
+  if (bar.a != 0x1)
+    abort ();
+  else if (!bar.c)
+    abort ();
+  else
+    exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-cins-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-cins-1.c
new file mode 100644
index 000000000..ac85e2378
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-cins-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* The tests also work with -mgp32.  For long long tests, only one of
+   the 32-bit parts is used.  */
+/* { dg-options "-O -march=octeon" } */
+/* { dg-final { scan-assembler-times "\tcins\t" 3 } } */
+/* { dg-final { scan-assembler-not "\tandi\t|sll\t" } } */
+
+NOMIPS16 long long
+f (long long i)
+{
+  return (i & 0xff) << 34;
+}
+
+NOMIPS16 int
+g (int i)
+{
+  return (i << 4) & 0xff0;
+}
+
+NOMIPS16 long long
+h (long long i)
+{
+  return (i << 4) & 0xfff;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-cins-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-cins-2.c
new file mode 100644
index 000000000..2dcff0aad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-cins-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O -march=octeon -mgp64" } */
+/* { dg-final { scan-assembler-not "\tcins\t" } } */
+
+NOMIPS16 unsigned
+f (unsigned i)
+{
+  return (i & 0xff) << 24;
+}
+
+NOMIPS16 unsigned long long
+g (unsigned long long i)
+{
+  return (i & 0x1ffffffffULL) << 4;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-dmul-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-dmul-1.c
new file mode 100644
index 000000000..b8b8c1bc3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-dmul-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -mgp64" } */
+/* { dg-final { scan-assembler "\tdmul\t" } } */
+/* { dg-final { scan-assembler-not "\tdmult\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+
+NOMIPS16 long long
+f (long long a, long long b)
+{
+  return a * b;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-dmul-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-dmul-2.c
new file mode 100644
index 000000000..6b2308c0b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-dmul-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -mgp64" } */
+/* { dg-final { scan-assembler-not "\tdmul" } } */
+
+NOMIPS16 long long
+f (long long a)
+{
+  return a * 7;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-exts-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-exts-1.c
new file mode 100644
index 000000000..b0f4be143
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-exts-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon" } */
+/* { dg-final { scan-assembler "\texts\t" } } */
+
+struct foo
+{
+  long long a:3;
+  long long b:23;
+  long long c:38;
+};
+
+NOMIPS16 int
+f (struct foo s)
+{
+  return s.b;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-exts-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-exts-2.c
new file mode 100644
index 000000000..fc5df639d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-exts-2.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-O -march=octeon -meb" } */
+/* { dg-final { scan-assembler-times "\texts\t" 4 } } */
+
+struct bar
+{
+  unsigned long long a:1;
+  long long b:14;
+  unsigned long long c:48;
+  long long d:1;
+};
+
+NOMIPS16 int
+f1 (struct bar *s, int a)
+{
+  return (int) s->b + a;
+}
+
+NOMIPS16 char
+f2 (struct bar *s)
+{
+  return s->d + 1;
+}
+
+NOMIPS16 int
+f3 ()
+{
+  struct bar s;
+  asm ("" : "=r"(s));
+  return (int) s.b + 1;
+}
+
+NOMIPS16 long long
+f4 (struct bar *s)
+{
+  return s->d;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-exts-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-exts-3.c
new file mode 100644
index 000000000..9d0e9302a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-exts-3.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O -march=octeon -mgp64" } */
+/* { dg-final { scan-assembler-times "\texts\t" 3 } } */
+
+struct foo
+{
+  unsigned long long a:10;
+  unsigned long long b:32;
+  unsigned long long c:22;
+};
+
+NOMIPS16 unsigned
+f (struct foo s)
+{
+  return s.b;
+}
+
+struct bar
+{
+  unsigned long long a:15;
+  unsigned long long b:48;
+  unsigned long long c:1;
+};
+
+NOMIPS16 int
+g (struct bar s)
+{
+  return (int) s.b;
+}
+
+NOMIPS16 int
+h (int i)
+{
+  return (i << 4) >> 24;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-exts-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-exts-4.c
new file mode 100644
index 000000000..7e6a578a1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-exts-4.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O -march=octeon -mgp64" } */
+/* { dg-final { scan-assembler-not "\tsll\t\[^\n\]*,0" } } */
+/* { dg-final { scan-assembler-times "\texts\t" 6 } } */
+
+#define TEST(ID, TYPE, SHIFT)				\
+  int NOMIPS16						\
+  f##ID (long long y)					\
+  {							\
+    return (TYPE) ((TYPE) (y >> SHIFT) + 1);		\
+  }							\
+  int NOMIPS16						\
+  g##ID (unsigned long long y)				\
+  {							\
+    return (TYPE) ((TYPE) (y >> SHIFT) + 1);		\
+  }
+
+TEST (1, int, 10)
+TEST (2, short, 5)
+TEST (3, char, 31)
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-exts-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-exts-5.c
new file mode 100644
index 000000000..e7a4738b9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-exts-5.c
@@ -0,0 +1,38 @@
+/* -mel version of octeon-exts-2.c.  */
+/* { dg-do compile } */
+/* { dg-options "-O -march=octeon -mel" } */
+/* { dg-final { scan-assembler-times "\texts\t" 4 } } */
+
+struct bar
+{
+  long long d:1;
+  unsigned long long c:48;
+  long long b:14;
+  unsigned long long a:1;
+};
+
+NOMIPS16 int
+f1 (struct bar *s, int a)
+{
+  return (int) s->b + a;
+}
+
+NOMIPS16 char
+f2 (struct bar *s)
+{
+  return s->d + 1;
+}
+
+NOMIPS16 int
+f3 ()
+{
+  struct bar s;
+  asm ("" : "=r"(s));
+  return (int) s.b + 1;
+}
+
+NOMIPS16 long long
+f4 (struct bar *s)
+{
+  return s->d;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-pop-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-pop-1.c
new file mode 100644
index 000000000..54d2e9c04
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-pop-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O -march=octeon -mgp64" } */
+/* { dg-final { scan-assembler "\tpop\t" } } */
+/* { dg-final { scan-assembler "\tdpop\t" } } */
+
+NOMIPS16 int
+f (long long a)
+{
+  return __builtin_popcountll (a);
+}
+
+NOMIPS16 int
+g (int a)
+{
+  return __builtin_popcount (a);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-seq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-seq-1.c
new file mode 100644
index 000000000..c07660a2e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-seq-1.c
@@ -0,0 +1,19 @@
+/* Check if we expand seq and sne.  */
+
+/* { dg-do compile } */
+/* { dg-options "-march=octeon" } */
+/* { dg-final { scan-assembler-times "\tseq\t|\tseqi\t" 4 } } */
+/* { dg-final { scan-assembler-times "\tsne\t|\tsnei\t" 4 } } */
+
+#define TEST(N, LHS, REL, RHS) \
+  NOMIPS16 int f##N (int a, int b) { return LHS REL RHS; }
+
+TEST (0, a, ==, b);
+TEST (1, a, ==, 23);
+TEST (2, a, ==, 511);
+TEST (3, a, ==, -200);
+
+TEST (10, a, !=, b);
+TEST (11, a, !=, 1);
+TEST (12, a, !=, 350);
+TEST (13, a, !=, -512);
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-seq-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-seq-2.c
new file mode 100644
index 000000000..83e068c54
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-seq-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -mgp64" } */
+/* { dg-final { scan-assembler-times "\tseq\t|\tseqi\t" 3 } } */
+/* { dg-final { scan-assembler-times "\tsne\t|\tsnei\t" 3 } } */
+
+#define TEST(N, LHS, REL, RHS) \
+  NOMIPS16 long long f##N (long long a, long long b) { return LHS REL RHS; }
+
+TEST (0, a, ==, b);
+TEST (1, a, ==, 23);
+TEST (2, a, ==, 511);
+
+TEST (3, a, !=, b);
+TEST (4, a, !=, 1);
+TEST (5, a, !=, 350);
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-seq-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-seq-3.c
new file mode 100644
index 000000000..899f14584
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-seq-3.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O -march=octeon -mgp64" } */
+
+/* { dg-final { scan-assembler-not "and\t\|andi\t\|ext\t\|sll\t\|srl\t" } } */
+/* { dg-final { scan-assembler-times "\tseqi\t\|\tsnei\t" 4 } } */
+
+
+#define TEST(N, LHS, REL, RHS) \
+  NOMIPS16 long long w##N (int a, int b) {return LHS REL RHS;} \
+  NOMIPS16 int n##N (long long a, long long b) {return LHS REL RHS;} \
+
+TEST (eq, a, ==, 10);
+TEST (ne, a, !=, 32);
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-seq-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-seq-4.c
new file mode 100644
index 000000000..e61bcb361
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/octeon-seq-4.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=octeon" } */
+/* { dg-final { scan-assembler-not "xor" } } */
+
+unsigned
+m (unsigned e);
+
+NOMIPS16 void
+f (unsigned i)
+{
+  unsigned j = m (i);
+  h (j, i != j);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr26765.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr26765.c
new file mode 100644
index 000000000..25c2e8d4c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr26765.c
@@ -0,0 +1,13 @@
+/* PR target/pr26765
+   This testcase used to trigger an unrecognizable insn.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -w" } */
+
+__thread int *a = 0;
+
+NOMIPS16 void foo (void)
+{
+  extern int *b;
+  b = (int *) ((*a));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr33256.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr33256.c
new file mode 100644
index 000000000..ead5888cc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr33256.c
@@ -0,0 +1,11 @@
+/* GCC used to report an ICE for this test because we generated a LO_SUM
+   for an illegitimate constant.  */
+/* { dg-options "-mabi=64 -msym32 -O2 -EB -mno-abicalls" } */
+extern unsigned long a[];
+int b (int);
+
+int
+c (void)
+{
+  return b (a[0]);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr33635-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr33635-1.c
new file mode 100644
index 000000000..78e761f71
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr33635-1.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mabi=64 -O2" } */
+
+NOMIPS16 long double __powitf2 (long double x, int m)
+{
+  long double y = x;
+  while (m >>= 1)
+    {
+      x = x * x;
+      if (m % 2)
+        y = y * x;
+    }
+  return y;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr33755.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr33755.c
new file mode 100644
index 000000000..ca6a1e698
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr33755.c
@@ -0,0 +1,30 @@
+/* { dg-do link } */
+/* { dg-options "-O2" } */
+
+volatile int gv;
+const char *ptrs[2];
+
+void
+foo (volatile int *v, const char **ptrs)
+{
+  switch (*v & 1)
+    {
+    case 0:
+      ptrs[0] = 0;
+      break;
+    case 1:
+      break;
+    default:
+      ptrs[1] = "Some text";
+      break;
+    }
+  while (*v > 0)
+    *v -= 1;
+}
+
+int
+main (void)
+{
+  foo (&gv, ptrs);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr34831.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr34831.c
new file mode 100644
index 000000000..2da436f71
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr34831.c
@@ -0,0 +1,7 @@
+/* { dg-options "-ffast-math -mips64 -mgp32" } */
+
+double
+foo (void)
+{
+  return __builtin_pow (0.0, -1.5);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr35802.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr35802.c
new file mode 100644
index 000000000..9ecc4d06e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr35802.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O2 -march=74kc -mgp32" } */
+__thread int x __attribute__((tls_model("initial-exec")));
+__thread int y __attribute__((tls_model("initial-exec")));
+
+int bar (void);
+
+NOMIPS16 void
+foo (int n)
+{
+  if (n > 5)
+    {
+      y = 0;
+      do
+	x += bar ();
+      while (n--);
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr37362.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr37362.c
new file mode 100644
index 000000000..14e3a75f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/pr37362.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=mips64r2 -mabi=n32" } */
+
+typedef float TFtype __attribute__((mode(TF)));
+
+TFtype
+__powitf (TFtype x, int m)
+{
+  unsigned int n = m < 0 ? -m : m;
+  TFtype y = n % 2 ? x : 1;
+  while (n >>= 1)
+    {
+      x = x * x;
+      if (n % 2)
+	y = y * x;
+    }
+  return m < 0 ? 1/y : y;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-1.c
new file mode 100644
index 000000000..b271e2bf4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-1.c
@@ -0,0 +1,45 @@
+/* { dg-options "-O2 -mabi=64 -mr10k-cache-barrier=store" } */
+
+/* Test that stores to uncached addresses do not get unnecessary
+   cache barriers.  */
+
+#define TEST(ADDR)					\
+  NOMIPS16 void						\
+  test_##ADDR (int n)					\
+  {							\
+    while (n--)						\
+      {							\
+	*(volatile char *) (0x##ADDR##UL) = 1;		\
+	*(volatile short *) (0x##ADDR##UL + 2) = 2;	\
+	*(volatile int *) (0x##ADDR##UL + 4) = 0;	\
+      }							\
+  }
+
+TEST (9000000000000000)
+TEST (900000fffffffff8)
+
+TEST (9200000000000000)
+TEST (920000fffffffff8)
+
+TEST (9400000000000000)
+TEST (940000fffffffff8)
+
+TEST (9600000000000000)
+TEST (960000fffffffff8)
+
+TEST (b800000000000000)
+TEST (b80000fffffffff8)
+
+TEST (ba00000000000000)
+TEST (ba0000fffffffff8)
+
+TEST (bc00000000000000)
+TEST (bc0000fffffffff8)
+
+TEST (be00000000000000)
+TEST (be0000fffffffff8)
+
+TEST (ffffffffa0000000)
+TEST (ffffffffbffffff8)
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c
new file mode 100644
index 000000000..68c4b7ef2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c
@@ -0,0 +1,18 @@
+/* { dg-options "-O2 -mr10k-cache-barrier=store -mips4 -mbranch-likely -mno-abicalls" } */
+int bar (int);
+
+/* Test that code after a branch-likely does not get an unnecessary
+   cache barrier.  */
+
+NOMIPS16 void
+foo (int n, int *x)
+{
+  do
+    n = bar (n * 4 + 1);
+  while (n);
+  /* The preceding branch should be a branch likely, with the shift as
+     its delay slot.  We therefore don't need a cache barrier here.  */
+  x[0] = 0;
+}
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-11.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-11.c
new file mode 100644
index 000000000..d1082d910
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-11.c
@@ -0,0 +1,13 @@
+/* { dg-options "-O2 -mr10k-cache-barrier=store -mno-abicalls" } */
+
+/* Test that loads are not unnecessarily protected.  */
+
+int bar (int);
+
+NOMIPS16 void
+foo (int *ptr)
+{
+  *ptr = bar (*ptr);
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 1 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-12.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-12.c
new file mode 100644
index 000000000..d41639109
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-12.c
@@ -0,0 +1,13 @@
+/* { dg-options "-O2 -mr10k-cache-barrier=load-store -mno-abicalls" } */
+
+/* Test that loads are correctly protected.  */
+
+int bar (int);
+
+NOMIPS16 void
+foo (int *ptr)
+{
+  *ptr = bar (*ptr);
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 2 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-13.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-13.c
new file mode 100644
index 000000000..3e955abf5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-13.c
@@ -0,0 +1,14 @@
+/* { dg-options "-O2 -mr10k-cache-barrier=store" } */
+
+/* Test that indirect calls are protected.  */
+
+int bar (int);
+
+NOMIPS16 void
+foo (void (*fn) (void), int x)
+{
+  if (x)
+    (*fn) ();
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 1 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-14.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-14.c
new file mode 100644
index 000000000..1fdcee0e2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-14.c
@@ -0,0 +1,5 @@
+/* { dg-options "(-mips16) -O2 -mr10k-cache-barrier=store" } */
+
+/* Test that indirect calls are protected.  */
+
+MIPS16 void foo (void) { } /* { dg-message "sorry, unimplemented" } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-15.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-15.c
new file mode 100644
index 000000000..a3e7f0db9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-15.c
@@ -0,0 +1,2 @@
+/* { dg-options "-O2 -mr10k-cache-barrier=store -mips2" } */
+/* { dg-error "requires.*cache.*instruction" "" { target *-*-* } 0 } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-2.c
new file mode 100644
index 000000000..3d06d0ddb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-2.c
@@ -0,0 +1,40 @@
+/* { dg-options "-O2 -mabi=64 -mr10k-cache-barrier=store" } */
+
+/* Test that stores to constant cached addresses are protected
+   by cache barriers.  */
+
+#define TEST(ADDR)					\
+  NOMIPS16 void						\
+  test_##ADDR (int n)					\
+  {							\
+    *(volatile int *) (0x##ADDR##UL) = 1;		\
+  }
+
+TEST (8ffffffffffffffc)
+TEST (9000010000000000)
+
+TEST (91fffffffffffffc)
+TEST (9200010000000000)
+
+TEST (93fffffffffffffc)
+TEST (9500010000000000)
+
+TEST (95fffffffffffffc)
+TEST (9600010000000000)
+
+TEST (b7fffffffffffffc)
+TEST (b800010000000000)
+
+TEST (b9fffffffffffffc)
+TEST (ba00010000000000)
+
+TEST (bbfffffffffffffc)
+TEST (bc00010000000000)
+
+TEST (bdfffffffffffffc)
+TEST (be00010000000000)
+
+TEST (ffffffff9ffffffc)
+TEST (ffffffffc0000000)
+
+/* { dg-final { scan-assembler-times "\tcache\t" 18 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-3.c
new file mode 100644
index 000000000..be2c7fbd7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-3.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O2 -mr10k-cache-barrier=store -mno-abicalls" } */
+
+/* Test that in-range stores to the frame are not protected by
+   cache barriers.  */
+
+void bar (int *x);
+
+NOMIPS16 void
+foo (int v)
+{
+  int x[0x100000];
+  bar (x);
+  x[0x20] = v;
+  bar (x);
+}
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-4.c
new file mode 100644
index 000000000..9dd23eafa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-4.c
@@ -0,0 +1,20 @@
+/* { dg-options "-O2 -mr10k-cache-barrier=store -mno-abicalls" } */
+
+void bar (int *x);
+
+/* Test that out-of-range stores to the frame are protected by cache
+   barriers.  */
+
+NOMIPS16 void
+foo (int v)
+{
+  int x[8];
+  bar (x);
+  if (v & 1)
+    x[0x100] = 0;
+  if (v & 2)
+    x[-0x100] = 0;
+  bar (x);
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 2 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-5.c
new file mode 100644
index 000000000..a6b53a9ea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-5.c
@@ -0,0 +1,19 @@
+/* { dg-options "-O2 -mr10k-cache-barrier=store -mno-abicalls -mabi=64" } */
+
+/* Test that in-range stores to static objects do not get an unnecessary
+   cache barrier.  */
+
+int x[4];
+void bar (void);
+
+NOMIPS16 void
+foo (int n)
+{
+  while (n--)
+    {
+      x[3] = 1;
+      bar ();
+    }
+}
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-6.c
new file mode 100644
index 000000000..c52caaa1a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-6.c
@@ -0,0 +1,19 @@
+/* { dg-options "-O2 -mr10k-cache-barrier=store -mabi=64" } */
+
+int x[4];
+void bar (void);
+
+/* Test that out-of-range stores to static objects are protected by a
+   cache barrier.  */
+
+NOMIPS16 void
+foo (int n)
+{
+  while (n--)
+    {
+      x[4] = 1;
+      bar ();
+    }
+}
+
+/* { dg-final { scan-assembler "\tcache\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c
new file mode 100644
index 000000000..3f738654c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c
@@ -0,0 +1,27 @@
+/* { dg-options "-O2 -mr10k-cache-barrier=store -mno-abicalls" } */
+
+void bar1 (void);
+void bar2 (void);
+void bar3 (void);
+
+NOMIPS16 void
+foo (int *x, int sel, int n)
+{
+  if (sel)
+    {
+      bar1 ();
+      x[0] = 1;
+    }
+  else
+    {
+      bar2 ();
+      x[1] = 0;
+    }
+  /* If there is one copy of this code, reached by two unconditional edges,
+     then it shouldn't need a third cache barrier.  */
+  x[2] = 2;
+  while (n--)
+    bar3 ();
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 2 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-8.c
new file mode 100644
index 000000000..394bf486f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-8.c
@@ -0,0 +1,15 @@
+/* { dg-options "-O2 -mr10k-cache-barrier=store -G8" } */
+
+/* Test that in-range stores to components of static objects
+   do not get an unnecessary cache barrier.  */
+
+struct { struct { char i[4]; } a; struct { char j[4]; } b; } s;
+
+NOMIPS16 void
+foo (int sel)
+{
+  s.a.i[0] = 1;
+  s.b.j[3] = 100;
+}
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-9.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-9.c
new file mode 100644
index 000000000..67b52f92d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-9.c
@@ -0,0 +1,19 @@
+/* { dg-options "-O2 -mr10k-cache-barrier=store -G8" } */
+
+/* Test that out-of-range stores to components of static objects
+   are protected by a cache barrier.  */
+
+struct { struct { char i[4]; } a; struct { char j[4]; } b; } s;
+
+NOMIPS16 void
+foo (int sel1, int sel2, int sel3)
+{
+  if (sel1)
+    s.a.i[8] = 1;
+  if (sel2)
+    s.b.j[4] = 100;
+  if (sel3)
+    s.a.i[-1] = 0;
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 3 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r3900-mult.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r3900-mult.c
new file mode 100644
index 000000000..4dc2b003f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/r3900-mult.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=r3900" } */
+/* { dg-final { scan-assembler "\tmult\t\[^\n\]*,\[^\n\]*," } } */
+
+NOMIPS16 int
+f (int a, int b)
+{
+  return a * b;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/rsqrt-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/rsqrt-1.c
new file mode 100644
index 000000000..f0a9b3aed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/rsqrt-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math isa=4 -mhard-float -mgp64" } */
+/* { dg-final { scan-assembler "rsqrt.d" } } */
+/* { dg-final { scan-assembler "rsqrt.s" } } */
+
+extern double sqrt(double);
+extern float sqrtf(float);
+
+NOMIPS16 double foo(double x)
+{
+  return 1.0/sqrt(x);
+}
+
+NOMIPS16 float bar(float x)
+{
+  return 1.0f/sqrtf(x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/rsqrt-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/rsqrt-2.c
new file mode 100644
index 000000000..bc81039d5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/rsqrt-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math isa=4 -mhard-float -mgp64" } */
+/* { dg-final { scan-assembler "rsqrt.d" } } */
+/* { dg-final { scan-assembler "rsqrt.s" } } */
+
+extern double sqrt(double);
+extern float sqrtf(float);
+
+NOMIPS16 double foo(double x)
+{
+  return sqrt(1.0/x);
+}
+
+NOMIPS16 float bar(float x)
+{
+  return sqrtf(1.0f/x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/rsqrt-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/rsqrt-3.c
new file mode 100644
index 000000000..cfa771ef8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/rsqrt-3.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 isa=4 -mhard-float" } */
+/* { dg-final { scan-assembler-not "rsqrt.d" } } */
+/* { dg-final { scan-assembler-not "rsqrt.s" } } */
+
+extern double sqrt(double);
+extern float sqrtf(float);
+
+double foo(double x)
+{
+  return 1.0/sqrt(x);
+}
+
+double bar(double x)
+{
+  return sqrt(1.0/x);
+}
+
+float foof(float x)
+{
+  return 1.0f/sqrtf(x);
+}
+
+float barf(float x)
+{
+  return sqrtf(1.0f/x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/rsqrt-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/rsqrt-4.c
new file mode 100644
index 000000000..726c35403
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/rsqrt-4.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -mips64 -mhard-float -mgp32" } */
+/* { dg-final { scan-assembler-not "\trsqrt.d\t" } } */
+/* { dg-final { scan-assembler-times "\trsqrt.s\t" 2 } } */
+
+extern double sqrt(double);
+extern float sqrtf(float);
+
+NOMIPS16 double f1 (double x)
+{
+  return 1.0 / sqrt (x);
+}
+
+NOMIPS16 double f2 (double x)
+{
+  return sqrt (1.0 / x);
+}
+
+NOMIPS16 float f3 (float x)
+{
+  return 1.0f / sqrtf (x);
+}
+
+NOMIPS16 float f4 (float x)
+{
+  return sqrtf (1.0f / x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/save-restore-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/save-restore-1.c
new file mode 100644
index 000000000..f6a854ee9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/save-restore-1.c
@@ -0,0 +1,20 @@
+/* Check that we can use the save instruction to save varargs.  */
+/* { dg-options "(-mips16) isa_rev>=1 -mabi=32 -O2" } */
+
+#include <stdarg.h>
+
+int bar (int, va_list ap);
+
+MIPS16 int
+foo (int n, ...)
+{
+  va_list ap;
+  int i;
+
+  va_start (ap, n);
+  i = bar (n, ap);
+  va_end (ap);
+  return i + 1;
+}
+/* { dg-final { scan-assembler "\tsave\t\\\$4-\\\$7" } } */
+/* { dg-final { scan-assembler "\trestore\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/save-restore-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/save-restore-2.c
new file mode 100644
index 000000000..4a11bc210
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/save-restore-2.c
@@ -0,0 +1,15 @@
+/* Check that we can use the save instruction to save spilled arguments.  */
+/* { dg-options "(-mips16) isa_rev>=1 -mabi=32 -O2" } */
+
+MIPS16 void
+foo (int *a, int b, int c)
+{
+  asm volatile ("" ::: "$2", "$3", "$4", "$5", "$6", "$7", "$8",
+		"$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16",
+		"$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24",
+		"$25", "$30", "memory");
+  a[b] = 1;
+  a[c] = 1;
+}
+/* { dg-final { scan-assembler "\tsave\t\\\$4-\\\$6," } } */
+/* { dg-final { scan-assembler "\trestore\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/save-restore-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/save-restore-3.c
new file mode 100644
index 000000000..d45fe50ea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/save-restore-3.c
@@ -0,0 +1,20 @@
+/* Check that we can use the save instruction to save spilled arguments
+   when the argument save area is out of range of a direct load or store.  */
+/* { dg-options "(-mips16) isa_rev>=1 -mabi=32 -O2" } */
+
+void bar (int *);
+
+MIPS16 void
+foo (int *a, int b, int c)
+{
+  int x[0x4000];
+  asm volatile ("" ::: "$2", "$3", "$4", "$5", "$6", "$7", "$8",
+		"$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16",
+		"$18", "$19", "$20", "$21", "$22", "$23", "$24",
+		"$25", "$30", "memory");
+  bar (x);
+  a[b] = 1;
+  a[c] = 1;
+}
+/* { dg-final { scan-assembler "\tsave\t\\\$4-\\\$6," } } */
+/* { dg-final { scan-assembler "\trestore\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/save-restore-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/save-restore-4.c
new file mode 100644
index 000000000..ef7722bce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/save-restore-4.c
@@ -0,0 +1,13 @@
+/* Check that we can use the save instruction to save $16, $17 and $31.  */
+/* { dg-options "(-mips16) isa_rev>=1 -mabi=32 -O2" } */
+
+void bar (void);
+
+MIPS16 void
+foo (void)
+{
+  bar ();
+  asm volatile ("" ::: "$16", "$17");
+}
+/* { dg-final { scan-assembler "\tsave\t\[0-9\]*,\\\$16,\\\$17,\\\$31" } } */
+/* { dg-final { scan-assembler "\trestore\t\[0-9\]*,\\\$16,\\\$17,\\\$31" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/save-restore-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/save-restore-5.c
new file mode 100644
index 000000000..0dd823a68
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/save-restore-5.c
@@ -0,0 +1,15 @@
+/* Check that we don't try to save the same register twice.  */
+/* { dg-options "(-mips16) isa_rev>=1 -mgp32 -O2" } */
+
+int bar (int, int, int, int);
+void frob (void);
+
+MIPS16 void
+foo (int a1, int a2, int a3, int a4)
+{
+  asm volatile ("" ::: "$2", "$3", "$4", "$5", "$6", "$7", "$8",
+		"$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16",
+		"$18", "$19", "$20", "$21", "$22", "$23", "$24",
+		"$25", "$30", "$31", "memory");
+  __builtin_eh_return (bar (a1, a2, a3, a4), frob);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/sb1-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/sb1-1.c
new file mode 100644
index 000000000..819938fcd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/sb1-1.c
@@ -0,0 +1,29 @@
+/* Test SB-1 v2sf extensions.  */
+/* { dg-do compile } */ 
+/* { dg-options "-march=sb1 -O2 -mpaired-single -mgp64 -ffast-math" } */
+/* { dg-final { scan-assembler "div.ps" } } */ 
+/* { dg-final { scan-assembler "recip.ps" } } */ 
+/* { dg-final { scan-assembler "sqrt.ps" } } */ 
+/* { dg-final { scan-assembler "rsqrt.ps" } } */ 
+
+typedef float v2sf __attribute__ ((vector_size (8)));
+
+NOMIPS16 v2sf divide (v2sf a, v2sf b)
+{
+  return a / b;
+}
+
+NOMIPS16 v2sf recip (v2sf a)
+{
+  return ((v2sf) {1.0, 1.0}) / a;
+}
+
+NOMIPS16 v2sf squareroot (v2sf a)
+{
+  return __builtin_mips_sqrt_ps (a);
+}
+
+NOMIPS16 v2sf rsqrt (v2sf a)
+{
+  return ((v2sf) {1.0, 1.0}) / __builtin_mips_sqrt_ps (a);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/scc-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/scc-1.c
new file mode 100644
index 000000000..d0dc04015
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/scc-1.c
@@ -0,0 +1,34 @@
+/* { dg-options "(-mips16) -O isa_rev>=1" } */
+
+/* { dg-final { scan-assembler-times {slt	\$2,\$5,\$4} 1 } } */
+/* { dg-final { scan-assembler-times {sltu	\$2,\$5,\$4} 1 } } */
+/* { dg-final { scan-assembler-times {slt	\$5,\$4} 1 } } */
+/* { dg-final { scan-assembler-times {sltu	\$5,\$4} 1 } } */
+
+/* { dg-final { scan-assembler-times {slt	\$2,\$0,\$4} 1 } } */
+/* { dg-final { scan-assembler-times {sltu	\$2,\$0,\$4} 1 } } */
+
+/* { dg-final { scan-assembler-times {slt	\$2,\$4,\$5} 1 } } */
+/* { dg-final { scan-assembler-times {sltu	\$2,\$4,\$5} 1 } } */
+/* { dg-final { scan-assembler-times {slt	\$4,\$5} 1 } } */
+/* { dg-final { scan-assembler-times {sltu	\$4,\$5} 1 } } */
+
+/* { dg-final { scan-assembler-times {slt	\$2,\$4,23}  1 } } */
+/* { dg-final { scan-assembler-times {sltu	\$2,\$4,23}  1 } } */
+/* { dg-final { scan-assembler-times {slt	\$4,23}  1 } } */
+/* { dg-final { scan-assembler-times {sltu	\$4,23}  1 } } */
+
+#define TEST(N, LHS, REL, RHS) \
+  NOMIPS16 int s##N (int a, int b) { return LHS REL RHS; } \
+  NOMIPS16 int u##N (unsigned a, unsigned b) { return LHS REL RHS; } \
+  MIPS16 int s##N##_16 (int a, int b) { return LHS REL RHS; } \
+  MIPS16 int u##N##_16 (unsigned a, unsigned b) { return LHS REL RHS; }
+
+#define TEST_NO16(N, LHS, REL, RHS) \
+  NOMIPS16 int s##N (int a, int b) { return LHS REL RHS; } \
+  NOMIPS16 int u##N (unsigned a, unsigned b) { return LHS REL RHS; }
+
+TEST (1, a, >, b);
+TEST_NO16 (2, a, >=, 1);
+TEST (3, a, <, b);
+TEST (4, a, <=, 22);
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/scc-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/scc-2.c
new file mode 100644
index 000000000..440c28b84
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/scc-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mgp64" } */
+
+/* { dg-final { scan-assembler-not "and\t\|andi\t\|ext\t\|sll\t\|srl\t" } } */
+/* { dg-final { scan-assembler-times "slt\t\|slti?u\t" 12 } } */
+
+
+#define TEST(N, LHS, REL, RHS) \
+  NOMIPS16 long long w##N (int a, int b) {return LHS REL RHS;} \
+  NOMIPS16 int n##N (long long a, long long b) {return LHS REL RHS;} \
+
+TEST (eq, a, ==, 0);
+TEST (ne, a, !=, 0);
+TEST (gt, a, >, b);
+TEST (ge, a, >=, 1);
+TEST (lt, a, <, b);
+TEST (le, a, <=, 11);
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/scc-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/scc-3.c
new file mode 100644
index 000000000..b295e782c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/scc-3.c
@@ -0,0 +1,16 @@
+/* { dg-options "(-mips16) -O -mabi=o64" } */
+
+/* { dg-final { scan-assembler-not "and\t\|andi\t\|ext\t\|sll\t\|srl\t" } } */
+/* { dg-final { scan-assembler-times "slt\t\|slti?u\t" 8 } } */
+
+
+#define TEST(N, LHS, REL, RHS) \
+  MIPS16 long long w##N (int a, int b) {return LHS REL RHS;} \
+  MIPS16 int n##N (long long a, long long b) {return LHS REL RHS;} \
+
+TEST (eq, a, ==, 0);
+
+TEST (gt, a, >, b);
+
+TEST (lt, a, <, b);
+TEST (le, a, <=, 11);
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/scc-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/scc-4.c
new file mode 100644
index 000000000..40460666c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/scc-4.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mabi=o64" } */
+
+/* { dg-final { scan-assembler "slt\t" } } */
+/* { dg-final { scan-assembler "sltu\t\|xor\t\|xori\t" } } */
+
+/* This test should work both in mips16 and non-mips16 mode.  */
+
+int
+f (long long a, long long b)
+{
+  return a > 5;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/sdata-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/sdata-1.c
new file mode 100644
index 000000000..f9a25cdc9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/sdata-1.c
@@ -0,0 +1,61 @@
+/* { dg-options "-G4 -mexplicit-relocs" } */
+
+/* { dg-final { scan-assembler     "%gp_?rel\\(l4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l4c\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(c4\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4c\\)" } } */
+
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l8a\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l8b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l8c\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(e8a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e8b\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(c8\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(g8a\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(g8b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g8c\\)" } } */
+
+static int l4a;
+static int l4b = 1;
+static int __attribute__((section(".sdata"))) l4c;
+extern int e4a;
+extern int __attribute__((section(".sdata"))) e4b;
+int __attribute__((common)) c4;
+int __attribute__((nocommon)) g4a;
+int g4b = 1;
+int __attribute__((section(".sdata"))) g4c = 2;
+
+static int l8a[2];
+static int l8b[2] = { 1, 2 };
+static int __attribute__((section(".sdata"))) l8c[2];
+extern int e8a[2];
+extern int __attribute__((section(".sdata"))) e8b[2];
+int __attribute__((common)) c8[2];
+int __attribute__((nocommon)) g8a[2];
+int g8b[2] = { 1, 2 };
+int __attribute__((section(".sdata"))) g8c[2] = { 1, 2 };
+
+int f32a (void) { return l4a; }
+int f32b (void) { return l4b; }
+int f32c (void) { return l4c; }
+int f32d (void) { return e4a; }
+int f32e (void) { return e4b; }
+int f32f (void) { return c4; }
+int f32g (void) { return g4a; }
+int f32h (void) { return g4b; }
+int f32i (void) { return g4c; }
+
+int f64a (void) { return l8a[0]; }
+int f64b (void) { return l8b[0]; }
+int f64c (void) { return l8c[0]; }
+int f64d (void) { return e8a[0]; }
+int f64e (void) { return e8b[0]; }
+int f64f (void) { return c8[0]; }
+int f64g (void) { return g8a[0]; }
+int f64h (void) { return g8b[0]; }
+int f64i (void) { return g8c[0]; }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/sdata-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/sdata-2.c
new file mode 100644
index 000000000..5a9fff2da
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/sdata-2.c
@@ -0,0 +1,61 @@
+/* { dg-options "-G4 -mexplicit-relocs -mno-local-sdata" } */
+
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l4a\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l4c\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(c4\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4c\\)" } } */
+
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l8a\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l8b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l8c\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(e8a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e8b\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(c8\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(g8a\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(g8b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g8c\\)" } } */
+
+static int l4a;
+static int l4b = 1;
+static int __attribute__((section(".sdata"))) l4c;
+extern int e4a;
+extern int __attribute__((section(".sdata"))) e4b;
+int __attribute__((common)) c4;
+int __attribute__((nocommon)) g4a;
+int g4b = 1;
+int __attribute__((section(".sdata"))) g4c = 2;
+
+static int l8a[2];
+static int l8b[2] = { 1, 2 };
+static int __attribute__((section(".sdata"))) l8c[2];
+extern int e8a[2];
+extern int __attribute__((section(".sdata"))) e8b[2];
+int __attribute__((common)) c8[2];
+int __attribute__((nocommon)) g8a[2];
+int g8b[2] = { 1, 2 };
+int __attribute__((section(".sdata"))) g8c[2] = { 1, 2 };
+
+int f32a (void) { return l4a; }
+int f32b (void) { return l4b; }
+int f32c (void) { return l4c; }
+int f32d (void) { return e4a; }
+int f32e (void) { return e4b; }
+int f32f (void) { return c4; }
+int f32g (void) { return g4a; }
+int f32h (void) { return g4b; }
+int f32i (void) { return g4c; }
+
+int f64a (void) { return l8a[0]; }
+int f64b (void) { return l8b[0]; }
+int f64c (void) { return l8c[0]; }
+int f64d (void) { return e8a[0]; }
+int f64e (void) { return e8b[0]; }
+int f64f (void) { return c8[0]; }
+int f64g (void) { return g8a[0]; }
+int f64h (void) { return g8b[0]; }
+int f64i (void) { return g8c[0]; }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/sdata-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/sdata-3.c
new file mode 100644
index 000000000..f23232495
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/sdata-3.c
@@ -0,0 +1,61 @@
+/* { dg-options "-G4 -mexplicit-relocs -mno-extern-sdata" } */
+
+/* { dg-final { scan-assembler     "%gp_?rel\\(l4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l4c\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(e4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e4b\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(c4\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4c\\)" } } */
+
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l8a\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l8b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l8c\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(e8a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e8b\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(c8\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(g8a\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(g8b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g8c\\)" } } */
+
+static int l4a;
+static int l4b = 1;
+static int __attribute__((section(".sdata"))) l4c;
+extern int e4a;
+extern int __attribute__((section(".sdata"))) e4b;
+int __attribute__((common)) c4;
+int __attribute__((nocommon)) g4a;
+int g4b = 1;
+int __attribute__((section(".sdata"))) g4c = 2;
+
+static int l8a[2];
+static int l8b[2] = { 1, 2 };
+static int __attribute__((section(".sdata"))) l8c[2];
+extern int e8a[2];
+extern int __attribute__((section(".sdata"))) e8b[2];
+int __attribute__((common)) c8[2];
+int __attribute__((nocommon)) g8a[2];
+int g8b[2] = { 1, 2 };
+int __attribute__((section(".sdata"))) g8c[2] = { 1, 2 };
+
+int f32a (void) { return l4a; }
+int f32b (void) { return l4b; }
+int f32c (void) { return l4c; }
+int f32d (void) { return e4a; }
+int f32e (void) { return e4b; }
+int f32f (void) { return c4; }
+int f32g (void) { return g4a; }
+int f32h (void) { return g4b; }
+int f32i (void) { return g4c; }
+
+int f64a (void) { return l8a[0]; }
+int f64b (void) { return l8b[0]; }
+int f64c (void) { return l8c[0]; }
+int f64d (void) { return e8a[0]; }
+int f64e (void) { return e8b[0]; }
+int f64f (void) { return c8[0]; }
+int f64g (void) { return g8a[0]; }
+int f64h (void) { return g8b[0]; }
+int f64i (void) { return g8c[0]; }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/sdata-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/sdata-4.c
new file mode 100644
index 000000000..7786c6db9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/sdata-4.c
@@ -0,0 +1,44 @@
+/* { dg-options "-G4 -mexplicit-relocs -mno-gpopt" } */
+
+/* { dg-final { scan-assembler-not "%gp_?rel" } } */
+/* { dg-final { scan-assembler-not "\\\$gp" } } */
+
+static int l4a;
+static int l4b = 1;
+static int __attribute__((section(".sdata"))) l4c;
+extern int e4a;
+extern int __attribute__((section(".sdata"))) e4b;
+int __attribute__((common)) c4;
+int __attribute__((nocommon)) g4a;
+int g4b = 1;
+int __attribute__((section(".sdata"))) g4c = 2;
+
+static int l8a[2];
+static int l8b[2] = { 1, 2 };
+static int __attribute__((section(".sdata"))) l8c[2];
+extern int e8a[2];
+extern int __attribute__((section(".sdata"))) e8b[2];
+int __attribute__((common)) c8[2];
+int __attribute__((nocommon)) g8a[2];
+int g8b[2] = { 1, 2 };
+int __attribute__((section(".sdata"))) g8c[2] = { 1, 2 };
+
+int f32a (void) { return l4a; }
+int f32b (void) { return l4b; }
+int f32c (void) { return l4c; }
+int f32d (void) { return e4a; }
+int f32e (void) { return e4b; }
+int f32f (void) { return c4; }
+int f32g (void) { return g4a; }
+int f32h (void) { return g4b; }
+int f32i (void) { return g4c; }
+
+int f64a (void) { return l8a[0]; }
+int f64b (void) { return l8b[0]; }
+int f64c (void) { return l8c[0]; }
+int f64d (void) { return e8a[0]; }
+int f64e (void) { return e8b[0]; }
+int f64f (void) { return c8[0]; }
+int f64g (void) { return g8a[0]; }
+int f64h (void) { return g8b[0]; }
+int f64i (void) { return g8c[0]; }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/seq-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/seq-1.c
new file mode 100644
index 000000000..ae23608ce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/seq-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler-times "\tsltu\t|\tsltiu\t" 4 } } */
+
+#define TEST(N, LHS, REL, RHS) \
+  NOMIPS16 int f##N (int a, int b) { return LHS REL RHS; }
+
+TEST (0, a, ==, 0);
+TEST (1, a, ==, 600);
+TEST (10, a, !=, 0);
+TEST (11, a, !=, -800);
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/smartmips-lwxs.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/smartmips-lwxs.c
new file mode 100644
index 000000000..c6bc495c8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/smartmips-lwxs.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* -mlong32 added because of PR target/38599.  */
+/* { dg-options "-O -msmartmips -mlong32" } */
+
+NOMIPS16 int scaled_indexed_word_load (int a[], int b)
+{
+  return a[b];
+}
+/* { dg-final { scan-assembler "\tlwxs\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/smartmips-ror-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/smartmips-ror-1.c
new file mode 100644
index 000000000..e9735b20a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/smartmips-ror-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O -msmartmips" } */
+
+NOMIPS16 int rotate_left (unsigned a, unsigned s)
+{
+  return (a << s) | (a >> (32 - s));
+}
+/* { dg-final { scan-assembler "\tror\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/smartmips-ror-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/smartmips-ror-2.c
new file mode 100644
index 000000000..ac4c94df8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/smartmips-ror-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O -msmartmips" } */
+
+NOMIPS16 int rotate_right (unsigned a, unsigned s)
+{
+  return (a >> s) | (a << (32 - s));
+}
+/* { dg-final { scan-assembler "\tror\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/smartmips-ror-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/smartmips-ror-3.c
new file mode 100644
index 000000000..360f3c463
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/smartmips-ror-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -msmartmips" } */
+
+#define S 13
+
+NOMIPS16 int rotate_left_constant (unsigned a)
+{
+  return (a << S) | (a >> (32 - S));
+}
+/* { dg-final { scan-assembler "\tror\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/smartmips-ror-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/smartmips-ror-4.c
new file mode 100644
index 000000000..b8b829445
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/smartmips-ror-4.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -msmartmips" } */
+
+#define S 13
+
+NOMIPS16 int rotate_right_constant (unsigned a)
+{
+  return (a >> S) | (a << (32 - S));
+}
+/* { dg-final { scan-assembler "\tror\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/timode-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/timode-1.c
new file mode 100644
index 000000000..fc087ee1c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/timode-1.c
@@ -0,0 +1,65 @@
+/* { dg-options "-mgp64" } */
+typedef int int128_t __attribute__((mode(TI)));
+typedef unsigned int uint128_t __attribute__((mode(TI)));
+
+#define UINT128_CONST(A, B) \
+  (((uint128_t) (0x ## A ## ULL) << 64) | (0x ## B ## ULL))
+
+volatile uint128_t a = UINT128_CONST (1111111111111111, a222222222222222);
+volatile uint128_t b = UINT128_CONST (0000000000000005, 0000000000000003);
+volatile uint128_t c = UINT128_CONST (5dddddddddddddde, e666666666666666);
+volatile uint128_t d = UINT128_CONST (e612340000000000, 5000000000234500);
+volatile uint128_t e = UINT128_CONST (43f011dddddddddf, 366666666689ab66);
+volatile uint128_t f = UINT128_CONST (4210100000000000, 1000000000010100);
+volatile uint128_t g = UINT128_CONST (a5e225dddddddddf, 6666666666aaee66);
+volatile uint128_t h = UINT128_CONST (e7f235dddddddddf, 7666666666abef66);
+volatile uint128_t i = UINT128_CONST (5e225dddddddddf6, 666666666aaee660);
+volatile uint128_t j = UINT128_CONST (0a5e225ddddddddd, f6666666666aaee6);
+volatile uint128_t k = UINT128_CONST (fa5e225ddddddddd, f6666666666aaee6);
+
+volatile int amount = 4;
+
+volatile uint128_t result;
+
+int
+main (void)
+{
+  result = a * b;
+  if (result != c)
+    return 1;
+
+  result = c + d;
+  if (result != e)
+    return 1;
+
+  result = e - d;
+  if (result != c)
+    return 1;
+
+  result = d & e;
+  if (result != f)
+    return 1;
+
+  result = d ^ e;
+  if (result != g)
+    return 1;
+
+  result = d | e;
+  if (result != h)
+    return 1;
+
+  result = g << amount;
+  if (result != i)
+    return 1;
+
+  result = g >> amount;
+  if (result != j)
+    return 1;
+
+  result = (int128_t) g >> amount;
+  if (result != k)
+    return 1;
+
+  return 0;
+}
+/* { dg-final { scan-assembler-not "\tjal" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/timode-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/timode-2.c
new file mode 100644
index 000000000..9f3e43c41
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/timode-2.c
@@ -0,0 +1,65 @@
+/* { dg-do run } */
+/* { dg-options "-mgp64" } */
+typedef int int128_t __attribute__((mode(TI)));
+typedef unsigned int uint128_t __attribute__((mode(TI)));
+
+#define UINT128_CONST(A, B) \
+  (((uint128_t) (0x ## A ## ULL) << 64) | (0x ## B ## ULL))
+
+volatile uint128_t a = UINT128_CONST (1111111111111111, a222222222222222);
+volatile uint128_t b = UINT128_CONST (0000000000000005, 0000000000000003);
+volatile uint128_t c = UINT128_CONST (5dddddddddddddde, e666666666666666);
+volatile uint128_t d = UINT128_CONST (e612340000000000, 5000000000234500);
+volatile uint128_t e = UINT128_CONST (43f011dddddddddf, 366666666689ab66);
+volatile uint128_t f = UINT128_CONST (4210100000000000, 1000000000010100);
+volatile uint128_t g = UINT128_CONST (a5e225dddddddddf, 6666666666aaee66);
+volatile uint128_t h = UINT128_CONST (e7f235dddddddddf, 7666666666abef66);
+volatile uint128_t i = UINT128_CONST (5e225dddddddddf6, 666666666aaee660);
+volatile uint128_t j = UINT128_CONST (0a5e225ddddddddd, f6666666666aaee6);
+volatile uint128_t k = UINT128_CONST (fa5e225ddddddddd, f6666666666aaee6);
+
+volatile int amount = 4;
+
+volatile uint128_t result;
+
+int
+main (void)
+{
+  result = a * b;
+  if (result != c)
+    return 1;
+
+  result = c + d;
+  if (result != e)
+    return 1;
+
+  result = e - d;
+  if (result != c)
+    return 1;
+
+  result = d & e;
+  if (result != f)
+    return 1;
+
+  result = d ^ e;
+  if (result != g)
+    return 1;
+
+  result = d | e;
+  if (result != h)
+    return 1;
+
+  result = g << amount;
+  if (result != i)
+    return 1;
+
+  result = g >> amount;
+  if (result != j)
+    return 1;
+
+  result = (int128_t) g >> amount;
+  if (result != k)
+    return 1;
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/truncate-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/truncate-1.c
new file mode 100644
index 000000000..7e54aae3e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/truncate-1.c
@@ -0,0 +1,20 @@
+/* { dg-options "-O -mgp64" } */
+
+#define TEST(ID, TYPE, SHIFT)				\
+  int __attribute__((nomips16))				\
+  f##ID (unsigned long long y)				\
+  {							\
+    return (TYPE) ((TYPE) (y >> SHIFT) + 1);		\
+  }
+
+TEST (1, int, 32)
+TEST (2, short, 32)
+TEST (3, char, 32)
+TEST (4, int, 33)
+TEST (5, short, 33)
+TEST (6, char, 33)
+TEST (7, int, 61)
+TEST (8, short, 61)
+TEST (9, char, 61)
+
+/* { dg-final { scan-assembler-not "\tsll\t\[^\n\]*,0" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/truncate-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/truncate-2.c
new file mode 100644
index 000000000..423dc26f4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/truncate-2.c
@@ -0,0 +1,20 @@
+/* { dg-options "-O -mgp64" } */
+
+#define TEST(ID, TYPE, SHIFT)				\
+  int NOMIPS16						\
+  f##ID (long long y)					\
+  {							\
+    return (TYPE) ((TYPE) (y >> SHIFT) + 1);		\
+  }
+
+TEST (1, int, 32)
+TEST (2, short, 32)
+TEST (3, char, 32)
+TEST (4, int, 33)
+TEST (5, short, 33)
+TEST (6, char, 33)
+TEST (7, int, 61)
+TEST (8, short, 61)
+TEST (9, char, 61)
+
+/* { dg-final { scan-assembler-not "\tsll\t\[^\n\]*,0" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/vr-mult-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/vr-mult-1.c
new file mode 100644
index 000000000..2ed4f2f9b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/vr-mult-1.c
@@ -0,0 +1,7 @@
+/* Make sure that mul/addu is preferred over mtlo/macc and that mul/subu
+   is preferred over mtlo/msac.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=vr5400" } */
+NOMIPS16 int f1 (int a, int b, int c) { return a + b * c; }
+NOMIPS16 int f2 (int a, int b, int c) { return a - b * c; }
+/* { dg-final { scan-assembler "\tmul\t.*\tmul\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/mips/vr-mult-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/vr-mult-2.c
new file mode 100644
index 000000000..7e8be5e42
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/mips/vr-mult-2.c
@@ -0,0 +1,7 @@
+/* Make sure that mul/addu is preferred over mtlo/macc and that mul/subu
+   is preferred over mtlo/msac.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=vr5500" } */
+NOMIPS16 int f1 (int a, int b, int c) { return a + b * c; }
+NOMIPS16 int f2 (int a, int b, int c) { return a - b * c; }
+/* { dg-final { scan-assembler "\tmul\t.*\tmul\t" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20020118-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20020118-1.c
new file mode 100644
index 000000000..393f3c2aa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20020118-1.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target powerpc*-*-* } }*/
+
+/* Test local alignment.  Test new target macro STARTING_FRAME_PHASE.  */
+/* Origin: Aldy Hernandez <aldyh@redhat.com>.  */
+
+extern void abort(void);
+
+int main ()
+{       
+  int darisa[4] __attribute__((aligned(16))) ;
+  int *stephanie = (int *) darisa;
+
+  if ((unsigned long) stephanie % 16 != 0)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20030218-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20030218-1.c
new file mode 100644
index 000000000..2a1c4e6d2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20030218-1.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+
+/* Test vectors that can interconvert without a cast.  */
+
+__ev64_opaque__ opp;
+int vint   __attribute__((vector_size (8)));
+short vshort __attribute__((vector_size (8)));
+float vfloat __attribute__((vector_size (8)));
+
+int
+main (void)
+{
+  __ev64_opaque__ george = { 1, 2 }; /* { dg-error "opaque vector types cannot be initialized" } */
+
+  opp = vfloat;
+  vshort = opp;
+  vfloat = vshort; /* { dg-error "incompatible types when assigning" } */
+
+  /* Just because this is a V2SI, it doesn't make it an opaque.  */
+  vint = vshort; /* { dg-message "note: use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts" } */
+  /* { dg-error "incompatible types when assigning" "" { target *-*-* } 22 } */
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20030505.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20030505.c
new file mode 100644
index 000000000..2bef590bf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20030505.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-W -mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+
+#define __vector __attribute__((vector_size(8)))
+
+typedef float                   __vector __ev64_fs__;
+
+__ev64_opaque__ *p1;
+__ev64_fs__ *p2;
+int *x;
+
+extern void f (__ev64_opaque__ *); /* { dg-message "expected.*but argument is of type" } */
+
+int main ()
+{
+	f (x);	/* { dg-warning "incompatible pointer type" } */
+	f (p1);
+	f (p2);
+	return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20040121-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20040121-1.c
new file mode 100644
index 000000000..f819a4949
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20040121-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-options "-O2 -mcpu=G5 " } */
+
+long long (*y)(int t);
+long long get_alias_set (int t)
+{
+  return y(t);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20040622-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20040622-1.c
new file mode 100644
index 000000000..c699296d4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20040622-1.c
@@ -0,0 +1,13 @@
+/* { dg-options "-Os -mlong-double-128" } */
+/* { dg-do compile { target { { rs6000-*-* } || { powerpc*-*-* && lp64 } } } } */
+/* Make sure compiler doesn't generate [reg+reg] address mode
+   for long doubles. */
+union arg {
+  int intarg;
+  long double longdoublearg;
+};
+long double d;
+int va(int n, union arg **argtable)
+{
+  (*argtable)[n].longdoublearg = d;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20041111-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20041111-1.c
new file mode 100644
index 000000000..94de2f03a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20041111-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-mcpu=power4 -O2" } */
+
+extern unsigned long long set_mask[65];
+extern  unsigned long long xyzzy(int) __attribute__((pure));
+
+int valid (int x)
+{
+  return(xyzzy(x) & set_mask[x]);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20050603-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20050603-1.c
new file mode 100644
index 000000000..041551ba5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20050603-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run { target powerpc*-*-* } } */
+/* { dg-options "-O2" } */
+#include <locale.h>
+#include <stdlib.h>
+register int *testreg asm ("r29");
+
+int x;
+int y;
+int *ext_func (int *p) { return p; }
+
+void test_reg_save_restore (int*) __attribute__((noinline));
+void
+test_reg_save_restore (int *p)
+{
+    setlocale (LC_ALL, "C");
+    testreg = ext_func(p);
+}
+main() {
+  testreg = &x;
+  test_reg_save_restore (&y);
+  if (testreg != &y)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20050603-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20050603-3.c
new file mode 100644
index 000000000..0f328e171
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20050603-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { ilp32 } } } */
+/* { dg-options "-O2" } */
+struct Q 
+{
+  long x:20;
+  long y:4;
+  long z:8;
+}b;
+/* This should generate a single rl[w]imi. */
+void rotins (unsigned int x)
+{
+  b.y = (x<<12) | (x>>20);
+}
+
+/* { dg-final { scan-assembler-not "inm" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20050830-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20050830-1.c
new file mode 100644
index 000000000..4a8f71a98
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20050830-1.c
@@ -0,0 +1,13 @@
+/* Make sure the doloop optimization is done for this loop. */
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "bdn" } } */
+extern int a[];
+int foo(int w) {
+  int n = w;
+  while (n >= 512)
+    {
+    a[n] = 42;
+    n -= 256;
+    }
+  }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20081204-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20081204-1.c
new file mode 100644
index 000000000..8a973d0ec
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/20081204-1.c
@@ -0,0 +1,9 @@
+/* Test for ICE arising from inconsistent use of TARGET_E500 versus
+   TARGET_HARD_FLOAT && !TARGET_FPRS.  */
+/* { dg-do compile } */
+/* { dg-options "-mcpu=750 -mfloat-gprs=single" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+
+static int comp(const void *a,const void *b){
+  return (*(float *)a<*(float *)b)-(*(float *)a>*(float *)b);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c
new file mode 100644
index 000000000..2971e553e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c
@@ -0,0 +1,18 @@
+/* Test generation of dlmzb for strlen on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "dlmzb\\. " } } */
+
+typedef __SIZE_TYPE__ size_t;
+
+size_t strlen(const char *);
+
+size_t
+strlen8(const long long *s)
+{
+  return strlen((const char *)s);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c
new file mode 100644
index 000000000..e65ba08eb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of macchw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "macchw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c
new file mode 100644
index 000000000..6263818c1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of macchw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "macchw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c
new file mode 100644
index 000000000..18d448c06
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c
@@ -0,0 +1,15 @@
+/* Test generation of macchwu on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "macchwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c
new file mode 100644
index 000000000..7728c8b68
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c
@@ -0,0 +1,17 @@
+/* Test generation of macchwu. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "macchwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c
new file mode 100644
index 000000000..2211cd158
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of machhw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "machhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c
new file mode 100644
index 000000000..4c54f27b5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of machhw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "machhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c
new file mode 100644
index 000000000..44d8ea68c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c
@@ -0,0 +1,15 @@
+/* Test generation of machhwu on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "machhwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c
new file mode 100644
index 000000000..0fc96d1bd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c
@@ -0,0 +1,17 @@
+/* Test generation of machhwu. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "machhwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c
new file mode 100644
index 000000000..43ec01914
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of maclhw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "maclhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (short)c;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c
new file mode 100644
index 000000000..d79df5285
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of maclhw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "maclhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c
new file mode 100644
index 000000000..0d65a5d34
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c
@@ -0,0 +1,15 @@
+/* Test generation of maclhwu on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "maclhwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (unsigned short)c;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c
new file mode 100644
index 000000000..5b148d66c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c
@@ -0,0 +1,17 @@
+/* Test generation of maclhwu. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "maclhwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (unsigned short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c
new file mode 100644
index 000000000..510e0c81c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of mulchw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulchw " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c
new file mode 100644
index 000000000..14b4df1c0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of mulchw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulchw\\. " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c
new file mode 100644
index 000000000..a0ecdac65
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c
@@ -0,0 +1,15 @@
+/* Test generation of mulchwu on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulchwu " } } */
+
+int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c
new file mode 100644
index 000000000..c4da99273
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c
@@ -0,0 +1,17 @@
+/* Test generation of mulchwu. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulchwu\\. " } } */
+
+int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c
new file mode 100644
index 000000000..efdd8cdbb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of mulhhw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulhhw " } } */
+
+int
+f(int b, int c)
+{
+  int a = (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c
new file mode 100644
index 000000000..cfa00034e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of mulhhw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulhhw\\. " } } */
+
+int
+f(int b, int c)
+{
+  int a = (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c
new file mode 100644
index 000000000..c6f7a2452
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c
@@ -0,0 +1,15 @@
+/* Test generation of mulhhwu on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulhhwu " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c
new file mode 100644
index 000000000..9b647e7d7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c
@@ -0,0 +1,17 @@
+/* Test generation of mulhhwu. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulhhwu\\. " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c
new file mode 100644
index 000000000..ea28b5542
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of mullhw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mullhw " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (short)c;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c
new file mode 100644
index 000000000..76bbb6403
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of mullhw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mullhw\\. " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c
new file mode 100644
index 000000000..152dfe9b8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c
@@ -0,0 +1,15 @@
+/* Test generation of mullhwu on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mullhwu " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (unsigned short)c;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c
new file mode 100644
index 000000000..ff4b8eca5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c
@@ -0,0 +1,17 @@
+/* Test generation of mullhwu. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mullhwu\\. " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (unsigned short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c
new file mode 100644
index 000000000..dd258efe5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of nmacchw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "nmacchw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c
new file mode 100644
index 000000000..2a470b9e7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of nmacchw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "nmacchw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c
new file mode 100644
index 000000000..f699a3fc4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of nmachhw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "nmachhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c
new file mode 100644
index 000000000..07a30c13f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of nmachhw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "nmachhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c
new file mode 100644
index 000000000..91eba842a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of nmaclhw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "nmaclhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (short)c;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c
new file mode 100644
index 000000000..83717a4ff
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of nmaclhw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "nmaclhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c
new file mode 100644
index 000000000..c69a7c91b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c
@@ -0,0 +1,17 @@
+/* Test generation of dlmzb for strlen on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "dlmzb\\. " } } */
+
+typedef __SIZE_TYPE__ size_t;
+
+size_t strlen(const char *);
+
+size_t
+strlen8(const long long *s)
+{
+  return strlen((const char *)s);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-macchw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-macchw-1.c
new file mode 100644
index 000000000..464eff43b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-macchw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of macchw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "macchw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c
new file mode 100644
index 000000000..bfe55d486
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of macchw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "macchw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-macchwu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-macchwu-1.c
new file mode 100644
index 000000000..1db6c6e71
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-macchwu-1.c
@@ -0,0 +1,14 @@
+/* Test generation of macchwu on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "macchwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c
new file mode 100644
index 000000000..eb0b9251c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c
@@ -0,0 +1,16 @@
+/* Test generation of macchwu. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "macchwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-machhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-machhw-1.c
new file mode 100644
index 000000000..78aac5cb6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-machhw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of machhw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "machhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-machhw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-machhw-2.c
new file mode 100644
index 000000000..caf05eb41
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-machhw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of machhw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "machhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c
new file mode 100644
index 000000000..7f1cab988
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c
@@ -0,0 +1,14 @@
+/* Test generation of machhwu on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "machhwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c
new file mode 100644
index 000000000..88a23087b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c
@@ -0,0 +1,16 @@
+/* Test generation of machhwu. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "machhwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c
new file mode 100644
index 000000000..327d2fbea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of maclhw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "maclhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (short)c;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c
new file mode 100644
index 000000000..3e92d7ac8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of maclhw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "maclhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-maclhwu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-maclhwu-1.c
new file mode 100644
index 000000000..248e54e8b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-maclhwu-1.c
@@ -0,0 +1,14 @@
+/* Test generation of maclhwu on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "maclhwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (unsigned short)c;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-maclhwu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-maclhwu-2.c
new file mode 100644
index 000000000..c27988e2b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-maclhwu-2.c
@@ -0,0 +1,16 @@
+/* Test generation of maclhwu. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "maclhwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (unsigned short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulchw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulchw-1.c
new file mode 100644
index 000000000..14b11e2f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulchw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of mulchw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulchw " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c
new file mode 100644
index 000000000..d09561cb1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of mulchw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulchw\\. " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulchwu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulchwu-1.c
new file mode 100644
index 000000000..44bb325ce
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulchwu-1.c
@@ -0,0 +1,14 @@
+/* Test generation of mulchwu on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulchwu " } } */
+
+int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulchwu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulchwu-2.c
new file mode 100644
index 000000000..cc72f6193
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulchwu-2.c
@@ -0,0 +1,16 @@
+/* Test generation of mulchwu. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulchwu\\. " } } */
+
+int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulhhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulhhw-1.c
new file mode 100644
index 000000000..4b27396ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulhhw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of mulhhw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulhhw " } } */
+
+int
+f(int b, int c)
+{
+  int a = (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulhhw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulhhw-2.c
new file mode 100644
index 000000000..4cfb7ebf0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulhhw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of mulhhw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulhhw\\. " } } */
+
+int
+f(int b, int c)
+{
+  int a = (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-1.c
new file mode 100644
index 000000000..b255a9bdf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-1.c
@@ -0,0 +1,14 @@
+/* Test generation of mulhhwu on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulhhwu " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c
new file mode 100644
index 000000000..e82bbc678
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c
@@ -0,0 +1,16 @@
+/* Test generation of mulhhwu. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulhhwu\\. " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c
new file mode 100644
index 000000000..910885753
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of mullhw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mullhw " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (short)c;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c
new file mode 100644
index 000000000..023eb7187
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of mullhw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mullhw\\. " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mullhwu-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mullhwu-1.c
new file mode 100644
index 000000000..3636e4c4e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mullhwu-1.c
@@ -0,0 +1,14 @@
+/* Test generation of mullhwu on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mullhwu " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (unsigned short)c;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mullhwu-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mullhwu-2.c
new file mode 100644
index 000000000..93bc9f390
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-mullhwu-2.c
@@ -0,0 +1,16 @@
+/* Test generation of mullhwu. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mullhwu\\. " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (unsigned short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c
new file mode 100644
index 000000000..2fc782688
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of nmacchw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmacchw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c
new file mode 100644
index 000000000..3931ec530
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of nmacchw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmacchw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c
new file mode 100644
index 000000000..62362d03c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of nmachhw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmachhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c
new file mode 100644
index 000000000..22dac059c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of nmachhw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmachhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-1.c
new file mode 100644
index 000000000..1fe13b137
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of nmaclhw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmaclhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (short)c;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-2.c
new file mode 100644
index 000000000..f2abc4ccf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of nmaclhw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmaclhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/980827-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/980827-1.c
new file mode 100644
index 000000000..c2c92337a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/980827-1.c
@@ -0,0 +1,29 @@
+/* { dg-do run { target { { *-*-linux* && ilp32 } && powerpc_fprs } } } */
+/* { dg-options -O2 } */
+
+extern void exit (int);
+extern void abort (void);
+
+double dval = 0;
+
+void splat (double d);
+
+int main(void)
+{
+  splat(0);
+  if (dval == 0)
+    abort();
+  exit (0);
+}
+
+void splat (double d)
+{
+  union {
+    double f;
+    unsigned int l[2];
+  } u;
+  
+  u.f = d + d;
+  u.l[1] |= 1;
+  asm volatile ("stfd %0,dval@sdarel(13)" : : "f" (u.f));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-1.c
new file mode 100644
index 000000000..b1809fe2c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Program to test PowerPC AltiVec instructions.  */
+
+#include <altivec.h>
+
+extern void abort (void);
+
+vector int a1 = { 100, 200, 300, 400 };
+vector int a2 = { 500, 600, 700, 800 };
+vector int addi = { 600, 800, 1000, 1200 };
+vector int avgi = { 300, 400, 500, 600 };
+
+vector float f1 = { 1.0, 2.0, 3.0, 4.0 };  
+vector float f2 = { 5.0, 6.0, 7.0, 8.0 };
+vector float f3;
+vector float addf = { 6.0, 8.0, 10.0, 12.0 };
+
+vector int k;
+vector float f, g, h;
+
+int main ()
+{
+  k = vec_add (a1, a2);
+  if (!vec_all_eq (addi, k))
+    abort ();
+
+  k = vec_avg (a1, a2);
+  if (!vec_all_eq (k, avgi))
+    abort ();
+
+  h = vec_add (f1, f2);
+  if (!vec_all_eq (h, addf))
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-10.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-10.c
new file mode 100644
index 000000000..f532eebbf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-10.c
@@ -0,0 +1,79 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec -fno-inline" } */
+
+#include <altivec.h>
+
+extern void exit (int);
+extern void abort (void);
+
+typedef union
+{
+  float         f[4];
+  unsigned int  i[4];
+  vector float  v;
+} vec_float_t;
+
+void 
+check_vec_all_num ()
+{
+  vec_float_t a, b, c;
+
+  a.i[0] = 0xfffa5a5a;
+  a.f[1] = 1.0;
+  a.f[2] = 1.0;
+  a.f[3] = 1.0;
+
+  b.f[0] = 1.0;
+  b.f[1] = 1.0;
+  b.f[2] = 1.0;
+  b.f[3] = 1.0;
+
+  c.i[0] = 0xfffa5a5a;
+  c.i[1] = 0xfffa5a5a;
+  c.i[2] = 0xfffa5a5a;
+  c.i[3] = 0xfffa5a5a;
+
+  if (vec_all_numeric (a.v))
+    abort ();
+
+  if (vec_all_nan (a.v))
+    abort ();
+
+  if (!vec_all_numeric (b.v))
+    abort ();
+
+  if (vec_all_nan (b.v))
+    abort ();
+
+  if (vec_all_numeric (c.v))
+    abort ();
+
+  if (!vec_all_nan (c.v))
+    abort ();
+
+}
+
+void 
+check_cmple()
+{
+  vector float a = {1.0, 2.0, 3.0, 4.0};
+  vector float b = {1.0, 3.0, 2.0, 5.0};
+  vector bool int aux;
+  vector signed int le = {-1, -1, 0, -1};
+
+  aux = vec_cmple (a, b);
+
+  if (!vec_all_eq (aux, le))
+    abort ();
+}
+
+
+int 
+main()
+{
+  check_cmple ();
+  check_vec_all_num ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-11.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-11.c
new file mode 100644
index 000000000..648993ab8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-11.c
@@ -0,0 +1,59 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mabi=altivec" } */
+/* { dg-final { scan-assembler-not "lvx" } } */
+#include <altivec.h>
+
+void foo (vector int);
+void foo_s (vector short);
+void foo_c (vector char);
+
+/* All constants should be loaded into vector register without
+   load from memory.  */
+void
+bar (void) 
+{
+  foo ((vector int) {0, 0, 0, 0});
+  foo ((vector int) {1, 1, 1, 1});
+  foo ((vector int) {15, 15, 15, 15});
+  foo ((vector int) {-16, -16, -16, -16});
+  foo ((vector int) {0x10001, 0x10001, 0x10001, 0x10001});
+  foo ((vector int) {0xf000f, 0xf000f, 0xf000f, 0xf000f});
+  foo ((vector int) {0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0});
+  foo ((vector int) {0x1010101, 0x1010101, 0x1010101, 0x1010101});  
+  foo ((vector int) {0xf0f0f0f, 0xf0f0f0f, 0xf0f0f0f, 0xf0f0f0f});  
+  foo ((vector int) {0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0});
+  foo ((vector int) {0x10101010, 0x10101010, 0x10101010, 0x10101010});
+  foo ((vector int) {0x1e1e1e1e, 0x1e1e1e1e, 0x1e1e1e1e, 0x1e1e1e1e});
+  foo ((vector int) {0x100010, 0x100010, 0x100010, 0x100010});
+  foo ((vector int) {0x1e001e, 0x1e001e, 0x1e001e, 0x1e001e});
+  foo ((vector int) {0x10, 0x10, 0x10, 0x10});
+  foo ((vector int) {0x1e, 0x1e, 0x1e, 0x1e});
+
+  foo_s ((vector short int) {0, 0, 0, 0, 0, 0, 0, 0});
+  foo_s ((vector short int) {1, 1, 1, 1, 1, 1, 1, 1});
+  foo_s ((vector short int) {15, 15, 15, 15, 15, 15, 15, 15});
+  foo_s ((vector short int) {-16, -16, -16, -16, -16, -16, -16, -16});
+  foo_s ((vector short int) {0xf0f0, 0xf0f0, 0xf0f0, 0xf0f0, 
+			       0xf0f0, 0xf0f0, 0xf0f0, 0xf0f0});
+  foo_s ((vector short int) {0xf0f, 0xf0f, 0xf0f, 0xf0f, 
+			       0xf0f, 0xf0f, 0xf0f, 0xf0f});
+  foo_s ((vector short int) {0x1010, 0x1010, 0x1010, 0x1010, 
+			       0x1010, 0x1010, 0x1010, 0x1010});
+  foo_s ((vector short int) {0x1e1e, 0x1e1e, 0x1e1e, 0x1e1e, 
+			       0x1e1e, 0x1e1e, 0x1e1e, 0x1e1e});
+
+  foo_c ((vector char) {0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0});
+  foo_c ((vector char) {1, 1, 1, 1, 1, 1, 1, 1, 
+			  1, 1, 1, 1, 1, 1, 1, 1});
+  foo_c ((vector char) {15, 15, 15, 15, 15, 15, 15, 15,
+			  15, 15, 15, 15, 15, 15, 15, 15});
+  foo_c ((vector char) {-16, -16, -16, -16, -16, -16, -16, -16,
+			  -16, -16, -16, -16, -16, -16, -16, -16});
+  foo_c ((vector char) {16, 16, 16, 16, 16, 16, 16, 16,
+			  16, 16, 16, 16, 16, 16, 16, 16});
+  foo_c ((vector char) {30, 30, 30, 30, 30, 30, 30, 30,
+			  30, 30, 30, 30, 30, 30, 30, 30});
+
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-12.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-12.c
new file mode 100644
index 000000000..39d26940d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-12.c
@@ -0,0 +1,93 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Program to test PowerPC AltiVec instructions.  */
+
+#include <altivec.h>
+
+extern void abort (void);
+#define CHECK_IF(E) if(!(E)) abort()
+
+vector int a1 = (vector int){ 100, 200, 300, 400 };
+vector int a2 = (vector int){ 500, 600, 700, 800 };
+vector int addi = (vector int){ 600, 800, 1000, 1200 };
+vector int avgi = (vector int){ 300, 400, 500, 600 };
+
+vector float f1 = (vector float){ 1.0, 2.0, 3.0, 4.0 };
+vector float f2 = (vector float){ 5.0, 6.0, 7.0, 8.0 };
+vector float f3;
+vector float addf1 = (vector float){ 6.0, 8.0, 10.0, 12.0 };
+vector float addf2 = (vector float){ 6.1, 8.1, 10.1, 12.1 };
+vector float addf3 = (vector float){ 6.0, 8.0, 9.9, 12.1 };
+vector int k;
+vector float f, g, h;
+
+int main ()
+{
+  k = vec_add (a1, a2);
+  CHECK_IF (vec_all_eq (addi, k));
+  CHECK_IF (vec_all_ge (addi, k));
+  CHECK_IF (vec_all_le (addi, k));
+  CHECK_IF (vec_any_eq (addi, k));
+  CHECK_IF (vec_any_ge (addi, k));
+  CHECK_IF (vec_any_le (addi, k));
+  CHECK_IF (!vec_any_ne (addi, k));
+  CHECK_IF (!vec_any_lt (addi, k));
+  CHECK_IF (!vec_any_gt (addi, k));
+  CHECK_IF (!vec_any_ne (addi, k));
+  CHECK_IF (!vec_any_lt (addi, k));
+  CHECK_IF (!vec_any_gt (addi, k));
+
+  k = vec_avg (a1, a2);
+  CHECK_IF (vec_all_eq (k, avgi));
+
+  h = vec_add (f1, f2);
+  CHECK_IF (vec_all_eq (h, addf1));
+  CHECK_IF (vec_all_ge (h, addf1));
+  CHECK_IF (vec_all_le (h, addf1));
+  CHECK_IF (vec_any_eq (h, addf1));
+  CHECK_IF (vec_any_ge (h, addf1));
+  CHECK_IF (vec_any_le (h, addf1));
+  CHECK_IF (!vec_any_ne (h, addf1));
+  CHECK_IF (!vec_any_lt (h, addf1));
+  CHECK_IF (!vec_any_gt (h, addf1));
+  CHECK_IF (!vec_any_ne (h, addf1));
+  CHECK_IF (!vec_any_lt (h, addf1));
+  CHECK_IF (!vec_any_gt (h, addf1));
+
+  CHECK_IF (vec_all_gt (addf2, addf1));
+  CHECK_IF (vec_any_gt (addf2, addf1));
+  CHECK_IF (vec_all_ge (addf2, addf1));
+  CHECK_IF (vec_any_ge (addf2, addf1));
+  CHECK_IF (vec_all_ne (addf2, addf1));
+  CHECK_IF (vec_any_ne (addf2, addf1));
+  CHECK_IF (!vec_all_lt (addf2, addf1));
+  CHECK_IF (!vec_any_lt (addf2, addf1));
+  CHECK_IF (!vec_all_le (addf2, addf1));
+  CHECK_IF (!vec_any_le (addf2, addf1));
+  CHECK_IF (!vec_all_eq (addf2, addf1));
+  CHECK_IF (!vec_any_eq (addf2, addf1));
+
+  CHECK_IF (vec_any_eq (addf3, addf1));
+  CHECK_IF (vec_any_ne (addf3, addf1));
+  CHECK_IF (vec_any_lt (addf3, addf1));
+  CHECK_IF (vec_any_le (addf3, addf1));
+  CHECK_IF (vec_any_gt (addf3, addf1));
+  CHECK_IF (vec_any_ge (addf3, addf1));
+  CHECK_IF (!vec_all_eq (addf3, addf1));
+  CHECK_IF (!vec_all_ne (addf3, addf1));
+  CHECK_IF (!vec_all_lt (addf3, addf1));
+  CHECK_IF (!vec_all_le (addf3, addf1));
+  CHECK_IF (!vec_all_gt (addf3, addf1));
+  CHECK_IF (!vec_all_ge (addf3, addf1));
+
+  CHECK_IF (vec_all_numeric (addf3));
+  CHECK_IF (vec_all_in (addf1, addf2));
+
+  CHECK_IF (vec_step (vector bool char) == 16);
+  CHECK_IF (vec_step (addf3) == 4);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-13.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-13.c
new file mode 100644
index 000000000..22ff951b8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-13.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+/* Author: Ziemowit Laski  <zlaski@apple.com>  */
+
+/* This test case exercises intrinsic/argument combinations that,
+   while not in the Motorola AltiVec PIM, have nevertheless crept
+   into the AltiVec vernacular over the years.  */
+
+#include <altivec.h>
+
+void foo (void) 
+{
+  vector bool int boolVec1 = (vector bool int) vec_splat_u32(3);
+  vector bool short boolVec2 = (vector bool short) vec_splat_u16(3);
+  vector bool char boolVec3 = (vector bool char) vec_splat_u8(3);
+
+  boolVec1 = vec_sld( boolVec1, boolVec1, 4 );
+  boolVec2 = vec_sld( boolVec2, boolVec2, 2 );
+  boolVec3 = vec_sld( boolVec3, boolVec3, 1 );
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-14.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-14.c
new file mode 100644
index 000000000..4d3cf4f8c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-14.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+vector bool long vbl;		/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+vector signed long vsl;		/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+vector unsigned long vul;	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+vector bool long *pvbl;		/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+vector signed long *pvsl;	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+vector unsigned long *pvul;	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+
+void fvbl (vector bool long v) { }	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+void fvsl (vector signed long v) { }	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+void fvul (vector unsigned long v) { }	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+
+int main ()
+{
+  vector bool long lvbl;	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+  vector signed long lvsl;	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+  vector unsigned long lvul;	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-15.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-15.c
new file mode 100644
index 000000000..4e48cb765
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-15.c
@@ -0,0 +1,30 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+/* Test whether the C front-end is not excessively picky about
+   the integral types and literals that AltiVec instrinsics will
+   accept.  */
+
+vector int vi = { 1, 2, 3, 4 };
+
+int
+main (void)
+{
+    unsigned long ul = 2;
+    signed long sl = 2;
+    unsigned int ui = 2;
+    signed int si = 2;
+    float fl = 2.0;
+
+    vec_dst (&vi, ul, '\0');
+    vec_dst (&vi, sl, 0);
+    vec_dst (&vi, ui, '\0');
+    vec_dst (&vi, si, 0);
+    vec_dstst (&vi, (short)fl, '\0');
+
+    return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-16.c
new file mode 100644
index 000000000..7f7d2b013
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-16.c
@@ -0,0 +1,22 @@
+/* This is a compile-only test for interaction of "-maltivec" and "-save-temps".  */
+/* Author:  Ziemowit Laski  <zlaski@apple.com>.  */
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-save-temps -maltivec" } */
+
+#include <altivec.h>
+
+#define vector_float vector float
+#define vector_float_foo vector float foo
+#define vector_float_bar_eq vector float bar =
+
+/* NB: Keep the following split across three lines.  */
+vector
+int
+a1 = { 100, 200, 300, 400 };
+
+vector_float f1 = { 1.0, 2.0, 3.0, 4.0 };  
+vector_float_foo = { 3.0, 4.0, 5.0, 6.0 };
+vector_float_bar_eq { 8.0, 7.0, 6.0, 5.0 };
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-17.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-17.c
new file mode 100644
index 000000000..8b1083268
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-17.c
@@ -0,0 +1,11 @@
+/* Verify a statement in the GCC Manual that GCC allows the use of a
+   typedef name as a vector type specifier.  */
+
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec" } */
+
+typedef unsigned int ui;
+typedef signed char sc;
+__vector ui vui;
+__vector sc vsc;
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-18.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-18.c
new file mode 100644
index 000000000..5d9885820
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-18.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec" } */
+/* { dg-final { scan-assembler "vcmpgtub" { target *-*-linux* } } } */
+/* { dg-final { scan-assembler "vcmpgtsb" { target *-*-darwin* } } } */
+/* { dg-final { scan-assembler "vcmpgtsh" } } */
+/* { dg-final { scan-assembler "vcmpgtsw" } } */
+
+/* Verify a statement in the GCC Manual that vector type specifiers can
+   omit "signed" or "unsigned".  The default is the default signedness
+   of the base type, which differs depending on the ABI.  */
+
+#include <altivec.h>
+
+extern vector char vc1, vc2;
+extern vector short vs1, vs2;
+extern vector int vi1, vi2;
+
+int signedness (void)
+{
+    return vec_all_le (vc1, vc2) 
+           && vec_all_le (vs1, vs2)
+           && vec_all_le (vi1, vi2);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-19.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-19.c
new file mode 100644
index 000000000..80f305a54
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-19.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+/* { dg-final { scan-assembler "dst" } } */
+
+void foo ( char* image )
+{
+  while ( 1 )
+    {
+      __builtin_altivec_dst( (void *)( (long)image & ~0x0f ), 0, 0 );
+      image += 48;
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-2.c
new file mode 100644
index 000000000..4f341dd42
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Program to test the vector_size attribute.  This needs to run on a
+   target that has vectors, so use AltiVec.  */
+
+#define vector __attribute__((vector_size(16)))
+
+vector int foobar;
+
+/* Only floats and integrals allowed.  We don't care if they map to SIs.  */
+struct X { int frances; };
+vector struct X hotdog;	/* { dg-error "invalid vector type" } */
+
+/* Arrays of vectors.  */
+vector char b[10], ouch;
+
+/* Pointers of vectors.  */
+vector short *shoe, polish;
+
+int xxx[sizeof(foobar) == 16 ? 69 : -1];
+
+int nc17[sizeof(shoe) == sizeof (char *) ? 69 : -1];
+
+code ()
+{
+  *shoe = polish;
+  b[1] = ouch;
+}
+
+vector short
+hoop ()
+{
+  return polish;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-20.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-20.c
new file mode 100644
index 000000000..b2c29a979
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-20.c
@@ -0,0 +1,23 @@
+/* { dg-do compile { target powerpc_altivec_ok } } */
+/* { dg-options "-maltivec -mcpu=G5 -O2" } */
+
+#include <altivec.h>
+
+void foo( float scalar)
+{
+    unsigned long width;
+    unsigned long x;
+    vector float vColor;
+    vector unsigned int selectMask;
+    vColor = vec_perm( vec_ld( 0, &scalar), vec_ld( 3, &scalar), vec_lvsl( 0, &scalar) );
+
+    float *destRow;
+    vector float store, load0;
+
+    for( ; x < width; x++)
+    {
+            load0 = vec_sel( vColor, load0, selectMask );
+            vec_st( store, 0, destRow );
+            store = load0;
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-21.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-21.c
new file mode 100644
index 000000000..906aa197a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-21.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+extern void preansi();
+
+typedef void (*pvecfunc) ();
+
+void foo(pvecfunc pvf) {
+   vector int v = (vector int){1, 2, 3, 4};
+#ifndef __LP64__
+   preansi (4, 4.0, v); /* { dg-error "AltiVec argument passed to unprototyped function" "" { target ilp32 } } */
+   (*pvf)  (4, 4.0, v); /* { dg-error "AltiVec argument passed to unprototyped function" "" { target ilp32 } } */
+#endif /* __LP64__ */
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-22.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-22.c
new file mode 100644
index 000000000..3c07309e4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-22.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O3 -maltivec" } */
+/* { dg-final { scan-assembler-not "mfcr" } } */
+
+#include <altivec.h>
+
+int foo(vector float x, vector float y) {
+        if (vec_all_eq(x,y)) return 3245;
+        else return 12;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-23.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-23.c
new file mode 100644
index 000000000..3b039f73b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-23.c
@@ -0,0 +1,24 @@
+/* Verify that it is possible to define variables of composite types
+   containing vector types.  We used to crash handling the
+   initializer of automatic ones.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec" } */
+
+#include <altivec.h>
+
+typedef vector int vt;
+typedef struct { vt x; int y[sizeof(vt) / sizeof (int)]; } st;
+#define INIT { 1, 2, 3, 4 }
+
+void f ()
+{
+  vt x = INIT;
+  vt y[1] = { INIT };
+  st s = { INIT, INIT };
+}
+
+vt x = INIT;
+vt y[1] = { INIT };
+st s = { INIT, INIT };
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-24.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-24.c
new file mode 100644
index 000000000..d296fe246
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-24.c
@@ -0,0 +1,35 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+extern void abort (void);
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+#define MAGIC_NUMBER 12345
+
+v4si my_vect;
+int my_array[4] __attribute__ ((aligned (16)));
+
+void initialize (int a)
+{
+  my_vect = (v4si) {0, a, 2, 3};
+  vec_st (my_vect, 0, my_array);
+}
+
+int verify (void)
+{
+  if (my_array[1] != MAGIC_NUMBER)
+    abort ();
+}
+
+int main (void)
+{
+  initialize (MAGIC_NUMBER);
+  verify ();
+  return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-25.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-25.c
new file mode 100644
index 000000000..a3bd0fd00
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-25.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -Wall" } */
+
+
+#define vector __attribute__((__vector_size__(16) ))
+vector int f()
+{
+  int t = 4;
+  return (vector int){t,t,t,t};
+}
+vector int f1()
+{
+  return (vector int){4,4,4,4};
+}
+
+/* We should be able to materialize the constant vector without
+   any lvewx instructions as it is constant. */
+/* { dg-final { scan-assembler-not "lvewx" } } */
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-26.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-26.c
new file mode 100644
index 000000000..689d13a51
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-26.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* A compiler implementing context-sensitive keywords must define this
+   preprocessor macro so that altivec.h does not provide the vector,
+   pixel, etc. macros.  */
+
+#ifndef __APPLE_ALTIVEC__
+#error __APPLE_ALTIVEC__ not pre-defined
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-27.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-27.c
new file mode 100644
index 000000000..7db0ea01f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-27.c
@@ -0,0 +1,32 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#define f0() void x0 (vector float x) { }
+f0 ()
+
+#define f1(type) void x1##type (vector type x) { }
+f1 (float)
+
+#define f2(v, type) void x2##type (v type x) { }
+f2 (vector, float)
+
+#define f3(type) void x3##type (vector bool type x) { }
+f3 (int)
+
+#define f4(v, type) void x4##type (v bool type x) { }
+f4 (vector, int)
+
+#define f5(b, type) void x5##type (vector b type x) { }
+f5 (bool, int)
+
+#define f6(v, b, type) void x6##type (v b type x) { }
+f6 (vector, bool, int)
+
+#define f7(v, b, type) void x7##type (v type b x) { }
+f7 (vector, bool, int)
+
+int vector = 6;
+
+#define v1(v) int x8 (int v) { return v; }
+v1(vector)
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-28.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-28.c
new file mode 100644
index 000000000..db6c25ac7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-28.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#define B bool
+#define P pixel
+#define I int
+#define BI bool int
+#define PI pixel int
+
+vector B int i;
+vector P int j;
+vector B I k;
+vector P I l;
+vector BI m;
+vector PI n;
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-29.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-29.c
new file mode 100644
index 000000000..10a25ecbb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-29.c
@@ -0,0 +1,23 @@
+/* PR target/39558 */
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -save-temps" } */
+
+#define ATTRIBUTE_UNUSED __attribute__((unused))
+
+int *foo (int *vector)
+{
+  return vector;
+}
+
+int *bar (int *vector ATTRIBUTE_UNUSED)
+{
+  return vector;
+}
+
+int *baz (int *vector __attribute__((unused)))
+{
+  return vector;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-3.c
new file mode 100644
index 000000000..d388ad299
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-3.c
@@ -0,0 +1,80 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+extern void exit (int);
+extern void abort (void);
+
+typedef int int4 __attribute__ ((vector_size (16)));
+typedef float float4 __attribute__ ((vector_size (16)));
+
+int4 a1 = (int4) { 100, 200, 300, 400 };
+int4 a2 = (int4) { 500, 600, 700, 800 };
+
+float4 f1 = (float4) { 1.0, 2.0, 3.0, 4.0 };  
+float4 f2 = (float4) { 5.0, 6.0, 7.0, 8.0 };
+
+int i3[4] __attribute__((aligned(16)));
+int j3[4] __attribute__((aligned(16)));
+float h3[4] __attribute__((aligned(16)));
+float g3[4] __attribute__((aligned(16)));
+
+#define vec_store(dst, src) \
+  __builtin_vec_st (src, 0, (__typeof__ (src) *) dst)
+
+#define vec_add_int4(x, y) \
+  __builtin_altivec_vaddsws (x, y)
+
+#define vec_add_float4(x, y) \
+  __builtin_altivec_vaddfp (x, y)
+
+#define my_abs(x) (x > 0.0F ? x : -x)
+
+void
+compare_int4 (int *a, int *b)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    if (a[i] != b[i])
+      abort ();
+}
+
+void
+compare_float4 (float *a, float *b)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    if (my_abs(a[i] - b[i]) >= 1.0e-6)
+      abort ();
+}
+
+void
+main1 ()
+{
+  int loc1 = 600, loc2 = 800;
+  int4 a3 = (int4) { loc1, loc2, 1000, 1200 };
+  int4 itmp;
+  double locf = 12.0;
+  float4 f3 = (float4) { 6.0, 8.0, 10.0, 12.0 };
+  float4 ftmp;
+
+  vec_store (i3, a3);
+  itmp = vec_add_int4 (a1, a2);
+  vec_store (j3, itmp);
+  compare_int4 (i3, j3);
+
+  vec_store (g3, f3);
+  ftmp = vec_add_float4 (f1, f2);
+  vec_store (h3, ftmp);
+  compare_float4 (g3, h3);
+}
+
+int
+main ()
+{
+  main1 ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-30.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-30.c
new file mode 100644
index 000000000..99783191d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-30.c
@@ -0,0 +1,32 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <stdbool.h>
+#include <altivec.h>
+
+#define f0(type) void x0##type (vector bool type x) { }
+f0 (int)
+
+#define f1(v, type) void x1##type (v bool type x) { }
+f1 (vector, int)
+
+#define f2(b, type) void x2##type (vector b type x) { }
+f2 (bool, int)
+
+#define f3(v, b, type) void x3##type (v b type x) { }
+f3 (vector, bool, int)
+
+#define f4(v, b, type) void x4##type (v type b x) { }
+f4 (vector, bool, int)
+
+#define B bool
+#define I int
+#define BI bool int
+#define VBI vector bool int
+
+vector bool int a;
+vector B int b;
+vector B I c;
+vector BI d;
+VBI e;
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-31.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-31.c
new file mode 100644
index 000000000..233efe1be
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-31.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#define f0(type) void x0##type (vector _Bool type x) { }
+f0 (int)
+
+#define f1(v, type) void x1##type (v _Bool type x) { }
+f1 (vector, int)
+
+#define f2(b, type) void x2##type (vector b type x) { }
+f2 (_Bool, int)
+
+#define f3(v, b, type) void x3##type (v b type x) { }
+f3 (vector, _Bool, int)
+
+#define f4(v, b, type) void x4##type (v type b x) { }
+f4 (vector, _Bool, int)
+
+#define B _Bool
+#define I int
+#define BI _Bool int
+#define VBI vector _Bool int
+
+vector _Bool int a;
+vector B int b;
+vector B I c;
+vector BI d;
+VBI e;
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-4.c
new file mode 100644
index 000000000..a5617e25b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-4.c
@@ -0,0 +1,65 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O0 -Wall" } */
+
+#define vector __attribute__((vector_size(16)))
+
+static int vector x, y;
+
+static vector signed int i,j;
+static vector signed short s,t;
+static vector signed char c,d;
+static vector float f,g;
+
+static vector unsigned char uc;
+
+static vector signed int *pi;
+
+static int int1, int2;
+
+void
+b()
+{
+  __builtin_altivec_vadduwm (x, y);
+
+  /* Make sure the predicates accept correct argument types.  */
+  
+  int1 = __builtin_altivec_vcmpbfp_p (0, f, g);
+  int1 = __builtin_altivec_vcmpeqfp_p (0, f, g);
+  int1 = __builtin_altivec_vcmpequb_p (0, c, d);
+  int1 = __builtin_altivec_vcmpequh_p (0, s, t);
+  int1 = __builtin_altivec_vcmpequw_p (0, i, j);
+  int1 = __builtin_altivec_vcmpgefp_p (0, f, g);
+  int1 = __builtin_altivec_vcmpgtfp_p (0, f, g);
+  int1 = __builtin_altivec_vcmpgtsb_p (0, c, d);
+  int1 = __builtin_altivec_vcmpgtsh_p (0, s, t);
+  int1 = __builtin_altivec_vcmpgtsw_p (0, i, j);
+  int1 = __builtin_altivec_vcmpgtub_p (0, c, d);
+  int1 = __builtin_altivec_vcmpgtuh_p (0, s, t);
+  int1 = __builtin_altivec_vcmpgtuw_p (0, i, j);
+
+  __builtin_altivec_mtvscr (i);
+  __builtin_altivec_dssall ();
+  s = __builtin_altivec_mfvscr ();
+  __builtin_altivec_dss (3);
+
+  __builtin_altivec_dst (pi, int1 + int2, 3);
+  __builtin_altivec_dstst (pi, int1 + int2, 3);
+  __builtin_altivec_dststt (pi, int1 + int2, 3);
+  __builtin_altivec_dstt (pi, int1 + int2, 3);
+
+  uc = (vector unsigned char) __builtin_altivec_lvsl (int1 + 69, pi);
+  uc = (vector unsigned char) __builtin_altivec_lvsr (int1 + 69, pi);
+
+  c = __builtin_altivec_lvebx (int1, pi);
+  s = __builtin_altivec_lvehx (int1, pi);
+  i = __builtin_altivec_lvewx (int1, pi);
+  i = __builtin_altivec_lvxl (int1, pi);
+  i = __builtin_altivec_lvx (int1, pi);
+
+  __builtin_altivec_stvx (i, int2, pi);
+  __builtin_altivec_stvebx (c, int2, pi);
+  __builtin_altivec_stvehx (s, int2, pi);
+  __builtin_altivec_stvewx (i, int2, pi);
+  __builtin_altivec_stvxl (i, int2, pi);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-5.c
new file mode 100644
index 000000000..ae85cdbdc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-5.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#define vector __attribute__((vector_size(16)))
+
+void foo (const unsigned long x,
+	  vector signed int a, vector signed int b)
+{
+  unsigned char d[64];
+
+  __builtin_altivec_stvewx (b, 0, d);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-6.c
new file mode 100644
index 000000000..dc115f942
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-6.c
@@ -0,0 +1,66 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O0 -Wall" } */
+
+#include <altivec.h>
+
+/* These denote "generic" GCC vectors.  */
+static int __attribute__((vector_size(16))) x, y;
+
+static vector signed int i,j;
+static vector signed short s,t;
+static vector signed char c,d;
+static vector float f,g;
+
+static vector unsigned char uc;
+
+static vector signed int *pi;
+
+static int int1, int2;
+
+void
+b()
+{
+  vec_add (x, y);
+
+  /* Make sure the predicates accept correct argument types.  */
+
+  int1 = vec_all_in (f, g);
+  int1 = vec_all_ge (f, g);
+  int1 = vec_all_eq (c, d);
+  int1 = vec_all_ne (s, t);
+  int1 = vec_any_eq (i, j);
+  int1 = vec_any_ge (f, g);
+  int1 = vec_all_ngt (f, g);
+  int1 = vec_any_ge (c, d);
+  int1 = vec_any_ge (s, t);
+  int1 = vec_any_ge (i, j);
+  int1 = vec_any_ge (c, d);
+  int1 = vec_any_ge (s, t);
+  int1 = vec_any_ge (i, j);
+
+  vec_mtvscr (i);
+  vec_dssall ();
+  s = (vector signed short) vec_mfvscr ();
+  vec_dss (3);
+
+  vec_dst (pi, int1 + int2, 3);
+  vec_dstst (pi, int1 + int2, 3);
+  vec_dststt (pi, int1 + int2, 3);
+  vec_dstt (pi, int1 + int2, 3);
+
+  uc = (vector unsigned char) vec_lvsl (int1 + 69, (signed int *) pi);
+  uc = (vector unsigned char) vec_lvsr (int1 + 69, (signed int *) pi);
+
+  c = vec_lde (int1, (signed char *) pi);
+  s = vec_lde (int1, (signed short *) pi);
+  i = vec_lde (int1, (signed int *) pi);
+  i = vec_ldl (int1, pi);
+  i = vec_ld (int1, pi);
+
+  vec_st (i, int2, pi);
+  vec_ste (c, int2, (signed char *) pi);
+  vec_ste (s, int2, (signed short *) pi);
+  vec_ste (i, int2, (signed int *) pi);
+  vec_stl (i, int2, pi);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-7.c
new file mode 100644
index 000000000..30a1ee520
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-7.c
@@ -0,0 +1,46 @@
+/* Origin: Aldy Hernandez  <aldyh@redhat.com>  */
+
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+int **intp;
+int *var_int;
+unsigned int **uintp;
+vector pixel *varpixel;
+vector signed char *vecchar;
+vector signed int *vecint;
+vector signed short *vecshort;
+vector unsigned char *vecuchar;
+vector unsigned int *vecuint;
+vector unsigned short *vecushort;
+vector float *vecfloat;
+
+int main ()
+{
+  *vecfloat++ = vec_andc((vector bool int)vecint[0], vecfloat[1]);
+  *vecfloat++ = vec_andc(vecfloat[0], (vector bool int)vecint[1]);
+  *vecfloat++ = vec_vxor((vector bool int)vecint[0], vecfloat[1]);
+  *vecfloat++ = vec_vxor(vecfloat[0], (vector bool int)vecint[1]);
+  *varpixel++ = vec_packpx(vecuint[0], vecuint[1]);
+  *varpixel++ = vec_vpkpx(vecuint[0], vecuint[1]);
+  *vecshort++ = vec_vmulosb(vecchar[0], vecchar[1]);
+  *vecint++ = vec_ld(var_int[0], intp[1]);
+  *vecint++ = vec_lde(var_int[0], intp[1]);
+  *vecint++ = vec_ldl(var_int[0], intp[1]);
+  *vecint++ = vec_lvewx(var_int[0], intp[1]);
+  *vecint++ = vec_unpackh(vecshort[0]);
+  *vecint++ = vec_unpackl(vecshort[0]);
+  *vecushort++ = vec_andc((vector bool short)vecshort[0], vecushort[1]);
+  *vecushort++ = vec_andc(vecushort[0], (vector bool short)vecshort[1]);
+  *vecushort++ = vec_vxor((vector bool short)vecshort[0], vecushort[1]);
+  *vecushort++ = vec_vxor(vecushort[0], (vector bool short)vecshort[1]);
+  *vecuint++ = vec_ld(var_int[0], uintp[1]);
+  *vecuint++ = vec_lvx(var_int[0], uintp[1]);
+  *vecuint++ = vec_vmsumubm(vecuchar[0], vecuchar[1], vecuint[2]);
+  *vecuchar++ = vec_xor(vecuchar[0], (vector unsigned char)vecchar[1]);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-8.c
new file mode 100644
index 000000000..6668cf2db
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-8.c
@@ -0,0 +1,19 @@
+/* Origin: Aldy Hernandez  <aldyh@redhat.com>  */
+/* Test rs6000_legitimate_address.  PRE_INC should be invalid.  */
+
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+vector signed short *hannah;
+
+int
+main ()
+{
+  *hannah++ = __builtin_altivec_vspltish (5);
+  *hannah++ = __builtin_altivec_vspltish (6);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-9.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-9.c
new file mode 100644
index 000000000..b34dc1b51
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-9.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec -g" } */
+
+/* PR9564 */
+
+extern int vfork(void);
+
+void
+boom (void)
+{
+  char buf[65536];
+  vfork();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-1.c
new file mode 100644
index 000000000..20d29bf05
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-1.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Basic test for the new VMX intrinsics.  */
+#include <altivec.h>
+
+int f(vector int a, int b)
+{
+  return vec_extract (a, b);
+}
+short f1(vector short a, int b)
+{
+  return vec_extract (a, b);
+}
+vector short f2(vector short a, int b)
+{
+  return vec_insert (b, a, b);
+}
+vector float f3(vector float a, int b)
+{
+  return vec_insert (b, a, b);
+}
+
+float g(void);
+
+vector float f4(float b, int t)
+{
+  return vec_promote (g(), t);
+}
+vector float f5(float b)
+{
+  return vec_splats (g());
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-2.c
new file mode 100644
index 000000000..fdb375c9e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-2.c
@@ -0,0 +1,141 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+/* Test the vec_extract VMX intrinsics.  */
+#include <altivec.h>
+
+extern void abort (void);
+
+vector int a = {0, 1, 2, 3};
+vector short b = {0, 1, 2, 3, 4, 5, 6, 7};
+
+int f(vector int a, int b)
+{
+  return vec_extract (a, b);
+}
+
+int f0 (vector int a)
+{
+  return vec_extract (a, 0);
+}
+int f1 (vector int a)
+{
+  return vec_extract (a, 1);
+}
+int f2 (vector int a)
+{
+  return vec_extract (a, 2);
+}
+int f3 (vector int a)
+{
+  return vec_extract (a, 3);
+}
+int f4 (vector int a)
+{
+  return vec_extract (a, 4);
+}
+
+int g(vector short a, int b)
+{
+  return vec_extract (a, b);
+}
+
+int g0 (vector short a)
+{
+  return vec_extract (a, 0);
+}
+int g1 (vector short a)
+{
+  return vec_extract (a, 1);
+}
+int g2 (vector short a)
+{
+  return vec_extract (a, 2);
+}
+int g3 (vector short a)
+{
+  return vec_extract (a, 3);
+}
+
+int g4 (vector short a)
+{ 
+  return vec_extract (a, 4);
+}
+int g5 (vector short a)
+{ 
+  return vec_extract (a, 5);
+}
+int g6 (vector short a)
+{ 
+  return vec_extract (a, 6);
+}
+int g7 (vector short a)
+{ 
+  return vec_extract (a, 7);
+}
+int g8 (vector short a)
+{ 
+  return vec_extract (a, 8);
+}
+int main1(void) __attribute__((noinline));
+int main1(void)
+{ 
+  int i;
+  /* Check vec_extract with a non constant element numbering */
+  for(i=0;i<10;i++)
+    { 
+      if (f(a, i) != (i&0x3))
+        abort ();
+    }
+  
+  /* Check vec_extract with a constant element numbering */
+  if (f0(a) != 0)
+    abort ();
+  if (f1(a) != 1)
+    abort ();
+  if (f2(a) != 2)
+    abort ();
+  if (f3(a) != 3)
+    abort ();
+  /* Check that vec_extract works with a constant element higher than
+     the number of elements.  */
+  if (f4(a) != 0)
+    abort ();
+
+  /* Check vec_extract with a non constant element numbering */
+  for(i=0;i<10;i++)
+    {
+      if (g(b, i) != (i&0x7))
+        abort ();
+    }
+  
+  /* Check vec_extract with a constant element numbering */
+  if (g0(b) != 0)
+    abort ();
+  if (g1(b) != 1)
+    abort ();
+  if (g2(b) != 2)
+    abort ();
+  if (g3(b) != 3)
+    abort ();
+  if (g4(b) != 4)
+    abort ();
+  if (g5(b) != 5)
+    abort ();
+  if (g6(b) != 6)
+    abort ();
+  if (g7(b) != 7)
+    abort ();
+  /* Check that vec_extract works with a constant element higher than
+     the number of elements.  */
+  if (g8(b) != 0)
+    abort ();
+  
+  return 0;
+}
+
+int main(void)
+{ 
+  return main1 ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-3.c
new file mode 100644
index 000000000..b941ab186
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-3.c
@@ -0,0 +1,37 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+/* Test the vec_splats and vec_promote VMX intrinsics.  */
+#include <altivec.h>
+    
+extern void abort (void);
+        
+vector int a = {0, 0, 0, 0};
+int main1(int t) __attribute__((noinline));
+int main1(int t)
+{ 
+  int i;
+  vector int b = vec_splats(0);
+  if (__builtin_memcmp (&a, &b, sizeof(vector int)))
+    abort ();
+  
+  b = vec_splats(t);
+  if (__builtin_memcmp (&a, &b, sizeof(vector int)))
+    abort ();
+  
+  b = vec_promote(0, 1);
+  if (vec_extract (b, 1) != 0)
+    abort ();
+  
+  b = vec_promote(t, t);
+  if (vec_extract (b, t) != 0)
+    abort ();
+  
+  return 0;
+} 
+    
+int main(void)
+{ 
+  return main1 (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-4.c
new file mode 100644
index 000000000..c694691d4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-4.c
@@ -0,0 +1,42 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Test the vec_splats and vec_promote VMX intrinsics.  */
+#include <altivec.h>
+    
+extern void abort (void);
+        
+vector int a[] = {{0, 0, 0, 0}, {1,0,0,0}, {1,2,0,0},{1,2,3,0},{1,2,3,4},{5,2,3,4},{5,6,3,4}};
+vector int c = {0,6,3,4};
+vector int d = {0,0,3,4};
+int main1(int t) __attribute__((noinline));
+int main1(int t)
+{ 
+  int i;
+  vector int b = vec_splats(0);
+  for(i = 0;i<sizeof(a)/sizeof(a[0])-1;i++)
+    { 
+	if (__builtin_memcmp (&b, &a[i], sizeof(vector int)))
+          abort ();
+        b = vec_insert(i+1, b, i);
+    } 
+  if (__builtin_memcmp (&b, &a[i], sizeof(vector int)))
+    abort ();
+  
+  b = vec_insert(0, b, 0);
+  if (__builtin_memcmp (&b, &c, sizeof(vector int)))
+    abort ();
+  
+  b = vec_insert(0, b, 1);
+  if (__builtin_memcmp (&b, &d, sizeof(vector int)))
+    abort ();
+  
+  return 0;
+} 
+  
+int main(void)
+{
+  return main1 (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-5.c
new file mode 100644
index 000000000..95f109d1a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-5.c
@@ -0,0 +1,25 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Basic test for the new VMX intrinsics and error messages.  */
+#include <altivec.h>
+
+int main(int argc, char **argv)
+{
+vector float t;
+    vec_promote();                      /* { dg-error "vec_promote only accepts 2" } */
+    vec_promote(1.0f);                  /* { dg-error "vec_promote only accepts 2" } */
+    vec_promote(1.0f, 2, 3);            /* { dg-error "vec_promote only accepts 2" } */
+    vec_extract ();                     /* { dg-error "vec_extract only accepts 2" } */
+    vec_extract (t);                    /* { dg-error "vec_extract only accepts 2" } */
+    vec_extract (t, 2);
+    vec_extract (t, 2, 5, 6);           /* { dg-error "vec_extract only accepts 2" } */
+    vec_splats ();                      /* { dg-error "vec_splats only accepts 1" } */
+    vec_splats (t, 3);                  /* { dg-error "vec_splats only accepts 1" } */
+    vec_insert ();                      /* { dg-error "vec_insert only accepts 3" } */
+    vec_insert (t);                     /* { dg-error "vec_insert only accepts 3" } */
+    vec_insert (t, 3);                  /* { dg-error "vec_insert only accepts 3" } */
+    vec_insert (t, 3, 2, 4, 6, 6);      /* { dg-error "vec_insert only accepts 3" } */
+    return 0;
+}  
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-6.c
new file mode 100644
index 000000000..5d62f18e1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-6.c
@@ -0,0 +1,12 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */
+#include <altivec.h>
+
+/* This used to ICE with reloading of a constant address. */
+
+vector float f(void)
+{
+  vector float * a = (void*)16;
+  return vec_lvlx (0, a);
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-7.c
new file mode 100644
index 000000000..ae7769400
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-7.c
@@ -0,0 +1,28 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "vor" 2 } } */
+#include <altivec.h>
+
+/* Make sure that lvlx and lvrx are not combined into one insn and
+   we still get a vor. */
+
+vector unsigned char
+lvx_float (long off, float *p)
+{
+    vector unsigned char l, r;
+
+    l = (vector unsigned char) vec_lvlx (off, p);
+    r = (vector unsigned char) vec_lvrx (off, p);
+    return vec_or(l, r);
+}
+
+vector unsigned char
+lvxl_float (long off, float *p)
+{
+    vector unsigned char l, r;
+
+    l = (vector unsigned char) vec_lvlxl (off, p);
+    r = (vector unsigned char) vec_lvrxl (off, p);
+    return vec_or(l, r);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-8.c
new file mode 100644
index 000000000..dda5eb0c1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-cell-8.c
@@ -0,0 +1,57 @@
+/* { dg-do run { target { powerpc*-*-* && cell_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! cell_hw } } } } */
+/* { dg-require-effective-target powerpc_ppu_ok } */
+/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */
+#include <altivec.h>
+#include <string.h>
+
+extern void abort (void);
+
+typedef short int sint16;
+typedef signed char int8;
+
+int main1(void) __attribute__((noinline));
+int main1(void)
+{
+    sint16 test_vector[4] = { 1678, -2356, 19246, -17892 };
+    int8 test_dst[128] __attribute__(( aligned( 16 )));
+    float test_out[4] __attribute__(( aligned( 16 )));
+    int p;
+
+    for( p = 0; p < 24; ++p )
+    {
+        memset( test_dst, 0, 128 );
+        memcpy( &test_dst[p], test_vector, 8 );
+        {
+            vector float VR, VL, V;
+   /* load the righthand section of the misaligned vector */
+            VR = (vector float) vec_lvrx( 8, &test_dst[p] );
+            VL = (vector float) vec_lvlx( 0, &test_dst[p] );
+   /* Vector Shift Left Double by Octet Immediate, move the right hand section into the bytes */
+            VR = vec_vsldoi( VR, VR, 2 << 2 ); 
+   /* or those two together */
+            V = vec_vor( VL, VR );
+   /* sign extend */
+            V = (vector float) vec_vupkhsh((vector bool short)V );
+   /* fixed to float by S16_SHIFT_BITS bits */
+            V = (vector float) vec_vcfsx ((vector signed int)V, 5 ); 
+
+            vec_stvx( V, 0, &test_out[0] );
+            if (test_out[0] != 52.437500)
+                abort ();
+            if (test_out[1] != -73.625000)
+                abort ();
+            if (test_out[2] != 601.437500)
+                abort ();
+            if (test_out[3] != -559.125000)
+                abort ();
+        }
+    }
+return 0;
+}
+
+
+int main(void)
+{
+  return main1();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-consts.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-consts.c
new file mode 100644
index 000000000..2c5bc99cf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-consts.c
@@ -0,0 +1,318 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec -O2" } */
+
+/* Check that "easy" AltiVec constants are correctly synthesized.  */
+
+extern void abort (void);
+
+typedef __attribute__ ((vector_size (16))) unsigned char v16qi;
+typedef __attribute__ ((vector_size (16))) unsigned short v8hi;
+typedef __attribute__ ((vector_size (16))) unsigned int v4si;
+
+char w[16] __attribute__((aligned(16)));
+ 
+
+/* Emulate the vspltis? instructions on a 16-byte array of chars.  */
+
+void vspltisb (char *v, int val)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    v[i] = val;
+}
+
+void vspltish (char *v, int val)
+{
+  int i;
+  for (i = 0; i < 16; i += 2)
+    v[i] = val >> 7, v[i + 1] = val;
+}
+
+void vspltisw (char *v, int val)
+{
+  int i;
+  for (i = 0; i < 16; i += 4)
+    v[i] = v[i + 1] = v[i + 2] = val >> 7, v[i + 3] = val;
+}
+
+
+/* Use three different check functions for each mode-instruction pair.
+   The callers have no typecasting and no addressable vectors, to make
+   the test more robust.  */
+
+void __attribute__ ((noinline)) check_v16qi (v16qi v1, char *v2)
+{
+  if (memcmp (&v1, v2, 16))
+    abort ();
+}
+
+void __attribute__ ((noinline)) check_v8hi (v8hi v1, char *v2)
+{
+  if (memcmp (&v1, v2, 16))
+    abort ();
+}
+
+void __attribute__ ((noinline)) check_v4si (v4si v1, char *v2)
+{
+  if (memcmp (&v1, v2, 16))
+    abort ();
+}
+
+
+/* V16QI tests.  */
+
+void v16qi_vspltisb ()
+{
+  v16qi v = { 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15 };
+  vspltisb (w, 15);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltisb_neg ()
+{
+  v16qi v = { -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5 };
+  vspltisb (w, -5);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltisb_addself ()
+{
+  v16qi v = { 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30 };
+  vspltisb (w, 30);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltisb_neg_addself ()
+{
+  v16qi v = { -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24 };
+  vspltisb (w, -24);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltish ()
+{
+  v16qi v = { 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15 };
+  vspltish (w, 15);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltish_addself ()
+{
+  v16qi v = { 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30 };
+  vspltish (w, 30);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltish_neg ()
+{
+  v16qi v = { -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5 };
+  vspltish (w, -5);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltisw ()
+{
+  v16qi v = { 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15 };
+  vspltisw (w, 15);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltisw_addself ()
+{
+  v16qi v = { 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30 };
+  vspltisw (w, 30);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltisw_neg ()
+{
+  v16qi v = { -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5 };
+  vspltisw (w, -5);
+  check_v16qi (v, w);
+}
+
+
+/* V8HI tests. */
+
+void v8hi_vspltisb ()
+{
+  v8hi v = { 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F };
+  vspltisb (w, 15);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltisb_addself ()
+{
+  v8hi v = { 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E };
+  vspltisb (w, 30);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltisb_neg ()
+{
+  v8hi v = { 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB };
+  vspltisb (w, -5);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltish ()
+{
+  v8hi v = { 15, 15, 15, 15, 15, 15, 15, 15 };
+  vspltish (w, 15);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltish_neg ()
+{
+  v8hi v = { -5, -5, -5, -5, -5, -5, -5, -5 };
+  vspltish (w, -5);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltish_addself ()
+{
+  v8hi v = { 30, 30, 30, 30, 30, 30, 30, 30 };
+  vspltish (w, 30);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltish_neg_addself ()
+{
+  v8hi v = { -24, -24, -24, -24, -24, -24, -24, -24 };
+  vspltish (w, -24);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltisw ()
+{
+  v8hi v = { 0, 15, 0, 15, 0, 15, 0, 15 };
+  vspltisw (w, 15);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltisw_addself ()
+{
+  v8hi v = { 0, 30, 0, 30, 0, 30, 0, 30 };
+  vspltisw (w, 30);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltisw_neg ()
+{
+  v8hi v = { -1, -5, -1, -5, -1, -5, -1, -5 };
+  vspltisw (w, -5);
+  check_v8hi (v, w);
+}
+
+/* V4SI tests. */
+
+void v4si_vspltisb ()
+{
+  v4si v = { 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F };
+  vspltisb (w, 15);
+  check_v4si (v, w);
+}
+
+void v4si_vspltisb_addself ()
+{
+  v4si v = { 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E };
+  vspltisb (w, 30);
+  check_v4si (v, w);
+}
+
+void v4si_vspltisb_neg ()
+{
+  v4si v = { 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB };
+  vspltisb (w, -5);
+  check_v4si (v, w);
+}
+
+void v4si_vspltish ()
+{
+  v4si v = { 0x000F000F, 0x000F000F, 0x000F000F, 0x000F000F };
+  vspltish (w, 15);
+  check_v4si (v, w);
+}
+
+void v4si_vspltish_addself ()
+{
+  v4si v = { 0x001E001E, 0x001E001E, 0x001E001E, 0x001E001E };
+  vspltish (w, 30);
+  check_v4si (v, w);
+}
+
+void v4si_vspltish_neg ()
+{
+  v4si v = { 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB };
+  vspltish (w, -5);
+  check_v4si (v, w);
+}
+
+void v4si_vspltisw ()
+{
+  v4si v = { 15, 15, 15, 15 };
+  vspltisw (w, 15);
+  check_v4si (v, w);
+}
+
+void v4si_vspltisw_neg ()
+{
+  v4si v = { -5, -5, -5, -5 };
+  vspltisw (w, -5);
+  check_v4si (v, w);
+}
+
+void v4si_vspltisw_addself ()
+{
+  v4si v = { 30, 30, 30, 30 };
+  vspltisw (w, 30);
+  check_v4si (v, w);
+}
+
+void v4si_vspltisw_neg_addself ()
+{
+  v4si v = { -24, -24, -24, -24 };
+  vspltisw (w, -24);
+  check_v4si (v, w);
+}
+
+
+
+int main ()
+{
+  v16qi_vspltisb ();
+  v16qi_vspltisb_neg ();
+  v16qi_vspltisb_addself ();
+  v16qi_vspltisb_neg_addself ();
+  v16qi_vspltish ();
+  v16qi_vspltish_addself ();
+  v16qi_vspltish_neg ();
+  v16qi_vspltisw ();
+  v16qi_vspltisw_addself ();
+  v16qi_vspltisw_neg ();
+
+  v8hi_vspltisb ();
+  v8hi_vspltisb_addself ();
+  v8hi_vspltisb_neg ();
+  v8hi_vspltish ();
+  v8hi_vspltish_neg ();
+  v8hi_vspltish_addself ();
+  v8hi_vspltish_neg_addself ();
+  v8hi_vspltisw ();
+  v8hi_vspltisw_addself ();
+  v8hi_vspltisw_neg ();
+
+  v4si_vspltisb ();
+  v4si_vspltisb_addself ();
+  v4si_vspltisb_neg ();
+  v4si_vspltish ();
+  v4si_vspltish_addself ();
+  v4si_vspltish_neg ();
+  v4si_vspltisw ();
+  v4si_vspltisw_neg ();
+  v4si_vspltisw_addself ();
+  v4si_vspltisw_neg_addself ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-macros.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-macros.c
new file mode 100644
index 000000000..c07eaa36a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-macros.c
@@ -0,0 +1,64 @@
+/* Copyright (C) 2007 Free Software Foundation, Inc.  */
+
+/* { dg-do preprocess } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Conditional macros should not be expanded by pragmas.  */
+#pragma __vector
+_Pragma ("__vector")
+
+/* Redefinition of conditional macros.  */
+/* No warning should be generated.  */
+
+#define __vector __new_vector
+#define __pixel __new_pixel
+#define __bool __new_bool
+#define vector new_vector
+#define pixel new_pixel
+#define bool new_bool
+
+/* Definition of conditional macros.  */
+/* No warning should be generated.  */
+
+#undef __vector
+#define __vector __new_vector
+
+#undef __pixel
+#define __pixel __new_pixel
+
+#undef __bool
+#define __bool __new_bool
+
+#undef vector
+#define vector new_vector
+
+#undef pixel
+#define pixel new_pixel
+
+#undef bool
+#define bool new_bool
+
+/* Re-definition of "unconditional" macros.  */
+/* Warnings should be generated as usual.  */
+
+#define __vector	__newer_vector
+#define __pixel		__newer_pixel
+#define __bool		__newer_bool
+#define vector		newer_vector
+#define pixel		newer_pixel
+#define bool		newer_bool
+
+/* { dg-warning "redefined" "__vector redefined"  { target *-*-* } 45 } */
+/* { dg-warning "redefined" "__pixel redefined"   { target *-*-* } 46 } */
+/* { dg-warning "redefined" "__bool redefined"    { target *-*-* } 47 } */
+/* { dg-warning "redefined" "vector redefined"    { target *-*-* } 48 } */
+/* { dg-warning "redefined" "pixel redefined"     { target *-*-* } 49 } */
+/* { dg-warning "redefined" "bool redefined"      { target *-*-* } 50 } */
+
+/* { dg-message "location of the previous"  "prev __vector defn"  { target *-*-* } 25 } */
+/* { dg-message "location of the previous"  "prev __pixel defn"   { target *-*-* } 28 } */
+/* { dg-message "location of the previous"  "prev __bool defn"    { target *-*-* } 31 } */
+/* { dg-message "location of the previous"  "prev vector defn"    { target *-*-* } 34 } */
+/* { dg-message "location of the previous"  "prev pixel defn"     { target *-*-* } 37 } */
+/* { dg-message "location of the previous"  "prev bool defn"      { target *-*-* } 40 } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-pr22085.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-pr22085.c
new file mode 100644
index 000000000..a7b81bbad
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-pr22085.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -fpreprocessed" } */
+
+/* Program to test AltiVec with -fpreprocessed.  */
+int foo(__attribute__((altivec(vector__))) float x,
+        __attribute__((altivec(vector__))) float y)
+{
+  if (__builtin_vec_vcmpeq_p (2, (x), (y)))
+    return 3245;
+  else
+    return 12;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-splat.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-splat.c
new file mode 100644
index 000000000..91ab72d78
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-splat.c
@@ -0,0 +1,49 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec -O2" } */
+
+/* Testcase by Richard Guenther and Steven Bosscher.
+   Check that "easy" AltiVec constants are correctly synthesized
+   if they need to be reloaded.  */
+
+typedef __attribute__ ((vector_size (16))) unsigned char v16qi;
+typedef __attribute__ ((vector_size (16))) unsigned short v8hi;
+typedef __attribute__ ((vector_size (16))) unsigned int v4si;
+
+#define REGLIST								\
+  "77",  "78",  "79",  "80",  "81",  "82",  "83",  "84",  "85",  "86",	\
+  "87",  "88",  "89",  "90",  "91",  "92",  "93",  "94",  "95",  "96",	\
+  "97",  "98",  "99", "100", "101", "102", "103", "104", "105", "106",	\
+ "107", "108"
+
+
+#define TEST(a, result, b)				\
+  void a##_##b (int h)					\
+  {							\
+    volatile a tmp;					\
+    while (h-- > 0)					\
+      {							\
+        asm ("" : : : REGLIST);				\
+        tmp = (a) (result) __builtin_altivec_##b (5);	\
+      }							\
+  }							\
+							\
+  void a##_##b##_neg (int h)				\
+  {							\
+    volatile a tmp;					\
+    while (h-- > 0)					\
+      {							\
+        asm ("" : : : REGLIST);				\
+        tmp = (a) (result) __builtin_altivec_##b (-5);	\
+      }							\
+  }
+
+TEST(v16qi, v16qi, vspltisb)
+TEST(v16qi, v8hi, vspltish)
+TEST(v16qi, v4si, vspltisw)
+TEST(v8hi, v16qi, vspltisb)
+TEST(v8hi, v8hi, vspltish)
+TEST(v8hi, v4si, vspltisw)
+TEST(v4si, v16qi, vspltisb)
+TEST(v4si, v8hi, vspltish)
+TEST(v4si, v4si, vspltisw)
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c
new file mode 100644
index 000000000..41de95225
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c
@@ -0,0 +1,91 @@
+/* { dg-do compile { target powerpc*-*-linux* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Valid AltiVec vector types should be accepted with no warnings.  */
+
+__vector char vc;
+__vector unsigned char vuc;
+__vector signed char vsc;
+__vector __bool char vbc;
+__vector short vh;
+__vector signed short vsh;
+__vector unsigned short vuh;
+__vector short int vhi;
+__vector signed short int vshi;
+__vector unsigned short int vuhi;
+__vector __bool short vbh;
+__vector __bool short int vbhi;
+__vector int vi;
+__vector unsigned int vui;
+__vector signed int vsi;
+__vector __bool int vbi;
+__vector unsigned vuj;
+__vector signed vsj;
+__vector __bool vbj;
+__vector float vf;
+__vector _Bool vb;
+
+/* These should be rejected as invalid AltiVec types.  */
+
+__vector long long vll;			/* { dg-error "AltiVec types" "" } */
+__vector unsigned long long vull;	/* { dg-error "AltiVec types" "" } */
+__vector signed long long vsll;		/* { dg-error "AltiVec types" "" } */
+__vector __bool long long vbll;		/* { dg-error "AltiVec types" "" } */
+__vector long long int vlli;		/* { dg-error "AltiVec types" "" } */
+__vector unsigned long long int vulli;	/* { dg-error "AltiVec types" "" } */
+__vector signed long long int vslli;	/* { dg-error "AltiVec types" "" } */
+__vector __bool long long int vblli;	/* { dg-error "AltiVec types" "" } */
+__vector double vd1;			/* { dg-error "AltiVec types" "" } */
+__vector long double vld;		/* { dg-error "AltiVec types" "" } */
+__vector _Complex float vcf;		/* { dg-error "AltiVec types" "" } */
+__vector _Complex double vcd;		/* { dg-error "AltiVec types" "" } */
+__vector _Complex long double vcld;	/* { dg-error "AltiVec types" "" } */
+__vector _Complex signed char vcsc;	/* { dg-error "AltiVec types" "" } */
+__vector _Complex unsigned char vcuc;	/* { dg-error "AltiVec types" "" } */
+__vector _Complex short vcss;		/* { dg-error "AltiVec types" "" } */
+__vector _Complex unsigned short vcus;	/* { dg-error "AltiVec types" "" } */
+__vector _Complex int vcsi;		/* { dg-error "AltiVec types" "" } */
+__vector _Complex unsigned int vcui;	/* { dg-error "AltiVec types" "" } */
+__vector _Complex long vcsl;		/* { dg-error "AltiVec types" "" } */
+__vector _Complex unsigned long vcul;	/* { dg-error "AltiVec types" "" } */
+__vector _Complex long long vcsll;	/* { dg-error "AltiVec types" "" } */
+__vector _Complex unsigned long long vcull; /* { dg-error "AltiVec types" "" } */
+__vector __complex float v_cf;		/* { dg-error "AltiVec types" "" } */
+__vector __complex double v_cd;		/* { dg-error "AltiVec types" "" } */
+__vector __complex long double v_cld;	/* { dg-error "AltiVec types" "" } */
+__vector __complex signed char v_csc;	/* { dg-error "AltiVec types" "" } */
+__vector __complex unsigned char v_cuc;	/* { dg-error "AltiVec types" "" } */
+__vector __complex short v_css;		/* { dg-error "AltiVec types" "" } */
+__vector __complex unsigned short v_cus; /* { dg-error "AltiVec types" "" } */
+__vector __complex int v_csi;		/* { dg-error "AltiVec types" "" } */
+__vector __complex unsigned int v_cui;	/* { dg-error "AltiVec types" "" } */
+__vector __complex long v_csl;		/* { dg-error "AltiVec types" "" } */
+__vector __complex unsigned long v_cul;	/* { dg-error "AltiVec types" "" } */
+__vector __complex long long v_csll;	/* { dg-error "AltiVec types" "" } */
+__vector __complex unsigned long long v_cull; /* { dg-error "AltiVec types" "" } */
+
+/* These should be rejected because the component types are invalid.  We
+   don't care about the actual error messages here.  */
+
+__vector __bool unsigned char vbuc;	/* { dg-error "" "" } */
+__vector __bool signed char vbsc;	/* { dg-error "" "" } */
+__vector __bool unsigned short vbuh;	/* { dg-error "" "" } */
+__vector __bool signed short vbsh;	/* { dg-error "" "" } */
+__vector __bool unsigned int vbui;	/* { dg-error "" "" } */
+__vector __bool signed int vbsi;	/* { dg-error "" "" } */
+__vector __bool unsigned vbuj;		/* { dg-error "" "" } */
+__vector __bool signed vbsj;		/* { dg-error "" "" } */
+__vector signed float vsf;		/* { dg-error "" "" } */
+__vector unsigned float vuf;		/* { dg-error "" "" } */
+__vector short float vsf;		/* { dg-error "" "" } */
+__vector signed double vsd;		/* { dg-error "" "" } */
+__vector unsigned double vud;		/* { dg-error "" "" } */
+__vector short double vsd;		/* { dg-error "" "" } */
+__vector __bool float vbf;		/* { dg-error "" "" } */
+__vector __bool double vbd;		/* { dg-error "" "" } */
+__vector __bool short float blf;	/* { dg-error "" "" } */
+__vector __bool short double vlbd;	/* { dg-error "" "" } */
+
+/* { dg-message "note: previous" "prev vsf" { target *-*-* } 79 } */
+/* { dg-message "note: previous" "prev vsd" { target *-*-* } 82 } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c
new file mode 100644
index 000000000..f64c0c5aa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target powerpc*-*-linux* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* These should get warnings for 32-bit code.  */
+
+__vector long vl;			/* { dg-warning "deprecated" "" } */
+__vector unsigned long vul;		/* { dg-warning "deprecated" "" } */
+__vector signed long vsl;		/* { dg-warning "deprecated" "" } */
+__vector __bool long int vbli;		/* { dg-warning "deprecated" "" } */
+__vector long int vli;			/* { dg-warning "deprecated" "" } */
+__vector unsigned long int vuli;	/* { dg-warning "deprecated" "" } */
+__vector signed long int vsli;		/* { dg-warning "deprecated" "" } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c
new file mode 100644
index 000000000..38c4d6c16
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target powerpc*-*-linux* } } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* These should be rejected for 64-bit code.  */
+
+__vector long vl;			/* { dg-error "invalid for 64" "" } */
+__vector unsigned long vul;		/* { dg-error "invalid for 64" "" } */
+__vector signed long vsl;		/* { dg-error "invalid for 64" "" } */
+__vector __bool long int vbli;		/* { dg-error "invalid for 64" "" } */
+__vector long int vli;			/* { dg-error "invalid for 64" "" } */
+__vector unsigned long int vuli;	/* { dg-error "invalid for 64" "" } */
+__vector signed long int vsli;		/* { dg-error "invalid for 64" "" } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c
new file mode 100644
index 000000000..212f67339
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target powerpc*-*-linux* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mno-warn-altivec-long" } */
+
+/* These should not get warnings for 32-bit code when the warning is
+   disabled.  */
+
+__vector long vl;
+__vector unsigned long vul;
+__vector signed long vsl;
+__vector __bool long int vbli;
+__vector long int vli;
+__vector unsigned long int vuli;
+__vector signed long int vsli;
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-varargs-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-varargs-1.c
new file mode 100644
index 000000000..1349ae590
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-varargs-1.c
@@ -0,0 +1,82 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec -fno-inline" } */
+
+#include <stdarg.h>
+
+extern void exit (int);
+extern void abort (void);
+
+#define vector __attribute__((vector_size (16)))
+
+const vector unsigned int v1 = {10,11,12,13};
+const vector unsigned int v2 = {20,21,22,23};
+const vector unsigned int v3 = {30,31,32,33};
+const vector unsigned int v4 = {40,41,42,43};
+
+void foo(vector unsigned int a, ...)
+{
+  va_list args;
+  vector unsigned int v;
+
+  va_start (args, a);
+  if (memcmp (&a, &v1, sizeof (v)) != 0)
+    abort ();
+  v = va_arg (args, vector unsigned int);
+  if (memcmp (&v, &v2, sizeof (v)) != 0)
+    abort ();
+  v = va_arg (args, vector unsigned int);
+  if (memcmp (&v, &v3, sizeof (v)) != 0)
+    abort ();
+  v = va_arg (args, vector unsigned int);
+  if (memcmp (&v, &v4, sizeof (v)) != 0)
+    abort ();
+  va_end (args);
+}
+
+void bar(vector unsigned int a, ...)
+{
+  va_list args;
+  vector unsigned int v;
+  int b;
+
+  va_start (args, a);
+  if (memcmp (&a, &v1, sizeof (v)) != 0)
+    abort ();
+  b = va_arg (args, int);
+  if (b != 2)
+    abort ();
+  v = va_arg (args, vector unsigned int);
+  if (memcmp (&v, &v2, sizeof (v)) != 0)
+    abort ();
+  v = va_arg (args, vector unsigned int);
+  if (memcmp (&v, &v3, sizeof (v)) != 0)
+    abort ();
+  va_end (args);
+}
+
+
+int main1(void)
+{
+  /* In this call, in the Darwin ABI, the first argument goes into v2
+     the second one into r9-r10 and memory,
+     and the next two in memory.  */
+  foo ((vector unsigned int){10,11,12,13},
+       (vector unsigned int){20,21,22,23},
+       (vector unsigned int){30,31,32,33},
+       (vector unsigned int){40,41,42,43});
+  /* In this call, in the Darwin ABI, the first argument goes into v2
+     the second one into r9, then r10 is reserved and
+     there are two words of padding in memory, and the next two arguments
+     go after the padding.  */
+  bar ((vector unsigned int){10,11,12,13}, 2,
+       (vector unsigned int){20,21,22,23},
+       (vector unsigned int){30,31,32,33});
+  return 0;
+}
+
+int main (void)
+{
+  return main1 ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c
new file mode 100644
index 000000000..3689f9749
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c
@@ -0,0 +1,605 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+int printf(const char * , ...);
+extern void abort();
+
+void foo(char *bS, char *bS_edge, int field_MBAFF, int top){
+  char intra[16]       __attribute__ ((aligned(16)));
+  signed short mv_const[8] __attribute__((aligned(16)));
+  
+  vector signed short v_three, v_ref_mask00, v_ref_mask01, v_vec_maskv, v_vec_maskh;
+  vector unsigned char v_permv, v_permh, v_bS, v_bSh, v_bSv, v_cbp_maskv, v_cbp_maskvn, v_cbp_maskh, v_cbp_maskhn, v_intra_maskh, v_intra_maskv, v_intra_maskhn, v_intra_maskvn;
+  vector unsigned char tmp7, tmp8, tmp9, tmp10, v_c1, v_cbp1, v_cbp2, v_pocl, v_poch;
+  vector signed short v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
+  vector signed short idx0;
+  vector signed short tmp00, tmp01, tmp02, tmp03;
+  vector unsigned char v_zero   = (vector unsigned char) {'a','b','c','d','e','f','g','h','i','j','k','l','m','n','o','p'};
+  v_three  = (vector signed short) vec_ld (0, (vector signed short *) mv_const);
+
+  vector unsigned char v_coef_mask = vec_ld(0, (vector unsigned char *)mv_const);
+  vector unsigned char v_coef_mask_hi = vec_splat(v_coef_mask, 0);
+  vector unsigned char v_coef_mask_lo = vec_splat(v_coef_mask, 1);
+  v_coef_mask = vec_sld(v_coef_mask_hi, v_coef_mask_lo, 8);
+  vector unsigned char v_bit_mask = vec_sub(vec_splat_u8(7), vec_lvsl(0, (unsigned char *)0));
+  v_bit_mask  = vec_sld(vec_sld(v_bit_mask, v_bit_mask, 8), v_bit_mask, 8);
+  v_bit_mask  = vec_sl(vec_splat_u8(1), v_bit_mask);
+  tmp5        = (vector signed short) vec_and(v_coef_mask, v_bit_mask);
+
+  intra[0] = 1;
+  tmp8     = vec_ld (0, (vector unsigned char *) intra);
+  tmp9     = vec_ld (0, (vector unsigned char *) mv_const);
+  tmp10    = vec_ld (0, (vector unsigned char *) mv_const);
+  v_permv  = vec_ld (0, (vector unsigned char *) mv_const);
+  v_permh  = vec_ld (0, (vector unsigned char *) mv_const);
+  tmp6     = vec_ld (0, (vector signed short *) mv_const);
+
+  tmp8     = vec_splat((vector unsigned char) tmp8, 0);
+  tmp9     = vec_splat((vector unsigned char) tmp9, 12);
+  tmp10    = vec_splat((vector unsigned char) tmp10, 12);
+  tmp9     = vec_sld ((vector unsigned char) tmp9,(vector unsigned char) tmp8, 12);
+  tmp10    = vec_sld ((vector unsigned char) tmp10, (vector unsigned char) tmp8, 12);
+  v_intra_maskv  = vec_or (tmp9, tmp8);
+  v_intra_maskh  = vec_or (tmp10, tmp8);
+  v_intra_maskv  = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_intra_maskv, (vector unsigned char) v_zero);
+  v_intra_maskh  = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_intra_maskh, (vector unsigned char) v_zero);
+
+  tmp9   = vec_lvsl (4 + (top<<2), (unsigned char *) 0x0);
+  v_cbp1 = vec_perm ((vector unsigned char) tmp6, (vector unsigned char) tmp6, tmp9);
+  v_cbp2 = (vector unsigned char) vec_perm ((vector unsigned char) tmp5, (vector unsigned char) tmp5, (vector unsigned char) v_permv);
+  v_cbp1 = (vector unsigned char) vec_sld  ((vector unsigned char) v_cbp1,(vector unsigned char) v_cbp2, 12);
+  v_cbp_maskv = vec_or (v_cbp1, v_cbp2);
+
+  tmp9   = vec_lvsl (12 + (top<<2), (unsigned char *) 0x0);
+  v_cbp1 = vec_perm ((vector unsigned char) tmp6, (vector unsigned char) tmp6, tmp9);
+  v_cbp2 = (vector unsigned char) vec_perm ((vector unsigned char) tmp5, (vector unsigned char) tmp5, (vector unsigned char) v_permh);
+  v_cbp1 = (vector unsigned char) vec_sld  ((vector unsigned char) v_cbp1,(vector unsigned char) v_cbp2, 12);
+  v_cbp_maskh = vec_or (v_cbp1, v_cbp2);
+
+  v_cbp_maskv = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_cbp_maskv, (vector unsigned char) v_zero);
+  v_cbp_maskh = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_cbp_maskh, (vector unsigned char) v_zero);
+
+  intra[0]  =0; 
+  intra[1]  =1;
+  intra[2]  =2;
+  intra[3]  =3;
+  intra[4]  =4;
+  intra[5]  = 5;
+  intra[6]  =6;
+  intra[7]  =7;
+  intra[8]  =8;
+  intra[9]  =9;
+  intra[10] =9;
+  intra[11] =9;
+  intra[12] = 0xff;
+
+  idx0   = vec_ld (0, (signed short *) intra);
+  
+  v_c1   = (vector unsigned char)  {'1','2','3','4','5','6','7','8','1','2','3','4','5','6','7','8'};
+
+  if (field_MBAFF){
+    v0   = (vector signed short) vec_and ((vector unsigned char) idx0, v_c1);
+    idx0 = (vector signed short) vec_sra ((vector unsigned char) idx0, v_c1);
+
+    v1   = vec_sld (v0, v0, 15);
+    v1   = (vector signed short) vec_pack (v1, v0);
+    
+    v2   = vec_sld (v1, v1, 2);
+    v3   = vec_sld (v1, v1, 10);
+    
+    v4   = (vector signed short) vec_cmpeq ((vector signed char) v1, (vector signed char) v2);
+    v5   = (vector signed short) vec_cmpeq ((vector signed char) v1, (vector signed char) v3);
+    v6   = (vector signed short) vec_cmpeq ((vector signed char) v2, (vector signed char) v3);
+  }
+  else  {
+    v4 = v5 = v6 = (vector signed short) vec_nor (v_zero, v_zero);
+  }
+
+  tmp1   = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1);
+  v_c1   = vec_mergeh ((vector unsigned char) v_zero, v_c1);
+  tmp1   = (vector signed short) vec_add (tmp1, (vector signed short) v_c1); 
+
+  v_pocl = vec_ld (0, (vector unsigned char *) mv_const);
+  v_poch = vec_ld (0, (vector unsigned char *) mv_const);
+  tmp2   = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1);      
+
+  v_pocl = vec_ld (0,  (vector unsigned char *) mv_const);
+  v_poch = vec_ld (16, (vector unsigned char *) mv_const);
+  tmp1   = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1);
+  tmp1   = vec_sel (tmp1, tmp2, (vector unsigned short) {0xffff,0xffff,0,0,0,0,0,0});
+
+  tmp3   = (vector signed short) vec_splat ((vector unsigned char) idx0, 12);
+  v_c1   = (vector unsigned char) vec_nor (v_zero, v_zero);
+  tmp0   = (vector signed short) vec_cmpeq ((vector signed char) idx0, (vector signed char) v_c1);
+  tmp1   = vec_sel (tmp1, (vector signed short) tmp3, (vector unsigned short) tmp0);
+
+  tmp2   = vec_sld (tmp1, tmp1, 15);
+  tmp1   = (vector signed short) vec_pack (tmp2, tmp1);
+  
+  tmp2   = vec_sld (tmp1, tmp1, 2);
+  tmp3   = vec_sld (tmp1, tmp1, 10);
+
+  tmp0   = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp2);
+  tmp4   = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp3);
+  tmp1   = (vector signed short) vec_cmpeq ((vector signed char) tmp2, (vector signed char) tmp3);
+  tmp0   = vec_and (tmp0, v4);
+  tmp4   = vec_and (tmp4, v5);
+  tmp1   = vec_and (tmp1, v6);
+  tmp2   = vec_sld ((vector signed short) tmp0, (vector signed short) tmp0, 8);
+  tmp3   = vec_sld ((vector signed short) tmp4, (vector signed short) tmp4, 8);
+  tmp5   = vec_sld ((vector signed short) tmp1, (vector signed short) tmp1, 8);
+  tmp0   = vec_and (tmp0, tmp2);
+  tmp4   = vec_and (tmp4, tmp3);
+  tmp1   = vec_and (tmp1, tmp5);
+  v_ref_mask00 = vec_mergeh ((vector signed short) tmp0, (vector signed short) v_c1);
+  v_ref_mask01 = vec_mergeh ((vector signed short) tmp4, (vector signed short) tmp1);
+  v_ref_mask00 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask00, (vector unsigned char) v_ref_mask00);
+  v_ref_mask01 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask01, (vector unsigned char) v_ref_mask01);
+  
+  v0     = vec_ld (0,  (vector signed short *) mv_const);
+  v1     = vec_ld (16, (vector signed short *) mv_const);
+  v4     = vec_ld (64, (vector signed short *) mv_const);
+  v5     = vec_ld (80, (vector signed short *) mv_const);
+  v8     = vec_ld (0,  (vector signed short *) mv_const);
+  v9     = vec_ld (16, (vector signed short *) mv_const);
+
+  tmp0   = (vector signed short) vec_perm ((vector unsigned char) v8, 
+		(vector unsigned char) v8, (vector unsigned char) {0,1,2,3,8,9,10,11,4,5,6,7,12,13,14,15});
+  tmp1   = (vector signed short) vec_mergeh ((vector signed int) v0, (vector signed int) v1);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp3   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp4   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp0   = (vector signed short) vec_perm ((vector unsigned char) v9, (vector unsigned char) v9, 
+			(vector unsigned char) {0,1,2,3,8,9,10,11,4,5,6,7,12,13,14,15});
+  tmp1   = (vector signed short) vec_mergeh ((vector signed int) v4, (vector signed int) v5);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp5   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp6   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 12);
+  tmp6   = vec_sld (tmp4, tmp4, 12);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp00  = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4);
+
+  tmp0   = (vector signed short) vec_mergeh ((vector signed int) v0, (vector signed int) v1);
+  tmp1   = (vector signed short) vec_mergel ((vector signed int) v0, (vector signed int) v1);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp3   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp4   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  
+  tmp0   = (vector signed short) vec_mergeh ((vector signed int) v4, (vector signed int) v5);
+  tmp1   = (vector signed short) vec_mergel ((vector signed int) v4, (vector signed int) v5);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp5   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp6   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 12);
+  tmp6   = vec_sld (tmp4, tmp4, 12);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp01  = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4);
+
+  v2     = vec_ld (32, (vector signed short *) mv_const);
+  v3     = vec_ld (48, (vector signed short *) mv_const);
+  v6     = vec_ld (96, (vector signed short *) mv_const);
+  v7     = vec_ld (112,(vector signed short *) mv_const);
+
+  tmp0   = (vector signed short) vec_mergel ((vector signed int) v0, (vector signed int) v1);
+  tmp1   = (vector signed short) vec_mergeh ((vector signed int) v2, (vector signed int) v3);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp3   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp4   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  
+  tmp0   = (vector signed short) vec_mergel ((vector signed int) v4, (vector signed int) v5);
+  tmp1   = (vector signed short) vec_mergeh ((vector signed int) v6, (vector signed int) v7);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp5   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp6   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 12);
+  tmp6   = vec_sld (tmp4, tmp4, 12);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp02  = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4);
+
+  tmp0   = (vector signed short) vec_mergeh ((vector signed int) v2, (vector signed int) v3);
+  tmp1   = (vector signed short) vec_mergel ((vector signed int) v2, (vector signed int) v3);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp3   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp4   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  
+  tmp0   = (vector signed short) vec_mergeh ((vector signed int) v6, (vector signed int) v7);
+  tmp1   = (vector signed short) vec_mergel ((vector signed int) v6, (vector signed int) v7);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp5   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp6   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 12);
+  tmp6   = vec_sld (tmp4, tmp4, 12);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp03  = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4);
+
+  tmp0   = (vector signed short) vec_pack ((vector unsigned int) tmp00, (vector unsigned int) tmp01);
+  tmp1   = (vector signed short) vec_pack ((vector unsigned int) tmp02, (vector unsigned int) tmp03);
+  tmp2   = (vector signed short) vec_mergeh ((vector signed int) tmp0, (vector signed int) tmp1);
+  tmp3   = (vector signed short) vec_mergel ((vector signed int) tmp0, (vector signed int) tmp1);
+  tmp4   = (vector signed short) vec_mergeh ((vector signed int) tmp2, (vector signed int) tmp3);
+  tmp5   = (vector signed short) vec_mergel ((vector signed int) tmp2, (vector signed int) tmp3);
+  tmp4   = vec_and (v_ref_mask00, tmp4);
+  tmp5   = vec_and (v_ref_mask01, tmp5);
+
+  tmp0   = vec_nor (v_ref_mask00, v_ref_mask01);
+  tmp1   = vec_and (v_ref_mask00, v_ref_mask01);
+  tmp2   = vec_and (tmp4, tmp5);
+  tmp2   = vec_and (tmp2, tmp1);
+  tmp3   = vec_nor (tmp4, tmp5);
+  tmp3   = vec_nor (tmp3, tmp1);
+  v_vec_maskv = vec_or (tmp0, tmp2);
+  v_vec_maskv = vec_or (v_vec_maskv, tmp3);
+
+  intra[0]  = 1; 
+  intra[1]  = 1;
+  intra[2]  = 2;
+  intra[3]  = 3;
+  intra[4]  = 2;
+  intra[5]  = 2;
+  intra[6]  = 2;
+  intra[7]  = 1;
+  intra[8]  = 1;
+  intra[9]  = 5;
+  intra[10] = 5;
+  intra[11] = 5;
+  
+  intra[13] = 0;
+  intra[14] = 0;
+  intra[15] = 0;
+
+  idx0   = vec_ld (0, (signed short *) intra);
+  
+  v_c1   = (vector unsigned char)  {'1','2','3','4','5','6','7','8','1','2','3','4','5','6','7','8'};
+
+  if (field_MBAFF){
+    v8   = (vector signed short) vec_and ((vector unsigned char) idx0, v_c1);
+    idx0 = (vector signed short) vec_sra ((vector unsigned char) idx0, v_c1);
+
+    v9   = vec_sld (v8, v8, 15);
+    v9   = (vector signed short) vec_pack (v9, v8);
+    
+    v10  = vec_sld (v9, v9, 2);
+    v11  = vec_sld (v9, v9, 10);
+    
+    v8   = (vector signed short) vec_cmpeq ((vector signed char) v9, (vector signed char) v10);
+    v9   = (vector signed short) vec_cmpeq ((vector signed char) v9, (vector signed char) v11);
+    v10  = (vector signed short) vec_cmpeq ((vector signed char) v10, (vector signed char) v11);
+  }
+  else  {
+    v8 = v9 = v10 = (vector signed short) vec_nor (v_zero, v_zero);
+  }
+
+  tmp1   = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1);
+  
+if (1){
+	int m;
+	unsigned char toto2[16] __attribute__((aligned(16)));
+	
+	printf("vc1\n");
+	vec_st(v_c1, 0, (unsigned char *) toto2);
+	for (m=0; m<16;m++) {printf("%c ", toto2[m]);}
+	
+	printf("\nv_zero\n");
+	
+	vec_st (v_zero, 0, (unsigned char *) toto2);
+	for (m=0; m< 16; m++) {printf("%c ", toto2[m]);}
+	printf("\n");
+}
+
+  v_c1   = vec_mergeh ((vector unsigned char) v_zero, v_c1);
+  tmp1   = (vector signed short) vec_add (tmp1, (vector signed short) v_c1); 
+
+if (1){
+	vector unsigned char vres = 
+        (vector unsigned char){'a','1','b','2','c','3','d','4','e','5','f','6','g','7','h','8'};
+	unsigned char toto2[16] __attribute__((aligned(16)));
+	int m;
+	
+	printf("vc1\n");
+	vec_st(v_c1, 0, (unsigned char *) toto2);
+	for (m=0; m<16;m++) {printf("%c ", toto2[m]);}
+	printf("\n");
+	if (!vec_all_eq (vres, v_c1))
+	  abort();
+}
+
+  v_pocl = vec_ld (32, (vector unsigned char *) mv_const);
+  v_poch = vec_ld (48, (vector unsigned char *) mv_const);
+  tmp2   = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1);      
+
+  v_pocl = vec_ld (0,  (vector unsigned char *) mv_const);
+  v_poch = vec_ld (16, (vector unsigned char *) mv_const);
+
+  tmp1   = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1);
+ 
+  tmp1   = vec_sel (tmp1, tmp2, (vector unsigned short) {0xffff,0xffff,0,0,0,0,0,0});
+
+
+  tmp3   = (vector signed short) vec_splat ((vector unsigned char) idx0, 12);
+  v_c1   = (vector unsigned char) vec_nor (v_zero, v_zero);
+  tmp0   = (vector signed short) vec_cmpeq ((vector signed char) idx0, (vector signed char) v_c1);
+  tmp1   = vec_sel (tmp1, (vector signed short) tmp3, (vector unsigned short) tmp0);
+
+  tmp2   = vec_sld (tmp1, tmp1, 15);
+  tmp1   = (vector signed short) vec_pack (tmp2, tmp1);
+  
+
+  tmp2   = vec_sld (tmp1, tmp1, 2);
+  tmp3   = vec_sld (tmp1, tmp1, 10);
+
+  tmp0   = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp2);
+  tmp4   = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp3);
+  tmp1   = (vector signed short) vec_cmpeq ((vector signed char) tmp2, (vector signed char) tmp3);
+  tmp0   = vec_and (tmp0, v8);
+  tmp4   = vec_and (tmp4, v9);
+  tmp1   = vec_and (tmp1, v10);
+  tmp2   = vec_sld ((vector signed short) tmp0, (vector signed short) tmp0, 8);
+  tmp3   = vec_sld ((vector signed short) tmp4, (vector signed short) tmp4, 8);
+  tmp5   = vec_sld ((vector signed short) tmp1, (vector signed short) tmp1, 8);
+  tmp0   = vec_and (tmp0, tmp2);
+  tmp4   = vec_and (tmp4, tmp3);
+  tmp1   = vec_and (tmp1, tmp5);
+  v_ref_mask00 = vec_mergeh ((vector signed short) tmp0, (vector signed short) v_c1);
+  v_ref_mask01 = vec_mergeh ((vector signed short) tmp4, (vector signed short) tmp1);
+  v_ref_mask00 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask00, (vector unsigned char) v_ref_mask00);
+  v_ref_mask01 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask01, (vector unsigned char) v_ref_mask01);
+  
+
+  v_permv= vec_ld (0, (vector unsigned char *) mv_const);
+  v8     = vec_ld (0,  (vector signed short *) mv_const);
+  v9     = vec_ld (16, (vector signed short *) mv_const);
+  tmp2   = vec_perm (v0, v0, v_permv);
+  tmp3   = vec_sub (vec_max (v8, v0), vec_min (v8, v0));
+  tmp4   = vec_sub (vec_max (v8, tmp2), vec_min (v8, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  
+  tmp2   = vec_perm (v2, v2, v_permv);
+  tmp5   = vec_sub (vec_max (v9, v2), vec_min (v9, v2));
+  tmp6   = vec_sub (vec_max (v9, tmp2), vec_min (v9, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp00  = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4);
+
+  tmp2   = vec_perm (v1, v1, v_permv);
+  tmp3   = vec_sub (vec_max (v0, v1), vec_min (v0, v1));
+  tmp4   = vec_sub (vec_max (v0, tmp2), vec_min (v0, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  
+  tmp2   = vec_perm (v3, v3, v_permv);
+  tmp5   = vec_sub (vec_max (v2, v3), vec_min (v2, v3));
+  tmp6   = vec_sub (vec_max (v2, tmp2), vec_min (v2, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp01  = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4);
+
+  tmp2   = vec_perm (v4, v4, v_permv);
+  tmp3   = vec_sub (vec_max (v1, v4), vec_min (v1, v4));
+  tmp4   = vec_sub (vec_max (v1, tmp2), vec_min (v1, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  
+  tmp2   = vec_perm (v6, v6, v_permv);
+  tmp5   = vec_sub (vec_max (v3, v6), vec_min (v3, v6));
+  tmp6   = vec_sub (vec_max (v3, tmp2), vec_min (v3, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp02  = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4);
+
+
+  tmp2   = vec_perm (v5, v5, v_permv);
+  tmp3   = vec_sub (vec_max (v4, v5), vec_min (v4, v5));
+  tmp4   = vec_sub (vec_max (v4, tmp2), vec_min (v4, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  
+  tmp2   = vec_perm (v7, v7, v_permv);
+  tmp5   = vec_sub (vec_max (v6, v7), vec_min (v6, v7));
+  tmp6   = vec_sub (vec_max (v6, tmp2), vec_min (v6, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp03  = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4);
+
+  tmp0   = (vector signed short) vec_pack ((vector unsigned short) tmp00, (vector unsigned short) tmp01);
+  tmp1   = (vector signed short) vec_pack ((vector unsigned short) tmp02, (vector unsigned short) tmp03);
+  tmp2   = (vector signed short) vec_mergeh ((vector signed int) tmp0, (vector signed int) tmp1);
+  tmp3   = (vector signed short) vec_mergel ((vector signed int) tmp0, (vector signed int) tmp1);
+  tmp4   = (vector signed short) vec_mergeh ((vector signed int) tmp2, (vector signed int) tmp3);
+  tmp5   = (vector signed short) vec_mergel ((vector signed int) tmp2, (vector signed int) tmp3);
+  tmp4   = vec_and (v_ref_mask00, tmp4);
+  tmp5   = vec_and (v_ref_mask01, tmp5);
+
+  tmp0   = vec_nor (v_ref_mask00, v_ref_mask01);
+  tmp1   = vec_and (v_ref_mask00, v_ref_mask01);
+  tmp2   = vec_and (tmp4, tmp5);
+  tmp2   = vec_and (tmp2, tmp1);
+  tmp3   = vec_nor (tmp4, tmp5);
+  tmp3   = vec_nor (tmp3, tmp1);
+  v_vec_maskh = vec_or (tmp0, tmp2);
+  v_vec_maskh = vec_or (v_vec_maskh, tmp3);
+
+
+  v_intra_maskvn = vec_nor (v_intra_maskv, v_intra_maskv);
+  v_intra_maskhn = vec_nor (v_intra_maskh, v_intra_maskh);
+  v_cbp_maskvn = (vector unsigned char) vec_cmpeq ((vector unsigned char) v_cbp_maskv, (vector unsigned char) v_zero);
+  v_cbp_maskhn = (vector unsigned char) vec_cmpeq ((vector unsigned char) v_cbp_maskh, (vector unsigned char) v_zero);
+
+  v_cbp_maskv  = vec_and (v_cbp_maskv, v_intra_maskvn);
+  v_cbp_maskh  = vec_and (v_cbp_maskh, v_intra_maskhn);
+  v_vec_maskv  = vec_and (v_vec_maskv, (vector signed short) v_intra_maskvn);
+  v_vec_maskv  = vec_and (v_vec_maskv, (vector signed short) v_cbp_maskvn);
+  v_vec_maskh  = vec_and (v_vec_maskh, (vector signed short) v_intra_maskhn);
+  v_vec_maskh  = vec_and (v_vec_maskh, (vector signed short) v_cbp_maskhn);
+
+  tmp9        = vec_splat_u8(2);
+  tmp8        = vec_splat_u8(1);
+  v_bS        = vec_ld (0, (vector unsigned char *) mv_const);
+  
+  v_bSv       = vec_and ((vector unsigned char) v_bS, (vector unsigned char)v_intra_maskv);
+  tmp7        = vec_and ((vector unsigned char)tmp9, (vector unsigned char)v_cbp_maskv);
+  tmp6        = (vector signed short) vec_and ((vector unsigned char)tmp8, (vector unsigned char)v_vec_maskv);
+  tmp7        = vec_or  ((vector unsigned char)tmp7, (vector unsigned char)tmp6);
+  v_bSv       = vec_or  ((vector unsigned char)tmp7, (vector unsigned char)v_bSv);
+
+  v_bS        = vec_ld (0, (vector unsigned char *) mv_const);
+  v_bSh       = vec_and ((vector unsigned char) v_bS, (vector unsigned char)v_intra_maskh);
+  tmp7        = vec_and ((vector unsigned char)tmp9, (vector unsigned char)v_cbp_maskh);
+  tmp6        = (vector signed short) vec_and ((vector unsigned char)tmp8, (vector unsigned char)v_vec_maskh);
+  tmp7        = vec_or  ((vector unsigned char)tmp7, (vector unsigned char)tmp6);
+  v_bSh       = vec_or  ((vector unsigned char)tmp7, (vector unsigned char)v_bSh);
+
+  v_permh     = (vector unsigned char) vec_ld (0 , (vector unsigned char *) mv_const);
+  v_permv     = (vector unsigned char) vec_ld (0, (vector unsigned char *) mv_const);
+  v_bSv       = vec_and (v_bSv, v_permv);
+  v_bSh       = vec_and (v_bSh, v_permh);
+
+  vec_st (v_bSv, 0, (unsigned char *) mv_const);
+  vec_st (v_bSh, 0, (unsigned char *) mv_const);
+
+  v_bSv = vec_mergeh (v_bSv, v_bSv);
+  v_bSv = vec_mergeh (v_bSv, v_bSv);
+  v_bSh = vec_mergeh (v_bSh, v_bSh);
+  v_bSh = vec_mergeh (v_bSh, v_bSh);
+    
+  vec_st (v_bSv, 0, (vector unsigned char *) mv_const);
+  vec_st (v_bSh, 0,(vector unsigned char *) mv_const);
+}
+
+
+int main(int argc, char **argv)
+{
+    char toto[32] __attribute__((aligned(16)));
+
+    foo(toto, toto, 0, 0);
+    return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c
new file mode 100644
index 000000000..594ec88b4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Check that "volatile" type qualifier is propagated to vector type.  */
+
+#include <altivec.h>
+
+vector float *f (volatile vector float *a)
+{
+  return a;  /* { dg-warning "discards qualifiers" } */
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/asm-y.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/asm-y.c
new file mode 100644
index 000000000..7d5a6a617
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/asm-y.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+/* Test that %yN does not cause an internal error if used incorrectly.  */
+
+int f(int *a)
+{
+  asm ("#%y0" : "=m"(a[2])); /* { dg-error "try using the 'Z' constraint" } */
+  asm ("#%y0" : "=m"(a[1])); /* { dg-error "try using the 'Z' constraint" } */
+  asm ("#%y0" : "=m"(a[0]));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c
new file mode 100644
index 000000000..b1b067283
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2 -mavoid-indexed-addresses" } */
+
+/* { dg-final { scan-assembler-not "lbzx" } }
+
+/* Ensure that an indexed load is not generated with
+   -mavoid-indexed-addresses. */
+
+char
+do_one (char *base, unsigned long offset)
+{
+  return base[offset];
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c
new file mode 100644
index 000000000..aa1da5245
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target powerpc_fprs } } */
+/* { dg-options "-O2 -fpic" } */
+double foo (double x) {
+  return x + 1.75;
+}
+/* { dg-final { scan-assembler "lfs" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/compress-float-ppc.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/compress-float-ppc.c
new file mode 100644
index 000000000..312642e68
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/compress-float-ppc.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target powerpc_fprs } } */
+/* { dg-options "-O2" } */
+double foo (double x) {
+  return x + 1.75;
+}
+/* { dg-final { scan-assembler "lfs" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/const-compare.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/const-compare.c
new file mode 100644
index 000000000..c9e50cfbb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/const-compare.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-options "-m64 -O1 -static" } */
+typedef unsigned long long uint64_t;
+
+static int
+match(name, pat)
+ uint64_t *name, *pat;
+{
+ int ok=0, negate_range;
+ uint64_t c, k;
+
+  c = *pat++;
+  switch (c & 0xffffffffffULL) {
+  case ((uint64_t)(('[')|0x8000000000ULL)):
+   if ((negate_range = ((*pat & 0xffffffffffULL) == ((uint64_t)(('!')|0x8000000000ULL)) )) != '\0')
+    ++pat;
+   while (((c = *pat++) & 0xffffffffffULL) )
+    if ((*pat & 0xffffffffffULL) == ((uint64_t)(('-')|0x8000000000ULL))) 
+      {
+       pat += 2;
+      } 
+
+   if (ok == negate_range)
+    return(0);
+   break;
+  }
+ return(*name == '\0');
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c
new file mode 100644
index 000000000..3b13c6236
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-options "-O" } */
+/* { dg-final { scan-assembler "li r3,12345\n\t(bl|jbsr) " } } */
+
+/* Check that zero-size structures don't affect parameter passing.  */
+
+struct empty { };
+extern void foo (struct empty e, int a);
+void bar (void) {
+  struct empty e;
+  foo (e, 12345);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-10.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-10.c
new file mode 100644
index 000000000..68540b8a1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-10.c
@@ -0,0 +1,25 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+struct b
+{
+  long long t;
+  int i;
+};
+
+struct c
+{
+  double d;
+  int i;
+};
+
+struct n
+{
+  long long ll;
+  int tt;
+  struct c d;
+  struct b h;
+  int t;
+};
+int f[sizeof(struct n)!=48?-1:1];
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-11.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-11.c
new file mode 100644
index 000000000..5d01572a8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-11.c
@@ -0,0 +1,31 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+struct A
+{
+  long long a;
+  unsigned char b;
+};
+
+struct D
+{
+  unsigned char y;
+  struct A x;
+  unsigned char z;
+};
+
+struct E
+{
+  long long d;
+  unsigned char e;
+};
+
+struct y
+{
+  struct A b2;
+  struct D b3;
+  struct E b4;
+};
+
+int f[sizeof(struct y)!=56?-1:1];
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c
new file mode 100644
index 000000000..4764831e8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c
@@ -0,0 +1,24 @@
+/* { dg-do run { target powerpc*-*-darwin* } } */
+
+/* You might think you'd need -maltivec for this, but actually you
+   don't; GCC will happily do everything in GPRs, and it still
+   tests that the ABI is correct.  */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#define vector __attribute__((vector_size(16)))
+
+int main(void)
+{
+  vector unsigned int v = { 100, 200, 300, 400 };
+  vector unsigned int w = { 4, 5, 6, 7 };
+  char x[64];
+  sprintf (x, "%lvu,%d,%lvu", v, 1, w);
+  if (strcmp (x, "100 200 300 400,1,4 5 6 7") != 0)
+    {
+      puts (x);
+      abort ();
+    }
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-3.c
new file mode 100644
index 000000000..021abc8fe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+struct f
+{
+  int i;
+  long long ll;
+};
+
+int f[sizeof(struct f)!=12?-1:1];
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-4.c
new file mode 100644
index 000000000..d146c46ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-4.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+struct f
+{
+  long long ll;
+  int i;
+};
+
+int f[sizeof(struct f)!=16?-1:1];
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-5.c
new file mode 100644
index 000000000..4965c5bd8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-5.c
@@ -0,0 +1,30 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+struct A
+{
+  long long a;
+  unsigned char b;
+};
+
+struct B
+{
+  struct A x;
+  unsigned char z;
+};
+
+struct C
+{
+  long d;
+  unsigned char e;
+};
+
+struct z
+{ 
+  struct A b2;
+  struct B b3;
+  struct C b4;
+};
+
+int f[sizeof(struct z)!=48?-1:1];
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-6.c
new file mode 100644
index 000000000..1892e15bc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-6.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+struct a
+{
+  int tt;
+  long long t;
+  int i;
+};
+
+struct g
+{
+  int tt;
+  struct a d;
+  int t;
+};
+
+int f[sizeof(struct g)!=24?-1:1];
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-7.c
new file mode 100644
index 000000000..8af61ddac
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-7.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+struct b
+{
+  long long t;
+  int i;
+};
+struct h
+{
+  int tt;
+  struct b d;
+  int t;
+};
+
+int f[sizeof(struct h)!=24?-1:1];
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-8.c
new file mode 100644
index 000000000..eac0d12d1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-8.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+
+struct c
+{
+  double d;
+  int i;
+};
+
+struct j
+{
+  int tt;
+  struct c d;
+  int t;
+};
+
+int f[sizeof(struct j)!=24?-1:1];
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-9.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-9.c
new file mode 100644
index 000000000..fa5bd017f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-abi-9.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+struct b
+{
+  long long t;
+  int i;
+};
+
+struct l
+{
+  int i;
+  double d;
+};
+struct k
+{
+  int tt;
+  struct l d;
+  struct b h;
+  int t;
+};
+
+int f[sizeof(struct k)!=36?-1:1];
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c
new file mode 100644
index 000000000..fe4b72615
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c
@@ -0,0 +1,12 @@
+/* Check that sizeof(bool) is 4 if we don't use special options. */
+/* Matt Austern  <austern@apple.com> */
+/* { dg-do run { target powerpc*-*-darwin* } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "-m64" } { "" } } */
+
+int dummy1[sizeof(_Bool) - 3];
+int dummy2[5 - sizeof(_Bool)];
+
+int main()
+{
+  return sizeof(_Bool) == 4 ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-bool-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-bool-2.c
new file mode 100644
index 000000000..fdbe1a2a4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-bool-2.c
@@ -0,0 +1,12 @@
+/* Check that sizeof(bool) is 1 if we use the -mone-byte-bool option. */
+/* Matt Austern  <austern@apple.com> */
+/* { dg-do run { target powerpc*-*-darwin* } } */
+/* { dg-options "-mone-byte-bool" } */
+
+int dummy1[sizeof(_Bool)];
+int dummy2[2 - sizeof(_Bool)];
+
+int main()
+{
+  return sizeof(_Bool) == 1 ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-ehreturn-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-ehreturn-1.c
new file mode 100644
index 000000000..71ee094bf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-ehreturn-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-mcpu=G3 -funwind-tables" } */
+/* { dg-final { scan-assembler "bl save_world" } } */
+/* { dg-final { scan-assembler ".byte\t0x6b" } } */
+
+/* Verify that on Darwin, even with -mcpu=G3, __builtin_eh_return
+   saves Altivec registers using save_world, and reports their
+   location in its EH information.  */
+
+long offset;
+void *handler;
+
+extern void setup_offset(void);
+
+void foo(void)
+{
+  __builtin_unwind_init ();
+  setup_offset();
+  __builtin_eh_return (offset, handler);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-longdouble.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-longdouble.c
new file mode 100644
index 000000000..8e4259af3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-longdouble.c
@@ -0,0 +1,119 @@
+/* { dg-do run { target powerpc*-*-darwin* } } */
+/* { dg-options "" } */
+/* No options so 'long long' can be used.  */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+typedef unsigned long long uint64_t;
+typedef uint64_t ldbits[2];
+
+union ldu 
+{
+  ldbits lb;
+  long double ld;
+};
+
+static const struct {
+  ldbits a;
+  ldbits b;
+  ldbits result;
+} single_tests[] = {
+  /* Test of values that add to near +Inf.  */
+  { { 0x7FEFFFFFFFFFFFFFLL, 0xFC88000000000000LL },
+    { 0x7C94000000000000LL, 0x0000000000000000LL },
+    { 0x7FEFFFFFFFFFFFFFLL, 0x7C80000000000000LL } },
+  { { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL },
+    { 0x792FFFFFFFFFFFFFLL, 0x0000000000000000LL },
+    { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL } },
+  { { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL },
+    { 0x7930000000000000LL, 0xF5DFFFFFFFFFFFFFLL },
+    /* correct result is: { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL } */
+    { 0x7FF0000000000000LL, 0x0000000000000000LL } },
+  /* Test of values that add to +Inf.  */
+  { { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL },
+    { 0x7930000000000000LL, 0x0000000000000000LL },
+    { 0x7FF0000000000000LL, 0x0000000000000000LL } },
+  /* Tests of Inf addition.  */
+  { { 0x7FF0000000000000LL, 0x0000000000000000LL },
+    { 0x0000000000000000LL, 0x0000000000000000LL },
+    { 0x7FF0000000000000LL, 0x0000000000000000LL } },
+  { { 0x7FF0000000000000LL, 0x0000000000000000LL },
+    { 0x7FF0000000000000LL, 0x0000000000000000LL },
+    { 0x7FF0000000000000LL, 0x0000000000000000LL } },
+  /* Test of Inf addition producing NaN.  */
+  { { 0x7FF0000000000000LL, 0x0000000000000000LL },
+    { 0xFFF0000000000000LL, 0x0000000000000000LL },
+    { 0x7FF8000000000000LL, 0x0000000000000000LL } },
+  /* Tests of NaN addition.  */
+  { { 0x7FF8000000000000LL, 0x0000000000000000LL },
+    { 0x0000000000000000LL, 0x0000000000000000LL },
+    { 0x7FF8000000000000LL, 0x7FF8000000000000LL } },
+  { { 0x7FF8000000000000LL, 0x0000000000000000LL },
+    { 0x7FF0000000000000LL, 0x0000000000000000LL },
+    { 0x7FF8000000000000LL, 0x7FF8000000000000LL } },
+  /* Addition of positive integers, with interesting rounding properties.  */
+  { { 0x4690000000000000LL, 0x4330000000000000LL },
+    { 0x4650000000000009LL, 0xC2FFFFFFFFFFFFF2LL },
+    /* correct result is: { 0x4691000000000001LL, 0xC32C000000000000LL } */
+    { 0x4691000000000001LL, 0xc32bfffffffffffeLL } },
+  { { 0x4690000000000000LL, 0x4330000000000000LL },
+    { 0x4650000000000008LL, 0x42F0000000000010LL },
+    { 0x4691000000000001LL, 0xC32E000000000000LL } },
+  { { 0x469FFFFFFFFFFFFFLL, 0x433FFFFFFFFFFFFFLL },
+    { 0x4340000000000000LL, 0x3FF0000000000000LL },
+    { 0x46A0000000000000LL, 0x0000000000000000LL } },
+  { { 0x469FFFFFFFFFFFFFLL, 0x433FFFFFFFFFFFFFLL },
+    { 0x4340000000000000LL, 0x0000000000000000LL },
+    { 0x46A0000000000000LL, 0xBFF0000000000000LL } },
+  /* Subtraction of integers, with cancellation.  */
+  { { 0x4690000000000000LL, 0x4330000000000000LL },
+    { 0xC690000000000000LL, 0xC330000000000000LL },
+    { 0x0000000000000000LL, 0x0000000000000000LL } },
+  { { 0x4690000000000000LL, 0x4330000000000000LL },
+    { 0xC330000000000000LL, 0x0000000000000000LL },
+    { 0x4690000000000000LL, 0x0000000000000000LL } },
+  { { 0x4690000000000000LL, 0x4330000000000000LL },
+    { 0xC330000000000000LL, 0x3FA0000000000000LL },
+    { 0x4690000000000000LL, 0x3FA0000000000000LL } },
+  { { 0x4690000000000000LL, 0x4330000000000000LL },
+    { 0xC690000000000000LL, 0x3FA0000000000000LL },
+    /* correct result is: { 0x4330000000000000LL, 0x3FA0000000000000LL } */
+    { 0x4330000000000000LL, 0x0000000000000000LL } }
+};
+    
+static int fail = 0;
+
+static void
+run_single_tests (void)
+{
+  size_t i;
+  for (i = 0; i < sizeof (single_tests) / sizeof (single_tests[0]); i++)
+    {
+      union ldu a, b, result, expected;
+      memcpy (a.lb, single_tests[i].a, sizeof (ldbits));
+      memcpy (b.lb, single_tests[i].b, sizeof (ldbits));
+      memcpy (expected.lb, single_tests[i].result, sizeof (ldbits));
+      result.ld = a.ld + b.ld;
+      if (memcmp (result.lb, expected.lb,
+		  result.ld == result.ld ? sizeof (ldbits) : sizeof (double))
+	  != 0)
+	{
+	  printf ("FAIL: %016llx %016llx + %016llx %016llx\n",
+		  a.lb[0], a.lb[1], b.lb[0], b.lb[1]);
+	  printf (" = %016llx %016llx not %016llx %016llx\n",
+		  result.lb[0], result.lb[1], expected.lb[0], expected.lb[1]);
+	  fail = 1;
+	}
+    }
+}
+
+int main(void)
+{
+  run_single_tests();
+  if (fail)
+    abort ();
+  else
+    exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c
new file mode 100644
index 000000000..0692b3d80
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c
@@ -0,0 +1,22 @@
+/* { dg-do run { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc64 } */
+/* { dg-options "-mcpu=G5" } */
+
+#include <stdlib.h>
+
+int  msw(long long in)
+{
+  union {
+    long long ll;
+    int  i[2];
+  } ud;
+  ud.ll = in;
+  return ud.i[0];
+}
+
+int main()
+{
+  if (msw(1) != 0)
+    abort();
+  exit(0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-misaligned.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-misaligned.c
new file mode 100644
index 000000000..9e53b7b22
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-misaligned.c
@@ -0,0 +1,32 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-options "-O2 -mpowerpc64" } */
+
+typedef struct Nlm_rect {
+  short sh1;
+  short sh2;
+  short sh3;
+  short sh4;
+} S8;
+
+typedef struct udv_mouse_select {
+    short Action_type;
+    S8 rcClip;
+    int pgp;
+  } UDVselect;
+
+UDVselect ms;
+int UDV(S8 rcClip);
+
+int main()
+{
+    ms.rcClip.sh1 = 1;
+    ms.rcClip.sh4 = 4;
+    return UDV(ms.rcClip);
+}
+
+int UDV(S8 rcClip){
+
+	return !(rcClip.sh1 == 1 && rcClip.sh4 == 4);
+}
+	
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-save-world-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-save-world-1.c
new file mode 100644
index 000000000..c45a90f0f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/darwin-save-world-1.c
@@ -0,0 +1,19 @@
+/* { dg-do run { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-skip-if "need to be able to execute AltiVec" { ! { powerpc_altivec_ok && vmx_hw } } } */
+/* { dg-options "-maltivec" } */
+
+/* With altivec turned on, Darwin wants to save the world but we did not mark lr as being saved any more
+   as saving the lr is not needed for saving altivec registers.  */
+
+int main (void)
+{
+  __label__ l1;
+  void __attribute__((used)) q(void)
+  {
+    goto l1;
+  }
+
+  l1:;
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/dfp-dd.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/dfp-dd.c
new file mode 100644
index 000000000..85da90705
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/dfp-dd.c
@@ -0,0 +1,33 @@
+/* Test generation of DFP instructions for POWER6.  */
+/* Origin: Janis Johnson <janis187@us.ibm.com> */
+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */
+/* { dg-options "-std=gnu99 -mcpu=power6" } */
+
+/* { dg-final { scan-assembler "dadd" } } */
+/* { dg-final { scan-assembler "ddiv" } } */
+/* { dg-final { scan-assembler "dmul" } } */
+/* { dg-final { scan-assembler "dsub" } } */
+/* { dg-final { scan-assembler-times "dcmpu" 6 } } */
+/* { dg-final { scan-assembler-times "dctfix" 2 } } */
+/* { dg-final { scan-assembler-times "drintn" 2 } } */
+/* { dg-final { scan-assembler-times "dcffixq" 2 } } */
+
+extern _Decimal64 a, b, c;
+extern int result;
+extern int si;
+extern long long di;
+
+void add (void) { a = b + c; }
+void div (void) { a = b / c; }
+void mul (void) { a = b * c; }
+void sub (void) { a = b - c; }
+void eq (void) { result = a == b; }
+void ne (void) { result = a != b; }
+void lt (void) { result = a < b; }
+void le (void) { result = a <= b; }
+void gt (void) { result = a > b; }
+void ge (void) { result = a >= b; }
+void ddsi (void) { si = a; }
+void dddi (void) { di = a; }
+void sidd (void) { a = si; }
+void didd (void) { a = di; }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/dfp-td.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/dfp-td.c
new file mode 100644
index 000000000..752ba8874
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/dfp-td.c
@@ -0,0 +1,33 @@
+/* Test generation of DFP instructions for POWER6.  */
+/* Origin: Janis Johnson <janis187@us.ibm.com> */
+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */
+/* { dg-options "-std=gnu99 -mcpu=power6" } */
+
+/* { dg-final { scan-assembler "daddq" } } */
+/* { dg-final { scan-assembler "ddivq" } } */
+/* { dg-final { scan-assembler "dmulq" } } */
+/* { dg-final { scan-assembler "dsubq" } } */
+/* { dg-final { scan-assembler-times "dcmpuq" 6 } } */
+/* { dg-final { scan-assembler-times "dctfixq" 2 } } */
+/* { dg-final { scan-assembler-times "drintnq" 2 } } */
+/* { dg-final { scan-assembler-times "dcffixq" 2 } } */
+
+extern _Decimal128 a, b, c;
+extern int result;
+extern int si;
+extern long long di;
+
+void add (void) { a = b + c; }
+void div (void) { a = b / c; }
+void mul (void) { a = b * c; }
+void sub (void) { a = b - c; }
+void eq (void) { result = a == b; }
+void ne (void) { result = a != b; }
+void lt (void) { result = a < b; }
+void le (void) { result = a <= b; }
+void gt (void) { result = a > b; }
+void ge (void) { result = a >= b; }
+void tdsi (void) { si = a; }
+void tddi (void) { di = a; }
+void sitd (void) { a = si; }
+void ditd (void) { a = di; }
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/doloop-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/doloop-1.c
new file mode 100644
index 000000000..d4bc45415
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/doloop-1.c
@@ -0,0 +1,17 @@
+/* Make sure both loops are recognized as doloops.
+   If so, "bdnz" will be generated on ppc; if not,
+   you will get "ble" or "blt" or "bge".  */
+
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O2" } */
+void foo (int count, char* pca, char* pcb) {
+    int i;
+    if (count > 10)
+        for (i = 0; i < count; ++i)
+            pcb += i;
+    else
+        for (i = 0; i < count; ++i)
+            pca += i;
+    *pca = *pcb;
+}
+/* { dg-final { scan-assembler "bdnz" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/e500-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/e500-1.c
new file mode 100644
index 000000000..76a0e4a22
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/e500-1.c
@@ -0,0 +1,14 @@
+/* Test functioning of command option -mno-isel */
+/* { dg-do compile { target powerpc*-*-linux* } } */
+/* { dg-options "-O2 -mno-isel" } */
+
+/* { dg-final { scan-assembler-not "isel" } } */
+
+int
+foo (int x, int y)
+{
+  if (x < y)
+    return x;
+  else
+    return y;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/gcse-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/gcse-1.c
new file mode 100644
index 000000000..799cde1dd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/gcse-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { *-*-linux* && ilp32 } } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "@ha" 1 } } */
+
+
+/* Test for PR 7003, address of array loaded int register
+   twice without any need. */
+
+extern const char flags [256];
+
+unsigned char * f (unsigned char * s) {
+  while (flags[*++s]);
+  while (!flags[*++s]);
+  return s;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/indexed-addr.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/indexed-addr.c
new file mode 100644
index 000000000..6933b23e0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/indexed-addr.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler "3,\.*3,\.*4" } }
+
+/* Ensure that indexed address are output with base address in rA position
+   and index in rB position.  */
+
+char
+do_one (char *base, unsigned long offset)
+{
+  return base[offset];
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/leaf.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/leaf.c
new file mode 100644
index 000000000..079418930
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/leaf.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target rs6000-*-* } }  */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "\tstwu 1,-\[0-9\]*(1)\n" } } */
+
+int Leaf (int i)
+{
+  return i + 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/longcall-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/longcall-1.c
new file mode 100644
index 000000000..e7187f17a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/longcall-1.c
@@ -0,0 +1,13 @@
+/* PR target/35100 */
+/* { dg-do compile { target fpic } } */
+/* { dg-options "-fpic" } */
+
+void foo (void) __attribute__((__longcall__));
+int baz (void) __attribute__((__longcall__));
+
+int
+bar (void)
+{
+  foo ();
+  return baz () + 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/macho-lo-sum.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/macho-lo-sum.c
new file mode 100644
index 000000000..9e0b8656c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/macho-lo-sum.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-options "-O2 -mpowerpc64 -mdynamic-no-pic" } */
+
+long long knight_attacks[64];
+long long InitializeAttackBoards(void);
+
+int main()
+{
+	return InitializeAttackBoards();
+}
+
+long long InitializeAttackBoards(void)
+{
+
+  int i,j;
+
+  for(i=0;i<64;i++) { }
+
+  for(i=0;i<64;i++) {
+    knight_attacks[i]=0;
+    for(j=0;j<8;j++) {
+      knight_attacks[i]= 0;
+    }
+  }
+
+  return knight_attacks[0];
+
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/non-lazy-ptr-test.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/non-lazy-ptr-test.c
new file mode 100644
index 000000000..10cce470a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/non-lazy-ptr-test.c
@@ -0,0 +1,40 @@
+/* { dg-do compile { target powerpc*-apple-darwin* } } */
+/* { dg-options "-S" } */
+
+typedef void PF (void);
+
+static void f(void) {
+}
+
+void f1(void) {
+}
+
+extern void f2(void) {
+}
+
+static void f3(void);
+
+void pe(void)
+{
+}
+
+PF* g (void) { f(); return f; }
+PF* x (void) { return f1; }
+PF* y (void) { f2(); return f2; }
+PF* z (void) { return f3; }
+PF* w (void) { pe(); return pe; }
+
+int main()
+{
+	(*g())();
+	(*x())();
+	(*y())();
+	(*z())();
+	(*w())();
+	return 0;
+}
+
+void f3(void) {
+}
+
+/* { dg-final { scan-assembler-not "non_lazy_ptr" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-1.c
new file mode 100644
index 000000000..641a8e022
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-1.c
@@ -0,0 +1,33 @@
+/* { dg-do compile { target powerpc-*-linux*paired* } } */
+/* { dg-options "-mpaired -m32 -ffinite-math-only " } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+
+static float in1[2] __attribute__ ((aligned (8))) =
+{6.0, 7.0};
+static float in2[2] __attribute__ ((aligned (8))) =
+{4.0, 3.0};
+
+static float out[2] __attribute__ ((aligned (8)));
+
+vector float a, b, c, d;
+void
+test_api ()
+{
+  b = paired_lx (0, in1);
+  c = paired_lx (0, in2);
+
+  a = paired_sub (b, c);
+
+  paired_stx (a, 0, out);
+}
+
+int
+main ()
+{
+  test_api ();
+  return (0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-10.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-10.c
new file mode 100644
index 000000000..114f5f74b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-10.c
@@ -0,0 +1,25 @@
+/* { dg-do compile { target powerpc-*-linux*paired* } } */
+/* { dg-options "-mpaired -m32 -ffinite-math-only " } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+void
+test_api (float y, float x)
+{
+  vector float c = {x, y};
+  vector float b = {0.0, 8.0};
+  vector float a;
+
+  a = paired_sub (b, c);
+  paired_stx (a, 0, out);
+}
+
+
+int main ()
+{
+  test_api (6, 7);
+  return (0); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-2.c
new file mode 100644
index 000000000..ef409027f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-2.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target powerpc-*-linux*paired* } } */
+/* { dg-options "-mpaired -m32 -ffinite-math-only" } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+#include <stdlib.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+
+vector float b = { 3.0, 8.0 };
+vector float c = { 3.0, 5.0 };
+
+vector float a = { 0.0, 0.0 };
+void
+test_api ()
+{
+
+  if (paired_cmpu0_eq (b, c))
+    {
+      a = paired_sub (b, c);
+      paired_stx (a, 0, out);
+    }
+
+  if ((out[1]) != 3.0)
+    abort ();
+}
+
+int
+main ()
+{
+  test_api ();
+  return (0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-3.c
new file mode 100644
index 000000000..756d6e111
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-3.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target powerpc-*-linux*paired* } } */
+/* { dg-options "-mpaired -m32 -ffinite-math-only" } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+#include <stdlib.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+
+vector float b = { 2.0, 8.0 };
+vector float c = { 3.0, 5.0 };
+
+vector float a = { 0.0, 0.0 };
+void
+test_api ()
+{
+
+  if (paired_cmpu0_lt (b, c))
+    {
+      a = paired_add (b, c);
+      paired_stx (a, 0, out);
+    }
+  if ((out[0] != 5.0) || (out[1] != 13.0))
+    abort ();
+}
+
+int
+main ()
+{
+  test_api ();
+  return (0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-4.c
new file mode 100644
index 000000000..3d5c1549b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-4.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target powerpc-*-linux*paired* } } */
+/* { dg-options "-mpaired -m32 -ffinite-math-only" } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+#include <stdlib.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+
+vector float b = { 3.0, 8.0 };
+vector float c = { 2.0, 5.0 };
+
+vector float a = { 0.0, 0.0 };
+void
+test_api ()
+{
+
+  if (paired_cmpu0_gt (b, c))
+    {
+      a = paired_add (b, c);
+      paired_stx (a, 0, out);
+    }
+  if ((out[0] != 5.0) || (out[1] != 13.0))
+    abort ();
+}
+
+int
+main ()
+{
+  test_api ();
+  return (0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-5.c
new file mode 100644
index 000000000..df3bb4441
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-5.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target powerpc-*-linux*paired* } } */
+/* { dg-options "-mpaired -m32 -ffinite-math-only" } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+#include <stdlib.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+
+vector float b = { 3.0, 5.0 };
+vector float c = { 2.0, 5.0 };
+
+vector float a = { 0.0, 0.0 };
+void
+test_api ()
+{
+
+  if (paired_cmpu1_eq (b, c))
+    {
+      a = paired_add (b, c);
+      paired_stx (a, 0, out);
+    }
+  if ((out[0] != 5.0) || (out[1] != 10.0))
+    abort ();
+}
+
+int
+main ()
+{
+  test_api ();
+  return (0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-6.c
new file mode 100644
index 000000000..0d6ab52e9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-6.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target powerpc-*-linux*paired* } } */
+/* { dg-options "-mpaired -m32 -ffinite-math-only" } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+#include <stdlib.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+
+vector float b = { 3.0, 5.0 };
+vector float c = { 2.0, 6.0 };
+
+vector float a = { 0.0, 0.0 };
+void
+test_api ()
+{
+
+  if (paired_cmpu1_lt (b, c))
+    {
+      a = paired_add (b, c);
+      paired_stx (a, 0, out);
+    }
+  if ((out[0] != 5.0) || (out[1] != 11.0))
+    abort ();
+}
+
+int
+main ()
+{
+  test_api ();
+  return (0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-7.c
new file mode 100644
index 000000000..aa1edd033
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-7.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target powerpc-*-linux*paired* } } */
+/* { dg-options "-mpaired -m32 -ffinite-math-only" } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+#include <stdlib.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+
+vector float b = { 2.0, 8.0 };
+vector float c = { 3.0, 6.0 };
+
+vector float a = { 0.0, 0.0 };
+void
+test_api ()
+{
+
+  if (paired_cmpu1_gt (b, c))
+    {
+      a = paired_add (b, c);
+      paired_stx (a, 0, out);
+    }
+  if ((out[0] != 5.0) || (out[1] != 14.0))
+    abort ();
+}
+
+int
+main ()
+{
+  test_api ();
+  return (0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-8.c
new file mode 100644
index 000000000..03e4da29e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-8.c
@@ -0,0 +1,25 @@
+/* { dg-do compile { target powerpc-*-linux*paired* } } */
+/* { dg-options "-mpaired -m32 -ffinite-math-only " } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+void
+test_api (float x)
+{
+  vector float c = {x, x};
+  vector float b = {60.0, 88.0};
+  vector float a;
+
+  a = paired_sub (b, c);
+  paired_stx (a, 0, out);
+}
+
+
+int main ()
+{
+  test_api (6);
+  return (0); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-9.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-9.c
new file mode 100644
index 000000000..2d96cd4f7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/paired-9.c
@@ -0,0 +1,25 @@
+/* { dg-do compile { target powerpc-*-linux*paired* } } */
+/* { dg-options "-mpaired -m32 -ffinite-math-only " } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+void
+test_api (float y, float x)
+{
+  vector float c = {x, 7.0};
+  vector float b = {0.0, 8.0};
+  vector float a;
+
+  a = paired_sub (b, c);
+  paired_stx (a, 0, out);
+}
+
+
+int main ()
+{
+  test_api (6, 7);
+  return (0); 
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/parity-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/parity-1.c
new file mode 100644
index 000000000..c991d4caa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/parity-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { ilp32 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power5" } */
+/* { dg-final { scan-assembler "popcntb" } } */
+/* { dg-final { scan-assembler-not "mullw" } } */
+
+int foo(int x)
+{
+  return __builtin_parity(x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/popcount-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/popcount-1.c
new file mode 100644
index 000000000..c94d155e1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/popcount-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { ilp32 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power5" } */
+/* { dg-final { scan-assembler "popcntb" } } */
+/* { dg-final { scan-assembler-not "mullw" } } */
+
+int foo(int x)
+{
+  return __builtin_popcount(x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/powerpc.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/powerpc.exp
new file mode 100644
index 000000000..bb97e1e97
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/powerpc.exp
@@ -0,0 +1,41 @@
+#   Copyright (C) 2005, 2007 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the 'dg.exp' driver.
+
+# Exit immediately if this isn't a PowerPC target.
+if { ![istarget powerpc*-*-*] && ![istarget rs6000-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize 'dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-and-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-and-1.c
new file mode 100644
index 000000000..3d4237ce9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-and-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,0,0,30"  } } */
+/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,0,29,30"  } } */
+/* { dg-final { scan-assembler-not "rldicr" } } */
+
+/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */
+
+/* PR 16457 - use rlwinm insn.  */
+
+char *foo1 (char *p, unsigned int x)
+{
+  return p - (x & ~1);
+}
+
+char *foo2 (char *p, unsigned int x)
+{
+  return p - (x & 6);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c
new file mode 100644
index 000000000..34e5a28e1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c
@@ -0,0 +1,67 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,1,31"  } } */
+/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,0xffffffff" } } */
+
+/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */
+
+/* PR 17104 many sign extends added.  */
+
+struct {
+ int f1 : 1;
+ int f2 : 1;
+ int f3 : 1;
+ int f4 : 1;
+ int f5 : 1;
+ int f6 : 1;
+ int f7 : 1;
+ int f8 : 1;
+ int f9 : 1;
+ int f10 : 1;
+ int f11 : 1;
+ int f12 : 1;
+ int f13 : 1;
+ int f14 : 1;
+ int f15 : 1;
+ int f16 : 1;
+ int f17 : 2;
+ int f18 : 2;
+ int f19 : 2;
+ int f20 : 2;
+ int f21 : 2;
+ int f22 : 2;
+ int f23 : 2;
+ int f24 : 2;
+ } s;
+
+void foo ()
+{
+
+    s.f1 = 0;
+    s.f2 = 0;
+    s.f3 = 0;
+    s.f4 = 0;
+    s.f5 = 0;
+    s.f6 = 0;
+    s.f7 = 0;
+    s.f8 = 0;
+    s.f9 = 0;
+    s.f10 = 0;
+    s.f11 = 0;
+    s.f12 = 0;
+    s.f13 = 0;
+    s.f14 = 0;
+    s.f15 = 0;
+    s.f16 = 0;
+    s.f17 = 0;
+    s.f18 = 0;
+    s.f19 = 0;
+    s.f20 = 0;
+    s.f21 = 0;
+    s.f22 = 0;
+    s.f23 = 0;
+    s.f24 = 0;
+
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-compare-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-compare-1.c
new file mode 100644
index 000000000..2566423a0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-compare-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-not "cmpw" } } */
+
+/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */
+
+/* PR 16458: Extraneous compare.  */
+
+int foo (unsigned a, unsigned b)
+{
+  if (a == b) return 1;
+  if (a > b)  return 2;
+  if (a < b)  return 3;
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-eabi.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-eabi.c
new file mode 100644
index 000000000..47ba1a733
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-eabi.c
@@ -0,0 +1,4 @@
+/* PR target/16952 */
+/* { dg-do compile { target { powerpc*-*-linux* && ilp32 } } } */
+/* { dg-options "-meabi -mrelocatable" } */
+char *s = "boo";
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c
new file mode 100644
index 000000000..163a4b992
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c
@@ -0,0 +1,10 @@
+/* PR rtl-optimization/10588 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int foo(int x)
+{
+  return x == 0;
+}
+
+/* { dg-final { scan-assembler "cntlzw" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-1.c
new file mode 100644
index 000000000..ff959f2d1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-ffast-math -O2" } */
+/* { dg-final { scan-assembler-not "f(add|sub|mul|neg)" } } */
+
+void foo(double *a, double *b, double *c, double *d)
+{
+  a[0] =  b[0] + c[0] * d[0];		// fmadd
+  a[1] =  b[1] - c[1] * d[1];		// fnmsub with fast-math
+  a[2] = -b[2] + c[2] * d[2];   	// fmsub
+  a[3] = -b[3] - c[3] * d[3];		// fnmadd with fast-math
+  a[4] = -( b[4] + c[4] * d[4]);	// fnmadd
+  a[5] = -( b[5] - c[5] * d[5]);	// fmsub with fast-math
+  a[6] = -(-b[6] + c[6] * d[6]);	// fnmsub
+  a[7] = -(-b[7] - c[7] * d[7]);	// fmadd with fast-math
+  a[10] =  b[10] - c[10] * -d[10];	// fmadd
+  a[11] =  b[11] + c[11] * -d[11];	// fnmsub with fast-math
+  a[12] = -b[12] - c[12] * -d[12];   	// fmsub
+  a[13] = -b[13] + c[13] * -d[13];	// fnmadd with fast-math
+  a[14] = -( b[14] - c[14] * -d[14]);	// fnmadd
+  a[15] = -( b[15] + c[15] * -d[15]);	// fmsub with fast-math
+  a[16] = -(-b[16] - c[16] * -d[16]);	// fnmsub
+  a[17] = -(-b[17] + c[17] * -d[17]);	// fmadd with fast-math
+}
+
+void foos(float *a, float *b, float *c, float *d)
+{
+  a[0] =  b[0] + c[0] * d[0];		// fmadd
+  a[1] =  b[1] - c[1] * d[1];		// fnmsub with fast-math
+  a[2] = -b[2] + c[2] * d[2];   	// fmsub
+  a[3] = -b[3] - c[3] * d[3];		// fnmadd with fast-math
+  a[4] = -( b[4] + c[4] * d[4]);	// fnmadd
+  a[5] = -( b[5] - c[5] * d[5]);	// fmsub with fast-math
+  a[6] = -(-b[6] + c[6] * d[6]);	// fnmsub
+  a[7] = -(-b[7] - c[7] * d[7]);	// fmadd with fast-math
+  a[10] =  b[10] - c[10] * -d[10];	// fmadd
+  a[11] =  b[11] + c[11] * -d[11];	// fnmsub with fast-math
+  a[12] = -b[12] - c[12] * -d[12];   	// fmsub
+  a[13] = -b[13] + c[13] * -d[13];	// fnmadd with fast-math
+  a[14] = -( b[14] - c[14] * -d[14]);	// fnmadd
+  a[15] = -( b[15] + c[15] * -d[15]);	// fmsub with fast-math
+  a[16] = -(-b[16] - c[16] * -d[16]);	// fnmsub
+  a[17] = -(-b[17] + c[17] * -d[17]);	// fmadd with fast-math
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-2.c
new file mode 100644
index 000000000..02ed811da
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-2.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "f(add|sub|mul|neg)" } } */
+
+void foo(double *a, double *b, double *c, double *d)
+{
+  a[0] =  b[0] + c[0] * d[0];		// fmadd
+  a[2] = -b[2] + c[2] * d[2];   	// fmsub
+  a[4] = -( b[4] + c[4] * d[4]);	// fnmadd
+  a[6] = -(-b[6] + c[6] * d[6]);	// fnmsub
+  a[10] =  b[10] - c[10] * -d[10];	// fmadd
+  a[12] = -b[12] - c[12] * -d[12];   	// fmsub
+  a[14] = -( b[14] - c[14] * -d[14]);	// fnmadd
+  a[16] = -(-b[16] - c[16] * -d[16]);	// fnmsub
+}
+
+void foos(float *a, float *b, float *c, float *d)
+{
+  a[0] =  b[0] + c[0] * d[0];		// fmadd
+  a[2] = -b[2] + c[2] * d[2];   	// fmsub
+  a[4] = -( b[4] + c[4] * d[4]);	// fnmadd
+  a[6] = -(-b[6] + c[6] * d[6]);	// fnmsub
+  a[10] =  b[10] - c[10] * -d[10];	// fmadd
+  a[12] = -b[12] - c[12] * -d[12];   	// fmsub
+  a[14] = -( b[14] - c[14] * -d[14]);	// fnmadd
+  a[16] = -(-b[16] - c[16] * -d[16]);	// fnmsub
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-3.c
new file mode 100644
index 000000000..d4205225c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-3.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "f(add|sub|mul)" } } */
+
+void foo(double *a, double *b, double *c, double *d)
+{
+#if 0
+  a[1] =  b[1] - c[1] * d[1];		// fneg, fmadd without fast-math
+#endif
+  a[3] = -b[3] - c[3] * d[3];		// fneg, fmsub without fast-math
+#if 0
+  a[5] = -( b[5] - c[5] * d[5]);	// fneg, fnmadd without fast-math
+#endif
+  a[7] = -(-b[7] - c[7] * d[7]);	// fneg, fnmsub without fast-math
+  a[11] =  b[11] + c[11] * -d[11];	// fneg, fmadd without fast-math
+  a[13] = -b[13] + c[13] * -d[13];	// fneg, fmsub without fast-math
+  a[15] = -( b[15] + c[15] * -d[15]);	// fneg, fnmadd without fast-math
+  a[17] = -(-b[17] + c[17] * -d[17]);	// fneg, fnmsub without fast-math
+}
+
+void foos(float *a, float *b, float *c, float *d)
+{
+#if 0
+  a[1] =  b[1] - c[1] * d[1];		// fneg, fmadd without fast-math
+#endif
+  a[3] = -b[3] - c[3] * d[3];		// fneg, fmsub without fast-math
+#if 0
+  a[5] = -( b[5] - c[5] * d[5]);	// fneg, fnmadd without fast-math
+#endif
+  a[7] = -(-b[7] - c[7] * d[7]);	// fneg, fnmsub without fast-math
+  a[11] =  b[11] + c[11] * -d[11];	// fneg, fmadd without fast-math
+  a[13] = -b[13] + c[13] * -d[13];	// fneg, fmsub without fast-math
+  a[15] = -( b[15] + c[15] * -d[15]);	// fneg, fnmadd without fast-math
+  a[17] = -(-b[17] + c[17] * -d[17]);	// fneg, fnmsub without fast-math
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c
new file mode 100644
index 000000000..8d364352a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O -mpowerpc-gfxopt -fno-trapping-math" } */
+/* { dg-final { scan-assembler "fsel" } } */
+
+/* If the user doesn't care about signals, fsel can be used in many cases.  */
+
+double foo(double a, double b, double c, double d)
+{
+  return a < b ? c : d;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fsel-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fsel-2.c
new file mode 100644
index 000000000..9768b165c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fsel-2.c
@@ -0,0 +1,80 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O -mpowerpc-gfxopt -g0 -ffinite-math-only" } */
+/* { dg-final { scan-assembler-not "^L" } } */
+
+/* Every single one of these should be compiled into straight-line
+   code using fsel (or, in a few cases, hardwired to 'true' or
+   'false'), no branches anywhere.  */
+
+double
+test_isunordered(double x, double y, double a, double b)
+{
+  return __builtin_isunordered(x, y) ? a : b;
+}
+
+double
+test_not_isunordered(double x, double y, double a, double b)
+{
+  return !__builtin_isunordered(x, y) ? a : b;
+}
+
+double
+test_isless(double x, double y, double a, double b)
+{
+  return __builtin_isless(x, y) ? a : b;
+}
+
+double
+test_not_isless(double x, double y, double a, double b)
+{
+  return !__builtin_isless(x, y) ? a : b;
+}
+
+double
+test_islessequal(double x, double y, double a, double b)
+{
+  return __builtin_islessequal(x, y) ? a : b;
+}
+
+double
+test_not_islessequal(double x, double y, double a, double b)
+{
+  return !__builtin_islessequal(x, y) ? a : b;
+}
+
+double
+test_isgreater(double x, double y, double a, double b)
+{
+  return __builtin_isgreater(x, y) ? a : b;
+}
+
+double
+test_not_isgreater(double x, double y, double a, double b)
+{
+  return !__builtin_isgreater(x, y) ? a : b;
+}
+
+double
+test_isgreaterequal(double x, double y, double a, double b)
+{
+  return __builtin_isgreaterequal(x, y) ? a : b;
+}
+
+double
+test_not_isgreaterequal(double x, double y, double a, double b)
+{
+  return !__builtin_isgreaterequal(x, y) ? a : b;
+}
+
+double
+test_islessgreater(double x, double y, double a, double b)
+{
+  return __builtin_islessgreater(x, y) ? a : b;
+}
+
+double
+test_not_islessgreater(double x, double y, double a, double b)
+{
+  return !__builtin_islessgreater(x, y) ? a : b;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fsel-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fsel-3.c
new file mode 100644
index 000000000..1d07c528e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-fsel-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O -mpowerpc-gfxopt" } */
+/* { dg-final { scan-assembler-not "fsub" } } */
+
+/* Check that an fsub isn't generated when no arithmetic was requested;
+   such an fsub might incorrectly set floating-point exception flags.  */
+
+double foo(double a, double b, double c, double d)
+{
+  return a < b ? c : d;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-ldstruct.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-ldstruct.c
new file mode 100644
index 000000000..da6001fcd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-ldstruct.c
@@ -0,0 +1,21 @@
+/* { dg-do run { target powerpc*-*-eabi* powerpc*-*-elf* powerpc*-*-linux* } } */
+/* { dg-options "-O -mlong-double-128" } */
+
+#include <stdlib.h>
+
+/* SVR4 and EABI both specify that 'long double' is aligned to a 128-bit
+   boundary in structures.  */
+
+struct {
+  int x;
+  long double d;
+} s;
+
+int main(void)
+{
+  if (sizeof (s) != 32)
+    abort ();
+  if ((char *)&s.d - (char *)&s != 16)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c
new file mode 100644
index 000000000..750cf85f0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c
@@ -0,0 +1,52 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-not "fmr \[0-9\]+,\[0-9\]+" } }
+
+/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */
+
+/* PR 16796: Extraneous move.  */
+
+static const double huge = 1.0e300;
+typedef int int64_t __attribute__ ((__mode__ (__DI__)));
+typedef unsigned int u_int64_t __attribute__ ((__mode__ (__DI__)));
+
+double __floor(double x)
+{
+  union {
+    double dbl_val;
+    long int long_val;
+  } temp;
+
+  int64_t i0,j0;
+  u_int64_t i;
+  temp.dbl_val = x;
+  i0 = temp.long_val;
+
+  j0 = ((i0>>52)&0x7ff)-0x3ff;
+  if(j0<52) {
+    if(j0<0) {
+      if(huge+x>0.0) {
+        if(i0>=0) {i0=0;}
+        else if((i0&0x7fffffffffffffff)!=0)
+        { i0=0xbff0000000000000;}
+      }
+    } else {
+      i = (0x000fffffffffffff)>>j0;
+      if((i0&i)==0) return x;
+      if(huge+x>0.0) {
+        if(i0<0) i0 += (0x0010000000000000)>>j0;
+        i0 &= (~i);
+      }
+    }
+  } else {
+    if (j0==0x400)
+      return x+x;
+    else
+      return x;
+  }
+  temp.long_val = i0;
+  x = temp.dbl_val;
+  return x;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-negeq0-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-negeq0-1.c
new file mode 100644
index 000000000..0386ecba7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-negeq0-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+long foo(long x)
+{
+  return -(x == 0);
+}
+
+long bar(long x)
+{
+  long t = __builtin_clzl(x);
+  return -(t>>(sizeof(long) == 8 ? 6 : 5));
+}
+
+/* { dg-final { scan-assembler-not "cntlz" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-paired.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-paired.c
new file mode 100644
index 000000000..a3b61fd3f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-paired.c
@@ -0,0 +1,45 @@
+/* { dg-do compile { target powerpc-*-linux*paired* } } */
+/* { dg-options "-mpaired -m32 -ffinite-math-only" } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+
+vector float a, b, c, d;
+
+void
+test_api ()
+{
+  b = paired_msub (b, c, d);
+  b = paired_madd (b, c, d);
+  b = paired_nmadd (b, c, d);
+  b = paired_nmsub (b, c, d);
+  b = paired_sum0 (a, b, c);
+  b = paired_sum1 (a, b, c);
+  b = paired_div (b, c);
+  b = paired_add (a, c);
+  b = paired_sub (a, c);
+  b = paired_mul (a, c);
+  b = paired_neg (a);
+  b = paired_muls0 (a, c);
+  b = paired_muls1 (a, c);
+  b = paired_madds0 (a, c, d);
+  b = paired_madds1 (a, c, d);
+  b = paired_merge00 (a, c);
+  b = paired_merge01 (a, c);
+  b = paired_merge10 (a, c);
+  b = paired_merge11 (a, c);
+  b = paired_abs (a);
+  b = paired_nabs (a);
+  b = paired_sqrt (a);
+  b = paired_res (a);
+  b = paired_sel (a, b, c);
+}
+
+int
+main (void)
+{
+  test_api ();
+  return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c
new file mode 100644
index 000000000..8ec39b45a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { { powerpc*-*-linux* && ilp32 } || { powerpc-*-eabi* } } } } */
+/* { dg-options "-O2 -fno-common -G 8 -meabi -msdata=eabi" } */
+/* { dg-final { scan-assembler "\\.section\[ \t\]\\.sdata," } } */
+/* { dg-final { scan-assembler "\\.section\[ \t\]\\.sdata2," } } */
+/* { dg-final { scan-assembler "sdat@sda21\\((13|0)\\)" } } */
+/* { dg-final { scan-assembler "sdat2@sda21\\((2|0)\\)" } } */
+
+
+int sdat = 2;
+const char sdat2[] = "1234";
+
+const char * test (void)
+{
+  return sdat ? sdat2 : 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-sdata-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-sdata-2.c
new file mode 100644
index 000000000..9b577df52
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-sdata-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { { powerpc*-*-linux* && ilp32 } || { powerpc-*-eabi* } } } } */
+/* { dg-options "-O2 -fno-common -G 8 -msdata=sysv" } */
+/* { dg-final { scan-assembler "\\.section\[ \t\]\\.sdata," } } */
+/* { dg-final { scan-assembler-not "\\.section\[ \t\]\\.sdata2," } } */
+/* { dg-final { scan-assembler "sdat@sdarel\\(13\\)" } } */
+/* { dg-final { scan-assembler "sdat2@sdarel\\(13\\)" } } */
+
+
+int sdat = 2;
+const char sdat2[] = "1234";
+
+const char * test (void)
+{
+  return sdat ? sdat2 : 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-spe.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-spe.c
new file mode 100644
index 000000000..b56439433
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-spe.c
@@ -0,0 +1,663 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single -O0" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+
+/* (Test with -O0 so we don't optimize any of them away).  */
+
+#include <spe.h>
+
+/* Test PowerPC SPE extensions.  */
+
+#define vector __attribute__((vector_size(8)))
+
+vector int a, b, c, *ap;
+vector float f, g, h;
+unsigned int *uip;
+unsigned short *usp;
+int i, j, *ip;
+uint64_t ull;
+int64_t sll;
+unsigned ui;
+float fl;
+uint16_t u16;
+int16_t s16;
+
+/* These are the only documented/supported accesor functions for the
+   SPE builtins.  */
+void
+test_api ()
+{
+  c = __ev_addw (a, b);
+  c = __ev_addiw (a, 8);
+  c = __ev_subfw (a, b);
+  c = __ev_subifw (8, a);
+  c = __ev_abs (a);
+  c = __ev_neg (a);
+  c = __ev_extsb (a);
+  c = __ev_extsh (a);
+  c = __ev_and (a, b);
+  c = __ev_or (a, b);
+  c = __ev_xor (a, b);
+  c = __ev_nand (a, b);
+  c = __ev_nor (a, b);
+  c = __ev_eqv (a, b);
+  c = __ev_andc (a, b);
+  c = __ev_orc (a, b);
+  c = __ev_rlw (a, b);
+  c = __ev_rlwi (a, 8);
+  c = __ev_slw (a, b);
+  c = __ev_slwi (a, 8);
+  c = __ev_srws (a, b);
+  c = __ev_srwu (a, b);
+  c = __ev_srwis (a, 8);
+  c = __ev_srwiu (a, 8);
+  c = __ev_cntlzw (a);
+  c = __ev_cntlsw (a);
+  c = __ev_rndw (a);
+  c = __ev_mergehi (a, b);
+  c = __ev_mergelo (a, b);
+  c = __ev_mergelohi (a, b);
+  c = __ev_mergehilo (a, b);
+  c = __ev_splati (5);
+  c = __ev_splatfi (6);
+  c = __ev_divws (a, b);
+  c = __ev_divwu (a, b);
+  c = __ev_mra (a);
+  i = __brinc (5, 6);
+
+  /* Loads.  */
+  c = __ev_lddx (ap, i);
+  c = __ev_ldwx (ap, i);
+  c = __ev_ldhx (ap, i);
+
+  c = __ev_lwhex (uip, i);
+  c = __ev_lwhoux (uip, i);
+  c = __ev_lwhosx (uip, i);
+  c = __ev_lwwsplatx (uip, i);
+  c = __ev_lwhsplatx (uip, i);
+
+  c = __ev_lhhesplatx (usp, i);
+  c = __ev_lhhousplatx (usp, i);
+  c = __ev_lhhossplatx (usp, i);
+
+  c = __ev_ldd (ap, 5);
+  c = __ev_ldw (ap, 6);
+  c = __ev_ldh (ap, 7);
+  c = __ev_lwhe (uip, 6);
+  c = __ev_lwhou (uip, 6);
+  c = __ev_lwhos (uip, 7);
+  c = __ev_lwwsplat (uip, 7);
+  c = __ev_lwhsplat (uip, 7);
+  c = __ev_lhhesplat (usp, 7);
+  c = __ev_lhhousplat (usp, 7);
+  c = __ev_lhhossplat (usp, 7);
+
+  /* Stores.  */
+  __ev_stddx (a, ap, 9);
+  __ev_stdwx (a, ap, 9);
+  __ev_stdhx (a, ap, 9);
+  __ev_stwwex (a, uip, 9);
+  __ev_stwwox (a, uip, 9);
+  __ev_stwhex (a, uip, 9);
+  __ev_stwhox (a, uip, 9);
+  __ev_stdd (a, ap, 9);
+  __ev_stdw (a, ap, 9);
+  __ev_stdh (a, ap, 9);
+  __ev_stwwe (a, uip, 9);
+  __ev_stwwo (a, uip, 9);
+  __ev_stwhe (a, uip, 9);
+  __ev_stwho (a, uip, 9);
+
+  /* Fixed point complex.  */
+  c = __ev_mhossf (a, b);
+  c = __ev_mhosmf (a, b);
+  c = __ev_mhosmi (a, b);
+  c = __ev_mhoumi (a, b);
+  c = __ev_mhessf (a, b);
+  c = __ev_mhesmf (a, b);
+  c = __ev_mhesmi (a, b);
+  c = __ev_mheumi (a, b);
+  c = __ev_mhossfa (a, b);
+  c = __ev_mhosmfa (a, b);
+  c = __ev_mhosmia (a, b);
+  c = __ev_mhoumia (a, b);
+  c = __ev_mhessfa (a, b);
+  c = __ev_mhesmfa (a, b);
+  c = __ev_mhesmia (a, b);
+  c = __ev_mheumia (a, b);
+
+  c = __ev_mhoumf (a, b);
+  c = __ev_mheumf (a, b);
+  c = __ev_mhoumfa (a, b);
+  c = __ev_mheumfa (a, b);
+
+  c = __ev_mhossfaaw (a, b);
+  c = __ev_mhossiaaw (a, b);
+  c = __ev_mhosmfaaw (a, b);
+  c = __ev_mhosmiaaw (a, b);
+  c = __ev_mhousiaaw (a, b);
+  c = __ev_mhoumiaaw (a, b);
+  c = __ev_mhessfaaw (a, b);
+  c = __ev_mhessiaaw (a, b);
+  c = __ev_mhesmfaaw (a, b);
+  c = __ev_mhesmiaaw (a, b);
+  c = __ev_mheusiaaw (a, b);
+  c = __ev_mheumiaaw (a, b);
+
+  c = __ev_mhousfaaw (a, b);
+  c = __ev_mhoumfaaw (a, b);
+  c = __ev_mheusfaaw (a, b);
+  c = __ev_mheumfaaw (a, b);
+
+  c = __ev_mhossfanw (a, b);
+  c = __ev_mhossianw (a, b);
+  c = __ev_mhosmfanw (a, b);
+  c = __ev_mhosmianw (a, b);
+  c = __ev_mhousianw (a, b);
+  c = __ev_mhoumianw (a, b);
+  c = __ev_mhessfanw (a, b);
+  c = __ev_mhessianw (a, b);
+  c = __ev_mhesmfanw (a, b);
+  c = __ev_mhesmianw (a, b);
+  c = __ev_mheusianw (a, b);
+  c = __ev_mheumianw (a, b);
+
+  c = __ev_mhousfanw (a, b);
+  c = __ev_mhoumfanw (a, b);
+  c = __ev_mheusfanw (a, b);
+  c = __ev_mheumfanw (a, b);
+
+  c = __ev_mhogsmfaa (a, b);
+  c = __ev_mhogsmiaa (a, b);
+  c = __ev_mhogumiaa (a, b);
+  c = __ev_mhegsmfaa (a, b);
+  c = __ev_mhegsmiaa (a, b);
+  c = __ev_mhegumiaa (a, b);
+
+  c = __ev_mhogumfaa (a, b);
+  c = __ev_mhegumfaa (a, b);
+
+  c = __ev_mhogsmfan (a, b);
+  c = __ev_mhogsmian (a, b);
+  c = __ev_mhogumian (a, b);
+  c = __ev_mhegsmfan (a, b);
+  c = __ev_mhegsmian (a, b);
+  c = __ev_mhegumian (a, b);
+
+  c = __ev_mhogumfan (a, b);
+  c = __ev_mhegumfan (a, b);
+
+  c = __ev_mwhssf (a, b);
+  c = __ev_mwhsmf (a, b);
+  c = __ev_mwhsmi (a, b);
+  c = __ev_mwhumi (a, b);
+  c = __ev_mwhssfa (a, b);
+  c = __ev_mwhsmfa (a, b);
+  c = __ev_mwhsmia (a, b);
+  c = __ev_mwhumia (a, b);
+
+  c = __ev_mwhumf (a, b);
+  c = __ev_mwhumfa (a, b);
+
+  c = __ev_mwlumi (a, b);
+  c = __ev_mwlumia (a, b);
+  c = __ev_mwlumiaaw (a, b);
+
+  c = __ev_mwlssiaaw (a, b);
+  c = __ev_mwlsmiaaw (a, b);
+  c = __ev_mwlusiaaw (a, b);
+  c = __ev_mwlusiaaw (a, b);
+
+  c = __ev_mwlssianw (a, b);
+  c = __ev_mwlsmianw (a, b);
+  c = __ev_mwlusianw (a, b);
+  c = __ev_mwlumianw (a, b);
+
+  c = __ev_mwssf (a, b);
+  c = __ev_mwsmf (a, b);
+  c = __ev_mwsmi (a, b);
+  c = __ev_mwumi (a, b);
+  c = __ev_mwssfa (a, b);
+  c = __ev_mwsmfa (a, b);
+  c = __ev_mwsmia (a, b);
+  c = __ev_mwumia (a, b);
+  c = __ev_mwumf (a, b);
+  c = __ev_mwumfa (a, b);
+  c = __ev_mwssfaa (a, b);
+  c = __ev_mwsmfaa (a, b);
+  c = __ev_mwsmiaa (a, b);
+  c = __ev_mwumiaa (a, b);
+  c = __ev_mwumfaa (a, b);
+  c = __ev_mwssfan (a, b);
+  c = __ev_mwsmfan (a, b);
+  c = __ev_mwsmian (a, b);
+  c = __ev_mwumian (a, b);
+  c = __ev_mwumfan (a, b);
+  c = __ev_addssiaaw (a);
+  c = __ev_addsmiaaw (a);
+  c = __ev_addusiaaw (a);
+  c = __ev_addumiaaw (a);
+  c = __ev_addusfaaw (a);
+  c = __ev_addumfaaw (a);
+  c = __ev_addsmfaaw (a);
+  c = __ev_addssfaaw (a);
+  c = __ev_subfssiaaw (a);
+  c = __ev_subfsmiaaw (a);
+  c = __ev_subfusiaaw (a);
+  c = __ev_subfumiaaw (a);
+  c = __ev_subfusfaaw (a);
+  c = __ev_subfumfaaw (a);
+  c = __ev_subfsmfaaw (a);
+  c = __ev_subfssfaaw (a);
+
+  /* Floating point SIMD instructions.  */
+  c = __ev_fsabs (a);
+  c = __ev_fsnabs (a);
+  c = __ev_fsneg (a);
+  c = __ev_fsadd (a, b);
+  c = __ev_fssub (a, b);
+  c = __ev_fsmul (a, b);
+  c = __ev_fsdiv (a, b);
+  c = __ev_fscfui (a);
+  c = __ev_fscfsi (a);
+  c = __ev_fscfuf (a);
+  c = __ev_fscfsf (a);
+  c = __ev_fsctui (a);
+  c = __ev_fsctsi (a);
+  c = __ev_fsctuf (a);
+  c = __ev_fsctsf (a);
+  c = __ev_fsctuiz (a);
+  c = __ev_fsctsiz (a);
+
+  /* Non supported sythetic instructions made from two instructions.  */
+
+  c = __ev_mwhssfaaw (a, b);
+  c = __ev_mwhssiaaw (a, b);
+  c = __ev_mwhsmfaaw (a, b);
+  c = __ev_mwhsmiaaw (a, b);
+  c = __ev_mwhusiaaw (a, b);
+  c = __ev_mwhumiaaw (a, b);
+  c = __ev_mwhusfaaw (a, b);
+  c = __ev_mwhumfaaw (a, b);
+  c = __ev_mwhssfanw (a, b);
+  c = __ev_mwhssianw (a, b);
+  c = __ev_mwhsmfanw (a, b);
+  c = __ev_mwhsmianw (a, b);
+  c = __ev_mwhusianw (a, b);
+  c = __ev_mwhumianw (a, b);
+  c = __ev_mwhusfanw (a, b);
+  c = __ev_mwhumfanw (a, b);
+
+  c = __ev_mwhgssfaa (a, b);
+  c = __ev_mwhgsmfaa (a, b);
+  c = __ev_mwhgsmiaa (a, b);
+  c = __ev_mwhgumiaa (a, b);
+  c = __ev_mwhgssfan (a, b);
+  c = __ev_mwhgsmfan (a, b);
+  c = __ev_mwhgsmian (a, b);
+  c = __ev_mwhgumian (a, b);
+
+  /* Creating, insertion, and extraction.  */
+
+  a = __ev_create_u64 ((uint64_t) 55);
+  a = __ev_create_s64 ((int64_t) 66);
+  a = __ev_create_fs (3.14F, 2.18F);
+  a = __ev_create_u32 ((uint32_t) 5, (uint32_t) i);
+  a = __ev_create_s32 ((int32_t) 5, (int32_t) 6);
+  a = __ev_create_u16 ((uint16_t) 6, (uint16_t) 6, (uint16_t) 7, (uint16_t) 1);
+  a = __ev_create_s16 ((int16_t) 6, (int16_t) 6, (int16_t) 7, (int16_t) 9);
+  a = __ev_create_sfix32_fs (3.0F, 2.0F);
+  a = __ev_create_ufix32_fs (3.0F, 2.0F);
+  a = __ev_create_ufix32_u32 (3U, 5U);
+  a = __ev_create_sfix32_s32 (6, 9);
+  ull = __ev_convert_u64 (a);
+  sll = __ev_convert_s64 (a);
+  i = __ev_get_upper_u32 (a);
+  ui = __ev_get_lower_u32 (a);
+  i = __ev_get_upper_s32 (a);
+  i = __ev_get_lower_s32 (a);
+  fl = __ev_get_upper_fs (a);
+  fl = __ev_get_lower_fs (a);
+  u16 = __ev_get_u16 (a, 5U);
+  s16 = __ev_get_s16 (a, 5U);
+  ui = __ev_get_upper_ufix32_u32 (a);
+  ui = __ev_get_lower_ufix32_u32 (a);
+  i = __ev_get_upper_sfix32_s32 (a);
+  i = __ev_get_lower_sfix32_s32 (a);
+  fl = __ev_get_upper_sfix32_fs (a);
+  fl = __ev_get_lower_sfix32_fs (a);
+  fl = __ev_get_upper_ufix32_fs (a);
+  fl = __ev_get_lower_ufix32_fs (a);
+  a = __ev_set_upper_u32 (a, 5U);
+  a = __ev_set_lower_u32 (a, 5U);
+  a = __ev_set_upper_s32 (a, 5U);
+  a = __ev_set_lower_s32 (a, 6U);
+  a = __ev_set_upper_fs (a, 6U);
+  a = __ev_set_lower_fs (a, fl);
+  a = __ev_set_upper_ufix32_u32 (a, 5U);
+  a = __ev_set_lower_ufix32_u32 (a, 5U);
+  a = __ev_set_upper_sfix32_s32 (a, 5);
+  a = __ev_set_lower_sfix32_s32 (a, 5);
+  a =  __ev_set_upper_sfix32_fs (a, fl);
+  a = __ev_set_lower_sfix32_fs (a, fl);
+  a = __ev_set_upper_ufix32_fs (a, fl);
+  a = __ev_set_lower_ufix32_fs (a, fl);
+  a = __ev_set_acc_u64 ((uint64_t) 640);
+  a = __ev_set_acc_s64 ((int64_t) 460);
+  a = __ev_set_acc_vec64 (b);
+  a = __ev_set_u32 (a, 5, 6);
+  a = __ev_set_s32 (a, 5, 6);
+  a = __ev_set_fs (a, fl, 5);
+  a = __ev_set_u16 (a, 5U, 3);
+  a = __ev_set_s16 (a, 5, 6);
+  a = __ev_set_ufix32_u32 (a, 5U, 6U);
+  a = __ev_set_sfix32_s32 (a, 3, 6);
+  a = __ev_set_ufix32_fs (a, fl, 5);
+  a = __ev_set_sfix32_fs (a, fl, 5);
+  ui = __ev_get_u32 (a, 1);
+  i = __ev_get_s32 (a, 0);
+  fl = __ev_get_fs (a, 1);
+  u16 = __ev_get_u16 (a, 2);
+  s16 = __ev_get_s16 (a, 2);
+  ui = __ev_get_ufix32_u32 (a, 1);
+  i = __ev_get_sfix32_s32 (a, 0);
+  fl = __ev_get_ufix32_fs (a, 1);
+  fl = __ev_get_sfix32_fs (a, 0);
+
+  /* Predicates.  */
+  i = __ev_any_gts (a, b);
+  i = __ev_all_gts (a, b);
+  i = __ev_upper_gts (a, b);
+  i = __ev_lower_gts (a, b);
+  a = __ev_select_gts (a, b, c, c);
+
+  i = __ev_any_gtu (a, b);
+  i = __ev_all_gtu (a, b);
+  i = __ev_upper_gtu (a, b);
+  i = __ev_lower_gtu (a, b);
+  a = __ev_select_gtu (a, b, c, c);
+
+  i = __ev_any_lts (a, b);
+  i = __ev_all_lts (a, b);
+  i = __ev_upper_lts (a, b);
+  i = __ev_lower_lts (a, b);
+  a = __ev_select_lts (a, b, c, c);
+
+  i = __ev_any_ltu (a, b);
+  i = __ev_all_ltu (a, b);
+  i = __ev_upper_ltu (a, b);
+  i = __ev_lower_ltu (a, b);
+  a = __ev_select_ltu (a, b, c, c);
+
+  i = __ev_any_eq (a, b);
+  i = __ev_all_eq (a, b);
+  i = __ev_upper_eq (a, b);
+  i = __ev_lower_eq (a, b);
+  a = __ev_select_eq (a, b, c, c);
+
+  i = __ev_any_fs_gt (a, b);
+  i = __ev_all_fs_gt (a, b);
+  i = __ev_upper_fs_gt (a, b);
+  i = __ev_lower_fs_gt (a, b);
+  a = __ev_select_fs_gt (a, b, c, c);
+
+  i = __ev_any_fs_lt (a, b);
+  i = __ev_all_fs_lt (a, b);
+  i = __ev_upper_fs_lt (a, b);
+  i = __ev_lower_fs_lt (a, b);
+  a = __ev_select_fs_lt (a, b, c, b);
+
+  i = __ev_any_fs_eq (a, b);
+  i = __ev_all_fs_eq (a, b);
+  i = __ev_upper_fs_eq (a, b);
+  i = __ev_lower_fs_eq (a, b);
+  a = __ev_select_fs_eq (a, b, c, c);
+
+  i = __ev_any_fs_tst_gt (a, b);
+  i = __ev_all_fs_tst_gt (a, b);
+  i = __ev_upper_fs_tst_gt (a, b);
+  i = __ev_lower_fs_tst_gt (a, b);
+  a = __ev_select_fs_tst_gt (a, b, c, c);
+
+  i = __ev_any_fs_tst_lt (a, b);
+  i = __ev_all_fs_tst_lt (a, b);
+  i = __ev_upper_fs_tst_lt (a, b);
+  i = __ev_lower_fs_tst_lt (a, b);
+  a = __ev_select_fs_tst_lt (a, b, c, c);
+
+  i = __ev_any_fs_tst_eq (a, b);
+  i = __ev_all_fs_tst_eq (a, b);
+  i = __ev_upper_fs_tst_eq (a, b);
+  i = __ev_lower_fs_tst_eq (a, b);
+  a = __ev_select_fs_tst_eq (a, b, c, c);
+}
+
+int
+main (void)
+{
+  /* Generic binary operations.  */
+  c = __builtin_spe_evaddw (a, b);
+  c = __builtin_spe_evand (a, b);
+  c = __builtin_spe_evandc (a, b);
+  c = __builtin_spe_evdivws (a, b);
+  c = __builtin_spe_evdivwu (a, b);
+  c = __builtin_spe_eveqv (a, b);
+  h = __builtin_spe_evfsadd (f, g);
+  h = __builtin_spe_evfsdiv (f, g);
+  h = __builtin_spe_evfsmul (f, g);
+  h = __builtin_spe_evfssub (f, g);
+  c = __builtin_spe_evlddx (ap, j);
+  c = __builtin_spe_evldhx (ap, j);
+  c = __builtin_spe_evldwx (ap, j);
+  c = __builtin_spe_evlhhesplatx (usp, j);
+  c = __builtin_spe_evlhhossplatx (usp, j);
+  c = __builtin_spe_evlhhousplatx (usp, j);
+  c = __builtin_spe_evlwhex (uip, j);
+  c = __builtin_spe_evlwhosx (uip, j);
+  c = __builtin_spe_evlwhoux (uip, j);
+  c = __builtin_spe_evlwhsplatx (uip, j);
+  c = __builtin_spe_evlwwsplatx (uip, j);
+  c = __builtin_spe_evmergehi (a, b);
+  c = __builtin_spe_evmergehilo (a, b);
+  c = __builtin_spe_evmergelo (a, b);
+  c = __builtin_spe_evmergelohi (a, b);
+  c = __builtin_spe_evmhegsmfaa (a, b);
+  c = __builtin_spe_evmhegsmfan (a, b);
+  c = __builtin_spe_evmhegsmiaa (a, b);
+  c = __builtin_spe_evmhegsmian (a, b);
+  c = __builtin_spe_evmhegumiaa (a, b);
+  c = __builtin_spe_evmhegumian (a, b);
+  c = __builtin_spe_evmhesmf (a, b);
+  c = __builtin_spe_evmhesmfa (a, b);
+  c = __builtin_spe_evmhesmfaaw (a, b);
+  c = __builtin_spe_evmhesmfanw (a, b);
+  c = __builtin_spe_evmhesmi (a, b);
+  c = __builtin_spe_evmhesmia (a, b);
+  c = __builtin_spe_evmhesmiaaw (a, b);
+  c = __builtin_spe_evmhesmianw (a, b);
+  c = __builtin_spe_evmhessf (a, b);
+  c = __builtin_spe_evmhessfa (a, b);
+  c = __builtin_spe_evmhessfaaw (a, b);
+  c = __builtin_spe_evmhessfanw (a, b);
+  c = __builtin_spe_evmhessiaaw (a, b);
+  c = __builtin_spe_evmhessianw (a, b);
+  c = __builtin_spe_evmheumi (a, b);
+  c = __builtin_spe_evmheumia (a, b);
+  c = __builtin_spe_evmheumiaaw (a, b);
+  c = __builtin_spe_evmheumianw (a, b);
+  c = __builtin_spe_evmheusiaaw (a, b);
+  c = __builtin_spe_evmheusianw (a, b);
+  c = __builtin_spe_evmhogsmfaa (a, b);
+  c = __builtin_spe_evmhogsmfan (a, b);
+  c = __builtin_spe_evmhogsmiaa (a, b);
+  c = __builtin_spe_evmhogsmian (a, b);
+  c = __builtin_spe_evmhogumiaa (a, b);
+  c = __builtin_spe_evmhogumian (a, b);
+  c = __builtin_spe_evmhosmf (a, b);
+  c = __builtin_spe_evmhosmfa (a, b);
+  c = __builtin_spe_evmhosmfaaw (a, b);
+  c = __builtin_spe_evmhosmfanw (a, b);
+  c = __builtin_spe_evmhosmi (a, b);
+  c = __builtin_spe_evmhosmia (a, b);
+  c = __builtin_spe_evmhosmiaaw (a, b);
+  c = __builtin_spe_evmhosmianw (a, b);
+  c = __builtin_spe_evmhossf (a, b);
+  c = __builtin_spe_evmhossfa (a, b);
+  c = __builtin_spe_evmhossfaaw (a, b);
+  c = __builtin_spe_evmhossfanw (a, b);
+  c = __builtin_spe_evmhossiaaw (a, b);
+  c = __builtin_spe_evmhossianw (a, b);
+  c = __builtin_spe_evmhoumi (a, b);
+  c = __builtin_spe_evmhoumia (a, b);
+  c = __builtin_spe_evmhoumiaaw (a, b);
+  c = __builtin_spe_evmhoumianw (a, b);
+  c = __builtin_spe_evmhousiaaw (a, b);
+  c = __builtin_spe_evmhousianw (a, b);
+  c = __builtin_spe_evmwhsmf (a, b);
+  c = __builtin_spe_evmwhsmfa (a, b);
+  c = __builtin_spe_evmwhsmi (a, b);
+  c = __builtin_spe_evmwhsmia (a, b);
+  c = __builtin_spe_evmwhssf (a, b);
+  c = __builtin_spe_evmwhssfa (a, b);
+  c = __builtin_spe_evmwhumi (a, b);
+  c = __builtin_spe_evmwhumia (a, b);
+  c = __builtin_spe_evmwlsmiaaw (a, b);
+  c = __builtin_spe_evmwlsmianw (a, b);
+  c = __builtin_spe_evmwlssiaaw (a, b);
+  c = __builtin_spe_evmwlssianw (a, b);
+  c = __builtin_spe_evmwlumi (a, b);
+  c = __builtin_spe_evmwlumia (a, b);
+  c = __builtin_spe_evmwlumiaaw (a, b);
+  c = __builtin_spe_evmwlumianw (a, b);
+  c = __builtin_spe_evmwlusiaaw (a, b);
+  c = __builtin_spe_evmwlusianw (a, b);
+  c = __builtin_spe_evmwsmf (a, b);
+  c = __builtin_spe_evmwsmfa (a, b);
+  c = __builtin_spe_evmwsmfaa (a, b);
+  c = __builtin_spe_evmwsmfan (a, b);
+  c = __builtin_spe_evmwsmi (a, b);
+  c = __builtin_spe_evmwsmia (a, b);
+  c = __builtin_spe_evmwsmiaa (a, b);
+  c = __builtin_spe_evmwsmian (a, b);
+  c = __builtin_spe_evmwssf (a, b);
+  c = __builtin_spe_evmwssfa (a, b);
+  c = __builtin_spe_evmwssfaa (a, b);
+  c = __builtin_spe_evmwssfan (a, b);
+  c = __builtin_spe_evmwumi (a, b);
+  c = __builtin_spe_evmwumia (a, b);
+  c = __builtin_spe_evmwumiaa (a, b);
+  c = __builtin_spe_evmwumian (a, b);
+  c = __builtin_spe_evnand (a, b);
+  c = __builtin_spe_evnor (a, b);
+  c = __builtin_spe_evor (a, b);
+  c = __builtin_spe_evorc (a, b);
+  c = __builtin_spe_evrlw (a, b);
+  c = __builtin_spe_evslw (a, b);
+  c = __builtin_spe_evsrws (a, b);
+  c = __builtin_spe_evsrwu (a, b);
+  c = __builtin_spe_evsubfw (a, b);
+  c = __builtin_spe_evxor (a, b);
+
+  c = __builtin_spe_evmwhssfaa (a, b);
+  c = __builtin_spe_evmwhssmaa (a, b);
+  c = __builtin_spe_evmwhsmfaa (a, b);
+  c = __builtin_spe_evmwhsmiaa (a, b);
+  c = __builtin_spe_evmwhusiaa (a, b);
+  c = __builtin_spe_evmwhumiaa (a, b);
+  c = __builtin_spe_evmwhssfan (a, b);
+  c = __builtin_spe_evmwhssian (a, b);
+  c = __builtin_spe_evmwhsmfan (a, b);
+  c = __builtin_spe_evmwhsmian (a, b);
+  c = __builtin_spe_evmwhusian (a, b);
+  c = __builtin_spe_evmwhumian (a, b);
+  c = __builtin_spe_evmwhgssfaa (a, b);
+  c = __builtin_spe_evmwhgsmfaa (a, b);
+  c = __builtin_spe_evmwhgsmiaa (a, b);
+  c = __builtin_spe_evmwhgumiaa (a, b);
+  c = __builtin_spe_evmwhgssfan (a, b);
+  c = __builtin_spe_evmwhgsmfan (a, b);
+  c = __builtin_spe_evmwhgsmian (a, b);
+  c = __builtin_spe_evmwhgumian (a, b);
+  i = __builtin_spe_brinc (i, j);
+
+  /* Generic unary operations.  */
+  a = __builtin_spe_evabs (b);
+  a = __builtin_spe_evaddsmiaaw (b);
+  a = __builtin_spe_evaddssiaaw (b);
+  a = __builtin_spe_evaddumiaaw (b);
+  a = __builtin_spe_evaddusiaaw (b);
+  a = __builtin_spe_evcntlsw (b);
+  a = __builtin_spe_evcntlzw (b);
+  a = __builtin_spe_evextsb (b);
+  a = __builtin_spe_evextsh (b);
+  f = __builtin_spe_evfsabs (g);
+  f = __builtin_spe_evfscfsf (g);
+  a = __builtin_spe_evfscfsi (g);
+  f = __builtin_spe_evfscfuf (g);
+  f = __builtin_spe_evfscfui (a);
+  f = __builtin_spe_evfsctsf (g);
+  a = __builtin_spe_evfsctsi (g);
+  a = __builtin_spe_evfsctsiz (g);
+  f = __builtin_spe_evfsctuf (g);
+  a = __builtin_spe_evfsctui (g);
+  a = __builtin_spe_evfsctuiz (g);
+  f = __builtin_spe_evfsnabs (g);
+  f = __builtin_spe_evfsneg (g);
+  a = __builtin_spe_evmra (b);
+  a = __builtin_spe_evneg (b);
+  a = __builtin_spe_evrndw (b);
+  a = __builtin_spe_evsubfsmiaaw (b);
+  a = __builtin_spe_evsubfssiaaw (b);
+  a = __builtin_spe_evsubfumiaaw (b);
+  a = __builtin_spe_evsubfusiaaw (b);
+
+  /* Unary operations of the form: X = foo (5_bit_signed_immediate).  */
+  a = __builtin_spe_evsplatfi (5);
+  a = __builtin_spe_evsplati (5);
+
+  /* Binary operations of the form: X = foo(Y, 5_bit_immediate).  */
+  a = __builtin_spe_evaddiw (b, 13);
+  a = __builtin_spe_evldd (ap, 13);
+  a = __builtin_spe_evldh (ap, 13);
+  a = __builtin_spe_evldw (ap, 13);
+  a = __builtin_spe_evlhhesplat (usp, 13);
+  a = __builtin_spe_evlhhossplat (usp, 13);
+  a = __builtin_spe_evlhhousplat (usp, 13);
+  a = __builtin_spe_evlwhe (uip, 13);
+  a = __builtin_spe_evlwhos (uip, 13);
+  a = __builtin_spe_evlwhou (uip, 13);
+  a = __builtin_spe_evlwhsplat (uip, 13);
+  a = __builtin_spe_evlwwsplat (uip, 13);
+
+  a = __builtin_spe_evrlwi (b, 13);
+  a = __builtin_spe_evslwi (b, 13);
+  a = __builtin_spe_evsrwis (b, 13);
+  a = __builtin_spe_evsrwiu (b, 13);
+  a = __builtin_spe_evsubifw (b, 13);
+
+  /* Store indexed builtins.  */
+  __builtin_spe_evstddx (b, ap, j);
+  __builtin_spe_evstdhx (b, ap, j);
+  __builtin_spe_evstdwx (b, ap, j);
+  __builtin_spe_evstwhex (b, uip, j);
+  __builtin_spe_evstwhox (b, uip, j);
+  __builtin_spe_evstwwex (b, uip, j);
+  __builtin_spe_evstwwox (b, uip, j);
+
+  /* Store indexed immediate builtins.  */
+  __builtin_spe_evstdd (b, ap, 5);
+  __builtin_spe_evstdh (b, ap, 5);
+  __builtin_spe_evstdw (b, ap, 5);
+  __builtin_spe_evstwhe (b, uip, 5);
+  __builtin_spe_evstwho (b, uip, 5);
+  __builtin_spe_evstwwe (b, uip, 5);
+  __builtin_spe_evstwwo (b, uip, 5);
+
+  /* SPEFSCR builtins.  */
+  i = __builtin_spe_mfspefscr ();
+  __builtin_spe_mtspefscr (j);
+
+  test_api ();
+  
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c
new file mode 100644
index 000000000..f07e818fa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c
@@ -0,0 +1,7 @@
+/* Test that SPE targets do not permit -m64.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile { target powerpc-*-*spe } } */
+/* { dg-options "-m64" } */
+
+/* { dg-error "-m64 not supported in this configuration" "SPE not 64-bit" { target *-*-* } 0 } */
+/* { dg-error "64-bit E500 not supported" "64-bit E500" { target *-*-* } 0 } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c
new file mode 100644
index 000000000..465fc41e1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c
@@ -0,0 +1,35 @@
+/* { dg-do run { target powerpc*-*-linux* powerpc*-*-eabi* } } */
+/* { dg-options {} } */
+
+/* Test stack pointer alignment against variable alloca.  */
+/* Inspired by PR libgcj/10610.  */
+/* Origin: Franz Sirl <Franz.Sirl-kernel@lauterbach.com>.  */
+
+extern void abort (void);
+extern void exit (int);
+
+register unsigned long sp __asm__ ("r1");
+
+void g (int * val __attribute__ ((unused)))
+{
+  if (sp & 0xf)
+    abort ();
+}
+
+void f (int val)
+{
+  int *val1 = __builtin_alloca (val);
+
+  g (val1);
+  return;
+}
+
+int main (void)
+{
+  int i;
+
+  for (i = 1; i < 32; i++)
+    f (i);
+  
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c
new file mode 100644
index 000000000..47a29ed3f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-mpowerpc-gfxopt" } */
+/* { dg-final { scan-assembler "stfiwx" } } */
+
+int foo (double x)
+{
+  return x;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c
new file mode 100644
index 000000000..a9a16ab2f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O -maltivec" } */
+/* { dg-final { scan-assembler "lvx" } } */
+
+void foo(void)
+{
+  int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 1, 1, 1, 1, 1 };
+  bar (x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c
new file mode 100644
index 000000000..1a290719c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O -maltivec" } */
+/* { dg-final { scan-assembler "stvx" } } */
+
+#include <string.h>
+
+void foo(void)
+{
+  int x[8] __attribute__((aligned(128)));
+  memset (x, 0, sizeof (x));
+  bar (x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c
new file mode 100644
index 000000000..1b836d727
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c
@@ -0,0 +1,229 @@
+/* { dg-do run { target { powerpc_fprs && { ilp32 && dfprt } } } } */
+/* { dg-options "-std=gnu99 -O2 -fno-strict-aliasing" } */
+
+/* Testcase to check for ABI compliance of parameter passing
+   for the PowerPC ELF ABI for decimal float values.  */
+
+extern void abort (void);
+int failcnt = 0;
+
+/* Support compiling the test to report individual failures; default is
+   to abort as soon as a check fails.  */
+#ifdef DBG
+#include <stdio.h>
+#define FAILURE { printf ("failed at line %d\n", __LINE__); failcnt++; }
+#else
+#define FAILURE abort ();
+#endif
+
+typedef struct
+{
+  int pad;
+  _Decimal32 d;
+} d32parm_t;
+
+typedef struct
+{
+  unsigned int gprs[8];
+  double fprs[8];
+} reg_parms_t;
+
+reg_parms_t gparms;
+
+
+/* Testcase could break on future gcc's, if parameter regs
+   are changed before this asm.  */
+
+#define save_parms(lparms)				\
+    asm volatile ("lis 11,gparms@ha\n\t"		\
+                  "la 11,gparms@l(11)\n\t"		\
+                  "st 3,0(11)\n\t"		        \
+	          "st 4,4(11)\n\t"			\
+	          "st 5,8(11)\n\t"			\
+	          "st 6,12(11)\n\t"			\
+	          "st 7,16(11)\n\t"			\
+	          "st 8,20(11)\n\t"			\
+	          "st 9,24(11)\n\t"			\
+	          "st 10,28(11)\n\t"			\
+                  "stfd 1,32(11)\n\t"			\
+	          "stfd 2,40(11)\n\t"			\
+	          "stfd 3,48(11)\n\t"			\
+	          "stfd 4,56(11)\n\t"			\
+	          "stfd 5,64(11)\n\t"			\
+	          "stfd 6,72(11)\n\t"			\
+	          "stfd 7,80(11)\n\t"			\
+	          "stfd 8,88(11)\n\t":::"11", "memory");  \
+                  lparms = gparms;
+
+typedef struct sf
+{
+  struct sf *backchain;
+  int a1;
+  unsigned int slot[200];
+} stack_frame_t;
+
+/* Fill up floating point registers with double arguments, forcing
+   decimal float arguments into the parameter save area.  */
+void __attribute__ ((noinline))
+func0 (double a1, double a2, double a3, double a4, double a5,
+       double a6, double a7, double a8, _Decimal64 a9, _Decimal128 a10)
+{
+  reg_parms_t lparms;
+  stack_frame_t *sp;
+
+  save_parms (lparms);
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != lparms.fprs[0]) FAILURE
+  if (a2 != lparms.fprs[1]) FAILURE
+  if (a3 != lparms.fprs[2]) FAILURE
+  if (a4 != lparms.fprs[3]) FAILURE
+  if (a5 != lparms.fprs[4]) FAILURE
+  if (a6 != lparms.fprs[5]) FAILURE
+  if (a7 != lparms.fprs[6]) FAILURE
+  if (a8 != lparms.fprs[7]) FAILURE
+  if (a9 != *(_Decimal64 *)&sp->slot[0]) FAILURE
+  if (a10 != *(_Decimal128 *)&sp->slot[2]) FAILURE
+}
+
+/* Alternate 64-bit and 128-bit decimal float arguments, checking that
+   _Decimal128 is always passed in even/odd register pairs.  */
+void __attribute__ ((noinline))
+func1 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4,
+       _Decimal64 a5, _Decimal128 a6, _Decimal64 a7, _Decimal128 a8)
+{
+  reg_parms_t lparms;
+  stack_frame_t *sp;
+
+  save_parms (lparms);
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != *(_Decimal64 *)&lparms.fprs[0]) FAILURE	/* f1 */
+  if (a2 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE	/* f2 & f3 */
+  if (a3 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE	/* f4 */
+  if (a4 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE	/* f6 & f7 */
+  if (a5 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE	/* f8 */
+  if (a6 != *(_Decimal128 *)&sp->slot[0]) FAILURE
+  if (a7 != *(_Decimal64 *)&sp->slot[4]) FAILURE
+  if (a8 != *(_Decimal128 *)&sp->slot[6]) FAILURE
+}
+
+void __attribute__ ((noinline))
+func2 (_Decimal128 a1, _Decimal64 a2, _Decimal128 a3, _Decimal64 a4,
+       _Decimal128 a5, _Decimal64 a6, _Decimal128 a7, _Decimal64 a8)
+{
+  reg_parms_t lparms;
+  stack_frame_t *sp;
+
+  save_parms (lparms);
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE	/* f2 & f3 */
+  if (a2 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE	/* f4 */
+  if (a3 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE	/* f6 & f7 */
+  if (a4 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE	/* f8 */
+  if (a5 != *(_Decimal128 *)&sp->slot[0]) FAILURE
+  if (a6 != *(_Decimal64 *)&sp->slot[4]) FAILURE
+  if (a7 != *(_Decimal128 *)&sp->slot[6]) FAILURE
+  if (a8 != *(_Decimal64 *)&sp->slot[10]) FAILURE
+}
+
+void __attribute__ ((noinline))
+func3 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4,
+       _Decimal64 a5)
+{
+  reg_parms_t lparms;
+  stack_frame_t *sp;
+
+  save_parms (lparms);
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != *(_Decimal64 *)&lparms.fprs[0]) FAILURE	/* f1 */
+  if (a2 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE	/* f2 & f3 */
+  if (a3 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE	/* f4 */
+  if (a4 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE	/* f6 & f7 */
+  if (a5 != *(_Decimal128 *)&sp->slot[0]) FAILURE
+}
+
+void __attribute__ ((noinline))
+func4 (_Decimal32 a1, _Decimal32 a2, _Decimal32 a3, _Decimal32 a4,
+       _Decimal32 a5, _Decimal32 a6, _Decimal32 a7, _Decimal32 a8,
+       _Decimal32 a9, _Decimal32 a10, _Decimal32 a11, _Decimal32 a12,
+       _Decimal32 a13, _Decimal32 a14, _Decimal32 a15, _Decimal32 a16)
+{
+  reg_parms_t lparms;
+  stack_frame_t *sp;
+
+  save_parms (lparms);
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  /* _Decimal32 is passed in the lower half of an FPR, or in parameter slot.  */
+  if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE		/* f1  */
+  if (a2 != ((d32parm_t *)&lparms.fprs[1])->d) FAILURE		/* f2  */
+  if (a3 != ((d32parm_t *)&lparms.fprs[2])->d) FAILURE		/* f3  */
+  if (a4 != ((d32parm_t *)&lparms.fprs[3])->d) FAILURE		/* f4  */
+  if (a5 != ((d32parm_t *)&lparms.fprs[4])->d) FAILURE		/* f5  */
+  if (a6 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE		/* f6  */
+  if (a7 != ((d32parm_t *)&lparms.fprs[6])->d) FAILURE		/* f7  */
+  if (a8 != ((d32parm_t *)&lparms.fprs[7])->d) FAILURE		/* f8  */
+  if (a9 != *(_Decimal32 *)&sp->slot[0]) FAILURE
+  if (a10 != *(_Decimal32 *)&sp->slot[1]) FAILURE
+  if (a11 != *(_Decimal32 *)&sp->slot[2]) FAILURE
+  if (a12 != *(_Decimal32 *)&sp->slot[3]) FAILURE
+  if (a13 != *(_Decimal32 *)&sp->slot[4]) FAILURE
+  if (a14 != *(_Decimal32 *)&sp->slot[5]) FAILURE
+  if (a15 != *(_Decimal32 *)&sp->slot[6]) FAILURE
+  if (a16 != *(_Decimal32 *)&sp->slot[7]) FAILURE
+}
+
+void __attribute__ ((noinline))
+func5 (_Decimal32 a1, _Decimal64 a2, _Decimal128 a3,
+       _Decimal32 a4, _Decimal64 a5, _Decimal128 a6,
+       _Decimal32 a7, _Decimal64 a8, _Decimal128 a9,
+       _Decimal32 a10, _Decimal64 a11, _Decimal128 a12)
+{
+  reg_parms_t lparms;
+  stack_frame_t *sp;
+
+  save_parms (lparms);
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE		/* f1      */
+  if (a2 != *(_Decimal64 *)&lparms.fprs[1]) FAILURE		/* f2      */
+  if (a3 != *(_Decimal128 *)&lparms.fprs[3]) FAILURE		/* f4 & f5 */
+  if (a4 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE		/* f6      */
+  if (a5 != *(_Decimal64 *)&lparms.fprs[6]) FAILURE		/* f7      */
+
+  if (a6 != *(_Decimal128 *)&sp->slot[0]) FAILURE
+  if (a7 != *(_Decimal32 *)&sp->slot[4]) FAILURE
+  if (a8 != *(_Decimal64 *)&sp->slot[6]) FAILURE
+  if (a9 != *(_Decimal128 *)&sp->slot[8]) FAILURE
+  if (a10 != *(_Decimal32 *)&sp->slot[12]) FAILURE
+  if (a11 != *(_Decimal64 *)&sp->slot[14]) FAILURE
+  if (a12 != *(_Decimal128 *)&sp->slot[16]) FAILURE
+}
+
+int
+main ()
+{
+  func0 (1., 2., 3., 4., 5., 6., 7., 8., 9.dd, 10.dl);
+  func1 (1.dd, 2.dl, 3.dd, 4.dl, 5.dd, 6.dl, 7.dd, 8.dl);
+  func2 (1.dl, 2.dd, 3.dl, 4.dd, 5.dl, 6.dd, 7.dl, 8.dd);
+  func3 (1.dd, 2.dl, 3.dd, 4.dl, 5.dl);
+  func4 (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df,
+	 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df,
+	 515.2df, 516.2df);
+  func5 (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl,
+	 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl);
+
+  if (failcnt != 0)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c
new file mode 100644
index 000000000..c2c08a860
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c
@@ -0,0 +1,363 @@
+/* { dg-do run { target { powerpc*-*-* && lp64 } } } */
+/* { dg-options "-O2" } */
+#include <stdarg.h>
+#include <signal.h>
+#include <stdio.h>
+
+/* Testcase to check for ABI compliance of parameter passing
+   for the PowerPC64 ABI.  
+   Parameter passing of integral and floating point is tested.  */
+
+extern void abort (void);
+
+typedef struct
+{
+  unsigned long gprs[8];
+  double fprs[13];
+} reg_parms_t;
+
+reg_parms_t gparms;
+
+
+/* Testcase could break on future gcc's, if parameter regs
+   are changed before this asm.  */
+
+#ifndef __MACH__
+#define save_parms(lparms)				\
+    asm volatile ("ld 11,gparms@got(2)\n\t"                \
+                  "std 3,0(11)\n\t"		        \
+	          "std 4,8(11)\n\t"			\
+	          "std 5,16(11)\n\t"			\
+	          "std 6,24(11)\n\t"			\
+	          "std 7,32(11)\n\t"			\
+	          "std 8,40(11)\n\t"			\
+	          "std 9,48(11)\n\t"			\
+	          "std 10,56(11)\n\t"                 \
+                  "stfd 1,64(11)\n\t"		        \
+	          "stfd 2,72(11)\n\t"			\
+	          "stfd 3,80(11)\n\t"			\
+	          "stfd 4,88(11)\n\t"			\
+	          "stfd 5,96(11)\n\t"			\
+	          "stfd 6,104(11)\n\t"			\
+	          "stfd 7,112(11)\n\t"			\
+	          "stfd 8,120(11)\n\t"			\
+	          "stfd 9,128(11)\n\t"			\
+	          "stfd 10,136(11)\n\t"			\
+	          "stfd 11,144(11)\n\t"			\
+	          "stfd 12,152(11)\n\t"                 \
+	          "stfd 13,160(11)\n\t":::"11", "memory");  \
+                  lparms = gparms;
+#else
+#define save_parms(lparms)				\
+    asm volatile ("ld r11,gparms@got(r2)\n\t"           \
+                  "std r3,0(r11)\n\t"		        \
+	          "std r4,8(r11)\n\t"			\
+	          "std r5,16(r11)\n\t"			\
+	          "std r6,24(r11)\n\t"			\
+	          "std r7,32(r11)\n\t"			\
+	          "std r8,40(r11)\n\t"			\
+	          "std r9,48(r11)\n\t"			\
+	          "std r10,56(r11)\n\t"                 \
+                  "stfd f1,64(r11)\n\t"		        \
+	          "stfd f2,72(r11)\n\t"			\
+	          "stfd f3,80(r11)\n\t"			\
+	          "stfd f4,88(r11)\n\t"			\
+	          "stfd f5,96(r11)\n\t"			\
+	          "stfd f6,104(r11)\n\t"		\
+	          "stfd f7,112(r11)\n\t"		\
+	          "stfd f8,120(r11)\n\t"		\
+	          "stfd f9,128(r11)\n\t"		\
+	          "stfd f10,136(r11)\n\t"		\
+	          "stfd f11,144(r11)\n\t"		\
+	          "stfd f12,152(r11)\n\t"               \
+	          "stfd f13,160(r11)\n\t":::"r11", "memory");  \
+                  lparms = gparms;
+#endif
+
+/* Stackframe structure relevant for parameter passing.  */
+typedef union
+{
+  double d;
+  unsigned long l;
+  unsigned int i[2];
+} parm_t;
+
+typedef struct sf
+{
+  struct sf *backchain;
+  long a1;
+  long a2;
+  long a3;
+  long a4;
+  long a5;
+  parm_t slot[100];
+} stack_frame_t;
+
+
+/* Paramter passing.
+   s : gpr 3
+   l : gpr 4
+   d : fpr 1
+*/
+void __attribute__ ((noinline)) fcld (char *s, long l, double d)
+{
+  reg_parms_t lparms;
+  save_parms (lparms);
+
+  if (s != (char *) lparms.gprs[0])
+    abort ();
+
+  if (l != lparms.gprs[1])
+    abort ();
+
+  if (d != lparms.fprs[0])
+    abort ();
+}
+
+/* Paramter passing.
+   s : gpr 3
+   l : gpr 4
+   d : fpr 2
+   i : gpr 5
+*/
+void __attribute__ ((noinline))
+fcldi (char *s, long l, double d, signed int i)
+{
+  reg_parms_t lparms;
+  save_parms (lparms);
+
+  if (s != (char *) lparms.gprs[0])
+    abort ();
+
+  if (l != lparms.gprs[1])
+    abort ();
+
+  if (d != lparms.fprs[0])
+    abort ();
+
+  if ((signed long) i != lparms.gprs[3])
+    abort ();
+}
+
+/* Paramter passing.
+   s : gpr 3
+   l : gpr 4
+   d : fpr 2
+   i : gpr 5
+*/
+void __attribute__ ((noinline))
+fcldu (char *s, long l, float d, unsigned int i)
+{
+  reg_parms_t lparms;
+  save_parms (lparms);
+
+  if (s != (char *) lparms.gprs[0])
+    abort ();
+
+  if (l != lparms.gprs[1])
+    abort ();
+
+  if ((double) d != lparms.fprs[0])
+    abort ();
+
+  if ((unsigned long) i != lparms.gprs[3])
+    abort ();
+}
+
+/* Paramter passing.
+   s : gpr 3
+   l : slot 1
+   d : slot 2
+*/
+
+void __attribute__ ((noinline)) fceld (char *s, ...)
+{
+  stack_frame_t *sp;
+  reg_parms_t lparms;
+  va_list arg;
+  double d;
+  long l;
+  save_parms (lparms);
+
+  va_start (arg, s);
+
+  if (s != (char *) lparms.gprs[0])
+    abort ();
+
+  l = va_arg (arg, long);
+  d = va_arg (arg, double);
+
+  /* Go back one frame.  */
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (sp->slot[1].l != l)
+    abort ();
+
+  if (sp->slot[2].d != d)
+    abort ();
+}
+
+/* Paramter passing.
+   s : gpr 3
+   i : gpr 4
+   j : gpr 5
+   d : slot 3
+   l : slot 4
+*/
+void __attribute__ ((noinline)) fciiedl (char *s, int i, int j, ...)
+{
+  stack_frame_t *sp;
+  reg_parms_t lparms;
+  va_list arg;
+  double d;
+  long l;
+  save_parms (lparms);
+
+  va_start (arg, j);
+
+  if (s != (char *) lparms.gprs[0])
+    abort ();
+
+  if ((long) i != lparms.gprs[1])
+    abort ();
+
+  if ((long) j != lparms.gprs[2])
+    abort ();
+
+  d = va_arg (arg, double);
+  l = va_arg (arg, long);
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (sp->slot[3].d != d)
+    abort ();
+
+  if (sp->slot[4].l != l)
+    abort ();
+}
+
+/* 
+Parameter     Register     Offset in parameter save area
+c             r3           0-7    (not stored in parameter save area)
+ff            f1           8-15   (not stored)
+d             r5           16-23  (not stored)
+ld            f2           24-31  (not stored)
+f             r7           32-39  (not stored)
+s             r8,r9        40-55  (not stored)
+gg            f3           56-63  (not stored)
+t             (none)       64-79  (stored in parameter save area)
+e             (none)       80-87  (stored)
+hh            f4           88-95  (stored)  
+
+*/
+
+typedef struct
+{
+  int a;
+  double dd;
+} sparm;
+
+typedef union
+{
+  int i[2];
+  long l;
+  double d;
+} double_t;
+
+/* Example from ABI documentation with slight changes.
+   Paramter passing. 
+   c  : gpr 3
+   ff : fpr 1
+   d  : gpr 5
+   ld : fpr 2
+   f  : gpr 7
+   s  : gpr 8 - 9
+   gg : fpr 3
+   t  : save area offset 64 - 79 
+   e  : save area offset 80 - 88
+   hh : fpr 4   
+*/
+
+void __attribute__ ((noinline))
+fididisdsid (int c, double ff, int d, double ld, int f,
+	     sparm s, double gg, sparm t, int e, double hh)
+{
+  stack_frame_t *sp;
+  reg_parms_t lparms;
+  double_t dx, dy;
+
+  save_parms (lparms);
+
+  /* Parm 0: int.  */
+  if ((long) c != lparms.gprs[0])
+    abort ();
+
+  /* Parm 1: double.  */
+  if (ff != lparms.fprs[0])
+    abort ();
+
+  /* Parm 2: int.  */
+  if ((long) d != lparms.gprs[2])
+    abort ();
+
+  /* Parm 3: double.  */
+  if (ld != lparms.fprs[1])
+    abort ();
+
+  /* Parm 4: int.  */
+  if ((long) f != lparms.gprs[4])
+    abort ();
+
+  /* Parm 5: struct sparm.  */
+  dx.l = lparms.gprs[5];
+  dy.l = lparms.gprs[6];
+
+  if (s.a != dx.i[0])
+    abort ();
+  if (s.dd != dy.d)
+    abort ();
+
+  /* Parm 6: double.  */
+  if (gg != lparms.fprs[2])
+    abort ();
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  /* Parm 7: struct sparm.  */
+  dx.l = sp->slot[8].l;
+  dy.l = sp->slot[9].l;
+  if (t.a != dx.i[0])
+    abort ();
+  if (t.dd != dy.d)
+    abort ();
+
+  /* Parm 8: int.  */
+  if (e != sp->slot[10].l)
+    abort ();
+
+  /* Parm 9: double.  */
+
+  if (hh != lparms.fprs[3])
+    abort ();
+}
+
+int
+main ()
+{
+  char *s = "ii";
+
+  fcld (s, 1, 1.0);
+  fcldi (s, 1, 1.0, -2);
+  fcldu (s, 1, 1.0, 2);
+  fceld (s, 1, 1.0);
+  fciiedl (s, 1, 2, 1.0, 3);
+  fididisdsid (1, 1.0, 2, 2.0, -1, (sparm)
+	       {
+	       3, 3.0}, 4.0, (sparm)
+	       {
+	       5, 5.0}, 6, 7.0);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c
new file mode 100644
index 000000000..a9883d9e3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c
@@ -0,0 +1,403 @@
+/* { dg-do run { target { { powerpc*-*-linux* && lp64 } && powerpc_altivec_ok } } } */
+/* { dg-options "-O2 -fprofile -mprofile-kernel -maltivec -mabi=altivec" } */
+#include <stdarg.h>
+#include <signal.h>
+#include <altivec.h>
+#include <stdlib.h>
+
+/* Testcase to check for ABI compliance of parameter passing
+   for the PowerPC64 ABI.  */
+
+void __attribute__((no_instrument_function))
+sig_ill_handler (int sig)
+{
+    exit(0);
+}
+
+extern void abort (void);
+
+typedef struct
+{
+  unsigned long gprs[8];
+  double fprs[13];
+  long pad;
+  vector int vrs[12];
+} reg_parms_t;
+
+reg_parms_t gparms;
+
+/* _mcount call is done on Linux ppc64 early in the prologue.
+   my_mcount will provide a entry point _mcount,
+   which will save all register to gparms. 
+   Note that _mcount need to restore lr to original value,
+   therefor use ctr to return.  
+*/
+
+void __attribute__((no_instrument_function))
+my_mcount() 
+{
+  asm volatile (".type	_mcount,@function\n\t"
+		".globl	_mcount\n\t"
+		"_mcount:\n\t"
+                "mflr 0\n\t"
+                "mtctr 0\n\t"
+                "ld 0,16(1)\n\t"
+		"mtlr 0\n\t"
+		"ld 11,gparms@got(2)\n\t" 
+		"std 3,0(11)\n\t"		
+		"std 4,8(11)\n\t"
+		"std 5,16(11)\n\t"	
+		"std 6,24(11)\n\t"	
+		"std 7,32(11)\n\t"	
+		"std 8,40(11)\n\t"	
+		"std 9,48(11)\n\t"	
+		"std 10,56(11)\n\t"   
+		"stfd 1,64(11)\n\t"	
+		"stfd 2,72(11)\n\t"	
+		"stfd 3,80(11)\n\t"	
+		"stfd 4,88(11)\n\t"	
+		"stfd 5,96(11)\n\t"	
+		"stfd 6,104(11)\n\t"	
+		"stfd 7,112(11)\n\t"	
+		"stfd 8,120(11)\n\t"	
+		"stfd 9,128(11)\n\t"	
+		"stfd 10,136(11)\n\t"	
+		"stfd 11,144(11)\n\t"	
+		"stfd 12,152(11)\n\t" 
+		"stfd 13,160(11)\n\t" 
+		"li 3,176\n\t"        
+		"stvx 2,3,11\n\t"	
+		"addi 3,3,16\n\t" 
+		"stvx 3,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 4,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 5,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 6,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 7,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 8,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 9,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 10,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 11,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 12,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 13,3,11\n\t"	
+		"ld 3,0(11)\n\t"
+		"bctr");
+}
+
+/* Stackframe structure relevant for parameter passing.  */
+typedef union
+{
+  double d;
+  unsigned long l;
+  unsigned int i[2];
+} parm_t;
+
+typedef struct sf
+{
+  struct sf *backchain;
+  long a1;
+  long a2;
+  long a3;
+  long a4;
+  long a5;
+  parm_t slot[100];
+} stack_frame_t;
+
+typedef union
+{
+  unsigned int i[4];
+  unsigned long l[2];
+  vector int v;
+} vector_int_t;
+
+/* Paramter passing.
+   s : gpr 3
+   v : vpr 2
+   i : gpr 7
+*/
+void __attribute__ ((noinline))
+fcvi (char *s, vector int v, int i)
+{
+  reg_parms_t lparms = gparms;
+
+  if (s != (char *) lparms.gprs[0])
+    abort();
+
+  if (!vec_all_eq (v, lparms.vrs[0]))
+    abort ();
+
+  if ((long) i != lparms.gprs[4])
+    abort();
+}
+/* Paramter passing.
+   s : gpr 3
+   v : vpr 2
+   w : vpr 3
+*/
+
+void __attribute__ ((noinline))
+fcvv (char *s, vector int v, vector int w)
+{
+  vector int a, c = {6, 8, 10, 12};
+  reg_parms_t lparms = gparms;
+
+  if (s != (char *) lparms.gprs[0])
+    abort();
+
+  if (!vec_all_eq (v, lparms.vrs[0]))
+    abort ();
+
+  if (!vec_all_eq (w, lparms.vrs[1]))
+    abort ();
+
+  a = vec_add (v,w);
+
+  if (!vec_all_eq (a, c))
+    abort ();
+}
+
+/* Paramter passing.
+   s : gpr 3
+   i : gpr 4
+   v : vpr 2
+   w : vpr 3
+*/
+void __attribute__ ((noinline))
+fcivv (char *s, int i, vector int v, vector int w)
+{
+  vector int a, c = {6, 8, 10, 12};
+  reg_parms_t lparms = gparms;
+
+  if (s != (char *) lparms.gprs[0])
+    abort();
+
+  if ((long) i != lparms.gprs[1])
+    abort();
+
+  if (!vec_all_eq (v, lparms.vrs[0]))
+    abort ();
+
+  if (!vec_all_eq (w, lparms.vrs[1]))
+    abort ();
+
+  a = vec_add (v,w);
+  
+  if (!vec_all_eq (a, c))
+    abort ();
+}
+
+/* Paramter passing.
+   s : gpr 3
+   v : slot 2-3
+   w : slot 4-5
+*/
+
+void __attribute__ ((noinline))
+fcevv (char *s, ...)
+{
+  vector int a, c = {6, 8, 10, 12};
+  vector int v,w;
+  stack_frame_t *sp;
+  reg_parms_t lparms = gparms;
+  va_list arg;
+
+  va_start (arg, s);
+
+  if (s != (char *) lparms.gprs[0])
+    abort();
+
+  v = va_arg(arg, vector int);
+  w = va_arg(arg, vector int);
+  a = vec_add (v,w);
+  
+  if (!vec_all_eq (a, c))
+    abort ();
+
+  /* Go back one frame.  */
+  sp = __builtin_frame_address(0);
+  sp = sp->backchain;
+  
+  if (sp->slot[2].l != 0x100000002ULL
+      || sp->slot[4].l != 0x500000006ULL)
+    abort();
+}
+
+/* Paramter passing.
+   s : gpr 3
+   i : gpr 4
+   j : gpr 5
+   v : slot 4-5
+   w : slot 6-7
+*/
+void __attribute__ ((noinline))
+fciievv (char *s, int i, int j, ...)
+{
+  vector int a, c = {6, 8, 10, 12};
+  vector int v,w;
+  stack_frame_t *sp;
+  reg_parms_t lparms = gparms;
+  va_list arg;
+
+  va_start (arg, j);
+
+  if (s != (char *) lparms.gprs[0])
+    abort();
+
+  if ((long) i != lparms.gprs[1])
+    abort();
+
+  if ((long) j != lparms.gprs[2])
+    abort();
+  
+  v = va_arg(arg, vector int);
+  w = va_arg(arg, vector int);
+  a = vec_add (v,w);
+  
+  if (!vec_all_eq (a, c))
+    abort ();
+
+  sp = __builtin_frame_address(0);
+  sp = sp->backchain;
+  
+  if (sp->slot[4].l != 0x100000002ULL
+      || sp->slot[6].l != 0x500000006ULL)
+    abort();
+}
+
+void __attribute__ ((noinline))
+fcvevv (char *s, vector int x, ...)
+{
+  vector int a, c = {7, 10, 13, 16};
+  vector int v,w;
+  stack_frame_t *sp;
+  reg_parms_t lparms = gparms;
+  va_list arg;
+
+  va_start (arg, x);
+  
+  v = va_arg(arg, vector int);
+  w = va_arg(arg, vector int);
+
+  a = vec_add (v,w);
+  a = vec_add (a, x);
+ 
+  if (!vec_all_eq (a, c))
+    abort ();
+
+  sp = __builtin_frame_address(0);
+  sp = sp->backchain;
+  
+  if (sp->slot[4].l != 0x100000002ULL
+      || sp->slot[6].l != 0x500000006ULL)
+    abort();
+}
+
+int __attribute__((no_instrument_function, noinline))
+main1() 
+{   
+  char *s = "vv";
+  vector int v = {1, 2, 3, 4};
+  vector int w = {5, 6, 7, 8};
+ 
+  fcvi (s, v, 2);
+  fcvv (s, v, w);
+  fcivv (s, 1, v, w);
+  fcevv (s, v, w);
+  fciievv (s, 1, 2, v, w);
+  fcvevv (s, v, v, w);
+  return 0;
+}
+
+int __attribute__((no_instrument_function)) 
+main()
+{
+  /* Exit on systems without altivec.  */
+  signal (SIGILL, sig_ill_handler);
+  /* Altivec instruction, 'vor %v0,%v0,%v0'.  */
+  asm volatile (".long 0x10000484");
+  signal (SIGILL, SIG_DFL);
+
+  return main1 ();
+}
+
+/* Paramter passing.
+   Function called with no prototype.
+   s : gpr 3
+   v : vpr 2 gpr 5-6
+   w : vpr 3 gpr 7-8
+   x : vpr 4 gpr 9-10
+   y : vpr 5 slot 8-9
+*/
+void
+fnp_cvvvv (char *s, vector int v, vector int w,
+	   vector int x, vector int y)
+{
+  vector int a, c = {12, 16, 20, 24};
+  reg_parms_t lparms = gparms;
+  stack_frame_t *sp;
+  vector_int_t v0, v1, v2, v3;
+
+  if (s != (char *) lparms.gprs[0])
+    abort();
+
+  if (!vec_all_eq (v, lparms.vrs[0]))
+    abort ();
+
+  if (!vec_all_eq (w, lparms.vrs[1]))
+    abort ();
+
+  if (!vec_all_eq (x, lparms.vrs[2]))
+    abort ();
+
+  if (!vec_all_eq (y, lparms.vrs[3]))
+    abort ();
+
+  a = vec_add (v,w);
+  a = vec_add (a,x);  
+  a = vec_add (a,y);  
+  
+  if (!vec_all_eq (a, c))
+    abort ();
+  
+  v0.v = lparms.vrs[0];
+  v1.v = lparms.vrs[1];
+  v2.v = lparms.vrs[2];
+  v3.v = lparms.vrs[3];
+
+  if (v0.l[0] != lparms.gprs[2])
+    abort ();
+
+  if (v0.l[1] != lparms.gprs[3])
+    abort ();
+
+  if (v1.l[0] != lparms.gprs[4])
+    abort ();
+
+  if (v1.l[1] != lparms.gprs[5])
+    abort ();
+
+  if (v2.l[0] != lparms.gprs[6])
+    abort ();
+
+  if (v2.l[1] != lparms.gprs[7])
+    abort ();
+
+  sp = __builtin_frame_address(0);
+  sp = sp->backchain;
+  
+  if (sp->slot[8].l != v3.l[0])
+    abort ();
+
+  if (sp->slot[9].l != v3.l[1])
+    abort ();
+}  
+  
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c
new file mode 100644
index 000000000..8c78c9e2b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-options "-Wall" } */
+/* Testcase to check for ABI compliance of parameter passing
+   for the PowerPC64 ABI.  */
+
+typedef int __attribute__((vector_size(16))) v4si;
+typedef int __attribute__((vector_size(8))) v2si;
+
+v4si 
+f(v4si v)
+{ /* { dg-error "altivec instructions are disabled" "PR18631" { xfail *-*-* } } */
+    return v;
+}
+
+v2si 
+g(v2si v)
+{
+    return v;
+}
+
+int 
+main()
+{
+    v4si v = { 1, 2, 3, 4 };
+    v2si w = { 5, 6 };
+    v = f (v); /* { dg-error "altivec instructions are disabled" "PR18631" { xfail *-*-* } } */
+    w = g (w);
+    return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c
new file mode 100644
index 000000000..3badf7f98
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c
@@ -0,0 +1,318 @@
+/* { dg-do run { target { powerpc64-*-* && { lp64 && dfprt } } } } */
+/* { dg-options "-std=gnu99 -O2 -fno-strict-aliasing" } */
+
+/* Testcase to check for ABI compliance of parameter passing
+   for the PowerPC64 ELF ABI for decimal float values.  */
+
+extern void abort (void);
+int failcnt = 0;
+
+/* Support compiling the test to report individual failures; default is
+   to abort as soon as a check fails.  */
+#ifdef DBG
+#include <stdio.h>
+#define FAILURE { printf ("failed at line %d\n", __LINE__); failcnt++; }
+#else
+#define FAILURE abort ();
+#endif
+
+typedef struct
+{
+  int pad;
+  _Decimal32 d;
+} d32parm_t;
+
+typedef struct
+{
+  unsigned long gprs[8];
+  double fprs[13];
+} reg_parms_t;
+
+reg_parms_t gparms;
+
+
+/* Testcase could break on future gcc's, if parameter regs
+   are changed before this asm.  */
+
+#ifndef __MACH__
+#define save_parms(lparms)				\
+    asm volatile ("ld 11,gparms@got(2)\n\t"                \
+                  "std 3,0(11)\n\t"		        \
+	          "std 4,8(11)\n\t"			\
+	          "std 5,16(11)\n\t"			\
+	          "std 6,24(11)\n\t"			\
+	          "std 7,32(11)\n\t"			\
+	          "std 8,40(11)\n\t"			\
+	          "std 9,48(11)\n\t"			\
+	          "std 10,56(11)\n\t"			\
+                  "stfd 1,64(11)\n\t"			\
+	          "stfd 2,72(11)\n\t"			\
+	          "stfd 3,80(11)\n\t"			\
+	          "stfd 4,88(11)\n\t"			\
+	          "stfd 5,96(11)\n\t"			\
+	          "stfd 6,104(11)\n\t"			\
+	          "stfd 7,112(11)\n\t"			\
+	          "stfd 8,120(11)\n\t"			\
+	          "stfd 9,128(11)\n\t"			\
+	          "stfd 10,136(11)\n\t"			\
+	          "stfd 11,144(11)\n\t"			\
+	          "stfd 12,152(11)\n\t"                 \
+	          "stfd 13,160(11)\n\t":::"11", "memory");  \
+                  lparms = gparms;
+#else
+#define save_parms(lparms)				\
+    asm volatile ("ld r11,gparms@got(r2)\n\t"           \
+                  "std r3,0(r11)\n\t"		        \
+	          "std r4,8(r11)\n\t"			\
+	          "std r5,16(r11)\n\t"			\
+	          "std r6,24(r11)\n\t"			\
+	          "std r7,32(r11)\n\t"			\
+	          "std r8,40(r11)\n\t"			\
+	          "std r9,48(r11)\n\t"			\
+	          "std r10,56(r11)\n\t"                 \
+                  "stfd f1,64(r11)\n\t"		        \
+	          "stfd f2,72(r11)\n\t"			\
+	          "stfd f3,80(r11)\n\t"			\
+	          "stfd f4,88(r11)\n\t"			\
+	          "stfd f5,96(r11)\n\t"			\
+	          "stfd f6,104(r11)\n\t"		\
+	          "stfd f7,112(r11)\n\t"		\
+	          "stfd f8,120(r11)\n\t"		\
+	          "stfd f9,128(r11)\n\t"		\
+	          "stfd f10,136(r11)\n\t"		\
+	          "stfd f11,144(r11)\n\t"		\
+	          "stfd f12,152(r11)\n\t"               \
+	          "stfd f13,160(r11)\n\t":::"r11", "memory");  \
+                  lparms = gparms;
+#endif
+
+typedef struct sf
+{
+  struct sf *backchain;
+  long a1;
+  long a2;
+  long a3;
+  long a4;
+  long a5;
+  unsigned long slot[100];
+} stack_frame_t;
+
+/* Fill up floating point registers with double arguments, forcing
+   decimal float arguments into the parameter save area.  */
+void __attribute__ ((noinline))
+func0 (double a1, double a2, double a3, double a4, double a5, double a6,
+       double a7, double a8, double a9, double a10, double a11, double a12,
+       double a13, double a14, 
+       _Decimal64 a15, _Decimal128 a16, _Decimal64 a17)
+{
+  reg_parms_t lparms;
+  stack_frame_t *sp;
+
+  save_parms (lparms);
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != lparms.fprs[0]) FAILURE
+  if (a2 != lparms.fprs[1]) FAILURE
+  if (a3 != lparms.fprs[2]) FAILURE
+  if (a4 != lparms.fprs[3]) FAILURE
+  if (a5 != lparms.fprs[4]) FAILURE
+  if (a6 != lparms.fprs[5]) FAILURE
+  if (a7 != lparms.fprs[6]) FAILURE
+  if (a8 != lparms.fprs[7]) FAILURE
+  if (a9 != lparms.fprs[8]) FAILURE
+  if (a10 != lparms.fprs[9]) FAILURE
+  if (a11 != lparms.fprs[10]) FAILURE
+  if (a12 != lparms.fprs[11]) FAILURE
+  if (a13 != lparms.fprs[12]) FAILURE
+  if (a14 != *(double *)&sp->slot[13]) FAILURE
+  if (a15 != *(_Decimal64 *)&sp->slot[14]) FAILURE
+  if (a16 != *(_Decimal128 *)&sp->slot[15]) FAILURE
+  if (a17 != *(_Decimal64 *)&sp->slot[17]) FAILURE
+}
+
+void __attribute__ ((noinline))
+func1 (double a1, double a2, double a3, double a4, double a5, double a6,
+       double a7, double a8, double a9, double a10, double a11, double a12,
+       double a13, _Decimal128 a14)
+{
+  reg_parms_t lparms;
+  stack_frame_t *sp;
+
+  save_parms (lparms);
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != lparms.fprs[0]) FAILURE
+  if (a2 != lparms.fprs[1]) FAILURE
+  if (a3 != lparms.fprs[2]) FAILURE
+  if (a4 != lparms.fprs[3]) FAILURE
+  if (a5 != lparms.fprs[4]) FAILURE
+  if (a6 != lparms.fprs[5]) FAILURE
+  if (a7 != lparms.fprs[6]) FAILURE
+  if (a8 != lparms.fprs[7]) FAILURE
+  if (a9 != lparms.fprs[8]) FAILURE
+  if (a10 != lparms.fprs[9]) FAILURE
+  if (a11 != lparms.fprs[10]) FAILURE
+  if (a12 != lparms.fprs[11]) FAILURE
+  if (a13 != lparms.fprs[12]) FAILURE
+  if (a14 != *(_Decimal128 *)&sp->slot[13]) FAILURE
+}
+
+void __attribute__ ((noinline))
+func2 (double a1, double a2, double a3, double a4, double a5, double a6,
+       double a7, double a8, double a9, double a10, double a11, double a12,
+       _Decimal128 a13)
+{
+  reg_parms_t lparms;
+  stack_frame_t *sp;
+
+  save_parms (lparms);
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != lparms.fprs[0]) FAILURE
+  if (a2 != lparms.fprs[1]) FAILURE
+  if (a3 != lparms.fprs[2]) FAILURE
+  if (a4 != lparms.fprs[3]) FAILURE
+  if (a5 != lparms.fprs[4]) FAILURE
+  if (a6 != lparms.fprs[5]) FAILURE
+  if (a7 != lparms.fprs[6]) FAILURE
+  if (a8 != lparms.fprs[7]) FAILURE
+  if (a9 != lparms.fprs[8]) FAILURE
+  if (a10 != lparms.fprs[9]) FAILURE
+  if (a11 != lparms.fprs[10]) FAILURE
+  if (a12 != lparms.fprs[11]) FAILURE
+  if (a13 != *(_Decimal128 *)&sp->slot[12]) FAILURE
+}
+
+void __attribute__ ((noinline))
+func3 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4,
+       _Decimal64 a5, _Decimal128 a6, _Decimal64 a7, _Decimal128 a8,
+       _Decimal64 a9, _Decimal128 a10)
+{
+  reg_parms_t lparms;
+  stack_frame_t *sp;
+
+  save_parms (lparms);
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != *(_Decimal64 *)&lparms.fprs[0]) FAILURE	/* f1        */
+  if (a2 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE	/* f2 & f3   */
+  if (a3 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE	/* f4        */
+  if (a4 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE	/* f6 & f7   */
+  if (a5 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE	/* f8        */
+  if (a6 != *(_Decimal128 *)&lparms.fprs[9]) FAILURE	/* f10 & f11 */
+  if (a7 != *(_Decimal64 *)&lparms.fprs[11]) FAILURE	/* f12       */
+  if (a8 != *(_Decimal128 *)&sp->slot[10]) FAILURE
+  if (a9 != *(_Decimal64 *)&sp->slot[12]) FAILURE
+  if (a10 != *(_Decimal128 *)&sp->slot[13]) FAILURE
+}
+
+void __attribute__ ((noinline))
+func4 (_Decimal128 a1, _Decimal64 a2, _Decimal128 a3, _Decimal64 a4,
+       _Decimal128 a5, _Decimal64 a6, _Decimal128 a7, _Decimal64 a8)
+{
+  reg_parms_t lparms;
+  stack_frame_t *sp;
+
+  save_parms (lparms);
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE	/* f2 & f3   */
+  if (a2 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE	/* f4        */
+  if (a3 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE	/* f6 & f7   */
+  if (a4 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE	/* f8        */
+  if (a5 != *(_Decimal128 *)&lparms.fprs[9]) FAILURE	/* f10 & f11 */
+  if (a6 != *(_Decimal64 *)&lparms.fprs[11]) FAILURE	/* f12       */
+  if (a7 != *(_Decimal128 *)&sp->slot[9]) FAILURE
+  if (a8 != *(_Decimal64 *)&sp->slot[11]) FAILURE
+}
+
+void __attribute__ ((noinline))
+func5 (_Decimal32 a1, _Decimal32 a2, _Decimal32 a3, _Decimal32 a4,
+       _Decimal32 a5, _Decimal32 a6, _Decimal32 a7, _Decimal32 a8,
+       _Decimal32 a9, _Decimal32 a10, _Decimal32 a11, _Decimal32 a12,
+       _Decimal32 a13, _Decimal32 a14, _Decimal32 a15, _Decimal32 a16)
+{
+  reg_parms_t lparms;
+  stack_frame_t *sp;
+
+  save_parms (lparms);
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  /* _Decimal32 is passed in the lower half of an FPR or parameter slot.  */
+  if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE		/* f1  */
+  if (a2 != ((d32parm_t *)&lparms.fprs[1])->d) FAILURE		/* f2  */
+  if (a3 != ((d32parm_t *)&lparms.fprs[2])->d) FAILURE		/* f3  */
+  if (a4 != ((d32parm_t *)&lparms.fprs[3])->d) FAILURE		/* f4  */
+  if (a5 != ((d32parm_t *)&lparms.fprs[4])->d) FAILURE		/* f5  */
+  if (a6 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE		/* f6  */
+  if (a7 != ((d32parm_t *)&lparms.fprs[6])->d) FAILURE		/* f7  */
+  if (a8 != ((d32parm_t *)&lparms.fprs[7])->d) FAILURE		/* f8  */
+  if (a9 != ((d32parm_t *)&lparms.fprs[8])->d) FAILURE		/* f9  */
+  if (a10 != ((d32parm_t *)&lparms.fprs[9])->d) FAILURE		/* f10 */
+  if (a11 != ((d32parm_t *)&lparms.fprs[10])->d) FAILURE	/* f11 */
+  if (a12 != ((d32parm_t *)&lparms.fprs[11])->d) FAILURE	/* f12 */
+  if (a13 != ((d32parm_t *)&lparms.fprs[12])->d) FAILURE	/* f13 */
+  if (a14 != ((d32parm_t *)&sp->slot[13])->d) FAILURE
+  if (a15 != ((d32parm_t *)&sp->slot[14])->d) FAILURE
+  if (a16 != ((d32parm_t *)&sp->slot[15])->d) FAILURE
+}
+
+void __attribute__ ((noinline))
+func6 (_Decimal32 a1, _Decimal64 a2, _Decimal128 a3,
+       _Decimal32 a4, _Decimal64 a5, _Decimal128 a6,
+       _Decimal32 a7, _Decimal64 a8, _Decimal128 a9,
+       _Decimal32 a10, _Decimal64 a11, _Decimal128 a12)
+{
+  reg_parms_t lparms;
+  stack_frame_t *sp;
+
+  save_parms (lparms);
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE		/* f1        */
+  if (a2 != *(_Decimal64 *)&lparms.fprs[1]) FAILURE		/* f2        */
+  if (a3 != *(_Decimal128 *)&lparms.fprs[3]) FAILURE		/* f4 & f5   */
+  if (a4 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE		/* f6        */
+  if (a5 != *(_Decimal64 *)&lparms.fprs[6]) FAILURE		/* f7        */
+  if (a6 != *(_Decimal128 *)&lparms.fprs[7]) FAILURE		/* f8 & f9   */
+  if (a7 != ((d32parm_t *)&lparms.fprs[9])->d) FAILURE		/* f10       */
+  if (a8 != *(_Decimal64 *)&lparms.fprs[10]) FAILURE		/* f11       */
+  if (a9 != *(_Decimal128 *)&lparms.fprs[11]) FAILURE		/* f12 & f13 */
+  if (a10 != ((d32parm_t *)&sp->slot[12])->d) FAILURE
+  if (a11 != *(_Decimal64 *)&sp->slot[13]) FAILURE
+}
+
+int
+main (void)
+{
+  func0 (1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, 8.5, 9.5, 10.5, 11.5, 12.5, 13.5,
+	 14.5, 15.2dd, 16.2dl, 17.2dd);
+  func1 (101.5, 102.5, 103.5, 104.5, 105.5, 106.5, 107.5, 108.5, 109.5,
+	 110.5, 111.5, 112.5, 113.5, 114.2dd);
+  func2 (201.5, 202.5, 203.5, 204.5, 205.5, 206.5, 207.5, 208.5, 209.5,
+	 210.5, 211.5, 212.5, 213.2dd);
+  func3 (301.2dd, 302.2dl, 303.2dd, 304.2dl, 305.2dd, 306.2dl, 307.2dd,
+	 308.2dl, 309.2dd, 310.2dl);
+  func4 (401.2dl, 402.2dd, 403.2dl, 404.2dd, 405.2dl, 406.2dd, 407.2dl,
+	 408.2dd);
+#if 0
+  /* _Decimal32 doesn't yet follow the ABI; enable this when it does.  */
+  func5 (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df,
+	 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df,
+	 515.2df, 516.2df);
+  func6 (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl,
+	 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl);
+#endif
+
+  if (failcnt != 0)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c
new file mode 100644
index 000000000..eb1af58aa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c
@@ -0,0 +1,12 @@
+// { dg-do compile }
+// { dg-options "-O2 -mpowerpc64" }
+// xfail: PR middle-end/37272
+// { dg-final { scan-assembler-not "stfd" { xfail lp64 }  }  }
+
+// The register allocator should have allocated the temporary long long value in a floating point register.
+
+double
+d2ll2d (double d)
+{
+        return (double)(long long)d;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c
new file mode 100644
index 000000000..21090af23
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c
@@ -0,0 +1,22 @@
+/* { dg-do link } */
+/* { dg-options "-mminimal-toc" { target { powerpc*-*-* && lp64 } } } */
+
+char *strchr (const char *, int);
+
+int
+foo (int a)
+{
+  int b;
+
+  b = 0;
+  if ("/"[1] != '\0')
+    if (strchr ("/", a))
+      b = 1;
+  return b;
+}
+
+int
+main (void)
+{
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppu-intrinsics.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppu-intrinsics.c
new file mode 100644
index 000000000..3d9afb25a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/ppu-intrinsics.c
@@ -0,0 +1,43 @@
+/* { dg-do link { target { *-*-linux* && powerpc_fprs } } } */
+/* { dg-options "-W -Wall -Wno-uninitialized -mcpu=cell" } */
+/* Test some PPU intrinsics from <ppu_intrinsics.h>.  */
+
+#include <ppu_intrinsics.h>
+
+int main ()
+{
+  double d, d1, d2;
+  float f, f1, f2;
+  unsigned long long ull, a, b;
+  long long ll;
+  int i;
+
+#ifdef __powerpc64__
+  ull = __rldcl (a, b, 3);
+  ull = __rldcr (a, b, 3);
+  ull = __rldic (a, 3, 4);
+  ull = __rldicl (a, 4, 5);
+  ull = __rldicr (a, 2, 3);
+  ull = __rldimi (a, b, 4, 6);
+#endif
+  ull = __rlwimi (a, b, 6, 9, 12);
+  ull = __rlwnm (a, b, 3, 5);
+  d = __fmul (d1, d2);
+  f = __fmuls (f1, f2);
+  f = __frsp (f);
+  d = __fcfid (ll);
+  d = __frsqrte (d1);
+  ll = __fctid (d);
+  ll = __fctidz (d);
+  i = __fctiw (d);
+  i = __fctiwz (d);
+
+  __protected_stream_count (1, 2);
+  __protected_stream_go ();
+  __protected_stream_set (1, 0x1000, 3);
+  __protected_stream_stop (3);
+  __protected_stream_stop_all ();
+  __protected_unlimited_stream_set (3, 0x1000, 1);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr16155.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr16155.c
new file mode 100644
index 000000000..fffe957dc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr16155.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -ansi" } */
+
+/* PR 16155
+ * Compilation of a simple altivec test program fails if the -ansi flag is
+ * given to gcc, when compiling with -maltivec.
+ */
+
+#include <altivec.h>
+
+void foo(void)
+{
+  vector unsigned short a, b;
+  a = vec_splat(b, 0);
+}
+
+/* { dg-bogus "parse error before \"typeof\"" "-maltivec -mansi" { target powerpc*-*-* } 0 } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr16286.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr16286.c
new file mode 100644
index 000000000..790b6409f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr16286.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* PR 16286
+   Compilation of a simple Altivec test program fails if vector, pixel
+   and/or bool are #undefined when compiling with -maltivec.  This may be
+   done for building C++ programs that use the STL <vector>.  */
+
+#include <altivec.h>
+#undef vector
+#undef pixel
+#undef bool
+
+void test(void)
+{
+        __vector unsigned int a, b;
+	__vector __pixel v0;
+	__vector __bool v1;
+
+        a = vec_and(a, b);
+	vec_step (b);
+}
+
+/* { dg-bogus "(syntax|parse) error before \"vector\"" "-maltivec" { target powerpc*-*-* } 0 } */
+/* { dg-bogus "(syntax|parse) error before \"pixel\"" "-maltivec" { target powerpc*-*-* } 0 } */
+/* { dg-bogus "(syntax|parse) error before \"bool\"" "-maltivec" { target powerpc*-*-* } 0 } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr18096-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr18096-1.c
new file mode 100644
index 000000000..74612f393
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr18096-1.c
@@ -0,0 +1,12 @@
+/* PR middle-end/18096  */
+/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
+/* { dg-options "-O2" } */
+
+void f(char*);
+
+void mkcatdefs(char *fname) /* { dg-error "too large" "stack frame too large" } */
+{
+  char line [2147483647];
+  f(line);
+} 
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr25960.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr25960.c
new file mode 100644
index 000000000..9ab9a10a1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr25960.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* powerpc*-*-linux* } } } */
+/* { dg-options "-O2 -mlong-double-128" } */
+
+extern void abort (void);
+
+volatile long double l, m, n;
+
+int
+main (void)
+{
+  l = __builtin_copysignl (0.0L, -1.0L);
+  m = __builtin_copysignl (0.0L, -1.0L);
+  n = l + m;
+  if (__builtin_copysignl (1.0L, n) >= 0.0L)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr26350.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr26350.c
new file mode 100644
index 000000000..6b4b20627
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr26350.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* powerpc*-*-linux* } } } */
+/* { dg-options "-O2 -mlong-double-128 -fpic" } */
+
+typedef int int32_t __attribute__ ((__mode__ (__SI__)));
+typedef unsigned char uint8_t;
+typedef unsigned int uint32_t;
+typedef struct REGS REGS;
+typedef union { uint32_t F; } FW;
+typedef union { struct { FW L; } F; } DW;
+typedef struct _PSW {
+  DW ia;
+} PSW;
+struct REGS {
+  PSW psw;
+  DW cr[16];
+};
+struct ebfp {
+  long double v;
+};
+
+void s390_convert_fix32_to_bfp_ext_reg (REGS *regs)
+{
+  struct ebfp op1;
+  int32_t op2;
+  ((regs))->psw.ia.F.L.F += (4);
+  if(!((regs)->cr[(0)].F.L.F & 0x00040000))
+    op1.v = (long double)op2;
+  put_ebfp(&op1);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr27158.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr27158.c
new file mode 100644
index 000000000..5476577a9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr27158.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec" } */
+#define REGLIST                                                              \
+         "77",  "78",  "79",  "80",  "81",  "82",  "83",  "84",  "85",  "86",\
+         "87",  "88",  "89",  "90",  "91",  "92",  "93",  "94",  "95",  "96",\
+         "97",  "98",  "99", "100", "101", "102", "103", "104", "105", "106",\
+        "107", "108"
+
+typedef __attribute__ ((vector_size (16))) float v4sf;
+
+void
+foo (int H)
+{
+  volatile v4sf tmp;
+  while (H-- > 0)
+    {
+      asm ("" : : : REGLIST);
+      tmp = (v4sf) __builtin_altivec_vspltisw (1);
+    }
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr35907.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr35907.c
new file mode 100644
index 000000000..7d5465ea1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr35907.c
@@ -0,0 +1,57 @@
+/* PR target/35907 */
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec" } */
+
+#define vector __attribute__((vector_size (16)))
+union
+{
+  vector int k;
+  int c[16];
+} u, v, w;
+vector int m;
+
+void __attribute__((noinline))
+bar (void *i, vector int j)
+{
+  asm volatile ("" : : "r" (i), "r" (&j) : "memory");
+}
+
+int __attribute__((noinline))
+foo (int i, vector int j)
+{
+  char *p = __builtin_alloca (64 + i);
+  m += u.k;
+  v.k = m;
+  w.k = j;
+  if (__builtin_memcmp (&v.c, &w.c, 16) != 0)
+    __builtin_abort ();
+  j += u.k;
+  bar (p, j);
+  j += u.k;
+  bar (p, j);
+  return 0;
+}
+
+void
+test (void)
+{
+  vector int l;
+  int i;
+  for (i = 0; i < 4; i++)
+    u.c[i] = i;
+  l = u.k;
+  if (foo (64, l))
+    __builtin_abort ();
+  l += u.k;
+  if (foo (64, l))
+    __builtin_abort ();
+}
+
+int
+main ()
+{
+  test ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr37168.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr37168.c
new file mode 100644
index 000000000..8d35157d0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr37168.c
@@ -0,0 +1,14 @@
+/* PR target/37168 */
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec" } */
+
+#define C 3.68249351546114573519399405666776E-44f
+#define vector __attribute__ ((altivec (vector__)))
+
+vector float
+foo (vector float a)
+{
+  vector float b = __builtin_vec_madd (b, a, (vector float) { C, C, C, C });
+  return b;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr39902-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr39902-2.c
new file mode 100644
index 000000000..463a36c1b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/pr39902-2.c
@@ -0,0 +1,28 @@
+/* Check that simplification "x*(-1)" -> "-x" is not performed for decimal
+   float types.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */
+/* { dg-options "-std=gnu99 -O -mcpu=power6" } */
+/* { dg-final { scan-assembler-not "fneg" } } */
+
+extern _Decimal32 a32, b32;
+extern _Decimal64 a64, b64;
+extern _Decimal128 a128, b128;
+
+void
+foo32 (void)
+{
+  b32 = a32 * -1.0DF;
+}
+
+void
+foo64 (void)
+{
+  b64 = a64 * -1.0DD;
+}
+
+void
+foo128 (void)
+{
+  b128 = a128 * -1.0DL;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rotate.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rotate.c
new file mode 100644
index 000000000..5d47215d9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rotate.c
@@ -0,0 +1,6 @@
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "slwi" } } */
+unsigned int foo (unsigned int x)
+{
+  return ((x >> 16) & 0xffff) | ((x & 0xffff) << 16);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c
new file mode 100644
index 000000000..66bb61d25
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target powerpc*-*-darwin* powerpc*-*-linux* } } */
+/* { dg-options "-mno-powerpc-gfxopt -mpowerpc64" } */
+extern void bar (void *);
+extern double x;
+void
+foo (void)
+{
+  char buf2 [32][1024];
+  bar (buf2 [(int) x]);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c
new file mode 100644
index 000000000..410f780de
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target powerpc*-*-* rs6000-*-* } } */
+/* { dg-options "-mno-powerpc-gfxopt" } */
+/* { dg-final { scan-assembler-not "stfiwx" } } */
+
+/* A basic test of the old-style (not stfiwx) fp -> int conversion.  */
+int f(double a, double b)
+{
+  int a1 = a;
+  int b1 = b;
+  return a1+b1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-1.c
new file mode 100644
index 000000000..8d474f076
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run { target { { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* } || { powerpc*-*-linux* && lp64 } } } } */
+/* { dg-options "-mlong-double-128" } */
+
+/* Check that long double values are rounded correctly when being converted
+   to 32-bit integers.  All these values are of the form +/- 2 +/- 2^-60.  */
+
+extern void abort(void);
+extern void exit(int);
+
+int main(void)
+{
+  long double l1 = 1.9999999999999999991326382620115964527941L;
+  long double l2 = 2.0000000000000000008673617379884035472059L;
+  long double l3 = -2.0000000000000000008673617379884035472059L;
+  long double l4 = -1.9999999999999999991326382620115964527941L;
+  
+  if ((int) l1 != 1)
+    abort ();
+  if ((int) l2 != 2)
+    abort ();
+  if ((int) l3 != -2)
+    abort ();
+  if ((int) l4 != -1)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-2.c
new file mode 100644
index 000000000..5dc74cd2d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-2.c
@@ -0,0 +1,22 @@
+/* { dg-do run { target { { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* } || { powerpc*-*-linux* && lp64 } } } } */
+/* { dg-options "-mlong-double-128" } */
+
+/* Check that LDBL_EPSILON is right for 'long double'.  */
+
+#include <float.h>
+
+extern void abort (void);
+
+int main(void)
+{
+  volatile long double ee = 1.0;
+  long double eps = ee;
+  while (ee + 1.0 != 1.0)
+    {
+      eps = ee;
+      ee = eps / 2;
+    }
+  if (eps != LDBL_EPSILON)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c
new file mode 100644
index 000000000..375241ec6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target { ilp32 } } } */
+/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */
+/* This used to ICE as the peephole was not checking to see
+   if the register is a floating point one (I think this cannot
+   happen in real life except in this example).  */
+
+register volatile double t1 __asm__("r14");
+register volatile double t2 __asm__("r15");
+register volatile double t3 __asm__("r16"), t4 __asm__("r17");
+void t(double *a, double *b)
+{
+        t1 = a[-1];
+        t2 = a[0];
+        t3 = a[1];
+        t4 = a[2];
+        b[-1] = t1;
+        b[0] = t2;
+        b[1] = t3;
+        b[2] = t4;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c
new file mode 100644
index 000000000..567ad8c92
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target { powerpc_fprs && ilp32 } } } */
+/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w" } */
+/* { dg-final { scan-assembler-not "lfd" } } */
+/* { dg-final { scan-assembler-not "sfd" } } */
+/* { dg-final { scan-assembler "lfq" } } */
+/* { dg-final { scan-assembler "stfq" } } */
+
+register volatile double t1 __asm__("fr0");
+register volatile double t2 __asm__("fr1");
+register volatile double t3 __asm__("fr2"), t4 __asm__("fr3");
+void t(double *a, double *b)
+{
+        t1 = a[-1];
+        t2 = a[0];
+        t3 = a[1];
+        t4 = a[2];
+        b[-1] = t1;
+        b[0] = t2;
+        b[1] = t3;
+        b[2] = t4;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe-small-data-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe-small-data-1.c
new file mode 100644
index 000000000..8bdb154e1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe-small-data-1.c
@@ -0,0 +1,14 @@
+/* Verify that we don't ICE trying to put SPE data in .sdata2.  */
+/* { dg-do run { target { powerpc*-*-linux* && powerpc_spe } } } */
+/* { dg-options "-msdata=eabi -mcall-eabi -G 8" } */
+
+#include <spe.h>
+
+__ev64_fs__ x;
+
+int main(void)
+{
+  x = __ev_fsabs (x);
+  return(0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe-small-data-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe-small-data-2.c
new file mode 100644
index 000000000..2a466e344
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe-small-data-2.c
@@ -0,0 +1,12 @@
+/* Verify that we don't ICE trying to put float data in .sdata2.  */
+/* { dg-do run { target { powerpc*-*-linux* && powerpc_spe } } } */
+/* { dg-options "-msdata=eabi -mcall-eabi -G 8" } */
+
+double x;
+
+int main(void)
+{
+  x = x * 2;
+  return(0);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe-unwind-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe-unwind-1.c
new file mode 100644
index 000000000..84d4bf288
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe-unwind-1.c
@@ -0,0 +1,116 @@
+/* Verify that unwinding can find SPE registers in signal frames.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do run { target { powerpc*-*-linux* && powerpc_spe } } } */
+/* { dg-options "-fexceptions -fnon-call-exceptions -O2" } */
+
+#include <unwind.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <string.h>
+
+int count;
+char *null;
+int found_reg;
+
+typedef int v2si __attribute__((__vector_size__(8)));
+
+v2si v1 = { 123, 234 };
+v2si v2 = { 345, 456 };
+
+static _Unwind_Reason_Code
+force_unwind_stop (int version, _Unwind_Action actions,
+                   _Unwind_Exception_Class exc_class,
+                   struct _Unwind_Exception *exc_obj,
+                   struct _Unwind_Context *context,
+                   void *stop_parameter)
+{
+  unsigned int reg;
+  if (actions & _UA_END_OF_STACK)
+    abort ();
+  if (_Unwind_GetGR (context, 1215) == 123)
+    found_reg = 1;
+  return _URC_NO_REASON;
+}
+
+static void force_unwind ()
+{
+  struct _Unwind_Exception *exc = malloc (sizeof (*exc));
+  memset (&exc->exception_class, 0, sizeof (exc->exception_class));
+  exc->exception_cleanup = 0;
+
+#ifndef __USING_SJLJ_EXCEPTIONS__
+  _Unwind_ForcedUnwind (exc, force_unwind_stop, 0);
+#else
+  _Unwind_SjLj_ForcedUnwind (exc, force_unwind_stop, 0);
+#endif
+
+  abort ();
+}
+
+static void counter (void *p __attribute__((unused)))
+{
+  ++count;
+}
+
+static void handler (void *p __attribute__((unused)))
+{
+  if (count != 2)
+    abort ();
+  if (!found_reg)
+    abort ();
+  exit (0);
+}
+
+static int __attribute__((noinline)) fn5 ()
+{
+  char dummy __attribute__((cleanup (counter)));
+  force_unwind ();
+  return 0;
+}
+
+static void fn4 (int sig)
+{
+  char dummy __attribute__((cleanup (counter)));
+  /* Clobber high part without compiler's knowledge so the only saved
+     copy is from the signal frame.  */
+  asm volatile ("evmergelo 15,15,15");
+  fn5 ();
+  null = NULL;
+}
+
+static void fn3 ()
+{
+  abort ();
+}
+
+static int __attribute__((noinline)) fn2 ()
+{
+  register v2si r15 asm("r15");
+  r15 = v1;
+  asm volatile ("" : "+r" (r15));
+  *null = 0;
+  fn3 ();
+  return 0;
+}
+
+static int __attribute__((noinline)) fn1 ()
+{
+  signal (SIGSEGV, fn4);
+  signal (SIGBUS, fn4);
+  fn2 ();
+  return 0;
+}
+
+static int __attribute__((noinline)) fn0 ()
+{
+  char dummy __attribute__((cleanup (handler)));
+  fn1 ();
+  null = 0;
+  return 0;
+}
+
+int main()
+{ 
+  fn0 ();
+  abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c
new file mode 100644
index 000000000..09f813482
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+/* { dg-final { scan-assembler "evstdd" } } */
+
+void foo(void)
+{
+  int x[8] __attribute__((aligned(64))) = { 1, 1, 1, 1, 1, 1, 1, 1 };
+  bar (x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe-vector-memset.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe-vector-memset.c
new file mode 100644
index 000000000..7ecaf1037
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe-vector-memset.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_spe } */
+/* { dg-options "-O -mspe=yes" } */
+/* { dg-final { scan-assembler "evstdd" } } */
+
+#include <string.h>
+
+void foo(void)
+{
+  int x[8] __attribute__((aligned(64)));
+  memset (x, 0, sizeof (x));
+  bar (x);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe1.c
new file mode 100644
index 000000000..ddbb5a6e1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/spe1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single -O0" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+
+/* (Test with -O0 so we don't optimize any of them away).  */
+
+
+typedef float __attribute__((vector_size(8))) __ev64_fs__;
+
+__ev64_opaque__ Foo (void);
+
+void Bar ()
+{
+  __ev64_fs__ fs = Foo ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/stabs-attrib-vect-darwin.c b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/stabs-attrib-vect-darwin.c
new file mode 100644
index 000000000..3c52287b3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/powerpc/stabs-attrib-vect-darwin.c
@@ -0,0 +1,11 @@
+/* Test Attribute Vector associated with vector type stabs.  */
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-options "-gstabs+ -fno-eliminate-unused-debug-types -faltivec" } */
+
+int main ()
+{
+  vector int vi = { 6,7,8,9 };
+  return 0;
+}
+
+/* { dg-final { scan-assembler ".stabs.*vi\:\\(0,\[0-9\]+\\)=\@V" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20020926-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20020926-1.c
new file mode 100644
index 000000000..aaa134276
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20020926-1.c
@@ -0,0 +1,14 @@
+/* Make sure that LEGITIMIZE_ADDRESS is called to handle
+   negative displacements.  */
+
+/* { dg-do compile { target { s390-*-* } } } */
+/* { dg-options "-O2 -mesa" } */
+
+int test (int *addr)
+{
+  return *(addr - 1);
+}
+
+/* { dg-final { scan-assembler "-4096" } } */
+/* { dg-final { scan-assembler-not "ahi" } } */
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20030123-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20030123-1.c
new file mode 100644
index 000000000..96ac6f76c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20030123-1.c
@@ -0,0 +1,19 @@
+/* This used to ICE due to a reload bug on s390*.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-omit-frame-pointer" } */
+
+extern void *alloca (__SIZE_TYPE__);
+
+void func (char *p);
+
+void test (void)
+{
+   char *p = alloca (4096);
+   long idx;
+
+   asm ("" : "=r" (idx) : : "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "12");
+
+   func (p + idx + 1);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20030129-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20030129-1.c
new file mode 100644
index 000000000..1cbd8b482
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20030129-1.c
@@ -0,0 +1,37 @@
+/* This used to ICE due to a reload bug on s390*.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int f (unsigned int);
+void g (void *);
+
+void test (void *p, void *dummy)
+{
+  unsigned int flags = 0;
+
+  if (dummy)
+    g (dummy);
+
+  if (p)
+    flags |= 0x80000000;
+
+  asm volatile ("" : : : "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12");
+
+  if (dummy)
+    g (dummy);
+
+  if (p) 
+    {
+      flags |= 0x20000000|0x80000000;
+
+      if (!f (0))
+        flags &= ~0x80000000;
+    }
+
+  f (flags);
+
+  if (dummy)
+    g (dummy);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20040305-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20040305-1.c
new file mode 100644
index 000000000..a241f041c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20040305-1.c
@@ -0,0 +1,53 @@
+
+/* The testcase failed due to corrupted alias information.
+   During the crossjump analyzing step the mem alias info of the
+   st instructions are merged and get copied during basic block
+   reordering which leads to an insn with wrong alias info.
+   The scheduler afterwards exchanges the mvc and st instructions 
+   not recognizing the anti dependence.  */
+/* { dg-do run } */
+/* { dg-options "-O3 -mtune=z990 -fno-inline" } */
+
+extern void exit (int);
+extern void abort (void);
+
+int f;
+int g;
+int h;
+
+int* x  = &f;
+int* p1 = &g;
+int* p2 = &h;
+
+int
+foo(void)
+{
+
+  if (*x == 0)
+    {
+      x = p1;         /* mvc - memory to memory */
+      p1 = (int*)0;   /* st  - register to memory */
+      return 1;
+    }
+  if (*x == 5)
+    {
+      f = 1;
+      g = 2;
+
+      p2 = (int*)0;   /* st */   
+      return 1;
+    }
+}
+
+int
+main (int argc, char** argv)
+{
+  foo ();
+
+  /* If the scheduler has exchanged the mvc and st instructions,
+     x is 0. The expected result is &g.  */
+  if (x == &g)
+    exit (0);
+  else
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20041109-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20041109-1.c
new file mode 100644
index 000000000..bf768439c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20041109-1.c
@@ -0,0 +1,21 @@
+/* This used to ICE due to a literal pool handling bug on s390x.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-omit-frame-pointer" } */
+
+static struct table { int x; } table[3];
+
+int test (void)
+{
+  struct table *t;
+
+  for (t = table; t < &table[3]; t++)
+    asm volatile ("" : : : "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "12");
+
+  for (t = table; t < &table[3]; t++)
+    if (t->x)
+      return 1;
+
+  return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20041216-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20041216-1.c
new file mode 100644
index 000000000..492ee6c18
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20041216-1.c
@@ -0,0 +1,23 @@
+/* This test case would get an unresolved symbol during link
+   because stabs referred to an optimized-away literal pool
+   entry.  */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -gstabs" } */
+
+int main (void)
+{
+  static char buf[4096];
+  char *p;
+
+  do
+    {
+      p = buf;
+      asm volatile ("" : : : "memory", "0", "1", "2", "3", "4", "5", "6",
+				       "7", "8", "9", "10", "12");
+    }
+  while (*p);
+
+  return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20050409-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20050409-1.c
new file mode 100644
index 000000000..4763afad3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20050409-1.c
@@ -0,0 +1,18 @@
+/* This used to ICE due to a regmove problem on s390.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+
+extern void abort (void);
+extern void **alloc (void);
+
+void *test (void)
+{
+  void **p = alloc ();
+  if (!p) abort ();
+
+  __builtin_set_thread_pointer (p);
+  return *p;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20050524-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20050524-1.c
new file mode 100644
index 000000000..7b94fd0f0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20050524-1.c
@@ -0,0 +1,34 @@
+/* This test case used to abort due to a reload bug with
+   elimination offsets.  */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -mpacked-stack" } */
+
+extern void abort (void);
+
+double bar (double) __attribute__ ((noinline));
+double bar (double x) { return x; }
+
+double
+foo (int j, double f0, double f2, double f4, double f6, double x) __attribute__ ((noinline));
+
+double
+foo (int j, double f0, double f2, double f4, double f6, double x)
+{
+  if (j)
+    return bar (x) + 4.0;
+  else
+    return bar (x);
+}
+
+int
+main (void)
+{
+  if (foo (0, 0, 0, 0, 0, 10) != 10)
+    abort ();
+  if (foo (1, 0, 0, 0, 0, 10) != 14)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20050824-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20050824-1.c
new file mode 100644
index 000000000..c24e1e26f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20050824-1.c
@@ -0,0 +1,34 @@
+/* Make sure that the S/390 specific shift_count_operand
+   predicate work properly.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+unsigned long long
+f (unsigned long long a, unsigned long b)
+{
+  asm ("" : : : 
+#ifdef __s390x__
+		"r13", "r14",
+#endif
+		"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 
+                "r8", "r9", "r10", "r11", "r12");
+
+  return a << ((b + 3) & 63);
+}
+
+unsigned long long
+g (unsigned long long a, char **b , int c, int d, int e, int f)
+{
+  char buffer [4096];
+
+  *b = &buffer[0];
+
+  return a << ((unsigned long)&f & 63);
+}
+
+unsigned long long
+h (unsigned long long a, int b, int c, int d, int e, int f)
+{
+  return a << (((unsigned long)&f + 3));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20071212-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20071212-1.c
new file mode 100644
index 000000000..e5d05ad41
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20071212-1.c
@@ -0,0 +1,11 @@
+/* This used to fail due to bug in the On constraint causing a slgfi
+   to be emitted with an immediate not fitting into 32bit.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=z9-109" } */
+
+long
+foo (long a)
+{
+  return a - (1ULL << 32);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20090223-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20090223-1.c
new file mode 100644
index 000000000..443ccb9aa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/20090223-1.c
@@ -0,0 +1,60 @@
+/* The RTL loop optimizer used to replace the output register of the
+   inline assembly with a pseudo although the variable is declared as
+   register asm ("0").  */
+
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+static unsigned char __attribute__ ((always_inline))
+mytoupper (unsigned char c)
+{
+  if (c >= 'a' && c <= 'z')
+    c -= 'a' - 'A';
+  return c;
+}
+
+static unsigned long __attribute__ ((always_inline))
+strlen (const char *s)
+{
+  register unsigned long r0 asm ("0");
+  const char *tmp = s;
+
+  asm (
+#ifdef __s390x__
+       "  lghi  %0, 0\n"
+#else
+       "  lhi   %0, 0\n"
+#endif
+       "0:srst  %0,%1\n"
+       "  jo    0b"
+       : "=d" (r0), "+a" (tmp)
+       :
+       :"cc");
+  return r0 - (unsigned long) s;
+}
+
+char boot_command_line[] = "this is a test";
+
+void __attribute__ ((noinline))
+foo (char *str)
+{
+  if (strcmp (str, "THIS IS A TEST") != 0)
+    abort ();
+}
+
+int
+main ()
+{
+  char upper_command_line[1024];
+  int i;
+
+  for (i = 0; i < strlen (boot_command_line); i++)
+    upper_command_line[i] = mytoupper (boot_command_line[i]);
+
+  upper_command_line[strlen (boot_command_line)] = 0;
+  foo (upper_command_line);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/frame-addr1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/frame-addr1.c
new file mode 100644
index 000000000..fda419ff0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/frame-addr1.c
@@ -0,0 +1,53 @@
+/* builtin_frame_address(n) with n>0 has always been troublesome ...
+   especially when the S/390 packed stack layout comes into play.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -fno-optimize-sibling-calls -mbackchain -mpacked-stack -msoft-float" } */
+
+#ifdef __s390x__
+/* 64bit: 3 words to be saved: backchain, r14 and r15  */
+#define SAVE_AREA_SIZE 3*8
+#else
+/* 32bit: 4 words to be saved: backchain, r13, r14 and r15  */
+#define SAVE_AREA_SIZE 4*4
+#endif
+extern void abort(void);
+
+#define EXPAND_CHECK(n)						\
+  void __attribute__((noinline))				\
+    foo1_##n (void *p)						\
+  {								\
+    if (p - __builtin_frame_address (n) != SAVE_AREA_SIZE)	\
+      abort ();							\
+  }								\
+  void __attribute__((noinline))				\
+    foo2_##n (void *p)						\
+  {								\
+    if (p - __builtin_frame_address (n) != SAVE_AREA_SIZE)	\
+      abort ();							\
+    foo1_##n (__builtin_frame_address (n));			\
+  }								\
+  void __attribute__((noinline))				\
+    foo3_##n ()							\
+  {								\
+    foo2_##n (__builtin_frame_address (n));			\
+  }								\
+  void __attribute__((noinline))				\
+    foo4_##n ()							\
+  {								\
+    foo3_##n ();						\
+  }
+
+EXPAND_CHECK (0)
+EXPAND_CHECK (1)
+EXPAND_CHECK (2)
+
+int
+main ()
+{
+  foo4_0 ();
+  foo4_1 ();
+  foo4_2 ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/frame-addr2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/frame-addr2.c
new file mode 100644
index 000000000..f6f9687a0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/frame-addr2.c
@@ -0,0 +1,50 @@
+/* builtin_frame_address(n) with n>0 has always been troublesome.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -fno-optimize-sibling-calls -mbackchain" } */
+
+#ifdef __s390x__
+#define SAVE_AREA_SIZE 160
+#else
+#define SAVE_AREA_SIZE 96
+#endif
+extern void abort(void);
+
+#define EXPAND_CHECK(n)						\
+  void __attribute__((noinline))				\
+    foo1_##n (void *p)						\
+  {								\
+    if (p - __builtin_frame_address (n) != SAVE_AREA_SIZE)	\
+      abort ();							\
+  }								\
+  void __attribute__((noinline))				\
+    foo2_##n (void *p)						\
+  {								\
+    if (p - __builtin_frame_address (n) != SAVE_AREA_SIZE)	\
+      abort ();							\
+    foo1_##n (__builtin_frame_address (n));			\
+  }								\
+  void __attribute__((noinline))				\
+    foo3_##n ()							\
+  {								\
+    foo2_##n (__builtin_frame_address (n));			\
+  }								\
+  void __attribute__((noinline))				\
+    foo4_##n ()							\
+  {								\
+    foo3_##n ();						\
+  }
+
+EXPAND_CHECK (0)
+EXPAND_CHECK (1)
+EXPAND_CHECK (2)
+
+int
+main ()
+{
+  foo4_0 ();
+  foo4_1 ();
+  foo4_2 ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/pr20927.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/pr20927.c
new file mode 100644
index 000000000..dbc990f15
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/pr20927.c
@@ -0,0 +1,23 @@
+/* This caused an ICE on s390x due to a reload inheritance bug.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct point { double x, y; };
+extern void use (struct point);
+
+void test (struct point *pc, struct point p1)
+{
+  struct point p0 = *pc;
+
+  if (p0.x == p1.x && p0.y == p1.y)
+    use (p0);
+
+  asm ("" : : : "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10");
+
+  p1.y -= p0.y;
+
+  use (p0);
+  use (p1);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/pr24624.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/pr24624.c
new file mode 100644
index 000000000..bc2070c4b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/pr24624.c
@@ -0,0 +1,67 @@
+/* This used to ICE due to a backend problem on s390.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1 -mpacked-stack" } */
+
+typedef unsigned int __u32;
+typedef struct
+{
+  volatile int counter;
+} __attribute__ ((aligned (4))) atomic_t;
+static __inline__ __attribute__ ((always_inline))
+     void atomic_inc (volatile atomic_t * v)
+{
+  (
+    {
+    typeof (v->counter) old_val, new_val;
+  __asm__ __volatile__ (
+	"   l     %0,0(%3)\n" 
+	"0: lr    %1,%0\n" 
+	"   ar    %1,%4\n" 
+	"   cs    %0,%1,0(%3)\n" 
+	"   jl    0b": 
+	"=&d" (old_val), "=&d" (new_val), "=m" (((atomic_t *) (v))->counter): 
+	"a" (v), "d" (1), "m" (((atomic_t *) (v))->counter):
+	"cc", "memory");
+    });
+}
+extern unsigned long volatile __attribute__ ((section (".data"))) jiffies;
+struct inet_peer
+{
+  unsigned long dtime;
+  atomic_t refcnt;
+};
+static volatile int peer_total;
+int inet_peer_threshold = 65536 + 128;
+int inet_peer_minttl = 120 * 100;
+int inet_peer_maxttl = 10 * 60 * 100;
+static int
+cleanup_once (unsigned long ttl)
+{
+  struct inet_peer *p;
+  if (p != ((void *) 0))
+    {
+      if (((
+	     {
+	     1;}
+	   ) && ((long) (jiffies) - (long) (p->dtime + ttl) < 0)))
+	{
+	  return -1;
+	}
+      atomic_inc (&p->refcnt);
+    }
+}
+struct inet_peer *
+inet_getpeer (__u32 daddr, int create)
+{
+  int i;
+  int ttl;
+  if (peer_total >= inet_peer_threshold)
+    ttl = inet_peer_minttl;
+  else
+    ttl =
+      inet_peer_maxttl - (inet_peer_maxttl -
+			  inet_peer_minttl) / 100 * peer_total /
+      inet_peer_threshold * 100;
+  for (i = 0; i < 30 && !cleanup_once (ttl); i++);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/pr27661.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/pr27661.c
new file mode 100644
index 000000000..1ff6dcc7c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/pr27661.c
@@ -0,0 +1,25 @@
+/* This used to ICE on s390 due to a reload bug.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=z990 -ftracer" } */
+
+extern int memcmp (const void *s1, const void *s2, unsigned long n);
+extern int printf (__const char *__restrict __format, ...);
+
+struct test
+{
+  char tmp[4096];
+  char msgtype[2];
+};
+
+void test (struct test *testtb)
+{
+  if (testtb)
+    printf ("a");
+
+  if (memcmp(testtb->msgtype, "a", 2))
+    printf ("a");
+
+  printf ("b");
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/pr36822.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/pr36822.c
new file mode 100644
index 000000000..fb021f214
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/pr36822.c
@@ -0,0 +1,16 @@
+/* This used to ICE on s390 due to bug in the definition of the 'R'
+   constraint which replaced the 'm' constraint (together with 'T')
+   while adding z10 support.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+int boo()
+{
+  struct {
+    unsigned char pad[4096];
+    unsigned long bar;
+  } *foo;
+  asm volatile( "" : "=m" (*(unsigned long long*)(foo->bar))
+		: "a" (&foo->bar));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/return-addr1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/return-addr1.c
new file mode 100644
index 000000000..8872b89b7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/return-addr1.c
@@ -0,0 +1,46 @@
+/* builtin_return_address(n) with n>0 has always been troublesome ...
+   especially when the S/390 packed stack layout comes into play.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -fno-optimize-sibling-calls -mbackchain -mpacked-stack -msoft-float" } */
+
+void *addr1;
+
+extern void abort (void);
+
+void * __attribute__((noinline))
+foo1 ()
+{
+  addr1 = __builtin_return_address (2);
+}
+
+void * __attribute__((noinline))
+foo2 ()
+{
+  foo1 ();
+}
+
+void * __attribute__((noinline))
+foo3 ()
+{
+  foo2 ();
+}
+
+void __attribute__((noinline))
+bar ()
+{
+  void *addr2;
+
+  foo3 ();
+  asm volatile ("basr  %0,0\n\t" : "=d" (addr2));
+  /* basr is two bytes in length.  */
+  if (addr2 - addr1 != 2)
+    abort ();
+}
+
+int
+main ()
+{
+  bar();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/return-addr2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/return-addr2.c
new file mode 100644
index 000000000..c94d05284
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/return-addr2.c
@@ -0,0 +1,45 @@
+/* builtin_return_address(n) with n>0 has always been troublesome.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -fno-optimize-sibling-calls -mbackchain" } */
+
+void *addr1;
+
+extern void abort (void);
+
+void * __attribute__((noinline))
+foo1 ()
+{
+  addr1 = __builtin_return_address (2);
+}
+
+void * __attribute__((noinline))
+foo2 ()
+{
+  foo1 ();
+}
+
+void * __attribute__((noinline))
+foo3 ()
+{
+  foo2 ();
+}
+
+void __attribute__((noinline))
+bar ()
+{
+  void *addr2;
+
+  foo3 ();
+  asm volatile ("basr  %0,0\n\t" : "=d" (addr2));
+  /* basr is two bytes in length.  */
+  if (addr2 - addr1 != 2)
+    abort ();
+}
+
+int
+main ()
+{
+  bar();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/s390.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/s390.exp
new file mode 100644
index 000000000..d69330986
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/s390.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 2007 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a s390 target.
+if ![istarget s390*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/s390/tf_to_di-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/tf_to_di-1.c
new file mode 100644
index 000000000..d79e6f350
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/s390/tf_to_di-1.c
@@ -0,0 +1,46 @@
+/* { dg-options "-O0 -mlong-double-128" } */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+void
+check_ll (long double ld, long long ll)
+{
+  if ((long long)ld != ll)
+    {
+      printf ("ld: %Lf expect: %lld result: %lld\n",
+	      ld, ll, (long long)ld);
+      abort ();
+    }
+}
+
+void
+check_ull (long double ld, unsigned long long ull)
+{
+  if ((unsigned long long)ld != ull)
+    {
+      printf ("ld: %Lf expect: %llu result: %llu\n",
+	      ld, ull, (unsigned long long)ld);
+      abort ();
+    }
+}
+
+int
+main ()
+{
+  const long long ll_max = (long long)((1ULL << 63) - 1);
+  const long long ll_min = -ll_max - 1;
+
+  check_ll (206.23253, 206LL);
+  check_ull (206.23253, 206ULL);
+  check_ll ((long double)ll_max, ll_max);
+  check_ull ((long double)ll_max, ll_max);
+  check_ll ((long double)ll_min, ll_min);
+  check_ll (0.0, 0);
+  check_ull (0.0, 0);
+  check_ll (-1.0, -1);
+  check_ll ((long double)0xffffffffffffffffULL, ll_max);
+  check_ull ((long double)0xffffffffffffffffULL, 0xffffffffffffffffULL);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/20080410-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/20080410-1.c
new file mode 100644
index 000000000..ebd783dd0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/20080410-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile { target "sh-*-*" } } */
+/* { dg-options "-O0 -m4 -ml -fira" } */
+/* { dg-final { scan-assembler-not "add\tr0,r0" } } */
+
+/* This test checks that chain reloads conflict.  I they don't
+   conflict, the same hard register R0 is used for the both reloads
+   but in this case the second reload needs an intermediate register
+   (which is the reload register).  As the result we have the
+   following code
+
+   	mov	#4,r0   -- first reload
+	mov	r14,r0  -- second reload
+	add	r0,r0   -- second reload
+
+   The right code should be
+
+   	mov	#4,r0   -- first reload
+	mov	r14,r1  -- second reload
+	add	r0,r1   -- second reload
+
+*/
+
+_Complex float foo_float ();
+
+void bar_float ()
+{
+  __real foo_float ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/pr21255-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/pr21255-1.c
new file mode 100644
index 000000000..5d5b6d7f9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/pr21255-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+/* { dg-final { scan-assembler "mov fr4,fr.; mov fr5,fr." { target sh-*-* } } } */
+/* { dg-final { scan-assembler "mov fr4,fr.; mov fr5,fr." { target sh[1234lb]*-*-* } } } */
+/* { dg-final { scan-assembler "mov fr0,fr.; mov fr1,fr." { target sh[56]*-*-* } } } */
+double
+f (double d)
+{
+  double r;
+
+#if defined (__SH_FPU_DOUBLE__)
+  asm ("mov %S1,%S0; mov %R1,%R0" : "=f" (r) : "f" (d));
+#else
+  asm ("mov fr4,fr4; mov fr5,fr5");
+#endif
+  return r;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/pr21255-2-mb.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/pr21255-2-mb.c
new file mode 100644
index 000000000..ac2ce687e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/pr21255-2-mb.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-mb -O2 -fomit-frame-pointer" } */
+/* { dg-final { scan-assembler "mov @r.,r.; mov @\\(4,r.\\),r." } } */
+double d;
+
+double
+f (void)
+{
+  double r;
+
+/* If -ml from the target options is passed after -mb from dg-options, we
+   end up with th reverse endianness.  */
+#if TARGET_SHMEDIA || defined (__LITTLE_ENDIAN__)
+  asm ("mov @r1,r3; mov @(4,r1),r4");
+#else
+  asm ("mov %S1,%S0; mov %R1,%R0" : "=&r" (r) : "m" (d));
+#endif
+  return r;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c
new file mode 100644
index 000000000..c63a573ea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-ml -O2 -fomit-frame-pointer" } */
+/* { dg-final { scan-assembler "mov @\\(4,r.\\),r.; mov @r.,r." } } */
+double d;
+
+double
+f (void)
+{
+  double r;
+
+/* If -mb from the target options is passed after -ml from dg-options, we
+   end up with th reverse endianness.  */
+#if TARGET_SHMEDIA || defined (__BIG_ENDIAN__)
+  asm ("mov @(4,r1),r4; mov @r1,r3");
+#else
+  asm ("mov %S1,%S0; mov %R1,%R0" : "=&r" (r) : "m" (d));
+#endif
+  return r;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/pr21255-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/pr21255-3.c
new file mode 100644
index 000000000..7edd8cb7c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/pr21255-3.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+/* { dg-final { scan-assembler "mov #?0,r.*; mov #?20,r" } } */
+/* { dg-final { scan-assembler "mov #?1077149696,r.*; mov #?0,r" } } */
+double
+f ()
+{
+  double r;
+
+  asm ("mov %S1,%S0; mov %R1,%R0" : "=r" (r) : "i" (20));
+  asm ("mov %S1,%S0; mov %R1,%R0" : "+r" (r) : "i" (20.));
+  return r;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/pr21255-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/pr21255-4.c
new file mode 100644
index 000000000..c848c26c0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/pr21255-4.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { sh*-*-* && nonpic } } } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+
+double
+f ()
+{
+  double r;
+
+  asm ("mov %S1,%S0; mov %R1,%R0" : "=r" (r) : "i" (f));
+/* { dg-error "invalid operand to %S" "" {target "sh*-*-*" }  9 } */
+/* { dg-error "invalid operand to %R" "" {target "sh*-*-*" }  9 } */
+  return r;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh-relax-vxworks.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh-relax-vxworks.c
new file mode 100644
index 000000000..f8c2ffef4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh-relax-vxworks.c
@@ -0,0 +1,5 @@
+/* Check that -mrelax produces the correct error message.  */
+/* { dg-do compile { target { sh-*-vxworks* && nonpic } } } */
+/* { dg-error "-mrelax is only supported for RTP PIC" "" { target *-*-* } 0 } */
+/* { dg-options "-O1 -mrelax" } */
+int x;
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh-relax.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh-relax.c
new file mode 100644
index 000000000..54422de46
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh-relax.c
@@ -0,0 +1,41 @@
+/* Check that -mrelax works.  */
+/* { dg-do run { target { { sh-*-* sh?-*-* } && { ! { sh*-*-vxworks* && nonpic } } } } } */
+/* { dg-options "-O1 -mrelax" } */
+
+extern void abort (void);
+extern int qwerty (int);
+
+int
+f (int i)
+{
+  return qwerty (i) + 1;
+}
+
+int
+qwerty (int i)
+{
+  switch (i)
+    {
+    case 1:
+      return 'q';
+    case 2:
+      return 'w';
+    case 3:
+      return 'e';
+    case 4:
+      return 'r';
+    case 5:
+      return 't';
+    case 6:
+      return 'y';
+    }
+}
+
+int
+main ()
+{
+  if (f (1) != 'q' + 1 || f (2) != 'w' + 1 || f (3) != 'e' + 1
+      || f(4) != 'r' + 1 || f (5) != 't' + 1 || f (6) != 'y' + 1)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh.exp
new file mode 100644
index 000000000..9389d4455
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 2007 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a sh target.
+if ![istarget sh*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-band.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-band.c
new file mode 100644
index 000000000..34862b725
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-band.c
@@ -0,0 +1,91 @@
+/* Testcase to check generation of a SH2A specific instruction for
+   "BAND.B #imm3, @(disp12, Rn)".  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O1 -mbitops" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "band.b"} }  */
+
+volatile struct
+{
+  union
+  {
+    unsigned char BYTE;
+    struct
+    {
+      unsigned char BIT7:1;
+      unsigned char BIT6:1;
+      unsigned char BIT5:1;
+      unsigned char BIT4:1;
+      unsigned char BIT3:1;
+      unsigned char BIT2:1;
+      unsigned char BIT1:1;
+      unsigned char BIT0:1;
+    }
+    BIT;
+  }
+  ICR0;
+}
+USRSTR;
+
+volatile union t_IOR
+{
+  unsigned short WORD;
+  struct
+  {
+    unsigned char IOR15:1;
+    unsigned char IOR14:1;
+    unsigned char IOR13:1;
+    unsigned char IOR12:1;
+    unsigned char IOR11:1;
+    unsigned char IOR10:1;
+    unsigned char IOR9:1;
+    unsigned char IOR8:1;
+    unsigned char IOR7:1;
+    unsigned char IOR6:1;
+    unsigned char IOR5:1;
+    unsigned char IOR4:1;
+    unsigned char IOR3:1;
+    unsigned char IOR2:1;
+    unsigned char IOR1:1;
+    unsigned char IOR0:1;
+  }
+  BIT;
+}
+PORT;
+
+int
+main ()
+{
+  volatile unsigned char a;
+
+  /* Instruction generated is BAND.B #imm3, @(disp12, Rn)  */
+  USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 & USRSTR.ICR0.BIT.BIT1;
+  USRSTR.ICR0.BIT.BIT2 = USRSTR.ICR0.BIT.BIT6 & USRSTR.ICR0.BIT.BIT6;
+  USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 & USRSTR.ICR0.BIT.BIT4;
+  USRSTR.ICR0.BIT.BIT6 = USRSTR.ICR0.BIT.BIT1 & USRSTR.ICR0.BIT.BIT3;
+
+  a = USRSTR.ICR0.BIT.BIT0 & USRSTR.ICR0.BIT.BIT1;
+  a = USRSTR.ICR0.BIT.BIT5 & USRSTR.ICR0.BIT.BIT7;
+  a = USRSTR.ICR0.BIT.BIT2 & USRSTR.ICR0.BIT.BIT6;
+
+  PORT.BIT.IOR13 = PORT.BIT.IOR0  &  USRSTR.ICR0.BIT.BIT7;
+  PORT.BIT.IOR15 = PORT.BIT.IOR6  &  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR3  = PORT.BIT.IOR2  &  USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR1  = PORT.BIT.IOR13 &  USRSTR.ICR0.BIT.BIT1;
+
+  PORT.BIT.IOR1  = PORT.BIT.IOR2  &  USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR11 = PORT.BIT.IOR9  &  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR8  = PORT.BIT.IOR14 &  USRSTR.ICR0.BIT.BIT5;
+
+  PORT.BIT.IOR10 &= USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR1  &= USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR5  &= USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR14 &= USRSTR.ICR0.BIT.BIT4;
+
+  /* Instruction generated on using size optimization option "-Os".  */
+  a = a & USRSTR.ICR0.BIT.BIT1;
+  a = a & USRSTR.ICR0.BIT.BIT4;
+  a = a & USRSTR.ICR0.BIT.BIT0;
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bclr.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bclr.c
new file mode 100644
index 000000000..d4e11f952
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bclr.c
@@ -0,0 +1,57 @@
+/* Testcase to check generation of a SH2A specific instruction
+   'BCLR #imm3,Rn'.  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O1" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bclr"} }  */
+
+struct a
+{
+  char a, b;
+  short c;
+};
+
+/* This function generates the instruction "BCLR #imm3,Rn" only
+   on using optimization option "-O1" and above.  */
+
+int
+a2 ()
+{
+  volatile int j;
+  volatile static struct a x = {1, 66, ~1}, y = {1, 2, ~2};
+
+  if (j > 1)
+    return (x.a == y.a && (x.b & ~1) == y.b);
+  if (j > 2)
+    return (x.a == y.a && (x.b & ~2) == y.b);
+  if (j > 3)
+    return (x.a == y.a && (x.b & ~4) == y.b);
+  if (j > 4)
+    return (x.a == y.a && (x.b & ~8) == y.b);
+  if (j > 5)
+    return (x.a == y.a && (x.b & ~16) == y.b);
+  if (j > 6)
+    return (x.a == y.a && (x.b & ~32) == y.b);
+  if (j > 7)
+    return (x.a == y.a && (x.b & ~64) == y.b);
+  if (j > 8)
+    return (x.a == y.a && (x.b & ~128) == y.b);
+}
+
+int
+main ()
+{
+  volatile unsigned char x;
+
+  x &= 0xFE;
+  x &= 0xFD;
+  x &= 0xFB;
+  x &= 0xF7;
+  x &= 0xEF;
+  x &= 0xDF;
+  x &= 0xBF;
+  x &= 0x7F;
+
+  if (!a2 ())
+    return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c
new file mode 100644
index 000000000..41cb3bdfe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c
@@ -0,0 +1,55 @@
+/* Testcase to check generation of a SH2A specific instruction
+   "BCLR #imm3,@(disp12,Rn)".  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O2 -mbitops" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bclr"} }  */
+/* { dg-final { scan-assembler "bclr.b"} }  */
+
+volatile union un_paddr
+{
+  unsigned char BYTE;
+  struct
+  {
+    unsigned char B15:1;
+    unsigned char B14:1;
+    unsigned char B13:1;
+    unsigned char B12:1;
+    unsigned char B11:1;
+    unsigned char B10:1;
+    unsigned char B9:1;
+    unsigned char B8:1;
+    unsigned char B7:1;
+    unsigned char B6:1;
+    unsigned char B5:1;
+    unsigned char B4:1;
+    unsigned char B3:1;
+    unsigned char B2:1;
+    unsigned char B1:1;
+    unsigned char B0:1;
+  }
+  BIT;
+}
+PADDR;
+
+int
+main ()
+{
+  PADDR.BIT.B0 = 0;
+  PADDR.BIT.B3 = 0;
+  PADDR.BIT.B6 = 0;
+
+  PADDR.BIT.B1 &= 0;
+  PADDR.BIT.B4 &= 0;
+  PADDR.BIT.B7 &= 0;
+
+  PADDR.BIT.B10 = 0;
+  PADDR.BIT.B13 = 0;
+  PADDR.BIT.B15 = 0;
+
+  PADDR.BIT.B9 &= 0;
+  PADDR.BIT.B12 &= 0;
+  PADDR.BIT.B14 &= 0;
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bld.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bld.c
new file mode 100644
index 000000000..1cf56fe27
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bld.c
@@ -0,0 +1,43 @@
+/* A testcase to check generation of the following SH2A specific
+   instructions.
+
+    BLD #imm3, Rn
+    BLD.B #imm3, @(disp12, Rn)
+ */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-Os -mbitops" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bld"} }  */
+/* { dg-final { scan-assembler "bld.b"} }  */
+
+volatile struct
+{
+  union
+  {
+    unsigned char BYTE;
+    struct
+    {
+      unsigned char BIT7:1;
+      unsigned char BIT6:1;
+      unsigned char BIT5:1;
+      unsigned char BIT4:1;
+      unsigned char BIT3:1;
+      unsigned char BIT2:1;
+      unsigned char BIT1:1;
+      unsigned char BIT0:1;
+    }
+    BIT;
+  }
+  ICR0;
+}
+USRSTR;
+
+int
+main ()
+{
+  volatile unsigned char a, b, c;
+  USRSTR.ICR0.BIT.BIT6 &= a;
+  USRSTR.ICR0.BIT.BIT5 |= b;
+  USRSTR.ICR0.BIT.BIT4 ^= c;
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bor.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bor.c
new file mode 100644
index 000000000..c3803c6b9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bor.c
@@ -0,0 +1,91 @@
+/* Testcase to check generation of a SH2A specific instruction for
+   "BOR.B #imm3, @(disp12, Rn)".  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O1 -mbitops" } */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bor.b"} }  */
+
+volatile struct
+{
+  union
+  {
+    unsigned char BYTE;
+    struct
+    {
+      unsigned char BIT7:1;
+      unsigned char BIT6:1;
+      unsigned char BIT5:1;
+      unsigned char BIT4:1;
+      unsigned char BIT3:1;
+      unsigned char BIT2:1;
+      unsigned char BIT1:1;
+      unsigned char BIT0:1;
+    }
+    BIT;
+  }
+  ICR0;
+}
+USRSTR;
+
+volatile union t_IOR
+{
+  unsigned short WORD;
+  struct
+  {
+    unsigned char IOR15:1;
+    unsigned char IOR14:1;
+    unsigned char IOR13:1;
+    unsigned char IOR12:1;
+    unsigned char IOR11:1;
+    unsigned char IOR10:1;
+    unsigned char IOR9:1;
+    unsigned char IOR8:1;
+    unsigned char IOR7:1;
+    unsigned char IOR6:1;
+    unsigned char IOR5:1;
+    unsigned char IOR4:1;
+    unsigned char IOR3:1;
+    unsigned char IOR2:1;
+    unsigned char IOR1:1;
+    unsigned char IOR0:1;
+  }
+  BIT;
+}
+PORT;
+
+int
+main ()
+{
+  volatile unsigned char a;
+
+  /* Instruction generated is BOR.B #imm3, @(disp12, Rn)  */
+  USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 | USRSTR.ICR0.BIT.BIT1;
+  USRSTR.ICR0.BIT.BIT2 = USRSTR.ICR0.BIT.BIT6 | USRSTR.ICR0.BIT.BIT6;
+  USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 | USRSTR.ICR0.BIT.BIT4;
+  USRSTR.ICR0.BIT.BIT6 = USRSTR.ICR0.BIT.BIT1 | USRSTR.ICR0.BIT.BIT3;
+
+  a = USRSTR.ICR0.BIT.BIT0 | USRSTR.ICR0.BIT.BIT1;
+  a = USRSTR.ICR0.BIT.BIT5 | USRSTR.ICR0.BIT.BIT7;
+  a = USRSTR.ICR0.BIT.BIT2 | USRSTR.ICR0.BIT.BIT6;
+
+  PORT.BIT.IOR13 = PORT.BIT.IOR0  |  USRSTR.ICR0.BIT.BIT7;
+  PORT.BIT.IOR15 = PORT.BIT.IOR6  |  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR3  = PORT.BIT.IOR2  |  USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR1  = PORT.BIT.IOR13 |  USRSTR.ICR0.BIT.BIT1;
+
+  PORT.BIT.IOR1  = PORT.BIT.IOR2  |  USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR11 = PORT.BIT.IOR9  |  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR8  = PORT.BIT.IOR14 |  USRSTR.ICR0.BIT.BIT5;
+
+  PORT.BIT.IOR10 |= USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR1  |= USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR5  |= USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR14 |= USRSTR.ICR0.BIT.BIT4;
+
+  /* Instruction generated on using size optimization option "-Os".  */
+  a = a & USRSTR.ICR0.BIT.BIT1;
+  a = a & USRSTR.ICR0.BIT.BIT4;
+  a = a & USRSTR.ICR0.BIT.BIT0;
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bset.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bset.c
new file mode 100644
index 000000000..b64852b4c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bset.c
@@ -0,0 +1,57 @@
+/* Testcase to check generation of a SH2A specific instruction
+  'BSET #imm3,Rn'.  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O1" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bset"} }  */
+
+struct a
+{
+  char a, b;
+  short c;
+};
+
+/* This function generates the instruction "BSET #imm3,Rn" only
+   on using optimization option "-O1" and above.  */
+
+int
+a2 ()
+{
+  volatile int j;
+  volatile static struct a x = {1, 66, ~1}, y = {1, 2, ~2};
+
+  if (j > 1)
+    return (x.a == y.a && (x.b | 1) == y.b);
+  if (j > 2)
+    return (x.a == y.a && (x.b | 2) == y.b);
+  if (j > 3)
+    return (x.a == y.a && (x.b | 4) == y.b);
+  if (j > 4)
+    return (x.a == y.a && (x.b | 8) == y.b);
+  if (j > 5)
+    return (x.a == y.a && (x.b | 16) == y.b);
+  if (j > 6)
+    return (x.a == y.a && (x.b | 32) == y.b);
+  if (j > 7)
+    return (x.a == y.a && (x.b | 64) == y.b);
+  if (j > 8)
+    return (x.a == y.a && (x.b | 128) == y.b);
+}
+
+int
+main ()
+{
+  volatile unsigned char x;
+
+  x |= 0x1;
+  x |= 0x2;
+  x |= 0x4;
+  x |= 0x8;
+  x |= 0x16;
+  x |= 0x32;
+  x |= 0x64;
+  x |= 0x128;
+
+  if (!a2 ())
+    return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c
new file mode 100644
index 000000000..b0ebf0851
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c
@@ -0,0 +1,55 @@
+/* Testcase to check generation of a SH2A specific instruction
+   "BSET #imm3,@(disp12,Rn)".  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O2 -mbitops" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bset"} }  */
+/* { dg-final { scan-assembler "bset.b"} }  */
+
+volatile union un_paddr
+{
+  unsigned char BYTE;
+  struct
+  {
+    unsigned char B15:1;
+    unsigned char B14:1;
+    unsigned char B13:1;
+    unsigned char B12:1;
+    unsigned char B11:1;
+    unsigned char B10:1;
+    unsigned char B9:1;
+    unsigned char B8:1;
+    unsigned char B7:1;
+    unsigned char B6:1;
+    unsigned char B5:1;
+    unsigned char B4:1;
+    unsigned char B3:1;
+    unsigned char B2:1;
+    unsigned char B1:1;
+    unsigned char B0:1;
+  }
+  BIT;
+}
+PADDR;
+
+int
+main ()
+{
+  PADDR.BIT.B0 = 1;
+  PADDR.BIT.B3 = 1;
+  PADDR.BIT.B6 = 1;
+
+  PADDR.BIT.B1 |= 1;
+  PADDR.BIT.B4 |= 1;
+  PADDR.BIT.B7 |= 1;
+
+  PADDR.BIT.B10 = 1;
+  PADDR.BIT.B13 = 1;
+  PADDR.BIT.B15 = 1;
+
+  PADDR.BIT.B9  |= 1;
+  PADDR.BIT.B12 |= 1;
+  PADDR.BIT.B14 |= 1;
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bxor.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bxor.c
new file mode 100644
index 000000000..afe0a5ec9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-bxor.c
@@ -0,0 +1,91 @@
+/* Testcase to check generation of a SH2A specific instruction for
+   "BXOR.B #imm3, @(disp12, Rn)".  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O1 -mbitops" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bxor.b"} }  */
+
+volatile struct
+{
+  union
+  {
+    unsigned char BYTE;
+    struct
+    {
+      unsigned char BIT7:1;
+      unsigned char BIT6:1;
+      unsigned char BIT5:1;
+      unsigned char BIT4:1;
+      unsigned char BIT3:1;
+      unsigned char BIT2:1;
+      unsigned char BIT1:1;
+      unsigned char BIT0:1;
+    }
+    BIT;
+  }
+  ICR0;
+}
+USRSTR;
+
+volatile union t_IOR
+{
+  unsigned short WORD;
+  struct
+  {
+    unsigned char IOR15:1;
+    unsigned char IOR14:1;
+    unsigned char IOR13:1;
+    unsigned char IOR12:1;
+    unsigned char IOR11:1;
+    unsigned char IOR10:1;
+    unsigned char IOR9:1;
+    unsigned char IOR8:1;
+    unsigned char IOR7:1;
+    unsigned char IOR6:1;
+    unsigned char IOR5:1;
+    unsigned char IOR4:1;
+    unsigned char IOR3:1;
+    unsigned char IOR2:1;
+    unsigned char IOR1:1;
+    unsigned char IOR0:1;
+  }
+  BIT;
+}
+PORT;
+
+int
+main ()
+{
+  volatile unsigned char a;
+
+  /* Instruction generated is BXOR.B #imm3, @(disp12, Rn)  */
+  USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 ^ USRSTR.ICR0.BIT.BIT1;
+  USRSTR.ICR0.BIT.BIT2 = USRSTR.ICR0.BIT.BIT6 ^ USRSTR.ICR0.BIT.BIT6;
+  USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 ^ USRSTR.ICR0.BIT.BIT4;
+  USRSTR.ICR0.BIT.BIT6 = USRSTR.ICR0.BIT.BIT1 ^ USRSTR.ICR0.BIT.BIT3;
+
+  a = USRSTR.ICR0.BIT.BIT0 ^ USRSTR.ICR0.BIT.BIT1;
+  a = USRSTR.ICR0.BIT.BIT5 ^ USRSTR.ICR0.BIT.BIT7;
+  a = USRSTR.ICR0.BIT.BIT2 ^ USRSTR.ICR0.BIT.BIT6;
+
+  PORT.BIT.IOR13 = PORT.BIT.IOR0  ^  USRSTR.ICR0.BIT.BIT7;
+  PORT.BIT.IOR15 = PORT.BIT.IOR6  ^  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR3  = PORT.BIT.IOR2  ^  USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR1  = PORT.BIT.IOR13 ^  USRSTR.ICR0.BIT.BIT1;
+
+  PORT.BIT.IOR1  = PORT.BIT.IOR2  ^  USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR11 = PORT.BIT.IOR9  ^  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR8  = PORT.BIT.IOR14 ^  USRSTR.ICR0.BIT.BIT5;
+
+  PORT.BIT.IOR10 ^= USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR1  ^= USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR5  ^= USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR14 ^= USRSTR.ICR0.BIT.BIT4;
+
+  /* Instruction generated on using size optimization option "-Os".  */
+  a = a ^ USRSTR.ICR0.BIT.BIT1;
+  a = a ^ USRSTR.ICR0.BIT.BIT4;
+  a = a ^ USRSTR.ICR0.BIT.BIT0;
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-jsrn.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-jsrn.c
new file mode 100644
index 000000000..9b9b92cb9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-jsrn.c
@@ -0,0 +1,15 @@
+/* Testcase to check generation of a SH2A specific instruction for
+   'JSR/N @Rm'.  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O0" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "jsr/n"} }  */
+
+void foo(void)
+{
+}
+
+void bar()
+{
+  foo();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-movi20s.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-movi20s.c
new file mode 100644
index 000000000..55d2f665b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-movi20s.c
@@ -0,0 +1,14 @@
+/* Testcase to check generation of 'MOVI20S #imm20, Rn'.  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O0" } */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "movi20s"} }  */
+
+volatile long la;
+
+void
+testfun (void)
+{
+  la = -134217728;
+  la = 134217216;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-movrt.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-movrt.c
new file mode 100644
index 000000000..9df9f4ba9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-movrt.c
@@ -0,0 +1,15 @@
+/* Testcase to check generation of a SH2A specific instruction for
+   'MOVRT Rn'.  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O1" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "movrt"} }  */
+
+int
+foo (void)
+{
+  int a, b, g, stop;
+  if (stop = ((a + b) % 2 != g))
+    ;
+  return stop;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-prefetch.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-prefetch.c
new file mode 100644
index 000000000..e0c9a0d7d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-prefetch.c
@@ -0,0 +1,34 @@
+/* Testcase to check generation of a SH2A specific instruction PREF @Rm.  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O0" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "pref"} }  */
+
+void
+opt (void)
+{
+  int *p, wk;
+  int data[100];
+
+  /* data prefetch , instructions hit the cache. */
+
+  __builtin_prefetch (&data[0], 0, 0);
+  __builtin_prefetch (&data[0], 0, 1);
+  __builtin_prefetch (&data[0], 0, 2);
+  __builtin_prefetch (&data[0], 0, 3);
+  __builtin_prefetch (&data[0], 1, 0);
+  __builtin_prefetch (&data[0], 1, 1);
+  __builtin_prefetch (&data[0], 1, 2);
+  __builtin_prefetch (&data[0], 1, 3);
+
+
+  for (p = &data[0]; p < &data[9]; p++)
+    {
+      if (*p > *(p + 1))
+        {
+          wk = *p;
+          *p = *(p + 1);
+          *(p + 1) = wk;
+        }
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-resbank.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-resbank.c
new file mode 100644
index 000000000..aab6852f3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-resbank.c
@@ -0,0 +1,12 @@
+/* Test for resbank attribute.  */
+/* { dg-do assemble {target sh*-*-*}} */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */
+/* { dg-final { scan-assembler "resbank" } } */
+ 
+extern void bar(void);
+ 
+void foo(void) __attribute__((interrupt_handler, resbank));
+void foo(void)
+{
+  bar();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-rtsn.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-rtsn.c
new file mode 100644
index 000000000..2601ced5c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-rtsn.c
@@ -0,0 +1,11 @@
+/* Testcase to check generation of a SH2A specific instruction for
+   'RTS/N'.  */
+/* { dg-do assemble {target sh*-*-*}}  */
+/* { dg-options "-O0" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "rts/n"} }  */
+
+void
+bar (void)
+{
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c
new file mode 100644
index 000000000..8029b03dd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c
@@ -0,0 +1,22 @@
+/* Testcase to check generation of a SH2A specific,
+   TBR relative jump instruction - 'JSR @@(disp8,TBR)'.  */
+/* { dg-do assemble {target sh*-*-*}} */
+/* { dg-options "" } */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */
+/* { dg-final { scan-assembler-times "jsr/n\\t@@\\(40,tbr\\)" 1} } */
+/* { dg-final { scan-assembler-times "jsr/n\\t@@\\(72,tbr\\)" 1} } */
+ 
+extern void foo1 (void) __attribute__ ((function_vector(10)));
+extern void foo2 (void);
+extern int bar1 (void) __attribute__ ((function_vector(18)));
+extern int bar2 (void);
+
+int
+bar()
+{
+  foo1();
+  foo2();
+
+  bar1();
+  bar2();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c
new file mode 100644
index 000000000..b7081bf71
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c
@@ -0,0 +1,73 @@
+/* Verify that we generate movua to load unaligned 32-bit values.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O" } */
+/* { dg-final { scan-assembler-times "\tmovua\\.l\t" 6 } } */
+
+#ifdef __SH4A__
+/* Aligned.  */
+struct s0 { long long d : 32; } x0;
+long long f0() {
+  return x0.d;
+}
+
+/* Unaligned load.  */
+struct s1 { long long c : 8; long long d : 32; } x1;
+long long f1() {
+  return x1.d;
+}
+
+/* Unaligned load.  */
+struct s2 { long long c : 16; long long d : 32; } x2;
+long long f2() {
+  return x2.d;
+}
+
+/* Unaligned load.  */
+struct s3 { long long c : 24; long long d : 32; } x3;
+long long f3() {
+  return x3.d;
+}
+
+/* Aligned.  */
+struct s4 { long long c : 32; long long d : 32; } x4;
+long long f4() {
+  return x4.d;
+}
+
+/* Aligned.  */
+struct u0 { unsigned long long d : 32; } y0;
+unsigned long long g0() {
+  return y0.d;
+}
+
+/* Unaligned load.  */
+struct u1 { long long c : 8; unsigned long long d : 32; } y1;
+unsigned long long g1() {
+  return y1.d;
+}
+
+/* Unaligned load.  */
+struct u2 { long long c : 16; unsigned long long d : 32; } y2;
+unsigned long long g2() {
+  return y2.d;
+}
+
+/* Unaligned load.  */
+struct u3 { long long c : 24; unsigned long long d : 32; } y3;
+unsigned long long g3() {
+  return y3.d;
+}
+
+/* Aligned.  */
+struct u4 { long long c : 32; unsigned long long d : 32; } y4;
+unsigned long long g4() {
+  return y4.d;
+}
+#else
+asm ("movua.l\t");
+asm ("movua.l\t");
+asm ("movua.l\t");
+asm ("movua.l\t");
+asm ("movua.l\t");
+asm ("movua.l\t");
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-cos.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-cos.c
new file mode 100644
index 000000000..198d41f86
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-cos.c
@@ -0,0 +1,13 @@
+/* Verify that we generate single-precision sine and cosine approximate
+   (fsca) in fast math mode.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O -ffast-math" } */
+/* { dg-final { scan-assembler "\tfsca\t" } } */
+
+#if defined __SH4A__ && ! defined __SH4_NOFPU__
+#include <math.h>
+
+double test(double f) { return cos(f); }
+#else
+asm ("fsca\t");
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-cosf.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-cosf.c
new file mode 100644
index 000000000..f78c140d5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-cosf.c
@@ -0,0 +1,13 @@
+/* Verify that we generate single-precision sine and cosine approximate
+   (fsca) in fast math mode.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O -ffast-math" } */
+/* { dg-final { scan-assembler "\tfsca\t" } } */
+
+#if defined __SH4A__ && ! defined __SH4_NOFPU__
+#include <math.h>
+
+float test(float f) { return cosf(f); }
+#else
+asm ("fsca\t");
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-fprun.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-fprun.c
new file mode 100644
index 000000000..40c2b05aa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-fprun.c
@@ -0,0 +1,37 @@
+/* Verify that fsca and fssra yield reasonable results.  */
+/* This test calls the sinf and cosf library functions for targets other
+   than sh4a, but the VxWorks kernel doesn't have those functions.  */
+/* { dg-do run { target { "sh*-*-*" && { ! vxworks_kernel } } } } */
+/* { dg-options "-O -ffast-math" } */
+
+#include <math.h>
+#include <stdlib.h>
+
+float sqrt_arg = 4.0f, sqrt_res = 2.0f;
+float dg2rad_f;
+double dg2rad_d;
+
+void check_f (float res, float expected) {
+  if (res >= expected - 0.001f && res <= expected + 0.001f)
+    return;
+
+  abort ();
+}
+
+void check_d (double res, double expected) {
+  if (res >= expected - 0.001 && res <= expected + 0.001)
+    return;
+
+  abort ();
+}
+
+int main() {
+  check_f (sqrtf(sqrt_arg), sqrt_res);
+  dg2rad_f = dg2rad_d = atan(1) / 45;
+  check_f (sinf(90*dg2rad_f), 1);
+  check_f (cosf(90*dg2rad_f), 0);
+  check_d (sin(-90*dg2rad_d), -1);
+  check_d (cos(180*dg2rad_d), -1);
+  check_d (sin(-45*dg2rad_d) * cosf(135*dg2rad_f), 0.5);
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c
new file mode 100644
index 000000000..c8f04e4d2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c
@@ -0,0 +1,13 @@
+/* Verify that we generate single-precision square root reciprocal
+   approximate (fsrra) in fast math mode.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O -ffast-math" } */
+/* { dg-final { scan-assembler "\tfsrra\t" } } */
+
+#if defined __SH4A__ && ! defined __SH4_NOFPU__
+#include <math.h>
+
+float test(float f) { return 1 / sqrtf(f); }
+#else
+asm ("fsrra\t");
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c
new file mode 100644
index 000000000..689279298
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c
@@ -0,0 +1,17 @@
+/* Verify that we generate movua to copy unaligned memory regions to
+   32-bit-aligned addresses.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O" } */
+/* { dg-final { scan-assembler-times "\tmovua\\.l\t(.*)+" 2 } } */
+
+#ifdef __SH4A__
+#include <stdlib.h>
+
+struct s { int i; char a[10], b[10]; } x;
+int f() {
+  memcpy(x.a, x.b, 10);
+}
+#else
+asm ("movua.l\t+");
+asm ("movua.l\t+");
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-sin.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-sin.c
new file mode 100644
index 000000000..9f46f6007
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-sin.c
@@ -0,0 +1,13 @@
+/* Verify that we generate single-precision sine and cosine approximate
+   (fsca) in fast math mode.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O -ffast-math" } */
+/* { dg-final { scan-assembler "\tfsca\t" } } */
+
+#if defined __SH4A__ && ! defined __SH4_NOFPU__
+#include <math.h>
+
+double test(double f) { return sin(f); }
+#else
+asm ("fsca\t");
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-sincos.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-sincos.c
new file mode 100644
index 000000000..f42937975
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-sincos.c
@@ -0,0 +1,14 @@
+/* Verify that we generate a single single-precision sine and cosine
+   approximate (fsca) in fast math mode when a function computes both
+   sine and cosine.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O -ffast-math" } */
+/* { dg-final { scan-assembler-times "\tfsca\t" 1 } } */
+
+#if defined __SH4A__ && ! defined __SH4_NOFPU__
+#include <math.h>
+
+double test(double f) { return sin(f) + cos(f); }
+#else
+asm ("fsca\t");
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c
new file mode 100644
index 000000000..42913dbd5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c
@@ -0,0 +1,14 @@
+/* Verify that we generate a single single-precision sine and cosine
+   approximate (fsca) in fast math mode when a function computes both
+   sine and cosine.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O -ffast-math" } */
+/* { dg-final { scan-assembler-times "\tfsca\t" 1 } } */
+
+#if defined __SH4A__ && ! defined __SH4_NOFPU__
+#include <math.h>
+
+float test(float f) { return sinf(f) + cosf(f); }
+#else
+asm ("fsca\t");
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-sinf.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-sinf.c
new file mode 100644
index 000000000..2a2343fd7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sh/sh4a-sinf.c
@@ -0,0 +1,13 @@
+/* Verify that we generate single-precision sine and cosine approximate
+   (fsca) in fast math mode.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O -ffast-math" } */
+/* { dg-final { scan-assembler "\tfsca\t" } } */
+
+#if defined __SH4A__ && ! defined __SH4_NOFPU__
+#include <math.h>
+
+float test(float f) { return sinf(f); }
+#else
+asm ("fsca\t");
+#endif
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/20001013-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/20001013-1.c
new file mode 100644
index 000000000..891ccab0a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/20001013-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
+
+extern void abort (void);
+extern void exit (int);
+
+int l;
+
+int baz (double x)
+{
+  return l == 0;
+}
+
+double bar (double x)
+{
+  return 1.0;
+}
+
+double foo (double x)
+{
+  if (l == -1 || baz (x)) return x;
+  if (x < 0.0)
+    return bar (x);
+  else
+    return 0.0;
+}
+
+union {
+  double d;
+  long long l;
+} x = { l: 0x7ff8000000000000LL }, y;
+
+main ()
+{
+  unsigned int fsr = 0;
+  __asm __volatile ("ld %0, %%fsr" : : "m" (fsr));
+  y.d = foo (x.d);
+  __asm __volatile ("st %%fsr, %0" : "=m" (fsr));
+  if (x.l != y.l || (fsr & 0x3ff))
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/20001101-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/20001101-1.c
new file mode 100644
index 000000000..ec67e115f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/20001101-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
+
+extern void abort (void);
+extern void exit (int);
+
+int foo(double a, int b, int c, double *d, int h)
+{
+  int f, g;
+  double e;
+
+l:
+  f = (int) a;
+  a -= (double) f;
+  if (b == 1)
+    {
+      g = c;
+      f += g;
+      c -= g;
+    }
+  if (b == 2)
+    {
+      f++;
+      h = c;
+    }
+  if (!h)
+    {
+      for (g = 0; g <= 10; g++)
+        for (h = 0; h <= 10; h++)
+          e += d [10 + g - h];
+      goto l;
+    }
+  return f & 7;
+}
+
+int main()
+{
+  if (foo(0.1, 1, 3, 0, 1) != 3)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/20001102-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/20001102-1.c
new file mode 100644
index 000000000..b4ce8a0e7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/20001102-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
+
+extern void abort (void);
+extern void exit (int);
+
+int foo(double a, int b, int c, double *d, int h)
+{
+  int f, g;
+  double e;
+
+l:
+  f = (int) a;
+  a -= (double) f;
+  if (b == 1)
+    {
+      g = c;
+      f += g;
+      c -= g;
+    }
+  if (b == 2)
+    {
+      f++;
+      h = c;
+      goto l;
+    }
+
+  asm volatile ("" : : :
+		"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+		"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+		"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+		"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31");
+
+  return f & 7;
+}
+
+int main()
+{
+  if (foo(0.1, 1, 3, 0, 1) != 3)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/20020116-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/20020116-2.c
new file mode 100644
index 000000000..828ffff26
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/20020116-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=supersparc" } */
+
+/* This testcase ICEd on sparc64 because -mcpu=supersparc and implicit
+   -m64 resulted in MASK_V8 and MASK_V9 to be set at the same time.  */
+
+void bar (long *x, long *y);
+
+void foo (int x, long *y, long *z)
+{
+  int i;
+
+  for (i = x - 1; i >= 0; i--)
+    {
+      bar (z + i * 3 + 1, y);
+      bar (z + i * 3 + 2, y);
+    }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/20020416-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/20020416-1.c
new file mode 100644
index 000000000..05f0ee655
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/20020416-1.c
@@ -0,0 +1,15 @@
+/* PR bootstrap/6315 */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mhard-quad-float" } */
+
+void bar (const char *, ...);
+
+void
+foo (const char *x, long double y, int z)
+{
+  if (z >= 0)
+    bar (x, z, y);
+  else
+    bar (x, y);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/align.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/align.c
new file mode 100644
index 000000000..804ca9397
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/align.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef long long int64_t;
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+vec16 foo1 (vec16 a, vec16 b) {
+  return __builtin_vis_faligndatav4hi (a, b);
+}
+
+vec32 foo2 (vec32 a, vec32 b) {
+  return __builtin_vis_faligndatav2si (a, b);
+}
+
+vec8 foo3 (vec8 a, vec8 b) {
+  return __builtin_vis_faligndatav8qi (a, b);
+}
+
+int64_t foo4 (int64_t a, int64_t b) {
+  return __builtin_vis_faligndatadi (a, b);
+}
+
+unsigned char * foo5 (unsigned char *data) {
+  return __builtin_vis_alignaddr (data, 0);
+}
+
+/* { dg-final { scan-assembler-times "faligndata" 4 } } */
+/* { dg-final { scan-assembler "alignaddr.*%g0" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/combined-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/combined-1.c
new file mode 100644
index 000000000..5f19db3b0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/combined-1.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int vec32 __attribute__((vector_size(8)));
+
+vec16 fun16(vec16 a, vec16 b)
+{
+  return (~a & b) + (b | a) - (a ^ b);
+}
+
+vec32 fun32(vec32 a, vec32 b)
+{
+  return (~a & b) + (b | a) - (a ^ b);
+}
+
+/* This should be transformed into ~b & a.  */
+vec16 fun16b(vec16 a, vec16 b)
+{
+  return (a & ~b) + (b | a) - (a ^ b);
+}
+
+vec32 fun32b(vec32 a, vec32 b)
+{
+  return (a & ~b) + (b | a) - (a ^ b);
+}
+
+/* { dg-final { scan-assembler-times "fandnot1\t%" 4 } } */
+/* { dg-final { scan-assembler-times "for\t%" 4 } } */
+/* { dg-final { scan-assembler-times "fpadd" 4 } } */
+/* { dg-final { scan-assembler-times "fxor\t%" 4 } } */
+/* { dg-final { scan-assembler-times "fpsub" 4 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/combined-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/combined-2.c
new file mode 100644
index 000000000..c4b70a55a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/combined-2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
+typedef unsigned char pixel __attribute__((vector_size(4)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+
+vec16 foo (pixel a, pixel b) {
+  vec8 c = __builtin_vis_fpmerge (a, b);
+  vec16 d = { -1, -1, -1, -1 };
+  vec16 e = __builtin_vis_fmul8x16 (a, d);
+
+  return e;
+}
+
+vec16 bar (pixel a) {
+  vec16 d = { 0, 0, 0, 0 };
+  vec16 e = __builtin_vis_fmul8x16 (a, d);  /* Mulitplication by 0 = 0.  */
+
+  return e;
+}
+
+/* { dg-final { scan-assembler "fmul8x16" } } */
+/* { dg-final { scan-assembler "fzero" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fand.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fand.c
new file mode 100644
index 000000000..3194c921c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fand.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () & foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return a & b;
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () & foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return a & b;
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return foo1_32 () & foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return a & b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fand\t%" 3 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fandnot.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fandnot.c
new file mode 100644
index 000000000..41db849c2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fandnot.c
@@ -0,0 +1,96 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () & foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return ~a & b;
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () & foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return ~a & b;
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~foo1_32 () & foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return ~a & b;
+}
+#endif
+
+
+/* This should be transformed into ~b & a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () & ~foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2b(vec8 a, vec8 b)
+{
+  return a & ~b;
+}
+#endif
+
+vec16 fun16b(void)
+{
+  return foo1_16 () & ~foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2b(vec16 a, vec16 b)
+{
+  return a & ~b;
+}
+#endif
+
+vec32 fun32b(void)
+{
+  return foo1_32 () & ~foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2b(vec32 a, vec32 b)
+{
+  return a & ~b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fandnot1\t%" 6 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fandnots.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fandnots.c
new file mode 100644
index 000000000..7a5ed2414
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fandnots.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () & foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () & foo1_16 ();
+}
+
+
+/* This should be transformed into ~b & a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () & ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return foo1_16 () & ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fandnot1s\t%" 4 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fands.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fands.c
new file mode 100644
index 000000000..f924f4531
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fands.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () & foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () & foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fands\t%" 2 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fexpand-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fexpand-2.c
new file mode 100644
index 000000000..e8b0970fe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fexpand-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -fdump-tree-final_cleanup -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(4)));
+
+vec16 foo () {
+  vec8 a = {(unsigned char)1,(unsigned char)2,(unsigned char)4,(unsigned char)8};
+  return __builtin_vis_fexpand (a);
+}
+
+/* { dg-final { scan-tree-dump "{ 16, 32, 64, 128 }" "final_cleanup" } } */
+/* { dg-final { cleanup-tree-dump "final_cleanup" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fexpand.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fexpand.c
new file mode 100644
index 000000000..21aeafff0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fexpand.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(4)));
+
+vec16 foo (vec8 a) {
+  return __builtin_vis_fexpand (a);
+}
+
+/* { dg-final { scan-assembler "fexpand\t%" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fnand.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fnand.c
new file mode 100644
index 000000000..89fe8694d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fnand.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () & foo2_8 ());
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () & foo2_16 ());
+}
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~(foo1_32 () & foo2_32 ());
+}
+
+
+/* DeMorgan's Law's at work.  */
+vec8 fun8b(void)
+{
+  return ~foo1_8 () | ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return ~foo1_16 () | ~foo2_16 ();
+}
+
+vec32 fun32b(void)
+{
+  return ~foo1_32 () | ~foo2_32 ();
+}
+
+/* { dg-final { scan-assembler-times "fnand\t%" 6 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fnands.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fnands.c
new file mode 100644
index 000000000..05d6c4733
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fnands.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () & foo2_8 ());
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () & foo1_16 ());
+}
+
+/* DeMorgan's Law's at work.  */
+vec8 fun8b(void)
+{
+  return ~foo1_8 () | ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return ~foo1_16 () | ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fnands\t%" 4 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fnot.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fnot.c
new file mode 100644
index 000000000..dceee52f7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fnot.c
@@ -0,0 +1,56 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern void foo2_8(vec8);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a)
+{
+  foo2_8 (~a);
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern void foo2_16(vec16);
+
+
+vec16 fun16(void)
+{
+  return ~foo1_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a)
+{
+  foo2_16 (~a);
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern void foo2_32(vec32);
+
+vec32 fun32(void)
+{
+  return ~foo1_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a)
+{
+  foo2_32 (~a);
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fnot1\t%" 3 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fnots.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fnots.c
new file mode 100644
index 000000000..f50eb0b3a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fnots.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 ();
+}
+
+extern vec16 foo1_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fnot1s\t%" 2 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/for.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/for.c
new file mode 100644
index 000000000..7348dce20
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/for.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () | foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return a | b;
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () | foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return a | b;
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return foo1_32 () | foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return a | b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "for\t%" 3 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fornot.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fornot.c
new file mode 100644
index 000000000..09fdb4f98
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fornot.c
@@ -0,0 +1,96 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () | foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return ~a | b;
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () | foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return ~a | b;
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~foo1_32 () | foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return ~a | b;
+}
+#endif
+
+
+/* This should be transformed into ~b | a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () | ~foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2b(vec8 a, vec8 b)
+{
+  return a | ~b;
+}
+#endif
+
+vec16 fun16b(void)
+{
+  return foo1_16 () | ~foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2b(vec16 a, vec16 b)
+{
+  return a | ~b;
+}
+#endif
+
+vec32 fun32b(void)
+{
+  return foo1_32 () | ~foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2b(vec32 a, vec32 b)
+{
+  return a | ~b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fornot1\t%" 6 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fornots.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fornots.c
new file mode 100644
index 000000000..db29a9926
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fornots.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () | foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () | foo1_16 ();
+}
+
+
+/* This should be transformed into ~b | a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () | ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return foo1_16 () | ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fornot1s\t%" 4 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fors.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fors.c
new file mode 100644
index 000000000..0afdd4bbc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fors.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () | foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () | foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fors\t%" 2 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpack16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpack16.c
new file mode 100644
index 000000000..79e0c4c15
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpack16.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(4)));
+
+vec8 foo (vec16 a) {
+  return __builtin_vis_fpack16 (a);
+}
+
+/* { dg-final { scan-assembler "fpack16\t%" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpack32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpack32.c
new file mode 100644
index 000000000..031372e21
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpack32.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+vec8 foo (vec32 a, vec8 b) {
+  return __builtin_vis_fpack32 (a, b);
+}
+
+/* { dg-final { scan-assembler "fpack32\t%" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpackfix.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpackfix.c
new file mode 100644
index 000000000..815bec0cf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpackfix.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+vec16 foo (vec32 a) {
+  return __builtin_vis_fpackfix (a);
+}
+
+/* { dg-final { scan-assembler "fpackfix\t%" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpadd16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpadd16.c
new file mode 100644
index 000000000..071282d2e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpadd16.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+  return a + b;
+}
+
+/* { dg-final { scan-assembler "fpadd16\t%" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpadd16s.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpadd16s.c
new file mode 100644
index 000000000..7f65a7a93
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpadd16s.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(4)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+  return a + b;
+}
+
+/* { dg-final { scan-assembler "fpadd16s\t%" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpadd32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpadd32.c
new file mode 100644
index 000000000..7c57018a7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpadd32.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+
+vec32 foo(vec32 a, vec32 b)
+{
+  return a + b;
+}
+
+/* { dg-final { scan-assembler "fpadd32\t%" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpadd32s.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpadd32s.c
new file mode 100644
index 000000000..709ad83c4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpadd32s.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(4)));
+
+extern vec32 foo1(void);
+extern vec32 foo2(void);
+
+vec32 bar(void)
+{
+  return foo1 () + foo2 ();
+}
+
+/* { dg-final { scan-assembler "fpadd32s\t%" }  } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpmerge-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpmerge-2.c
new file mode 100644
index 000000000..423172fbb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpmerge-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis -O1 -fdump-tree-final_cleanup" } */
+typedef unsigned char pixel __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(4)));
+
+#define _(ARG) (unsigned char)ARG
+
+pixel foo () {
+  vec8 a = { _(1), _(3), _(5), _(7) };
+  vec8 b = { _(2), _(4), _(6), _(8) };
+  return __builtin_vis_fpmerge (a, b);
+}
+
+/* { dg-final { scan-assembler-not "fpmerge\t%" } } */
+/* { dg-final { scan-tree-dump "{ 1, 2, 3, 4, 5, 6, 7, 8 }" "final_cleanup" } } */
+/* { dg-final { cleanup-tree-dump "final_cleanup" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpmerge.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpmerge.c
new file mode 100644
index 000000000..4d6a9c023
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpmerge.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef unsigned char pixel __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(4)));
+
+pixel foo (vec8 a, vec8 b) {
+  return __builtin_vis_fpmerge (a, b);
+}
+
+/* { dg-final { scan-assembler "fpmerge\t%" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpmul-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpmul-2.c
new file mode 100644
index 000000000..376d47b40
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpmul-2.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis -O1 -fdump-tree-final_cleanup" } */
+
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+typedef unsigned char pixel __attribute__((vector_size(4)));
+typedef short pixel16 __attribute__((vector_size(4)));
+
+vec16 foo1 () {
+  pixel a = { (unsigned char)1, (unsigned char)2, (unsigned char)3, (unsigned char)4 };
+  vec16 b = { (short)1, (short)2, (short)3, (short)4 };
+  return __builtin_vis_fmul8x16 (a, b);
+}
+
+vec16 foo1_1 () {
+  pixel a = { (unsigned char)1, (unsigned char)1, (unsigned char)1, (unsigned char)1 };
+  vec16 b = { (short)256, (short)512, (short)1024, (short)2048 };
+  return __builtin_vis_fmul8x16 (a, b);
+}
+
+vec16 foo1_2 () {
+  pixel a = { (unsigned char)255, (unsigned char)255, (unsigned char)255, (unsigned char)255 };
+  vec16 b = { (short)256, (short)512, (short)1024, (short)32767 };
+  return __builtin_vis_fmul8x16 (a, b);
+}
+/* { dg-final { scan-assembler-not "fmul8x16\t%" } } */
+/* { dg-final { scan-tree-dump "{ 0, 0, 0, 0 }" "final_cleanup" } } */
+/* { dg-final { scan-tree-dump "{ 1, 2, 4, 8 }" "final_cleanup" } } */
+/* { dg-final { scan-tree-dump "{ 255, 510, 1020, 32639 }" "final_cleanup" } } */
+
+vec16 foo2 () {
+  pixel a = { 1, 2, 3, 4 };
+  pixel16 b = { 256, 512 };
+  return __builtin_vis_fmul8x16au (a, b);
+}
+/* { dg-final { scan-assembler-not "fmul8x16au\t%" } } */
+/* { dg-final { scan-tree-dump "{ 1, 2, 3, 4 }" "final_cleanup" } } */
+
+vec16 foo3 () {
+  pixel a = { 1, 2, 3, 4 };
+  pixel16 b = { 256, 512 };
+  return __builtin_vis_fmul8x16al (a, b);
+}
+/* { dg-final { scan-assembler-not "fmul8x16al\t%" } } */
+/* { dg-final { scan-tree-dump "{ 2, 4, 6, 8 }" "final_cleanup" } } */
+/* { dg-final { cleanup-tree-dump "final_cleanup" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpmul.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpmul.c
new file mode 100644
index 000000000..71b3b17ac
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpmul.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char pixel __attribute__((vector_size(4)));
+typedef short pixel16 __attribute__((vector_size(4)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+vec16 foo1 (pixel a, vec16 b) {
+  return __builtin_vis_fmul8x16 (a, b);
+}
+
+vec16 foo2 (pixel a, pixel16 b) {
+  return __builtin_vis_fmul8x16au (a, b);
+}
+
+vec16 foo3 (pixel a, pixel16 b) {
+  return __builtin_vis_fmul8x16al (a, b);
+}
+
+vec16 foo4 (vec8 a, vec16 b) {
+  return __builtin_vis_fmul8sux16 (a, b);
+}
+
+vec16 foo5 (vec8 a, vec16 b) {
+  return __builtin_vis_fmul8ulx16 (a, b);
+}
+
+vec32 foo6 (pixel a, pixel16 b) {
+  return __builtin_vis_fmuld8sux16 (a, b);
+}
+
+vec32 foo7 (pixel a, pixel16 b) {
+  return __builtin_vis_fmuld8ulx16 (a, b);
+}
+
+/* { dg-final { scan-assembler "fmul8x16\t%" } } */
+/* { dg-final { scan-assembler "fmul8x16au\t%" } } */
+/* { dg-final { scan-assembler "fmul8x16al\t%" } } */
+/* { dg-final { scan-assembler "fmul8sux16\t%" } } */
+/* { dg-final { scan-assembler "fmul8ulx16\t%" } } */
+/* { dg-final { scan-assembler "fmuld8sux16\t%" } } */
+/* { dg-final { scan-assembler "fmuld8ulx16\t%" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpsub16.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpsub16.c
new file mode 100644
index 000000000..05642dec1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpsub16.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+  return a - b;
+}
+
+/* { dg-final { scan-assembler "fpsub16\t%" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpsub16s.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpsub16s.c
new file mode 100644
index 000000000..29e0d3e18
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpsub16s.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(4)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+  return a - b;
+}
+
+/* { dg-final { scan-assembler "fpsub16s\t%" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpsub32.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpsub32.c
new file mode 100644
index 000000000..e1813f491
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpsub32.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+
+vec32 foo(vec32 a, vec32 b)
+{
+  return a - b;
+}
+
+/* { dg-final { scan-assembler "fpsub32\t%" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpsub32s.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpsub32s.c
new file mode 100644
index 000000000..c9d4ccc6e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fpsub32s.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(4)));
+
+extern vec32 foo1(void);
+extern vec32 foo2(void);
+
+vec32 bar(void)
+{
+  return foo1 () - foo2 ();
+}
+
+/* { dg-final { scan-assembler "fpsub32s\t%" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fxnor.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fxnor.c
new file mode 100644
index 000000000..a685e08e0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fxnor.c
@@ -0,0 +1,96 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () ^ foo2_8 ());
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return ~(a ^ b);
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () ^ foo2_16 ());
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return ~(a ^ b);
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~(foo1_32 () ^ foo2_32 ());
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return ~(a ^ b);
+}
+#endif
+
+
+/* This should be transformed into ~(b ^ a).  */
+vec8 fun8b(void)
+{
+  return foo1_8 () ^ ~foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2b(vec8 a, vec8 b)
+{
+  return a ^ ~b;
+}
+#endif
+
+vec16 fun16b(void)
+{
+  return foo1_16 () ^ ~foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2b(vec16 a, vec16 b)
+{
+  return a ^ ~b;
+}
+#endif
+
+vec32 fun32b(void)
+{
+  return foo1_32 () ^ ~foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2b(vec32 a, vec32 b)
+{
+  return a ^ ~b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fxnor\t%" 6 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fxnors.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fxnors.c
new file mode 100644
index 000000000..29775cffe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fxnors.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () ^ foo2_8 ());
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () ^ foo1_16 ());
+}
+
+
+/* This should be transformed into ~(b ^ a).  */
+vec8 fun8b(void)
+{
+  return foo1_8 () ^ ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return foo1_16 () ^ ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fxnors\t%" 4 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fxor.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fxor.c
new file mode 100644
index 000000000..581b37b54
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fxor.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () ^ foo2_8 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return a ^ b;
+}
+#endif
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () ^ foo2_16 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return a ^ b;
+}
+#endif
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return foo1_32 () ^ foo2_32 ();
+}
+
+#ifndef __LP64__
+/* Test the 32-bit splitter. */
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return a ^ b;
+}
+#endif
+
+/* { dg-final { scan-assembler-times "fxor\t%" 3 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fxors.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fxors.c
new file mode 100644
index 000000000..5da017a28
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/fxors.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () ^ foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () ^ foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fxors\t%" 2 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/globalreg-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/globalreg-1.c
new file mode 100644
index 000000000..3839d9f13
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/globalreg-1.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -Os" } */
+
+/* This is a massively distilled test case based upon
+   mm/memory.c:unmap_vmas() in the Linux kernel when compiled
+   on sparc64 for SMP which uses a global register as the
+   base of the per-cpu variable area.
+
+   Because of a bug in global register handling in the dataflow
+   code, the loop-invariant pass would move 'expression(regval)'
+   outside of the loop.  */
+
+extern void exit(int);
+extern void abort(void);
+
+register unsigned long regval __asm__("g6");
+
+extern void cond_resched(void);
+
+unsigned int var;
+
+static unsigned long expression(unsigned long v)
+{
+  unsigned long ret;
+
+  __asm__("" : "=r" (ret) : "0" (0));
+  return ret + v;
+}
+
+void func(unsigned long *pp)
+{
+  int i;
+
+  for (i = 0; i < 56; i++) {
+    cond_resched();
+    *pp = expression(regval);
+  }
+}
+
+void __attribute__((noinline)) cond_resched(void)
+{
+	regval++;
+}
+
+int main(void)
+{
+  unsigned long val;
+
+  regval = 100;
+  func(&val);
+  if (val != 156)
+    abort();
+  exit(0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/mfpu.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/mfpu.c
new file mode 100644
index 000000000..e95754c5d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/mfpu.c
@@ -0,0 +1,11 @@
+/* Reported by Peter A. Krauss <peter.a.krauss@web.de> */
+
+/* { dg-do compile } */
+/* { dg-options "-mfpu" } */
+
+float square(float x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler "fmuls" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/noresult.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/noresult.c
new file mode 100644
index 000000000..1be7458d2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/noresult.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+
+void foo (vec16 a) {
+  __builtin_vis_fpack16 (a);
+}
+
+/* { dg-final { scan-assembler-not "fpack16\t%" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/pdist-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/pdist-2.c
new file mode 100644
index 000000000..9e061fdfd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/pdist-2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis -O1 -fdump-tree-final_cleanup" } */
+
+typedef long long int64_t;
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+#define _(A) (unsigned char)A
+
+int64_t foo () {
+  int64_t d = 2;
+  vec8 a = { _(1), _(2), _(3), _(4), _(5), _(6), _(7), _(255) };
+  vec8 b = { _(2), _(4), _(8), _(16), _(32), _(64), _(128), _(8) };
+  d = __builtin_vis_pdist (a, b, d);
+  return d;
+}
+
+/* { dg-final { scan-assembler-not "pdist\t%" } } */
+/* { dg-final { scan-tree-dump "return 475" "final_cleanup" } } */
+/* { dg-final { cleanup-tree-dump "final_cleanup" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/pdist-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/pdist-3.c
new file mode 100644
index 000000000..03df4d96d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/pdist-3.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-mcpu=ultrasparc -mvis -O1" } */
+
+typedef long long int64_t;
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+extern void abort ();
+extern void exit (int);
+
+#define _(A) (unsigned char)A
+
+int64_t foo (vec8 a, vec8 b) {
+  int64_t d = 2;
+  d = __builtin_vis_pdist (a, b, d);
+  return d;
+}
+
+int64_t bar () {
+  int64_t d = 2;
+  vec8 a = { _(1), _(2), _(3), _(4), _(5), _(6), _(7), _(255) };
+  vec8 b = { _(2), _(4), _(8), _(16), _(32), _(64), _(128), _(8) };
+  d = __builtin_vis_pdist (a, b, d);
+  return d;
+}
+
+
+static vec8 a = { 1, 2, 3, 4, 5, 6, 7, 255 };
+static vec8 b = { 2, 4, 8, 16, 32, 64, 128, 8 };
+
+int main (int argc, char *argv[]) {
+
+  if (foo (a, b) != bar ())
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/pdist.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/pdist.c
new file mode 100644
index 000000000..6ecc20aa1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/pdist.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef long long int64_t;
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+int64_t foo (vec8 a, vec8 b) {
+  int64_t d = 0;
+  d = __builtin_vis_pdist (a, b, d);
+  return d;
+}
+
+int64_t bar (vec8 a, vec8 b) {
+  int64_t d = 0;
+  return __builtin_vis_pdist (a, b, d);
+}
+
+int64_t baz (vec8 a, vec8 b, int64_t d) {
+  int64_t e = __builtin_vis_pdist (a, b, d);
+  return e + d;
+}
+
+/* { dg-final { scan-assembler-times "pdist\t%" 3 } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-constant-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-constant-1.c
new file mode 100644
index 000000000..491f9d3f8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-constant-1.c
@@ -0,0 +1,13 @@
+/* PR optimization/10876 */
+
+/* { dg-do compile } */
+
+/* Verify that adding the constant 4096 is turned
+   into substracting the constant -4096. */
+
+int foo(int a)
+{
+  return a+4096;
+}
+
+/* { dg-final { scan-assembler "sub" } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-dwarf2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-dwarf2.c
new file mode 100644
index 000000000..819ec3863
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-dwarf2.c
@@ -0,0 +1,32 @@
+/* PR target/10114 */
+/* Originator: James Troup <james@nocrew.org> */
+
+/* { dg-do compile } */
+/* { dg-options "-g -O1" } */
+
+extern __inline double sqrt (double __x)
+{
+  register double __r;
+  __asm ("fsqrtd %1,%0" : "=f" (__r) : "f" (__x));
+  return __r;
+}
+
+static double our_skew, max_update_skew;
+
+static double Sqr(double x)
+{
+  return x*x;
+}
+
+void REF_SetReference(double skew)
+{
+  double previous_skew, new_skew;
+  double old_weight, new_weight, sum_weight;
+  double delta_freq1, delta_freq2;
+  double skew1, skew2;
+
+  previous_skew = our_skew;
+  skew1 = sqrt((Sqr(delta_freq1) * old_weight + Sqr(delta_freq2) * new_weight) / sum_weight);
+  skew2 = (previous_skew * old_weight + new_skew * new_weight) / sum_weight;
+  our_skew = skew1 + skew2;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-frame-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-frame-1.c
new file mode 100644
index 000000000..7aac1e26e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-frame-1.c
@@ -0,0 +1,13 @@
+/* PR target/24284 */
+
+/* { dg-do compile } */
+/* { dg-options "-O -g" } */
+
+void do_run(void *ip)
+{
+  char dummy[8192];
+
+  __asm__("" : : "g"(dummy));
+
+  goto *ip;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-getcontext-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-getcontext-1.c
new file mode 100644
index 000000000..cd468c562
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-getcontext-1.c
@@ -0,0 +1,118 @@
+/* PR middle-end/22127 */
+/* Testcase by <akr@m17n.org> */
+
+/* { dg-do run { target *-*-solaris2.* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O" } */
+
+typedef unsigned int size_t;
+extern int printf(const char *, ...);
+typedef unsigned char uint8_t;
+typedef unsigned int uint32_t;
+typedef unsigned int uint_t;
+typedef char *caddr_t;
+typedef int greg_t;
+typedef greg_t gregset_t[19];
+struct rwindow {
+ greg_t rw_local[8];
+ greg_t rw_in[8];
+};
+typedef struct gwindows {
+ int wbcnt;
+ greg_t *spbuf[31];
+ struct rwindow wbuf[31];
+} gwindows_t;
+struct fpu {
+ union {
+  uint32_t fpu_regs[32];
+  double fpu_dregs[16];
+ } fpu_fr;
+ struct fq *fpu_q;
+ uint32_t fpu_fsr;
+ uint8_t fpu_qcnt;
+ uint8_t fpu_q_entrysize;
+ uint8_t fpu_en;
+};
+typedef struct fpu fpregset_t;
+typedef struct {
+ unsigned int xrs_id;
+ caddr_t xrs_ptr;
+} xrs_t;
+typedef struct {
+ gregset_t gregs;
+ gwindows_t *gwins;
+ fpregset_t fpregs;
+ xrs_t xrs;
+ long filler[19];
+} mcontext_t;
+typedef struct {
+ unsigned int __sigbits[4];
+} sigset_t;
+typedef struct sigaltstack {
+ void *ss_sp;
+ size_t ss_size;
+ int ss_flags;
+} stack_t;
+typedef struct ucontext ucontext_t;
+struct ucontext {
+ uint_t uc_flags;
+ ucontext_t *uc_link;
+ sigset_t uc_sigmask;
+ stack_t uc_stack;
+ mcontext_t uc_mcontext;
+ long uc_filler[23];
+};
+extern int getcontext(ucontext_t *);
+extern int setcontext(const ucontext_t *);
+
+int flag;
+ucontext_t cont;
+int pad[100];
+typedef void (*fun_t)(int);
+fun_t p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12;
+
+int global;
+
+extern void abort(void);
+
+void h1(int v)
+{
+  global = v;
+}
+
+void h2(int v)
+{
+  if (v != 1)
+    abort();
+}
+
+void f(void)
+{
+  flag = 1;
+  setcontext(&cont);
+}
+
+int g(void)
+{
+  int ret;
+
+  flag = 0;
+  getcontext(&cont);
+  ret = flag;
+  if (ret == 0) {
+    h1 (flag);
+    p0 = p1 = p2 = p3 = p4 = p5 = p6 = p7 = p8 = h1;
+    f();
+    p0(ret); p1(ret); p2(ret); p3(ret); p4(ret); p5(ret); p6(ret); p7(ret); p8(ret);
+  }
+  else {
+    h2 (flag);
+  }
+  return ret;
+}
+
+int main(void)
+{
+  g();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-loop-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-loop-1.c
new file mode 100644
index 000000000..cb8d00762
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-loop-1.c
@@ -0,0 +1,19 @@
+/* PR optimization/10157 */
+/* Originator: Peter van Hoof <p.van-hoof@qub.ac.uk> */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math" } */
+
+/* Verify that the loop optimizer doesn't
+   emit invalid reg-to-reg copy insns. */
+
+void g() {
+  while(1) {
+    int i,n;
+    double p,r;
+    for( i=0; i < n; i++ )
+      if( p > 1. )
+        for( i=0; i < n; i++ )
+          r += 2.;
+  }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-reg-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-reg-1.c
new file mode 100644
index 000000000..0adb4cdca
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-reg-1.c
@@ -0,0 +1,11 @@
+/* PR middle-end/20263 */
+
+/* { dg-do assemble } */
+/* { dg-options "" } */
+
+register void *tp __asm__("%g7");
+
+void set_tp(void)
+{
+  tp = 0;
+} 
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-ret.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-ret.c
new file mode 100644
index 000000000..11afc1082
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-ret.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-mcpu=ultrasparc -O" } */
+
+/* Make sure that Ultrasparc return insn do not read below the stack.  */
+
+int bar (int a, int b, int c, int d, int e, int f, int g, int h)
+{
+  int res;
+
+  toto (&res);
+  return h;
+}
+/* { dg-final { global compiler_flags; if ![string match "*-m64 *" $compiler_flags] { scan-assembler "return\[ \t\]*%i7\\+8\n\[^\n\]*ld\[ \t\]*\\\[%sp\\+96\\\]" } } } */
+
+int bar2 ()
+{
+  int res;
+
+  toto (&res);
+  return res;
+}
+/* { dg-final { global compiler_flags; if ![string match "*-m64 *" $compiler_flags] { scan-assembler "return\[ \t\]*%i7\\+8\n\[^\n\]*nop" } } } */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-trap-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-trap-1.c
new file mode 100644
index 000000000..82a86fbe1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc-trap-1.c
@@ -0,0 +1,21 @@
+/* PR target/15693 */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* This used to fail on SPARC at -O2 because the combiner
+   produces a compare insn that was not rematched by the
+   compare expander.  */
+
+static __inline__ __attribute__ ((always_inline))
+int page_mapping (unsigned flags)
+{
+  if (1u & (flags >> 16))
+    return 1;
+  return 0;
+}
+void install_page (unsigned flags)
+{
+  if (__builtin_expect (!page_mapping (flags), 0))
+    __builtin_trap ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc.exp
new file mode 100644
index 000000000..9658d08bc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/sparc.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 1997, 2004, 2007 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a SPARC target.
+if ![istarget sparc*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/struct-ret-check.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/struct-ret-check.c
new file mode 100644
index 000000000..350224eb6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/struct-ret-check.c
@@ -0,0 +1,126 @@
+/* Copyright (C) 2006 Free Software Foundation, Inc. */
+/* Contributed by Carlos O'Donell on 2006-03-14 */
+
+/* Test that GCC follows the SPARC 32-bit psABI with regards to
+   structure return checking in a callee. When -mstd-struct-return 
+   is specificed then gcc will emit code to skip the unimp insn. */ 
+
+/* Origin: Carlos O'Donell <carlos@codesourcery.com> */
+/* { dg-do run { target sparc*-*-solaris* sparc*-*-linux* sparc*-*-*bsd* } } */
+/* { dg-options "-mstd-struct-return" } */
+/* { dg-require-effective-target ilp32 } */
+#include <stdio.h>
+#include <stdlib.h>
+#include <signal.h>
+
+/* Local declaration of div_t structure */
+struct mydiv_t {
+  int rem;
+  int quot;
+};
+
+/* Global check variable used by signal handler */
+int check = 1;
+struct mydiv_t dcheck;
+
+struct mydiv_t foo (void)
+{
+  struct mydiv_t bar;
+  bar.rem = 3;
+  bar.quot = 4;
+  return bar;
+}
+
+void handle_sigill (int signum)
+{
+  if (signum == SIGILL && check == 2)
+    {
+      /* We expected a SIGILL due to a mismatch in unimp size
+	 and struct mydiv_t size */
+      exit (0);
+    }
+  else
+    abort ();
+}
+
+/* Implement 3 checks to validate SPARC 32-bit psABI callee 
+   returns struct
+   
+   Test1: Save area is valid. unimp size is valid.
+   Success: Save area modified correctly.
+   Failure: Save area unmodified.
+
+   Test2: Save area is valid. unimp size is invalid (invalid insn).
+   Success: Save area unmodified. check == 2.
+   Failure: Save area modified or check == 1.
+
+   Test3: Save area is invalid. unimp size is invalid (invalid size).
+   Success: Will raise a SIGILL. 
+   Failure: SIGSEGV caused by write to invalid save area. */
+
+int main (void)
+{
+  dcheck.rem = 1;
+  dcheck.quot = 2;
+
+  /*** Test1 ***/
+  /* Insert a call, insert unimp by hand */
+  __asm__ ("st %1, [ %%sp + 0x40 ]\n\t"
+	   "call foo\n\t"
+	   " nop\n\t"
+	   "unimp %2\n\t" 
+	   : "=m" (dcheck)
+	   : "r" (&dcheck), "i" (sizeof(struct mydiv_t)) 
+	   : "memory");
+
+  /* If the caller doesn't adjust the return, then it crashes.
+     Check the result too. */
+
+  if ((dcheck.rem != 3) || (dcheck.quot !=4))
+    abort ();
+  
+
+  /*** Test 2 ***/
+  dcheck.rem = 1;
+  dcheck.quot = 2;
+
+  /* Ignore the return of the function */
+  __asm__ ("st %3, [ %%sp + 0x40 ]\n\t"
+	   "call foo\n\t"
+	   " nop\n\t"
+	   "mov %2, %0\n\t"
+	   : "+r" (check), "=m" (dcheck) 
+	   : "i" (0x2), "r" (&dcheck)
+	   : "memory");
+
+  /* If the caller does an unconditional adjustment it will skip
+     the mov, and then we can fail the test based on check's value 
+     We pass a valid pointer to a save area in order to check if 
+     caller incorrectly wrote to the save area aswell. There may
+     be a case where the unimp check and skip is correct, but the
+     write to the save area still occurs. */
+
+  if (check != 2)
+    abort ();
+
+  if ((dcheck.rem != 1) || (dcheck.quot != 2))
+    abort ();
+
+  /*** Test 3 ***/
+  /* Prepare a test that must SIGILL. According to the spec
+     if the sizes of the save area and return don't match then
+     the copy is ignored and we return to the unimp. */
+
+  signal (SIGILL, handle_sigill);
+
+  __asm__ ("st %%g0, [ %%sp + 0x40 ]\n\t"
+	   "call foo\n\t"
+	   " nop\n\t"
+	   "unimp %0\n\t"
+	   : /* No outputs */ 
+	   : "i" (sizeof(struct mydiv_t)-1) 
+	   : "memory");
+
+  /* NEVER REACHED */
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp1.c
new file mode 100644
index 000000000..7db750589
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp1.c
@@ -0,0 +1,8 @@
+/* Simplified from testcase by David Staepelaere <staapa@ultimatech.com> */
+
+/* { dg-do compile } */
+/* { dg-options -mcpu=ultrasparc } */
+
+int foo(long long y) {
+  return -1 * y;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp10.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp10.c
new file mode 100644
index 000000000..d3edaca6c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp10.c
@@ -0,0 +1,27 @@
+/* PR target/11965 */
+/* Originator: <jk@tools.de> */
+
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-O -mcpu=ultrasparc" } */
+
+/* This used to fail on 32-bit Ultrasparc because GCC emitted
+   an invalid shift instruction.  */
+
+
+static inline unsigned int shift(int n, unsigned int value)
+{
+  return value << n;
+}
+
+unsigned int val = 1;
+
+int main(void)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    val = shift(32, val);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp11.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp11.c
new file mode 100644
index 000000000..91e64782b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp11.c
@@ -0,0 +1,26 @@
+/* PR target/17245 */
+/* Origin: <aaronw@net.com> */
+/* Testcase by Christian Ehrhardt <ehrhardt@mathematik.uni-ulm.de> */
+
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=v9" } */
+
+/* This used to fail on 32-bit Ultrasparc because reload was emitting
+   a move insn that doesn't satisfy its constraints.  */
+
+int n; 
+double range ;
+double bin ;
+double wmean;
+
+double f ()
+{
+  int i ;
+  long double W = 0 ;
+  for ( i = 0 ; i < n ; i ++) {
+    double xi = range;
+    double wi = bin;
+    W += wi ;
+    wmean += ( xi - wmean) * ( wi / W);
+  }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp2.c
new file mode 100644
index 000000000..24202ba5a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp2.c
@@ -0,0 +1,11 @@
+/* Copyright (C) 1999 Free Software Foundation
+   by Alexandre Oliva <oliva@lsd.ic.unicamp.br>
+   Simplified from libg++/src/Fix16.cc */
+
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+
+short foo() {
+  short i = (short)(1<<15);
+  return i;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp3.c
new file mode 100644
index 000000000..870258813
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp3.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-skip-if "" { ! { ilp32 && ultrasparc_hw } } } */
+/* { dg-options "-mcpu=ultrasparc -mv8plus" } */
+
+extern void abort (void);
+extern void exit (int);
+
+unsigned long long foo (unsigned long long x)
+{
+  return 0x73500000735LL * x;
+}
+
+unsigned long long a, b;
+unsigned long p;
+
+unsigned long long bar (void)  
+{
+  unsigned long long c = a | b;
+  return 0x73500000735LL * c;
+}
+
+unsigned long long baz (void)
+{
+  unsigned long long c = (p + 345) & -2;
+  return c * a;
+}
+
+int main (void)
+{
+  if (foo (0x56789LL) != 0x26f32e5d26f32e5dLL)
+    abort ();
+  a = 0x8000000080000000LL;
+  b = 0x0000000180000001LL;
+  if (bar () != 0x120480000735LL)
+    abort ();
+  p = 0xffffffff;
+  if (baz () != 0xac00000000LL)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp4.c
new file mode 100644
index 000000000..f3958cbe7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp4.c
@@ -0,0 +1,12 @@
+/* Simplified from PR target/5309.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ultrasparc" } */
+
+extern long bar (unsigned int);
+
+long
+foo (long x, unsigned int y)
+{
+  return *(((long *) (bar (y) - 1)) + 1 + (x >> 2) % 359);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp5.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp5.c
new file mode 100644
index 000000000..feb6cf244
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp5.c
@@ -0,0 +1,13 @@
+/* PR target/10072 */
+/* Originator: Peter van Hoof <p.van-hoof@qub.ac.uk> */
+
+/* { dg-do compile } */
+/* { dg-options "-std=c99 -O1 -mcpu=ultrasparc -ffast-math" } */
+
+void p(int v)
+{
+  int i=v,j;
+  float a,b,c,x[i];
+
+  x[i] = (a/(((b)>(c)) ? (b) : (c)) - (((i) == (j)) ? 1.f : 0.f));
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp6.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp6.c
new file mode 100644
index 000000000..ad341dc16
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp6.c
@@ -0,0 +1,151 @@
+/* PR target/7784 */
+/* Originator: Peter van Hoof <p.van-hoof@qub.ac.uk> */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ultrasparc" } */
+
+typedef struct
+{
+  float EnergyErg;
+  float ots;
+} EmLine;
+
+extern const int ipH_LIKE ;
+extern const int ipHYDROGEN ;
+extern const int ipH1s;
+extern const int ipH2s;
+extern const int ipH2p;
+
+extern EmLine ****EmisLines;
+
+typedef struct
+{
+  long n;
+  long s;
+  long l;
+} Elevels;
+
+extern struct t_iso
+{
+  float ***Pop2Ion;
+  long int numLevels[2][30L];
+} iso;
+
+extern struct t_LineSave
+{
+  long int nsum;
+  long int ndsum;
+  long int nComment;
+  long int npxdd;
+  long int ipass;
+  char chHoldComments[10][200];
+} LineSave;
+
+extern struct t_hydro
+{
+  int lgHydEmiss;
+  float **pestrk ;
+} hydro;
+
+extern struct t_dense
+{
+  double DensityLaw[10];
+  float frad[500];
+  float fhden[500];
+  float den0;
+  double eden;
+} dense;
+
+extern struct t_abund
+{
+  float xIonFracs[30L +3][30L +1];
+} abund;
+
+extern struct t_CaseBHS
+{
+  long int nDensity[2][8] , ntemp[2][8] , ncut[2][8] ;
+  int lgHCaseBOK[2][8];
+} CaseBHS ;
+
+extern struct t_smbeta
+{
+  float SimHBeta,
+    cn4861,
+    cn1216,
+    sv4861,
+    sv1216;
+} smbeta;
+
+extern struct t_phycon
+{
+  float te;
+} phycon;
+
+
+extern struct t_sphere
+{
+  int lgSphere;
+  float covgeo;
+} sphere;
+
+void linadd(double xInten, float wavelength, char *chLab, char chInfo);
+
+extern struct t_radiusVar
+{
+  int lgDrNeg;
+  double dVeff;
+} radius;
+
+void lines_hydro(void)
+{
+  long int i, nelem, ipHi, ipLo;
+  double hbetab, em , EmisFac, pump;
+  char chLabel[5];
+
+  linadd(abund.xIonFracs[ipHYDROGEN][1]*iso.Pop2Ion[ipH_LIKE][ipHYDROGEN][3]*hydro.pestrk[3][2]*3.025e-12, 6563,"Strk",'i');
+
+  linadd(abund.xIonFracs[ipHYDROGEN][1]*iso.Pop2Ion[ipH_LIKE][ipHYDROGEN][4]*hydro.pestrk[4][2]*4.084e-12, 4861,"Strk",'i');
+
+  linadd(abund.xIonFracs[ipHYDROGEN][1]*iso.Pop2Ion[ipH_LIKE][ipHYDROGEN][4]*hydro.pestrk[4][3]*1.059e-12, 18751,"Strk",'i');
+
+  linadd(abund.xIonFracs[ipHYDROGEN][1]*iso.Pop2Ion[ipH_LIKE][ipHYDROGEN][5]*hydro.pestrk[5][4]*4.900e-13, 40512,"Strk",'i');
+
+  ((void)((LineSave.ipass <1 || EmisLines[ipH_LIKE][ipHYDROGEN][ipH2p][ipH1s].ots>= 0.) || (__assert("LineSave.ipass <1 || EmisLines[ipH_LIKE][ipHYDROGEN][ipH2p][ipH1s].ots>= 0.", "lines_hydro.c", 118), 0)));
+
+  linadd(EmisLines[ipH_LIKE][ipHYDROGEN][3][ipH2s].ots*EmisLines[ipH_LIKE][ipHYDROGEN][3][ipH2s].EnergyErg, 6563,"Dest",'i');
+
+  linadd(EmisLines[ipH_LIKE][ipHYDROGEN][5][4].ots*EmisLines[ipH_LIKE][ipHYDROGEN][5][4].EnergyErg,40516, "Dest",'i');
+
+  smbeta.SimHBeta = smbeta.SimHBeta/(float)radius.dVeff*sphere.covgeo;
+
+  linadd(smbeta.SimHBeta,4861,"Q(H)",'i');
+
+  smbeta.SimHBeta = smbeta.SimHBeta*(float)radius.dVeff/sphere.covgeo;
+
+  for( nelem=0; nelem < 30L; nelem++ )
+  {
+    int iCase;
+    for( iCase=0; iCase<2; ++iCase )
+    {
+      char chAB[2]={'A','B'};
+      char chLab[5]="Ca  ";
+
+      for( ipLo=1+iCase; ipLo<(((6)<(iso.numLevels[ipH_LIKE][nelem])) ? (6) : (5)); ++ipLo )
+      {
+        for( ipHi=ipLo+1; ipHi< (((ipLo+5)<(iso.numLevels[ipH_LIKE][nelem])) ? (ipLo+5) : (iso.numLevels[ipH_LIKE][nelem])); ++ipHi )
+        {
+          float wl;
+
+          hbetab = HSRate( ipHi,ipLo , nelem+1, phycon.te , dense.eden, chAB[iCase] );
+          if( hbetab<=0. )
+            CaseBHS.lgHCaseBOK[iCase][nelem] = 0;
+
+          if( !hydro.lgHydEmiss )
+            hbetab *= abund.xIonFracs[nelem][nelem+1]*dense.eden;
+
+         linadd(hbetab,wl,chLab,'i' );
+        }
+      }
+    }
+  }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp7.c
new file mode 100644
index 000000000..b5a17b448
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp7.c
@@ -0,0 +1,51 @@
+/* PR c/8281 */
+/* Originator: TANIGUCHI Yasuaki <yasuaki@k8.dion.ne.jp> */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -mcpu=ultrasparc -fPIC" } */
+
+static const double bp = 1.0, dp_l[] = { 0.0 };
+
+double __ieee754_pow(double x, double y)
+{
+  union {
+    int lo;
+    double d;
+  }uz;
+
+  double y1,t1,p_h,t,z;
+  double z_h,z_l,p_l;
+  double t2,r,s,u,v,w;
+  int i = 0;
+ 
+  double s_h,t_h;
+  double s2,s_l,t_l;
+ 
+ 
+  v = 1.0/(v+bp);
+  uz.d = s_h = s = u*v;
+  uz.lo = 0;
+  s_h = uz.d;
+  uz.d = t_h;
+  uz.lo = 3;
+  t_h = uz.d;
+  s_l = v*((u-s_h*t_h)-s_h*t_l);
+  s2 = s*s;
+  r = s2* s2* (1.1+s2*(1.2+s2*(1.3+s2*(1.4+s2*(1.5+s2*1.6)))));
+  s2 = s_h*s_h;
+  uz.lo = 0;
+  t_h = uz.d;
+  t_l = r-((t_h-3.0)-s2);
+  v = s_l*t_h+t_l*s;
+  p_l = v-(p_h-u);
+  z_h = bp *p_h;
+  z_l = bp*p_h+p_l*1.0+dp_l[i];
+  t = (double)i;
+  t1 = (((bp+z_l)+bp)+t);
+  t2 = z_l-(((t1-t)-bp)-z_h);
+  p_l = (y-y1)*t1+y*t2;
+  z = p_l+p_h;
+
+  return s*z;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp8.c
new file mode 100644
index 000000000..a8bfefee5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp8.c
@@ -0,0 +1,40 @@
+/* PR target/10067 */
+/* Originator: <dat94ali@ludat.lth.se> */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=supersparc" } */
+
+struct _reent;
+
+extern unsigned long __malloc_trim_threshold;
+extern unsigned long __malloc_top_pad;
+
+int _mallopt_r(struct _reent *reent_ptr, int param_number, int value)
+{
+  __malloc_lock(reent_ptr);
+
+  switch(param_number)
+  {
+    case -1:
+      __malloc_trim_threshold = value;
+      __malloc_unlock(reent_ptr);
+      return 1;
+
+    case -2:
+      __malloc_top_pad = value;
+      __malloc_unlock(reent_ptr);
+      return 1;
+
+    case -3:
+      __malloc_unlock(reent_ptr);
+      return 1;
+
+    case -4:
+      __malloc_unlock(reent_ptr);
+      return value == 0;
+
+    default:
+      __malloc_unlock(reent_ptr);
+      return 0;
+  }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp9.c b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp9.c
new file mode 100644
index 000000000..b26d7dce1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/sparc/ultrasp9.c
@@ -0,0 +1,41 @@
+/* PR optimization/11018 */
+/* Originator: <partain@dcs.gla.ac.uk> */
+
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-O2 -mcpu=ultrasparc" } */
+
+/* This used to fail on 32-bit Ultrasparc because
+   of broken DImode shift patterns.  */
+
+extern void abort(void);
+
+typedef unsigned long long uint64_t;
+typedef unsigned int size_t;
+
+
+void to_octal (uint64_t value, char *where, size_t size)
+{
+  uint64_t v = value;
+  size_t i = size;
+
+  do
+    {
+      where[--i] = '0' + (v & ((1 << 3) - 1));
+      v >>= 3;
+    }
+  while (i);
+}
+
+
+int main (void)
+{
+  char buf[8];
+
+  to_octal(010644, buf, 6);
+
+  if (buf[1] != '1')
+     abort();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/Wmain.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/Wmain.c
new file mode 100644
index 000000000..58eca021b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/Wmain.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-Wmain -mstdmain" } */
+
+int main (void *wrong)/* { dg-warning "first argument of 'main' should be 'int'" "" } */
+{ 
+  /* { dg-warning "'main' takes only zero or two arguments" "" { target *-*-* } 4 } */
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/abi.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/abi.c
new file mode 100644
index 000000000..b435f1ede
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/abi.c
@@ -0,0 +1,474 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+/* Test that arguments are passed in the correct location according to the ABI.  */
+
+#include <stdlib.h>
+
+/* Hack to allow calling func_asm which takes 84 arguments that are scalars.
+   The function func_call takes 84 union quadword arguments, so we can check to
+   see if each scalar is passed in the correct location.  This asm glues the
+   two functions together, so that the compiler is not aware of the
+   aliasing.  */
+__asm__ ("func_asm = func_call");
+
+typedef unsigned int uqword __attribute__((mode(TI)));
+typedef int qword __attribute__((mode(TI)));
+
+union u
+{
+  uqword		uq;
+  qword			sq;
+  double		d[2];
+  float			f[4];
+  unsigned long long	ull[2];
+  long long		sll[2];
+  unsigned long		ul[4];
+  long			sl[4];
+  unsigned int		ui[4];
+  int			si[4];
+  unsigned short	us[8];
+  short			ss[8];
+  unsigned char		uc[16];
+  signed char		sc[16];
+};
+
+
+extern void func_asm(signed char a1,
+		     unsigned char a2,
+		     short a3,
+		     unsigned short a4,
+		     int a5,
+		     unsigned int a6,
+		     long a7,
+		     unsigned long a8,
+		     long long a9,
+		     unsigned long long a10,
+		     float a11,
+		     double a12,
+		     int a13,
+		     int a14,
+		     int a15,
+		     int a16,
+		     int a17,
+		     int a18,
+		     int a19,
+		     int a20,
+		     int a21,
+		     int a22,
+		     int a23,
+		     int a24,
+		     int a25,
+		     int a26,
+		     int a27,
+		     int a28,
+		     int a29,
+		     int a30,
+		     int a31,
+		     int a32,
+		     int a33,
+		     int a34,
+		     int a35,
+		     int a36,
+		     int a37,
+		     int a38,
+		     int a39,
+		     int a40,
+		     int a41,
+		     int a42,
+		     int a43,
+		     int a44,
+		     int a45,
+		     int a46,
+		     int a47,
+		     int a48,
+		     int a49,
+		     int a50,
+		     int a51,
+		     int a52,
+		     int a53,
+		     int a54,
+		     int a55,
+		     int a56,
+		     int a57,
+		     int a58,
+		     int a59,
+		     int a60,
+		     int a61,
+		     int a62,
+		     int a63,
+		     int a64,
+		     int a65,
+		     int a66,
+		     int a67,
+		     int a68,
+		     int a69,
+		     int a70,
+		     int a71,
+		     int a72,
+		     signed char a73,
+		     unsigned char a74,
+		     short a75,
+		     unsigned short a76,
+		     int a77,
+		     unsigned int a78,
+		     long a79,
+		     unsigned long a80,
+		     long long a81,
+		     unsigned long long a82,
+		     float a83,
+		     double a84);
+
+void func_call(union u a1,
+	       union u a2,
+	       union u a3,
+	       union u a4,
+	       union u a5,
+	       union u a6,
+	       union u a7,
+	       union u a8,
+	       union u a9,
+	       union u a10,
+	       union u a11,
+	       union u a12,
+	       union u a13,
+	       union u a14,
+	       union u a15,
+	       union u a16,
+	       union u a17,
+	       union u a18,
+	       union u a19,
+	       union u a20,
+	       union u a21,
+	       union u a22,
+	       union u a23,
+	       union u a24,
+	       union u a25,
+	       union u a26,
+	       union u a27,
+	       union u a28,
+	       union u a29,
+	       union u a30,
+	       union u a31,
+	       union u a32,
+	       union u a33,
+	       union u a34,
+	       union u a35,
+	       union u a36,
+	       union u a37,
+	       union u a38,
+	       union u a39,
+	       union u a40,
+	       union u a41,
+	       union u a42,
+	       union u a43,
+	       union u a44,
+	       union u a45,
+	       union u a46,
+	       union u a47,
+	       union u a48,
+	       union u a49,
+	       union u a50,
+	       union u a51,
+	       union u a52,
+	       union u a53,
+	       union u a54,
+	       union u a55,
+	       union u a56,
+	       union u a57,
+	       union u a58,
+	       union u a59,
+	       union u a60,
+	       union u a61,
+	       union u a62,
+	       union u a63,
+	       union u a64,
+	       union u a65,
+	       union u a66,
+	       union u a67,
+	       union u a68,
+	       union u a69,
+	       union u a70,
+	       union u a71,
+	       union u a72,
+	       union u a73,
+	       union u a74,
+	       union u a75,
+	       union u a76,
+	       union u a77,
+	       union u a78,
+	       union u a79,
+	       union u a80,
+	       union u a81,
+	       union u a82,
+	       union u a83,
+	       union u a84)
+{
+  /* arguments passed in registers */
+  if (a1.sc[3] != -1)			/* signed char */
+    abort ();
+
+  if (a2.uc[3] != +2)			/* unsigned char */
+    abort ();
+
+  if (a3.ss[1] != -3)			/* short */
+    abort ();
+
+  if (a4.us[1] != +4)			/* unsigned short */
+    abort ();
+
+  if (a5.si[0] != -5)			/* int */
+    abort ();
+
+  if (a6.ui[0] != +6)			/* unsigned int */
+    abort ();
+
+  if (a7.sl[0] != -7)			/* long */
+    abort ();
+
+  if (a8.ul[0] != +8)			/* unsigned long */
+    abort ();
+
+  if (a9.sll[0] != -9)			/* long long */
+    abort ();
+
+  if (a10.ull[0] != +10)		/* unsigned long long */
+    abort ();
+
+  if (a11.f[0] != -11.0f)		/* float */
+    abort ();
+
+  if (a12.d[0] != +12.0)		/* double */
+    abort ();
+
+  if (a13.si[0] != -13)			/* int */
+    abort ();
+
+  if (a14.si[0] != +14)			/* int */
+    abort ();
+
+  if (a15.si[0] != -15)			/* int */
+    abort ();
+
+  if (a16.si[0] != +16)			/* int */
+    abort ();
+
+  if (a17.si[0] != -17)			/* int */
+    abort ();
+
+  if (a18.si[0] != +18)			/* int */
+    abort ();
+
+  if (a19.si[0] != -19)			/* int */
+    abort ();
+
+  if (a20.si[0] != +20)			/* int */
+    abort ();
+
+  if (a21.si[0] != -21)			/* int */
+    abort ();
+
+  if (a22.si[0] != +22)			/* int */
+    abort ();
+
+  if (a23.si[0] != -23)			/* int */
+    abort ();
+
+  if (a24.si[0] != +24)			/* int */
+    abort ();
+
+  if (a25.si[0] != -25)			/* int */
+    abort ();
+
+  if (a26.si[0] != +26)			/* int */
+    abort ();
+
+  if (a27.si[0] != -27)			/* int */
+    abort ();
+
+  if (a28.si[0] != +28)			/* int */
+    abort ();
+
+  if (a29.si[0] != -29)			/* int */
+    abort ();
+
+  if (a30.si[0] != +30)			/* int */
+    abort ();
+
+  if (a31.si[0] != -31)			/* int */
+    abort ();
+
+  if (a32.si[0] != +32)			/* int */
+    abort ();
+
+  if (a33.si[0] != -33)			/* int */
+    abort ();
+
+  if (a34.si[0] != +34)			/* int */
+    abort ();
+
+  if (a35.si[0] != -35)			/* int */
+    abort ();
+
+  if (a36.si[0] != +36)			/* int */
+    abort ();
+
+  if (a37.si[0] != -37)			/* int */
+    abort ();
+
+  if (a38.si[0] != +38)			/* int */
+    abort ();
+
+  if (a39.si[0] != -39)			/* int */
+    abort ();
+
+  if (a40.si[0] != +40)			/* int */
+    abort ();
+
+  if (a41.si[0] != -41)			/* int */
+    abort ();
+
+  if (a42.si[0] != +42)			/* int */
+    abort ();
+
+  if (a43.si[0] != -43)			/* int */
+    abort ();
+
+  if (a44.si[0] != +44)			/* int */
+    abort ();
+
+  if (a45.si[0] != -45)			/* int */
+    abort ();
+
+  if (a46.si[0] != +46)			/* int */
+    abort ();
+
+  if (a47.si[0] != -47)			/* int */
+    abort ();
+
+  if (a48.si[0] != +48)			/* int */
+    abort ();
+
+  if (a49.si[0] != -49)			/* int */
+    abort ();
+
+  if (a50.si[0] != +50)			/* int */
+    abort ();
+
+  if (a51.si[0] != -51)			/* int */
+    abort ();
+
+  if (a52.si[0] != +52)			/* int */
+    abort ();
+
+  if (a53.si[0] != -53)			/* int */
+    abort ();
+
+  if (a54.si[0] != +54)			/* int */
+    abort ();
+
+  if (a55.si[0] != -55)			/* int */
+    abort ();
+
+  if (a56.si[0] != +56)			/* int */
+    abort ();
+
+  if (a57.si[0] != -57)			/* int */
+    abort ();
+
+  if (a58.si[0] != +58)			/* int */
+    abort ();
+
+  if (a59.si[0] != -59)			/* int */
+    abort ();
+
+  if (a60.si[0] != +60)			/* int */
+    abort ();
+
+  if (a61.si[0] != -61)			/* int */
+    abort ();
+
+  if (a62.si[0] != +62)			/* int */
+    abort ();
+
+  if (a63.si[0] != -63)			/* int */
+    abort ();
+
+  if (a64.si[0] != +64)			/* int */
+    abort ();
+
+  if (a65.si[0] != -65)			/* int */
+    abort ();
+
+  if (a66.si[0] != +66)			/* int */
+    abort ();
+
+  if (a67.si[0] != -67)			/* int */
+    abort ();
+
+  if (a68.si[0] != +68)			/* int */
+    abort ();
+
+  if (a69.si[0] != -69)			/* int */
+    abort ();
+
+  if (a70.si[0] != +70)			/* int */
+    abort ();
+
+  if (a71.si[0] != -71)			/* int */
+    abort ();
+
+  if (a72.si[0] != +72)			/* int */
+    abort ();
+
+  /* arguments passed on the stack */
+  if (a73.sc[3] != -73)			/* signed char */
+    abort ();
+
+  if (a74.uc[3] != 74)			/* unsigned char */
+    abort ();
+
+  if (a75.ss[1] != -75)			/* short */
+    abort ();
+
+  if (a76.us[1] != +76)			/* unsigned short */
+    abort ();
+
+  if (a77.si[0] != -77)			/* int */
+    abort ();
+
+  if (a78.ui[0] != +78)			/* unsigned int */
+    abort ();
+
+  if (a79.sl[0] != -79)			/* long */
+    abort ();
+
+  if (a80.ul[0] != +80)			/* unsigned long */
+    abort ();
+
+  if (a81.sll[0] != -81)		/* long long */
+    abort ();
+
+  if (a82.ull[0] != +82)		/* unsigned long long */
+    abort ();
+
+  if (a83.f[0] != -83.0f)		/* float */
+    abort ();
+
+  if (a84.d[0] != +84.0)		/* double */
+    abort ();
+}
+
+int main(void)
+{
+  func_asm(-1,   +2,  -3,  +4,  -5,  +6,  -7,  +8,  -9, +10,
+	   -11, +12, -13, +14, -15, +16, -17, +18, -19, +20,
+	   -21, +22, -23, +24, -25, +26, -27, +28, -29, +30,
+	   -31, +32, -33, +34, -35, +36, -37, +38, -39, +40,
+	   -41, +42, -43, +44, -45, +46, -47, +48, -49, +50,
+	   -51, +52, -53, +54, -55, +56, -57, +58, -59, +60,
+	   -61, +62, -63, +64, -65, +66, -67, +68, -69, +70,
+	   -71, +72, -73, +74, -75, +76, -77, +78, -79, +80,
+	   -81, +82, -83, +84);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/compare-dp.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/compare-dp.c
new file mode 100644
index 000000000..cbc7663b9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/compare-dp.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler-not "__eqdf2" } } */
+
+/* Ensure double precision comparisons are always inlined.  */
+
+int test (double a, double b) __attribute__((noinline));
+int test (double a, double b)
+{
+  return a == b;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/cpat-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/cpat-1.c
new file mode 100644
index 000000000..6fe292562
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/cpat-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -w" } */
+/* { dg-final { scan-assembler-times "lqr\t.3,.LC" 4 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,1\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,2\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,3\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,4\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,5\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,6\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,7\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,8\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,9\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,10\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,11\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,12\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,13\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,14\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,15\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,2\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,4\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,6\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,8\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,10\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,12\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,14\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cwd\t.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cwd\t.3,4\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cwd\t.3,8\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cwd\t.3,12\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cdd\t.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cdd\t.3,8\\(.sp\\)" 1 } } */
+
+__vector unsigned char
+not_cpat0()
+{
+  /* Contains no runs */
+  return (__vector unsigned char) {
+	    0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+	    0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F};
+}
+
+__vector unsigned char
+not_cpat1()
+{
+  /* Includes 1 run but not in the right place. */
+  return (__vector unsigned char) {
+	    0x10, 0x02, 0x03, 0x13, 0x14, 0x15, 0x16, 0x17,
+	    0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F};
+}
+
+__vector unsigned char
+not_cpat2()
+{
+  /* Includes 2 runs. */
+  return (__vector unsigned char) {
+	    0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+	    0x00, 0x01, 0x02, 0x03, 0x00, 0x01, 0x02, 0x03};
+}
+
+__vector unsigned char
+not_cpat3()
+{
+  /* Includes 1 incorrect run. */
+  return (__vector unsigned char) {
+	    0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+	    0x00, 0x01, 0x02, 0x03, 0x05, 0x06, 0x07, 0x1F};
+}
+
+__vector unsigned char cbd_0() { return (__vector unsigned char) { 0x03, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_1() { return (__vector unsigned char) { 0x10, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_2() { return (__vector unsigned char) { 0x10, 0x11, 0x03, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_3() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_4() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x03, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_5() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_6() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x03, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_7() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_8() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x03, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_9() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_a() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x03, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_b() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x03, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_c() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x03, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_d() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x03, 0x1E, 0x1F}; }
+__vector unsigned char cbd_e() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x03, 0x1F}; }
+__vector unsigned char cbd_f() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x03}; }
+
+__vector unsigned char chd_0() { return (__vector unsigned char) { 0x02, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char chd_2() { return (__vector unsigned char) { 0x10, 0x11, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char chd_4() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x02, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char chd_6() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char chd_8() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x02, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char chd_a() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char chd_c() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x02, 0x03, 0x1E, 0x1F}; }
+__vector unsigned char chd_e() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x02, 0x03}; }
+
+__vector unsigned char cwd_0() { return (__vector unsigned char) { 0x00, 0x01, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cwd_4() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x00, 0x01, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cwd_8() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cwd_c() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x00, 0x01, 0x02, 0x03}; }
+
+__vector unsigned char cdd_0() { return (__vector unsigned char) { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cdd_8() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07}; }
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/cpat-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/cpat-2.c
new file mode 100644
index 000000000..d5f86ed30
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/cpat-2.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -w" } */
+/* { dg-final { scan-assembler-times "cbd	.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,1\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,2\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,3\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,15\\(.sp\\)" 22 } } */
+/* { dg-final { scan-assembler-times "chd	.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd	.3,2\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "ila	.3,66051" 2 } } */
+
+#define MAKE_UINT(a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,aA,aB,aC,aD,aE,aF) ((unsigned int)(a0 << 24 | a1 << 16 | a2 << 8 | a3))
+
+unsigned int cbd_0() { return MAKE_UINT( 0x03, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_1() { return MAKE_UINT( 0x10, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_2() { return MAKE_UINT( 0x10, 0x11, 0x03, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_3() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_4() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x03, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_5() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_6() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x03, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_7() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_8() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x03, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_9() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_a() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x03, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_b() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_c() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x03, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_d() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x03, 0x1E, 0x1F); }
+unsigned int cbd_e() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x03, 0x1F); }
+unsigned int cbd_f() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x03); }
+unsigned int chd_0() { return MAKE_UINT( 0x02, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int chd_2() { return MAKE_UINT( 0x10, 0x11, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int chd_4() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x02, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int chd_6() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int chd_8() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x02, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int chd_a() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int chd_c() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x02, 0x03, 0x1E, 0x1F); }
+unsigned int chd_e() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x02, 0x03); }
+unsigned int cwd_0() { return MAKE_UINT( 0x00, 0x01, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cwd_4() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x00, 0x01, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cwd_8() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cwd_c() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x00, 0x01, 0x02, 0x03); }
+unsigned int cdd_0() { return MAKE_UINT( 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cdd_8() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); }
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/cpat-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/cpat-3.c
new file mode 100644
index 000000000..ced50111f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/cpat-3.c
@@ -0,0 +1,61 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -w" } */
+/* { dg-final { scan-assembler-times "cbd	.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,1\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,2\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,3\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,4\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,5\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,6\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,7\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,15\\(.sp\\)" 15 } } */
+/* { dg-final { scan-assembler-times "chd	.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd	.3,2\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd	.3,4\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd	.3,6\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cwd	.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cwd	.3,4\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cdd	.3,0\\(.sp\\)" 1 } } */
+
+#define MAKE_ULLONG(a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,aA,aB,aC,aD,aE,aF) \
+  ((unsigned long long) \
+    (a0##ull << 56 \
+     | a1##ull << 48 \
+     | a2##ull << 40 \
+     | a3##ull << 32\
+     | a4##ull << 24\
+     | a5##ull << 16 \
+     | a6##ull << 8 \
+     | a7##ull ))
+
+unsigned long long cbd_0() { return MAKE_ULLONG( 0x03, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_1() { return MAKE_ULLONG( 0x10, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_2() { return MAKE_ULLONG( 0x10, 0x11, 0x03, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_3() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_4() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x03, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_5() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_6() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x03, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_7() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_8() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x03, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_9() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_a() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x03, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_b() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_c() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x03, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_d() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x03, 0x1E, 0x1F); }
+unsigned long long cbd_e() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x03, 0x1F); }
+unsigned long long cbd_f() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x03); }
+unsigned long long chd_0() { return MAKE_ULLONG( 0x02, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long chd_2() { return MAKE_ULLONG( 0x10, 0x11, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long chd_4() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x02, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long chd_6() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long chd_8() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x02, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long chd_a() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long chd_c() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x02, 0x03, 0x1E, 0x1F); }
+unsigned long long chd_e() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x02, 0x03); }
+unsigned long long cwd_0() { return MAKE_ULLONG( 0x00, 0x01, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cwd_4() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x00, 0x01, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cwd_8() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cwd_c() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x00, 0x01, 0x02, 0x03); }
+unsigned long long cdd_0() { return MAKE_ULLONG( 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cdd_8() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); }
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/cpat-4.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/cpat-4.c
new file mode 100644
index 000000000..89110a66d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/cpat-4.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -w" } */
+/* { dg-final { scan-assembler-times "il\t.3,4611" 1 } } */
+/* { dg-final { scan-assembler-times "il\t.3,4627" 25 } } */
+/* { dg-final { scan-assembler-times "il\t.3,515" 3 } } */
+/* { dg-final { scan-assembler-times "il\t.3,787" 1 } } */
+
+#define MAKE_USHORT(a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,aA,aB,aC,aD,aE,aF) ((unsigned short)(a2 << 8 | a3))
+
+unsigned short cbd_0() { return MAKE_USHORT( 0x03, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_1() { return MAKE_USHORT( 0x10, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_2() { return MAKE_USHORT( 0x10, 0x11, 0x03, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_3() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_4() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x03, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_5() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_6() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x03, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_7() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_8() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x03, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_9() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_a() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x03, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_b() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_c() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x03, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_d() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x03, 0x1E, 0x1F); }
+unsigned short cbd_e() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x03, 0x1F); }
+unsigned short cbd_f() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x03); }
+unsigned short chd_0() { return MAKE_USHORT( 0x02, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short chd_2() { return MAKE_USHORT( 0x10, 0x11, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short chd_4() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x02, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short chd_6() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short chd_8() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x02, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short chd_a() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short chd_c() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x02, 0x03, 0x1E, 0x1F); }
+unsigned short chd_e() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x02, 0x03); }
+unsigned short cwd_0() { return MAKE_USHORT( 0x00, 0x01, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cwd_4() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x00, 0x01, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cwd_8() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cwd_c() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x00, 0x01, 0x02, 0x03); }
+unsigned short cdd_0() { return MAKE_USHORT( 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cdd_8() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); }
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/dfcgt-nan.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/dfcgt-nan.c
new file mode 100644
index 000000000..18ce01356
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/dfcgt-nan.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=celledp -O1" } */
+/* { dg-final { scan-assembler "dfceq" } } */
+
+/* GCC previously transformed an "a <= b" test into "! (a > b)" when
+   compiling with -march=celledp, so that the dfcgt instruction can be
+   used to implement the comparison.
+
+   However, this transformation violates the IEEE-754 standard in the
+   presence of NaN values.  If either a or b is a NaN, a <= b should
+   evaluate to false according to IEEE rules.  However, after the
+   transformation, a > b as implemented by dfcgt itself returns false,
+   so the transformed test returns true.
+
+   Note that the equivalent transformation is valid for single-
+   precision floating-point values on the Cell SPU, because the format
+   does not have NaNs.  It is invalid for double-precision, even on
+   Cell, however.  */
+
+int test (double a, double b) __attribute__ ((noinline));
+int test (double a, double b)
+{
+  return a <= b;
+}
+
+int main (void)
+{
+  double x = 0.0;
+  double y = 0.0/0.0;
+  return test (x, y);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/dfcmeq.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/dfcmeq.c
new file mode 100644
index 000000000..9286361b3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/dfcmeq.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=celledp -O1" } */
+/* { dg-final { scan-assembler "dfcmeq" } } */
+
+int foo(double x, double y)
+{
+  if (__builtin_fabs(x) == __builtin_fabs(y))
+    return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/dfcmgt.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/dfcmgt.c
new file mode 100644
index 000000000..ef7ef5899
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/dfcmgt.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=celledp -O1" } */
+/* { dg-final { scan-assembler "dfcmgt" } } */
+
+int foo(double x, double y)
+{
+  if (__builtin_fabs(x) > __builtin_fabs(y))
+    return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/fixed-range-bad.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/fixed-range-bad.c
new file mode 100644
index 000000000..099328378
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/fixed-range-bad.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-mfixed-range=1-x" } */
+/* { dg-warning "unknown register name" "" { target spu-*-* } 0 } */
+
+int i;
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/fixed-range.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/fixed-range.c
new file mode 100644
index 000000000..8dcb7fe4c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/fixed-range.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mfixed-range=1-20" } */
+/* { dg-final { scan-assembler "lqd.*21" } } */
+
+int foo (int i)
+{
+  return i;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/intrinsics-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/intrinsics-1.c
new file mode 100644
index 000000000..2720889f0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/intrinsics-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-std=c99 -pedantic-errors" } */
+#include <spu_intrinsics.h>
+/* With this intrinsics section, we used to ICE as we would try
+   to convert from an vector to an integer type.  */
+void f(void)
+{
+  vec_uint4 gt, N;
+  vec_int4 a;
+  int *a1;
+  _Complex double b;
+  gt = spu_cmpgt(a, N); /* { dg-error "parameter list" } */
+  gt = spu_cmpgt(a, a1); /* { dg-error "integer from pointer without a cast" } */
+  gt = spu_cmpgt(a, b); /* { dg-error "parameter list" } */
+  gt = spu_cmpgt(a, a);
+  a = spu_cmpgt(a, a); /* { dg-message "note: use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts" } */ 
+/* { dg-message "note: expected 'int'" "" { target *-*-* } 13 } */
+/* { dg-error "incompatible types when assigning" "" { target *-*-* } 16 } */
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/intrinsics-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/intrinsics-2.c
new file mode 100644
index 000000000..43a272b91
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/intrinsics-2.c
@@ -0,0 +1,305 @@
+/* { dg-do run } */
+/* { dg-options "-std=c99" } */
+#include <vec_types.h>
+extern void abort (void);
+extern void exit (int);
+
+typedef union {
+  vec_ullong2   vull;
+  vec_double2   vd;
+  unsigned int  ui[4];
+  unsigned long long ull[2];
+  double        d[2];
+} v128;
+
+static v128 a, b, c, d, a0, b0, a1, b1;
+static int samples = 10;
+unsigned int seed = 0;
+
+unsigned int rand_local()
+{
+  seed = seed * 69607 + 54329;
+  return (seed);
+}
+
+double rand_double(double min, double max)
+{
+  union {
+    unsigned int ui[2];
+    double d;
+  } x;
+
+  x.ui[0] = (rand_local() & 0x000FFFFF) | 0x3FF00000;
+  x.ui[1] = rand_local();
+  x.d -= 1.0;
+  x.d *= max - min;
+  x.d += min;
+  return (x.d);
+}
+
+vec_double2 rand_vd(double min, double max)
+{
+  int i;
+  static v128 val;
+
+  for (i=0; i<2; i++) val.d[i] = rand_double(min, max);
+  return (val.vd);
+}
+
+int test_spu_cmpeq()
+{
+  int i, j;
+  unsigned long long exp;
+
+  /* double */
+  for (i=0; i<samples; i++) {
+    a.vd = rand_vd(-4.0, 4.0);
+    b.vd = rand_vd(-4.0, 4.0);
+    d.vull = spu_cmpeq(a.vd, b.vd);
+    for (j=0; j<2; j++) {
+      exp = (a.d[j] == b.d[j]) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  }
+
+  /* compare zeros  */
+    d.vull = spu_cmpeq(a0.vd, b0.vd);
+    for (j=0; j<2; j++) {
+      exp = (a0.d[j] == b0.d[j]) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+
+  /* compare NaNs  */
+    d.vull = spu_cmpeq(a1.vd, b1.vd);
+    for (j=0; j<2; j++) {
+      exp = (a1.d[j] == b1.d[j]) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  return 0;
+}
+
+int test_spu_cmpgt()
+{   
+  int i, j;
+  unsigned long long exp;
+
+  /* double */
+  for (i=0; i<samples; i++) {
+    a.vd = rand_vd(-4.0, 4.0);
+    b.vd = rand_vd(-4.0, 4.0);
+    d.vull = spu_cmpgt(a.vd, b.vd);
+    for (j=0; j<2; j++) {
+      exp = (a.d[j] > b.d[j]) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    } 
+  }
+
+  /* compare zeros  */
+    d.vull = spu_cmpgt(a0.vd, b0.vd);
+    for (j=0; j<2; j++) {
+      exp = (a0.d[j] > b0.d[j]) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  /* compare NaNs  */
+    d.vull = spu_cmpgt(a1.vd, b1.vd);
+    for (j=0; j<2; j++) {
+      exp = (a1.d[j] > b1.d[j]) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  return 0;
+}
+
+int test_spu_cmpabseq()
+{   
+  int i, j;
+  unsigned long long exp;
+
+  /* double */
+  for (i=0; i<samples; i++) {
+    a.vd = rand_vd(-4.0, 4.0);
+    b.vd = rand_vd(-4.0, 4.0);
+    d.vull = spu_cmpabseq(a.vd, b.vd);
+    for (j=0; j<2; j++) {
+      exp = ((a.d[j] == b.d[j]) || (-a.d[j] == b.d[j]) || (a.d[j] == -b.d[j])) ?
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    } 
+  }
+
+  /* compare zeros  */
+    d.vull = spu_cmpabseq(a0.vd, b0.vd);
+    for (j=0; j<2; j++) {
+      exp = ((a0.d[j] == b0.d[j]) || (-a0.d[j] == b0.d[j]) || (a0.d[j] == -b0.d[j])) ?
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+
+  /* compare NaNs  */
+    d.vull = spu_cmpabseq(a1.vd, b1.vd);
+    for (j=0; j<2; j++) {
+      exp = ((a1.d[j] == b1.d[j]) || (-a1.d[j] == b1.d[j]) || (a1.d[j] == -b1.d[j])) ?
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  return 0;
+}
+
+int test_spu_cmpabsgt()
+{
+  int i, j;
+  unsigned long long exp;
+  double abs_a, abs_b;
+  
+  /* double */
+  for (i=0; i<samples; i++) {
+    a.vd = rand_vd(-4.0, 4.0);
+    b.vd = rand_vd(-4.0, 4.0);
+    d.vull = spu_cmpabsgt(a.vd, b.vd);
+    for (j=0; j<2; j++) {
+      double abs_a = (a.d[j] < 0.0) ? -a.d[j] : a.d[j];
+      double abs_b = (b.d[j] < 0.0) ? -b.d[j] : b.d[j];
+      exp = (abs_a > abs_b) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  }
+
+  /* compare zeros  */
+    d.vull = spu_cmpabsgt(a0.vd, b0.vd);
+    for (j=0; j<2; j++) {
+      abs_a = (a0.d[j] < 0.0) ? -a0.d[j] : a0.d[j];
+      abs_b = (b0.d[j] < 0.0) ? -b0.d[j] : b0.d[j];
+      exp = (abs_a > abs_b) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  /* compare NaNs  */
+    d.vull = spu_cmpabsgt(a1.vd, b1.vd);
+    for (j=0; j<2; j++) {
+      abs_a = (a1.d[j] < 0.0) ? -a1.d[j] : a1.d[j];
+      abs_b = (b1.d[j] < 0.0) ? -b1.d[j] : b1.d[j];
+      exp = (abs_a > abs_b) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  return 0;
+}
+
+int test_spu_testsv()
+{
+  int i, j;
+  unsigned long long exp;
+  struct _samples {
+    unsigned long long v;
+    unsigned int sv;
+ } samples[] = {
+  {0x0000000000000000ULL, SPU_SV_POS_ZERO},
+  {0x8000000000000000ULL, SPU_SV_NEG_ZERO},
+  {0x0000000000000001ULL, SPU_SV_POS_DENORM},
+  {0x0000000080000000ULL, SPU_SV_POS_DENORM},
+  {0x0000000100000000ULL, SPU_SV_POS_DENORM},
+  {0x0008000000000000ULL, SPU_SV_POS_DENORM},
+  {0x000FFFFFFFFFFFFFULL, SPU_SV_POS_DENORM},
+  {0x00000000FFF00000ULL, SPU_SV_POS_DENORM},
+  {0x8000000000000001ULL, SPU_SV_NEG_DENORM},
+  {0x8000000080000000ULL, SPU_SV_NEG_DENORM},
+  {0x8000000100000000ULL, SPU_SV_NEG_DENORM},
+  {0x8008000000000000ULL, SPU_SV_NEG_DENORM},
+  {0x800FFFFFFFFFFFFFULL, SPU_SV_NEG_DENORM},
+  {0x80000000FFF00000ULL, SPU_SV_NEG_DENORM},
+  {0x0010000000000000ULL, 0},
+  {0x0010000000000001ULL, 0},
+  {0x3FF0000000000000ULL, 0},
+  {0x3FF00000FFF00000ULL, 0},
+  {0xBFF0000000000000ULL, 0},
+  {0xBFF00000FFF00000ULL, 0},
+  {0x7FE0000000000000ULL, 0},
+  {0x7FEFFFFFFFFFFFFFULL, 0},
+  {0x8010000000000000ULL, 0},
+  {0x8010000000000001ULL, 0},
+  {0xFFE0000000000000ULL, 0},
+  {0xFFEFFFFFFFFFFFFFULL, 0},
+  {0x7FF0000000000000ULL, SPU_SV_POS_INFINITY},
+  {0xFFF0000000000000ULL, SPU_SV_NEG_INFINITY},
+  {0x7FF0000000000001ULL, SPU_SV_NAN},
+  {0x7FF0000080000000ULL, SPU_SV_NAN},
+  {0x7FF0000100000000ULL, SPU_SV_NAN},
+  {0x7FFFFFFFFFFFFFFFULL, SPU_SV_NAN},
+  {0xFFF0000000000001ULL, SPU_SV_NAN},
+  {0xFFF0000080000000ULL, SPU_SV_NAN},
+  {0xFFF0000100000000ULL, SPU_SV_NAN},
+  {0xFFFFFFFFFFFFFFFFULL, SPU_SV_NAN}
+ };
+
+  unsigned char cnt = sizeof(samples)/sizeof(struct _samples);
+  int e0;
+    for (e0=0; e0<cnt; e0++)
+    {   
+      a.ull[0] = samples[e0].v;
+      a.d[1] = rand_double(-1, -4);
+
+      d.vull = spu_testsv(a.vd, SPU_SV_NEG_DENORM);
+      exp = (SPU_SV_NEG_DENORM & samples[e0].sv) ? 0xFFFFFFFFFFFFFFFFULL : 0ULL;
+      if (exp != d.ull[0] || d.ull[1] != 0) abort();
+    
+      d.vull = spu_testsv(a.vd, SPU_SV_POS_DENORM);
+      exp = (SPU_SV_POS_DENORM & samples[e0].sv) ? 0xFFFFFFFFFFFFFFFFULL : 0ULL;
+      if (exp != d.ull[0] || d.ull[1] != 0) abort();
+    
+      d.vull = spu_testsv(a.vd, SPU_SV_NEG_ZERO);
+      exp = (SPU_SV_NEG_ZERO & samples[e0].sv) ? 0xFFFFFFFFFFFFFFFFULL : 0ULL;
+      if (exp != d.ull[0] || d.ull[1] != 0) abort();
+    
+      d.vull = spu_testsv(a.vd, SPU_SV_POS_ZERO);
+      exp = (SPU_SV_POS_ZERO & samples[e0].sv) ? 0xFFFFFFFFFFFFFFFFULL : 0ULL;
+      if (exp != d.ull[0] || d.ull[1] != 0) abort();
+    
+      d.vull = spu_testsv(a.vd, SPU_SV_NEG_INFINITY);
+      exp = (SPU_SV_NEG_INFINITY & samples[e0].sv) ? 0xFFFFFFFFFFFFFFFFULL : 0ULL;
+      if (exp != d.ull[0] || d.ull[1] != 0) abort();
+    
+      d.vull = spu_testsv(a.vd, SPU_SV_POS_INFINITY);
+      exp = (SPU_SV_POS_INFINITY & samples[e0].sv) ? 0xFFFFFFFFFFFFFFFFULL : 0ULL;
+      if (exp != d.ull[0] || d.ull[1] != 0) abort();
+    
+      d.vull = spu_testsv(a.vd, SPU_SV_NAN);
+      exp = (SPU_SV_NAN & samples[e0].sv) ? 0xFFFFFFFFFFFFFFFFULL : 0ULL;
+      if (exp != d.ull[0] || d.ull[1] != 0) abort();
+   }  
+  return 0;
+}
+
+int main()
+{
+  /* +0.0 and -0.0  */
+  a0.d[0] = 0.0; a0.d[1] = -0.0; b0.d[0] = -0.0; b0.d[1] = 0.0;
+  /* NaN  */
+  a1.d[0] = 0.0/0.0; a1.d[1] = 0.0/-0.0; b1.d[0] = -0.0/0.0;  b1.d[1] = -0.0/-0.0;
+
+  test_spu_cmpeq();
+  test_spu_cmpabseq();
+  test_spu_cmpgt();
+  test_spu_cmpabsgt();
+  test_spu_testsv();
+  return 0;
+}
+
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/intrinsics-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/intrinsics-3.c
new file mode 100644
index 000000000..db9832eb2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/intrinsics-3.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+#include <spu_intrinsics.h>
+void f0 (vec_uint4 *in)
+{
+  vec_float4 out = spu_convtf (in[0], 128); /* { dg-error "expects an integer literal in the range" "0, 127"  }*/
+}
+
+void f1 (vec_int4 *in)
+{
+  vec_float4 out = spu_convtf (in[0], 128); /* { dg-error "expects an integer literal in the range" "0, 127"  }*/
+}
+
+void f2 (vec_float4 *in)
+{
+  vec_int4 out = spu_convts (in[0], 128); /* { dg-error "expects an integer literal in the range" "0, 127"  }*/
+}
+
+void f3 (vec_float4 *in)
+{
+  vec_uint4 out = spu_convtu (in[0], 128); /* { dg-error "expects an integer literal in the range" "0, 127"  }*/
+}
+
+/* Test that these intrinsics accept non-literal arguments */
+void f4 (vec_uint4 *in, int n)
+{
+  vec_float4 out = spu_convtf (in[0], n);
+}
+
+void f5 (vec_int4 *in, int n)
+{
+  vec_float4 out = spu_convtf (in[0], n);
+}
+
+void f6 (vec_float4 *in, int n)
+{
+  vec_int4 out = spu_convts (in[0], n);
+}
+
+void f7 (vec_float4 *in, int n)
+{
+  vec_uint4 out = spu_convtu (in[0], n);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/intrinsics-sr.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/intrinsics-sr.c
new file mode 100644
index 000000000..f7c62ddcb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/intrinsics-sr.c
@@ -0,0 +1,496 @@
+/* { dg-do compile } */
+/* { dg-options "-std=c99" } */
+
+#include <spu_intrinsics.h>
+
+/* spu_sr */
+
+vector unsigned short test_sr_1 (vector unsigned short ra, vector unsigned short count)
+{
+  return spu_sr (ra, count);
+}
+
+vector signed short test_sr_2 (vector signed short ra, vector unsigned short count)
+{
+  return spu_sr (ra, count);
+}
+
+vector unsigned int test_sr_3 (vector unsigned int ra, vector unsigned int count)
+{
+  return spu_sr (ra, count);
+}
+
+vector signed int test_sr_4 (vector signed int ra, vector unsigned int count)
+{
+  return spu_sr (ra, count);
+}
+
+vector unsigned short test_sr_5 (vector unsigned short ra)
+{
+  return spu_sr (ra, 11);
+}
+
+vector signed short test_sr_6 (vector signed short ra)
+{
+  return spu_sr (ra, 11);
+}
+
+vector unsigned short test_sr_7 (vector unsigned short ra, unsigned int count)
+{
+  return spu_sr (ra, count);
+}
+
+vector signed short test_sr_8 (vector signed short ra, unsigned int count)
+{
+  return spu_sr (ra, count);
+}
+
+vector unsigned int test_sr_9 (vector unsigned int ra)
+{
+  return spu_sr (ra, 11);
+}
+
+vector signed int test_sr_10 (vector signed int ra)
+{
+  return spu_sr (ra, 11);
+}
+
+vector unsigned int test_sr_11 (vector unsigned int ra, unsigned int count)
+{
+  return spu_sr (ra, count);
+}
+
+vector signed int test_sr_12 (vector signed int ra, unsigned int count)
+{
+  return spu_sr (ra, count);
+}
+
+
+/* spu_sra */
+
+vector unsigned short test_sra_1 (vector unsigned short ra, vector unsigned short count)
+{
+  return spu_sra (ra, count);
+}
+
+vector signed short test_sra_2 (vector signed short ra, vector unsigned short count)
+{
+  return spu_sra (ra, count);
+}
+
+vector unsigned int test_sra_3 (vector unsigned int ra, vector unsigned int count)
+{
+  return spu_sra (ra, count);
+}
+
+vector signed int test_sra_4 (vector signed int ra, vector unsigned int count)
+{
+  return spu_sra (ra, count);
+}
+
+vector unsigned short test_sra_5 (vector unsigned short ra)
+{
+  return spu_sra (ra, 11);
+}
+
+vector signed short test_sra_6 (vector signed short ra)
+{
+  return spu_sra (ra, 11);
+}
+
+vector unsigned short test_sra_7 (vector unsigned short ra, unsigned int count)
+{
+  return spu_sra (ra, count);
+}
+
+vector signed short test_sra_8 (vector signed short ra, unsigned int count)
+{
+  return spu_sra (ra, count);
+}
+
+vector unsigned int test_sra_9 (vector unsigned int ra)
+{
+  return spu_sra (ra, 11);
+}
+
+vector signed int test_sra_10 (vector signed int ra)
+{
+  return spu_sra (ra, 11);
+}
+
+vector unsigned int test_sra_11 (vector unsigned int ra, unsigned int count)
+{
+  return spu_sra (ra, count);
+}
+
+vector signed int test_sra_12 (vector signed int ra, unsigned int count)
+{
+  return spu_sra (ra, count);
+}
+
+/* spu_srqw */
+
+vector unsigned char test_srqw_1 (vector unsigned char ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector signed char test_srqw_2 (vector signed char ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector unsigned short test_srqw_3 (vector unsigned short ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector signed short test_srqw_4 (vector signed short ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector unsigned int test_srqw_5 (vector unsigned int ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector signed int test_srqw_6 (vector signed int ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector unsigned long test_srqw_7 (vector unsigned long ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector signed long test_srqw_8 (vector signed long ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector unsigned long long test_srqw_9 (vector unsigned long long ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector signed long long test_srqw_10 (vector signed long long ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector float test_srqw_11 (vector float ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector double test_srqw_12 (vector double ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector unsigned char test_srqw_13 (vector unsigned char ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector signed char test_srqw_14 (vector signed char ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector unsigned short test_srqw_15 (vector unsigned short ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector signed short test_srqw_16 (vector signed short ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector unsigned int test_srqw_17 (vector unsigned int ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector signed int test_srqw_18 (vector signed int ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector unsigned long test_srqw_19 (vector unsigned long ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector signed long test_srqw_20 (vector signed long ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector unsigned long long test_srqw_21 (vector unsigned long long ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector signed long long test_srqw_22 (vector signed long long ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector float test_srqw_23 (vector float ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector double test_srqw_24 (vector double ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+/* spu_srqwbyte */
+
+vector unsigned char test_srqwbyte_1 (vector unsigned char ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector signed char test_srqwbyte_2 (vector signed char ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector unsigned short test_srqwbyte_3 (vector unsigned short ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector signed short test_srqwbyte_4 (vector signed short ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector unsigned int test_srqwbyte_5 (vector unsigned int ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector signed int test_srqwbyte_6 (vector signed int ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector unsigned long test_srqwbyte_7 (vector unsigned long ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector signed long test_srqwbyte_8 (vector signed long ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector unsigned long long test_srqwbyte_9 (vector unsigned long long ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector signed long long test_srqwbyte_10 (vector signed long long ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector float test_srqwbyte_11 (vector float ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector double test_srqwbyte_12 (vector double ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector unsigned char test_srqwbyte_13 (vector unsigned char ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector signed char test_srqwbyte_14 (vector signed char ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector unsigned short test_srqwbyte_15 (vector unsigned short ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector signed short test_srqwbyte_16 (vector signed short ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector unsigned int test_srqwbyte_17 (vector unsigned int ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector signed int test_srqwbyte_18 (vector signed int ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector unsigned long test_srqwbyte_19 (vector unsigned long ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector signed long test_srqwbyte_20 (vector signed long ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector unsigned long long test_srqwbyte_21 (vector unsigned long long ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector signed long long test_srqwbyte_22 (vector signed long long ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector float test_srqwbyte_23 (vector float ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector double test_srqwbyte_24 (vector double ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+/* spu_srqwbytebc */
+
+vector unsigned char test_srqwbytebc_1 (vector unsigned char ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector signed char test_srqwbytebc_2 (vector signed char ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector unsigned short test_srqwbytebc_3 (vector unsigned short ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector signed short test_srqwbytebc_4 (vector signed short ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector unsigned int test_srqwbytebc_5 (vector unsigned int ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector signed int test_srqwbytebc_6 (vector signed int ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector unsigned long test_srqwbytebc_7 (vector unsigned long ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector signed long test_srqwbytebc_8 (vector signed long ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector unsigned long long test_srqwbytebc_9 (vector unsigned long long ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector signed long long test_srqwbytebc_10 (vector signed long long ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector float test_srqwbytebc_11 (vector float ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector double test_srqwbytebc_12 (vector double ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector unsigned char test_srqwbytebc_13 (vector unsigned char ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector signed char test_srqwbytebc_14 (vector signed char ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector unsigned short test_srqwbytebc_15 (vector unsigned short ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector signed short test_srqwbytebc_16 (vector signed short ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector unsigned int test_srqwbytebc_17 (vector unsigned int ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector signed int test_srqwbytebc_18 (vector signed int ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector unsigned long test_srqwbytebc_19 (vector unsigned long ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector signed long test_srqwbytebc_20 (vector signed long ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector unsigned long long test_srqwbytebc_21 (vector unsigned long long ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector signed long long test_srqwbytebc_22 (vector signed long long ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector float test_srqwbytebc_23 (vector float ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector double test_srqwbytebc_24 (vector double ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/muldivti3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/muldivti3.c
new file mode 100644
index 000000000..0363e3420
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/muldivti3.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-std=c99" } */
+#include <stdlib.h>
+typedef unsigned int uqword __attribute__((mode(TI)));
+typedef int qword __attribute__((mode(TI)));
+
+typedef union
+{
+  uqword                uq;
+  qword                 q;
+  unsigned long long    ull[2];
+} u;
+
+int main(void)
+{
+  uqword e, f;
+  qword g, h;
+
+  e = 0x1111111111111111ULL;
+  f = 0xFULL;
+  g = 0x0000000000111100ULL;
+  h = 0x0000000000000000ULL;
+
+  u m, n, o, p, q;
+
+  m.ull[0] = f;
+  m.ull[1] = e;
+  n.ull[0] = h;
+  n.ull[1] = g;
+
+  /* __multi3  */
+  o.q = m.q * n.q;
+
+  o.q = o.q + n.q + 0x1110FF;
+  /* __udivti3, __umodti3  */
+  p.uq = o.uq / n.uq;
+  q.uq = o.uq % n.uq;
+  if (p.uq != (m.uq+1)) abort();
+  if (q.uq != 0x1110FF) abort();
+  /* __divti3, __modti3  */
+  p.q = -o.q / n.q;
+  q.q = -o.q % n.q;
+  if ((-p.q * n.q - q.q) != o.q) abort();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/spu.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/spu.exp
new file mode 100644
index 000000000..e0d76a7e5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/spu.exp
@@ -0,0 +1,41 @@
+#   Copyright (C) 2005, 2007 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the 'dg.exp' driver.
+
+# Exit immediately if this isn't a SPU target.
+if { ![istarget spu-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize 'dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/subti3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/subti3.c
new file mode 100644
index 000000000..4112c958c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/subti3.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-options "-std=c99" } */
+#include <stdlib.h>
+typedef int TItype __attribute__ ((mode (TI)));
+typedef int DItype __attribute__ ((mode (DI)));
+typedef unsigned int UDItype __attribute__ ((mode (DI)));
+
+struct DIstruct {DItype high, low;};
+typedef union
+{
+  struct DIstruct s;
+  TItype t;
+} TIunion;
+
+static
+void sub_ddmmss (UDItype *sh, UDItype *sl, UDItype ah, UDItype al, UDItype bh, UDItype bl)
+{
+  UDItype x;
+  x = al - bl;
+  *sh = ah - bh - (x > al);
+  *sl = x;
+}
+
+int main(void)
+{
+  TIunion aa, bb, cc;
+  TItype m = 0x1111111111111110ULL;
+  TItype n = 0x1111111111111111ULL;
+  TItype d;
+
+  aa.s.high = m;
+  aa.s.low = m;
+  bb.s.high = n;
+  bb.s.low = n;
+
+
+  sub_ddmmss (&cc.s.high, &cc.s.low, aa.s.high, aa.s.low, bb.s.high, bb.s.low);
+  d = aa.t - bb.t;
+  if (d != cc.t)
+   abort();
+  cc.t = aa.t -d;
+  if (cc.t != bb.t)
+   abort();
+ return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/tag_manager.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/tag_manager.c
new file mode 100644
index 000000000..4b3ab9f8d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/tag_manager.c
@@ -0,0 +1,312 @@
+/* Copyright (C) 2007, 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* { dg-do run } */
+
+#include <spu_mfcio.h>
+#include <stdlib.h>
+
+/* This test directly accesses the internal table used
+   by the MFC tag manager.  */
+extern vector unsigned int __mfc_tag_table;
+
+
+/* This tag tests invalid tag release.  Invalid tag release does
+   nothing to the tag table.  */
+void
+test_tag_release01 (void)
+{
+  unsigned int copy;
+  copy = spu_extract (__mfc_tag_table, 0);
+
+  mfc_tag_release (35);
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+}
+
+/* More invalid release tests.  */
+void
+test_tag_release_invalid (void)
+{
+  unsigned int copy;
+  copy = spu_extract (__mfc_tag_table, 0);
+
+  if (mfc_tag_release (32) != MFC_TAG_INVALID)
+    abort ();
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+
+  if (mfc_tag_release (17) != MFC_TAG_INVALID)
+    abort ();
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+}
+
+/* Invalid multiple-tag release tests.  */
+void
+test_tag_group_release_invalid (void)
+{
+  unsigned int copy;
+  copy = spu_extract (__mfc_tag_table, 0);
+
+  if (mfc_multi_tag_release (32, 10) != MFC_TAG_INVALID)
+    abort ();
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+
+  if (mfc_multi_tag_release (28, 10) != MFC_TAG_INVALID)
+    abort ();
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+
+  if (mfc_multi_tag_release (17, 10) != MFC_TAG_INVALID)
+    abort ();
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+
+  if (mfc_multi_tag_release (32, 10) != MFC_TAG_INVALID)
+    abort ();
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+}
+
+/* The tag table should be in a pristine mode to run this test.  */
+void
+test_tag_reserve01 (void)
+{
+  unsigned int correct_table[32] =
+    {
+		  0x80000000, 0xC0000000, 0xE0000000,
+      0xF0000000, 0xF8000000, 0xFC000000, 0xFE000000,
+      0xFF000000, 0xFF800000, 0xFFC00000, 0xFFE00000,
+      0xFFF00000, 0xFFF80000, 0xFFFC0000, 0xFFFE0000,
+      0xFFFF0000, 0xFFFF8000, 0xFFFFC000, 0xFFFFE000,
+      0xFFFFF000, 0xFFFFF800, 0xFFFFFC00, 0xFFFFFE00,
+      0xFFFFFF00, 0xFFFFFF80, 0xFFFFFFC0, 0xFFFFFFE0,
+      0xFFFFFFF0, 0xFFFFFFF8, 0xFFFFFFFC, 0xFFFFFFFE,
+      0xFFFFFFFF
+    };
+
+  unsigned int tag;
+  unsigned int i;
+
+  for (i = 0; i < 32; i++)
+    {
+      tag = mfc_tag_reserve ();
+      if (tag != i)
+	abort ();
+    }
+
+  for (i = 0; i < 32; i++)
+    {
+      tag = mfc_tag_reserve ();
+      if (tag != MFC_TAG_INVALID)
+	abort ();
+    }
+
+  for (i = 0; i < 32; i++)
+    {
+      mfc_tag_release (i);
+      if (spu_extract (__mfc_tag_table, 0) != correct_table[i])
+	abort ();
+    }
+}
+
+/* The tag table should be in a pristine mode to run this test.  */
+void
+test_tag_reserve02 (void)
+{
+  unsigned int correct_table[32] =
+    {
+      0x80000000, 0xC0000000, 0xA0000000, 0xF0000000,
+      0xA8000000, 0xFC000000, 0xAA000000, 0xFF000000,
+      0xAA800000, 0xFFC00000, 0xAAA00000, 0xFFF00000,
+      0xAAA80000, 0xFFFC0000, 0xAAAA0000, 0xFFFF0000,
+      0xAAAA8000, 0xFFFFC000, 0xAAAAA000, 0xFFFFF000,
+      0xAAAAA800, 0xFFFFFC00, 0xAAAAAA00, 0xFFFFFF00,
+      0xAAAAAA80, 0xFFFFFFC0, 0xAAAAAAA0, 0xFFFFFFF0,
+      0xAAAAAAA8, 0xFFFFFFFC, 0xAAAAAAAA, 0xFFFFFFFF
+    };
+
+  unsigned int correct_table2[32] =
+    {
+      0x80000000, 0xEAAAAAAA, 0xA0000000, 0xFAAAAAAA,
+      0xA8000000, 0xFEAAAAAA, 0xAA000000, 0xFFAAAAAA,
+      0xAA800000, 0xFFEAAAAA, 0xAAA00000, 0xFFFAAAAA,
+      0xAAA80000, 0xFFFEAAAA, 0xAAAA0000, 0xFFFFAAAA,
+      0xAAAA8000, 0xFFFFEAAA, 0xAAAAA000, 0xFFFFFAAA,
+      0xAAAAA800, 0xFFFFFEAA, 0xAAAAAA00, 0xFFFFFFAA,
+      0xAAAAAA80, 0xFFFFFFEA, 0xAAAAAAA0, 0xFFFFFFFA,
+      0xAAAAAAA8, 0xFFFFFFFE, 0xAAAAAAAA, 0xFFFFFFFF
+    };
+
+  unsigned int tag;
+  unsigned int i;
+
+  /* Reserve all 32 tags.  */
+  for (i = 0; i < 32; i++)
+    {
+      tag = mfc_tag_reserve();
+      if (tag != i)
+	abort ();
+    }
+
+  for (i = 0; i < 32; i++)
+    {
+      tag = mfc_tag_reserve();
+      if (tag != MFC_TAG_INVALID)
+	abort ();
+    }
+
+  /* Release only 16 tags with a stride of 2.  */
+  for (i = 0; i < 32; i += 2)
+    {
+      mfc_tag_release (i);
+      if (spu_extract (__mfc_tag_table, 0) != correct_table[i])
+	abort ();
+    }
+
+  /* Release the other 16 tags with a stride of 2.  */
+  for (i = 1; i < 32; i += 2)
+    {
+      mfc_tag_release (i);
+      if (spu_extract (__mfc_tag_table, 0) != correct_table2[i])
+	abort ();
+    }
+}
+
+/* The tag table should be in a pristine mode to run this test.  */
+void
+test_tag_reserve03 (void)
+{
+  unsigned int tag;
+  unsigned int i;
+
+  /* Reserve all 32 tags.  */
+  for (i = 0; i < 32; i++)
+    {
+      tag = mfc_tag_reserve ();
+      if (tag != i)
+	abort ();
+    }
+
+  for (i = 0; i < 32; i++)
+    {
+      tag = mfc_tag_reserve ();
+      if (tag != MFC_TAG_INVALID)
+	abort ();
+    }
+
+  /* Release only 16 tags with a stride of 2.  */
+  for (i = 0; i < 32; i += 2)
+    mfc_tag_release (i);
+
+  /* Now let's re-reserve those tags.  */
+  for (i = 0; i < 32; i += 2)
+    {
+      tag = mfc_tag_reserve ();
+      if (tag != i)
+	abort ();
+    }
+
+  /* Release all tags.  */
+  for (i = 0; i < 32; i++)
+    mfc_tag_release (i);
+
+  if (spu_extract (__mfc_tag_table,0) != 0xFFFFFFFF)
+    abort ();
+}
+
+
+void
+test_tag_group_reserve (void)
+{
+  unsigned int tag;
+  unsigned int i;
+  unsigned int copy;
+
+  /* Reserve all tags.  */
+  for (i = 0; i < 32; i++)
+    mfc_tag_reserve();
+
+  /* Release the first 4. */
+  for (i = 0; i < 4; i++)
+    mfc_tag_release (i);
+
+  /* Release tag 5 to 7.  */
+  for (i = 5; i < 8; i++)
+    mfc_tag_release (i);
+
+  /* Release tag 9 to 19.  */
+  for (i = 9; i < 20; i++)
+    mfc_tag_release (i);
+
+  /* Tag table should be 0xF77FF000.  */
+  if (spu_extract (__mfc_tag_table, 0) != 0xF77FF000)
+    abort ();
+
+
+  /* Verify invalid release is detected.  */
+  copy = spu_extract (__mfc_tag_table, 0);
+  if (mfc_multi_tag_release (1, 5) != MFC_TAG_INVALID)
+    abort ();
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+
+
+  /* Reserve multiple tags.  */
+  tag = mfc_multi_tag_reserve (5);
+  if (tag != 9)
+    abort ();
+
+  /* Tag table should be 0xF703F000.  */
+  if (spu_extract (__mfc_tag_table, 0) != 0xF703F000)
+    abort ();
+
+
+  /* Release 5 tags in the group.  */
+  mfc_multi_tag_release (tag, 5);
+
+  /* Tag table should be 0xF77FF000.  */
+  if (spu_extract (__mfc_tag_table, 0) != 0xF77FF000)
+    abort ();
+
+
+  /* This call should not do anything.  */
+  mfc_multi_tag_release (32, 5);
+
+  /* Tag table should be 0xF77FF000.  */
+  if (spu_extract (__mfc_tag_table, 0) != 0xF77FF000)
+    abort ();
+}
+
+
+int
+main (void)
+{
+  test_tag_release01 ();
+  test_tag_release_invalid ();
+  test_tag_group_release_invalid ();
+
+  test_tag_reserve01 ();
+  test_tag_reserve02 ();
+  test_tag_reserve03 ();
+
+  test_tag_group_reserve ();
+
+  return 0;
+}
+
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/vector-ansi.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/vector-ansi.c
new file mode 100644
index 000000000..3c0861699
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/vector-ansi.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-ansi" } */
+
+/* This is done by spu_internals.h, but we not include it here to keep
+   down the dependencies.  */
+
+#ifndef __VECTOR_KEYWORD_SUPPORTED__
+#define vector __vector
+#endif
+
+/* __vector is expanded unconditionally by the preprocessor.  */
+__vector int vi;
+__vector unsigned char vuc;
+__vector signed char vsc;
+__vector unsigned short vus;
+__vector signed short vss;
+__vector unsigned int vui;
+__vector signed int vsi;
+__vector unsigned long long ull;
+__vector signed long long sll;
+__vector float vf;
+__vector double vd;
+
+/* vector is expanded by the define above, regardless of context.  */
+vector int vi;
+vector unsigned char vuc;
+vector signed char vsc;
+vector unsigned short vus;
+vector signed short vss;
+vector unsigned int vui;
+vector signed int vsi;
+vector unsigned long long ull;
+vector signed long long sll;
+vector float vf;
+vector double vd;
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/spu/vector.c b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/vector.c
new file mode 100644
index 000000000..237f93b7e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/spu/vector.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+#ifndef __VECTOR_KEYWORD_SUPPORTED__
+#error __VECTOR_KEYWORD_SUPPORTED__ is not defined
+#endif
+
+/* __vector is expanded unconditionally.  */
+__vector int vi;
+__vector unsigned char vuc;
+__vector signed char vsc;
+__vector unsigned short vus;
+__vector signed short vss;
+__vector unsigned int vui;
+__vector signed int vsi;
+__vector unsigned long long ull;
+__vector signed long long sll;
+__vector float vf;
+__vector double vd;
+
+/* vector is expanded conditionally, based on the context.  */
+vector int vi;
+vector unsigned char vuc;
+vector signed char vsc;
+vector unsigned short vus;
+vector signed short vss;
+vector unsigned int vui;
+vector signed int vsi;
+vector unsigned long long ull;
+vector signed long long sll;
+vector float vf;
+vector double vd;
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/README.gcc b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/README.gcc
new file mode 100644
index 000000000..fca0dfe76
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/README.gcc
@@ -0,0 +1,18 @@
+This contains a testsuite for the AMD64 psABI.
+The ABI document is at http://www.x86-64.org/documentation/abi.pdf .
+The content of this directory in the GCC tree is just a (partial) copy of the
+ABI testsuite at cvs.x86-64.org.
+
+See http://www.x86-64.org/cvsaccess for accessing the anonymous CVS server.
+The module 'abitest' contains the master copy of this directory.
+
+The whole testsuite is licensed under GPL v2.
+
+Be aware that some of the test_*.c files here are generated, with the
+generators only being in the master copy of the testsuite.
+
+To change anything, please contact discuss@x86-64.org or the current
+maintainer of the testuite directly.
+
+The current maintainer is:
+  matz@suse.de
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/abi-x86_64.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/abi-x86_64.exp
new file mode 100644
index 000000000..521bd53ee
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/abi-x86_64.exp
@@ -0,0 +1,48 @@
+# Copyright (C) 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# The x86-64 ABI testsuite needs one additional assembler file for most
+# testcases.  For simplicity we will just link it into each test.
+
+load_lib c-torture.exp
+load_lib target-supports.exp
+load_lib torture-options.exp
+
+if { (![istarget x86_64-*-*] && ![istarget i?86-*-*])
+     || ![is-effective-target lp64] } then {
+  return
+}
+
+
+torture-init
+set-torture-options $C_TORTURE_OPTIONS
+set additional_flags "-W -Wall -Wno-abi"
+
+foreach src [lsort [glob -nocomplain $srcdir/$subdir/test_*.c]] {
+    if {[runtest_file_p $runtests $src]} {
+	if { ([istarget *-*-darwin*]) } then {
+	    c-torture-execute [list $src \
+				    $srcdir/$subdir/asm-support-darwin.s] \
+				    $additional_flags
+	} else {
+	    c-torture-execute [list $src \
+				    $srcdir/$subdir/asm-support.S] \
+				    $additional_flags
+	}
+    }
+}
+
+torture-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/args.h b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/args.h
new file mode 100644
index 000000000..99d7b76f8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/args.h
@@ -0,0 +1,186 @@
+#ifndef INCLUDED_ARGS_H
+#define INCLUDED_ARGS_H
+
+#include <string.h>
+
+/* This defines the calling sequences for integers and floats.  */
+#define I0 rdi
+#define I1 rsi
+#define I2 rdx
+#define I3 rcx
+#define I4 r8
+#define I5 r9
+#define F0 xmm0
+#define F1 xmm1
+#define F2 xmm2
+#define F3 xmm3
+#define F4 xmm4
+#define F5 xmm5
+#define F6 xmm6
+#define F7 xmm7
+
+typedef union {
+  float _float[4];
+  double _double[2];
+  long _long[2];
+  int _int[4];
+  unsigned long _ulong[2];
+#ifdef CHECK_M64_M128
+  __m64 _m64[2];
+  __m128 _m128[1];
+#endif
+} XMM_T;
+
+typedef union {
+  float _float;
+  double _double;
+  ldouble _ldouble;
+  ulong _ulong[2];
+} X87_T;
+extern void (*callthis)(void);
+extern unsigned long rax,rbx,rcx,rdx,rsi,rdi,rsp,rbp,r8,r9,r10,r11,r12,r13,r14,r15;
+XMM_T xmm_regs[16];
+X87_T x87_regs[8];
+extern volatile unsigned long volatile_var;
+extern void snapshot (void);
+extern void snapshot_ret (void);
+#define WRAP_CALL(N) \
+  (callthis = (void (*)()) (N), (typeof (&N)) snapshot)
+#define WRAP_RET(N) \
+  (callthis = (void (*)()) (N), (typeof (&N)) snapshot_ret)
+
+/* Clear all integer registers.  */
+#define clear_int_hardware_registers \
+  asm __volatile__ ("xor %%rax, %%rax\n\t" \
+		    "xor %%rbx, %%rbx\n\t" \
+		    "xor %%rcx, %%rcx\n\t" \
+		    "xor %%rdx, %%rdx\n\t" \
+		    "xor %%rsi, %%rsi\n\t" \
+		    "xor %%rdi, %%rdi\n\t" \
+		    "xor %%r8, %%r8\n\t" \
+		    "xor %%r9, %%r9\n\t" \
+		    "xor %%r10, %%r10\n\t" \
+		    "xor %%r11, %%r11\n\t" \
+		    "xor %%r12, %%r12\n\t" \
+		    "xor %%r13, %%r13\n\t" \
+		    "xor %%r14, %%r14\n\t" \
+		    "xor %%r15, %%r15\n\t" \
+		    ::: "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "r8", \
+		    "r9", "r10", "r11", "r12", "r13", "r14", "r15");
+
+/* This is the list of registers available for passing arguments. Not all of
+   these are used or even really available.  */
+struct IntegerRegisters
+{
+  unsigned long rax, rbx, rcx, rdx, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15;
+};
+struct FloatRegisters
+{
+  double mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7;
+  ldouble st0, st1, st2, st3, st4, st5, st6, st7;
+  XMM_T xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8, xmm9,
+        xmm10, xmm11, xmm12, xmm13, xmm14, xmm15;
+};
+
+/* Implemented in scalarargs.c  */
+extern struct IntegerRegisters iregs;
+extern struct FloatRegisters fregs;
+extern unsigned int num_iregs, num_fregs;
+
+#define check_int_arguments do { \
+  assert (num_iregs <= 0 || iregs.I0 == I0); \
+  assert (num_iregs <= 1 || iregs.I1 == I1); \
+  assert (num_iregs <= 2 || iregs.I2 == I2); \
+  assert (num_iregs <= 3 || iregs.I3 == I3); \
+  assert (num_iregs <= 4 || iregs.I4 == I4); \
+  assert (num_iregs <= 5 || iregs.I5 == I5); \
+  } while (0)
+
+#define check_char_arguments check_int_arguments
+#define check_short_arguments check_int_arguments
+#define check_long_arguments check_int_arguments
+
+/* Clear register struct.  */
+#define clear_struct_registers \
+  rax = rbx = rcx = rdx = rdi = rsi = rbp = rsp \
+    = r8 = r9 = r10 = r11 = r12 = r13 = r14 = r15 = 0; \
+  memset (&iregs, 0, sizeof (iregs)); \
+  memset (&fregs, 0, sizeof (fregs)); \
+  memset (xmm_regs, 0, sizeof (xmm_regs)); \
+  memset (x87_regs, 0, sizeof (x87_regs));
+
+/* Clear both hardware and register structs for integers.  */
+#define clear_int_registers \
+  clear_struct_registers \
+  clear_int_hardware_registers
+
+/* TODO: Do the checking.  */
+#define check_f_arguments(T) do { \
+  assert (num_fregs <= 0 || fregs.xmm0._ ## T [0] == xmm_regs[0]._ ## T [0]); \
+  assert (num_fregs <= 1 || fregs.xmm1._ ## T [0] == xmm_regs[1]._ ## T [0]); \
+  assert (num_fregs <= 2 || fregs.xmm2._ ## T [0] == xmm_regs[2]._ ## T [0]); \
+  assert (num_fregs <= 3 || fregs.xmm3._ ## T [0] == xmm_regs[3]._ ## T [0]); \
+  assert (num_fregs <= 4 || fregs.xmm4._ ## T [0] == xmm_regs[4]._ ## T [0]); \
+  assert (num_fregs <= 5 || fregs.xmm5._ ## T [0] == xmm_regs[5]._ ## T [0]); \
+  assert (num_fregs <= 6 || fregs.xmm6._ ## T [0] == xmm_regs[6]._ ## T [0]); \
+  assert (num_fregs <= 7 || fregs.xmm7._ ## T [0] == xmm_regs[7]._ ## T [0]); \
+  } while (0)
+
+#define check_float_arguments check_f_arguments(float)
+#define check_double_arguments check_f_arguments(double)
+
+#define check_vector_arguments(T,O) do { \
+  assert (num_fregs <= 0 \
+	  || memcmp (((char *) &fregs.xmm0) + (O), \
+		     &xmm_regs[0], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 1 \
+	  || memcmp (((char *) &fregs.xmm1) + (O), \
+		     &xmm_regs[1], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 2 \
+	  || memcmp (((char *) &fregs.xmm2) + (O), \
+		     &xmm_regs[2], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 3 \
+	  || memcmp (((char *) &fregs.xmm3) + (O), \
+		     &xmm_regs[3], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 4 \
+	  || memcmp (((char *) &fregs.xmm4) + (O), \
+		     &xmm_regs[4], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 5 \
+	  || memcmp (((char *) &fregs.xmm5) + (O), \
+		     &xmm_regs[5], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 6 \
+	  || memcmp (((char *) &fregs.xmm6) + (O), \
+		     &xmm_regs[6], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 7 \
+	  || memcmp (((char *) &fregs.xmm7) + (O), \
+		     &xmm_regs[7], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  } while (0)
+
+#define check_m64_arguments check_vector_arguments(m64, 0)
+#define check_m128_arguments check_vector_arguments(m128, 0)
+
+/* ldoubles are not passed in registers */
+#define check_ldouble_arguments
+
+/* TODO: Do the clearing.  */
+#define clear_float_hardware_registers
+#define clear_x87_hardware_registers
+
+#define clear_float_registers \
+  clear_struct_registers \
+  clear_float_hardware_registers
+
+#define clear_x87_registers \
+  clear_struct_registers \
+  clear_x87_hardware_registers
+
+
+#endif /* INCLUDED_ARGS_H  */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/asm-support-darwin.s b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/asm-support-darwin.s
new file mode 100644
index 000000000..5a7c91be6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/asm-support-darwin.s
@@ -0,0 +1,77 @@
+	.file	"snapshot.S"
+	.text
+	.p2align 4,,15
+.globl _snapshot
+_snapshot:
+.LFB3:
+	movq	%rax, _rax(%rip)
+	movq	%rbx, _rbx(%rip)
+	movq	%rcx, _rcx(%rip)
+	movq	%rdx, _rdx(%rip)
+	movq	%rdi, _rdi(%rip)
+	movq	%rsi, _rsi(%rip)
+	movq	%rbp, _rbp(%rip)
+	movq	%rsp, _rsp(%rip)
+	movq	%r8, _r8(%rip)
+	movq	%r9, _r9(%rip)
+	movq	%r10, _r10(%rip)
+	movq	%r11, _r11(%rip)
+	movq	%r12, _r12(%rip)
+	movq	%r13, _r13(%rip)
+	movq	%r14, _r14(%rip)
+	movq	%r15, _r15(%rip)
+	movdqu	%xmm0, _xmm_regs+0(%rip)
+	movdqu	%xmm1, _xmm_regs+16(%rip)
+	movdqu	%xmm2, _xmm_regs+16*2(%rip)
+	movdqu	%xmm3, _xmm_regs+16*3(%rip)
+	movdqu	%xmm4, _xmm_regs+16*4(%rip)
+	movdqu	%xmm5, _xmm_regs+16*5(%rip)
+	movdqu	%xmm6, _xmm_regs+16*6(%rip)
+	movdqu	%xmm7, _xmm_regs+16*7(%rip)
+	movdqu	%xmm8, _xmm_regs+16*8(%rip)
+	movdqu	%xmm9, _xmm_regs+16*9(%rip)
+	movdqu	%xmm10, _xmm_regs+16*10(%rip)
+	movdqu	%xmm11, _xmm_regs+16*11(%rip)
+	movdqu	%xmm12, _xmm_regs+16*12(%rip)
+	movdqu	%xmm13, _xmm_regs+16*13(%rip)
+	movdqu	%xmm14, _xmm_regs+16*14(%rip)
+	movdqu	%xmm15, _xmm_regs+16*15(%rip)
+	jmp	*_callthis(%rip)
+.LFE3:
+	.p2align 4,,15
+.globl _snapshot_ret
+_snapshot_ret:
+	movq	%rdi, _rdi(%rip)
+	subq	$8, %rsp
+	call	*_callthis(%rip)
+	addq	$8, %rsp
+	movq	%rax, _rax(%rip)
+	movq	%rdx, _rdx(%rip)
+	movdqu	%xmm0, _xmm_regs+0(%rip)
+	movdqu	%xmm1, _xmm_regs+16(%rip)
+	fstpt	_x87_regs(%rip)
+	fstpt	_x87_regs+16(%rip)
+	fldt	_x87_regs+16(%rip)
+	fldt	_x87_regs(%rip)
+	ret
+
+	.comm	_callthis,8
+	.comm	_rax,8
+	.comm	_rbx,8
+	.comm	_rcx,8
+	.comm	_rdx,8
+	.comm	_rsi,8
+	.comm	_rdi,8
+	.comm	_rsp,8
+	.comm	_rbp,8
+	.comm	_r8,8
+	.comm	_r9,8
+	.comm	_r10,8
+	.comm	_r11,8
+	.comm	_r12,8
+	.comm	_r13,8
+	.comm	_r14,8
+	.comm	_r15,8
+	.comm	_xmm_regs,256
+	.comm	_x87_regs,128
+	.comm   _volatile_var,8
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/asm-support.S b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/asm-support.S
new file mode 100644
index 000000000..cb1e31ea7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/asm-support.S
@@ -0,0 +1,85 @@
+	.file	"snapshot.S"
+#ifdef __AVX__
+	.sse_check none
+#endif
+	.text
+	.p2align 4,,15
+.globl snapshot
+	.type	snapshot, @function
+snapshot:
+.LFB3:
+	movq	%rax, rax(%rip)
+	movq	%rbx, rbx(%rip)
+	movq	%rcx, rcx(%rip)
+	movq	%rdx, rdx(%rip)
+	movq	%rdi, rdi(%rip)
+	movq	%rsi, rsi(%rip)
+	movq	%rbp, rbp(%rip)
+	movq	%rsp, rsp(%rip)
+	movq	%r8, r8(%rip)
+	movq	%r9, r9(%rip)
+	movq	%r10, r10(%rip)
+	movq	%r11, r11(%rip)
+	movq	%r12, r12(%rip)
+	movq	%r13, r13(%rip)
+	movq	%r14, r14(%rip)
+	movq	%r15, r15(%rip)
+	movdqu	%xmm0, xmm_regs+0(%rip)
+	movdqu	%xmm1, xmm_regs+16(%rip)
+	movdqu	%xmm2, xmm_regs+16*2(%rip)
+	movdqu	%xmm3, xmm_regs+16*3(%rip)
+	movdqu	%xmm4, xmm_regs+16*4(%rip)
+	movdqu	%xmm5, xmm_regs+16*5(%rip)
+	movdqu	%xmm6, xmm_regs+16*6(%rip)
+	movdqu	%xmm7, xmm_regs+16*7(%rip)
+	movdqu	%xmm8, xmm_regs+16*8(%rip)
+	movdqu	%xmm9, xmm_regs+16*9(%rip)
+	movdqu	%xmm10, xmm_regs+16*10(%rip)
+	movdqu	%xmm11, xmm_regs+16*11(%rip)
+	movdqu	%xmm12, xmm_regs+16*12(%rip)
+	movdqu	%xmm13, xmm_regs+16*13(%rip)
+	movdqu	%xmm14, xmm_regs+16*14(%rip)
+	movdqu	%xmm15, xmm_regs+16*15(%rip)
+	jmp	*callthis(%rip)
+.LFE3:
+	.size	snapshot, .-snapshot
+
+	.p2align 4,,15
+.globl snapshot_ret
+	.type	snapshot_ret, @function
+snapshot_ret:
+	movq	%rdi, rdi(%rip)
+	subq	$8, %rsp
+	call	*callthis(%rip)
+	addq	$8, %rsp
+	movq	%rax, rax(%rip)
+	movq	%rdx, rdx(%rip)
+	movdqu	%xmm0, xmm_regs+0(%rip)
+	movdqu	%xmm1, xmm_regs+16(%rip)
+	fstpt	x87_regs(%rip)
+	fstpt	x87_regs+16(%rip)
+	fldt	x87_regs+16(%rip)
+	fldt	x87_regs(%rip)
+	ret
+	.size	snapshot_ret, .-snapshot_ret
+
+	.comm	callthis,8,8
+	.comm	rax,8,8
+	.comm	rbx,8,8
+	.comm	rcx,8,8
+	.comm	rdx,8,8
+	.comm	rsi,8,8
+	.comm	rdi,8,8
+	.comm	rsp,8,8
+	.comm	rbp,8,8
+	.comm	r8,8,8
+	.comm	r9,8,8
+	.comm	r10,8,8
+	.comm	r11,8,8
+	.comm	r12,8,8
+	.comm	r13,8,8
+	.comm	r14,8,8
+	.comm	r15,8,8
+	.comm	xmm_regs,256,32
+	.comm	x87_regs,128,32
+	.comm   volatile_var,8,8
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/abi-avx.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/abi-avx.exp
new file mode 100644
index 000000000..e5561283d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/abi-avx.exp
@@ -0,0 +1,50 @@
+# Copyright (C) 2009 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# The x86-64 AVX ABI testsuite needs one additional assembler file for most
+# testcases.  For simplicity we will just link it into each test.
+
+load_lib c-torture.exp
+load_lib target-supports.exp
+load_lib torture-options.exp
+
+if { (![istarget x86_64-*-*] && ![istarget i?86-*-*])
+     || ![is-effective-target lp64]
+     || ![is-effective-target avx] } then {
+  return
+}
+
+
+torture-init
+set-torture-options $C_TORTURE_OPTIONS
+set additional_flags "-W -Wall -mavx"
+
+foreach src [lsort [glob -nocomplain $srcdir/$subdir/test_*.c]] {
+    if {[runtest_file_p $runtests $src]} {
+	if { ([istarget *-*-darwin*]) } then {
+	    # FIXME: Darwin isn't tested.
+	    c-torture-execute [list $src \
+				    $srcdir/$subdir/asm-support-darwin.s] \
+				    $additional_flags
+	} else {
+	    c-torture-execute [list $src \
+				    $srcdir/$subdir/asm-support.S] \
+				    $additional_flags
+	}
+    }
+}
+
+torture-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/args.h b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/args.h
new file mode 100644
index 000000000..5fa4a5e6c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/args.h
@@ -0,0 +1,180 @@
+#ifndef INCLUDED_ARGS_H
+#define INCLUDED_ARGS_H
+
+#include <immintrin.h>
+#include <string.h>
+
+/* Assertion macro.  */
+#define assert(test) if (!(test)) abort()
+
+#ifdef __GNUC__
+#define ATTRIBUTE_UNUSED __attribute__((__unused__))
+#else
+#define ATTRIBUTE_UNUSED
+#endif
+
+/* This defines the calling sequences for integers and floats.  */
+#define I0 rdi
+#define I1 rsi
+#define I2 rdx
+#define I3 rcx
+#define I4 r8
+#define I5 r9
+#define F0 ymm0
+#define F1 ymm1
+#define F2 ymm2
+#define F3 ymm3
+#define F4 ymm4
+#define F5 ymm5
+#define F6 ymm6
+#define F7 ymm7
+
+typedef union {
+  float _float[8];
+  double _double[4];
+  long _long[4];
+  int _int[8];
+  unsigned long _ulong[4];
+  __m64 _m64[4];
+  __m128 _m128[2];
+  __m256 _m256[1];
+} YMM_T;
+
+typedef union {
+  float _float;
+  double _double;
+  long double _ldouble;
+  unsigned long _ulong[2];
+} X87_T;
+extern void (*callthis)(void);
+extern unsigned long rax,rbx,rcx,rdx,rsi,rdi,rsp,rbp,r8,r9,r10,r11,r12,r13,r14,r15;
+YMM_T ymm_regs[16];
+X87_T x87_regs[8];
+extern volatile unsigned long volatile_var;
+extern void snapshot (void);
+extern void snapshot_ret (void);
+#define WRAP_CALL(N) \
+  (callthis = (void (*)()) (N), (typeof (&N)) snapshot)
+#define WRAP_RET(N) \
+  (callthis = (void (*)()) (N), (typeof (&N)) snapshot_ret)
+
+/* Clear all integer registers.  */
+#define clear_int_hardware_registers \
+  asm __volatile__ ("xor %%rax, %%rax\n\t" \
+		    "xor %%rbx, %%rbx\n\t" \
+		    "xor %%rcx, %%rcx\n\t" \
+		    "xor %%rdx, %%rdx\n\t" \
+		    "xor %%rsi, %%rsi\n\t" \
+		    "xor %%rdi, %%rdi\n\t" \
+		    "xor %%r8, %%r8\n\t" \
+		    "xor %%r9, %%r9\n\t" \
+		    "xor %%r10, %%r10\n\t" \
+		    "xor %%r11, %%r11\n\t" \
+		    "xor %%r12, %%r12\n\t" \
+		    "xor %%r13, %%r13\n\t" \
+		    "xor %%r14, %%r14\n\t" \
+		    "xor %%r15, %%r15\n\t" \
+		    ::: "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "r8", \
+		    "r9", "r10", "r11", "r12", "r13", "r14", "r15");
+
+/* This is the list of registers available for passing arguments. Not all of
+   these are used or even really available.  */
+struct IntegerRegisters
+{
+  unsigned long rax, rbx, rcx, rdx, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15;
+};
+struct FloatRegisters
+{
+  double mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7;
+  long double st0, st1, st2, st3, st4, st5, st6, st7;
+  YMM_T ymm0, ymm1, ymm2, ymm3, ymm4, ymm5, ymm6, ymm7, ymm8, ymm9,
+        ymm10, ymm11, ymm12, ymm13, ymm14, ymm15;
+};
+
+/* Implemented in scalarargs.c  */
+extern struct IntegerRegisters iregs;
+extern struct FloatRegisters fregs;
+extern unsigned int num_iregs, num_fregs;
+
+#define check_int_arguments do { \
+  assert (num_iregs <= 0 || iregs.I0 == I0); \
+  assert (num_iregs <= 1 || iregs.I1 == I1); \
+  assert (num_iregs <= 2 || iregs.I2 == I2); \
+  assert (num_iregs <= 3 || iregs.I3 == I3); \
+  assert (num_iregs <= 4 || iregs.I4 == I4); \
+  assert (num_iregs <= 5 || iregs.I5 == I5); \
+  } while (0)
+
+#define check_char_arguments check_int_arguments
+#define check_short_arguments check_int_arguments
+#define check_long_arguments check_int_arguments
+
+/* Clear register struct.  */
+#define clear_struct_registers \
+  rax = rbx = rcx = rdx = rdi = rsi = rbp = rsp \
+    = r8 = r9 = r10 = r11 = r12 = r13 = r14 = r15 = 0; \
+  memset (&iregs, 0, sizeof (iregs)); \
+  memset (&fregs, 0, sizeof (fregs)); \
+  memset (ymm_regs, 0, sizeof (ymm_regs)); \
+  memset (x87_regs, 0, sizeof (x87_regs));
+
+/* Clear both hardware and register structs for integers.  */
+#define clear_int_registers \
+  clear_struct_registers \
+  clear_int_hardware_registers
+
+/* TODO: Do the checking.  */
+#define check_f_arguments(T) do { \
+  assert (num_fregs <= 0 || fregs.ymm0._ ## T [0] == ymm_regs[0]._ ## T [0]); \
+  assert (num_fregs <= 1 || fregs.ymm1._ ## T [0] == ymm_regs[1]._ ## T [0]); \
+  assert (num_fregs <= 2 || fregs.ymm2._ ## T [0] == ymm_regs[2]._ ## T [0]); \
+  assert (num_fregs <= 3 || fregs.ymm3._ ## T [0] == ymm_regs[3]._ ## T [0]); \
+  assert (num_fregs <= 4 || fregs.ymm4._ ## T [0] == ymm_regs[4]._ ## T [0]); \
+  assert (num_fregs <= 5 || fregs.ymm5._ ## T [0] == ymm_regs[5]._ ## T [0]); \
+  assert (num_fregs <= 6 || fregs.ymm6._ ## T [0] == ymm_regs[6]._ ## T [0]); \
+  assert (num_fregs <= 7 || fregs.ymm7._ ## T [0] == ymm_regs[7]._ ## T [0]); \
+  } while (0)
+
+#define check_float_arguments check_f_arguments(float)
+#define check_double_arguments check_f_arguments(double)
+
+#define check_vector_arguments(T,O) do { \
+  assert (num_fregs <= 0 \
+	  || memcmp (((char *) &fregs.ymm0) + (O), \
+		     &ymm_regs[0], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 1 \
+	  || memcmp (((char *) &fregs.ymm1) + (O), \
+		     &ymm_regs[1], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 2 \
+	  || memcmp (((char *) &fregs.ymm2) + (O), \
+		     &ymm_regs[2], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 3 \
+	  || memcmp (((char *) &fregs.ymm3) + (O), \
+		     &ymm_regs[3], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 4 \
+	  || memcmp (((char *) &fregs.ymm4) + (O), \
+		     &ymm_regs[4], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 5 \
+	  || memcmp (((char *) &fregs.ymm5) + (O), \
+		     &ymm_regs[5], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 6 \
+	  || memcmp (((char *) &fregs.ymm6) + (O), \
+		     &ymm_regs[6], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 7 \
+	  || memcmp (((char *) &fregs.ymm7) + (O), \
+		     &ymm_regs[7], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  } while (0)
+
+#define check_m64_arguments check_vector_arguments(m64, 0)
+#define check_m128_arguments check_vector_arguments(m128, 0)
+#define check_m256_arguments check_vector_arguments(m256, 0)
+
+#endif /* INCLUDED_ARGS_H  */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/asm-support.S b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/asm-support.S
new file mode 100644
index 000000000..a4d002e19
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/asm-support.S
@@ -0,0 +1,82 @@
+	.file	"snapshot.S"
+	.text
+	.p2align 4,,15
+.globl snapshot
+	.type	snapshot, @function
+snapshot:
+.LFB3:
+	movq	%rax, rax(%rip)
+	movq	%rbx, rbx(%rip)
+	movq	%rcx, rcx(%rip)
+	movq	%rdx, rdx(%rip)
+	movq	%rdi, rdi(%rip)
+	movq	%rsi, rsi(%rip)
+	movq	%rbp, rbp(%rip)
+	movq	%rsp, rsp(%rip)
+	movq	%r8, r8(%rip)
+	movq	%r9, r9(%rip)
+	movq	%r10, r10(%rip)
+	movq	%r11, r11(%rip)
+	movq	%r12, r12(%rip)
+	movq	%r13, r13(%rip)
+	movq	%r14, r14(%rip)
+	movq	%r15, r15(%rip)
+	vmovdqu	%ymm0, ymm_regs+0(%rip)
+	vmovdqu	%ymm1, ymm_regs+32(%rip)
+	vmovdqu	%ymm2, ymm_regs+32*2(%rip)
+	vmovdqu	%ymm3, ymm_regs+32*3(%rip)
+	vmovdqu	%ymm4, ymm_regs+32*4(%rip)
+	vmovdqu	%ymm5, ymm_regs+32*5(%rip)
+	vmovdqu	%ymm6, ymm_regs+32*6(%rip)
+	vmovdqu	%ymm7, ymm_regs+32*7(%rip)
+	vmovdqu	%ymm8, ymm_regs+32*8(%rip)
+	vmovdqu	%ymm9, ymm_regs+32*9(%rip)
+	vmovdqu	%ymm10, ymm_regs+32*10(%rip)
+	vmovdqu	%ymm11, ymm_regs+32*11(%rip)
+	vmovdqu	%ymm12, ymm_regs+32*12(%rip)
+	vmovdqu	%ymm13, ymm_regs+32*13(%rip)
+	vmovdqu	%ymm14, ymm_regs+32*14(%rip)
+	vmovdqu	%ymm15, ymm_regs+32*15(%rip)
+	jmp	*callthis(%rip)
+.LFE3:
+	.size	snapshot, .-snapshot
+
+	.p2align 4,,15
+.globl snapshot_ret
+	.type	snapshot_ret, @function
+snapshot_ret:
+	movq	%rdi, rdi(%rip)
+	subq	$8, %rsp
+	call	*callthis(%rip)
+	addq	$8, %rsp
+	movq	%rax, rax(%rip)
+	movq	%rdx, rdx(%rip)
+	vmovdqu	%ymm0, ymm_regs+0(%rip)
+	vmovdqu	%ymm1, ymm_regs+32(%rip)
+	fstpt	x87_regs(%rip)
+	fstpt	x87_regs+16(%rip)
+	fldt	x87_regs+16(%rip)
+	fldt	x87_regs(%rip)
+	ret
+	.size	snapshot_ret, .-snapshot_ret
+
+	.comm	callthis,8,8
+	.comm	rax,8,8
+	.comm	rbx,8,8
+	.comm	rcx,8,8
+	.comm	rdx,8,8
+	.comm	rsi,8,8
+	.comm	rdi,8,8
+	.comm	rsp,8,8
+	.comm	rbp,8,8
+	.comm	r8,8,8
+	.comm	r9,8,8
+	.comm	r10,8,8
+	.comm	r11,8,8
+	.comm	r12,8,8
+	.comm	r13,8,8
+	.comm	r14,8,8
+	.comm	r15,8,8
+	.comm	ymm_regs,512,32
+	.comm	x87_regs,128,32
+	.comm   volatile_var,8,8
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/avx-check.h b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/avx-check.h
new file mode 100644
index 000000000..7f1f8f9fc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/avx-check.h
@@ -0,0 +1,28 @@
+#include <stdlib.h>
+#include "cpuid.h"
+
+static void avx_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run AVX test only if host has AVX support.  */
+  if (ecx & bit_AVX)
+    {
+      avx_test ();
+#ifdef DEBUG
+      printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/test_m256_returning.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/test_m256_returning.c
new file mode 100644
index 000000000..072d83962
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/test_m256_returning.c
@@ -0,0 +1,32 @@
+#include <stdio.h>
+#include "avx-check.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+__m256
+fun_test_returning___m256 (void)
+{
+  volatile_var++;
+  return (__m256){73,0,0,0,0,0,0,0};
+}
+
+__m256 test_256;
+
+static void
+avx_test (void)
+{
+  unsigned failed = 0;
+  YMM_T ymmt1, ymmt2;
+
+  clear_struct_registers;
+  test_256 = (__m256){73,0,0,0,0,0,0,0};
+  ymmt1._m256[0] = test_256;
+  ymmt2._m256[0] = WRAP_RET (fun_test_returning___m256)();
+  if (memcmp (&ymmt1, &ymmt2, sizeof (ymmt2)) != 0)
+    printf ("fail m256\n"), failed++;
+  if (failed)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_m256.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_m256.c
new file mode 100644
index 000000000..ffc3ec36b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_m256.c
@@ -0,0 +1,168 @@
+#include <stdio.h>
+#include "avx-check.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+/* This struct holds values for argument checking.  */
+struct 
+{
+  YMM_T i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23;
+} values;
+
+char *pass;
+int failed = 0;
+
+#undef assert
+#define assert(c) do { \
+  if (!(c)) {failed++; printf ("failed %s\n", pass); } \
+} while (0)
+
+#define compare(X1,X2,T) do { \
+  assert (memcmp (&X1, &X2, sizeof (T)) == 0); \
+} while (0)
+
+fun_check_passing_m256_8_values (__m256 i0 ATTRIBUTE_UNUSED, __m256 i1 ATTRIBUTE_UNUSED, __m256 i2 ATTRIBUTE_UNUSED, __m256 i3 ATTRIBUTE_UNUSED, __m256 i4 ATTRIBUTE_UNUSED, __m256 i5 ATTRIBUTE_UNUSED, __m256 i6 ATTRIBUTE_UNUSED, __m256 i7 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  compare (values.i0, i0, __m256);
+  compare (values.i1, i1, __m256);
+  compare (values.i2, i2, __m256);
+  compare (values.i3, i3, __m256);
+  compare (values.i4, i4, __m256);
+  compare (values.i5, i5, __m256);
+  compare (values.i6, i6, __m256);
+  compare (values.i7, i7, __m256);
+}
+
+void
+fun_check_passing_m256_8_regs (__m256 i0 ATTRIBUTE_UNUSED, __m256 i1 ATTRIBUTE_UNUSED, __m256 i2 ATTRIBUTE_UNUSED, __m256 i3 ATTRIBUTE_UNUSED, __m256 i4 ATTRIBUTE_UNUSED, __m256 i5 ATTRIBUTE_UNUSED, __m256 i6 ATTRIBUTE_UNUSED, __m256 i7 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m256_arguments;
+}
+
+void
+fun_check_passing_m256_20_values (__m256 i0 ATTRIBUTE_UNUSED, __m256 i1 ATTRIBUTE_UNUSED, __m256 i2 ATTRIBUTE_UNUSED, __m256 i3 ATTRIBUTE_UNUSED, __m256 i4 ATTRIBUTE_UNUSED, __m256 i5 ATTRIBUTE_UNUSED, __m256 i6 ATTRIBUTE_UNUSED, __m256 i7 ATTRIBUTE_UNUSED, __m256 i8 ATTRIBUTE_UNUSED, __m256 i9 ATTRIBUTE_UNUSED, __m256 i10 ATTRIBUTE_UNUSED, __m256 i11 ATTRIBUTE_UNUSED, __m256 i12 ATTRIBUTE_UNUSED, __m256 i13 ATTRIBUTE_UNUSED, __m256 i14 ATTRIBUTE_UNUSED, __m256 i15 ATTRIBUTE_UNUSED, __m256 i16 ATTRIBUTE_UNUSED, __m256 i17 ATTRIBUTE_UNUSED, __m256 i18 ATTRIBUTE_UNUSED, __m256 i19 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  compare (values.i0, i0, __m256);
+  compare (values.i1, i1, __m256);
+  compare (values.i2, i2, __m256);
+  compare (values.i3, i3, __m256);
+  compare (values.i4, i4, __m256);
+  compare (values.i5, i5, __m256);
+  compare (values.i6, i6, __m256);
+  compare (values.i7, i7, __m256);
+  compare (values.i8, i8, __m256);
+  compare (values.i9, i9, __m256);
+  compare (values.i10, i10, __m256);
+  compare (values.i11, i11, __m256);
+  compare (values.i12, i12, __m256);
+  compare (values.i13, i13, __m256);
+  compare (values.i14, i14, __m256);
+  compare (values.i15, i15, __m256);
+  compare (values.i16, i16, __m256);
+  compare (values.i17, i17, __m256);
+  compare (values.i18, i18, __m256);
+  compare (values.i19, i19, __m256);
+}
+
+void
+fun_check_passing_m256_20_regs (__m256 i0 ATTRIBUTE_UNUSED, __m256 i1 ATTRIBUTE_UNUSED, __m256 i2 ATTRIBUTE_UNUSED, __m256 i3 ATTRIBUTE_UNUSED, __m256 i4 ATTRIBUTE_UNUSED, __m256 i5 ATTRIBUTE_UNUSED, __m256 i6 ATTRIBUTE_UNUSED, __m256 i7 ATTRIBUTE_UNUSED, __m256 i8 ATTRIBUTE_UNUSED, __m256 i9 ATTRIBUTE_UNUSED, __m256 i10 ATTRIBUTE_UNUSED, __m256 i11 ATTRIBUTE_UNUSED, __m256 i12 ATTRIBUTE_UNUSED, __m256 i13 ATTRIBUTE_UNUSED, __m256 i14 ATTRIBUTE_UNUSED, __m256 i15 ATTRIBUTE_UNUSED, __m256 i16 ATTRIBUTE_UNUSED, __m256 i17 ATTRIBUTE_UNUSED, __m256 i18 ATTRIBUTE_UNUSED, __m256 i19 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m256_arguments;
+}
+
+
+#define def_check_passing8(_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _func1, _func2, TYPE) \
+  values.i0.TYPE[0] = _i0; \
+  values.i1.TYPE[0] = _i1; \
+  values.i2.TYPE[0] = _i2; \
+  values.i3.TYPE[0] = _i3; \
+  values.i4.TYPE[0] = _i4; \
+  values.i5.TYPE[0] = _i5; \
+  values.i6.TYPE[0] = _i6; \
+  values.i7.TYPE[0] = _i7; \
+  WRAP_CALL(_func1) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7); \
+  \
+  clear_struct_registers; \
+  fregs.F0.TYPE[0] = _i0; \
+  fregs.F1.TYPE[0] = _i1; \
+  fregs.F2.TYPE[0] = _i2; \
+  fregs.F3.TYPE[0] = _i3; \
+  fregs.F4.TYPE[0] = _i4; \
+  fregs.F5.TYPE[0] = _i5; \
+  fregs.F6.TYPE[0] = _i6; \
+  fregs.F7.TYPE[0] = _i7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7);
+
+#define def_check_passing20(_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _i12, _i13, _i14, _i15, _i16, _i17, _i18, _i19, _func1, _func2, TYPE) \
+  values.i0.TYPE[0] = _i0; \
+  values.i1.TYPE[0] = _i1; \
+  values.i2.TYPE[0] = _i2; \
+  values.i3.TYPE[0] = _i3; \
+  values.i4.TYPE[0] = _i4; \
+  values.i5.TYPE[0] = _i5; \
+  values.i6.TYPE[0] = _i6; \
+  values.i7.TYPE[0] = _i7; \
+  values.i8.TYPE[0] = _i8; \
+  values.i9.TYPE[0] = _i9; \
+  values.i10.TYPE[0] = _i10; \
+  values.i11.TYPE[0] = _i11; \
+  values.i12.TYPE[0] = _i12; \
+  values.i13.TYPE[0] = _i13; \
+  values.i14.TYPE[0] = _i14; \
+  values.i15.TYPE[0] = _i15; \
+  values.i16.TYPE[0] = _i16; \
+  values.i17.TYPE[0] = _i17; \
+  values.i18.TYPE[0] = _i18; \
+  values.i19.TYPE[0] = _i19; \
+  WRAP_CALL(_func1) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _i12, _i13, _i14, _i15, _i16, _i17, _i18, _i19); \
+  \
+  clear_struct_registers; \
+  fregs.F0.TYPE[0] = _i0; \
+  fregs.F1.TYPE[0] = _i1; \
+  fregs.F2.TYPE[0] = _i2; \
+  fregs.F3.TYPE[0] = _i3; \
+  fregs.F4.TYPE[0] = _i4; \
+  fregs.F5.TYPE[0] = _i5; \
+  fregs.F6.TYPE[0] = _i6; \
+  fregs.F7.TYPE[0] = _i7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _i12, _i13, _i14, _i15, _i16, _i17, _i18, _i19);
+
+void
+test_m256_on_stack ()
+{
+  __m256 x[8];
+  int i;
+  for (i = 0; i < 8; i++)
+    x[i] = (__m256){32+i, 0, 0, 0, 0, 0, 0, 0};
+  pass = "m256-8";
+  def_check_passing8(x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], fun_check_passing_m256_8_values, fun_check_passing_m256_8_regs, _m256);
+}
+
+void
+test_too_many_m256 ()
+{
+  __m256 x[20];
+  int i;
+  for (i = 0; i < 20; i++)
+    x[i] = (__m256){32+i, 0, 0, 0, 0, 0, 0, 0};
+  pass = "m256-20";
+  def_check_passing20(x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], x[8], x[9], x[10], x[11], x[12], x[13], x[14], x[15], x[16], x[17], x[18], x[19], fun_check_passing_m256_20_values, fun_check_passing_m256_20_regs, _m256);
+}
+
+static void
+avx_test (void)
+{
+  test_m256_on_stack ();
+  test_too_many_m256 ();
+  if (failed)
+    abort ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_structs.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_structs.c
new file mode 100644
index 000000000..9a8f71dbb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_structs.c
@@ -0,0 +1,61 @@
+#include "avx-check.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+struct m256_struct
+{
+  __m256 x;
+};
+
+struct m256_2_struct
+{
+  __m256 x1, x2;
+};
+
+/* Check that the struct is passed as the individual members in fregs.  */
+void
+check_struct_passing1 (struct m256_struct ms1 ATTRIBUTE_UNUSED,
+		       struct m256_struct ms2 ATTRIBUTE_UNUSED,
+		       struct m256_struct ms3 ATTRIBUTE_UNUSED,
+		       struct m256_struct ms4 ATTRIBUTE_UNUSED,
+		       struct m256_struct ms5 ATTRIBUTE_UNUSED,
+		       struct m256_struct ms6 ATTRIBUTE_UNUSED,
+		       struct m256_struct ms7 ATTRIBUTE_UNUSED,
+		       struct m256_struct ms8 ATTRIBUTE_UNUSED)
+{
+  check_m256_arguments;
+}
+
+void
+check_struct_passing2 (struct m256_2_struct ms ATTRIBUTE_UNUSED)
+{
+  /* Check the passing on the stack by comparing the address of the
+     stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&ms.x1 == rsp+8);
+  assert ((unsigned long)&ms.x2 == rsp+40);
+}
+
+static void
+avx_test (void)
+{
+  struct m256_struct m256s [8];
+  struct m256_2_struct m256_2s = { 
+      { 48.394, 39.3, -397.9, 3484.9, -8.394, -93.3, 7.9, 84.94 },
+      { -8.394, -3.3, -39.9, 34.9, 7.9, 84.94, -48.394, 39.3 }
+  };
+  int i;
+
+  for (i = 0; i < 8; i++)
+    m256s[i].x = (__m256){32+i, 0, i, 0, -i, 0, i - 12, i + 8};
+
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    fregs.ymm0._m256[i] = m256s[i].x;
+  num_fregs = 8;
+  WRAP_CALL (check_struct_passing1)(m256s[0], m256s[1], m256s[2], m256s[3],
+				    m256s[4], m256s[5], m256s[6], m256s[7]);
+  WRAP_CALL (check_struct_passing2)(m256_2s);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_unions.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_unions.c
new file mode 100644
index 000000000..f83209b27
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_unions.c
@@ -0,0 +1,143 @@
+#include "avx-check.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+union un1
+{
+  __m256 x;
+  float f;
+};
+
+union un2
+{
+  __m256 x;
+  double d;
+};
+
+union un3
+{
+  __m256 x;
+  __m128 v;
+};
+
+union un4
+{
+  __m256 x;
+  long double ld;
+};
+
+union un5
+{
+  __m256 x;
+  int i;
+};
+
+void
+check_union_passing1(union un1 u1 ATTRIBUTE_UNUSED,
+		     union un1 u2 ATTRIBUTE_UNUSED,
+		     union un1 u3 ATTRIBUTE_UNUSED,
+		     union un1 u4 ATTRIBUTE_UNUSED,
+		     union un1 u5 ATTRIBUTE_UNUSED,
+		     union un1 u6 ATTRIBUTE_UNUSED,
+		     union un1 u7 ATTRIBUTE_UNUSED,
+		     union un1 u8 ATTRIBUTE_UNUSED)
+{
+  check_m256_arguments;
+}
+
+void
+check_union_passing2(union un2 u1 ATTRIBUTE_UNUSED,
+		     union un2 u2 ATTRIBUTE_UNUSED,
+		     union un2 u3 ATTRIBUTE_UNUSED,
+		     union un2 u4 ATTRIBUTE_UNUSED,
+		     union un2 u5 ATTRIBUTE_UNUSED,
+		     union un2 u6 ATTRIBUTE_UNUSED,
+		     union un2 u7 ATTRIBUTE_UNUSED,
+		     union un2 u8 ATTRIBUTE_UNUSED)
+{
+  check_m256_arguments;
+}
+
+void
+check_union_passing3(union un3 u1 ATTRIBUTE_UNUSED,
+		     union un3 u2 ATTRIBUTE_UNUSED,
+		     union un3 u3 ATTRIBUTE_UNUSED,
+		     union un3 u4 ATTRIBUTE_UNUSED,
+		     union un3 u5 ATTRIBUTE_UNUSED,
+		     union un3 u6 ATTRIBUTE_UNUSED,
+		     union un3 u7 ATTRIBUTE_UNUSED,
+		     union un3 u8 ATTRIBUTE_UNUSED)
+{
+  check_m256_arguments;
+}
+
+void
+check_union_passing4(union un4 u ATTRIBUTE_UNUSED)
+{
+   /* Check the passing on the stack by comparing the address of the
+      stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&u.x == rsp+8);
+  assert ((unsigned long)&u.ld == rsp+8);
+}
+
+void
+check_union_passing5(union un5 u ATTRIBUTE_UNUSED)
+{
+   /* Check the passing on the stack by comparing the address of the
+      stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&u.x == rsp+8);
+  assert ((unsigned long)&u.i == rsp+8);
+}
+
+#define check_union_passing1 WRAP_CALL(check_union_passing1)
+#define check_union_passing2 WRAP_CALL(check_union_passing2)
+#define check_union_passing3 WRAP_CALL(check_union_passing3)
+#define check_union_passing4 WRAP_CALL(check_union_passing4)
+#define check_union_passing5 WRAP_CALL(check_union_passing5)
+
+static void
+avx_test (void)
+{
+  union un1 u1[8];
+  union un2 u2[8];
+  union un3 u3[8];
+  union un4 u4;
+  union un5 u5;
+  int i;
+
+  for (i = 0; i < 8; i++)
+    u1[i].x = (__m256){32+i, 0, i, 0, -i, 0, i - 12, i + 8};
+
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    fregs.ymm0._m256[i] = u1[i].x;
+  num_fregs = 8;
+  check_union_passing1(u1[0], u1[1], u1[2], u1[3],
+		       u1[4], u1[5], u1[6], u1[7]);
+
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    {
+      u2[i].x = u1[i].x;
+      fregs.ymm0._m256[i] = u2[i].x;
+    }
+  num_fregs = 8;
+  check_union_passing2(u2[0], u2[1], u2[2], u2[3],
+		       u2[4], u2[5], u2[6], u2[7]);
+
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    {
+      u3[i].x = u1[i].x;
+      fregs.ymm0._m256[i] = u3[i].x;
+    }
+  num_fregs = 8;
+  check_union_passing3(u3[0], u3[1], u3[2], u3[3],
+		       u3[4], u3[5], u3[6], u3[7]);
+
+  check_union_passing4(u4);
+  check_union_passing5(u5);
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/callabi.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/callabi.exp
new file mode 100644
index 000000000..e76d0c101
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/callabi.exp
@@ -0,0 +1,36 @@
+#   Copyright (C) 2009 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+if { (![istarget x86_64-*-*] && ![istarget i?86-*-*])
+     || [is-effective-target ilp32] } then {
+  return
+}
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+dg-init
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+    "" $DEFAULT_CFLAGS
+dg-finish
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/callabi.h b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/callabi.h
new file mode 100644
index 000000000..d008ad659
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/callabi.h
@@ -0,0 +1,50 @@
+/* First the default target definition.  */
+#ifndef __GNUC_VA_LIST
+#define __GNUC_VA_LIST
+  typedef __builtin_va_list __gnuc_va_list;
+#endif
+
+#ifndef _VA_LIST_DEFINED
+#define _VA_LIST_DEFINED
+  typedef __gnuc_va_list va_list;
+#endif
+
+#define __va_copy(d,s)	__builtin_va_copy(d,s)
+#define __va_start(v,l)	__builtin_va_start(v,l)
+#define __va_arg(v,l)	__builtin_va_arg(v,l)
+#define __va_end(v)	__builtin_va_end(v)
+
+#define __ms_va_copy(d,s) __builtin_ms_va_copy(d,s)
+#define __ms_va_start(v,l) __builtin_ms_va_start(v,l)
+#define __ms_va_arg(v,l)	__builtin_va_arg(v,l)
+#define __ms_va_end(v) __builtin_ms_va_end(v)
+
+#define __sysv_va_copy(d,s) __builtin_sysv_va_copy(d,s)
+#define __sysv_va_start(v,l) __builtin_sysv_va_start(v,l)
+#define __sysv_va_arg(v,l)	__builtin_va_arg(v,l)
+#define __sysv_va_end(v) __builtin_sysv_va_end(v)
+
+#define CALLABI_NATIVE
+
+#ifdef _WIN64
+#define CALLABI_CROSS __attribute__ ((sysv_abi))
+
+#define CROSS_VA_LIST	__builtin_sysv_va_list
+
+#define CROSS_VA_COPY(d,s) __sysv_va_copy(d,s)
+#define CROSS_VA_START(v,l) __sysv_va_start(v,l)
+#define CROSS_VA_ARG(v,l) __sysv_va_arg(v,l)
+#define CROSS_VA_END(v)  __sysv_va_end(v)
+
+#else
+
+#define CALLABI_CROSS __attribute__ ((ms_abi))
+
+#define CROSS_VA_LIST	__builtin_ms_va_list
+
+#define CROSS_VA_COPY(d,s) __ms_va_copy(d,s)
+#define CROSS_VA_START(v,l) __ms_va_start(v,l)
+#define CROSS_VA_ARG(v,l) __ms_va_arg(v,l)
+#define CROSS_VA_END(v)  __ms_va_end(v)
+
+#endif
\ No newline at end of file
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c
new file mode 100644
index 000000000..7d0b50636
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c
@@ -0,0 +1,40 @@
+/* Test for cross x86_64<->w64 abi standard calls.
+*/
+/* Origin: Kai Tietz <kai.tietz@onevision.com> */
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -ffast-math" } */
+#include "callabi.h"
+
+extern void abort (void);
+
+long double
+CALLABI_CROSS func_cross (long double a, double b, float c, long d, int e,
+			  char f)
+{
+  long double ret;
+  ret = a + (long double) b + (long double) c;
+  ret *= (long double) (d + (long) e);
+  if (f>0)
+    ret += func_cross (a,b,c,d,e,-f);
+  return ret;
+}
+
+long double
+CALLABI_NATIVE func_native (long double a, double b, float c, long d, int e,
+			    char f)
+{
+  long double ret;
+  ret = a + (long double) b + (long double) c;
+  ret *= (long double) (d + (long) e);
+  if (f>0)
+    ret += func_native (a,b,c,d,e,-f);
+  return ret;
+}
+
+int main ()
+{
+  if (func_cross (1.0,2.0,3.0,1,2,3)
+      != func_native (1.0,2.0,3.0,1,2,3))
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c
new file mode 100644
index 000000000..0c0cbb271
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c
@@ -0,0 +1,24 @@
+/* Test for cross x86_64<->w64 abi standard calls via variable.
+*/
+/* Origin: Kai Tietz <kai.tietz@onevision.com> */
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -ffast-math" } */
+#include "callabi.h"
+
+extern void abort (void);
+
+typedef int (CALLABI_CROSS *func)(void *, char *, char *, short, long long);
+
+int CALLABI_CROSS
+callback(void * ptr, char *string1, char *string2, short number, long long rand)
+{
+    return (rand != 0x1234567890abcdefLL);
+}
+
+int main()
+{
+    volatile func callme = callback;
+    if(callme(0, 0, 0, 0, 0x1234567890abcdefLL))
+     abort();
+    return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/pr38891.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/pr38891.c
new file mode 100644
index 000000000..d31b8c377
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/pr38891.c
@@ -0,0 +1,10 @@
+/* Test for cross x86_64<->w64 abi standard calls.
+*/
+/* { dg-do compile } */
+/* { dg-options "-mno-sse" } */
+#include "callabi.h"
+
+long double
+CALLABI_CROSS func_cross ()
+{
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-1.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-1.c
new file mode 100644
index 000000000..a6d8463ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-1.c
@@ -0,0 +1,47 @@
+/* Test for cross x86_64<->w64 abi va_list calls.
+*/
+/* Origin: Kai Tietz <kai.tietz@onevision.com> */
+/* { dg-do run } */
+/* { dg-options "-std=gnu99" } */
+#include "callabi.h"
+
+extern __SIZE_TYPE__ strlen (const char *);
+extern int sprintf (char *,const char *, ...);
+extern void abort (void);
+
+static
+void CALLABI_CROSS vdo_cpy (char *s, CROSS_VA_LIST argp)
+{
+  __SIZE_TYPE__ len;
+  char *r = s;
+  char *e;
+  *r = 0;
+  for (;;) {
+    e = CROSS_VA_ARG (argp,char *);
+    if (*e == 0) break;
+    sprintf (r,"%s", e);
+    r += strlen (r);
+  }
+}
+
+static
+void CALLABI_CROSS do_cpy (char *s, ...)
+{
+  CROSS_VA_LIST argp;
+  CROSS_VA_START (argp, s);
+  vdo_cpy (s, argp);
+  CROSS_VA_END (argp);
+}
+
+int main ()
+{
+  char s[256];
+
+  do_cpy (s, "1","2","3","4", "5", "6", "7", "");
+
+  if (s[0] != '1' || s[1] !='2' || s[2] != '3' || s[3] != '4'
+      || s[4] != '5' || s[5] != '6' || s[6] != '7' || s[7] != 0)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-2.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-2.c
new file mode 100644
index 000000000..e281e860f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-2.c
@@ -0,0 +1,47 @@
+/* Test for cross x86_64<->w64 abi va_list calls.
+*/
+/* Origin: Kai Tietz <kai.tietz@onevision.com> */
+/* { dg-do run } */
+/* { dg-options "-std=gnu99" } */
+#include "callabi.h"
+
+extern void abort (void);
+
+#define SZ_ARGS	1ll,2ll,3ll,4ll,5ll,6ll,7ll,0ll
+
+static
+int CALLABI_CROSS fct1 (va_list argp, ...)
+{
+  long long p1,p2;
+  int ret = 1;
+  CROSS_VA_LIST argp_2;
+  CROSS_VA_START (argp_2,argp);
+
+  do {
+    p1 = CROSS_VA_ARG (argp_2, long long);
+    p2 = __va_arg (argp, long long);
+    if (p1 != p2)
+      ret = 0;
+  } while (ret && p1 != 0);
+  CROSS_VA_END (argp_2);
+  return ret;
+}
+
+static
+int fct2 (int dummy, ...)
+{
+  va_list argp;
+  int ret = dummy;
+
+  __va_start (argp, dummy);
+  ret += fct1 (argp, SZ_ARGS);
+  __va_end (argp);
+  return ret;
+}
+
+int main()
+{
+  if (fct2 (-1, SZ_ARGS) != 0)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-3.c
new file mode 100644
index 000000000..7cca7ac87
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-3.c
@@ -0,0 +1,47 @@
+/* Test for cross x86_64<->w64 abi va_list calls.
+*/
+/* Origin: Kai Tietz <kai.tietz@onevision.com> */
+/* { dg-do run } */
+/* { dg-options "-std=gnu99" } */
+#include "callabi.h"
+
+extern void abort (void);
+
+#define SZ_ARGS	1ll,2ll,3ll,4ll,5ll,6ll,7ll,0ll
+
+static
+int fct1 (CROSS_VA_LIST argp, ...)
+{
+  long long p1,p2;
+  int ret = 1;
+  va_list argp_2;
+
+    __va_start (argp_2,argp);
+  do {
+    p1 = __va_arg (argp_2, long long);
+    p2 = CROSS_VA_ARG (argp, long long);
+    if (p1 != p2)
+      ret = 0;
+  } while (ret && p1 != 0);
+  __va_end (argp_2);
+  return ret;
+}
+
+static
+int CALLABI_CROSS fct2 (int dummy, ...)
+{
+  CROSS_VA_LIST argp;
+  int ret = dummy;
+
+  CROSS_VA_START (argp, dummy);
+  ret += fct1 (argp, SZ_ARGS);
+  CROSS_VA_END (argp);
+  return ret;
+}
+
+int main()
+{
+  if (fct2 (-1, SZ_ARGS) != 0)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/defines.h b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/defines.h
new file mode 100644
index 000000000..a32daf694
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/defines.h
@@ -0,0 +1,148 @@
+#ifndef DEFINED_DEFINES_H
+#define DEFINED_DEFINES_H
+
+/* Get __m64 and __m128. */
+#include <xmmintrin.h>
+
+typedef unsigned long ulong;
+typedef long double ldouble;
+
+/* These defines determines what part of the test should be run.  When
+   GCC implements these parts, the defines should be uncommented to
+   enable testing.  */
+
+/* Scalar type __int128.  */
+/* #define CHECK_INT128 */
+
+/* Scalar type long double.  */
+#define CHECK_LONG_DOUBLE
+
+/* Scalar type __float128.  */
+/* #define CHECK_FLOAT128 */
+
+/* Scalar types __m64 and __m128.  */
+#define CHECK_M64_M128
+
+/* Returning of complex type.  */
+#define CHECK_COMPLEX
+
+/* Structs with size >= 16.  */
+#define CHECK_LARGER_STRUCTS
+
+/* Checks for passing floats and doubles.  */
+#define CHECK_FLOAT_DOUBLE_PASSING
+
+/* Union passing with not-extremely-simple unions.  */
+#define CHECK_LARGER_UNION_PASSING
+
+/* Variable args.  */
+#define CHECK_VARARGS
+
+/* Check argument passing and returning for scalar types with sizeof = 16.  */
+/* TODO: Implement these tests. Don't activate them for now.  */
+#define CHECK_LARGE_SCALAR_PASSING
+
+/* Defines for sizing and alignment.  */
+
+#define TYPE_SIZE_CHAR         1
+#define TYPE_SIZE_SHORT        2
+#define TYPE_SIZE_INT          4
+#define TYPE_SIZE_LONG         8
+#define TYPE_SIZE_LONG_LONG    8
+#define TYPE_SIZE_INT128       16
+#define TYPE_SIZE_FLOAT        4
+#define TYPE_SIZE_DOUBLE       8
+#define TYPE_SIZE_LONG_DOUBLE  16
+#define TYPE_SIZE_FLOAT128     16
+#define TYPE_SIZE_M64          8
+#define TYPE_SIZE_M128         16
+#define TYPE_SIZE_ENUM         4
+#define TYPE_SIZE_POINTER      8
+
+#define TYPE_ALIGN_CHAR        1
+#define TYPE_ALIGN_SHORT       2
+#define TYPE_ALIGN_INT         4
+#define TYPE_ALIGN_LONG        8
+#define TYPE_ALIGN_LONG_LONG   8
+#define TYPE_ALIGN_INT128      16
+#define TYPE_ALIGN_FLOAT       4
+#define TYPE_ALIGN_DOUBLE      8
+#define TYPE_ALIGN_LONG_DOUBLE 16
+#define TYPE_ALIGN_FLOAT128    16
+#define TYPE_ALIGN_M64         8
+#define TYPE_ALIGN_M128        16
+#define TYPE_ALIGN_ENUM        4
+#define TYPE_ALIGN_POINTER     8
+
+/* These defines control the building of the list of types to check. There
+   is a string identifying the type (with a comma after), a size of the type
+   (also with a comma and an integer for adding to the total amount of types)
+   and an alignment of the type (which is currently not really needed since
+   the abi specifies that alignof == sizeof for all scalar types).  */
+#ifdef CHECK_INT128
+#define CI128_STR "__int128",
+#define CI128_SIZ TYPE_SIZE_INT128,
+#define CI128_ALI TYPE_ALIGN_INT128,
+#define CI128_RET "???",
+#else
+#define CI128_STR
+#define CI128_SIZ
+#define CI128_ALI
+#define CI128_RET
+#endif
+#ifdef CHECK_LONG_DOUBLE
+#define CLD_STR "long double",
+#define CLD_SIZ TYPE_SIZE_LONG_DOUBLE,
+#define CLD_ALI TYPE_ALIGN_LONG_DOUBLE,
+#define CLD_RET "x87_regs[0]._ldouble",
+#else
+#define CLD_STR
+#define CLD_SIZ
+#define CLD_ALI
+#define CLD_RET
+#endif
+#ifdef CHECK_FLOAT128
+#define CF128_STR "__float128",
+#define CF128_SIZ TYPE_SIZE_FLOAT128,
+#define CF128_ALI TYPE_ALIGN_FLOAT128, 
+#define CF128_RET "???",
+#else
+#define CF128_STR
+#define CF128_SIZ
+#define CF128_ALI
+#define CF128_RET
+#endif
+#ifdef CHECK_M64_M128
+#define CMM_STR "__m64", "__m128",
+#define CMM_SIZ TYPE_SIZE_M64, TYPE_SIZE_M128,
+#define CMM_ALI TYPE_ALIGN_M64, TYPE_ALIGN_M128,
+#define CMM_RET "???", "???",
+#else
+#define CMM_STR
+#define CMM_SIZ
+#define CMM_ALI
+#define CMM_RET
+#endif
+
+/* Used in size and alignment tests.  */
+enum dummytype { enumtype };
+
+extern void abort (void);
+
+/* Assertion macro.  */
+#define assert(test) if (!(test)) abort()
+
+#ifdef __GNUC__
+#define ATTRIBUTE_UNUSED __attribute__((__unused__))
+#else
+#define ATTRIBUTE_UNUSED
+#endif
+
+#ifdef __GNUC__
+#define PACKED __attribute__((__packed__))
+#else
+#warning Some tests will fail due to missing __packed__ support
+#define PACKED
+#endif
+
+#endif /* DEFINED_DEFINES_H */
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/macros.h b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/macros.h
new file mode 100644
index 000000000..98fbc660f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/macros.h
@@ -0,0 +1,53 @@
+#ifndef MACROS_H
+
+#define check_size(_t, _size) assert(sizeof(_t) == (_size))
+
+#define check_align(_t, _align) assert(__alignof__(_t) == (_align))
+
+#define check_align_lv(_t, _align) assert(__alignof__(_t) == (_align) \
+					  && (((unsigned long)&(_t)) & ((_align) - 1) ) == 0)
+
+#define check_basic_struct_size_and_align(_type, _size, _align) { \
+  struct _str { _type dummy; } _t; \
+  check_size(_t, _size); \
+  check_align_lv(_t, _align); \
+}
+
+#define check_array_size_and_align(_type, _size, _align) { \
+  _type _a[1]; _type _b[2]; _type _c[16]; \
+  struct _str { _type _a[1]; } _s; \
+  check_align_lv(_a[0], _align); \
+  check_size(_a, _size); \
+  check_size(_b, (_size*2)); \
+  check_size(_c, (_size*16)); \
+  check_size(_s, _size); \
+  check_align_lv(_s._a[0], _align); \
+}
+
+#define check_basic_union_size_and_align(_type, _size, _align) { \
+  union _union { _type dummy; } _u; \
+  check_size(_u, _size); \
+  check_align_lv(_u, _align); \
+}
+
+#define run_signed_tests2(_function, _arg1, _arg2) \
+  _function(_arg1, _arg2); \
+  _function(signed _arg1, _arg2); \
+  _function(unsigned _arg1, _arg2);
+
+#define run_signed_tests3(_function, _arg1, _arg2, _arg3) \
+  _function(_arg1, _arg2, _arg3); \
+  _function(signed _arg1, _arg2, _arg3); \
+  _function(unsigned _arg1, _arg2, _arg3);
+
+/* Check size of a struct and a union of three types.  */
+
+#define check_struct_and_union3(type1, type2, type3, struct_size, align_size) \
+{ \
+  struct _str { type1 t1; type2 t2; type3 t3; } _t; \
+  union _uni { type1 t1; type2 t2; type3 t3; } _u; \
+  check_size(_t, struct_size); \
+  check_size(_u, align_size); \
+}
+
+#endif // MACROS_H
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_3_element_struct_and_unions.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_3_element_struct_and_unions.c
new file mode 100644
index 000000000..5227c6087
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_3_element_struct_and_unions.c
@@ -0,0 +1,523 @@
+/* This is an autogenerated file. Do not edit.  */
+
+#include "defines.h"
+#include "macros.h"
+
+/* Check structs and unions of all permutations of 3 basic types.  */
+int
+main (void)
+{
+  check_struct_and_union3(char, char, char, 3, 1);
+  check_struct_and_union3(char, char, short, 4, 2);
+  check_struct_and_union3(char, char, int, 8, 4);
+  check_struct_and_union3(char, char, long, 16, 8);
+  check_struct_and_union3(char, char, long long, 16, 8);
+  check_struct_and_union3(char, char, float, 8, 4);
+  check_struct_and_union3(char, char, double, 16, 8);
+  check_struct_and_union3(char, char, long double, 32, 16);
+  check_struct_and_union3(char, short, char, 6, 2);
+  check_struct_and_union3(char, short, short, 6, 2);
+  check_struct_and_union3(char, short, int, 8, 4);
+  check_struct_and_union3(char, short, long, 16, 8);
+  check_struct_and_union3(char, short, long long, 16, 8);
+  check_struct_and_union3(char, short, float, 8, 4);
+  check_struct_and_union3(char, short, double, 16, 8);
+  check_struct_and_union3(char, short, long double, 32, 16);
+  check_struct_and_union3(char, int, char, 12, 4);
+  check_struct_and_union3(char, int, short, 12, 4);
+  check_struct_and_union3(char, int, int, 12, 4);
+  check_struct_and_union3(char, int, long, 16, 8);
+  check_struct_and_union3(char, int, long long, 16, 8);
+  check_struct_and_union3(char, int, float, 12, 4);
+  check_struct_and_union3(char, int, double, 16, 8);
+  check_struct_and_union3(char, int, long double, 32, 16);
+  check_struct_and_union3(char, long, char, 24, 8);
+  check_struct_and_union3(char, long, short, 24, 8);
+  check_struct_and_union3(char, long, int, 24, 8);
+  check_struct_and_union3(char, long, long, 24, 8);
+  check_struct_and_union3(char, long, long long, 24, 8);
+  check_struct_and_union3(char, long, float, 24, 8);
+  check_struct_and_union3(char, long, double, 24, 8);
+  check_struct_and_union3(char, long, long double, 32, 16);
+  check_struct_and_union3(char, long long, char, 24, 8);
+  check_struct_and_union3(char, long long, short, 24, 8);
+  check_struct_and_union3(char, long long, int, 24, 8);
+  check_struct_and_union3(char, long long, long, 24, 8);
+  check_struct_and_union3(char, long long, long long, 24, 8);
+  check_struct_and_union3(char, long long, float, 24, 8);
+  check_struct_and_union3(char, long long, double, 24, 8);
+  check_struct_and_union3(char, long long, long double, 32, 16);
+  check_struct_and_union3(char, float, char, 12, 4);
+  check_struct_and_union3(char, float, short, 12, 4);
+  check_struct_and_union3(char, float, int, 12, 4);
+  check_struct_and_union3(char, float, long, 16, 8);
+  check_struct_and_union3(char, float, long long, 16, 8);
+  check_struct_and_union3(char, float, float, 12, 4);
+  check_struct_and_union3(char, float, double, 16, 8);
+  check_struct_and_union3(char, float, long double, 32, 16);
+  check_struct_and_union3(char, double, char, 24, 8);
+  check_struct_and_union3(char, double, short, 24, 8);
+  check_struct_and_union3(char, double, int, 24, 8);
+  check_struct_and_union3(char, double, long, 24, 8);
+  check_struct_and_union3(char, double, long long, 24, 8);
+  check_struct_and_union3(char, double, float, 24, 8);
+  check_struct_and_union3(char, double, double, 24, 8);
+  check_struct_and_union3(char, double, long double, 32, 16);
+  check_struct_and_union3(char, long double, char, 48, 16);
+  check_struct_and_union3(char, long double, short, 48, 16);
+  check_struct_and_union3(char, long double, int, 48, 16);
+  check_struct_and_union3(char, long double, long, 48, 16);
+  check_struct_and_union3(char, long double, long long, 48, 16);
+  check_struct_and_union3(char, long double, float, 48, 16);
+  check_struct_and_union3(char, long double, double, 48, 16);
+  check_struct_and_union3(char, long double, long double, 48, 16);
+  check_struct_and_union3(short, char, char, 4, 2);
+  check_struct_and_union3(short, char, short, 6, 2);
+  check_struct_and_union3(short, char, int, 8, 4);
+  check_struct_and_union3(short, char, long, 16, 8);
+  check_struct_and_union3(short, char, long long, 16, 8);
+  check_struct_and_union3(short, char, float, 8, 4);
+  check_struct_and_union3(short, char, double, 16, 8);
+  check_struct_and_union3(short, char, long double, 32, 16);
+  check_struct_and_union3(short, short, char, 6, 2);
+  check_struct_and_union3(short, short, short, 6, 2);
+  check_struct_and_union3(short, short, int, 8, 4);
+  check_struct_and_union3(short, short, long, 16, 8);
+  check_struct_and_union3(short, short, long long, 16, 8);
+  check_struct_and_union3(short, short, float, 8, 4);
+  check_struct_and_union3(short, short, double, 16, 8);
+  check_struct_and_union3(short, short, long double, 32, 16);
+  check_struct_and_union3(short, int, char, 12, 4);
+  check_struct_and_union3(short, int, short, 12, 4);
+  check_struct_and_union3(short, int, int, 12, 4);
+  check_struct_and_union3(short, int, long, 16, 8);
+  check_struct_and_union3(short, int, long long, 16, 8);
+  check_struct_and_union3(short, int, float, 12, 4);
+  check_struct_and_union3(short, int, double, 16, 8);
+  check_struct_and_union3(short, int, long double, 32, 16);
+  check_struct_and_union3(short, long, char, 24, 8);
+  check_struct_and_union3(short, long, short, 24, 8);
+  check_struct_and_union3(short, long, int, 24, 8);
+  check_struct_and_union3(short, long, long, 24, 8);
+  check_struct_and_union3(short, long, long long, 24, 8);
+  check_struct_and_union3(short, long, float, 24, 8);
+  check_struct_and_union3(short, long, double, 24, 8);
+  check_struct_and_union3(short, long, long double, 32, 16);
+  check_struct_and_union3(short, long long, char, 24, 8);
+  check_struct_and_union3(short, long long, short, 24, 8);
+  check_struct_and_union3(short, long long, int, 24, 8);
+  check_struct_and_union3(short, long long, long, 24, 8);
+  check_struct_and_union3(short, long long, long long, 24, 8);
+  check_struct_and_union3(short, long long, float, 24, 8);
+  check_struct_and_union3(short, long long, double, 24, 8);
+  check_struct_and_union3(short, long long, long double, 32, 16);
+  check_struct_and_union3(short, float, char, 12, 4);
+  check_struct_and_union3(short, float, short, 12, 4);
+  check_struct_and_union3(short, float, int, 12, 4);
+  check_struct_and_union3(short, float, long, 16, 8);
+  check_struct_and_union3(short, float, long long, 16, 8);
+  check_struct_and_union3(short, float, float, 12, 4);
+  check_struct_and_union3(short, float, double, 16, 8);
+  check_struct_and_union3(short, float, long double, 32, 16);
+  check_struct_and_union3(short, double, char, 24, 8);
+  check_struct_and_union3(short, double, short, 24, 8);
+  check_struct_and_union3(short, double, int, 24, 8);
+  check_struct_and_union3(short, double, long, 24, 8);
+  check_struct_and_union3(short, double, long long, 24, 8);
+  check_struct_and_union3(short, double, float, 24, 8);
+  check_struct_and_union3(short, double, double, 24, 8);
+  check_struct_and_union3(short, double, long double, 32, 16);
+  check_struct_and_union3(short, long double, char, 48, 16);
+  check_struct_and_union3(short, long double, short, 48, 16);
+  check_struct_and_union3(short, long double, int, 48, 16);
+  check_struct_and_union3(short, long double, long, 48, 16);
+  check_struct_and_union3(short, long double, long long, 48, 16);
+  check_struct_and_union3(short, long double, float, 48, 16);
+  check_struct_and_union3(short, long double, double, 48, 16);
+  check_struct_and_union3(short, long double, long double, 48, 16);
+  check_struct_and_union3(int, char, char, 8, 4);
+  check_struct_and_union3(int, char, short, 8, 4);
+  check_struct_and_union3(int, char, int, 12, 4);
+  check_struct_and_union3(int, char, long, 16, 8);
+  check_struct_and_union3(int, char, long long, 16, 8);
+  check_struct_and_union3(int, char, float, 12, 4);
+  check_struct_and_union3(int, char, double, 16, 8);
+  check_struct_and_union3(int, char, long double, 32, 16);
+  check_struct_and_union3(int, short, char, 8, 4);
+  check_struct_and_union3(int, short, short, 8, 4);
+  check_struct_and_union3(int, short, int, 12, 4);
+  check_struct_and_union3(int, short, long, 16, 8);
+  check_struct_and_union3(int, short, long long, 16, 8);
+  check_struct_and_union3(int, short, float, 12, 4);
+  check_struct_and_union3(int, short, double, 16, 8);
+  check_struct_and_union3(int, short, long double, 32, 16);
+  check_struct_and_union3(int, int, char, 12, 4);
+  check_struct_and_union3(int, int, short, 12, 4);
+  check_struct_and_union3(int, int, int, 12, 4);
+  check_struct_and_union3(int, int, long, 16, 8);
+  check_struct_and_union3(int, int, long long, 16, 8);
+  check_struct_and_union3(int, int, float, 12, 4);
+  check_struct_and_union3(int, int, double, 16, 8);
+  check_struct_and_union3(int, int, long double, 32, 16);
+  check_struct_and_union3(int, long, char, 24, 8);
+  check_struct_and_union3(int, long, short, 24, 8);
+  check_struct_and_union3(int, long, int, 24, 8);
+  check_struct_and_union3(int, long, long, 24, 8);
+  check_struct_and_union3(int, long, long long, 24, 8);
+  check_struct_and_union3(int, long, float, 24, 8);
+  check_struct_and_union3(int, long, double, 24, 8);
+  check_struct_and_union3(int, long, long double, 32, 16);
+  check_struct_and_union3(int, long long, char, 24, 8);
+  check_struct_and_union3(int, long long, short, 24, 8);
+  check_struct_and_union3(int, long long, int, 24, 8);
+  check_struct_and_union3(int, long long, long, 24, 8);
+  check_struct_and_union3(int, long long, long long, 24, 8);
+  check_struct_and_union3(int, long long, float, 24, 8);
+  check_struct_and_union3(int, long long, double, 24, 8);
+  check_struct_and_union3(int, long long, long double, 32, 16);
+  check_struct_and_union3(int, float, char, 12, 4);
+  check_struct_and_union3(int, float, short, 12, 4);
+  check_struct_and_union3(int, float, int, 12, 4);
+  check_struct_and_union3(int, float, long, 16, 8);
+  check_struct_and_union3(int, float, long long, 16, 8);
+  check_struct_and_union3(int, float, float, 12, 4);
+  check_struct_and_union3(int, float, double, 16, 8);
+  check_struct_and_union3(int, float, long double, 32, 16);
+  check_struct_and_union3(int, double, char, 24, 8);
+  check_struct_and_union3(int, double, short, 24, 8);
+  check_struct_and_union3(int, double, int, 24, 8);
+  check_struct_and_union3(int, double, long, 24, 8);
+  check_struct_and_union3(int, double, long long, 24, 8);
+  check_struct_and_union3(int, double, float, 24, 8);
+  check_struct_and_union3(int, double, double, 24, 8);
+  check_struct_and_union3(int, double, long double, 32, 16);
+  check_struct_and_union3(int, long double, char, 48, 16);
+  check_struct_and_union3(int, long double, short, 48, 16);
+  check_struct_and_union3(int, long double, int, 48, 16);
+  check_struct_and_union3(int, long double, long, 48, 16);
+  check_struct_and_union3(int, long double, long long, 48, 16);
+  check_struct_and_union3(int, long double, float, 48, 16);
+  check_struct_and_union3(int, long double, double, 48, 16);
+  check_struct_and_union3(int, long double, long double, 48, 16);
+  check_struct_and_union3(long, char, char, 16, 8);
+  check_struct_and_union3(long, char, short, 16, 8);
+  check_struct_and_union3(long, char, int, 16, 8);
+  check_struct_and_union3(long, char, long, 24, 8);
+  check_struct_and_union3(long, char, long long, 24, 8);
+  check_struct_and_union3(long, char, float, 16, 8);
+  check_struct_and_union3(long, char, double, 24, 8);
+  check_struct_and_union3(long, char, long double, 32, 16);
+  check_struct_and_union3(long, short, char, 16, 8);
+  check_struct_and_union3(long, short, short, 16, 8);
+  check_struct_and_union3(long, short, int, 16, 8);
+  check_struct_and_union3(long, short, long, 24, 8);
+  check_struct_and_union3(long, short, long long, 24, 8);
+  check_struct_and_union3(long, short, float, 16, 8);
+  check_struct_and_union3(long, short, double, 24, 8);
+  check_struct_and_union3(long, short, long double, 32, 16);
+  check_struct_and_union3(long, int, char, 16, 8);
+  check_struct_and_union3(long, int, short, 16, 8);
+  check_struct_and_union3(long, int, int, 16, 8);
+  check_struct_and_union3(long, int, long, 24, 8);
+  check_struct_and_union3(long, int, long long, 24, 8);
+  check_struct_and_union3(long, int, float, 16, 8);
+  check_struct_and_union3(long, int, double, 24, 8);
+  check_struct_and_union3(long, int, long double, 32, 16);
+  check_struct_and_union3(long, long, char, 24, 8);
+  check_struct_and_union3(long, long, short, 24, 8);
+  check_struct_and_union3(long, long, int, 24, 8);
+  check_struct_and_union3(long, long, long, 24, 8);
+  check_struct_and_union3(long, long, long long, 24, 8);
+  check_struct_and_union3(long, long, float, 24, 8);
+  check_struct_and_union3(long, long, double, 24, 8);
+  check_struct_and_union3(long, long, long double, 32, 16);
+  check_struct_and_union3(long, long long, char, 24, 8);
+  check_struct_and_union3(long, long long, short, 24, 8);
+  check_struct_and_union3(long, long long, int, 24, 8);
+  check_struct_and_union3(long, long long, long, 24, 8);
+  check_struct_and_union3(long, long long, long long, 24, 8);
+  check_struct_and_union3(long, long long, float, 24, 8);
+  check_struct_and_union3(long, long long, double, 24, 8);
+  check_struct_and_union3(long, long long, long double, 32, 16);
+  check_struct_and_union3(long, float, char, 16, 8);
+  check_struct_and_union3(long, float, short, 16, 8);
+  check_struct_and_union3(long, float, int, 16, 8);
+  check_struct_and_union3(long, float, long, 24, 8);
+  check_struct_and_union3(long, float, long long, 24, 8);
+  check_struct_and_union3(long, float, float, 16, 8);
+  check_struct_and_union3(long, float, double, 24, 8);
+  check_struct_and_union3(long, float, long double, 32, 16);
+  check_struct_and_union3(long, double, char, 24, 8);
+  check_struct_and_union3(long, double, short, 24, 8);
+  check_struct_and_union3(long, double, int, 24, 8);
+  check_struct_and_union3(long, double, long, 24, 8);
+  check_struct_and_union3(long, double, long long, 24, 8);
+  check_struct_and_union3(long, double, float, 24, 8);
+  check_struct_and_union3(long, double, double, 24, 8);
+  check_struct_and_union3(long, double, long double, 32, 16);
+  check_struct_and_union3(long, long double, char, 48, 16);
+  check_struct_and_union3(long, long double, short, 48, 16);
+  check_struct_and_union3(long, long double, int, 48, 16);
+  check_struct_and_union3(long, long double, long, 48, 16);
+  check_struct_and_union3(long, long double, long long, 48, 16);
+  check_struct_and_union3(long, long double, float, 48, 16);
+  check_struct_and_union3(long, long double, double, 48, 16);
+  check_struct_and_union3(long, long double, long double, 48, 16);
+  check_struct_and_union3(long long, char, char, 16, 8);
+  check_struct_and_union3(long long, char, short, 16, 8);
+  check_struct_and_union3(long long, char, int, 16, 8);
+  check_struct_and_union3(long long, char, long, 24, 8);
+  check_struct_and_union3(long long, char, long long, 24, 8);
+  check_struct_and_union3(long long, char, float, 16, 8);
+  check_struct_and_union3(long long, char, double, 24, 8);
+  check_struct_and_union3(long long, char, long double, 32, 16);
+  check_struct_and_union3(long long, short, char, 16, 8);
+  check_struct_and_union3(long long, short, short, 16, 8);
+  check_struct_and_union3(long long, short, int, 16, 8);
+  check_struct_and_union3(long long, short, long, 24, 8);
+  check_struct_and_union3(long long, short, long long, 24, 8);
+  check_struct_and_union3(long long, short, float, 16, 8);
+  check_struct_and_union3(long long, short, double, 24, 8);
+  check_struct_and_union3(long long, short, long double, 32, 16);
+  check_struct_and_union3(long long, int, char, 16, 8);
+  check_struct_and_union3(long long, int, short, 16, 8);
+  check_struct_and_union3(long long, int, int, 16, 8);
+  check_struct_and_union3(long long, int, long, 24, 8);
+  check_struct_and_union3(long long, int, long long, 24, 8);
+  check_struct_and_union3(long long, int, float, 16, 8);
+  check_struct_and_union3(long long, int, double, 24, 8);
+  check_struct_and_union3(long long, int, long double, 32, 16);
+  check_struct_and_union3(long long, long, char, 24, 8);
+  check_struct_and_union3(long long, long, short, 24, 8);
+  check_struct_and_union3(long long, long, int, 24, 8);
+  check_struct_and_union3(long long, long, long, 24, 8);
+  check_struct_and_union3(long long, long, long long, 24, 8);
+  check_struct_and_union3(long long, long, float, 24, 8);
+  check_struct_and_union3(long long, long, double, 24, 8);
+  check_struct_and_union3(long long, long, long double, 32, 16);
+  check_struct_and_union3(long long, long long, char, 24, 8);
+  check_struct_and_union3(long long, long long, short, 24, 8);
+  check_struct_and_union3(long long, long long, int, 24, 8);
+  check_struct_and_union3(long long, long long, long, 24, 8);
+  check_struct_and_union3(long long, long long, long long, 24, 8);
+  check_struct_and_union3(long long, long long, float, 24, 8);
+  check_struct_and_union3(long long, long long, double, 24, 8);
+  check_struct_and_union3(long long, long long, long double, 32, 16);
+  check_struct_and_union3(long long, float, char, 16, 8);
+  check_struct_and_union3(long long, float, short, 16, 8);
+  check_struct_and_union3(long long, float, int, 16, 8);
+  check_struct_and_union3(long long, float, long, 24, 8);
+  check_struct_and_union3(long long, float, long long, 24, 8);
+  check_struct_and_union3(long long, float, float, 16, 8);
+  check_struct_and_union3(long long, float, double, 24, 8);
+  check_struct_and_union3(long long, float, long double, 32, 16);
+  check_struct_and_union3(long long, double, char, 24, 8);
+  check_struct_and_union3(long long, double, short, 24, 8);
+  check_struct_and_union3(long long, double, int, 24, 8);
+  check_struct_and_union3(long long, double, long, 24, 8);
+  check_struct_and_union3(long long, double, long long, 24, 8);
+  check_struct_and_union3(long long, double, float, 24, 8);
+  check_struct_and_union3(long long, double, double, 24, 8);
+  check_struct_and_union3(long long, double, long double, 32, 16);
+  check_struct_and_union3(long long, long double, char, 48, 16);
+  check_struct_and_union3(long long, long double, short, 48, 16);
+  check_struct_and_union3(long long, long double, int, 48, 16);
+  check_struct_and_union3(long long, long double, long, 48, 16);
+  check_struct_and_union3(long long, long double, long long, 48, 16);
+  check_struct_and_union3(long long, long double, float, 48, 16);
+  check_struct_and_union3(long long, long double, double, 48, 16);
+  check_struct_and_union3(long long, long double, long double, 48, 16);
+  check_struct_and_union3(float, char, char, 8, 4);
+  check_struct_and_union3(float, char, short, 8, 4);
+  check_struct_and_union3(float, char, int, 12, 4);
+  check_struct_and_union3(float, char, long, 16, 8);
+  check_struct_and_union3(float, char, long long, 16, 8);
+  check_struct_and_union3(float, char, float, 12, 4);
+  check_struct_and_union3(float, char, double, 16, 8);
+  check_struct_and_union3(float, char, long double, 32, 16);
+  check_struct_and_union3(float, short, char, 8, 4);
+  check_struct_and_union3(float, short, short, 8, 4);
+  check_struct_and_union3(float, short, int, 12, 4);
+  check_struct_and_union3(float, short, long, 16, 8);
+  check_struct_and_union3(float, short, long long, 16, 8);
+  check_struct_and_union3(float, short, float, 12, 4);
+  check_struct_and_union3(float, short, double, 16, 8);
+  check_struct_and_union3(float, short, long double, 32, 16);
+  check_struct_and_union3(float, int, char, 12, 4);
+  check_struct_and_union3(float, int, short, 12, 4);
+  check_struct_and_union3(float, int, int, 12, 4);
+  check_struct_and_union3(float, int, long, 16, 8);
+  check_struct_and_union3(float, int, long long, 16, 8);
+  check_struct_and_union3(float, int, float, 12, 4);
+  check_struct_and_union3(float, int, double, 16, 8);
+  check_struct_and_union3(float, int, long double, 32, 16);
+  check_struct_and_union3(float, long, char, 24, 8);
+  check_struct_and_union3(float, long, short, 24, 8);
+  check_struct_and_union3(float, long, int, 24, 8);
+  check_struct_and_union3(float, long, long, 24, 8);
+  check_struct_and_union3(float, long, long long, 24, 8);
+  check_struct_and_union3(float, long, float, 24, 8);
+  check_struct_and_union3(float, long, double, 24, 8);
+  check_struct_and_union3(float, long, long double, 32, 16);
+  check_struct_and_union3(float, long long, char, 24, 8);
+  check_struct_and_union3(float, long long, short, 24, 8);
+  check_struct_and_union3(float, long long, int, 24, 8);
+  check_struct_and_union3(float, long long, long, 24, 8);
+  check_struct_and_union3(float, long long, long long, 24, 8);
+  check_struct_and_union3(float, long long, float, 24, 8);
+  check_struct_and_union3(float, long long, double, 24, 8);
+  check_struct_and_union3(float, long long, long double, 32, 16);
+  check_struct_and_union3(float, float, char, 12, 4);
+  check_struct_and_union3(float, float, short, 12, 4);
+  check_struct_and_union3(float, float, int, 12, 4);
+  check_struct_and_union3(float, float, long, 16, 8);
+  check_struct_and_union3(float, float, long long, 16, 8);
+  check_struct_and_union3(float, float, float, 12, 4);
+  check_struct_and_union3(float, float, double, 16, 8);
+  check_struct_and_union3(float, float, long double, 32, 16);
+  check_struct_and_union3(float, double, char, 24, 8);
+  check_struct_and_union3(float, double, short, 24, 8);
+  check_struct_and_union3(float, double, int, 24, 8);
+  check_struct_and_union3(float, double, long, 24, 8);
+  check_struct_and_union3(float, double, long long, 24, 8);
+  check_struct_and_union3(float, double, float, 24, 8);
+  check_struct_and_union3(float, double, double, 24, 8);
+  check_struct_and_union3(float, double, long double, 32, 16);
+  check_struct_and_union3(float, long double, char, 48, 16);
+  check_struct_and_union3(float, long double, short, 48, 16);
+  check_struct_and_union3(float, long double, int, 48, 16);
+  check_struct_and_union3(float, long double, long, 48, 16);
+  check_struct_and_union3(float, long double, long long, 48, 16);
+  check_struct_and_union3(float, long double, float, 48, 16);
+  check_struct_and_union3(float, long double, double, 48, 16);
+  check_struct_and_union3(float, long double, long double, 48, 16);
+  check_struct_and_union3(double, char, char, 16, 8);
+  check_struct_and_union3(double, char, short, 16, 8);
+  check_struct_and_union3(double, char, int, 16, 8);
+  check_struct_and_union3(double, char, long, 24, 8);
+  check_struct_and_union3(double, char, long long, 24, 8);
+  check_struct_and_union3(double, char, float, 16, 8);
+  check_struct_and_union3(double, char, double, 24, 8);
+  check_struct_and_union3(double, char, long double, 32, 16);
+  check_struct_and_union3(double, short, char, 16, 8);
+  check_struct_and_union3(double, short, short, 16, 8);
+  check_struct_and_union3(double, short, int, 16, 8);
+  check_struct_and_union3(double, short, long, 24, 8);
+  check_struct_and_union3(double, short, long long, 24, 8);
+  check_struct_and_union3(double, short, float, 16, 8);
+  check_struct_and_union3(double, short, double, 24, 8);
+  check_struct_and_union3(double, short, long double, 32, 16);
+  check_struct_and_union3(double, int, char, 16, 8);
+  check_struct_and_union3(double, int, short, 16, 8);
+  check_struct_and_union3(double, int, int, 16, 8);
+  check_struct_and_union3(double, int, long, 24, 8);
+  check_struct_and_union3(double, int, long long, 24, 8);
+  check_struct_and_union3(double, int, float, 16, 8);
+  check_struct_and_union3(double, int, double, 24, 8);
+  check_struct_and_union3(double, int, long double, 32, 16);
+  check_struct_and_union3(double, long, char, 24, 8);
+  check_struct_and_union3(double, long, short, 24, 8);
+  check_struct_and_union3(double, long, int, 24, 8);
+  check_struct_and_union3(double, long, long, 24, 8);
+  check_struct_and_union3(double, long, long long, 24, 8);
+  check_struct_and_union3(double, long, float, 24, 8);
+  check_struct_and_union3(double, long, double, 24, 8);
+  check_struct_and_union3(double, long, long double, 32, 16);
+  check_struct_and_union3(double, long long, char, 24, 8);
+  check_struct_and_union3(double, long long, short, 24, 8);
+  check_struct_and_union3(double, long long, int, 24, 8);
+  check_struct_and_union3(double, long long, long, 24, 8);
+  check_struct_and_union3(double, long long, long long, 24, 8);
+  check_struct_and_union3(double, long long, float, 24, 8);
+  check_struct_and_union3(double, long long, double, 24, 8);
+  check_struct_and_union3(double, long long, long double, 32, 16);
+  check_struct_and_union3(double, float, char, 16, 8);
+  check_struct_and_union3(double, float, short, 16, 8);
+  check_struct_and_union3(double, float, int, 16, 8);
+  check_struct_and_union3(double, float, long, 24, 8);
+  check_struct_and_union3(double, float, long long, 24, 8);
+  check_struct_and_union3(double, float, float, 16, 8);
+  check_struct_and_union3(double, float, double, 24, 8);
+  check_struct_and_union3(double, float, long double, 32, 16);
+  check_struct_and_union3(double, double, char, 24, 8);
+  check_struct_and_union3(double, double, short, 24, 8);
+  check_struct_and_union3(double, double, int, 24, 8);
+  check_struct_and_union3(double, double, long, 24, 8);
+  check_struct_and_union3(double, double, long long, 24, 8);
+  check_struct_and_union3(double, double, float, 24, 8);
+  check_struct_and_union3(double, double, double, 24, 8);
+  check_struct_and_union3(double, double, long double, 32, 16);
+  check_struct_and_union3(double, long double, char, 48, 16);
+  check_struct_and_union3(double, long double, short, 48, 16);
+  check_struct_and_union3(double, long double, int, 48, 16);
+  check_struct_and_union3(double, long double, long, 48, 16);
+  check_struct_and_union3(double, long double, long long, 48, 16);
+  check_struct_and_union3(double, long double, float, 48, 16);
+  check_struct_and_union3(double, long double, double, 48, 16);
+  check_struct_and_union3(double, long double, long double, 48, 16);
+  check_struct_and_union3(long double, char, char, 32, 16);
+  check_struct_and_union3(long double, char, short, 32, 16);
+  check_struct_and_union3(long double, char, int, 32, 16);
+  check_struct_and_union3(long double, char, long, 32, 16);
+  check_struct_and_union3(long double, char, long long, 32, 16);
+  check_struct_and_union3(long double, char, float, 32, 16);
+  check_struct_and_union3(long double, char, double, 32, 16);
+  check_struct_and_union3(long double, char, long double, 48, 16);
+  check_struct_and_union3(long double, short, char, 32, 16);
+  check_struct_and_union3(long double, short, short, 32, 16);
+  check_struct_and_union3(long double, short, int, 32, 16);
+  check_struct_and_union3(long double, short, long, 32, 16);
+  check_struct_and_union3(long double, short, long long, 32, 16);
+  check_struct_and_union3(long double, short, float, 32, 16);
+  check_struct_and_union3(long double, short, double, 32, 16);
+  check_struct_and_union3(long double, short, long double, 48, 16);
+  check_struct_and_union3(long double, int, char, 32, 16);
+  check_struct_and_union3(long double, int, short, 32, 16);
+  check_struct_and_union3(long double, int, int, 32, 16);
+  check_struct_and_union3(long double, int, long, 32, 16);
+  check_struct_and_union3(long double, int, long long, 32, 16);
+  check_struct_and_union3(long double, int, float, 32, 16);
+  check_struct_and_union3(long double, int, double, 32, 16);
+  check_struct_and_union3(long double, int, long double, 48, 16);
+  check_struct_and_union3(long double, long, char, 32, 16);
+  check_struct_and_union3(long double, long, short, 32, 16);
+  check_struct_and_union3(long double, long, int, 32, 16);
+  check_struct_and_union3(long double, long, long, 32, 16);
+  check_struct_and_union3(long double, long, long long, 32, 16);
+  check_struct_and_union3(long double, long, float, 32, 16);
+  check_struct_and_union3(long double, long, double, 32, 16);
+  check_struct_and_union3(long double, long, long double, 48, 16);
+  check_struct_and_union3(long double, long long, char, 32, 16);
+  check_struct_and_union3(long double, long long, short, 32, 16);
+  check_struct_and_union3(long double, long long, int, 32, 16);
+  check_struct_and_union3(long double, long long, long, 32, 16);
+  check_struct_and_union3(long double, long long, long long, 32, 16);
+  check_struct_and_union3(long double, long long, float, 32, 16);
+  check_struct_and_union3(long double, long long, double, 32, 16);
+  check_struct_and_union3(long double, long long, long double, 48, 16);
+  check_struct_and_union3(long double, float, char, 32, 16);
+  check_struct_and_union3(long double, float, short, 32, 16);
+  check_struct_and_union3(long double, float, int, 32, 16);
+  check_struct_and_union3(long double, float, long, 32, 16);
+  check_struct_and_union3(long double, float, long long, 32, 16);
+  check_struct_and_union3(long double, float, float, 32, 16);
+  check_struct_and_union3(long double, float, double, 32, 16);
+  check_struct_and_union3(long double, float, long double, 48, 16);
+  check_struct_and_union3(long double, double, char, 32, 16);
+  check_struct_and_union3(long double, double, short, 32, 16);
+  check_struct_and_union3(long double, double, int, 32, 16);
+  check_struct_and_union3(long double, double, long, 32, 16);
+  check_struct_and_union3(long double, double, long long, 32, 16);
+  check_struct_and_union3(long double, double, float, 32, 16);
+  check_struct_and_union3(long double, double, double, 32, 16);
+  check_struct_and_union3(long double, double, long double, 48, 16);
+  check_struct_and_union3(long double, long double, char, 48, 16);
+  check_struct_and_union3(long double, long double, short, 48, 16);
+  check_struct_and_union3(long double, long double, int, 48, 16);
+  check_struct_and_union3(long double, long double, long, 48, 16);
+  check_struct_and_union3(long double, long double, long long, 48, 16);
+  check_struct_and_union3(long double, long double, float, 48, 16);
+  check_struct_and_union3(long double, long double, double, 48, 16);
+  check_struct_and_union3(long double, long double, long double, 48, 16);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_alignment.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_alignment.c
new file mode 100644
index 000000000..d3d57d788
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_alignment.c
@@ -0,0 +1,42 @@
+/* This checks alignment of basic types.  */
+
+#include "defines.h"
+#include "macros.h"
+
+
+int
+main (void)
+{
+  /* Integral types.  */
+  run_signed_tests2(check_align, char, TYPE_ALIGN_CHAR);
+  run_signed_tests2(check_align, short, TYPE_ALIGN_SHORT);
+  run_signed_tests2(check_align, int, TYPE_ALIGN_INT);
+  run_signed_tests2(check_align, long, TYPE_ALIGN_LONG);
+  run_signed_tests2(check_align, long long, TYPE_ALIGN_LONG_LONG);
+#ifdef CHECK_INT128
+  run_signed_tests2(check_align, __int128, TYPE_ALIGN_INT128);
+#endif
+  check_align(enumtype, TYPE_ALIGN_ENUM);
+
+  /* Floating point types.  */
+  check_align(float, TYPE_ALIGN_FLOAT);
+  check_align(double, TYPE_ALIGN_DOUBLE);
+#ifdef CHECK_LONG_DOUBLE
+  check_align(long double, TYPE_ALIGN_LONG_DOUBLE);
+#endif
+#ifdef CHECK_FLOAT128
+  check_align(__float128, TYPE_ALIGN_FLOAT128);
+#endif
+
+  /* Packed types - MMX, 3DNow!, SSE and SSE2.  */
+#ifdef CHECK_M64_M128
+  check_align(__m64, TYPE_ALIGN_M64);
+  check_align(__m128, TYPE_ALIGN_M128);
+#endif
+
+  /* Pointer types.  */
+  check_align(void *, TYPE_ALIGN_POINTER);
+  check_align(void (*)(), TYPE_ALIGN_POINTER);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_array_size_and_align.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_array_size_and_align.c
new file mode 100644
index 000000000..09c737f05
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_array_size_and_align.c
@@ -0,0 +1,41 @@
+/* This checks .  */
+
+#include "defines.h"
+#include "macros.h"
+
+
+int
+main (void)
+{
+  /* Integral types.  */
+  run_signed_tests3(check_array_size_and_align, char, TYPE_SIZE_CHAR, TYPE_ALIGN_CHAR);
+  run_signed_tests3(check_array_size_and_align, short, TYPE_SIZE_SHORT, TYPE_ALIGN_SHORT);
+  run_signed_tests3(check_array_size_and_align, int, TYPE_SIZE_INT, TYPE_ALIGN_INT);
+  run_signed_tests3(check_array_size_and_align, long, TYPE_SIZE_LONG, TYPE_ALIGN_LONG);
+  run_signed_tests3(check_array_size_and_align, long long, TYPE_SIZE_LONG_LONG, TYPE_ALIGN_LONG_LONG);
+#ifdef CHECK_INT128
+  run_signed_tests3(check_array_size_and_align, __int128, TYPE_SIZE_INT128, TYPE_ALIGN_INT128);
+#endif
+  check_array_size_and_align(enum dummytype, TYPE_SIZE_ENUM, TYPE_ALIGN_ENUM);
+
+  /* Floating point types.  */
+  check_array_size_and_align(float, TYPE_SIZE_FLOAT, TYPE_ALIGN_FLOAT);
+  check_array_size_and_align(double, TYPE_SIZE_DOUBLE, TYPE_ALIGN_DOUBLE);
+#ifdef CHECK_LONG_DOUBLE
+  check_array_size_and_align(long double, TYPE_SIZE_LONG_DOUBLE, TYPE_ALIGN_LONG_DOUBLE);
+#endif
+#ifdef CHECK_FLOAT128
+  check_array_size_and_align(__float128, TYPE_SIZE_FLOAT128, TYPE_ALIGN_FLOAT128);
+#endif
+
+  /* Packed types - MMX, 3DNow!, SSE and SSE2.  */
+#ifdef CHECK_M64_M128
+  check_array_size_and_align(__m64, TYPE_SIZE_M64, TYPE_ALIGN_M64);
+  check_array_size_and_align(__m128, TYPE_SIZE_M128, TYPE_ALIGN_M128);
+#endif
+
+  /* Pointer types. The function pointer doesn't work with these macros.  */
+  check_array_size_and_align(void *, TYPE_SIZE_POINTER, TYPE_ALIGN_POINTER);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_returning.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_returning.c
new file mode 100644
index 000000000..92c906fc8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_returning.c
@@ -0,0 +1,78 @@
+/* This is an autogenerated file. Do not edit.  */
+
+#include "defines.h"
+#include "macros.h"
+#include "args.h"
+
+char
+fun_test_returning_char (void)
+{
+  volatile_var++;
+  return 64;
+}
+
+short
+fun_test_returning_short (void)
+{
+  volatile_var++;
+  return 65;
+}
+
+int
+fun_test_returning_int (void)
+{
+  volatile_var++;
+  return 66;
+}
+
+long
+fun_test_returning_long (void)
+{
+  volatile_var++;
+  return 67;
+}
+
+long long
+fun_test_returning_long_long (void)
+{
+  volatile_var++;
+  return 68;
+}
+
+float
+fun_test_returning_float (void)
+{
+  volatile_var++;
+  return 69;
+}
+
+double
+fun_test_returning_double (void)
+{
+  volatile_var++;
+  return 70;
+}
+
+long double
+fun_test_returning_long_double (void)
+{
+  volatile_var++;
+  return 71;
+}
+
+#define def_test_returning_type_xmm(fun, type, ret, reg) \
+  { type var = WRAP_RET (fun) (); \
+  assert (ret == (type) reg && ret == var); }
+int
+main (void)
+{
+  def_test_returning_type_xmm(fun_test_returning_char, char, 64, rax);
+  def_test_returning_type_xmm(fun_test_returning_short, short, 65, rax);
+  def_test_returning_type_xmm(fun_test_returning_int, int, 66, rax);
+  def_test_returning_type_xmm(fun_test_returning_long, long, 67, rax);
+  def_test_returning_type_xmm(fun_test_returning_long_long, long long, 68, rax);
+  def_test_returning_type_xmm(fun_test_returning_float, float, 69, xmm_regs[0]._float[0]);
+  def_test_returning_type_xmm(fun_test_returning_double, double, 70, xmm_regs[0]._double[0]);
+  def_test_returning_type_xmm(fun_test_returning_long_double, long double, 71, x87_regs[0]._ldouble);
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_sizes.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_sizes.c
new file mode 100644
index 000000000..74427c694
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_sizes.c
@@ -0,0 +1,42 @@
+/* This checks sizes of basic types.  */
+
+#include "defines.h"
+#include "macros.h"
+
+
+int
+main (void)
+{
+  /* Integral types.  */
+  run_signed_tests2(check_size, char, TYPE_SIZE_CHAR);
+  run_signed_tests2(check_size, short, TYPE_SIZE_SHORT);
+  run_signed_tests2(check_size, int, TYPE_SIZE_INT);
+  run_signed_tests2(check_size, long, TYPE_SIZE_LONG);
+  run_signed_tests2(check_size, long long, TYPE_SIZE_LONG_LONG);
+#ifdef CHECK_INT128
+  run_signed_tests2(check_size, __int128, TYPE_SIZE_INT128);
+#endif
+  check_size(enumtype, TYPE_SIZE_ENUM);
+
+  /* Floating point types.  */
+  check_size(float, TYPE_SIZE_FLOAT);
+  check_size(double, TYPE_SIZE_DOUBLE);
+#ifdef CHECK_LONG_DOUBLE
+  check_size(long double, TYPE_SIZE_LONG_DOUBLE);
+#endif
+#ifdef CHECK_FLOAT128
+  check_size(__float128, TYPE_SIZE_FLOAT128);
+#endif
+
+  /* Packed types - MMX, 3DNow!, SSE and SSE2.  */
+#ifdef CHECK_M64_M128
+  check_size(__m64, TYPE_SIZE_M64);
+  check_size(__m128, TYPE_SIZE_M128);
+#endif
+
+  /* Pointer types.  */
+  check_size(void *, TYPE_SIZE_POINTER);
+  check_size(void (*)(), TYPE_SIZE_POINTER);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_struct_size_and_align.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_struct_size_and_align.c
new file mode 100644
index 000000000..783da6ff5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_struct_size_and_align.c
@@ -0,0 +1,42 @@
+/* This checks size and alignment of structs with a single basic type
+   element. All basic types are checked.  */
+
+#include "defines.h"
+#include "macros.h"
+
+
+int
+main (void)
+{
+  /* Integral types.  */
+  run_signed_tests3(check_basic_struct_size_and_align, char, TYPE_SIZE_CHAR, TYPE_ALIGN_CHAR);
+  run_signed_tests3(check_basic_struct_size_and_align, short, TYPE_SIZE_SHORT, TYPE_ALIGN_SHORT);
+  run_signed_tests3(check_basic_struct_size_and_align, int, TYPE_SIZE_INT, TYPE_ALIGN_INT);
+  run_signed_tests3(check_basic_struct_size_and_align, long, TYPE_SIZE_LONG, TYPE_ALIGN_LONG);
+  run_signed_tests3(check_basic_struct_size_and_align, long long, TYPE_SIZE_LONG_LONG, TYPE_ALIGN_LONG_LONG);
+#ifdef CHECK_INT128
+  run_signed_tests3(check_basic_struct_size_and_align, __int128, TYPE_SIZE_INT128, TYPE_ALIGN_INT128);
+#endif
+  check_basic_struct_size_and_align(enum dummytype, TYPE_SIZE_ENUM, TYPE_ALIGN_ENUM);
+
+  /* Floating point types.  */
+  check_basic_struct_size_and_align(float, TYPE_SIZE_FLOAT, TYPE_ALIGN_FLOAT);
+  check_basic_struct_size_and_align(double, TYPE_SIZE_DOUBLE, TYPE_ALIGN_DOUBLE);
+#ifdef CHECK_LONG_DOUBLE
+  check_basic_struct_size_and_align(long double, TYPE_SIZE_LONG_DOUBLE, TYPE_ALIGN_LONG_DOUBLE);
+#endif
+#ifdef CHECK_FLOAT128
+  check_basic_struct_size_and_align(__float128, TYPE_SIZE_FLOAT128, TYPE_ALIGN_FLOAT128);
+#endif
+
+  /* Packed types - MMX, 3DNow!, SSE and SSE2.  */
+#ifdef CHECK_M64_M128
+  check_basic_struct_size_and_align(__m64, TYPE_SIZE_M64, TYPE_ALIGN_M64);
+  check_basic_struct_size_and_align(__m128, TYPE_SIZE_M128, TYPE_ALIGN_M128);
+#endif
+
+  /* Pointer types. The function pointer doesn't work with these macros.  */
+  check_basic_struct_size_and_align(void *, TYPE_SIZE_POINTER, TYPE_ALIGN_POINTER);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_union_size_and_align.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_union_size_and_align.c
new file mode 100644
index 000000000..a5a51f290
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_basic_union_size_and_align.c
@@ -0,0 +1,41 @@
+/* Test of simple unions, size and alignment.  */
+
+#include "defines.h"
+#include "macros.h"
+
+
+int
+main (void)
+{
+  /* Integral types.  */
+  run_signed_tests3(check_basic_union_size_and_align, char, TYPE_SIZE_CHAR, TYPE_ALIGN_CHAR);
+  run_signed_tests3(check_basic_union_size_and_align, short, TYPE_SIZE_SHORT, TYPE_ALIGN_SHORT);
+  run_signed_tests3(check_basic_union_size_and_align, int, TYPE_SIZE_INT, TYPE_ALIGN_INT);
+  run_signed_tests3(check_basic_union_size_and_align, long, TYPE_SIZE_LONG, TYPE_ALIGN_LONG);
+  run_signed_tests3(check_basic_union_size_and_align, long long, TYPE_SIZE_LONG_LONG, TYPE_ALIGN_LONG_LONG);
+#ifdef CHECK_INT128
+  run_signed_tests3(check_basic_union_size_and_align, __int128, TYPE_SIZE_INT128, TYPE_ALIGN_INT128);
+#endif
+  check_basic_union_size_and_align(enum dummytype, TYPE_SIZE_ENUM, TYPE_ALIGN_ENUM);
+
+  /* Floating point types.  */
+  check_basic_union_size_and_align(float, TYPE_SIZE_FLOAT, TYPE_ALIGN_FLOAT);
+  check_basic_union_size_and_align(double, TYPE_SIZE_DOUBLE, TYPE_ALIGN_DOUBLE);
+#ifdef CHECK_LONG_DOUBLE
+  check_basic_union_size_and_align(long double, TYPE_SIZE_LONG_DOUBLE, TYPE_ALIGN_LONG_DOUBLE);
+#endif
+#ifdef CHECK_FLOAT128
+  check_basic_union_size_and_align(__float128, TYPE_SIZE_FLOAT128, TYPE_ALIGN_FLOAT128);
+#endif
+
+  /* Packed types - MMX, 3DNow!, SSE and SSE2.  */
+#ifdef CHECK_M64_M128
+  check_basic_union_size_and_align(__m64, TYPE_SIZE_M64, TYPE_ALIGN_M64);
+  check_basic_union_size_and_align(__m128, TYPE_SIZE_M128, TYPE_ALIGN_M128);
+#endif
+
+  /* Pointer types. The function pointer doesn't work with these macros.  */
+  check_basic_union_size_and_align(void *, TYPE_SIZE_POINTER, TYPE_ALIGN_POINTER);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_bitfields.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_bitfields.c
new file mode 100644
index 000000000..27ab1c6aa
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_bitfields.c
@@ -0,0 +1,162 @@
+/* This is a small test to see if bitfields are working.  It is only a
+   few structs and a union and a test to see if they have the correct
+   size, if values can be read and written and a couple of argument
+   passing tests.  No alignment testing is done.  */
+
+#include "defines.h"
+#include "macros.h"
+
+
+/* These five bitfields are taken from the System V ABI, Intel 386
+   architecture supplement.  */
+
+/* Word aligned, sizeof is 4.  */
+struct RightToLeft
+{
+  int j:5;
+  int k:6;
+  int m:7;
+};
+
+/* Word aligned, sizeof is 12.  */
+struct BoundaryAlignment
+{
+  short s:9;
+  int   j:9;
+  char  c;
+  short t:9;
+  short u:9;
+  char  d;
+};
+
+/* Halfword aligned, sizeof is 2.  */
+struct StorageUnitSharing
+{
+  char  c;
+  short s:8;
+};
+
+/* Halfword aligned, sizeof is 2.  */
+union Allocation
+{
+  char  c;
+  short s:8;
+};
+
+/* Byte aligned, sizeof is 9.  */
+struct Unnamed
+{
+  char  c;
+  int    :0;
+  char  d;
+  short  :9;
+  char  e;
+  char   :0;
+};
+
+/* Extra struct testing bitfields in larger types.
+   Doubleword aligned, sizeof is 8.  */
+struct LargerTypes
+{
+  long long l:33;
+  int       i:31;
+};
+
+
+void
+passing1 (struct RightToLeft str, int j, int k, int m)
+{
+  assert (str.j == j);
+  assert (str.k == k);
+  assert (str.m == m);
+}
+
+void
+passing2 (struct BoundaryAlignment str, short s, int j, char c, short t,
+	  short u, char d)
+{
+  assert (str.s == s);
+  assert (str.j == j);
+  assert (str.c == c);
+  assert (str.t == t);
+  assert (str.u == u);
+  assert (str.d == d);
+}
+
+void
+passing3 (struct StorageUnitSharing str, char c, short s)
+{
+  assert (str.c == c);
+  assert (str.s == s);
+}
+
+void
+passing4 (struct Unnamed str, char c, char d, char e)
+{
+  assert (str.c == c);
+  assert (str.d == d);
+  assert (str.e == e);
+}
+
+void
+passing5 (struct LargerTypes str, long long l, int i)
+{
+  assert (str.l == l);
+  assert (str.i == i);
+}
+
+
+void
+passingU (union Allocation u, char c)
+{
+  assert (u.c == c);
+  assert (u.s == c);
+}
+
+
+int
+main (void)
+{
+  struct RightToLeft str1;
+  struct BoundaryAlignment str2;
+  struct StorageUnitSharing str3;
+  struct Unnamed str4;
+  struct LargerTypes str5;
+  union Allocation u;
+
+  /* Check sizeof's.  */
+  check_size(str1, 4);
+  check_size(str2, 12);
+  check_size(str3, 2);
+  check_size(str4, 9);
+  check_size(str5, 8);
+  check_size(u, 2);
+
+  /* Check alignof's.  */
+  check_align_lv(str1, 4);
+  check_align_lv(str2, 4);
+  check_align_lv(str3, 2);
+  check_align_lv(str4, 1);
+  check_align_lv(str5, 8);
+  check_align_lv(u, 2);
+
+  /* Check passing.  */
+  str1.j = str2.s = str3.c = str4.c = str5.l = 4;
+  str1.k = str2.j = str3.s = str4.d = str5.i = 5;
+  str1.m = str2.c = str4.e = 6;
+  str2.t = 7;
+  str2.u = 8;
+  str2.d = 9;
+  passing1 (str1, 4, 5, 6);
+  passing2 (str2, 4, 5, 6, 7, 8, 9);
+  passing3 (str3, 4, 5);
+  passing4 (str4, 4, 5, 6);
+  passing5 (str5, 4, 5);
+
+  u.c = 5;
+  passingU (u, 5);
+  u.s = 6;
+  passingU (u, 6);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_complex_returning.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_complex_returning.c
new file mode 100644
index 000000000..9e9678d7b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_complex_returning.c
@@ -0,0 +1,83 @@
+/* This is a small test case for returning a complex number. Written by
+   Andreas Jaeger.  */
+
+#include "defines.h"
+
+
+#define BUILD_F_COMPLEX(real, imag) \
+  ({ __complex__ float __retval; \
+     __real__ __retval = (real); \
+     __imag__ __retval = (imag); \
+     __retval; })
+
+#define BUILD_D_COMPLEX(real, imag) \
+  ({ __complex__ double __retval; \
+     __real__ __retval = (real); \
+     __imag__ __retval = (imag); \
+     __retval; })
+
+#define BUILD_LD_COMPLEX(real, imag) \
+  ({ __complex__ long double __retval; \
+     __real__ __retval = (real); \
+     __imag__ __retval = (imag); \
+     __retval; })
+
+__complex__ float
+aj_f_times2 (__complex__ float x)
+{
+  __complex__ float res;
+
+  __real__ res = (2.0 * __real__ x);
+  __imag__ res = (2.0 * __imag__ x);
+
+  return res;
+}
+
+__complex__ double
+aj_d_times2 (__complex__ double x)
+{
+  __complex__ double res;
+
+  __real__ res = (2.0 * __real__ x);
+  __imag__ res = (2.0 * __imag__ x);
+
+  return res;
+}
+
+__complex__ long double
+aj_ld_times2 (__complex__ long double x)
+{
+  __complex__ long double res;
+
+  __real__ res = (2.0 * __real__ x);
+  __imag__ res = (2.0 * __imag__ x);
+
+  return res;
+}
+
+int
+main (void)
+{
+#ifdef CHECK_COMPLEX
+  _Complex float fc, fd;
+  _Complex double dc, dd;
+  _Complex long double ldc, ldd;
+
+  fc = BUILD_LD_COMPLEX (2.0f, 3.0f);
+  fd = aj_f_times2 (fc);
+
+  assert (__real__ fd == 4.0f && __imag__ fd == 6.0f);
+
+  dc = BUILD_LD_COMPLEX (2.0, 3.0);
+  dd = aj_ld_times2 (dc);
+
+  assert (__real__ dd == 4.0 && __imag__ dd == 6.0);
+
+  ldc = BUILD_LD_COMPLEX (2.0L, 3.0L);
+  ldd = aj_ld_times2 (ldc);
+
+  assert (__real__ ldd == 4.0L && __imag__ ldd == 6.0L);
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_m64m128_returning.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_m64m128_returning.c
new file mode 100644
index 000000000..cde034693
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_m64m128_returning.c
@@ -0,0 +1,54 @@
+#include <stdio.h>
+#include "defines.h"
+#include "macros.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+__m64
+fun_test_returning___m64 (void)
+{
+  volatile_var++;
+  return (__m64){72,0};
+}
+
+__m128
+fun_test_returning___m128 (void)
+{
+  volatile_var++;
+  return (__m128){73,0,0,0};
+}
+
+__m64 test_64;
+__m128 test_128;
+
+int
+main (void)
+{
+  unsigned failed = 0;
+  XMM_T xmmt1, xmmt2;
+
+  /* We jump through hoops to compare the results as gcc 3.3 does throw
+     an ICE when trying to generate a compare for a == b, when a and b
+     are of __m64 or __m128 type :-(  */
+  clear_struct_registers;
+  test_64 = (__m64){72,0};
+  xmmt1._m64[0] = test_64;
+  xmmt2._m64[0] = WRAP_RET (fun_test_returning___m64)();
+  if (xmmt1._long[0] != xmmt2._long[0]
+      || xmmt1._long[0] != xmm_regs[0]._long[0])
+    printf ("fail m64\n"), failed++;
+
+  clear_struct_registers;
+  test_128 = (__m128){73,0};
+  xmmt1._m128[0] = test_128;
+  xmmt2._m128[0] = WRAP_RET (fun_test_returning___m128)();
+  if (xmmt1._long[0] != xmmt2._long[0]
+      || xmmt1._long[0] != xmm_regs[0]._long[0])
+    printf ("fail m128\n"), failed++;
+  if (failed)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_floats.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_floats.c
new file mode 100644
index 000000000..42fff97b0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_floats.c
@@ -0,0 +1,502 @@
+/* This is an autogenerated file. Do not edit.  */
+
+#include "defines.h"
+#include "macros.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+/* This struct holds values for argument checking.  */
+struct 
+{
+  float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, f21, f22, f23;
+} values_float;
+
+struct 
+{
+  double f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, f21, f22, f23;
+} values_double;
+
+struct 
+{
+  ldouble f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, f21, f22, f23;
+} values_ldouble;
+
+void
+fun_check_float_passing_float8_values (float f0 ATTRIBUTE_UNUSED, float f1 ATTRIBUTE_UNUSED, float f2 ATTRIBUTE_UNUSED, float f3 ATTRIBUTE_UNUSED, float f4 ATTRIBUTE_UNUSED, float f5 ATTRIBUTE_UNUSED, float f6 ATTRIBUTE_UNUSED, float f7 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_float.f0 == f0);
+  assert (values_float.f1 == f1);
+  assert (values_float.f2 == f2);
+  assert (values_float.f3 == f3);
+  assert (values_float.f4 == f4);
+  assert (values_float.f5 == f5);
+  assert (values_float.f6 == f6);
+  assert (values_float.f7 == f7);
+
+}
+
+void
+fun_check_float_passing_float8_regs (float f0 ATTRIBUTE_UNUSED, float f1 ATTRIBUTE_UNUSED, float f2 ATTRIBUTE_UNUSED, float f3 ATTRIBUTE_UNUSED, float f4 ATTRIBUTE_UNUSED, float f5 ATTRIBUTE_UNUSED, float f6 ATTRIBUTE_UNUSED, float f7 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_float_arguments;
+}
+
+void
+fun_check_float_passing_float16_values (float f0 ATTRIBUTE_UNUSED, float f1 ATTRIBUTE_UNUSED, float f2 ATTRIBUTE_UNUSED, float f3 ATTRIBUTE_UNUSED, float f4 ATTRIBUTE_UNUSED, float f5 ATTRIBUTE_UNUSED, float f6 ATTRIBUTE_UNUSED, float f7 ATTRIBUTE_UNUSED, float f8 ATTRIBUTE_UNUSED, float f9 ATTRIBUTE_UNUSED, float f10 ATTRIBUTE_UNUSED, float f11 ATTRIBUTE_UNUSED, float f12 ATTRIBUTE_UNUSED, float f13 ATTRIBUTE_UNUSED, float f14 ATTRIBUTE_UNUSED, float f15 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_float.f0 == f0);
+  assert (values_float.f1 == f1);
+  assert (values_float.f2 == f2);
+  assert (values_float.f3 == f3);
+  assert (values_float.f4 == f4);
+  assert (values_float.f5 == f5);
+  assert (values_float.f6 == f6);
+  assert (values_float.f7 == f7);
+  assert (values_float.f8 == f8);
+  assert (values_float.f9 == f9);
+  assert (values_float.f10 == f10);
+  assert (values_float.f11 == f11);
+  assert (values_float.f12 == f12);
+  assert (values_float.f13 == f13);
+  assert (values_float.f14 == f14);
+  assert (values_float.f15 == f15);
+
+}
+
+void
+fun_check_float_passing_float16_regs (float f0 ATTRIBUTE_UNUSED, float f1 ATTRIBUTE_UNUSED, float f2 ATTRIBUTE_UNUSED, float f3 ATTRIBUTE_UNUSED, float f4 ATTRIBUTE_UNUSED, float f5 ATTRIBUTE_UNUSED, float f6 ATTRIBUTE_UNUSED, float f7 ATTRIBUTE_UNUSED, float f8 ATTRIBUTE_UNUSED, float f9 ATTRIBUTE_UNUSED, float f10 ATTRIBUTE_UNUSED, float f11 ATTRIBUTE_UNUSED, float f12 ATTRIBUTE_UNUSED, float f13 ATTRIBUTE_UNUSED, float f14 ATTRIBUTE_UNUSED, float f15 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_float_arguments;
+}
+
+void
+fun_check_float_passing_float20_values (float f0 ATTRIBUTE_UNUSED, float f1 ATTRIBUTE_UNUSED, float f2 ATTRIBUTE_UNUSED, float f3 ATTRIBUTE_UNUSED, float f4 ATTRIBUTE_UNUSED, float f5 ATTRIBUTE_UNUSED, float f6 ATTRIBUTE_UNUSED, float f7 ATTRIBUTE_UNUSED, float f8 ATTRIBUTE_UNUSED, float f9 ATTRIBUTE_UNUSED, float f10 ATTRIBUTE_UNUSED, float f11 ATTRIBUTE_UNUSED, float f12 ATTRIBUTE_UNUSED, float f13 ATTRIBUTE_UNUSED, float f14 ATTRIBUTE_UNUSED, float f15 ATTRIBUTE_UNUSED, float f16 ATTRIBUTE_UNUSED, float f17 ATTRIBUTE_UNUSED, float f18 ATTRIBUTE_UNUSED, float f19 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_float.f0 == f0);
+  assert (values_float.f1 == f1);
+  assert (values_float.f2 == f2);
+  assert (values_float.f3 == f3);
+  assert (values_float.f4 == f4);
+  assert (values_float.f5 == f5);
+  assert (values_float.f6 == f6);
+  assert (values_float.f7 == f7);
+  assert (values_float.f8 == f8);
+  assert (values_float.f9 == f9);
+  assert (values_float.f10 == f10);
+  assert (values_float.f11 == f11);
+  assert (values_float.f12 == f12);
+  assert (values_float.f13 == f13);
+  assert (values_float.f14 == f14);
+  assert (values_float.f15 == f15);
+  assert (values_float.f16 == f16);
+  assert (values_float.f17 == f17);
+  assert (values_float.f18 == f18);
+  assert (values_float.f19 == f19);
+
+}
+
+void
+fun_check_float_passing_float20_regs (float f0 ATTRIBUTE_UNUSED, float f1 ATTRIBUTE_UNUSED, float f2 ATTRIBUTE_UNUSED, float f3 ATTRIBUTE_UNUSED, float f4 ATTRIBUTE_UNUSED, float f5 ATTRIBUTE_UNUSED, float f6 ATTRIBUTE_UNUSED, float f7 ATTRIBUTE_UNUSED, float f8 ATTRIBUTE_UNUSED, float f9 ATTRIBUTE_UNUSED, float f10 ATTRIBUTE_UNUSED, float f11 ATTRIBUTE_UNUSED, float f12 ATTRIBUTE_UNUSED, float f13 ATTRIBUTE_UNUSED, float f14 ATTRIBUTE_UNUSED, float f15 ATTRIBUTE_UNUSED, float f16 ATTRIBUTE_UNUSED, float f17 ATTRIBUTE_UNUSED, float f18 ATTRIBUTE_UNUSED, float f19 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_float_arguments;
+}
+
+void
+fun_check_float_passing_double8_values (double f0 ATTRIBUTE_UNUSED, double f1 ATTRIBUTE_UNUSED, double f2 ATTRIBUTE_UNUSED, double f3 ATTRIBUTE_UNUSED, double f4 ATTRIBUTE_UNUSED, double f5 ATTRIBUTE_UNUSED, double f6 ATTRIBUTE_UNUSED, double f7 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_double.f0 == f0);
+  assert (values_double.f1 == f1);
+  assert (values_double.f2 == f2);
+  assert (values_double.f3 == f3);
+  assert (values_double.f4 == f4);
+  assert (values_double.f5 == f5);
+  assert (values_double.f6 == f6);
+  assert (values_double.f7 == f7);
+
+}
+
+void
+fun_check_float_passing_double8_regs (double f0 ATTRIBUTE_UNUSED, double f1 ATTRIBUTE_UNUSED, double f2 ATTRIBUTE_UNUSED, double f3 ATTRIBUTE_UNUSED, double f4 ATTRIBUTE_UNUSED, double f5 ATTRIBUTE_UNUSED, double f6 ATTRIBUTE_UNUSED, double f7 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_double_arguments;
+}
+
+void
+fun_check_float_passing_double16_values (double f0 ATTRIBUTE_UNUSED, double f1 ATTRIBUTE_UNUSED, double f2 ATTRIBUTE_UNUSED, double f3 ATTRIBUTE_UNUSED, double f4 ATTRIBUTE_UNUSED, double f5 ATTRIBUTE_UNUSED, double f6 ATTRIBUTE_UNUSED, double f7 ATTRIBUTE_UNUSED, double f8 ATTRIBUTE_UNUSED, double f9 ATTRIBUTE_UNUSED, double f10 ATTRIBUTE_UNUSED, double f11 ATTRIBUTE_UNUSED, double f12 ATTRIBUTE_UNUSED, double f13 ATTRIBUTE_UNUSED, double f14 ATTRIBUTE_UNUSED, double f15 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_double.f0 == f0);
+  assert (values_double.f1 == f1);
+  assert (values_double.f2 == f2);
+  assert (values_double.f3 == f3);
+  assert (values_double.f4 == f4);
+  assert (values_double.f5 == f5);
+  assert (values_double.f6 == f6);
+  assert (values_double.f7 == f7);
+  assert (values_double.f8 == f8);
+  assert (values_double.f9 == f9);
+  assert (values_double.f10 == f10);
+  assert (values_double.f11 == f11);
+  assert (values_double.f12 == f12);
+  assert (values_double.f13 == f13);
+  assert (values_double.f14 == f14);
+  assert (values_double.f15 == f15);
+
+}
+
+void
+fun_check_float_passing_double16_regs (double f0 ATTRIBUTE_UNUSED, double f1 ATTRIBUTE_UNUSED, double f2 ATTRIBUTE_UNUSED, double f3 ATTRIBUTE_UNUSED, double f4 ATTRIBUTE_UNUSED, double f5 ATTRIBUTE_UNUSED, double f6 ATTRIBUTE_UNUSED, double f7 ATTRIBUTE_UNUSED, double f8 ATTRIBUTE_UNUSED, double f9 ATTRIBUTE_UNUSED, double f10 ATTRIBUTE_UNUSED, double f11 ATTRIBUTE_UNUSED, double f12 ATTRIBUTE_UNUSED, double f13 ATTRIBUTE_UNUSED, double f14 ATTRIBUTE_UNUSED, double f15 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_double_arguments;
+}
+
+void
+fun_check_float_passing_double20_values (double f0 ATTRIBUTE_UNUSED, double f1 ATTRIBUTE_UNUSED, double f2 ATTRIBUTE_UNUSED, double f3 ATTRIBUTE_UNUSED, double f4 ATTRIBUTE_UNUSED, double f5 ATTRIBUTE_UNUSED, double f6 ATTRIBUTE_UNUSED, double f7 ATTRIBUTE_UNUSED, double f8 ATTRIBUTE_UNUSED, double f9 ATTRIBUTE_UNUSED, double f10 ATTRIBUTE_UNUSED, double f11 ATTRIBUTE_UNUSED, double f12 ATTRIBUTE_UNUSED, double f13 ATTRIBUTE_UNUSED, double f14 ATTRIBUTE_UNUSED, double f15 ATTRIBUTE_UNUSED, double f16 ATTRIBUTE_UNUSED, double f17 ATTRIBUTE_UNUSED, double f18 ATTRIBUTE_UNUSED, double f19 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_double.f0 == f0);
+  assert (values_double.f1 == f1);
+  assert (values_double.f2 == f2);
+  assert (values_double.f3 == f3);
+  assert (values_double.f4 == f4);
+  assert (values_double.f5 == f5);
+  assert (values_double.f6 == f6);
+  assert (values_double.f7 == f7);
+  assert (values_double.f8 == f8);
+  assert (values_double.f9 == f9);
+  assert (values_double.f10 == f10);
+  assert (values_double.f11 == f11);
+  assert (values_double.f12 == f12);
+  assert (values_double.f13 == f13);
+  assert (values_double.f14 == f14);
+  assert (values_double.f15 == f15);
+  assert (values_double.f16 == f16);
+  assert (values_double.f17 == f17);
+  assert (values_double.f18 == f18);
+  assert (values_double.f19 == f19);
+
+}
+
+void
+fun_check_float_passing_double20_regs (double f0 ATTRIBUTE_UNUSED, double f1 ATTRIBUTE_UNUSED, double f2 ATTRIBUTE_UNUSED, double f3 ATTRIBUTE_UNUSED, double f4 ATTRIBUTE_UNUSED, double f5 ATTRIBUTE_UNUSED, double f6 ATTRIBUTE_UNUSED, double f7 ATTRIBUTE_UNUSED, double f8 ATTRIBUTE_UNUSED, double f9 ATTRIBUTE_UNUSED, double f10 ATTRIBUTE_UNUSED, double f11 ATTRIBUTE_UNUSED, double f12 ATTRIBUTE_UNUSED, double f13 ATTRIBUTE_UNUSED, double f14 ATTRIBUTE_UNUSED, double f15 ATTRIBUTE_UNUSED, double f16 ATTRIBUTE_UNUSED, double f17 ATTRIBUTE_UNUSED, double f18 ATTRIBUTE_UNUSED, double f19 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_double_arguments;
+}
+
+void
+fun_check_x87_passing_ldouble8_values (ldouble f0 ATTRIBUTE_UNUSED, ldouble f1 ATTRIBUTE_UNUSED, ldouble f2 ATTRIBUTE_UNUSED, ldouble f3 ATTRIBUTE_UNUSED, ldouble f4 ATTRIBUTE_UNUSED, ldouble f5 ATTRIBUTE_UNUSED, ldouble f6 ATTRIBUTE_UNUSED, ldouble f7 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_ldouble.f0 == f0);
+  assert (values_ldouble.f1 == f1);
+  assert (values_ldouble.f2 == f2);
+  assert (values_ldouble.f3 == f3);
+  assert (values_ldouble.f4 == f4);
+  assert (values_ldouble.f5 == f5);
+  assert (values_ldouble.f6 == f6);
+  assert (values_ldouble.f7 == f7);
+
+}
+
+void
+fun_check_x87_passing_ldouble8_regs (ldouble f0 ATTRIBUTE_UNUSED, ldouble f1 ATTRIBUTE_UNUSED, ldouble f2 ATTRIBUTE_UNUSED, ldouble f3 ATTRIBUTE_UNUSED, ldouble f4 ATTRIBUTE_UNUSED, ldouble f5 ATTRIBUTE_UNUSED, ldouble f6 ATTRIBUTE_UNUSED, ldouble f7 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_ldouble_arguments;
+}
+
+void
+fun_check_x87_passing_ldouble16_values (ldouble f0 ATTRIBUTE_UNUSED, ldouble f1 ATTRIBUTE_UNUSED, ldouble f2 ATTRIBUTE_UNUSED, ldouble f3 ATTRIBUTE_UNUSED, ldouble f4 ATTRIBUTE_UNUSED, ldouble f5 ATTRIBUTE_UNUSED, ldouble f6 ATTRIBUTE_UNUSED, ldouble f7 ATTRIBUTE_UNUSED, ldouble f8 ATTRIBUTE_UNUSED, ldouble f9 ATTRIBUTE_UNUSED, ldouble f10 ATTRIBUTE_UNUSED, ldouble f11 ATTRIBUTE_UNUSED, ldouble f12 ATTRIBUTE_UNUSED, ldouble f13 ATTRIBUTE_UNUSED, ldouble f14 ATTRIBUTE_UNUSED, ldouble f15 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_ldouble.f0 == f0);
+  assert (values_ldouble.f1 == f1);
+  assert (values_ldouble.f2 == f2);
+  assert (values_ldouble.f3 == f3);
+  assert (values_ldouble.f4 == f4);
+  assert (values_ldouble.f5 == f5);
+  assert (values_ldouble.f6 == f6);
+  assert (values_ldouble.f7 == f7);
+  assert (values_ldouble.f8 == f8);
+  assert (values_ldouble.f9 == f9);
+  assert (values_ldouble.f10 == f10);
+  assert (values_ldouble.f11 == f11);
+  assert (values_ldouble.f12 == f12);
+  assert (values_ldouble.f13 == f13);
+  assert (values_ldouble.f14 == f14);
+  assert (values_ldouble.f15 == f15);
+
+}
+
+void
+fun_check_x87_passing_ldouble16_regs (ldouble f0 ATTRIBUTE_UNUSED, ldouble f1 ATTRIBUTE_UNUSED, ldouble f2 ATTRIBUTE_UNUSED, ldouble f3 ATTRIBUTE_UNUSED, ldouble f4 ATTRIBUTE_UNUSED, ldouble f5 ATTRIBUTE_UNUSED, ldouble f6 ATTRIBUTE_UNUSED, ldouble f7 ATTRIBUTE_UNUSED, ldouble f8 ATTRIBUTE_UNUSED, ldouble f9 ATTRIBUTE_UNUSED, ldouble f10 ATTRIBUTE_UNUSED, ldouble f11 ATTRIBUTE_UNUSED, ldouble f12 ATTRIBUTE_UNUSED, ldouble f13 ATTRIBUTE_UNUSED, ldouble f14 ATTRIBUTE_UNUSED, ldouble f15 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_ldouble_arguments;
+}
+
+void
+fun_check_x87_passing_ldouble20_values (ldouble f0 ATTRIBUTE_UNUSED, ldouble f1 ATTRIBUTE_UNUSED, ldouble f2 ATTRIBUTE_UNUSED, ldouble f3 ATTRIBUTE_UNUSED, ldouble f4 ATTRIBUTE_UNUSED, ldouble f5 ATTRIBUTE_UNUSED, ldouble f6 ATTRIBUTE_UNUSED, ldouble f7 ATTRIBUTE_UNUSED, ldouble f8 ATTRIBUTE_UNUSED, ldouble f9 ATTRIBUTE_UNUSED, ldouble f10 ATTRIBUTE_UNUSED, ldouble f11 ATTRIBUTE_UNUSED, ldouble f12 ATTRIBUTE_UNUSED, ldouble f13 ATTRIBUTE_UNUSED, ldouble f14 ATTRIBUTE_UNUSED, ldouble f15 ATTRIBUTE_UNUSED, ldouble f16 ATTRIBUTE_UNUSED, ldouble f17 ATTRIBUTE_UNUSED, ldouble f18 ATTRIBUTE_UNUSED, ldouble f19 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_ldouble.f0 == f0);
+  assert (values_ldouble.f1 == f1);
+  assert (values_ldouble.f2 == f2);
+  assert (values_ldouble.f3 == f3);
+  assert (values_ldouble.f4 == f4);
+  assert (values_ldouble.f5 == f5);
+  assert (values_ldouble.f6 == f6);
+  assert (values_ldouble.f7 == f7);
+  assert (values_ldouble.f8 == f8);
+  assert (values_ldouble.f9 == f9);
+  assert (values_ldouble.f10 == f10);
+  assert (values_ldouble.f11 == f11);
+  assert (values_ldouble.f12 == f12);
+  assert (values_ldouble.f13 == f13);
+  assert (values_ldouble.f14 == f14);
+  assert (values_ldouble.f15 == f15);
+  assert (values_ldouble.f16 == f16);
+  assert (values_ldouble.f17 == f17);
+  assert (values_ldouble.f18 == f18);
+  assert (values_ldouble.f19 == f19);
+
+}
+
+void
+fun_check_x87_passing_ldouble20_regs (ldouble f0 ATTRIBUTE_UNUSED, ldouble f1 ATTRIBUTE_UNUSED, ldouble f2 ATTRIBUTE_UNUSED, ldouble f3 ATTRIBUTE_UNUSED, ldouble f4 ATTRIBUTE_UNUSED, ldouble f5 ATTRIBUTE_UNUSED, ldouble f6 ATTRIBUTE_UNUSED, ldouble f7 ATTRIBUTE_UNUSED, ldouble f8 ATTRIBUTE_UNUSED, ldouble f9 ATTRIBUTE_UNUSED, ldouble f10 ATTRIBUTE_UNUSED, ldouble f11 ATTRIBUTE_UNUSED, ldouble f12 ATTRIBUTE_UNUSED, ldouble f13 ATTRIBUTE_UNUSED, ldouble f14 ATTRIBUTE_UNUSED, ldouble f15 ATTRIBUTE_UNUSED, ldouble f16 ATTRIBUTE_UNUSED, ldouble f17 ATTRIBUTE_UNUSED, ldouble f18 ATTRIBUTE_UNUSED, ldouble f19 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_ldouble_arguments;
+}
+
+#define def_check_float_passing8(_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _func1, _func2, TYPE) \
+  values_ ## TYPE .f0 = _f0; \
+  values_ ## TYPE .f1 = _f1; \
+  values_ ## TYPE .f2 = _f2; \
+  values_ ## TYPE .f3 = _f3; \
+  values_ ## TYPE .f4 = _f4; \
+  values_ ## TYPE .f5 = _f5; \
+  values_ ## TYPE .f6 = _f6; \
+  values_ ## TYPE .f7 = _f7; \
+  WRAP_CALL(_func1) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7); \
+  \
+  clear_float_registers; \
+  fregs.F0._ ## TYPE [0] = _f0; \
+  fregs.F1._ ## TYPE [0] = _f1; \
+  fregs.F2._ ## TYPE [0] = _f2; \
+  fregs.F3._ ## TYPE [0] = _f3; \
+  fregs.F4._ ## TYPE [0] = _f4; \
+  fregs.F5._ ## TYPE [0] = _f5; \
+  fregs.F6._ ## TYPE [0] = _f6; \
+  fregs.F7._ ## TYPE [0] = _f7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7);
+
+#define def_check_float_passing16(_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _func1, _func2, TYPE) \
+  values_ ## TYPE .f0 = _f0; \
+  values_ ## TYPE .f1 = _f1; \
+  values_ ## TYPE .f2 = _f2; \
+  values_ ## TYPE .f3 = _f3; \
+  values_ ## TYPE .f4 = _f4; \
+  values_ ## TYPE .f5 = _f5; \
+  values_ ## TYPE .f6 = _f6; \
+  values_ ## TYPE .f7 = _f7; \
+  values_ ## TYPE .f8 = _f8; \
+  values_ ## TYPE .f9 = _f9; \
+  values_ ## TYPE .f10 = _f10; \
+  values_ ## TYPE .f11 = _f11; \
+  values_ ## TYPE .f12 = _f12; \
+  values_ ## TYPE .f13 = _f13; \
+  values_ ## TYPE .f14 = _f14; \
+  values_ ## TYPE .f15 = _f15; \
+  WRAP_CALL(_func1) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15); \
+  \
+  clear_float_registers; \
+  fregs.F0._ ## TYPE [0] = _f0; \
+  fregs.F1._ ## TYPE [0] = _f1; \
+  fregs.F2._ ## TYPE [0] = _f2; \
+  fregs.F3._ ## TYPE [0] = _f3; \
+  fregs.F4._ ## TYPE [0] = _f4; \
+  fregs.F5._ ## TYPE [0] = _f5; \
+  fregs.F6._ ## TYPE [0] = _f6; \
+  fregs.F7._ ## TYPE [0] = _f7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15);
+
+#define def_check_float_passing20(_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _f16, _f17, _f18, _f19, _func1, _func2, TYPE) \
+  values_ ## TYPE .f0 = _f0; \
+  values_ ## TYPE .f1 = _f1; \
+  values_ ## TYPE .f2 = _f2; \
+  values_ ## TYPE .f3 = _f3; \
+  values_ ## TYPE .f4 = _f4; \
+  values_ ## TYPE .f5 = _f5; \
+  values_ ## TYPE .f6 = _f6; \
+  values_ ## TYPE .f7 = _f7; \
+  values_ ## TYPE .f8 = _f8; \
+  values_ ## TYPE .f9 = _f9; \
+  values_ ## TYPE .f10 = _f10; \
+  values_ ## TYPE .f11 = _f11; \
+  values_ ## TYPE .f12 = _f12; \
+  values_ ## TYPE .f13 = _f13; \
+  values_ ## TYPE .f14 = _f14; \
+  values_ ## TYPE .f15 = _f15; \
+  values_ ## TYPE .f16 = _f16; \
+  values_ ## TYPE .f17 = _f17; \
+  values_ ## TYPE .f18 = _f18; \
+  values_ ## TYPE .f19 = _f19; \
+  WRAP_CALL(_func1) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _f16, _f17, _f18, _f19); \
+  \
+  clear_float_registers; \
+  fregs.F0._ ## TYPE [0] = _f0; \
+  fregs.F1._ ## TYPE [0] = _f1; \
+  fregs.F2._ ## TYPE [0] = _f2; \
+  fregs.F3._ ## TYPE [0] = _f3; \
+  fregs.F4._ ## TYPE [0] = _f4; \
+  fregs.F5._ ## TYPE [0] = _f5; \
+  fregs.F6._ ## TYPE [0] = _f6; \
+  fregs.F7._ ## TYPE [0] = _f7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _f16, _f17, _f18, _f19);
+
+#define def_check_x87_passing8(_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _func1, _func2, TYPE) \
+  values_ ## TYPE .f0 = _f0; \
+  values_ ## TYPE .f1 = _f1; \
+  values_ ## TYPE .f2 = _f2; \
+  values_ ## TYPE .f3 = _f3; \
+  values_ ## TYPE .f4 = _f4; \
+  values_ ## TYPE .f5 = _f5; \
+  values_ ## TYPE .f6 = _f6; \
+  values_ ## TYPE .f7 = _f7; \
+  WRAP_CALL(_func1) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7); \
+  \
+  clear_x87_registers; \
+  num_fregs = 0; \
+  WRAP_CALL(_func2) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7);
+
+#define def_check_x87_passing16(_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _func1, _func2, TYPE) \
+  values_ ## TYPE .f0 = _f0; \
+  values_ ## TYPE .f1 = _f1; \
+  values_ ## TYPE .f2 = _f2; \
+  values_ ## TYPE .f3 = _f3; \
+  values_ ## TYPE .f4 = _f4; \
+  values_ ## TYPE .f5 = _f5; \
+  values_ ## TYPE .f6 = _f6; \
+  values_ ## TYPE .f7 = _f7; \
+  values_ ## TYPE .f8 = _f8; \
+  values_ ## TYPE .f9 = _f9; \
+  values_ ## TYPE .f10 = _f10; \
+  values_ ## TYPE .f11 = _f11; \
+  values_ ## TYPE .f12 = _f12; \
+  values_ ## TYPE .f13 = _f13; \
+  values_ ## TYPE .f14 = _f14; \
+  values_ ## TYPE .f15 = _f15; \
+  WRAP_CALL(_func1) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15); \
+  \
+  clear_x87_registers; \
+  num_fregs = 0; \
+  WRAP_CALL(_func2) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15);
+
+#define def_check_x87_passing20(_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _f16, _f17, _f18, _f19, _func1, _func2, TYPE) \
+  values_ ## TYPE .f0 = _f0; \
+  values_ ## TYPE .f1 = _f1; \
+  values_ ## TYPE .f2 = _f2; \
+  values_ ## TYPE .f3 = _f3; \
+  values_ ## TYPE .f4 = _f4; \
+  values_ ## TYPE .f5 = _f5; \
+  values_ ## TYPE .f6 = _f6; \
+  values_ ## TYPE .f7 = _f7; \
+  values_ ## TYPE .f8 = _f8; \
+  values_ ## TYPE .f9 = _f9; \
+  values_ ## TYPE .f10 = _f10; \
+  values_ ## TYPE .f11 = _f11; \
+  values_ ## TYPE .f12 = _f12; \
+  values_ ## TYPE .f13 = _f13; \
+  values_ ## TYPE .f14 = _f14; \
+  values_ ## TYPE .f15 = _f15; \
+  values_ ## TYPE .f16 = _f16; \
+  values_ ## TYPE .f17 = _f17; \
+  values_ ## TYPE .f18 = _f18; \
+  values_ ## TYPE .f19 = _f19; \
+  WRAP_CALL(_func1) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _f16, _f17, _f18, _f19); \
+  \
+  clear_x87_registers; \
+  num_fregs = 0; \
+  WRAP_CALL(_func2) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _f16, _f17, _f18, _f19);
+
+void
+test_floats_on_stack ()
+{
+  def_check_float_passing8(32, 33, 34, 35, 36, 37, 38, 39, fun_check_float_passing_float8_values, fun_check_float_passing_float8_regs, float);
+
+  def_check_float_passing16(32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, fun_check_float_passing_float16_values, fun_check_float_passing_float16_regs, float);
+}
+
+void
+test_too_many_floats ()
+{
+  def_check_float_passing20(32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, fun_check_float_passing_float20_values, fun_check_float_passing_float20_regs, float);
+}
+
+void
+test_doubles_on_stack ()
+{
+  def_check_float_passing8(32, 33, 34, 35, 36, 37, 38, 39, fun_check_float_passing_double8_values, fun_check_float_passing_double8_regs, double);
+
+  def_check_float_passing16(32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, fun_check_float_passing_double16_values, fun_check_float_passing_double16_regs, double);
+}
+
+void
+test_too_many_doubles ()
+{
+  def_check_float_passing20(32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, fun_check_float_passing_double20_values, fun_check_float_passing_double20_regs, double);
+}
+
+void
+test_long_doubles_on_stack ()
+{
+  def_check_x87_passing8(32, 33, 34, 35, 36, 37, 38, 39, fun_check_x87_passing_ldouble8_values, fun_check_x87_passing_ldouble8_regs, ldouble);
+}
+
+void
+test_too_many_long_doubles ()
+{
+  def_check_x87_passing20(32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, fun_check_x87_passing_ldouble20_values, fun_check_x87_passing_ldouble20_regs, ldouble);
+}
+
+void
+test_float128s_on_stack ()
+{
+}
+
+void
+test_too_many_float128s ()
+{
+}
+
+
+int
+main (void)
+{
+  test_floats_on_stack ();
+  test_too_many_floats ();
+  test_doubles_on_stack ();
+  test_too_many_doubles ();
+  test_long_doubles_on_stack ();
+  test_too_many_long_doubles ();
+  test_float128s_on_stack ();
+  test_too_many_float128s ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_integers.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_integers.c
new file mode 100644
index 000000000..d0d0f1fd2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_integers.c
@@ -0,0 +1,203 @@
+/* This is an autogenerated file. Do not edit.  */
+
+#include "defines.h"
+#include "macros.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+/* This struct holds values for argument checking.  */
+struct 
+{
+  int i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23;
+} values_int;
+
+struct 
+{
+  long i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23;
+} values_long;
+
+void
+fun_check_int_passing_int6_values (int i0 ATTRIBUTE_UNUSED, int i1 ATTRIBUTE_UNUSED, int i2 ATTRIBUTE_UNUSED, int i3 ATTRIBUTE_UNUSED, int i4 ATTRIBUTE_UNUSED, int i5 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_int.i0 == i0);
+  assert (values_int.i1 == i1);
+  assert (values_int.i2 == i2);
+  assert (values_int.i3 == i3);
+  assert (values_int.i4 == i4);
+  assert (values_int.i5 == i5);
+
+}
+
+void
+fun_check_int_passing_int6_regs (int i0 ATTRIBUTE_UNUSED, int i1 ATTRIBUTE_UNUSED, int i2 ATTRIBUTE_UNUSED, int i3 ATTRIBUTE_UNUSED, int i4 ATTRIBUTE_UNUSED, int i5 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_int_arguments;
+}
+
+void
+fun_check_int_passing_int12_values (int i0 ATTRIBUTE_UNUSED, int i1 ATTRIBUTE_UNUSED, int i2 ATTRIBUTE_UNUSED, int i3 ATTRIBUTE_UNUSED, int i4 ATTRIBUTE_UNUSED, int i5 ATTRIBUTE_UNUSED, int i6 ATTRIBUTE_UNUSED, int i7 ATTRIBUTE_UNUSED, int i8 ATTRIBUTE_UNUSED, int i9 ATTRIBUTE_UNUSED, int i10 ATTRIBUTE_UNUSED, int i11 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_int.i0 == i0);
+  assert (values_int.i1 == i1);
+  assert (values_int.i2 == i2);
+  assert (values_int.i3 == i3);
+  assert (values_int.i4 == i4);
+  assert (values_int.i5 == i5);
+  assert (values_int.i6 == i6);
+  assert (values_int.i7 == i7);
+  assert (values_int.i8 == i8);
+  assert (values_int.i9 == i9);
+  assert (values_int.i10 == i10);
+  assert (values_int.i11 == i11);
+
+}
+
+void
+fun_check_int_passing_int12_regs (int i0 ATTRIBUTE_UNUSED, int i1 ATTRIBUTE_UNUSED, int i2 ATTRIBUTE_UNUSED, int i3 ATTRIBUTE_UNUSED, int i4 ATTRIBUTE_UNUSED, int i5 ATTRIBUTE_UNUSED, int i6 ATTRIBUTE_UNUSED, int i7 ATTRIBUTE_UNUSED, int i8 ATTRIBUTE_UNUSED, int i9 ATTRIBUTE_UNUSED, int i10 ATTRIBUTE_UNUSED, int i11 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_int_arguments;
+}
+
+void
+fun_check_int_passing_long6_values (long i0 ATTRIBUTE_UNUSED, long i1 ATTRIBUTE_UNUSED, long i2 ATTRIBUTE_UNUSED, long i3 ATTRIBUTE_UNUSED, long i4 ATTRIBUTE_UNUSED, long i5 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_long.i0 == i0);
+  assert (values_long.i1 == i1);
+  assert (values_long.i2 == i2);
+  assert (values_long.i3 == i3);
+  assert (values_long.i4 == i4);
+  assert (values_long.i5 == i5);
+
+}
+
+void
+fun_check_int_passing_long6_regs (long i0 ATTRIBUTE_UNUSED, long i1 ATTRIBUTE_UNUSED, long i2 ATTRIBUTE_UNUSED, long i3 ATTRIBUTE_UNUSED, long i4 ATTRIBUTE_UNUSED, long i5 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_long_arguments;
+}
+
+void
+fun_check_int_passing_long12_values (long i0 ATTRIBUTE_UNUSED, long i1 ATTRIBUTE_UNUSED, long i2 ATTRIBUTE_UNUSED, long i3 ATTRIBUTE_UNUSED, long i4 ATTRIBUTE_UNUSED, long i5 ATTRIBUTE_UNUSED, long i6 ATTRIBUTE_UNUSED, long i7 ATTRIBUTE_UNUSED, long i8 ATTRIBUTE_UNUSED, long i9 ATTRIBUTE_UNUSED, long i10 ATTRIBUTE_UNUSED, long i11 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_long.i0 == i0);
+  assert (values_long.i1 == i1);
+  assert (values_long.i2 == i2);
+  assert (values_long.i3 == i3);
+  assert (values_long.i4 == i4);
+  assert (values_long.i5 == i5);
+  assert (values_long.i6 == i6);
+  assert (values_long.i7 == i7);
+  assert (values_long.i8 == i8);
+  assert (values_long.i9 == i9);
+  assert (values_long.i10 == i10);
+  assert (values_long.i11 == i11);
+
+}
+
+void
+fun_check_int_passing_long12_regs (long i0 ATTRIBUTE_UNUSED, long i1 ATTRIBUTE_UNUSED, long i2 ATTRIBUTE_UNUSED, long i3 ATTRIBUTE_UNUSED, long i4 ATTRIBUTE_UNUSED, long i5 ATTRIBUTE_UNUSED, long i6 ATTRIBUTE_UNUSED, long i7 ATTRIBUTE_UNUSED, long i8 ATTRIBUTE_UNUSED, long i9 ATTRIBUTE_UNUSED, long i10 ATTRIBUTE_UNUSED, long i11 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_long_arguments;
+}
+
+#define def_check_int_passing6(_i0, _i1, _i2, _i3, _i4, _i5, _func1, _func2, TYPE) \
+  values_ ## TYPE .i0 = _i0; \
+  values_ ## TYPE .i1 = _i1; \
+  values_ ## TYPE .i2 = _i2; \
+  values_ ## TYPE .i3 = _i3; \
+  values_ ## TYPE .i4 = _i4; \
+  values_ ## TYPE .i5 = _i5; \
+  WRAP_CALL(_func1) (_i0, _i1, _i2, _i3, _i4, _i5); \
+  \
+  clear_int_registers; \
+  iregs.I0 = _i0; \
+  iregs.I1 = _i1; \
+  iregs.I2 = _i2; \
+  iregs.I3 = _i3; \
+  iregs.I4 = _i4; \
+  iregs.I5 = _i5; \
+  num_iregs = 6; \
+  WRAP_CALL(_func2) (_i0, _i1, _i2, _i3, _i4, _i5);
+
+#define def_check_int_passing12(_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _func1, _func2, TYPE) \
+  values_ ## TYPE .i0 = _i0; \
+  values_ ## TYPE .i1 = _i1; \
+  values_ ## TYPE .i2 = _i2; \
+  values_ ## TYPE .i3 = _i3; \
+  values_ ## TYPE .i4 = _i4; \
+  values_ ## TYPE .i5 = _i5; \
+  values_ ## TYPE .i6 = _i6; \
+  values_ ## TYPE .i7 = _i7; \
+  values_ ## TYPE .i8 = _i8; \
+  values_ ## TYPE .i9 = _i9; \
+  values_ ## TYPE .i10 = _i10; \
+  values_ ## TYPE .i11 = _i11; \
+  WRAP_CALL(_func1) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11); \
+  \
+  clear_int_registers; \
+  iregs.I0 = _i0; \
+  iregs.I1 = _i1; \
+  iregs.I2 = _i2; \
+  iregs.I3 = _i3; \
+  iregs.I4 = _i4; \
+  iregs.I5 = _i5; \
+  num_iregs = 6; \
+  WRAP_CALL(_func2) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11);
+
+void
+test_ints_on_stack ()
+{
+  def_check_int_passing6(32, 33, 34, 35, 36, 37, fun_check_int_passing_int6_values, fun_check_int_passing_int6_regs, int);
+}
+
+void
+test_too_many_ints ()
+{
+  def_check_int_passing12(32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, fun_check_int_passing_int12_values, fun_check_int_passing_int12_regs, int);
+}
+
+void
+test_longs_on_stack ()
+{
+  def_check_int_passing6(32, 33, 34, 35, 36, 37, fun_check_int_passing_long6_values, fun_check_int_passing_long6_regs, long);
+}
+
+void
+test_too_many_longs ()
+{
+  def_check_int_passing12(32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, fun_check_int_passing_long12_values, fun_check_int_passing_long12_regs, long);
+}
+
+void
+test_int128s_on_stack ()
+{
+}
+
+void
+test_too_many_int128s ()
+{
+}
+
+
+int
+main (void)
+{
+  test_ints_on_stack ();
+  test_too_many_ints ();
+  test_longs_on_stack ();
+  test_too_many_longs ();
+  test_int128s_on_stack ();
+  test_too_many_int128s ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_m64m128.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_m64m128.c
new file mode 100644
index 000000000..237435c4e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_m64m128.c
@@ -0,0 +1,249 @@
+#include <stdio.h>
+#include "defines.h"
+#include "macros.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+/* This struct holds values for argument checking.  */
+struct 
+{
+  XMM_T i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23;
+} values;
+
+char *pass;
+int failed = 0;
+
+#undef assert
+#define assert(c) do { \
+  if (!(c)) {failed++; printf ("failed %s\n", pass); } \
+} while (0)
+
+#define compare(X1,X2,T) do { \
+  assert (memcmp (&X1, &X2, sizeof (T)) == 0); \
+} while (0)
+
+void
+fun_check_passing_m64_8_values (__m64 i0 ATTRIBUTE_UNUSED, __m64 i1 ATTRIBUTE_UNUSED, __m64 i2 ATTRIBUTE_UNUSED, __m64 i3 ATTRIBUTE_UNUSED, __m64 i4 ATTRIBUTE_UNUSED, __m64 i5 ATTRIBUTE_UNUSED, __m64 i6 ATTRIBUTE_UNUSED, __m64 i7 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  compare (values.i0, i0, __m64);
+  compare (values.i1, i1, __m64);
+  compare (values.i2, i2, __m64);
+  compare (values.i3, i3, __m64);
+  compare (values.i4, i4, __m64);
+  compare (values.i5, i5, __m64);
+  compare (values.i6, i6, __m64);
+  compare (values.i7, i7, __m64);
+}
+
+void
+fun_check_passing_m64_8_regs (__m64 i0 ATTRIBUTE_UNUSED, __m64 i1 ATTRIBUTE_UNUSED, __m64 i2 ATTRIBUTE_UNUSED, __m64 i3 ATTRIBUTE_UNUSED, __m64 i4 ATTRIBUTE_UNUSED, __m64 i5 ATTRIBUTE_UNUSED, __m64 i6 ATTRIBUTE_UNUSED, __m64 i7 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m64_arguments;
+}
+
+void
+fun_check_passing_m64_20_values (__m64 i0 ATTRIBUTE_UNUSED, __m64 i1 ATTRIBUTE_UNUSED, __m64 i2 ATTRIBUTE_UNUSED, __m64 i3 ATTRIBUTE_UNUSED, __m64 i4 ATTRIBUTE_UNUSED, __m64 i5 ATTRIBUTE_UNUSED, __m64 i6 ATTRIBUTE_UNUSED, __m64 i7 ATTRIBUTE_UNUSED, __m64 i8 ATTRIBUTE_UNUSED, __m64 i9 ATTRIBUTE_UNUSED, __m64 i10 ATTRIBUTE_UNUSED, __m64 i11 ATTRIBUTE_UNUSED, __m64 i12 ATTRIBUTE_UNUSED, __m64 i13 ATTRIBUTE_UNUSED, __m64 i14 ATTRIBUTE_UNUSED, __m64 i15 ATTRIBUTE_UNUSED, __m64 i16 ATTRIBUTE_UNUSED, __m64 i17 ATTRIBUTE_UNUSED, __m64 i18 ATTRIBUTE_UNUSED, __m64 i19 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  compare (values.i0 , i0, __m64);
+  compare (values.i1 , i1, __m64);
+  compare (values.i2 , i2, __m64);
+  compare (values.i3 , i3, __m64);
+  compare (values.i4 , i4, __m64);
+  compare (values.i5 , i5, __m64);
+  compare (values.i6 , i6, __m64);
+  compare (values.i7 , i7, __m64);
+  compare (values.i8 , i8, __m64);
+  compare (values.i9 , i9, __m64);
+  compare (values.i10 , i10, __m64);
+  compare (values.i11 , i11, __m64);
+  compare (values.i12 , i12, __m64);
+  compare (values.i13 , i13, __m64);
+  compare (values.i14 , i14, __m64);
+  compare (values.i15 , i15, __m64);
+  compare (values.i16 , i16, __m64);
+  compare (values.i17 , i17, __m64);
+  compare (values.i18 , i18, __m64);
+  compare (values.i19 , i19, __m64);
+}
+
+void
+fun_check_passing_m64_20_regs (__m64 i0 ATTRIBUTE_UNUSED, __m64 i1 ATTRIBUTE_UNUSED, __m64 i2 ATTRIBUTE_UNUSED, __m64 i3 ATTRIBUTE_UNUSED, __m64 i4 ATTRIBUTE_UNUSED, __m64 i5 ATTRIBUTE_UNUSED, __m64 i6 ATTRIBUTE_UNUSED, __m64 i7 ATTRIBUTE_UNUSED, __m64 i8 ATTRIBUTE_UNUSED, __m64 i9 ATTRIBUTE_UNUSED, __m64 i10 ATTRIBUTE_UNUSED, __m64 i11 ATTRIBUTE_UNUSED, __m64 i12 ATTRIBUTE_UNUSED, __m64 i13 ATTRIBUTE_UNUSED, __m64 i14 ATTRIBUTE_UNUSED, __m64 i15 ATTRIBUTE_UNUSED, __m64 i16 ATTRIBUTE_UNUSED, __m64 i17 ATTRIBUTE_UNUSED, __m64 i18 ATTRIBUTE_UNUSED, __m64 i19 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m64_arguments;
+}
+
+void
+fun_check_passing_m128_8_values (__m128 i0 ATTRIBUTE_UNUSED, __m128 i1 ATTRIBUTE_UNUSED, __m128 i2 ATTRIBUTE_UNUSED, __m128 i3 ATTRIBUTE_UNUSED, __m128 i4 ATTRIBUTE_UNUSED, __m128 i5 ATTRIBUTE_UNUSED, __m128 i6 ATTRIBUTE_UNUSED, __m128 i7 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  compare (values.i0, i0, __m128);
+  compare (values.i1, i1, __m128);
+  compare (values.i2, i2, __m128);
+  compare (values.i3, i3, __m128);
+  compare (values.i4, i4, __m128);
+  compare (values.i5, i5, __m128);
+  compare (values.i6, i6, __m128);
+  compare (values.i7, i7, __m128);
+}
+
+void
+fun_check_passing_m128_8_regs (__m128 i0 ATTRIBUTE_UNUSED, __m128 i1 ATTRIBUTE_UNUSED, __m128 i2 ATTRIBUTE_UNUSED, __m128 i3 ATTRIBUTE_UNUSED, __m128 i4 ATTRIBUTE_UNUSED, __m128 i5 ATTRIBUTE_UNUSED, __m128 i6 ATTRIBUTE_UNUSED, __m128 i7 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m128_arguments;
+}
+
+void
+fun_check_passing_m128_20_values (__m128 i0 ATTRIBUTE_UNUSED, __m128 i1 ATTRIBUTE_UNUSED, __m128 i2 ATTRIBUTE_UNUSED, __m128 i3 ATTRIBUTE_UNUSED, __m128 i4 ATTRIBUTE_UNUSED, __m128 i5 ATTRIBUTE_UNUSED, __m128 i6 ATTRIBUTE_UNUSED, __m128 i7 ATTRIBUTE_UNUSED, __m128 i8 ATTRIBUTE_UNUSED, __m128 i9 ATTRIBUTE_UNUSED, __m128 i10 ATTRIBUTE_UNUSED, __m128 i11 ATTRIBUTE_UNUSED, __m128 i12 ATTRIBUTE_UNUSED, __m128 i13 ATTRIBUTE_UNUSED, __m128 i14 ATTRIBUTE_UNUSED, __m128 i15 ATTRIBUTE_UNUSED, __m128 i16 ATTRIBUTE_UNUSED, __m128 i17 ATTRIBUTE_UNUSED, __m128 i18 ATTRIBUTE_UNUSED, __m128 i19 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  compare (values.i0 , i0, __m128);
+  compare (values.i1 , i1, __m128);
+  compare (values.i2 , i2, __m128);
+  compare (values.i3 , i3, __m128);
+  compare (values.i4 , i4, __m128);
+  compare (values.i5 , i5, __m128);
+  compare (values.i6 , i6, __m128);
+  compare (values.i7 , i7, __m128);
+  compare (values.i8 , i8, __m128);
+  compare (values.i9 , i9, __m128);
+  compare (values.i10 , i10, __m128);
+  compare (values.i11 , i11, __m128);
+  compare (values.i12 , i12, __m128);
+  compare (values.i13 , i13, __m128);
+  compare (values.i14 , i14, __m128);
+  compare (values.i15 , i15, __m128);
+  compare (values.i16 , i16, __m128);
+  compare (values.i17 , i17, __m128);
+  compare (values.i18 , i18, __m128);
+  compare (values.i19 , i19, __m128);
+}
+
+void
+fun_check_passing_m128_20_regs (__m128 i0 ATTRIBUTE_UNUSED, __m128 i1 ATTRIBUTE_UNUSED, __m128 i2 ATTRIBUTE_UNUSED, __m128 i3 ATTRIBUTE_UNUSED, __m128 i4 ATTRIBUTE_UNUSED, __m128 i5 ATTRIBUTE_UNUSED, __m128 i6 ATTRIBUTE_UNUSED, __m128 i7 ATTRIBUTE_UNUSED, __m128 i8 ATTRIBUTE_UNUSED, __m128 i9 ATTRIBUTE_UNUSED, __m128 i10 ATTRIBUTE_UNUSED, __m128 i11 ATTRIBUTE_UNUSED, __m128 i12 ATTRIBUTE_UNUSED, __m128 i13 ATTRIBUTE_UNUSED, __m128 i14 ATTRIBUTE_UNUSED, __m128 i15 ATTRIBUTE_UNUSED, __m128 i16 ATTRIBUTE_UNUSED, __m128 i17 ATTRIBUTE_UNUSED, __m128 i18 ATTRIBUTE_UNUSED, __m128 i19 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m128_arguments;
+}
+
+
+#define def_check_int_passing8(_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _func1, _func2, TYPE) \
+  values.i0.TYPE[0] = _i0; \
+  values.i1.TYPE[0] = _i1; \
+  values.i2.TYPE[0] = _i2; \
+  values.i3.TYPE[0] = _i3; \
+  values.i4.TYPE[0] = _i4; \
+  values.i5.TYPE[0] = _i5; \
+  values.i6.TYPE[0] = _i6; \
+  values.i7.TYPE[0] = _i7; \
+  WRAP_CALL(_func1) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7); \
+  \
+  clear_float_registers; \
+  fregs.F0.TYPE[0] = _i0; \
+  fregs.F1.TYPE[0] = _i1; \
+  fregs.F2.TYPE[0] = _i2; \
+  fregs.F3.TYPE[0] = _i3; \
+  fregs.F4.TYPE[0] = _i4; \
+  fregs.F5.TYPE[0] = _i5; \
+  fregs.F6.TYPE[0] = _i6; \
+  fregs.F7.TYPE[0] = _i7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7);
+
+#define def_check_int_passing20(_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _i12, _i13, _i14, _i15, _i16, _i17, _i18, _i19, _func1, _func2, TYPE) \
+  values.i0.TYPE[0] = _i0; \
+  values.i1.TYPE[0] = _i1; \
+  values.i2.TYPE[0] = _i2; \
+  values.i3.TYPE[0] = _i3; \
+  values.i4.TYPE[0] = _i4; \
+  values.i5.TYPE[0] = _i5; \
+  values.i6.TYPE[0] = _i6; \
+  values.i7.TYPE[0] = _i7; \
+  values.i8.TYPE[0] = _i8; \
+  values.i9.TYPE[0] = _i9; \
+  values.i10.TYPE[0] = _i10; \
+  values.i11.TYPE[0] = _i11; \
+  values.i12.TYPE[0] = _i12; \
+  values.i13.TYPE[0] = _i13; \
+  values.i14.TYPE[0] = _i14; \
+  values.i15.TYPE[0] = _i15; \
+  values.i16.TYPE[0] = _i16; \
+  values.i17.TYPE[0] = _i17; \
+  values.i18.TYPE[0] = _i18; \
+  values.i19.TYPE[0] = _i19; \
+  WRAP_CALL(_func1) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _i12, _i13, _i14, _i15, _i16, _i17, _i18, _i19); \
+  \
+  clear_float_registers; \
+  fregs.F0.TYPE[0] = _i0; \
+  fregs.F1.TYPE[0] = _i1; \
+  fregs.F2.TYPE[0] = _i2; \
+  fregs.F3.TYPE[0] = _i3; \
+  fregs.F4.TYPE[0] = _i4; \
+  fregs.F5.TYPE[0] = _i5; \
+  fregs.F6.TYPE[0] = _i6; \
+  fregs.F7.TYPE[0] = _i7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _i12, _i13, _i14, _i15, _i16, _i17, _i18, _i19);
+
+void
+test_m64_on_stack ()
+{
+  __m64 x[8];
+  int i;
+  for (i = 0; i < 8; i++)
+    x[i] = (__m64){32+i, 0};
+  pass = "m64-8";
+  def_check_int_passing8(x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], fun_check_passing_m64_8_values, fun_check_passing_m64_8_regs, _m64);
+}
+
+void
+test_too_many_m64 ()
+{
+  __m64 x[20];
+  int i;
+  for (i = 0; i < 20; i++)
+    x[i] = (__m64){32+i, 0};
+  pass = "m64-20";
+  def_check_int_passing20(x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], x[8], x[9], x[10], x[11], x[12], x[13], x[14], x[15], x[16], x[17], x[18], x[19], fun_check_passing_m64_20_values, fun_check_passing_m64_20_regs, _m64);
+}
+
+void
+test_m128_on_stack ()
+{
+  __m128 x[8];
+  int i;
+  for (i = 0; i < 8; i++)
+    x[i] = (__m128){32+i, 0, 0, 0};
+  pass = "m128-8";
+  def_check_int_passing8(x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], fun_check_passing_m128_8_values, fun_check_passing_m128_8_regs, _m128);
+}
+
+void
+test_too_many_m128 ()
+{
+  __m128 x[20];
+  int i;
+  for (i = 0; i < 20; i++)
+    x[i] = (__m128){32+i, 0, 0, 0};
+  pass = "m128-20";
+  def_check_int_passing20(x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], x[8], x[9], x[10], x[11], x[12], x[13], x[14], x[15], x[16], x[17], x[18], x[19], fun_check_passing_m128_20_values, fun_check_passing_m128_20_regs, _m128);
+}
+
+int
+main (void)
+{
+  test_m64_on_stack ();
+  test_too_many_m64 ();
+  test_m128_on_stack ();
+  test_too_many_m128 ();
+  if (failed)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_structs.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_structs.c
new file mode 100644
index 000000000..299bc80ca
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_structs.c
@@ -0,0 +1,261 @@
+/* This tests passing of structs. */
+
+#include "defines.h"
+#include "args.h"
+#include <complex.h>
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+struct int_struct
+{
+  int i;
+};
+
+struct long_struct
+{
+  long l;
+};
+
+struct long2_struct
+{
+  long l1, l2;
+};
+
+struct long3_struct
+{
+  long l1, l2, l3;
+};
+
+
+/* Check that the struct is passed as the individual members in iregs.  */
+void
+check_struct_passing1 (struct int_struct is ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+void
+check_struct_passing2 (struct long_struct ls ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+void
+check_struct_passing3 (struct long2_struct ls ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+void
+check_struct_passing4 (struct long3_struct ls ATTRIBUTE_UNUSED)
+{
+  /* Check the passing on the stack by comparing the address of the
+     stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&ls.l1 == rsp+8);
+  assert ((unsigned long)&ls.l2 == rsp+16);
+  assert ((unsigned long)&ls.l3 == rsp+24);
+}
+
+#ifdef CHECK_M64_M128
+struct m128_struct
+{
+  __m128 x;
+};
+
+struct m128_2_struct
+{
+  __m128 x1, x2;
+};
+
+/* Check that the struct is passed as the individual members in fregs.  */
+void
+check_struct_passing5 (struct m128_struct ms1 ATTRIBUTE_UNUSED,
+		       struct m128_struct ms2 ATTRIBUTE_UNUSED,
+		       struct m128_struct ms3 ATTRIBUTE_UNUSED,
+		       struct m128_struct ms4 ATTRIBUTE_UNUSED,
+		       struct m128_struct ms5 ATTRIBUTE_UNUSED,
+		       struct m128_struct ms6 ATTRIBUTE_UNUSED,
+		       struct m128_struct ms7 ATTRIBUTE_UNUSED,
+		       struct m128_struct ms8 ATTRIBUTE_UNUSED)
+{
+  check_m128_arguments;
+}
+
+void
+check_struct_passing6 (struct m128_2_struct ms ATTRIBUTE_UNUSED)
+{
+  /* Check the passing on the stack by comparing the address of the
+     stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&ms.x1 == rsp+8);
+  assert ((unsigned long)&ms.x2 == rsp+24);
+}
+#endif
+
+struct flex1_struct
+{
+  long i;
+  long flex[];
+};
+
+struct flex2_struct
+{
+  long i;
+  long flex[0];
+};
+
+void
+check_struct_passing7 (struct flex1_struct is ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+void
+check_struct_passing8 (struct flex2_struct is ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+struct complex1_struct
+{
+  int c;
+  __complex__ float x;
+};
+
+struct complex1a_struct
+{
+  long l;
+  float f;
+};
+
+struct complex2_struct
+{
+  int c;
+  __complex__ float x;
+  float y;
+};
+
+struct complex2a_struct
+{
+  long l;
+  double d;
+};
+
+void
+check_struct_passing9 (struct complex1_struct is ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+  check_float_arguments;
+}
+
+void
+check_struct_passing10 (struct complex2_struct is ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+  check_double_arguments;
+}
+
+static struct flex1_struct f1s = { 60, { } };
+static struct flex2_struct f2s = { 61, { } };
+
+int
+main (void)
+{
+  struct int_struct is = { 48 };
+  struct long_struct ls = { 49 };
+#ifdef CHECK_LARGER_STRUCTS
+  struct long2_struct l2s = { 50, 51 };
+  struct long3_struct l3s = { 52, 53, 54 };
+#endif
+#ifdef CHECK_M64_M128
+  struct m128_struct m128s[8];
+  struct m128_2_struct m128_2s = { 
+      { 48.394, 39.3, -397.9, 3484.9 },
+      { -8.394, -93.3, 7.9, 84.94 }
+  };
+  int i;
+#endif
+  struct complex1_struct c1s = { 4, ( -13.4 + 3.5*I ) };
+  union
+    {
+      struct complex1_struct c;
+      struct complex1a_struct u;
+    } c1u;
+  struct complex2_struct c2s = { 4, ( -13.4 + 3.5*I ), -34.5 };
+  union
+    {
+      struct complex2_struct c;
+      struct complex2a_struct u;
+    } c2u;
+
+  clear_struct_registers;
+  iregs.I0 = is.i;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  WRAP_CALL (check_struct_passing1)(is);
+
+  clear_struct_registers;
+  iregs.I0 = ls.l;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  WRAP_CALL (check_struct_passing2)(ls);
+
+#ifdef CHECK_LARGER_STRUCTS
+  clear_struct_registers;
+  iregs.I0 = l2s.l1;
+  iregs.I1 = l2s.l2;
+  num_iregs = 2;
+  clear_int_hardware_registers;
+  WRAP_CALL (check_struct_passing3)(l2s);
+  WRAP_CALL (check_struct_passing4)(l3s);
+#endif
+
+#ifdef CHECK_M64_M128
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    {
+      m128s[i].x = (__m128){32+i, 0, i, 0};
+      fregs.xmm0._m128[i] = m128s[i].x;
+    }
+  num_fregs = 8;
+  clear_float_hardware_registers;
+  WRAP_CALL (check_struct_passing5)(m128s[0], m128s[1], m128s[2], m128s[3],
+				    m128s[4], m128s[5], m128s[6], m128s[7]);
+  WRAP_CALL (check_struct_passing6)(m128_2s);
+#endif
+
+  clear_struct_registers;
+  iregs.I0 = f1s.i;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  WRAP_CALL (check_struct_passing7)(f1s);
+
+  clear_struct_registers;
+  iregs.I0 = f2s.i;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  WRAP_CALL (check_struct_passing8)(f2s);
+
+  clear_struct_registers;
+  c1u.c = c1s;
+  iregs.I0 = c1u.u.l;
+  num_iregs = 1;
+  fregs.xmm0._float [0] = c1u.u.f;
+  num_fregs = 1;
+  clear_int_hardware_registers;
+  clear_float_hardware_registers;
+  WRAP_CALL (check_struct_passing9)(c1s);
+
+  clear_struct_registers;
+  c2u.c = c2s;
+  iregs.I0 = c2u.u.l;
+  num_iregs = 1;
+  fregs.xmm0._double[0] = c2u.u.d;
+  num_fregs = 1;
+  clear_int_hardware_registers;
+  clear_float_hardware_registers;
+  WRAP_CALL (check_struct_passing10)(c2s);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_structs_and_unions.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_structs_and_unions.c
new file mode 100644
index 000000000..5b40196d4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_structs_and_unions.c
@@ -0,0 +1,95 @@
+/* This tests passing of structs. Only integers are tested.  */
+
+#include "defines.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+struct int_struct
+{
+  int i;
+};
+
+struct long_struct
+{
+  long l;
+};
+
+struct long2_struct
+{
+  long l1, l2;
+};
+
+struct long3_struct
+{
+  long l1, l2, l3;
+};
+
+union un1
+{
+  char c;
+  int i;
+};
+
+union un2
+{
+  char c1;
+  long l;
+  char c2;
+};
+
+union un3
+{
+  struct int_struct is;
+  struct long_struct ls;
+  union un1 un;
+};
+
+
+void
+check_mixed_passing1 (char c1 ATTRIBUTE_UNUSED, struct int_struct is ATTRIBUTE_UNUSED, char c2 ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+void
+check_mixed_passing2 (char c1 ATTRIBUTE_UNUSED, struct long3_struct ls ATTRIBUTE_UNUSED, char c2 ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+
+  /* Check the passing on the stack by comparing the address of the
+     stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&ls.l1 == rsp+8);
+  assert ((unsigned long)&ls.l2 == rsp+16);
+  assert ((unsigned long)&ls.l3 == rsp+24);
+}
+
+int
+main (void)
+{
+  struct int_struct is = { 64 };
+#ifdef CHECK_LARGER_STRUCTS
+  struct long3_struct l3s = { 65, 66, 67 };
+#endif
+
+  clear_struct_registers;
+  iregs.I0 = 8;
+  iregs.I1 = 64;
+  iregs.I2 = 9;
+  num_iregs = 3;
+  clear_int_hardware_registers;
+  WRAP_CALL (check_mixed_passing1)(8, is, 9);
+
+#ifdef CHECK_LARGER_STRUCTS 
+  clear_struct_registers;
+  iregs.I0 = 10;
+  iregs.I1 = 11;
+  num_iregs = 2;
+  clear_int_hardware_registers;
+  WRAP_CALL (check_mixed_passing2)(10, l3s, 11);
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_unions.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_unions.c
new file mode 100644
index 000000000..1e3e85fdb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_passing_unions.c
@@ -0,0 +1,229 @@
+/* This tests passing of structs.  */
+
+#include "defines.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+struct int_struct
+{
+  int i;
+};
+
+struct long_struct
+{
+  long l;
+};
+
+union un1
+{
+  char c;
+  int i;
+};
+
+union un2
+{
+  char c1;
+  long l;
+  char c2;
+};
+
+union un3
+{
+  struct int_struct is;
+  struct long_struct ls;
+  union un1 un;
+};
+
+
+void
+check_union_passing1(union un1 u ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+void
+check_union_passing2(union un2 u1 ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+void
+check_union_passing3(union un3 u ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+#define check_union_passing1 WRAP_CALL(check_union_passing1)
+#define check_union_passing2 WRAP_CALL(check_union_passing2)
+#define check_union_passing3 WRAP_CALL(check_union_passing3)
+
+#ifdef CHECK_M64_M128
+union un4
+{
+  __m128 x;
+  float f;
+};
+
+union un5
+{
+  __m128 x;
+  long i;
+};
+
+void
+check_union_passing4(union un4 u1 ATTRIBUTE_UNUSED,
+		     union un4 u2 ATTRIBUTE_UNUSED,
+		     union un4 u3 ATTRIBUTE_UNUSED,
+		     union un4 u4 ATTRIBUTE_UNUSED,
+		     union un4 u5 ATTRIBUTE_UNUSED,
+		     union un4 u6 ATTRIBUTE_UNUSED,
+		     union un4 u7 ATTRIBUTE_UNUSED,
+		     union un4 u8 ATTRIBUTE_UNUSED)
+{
+  check_m128_arguments;
+}
+
+void
+check_union_passing5(union un5 u ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+  check_vector_arguments(m128, 8);
+}
+
+#define check_union_passing4 WRAP_CALL(check_union_passing4)
+#define check_union_passing5 WRAP_CALL(check_union_passing5)
+#endif
+
+union un6
+{
+  long double ld;
+  int i;
+};
+
+
+void
+check_union_passing6(union un6 u ATTRIBUTE_UNUSED)
+{
+  /* Check the passing on the stack by comparing the address of the
+     stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&u.ld == rsp+8);
+  assert ((unsigned long)&u.i == rsp+8);
+}
+
+#define check_union_passing6 WRAP_CALL(check_union_passing6)
+
+int
+main (void)
+{
+  union un1 u1;
+#ifdef CHECK_LARGER_UNION_PASSING
+  union un2 u2;
+  union un3 u3;
+  struct int_struct is;
+  struct long_struct ls;
+#endif /* CHECK_LARGER_UNION_PASSING */
+#ifdef CHECK_M64_M128
+  union un4 u4[8];
+  union un5 u5 = { { 48.394, 39.3, -397.9, 3484.9 } };
+  int i;
+#endif
+  union un6 u6;
+
+  /* Check a union with char, int.  */
+  clear_struct_registers;
+  u1.i = 0;  /* clear the struct to not have high bits left */
+  u1.c = 32;
+  iregs.I0 = 32;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing1(u1);
+  u1.i = 0;  /* clear the struct to not have high bits left */
+  u1.i = 33;
+  iregs.I0 = 33;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing1(u1);
+
+  /* Check a union with char, long, char.  */
+#ifdef CHECK_LARGER_UNION_PASSING
+  clear_struct_registers;
+  u2.l = 0;  /* clear the struct to not have high bits left */
+  u2.c1 = 34;
+  iregs.I0 = 34;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing2(u2);
+  u2.l = 0;  /* clear the struct to not have high bits left */
+  u2.l = 35;
+  iregs.I0 = 35;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing2(u2);
+  u2.l = 0;  /* clear the struct to not have high bits left */
+  u2.c2 = 36;
+  iregs.I0 = 36;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing2(u2);
+
+  /* check a union containing two structs and a union.  */
+  clear_struct_registers;
+  is.i = 37;
+  u3.ls.l = 0;  /* clear the struct to not have high bits left */
+  u3.is = is;
+  iregs.I0 = 37;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing3(u3);
+  ls.l = 38;
+  u3.ls.l = 0;  /* clear the struct to not have high bits left */
+  u3.ls = ls;
+  iregs.I0 = 38;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing3(u3);
+  u1.c = 39;
+  u3.ls.l = 0;  /* clear the struct to not have high bits left */
+  u3.un = u1;
+  iregs.I0 = 39;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing3(u3);
+  u1.i = 40;
+  u3.ls.l = 0;  /* clear the struct to not have high bits left */
+  u3.un = u1;
+  iregs.I0 = 40;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing3(u3);
+#endif /* CHECK_LARGER_UNION_PASSING */
+
+#ifdef CHECK_M64_M128
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    {
+      u4[i].x = (__m128){32+i, 0, i, 0};
+      fregs.xmm0._m128[i] = u4[i].x;
+    }
+  num_fregs = 8;
+  clear_float_hardware_registers;
+  check_union_passing4(u4[0], u4[1], u4[2], u4[3],
+		       u4[4], u4[5], u4[6], u4[7]);
+
+  clear_struct_registers;
+  fregs.xmm0._m128[0] = u5.x;
+  num_fregs = 1;
+  num_iregs = 1;
+  iregs.I0 = u5.i;
+  clear_float_hardware_registers;
+  check_union_passing5(u5);
+#endif
+
+  u6.i = 2;
+  check_union_passing6(u6);
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_struct_returning.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_struct_returning.c
new file mode 100644
index 000000000..ef8d32904
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_struct_returning.c
@@ -0,0 +1,230 @@
+/* This tests returning of structures.  */
+
+#include <stdio.h>
+#include "defines.h"
+#include "macros.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+int current_test;
+int num_failed = 0;
+
+#undef assert
+#define assert(test) do { if (!(test)) {fprintf (stderr, "failed in test %d\n", current_test); num_failed++; } } while (0)
+
+#define xmm0f xmm_regs[0]._float
+#define xmm0d xmm_regs[0]._double
+#define xmm1f xmm_regs[1]._float
+#define xmm1d xmm_regs[1]._double
+
+typedef enum {
+  INT = 0,
+  SSE_F,
+  SSE_D,
+  X87,
+  MEM,
+  INT_SSE,
+  SSE_INT,
+  SSE_F_V
+} Type;
+
+/* Structures which should be returned in INTEGER.  */
+#define D(I,MEMBERS,B) struct S_ ## I { MEMBERS ; }; Type class_ ## I = INT; \
+struct S_ ## I f_ ## I (void) { struct S_ ## I s; memset (&s, 0, sizeof(s)); B; return s; }
+
+D(1,char m1, s.m1=42)
+D(2,short m1, s.m1=42)
+D(3,int m1, s.m1=42)
+D(4,long m1, s.m1=42)
+D(5,long long m1, s.m1=42)
+D(6,char m1;short s, s.m1=42)
+D(7,char m1;int i, s.m1=42)
+D(8,char m1; long l, s.m1=42)
+D(9,char m1; long long l, s.m1=42)
+D(10,char m1[16], s.m1[0]=42)
+D(11,short m1[8], s.m1[0]=42)
+D(12,int m1[4], s.m1[0]=42)
+D(13,long m1[2], s.m1[0]=42)
+D(14,long long m1[2], s.m1[0]=42)
+
+#undef D
+
+/* Structures which should be returned in SSE.  */
+#define D(I,MEMBERS,C,B) struct S_ ## I { MEMBERS ; }; Type class_ ## I = C; \
+struct S_ ## I f_ ## I (void) { struct S_ ## I s; memset (&s, 0, sizeof(s)); B; return s; }
+
+D(100,float f,SSE_F, s.f=42)
+D(101,double d,SSE_D, s.d=42)
+D(102,float f;float f2,SSE_F, s.f=42)
+D(103,float f;double d,SSE_F, s.f=42)
+D(104,double d; float f,SSE_D, s.d=42)
+D(105,double d; double d2,SSE_D, s.d=42)
+D(106,float f[2],SSE_F, s.f[0]=42)
+D(107,float f[3],SSE_F, s.f[0]=42)
+D(108,float f[4],SSE_F, s.f[0]=42)
+D(109,double d[2],SSE_D, s.d[0]=42)
+D(110,float f[2]; double d,SSE_F, s.f[0]=42)
+D(111,double d;float f[2],SSE_D, s.d=42)
+
+#undef D
+
+/* Structures which should be returned on x87 stack.  */
+#define D(I,MEMBERS) struct S_ ## I { MEMBERS ; }; Type class_ ## I = X87; \
+struct S_ ## I f_ ## I (void) { struct S_ ## I s = { 42 }; return s; }
+
+/* The only struct containing a long double, which is returned in
+   registers at all, is the singleton struct.  All others are too large.
+   This includes a struct containing complex long double, which is passed
+   in memory, although a complex long double type itself is returned in
+   two registers.  */
+D(200,long double ld)
+
+#undef D
+
+/* Structures which should be returned in INT (low) and SSE (high).  */
+#define D(I,MEMBERS) struct S_ ## I { MEMBERS ; }; Type class_ ## I = INT_SSE; \
+struct S_ ## I f_ ## I (void) { struct S_ ## I s = { 42,43 }; return s; }
+
+D(300,char m1; float m2)
+D(301,char m1; double m2)
+D(302,short m1; float m2)
+D(303,short m1; double m2)
+D(304,int m1; float m2)
+D(305,int m1; double m2)
+D(306,long m1; float m2)
+D(307,long m1; double m2)
+
+#undef D
+
+void check_300 (void)
+{
+  XMM_T x;
+  x._ulong[0] = rax;
+  switch (current_test) {
+    case 300: assert ((rax & 0xff) == 42 && x._float[1] == 43); break;
+    case 301: assert ((rax & 0xff) == 42 && xmm0d[0] == 43); break;
+    case 302: assert ((rax & 0xffff) == 42 && x._float[1] == 43); break;
+    case 303: assert ((rax & 0xffff) == 42 && xmm0d[0] == 43); break;
+    case 304: assert ((rax & 0xffffffff) == 42 && x._float[1] == 43); break;
+    case 305: assert ((rax & 0xffffffff) == 42 && xmm0d[0] == 43); break;
+    case 306: assert (rax == 42 && xmm0f[0] == 43); break;
+    case 307: assert (rax == 42 && xmm0d[0] == 43); break;
+    default: assert (0); break;
+  }
+}
+
+/* Structures which should be returned in SSE (low) and INT (high).  */
+#define D(I,MEMBERS,B) struct S_ ## I { MEMBERS ; }; Type class_ ## I = SSE_INT; \
+struct S_ ## I f_ ## I (void) { struct S_ ## I s; memset (&s, 0, sizeof(s));  B; return s; }
+
+D(400,float f[2];char c, s.f[0]=42; s.c=43)
+D(401,double d;char c, s.d=42; s.c=43)
+
+#undef D
+
+void check_400 (void)
+{
+  switch (current_test) {
+    case 400: assert (xmm0f[0] == 42 && (rax & 0xff) == 43); break;
+    case 401: assert (xmm0d[0] == 42 && (rax & 0xff) == 43); break;
+    default: assert (0); break;
+  }
+}
+
+/* Structures which should be returned in MEM.  */
+void *struct_addr;
+#define D(I,MEMBERS) struct S_ ## I { MEMBERS ; }; Type class_ ## I = MEM; \
+struct S_ ## I f_ ## I (void) { union {unsigned char c; struct S_ ## I s;} u; memset (&u.s, 0, sizeof(u.s)); u.c = 42; return u.s; }
+
+/* Too large.  */
+D(500,char m1[17])
+D(501,short m1[9])
+D(502,int m1[5])
+D(503,long m1[3])
+D(504,short m1[8];char c)
+D(505,char m1[1];int i[4])
+D(506,float m1[5])
+D(507,double m1[3])
+D(508,char m1[1];float f[4])
+D(509,char m1[1];double d[2])
+D(510,__complex long double m1[1])
+
+/* Too large due to padding.  */
+D(520,char m1[1];int i;char c2; int i2; char c3)
+
+/* Unnaturally aligned members.  */
+D(530,short m1[1];int i PACKED)
+
+#undef D
+
+
+/* Special tests.  */
+#define D(I,MEMBERS,C,B) struct S_ ## I { MEMBERS ; }; Type class_ ## I = C; \
+struct S_ ## I f_ ## I (void) { struct S_ ## I s; B; return s; }
+D(600,float f[4], SSE_F_V, s.f[0] = s.f[1] = s.f[2] = s.f[3] = 42)
+#undef D
+
+void clear_all (void)
+{
+  clear_int_registers;
+  clear_float_registers;
+  clear_x87_registers;
+}
+
+void check_all (Type class, unsigned long size)
+{
+  switch (class) {
+    case INT: if (size < 8) rax &= ~0UL >> (64-8*size); assert (rax == 42); break;
+    case SSE_F: assert (xmm0f[0] == 42); break;
+    case SSE_D: assert (xmm0d[0] == 42); break;
+    case SSE_F_V: assert (xmm0f[0] == 42 && xmm0f[1]==42 && xmm1f[0] == 42 && xmm1f[1] == 42); break;
+    case X87: assert (x87_regs[0]._ldouble == 42); break;
+    case INT_SSE: check_300(); break;
+    case SSE_INT: check_400(); break;
+    /* Ideally we would like to check that rax == struct_addr.
+       Unfortunately the address of the target struct escapes (for setting
+       struct_addr), so the return struct is a temporary one whose address
+       is given to the f_* functions, otherwise a conforming program
+       could notice the struct changing already before the function returns.
+       This temporary struct could be anywhere.  For GCC it will be on
+       stack, but noone is forbidding that it could be a static variable
+       if there's no threading or proper locking.  Nobody in his right mind
+       will not use the stack for that.  */
+    case MEM: assert (*(unsigned char*)struct_addr == 42 && rdi == rax); break;
+  }
+}
+
+#define D(I) { struct S_ ## I s; current_test = I; struct_addr = (void*)&s; \
+  clear_all(); \
+  s = WRAP_RET(f_ ## I) (); \
+  check_all(class_ ## I, sizeof(s)); \
+}
+
+int
+main (void)
+{
+  D(1) D(2) D(3) D(4) D(5) D(6) D(7) D(8) D(9) D(10) D(11) D(12) D(13) D(14)
+  
+  D(100) D(101) D(102) D(103) D(104) D(105) D(106) D(107) D(108) D(109) D(110)
+  D(111)
+
+  D(200)
+
+  D(300) D(301) D(302) D(303) D(304) D(305) D(306) D(307)
+
+  D(400) D(401)
+
+  D(500) D(501) D(502) D(503) D(504) D(505) D(506) D(507) D(508) D(509)
+  D(520)
+  D(530)
+
+  D(600)
+  if (num_failed)
+    abort ();
+
+  return 0;
+}
+#undef D
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_varargs.c b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_varargs.c
new file mode 100644
index 000000000..e6d99461d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/x86_64/abi/test_varargs.c
@@ -0,0 +1,97 @@
+/* Test variable number of arguments passed to functions. For now this is
+   just a simple test to see if it's working.  */
+
+#include <stdarg.h>
+#include "defines.h"
+
+
+#define ARG_INT     1
+#define ARG_DOUBLE  2
+#define ARG_POINTER 3
+
+union types
+{
+  int ivalue;
+  double dvalue;
+  void *pvalue;
+};
+
+struct arg
+{
+  int type;
+  union types value;
+};
+
+struct arg *arglist;
+
+/* This tests the argumentlist to see if it matches the format string which
+   is printf-like. Nothing will be printed of course. It can handle ints,
+   doubles and void pointers. The given value will be tested against the
+   values given in arglist.  
+   This test only assures that the variable argument passing is working.
+   No attempt is made to see if argument passing is done the right way.
+   Since the ABI doesn't say how it's done, checking this is not really
+   relevant.  */
+void
+my_noprintf (char *format, ...)
+{
+  va_list va_arglist;
+  char *c;
+
+  int ivalue;
+  double dvalue;
+  void *pvalue;
+  struct arg *argp = arglist;
+
+  va_start (va_arglist, format);
+  for (c = format; *c; c++)
+    if (*c == '%')
+      {
+	switch (*++c)
+	  {
+	  case 'd':
+	    assert (argp->type == ARG_INT);
+	    ivalue = va_arg (va_arglist, int);
+	    assert (argp->value.ivalue == ivalue);
+	    break;
+	  case 'f':
+	    assert (argp->type == ARG_DOUBLE);
+	    dvalue = va_arg (va_arglist, double);
+	    assert (argp->value.dvalue == dvalue);
+	    break;
+	  case 'p':
+	    assert (argp->type == ARG_POINTER);
+	    pvalue = va_arg (va_arglist, void *);
+	    assert (argp->value.pvalue == pvalue);
+	    break;
+	  default:
+	    abort ();
+	  }
+
+	argp++;
+      }
+}
+
+int
+main (void)
+{
+#ifdef CHECK_VARARGS
+  struct arg al[5];
+
+  al[0].type = ARG_INT;
+  al[0].value.ivalue = 256;
+  al[1].type = ARG_DOUBLE;
+  al[1].value.dvalue = 257.0;
+  al[2].type = ARG_POINTER;
+  al[2].value.pvalue = al;
+  al[3].type = ARG_DOUBLE;
+  al[3].value.dvalue = 258.0;
+  al[4].type = ARG_INT;
+  al[4].value.ivalue = 259;
+
+  arglist = al;
+  my_noprintf("%d%f%p%f%d", 256, 257.0, al, 258.0, 259);
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/below100.S b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/below100.S
new file mode 100644
index 000000000..27faa2ef4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/below100.S
@@ -0,0 +1,188 @@
+/******************************************************************
+***                                                             ***
+***     crt0 for __BELOW100__ attribute test with SID           ***
+***                                                             ***
+******************************************************************/
+
+                                /*************************************/
+                                /** Interrupt vectors at 0x8000     **/
+                                /*************************************/
+        .section .int_vec,"ax"
+        .global _start
+        .align 1
+_start:
+        jmpf _int_reset
+        //jmpf _int_basetimer
+        //jmpf _int_timer0
+        //jmpf _int_timer1
+        //jmpf _int_irq_4
+        //jmpf _int_irq_5
+        //jmpf _int_port0
+        //jmpf _int_port1
+        //jmpf _int_irq_8
+        //jmpf _int_irq_9
+        //jmpf _int_irq_a
+        //jmpf _int_irq_b
+        //jmpf _int_irq_c
+        //jmpf _int_irq_d
+        //jmpf _int_irq_e
+        //jmpf _int_irq_f
+                                /*************************************/
+                                /** reset code                      **/
+                                /*************************************/
+        .text
+_int_reset:
+                                /*************************************/
+                                /** setup stack pointer             **/
+                                /*************************************/
+        mov sp,#__stack
+                                /*************************************/
+                                /** zero .bss section               **/
+                                /*************************************/
+        mov r0,#__bss_start
+        mov r1,#__bss_end
+        mov r2,#0
+1:      mov.w (r0++),r2
+        blt r0,r1,1b
+                                /*************************************/
+                                /** copy inital value for .data     **/
+                                /*************************************/
+        mov r1,#__data_start
+        mov r3,#__data_end
+        mov r0,#@lo(__rdata)
+        mov r8,#@hi(__rdata)
+2:      movf.w r2,(r0++)
+        bnz r0,#0,3f
+        add r8,#1
+3:      mov.w (r1++),r2
+        blt r1,r3,2b
+                                /*************************************/
+                                /** call hardware init routine      **/
+                                /*************************************/
+        callf _hwinit
+                                /*************************************/
+                                /** call initializaton routines     **/
+                                /*************************************/
+        callf _init
+                                /*************************************/
+                                /** setup fini routines to be       **/
+                                /**  called from exit               **/
+                                /*************************************/
+        mov r2,#@fptr(_fini)
+        callf atexit
+                                /*************************************/
+                                /** call main() with empty          **/
+                                /**  argc/argv/envp                 **/
+                                /*************************************/
+        mov r2,#0
+        mov r3,#0
+        mov r4,#0
+        callf main
+                                /*************************************/
+                                /** return from main()              **/
+                                /*************************************/
+        callf exit
+                                /*************************************/
+                                /** should never reach this code    **/
+                                /*************************************/
+        jmpf _start
+                                /*************************************/
+                                /** default h/w initialize routine  **/
+                                /** and default _init/_finit for    **/
+                                /**  -nostartfiles option           **/
+                                /*************************************/
+        .globl _hwinit
+        .weak _hwinit
+_hwinit:
+        .globl _init
+        .weak _init
+_init:
+        .globl _fini
+        .weak _fini
+_fini:
+        ret
+
+/******************************************************************
+*******************************************************************
+***                                                             ***
+***       Chip information data for LC59_32K                    ***
+***                 Written by T.Matsukawa                      ***
+***                                                             ***
+*******************************************************************
+******************************************************************/
+
+                                /*************************************/
+                                /** Define convenient macros        **/
+                                /*************************************/
+#define BCD(x)  (((x)/10)%10)*0x10+((x)%10)
+#define BCD4(x) BCD((x)/100),BCD(x)
+#define BCD6(x) BCD((x)/10000),BCD((x)/100),BCD(x)
+                                /*************************************/
+                                /** Define memory sizes             **/
+                                /*************************************/
+#define RAM_SIZE 0x7E00
+#define ROM_SIZE 0x78000
+#define VRAM_SIZE 0x0000
+#define VRAM_ROW 0
+#define VRAM_COLUMN 0
+#define CGROM_SIZE 0x0000
+#define PROTECT_SIZE 0x0000
+
+                                /*************************************/
+                                /** section ".chip_info"            **/
+                                /*************************************/
+        .section .chip_info,"a"
+        .space  0xb8,0x00
+                                /*************************************/
+                                /** B8-BB : User option address     **/
+                                /*************************************/
+        .word   0x00000
+        .global __reset_vector
+#if 0x00000==0
+        .equ    __reset_vector,0x08000
+#else
+        .equ    __reset_vector,0x00000
+#endif
+                                /*************************************/
+                                /** BC-BF : Flash Protect address   **/
+                                /*************************************/
+#if PROTECT_SIZE==0
+        .word   0x00000000
+#else
+        .word   0x08000+ROM_SIZE-PROTECT_SIZE
+#endif
+                                /*************************************/
+                                /** C0-CF : Fixed string            **/
+                                /*************************************/
+1:	.ascii  "CHIPINFORMATION"
+2:	.space  (0x10-(2b-1b)),0x00
+                                /*************************************/
+                                /** D0-DF : Chipname                **/
+                                /*************************************/
+1:	.ascii  "LC59_32K"
+2:	.space  (0x10-(2b-1b)),0x00
+                                /*************************************/
+                                /** E0-E1 : Format version(BCD4)    **/
+                                /*************************************/
+        .byte   0x10, 0x00
+        .space  6, 0x00
+                                /*************************************/
+                                /** E8-F5 : Memory sizes            **/
+                                /*************************************/
+        .byte   BCD4(ROM_SIZE/1024)
+        .byte   BCD6(RAM_SIZE)
+        .byte   BCD6(VRAM_SIZE)
+        .byte   BCD4(VRAM_ROW)
+        .byte   BCD4(VRAM_COLUMN)
+        .byte   BCD4(CGROM_SIZE/1024)
+        .space  3, 0x00
+                                /*************************************/
+                                /** F9 : Package type               **/
+                                /*************************************/
+        .byte   0xff
+        .space  6, 0x00
+
+                                /*************************************/
+                                /** In order to link BIOS in library**/
+                                /*************************************/
+        .equ    dummy,__bios_entry
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/below100.ld b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/below100.ld
new file mode 100644
index 000000000..91c3e43f7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/below100.ld
@@ -0,0 +1,192 @@
+/******************************************************************
+*******************************************************************
+***                                                             ***
+***     Linker script for xstormy16-elf-gcc                     ***
+***           For SID   RAM=0x7E00                              ***
+***                     ROM=0x78000                             ***
+***                                                             ***
+*******************************************************************
+******************************************************************/
+
+OUTPUT_FORMAT("elf32-xstormy16", "elf32-xstormy16", "elf32-xstormy16")
+OUTPUT_ARCH(xstormy16)
+ENTRY(_start)
+SEARCH_DIR( . )
+GROUP(-lc -lsim -lgcc)
+PROVIDE( __target_package = 0xff);
+
+__malloc_start = 0x7E00;
+
+MEMORY
+{
+	RAM (w)    : ORIGIN = 0x00000, LENGTH = 0x07E00
+	CHIP (r)   : ORIGIN = 0x07f00, LENGTH = 0x00100
+	ROM (!w)   : ORIGIN = 0x08000, LENGTH = 0x78000
+}
+
+SECTIONS
+{
+	/* Zero initialized data with the below100 attribute.  */
+	.bss_below100 : {
+		SHORT(0)
+		__bss_start = .;
+		*(.bss_below100)
+		*(.bss_below100.*)
+		. = ALIGN(2);
+	} > RAM
+	
+	/* Non-zero initialized data with the below100 attribute.  */
+	.data_below100 : AT ( __rdata ) {
+		__data_start = . ;
+	        *(.data_0)
+		*(.data_below100)
+		*(.data_below100.*)
+		. = ALIGN(2);
+	} > RAM = 0
+	
+        /* Normal non-zero initialized data.  */
+       .data : AT ( __rdata + SIZEOF(.data_below100) ) {
+		*(.data)
+		*(.data.*)
+		*(.gnu.linkonce.d.*)
+		SORT(CONSTRUCTORS)
+		. = ALIGN(2);
+		__data_end = . ;
+	} > RAM =0
+	
+        /* Normal zero initialized data.  */
+	.bss : AT (LOADADDR(.data) + SIZEOF(.data)) {
+        	*(.dynbss)
+		*(.bss)
+		*(.bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(2);
+		__bss_end = .;
+	} > RAM
+	
+        /* The top of stack.  */
+	__stack = .;
+
+        /* Target chip info.  */
+	.chip_info : {
+		KEEP(*(.chip_info))
+	} > CHIP =0
+	
+        /* Reset and interrupt vectors at 8000.  */
+	.int_vec : {
+	        KEEP(*(.int_vec))
+	} > ROM =0
+	
+        /* Read only data.  */
+	.rodata : {
+        	*(.rodata)
+		*(.rodata.*)
+		*(.gnu.linkonce.r.*)
+	} > ROM =0
+	
+        /* C++ Construcrtors and destructors.  */
+	.ctors : {
+		KEEP (*crtbegin.o(.ctors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+		KEEP (*(SORT(.ctors.*)))
+		KEEP (*(.ctors))
+	} > ROM =0
+	
+	.dtors : {
+        	KEEP (*crtbegin.o(.dtors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+		KEEP (*(SORT(.dtors.*)))
+		KEEP (*(.dtors))
+	} > ROM =0
+
+        /* Pointer lookup table.. */
+	.plt : {
+	        *(.plt)
+	} > ROM =0
+
+        /* Other information.  */
+	.jcr : {
+	        KEEP (*(.jcr))
+	} > ROM =0
+	
+	.eh_frame : {
+	        KEEP (*(.eh_frame))
+	} > ROM =0
+
+	.gcc_except_table : {
+	        KEEP (*(.gcc_except_table))
+	} > ROM =0
+
+        /* Initialization values for data.  */
+	.data_init (NOLOAD) : {
+		__rdata = .;
+		. += SIZEOF(.data_below100);
+		. += SIZEOF(.data);
+		. += SIZEOF(.bss);
+	} > ROM
+
+        /* Executable code.  */
+	.text : {
+		*(.text)
+		*(.text.*)
+		*(.stub)
+		*(.gnu.warning)
+		*(.gnu.linkonce.t.*)
+	} > ROM =0
+
+        /* Startup/finish code.  */
+	.init : {
+        	KEEP (*crti.o(.init))
+		KEEP (*(EXCLUDE_FILE (*crtn.o ) .init))
+		KEEP (*(SORT(.init.*)))
+		KEEP (*(.init))
+	} > ROM =0
+	
+	.fini : {
+        	KEEP (*crti.o(.fini))
+		KEEP (*(EXCLUDE_FILE (*crtn.o ) .fini))
+		KEEP (*(SORT(.fini.*)))
+		KEEP (*(.fini))
+	} > ROM =0
+
+        /* Stab debugging sections.  */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment       0 : { *(.comment) }
+
+        /* DWARF debug sections.  */	
+	/* Symbols in the DWARF debugging sections are relative to
+	   the beginning of the section so we begin them at 0.  */
+
+   	/* DWARF 1.  */
+	.debug 0 : { *(.debug) }
+	.line 0 : { *(.line) }
+
+	/* GNU DWARF 1 extensions.  */
+	.debug_srcinfo 0 : { *(.debug_srcinfo) }
+	.debug_sfnames 0 : { *(.debug_sfnames) }
+
+	/* DWARF 1.1 and DWARF 2.  */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+
+	/* DWARF 2.  */
+	.debug_info     0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+
+        /* SGI/MIPS DWARF 2 extensions.  */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/below_100.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/below_100.c
new file mode 100644
index 000000000..9433f2ad8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/below_100.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "bn " } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+unsigned short   a_below __attribute__((__BELOW100__));
+unsigned short   b_below __attribute__((__BELOW100__));
+unsigned short * a_ptr = & a_below;
+unsigned short * b_ptr = & b_below;
+
+char *
+foo (void)
+{
+  if (a_below & 0x0100)
+    {
+      if (b_below & 0x0100)
+	return "Fail";
+      return "Success";
+    }
+
+  return "Fail";
+}
+
+char *
+bar (void)
+{
+  *a_ptr = 0x0100;
+  *b_ptr = 0xfeff;
+  return foo ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bp.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bp.c
new file mode 100644
index 000000000..26ca6a3b4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bp.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+#define a_val (*((volatile unsigned char *) 0x7f14))
+#define b_val (*((volatile unsigned char *) 0x7f10))
+
+unsigned char * a_ptr = (unsigned char *) 0x7f14;
+unsigned char * b_ptr = (unsigned char *) 0x7f10;
+
+int
+foo (void)
+{
+  if (a_val & 0x08)
+    {
+      if (b_val & 0x08)
+	return -1;
+
+      return 0;
+    }
+
+  return -1;
+}
+
+int
+bar (void)
+{
+  *a_ptr = 0x08;
+  *b_ptr = 0xf7;
+
+  return foo ();
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/01_const_to_b100b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/01_const_to_b100b.c
new file mode 100644
index 000000000..2b4438c4c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/01_const_to_b100b.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b B100,#18" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__));
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 = 0x12;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x12) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/02_const_to_b100w.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/02_const_to_b100w.c
new file mode 100644
index 000000000..d011ffd66
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/02_const_to_b100w.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w B100,#4660" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 = 0x1234;
+}
+
+int
+main (void)
+{
+  *p = 0x9876;
+  Do ();
+  return (*p == 0x1234) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/03_var_to_b100b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/03_var_to_b100b.c
new file mode 100644
index 000000000..bcc991189
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/03_var_to_b100b.c
@@ -0,0 +1,22 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b B100,r" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__));
+unsigned char *p = &B100;
+
+unsigned char yData = 0x12;
+
+void
+Do (void)
+{
+  B100 = yData;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x12) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/04_var_to_b100w.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/04_var_to_b100w.c
new file mode 100644
index 000000000..ab4748871
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/04_var_to_b100w.c
@@ -0,0 +1,22 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w B100,r" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+unsigned short wData = 0x1234;
+
+void
+Do (void)
+{
+  B100 = wData;
+}
+
+int
+main (void)
+{
+  *p = 0x9876;
+  Do ();
+  return (*p == 0x1234) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/05_b100b_to_var.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/05_b100b_to_var.c
new file mode 100644
index 000000000..e5f57e803
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/05_b100b_to_var.c
@@ -0,0 +1,22 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b r., *B100" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__));
+unsigned char *p = &B100;
+
+unsigned char yData = 0x12;
+
+void
+Do (void)
+{
+  yData = B100;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (yData == 0x34) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/06_b100w_to_var.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/06_b100w_to_var.c
new file mode 100644
index 000000000..b19d9bcf4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/06_b100w_to_var.c
@@ -0,0 +1,22 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,B100" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+unsigned short wData = 0x1234;
+
+void
+Do (void)
+{
+  wData = B100;
+}
+
+int
+main (void)
+{
+  *p = 0x3456;
+  Do ();
+  return (wData == 0x3456) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/10_set_b100b_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/10_set_b100b_bit_0.c
new file mode 100644
index 000000000..f0965f110
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/10_set_b100b_bit_0.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__));
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x01;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x35) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/10_set_b100b_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/10_set_b100b_bit_7.c
new file mode 100644
index 000000000..8b14c4308
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/10_set_b100b_bit_7.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__));
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x80;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0xb4) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/11_clr_b100b_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/11_clr_b100b_bit_0.c
new file mode 100644
index 000000000..79c265a24
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/11_clr_b100b_bit_0.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__));
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x01;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0xca) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/11_clr_b100b_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/11_clr_b100b_bit_7.c
new file mode 100644
index 000000000..d40e68f55
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/11_clr_b100b_bit_7.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__));
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x80;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0x4b) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_0.c
new file mode 100644
index 000000000..26b3711ea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_0.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x01)
+    {
+      if (B100B & 0x01)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_3.c
new file mode 100644
index 000000000..865ec549b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_3.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x08)
+    {
+      if (B100B & 0x08)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_7.c
new file mode 100644
index 000000000..efbe1243c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_7.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x80)
+    {
+      if (B100B & 0x80)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_0.c
new file mode 100644
index 000000000..81873954c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_0.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x01))
+    {
+      if (!(B100B & 0x01))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_3.c
new file mode 100644
index 000000000..3fc566aa9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_3.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x08))
+    {
+      if (!(B100B & 0x08))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_7.c
new file mode 100644
index 000000000..bc90eaf95
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_7.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x80))
+    {
+      if (!(B100B & 0x80))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_0.c
new file mode 100644
index 000000000..9164d05df
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_0.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x0001;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1235) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_7.c
new file mode 100644
index 000000000..848c3241f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_7.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x0080;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x12b4) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_8.c
new file mode 100644
index 000000000..f843d12af
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_8.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x0100;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1334) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_f.c
new file mode 100644
index 000000000..bba6dc9f4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_f.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x8000;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x9234) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_0.c
new file mode 100644
index 000000000..634f2fc65
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_0.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x0001;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xedca) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_7.c
new file mode 100644
index 000000000..4b7d1bd72
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_7.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x0080;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xed4b) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_8.c
new file mode 100644
index 000000000..1c5d4c402
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_8.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x0100;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xeccb) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_f.c
new file mode 100644
index 000000000..5140c6caf
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_f.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x8000;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0x6dcb) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_0.c
new file mode 100644
index 000000000..fb6a1ba31
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_0.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0001)
+    {
+      if (B100B & 0x0001)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_3.c
new file mode 100644
index 000000000..c62462914
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_3.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0008)
+    {
+      if (B100B & 0x0008)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_7.c
new file mode 100644
index 000000000..d1c3fbf56
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_7.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0080)
+    {
+      if (B100B & 0x0080)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_8.c
new file mode 100644
index 000000000..b10454203
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_8.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0100)
+    {
+      if (B100B & 0x0100)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_b.c
new file mode 100644
index 000000000..8fbded125
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_b.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0800)
+    {
+      if (B100B & 0x0800)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_f.c
new file mode 100644
index 000000000..ae97d96a8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_f.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x8000)
+    {
+      if (B100B & 0x8000)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_0.c
new file mode 100644
index 000000000..07c6e94d5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_0.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0001))
+    {
+      if (!(B100B & 0x0001))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_3.c
new file mode 100644
index 000000000..f2dd3fba6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_3.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0008))
+    {
+      if (!(B100B & 0x0008))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_7.c
new file mode 100644
index 000000000..af6eb6e17
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_7.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0080))
+    {
+      if (!(B100B & 0x0080))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_8.c
new file mode 100644
index 000000000..d50f8f82b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_8.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0100))
+    {
+      if (!(B100B & 0x0100))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_b.c
new file mode 100644
index 000000000..28d5a39bb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_b.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0800))
+    {
+      if (!(B100B & 0x0800))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_f.c
new file mode 100644
index 000000000..6a3f7025f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_f.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x8000))
+    {
+      if (!(B100B & 0x8000))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/20_set_b100b_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/20_set_b100b_bitfield_0.c
new file mode 100644
index 000000000..240e47299
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/20_set_b100b_bitfield_0.c
@@ -0,0 +1,32 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x35) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/20_set_b100b_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/20_set_b100b_bitfield_7.c
new file mode 100644
index 000000000..674e51a64
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/20_set_b100b_bitfield_7.c
@@ -0,0 +1,32 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0xb4) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/21_clr_b100b_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/21_clr_b100b_bitfield_0.c
new file mode 100644
index 000000000..3846a96d2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/21_clr_b100b_bitfield_0.c
@@ -0,0 +1,32 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0xca) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/21_clr_b100b_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/21_clr_b100b_bitfield_7.c
new file mode 100644
index 000000000..10174576f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/21_clr_b100b_bitfield_7.c
@@ -0,0 +1,32 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0x4b) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_0.c
new file mode 100644
index 000000000..9c4135776
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_0.c
@@ -0,0 +1,43 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b0)
+    {
+      if (B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_3.c
new file mode 100644
index 000000000..86f0f22f1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_3.c
@@ -0,0 +1,43 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b3)
+    {
+      if (B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_7.c
new file mode 100644
index 000000000..0df2f55dd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_7.c
@@ -0,0 +1,43 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b7)
+    {
+      if (B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_0.c
new file mode 100644
index 000000000..9acd8a6f9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_0.c
@@ -0,0 +1,43 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b0)
+    {
+      if (!B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_3.c
new file mode 100644
index 000000000..3ddbc1a10
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_3.c
@@ -0,0 +1,43 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b3)
+    {
+      if (!B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_7.c
new file mode 100644
index 000000000..3c0802e1e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_7.c
@@ -0,0 +1,43 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b7)
+    {
+      if (!B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_0.c
new file mode 100644
index 000000000..d2fb58096
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_0.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1235) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_7.c
new file mode 100644
index 000000000..148253440
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_7.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x12b4) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_8.c
new file mode 100644
index 000000000..ce495b3ec
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_8.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b8 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1334) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_f.c
new file mode 100644
index 000000000..057f2d023
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_f.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b15 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x9234) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_0.c
new file mode 100644
index 000000000..f32a16bd9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_0.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xedca) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_7.c
new file mode 100644
index 000000000..b123c5e3e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_7.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xed4b) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_8.c
new file mode 100644
index 000000000..ed923a1d0
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_8.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b8 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xeccb) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_f.c
new file mode 100644
index 000000000..2e0411519
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_f.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b15 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0x6dcb) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_0.c
new file mode 100644
index 000000000..223de1284
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_0.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b0)
+    {
+      if (B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_3.c
new file mode 100644
index 000000000..83b0a8a15
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_3.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b3)
+    {
+      if (B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_7.c
new file mode 100644
index 000000000..89e71b89f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_7.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b7)
+    {
+      if (B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_8.c
new file mode 100644
index 000000000..044541bfe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_8.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b8)
+    {
+      if (B100B.b8)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_b.c
new file mode 100644
index 000000000..e36934f8d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_b.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b11)
+    {
+      if (B100B.b11)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_f.c
new file mode 100644
index 000000000..90d0bbd9b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_f.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b15)
+    {
+      if (B100B.b15)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_0.c
new file mode 100644
index 000000000..a81359ca3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_0.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b0)
+    {
+      if (!B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_3.c
new file mode 100644
index 000000000..d9eff1abb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_3.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b3)
+    {
+      if (!B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_7.c
new file mode 100644
index 000000000..1d643ea02
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_7.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b7)
+    {
+      if (!B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_8.c
new file mode 100644
index 000000000..5a2b67863
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_8.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b8)
+    {
+      if (!B100B.b8)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_b.c
new file mode 100644
index 000000000..87f760b22
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_b.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b11)
+    {
+      if (!B100B.b11)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_f.c
new file mode 100644
index 000000000..1950ca27c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_f.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b15)
+    {
+      if (!B100B.b15)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/01_const_to_b100b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/01_const_to_b100b.c
new file mode 100644
index 000000000..0ffc4bad8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/01_const_to_b100b.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b B100,#18" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 = 0x12;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x12) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/02_const_to_b100w.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/02_const_to_b100w.c
new file mode 100644
index 000000000..e2ad793c9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/02_const_to_b100w.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w B100,#4660" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0x9876;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 = 0x1234;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x1234) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/03_var_to_b100b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/03_var_to_b100b.c
new file mode 100644
index 000000000..f78d18ab9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/03_var_to_b100b.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b B100,r" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *p = &B100;
+
+unsigned char yData = 0x12;
+
+void
+Do (void)
+{
+  B100 = yData;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x12) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/04_var_to_b100w.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/04_var_to_b100w.c
new file mode 100644
index 000000000..b9f3c55cd
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/04_var_to_b100w.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w B100,r" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0x9876;
+unsigned short *p = &B100;
+
+unsigned short wData = 0x1234;
+
+void
+Do (void)
+{
+  B100 = wData;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x1234) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/05_b100b_to_var.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/05_b100b_to_var.c
new file mode 100644
index 000000000..b2a0bd04c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/05_b100b_to_var.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b r., *B100" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *p = &B100;
+
+unsigned char yData = 0x12;
+
+void
+Do (void)
+{
+  yData = B100;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (yData == 0x34) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/06_b100w_to_var.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/06_b100w_to_var.c
new file mode 100644
index 000000000..50a6dd2a1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/06_b100w_to_var.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,B100" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0x3456;
+unsigned short *p = &B100;
+
+unsigned short wData = 0x1234;
+
+void
+Do (void)
+{
+  wData = B100;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (wData == 0x3456) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/10_set_b100b_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/10_set_b100b_bit_0.c
new file mode 100644
index 000000000..f81d26a3c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/10_set_b100b_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x01;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x35) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/10_set_b100b_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/10_set_b100b_bit_7.c
new file mode 100644
index 000000000..2c519132e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/10_set_b100b_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x80;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xb4) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/11_clr_b100b_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/11_clr_b100b_bit_0.c
new file mode 100644
index 000000000..500f9baf4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/11_clr_b100b_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x01;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xca) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/11_clr_b100b_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/11_clr_b100b_bit_7.c
new file mode 100644
index 000000000..7c71f6789
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/11_clr_b100b_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x80;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x4b) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_0.c
new file mode 100644
index 000000000..10dee7151
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x01)
+    {
+      if (B100B & 0x01)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_3.c
new file mode 100644
index 000000000..b36612409
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x08)
+    {
+      if (B100B & 0x08)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_7.c
new file mode 100644
index 000000000..9906a663c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x80)
+    {
+      if (B100B & 0x80)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_0.c
new file mode 100644
index 000000000..04cc92913
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x01))
+    {
+      if (!(B100B & 0x01))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_3.c
new file mode 100644
index 000000000..cbda60c27
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x08))
+    {
+      if (!(B100B & 0x08))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_7.c
new file mode 100644
index 000000000..49143469d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x80))
+    {
+      if (!(B100B & 0x80))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_0.c
new file mode 100644
index 000000000..acce9e1d9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x0001;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x1235) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_7.c
new file mode 100644
index 000000000..35fe30f5d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x0080;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x12b4) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_8.c
new file mode 100644
index 000000000..cc337fc04
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_8.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x0100;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x1334) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_f.c
new file mode 100644
index 000000000..1fce8df53
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_f.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x8000;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x9234) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_0.c
new file mode 100644
index 000000000..7c1c9b3e7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x0001;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xedca) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_7.c
new file mode 100644
index 000000000..fd707dc78
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x0080;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xed4b) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_8.c
new file mode 100644
index 000000000..7788de60b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_8.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x0100;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xeccb) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_f.c
new file mode 100644
index 000000000..8046ee370
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_f.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x8000;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x6dcb) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_0.c
new file mode 100644
index 000000000..a5df453ae
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0001)
+    {
+      if (B100B & 0x0001)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_3.c
new file mode 100644
index 000000000..8ff76e19d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0008)
+    {
+      if (B100B & 0x0008)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_7.c
new file mode 100644
index 000000000..8f542f31a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0080)
+    {
+      if (B100B & 0x0080)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_8.c
new file mode 100644
index 000000000..727104cb2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_8.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0100)
+    {
+      if (B100B & 0x0100)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_b.c
new file mode 100644
index 000000000..74fd66961
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_b.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0800)
+    {
+      if (B100B & 0x0800)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_f.c
new file mode 100644
index 000000000..79b3839d8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_f.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x8000)
+    {
+      if (B100B & 0x8000)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_0.c
new file mode 100644
index 000000000..94dc08884
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0001))
+    {
+      if (!(B100B & 0x0001))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_3.c
new file mode 100644
index 000000000..7bc005dba
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0008))
+    {
+      if (!(B100B & 0x0008))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_7.c
new file mode 100644
index 000000000..64fcdc251
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0080))
+    {
+      if (!(B100B & 0x0080))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_8.c
new file mode 100644
index 000000000..6a118126e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_8.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0100))
+    {
+      if (!(B100B & 0x0100))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_b.c
new file mode 100644
index 000000000..59a2f3578
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_b.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0800))
+    {
+      if (!(B100B & 0x0800))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_f.c
new file mode 100644
index 000000000..3b271902b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_f.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x8000))
+    {
+      if (!(B100B & 0x8000))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/20_set_b100b_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/20_set_b100b_bitfield_0.c
new file mode 100644
index 000000000..fef1f2ed4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/20_set_b100b_bitfield_0.c
@@ -0,0 +1,33 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 1;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x35) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/20_set_b100b_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/20_set_b100b_bitfield_7.c
new file mode 100644
index 000000000..b3900ca82
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/20_set_b100b_bitfield_7.c
@@ -0,0 +1,33 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 1;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xb4) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/21_clr_b100b_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/21_clr_b100b_bitfield_0.c
new file mode 100644
index 000000000..6106f3860
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/21_clr_b100b_bitfield_0.c
@@ -0,0 +1,33 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 0;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xca) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/21_clr_b100b_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/21_clr_b100b_bitfield_7.c
new file mode 100644
index 000000000..414eec653
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/21_clr_b100b_bitfield_7.c
@@ -0,0 +1,33 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 0;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x4b) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_0.c
new file mode 100644
index 000000000..b950c5184
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_0.c
@@ -0,0 +1,45 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b0)
+    {
+      if (B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_3.c
new file mode 100644
index 000000000..b9da6a5e6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_3.c
@@ -0,0 +1,45 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b3)
+    {
+      if (B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_7.c
new file mode 100644
index 000000000..667e892ea
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_7.c
@@ -0,0 +1,45 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b7)
+    {
+      if (B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_0.c
new file mode 100644
index 000000000..ebb63f74c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_0.c
@@ -0,0 +1,45 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b0)
+    {
+      if (!B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_3.c
new file mode 100644
index 000000000..a16768e40
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_3.c
@@ -0,0 +1,45 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b3)
+    {
+      if (!B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_7.c
new file mode 100644
index 000000000..6f6d181e5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_7.c
@@ -0,0 +1,45 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b7)
+    {
+      if (!B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_0.c
new file mode 100644
index 000000000..7ac5028af
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_0.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 1;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x1235) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_7.c
new file mode 100644
index 000000000..8ba664bed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_7.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 1;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x12b4) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_8.c
new file mode 100644
index 000000000..2a43500c1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_8.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b8 = 1;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x1334) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_f.c
new file mode 100644
index 000000000..9ae5ce48b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_f.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b15 = 1;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x9234) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_0.c
new file mode 100644
index 000000000..94fdf6969
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_0.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 0;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xedca) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_7.c
new file mode 100644
index 000000000..25f11a603
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_7.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 0;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xed4b) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_8.c
new file mode 100644
index 000000000..d065be146
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_8.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b8 = 0;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xeccb) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_f.c
new file mode 100644
index 000000000..4fbe71455
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_f.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b15 = 0;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x6dcb) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_0.c
new file mode 100644
index 000000000..054c0f51e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_0.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b0)
+    {
+      if (B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_3.c
new file mode 100644
index 000000000..75ef36b34
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_3.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b3)
+    {
+      if (B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_7.c
new file mode 100644
index 000000000..45df6371c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_7.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b7)
+    {
+      if (B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_8.c
new file mode 100644
index 000000000..187a47761
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_8.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b8)
+    {
+      if (B100B.b8)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_b.c
new file mode 100644
index 000000000..8cf4cfd53
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_b.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b11)
+    {
+      if (B100B.b11)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_f.c
new file mode 100644
index 000000000..235cef7d2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_f.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b15)
+    {
+      if (B100B.b15)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_0.c
new file mode 100644
index 000000000..bb80aca81
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_0.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b0)
+    {
+      if (!B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_3.c
new file mode 100644
index 000000000..5be556426
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_3.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b3)
+    {
+      if (!B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_7.c
new file mode 100644
index 000000000..0725b5542
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_7.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b7)
+    {
+      if (!B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_8.c
new file mode 100644
index 000000000..2ad3642f8
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_8.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b8)
+    {
+      if (!B100B.b8)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_b.c
new file mode 100644
index 000000000..e9af02f8e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_b.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b11)
+    {
+      if (!B100B.b11)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_f.c
new file mode 100644
index 000000000..a13ec8c2c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_f.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b15)
+    {
+      if (!B100B.b15)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/01_const_to_sfrb.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/01_const_to_sfrb.c
new file mode 100644
index 000000000..96e4adcfb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/01_const_to_sfrb.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b 32532,#18" } } */
+
+#define SFR (*((volatile unsigned char*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR = 0x12;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x12) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/02_const_to_sfrw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/02_const_to_sfrw.c
new file mode 100644
index 000000000..930ba4d96
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/02_const_to_sfrw.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w 32532,#4660" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR = 0x1234;
+}
+
+int
+main (void)
+{
+  *p = 0x9876;
+  Do ();
+  return (*p == 0x1234) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/03_var_to_sfrb.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/03_var_to_sfrb.c
new file mode 100644
index 000000000..8c4b1f1c7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/03_var_to_sfrb.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b 32532,r" } } */
+
+#define SFR (*((volatile unsigned char*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+unsigned char yData = 0x12;
+
+void
+Do (void)
+{
+  SFR = yData;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x12) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/04_var_to_sfrw.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/04_var_to_sfrw.c
new file mode 100644
index 000000000..c8d4a0e66
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/04_var_to_sfrw.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w 32532,r" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+unsigned short wData = 0x1234;
+
+void
+Do (void)
+{
+  SFR = wData;
+}
+
+int
+main (void)
+{
+  *p = 0x9876;
+  Do ();
+  return (*p == 0x1234) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/05_sfrb_to_var.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/05_sfrb_to_var.c
new file mode 100644
index 000000000..9471e295a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/05_sfrb_to_var.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b r., *32532" } } */
+
+#define SFR (*((volatile unsigned char*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+unsigned char yData = 0x12;
+
+void
+Do (void)
+{
+  yData = SFR;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (yData == 0x34) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/06_sfrw_to_var.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/06_sfrw_to_var.c
new file mode 100644
index 000000000..39cbab5c3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/06_sfrw_to_var.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r6,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+unsigned short wData = 0x9876;
+
+void
+Do (void)
+{
+  wData = SFR;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (wData == 0x1234) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/10_set_sfrb_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/10_set_sfrb_bit_0.c
new file mode 100644
index 000000000..644afb59c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/10_set_sfrb_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32532,#0" } } */
+
+#define SFR (*((volatile unsigned char*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x01;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x35) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/10_set_sfrb_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/10_set_sfrb_bit_7.c
new file mode 100644
index 000000000..90cd3c83f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/10_set_sfrb_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32532,#7" } } */
+
+#define SFR (*((volatile unsigned char*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x80;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0xb4) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/11_clr_sfrb_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/11_clr_sfrb_bit_0.c
new file mode 100644
index 000000000..59d6153ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/11_clr_sfrb_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32532,#0" } } */
+
+#define SFR (*((volatile unsigned char*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x01;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0xca) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/11_clr_sfrb_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/11_clr_sfrb_bit_7.c
new file mode 100644
index 000000000..0cb7e1761
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/11_clr_sfrb_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32532,#7" } } */
+
+#define SFR (*((volatile unsigned char*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x80;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0x4b) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_0.c
new file mode 100644
index 000000000..54b0b1f6d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+#define SFRA (*((volatile unsigned char*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile unsigned char*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x01)
+    {
+      if (SFRB & 0x01)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_3.c
new file mode 100644
index 000000000..4a575cc99
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+#define SFRA (*((volatile unsigned char*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile unsigned char*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x08)
+    {
+      if (SFRB & 0x08)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_7.c
new file mode 100644
index 000000000..747cbdd94
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+#define SFRA (*((volatile unsigned char*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile unsigned char*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x80)
+    {
+      if (SFRB & 0x80)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_0.c
new file mode 100644
index 000000000..d14969206
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+#define SFRA (*((volatile unsigned char*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile unsigned char*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x01))
+    {
+      if (!(SFRB & 0x01))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_3.c
new file mode 100644
index 000000000..be6112cf1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+#define SFRA (*((volatile unsigned char*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile unsigned char*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x08))
+    {
+      if (!(SFRB & 0x08))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_7.c
new file mode 100644
index 000000000..12e68cd5b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+#define SFRA (*((volatile unsigned char*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile unsigned char*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x80))
+    {
+      if (!(SFRB & 0x80))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_0.c
new file mode 100644
index 000000000..00f4f78cc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x0001;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1235) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_3.c
new file mode 100644
index 000000000..b5741fc48
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_3.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x0008;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x123c) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_7.c
new file mode 100644
index 000000000..ffcad45b2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x0080;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x12b4) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_8.c
new file mode 100644
index 000000000..3f19329f2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_8.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x0100;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1334) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_b.c
new file mode 100644
index 000000000..b5e8bb9e2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_b.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x0800;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1a34) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_f.c
new file mode 100644
index 000000000..767e95ff4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_f.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x8000;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x9234) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_0.c
new file mode 100644
index 000000000..fcabe0994
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x0001;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xedca) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_3.c
new file mode 100644
index 000000000..26281be87
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_3.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x0008;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xedc3) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_7.c
new file mode 100644
index 000000000..15ff063f4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x0080;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xed4b) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_8.c
new file mode 100644
index 000000000..c44817a73
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_8.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x0100;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xeccb) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_b.c
new file mode 100644
index 000000000..9f1c3a5e7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_b.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x0800;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xe5cb) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_f.c
new file mode 100644
index 000000000..46eef43c4
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_f.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x8000;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0x6dcb) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_0.c
new file mode 100644
index 000000000..287dd7a83
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x0001)
+    {
+      if (SFRB & 0x0001)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_3.c
new file mode 100644
index 000000000..719fa58df
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x0008)
+    {
+      if (SFRB & 0x0008)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_7.c
new file mode 100644
index 000000000..1b361c5fe
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x0080)
+    {
+      if (SFRB & 0x0080)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_8.c
new file mode 100644
index 000000000..c8a3ba7cb
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_8.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x0100)
+    {
+      if (SFRB & 0x0100)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_b.c
new file mode 100644
index 000000000..a0f5742c1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_b.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x0800)
+    {
+      if (SFRB & 0x0800)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_f.c
new file mode 100644
index 000000000..5e91bb23e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_f.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x8000)
+    {
+      if (SFRB & 0x8000)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_0.c
new file mode 100644
index 000000000..ac5d87fe3
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x0001))
+    {
+      if (!(SFRB & 0x0001))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_3.c
new file mode 100644
index 000000000..fa77f1bd1
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x0008))
+    {
+      if (!(SFRB & 0x0008))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_7.c
new file mode 100644
index 000000000..cb331f034
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x0080))
+    {
+      if (!(SFRB & 0x0080))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_8.c
new file mode 100644
index 000000000..105bf4d8d
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_8.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x0100))
+    {
+      if (!(SFRB & 0x0100))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_b.c
new file mode 100644
index 000000000..768cfb92b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_b.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x0800))
+    {
+      if (!(SFRB & 0x0800))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_f.c
new file mode 100644
index 000000000..533a3c61a
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_f.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x8000))
+    {
+      if (!(SFRB & 0x8000))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/20_set_sfrb_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/20_set_sfrb_bitfield_0.c
new file mode 100644
index 000000000..3879ed438
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/20_set_sfrb_bitfield_0.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32532,#0" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b0 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x35) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/20_set_sfrb_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/20_set_sfrb_bitfield_7.c
new file mode 100644
index 000000000..1b7bb8777
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/20_set_sfrb_bitfield_7.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32532,#7" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b7 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0xb4) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/21_clr_sfrb_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/21_clr_sfrb_bitfield_0.c
new file mode 100644
index 000000000..6f73231c7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/21_clr_sfrb_bitfield_0.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32532,#0" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b0 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0xca) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/21_clr_sfrb_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/21_clr_sfrb_bitfield_7.c
new file mode 100644
index 000000000..10063e492
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/21_clr_sfrb_bitfield_7.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32532,#7" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b7 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0x4b) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_0.c
new file mode 100644
index 000000000..bb8489b6c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_0.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b0)
+    {
+      if (SFRB.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_3.c
new file mode 100644
index 000000000..96b441c04
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_3.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b3)
+    {
+      if (SFRB.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_7.c
new file mode 100644
index 000000000..ad7bebdc6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_7.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b7)
+    {
+      if (SFRB.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_0.c
new file mode 100644
index 000000000..dfa59a939
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_0.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b0)
+    {
+      if (!SFRB.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_3.c
new file mode 100644
index 000000000..c311877c7
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_3.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b3)
+    {
+      if (!SFRB.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_7.c
new file mode 100644
index 000000000..2e4eea990
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_7.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b7)
+    {
+      if (!SFRB.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_0.c
new file mode 100644
index 000000000..d2351681c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_0.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32532,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b0 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1235) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_7.c
new file mode 100644
index 000000000..6f1cf87df
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_7.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32532,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b7 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x12b4) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_8.c
new file mode 100644
index 000000000..9de4c0def
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_8.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32533,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b8 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1334) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_f.c
new file mode 100644
index 000000000..e89757fb6
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_f.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32533,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b15 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x9234) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_0.c
new file mode 100644
index 000000000..5acd858fc
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_0.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32532,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b0 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xedca) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_7.c
new file mode 100644
index 000000000..112714e99
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_7.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32532,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b7 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xed4b) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_8.c
new file mode 100644
index 000000000..015f9bc15
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_8.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32533,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b8 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xeccb) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_f.c
new file mode 100644
index 000000000..0c85ffaa9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_f.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32533,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b15 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0x6dcb) ? 0 : 1;
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_0.c
new file mode 100644
index 000000000..d4861b21b
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_0.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bn 32532,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b0)
+    {
+      if (SFRB.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_3.c
new file mode 100644
index 000000000..5318305db
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_3.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bn 32532,#3" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b3)
+    {
+      if (SFRB.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_7.c
new file mode 100644
index 000000000..85b86a0e9
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_7.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b r., *32532" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b7)
+    {
+      if (SFRB.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_8.c
new file mode 100644
index 000000000..65412e3f5
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_8.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bn 32533,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b8)
+    {
+      if (SFRB.b8)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_b.c
new file mode 100644
index 000000000..951db3f2f
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_b.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bn 32533,#3" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b11)
+    {
+      if (SFRB.b11)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_f.c
new file mode 100644
index 000000000..b51daa862
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_f.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b r., *32533" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b15)
+    {
+      if (SFRB.b15)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_0.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_0.c
new file mode 100644
index 000000000..0680d4f03
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_0.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bp 32532,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b0)
+    {
+      if (!SFRB.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_3.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_3.c
new file mode 100644
index 000000000..17f07f907
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_3.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bp 32532,#3" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b3)
+    {
+      if (!SFRB.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_7.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_7.c
new file mode 100644
index 000000000..2c1cab89c
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_7.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b r., *32532" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b7)
+    {
+      if (!SFRB.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_8.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_8.c
new file mode 100644
index 000000000..2353cad4e
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_8.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bp 32533,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b8)
+    {
+      if (!SFRB.b8)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_b.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_b.c
new file mode 100644
index 000000000..123cb0605
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_b.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bp 32533,#3" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b11)
+    {
+      if (!SFRB.b11)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_f.c b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_f.c
new file mode 100644
index 000000000..daf5090d2
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_f.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b r., *32533" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b15)
+    {
+      if (!SFRB.b15)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/xstormy16.exp b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/xstormy16.exp
new file mode 100644
index 000000000..7699a42ed
--- /dev/null
+++ b/gcc-4.4.3/gcc/testsuite/gcc.target/xstormy16/xstormy16.exp
@@ -0,0 +1,42 @@
+# Tests for the xstormy16
+
+if {![istarget xstormy16-*-*]} {
+    return 0
+}
+
+load_lib gcc-dg.exp
+
+# Initialize `dg'.
+dg-init
+
+# Assemble the below100.S file which contains
+# support code for the rest of the tests.
+set old-dg-do-what-default "${dg-do-what-default}"
+set dg-do-what-default assemble
+dg-test -keep-output "$srcdir/$subdir/below100.S" "" ""
+set dg-do-what-default run
+
+
+# Main loop.
+foreach testcase [lsort [find $srcdir/$subdir *.c]] {
+    global test_counts
+
+    set base "[file rootname [file tail $testcase]]"
+
+    if ![runtest_file_p $runtests $testcase] {
+        continue
+    }
+
+    set fails_before $test_counts(FAIL,count)
+    dg-test $testcase "--save-temps -fno-inline-functions -L$srcdir/$subdir" ""
+    set fails_after $test_counts(FAIL,count)
+
+    if { $fails_before == $fails_after } {
+        catch "exec rm -f $base.i $base.s $base.o"
+    }
+}
+
+set dg-do-what-default "${old-dg-do-what-default}"
+
+# All done.
+dg-finish