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-rw-r--r--gcc-4.9/gcc/ChangeLog6
-rw-r--r--gcc-4.9/gcc/config/aarch64/aarch64-simd.md40
-rw-r--r--gcc-4.9/gcc/config/aarch64/aarch64.md3
-rw-r--r--gcc-4.9/gcc/config/aarch64/iterators.md6
-rw-r--r--gcc-4.9/gcc/testsuite/ChangeLog10
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62040.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62262.c20
7 files changed, 101 insertions, 5 deletions
diff --git a/gcc-4.9/gcc/ChangeLog b/gcc-4.9/gcc/ChangeLog
index 44fa361..473fceb 100644
--- a/gcc-4.9/gcc/ChangeLog
+++ b/gcc-4.9/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2014-08-27 Guozhi Wei <carrot@google.com>
+
+ PR target/62262
+ * config/aarch64/aarch64.md (*andim_ashift<mode>_bfiz): Check the shift
+ amount before using it.
+
2014-08-26 Joel Sherrill <joel.sherrill@oarcorp.com>
* doc/invoke.texi: -fno-cxa-atexit should be -fno-use-cxa-atexit.
diff --git a/gcc-4.9/gcc/config/aarch64/aarch64-simd.md b/gcc-4.9/gcc/config/aarch64/aarch64-simd.md
index 1f827b5..851e77a 100644
--- a/gcc-4.9/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc-4.9/gcc/config/aarch64/aarch64-simd.md
@@ -945,8 +945,8 @@
;; On big-endian this is { zeroes, operand }
(define_insn "move_lo_quad_internal_<mode>"
- [(set (match_operand:VQ 0 "register_operand" "=w,w,w")
- (vec_concat:VQ
+ [(set (match_operand:VQ_NO2E 0 "register_operand" "=w,w,w")
+ (vec_concat:VQ_NO2E
(match_operand:<VHALF> 1 "register_operand" "w,r,r")
(vec_duplicate:<VHALF> (const_int 0))))]
"TARGET_SIMD && !BYTES_BIG_ENDIAN"
@@ -960,9 +960,25 @@
(set_attr "length" "4")]
)
+(define_insn "move_lo_quad_internal_<mode>"
+ [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w")
+ (vec_concat:VQ_2E
+ (match_operand:<VHALF> 1 "register_operand" "w,r,r")
+ (const_int 0)))]
+ "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+ "@
+ dup\\t%d0, %1.d[0]
+ fmov\\t%d0, %1
+ dup\\t%d0, %1"
+ [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>")
+ (set_attr "simd" "yes,*,yes")
+ (set_attr "fp" "*,yes,*")
+ (set_attr "length" "4")]
+)
+
(define_insn "move_lo_quad_internal_be_<mode>"
- [(set (match_operand:VQ 0 "register_operand" "=w,w,w")
- (vec_concat:VQ
+ [(set (match_operand:VQ_NO2E 0 "register_operand" "=w,w,w")
+ (vec_concat:VQ_NO2E
(vec_duplicate:<VHALF> (const_int 0))
(match_operand:<VHALF> 1 "register_operand" "w,r,r")))]
"TARGET_SIMD && BYTES_BIG_ENDIAN"
@@ -976,6 +992,22 @@
(set_attr "length" "4")]
)
+(define_insn "move_lo_quad_internal_be_<mode>"
+ [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w")
+ (vec_concat:VQ_2E
+ (const_int 0)
+ (match_operand:<VHALF> 1 "register_operand" "w,r,r")))]
+ "TARGET_SIMD && BYTES_BIG_ENDIAN"
+ "@
+ dup\\t%d0, %1.d[0]
+ fmov\\t%d0, %1
+ dup\\t%d0, %1"
+ [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>")
+ (set_attr "simd" "yes,*,yes")
+ (set_attr "fp" "*,yes,*")
+ (set_attr "length" "4")]
+)
+
(define_expand "move_lo_quad_<mode>"
[(match_operand:VQ 0 "register_operand")
(match_operand:VQ 1 "register_operand")]
diff --git a/gcc-4.9/gcc/config/aarch64/aarch64.md b/gcc-4.9/gcc/config/aarch64/aarch64.md
index df81045..319f805 100644
--- a/gcc-4.9/gcc/config/aarch64/aarch64.md
+++ b/gcc-4.9/gcc/config/aarch64/aarch64.md
@@ -3157,7 +3157,8 @@
(and:GPI (ashift:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand 2 "const_int_operand" "n"))
(match_operand 3 "const_int_operand" "n")))]
- "exact_log2 ((INTVAL (operands[3]) >> INTVAL (operands[2])) + 1) >= 0
+ "(INTVAL (operands[2]) < (<GPI:sizen>))
+ && exact_log2 ((INTVAL (operands[3]) >> INTVAL (operands[2])) + 1) >= 0
&& (INTVAL (operands[3]) & ((1 << INTVAL (operands[2])) - 1)) == 0"
"ubfiz\\t%<w>0, %<w>1, %2, %P3"
[(set_attr "type" "bfm")]
diff --git a/gcc-4.9/gcc/config/aarch64/iterators.md b/gcc-4.9/gcc/config/aarch64/iterators.md
index e76e3ef..cfb1811 100644
--- a/gcc-4.9/gcc/config/aarch64/iterators.md
+++ b/gcc-4.9/gcc/config/aarch64/iterators.md
@@ -66,6 +66,12 @@
;; Quad vector modes.
(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V4SF V2DF])
+;; VQ without 2 element modes.
+(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V4SF])
+
+;; Quad vector with only 2 element modes.
+(define_mode_iterator VQ_2E [V2DI V2DF])
+
;; All vector modes, except double.
(define_mode_iterator VQ_S [V8QI V16QI V4HI V8HI V2SI V4SI])
diff --git a/gcc-4.9/gcc/testsuite/ChangeLog b/gcc-4.9/gcc/testsuite/ChangeLog
index 4a7de28..51626c3 100644
--- a/gcc-4.9/gcc/testsuite/ChangeLog
+++ b/gcc-4.9/gcc/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2014-09-04 Guozhi Wei <carrot@google.com>
+
+ PR target/62040
+ * gcc.target/aarch64/pr62040.c: New test.
+
+2014-08-27 Guozhi Wei <carrot@google.com>
+
+ PR target/62262
+ * gcc.target/aarch64/pr62262.c: New test.
+
2014-08-26 Dominik Vogt <vogt@linux.vnet.ibm.com>
* gfortran.dg/bessel_7.f90: Bump allowed precision to avoid
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62040.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62040.c
new file mode 100644
index 0000000..cfb4979
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62040.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-g -Os" } */
+
+#include "arm_neon.h"
+
+extern void bar (int32x4_t);
+
+void
+foo ()
+{
+ int32x4x4_t rows;
+ uint64x2x2_t row01;
+
+ row01.val[0] = vreinterpretq_u64_s32 (rows.val[0]);
+ row01.val[1] = vreinterpretq_u64_s32 (rows.val[1]);
+ uint64x1_t row3l = vget_low_u64 (row01.val[0]);
+ row01.val[0] = vcombine_u64 (vget_low_u64 (row01.val[1]), row3l);
+ int32x4_t xxx = vreinterpretq_s32_u64 (row01.val[0]);
+ int32x4_t out = vtrn1q_s32 (xxx, xxx);
+ bar (out);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62262.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62262.c
new file mode 100644
index 0000000..5bf90bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62262.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fprofile-use" } */
+
+static inline int CLZ(int mask) {
+ return mask ? __builtin_clz(mask) : 32;
+}
+
+int foo(int value)
+{
+ if (value == 0)
+ return 0;
+
+ int bias = CLZ(value);
+ value >>= bias;
+ int zeros = CLZ(value << 1);
+ value <<= zeros;
+
+ int packed = (unsigned)(value << 9) >> 9;
+ return packed;
+}