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authorAndrew Hsieh <andrewhsieh@google.com>2014-09-03 15:56:31 +0000
committerGerrit Code Review <noreply-gerritcodereview@google.com>2014-09-03 15:56:31 +0000
commit4254ad78d813b8c4cfc6c07218aee6b1be554f23 (patch)
tree8e9350d7e0339c5c7da9499ab5742527e21520c6 /gcc-4.9/gcc
parent9bba04175106d9b9e8a58715e3e7fa560c13e092 (diff)
parente97c99f15937e5762a973b25192aab824126a6d3 (diff)
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Merge "[gcc-4.9] Merge svn r214745 from google/gcc-4_9 branch. Merge gcc-4_9 source r214745 from google/gcc-4_9 branch."
Diffstat (limited to 'gcc-4.9/gcc')
-rw-r--r--gcc-4.9/gcc/ChangeLog412
-rw-r--r--gcc-4.9/gcc/DATESTAMP2
-rw-r--r--gcc-4.9/gcc/Makefile.in9
-rw-r--r--gcc-4.9/gcc/ada/ChangeLog9
-rw-r--r--gcc-4.9/gcc/ada/gsocket.h5
-rw-r--r--gcc-4.9/gcc/ada/s-osinte-rtems.adb2
-rw-r--r--gcc-4.9/gcc/ada/socket.c2
-rw-r--r--gcc-4.9/gcc/auto-profile.c2
-rw-r--r--gcc-4.9/gcc/bb-reorder.c3
-rw-r--r--gcc-4.9/gcc/c-family/ChangeLog12
-rw-r--r--gcc-4.9/gcc/c-family/array-notation-common.c13
-rw-r--r--gcc-4.9/gcc/c-family/c-common.c2
-rw-r--r--gcc-4.9/gcc/c/ChangeLog12
-rw-r--r--gcc-4.9/gcc/c/c-array-notation.c19
-rw-r--r--gcc-4.9/gcc/c/c-parser.c7
-rw-r--r--gcc-4.9/gcc/cgraphunit.c1
-rw-r--r--gcc-4.9/gcc/config/arm/vfp.md10
-rw-r--r--gcc-4.9/gcc/config/i386/driver-i386.c5
-rw-r--r--gcc-4.9/gcc/config/i386/i386.c15
-rw-r--r--gcc-4.9/gcc/config/i386/i386.h2
-rw-r--r--gcc-4.9/gcc/config/i386/i386.md175
-rw-r--r--gcc-4.9/gcc/config/i386/sse.md4
-rw-r--r--gcc-4.9/gcc/config/i386/x86-tune.def5
-rw-r--r--gcc-4.9/gcc/config/nios2/rtems.h34
-rw-r--r--gcc-4.9/gcc/config/nios2/t-rtems133
-rw-r--r--gcc-4.9/gcc/config/pa/pa-protos.h2
-rw-r--r--gcc-4.9/gcc/config/pa/pa.c87
-rw-r--r--gcc-4.9/gcc/config/pa/pa.h10
-rw-r--r--gcc-4.9/gcc/config/pa/pa.md30
-rw-r--r--gcc-4.9/gcc/config/rs6000/constraints.md16
-rw-r--r--gcc-4.9/gcc/config/rs6000/rs6000.c149
-rw-r--r--gcc-4.9/gcc/config/rs6000/rs6000.h171
-rw-r--r--gcc-4.9/gcc/config/rs6000/rs6000.md28
-rw-r--r--gcc-4.9/gcc/config/rs6000/vsx.md331
-rw-r--r--gcc-4.9/gcc/config/sh/sh.c6
-rw-r--r--gcc-4.9/gcc/config/sh/sh.opt2
-rw-r--r--gcc-4.9/gcc/coverage.c2
-rw-r--r--gcc-4.9/gcc/cp/ChangeLog74
-rw-r--r--gcc-4.9/gcc/cp/call.c5
-rw-r--r--gcc-4.9/gcc/cp/class.c23
-rw-r--r--gcc-4.9/gcc/cp/cp-array-notation.c30
-rw-r--r--gcc-4.9/gcc/cp/cp-tree.h1
-rw-r--r--gcc-4.9/gcc/cp/decl.c24
-rw-r--r--gcc-4.9/gcc/cp/decl2.c5
-rw-r--r--gcc-4.9/gcc/cp/expr.c8
-rw-r--r--gcc-4.9/gcc/cp/init.c57
-rw-r--r--gcc-4.9/gcc/cp/lambda.c5
-rw-r--r--gcc-4.9/gcc/cp/parser.c2
-rw-r--r--gcc-4.9/gcc/cp/pt.c18
-rw-r--r--gcc-4.9/gcc/cp/semantics.c5
-rw-r--r--gcc-4.9/gcc/cp/tree.c4
-rw-r--r--gcc-4.9/gcc/cp/typeck2.c3
-rw-r--r--gcc-4.9/gcc/cprop.c7
-rw-r--r--gcc-4.9/gcc/doc/invoke.texi128
-rw-r--r--gcc-4.9/gcc/doc/md.texi14
-rw-r--r--gcc-4.9/gcc/dwarf2out.c55
-rw-r--r--gcc-4.9/gcc/final.c2
-rw-r--r--gcc-4.9/gcc/fortran/ChangeLog56
-rw-r--r--gcc-4.9/gcc/fortran/frontend-passes.c30
-rw-r--r--gcc-4.9/gcc/fortran/gfortran.h2
-rw-r--r--gcc-4.9/gcc/fortran/openmp.c9
-rw-r--r--gcc-4.9/gcc/fortran/simplify.c11
-rw-r--r--gcc-4.9/gcc/fortran/trans-expr.c4
-rw-r--r--gcc-4.9/gcc/fortran/trans-openmp.c32
-rw-r--r--gcc-4.9/gcc/gcov-tool.c13
-rw-r--r--gcc-4.9/gcc/genconfig.c18
-rw-r--r--gcc-4.9/gcc/gimple-fold.c4
-rw-r--r--gcc-4.9/gcc/gimple.h24
-rw-r--r--gcc-4.9/gcc/gimplify.c2
-rw-r--r--gcc-4.9/gcc/go/gofrontend/parse.cc5
-rw-r--r--gcc-4.9/gcc/haifa-sched.c8
-rw-r--r--gcc-4.9/gcc/ifcvt.c31
-rw-r--r--gcc-4.9/gcc/l-ipo.c44
-rw-r--r--gcc-4.9/gcc/l-ipo.h1
-rw-r--r--gcc-4.9/gcc/lra-constraints.c14
-rw-r--r--gcc-4.9/gcc/lto/ChangeLog8
-rw-r--r--gcc-4.9/gcc/lto/lto-lang.c6
-rw-r--r--gcc-4.9/gcc/optabs.c5
-rw-r--r--gcc-4.9/gcc/sched-deps.c18
-rw-r--r--gcc-4.9/gcc/simplify-rtx.c2
-rw-r--r--gcc-4.9/gcc/testsuite/ChangeLog217
-rw-r--r--gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61455-2.c13
-rw-r--r--gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61455.c9
-rw-r--r--gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61962.c14
-rw-r--r--gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61963.c9
-rw-r--r--gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr62008.c10
-rw-r--r--gcc-4.9/gcc/testsuite/c-c++-common/pr61741.c22
-rw-r--r--gcc-4.9/gcc/testsuite/g++.dg/cpp0x/constexpr-array7.C13
-rw-r--r--gcc-4.9/gcc/testsuite/g++.dg/cpp0x/constexpr-empty7.C28
-rw-r--r--gcc-4.9/gcc/testsuite/g++.dg/cpp0x/constexpr-ptrmem3.C16
-rw-r--r--gcc-4.9/gcc/testsuite/g++.dg/cpp0x/initlist-array4.C9
-rw-r--r--gcc-4.9/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-template13.C7
-rw-r--r--gcc-4.9/gcc/testsuite/g++.dg/cpp0x/rv-cond1.C13
-rw-r--r--gcc-4.9/gcc/testsuite/g++.dg/expr/cond12.C12
-rw-r--r--gcc-4.9/gcc/testsuite/g++.dg/ext/restrict2.C8
-rw-r--r--gcc-4.9/gcc/testsuite/g++.dg/init/explicit2.C8
-rw-r--r--gcc-4.9/gcc/testsuite/g++.dg/ipa/devirt-39.C28
-rw-r--r--gcc-4.9/gcc/testsuite/g++.dg/opt/pr62146.C51
-rw-r--r--gcc-4.9/gcc/testsuite/g++.dg/tls/thread_local10.C23
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.c-torture/compile/pr60655-1.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.c-torture/execute/20050316-3.x2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.c-torture/execute/bitfld-6.c23
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.c-torture/execute/pr23135.x2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.c-torture/execute/pr61375.c35
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-4.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-5.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/atomic/stdatomic-flag.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/lto/pr60449_0.c30
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/lto/pr60449_1.c76
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/pr51879-18.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/pr57233.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/pr59418.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/pr61756.c14
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/pr61776.c27
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/pr62004.c47
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/pr62030.c50
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/torture/pr61964.c33
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/tree-ssa/ssa-copyprop-2.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/vect/pr62073.c40
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/arm/frame-pointer-1.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext-execute.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/arm/pr56184.C1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/arm/pr58784.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/arm/pr59896.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/arm/pr59985.C1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/arm/stack-red-zone.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmpd-2.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmps-2.c6
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmsd-2.c6
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmss-2.c6
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2d-2.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2pd-2.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2ps-2.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2q-2.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2d-2.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2pd-2.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2ps-2.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2q-2.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr61794.c12
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr61801.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr61855.c10
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr61923.c36
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c1
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/pr62030-octeon.c50
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-warn-1.c12
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-warn-2.c11
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-warn-3.c9
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60102.c11
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/sh/pr61996.c12
-rw-r--r--gcc-4.9/gcc/testsuite/gfortran.dg/array_assignment_5.f9016
-rw-r--r--gcc-4.9/gcc/testsuite/gfortran.dg/array_constructor_49.f9013
-rw-r--r--gcc-4.9/gcc/testsuite/gfortran.dg/bessel_7.f902
-rw-r--r--gcc-4.9/gcc/testsuite/gfortran.dg/dependency_44.f9036
-rw-r--r--gcc-4.9/gcc/testsuite/gfortran.dg/dot_product_3.f9015
-rw-r--r--gcc-4.9/gcc/testsuite/gfortran.dg/gomp/pr62131.f9019
-rw-r--r--gcc-4.9/gcc/testsuite/gfortran.dg/pr45636.f902
-rw-r--r--gcc-4.9/gcc/testsuite/gfortran.dg/realloc_on_assign_24.f9010
-rw-r--r--gcc-4.9/gcc/testsuite/gnat.dg/pack20.adb9
-rw-r--r--gcc-4.9/gcc/testsuite/gnat.dg/pack20.ads15
-rw-r--r--gcc-4.9/gcc/testsuite/gnat.dg/pack20_pkg.ads7
-rw-r--r--gcc-4.9/gcc/testsuite/lib/target-supports.exp7
-rw-r--r--gcc-4.9/gcc/toplev.c5
-rw-r--r--gcc-4.9/gcc/toplev.h5
-rw-r--r--gcc-4.9/gcc/tree-cfg.c106
-rw-r--r--gcc-4.9/gcc/tree-cfgcleanup.c61
-rw-r--r--gcc-4.9/gcc/tree-ssa-loop-ivopts.c2
-rw-r--r--gcc-4.9/gcc/tree-ssa-math-opts.c6
-rw-r--r--gcc-4.9/gcc/tree-ssa-operands.c6
-rw-r--r--gcc-4.9/gcc/tree-ssa-tail-merge.c14
-rw-r--r--gcc-4.9/gcc/tree-ssanames.h1
-rw-r--r--gcc-4.9/gcc/tree-vect-loop.c3
-rw-r--r--gcc-4.9/gcc/tree-vectorizer.h4
-rw-r--r--gcc-4.9/gcc/tree.h5
174 files changed, 3357 insertions, 698 deletions
diff --git a/gcc-4.9/gcc/ChangeLog b/gcc-4.9/gcc/ChangeLog
index df98072..44fa361 100644
--- a/gcc-4.9/gcc/ChangeLog
+++ b/gcc-4.9/gcc/ChangeLog
@@ -1,3 +1,415 @@
+2014-08-26 Joel Sherrill <joel.sherrill@oarcorp.com>
+
+ * doc/invoke.texi: -fno-cxa-atexit should be -fno-use-cxa-atexit.
+
+2014-08-26 Marek Polacek <polacek@redhat.com>
+
+ Backport from mainline
+ 2014-08-26 Marek Polacek <polacek@redhat.com>
+
+ PR c/61271
+ * tree-vectorizer.h (LOOP_REQUIRES_VERSIONING_FOR_ALIGNMENT,
+ LOOP_REQUIRES_VERSIONING_FOR_ALIAS): Wrap in parens.
+
+2014-08-24 Oleg Endo <olegendo@gcc.gnu.org>
+
+ Backport from mainline
+ 2014-08-24 Oleg Endo <olegendo@gcc.gnu.org>
+
+ PR target/61996
+ * config/sh/sh.opt (musermode): Allow negative form.
+ * config/sh/sh.c (sh_option_override): Disable TARGET_USERMODE for
+ targets that don't support it.
+ * doc/invoke.texi (SH Options): Rename sh-*-linux* to sh*-*-linux*.
+ Document -mno-usermode option.
+
+2014-08-23 John David Anglin <danglin@gcc.gnu.org>
+
+ PR target/62038
+ * config/pa/pa.c (pa_output_function_epilogue): Don't set
+ last_address when the current function is a thunk.
+ (pa_asm_output_mi_thunk): When we don't have named sections or they
+ are not being used, check that thunk can reach the stub table with a
+ short branch.
+
+2014-08-22 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ Backport from mainline
+ 2014-08-22 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ PR target/62195
+ * doc/md.texi (Machine Constraints): Update PowerPC wi constraint
+ documentation to state it is only for VSX operations.
+
+ * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Make wi
+ constraint only active if VSX.
+
+ * config/rs6000/rs6000.md (lfiwax): Use wj constraint instead of
+ wi cosntraint for ISA 2.07 lxsiwax/lxsiwzx instructions.
+ (lfiwzx): Likewise.
+
+2014-08-21 Uros Bizjak <ubizjak@gmail.com>
+
+ Backport from mainline
+ 2014-08-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/i386/i386.md (*ctz<mode>2_falsedep_1): Don't clear
+ destination if it is used in source.
+ (*clz<mode>2_lzcnt_falsedep_1): Likewise.
+ (*popcount<mode>2_falsedep_1): Likewise.
+
+ Backport from mainline
+ 2014-08-18 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/62011
+ * config/i386/x86-tune.def (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI):
+ New tune flag.
+ * config/i386/i386.h (TARGET_AVOID_FALSE_DEP_FOR_BMI): New define.
+ * config/i386/i386.md (unspec) <UNSPEC_INSN_FALSE_DEP>: New unspec.
+ (ffs<mode>2): Do not expand with tzcnt for
+ TARGET_AVOID_FALSE_DEP_FOR_BMI.
+ (ffssi2_no_cmove): Ditto.
+ (*tzcnt<mode>_1): Disable for TARGET_AVOID_FALSE_DEP_FOR_BMI.
+ (ctz<mode>2): New expander.
+ (*ctz<mode>2_falsedep_1): New insn_and_split pattern.
+ (*ctz<mode>2_falsedep): New insn.
+ (*ctz<mode>2): Rename from ctz<mode>2.
+ (clz<mode>2_lzcnt): New expander.
+ (*clz<mode>2_lzcnt_falsedep_1): New insn_and_split pattern.
+ (*clz<mode>2_lzcnt_falsedep): New insn.
+ (*clz<mode>2): Rename from ctz<mode>2.
+ (popcount<mode>2): New expander.
+ (*popcount<mode>2_falsedep_1): New insn_and_split pattern.
+ (*popcount<mode>2_falsedep): New insn.
+ (*popcount<mode>2): Rename from ctz<mode>2.
+ (*popcount<mode>2_cmp): Remove.
+ (*popcountsi2_cmp_zext): Ditto.
+
+2014-08-20 Martin Jambor <mjambor@suse.cz>
+ Wei Mi <wmi@google.com>
+
+ PR ipa/60449
+ PR middle-end/61776
+ * tree-ssa-operands.c (update_stmt_operands): Remove
+ MODIFIED_NORETURN_CALLS.
+ * tree-cfgcleanup.c (cleanup_call_ctrl_altering_flag): New func.
+ (cleanup_control_flow_bb): Use cleanup_call_ctrl_altering_flag.
+ (split_bb_on_noreturn_calls): Renamed from split_bbs_on_noreturn_calls.
+ (cleanup_tree_cfg_1): Use split_bb_on_noreturn_calls.
+ * tree-ssanames.h: Remove MODIFIED_NORETURN_CALLS.
+ * gimple.h (enum gf_mask): Add GF_CALL_CTRL_ALTERING.
+ (gimple_call_set_ctrl_altering): New func.
+ (gimple_call_ctrl_altering_p): Ditto.
+ * tree-cfg.c (gimple_call_initialize_ctrl_altering): Ditto.
+ (make_blocks): Use gimple_call_initialize_ctrl_altering.
+ (is_ctrl_altering_stmt): Use gimple_call_ctrl_altering_p.
+ (execute_fixup_cfg): Use gimple_call_ctrl_altering_p and
+ remove MODIFIED_NORETURN_CALLS.
+
+2014-08-20 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ Backport from mainline.
+ 2014-08-12 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+ PR target/62098
+ * config/arm/vfp.md (*combine_vcvtf2i): Fix constraint.
+ Remove unnecessary attributes.
+
+2014-08-16 John David Anglin <danglin@gcc.gnu.org>
+
+ PR target/61641
+ * config/pa/pa-protos.h (pa_output_addr_vec, pa_output_addr_diff_vec):
+ Declare.
+ * config/pa/pa.c (pa_reorg): Remove code to insert brtab marker insns.
+ (pa_output_addr_vec, pa_output_addr_diff_vec): New.
+ * config/pa/pa.h (ASM_OUTPUT_ADDR_VEC, ASM_OUTPUT_ADDR_DIFF_VEC):
+ Define.
+ * config/pa/pa.md (begin_brtab): Delete insn.
+ (end_brtab): Likewise.
+
+2014-08-15 Oleg Endo <olegendo@gcc.gnu.org>
+
+ Backport from mainline:
+ 2014-08-15 Oleg Endo <olegendo@gcc.gnu.org>
+
+ * doc/invoke.texi (SH options): Document missing processor variant
+ options. Remove references to Hitachi. Undocument deprecated mspace
+ option.
+
+2014-08-15 Tom de Vries <tom@codesourcery.com>
+
+ Backport from mainline:
+ 2014-08-14 Tom de Vries <tom@codesourcery.com>
+
+ PR rtl-optimization/62004
+ PR rtl-optimization/62030
+ * ifcvt.c (rtx_interchangeable_p): New function.
+ (noce_try_move, noce_process_if_block): Use rtx_interchangeable_p.
+
+ 2014-08-05 Richard Biener <rguenther@suse.de>
+
+ * emit-rtl.h (mem_attrs_eq_p): Declare.
+ * emit-rtl.c (mem_attrs_eq_p): Export.
+
+2014-08-15 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/62092
+ * gimplify.c (gimplify_adjust_omp_clauses_1): Don't remove
+ OMP_CLAUSE_SHARED for global vars if the global var is mentioned
+ in OMP_CLAUSE_MAP in some outer target region.
+
+>>>>>>> .r214216
+2014-08-14 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ Backport from mainline
+ 2014-08-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ PR target/61713
+ * gcc/optabs.c (expand_atomic_test_and_set): Do not try to emit
+ move to subtarget in serial version if result is ignored.
+
+2014-08-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ Backport from mainline
+ 2014-08-12 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ PR middle-end/62103
+ * gimple-fold.c (fold_ctor_reference): Don't fold in presence of
+ bitfields, that is when size doesn't match the size of type or the
+ size of the constructor.
+
+2014-08-12 Felix Yang <fei.yang0953@gmail.com>
+
+ PR tree-optimization/62073
+ * tree-vect-loop.c (vect_is_simple_reduction_1): Check that DEF1 has
+ a basic block.
+
+2014-08-12 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/62025
+ * sched-deps.c (find_inc): Check if inc_insn doesn't clobber
+ any registers that are used in mem_insn.
+
+2014-08-12 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ Backport patch from mainline
+ 2014-08-11 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ * config/rs6000/constraints.md (wh constraint): New constraint,
+ for FP registers if direct move is available.
+ (wi constraint): New constraint, for VSX/FP registers that can
+ handle 64-bit integers.
+ (wj constraint): New constraint for VSX/FP registers that can
+ handle 64-bit integers for direct moves.
+ (wk constraint): New constraint for VSX/FP registers that can
+ handle 64-bit doubles for direct moves.
+ (wy constraint): Make documentation match implementation.
+
+ * config/rs6000/rs6000.c (struct rs6000_reg_addr): Add
+ scalar_in_vmx_p field to simplify tests of whether SFmode or
+ DFmode can go in the Altivec registers.
+ (rs6000_hard_regno_mode_ok): Use scalar_in_vmx_p field.
+ (rs6000_setup_reg_addr_masks): Likewise.
+ (rs6000_debug_print_mode): Add debug support for scalar_in_vmx_p
+ field, and wh/wi/wj/wk constraints.
+ (rs6000_init_hard_regno_mode_ok): Setup scalar_in_vmx_p field, and
+ the wh/wi/wj/wk constraints.
+ (rs6000_preferred_reload_class): If SFmode/DFmode can go in the
+ upper registers, prefer VSX registers unless the operation is a
+ memory operation with REG+OFFSET addressing.
+
+ * config/rs6000/vsx.md (VSr mode attribute): Add support for
+ DImode. Change SFmode to use ww constraint instead of d to allow
+ SF registers in the upper registers.
+ (VSr2): Likewise.
+ (VSr3): Likewise.
+ (VSr5): Fix thinko in comment.
+ (VSa): New mode attribute that is an alternative to wa, that
+ returns the VSX register class that a mode can go in, but may not
+ be the preferred register class.
+ (VS_64dm): New mode attribute for appropriate register classes for
+ referencing 64-bit elements of vectors for direct moves and normal
+ moves.
+ (VS_64reg): Likewise.
+ (vsx_mov<mode>): Change wa constraint to <VSa> to limit the
+ register allocator to only registers the data type can handle.
+ (vsx_le_perm_load_<mode>): Likewise.
+ (vsx_le_perm_store_<mode>): Likewise.
+ (vsx_xxpermdi2_le_<mode>): Likewise.
+ (vsx_xxpermdi4_le_<mode>): Likewise.
+ (vsx_lxvd2x2_le_<mode>): Likewise.
+ (vsx_lxvd2x4_le_<mode>): Likewise.
+ (vsx_stxvd2x2_le_<mode>): Likewise.
+ (vsx_add<mode>3): Likewise.
+ (vsx_sub<mode>3): Likewise.
+ (vsx_mul<mode>3): Likewise.
+ (vsx_div<mode>3): Likewise.
+ (vsx_tdiv<mode>3_internal): Likewise.
+ (vsx_fre<mode>2): Likewise.
+ (vsx_neg<mode>2): Likewise.
+ (vsx_abs<mode>2): Likewise.
+ (vsx_nabs<mode>2): Likewise.
+ (vsx_smax<mode>3): Likewise.
+ (vsx_smin<mode>3): Likewise.
+ (vsx_sqrt<mode>2): Likewise.
+ (vsx_rsqrte<mode>2): Likewise.
+ (vsx_tsqrt<mode>2_internal): Likewise.
+ (vsx_fms<mode>4): Likewise.
+ (vsx_nfma<mode>4): Likewise.
+ (vsx_eq<mode>): Likewise.
+ (vsx_gt<mode>): Likewise.
+ (vsx_ge<mode>): Likewise.
+ (vsx_eq<mode>_p): Likewise.
+ (vsx_gt<mode>_p): Likewise.
+ (vsx_ge<mode>_p): Likewise.
+ (vsx_xxsel<mode>): Likewise.
+ (vsx_xxsel<mode>_uns): Likewise.
+ (vsx_copysign<mode>3): Likewise.
+ (vsx_float<VSi><mode>2): Likewise.
+ (vsx_floatuns<VSi><mode>2): Likewise.
+ (vsx_fix_trunc<mode><VSi>2): Likewise.
+ (vsx_fixuns_trunc<mode><VSi>2): Likewise.
+ (vsx_x<VSv>r<VSs>i): Likewise.
+ (vsx_x<VSv>r<VSs>ic): Likewise.
+ (vsx_btrunc<mode>2): Likewise.
+ (vsx_b2trunc<mode>2): Likewise.
+ (vsx_floor<mode>2): Likewise.
+ (vsx_ceil<mode>2): Likewise.
+ (vsx_<VS_spdp_insn>): Likewise.
+ (vsx_xscvspdp): Likewise.
+ (vsx_xvcvspuxds): Likewise.
+ (vsx_float_fix_<mode>2): Likewise.
+ (vsx_set_<mode>): Likewise.
+ (vsx_extract_<mode>_internal1): Likewise.
+ (vsx_extract_<mode>_internal2): Likewise.
+ (vsx_extract_<mode>_load): Likewise.
+ (vsx_extract_<mode>_store): Likewise.
+ (vsx_splat_<mode>): Likewise.
+ (vsx_xxspltw_<mode>): Likewise.
+ (vsx_xxspltw_<mode>_direct): Likewise.
+ (vsx_xxmrghw_<mode>): Likewise.
+ (vsx_xxmrglw_<mode>): Likewise.
+ (vsx_xxsldwi_<mode>): Likewise.
+ (vsx_xscvdpspn): Tighten constraints to only use register classes
+ the types use.
+ (vsx_xscvspdpn): Likewise.
+ (vsx_xscvdpspn_scalar): Likewise.
+
+ * config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wh, wi,
+ wj, and wk constraints.
+ (GPR_REG_CLASS_P): New helper macro for register classes targeting
+ general purpose registers.
+
+ * config/rs6000/rs6000.md (f32_dm): Use wh constraint for SDmode
+ direct moves.
+ (zero_extendsidi2_lfiwz): Use wj constraint for direct move of
+ DImode instead of wm. Use wk constraint for direct move of DFmode
+ instead of wm.
+ (extendsidi2_lfiwax): Likewise.
+ (lfiwax): Likewise.
+ (lfiwzx): Likewise.
+ (movdi_internal64): Likewise.
+
+ * doc/md.texi (PowerPC and IBM RS6000): Document wh, wi, wj, and
+ wk constraints. Make the wy constraint documentation match them
+ implementation.
+
+2014-08-12 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
+
+ Backport from mainline
+ 2014-08-04 Ganesh Gopalasubramanian
+ <Ganesh.Gopalasubramanian@amd.com>
+
+ * config/i386/i386.c (ix86_option_override_internal): Add
+ PTA_RDRND and PTA_MOVBE for bdver4.
+
+2014-08-12 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
+
+ Backport from mainline
+ 2014-08-04 Ganesh Gopalasubramanian
+ <Ganesh.Gopalasubramanian@amd.com>
+
+ * config/i386/driver-i386.c (host_detect_local_cpu): Handle AMD's extended
+ family information. Handle BTVER2 cpu with cpuid family value.
+
+2014-08-12 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
+
+ Backport from mainline
+ 2014-06-16 Ganesh Gopalasubramanian
+ <Ganesh.Gopalasubramanian@amd.com>
+
+ * config/i386/i386.c (ix86_expand_sse2_mulvxdi3): Issue
+ instructions "vpmuludq" and "vpaddq" instead of "vpmacsdql" for
+ handling 32-bit multiplication.
+
+2014-08-08 Guozhi Wei <carrot@google.com>
+
+ * config/rs6000/rs6000.md (*movdi_internal64): Add a new constraint.
+
+2014-08-07 Ilya Tocar <ilya.tocar@intel.com>
+
+ * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Fix
+ constraint.
+
+2014-08-06 Vladimir Makarov <vmakarov@redhat.com>
+
+ PR debug/61923
+ * haifa-sched.c (advance_one_cycle): Fix dump.
+ (schedule_block): Don't advance cycle if we are already at the
+ beginning of the cycle.
+
+2014-08-06 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/61320
+ * tree-ssa-loop-ivopts.c (may_be_unaligned_p): Properly
+ handle misaligned loads.
+
+2014-08-04 Rohit <rohitarulraj@freescale.com>
+
+ PR target/60102
+ * config/rs6000/rs6000.c
+ (rs6000_reg_names): Add SPE high register names.
+ (alt_reg_names): Likewise.
+ (rs6000_dwarf_register_span): For SPE high registers, replace
+ dwarf register numbers with GCC hard register numbers.
+ (rs6000_init_dwarf_reg_sizes_extra): Likewise.
+ (rs6000_dbx_register_number): For SPE high registers, return dwarf
+ register number for the corresponding GCC hard register number.
+ * config/rs6000/rs6000.h
+ (FIRST_PSEUDO_REGISTER): Update based on 32 newly added GCC hard
+ register numbers for SPE high registers.
+ (DWARF_FRAME_REGISTERS): Likewise.
+ (DWARF_REG_TO_UNWIND_COLUMN): Likewise.
+ (DWARF_FRAME_REGNUM): Likewise.
+ (FIXED_REGISTERS): Likewise.
+ (CALL_USED_REGISTERS): Likewise.
+ (CALL_REALLY_USED_REGISTERS): Likewise.
+ (REG_ALLOC_ORDER): Likewise.
+ (enum reg_class): Likewise.
+ (REG_CLASS_NAMES): Likewise.
+ (REG_CLASS_CONTENTS): Likewise.
+ (SPE_HIGH_REGNO_P): New macro to identify SPE high registers.
+
+2014-08-01 Vladimir Makarov <vmakarov@redhat.com>
+
+ * lra-constraints.c (remove_inheritance_pseudos): Process
+ destination pseudo too.
+
+2014-08-01 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ Backport from mainline
+ 2014-06-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ PR tree-optimization/61375
+ * tree-ssa-math-opts.c (find_bswap_or_nop_1): Cancel optimization if
+ symbolic number cannot be represented in an unsigned HOST_WIDE_INT.
+ (execute_optimize_bswap): Cancel optimization if CHAR_BIT != 8.
+
+2014-08-01 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/61964
+ * tree-ssa-tail-merge.c (gimple_equal_p): Handle non-SSA LHS solely
+ by structural equality.
+
2014-07-31 Oleg Endo <olegendo@gcc.gnu.org>
Backport from mainline
diff --git a/gcc-4.9/gcc/DATESTAMP b/gcc-4.9/gcc/DATESTAMP
index 06fdc77..2cd35d4 100644
--- a/gcc-4.9/gcc/DATESTAMP
+++ b/gcc-4.9/gcc/DATESTAMP
@@ -1 +1 @@
-20140801
+20140827
diff --git a/gcc-4.9/gcc/Makefile.in b/gcc-4.9/gcc/Makefile.in
index f94b35a..8680549 100644
--- a/gcc-4.9/gcc/Makefile.in
+++ b/gcc-4.9/gcc/Makefile.in
@@ -773,7 +773,7 @@ GCC_INSTALL_NAME := $(shell echo gcc|sed '$(program_transform_name)')
GCC_TARGET_INSTALL_NAME := $(target_noncanonical)-$(shell echo gcc|sed '$(program_transform_name)')
CPP_INSTALL_NAME := $(shell echo cpp|sed '$(program_transform_name)')
GCOV_INSTALL_NAME := $(shell echo gcov|sed '$(program_transform_name)')
-PROFILE_TOOL_INSTALL_NAME := $(shell echo profile_tool|sed '$(program_transform_name)')
+GCOV_TOOL_INSTALL_NAME := $(shell echo gcov-tool|sed '$(program_transform_name)')
# Setup the testing framework, if you have one
EXPECT = `if [ -f $${rootme}/../expect/expect ] ; then \
@@ -3243,13 +3243,6 @@ install-common: native lang.install-common installdirs
rm -f $(DESTDIR)$(bindir)/$(GCOV_INSTALL_NAME)$(exeext); \
$(INSTALL_PROGRAM) gcov$(exeext) $(DESTDIR)$(bindir)/$(GCOV_INSTALL_NAME)$(exeext); \
fi
-# Install profile_tool if it is available.
- -if [ -f $(srcdir)/../contrib/profile_tool ]; \
- then \
- rm -f $(DESTDIR)$(bindir)/$(PROFILE_TOOL_INSTALL_NAME)$(exeext); \
- $(INSTALL_PROGRAM) $(srcdir)/../contrib/profile_tool \
- $(DESTDIR)$(bindir)/$(PROFILE_TOOL_INSTALL_NAME)$(exeext); \
- fi
# Install gcov-tool if it was compiled.
-if [ -f gcov-tool$(exeext) ]; \
then \
diff --git a/gcc-4.9/gcc/ada/ChangeLog b/gcc-4.9/gcc/ada/ChangeLog
index 27d4ad7..c8c4d80 100644
--- a/gcc-4.9/gcc/ada/ChangeLog
+++ b/gcc-4.9/gcc/ada/ChangeLog
@@ -1,3 +1,12 @@
+2014-08-12 Joel Sherrill <joel.sherrill@oarcorp.com>
+
+ * socket.c: For RTEMS, use correct prototype of gethostbyname_r().
+ * gsocket.h Add include of <unistd.h> on RTEMS.
+
+2014-08-11 Joel Sherrill <joel.sherrill@oarcorp.com>
+
+ * s-osinte-rtems.adb: Correct formatting of line in license block.
+
2014-07-16 Release Manager
* GCC 4.9.1 released.
diff --git a/gcc-4.9/gcc/ada/gsocket.h b/gcc-4.9/gcc/ada/gsocket.h
index e21d714..1d9235f 100644
--- a/gcc-4.9/gcc/ada/gsocket.h
+++ b/gcc-4.9/gcc/ada/gsocket.h
@@ -183,6 +183,11 @@
#include <sys/time.h>
#endif
+#if defined(__rtems__)
+#include <unistd.h>
+/* Required, for read(), write(), and close() */
+#endif
+
/*
* RTEMS has these .h files but not until you have built and installed RTEMS.
* When building a C/C++ toolset, you also build the newlib C library, so the
diff --git a/gcc-4.9/gcc/ada/s-osinte-rtems.adb b/gcc-4.9/gcc/ada/s-osinte-rtems.adb
index de21785..9f01128 100644
--- a/gcc-4.9/gcc/ada/s-osinte-rtems.adb
+++ b/gcc-4.9/gcc/ada/s-osinte-rtems.adb
@@ -22,7 +22,7 @@
-- You should have received a copy of the GNU General Public License and --
-- a copy of the GCC Runtime Library Exception along with this program; --
-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
--- <http://www.gnu.org/licenses/>.
+-- <http://www.gnu.org/licenses/>. --
-- --
-- GNARL was developed by the GNARL team at Florida State University. It is --
-- now maintained by Ada Core Technologies Inc. in cooperation with Florida --
diff --git a/gcc-4.9/gcc/ada/socket.c b/gcc-4.9/gcc/ada/socket.c
index 18999b3..e658456 100644
--- a/gcc-4.9/gcc/ada/socket.c
+++ b/gcc-4.9/gcc/ada/socket.c
@@ -212,7 +212,7 @@ __gnat_gethostbyname (const char *name,
struct hostent *rh;
int ri;
-#if defined(__linux__) || defined(__GLIBC__)
+#if defined(__linux__) || defined(__GLIBC__) || defined(__rtems__)
(void) gethostbyname_r (name, ret, buf, buflen, &rh, h_errnop);
#else
rh = gethostbyname_r (name, ret, buf, buflen, h_errnop);
diff --git a/gcc-4.9/gcc/auto-profile.c b/gcc-4.9/gcc/auto-profile.c
index ddc2d5e..11c2016 100644
--- a/gcc-4.9/gcc/auto-profile.c
+++ b/gcc-4.9/gcc/auto-profile.c
@@ -958,6 +958,7 @@ read_aux_modules (void)
module_infos = XCNEWVEC (gcov_module_info *, num_aux_modules + 1);
module_infos[0] = module;
primary_module_id = module->ident;
+ record_module_name (module->ident, lbasename (in_fnames[0]));
if (aux_modules == NULL)
return;
unsigned curr_module = 1, max_group = PARAM_VALUE (PARAM_MAX_LIPO_GROUP);
@@ -1004,6 +1005,7 @@ read_aux_modules (void)
}
module_infos[curr_module++] = aux_module;
add_input_filename (*iter);
+ record_module_name (aux_module->ident, lbasename (*iter));
}
}
diff --git a/gcc-4.9/gcc/bb-reorder.c b/gcc-4.9/gcc/bb-reorder.c
index fa6f62f..b9a829e 100644
--- a/gcc-4.9/gcc/bb-reorder.c
+++ b/gcc-4.9/gcc/bb-reorder.c
@@ -95,7 +95,6 @@
#include "expr.h"
#include "params.h"
#include "diagnostic-core.h"
-#include "toplev.h" /* user_defined_section_attribute */
#include "tree-pass.h"
#include "df.h"
#include "bb-reorder.h"
@@ -2555,7 +2554,7 @@ gate_handle_partition_blocks (void)
we are going to omit the reordering. */
&& optimize_function_for_speed_p (cfun)
&& !DECL_ONE_ONLY (current_function_decl)
- && !user_defined_section_attribute);
+ && !DECL_HAS_EXPLICIT_SECTION_NAME_P(current_function_decl));
}
/* This function is the main 'entrance' for the optimization that
diff --git a/gcc-4.9/gcc/c-family/ChangeLog b/gcc-4.9/gcc/c-family/ChangeLog
index cbe8b06..e3c8c83 100644
--- a/gcc-4.9/gcc/c-family/ChangeLog
+++ b/gcc-4.9/gcc/c-family/ChangeLog
@@ -1,3 +1,15 @@
+2014-08-12 Igor Zamyatin <igor.zamyatin@intel.com>
+
+ PR other/61962
+ * array-notation-common.c (find_rank): Added handling for other
+ types of references.
+
+2014-08-01 Igor Zamyatin <igor.zamyatin@intel.com>
+
+ PR middle-end/61455
+ * array-notation-common.c (extract_array_notation_exprs): Handling
+ of DECL_EXPR added.
+
2014-07-17 Richard Biener <rguenther@suse.de>
Backport from mainline
diff --git a/gcc-4.9/gcc/c-family/array-notation-common.c b/gcc-4.9/gcc/c-family/array-notation-common.c
index c010039..f8bce04 100644
--- a/gcc-4.9/gcc/c-family/array-notation-common.c
+++ b/gcc-4.9/gcc/c-family/array-notation-common.c
@@ -221,11 +221,14 @@ find_rank (location_t loc, tree orig_expr, tree expr, bool ignore_builtin_fn,
current_rank++;
ii_tree = ARRAY_NOTATION_ARRAY (ii_tree);
}
- else if (TREE_CODE (ii_tree) == ARRAY_REF)
+ else if (handled_component_p (ii_tree)
+ || TREE_CODE (ii_tree) == INDIRECT_REF)
ii_tree = TREE_OPERAND (ii_tree, 0);
else if (TREE_CODE (ii_tree) == PARM_DECL
|| TREE_CODE (ii_tree) == VAR_DECL)
break;
+ else
+ gcc_unreachable ();
}
if (*rank == 0)
/* In this case, all the expressions this function has encountered thus
@@ -329,6 +332,14 @@ extract_array_notation_exprs (tree node, bool ignore_builtin_fn,
vec_safe_push (*array_list, node);
return;
}
+ if (TREE_CODE (node) == DECL_EXPR)
+ {
+ tree x = DECL_EXPR_DECL (node);
+ if (DECL_INITIAL (x))
+ extract_array_notation_exprs (DECL_INITIAL (x),
+ ignore_builtin_fn,
+ array_list);
+ }
else if (TREE_CODE (node) == STATEMENT_LIST)
{
tree_stmt_iterator ii_tsi;
diff --git a/gcc-4.9/gcc/c-family/c-common.c b/gcc-4.9/gcc/c-family/c-common.c
index 65c25bf..9923928 100644
--- a/gcc-4.9/gcc/c-family/c-common.c
+++ b/gcc-4.9/gcc/c-family/c-common.c
@@ -7378,8 +7378,6 @@ handle_section_attribute (tree *node, tree ARG_UNUSED (name), tree args,
if (targetm_common.have_named_sections)
{
- user_defined_section_attribute = true;
-
if ((TREE_CODE (decl) == FUNCTION_DECL
|| TREE_CODE (decl) == VAR_DECL)
&& TREE_CODE (TREE_VALUE (args)) == STRING_CST)
diff --git a/gcc-4.9/gcc/c/ChangeLog b/gcc-4.9/gcc/c/ChangeLog
index 4816d5c..6fb49c6 100644
--- a/gcc-4.9/gcc/c/ChangeLog
+++ b/gcc-4.9/gcc/c/ChangeLog
@@ -1,3 +1,15 @@
+2014-08-22 Igor Zamyatin <igor.zamyatin@intel.com>
+
+ PR other/62008
+ * c-parser.c (c_parser_array_notation): Check for correct
+ type of an array added.
+
+2014-08-01 Igor Zamyatin <igor.zamyatin@intel.com>
+
+ PR middle-end/61455
+ * c-array-notation.c (expand_array_notations): Handling
+ of DECL_EXPR added.
+
2014-07-16 Release Manager
* GCC 4.9.1 released.
diff --git a/gcc-4.9/gcc/c/c-array-notation.c b/gcc-4.9/gcc/c/c-array-notation.c
index 2305e1e..be08f53 100644
--- a/gcc-4.9/gcc/c/c-array-notation.c
+++ b/gcc-4.9/gcc/c/c-array-notation.c
@@ -1265,6 +1265,25 @@ expand_array_notations (tree *tp, int *walk_subtrees, void *)
rhs_loc, rhs, TREE_TYPE (rhs));
}
break;
+ case DECL_EXPR:
+ {
+ tree x = DECL_EXPR_DECL (*tp);
+ if (DECL_INITIAL (x))
+ {
+ location_t loc = DECL_SOURCE_LOCATION (x);
+ tree lhs = x;
+ tree rhs = DECL_INITIAL (x);
+ DECL_INITIAL (x) = NULL;
+ tree new_modify_expr = build_modify_expr (loc, lhs,
+ TREE_TYPE (lhs),
+ NOP_EXPR,
+ loc, rhs,
+ TREE_TYPE(rhs));
+ expand_array_notations (&new_modify_expr, walk_subtrees, NULL);
+ *tp = new_modify_expr;
+ }
+ }
+ break;
case CALL_EXPR:
*tp = fix_array_notation_call_expr (*tp);
break;
diff --git a/gcc-4.9/gcc/c/c-parser.c b/gcc-4.9/gcc/c/c-parser.c
index a51af2e..6ce277c 100644
--- a/gcc-4.9/gcc/c/c-parser.c
+++ b/gcc-4.9/gcc/c/c-parser.c
@@ -14074,6 +14074,13 @@ c_parser_array_notation (location_t loc, c_parser *parser, tree initial_index,
array_type = TREE_TYPE (array_value);
gcc_assert (array_type);
+ if (TREE_CODE (array_type) != ARRAY_TYPE
+ && TREE_CODE (array_type) != POINTER_TYPE)
+ {
+ error_at (loc, "base of array section must be pointer or array type");
+ c_parser_skip_until_found (parser, CPP_CLOSE_SQUARE, NULL);
+ return error_mark_node;
+ }
type = TREE_TYPE (array_type);
token = c_parser_peek_token (parser);
diff --git a/gcc-4.9/gcc/cgraphunit.c b/gcc-4.9/gcc/cgraphunit.c
index 83e436f..bff2833 100644
--- a/gcc-4.9/gcc/cgraphunit.c
+++ b/gcc-4.9/gcc/cgraphunit.c
@@ -1051,6 +1051,7 @@ analyze_functions (void)
struct cgraph_node *origin_node
= cgraph_get_node (DECL_ABSTRACT_ORIGIN (decl));
origin_node->used_as_abstract_origin = true;
+ enqueue_node (origin_node);
}
}
else
diff --git a/gcc-4.9/gcc/config/arm/vfp.md b/gcc-4.9/gcc/config/arm/vfp.md
index e1a48ee..7646484 100644
--- a/gcc-4.9/gcc/config/arm/vfp.md
+++ b/gcc-4.9/gcc/config/arm/vfp.md
@@ -1254,17 +1254,15 @@
)
(define_insn "*combine_vcvtf2i"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t")
+ [(set (match_operand:SI 0 "s_register_operand" "=t")
+ (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "0")
(match_operand 2
"const_double_vcvt_power_of_two" "Dp")))))]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
- "vcvt%?.s32.f32\\t%1, %1, %v2\;vmov%?\\t%0, %1"
+ "vcvt%?.s32.f32\\t%0, %1, %v2"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set_attr "ce_count" "2")
- (set_attr "type" "f_cvtf2i")
- (set_attr "length" "8")]
+ (set_attr "type" "f_cvtf2i")]
)
;; Store multiple insn used in function prologue.
diff --git a/gcc-4.9/gcc/config/i386/driver-i386.c b/gcc-4.9/gcc/config/i386/driver-i386.c
index 80f6a08..722c546 100644
--- a/gcc-4.9/gcc/config/i386/driver-i386.c
+++ b/gcc-4.9/gcc/config/i386/driver-i386.c
@@ -431,7 +431,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
model = (eax >> 4) & 0x0f;
family = (eax >> 8) & 0x0f;
- if (vendor == signature_INTEL_ebx)
+ if (vendor == signature_INTEL_ebx
+ || vendor == signature_AMD_ebx)
{
unsigned int extended_model, extended_family;
@@ -570,7 +571,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
if (name == signature_NSC_ebx)
processor = PROCESSOR_GEODE;
- else if (has_movbe)
+ else if (has_movbe && family == 22)
processor = PROCESSOR_BTVER2;
else if (has_avx2)
processor = PROCESSOR_BDVER4;
diff --git a/gcc-4.9/gcc/config/i386/i386.c b/gcc-4.9/gcc/config/i386/i386.c
index 8a1fbde..fcd5f0d 100644
--- a/gcc-4.9/gcc/config/i386/i386.c
+++ b/gcc-4.9/gcc/config/i386/i386.c
@@ -3260,12 +3260,13 @@ ix86_option_override_internal (bool main_args_p,
| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
| PTA_XSAVEOPT | PTA_FSGSBASE},
{"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+ | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+ | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
| PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
| PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
- | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE},
+ | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
+ | PTA_MOVBE},
{"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
@@ -45349,8 +45350,10 @@ ix86_expand_sse2_mulvxdi3 (rtx op0, rtx op1, rtx op2)
/* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
emit_insn (gen_ashlv2di3 (t4, t3, GEN_INT (32)));
- /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
- emit_insn (gen_xop_pmacsdql (op0, op1, op2, t4));
+ /* Multiply lower parts and add all */
+ t5 = gen_reg_rtx (V2DImode);
+ emit_insn (gen_vec_widen_umult_even_v4si (t5, gen_lowpart (V4SImode, op1), gen_lowpart (V4SImode, op2)));
+ op0 = expand_binop (mode, add_optab, t5, t4, op0, 1, OPTAB_DIRECT);
}
else
{
diff --git a/gcc-4.9/gcc/config/i386/i386.h b/gcc-4.9/gcc/config/i386/i386.h
index fb52741..f6b169c 100644
--- a/gcc-4.9/gcc/config/i386/i386.h
+++ b/gcc-4.9/gcc/config/i386/i386.h
@@ -461,6 +461,8 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];
ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS]
#define TARGET_ADJUST_UNROLL \
ix86_tune_features[X86_TUNE_ADJUST_UNROLL]
+#define TARGET_AVOID_FALSE_DEP_FOR_BMI \
+ ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI]
/* Feature tests against the various architecture variations. */
enum ix86_arch_indices {
diff --git a/gcc-4.9/gcc/config/i386/i386.md b/gcc-4.9/gcc/config/i386/i386.md
index 0587029..39d3958 100644
--- a/gcc-4.9/gcc/config/i386/i386.md
+++ b/gcc-4.9/gcc/config/i386/i386.md
@@ -111,6 +111,7 @@
UNSPEC_LEA_ADDR
UNSPEC_XBEGIN_ABORT
UNSPEC_STOS
+ UNSPEC_INSN_FALSE_DEP
;; For SSE/MMX support:
UNSPEC_FIX_NOTRUNC
@@ -11878,7 +11879,8 @@
DONE;
}
- flags_mode = TARGET_BMI ? CCCmode : CCZmode;
+ flags_mode
+ = (TARGET_BMI && !TARGET_AVOID_FALSE_DEP_FOR_BMI) ? CCCmode : CCZmode;
operands[2] = gen_reg_rtx (<MODE>mode);
operands[3] = gen_rtx_REG (flags_mode, FLAGS_REG);
@@ -11904,7 +11906,8 @@
(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
(clobber (reg:CC FLAGS_REG))])]
{
- enum machine_mode flags_mode = TARGET_BMI ? CCCmode : CCZmode;
+ enum machine_mode flags_mode
+ = (TARGET_BMI && !TARGET_AVOID_FALSE_DEP_FOR_BMI) ? CCCmode : CCZmode;
operands[3] = gen_lowpart (QImode, operands[2]);
operands[4] = gen_rtx_REG (flags_mode, FLAGS_REG);
@@ -11919,7 +11922,7 @@
(const_int 0)))
(set (match_operand:SWI48 0 "register_operand" "=r")
(ctz:SWI48 (match_dup 1)))]
- "TARGET_BMI"
+ "TARGET_BMI && !TARGET_AVOID_FALSE_DEP_FOR_BMI"
"tzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
@@ -11940,7 +11943,58 @@
(set_attr "btver2_decode" "double")
(set_attr "mode" "<MODE>")])
-(define_insn "ctz<mode>2"
+(define_expand "ctz<mode>2"
+ [(parallel
+ [(set (match_operand:SWI248 0 "register_operand")
+ (ctz:SWI248
+ (match_operand:SWI248 1 "nonimmediate_operand")))
+ (clobber (reg:CC FLAGS_REG))])])
+
+; False dependency happens when destination is only updated by tzcnt,
+; lzcnt or popcnt. There is no false dependency when destination is
+; also used in source.
+(define_insn_and_split "*ctz<mode>2_falsedep_1"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (ctz:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "rm")))
+ (clobber (reg:CC FLAGS_REG))]
+ "(TARGET_BMI || TARGET_GENERIC)
+ && TARGET_AVOID_FALSE_DEP_FOR_BMI && optimize_function_for_speed_p (cfun)"
+ "#"
+ "&& reload_completed"
+ [(parallel
+ [(set (match_dup 0)
+ (ctz:SWI48 (match_dup 1)))
+ (unspec [(match_dup 0)] UNSPEC_INSN_FALSE_DEP)
+ (clobber (reg:CC FLAGS_REG))])]
+{
+ if (!reg_mentioned_p (operands[0], operands[1]))
+ ix86_expand_clear (operands[0]);
+})
+
+(define_insn "*ctz<mode>2_falsedep"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (ctz:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "rm")))
+ (unspec [(match_operand:SWI48 2 "register_operand" "0")]
+ UNSPEC_INSN_FALSE_DEP)
+ (clobber (reg:CC FLAGS_REG))]
+ ""
+{
+ if (TARGET_BMI)
+ return "tzcnt{<imodesuffix>}\t{%1, %0|%0, %1}";
+ else if (TARGET_GENERIC)
+ /* tzcnt expands to 'rep bsf' and we can use it even if !TARGET_BMI. */
+ return "rep%; bsf{<imodesuffix>}\t{%1, %0|%0, %1}";
+ else
+ gcc_unreachable ();
+}
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "prefix_rep" "1")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "*ctz<mode>2"
[(set (match_operand:SWI248 0 "register_operand" "=r")
(ctz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "rm")))
(clobber (reg:CC FLAGS_REG))]
@@ -11987,7 +12041,47 @@
operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1);
})
-(define_insn "clz<mode>2_lzcnt"
+(define_expand "clz<mode>2_lzcnt"
+ [(parallel
+ [(set (match_operand:SWI248 0 "register_operand")
+ (clz:SWI248
+ (match_operand:SWI248 1 "nonimmediate_operand")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_LZCNT")
+
+(define_insn_and_split "*clz<mode>2_lzcnt_falsedep_1"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (clz:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "rm")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_LZCNT
+ && TARGET_AVOID_FALSE_DEP_FOR_BMI && optimize_function_for_speed_p (cfun)"
+ "#"
+ "&& reload_completed"
+ [(parallel
+ [(set (match_dup 0)
+ (clz:SWI48 (match_dup 1)))
+ (unspec [(match_dup 0)] UNSPEC_INSN_FALSE_DEP)
+ (clobber (reg:CC FLAGS_REG))])]
+{
+ if (!reg_mentioned_p (operands[0], operands[1]))
+ ix86_expand_clear (operands[0]);
+})
+
+(define_insn "*clz<mode>2_lzcnt_falsedep"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (clz:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "rm")))
+ (unspec [(match_operand:SWI48 2 "register_operand" "0")]
+ UNSPEC_INSN_FALSE_DEP)
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_LZCNT"
+ "lzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
+ [(set_attr "prefix_rep" "1")
+ (set_attr "type" "bitmanip")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "*clz<mode>2_lzcnt"
[(set (match_operand:SWI248 0 "register_operand" "=r")
(clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "rm")))
(clobber (reg:CC FLAGS_REG))]
@@ -12270,10 +12364,39 @@
(set_attr "prefix_0f" "1")
(set_attr "mode" "HI")])
-(define_insn "popcount<mode>2"
- [(set (match_operand:SWI248 0 "register_operand" "=r")
- (popcount:SWI248
- (match_operand:SWI248 1 "nonimmediate_operand" "rm")))
+(define_expand "popcount<mode>2"
+ [(parallel
+ [(set (match_operand:SWI248 0 "register_operand")
+ (popcount:SWI248
+ (match_operand:SWI248 1 "nonimmediate_operand")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_POPCNT")
+
+(define_insn_and_split "*popcount<mode>2_falsedep_1"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (popcount:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "rm")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_POPCNT
+ && TARGET_AVOID_FALSE_DEP_FOR_BMI && optimize_function_for_speed_p (cfun)"
+ "#"
+ "&& reload_completed"
+ [(parallel
+ [(set (match_dup 0)
+ (popcount:SWI48 (match_dup 1)))
+ (unspec [(match_dup 0)] UNSPEC_INSN_FALSE_DEP)
+ (clobber (reg:CC FLAGS_REG))])]
+{
+ if (!reg_mentioned_p (operands[0], operands[1]))
+ ix86_expand_clear (operands[0]);
+})
+
+(define_insn "*popcount<mode>2_falsedep"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (popcount:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand" "rm")))
+ (unspec [(match_operand:SWI48 2 "register_operand" "0")]
+ UNSPEC_INSN_FALSE_DEP)
(clobber (reg:CC FLAGS_REG))]
"TARGET_POPCNT"
{
@@ -12287,15 +12410,12 @@
(set_attr "type" "bitmanip")
(set_attr "mode" "<MODE>")])
-(define_insn "*popcount<mode>2_cmp"
- [(set (reg FLAGS_REG)
- (compare
- (popcount:SWI248
- (match_operand:SWI248 1 "nonimmediate_operand" "rm"))
- (const_int 0)))
- (set (match_operand:SWI248 0 "register_operand" "=r")
- (popcount:SWI248 (match_dup 1)))]
- "TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
+(define_insn "*popcount<mode>2"
+ [(set (match_operand:SWI248 0 "register_operand" "=r")
+ (popcount:SWI248
+ (match_operand:SWI248 1 "nonimmediate_operand" "rm")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_POPCNT"
{
#if TARGET_MACHO
return "popcnt\t{%1, %0|%0, %1}";
@@ -12307,25 +12427,6 @@
(set_attr "type" "bitmanip")
(set_attr "mode" "<MODE>")])
-(define_insn "*popcountsi2_cmp_zext"
- [(set (reg FLAGS_REG)
- (compare
- (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI(popcount:SI (match_dup 1))))]
- "TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
-{
-#if TARGET_MACHO
- return "popcnt\t{%1, %0|%0, %1}";
-#else
- return "popcnt{l}\t{%1, %0|%0, %1}";
-#endif
-}
- [(set_attr "prefix_rep" "1")
- (set_attr "type" "bitmanip")
- (set_attr "mode" "SI")])
-
(define_expand "bswapdi2"
[(set (match_operand:DI 0 "register_operand")
(bswap:DI (match_operand:DI 1 "nonimmediate_operand")))]
diff --git a/gcc-4.9/gcc/config/i386/sse.md b/gcc-4.9/gcc/config/i386/sse.md
index 57e2daa..4aced2d 100644
--- a/gcc-4.9/gcc/config/i386/sse.md
+++ b/gcc-4.9/gcc/config/i386/sse.md
@@ -5994,9 +5994,9 @@
(set_attr "mode" "<sseinsnmode>")])
(define_insn "vec_extract_lo_<mode><mask_name>"
- [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=<store_mask_constraint>")
+ [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=<store_mask_constraint>,v")
(vec_select:<ssehalfvecmode>
- (match_operand:V8FI 1 "nonimmediate_operand" "vm")
+ (match_operand:V8FI 1 "nonimmediate_operand" "v,m")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))]
"TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
diff --git a/gcc-4.9/gcc/config/i386/x86-tune.def b/gcc-4.9/gcc/config/i386/x86-tune.def
index cb44dc3..b7a703f 100644
--- a/gcc-4.9/gcc/config/i386/x86-tune.def
+++ b/gcc-4.9/gcc/config/i386/x86-tune.def
@@ -509,6 +509,11 @@ DEF_TUNE (X86_TUNE_NOT_VECTORMODE, "not_vectormode", m_K6)
DEF_TUNE (X86_TUNE_AVOID_VECTOR_DECODE, "avoid_vector_decode",
m_K8)
+/* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
+ for bit-manipulation instructions. */
+DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI, "avoid_false_dep_for_bmi",
+ m_SANDYBRIDGE | m_HASWELL | m_INTEL | m_GENERIC)
+
/*****************************************************************************/
/* This never worked well before. */
/*****************************************************************************/
diff --git a/gcc-4.9/gcc/config/nios2/rtems.h b/gcc-4.9/gcc/config/nios2/rtems.h
new file mode 100644
index 0000000..18caa58
--- /dev/null
+++ b/gcc-4.9/gcc/config/nios2/rtems.h
@@ -0,0 +1,34 @@
+/* Definitions for rtems targeting a NIOS2 using ELF.
+ Copyright (C) 2011-2014 Free Software Foundation, Inc.
+
+ Contributed by Chris Johns (chrisj@rtems.org).
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+/* Specify predefined symbols in preprocessor. */
+#define TARGET_OS_CPP_BUILTINS() \
+do { \
+ builtin_define ("__rtems__"); \
+ builtin_define ("__USE_INIT_FINI__"); \
+ builtin_assert ("system=rtems"); \
+} while (0)
+
+/* This toolchain implements the ABI for Linux Systems documented in the
+ Nios II Processor Reference Handbook.
+
+ This is done so RTEMS targets have Thread Local Storage like Linux. */
+#define TARGET_LINUX_ABI 1
diff --git a/gcc-4.9/gcc/config/nios2/t-rtems b/gcc-4.9/gcc/config/nios2/t-rtems
new file mode 100644
index 0000000..f95fa3c
--- /dev/null
+++ b/gcc-4.9/gcc/config/nios2/t-rtems
@@ -0,0 +1,133 @@
+# Custom RTEMS multilibs
+
+MULTILIB_OPTIONS = mhw-mul mhw-mulx mhw-div mcustom-fadds=253 mcustom-fdivs=255 mcustom-fmuls=252 mcustom-fsubs=254
+
+# Enumeration of multilibs
+
+# MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fsubs=254
+# MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mhw-div
+MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253
+MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fsubs=254
+# MULTILIB_EXCEPTIONS += mhw-mul
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div
+MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253
+MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-mulx
+MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253
+MULTILIB_EXCEPTIONS += mhw-div/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-div/mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-div/mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-div/mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mhw-div/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-div/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mhw-div/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mhw-div
+MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mcustom-fadds=253
+MULTILIB_EXCEPTIONS += mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mcustom-fdivs=255/mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mcustom-fdivs=255/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mcustom-fdivs=255
+MULTILIB_EXCEPTIONS += mcustom-fmuls=252/mcustom-fsubs=254
+MULTILIB_EXCEPTIONS += mcustom-fmuls=252
+MULTILIB_EXCEPTIONS += mcustom-fsubs=254
diff --git a/gcc-4.9/gcc/config/pa/pa-protos.h b/gcc-4.9/gcc/config/pa/pa-protos.h
index 2659dcd..1e48da5 100644
--- a/gcc-4.9/gcc/config/pa/pa-protos.h
+++ b/gcc-4.9/gcc/config/pa/pa-protos.h
@@ -49,6 +49,8 @@ extern const char *pa_output_mul_insn (int, rtx);
extern const char *pa_output_div_insn (rtx *, int, rtx);
extern const char *pa_output_mod_insn (int, rtx);
extern const char *pa_singlemove_string (rtx *);
+extern void pa_output_addr_vec (rtx, rtx);
+extern void pa_output_addr_diff_vec (rtx, rtx);
extern void pa_output_arg_descriptor (rtx);
extern void pa_output_global_address (FILE *, rtx, int);
extern void pa_print_operand (FILE *, rtx, int);
diff --git a/gcc-4.9/gcc/config/pa/pa.c b/gcc-4.9/gcc/config/pa/pa.c
index 871e4e5..5a7598c 100644
--- a/gcc-4.9/gcc/config/pa/pa.c
+++ b/gcc-4.9/gcc/config/pa/pa.c
@@ -4155,8 +4155,7 @@ static void
pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
{
rtx insn = get_last_insn ();
-
- last_address = 0;
+ bool extra_nop;
/* pa_expand_epilogue does the dirty work now. We just need
to output the assembler directives which denote the end
@@ -4180,8 +4179,10 @@ pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
if (insn && CALL_P (insn))
{
fputs ("\tnop\n", file);
- last_address += 4;
+ extra_nop = true;
}
+ else
+ extra_nop = false;
fputs ("\t.EXIT\n\t.PROCEND\n", file);
@@ -4194,12 +4195,13 @@ pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
cfun->machine->in_nsubspa = 2;
}
- /* Thunks do their own accounting. */
+ /* Thunks do their own insn accounting. */
if (cfun->is_thunk)
return;
if (INSN_ADDRESSES_SET_P ())
{
+ last_address = extra_nop ? 4 : 0;
insn = get_last_nonnote_insn ();
last_address += INSN_ADDRESSES (INSN_UID (insn));
if (INSN_P (insn))
@@ -8293,12 +8295,16 @@ pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
|| ((DECL_SECTION_NAME (thunk_fndecl)
== DECL_SECTION_NAME (function))
&& last_address < 262132)))
+ /* In this case, we need to be able to reach the start of
+ the stub table even though the function is likely closer
+ and can be jumped to directly. */
|| (targetm_common.have_named_sections
&& DECL_SECTION_NAME (thunk_fndecl) == NULL
&& DECL_SECTION_NAME (function) == NULL
- && last_address < 262132)
+ && total_code_bytes < MAX_PCREL17F_OFFSET)
+ /* Likewise. */
|| (!targetm_common.have_named_sections
- && last_address < 262132))))
+ && total_code_bytes < MAX_PCREL17F_OFFSET))))
{
if (!val_14)
output_asm_insn ("addil L'%2,%%r26", xoperands);
@@ -8944,40 +8950,15 @@ pa_following_call (rtx insn)
}
/* We use this hook to perform a PA specific optimization which is difficult
- to do in earlier passes.
-
- We surround the jump table itself with BEGIN_BRTAB and END_BRTAB
- insns. Those insns mark where we should emit .begin_brtab and
- .end_brtab directives when using GAS. This allows for better link
- time optimizations. */
+ to do in earlier passes. */
static void
pa_reorg (void)
{
- rtx insn;
-
remove_useless_addtr_insns (1);
if (pa_cpu < PROCESSOR_8000)
pa_combine_instructions ();
-
- /* Still need brtab marker insns. FIXME: the presence of these
- markers disables output of the branch table to readonly memory,
- and any alignment directives that might be needed. Possibly,
- the begin_brtab insn should be output before the label for the
- table. This doesn't matter at the moment since the tables are
- always output in the text section. */
- for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
- {
- /* Find an ADDR_VEC insn. */
- if (! JUMP_TABLE_DATA_P (insn))
- continue;
-
- /* Now generate markers for the beginning and end of the
- branch table. */
- emit_insn_before (gen_begin_brtab (), insn);
- emit_insn_after (gen_end_brtab (), insn);
- }
}
/* The PA has a number of odd instructions which can perform multiple
@@ -10572,4 +10553,46 @@ pa_legitimize_reload_address (rtx ad, enum machine_mode mode,
return NULL_RTX;
}
+/* Output address vector. */
+
+void
+pa_output_addr_vec (rtx lab, rtx body)
+{
+ int idx, vlen = XVECLEN (body, 0);
+
+ targetm.asm_out.internal_label (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
+ if (TARGET_GAS)
+ fputs ("\t.begin_brtab\n", asm_out_file);
+ for (idx = 0; idx < vlen; idx++)
+ {
+ ASM_OUTPUT_ADDR_VEC_ELT
+ (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
+ }
+ if (TARGET_GAS)
+ fputs ("\t.end_brtab\n", asm_out_file);
+}
+
+/* Output address difference vector. */
+
+void
+pa_output_addr_diff_vec (rtx lab, rtx body)
+{
+ rtx base = XEXP (XEXP (body, 0), 0);
+ int idx, vlen = XVECLEN (body, 1);
+
+ targetm.asm_out.internal_label (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
+ if (TARGET_GAS)
+ fputs ("\t.begin_brtab\n", asm_out_file);
+ for (idx = 0; idx < vlen; idx++)
+ {
+ ASM_OUTPUT_ADDR_DIFF_ELT
+ (asm_out_file,
+ body,
+ CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
+ CODE_LABEL_NUMBER (base));
+ }
+ if (TARGET_GAS)
+ fputs ("\t.end_brtab\n", asm_out_file);
+}
+
#include "gt-pa.h"
diff --git a/gcc-4.9/gcc/config/pa/pa.h b/gcc-4.9/gcc/config/pa/pa.h
index ac3f0eb..f6c9751 100644
--- a/gcc-4.9/gcc/config/pa/pa.h
+++ b/gcc-4.9/gcc/config/pa/pa.h
@@ -1193,6 +1193,16 @@ do { \
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL)
+/* This is how to output an absolute case-vector. */
+
+#define ASM_OUTPUT_ADDR_VEC(LAB,BODY) \
+ pa_output_addr_vec ((LAB),(BODY))
+
+/* This is how to output a relative case-vector. */
+
+#define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,BODY) \
+ pa_output_addr_diff_vec ((LAB),(BODY))
+
/* This is how to output an assembler line that says to advance the
location counter to a multiple of 2**LOG bytes. */
diff --git a/gcc-4.9/gcc/config/pa/pa.md b/gcc-4.9/gcc/config/pa/pa.md
index e55d0b8..a9421ac 100644
--- a/gcc-4.9/gcc/config/pa/pa.md
+++ b/gcc-4.9/gcc/config/pa/pa.md
@@ -8508,36 +8508,6 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
[(set_attr "type" "move")
(set_attr "length" "4")])
-;; These are just placeholders so we know where branch tables
-;; begin and end.
-(define_insn "begin_brtab"
- [(const_int 1)]
- ""
- "*
-{
- /* Only GAS actually supports this pseudo-op. */
- if (TARGET_GAS)
- return \".begin_brtab\";
- else
- return \"\";
-}"
- [(set_attr "type" "move")
- (set_attr "length" "0")])
-
-(define_insn "end_brtab"
- [(const_int 2)]
- ""
- "*
-{
- /* Only GAS actually supports this pseudo-op. */
- if (TARGET_GAS)
- return \".end_brtab\";
- else
- return \"\";
-}"
- [(set_attr "type" "move")
- (set_attr "length" "0")])
-
;;; EH does longjmp's from and within the data section. Thus,
;;; an interspace branch is required for the longjmp implementation.
;;; Registers r1 and r2 are used as scratch registers for the jump
diff --git a/gcc-4.9/gcc/config/rs6000/constraints.md b/gcc-4.9/gcc/config/rs6000/constraints.md
index 9d6a3bb..78a3ff0 100644
--- a/gcc-4.9/gcc/config/rs6000/constraints.md
+++ b/gcc-4.9/gcc/config/rs6000/constraints.md
@@ -68,6 +68,20 @@
(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]"
"If -mmfpgpr was used, a floating point register or NO_REGS.")
+(define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]"
+ "Floating point register if direct moves are available, or NO_REGS.")
+
+;; At present, DImode is not allowed in the Altivec registers. If in the
+;; future it is allowed, wi/wj can be set to VSX_REGS instead of FLOAT_REGS.
+(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
+ "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.")
+
+(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]"
+ "FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.")
+
+(define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]"
+ "FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.")
+
(define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]"
"Floating point register if the LFIWAX instruction is enabled or NO_REGS.")
@@ -101,7 +115,7 @@
"Floating point register if the STFIWX instruction is enabled or NO_REGS.")
(define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]"
- "VSX vector register to hold scalar float values or NO_REGS.")
+ "FP or VSX register to perform ISA 2.07 float ops or NO_REGS.")
(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"
"Floating point register if the LFIWZX instruction is enabled or NO_REGS.")
diff --git a/gcc-4.9/gcc/config/rs6000/rs6000.c b/gcc-4.9/gcc/config/rs6000/rs6000.c
index d7cbc6c..28ccf86 100644
--- a/gcc-4.9/gcc/config/rs6000/rs6000.c
+++ b/gcc-4.9/gcc/config/rs6000/rs6000.c
@@ -388,6 +388,7 @@ struct rs6000_reg_addr {
enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
+ bool scalar_in_vmx_p; /* Scalar value can go in VMX. */
};
static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
@@ -1221,7 +1222,12 @@ char rs6000_reg_names[][8] =
/* Soft frame pointer. */
"sfp",
/* HTM SPR registers. */
- "tfhar", "tfiar", "texasr"
+ "tfhar", "tfiar", "texasr",
+ /* SPE High registers. */
+ "0", "1", "2", "3", "4", "5", "6", "7",
+ "8", "9", "10", "11", "12", "13", "14", "15",
+ "16", "17", "18", "19", "20", "21", "22", "23",
+ "24", "25", "26", "27", "28", "29", "30", "31"
};
#ifdef TARGET_REGNAMES
@@ -1249,7 +1255,12 @@ static const char alt_reg_names[][8] =
/* Soft frame pointer. */
"sfp",
/* HTM SPR registers. */
- "tfhar", "tfiar", "texasr"
+ "tfhar", "tfiar", "texasr",
+ /* SPE High registers. */
+ "%rh0", "%rh1", "%rh2", "%rh3", "%rh4", "%rh5", "%rh6", "%rh7",
+ "%rh8", "%rh9", "%rh10", "%r11", "%rh12", "%rh13", "%rh14", "%rh15",
+ "%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23",
+ "%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31"
};
#endif
@@ -1723,8 +1734,7 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
asked for it. */
if (TARGET_VSX && VSX_REGNO_P (regno)
&& (VECTOR_MEM_VSX_P (mode)
- || (TARGET_VSX_SCALAR_FLOAT && mode == SFmode)
- || (TARGET_VSX_SCALAR_DOUBLE && (mode == DFmode || mode == DImode))
+ || reg_addr[mode].scalar_in_vmx_p
|| (TARGET_VSX_TIMODE && mode == TImode)
|| (TARGET_VADDUQM && mode == V1TImode)))
{
@@ -1733,10 +1743,7 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
if (ALTIVEC_REGNO_P (regno))
{
- if (mode == SFmode && !TARGET_UPPER_REGS_SF)
- return 0;
-
- if ((mode == DFmode || mode == DImode) && !TARGET_UPPER_REGS_DF)
+ if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p)
return 0;
return ALTIVEC_REGNO_P (last_regno);
@@ -1916,14 +1923,16 @@ rs6000_debug_print_mode (ssize_t m)
if (rs6000_vector_unit[m] != VECTOR_NONE
|| rs6000_vector_mem[m] != VECTOR_NONE
|| (reg_addr[m].reload_store != CODE_FOR_nothing)
- || (reg_addr[m].reload_load != CODE_FOR_nothing))
+ || (reg_addr[m].reload_load != CODE_FOR_nothing)
+ || reg_addr[m].scalar_in_vmx_p)
{
fprintf (stderr,
- " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c",
+ " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c Upper=%c",
rs6000_debug_vector_unit (rs6000_vector_unit[m]),
rs6000_debug_vector_unit (rs6000_vector_mem[m]),
(reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
- (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
+ (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*',
+ (reg_addr[m].scalar_in_vmx_p) ? 'y' : 'n');
}
fputs ("\n", stderr);
@@ -2040,6 +2049,10 @@ rs6000_debug_reg_global (void)
"wd reg_class = %s\n"
"wf reg_class = %s\n"
"wg reg_class = %s\n"
+ "wh reg_class = %s\n"
+ "wi reg_class = %s\n"
+ "wj reg_class = %s\n"
+ "wk reg_class = %s\n"
"wl reg_class = %s\n"
"wm reg_class = %s\n"
"wr reg_class = %s\n"
@@ -2059,6 +2072,10 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wh]],
+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]],
+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
@@ -2347,6 +2364,8 @@ rs6000_setup_reg_addr_masks (void)
for (m = 0; m < NUM_MACHINE_MODES; ++m)
{
+ enum machine_mode m2 = (enum machine_mode)m;
+
/* SDmode is special in that we want to access it only via REG+REG
addressing on power7 and above, since we want to use the LFIWZX and
STFIWZX instructions to load it. */
@@ -2381,13 +2400,12 @@ rs6000_setup_reg_addr_masks (void)
if (TARGET_UPDATE
&& (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
- && GET_MODE_SIZE (m) <= 8
- && !VECTOR_MODE_P (m)
- && !COMPLEX_MODE_P (m)
+ && GET_MODE_SIZE (m2) <= 8
+ && !VECTOR_MODE_P (m2)
+ && !COMPLEX_MODE_P (m2)
&& !indexed_only_p
- && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m) == 8)
- && !(m == DFmode && TARGET_UPPER_REGS_DF)
- && !(m == SFmode && TARGET_UPPER_REGS_SF))
+ && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m2) == 8)
+ && !reg_addr[m2].scalar_in_vmx_p)
{
addr_mask |= RELOAD_REG_PRE_INCDEC;
@@ -2618,37 +2636,44 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
f - Register class to use with traditional SFmode instructions.
v - Altivec register.
wa - Any VSX register.
+ wc - Reserved to represent individual CR bits (used in LLVM).
wd - Preferred register class for V2DFmode.
wf - Preferred register class for V4SFmode.
wg - Float register for power6x move insns.
+ wh - FP register for direct move instructions.
+ wi - FP or VSX register to hold 64-bit integers for VSX insns.
+ wj - FP or VSX register to hold 64-bit integers for direct moves.
+ wk - FP or VSX register to hold 64-bit doubles for direct moves.
wl - Float register if we can do 32-bit signed int loads.
wm - VSX register for ISA 2.07 direct move operations.
+ wn - always NO_REGS.
wr - GPR if 64-bit mode is permitted.
ws - Register class to do ISA 2.06 DF operations.
+ wt - VSX register for TImode in VSX registers.
wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
- wt - VSX register for TImode in VSX registers.
ww - Register class to do SF conversions in with VSX operations.
wx - Float register if we can do 32-bit int stores.
wy - Register class to do ISA 2.07 SF operations.
wz - Float register if we can do 32-bit unsigned int loads. */
if (TARGET_HARD_FLOAT && TARGET_FPRS)
- rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;
+ rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
- rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS;
+ rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
if (TARGET_VSX)
{
rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
- rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;
- rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS;
+ rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
+ rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
+ rs6000_constraints[RS6000_CONSTRAINT_wi] = FLOAT_REGS; /* DImode */
if (TARGET_VSX_TIMODE)
- rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS;
+ rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
- if (TARGET_UPPER_REGS_DF)
+ if (TARGET_UPPER_REGS_DF) /* DFmode */
{
rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS;
@@ -2662,19 +2687,26 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_ALTIVEC)
rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
- if (TARGET_MFPGPR)
+ if (TARGET_MFPGPR) /* DFmode */
rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
if (TARGET_LFIWAX)
- rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS;
+ rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */
if (TARGET_DIRECT_MOVE)
- rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
+ {
+ rs6000_constraints[RS6000_CONSTRAINT_wh] = FLOAT_REGS;
+ rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */
+ = rs6000_constraints[RS6000_CONSTRAINT_wi];
+ rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */
+ = rs6000_constraints[RS6000_CONSTRAINT_ws];
+ rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
+ }
if (TARGET_POWERPC64)
rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
- if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF)
+ if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) /* SFmode */
{
rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
@@ -2689,10 +2721,10 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
if (TARGET_STFIWX)
- rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS;
+ rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
if (TARGET_LFIWZX)
- rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS;
+ rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */
/* Set up the reload helper and direct move functions. */
if (TARGET_VSX || TARGET_ALTIVEC)
@@ -2715,10 +2747,11 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
if (TARGET_VSX && TARGET_UPPER_REGS_DF)
{
- reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
- reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
- reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
- reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
+ reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
+ reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
+ reg_addr[DFmode].scalar_in_vmx_p = true;
+ reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
+ reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
}
if (TARGET_P8_VECTOR)
{
@@ -2726,6 +2759,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
+ if (TARGET_UPPER_REGS_SF)
+ reg_addr[SFmode].scalar_in_vmx_p = true;
}
if (TARGET_VSX_TIMODE)
{
@@ -2782,10 +2817,11 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
if (TARGET_VSX && TARGET_UPPER_REGS_DF)
{
- reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
- reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
- reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
- reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
+ reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
+ reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
+ reg_addr[DFmode].scalar_in_vmx_p = true;
+ reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
+ reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
}
if (TARGET_P8_VECTOR)
{
@@ -2793,6 +2829,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
+ if (TARGET_UPPER_REGS_SF)
+ reg_addr[SFmode].scalar_in_vmx_p = true;
}
if (TARGET_VSX_TIMODE)
{
@@ -2833,6 +2871,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
for (m = 0; m < NUM_MACHINE_MODES; ++m)
{
+ enum machine_mode m2 = (enum machine_mode)m;
int reg_size2 = reg_size;
/* TFmode/TDmode always takes 2 registers, even in VSX. */
@@ -2841,7 +2880,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_size2 = UNITS_PER_FP_WORD;
rs6000_class_max_nregs[m][c]
- = (GET_MODE_SIZE (m) + reg_size2 - 1) / reg_size2;
+ = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
}
}
@@ -17167,7 +17206,14 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
prefer Altivec loads.. */
if (rclass == VSX_REGS)
{
- if (GET_MODE_SIZE (mode) <= 8)
+ if (MEM_P (x) && reg_addr[mode].scalar_in_vmx_p)
+ {
+ rtx addr = XEXP (x, 0);
+ if (rs6000_legitimate_offset_address_p (mode, addr, false, true)
+ || legitimate_lo_sum_address_p (mode, addr, false))
+ return FLOAT_REGS;
+ }
+ else if (GET_MODE_SIZE (mode) <= 8 && !reg_addr[mode].scalar_in_vmx_p)
return FLOAT_REGS;
if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
@@ -31171,13 +31217,13 @@ rs6000_dwarf_register_span (rtx reg)
{
if (BYTES_BIG_ENDIAN)
{
- parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
+ parts[2 * i] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
}
else
{
parts[2 * i] = gen_rtx_REG (SImode, regno);
- parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
+ parts[2 * i + 1] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
}
}
@@ -31197,11 +31243,11 @@ rs6000_init_dwarf_reg_sizes_extra (tree address)
rtx mem = gen_rtx_MEM (BLKmode, addr);
rtx value = gen_int_mode (4, mode);
- for (i = 1201; i < 1232; i++)
+ for (i = FIRST_SPE_HIGH_REGNO; i < LAST_SPE_HIGH_REGNO+1; i++)
{
- int column = DWARF_REG_TO_UNWIND_COLUMN (i);
- HOST_WIDE_INT offset
- = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
+ int column = DWARF_REG_TO_UNWIND_COLUMN
+ (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
+ HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
emit_move_insn (adjust_address (mem, mode, offset), value);
}
@@ -31220,9 +31266,9 @@ rs6000_init_dwarf_reg_sizes_extra (tree address)
for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
{
- int column = DWARF_REG_TO_UNWIND_COLUMN (i);
- HOST_WIDE_INT offset
- = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
+ int column = DWARF_REG_TO_UNWIND_COLUMN
+ (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
+ HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
emit_move_insn (adjust_address (mem, mode, offset), value);
}
@@ -31254,9 +31300,8 @@ rs6000_dbx_register_number (unsigned int regno)
return 99;
if (regno == SPEFSCR_REGNO)
return 612;
- /* SPE high reg number. We get these values of regno from
- rs6000_dwarf_register_span. */
- gcc_assert (regno >= 1200 && regno < 1232);
+ if (SPE_HIGH_REGNO_P (regno))
+ return regno - FIRST_SPE_HIGH_REGNO + 1200;
return regno;
}
diff --git a/gcc-4.9/gcc/config/rs6000/rs6000.h b/gcc-4.9/gcc/config/rs6000/rs6000.h
index 2b5d033..f363867 100644
--- a/gcc-4.9/gcc/config/rs6000/rs6000.h
+++ b/gcc-4.9/gcc/config/rs6000/rs6000.h
@@ -930,35 +930,36 @@ enum data_align { align_abi, align_opt, align_both };
The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
-#define FIRST_PSEUDO_REGISTER 117
+#define FIRST_PSEUDO_REGISTER 149
/* This must be included for pre gcc 3.0 glibc compatibility. */
#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
-/* Add 32 dwarf columns for synthetic SPE registers. */
-#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32)
+/* True if register is an SPE High register. */
+#define SPE_HIGH_REGNO_P(N) \
+ ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO)
+
+/* SPE high registers added as hard regs.
+ The sfp register and 3 HTM registers
+ aren't included in DWARF_FRAME_REGISTERS. */
+#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
/* The SPE has an additional 32 synthetic registers, with DWARF debug
info numbering for these registers starting at 1200. While eh_frame
register numbering need not be the same as the debug info numbering,
- we choose to number these regs for eh_frame at 1200 too. This allows
- future versions of the rs6000 backend to add hard registers and
- continue to use the gcc hard register numbering for eh_frame. If the
- extra SPE registers in eh_frame were numbered starting from the
- current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
- changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
- avoid invalidating older SPE eh_frame info.
+ we choose to number these regs for eh_frame at 1200 too.
We must map them here to avoid huge unwinder tables mostly consisting
of unused space. */
#define DWARF_REG_TO_UNWIND_COLUMN(r) \
- ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))
+ ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))
/* Use standard DWARF numbering for DWARF debugging information. */
#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
/* Use gcc hard register numbering for eh_frame. */
-#define DWARF_FRAME_REGNUM(REGNO) (REGNO)
+#define DWARF_FRAME_REGNUM(REGNO) \
+ (SPE_HIGH_REGNO_P (REGNO) ? ((REGNO) - FIRST_SPE_HIGH_REGNO + 1200) : (REGNO))
/* Map register numbers held in the call frame info that gcc has
collected using DWARF_FRAME_REGNUM to those that should be output in
@@ -992,7 +993,10 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1 \
- , 1, 1, 1, 1, 1, 1 \
+ , 1, 1, 1, 1, 1, 1, \
+ /* SPE High registers. */ \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
}
/* 1 for registers not available across function calls.
@@ -1012,7 +1016,10 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1 \
- , 1, 1, 1, 1, 1, 1 \
+ , 1, 1, 1, 1, 1, 1, \
+ /* SPE High registers. */ \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
}
/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
@@ -1031,7 +1038,10 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0 \
- , 0, 0, 0, 0, 0, 0 \
+ , 0, 0, 0, 0, 0, 0, \
+ /* SPE High registers. */ \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
}
#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
@@ -1114,7 +1124,10 @@ enum data_align { align_abi, align_opt, align_both };
96, 95, 94, 93, 92, 91, \
108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
109, 110, \
- 111, 112, 113, 114, 115, 116 \
+ 111, 112, 113, 114, 115, 116, \
+ 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \
+ 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \
+ 141, 142, 143, 144, 145, 146, 147, 148 \
}
/* True if register is floating-point. */
@@ -1349,6 +1362,7 @@ enum reg_class
CR_REGS,
NON_FLOAT_REGS,
CA_REGS,
+ SPE_HIGH_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
@@ -1380,6 +1394,7 @@ enum reg_class
"CR_REGS", \
"NON_FLOAT_REGS", \
"CA_REGS", \
+ "SPE_HIGH_REGS", \
"ALL_REGS" \
}
@@ -1387,30 +1402,54 @@ enum reg_class
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */
-#define REG_CLASS_CONTENTS \
-{ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
- { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
- { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
- { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
- { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
- { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, /* SPR_REGS */ \
- { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
- { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
- { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
- { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
- { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, /* SPECIAL_REGS */ \
- { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
- { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
- { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
- { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \
- { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \
- { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } /* ALL_REGS */ \
+#define REG_CLASS_CONTENTS \
+{ \
+ /* NO_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
+ /* BASE_REGS. */ \
+ { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
+ /* GENERAL_REGS. */ \
+ { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
+ /* FLOAT_REGS. */ \
+ { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \
+ /* ALTIVEC_REGS. */ \
+ { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, \
+ /* VSX_REGS. */ \
+ { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, \
+ /* VRSAVE_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, \
+ /* VSCR_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, \
+ /* SPE_ACC_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, \
+ /* SPEFSCR_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, \
+ /* SPR_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, \
+ /* NON_SPECIAL_REGS. */ \
+ { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, \
+ /* LINK_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, \
+ /* CTR_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, \
+ /* LINK_OR_CTR_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, \
+ /* SPECIAL_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, \
+ /* SPEC_OR_GEN_REGS. */ \
+ { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, \
+ /* CR0_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, \
+ /* CR_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, \
+ /* NON_FLOAT_REGS. */ \
+ { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, \
+ /* CA_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, \
+ /* SPE_HIGH_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff }, \
+ /* ALL_REGS. */ \
+ { 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff } \
}
/* The same information, inverted:
@@ -1439,6 +1478,10 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */
+ RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */
+ RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */
+ RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */
+ RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */
RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */
RS6000_CONSTRAINT_wm, /* VSX register for direct move */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
@@ -1463,6 +1506,9 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
#define VSX_REG_CLASS_P(CLASS) \
((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
+/* Return whether a given register class targets general purpose registers. */
+#define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS)
+
/* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use.
In general this is just CLASS; but on some machines
@@ -2349,6 +2395,39 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
&rs6000_reg_names[114][0], /* tfhar */ \
&rs6000_reg_names[115][0], /* tfiar */ \
&rs6000_reg_names[116][0], /* texasr */ \
+ \
+ &rs6000_reg_names[117][0], /* SPE rh0. */ \
+ &rs6000_reg_names[118][0], /* SPE rh1. */ \
+ &rs6000_reg_names[119][0], /* SPE rh2. */ \
+ &rs6000_reg_names[120][0], /* SPE rh3. */ \
+ &rs6000_reg_names[121][0], /* SPE rh4. */ \
+ &rs6000_reg_names[122][0], /* SPE rh5. */ \
+ &rs6000_reg_names[123][0], /* SPE rh6. */ \
+ &rs6000_reg_names[124][0], /* SPE rh7. */ \
+ &rs6000_reg_names[125][0], /* SPE rh8. */ \
+ &rs6000_reg_names[126][0], /* SPE rh9. */ \
+ &rs6000_reg_names[127][0], /* SPE rh10. */ \
+ &rs6000_reg_names[128][0], /* SPE rh11. */ \
+ &rs6000_reg_names[129][0], /* SPE rh12. */ \
+ &rs6000_reg_names[130][0], /* SPE rh13. */ \
+ &rs6000_reg_names[131][0], /* SPE rh14. */ \
+ &rs6000_reg_names[132][0], /* SPE rh15. */ \
+ &rs6000_reg_names[133][0], /* SPE rh16. */ \
+ &rs6000_reg_names[134][0], /* SPE rh17. */ \
+ &rs6000_reg_names[135][0], /* SPE rh18. */ \
+ &rs6000_reg_names[136][0], /* SPE rh19. */ \
+ &rs6000_reg_names[137][0], /* SPE rh20. */ \
+ &rs6000_reg_names[138][0], /* SPE rh21. */ \
+ &rs6000_reg_names[139][0], /* SPE rh22. */ \
+ &rs6000_reg_names[140][0], /* SPE rh22. */ \
+ &rs6000_reg_names[141][0], /* SPE rh24. */ \
+ &rs6000_reg_names[142][0], /* SPE rh25. */ \
+ &rs6000_reg_names[143][0], /* SPE rh26. */ \
+ &rs6000_reg_names[144][0], /* SPE rh27. */ \
+ &rs6000_reg_names[145][0], /* SPE rh28. */ \
+ &rs6000_reg_names[146][0], /* SPE rh29. */ \
+ &rs6000_reg_names[147][0], /* SPE rh30. */ \
+ &rs6000_reg_names[148][0], /* SPE rh31. */ \
}
/* Table of additional register names to use in user input. */
@@ -2404,7 +2483,17 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
{"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
{"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \
/* Transactional Memory Facility (HTM) Registers. */ \
- {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116} }
+ {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \
+ /* SPE high registers. */ \
+ {"rh0", 117}, {"rh1", 118}, {"rh2", 119}, {"rh3", 120}, \
+ {"rh4", 121}, {"rh5", 122}, {"rh6", 123}, {"rh7", 124}, \
+ {"rh8", 125}, {"rh9", 126}, {"rh10", 127}, {"rh11", 128}, \
+ {"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132}, \
+ {"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136}, \
+ {"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140}, \
+ {"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144}, \
+ {"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148}, \
+}
/* This is how to output an element of a case-vector that is relative. */
diff --git a/gcc-4.9/gcc/config/rs6000/rs6000.md b/gcc-4.9/gcc/config/rs6000/rs6000.md
index 26d0d15..d078491 100644
--- a/gcc-4.9/gcc/config/rs6000/rs6000.md
+++ b/gcc-4.9/gcc/config/rs6000/rs6000.md
@@ -56,6 +56,8 @@
(TFHAR_REGNO 114)
(TFIAR_REGNO 115)
(TEXASR_REGNO 116)
+ (FIRST_SPE_HIGH_REGNO 117)
+ (LAST_SPE_HIGH_REGNO 148)
])
;;
@@ -326,7 +328,7 @@
(define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
; Definitions for 32-bit fpr direct move
-(define_mode_attr f32_dm [(SF "wn") (SD "wm")])
+(define_mode_attr f32_dm [(SF "wn") (SD "wh")])
; These modes do not fit in integer registers in 32-bit mode.
; but on e500v2, the gpr are 64 bit registers
@@ -575,7 +577,7 @@
"")
(define_insn "*zero_extendsidi2_lfiwzx"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wu")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu")
(zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
"TARGET_POWERPC64 && TARGET_LFIWZX"
"@
@@ -745,7 +747,7 @@
"")
(define_insn "*extendsidi2_lfiwax"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wu")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
(sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
"TARGET_POWERPC64 && TARGET_LFIWAX"
"@
@@ -5623,7 +5625,7 @@
; We don't define lfiwax/lfiwzx with the normal definition, because we
; don't want to support putting SImode in FPR registers.
(define_insn "lfiwax"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
UNSPEC_LFIWAX))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
@@ -5703,7 +5705,7 @@
(set_attr "type" "fpload")])
(define_insn "lfiwzx"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
UNSPEC_LFIWZX))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
@@ -9457,8 +9459,8 @@
; ld/std require word-aligned displacements -> 'Y' constraint.
; List Y->r and r->Y before r->r for reload.
(define_insn "*mov<mode>_hardfloat64"
- [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm")
- (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))]
+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wk")
+ (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wk,r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -10237,8 +10239,8 @@
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
(define_insn "*movdi_internal64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm")
- (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi")
+ (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))]
"TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
@@ -10258,7 +10260,8 @@
mftgpr %0,%1
mffgpr %0,%1
mfvsrd %0,%x1
- mtvsrd %x0,%1"
+ mtvsrd %x0,%1
+ xxlxor %x0,%x0,%x0"
[(set_attr_alternative "type"
[(if_then_else
(match_test "update_indexed_address_mem (operands[0], VOIDmode)")
@@ -10299,8 +10302,9 @@
(const_string "mftgpr")
(const_string "mffgpr")
(const_string "mftgpr")
- (const_string "mffgpr")])
- (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")])
+ (const_string "mffgpr")
+ (const_string "vecsimple")])
+ (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")])
;; Generate all one-bits and clear left or right.
;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
diff --git a/gcc-4.9/gcc/config/rs6000/vsx.md b/gcc-4.9/gcc/config/rs6000/vsx.md
index 6d20eab..2cf5e7a 100644
--- a/gcc-4.9/gcc/config/rs6000/vsx.md
+++ b/gcc-4.9/gcc/config/rs6000/vsx.md
@@ -86,19 +86,26 @@
(V4SF "wf")
(V2DI "wd")
(V2DF "wd")
+ (DI "wi")
(DF "ws")
- (SF "d")
+ (SF "ww")
(V1TI "v")
(TI "wt")])
-;; Map the register class used for float<->int conversions
+;; Map the register class used for float<->int conversions (floating point side)
+;; VSr2 is the preferred register class, VSr3 is any register class that will
+;; hold the data
(define_mode_attr VSr2 [(V2DF "wd")
(V4SF "wf")
- (DF "ws")])
+ (DF "ws")
+ (SF "ww")
+ (DI "wi")])
(define_mode_attr VSr3 [(V2DF "wa")
(V4SF "wa")
- (DF "ws")])
+ (DF "ws")
+ (SF "ww")
+ (DI "wi")])
;; Map the register class for sp<->dp float conversions, destination
(define_mode_attr VSr4 [(SF "ws")
@@ -106,12 +113,27 @@
(V2DF "wd")
(V4SF "v")])
-;; Map the register class for sp<->dp float conversions, destination
+;; Map the register class for sp<->dp float conversions, source
(define_mode_attr VSr5 [(SF "ws")
(DF "f")
(V2DF "v")
(V4SF "wd")])
+;; The VSX register class that a type can occupy, even if it is not the
+;; preferred register class (VSr is the preferred register class that will get
+;; allocated first).
+(define_mode_attr VSa [(V16QI "wa")
+ (V8HI "wa")
+ (V4SI "wa")
+ (V4SF "wa")
+ (V2DI "wa")
+ (V2DF "wa")
+ (DI "wi")
+ (DF "ws")
+ (SF "ww")
+ (V1TI "wa")
+ (TI "wt")])
+
;; Same size integer type for floating point data
(define_mode_attr VSi [(V4SF "v4si")
(V2DF "v2di")
@@ -207,6 +229,16 @@
(V2DF "V4DF")
(V1TI "V2TI")])
+;; Map register class for 64-bit element in 128-bit vector for direct moves
+;; to/from gprs
+(define_mode_attr VS_64dm [(V2DF "wk")
+ (V2DI "wj")])
+
+;; Map register class for 64-bit element in 128-bit vector for normal register
+;; to register moves
+(define_mode_attr VS_64reg [(V2DF "ws")
+ (V2DI "wi")])
+
;; Constants for creating unspecs
(define_c_enum "unspec"
[UNSPEC_VSX_CONCAT
@@ -235,7 +267,7 @@
;; The patterns for LE permuted loads and stores come before the general
;; VSX moves so they match first.
(define_insn_and_split "*vsx_le_perm_load_<mode>"
- [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=wa")
+ [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>")
(match_operand:VSX_LE 1 "memory_operand" "Z"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX"
"#"
@@ -258,7 +290,7 @@
(set_attr "length" "8")])
(define_insn_and_split "*vsx_le_perm_load_<mode>"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>")
(match_operand:VSX_W 1 "memory_operand" "Z"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX"
"#"
@@ -350,7 +382,7 @@
(define_insn "*vsx_le_perm_store_<mode>"
[(set (match_operand:VSX_LE 0 "memory_operand" "=Z")
- (match_operand:VSX_LE 1 "vsx_register_operand" "+wa"))]
+ (match_operand:VSX_LE 1 "vsx_register_operand" "+<VSa>"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX"
"#"
[(set_attr "type" "vecstore")
@@ -395,7 +427,7 @@
(define_insn "*vsx_le_perm_store_<mode>"
[(set (match_operand:VSX_W 0 "memory_operand" "=Z")
- (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))]
+ (match_operand:VSX_W 1 "vsx_register_operand" "+<VSa>"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX"
"#"
[(set_attr "type" "vecstore")
@@ -585,8 +617,8 @@
(define_insn "*vsx_mov<mode>"
- [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?wa,?wa,wQ,?&r,??Y,??r,??r,<VSr>,?wa,*r,v,wZ, v")
- (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,wa,Z,wa,r,wQ,r,Y,r,j,j,j,W,v,wZ"))]
+ [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?<VSa>,?<VSa>,wQ,?&r,??Y,??r,??r,<VSr>,?<VSa>,*r,v,wZ, v")
+ (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,<VSa>,Z,<VSa>,r,wQ,r,Y,r,j,j,j,W,v,wZ"))]
"VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode))"
@@ -688,36 +720,36 @@
;; instructions are now combined with the insn for the traditional floating
;; point unit.
(define_insn "*vsx_add<mode>3"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvadd<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_sub<mode>3"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvsub<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_mul<mode>3"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvmul<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_mul>")])
(define_insn "*vsx_div<mode>3"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvdiv<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_div>")
@@ -753,8 +785,8 @@
(define_insn "*vsx_tdiv<mode>3_internal"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=x,x")
- (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")]
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")
+ (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_VSX_TDIV))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>tdiv<VSs> %0,%x1,%x2"
@@ -762,8 +794,8 @@
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_fre<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_FRES))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvre<VSs> %x0,%x1"
@@ -771,60 +803,60 @@
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_neg<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvneg<VSs> %x0,%x1"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_abs<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvabs<VSs> %x0,%x1"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_nabs<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(neg:VSX_F
(abs:VSX_F
- (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa"))))]
+ (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>"))))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvnabs<VSs> %x0,%x1"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_smax<mode>3"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvmax<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_smin<mode>3"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvmin<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_sqrt<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvsqrt<VSs> %x0,%x1"
[(set_attr "type" "<VStype_sqrt>")
(set_attr "fp_type" "<VSfptype_sqrt>")])
(define_insn "*vsx_rsqrte<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_RSQRT))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvrsqrte<VSs> %x0,%x1"
@@ -859,7 +891,7 @@
(define_insn "*vsx_tsqrt<mode>2_internal"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=x,x")
- (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_VSX_TSQRT))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>tsqrt<VSs> %0,%x1"
@@ -901,12 +933,12 @@
[(set_attr "type" "vecdouble")])
(define_insn "*vsx_fms<mode>4"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?wa,?wa")
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?<VSa>,?<VSa>")
(fma:VSX_F
- (match_operand:VSX_F 1 "vsx_register_operand" "%<VSr>,<VSr>,wa,wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,wa,0")
+ (match_operand:VSX_F 1 "vsx_register_operand" "%<VSr>,<VSr>,<VSa>,<VSa>")
+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,<VSa>,0")
(neg:VSX_F
- (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,wa"))))]
+ (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,<VSa>"))))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"@
xvmsuba<VSs> %x0,%x1,%x2
@@ -916,12 +948,12 @@
[(set_attr "type" "<VStype_mul>")])
(define_insn "*vsx_nfma<mode>4"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?wa,?wa")
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?<VSa>,?<VSa>")
(neg:VSX_F
(fma:VSX_F
- (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSr>,wa,wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,wa,0")
- (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,wa"))))]
+ (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSr>,<VSa>,<VSa>")
+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,<VSa>,0")
+ (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,<VSa>"))))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"@
xvnmadda<VSs> %x0,%x1,%x2
@@ -966,27 +998,27 @@
;; Vector conditional expressions (no scalar version for these instructions)
(define_insn "vsx_eq<mode>"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (eq:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (eq:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcmpeq<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_gt<mode>"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (gt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (gt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcmpgt<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_ge<mode>"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (ge:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (ge:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcmpge<VSs> %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
@@ -997,10 +1029,10 @@
(define_insn "*vsx_eq_<mode>_p"
[(set (reg:CC 74)
(unspec:CC
- [(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?wa"))]
+ [(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
UNSPEC_PREDICATE))
- (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
+ (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(eq:VSX_F (match_dup 1)
(match_dup 2)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@@ -1010,10 +1042,10 @@
(define_insn "*vsx_gt_<mode>_p"
[(set (reg:CC 74)
(unspec:CC
- [(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?wa"))]
+ [(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
UNSPEC_PREDICATE))
- (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
+ (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(gt:VSX_F (match_dup 1)
(match_dup 2)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@@ -1023,10 +1055,10 @@
(define_insn "*vsx_ge_<mode>_p"
[(set (reg:CC 74)
(unspec:CC
- [(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?wa"))]
+ [(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
UNSPEC_PREDICATE))
- (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
+ (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(ge:VSX_F (match_dup 1)
(match_dup 2)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@@ -1035,33 +1067,33 @@
;; Vector select
(define_insn "*vsx_xxsel<mode>"
- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
+ [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(if_then_else:VSX_L
- (ne:CC (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa")
+ (ne:CC (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_L 4 "zero_constant" ""))
- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))]
+ (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,<VSa>")
+ (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"xxsel %x0,%x3,%x2,%x1"
[(set_attr "type" "vecperm")])
(define_insn "*vsx_xxsel<mode>_uns"
- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
+ [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(if_then_else:VSX_L
- (ne:CCUNS (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa")
+ (ne:CCUNS (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,<VSa>")
(match_operand:VSX_L 4 "zero_constant" ""))
- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))]
+ (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,<VSa>")
+ (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"xxsel %x0,%x3,%x2,%x1"
[(set_attr "type" "vecperm")])
;; Copy sign
(define_insn "vsx_copysign<mode>3"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(unspec:VSX_F
- [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")]
+ [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")
+ (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_COPYSIGN))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcpsgn<VSs> %x0,%x2,%x1"
@@ -1074,7 +1106,7 @@
;; in rs6000.md so don't test VECTOR_UNIT_VSX_P, just test against VSX.
;; Don't use vsx_register_operand here, use gpc_reg_operand to match rs6000.md.
(define_insn "vsx_float<VSi><mode>2"
- [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa")
+ [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?<VSa>")
(float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>cvsx<VSc><VSs> %x0,%x1"
@@ -1082,7 +1114,7 @@
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_floatuns<VSi><mode>2"
- [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa")
+ [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?<VSa>")
(unsigned_float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>cvux<VSc><VSs> %x0,%x1"
@@ -1091,7 +1123,7 @@
(define_insn "vsx_fix_trunc<mode><VSi>2"
[(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>")
- (fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))]
+ (fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>cv<VSs>sx<VSc>s %x0,%x1"
[(set_attr "type" "<VStype_simple>")
@@ -1099,7 +1131,7 @@
(define_insn "vsx_fixuns_trunc<mode><VSi>2"
[(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>")
- (unsigned_fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))]
+ (unsigned_fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>cv<VSs>ux<VSc>s %x0,%x1"
[(set_attr "type" "<VStype_simple>")
@@ -1107,8 +1139,8 @@
;; Math rounding functions
(define_insn "vsx_x<VSv>r<VSs>i"
- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]
+ [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_VSX_ROUND_I))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>r<VSs>i %x0,%x1"
@@ -1116,8 +1148,8 @@
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_x<VSv>r<VSs>ic"
- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]
+ [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_VSX_ROUND_IC))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>r<VSs>ic %x0,%x1"
@@ -1125,16 +1157,16 @@
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_btrunc<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvr<VSs>iz %x0,%x1"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "*vsx_b2trunc<mode>2"
- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]
+ [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_FRIZ))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>r<VSs>iz %x0,%x1"
@@ -1142,8 +1174,8 @@
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_floor<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_FRIM))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvr<VSs>im %x0,%x1"
@@ -1151,8 +1183,8 @@
(set_attr "fp_type" "<VSfptype_simple>")])
(define_insn "vsx_ceil<mode>2"
- [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa")
- (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")]
+ [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
+ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")]
UNSPEC_FRIP))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvr<VSs>ip %x0,%x1"
@@ -1167,8 +1199,8 @@
;; scalar single precision instructions internally use the double format.
;; Prefer the altivec registers, since we likely will need to do a vperm
(define_insn "vsx_<VS_spdp_insn>"
- [(set (match_operand:<VS_spdp_res> 0 "vsx_register_operand" "=<VSr4>,?wa")
- (unspec:<VS_spdp_res> [(match_operand:VSX_SPDP 1 "vsx_register_operand" "<VSr5>,wa")]
+ [(set (match_operand:<VS_spdp_res> 0 "vsx_register_operand" "=<VSr4>,?<VSa>")
+ (unspec:<VS_spdp_res> [(match_operand:VSX_SPDP 1 "vsx_register_operand" "<VSr5>,<VSa>")]
UNSPEC_VSX_CVSPDP))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"<VS_spdp_insn> %x0,%x1"
@@ -1176,8 +1208,8 @@
;; xscvspdp, represent the scalar SF type as V4SF
(define_insn "vsx_xscvspdp"
- [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?wa")
- (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
+ [(set (match_operand:DF 0 "vsx_register_operand" "=ws")
+ (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSPDP))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"xscvspdp %x0,%x1"
@@ -1204,7 +1236,7 @@
;; ISA 2.07 xscvdpspn/xscvspdpn that does not raise an error on signalling NaNs
(define_insn "vsx_xscvdpspn"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,?wa")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=ww,?ww")
(unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "wd,wa")]
UNSPEC_VSX_CVDPSPN))]
"TARGET_XSCVDPSPN"
@@ -1212,16 +1244,16 @@
[(set_attr "type" "fp")])
(define_insn "vsx_xscvspdpn"
- [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?wa")
- (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
+ [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?ws")
+ (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wf,wa")]
UNSPEC_VSX_CVSPDPN))]
"TARGET_XSCVSPDPN"
"xscvspdpn %x0,%x1"
[(set_attr "type" "fp")])
(define_insn "vsx_xscvdpspn_scalar"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
- (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "f")]
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,?wa")
+ (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "ww,ww")]
UNSPEC_VSX_CVDPSPN))]
"TARGET_XSCVDPSPN"
"xscvdpspn %x0,%x1"
@@ -1309,10 +1341,10 @@
;; since the xsrdpiz instruction does not truncate the value if the floating
;; point value is < LONG_MIN or > LONG_MAX.
(define_insn "*vsx_float_fix_<mode>2"
- [(set (match_operand:VSX_DF 0 "vsx_register_operand" "=<VSr>,?wa")
+ [(set (match_operand:VSX_DF 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(float:VSX_DF
(fix:<VSI>
- (match_operand:VSX_DF 1 "vsx_register_operand" "<VSr>,?wa"))))]
+ (match_operand:VSX_DF 1 "vsx_register_operand" "<VSr>,?<VSa>"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& VECTOR_UNIT_VSX_P (<MODE>mode) && flag_unsafe_math_optimizations
&& !flag_trapping_math && TARGET_FRIZ"
@@ -1325,10 +1357,10 @@
;; Build a V2DF/V2DI vector from two scalars
(define_insn "vsx_concat_<mode>"
- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSr>,?wa")
+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(vec_concat:VSX_D
- (match_operand:<VS_scalar> 1 "vsx_register_operand" "ws,wa")
- (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,wa")))]
+ (match_operand:<VS_scalar> 1 "vsx_register_operand" "ws,<VSa>")
+ (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,<VSa>")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
if (BYTES_BIG_ENDIAN)
@@ -1359,18 +1391,18 @@
;; xxpermdi for little endian loads and stores. We need several of
;; these since the form of the PARALLEL differs by mode.
(define_insn "*vsx_xxpermdi2_le_<mode>"
- [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=wa")
+ [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>")
(vec_select:VSX_LE
- (match_operand:VSX_LE 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_LE 1 "vsx_register_operand" "<VSa>")
(parallel [(const_int 1) (const_int 0)])))]
"!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
"xxpermdi %x0,%x1,%x1,2"
[(set_attr "type" "vecperm")])
(define_insn "*vsx_xxpermdi4_le_<mode>"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>")
(vec_select:VSX_W
- (match_operand:VSX_W 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_W 1 "vsx_register_operand" "<VSa>")
(parallel [(const_int 2) (const_int 3)
(const_int 0) (const_int 1)])))]
"!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -1408,7 +1440,7 @@
;; lxvd2x for little endian loads. We need several of
;; these since the form of the PARALLEL differs by mode.
(define_insn "*vsx_lxvd2x2_le_<mode>"
- [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=wa")
+ [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>")
(vec_select:VSX_LE
(match_operand:VSX_LE 1 "memory_operand" "Z")
(parallel [(const_int 1) (const_int 0)])))]
@@ -1417,7 +1449,7 @@
[(set_attr "type" "vecload")])
(define_insn "*vsx_lxvd2x4_le_<mode>"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>")
(vec_select:VSX_W
(match_operand:VSX_W 1 "memory_operand" "Z")
(parallel [(const_int 2) (const_int 3)
@@ -1459,7 +1491,7 @@
(define_insn "*vsx_stxvd2x2_le_<mode>"
[(set (match_operand:VSX_LE 0 "memory_operand" "=Z")
(vec_select:VSX_LE
- (match_operand:VSX_LE 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_LE 1 "vsx_register_operand" "<VSa>")
(parallel [(const_int 1) (const_int 0)])))]
"!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
"stxvd2x %x1,%y0"
@@ -1468,7 +1500,7 @@
(define_insn "*vsx_stxvd2x4_le_<mode>"
[(set (match_operand:VSX_W 0 "memory_operand" "=Z")
(vec_select:VSX_W
- (match_operand:VSX_W 1 "vsx_register_operand" "wa")
+ (match_operand:VSX_W 1 "vsx_register_operand" "<VSa>")
(parallel [(const_int 2) (const_int 3)
(const_int 0) (const_int 1)])))]
"!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -1520,11 +1552,12 @@
;; Set the element of a V2DI/VD2F mode
(define_insn "vsx_set_<mode>"
- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?wa")
- (unspec:VSX_D [(match_operand:VSX_D 1 "vsx_register_operand" "wd,wa")
- (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,wa")
- (match_operand:QI 3 "u5bit_cint_operand" "i,i")]
- UNSPEC_VSX_SET))]
+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?<VSa>")
+ (unspec:VSX_D
+ [(match_operand:VSX_D 1 "vsx_register_operand" "wd,<VSa>")
+ (match_operand:<VS_scalar> 2 "vsx_register_operand" "<VS_64reg>,<VSa>")
+ (match_operand:QI 3 "u5bit_cint_operand" "i,i")]
+ UNSPEC_VSX_SET))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
int idx_first = BYTES_BIG_ENDIAN ? 0 : 1;
@@ -1549,11 +1582,11 @@
;; Optimize cases were we can do a simple or direct move.
;; Or see if we can avoid doing the move at all
(define_insn "*vsx_extract_<mode>_internal1"
- [(set (match_operand:<VS_scalar> 0 "register_operand" "=d,ws,?wa,r")
+ [(set (match_operand:<VS_scalar> 0 "register_operand" "=d,<VS_64reg>,r")
(vec_select:<VS_scalar>
- (match_operand:VSX_D 1 "register_operand" "d,wd,wa,wm")
+ (match_operand:VSX_D 1 "register_operand" "d,<VS_64reg>,<VS_64dm>")
(parallel
- [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD,wD")])))]
+ [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
{
int op0_regno = REGNO (operands[0]);
@@ -1570,14 +1603,14 @@
return "xxlor %x0,%x1,%x1";
}
- [(set_attr "type" "fp,vecsimple,vecsimple,mftgpr")
+ [(set_attr "type" "fp,vecsimple,mftgpr")
(set_attr "length" "4")])
(define_insn "*vsx_extract_<mode>_internal2"
- [(set (match_operand:<VS_scalar> 0 "vsx_register_operand" "=d,ws,ws,?wa")
+ [(set (match_operand:<VS_scalar> 0 "vsx_register_operand" "=d,<VS_64reg>,<VS_64reg>")
(vec_select:<VS_scalar>
- (match_operand:VSX_D 1 "vsx_register_operand" "d,wd,wd,wa")
- (parallel [(match_operand:QI 2 "u5bit_cint_operand" "wD,wD,i,i")])))]
+ (match_operand:VSX_D 1 "vsx_register_operand" "d,wd,wd")
+ (parallel [(match_operand:QI 2 "u5bit_cint_operand" "wD,wD,i")])))]
"VECTOR_MEM_VSX_P (<MODE>mode)
&& (!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE
|| INTVAL (operands[2]) != VECTOR_ELEMENT_SCALAR_64BIT)"
@@ -1605,7 +1638,7 @@
operands[3] = GEN_INT (fldDM);
return "xxpermdi %x0,%x1,%x1,%3";
}
- [(set_attr "type" "fp,vecsimple,vecperm,vecperm")
+ [(set_attr "type" "fp,vecsimple,vecperm")
(set_attr "length" "4")])
;; Optimize extracting a single scalar element from memory if the scalar is in
@@ -1643,7 +1676,7 @@
(define_insn "*vsx_extract_<mode>_store"
[(set (match_operand:<VS_scalar> 0 "memory_operand" "=m,Z,?Z")
(vec_select:<VS_scalar>
- (match_operand:VSX_D 1 "register_operand" "d,wd,wa")
+ (match_operand:VSX_D 1 "register_operand" "d,wd,<VSa>")
(parallel [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"@
@@ -1666,7 +1699,7 @@
(define_insn_and_split "vsx_extract_v4sf"
[(set (match_operand:SF 0 "vsx_register_operand" "=f,f")
(vec_select:SF
- (match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
+ (match_operand:V4SF 1 "vsx_register_operand" "<VSa>,<VSa>")
(parallel [(match_operand:QI 2 "u5bit_cint_operand" "O,i")])))
(clobber (match_scratch:V4SF 3 "=X,0"))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
@@ -1849,9 +1882,9 @@
;; V2DF/V2DI splat
(define_insn "vsx_splat_<mode>"
- [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?wa,?wa,?wa")
+ [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?<VSa>,?<VSa>,?<VSa>")
(vec_duplicate:VSX_D
- (match_operand:<VS_scalar> 1 "splat_input_operand" "ws,f,Z,wa,wa,Z")))]
+ (match_operand:<VS_scalar> 1 "splat_input_operand" "<VS_64reg>,f,Z,<VSa>,<VSa>,Z")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"@
xxpermdi %x0,%x1,%x1,0
@@ -1864,10 +1897,10 @@
;; V4SF/V4SI splat
(define_insn "vsx_xxspltw_<mode>"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>")
(vec_duplicate:VSX_W
(vec_select:<VS_scalar>
- (match_operand:VSX_W 1 "vsx_register_operand" "wf,wa")
+ (match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>")
(parallel
[(match_operand:QI 2 "u5bit_cint_operand" "i,i")]))))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -1880,8 +1913,8 @@
[(set_attr "type" "vecperm")])
(define_insn "vsx_xxspltw_<mode>_direct"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa")
- (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wf,wa")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>")
+ (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>")
(match_operand:QI 2 "u5bit_cint_operand" "i,i")]
UNSPEC_VSX_XXSPLTW))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -1890,11 +1923,11 @@
;; V4SF/V4SI interleave
(define_insn "vsx_xxmrghw_<mode>"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>")
(vec_select:VSX_W
(vec_concat:<VS_double>
- (match_operand:VSX_W 1 "vsx_register_operand" "wf,wa")
- (match_operand:VSX_W 2 "vsx_register_operand" "wf,wa"))
+ (match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>")
+ (match_operand:VSX_W 2 "vsx_register_operand" "wf,<VSa>"))
(parallel [(const_int 0) (const_int 4)
(const_int 1) (const_int 5)])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -1907,11 +1940,11 @@
[(set_attr "type" "vecperm")])
(define_insn "vsx_xxmrglw_<mode>"
- [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa")
+ [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>")
(vec_select:VSX_W
(vec_concat:<VS_double>
- (match_operand:VSX_W 1 "vsx_register_operand" "wf,wa")
- (match_operand:VSX_W 2 "vsx_register_operand" "wf,?wa"))
+ (match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>")
+ (match_operand:VSX_W 2 "vsx_register_operand" "wf,?<VSa>"))
(parallel [(const_int 2) (const_int 6)
(const_int 3) (const_int 7)])))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
@@ -1925,9 +1958,9 @@
;; Shift left double by word immediate
(define_insn "vsx_xxsldwi_<mode>"
- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=wa")
- (unspec:VSX_L [(match_operand:VSX_L 1 "vsx_register_operand" "wa")
- (match_operand:VSX_L 2 "vsx_register_operand" "wa")
+ [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSa>")
+ (unspec:VSX_L [(match_operand:VSX_L 1 "vsx_register_operand" "<VSa>")
+ (match_operand:VSX_L 2 "vsx_register_operand" "<VSa>")
(match_operand:QI 3 "u5bit_cint_operand" "i")]
UNSPEC_VSX_SLDWI))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
diff --git a/gcc-4.9/gcc/config/sh/sh.c b/gcc-4.9/gcc/config/sh/sh.c
index 62dcf0c..3d4553a 100644
--- a/gcc-4.9/gcc/config/sh/sh.c
+++ b/gcc-4.9/gcc/config/sh/sh.c
@@ -861,6 +861,12 @@ sh_option_override (void)
targetm.asm_out.aligned_op.di = NULL;
targetm.asm_out.unaligned_op.di = NULL;
}
+
+ /* User/priviledged mode is supported only on SH3*, SH4* and SH5*.
+ Disable it for everything else. */
+ if (! (TARGET_SH3 || TARGET_SH5) && TARGET_USERMODE)
+ TARGET_USERMODE = false;
+
if (TARGET_SH1)
{
if (! strcmp (sh_div_str, "call-div1"))
diff --git a/gcc-4.9/gcc/config/sh/sh.opt b/gcc-4.9/gcc/config/sh/sh.opt
index 1834c6b..bb6d395 100644
--- a/gcc-4.9/gcc/config/sh/sh.opt
+++ b/gcc-4.9/gcc/config/sh/sh.opt
@@ -343,7 +343,7 @@ Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1)
Cost to assume for a multiply insn
musermode
-Target Report RejectNegative Var(TARGET_USERMODE)
+Target Var(TARGET_USERMODE)
Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode.
;; We might want to enable this by default for TARGET_HARD_SH4, because
diff --git a/gcc-4.9/gcc/coverage.c b/gcc-4.9/gcc/coverage.c
index 6b1d0d6..bfc5731 100644
--- a/gcc-4.9/gcc/coverage.c
+++ b/gcc-4.9/gcc/coverage.c
@@ -658,7 +658,7 @@ typedef struct {
static vec<mod_id_to_name_t> *mod_names;
-static void
+void
record_module_name (unsigned int mod_id, const char *name)
{
mod_id_to_name_t t;
diff --git a/gcc-4.9/gcc/cp/ChangeLog b/gcc-4.9/gcc/cp/ChangeLog
index b0a474d..0c7ab33 100644
--- a/gcc-4.9/gcc/cp/ChangeLog
+++ b/gcc-4.9/gcc/cp/ChangeLog
@@ -1,3 +1,77 @@
+2014-08-26 Jason Merrill <jason@redhat.com>
+
+ PR c++/58624
+ * pt.c (tsubst_copy_and_build) [VAR_DECL]: Use TLS wrapper.
+ * semantics.c (finish_id_expression): Don't call TLS wrapper in a
+ template.
+
+2014-08-25 Jason Merrill <jason@redhat.com>
+
+ PR c++/62129
+ * class.c (outermost_open_class): New.
+ * cp-tree.h: Declare it.
+ * decl.c (maybe_register_incomplete_var): Use it.
+ (complete_vars): Handle any constant variable.
+ * expr.c (cplus_expand_constant): Handle CONSTRUCTOR.
+
+2014-08-22 Igor Zamyatin <igor.zamyatin@intel.com>
+
+ PR other/62008
+ * cp-array-notation.c (build_array_notation_ref): Added correct
+ handling of case with incorrect array.
+
+2014-08-19 Jason Merrill <jason@redhat.com>
+
+ PR c++/61214
+ PR tree-optimization/62091
+ * decl2.c (decl_needed_p): Return true for virtual functions when
+ devirtualizing.
+
+ Backport:
+ PR c++/61566
+ * pt.c (instantiate_class_template_1): Ignore lambda on
+ CLASSTYPE_DECL_LIST.
+ (push_template_decl_real): A lambda is not primary.
+ * lambda.c (maybe_add_lambda_conv_op): Distinguish between being
+ currently in a function and the lambda living in a function.
+
+ Backport:
+ PR c++/60417
+ * init.c (build_vec_init): Set CONSTRUCTOR_IS_DIRECT_INIT on
+ init-list for trailing elements.
+ * typeck2.c (process_init_constructor_array): Likewise.
+
+2014-08-07 Jason Merrill <jason@redhat.com>
+
+ PR c++/61959
+ * semantics.c (cxx_eval_bare_aggregate): Handle POINTER_PLUS_EXPR.
+
+ PR c++/61994
+ * init.c (build_vec_init): Leave atype an ARRAY_TYPE
+ if we're just returning an INIT_EXPR.
+
+ PR c++/60872
+ * call.c (standard_conversion): Don't try to apply restrict to void.
+
+ PR c++/58714
+ * tree.c (stabilize_expr): A stabilized prvalue is an xvalue.
+
+2014-08-01 Igor Zamyatin <igor.zamyatin@intel.com>
+
+ * cp-array-notation.c (expand_an_in_modify_expr): Fix the misprint
+ in error output.
+
+2014-08-01 Igor Zamyatin <igor.zamyatin@intel.com>
+
+ PR other/61963
+ * parser.c (cp_parser_array_notation): Added check for array_type.
+
+2014-08-01 Igor Zamyatin <igor.zamyatin@intel.com>
+
+ PR middle-end/61455
+ * cp-array-notation.c (expand_array_notation_exprs): Handling of
+ DECL_EXPR improved. Changed handling for INIT_EXPR.
+
2014-07-16 Release Manager
* GCC 4.9.1 released.
diff --git a/gcc-4.9/gcc/cp/call.c b/gcc-4.9/gcc/cp/call.c
index 2c67c03..223188a 100644
--- a/gcc-4.9/gcc/cp/call.c
+++ b/gcc-4.9/gcc/cp/call.c
@@ -1208,9 +1208,10 @@ standard_conversion (tree to, tree from, tree expr, bool c_cast_p,
&& TREE_CODE (TREE_TYPE (from)) != FUNCTION_TYPE)
{
tree nfrom = TREE_TYPE (from);
+ /* Don't try to apply restrict to void. */
+ int quals = cp_type_quals (nfrom) & ~TYPE_QUAL_RESTRICT;
from = build_pointer_type
- (cp_build_qualified_type (void_type_node,
- cp_type_quals (nfrom)));
+ (cp_build_qualified_type (void_type_node, quals));
conv = build_conv (ck_ptr, from, conv);
}
else if (TYPE_PTRDATAMEM_P (from))
diff --git a/gcc-4.9/gcc/cp/class.c b/gcc-4.9/gcc/cp/class.c
index 265afc4..711a567 100644
--- a/gcc-4.9/gcc/cp/class.c
+++ b/gcc-4.9/gcc/cp/class.c
@@ -7251,6 +7251,29 @@ currently_open_derived_class (tree t)
return NULL_TREE;
}
+/* Return the outermost enclosing class type that is still open, or
+ NULL_TREE. */
+
+tree
+outermost_open_class (void)
+{
+ if (!current_class_type)
+ return NULL_TREE;
+ tree r = NULL_TREE;
+ if (TYPE_BEING_DEFINED (current_class_type))
+ r = current_class_type;
+ for (int i = current_class_depth - 1; i > 0; --i)
+ {
+ if (current_class_stack[i].hidden)
+ break;
+ tree t = current_class_stack[i].type;
+ if (!TYPE_BEING_DEFINED (t))
+ break;
+ r = t;
+ }
+ return r;
+}
+
/* Returns the innermost class type which is not a lambda closure type. */
tree
diff --git a/gcc-4.9/gcc/cp/cp-array-notation.c b/gcc-4.9/gcc/cp/cp-array-notation.c
index fed60c9..a50ff1d 100644
--- a/gcc-4.9/gcc/cp/cp-array-notation.c
+++ b/gcc-4.9/gcc/cp/cp-array-notation.c
@@ -607,7 +607,7 @@ expand_an_in_modify_expr (location_t location, tree lhs,
if (lhs_rank == 0 && rhs_rank != 0)
{
- error_at (location, "%qD cannot be scalar when %qD is not", lhs, rhs);
+ error_at (location, "%qE cannot be scalar when %qE is not", lhs, rhs);
return error_mark_node;
}
if (lhs_rank != 0 && rhs_rank != 0 && lhs_rank != rhs_rank)
@@ -1147,13 +1147,13 @@ expand_array_notation_exprs (tree t)
case PARM_DECL:
case NON_LVALUE_EXPR:
case NOP_EXPR:
- case INIT_EXPR:
case ADDR_EXPR:
case ARRAY_REF:
case BIT_FIELD_REF:
case VECTOR_CST:
case COMPLEX_CST:
return t;
+ case INIT_EXPR:
case MODIFY_EXPR:
if (contains_array_notation_expr (t))
t = expand_an_in_modify_expr (loc, TREE_OPERAND (t, 0), NOP_EXPR,
@@ -1175,13 +1175,24 @@ expand_array_notation_exprs (tree t)
return t;
}
case DECL_EXPR:
- {
- tree x = DECL_EXPR_DECL (t);
- if (t && TREE_CODE (x) != FUNCTION_DECL)
+ if (contains_array_notation_expr (t))
+ {
+ tree x = DECL_EXPR_DECL (t);
if (DECL_INITIAL (x))
- t = expand_unary_array_notation_exprs (t);
+ {
+ location_t loc = DECL_SOURCE_LOCATION (x);
+ tree lhs = x;
+ tree rhs = DECL_INITIAL (x);
+ DECL_INITIAL (x) = NULL;
+ tree new_modify_expr = build_modify_expr (loc, lhs,
+ TREE_TYPE (lhs),
+ NOP_EXPR,
+ loc, rhs,
+ TREE_TYPE(rhs));
+ t = expand_array_notation_exprs (new_modify_expr);
+ }
+ }
return t;
- }
case STATEMENT_LIST:
{
tree_stmt_iterator i;
@@ -1392,7 +1403,10 @@ build_array_notation_ref (location_t loc, tree array, tree start, tree length,
if (TREE_CODE (type) == ARRAY_TYPE || TREE_CODE (type) == POINTER_TYPE)
TREE_TYPE (array_ntn_expr) = TREE_TYPE (type);
else
- gcc_unreachable ();
+ {
+ error_at (loc, "base of array section must be pointer or array type");
+ return error_mark_node;
+ }
SET_EXPR_LOCATION (array_ntn_expr, loc);
return array_ntn_expr;
diff --git a/gcc-4.9/gcc/cp/cp-tree.h b/gcc-4.9/gcc/cp/cp-tree.h
index e6323e7..b062b97 100644
--- a/gcc-4.9/gcc/cp/cp-tree.h
+++ b/gcc-4.9/gcc/cp/cp-tree.h
@@ -5113,6 +5113,7 @@ extern void resort_type_method_vec (void *, void *,
extern bool add_method (tree, tree, tree);
extern bool currently_open_class (tree);
extern tree currently_open_derived_class (tree);
+extern tree outermost_open_class (void);
extern tree current_nonlambda_class_type (void);
extern tree finish_struct (tree, tree);
extern void finish_struct_1 (tree);
diff --git a/gcc-4.9/gcc/cp/decl.c b/gcc-4.9/gcc/cp/decl.c
index 4dd0ec0..df4813d 100644
--- a/gcc-4.9/gcc/cp/decl.c
+++ b/gcc-4.9/gcc/cp/decl.c
@@ -14211,8 +14211,8 @@ grokmethod (cp_decl_specifier_seq *declspecs,
/* VAR is a VAR_DECL. If its type is incomplete, remember VAR so that
we can lay it out later, when and if its type becomes complete.
- Also handle constexpr pointer to member variables where the initializer
- is an unlowered PTRMEM_CST because the class isn't complete yet. */
+ Also handle constexpr variables where the initializer involves
+ an unlowered PTRMEM_CST because the class isn't complete yet. */
void
maybe_register_incomplete_var (tree var)
@@ -14237,12 +14237,13 @@ maybe_register_incomplete_var (tree var)
incomplete_var iv = {var, inner_type};
vec_safe_push (incomplete_vars, iv);
}
- else if (TYPE_PTRMEM_P (inner_type)
- && DECL_INITIAL (var)
- && TREE_CODE (DECL_INITIAL (var)) == PTRMEM_CST)
+ else if (!(DECL_LANG_SPECIFIC (var) && DECL_TEMPLATE_INFO (var))
+ && decl_constant_var_p (var)
+ && (TYPE_PTRMEM_P (inner_type) || CLASS_TYPE_P (inner_type)))
{
- tree context = TYPE_PTRMEM_CLASS_TYPE (inner_type);
- gcc_assert (TYPE_BEING_DEFINED (context));
+ /* When the outermost open class is complete we can resolve any
+ pointers-to-members. */
+ tree context = outermost_open_class ();
incomplete_var iv = {var, context};
vec_safe_push (incomplete_vars, iv);
}
@@ -14266,9 +14267,8 @@ complete_vars (tree type)
tree var = iv->decl;
tree type = TREE_TYPE (var);
- if (TYPE_PTRMEM_P (type))
- DECL_INITIAL (var) = cplus_expand_constant (DECL_INITIAL (var));
- else
+ if (TYPE_MAIN_VARIANT (strip_array_types (type))
+ == iv->incomplete_type)
{
/* Complete the type of the variable. The VAR_DECL itself
will be laid out in expand_expr. */
@@ -14276,6 +14276,10 @@ complete_vars (tree type)
cp_apply_type_quals_to_decl (cp_type_quals (type), var);
}
+ if (DECL_INITIAL (var)
+ && decl_constant_var_p (var))
+ DECL_INITIAL (var) = cplus_expand_constant (DECL_INITIAL (var));
+
/* Remove this entry from the list. */
incomplete_vars->unordered_remove (ix);
}
diff --git a/gcc-4.9/gcc/cp/decl2.c b/gcc-4.9/gcc/cp/decl2.c
index 3088918..4fc03e9 100644
--- a/gcc-4.9/gcc/cp/decl2.c
+++ b/gcc-4.9/gcc/cp/decl2.c
@@ -1931,6 +1931,11 @@ decl_needed_p (tree decl)
if (flag_keep_inline_dllexport
&& lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl)))
return true;
+ /* Virtual functions might be needed for devirtualization. */
+ if (flag_devirtualize
+ && TREE_CODE (decl) == FUNCTION_DECL
+ && DECL_VIRTUAL_P (decl))
+ return true;
/* Otherwise, DECL does not need to be emitted -- yet. A subsequent
reference to DECL might cause it to be emitted later. */
return false;
diff --git a/gcc-4.9/gcc/cp/expr.c b/gcc-4.9/gcc/cp/expr.c
index a62e0f9..99f8006 100644
--- a/gcc-4.9/gcc/cp/expr.c
+++ b/gcc-4.9/gcc/cp/expr.c
@@ -74,6 +74,14 @@ cplus_expand_constant (tree cst)
}
break;
+ case CONSTRUCTOR:
+ {
+ constructor_elt *elt;
+ unsigned HOST_WIDE_INT idx;
+ FOR_EACH_VEC_SAFE_ELT (CONSTRUCTOR_ELTS (cst), idx, elt)
+ elt->value = cplus_expand_constant (elt->value);
+ }
+
default:
/* There's nothing to do. */
break;
diff --git a/gcc-4.9/gcc/cp/init.c b/gcc-4.9/gcc/cp/init.c
index ecb103a..283843a 100644
--- a/gcc-4.9/gcc/cp/init.c
+++ b/gcc-4.9/gcc/cp/init.c
@@ -3565,19 +3565,11 @@ build_vec_init (tree base, tree maxindex, tree init,
try_block = begin_try_block ();
}
- /* If the initializer is {}, then all elements are initialized from {}.
- But for non-classes, that's the same as value-initialization. */
+ bool empty_list = false;
if (init && BRACE_ENCLOSED_INITIALIZER_P (init)
&& CONSTRUCTOR_NELTS (init) == 0)
- {
- if (CLASS_TYPE_P (type))
- /* Leave init alone. */;
- else
- {
- init = NULL_TREE;
- explicit_value_init_p = true;
- }
- }
+ /* Skip over the handling of non-empty init lists. */
+ empty_list = true;
/* Maybe pull out constant value when from_array? */
@@ -3697,14 +3689,8 @@ build_vec_init (tree base, tree maxindex, tree init,
vec_free (new_vec);
}
- /* Any elements without explicit initializers get {}. */
- if (cxx_dialect >= cxx11 && AGGREGATE_TYPE_P (type))
- init = build_constructor (init_list_type_node, NULL);
- else
- {
- init = NULL_TREE;
- explicit_value_init_p = true;
- }
+ /* Any elements without explicit initializers get T{}. */
+ empty_list = true;
}
else if (from_array)
{
@@ -3750,6 +3736,26 @@ build_vec_init (tree base, tree maxindex, tree init,
to = build1 (INDIRECT_REF, type, base);
+ /* If the initializer is {}, then all elements are initialized from T{}.
+ But for non-classes, that's the same as value-initialization. */
+ if (empty_list)
+ {
+ if (cxx_dialect >= cxx11 && AGGREGATE_TYPE_P (type))
+ {
+ if (BRACE_ENCLOSED_INITIALIZER_P (init)
+ && CONSTRUCTOR_NELTS (init) == 0)
+ /* Reuse it. */;
+ else
+ init = build_constructor (init_list_type_node, NULL);
+ CONSTRUCTOR_IS_DIRECT_INIT (init) = true;
+ }
+ else
+ {
+ init = NULL_TREE;
+ explicit_value_init_p = true;
+ }
+ }
+
if (from_array)
{
tree from;
@@ -3854,6 +3860,13 @@ build_vec_init (tree base, tree maxindex, tree init,
stmt_expr = finish_init_stmts (is_global, stmt_expr, compound_stmt);
+ current_stmt_tree ()->stmts_are_full_exprs_p = destroy_temps;
+
+ if (errors)
+ return error_mark_node;
+ if (const_init)
+ return build2 (INIT_EXPR, atype, obase, const_init);
+
/* Now make the result have the correct type. */
if (TREE_CODE (atype) == ARRAY_TYPE)
{
@@ -3863,12 +3876,6 @@ build_vec_init (tree base, tree maxindex, tree init,
TREE_NO_WARNING (stmt_expr) = 1;
}
- current_stmt_tree ()->stmts_are_full_exprs_p = destroy_temps;
-
- if (const_init)
- return build2 (INIT_EXPR, atype, obase, const_init);
- if (errors)
- return error_mark_node;
return stmt_expr;
}
diff --git a/gcc-4.9/gcc/cp/lambda.c b/gcc-4.9/gcc/cp/lambda.c
index 7bd0de1..6acbdd9 100644
--- a/gcc-4.9/gcc/cp/lambda.c
+++ b/gcc-4.9/gcc/cp/lambda.c
@@ -820,6 +820,7 @@ void
maybe_add_lambda_conv_op (tree type)
{
bool nested = (current_function_decl != NULL_TREE);
+ bool nested_def = decl_function_context (TYPE_MAIN_DECL (type));
tree callop = lambda_function (type);
if (LAMBDA_EXPR_CAPTURE_LIST (CLASSTYPE_LAMBDA_EXPR (type)) != NULL_TREE)
@@ -972,7 +973,7 @@ maybe_add_lambda_conv_op (tree type)
DECL_NOT_REALLY_EXTERN (fn) = 1;
DECL_DECLARED_INLINE_P (fn) = 1;
DECL_ARGUMENTS (fn) = build_this_parm (fntype, TYPE_QUAL_CONST);
- if (nested)
+ if (nested_def)
DECL_INTERFACE_KNOWN (fn) = 1;
if (generic_lambda_p)
@@ -1012,7 +1013,7 @@ maybe_add_lambda_conv_op (tree type)
DECL_NAME (arg) = NULL_TREE;
DECL_CONTEXT (arg) = fn;
}
- if (nested)
+ if (nested_def)
DECL_INTERFACE_KNOWN (fn) = 1;
if (generic_lambda_p)
diff --git a/gcc-4.9/gcc/cp/parser.c b/gcc-4.9/gcc/cp/parser.c
index 706f6c0..88478bf 100644
--- a/gcc-4.9/gcc/cp/parser.c
+++ b/gcc-4.9/gcc/cp/parser.c
@@ -6306,7 +6306,7 @@ cp_parser_array_notation (location_t loc, cp_parser *parser, tree *init_index,
parser->colon_corrects_to_scope_p = saved_colon_corrects;
if (*init_index == error_mark_node || length_index == error_mark_node
- || stride == error_mark_node)
+ || stride == error_mark_node || array_type == error_mark_node)
{
if (cp_lexer_peek_token (parser->lexer)->type == CPP_CLOSE_SQUARE)
cp_lexer_consume_token (parser->lexer);
diff --git a/gcc-4.9/gcc/cp/pt.c b/gcc-4.9/gcc/cp/pt.c
index 54676af..a049a1e 100644
--- a/gcc-4.9/gcc/cp/pt.c
+++ b/gcc-4.9/gcc/cp/pt.c
@@ -4706,6 +4706,9 @@ push_template_decl_real (tree decl, bool is_friend)
template <typename T> friend void A<T>::f();
is not primary. */
is_primary = false;
+ else if (TREE_CODE (decl) == TYPE_DECL
+ && LAMBDA_TYPE_P (TREE_TYPE (decl)))
+ is_primary = false;
else
is_primary = template_parm_scope_p ();
@@ -9144,6 +9147,11 @@ instantiate_class_template_1 (tree type)
&& DECL_OMP_DECLARE_REDUCTION_P (r))
cp_check_omp_declare_reduction (r);
}
+ else if (DECL_CLASS_TEMPLATE_P (t)
+ && LAMBDA_TYPE_P (TREE_TYPE (t)))
+ /* A closure type for a lambda in a default argument for a
+ member template. Ignore it; it will be instantiated with
+ the default argument. */;
else
{
/* Build new TYPE_FIELDS. */
@@ -15190,6 +15198,16 @@ tsubst_copy_and_build (tree t,
case PARM_DECL:
{
tree r = tsubst_copy (t, args, complain, in_decl);
+ if (TREE_CODE (r) == VAR_DECL
+ && !processing_template_decl
+ && !cp_unevaluated_operand
+ && DECL_THREAD_LOCAL_P (r))
+ {
+ if (tree wrap = get_tls_wrapper_fn (r))
+ /* Replace an evaluated use of the thread_local variable with
+ a call to its wrapper. */
+ r = build_cxx_call (wrap, 0, NULL, tf_warning_or_error);
+ }
if (TREE_CODE (TREE_TYPE (t)) != REFERENCE_TYPE)
/* If the original type was a reference, we'll be wrapped in
diff --git a/gcc-4.9/gcc/cp/semantics.c b/gcc-4.9/gcc/cp/semantics.c
index de5e536..db4f9fd 100644
--- a/gcc-4.9/gcc/cp/semantics.c
+++ b/gcc-4.9/gcc/cp/semantics.c
@@ -3496,6 +3496,7 @@ finish_id_expression (tree id_expression,
tree wrap;
if (VAR_P (decl)
&& !cp_unevaluated_operand
+ && !processing_template_decl
&& DECL_THREAD_LOCAL_P (decl)
&& (wrap = get_tls_wrapper_fn (decl)))
{
@@ -8982,7 +8983,9 @@ cxx_eval_bare_aggregate (const constexpr_call *call, tree t,
constructor_elt *inner = base_field_constructor_elt (n, ce->index);
inner->value = elt;
}
- else if (ce->index && TREE_CODE (ce->index) == NOP_EXPR)
+ else if (ce->index
+ && (TREE_CODE (ce->index) == NOP_EXPR
+ || TREE_CODE (ce->index) == POINTER_PLUS_EXPR))
{
/* This is an initializer for an empty base; now that we've
checked that it's constant, we can ignore it. */
diff --git a/gcc-4.9/gcc/cp/tree.c b/gcc-4.9/gcc/cp/tree.c
index 622ba99..2820ba0 100644
--- a/gcc-4.9/gcc/cp/tree.c
+++ b/gcc-4.9/gcc/cp/tree.c
@@ -3795,6 +3795,10 @@ stabilize_expr (tree exp, tree* initp)
{
init_expr = get_target_expr (exp);
exp = TARGET_EXPR_SLOT (init_expr);
+ if (CLASS_TYPE_P (TREE_TYPE (exp)))
+ exp = move (exp);
+ else
+ exp = rvalue (exp);
}
else
{
diff --git a/gcc-4.9/gcc/cp/typeck2.c b/gcc-4.9/gcc/cp/typeck2.c
index 0bdad2a..f8af096 100644
--- a/gcc-4.9/gcc/cp/typeck2.c
+++ b/gcc-4.9/gcc/cp/typeck2.c
@@ -1237,8 +1237,9 @@ process_init_constructor_array (tree type, tree init,
{
/* If this type needs constructors run for default-initialization,
we can't rely on the back end to do it for us, so make the
- initialization explicit by list-initializing from {}. */
+ initialization explicit by list-initializing from T{}. */
next = build_constructor (init_list_type_node, NULL);
+ CONSTRUCTOR_IS_DIRECT_INIT (next) = true;
next = massage_init_elt (TREE_TYPE (type), next, complain);
if (initializer_zerop (next))
/* The default zero-initialization is fine for us; don't
diff --git a/gcc-4.9/gcc/cprop.c b/gcc-4.9/gcc/cprop.c
index c3acb05..6a3429e 100644
--- a/gcc-4.9/gcc/cprop.c
+++ b/gcc-4.9/gcc/cprop.c
@@ -790,8 +790,11 @@ try_replace_reg (rtx from, rtx to, rtx insn)
/* REG_EQUAL may get simplified into register.
We don't allow that. Remove that note. This code ought
not to happen, because previous code ought to synthesize
- reg-reg move, but be on the safe side. */
- if (note && REG_NOTE_KIND (note) == REG_EQUAL && REG_P (XEXP (note, 0)))
+ reg-reg move, but be on the safe side. The REG_EQUAL note is
+ also removed when the source is a constant. */
+ if (note && REG_NOTE_KIND (note) == REG_EQUAL
+ && (REG_P (XEXP (note, 0))
+ || (set && CONSTANT_P (SET_SRC (set)))))
remove_note (insn, note);
return success;
diff --git a/gcc-4.9/gcc/doc/invoke.texi b/gcc-4.9/gcc/doc/invoke.texi
index d4ced84..2fb008d 100644
--- a/gcc-4.9/gcc/doc/invoke.texi
+++ b/gcc-4.9/gcc/doc/invoke.texi
@@ -13808,7 +13808,7 @@ are compatible with as many systems and code bases as possible.
@item -mkernel
@opindex mkernel
Enable kernel development mode. The @option{-mkernel} option sets
-@option{-static}, @option{-fno-common}, @option{-fno-cxa-atexit},
+@option{-static}, @option{-fno-common}, @option{-fno-use-cxa-atexit},
@option{-fno-exceptions}, @option{-fno-non-call-exceptions},
@option{-fapple-kext}, @option{-fno-weak} and @option{-fno-rtti} where
applicable. This mode also sets @option{-mno-altivec},
@@ -20741,6 +20741,72 @@ single-precision mode by default.
@opindex m4
Generate code for the SH4.
+@item -m4-100
+@opindex m4-100
+Generate code for SH4-100.
+
+@item -m4-100-nofpu
+@opindex m4-100-nofpu
+Generate code for SH4-100 in such a way that the
+floating-point unit is not used.
+
+@item -m4-100-single
+@opindex m4-100-single
+Generate code for SH4-100 assuming the floating-point unit is in
+single-precision mode by default.
+
+@item -m4-100-single-only
+@opindex m4-100-single-only
+Generate code for SH4-100 in such a way that no double-precision
+floating-point operations are used.
+
+@item -m4-200
+@opindex m4-200
+Generate code for SH4-200.
+
+@item -m4-200-nofpu
+@opindex m4-200-nofpu
+Generate code for SH4-200 without in such a way that the
+floating-point unit is not used.
+
+@item -m4-200-single
+@opindex m4-200-single
+Generate code for SH4-200 assuming the floating-point unit is in
+single-precision mode by default.
+
+@item -m4-200-single-only
+@opindex m4-200-single-only
+Generate code for SH4-200 in such a way that no double-precision
+floating-point operations are used.
+
+@item -m4-300
+@opindex m4-300
+Generate code for SH4-300.
+
+@item -m4-300-nofpu
+@opindex m4-300-nofpu
+Generate code for SH4-300 without in such a way that the
+floating-point unit is not used.
+
+@item -m4-300-single
+@opindex m4-300-single
+Generate code for SH4-300 in such a way that no double-precision
+floating-point operations are used.
+
+@item -m4-300-single-only
+@opindex m4-300-single-only
+Generate code for SH4-300 in such a way that no double-precision
+floating-point operations are used.
+
+@item -m4-340
+@opindex m4-340
+Generate code for SH4-340 (no MMU, no FPU).
+
+@item -m4-500
+@opindex m4-500
+Generate code for SH4-500 (no FPU). Passes @option{-isa=sh4-nofpu} to the
+assembler.
+
@item -m4a-nofpu
@opindex m4a-nofpu
Generate code for the SH4al-dsp, or for a SH4a in such a way that the
@@ -20766,6 +20832,33 @@ Same as @option{-m4a-nofpu}, except that it implicitly passes
@option{-dsp} to the assembler. GCC doesn't generate any DSP
instructions at the moment.
+@item -m5-32media
+@opindex m5-32media
+Generate 32-bit code for SHmedia.
+
+@item -m5-32media-nofpu
+@opindex m5-32media-nofpu
+Generate 32-bit code for SHmedia in such a way that the
+floating-point unit is not used.
+
+@item -m5-64media
+@opindex m5-64media
+Generate 64-bit code for SHmedia.
+
+@item -m5-64media-nofpu
+@opindex m5-64media-nofpu
+Generate 64-bit code for SHmedia in such a way that the
+floating-point unit is not used.
+
+@item -m5-compact
+@opindex m5-compact
+Generate code for SHcompact.
+
+@item -m5-compact-nofpu
+@opindex m5-compact-nofpu
+Generate code for SHcompact in such a way that the
+floating-point unit is not used.
+
@item -mb
@opindex mb
Compile code for the processor in big-endian mode.
@@ -20799,16 +20892,12 @@ Enable the use of bit manipulation instructions on SH2A.
Enable the use of the instruction @code{fmovd}. Check @option{-mdalign} for
alignment constraints.
-@item -mhitachi
-@opindex mhitachi
-Comply with the calling conventions defined by Renesas.
-
@item -mrenesas
-@opindex mhitachi
+@opindex mrenesas
Comply with the calling conventions defined by Renesas.
@item -mno-renesas
-@opindex mhitachi
+@opindex mno-renesas
Comply with the calling conventions defined for GCC before the Renesas
conventions were available. This option is the default for all
targets of the SH toolchain.
@@ -20816,12 +20905,12 @@ targets of the SH toolchain.
@item -mnomacsave
@opindex mnomacsave
Mark the @code{MAC} register as call-clobbered, even if
-@option{-mhitachi} is given.
+@option{-mrenesas} is given.
@item -mieee
@itemx -mno-ieee
@opindex mieee
-@opindex mnoieee
+@opindex mno-ieee
Control the IEEE compliance of floating-point comparisons, which affects the
handling of cases where the result of a comparison is unordered. By default
@option{-mieee} is implicitly enabled. If @option{-ffinite-math-only} is
@@ -20861,14 +20950,14 @@ separated list. For details on the atomic built-in functions see
@item none
Disable compiler generated atomic sequences and emit library calls for atomic
-operations. This is the default if the target is not @code{sh-*-linux*}.
+operations. This is the default if the target is not @code{sh*-*-linux*}.
@item soft-gusa
Generate GNU/Linux compatible gUSA software atomic sequences for the atomic
built-in functions. The generated atomic sequences require additional support
from the interrupt/exception handling code of the system and are only suitable
for SH3* and SH4* single-core systems. This option is enabled by default when
-the target is @code{sh-*-linux*} and SH3* or SH4*. When the target is SH4A,
+the target is @code{sh*-*-linux*} and SH3* or SH4*. When the target is SH4A,
this option will also partially utilize the hardware atomic instructions
@code{movli.l} and @code{movco.l} to create more efficient code, unless
@samp{strict} is specified.
@@ -20887,7 +20976,7 @@ setting @code{SR.IMASK = 1111}. This model works only when the program runs
in privileged mode and is only suitable for single-core systems. Additional
support from the interrupt/exception handling code of the system is not
required. This model is enabled by default when the target is
-@code{sh-*-linux*} and SH1* or SH2*.
+@code{sh*-*-linux*} and SH1* or SH2*.
@item hard-llcs
Generate hardware atomic sequences using the @code{movli.l} and @code{movco.l}
@@ -20922,21 +21011,20 @@ that are implied by the @code{tas.b} instruction. On multi-core SH4A
processors the @code{tas.b} instruction must be used with caution since it
can result in data corruption for certain cache configurations.
-@item -mspace
-@opindex mspace
-Optimize for space instead of speed. Implied by @option{-Os}.
-
@item -mprefergot
@opindex mprefergot
When generating position-independent code, emit function calls using
the Global Offset Table instead of the Procedure Linkage Table.
@item -musermode
+@itemx -mno-usermode
@opindex musermode
-Don't generate privileged mode only code. This option
-implies @option{-mno-inline-ic_invalidate}
-if the inlined code would not work in user mode.
-This is the default when the target is @code{sh-*-linux*}.
+@opindex mno-usermode
+Don't allow (allow) the compiler generating privileged mode code. Specifying
+@option{-musermode} also implies @option{-mno-inline-ic_invalidate} if the
+inlined code would not work in user mode. @option{-musermode} is the default
+when the target is @code{sh*-*-linux*}. If the target is SH1* or SH2*
+@option{-musermode} has no effect, since there is no user mode.
@item -multcost=@var{number}
@opindex multcost=@var{number}
diff --git a/gcc-4.9/gcc/doc/md.texi b/gcc-4.9/gcc/doc/md.texi
index 8e30aca..60ca799 100644
--- a/gcc-4.9/gcc/doc/md.texi
+++ b/gcc-4.9/gcc/doc/md.texi
@@ -2126,6 +2126,18 @@ VSX vector register to hold vector float data or NO_REGS.
@item wg
If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
+@item wh
+Floating point register if direct moves are available, or NO_REGS.
+
+@item wi
+FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
+
+@item wj
+FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
+
+@item wk
+FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.
+
@item wl
Floating point register if the LFIWAX instruction is enabled or NO_REGS.
@@ -2157,7 +2169,7 @@ FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
Floating point register if the STFIWX instruction is enabled or NO_REGS.
@item wy
-VSX vector register to hold scalar float values or NO_REGS.
+FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
@item wz
Floating point register if the LFIWZX instruction is enabled or NO_REGS.
diff --git a/gcc-4.9/gcc/dwarf2out.c b/gcc-4.9/gcc/dwarf2out.c
index 088e522..ca4bd16 100644
--- a/gcc-4.9/gcc/dwarf2out.c
+++ b/gcc-4.9/gcc/dwarf2out.c
@@ -8966,26 +8966,6 @@ add_top_level_skeleton_die_attrs (dw_die_ref die)
add_AT_lineptr (die, DW_AT_GNU_addr_base, debug_addr_section_label);
}
-/* Return the single type-unit die for skeleton type units. */
-
-static dw_die_ref
-get_skeleton_type_unit (void)
-{
- /* For dwarf_split_debug_sections with use_type info, all type units in the
- skeleton sections have identical dies (but different headers). This
- single die will be output many times. */
-
- static dw_die_ref skeleton_type_unit = NULL;
-
- if (skeleton_type_unit == NULL)
- {
- skeleton_type_unit = new_die (DW_TAG_type_unit, NULL, NULL);
- add_top_level_skeleton_die_attrs (skeleton_type_unit);
- skeleton_type_unit->die_abbrev = SKELETON_TYPE_DIE_ABBREV;
- }
- return skeleton_type_unit;
-}
-
/* Output skeleton debug sections that point to the dwo file. */
static void
@@ -9024,8 +9004,6 @@ output_skeleton_debug_sections (dw_die_ref comp_unit)
ASM_OUTPUT_LABEL (asm_out_file, debug_skeleton_abbrev_section_label);
output_die_abbrevs (SKELETON_COMP_DIE_ABBREV, comp_unit);
- if (use_debug_types)
- output_die_abbrevs (SKELETON_TYPE_DIE_ABBREV, get_skeleton_type_unit ());
dw2_asm_output_data (1, 0, "end of skeleton .debug_abbrev");
}
@@ -9087,38 +9065,6 @@ output_comdat_type_unit (comdat_type_node *node)
output_die (node->root_die);
unmark_dies (node->root_die);
-
-#if defined (OBJECT_FORMAT_ELF)
- if (dwarf_split_debug_info)
- {
- /* Produce the skeleton type-unit header. */
- const char *secname = ".debug_types";
-
- targetm.asm_out.named_section (secname,
- SECTION_DEBUG | SECTION_LINKONCE,
- comdat_key);
- if (DWARF_INITIAL_LENGTH_SIZE - DWARF_OFFSET_SIZE == 4)
- dw2_asm_output_data (4, 0xffffffff,
- "Initial length escape value indicating 64-bit DWARF extension");
-
- dw2_asm_output_data (DWARF_OFFSET_SIZE,
- DWARF_COMPILE_UNIT_HEADER_SIZE
- - DWARF_INITIAL_LENGTH_SIZE
- + size_of_die (get_skeleton_type_unit ())
- + DWARF_TYPE_SIGNATURE_SIZE + DWARF_OFFSET_SIZE,
- "Length of Type Unit Info");
- dw2_asm_output_data (2, dwarf_version, "DWARF version number");
- dw2_asm_output_offset (DWARF_OFFSET_SIZE,
- debug_skeleton_abbrev_section_label,
- debug_abbrev_section,
- "Offset Into Abbrev. Section");
- dw2_asm_output_data (1, DWARF2_ADDR_SIZE, "Pointer Size (in bytes)");
- output_signature (node->signature, "Type Signature");
- dw2_asm_output_data (DWARF_OFFSET_SIZE, 0, "Offset to Type DIE");
-
- output_die (get_skeleton_type_unit ());
- }
-#endif
}
/* Return the DWARF2/3 pubname associated with a decl. */
@@ -24331,7 +24277,6 @@ dwarf2out_finish (const char *filename)
skeleton die attrs are added when the skeleton type unit is
created, so ensure it is created by this point. */
add_top_level_skeleton_die_attrs (main_comp_unit_die);
- (void) get_skeleton_type_unit ();
htab_traverse_noresize (debug_str_hash, index_string, &index);
}
diff --git a/gcc-4.9/gcc/final.c b/gcc-4.9/gcc/final.c
index 9af0b2b..38c90b2 100644
--- a/gcc-4.9/gcc/final.c
+++ b/gcc-4.9/gcc/final.c
@@ -4501,8 +4501,6 @@ rest_of_handle_final (void)
assemble_end_function (current_function_decl, fnname);
- user_defined_section_attribute = false;
-
/* Free up reg info memory. */
free_reg_info ();
diff --git a/gcc-4.9/gcc/fortran/ChangeLog b/gcc-4.9/gcc/fortran/ChangeLog
index d2e070b..9f4bec7 100644
--- a/gcc-4.9/gcc/fortran/ChangeLog
+++ b/gcc-4.9/gcc/fortran/ChangeLog
@@ -1,3 +1,59 @@
+2014-08-21 Thomas Koenig <tkoenig@gcc.gnu.org>
+
+ Backport from trunk
+ PR fortran/62214
+ * frontend-passes.c (optimize_binop_array_assignment):
+ Do not try to optimize the array assignment for string
+ concatenation.
+
+2014-08-16 Thomas Koenig <tkoenig@gcc.gnu.org>
+
+ Backport from trunk
+ PR fortran/62142
+ * trans-expr.c (is_runtime_conformable): Add NULL pointer checks.
+
+2014-08-15 Thomas Koenig <tkoenig@gcc.gnu.org>
+
+ Backport from trunk
+ PR fortran/62106
+ * gfortran.h (symbol_attribute): Add fe_temp flag.
+ * frontend-passes.c (is_fe_temp): New function.
+ (create_var): Don't add a temporary for an already
+ created variable or for a constant.
+ (combine_ARRAY_constructor): Remove special handling
+ for constants.
+
+2014-08-15 Jakub Jelinek <jakub@redhat.com>
+ Tobias Burnus <burnus@net-b.de>
+
+ PR fortran/62131
+ * openmp.c (resolve_omp_atomic): Only complain if code->expr1's attr
+ is allocatable, rather than whenever var->attr.allocatable.
+
+2014-08-15 Jakub Jelinek <jakub@redhat.com>
+
+ PR fortran/62107
+ * trans-openmp.c (gfc_omp_finish_clause): Handle scalar pointer
+ or allocatable passed by reference.
+ (gfc_trans_omp_clauses) <case OMP_LIST_MAP>: Likewise.
+
+2014-08-14 Jakub Jelinek <jakub@redhat.com>
+
+ PR fortran/62076
+ * openmp.c (gfc_match_omp_clauses): When failed to match
+ operator name, defined op name or name, set buffer to
+ empty string. Don't call gfc_find_omp_udr if buffer is empty
+ string.
+ (gfc_match_omp_declare_reduction): Call gfc_undo_symbols ()
+ before calling gfc_free_omp_udr.
+
+2014-08-10 Thomas Koenig <tkoenig@gcc.gnu.org>
+
+ Backport from trunk
+ PR fortran/61999
+ * simplify.c (gfc_simplify_dot_product): Convert types of
+ vectors before calculating the result.
+
2014-07-19 Paul Thomas <pault@gcc.gnu.org>
Backport from mainline
diff --git a/gcc-4.9/gcc/fortran/frontend-passes.c b/gcc-4.9/gcc/fortran/frontend-passes.c
index 4646cc3..23a8ece 100644
--- a/gcc-4.9/gcc/fortran/frontend-passes.c
+++ b/gcc-4.9/gcc/fortran/frontend-passes.c
@@ -430,11 +430,26 @@ cfe_register_funcs (gfc_expr **e, int *walk_subtrees ATTRIBUTE_UNUSED,
return 0;
}
+/* Auxiliary function to check if an expression is a temporary created by
+ create var. */
+
+static bool
+is_fe_temp (gfc_expr *e)
+{
+ if (e->expr_type != EXPR_VARIABLE)
+ return false;
+
+ return e->symtree->n.sym->attr.fe_temp;
+}
+
+
/* Returns a new expression (a variable) to be used in place of the old one,
with an assignment statement before the current statement to set
the value of the variable. Creates a new BLOCK for the statement if
that hasn't already been done and puts the statement, plus the
- newly created variables, in that block. */
+ newly created variables, in that block. Special cases: If the
+ expression is constant or a temporary which has already
+ been created, just copy it. */
static gfc_expr*
create_var (gfc_expr * e)
@@ -448,6 +463,9 @@ create_var (gfc_expr * e)
gfc_namespace *ns;
int i;
+ if (e->expr_type == EXPR_CONSTANT || is_fe_temp (e))
+ return gfc_copy_expr (e);
+
/* If the block hasn't already been created, do so. */
if (inserted_block == NULL)
{
@@ -522,6 +540,7 @@ create_var (gfc_expr * e)
symbol->attr.flavor = FL_VARIABLE;
symbol->attr.referenced = 1;
symbol->attr.dimension = e->rank > 0;
+ symbol->attr.fe_temp = 1;
gfc_commit_symbol (symbol);
result = gfc_get_expr ();
@@ -884,6 +903,10 @@ optimize_binop_array_assignment (gfc_code *c, gfc_expr **rhs, bool seen_op)
return true;
break;
+ case INTRINSIC_CONCAT:
+ /* Do not do string concatenations. */
+ break;
+
default:
/* Binary operators. */
if (optimize_binop_array_assignment (c, &e->value.op.op1, true))
@@ -1082,10 +1105,7 @@ combine_array_constructor (gfc_expr *e)
if (op2->ts.type == BT_CHARACTER)
return false;
- if (op2->expr_type == EXPR_CONSTANT)
- scalar = gfc_copy_expr (op2);
- else
- scalar = create_var (gfc_copy_expr (op2));
+ scalar = create_var (gfc_copy_expr (op2));
oldbase = op1->value.constructor;
newbase = NULL;
diff --git a/gcc-4.9/gcc/fortran/gfortran.h b/gcc-4.9/gcc/fortran/gfortran.h
index 6b88aec..a193f53 100644
--- a/gcc-4.9/gcc/fortran/gfortran.h
+++ b/gcc-4.9/gcc/fortran/gfortran.h
@@ -724,7 +724,7 @@ typedef struct
optional:1, pointer:1, target:1, value:1, volatile_:1, temporary:1,
dummy:1, result:1, assign:1, threadprivate:1, not_always_present:1,
implied_index:1, subref_array_pointer:1, proc_pointer:1, asynchronous:1,
- contiguous:1;
+ contiguous:1, fe_temp: 1;
/* For CLASS containers, the pointer attribute is sometimes set internally
even though it was not directly specified. In this case, keep the
diff --git a/gcc-4.9/gcc/fortran/openmp.c b/gcc-4.9/gcc/fortran/openmp.c
index 68ba70f..58aaf66 100644
--- a/gcc-4.9/gcc/fortran/openmp.c
+++ b/gcc-4.9/gcc/fortran/openmp.c
@@ -464,7 +464,11 @@ gfc_match_omp_clauses (gfc_omp_clauses **cp, unsigned int mask,
|| !gfc_add_intrinsic (&sym->attr, NULL)))
rop = OMP_REDUCTION_NONE;
}
- gfc_omp_udr *udr = gfc_find_omp_udr (gfc_current_ns, buffer, NULL);
+ else
+ buffer[0] = '\0';
+ gfc_omp_udr *udr
+ = (buffer[0]
+ ? gfc_find_omp_udr (gfc_current_ns, buffer, NULL) : NULL);
gfc_omp_namelist **head = NULL;
if (rop == OMP_REDUCTION_NONE && udr)
rop = OMP_REDUCTION_USER;
@@ -1240,6 +1244,7 @@ gfc_match_omp_declare_reduction (void)
syntax:
gfc_current_locus = old_loc;
gfc_current_ns = combiner_ns->parent;
+ gfc_undo_symbols ();
gfc_free_omp_udr (omp_udr);
return MATCH_ERROR;
}
@@ -2739,7 +2744,7 @@ resolve_omp_atomic (gfc_code *code)
break;
}
- if (var->attr.allocatable)
+ if (gfc_expr_attr (code->expr1).allocatable)
{
gfc_error ("!$OMP ATOMIC with ALLOCATABLE variable at %L",
&code->loc);
diff --git a/gcc-4.9/gcc/fortran/simplify.c b/gcc-4.9/gcc/fortran/simplify.c
index 96d0f21..d205523 100644
--- a/gcc-4.9/gcc/fortran/simplify.c
+++ b/gcc-4.9/gcc/fortran/simplify.c
@@ -1878,13 +1878,22 @@ gfc_simplify_dim (gfc_expr *x, gfc_expr *y)
gfc_expr*
gfc_simplify_dot_product (gfc_expr *vector_a, gfc_expr *vector_b)
{
+
+ gfc_expr temp;
+
if (!is_constant_array_expr (vector_a)
|| !is_constant_array_expr (vector_b))
return NULL;
gcc_assert (vector_a->rank == 1);
gcc_assert (vector_b->rank == 1);
- gcc_assert (gfc_compare_types (&vector_a->ts, &vector_b->ts));
+
+ temp.expr_type = EXPR_OP;
+ gfc_clear_ts (&temp.ts);
+ temp.value.op.op = INTRINSIC_NONE;
+ temp.value.op.op1 = vector_a;
+ temp.value.op.op2 = vector_b;
+ gfc_type_convert_binary (&temp, 1);
return compute_dot_product (vector_a, 1, 0, vector_b, 1, 0, true);
}
diff --git a/gcc-4.9/gcc/fortran/trans-expr.c b/gcc-4.9/gcc/fortran/trans-expr.c
index dbfde1b..824ab78 100644
--- a/gcc-4.9/gcc/fortran/trans-expr.c
+++ b/gcc-4.9/gcc/fortran/trans-expr.c
@@ -7842,7 +7842,7 @@ is_runtime_conformable (gfc_expr *expr1, gfc_expr *expr2)
for (a = expr2->value.function.actual; a != NULL; a = a->next)
{
e1 = a->expr;
- if (e1->rank > 0 && !is_runtime_conformable (expr1, e1))
+ if (e1 && e1->rank > 0 && !is_runtime_conformable (expr1, e1))
return false;
}
return true;
@@ -7853,7 +7853,7 @@ is_runtime_conformable (gfc_expr *expr1, gfc_expr *expr2)
for (a = expr2->value.function.actual; a != NULL; a = a->next)
{
e1 = a->expr;
- if (e1->rank > 0 && !is_runtime_conformable (expr1, e1))
+ if (e1 && e1->rank > 0 && !is_runtime_conformable (expr1, e1))
return false;
}
return true;
diff --git a/gcc-4.9/gcc/fortran/trans-openmp.c b/gcc-4.9/gcc/fortran/trans-openmp.c
index da01a90..548b5d3 100644
--- a/gcc-4.9/gcc/fortran/trans-openmp.c
+++ b/gcc-4.9/gcc/fortran/trans-openmp.c
@@ -1022,6 +1022,7 @@ gfc_omp_finish_clause (tree c, gimple_seq *pre_p)
&& !GFC_DECL_CRAY_POINTEE (decl)
&& !GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (TREE_TYPE (decl))))
return;
+ tree orig_decl = decl;
c4 = build_omp_clause (OMP_CLAUSE_LOCATION (c), OMP_CLAUSE_MAP);
OMP_CLAUSE_MAP_KIND (c4) = OMP_CLAUSE_MAP_POINTER;
OMP_CLAUSE_DECL (c4) = decl;
@@ -1029,6 +1030,17 @@ gfc_omp_finish_clause (tree c, gimple_seq *pre_p)
decl = build_fold_indirect_ref (decl);
OMP_CLAUSE_DECL (c) = decl;
OMP_CLAUSE_SIZE (c) = NULL_TREE;
+ if (TREE_CODE (TREE_TYPE (orig_decl)) == REFERENCE_TYPE
+ && (GFC_DECL_GET_SCALAR_POINTER (orig_decl)
+ || GFC_DECL_GET_SCALAR_ALLOCATABLE (orig_decl)))
+ {
+ c3 = build_omp_clause (OMP_CLAUSE_LOCATION (c), OMP_CLAUSE_MAP);
+ OMP_CLAUSE_MAP_KIND (c3) = OMP_CLAUSE_MAP_POINTER;
+ OMP_CLAUSE_DECL (c3) = unshare_expr (decl);
+ OMP_CLAUSE_SIZE (c3) = size_int (0);
+ decl = build_fold_indirect_ref (decl);
+ OMP_CLAUSE_DECL (c) = decl;
+ }
}
if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (decl)))
{
@@ -1884,14 +1896,32 @@ gfc_trans_omp_clauses (stmtblock_t *block, gfc_omp_clauses *clauses,
TREE_ADDRESSABLE (decl) = 1;
if (n->expr == NULL || n->expr->ref->u.ar.type == AR_FULL)
{
- if (POINTER_TYPE_P (TREE_TYPE (decl)))
+ if (POINTER_TYPE_P (TREE_TYPE (decl))
+ && (gfc_omp_privatize_by_reference (decl)
+ || GFC_DECL_GET_SCALAR_POINTER (decl)
+ || GFC_DECL_GET_SCALAR_ALLOCATABLE (decl)
+ || GFC_DECL_CRAY_POINTEE (decl)
+ || GFC_DESCRIPTOR_TYPE_P
+ (TREE_TYPE (TREE_TYPE (decl)))))
{
+ tree orig_decl = decl;
node4 = build_omp_clause (input_location,
OMP_CLAUSE_MAP);
OMP_CLAUSE_MAP_KIND (node4) = OMP_CLAUSE_MAP_POINTER;
OMP_CLAUSE_DECL (node4) = decl;
OMP_CLAUSE_SIZE (node4) = size_int (0);
decl = build_fold_indirect_ref (decl);
+ if (TREE_CODE (TREE_TYPE (orig_decl)) == REFERENCE_TYPE
+ && (GFC_DECL_GET_SCALAR_POINTER (orig_decl)
+ || GFC_DECL_GET_SCALAR_ALLOCATABLE (orig_decl)))
+ {
+ node3 = build_omp_clause (input_location,
+ OMP_CLAUSE_MAP);
+ OMP_CLAUSE_MAP_KIND (node3) = OMP_CLAUSE_MAP_POINTER;
+ OMP_CLAUSE_DECL (node3) = decl;
+ OMP_CLAUSE_SIZE (node3) = size_int (0);
+ decl = build_fold_indirect_ref (decl);
+ }
}
if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (decl)))
{
diff --git a/gcc-4.9/gcc/gcov-tool.c b/gcc-4.9/gcc/gcov-tool.c
index e7b551e..37d1562 100644
--- a/gcc-4.9/gcc/gcov-tool.c
+++ b/gcc-4.9/gcc/gcov-tool.c
@@ -54,7 +54,6 @@ extern void set_use_existing_grouping (void);
extern void set_use_modu_list (void);
extern void lipo_set_substitute_string (const char *);
-#if !defined(_WIN32)
/* The following defines are needed by dyn-ipa.c.
They will also be emitted by the compiler with -fprofile-generate,
which means this file cannot be compiled with -fprofile-generate
@@ -77,18 +76,6 @@ WEAK_ATTR gcov_unsigned_t __gcov_lipo_cutoff;
WEAK_ATTR gcov_unsigned_t __gcov_lipo_random_seed;
WEAK_ATTR gcov_unsigned_t __gcov_lipo_dump_cgraph;
WEAK_ATTR gcov_unsigned_t __gcov_lipo_propagate_scale;
-#else
-gcov_unsigned_t __gcov_lipo_grouping_algorithm;
-gcov_unsigned_t __gcov_lipo_merge_modu_edges;
-gcov_unsigned_t __gcov_lipo_weak_inclusion;
-gcov_unsigned_t __gcov_lipo_max_mem;
-gcov_unsigned_t __gcov_lipo_comdat_algorithm;
-gcov_unsigned_t __gcov_lipo_random_group_size;
-gcov_unsigned_t __gcov_lipo_cutoff;
-gcov_unsigned_t __gcov_lipo_random_seed;
-gcov_unsigned_t __gcov_lipo_dump_cgraph;
-gcov_unsigned_t __gcov_lipo_propagate_scale;
-#endif
#undef WEAK_ATTR
diff --git a/gcc-4.9/gcc/genconfig.c b/gcc-4.9/gcc/genconfig.c
index cafa8d3..d1996c3 100644
--- a/gcc-4.9/gcc/genconfig.c
+++ b/gcc-4.9/gcc/genconfig.c
@@ -36,6 +36,8 @@ static int have_cc0_flag;
static int have_cmove_flag;
static int have_cond_exec_flag;
static int have_lo_sum_flag;
+static int have_rotate_flag;
+static int have_rotatert_flag;
static int have_peephole_flag;
static int have_peephole2_flag;
@@ -117,6 +119,16 @@ walk_insn_part (rtx part, int recog_p, int non_pc_set_src)
have_lo_sum_flag = 1;
return;
+ case ROTATE:
+ if (recog_p)
+ have_rotate_flag = 1;
+ return;
+
+ case ROTATERT:
+ if (recog_p)
+ have_rotatert_flag = 1;
+ return;
+
case SET:
walk_insn_part (SET_DEST (part), 0, recog_p);
walk_insn_part (SET_SRC (part), recog_p,
@@ -346,6 +358,12 @@ main (int argc, char **argv)
if (have_lo_sum_flag)
printf ("#define HAVE_lo_sum 1\n");
+ if (have_rotate_flag)
+ printf ("#define HAVE_rotate 1\n");
+
+ if (have_rotatert_flag)
+ printf ("#define HAVE_rotatert 1\n");
+
if (have_peephole_flag)
printf ("#define HAVE_peephole 1\n");
diff --git a/gcc-4.9/gcc/gimple-fold.c b/gcc-4.9/gcc/gimple-fold.c
index 57ab858..ab38bde 100644
--- a/gcc-4.9/gcc/gimple-fold.c
+++ b/gcc-4.9/gcc/gimple-fold.c
@@ -3106,8 +3106,8 @@ fold_ctor_reference (tree type, tree ctor, unsigned HOST_WIDE_INT offset,
result. */
if (!AGGREGATE_TYPE_P (TREE_TYPE (ctor)) && !offset
/* VIEW_CONVERT_EXPR is defined only for matching sizes. */
- && operand_equal_p (TYPE_SIZE (type),
- TYPE_SIZE (TREE_TYPE (ctor)), 0))
+ && !compare_tree_int (TYPE_SIZE (type), size)
+ && !compare_tree_int (TYPE_SIZE (TREE_TYPE (ctor)), size))
{
ret = canonicalize_constructor_val (unshare_expr (ctor), from_decl);
ret = fold_unary (VIEW_CONVERT_EXPR, type, ret);
diff --git a/gcc-4.9/gcc/gimple.h b/gcc-4.9/gcc/gimple.h
index 11959a8..50a5a86 100644
--- a/gcc-4.9/gcc/gimple.h
+++ b/gcc-4.9/gcc/gimple.h
@@ -90,6 +90,7 @@ enum gf_mask {
GF_CALL_NOTHROW = 1 << 4,
GF_CALL_ALLOCA_FOR_VAR = 1 << 5,
GF_CALL_INTERNAL = 1 << 6,
+ GF_CALL_CTRL_ALTERING = 1 << 7,
GF_OMP_PARALLEL_COMBINED = 1 << 0,
GF_OMP_FOR_KIND_MASK = 3 << 0,
GF_OMP_FOR_KIND_FOR = 0 << 0,
@@ -2447,6 +2448,29 @@ gimple_call_internal_fn (const_gimple gs)
return static_cast <const gimple_statement_call *> (gs)->u.internal_fn;
}
+/* If CTRL_ALTERING_P is true, mark GIMPLE_CALL S to be a stmt
+ that could alter control flow. */
+
+static inline void
+gimple_call_set_ctrl_altering (gimple s, bool ctrl_altering_p)
+{
+ GIMPLE_CHECK (s, GIMPLE_CALL);
+ if (ctrl_altering_p)
+ s->subcode |= GF_CALL_CTRL_ALTERING;
+ else
+ s->subcode &= ~GF_CALL_CTRL_ALTERING;
+}
+
+/* Return true if call GS calls an func whose GF_CALL_CTRL_ALTERING
+ flag is set. Such call could not be a stmt in the middle of a bb. */
+
+static inline bool
+gimple_call_ctrl_altering_p (const_gimple gs)
+{
+ GIMPLE_CHECK (gs, GIMPLE_CALL);
+ return (gs->subcode & GF_CALL_CTRL_ALTERING) != 0;
+}
+
/* Return the function type of the function called by GS. */
diff --git a/gcc-4.9/gcc/gimplify.c b/gcc-4.9/gcc/gimplify.c
index a550544..bcf6f09 100644
--- a/gcc-4.9/gcc/gimplify.c
+++ b/gcc-4.9/gcc/gimplify.c
@@ -6273,7 +6273,7 @@ gimplify_adjust_omp_clauses_1 (splay_tree_node n, void *data)
= splay_tree_lookup (ctx->variables, (splay_tree_key) decl);
if (on && (on->value & (GOVD_FIRSTPRIVATE | GOVD_LASTPRIVATE
| GOVD_PRIVATE | GOVD_REDUCTION
- | GOVD_LINEAR)) != 0)
+ | GOVD_LINEAR | GOVD_MAP)) != 0)
break;
ctx = ctx->outer_context;
}
diff --git a/gcc-4.9/gcc/go/gofrontend/parse.cc b/gcc-4.9/gcc/go/gofrontend/parse.cc
index 7614e6f..7a9faaa 100644
--- a/gcc-4.9/gcc/go/gofrontend/parse.cc
+++ b/gcc-4.9/gcc/go/gofrontend/parse.cc
@@ -2865,7 +2865,10 @@ Parse::function_lit()
// For a function literal, the next token must be a '{'. If we
// don't see that, then we may have a type expression.
if (!this->peek_token()->is_op(OPERATOR_LCURLY))
- return Expression::make_type(type, location);
+ {
+ hold_enclosing_vars.swap(this->enclosing_vars_);
+ return Expression::make_type(type, location);
+ }
bool hold_is_erroneous_function = this->is_erroneous_function_;
if (fntype_is_error)
diff --git a/gcc-4.9/gcc/haifa-sched.c b/gcc-4.9/gcc/haifa-sched.c
index 2d66e5c..653cb82 100644
--- a/gcc-4.9/gcc/haifa-sched.c
+++ b/gcc-4.9/gcc/haifa-sched.c
@@ -2972,7 +2972,7 @@ advance_one_cycle (void)
{
advance_state (curr_state);
if (sched_verbose >= 6)
- fprintf (sched_dump, ";;\tAdvanced a state.\n");
+ fprintf (sched_dump, ";;\tAdvance the current state.\n");
}
/* Update register pressure after scheduling INSN. */
@@ -6007,6 +6007,7 @@ schedule_block (basic_block *target_bb, state_t init_state)
modulo_insns_scheduled = 0;
ls.modulo_epilogue = false;
+ ls.first_cycle_insn_p = true;
/* Loop until all the insns in BB are scheduled. */
while ((*current_sched_info->schedule_more_p) ())
@@ -6077,7 +6078,6 @@ schedule_block (basic_block *target_bb, state_t init_state)
if (must_backtrack)
goto do_backtrack;
- ls.first_cycle_insn_p = true;
ls.shadows_only_p = false;
cycle_issued_insns = 0;
ls.can_issue_more = issue_rate;
@@ -6363,11 +6363,13 @@ schedule_block (basic_block *target_bb, state_t init_state)
break;
}
}
+ ls.first_cycle_insn_p = true;
}
if (ls.modulo_epilogue)
success = true;
end_schedule:
- advance_one_cycle ();
+ if (!ls.first_cycle_insn_p)
+ advance_one_cycle ();
perform_replacements_new_cycle ();
if (modulo_ii > 0)
{
diff --git a/gcc-4.9/gcc/ifcvt.c b/gcc-4.9/gcc/ifcvt.c
index 0d1adce..49ff85c 100644
--- a/gcc-4.9/gcc/ifcvt.c
+++ b/gcc-4.9/gcc/ifcvt.c
@@ -306,6 +306,28 @@ block_fallthru (basic_block bb)
return (e) ? e->dest : NULL_BLOCK;
}
+
+/* Return true if RTXs A and B can be safely interchanged. */
+
+static bool
+rtx_interchangeable_p (const_rtx a, const_rtx b)
+{
+ if (!rtx_equal_p (a, b))
+ return false;
+
+ if (GET_CODE (a) != MEM)
+ return true;
+
+ /* A dead type-unsafe memory reference is legal, but a live type-unsafe memory
+ reference is not. Interchanging a dead type-unsafe memory reference with
+ a live type-safe one creates a live type-unsafe memory reference, in other
+ words, it makes the program illegal.
+ We check here conservatively whether the two memory references have equal
+ memory attributes. */
+
+ return mem_attrs_eq_p (get_mem_attrs (a), get_mem_attrs (b));
+}
+
/* Go through a bunch of insns, converting them to conditional
execution format if possible. Return TRUE if all of the non-note
@@ -1034,6 +1056,9 @@ noce_try_move (struct noce_if_info *if_info)
|| (rtx_equal_p (if_info->a, XEXP (cond, 1))
&& rtx_equal_p (if_info->b, XEXP (cond, 0))))
{
+ if (!rtx_interchangeable_p (if_info->a, if_info->b))
+ return FALSE;
+
y = (code == EQ) ? if_info->a : if_info->b;
/* Avoid generating the move if the source is the destination. */
@@ -2504,7 +2529,7 @@ noce_process_if_block (struct noce_if_info *if_info)
if (! insn_b
|| insn_b != last_active_insn (else_bb, FALSE)
|| (set_b = single_set (insn_b)) == NULL_RTX
- || ! rtx_equal_p (x, SET_DEST (set_b)))
+ || ! rtx_interchangeable_p (x, SET_DEST (set_b)))
return FALSE;
}
else
@@ -2517,7 +2542,7 @@ noce_process_if_block (struct noce_if_info *if_info)
|| BLOCK_FOR_INSN (insn_b) != BLOCK_FOR_INSN (if_info->cond_earliest)
|| !NONJUMP_INSN_P (insn_b)
|| (set_b = single_set (insn_b)) == NULL_RTX
- || ! rtx_equal_p (x, SET_DEST (set_b))
+ || ! rtx_interchangeable_p (x, SET_DEST (set_b))
|| ! noce_operand_ok (SET_SRC (set_b))
|| reg_overlap_mentioned_p (x, SET_SRC (set_b))
|| modified_between_p (SET_SRC (set_b), insn_b, jump)
@@ -2583,7 +2608,7 @@ noce_process_if_block (struct noce_if_info *if_info)
/* Look and see if A and B are really the same. Avoid creating silly
cmove constructs that no one will fix up later. */
- if (rtx_equal_p (a, b))
+ if (rtx_interchangeable_p (a, b))
{
/* If we have an INSN_B, we don't have to create any new rtl. Just
move the instruction that we already have. If we don't have an
diff --git a/gcc-4.9/gcc/l-ipo.c b/gcc-4.9/gcc/l-ipo.c
index 59a9636..59dbd33 100644
--- a/gcc-4.9/gcc/l-ipo.c
+++ b/gcc-4.9/gcc/l-ipo.c
@@ -1564,6 +1564,15 @@ resolve_cgraph_node (struct cgraph_sym **slot, struct cgraph_node *node)
(*slot)->rep_decl = decl2;
return;
}
+ /* Similarly, pick the non-external symbol, since external
+ symbols may be eliminated by symtab_remove_unreachable_nodes
+ after ipa inlining (see process_references). */
+ if (DECL_EXTERNAL (decl1) && !DECL_EXTERNAL (decl2))
+ {
+ (*slot)->rep_node = node;
+ (*slot)->rep_decl = decl2;
+ return;
+ }
has_prof1 = has_profile_info (decl1);
bool is_aux1 = cgraph_is_auxiliary (decl1);
@@ -2304,31 +2313,44 @@ fixup_reference_list (struct varpool_node *node)
int i;
struct ipa_ref *ref;
struct ipa_ref_list *list = &node->ref_list;
- vec<cgraph_node_ptr> new_refered;
+ vec<symtab_node *> new_refered;
vec<int> new_refered_type;
- struct cgraph_node *c;
+ struct symtab_node *sym_node;
enum ipa_ref_use use_type = IPA_REF_LOAD;
new_refered.create (10);
new_refered_type.create (10);
for (i = 0; ipa_ref_list_reference_iterate (list, i, ref); i++)
{
- if (!is_a <cgraph_node> (ref->referred))
- continue;
-
- struct cgraph_node *cnode = ipa_ref_node (ref);
- struct cgraph_node *r_cnode
- = cgraph_lipo_get_resolved_node (cnode->decl);
- if (r_cnode != cnode)
+ if (is_a <cgraph_node> (ref->referred))
{
+ struct cgraph_node *cnode = ipa_ref_node (ref);
+ struct cgraph_node *r_cnode
+ = cgraph_lipo_get_resolved_node (cnode->decl);
new_refered.safe_push (r_cnode);
use_type = ref->use;
new_refered_type.safe_push ((int) use_type);
+ gcc_assert (use_type != IPA_REF_ADDR
+ || cnode->global.inlined_to
+ || cnode->address_taken);
+ if (use_type == IPA_REF_ADDR)
+ cgraph_mark_address_taken_node (r_cnode);
+ }
+ else if (is_a <varpool_node> (ref->referred))
+ {
+ struct varpool_node *var = ipa_ref_varpool_node (ref);
+ struct varpool_node *r_var = real_varpool_node (var->decl);
+ new_refered.safe_push (r_var);
+ use_type = ref->use;
+ new_refered_type.safe_push ((int) use_type);
}
+ else
+ gcc_assert (false);
}
- for (i = 0; new_refered.iterate (i, &c); ++i)
+ ipa_remove_all_references (&node->ref_list);
+ for (i = 0; new_refered.iterate (i, &sym_node); ++i)
{
- ipa_record_reference (node, c,
+ ipa_record_reference (node, sym_node,
(enum ipa_ref_use) new_refered_type[i], NULL);
}
}
diff --git a/gcc-4.9/gcc/l-ipo.h b/gcc-4.9/gcc/l-ipo.h
index e9c661b..a4ff3d5 100644
--- a/gcc-4.9/gcc/l-ipo.h
+++ b/gcc-4.9/gcc/l-ipo.h
@@ -63,6 +63,7 @@ int equivalent_struct_types_for_tbaa (const_tree t1, const_tree t2);
void lipo_link_and_fixup (void);
extern void copy_defined_module_set (tree, tree);
extern bool is_parsing_done_p (void);
+extern void record_module_name (unsigned int, const char *);
extern const char* get_module_name (unsigned int);
#endif
diff --git a/gcc-4.9/gcc/lra-constraints.c b/gcc-4.9/gcc/lra-constraints.c
index ec28b7f..f967d71 100644
--- a/gcc-4.9/gcc/lra-constraints.c
+++ b/gcc-4.9/gcc/lra-constraints.c
@@ -5851,6 +5851,20 @@ remove_inheritance_pseudos (bitmap remove_pseudos)
SUBREG_REG (SET_SRC (set)) = SET_SRC (prev_set);
else
SET_SRC (set) = SET_SRC (prev_set);
+ /* As we are finishing with processing the insn
+ here, check the destination too as it might
+ inheritance pseudo for another pseudo. */
+ if (bitmap_bit_p (remove_pseudos, dregno)
+ && bitmap_bit_p (&lra_inheritance_pseudos, dregno)
+ && (restore_regno
+ = lra_reg_info[dregno].restore_regno) >= 0)
+ {
+ if (GET_CODE (SET_DEST (set)) == SUBREG)
+ SUBREG_REG (SET_DEST (set))
+ = regno_reg_rtx[restore_regno];
+ else
+ SET_DEST (set) = regno_reg_rtx[restore_regno];
+ }
lra_push_insn_and_update_insn_regno_info (curr_insn);
lra_set_used_insn_alternative_by_uid
(INSN_UID (curr_insn), -1);
diff --git a/gcc-4.9/gcc/lto/ChangeLog b/gcc-4.9/gcc/lto/ChangeLog
index c029da6..6c6ea2b 100644
--- a/gcc-4.9/gcc/lto/ChangeLog
+++ b/gcc-4.9/gcc/lto/ChangeLog
@@ -1,3 +1,11 @@
+2014-08-15 Bin Cheng <bin.cheng@arm.com>
+
+ Backport from mainline
+ 2014-08-08 Bin Cheng <bin.cheng@arm.com>
+
+ PR lto/62032
+ * lto-lang.c (lto_init): Switch mis-matched arguments.
+
2014-07-16 Release Manager
* GCC 4.9.1 released.
diff --git a/gcc-4.9/gcc/lto/lto-lang.c b/gcc-4.9/gcc/lto/lto-lang.c
index f60d212..1a4da91 100644
--- a/gcc-4.9/gcc/lto/lto-lang.c
+++ b/gcc-4.9/gcc/lto/lto-lang.c
@@ -1186,10 +1186,10 @@ lto_init (void)
}
else
{
- lto_define_builtins (va_list_type_node,
- build_reference_type (va_list_type_node));
+ lto_define_builtins (build_reference_type (va_list_type_node),
+ va_list_type_node);
}
-
+
if (flag_cilkplus)
cilk_init_builtins ();
diff --git a/gcc-4.9/gcc/optabs.c b/gcc-4.9/gcc/optabs.c
index cd31b0e..39e8cd4 100644
--- a/gcc-4.9/gcc/optabs.c
+++ b/gcc-4.9/gcc/optabs.c
@@ -7337,7 +7337,10 @@ expand_atomic_test_and_set (rtx target, rtx mem, enum memmodel model)
perform the operation. */
if (!ret)
{
- emit_move_insn (subtarget, mem);
+ /* If the result is ignored skip the move to target. */
+ if (subtarget != const0_rtx)
+ emit_move_insn (subtarget, mem);
+
emit_move_insn (mem, trueval);
ret = subtarget;
}
diff --git a/gcc-4.9/gcc/sched-deps.c b/gcc-4.9/gcc/sched-deps.c
index df29bd3..1d47007 100644
--- a/gcc-4.9/gcc/sched-deps.c
+++ b/gcc-4.9/gcc/sched-deps.c
@@ -4747,6 +4747,24 @@ find_inc (struct mem_inc_info *mii, bool backwards)
goto next;
}
}
+
+ /* The inc instruction could have clobbers, make sure those
+ registers are not used in mem insn. */
+ for (def_rec = DF_INSN_DEFS (mii->inc_insn); *def_rec; def_rec++)
+ if (!reg_overlap_mentioned_p (DF_REF_REG (*def_rec), mii->mem_reg0))
+ {
+ df_ref *use_rec;
+ for (use_rec = DF_INSN_USES (mii->mem_insn); *use_rec; use_rec++)
+ if (reg_overlap_mentioned_p (DF_REF_REG (*def_rec),
+ DF_REF_REG (*use_rec)))
+ {
+ if (sched_verbose >= 5)
+ fprintf (sched_dump,
+ "inc clobber used in store failure.\n");
+ goto next;
+ }
+ }
+
newaddr = mii->inc_input;
if (mii->mem_index != NULL_RTX)
newaddr = gen_rtx_PLUS (GET_MODE (newaddr), newaddr,
diff --git a/gcc-4.9/gcc/simplify-rtx.c b/gcc-4.9/gcc/simplify-rtx.c
index 04af01e..c64de31 100644
--- a/gcc-4.9/gcc/simplify-rtx.c
+++ b/gcc-4.9/gcc/simplify-rtx.c
@@ -3330,6 +3330,7 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
prefer left rotation, if op1 is from bitsize / 2 + 1 to
bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
amount instead. */
+#if defined(HAVE_rotate) && defined(HAVE_rotatert)
if (CONST_INT_P (trueop1)
&& IN_RANGE (INTVAL (trueop1),
GET_MODE_BITSIZE (mode) / 2 + (code == ROTATE),
@@ -3337,6 +3338,7 @@ simplify_binary_operation_1 (enum rtx_code code, enum machine_mode mode,
return simplify_gen_binary (code == ROTATE ? ROTATERT : ROTATE,
mode, op0, GEN_INT (GET_MODE_BITSIZE (mode)
- INTVAL (trueop1)));
+#endif
/* FALLTHRU */
case ASHIFTRT:
if (trueop1 == CONST0_RTX (mode))
diff --git a/gcc-4.9/gcc/testsuite/ChangeLog b/gcc-4.9/gcc/testsuite/ChangeLog
index 7903199..4a7de28 100644
--- a/gcc-4.9/gcc/testsuite/ChangeLog
+++ b/gcc-4.9/gcc/testsuite/ChangeLog
@@ -1,3 +1,220 @@
+2014-08-26 Dominik Vogt <vogt@linux.vnet.ibm.com>
+
+ * gfortran.dg/bessel_7.f90: Bump allowed precision to avoid
+ failure on s390*-*-linux-gnu.
+
+2014-08-24 Oleg Endo <olegendo@gcc.gnu.org>
+
+ Backport from mainline
+ 2014-08-24 Oleg Endo <olegendo@gcc.gnu.org>
+
+ PR target/61996
+ * gcc.target/sh/pr61996.c: New.
+
+2014-08-22 Igor Zamyatin <igor.zamyatin@intel.com>
+
+ PR other/62008
+ * c-c++-common/cilk-plus/AN/pr62008.c: New test.
+
+2014-08-21 Thomas Koenig <tkoenig@gcc.gnu.org>
+
+ Backport from trunk
+ PR fortran/62214
+ * gfortran.dg/array_assignment_5.f90: New test.
+
+2014-08-20 Martin Jambor <mjambor@suse.cz>
+ Wei Mi <wmi@google.com>
+
+ PR ipa/60449
+ PR middle-end/61776
+ * testsuite/gcc.dg/lto/pr60449_1.c: New test.
+ * testsuite/gcc.dg/lto/pr60449_0.c: New test.
+ * testsuite/gcc.dg/pr61776.c: New test.
+
+2014-08-19 Janis Johnson <janisjo@codesourcery.com>
+
+ Backport from mainline:
+ 2014-08-19 Janis Johnson <janisjo@codesourcery.com>
+
+ * lib/target-supports.exp
+ (check_effective_target_arm_v8_neon_ok_nocache): Add
+ "-march-armv8-a" to compile flags.
+
+2014-08-15 Thomas Koenig <tkoenig@gcc.gnu.org>
+
+ Backport from trunk
+ PR fortran/62142
+ * gfortran.dg/realloc_on_assign_24.f90: New test.
+
+2014-08-15 Tom de Vries <tom@codesourcery.com>
+
+ Backport from mainline:
+ 2014-08-14 Tom de Vries <tom@codesourcery.com>
+
+ PR rtl-optimization/62004
+ PR rtl-optimization/62030
+ * gcc.dg/pr62004.c: New test.
+ * gcc.dg/pr62030.c: Same.
+ * gcc.target/mips/pr62030-octeon.c: Same.
+
+2014-08-15 Thomas Koenig <tkoenig@gcc.gnu.org>
+
+ Backport from trunk
+ PR fortran/62106
+ * gfortran.dg/array_constructor_49.f90: New test.
+
+2014-08-15 Jakub Jelinek <jakub@redhat.com>
+ Tobias Burnus <burnus@net-b.de>
+
+ PR fortran/62131
+ * gfortran.dg/gomp/pr62131.f90: New test.
+
+2014-08-14 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ Backport from mainline
+ 2014-08-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ PR target/61713
+ * gcc.dg/pr61756.c: New test.
+
+2014-08-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ Backport from mainline
+ 2014-08-12 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ PR middle-end/62103
+ * gcc.c-torture/execute/bitfld-6.c: New test.
+
+2014-08-12 Felix Yang <fei.yang0953@gmail.com>
+
+ PR tree-optimization/62073
+ * gcc.dg/vect/pr62073.c: New test.
+
+2014-08-12 Janis Johnson <janisjo@codesourcery.com>
+
+ Backport from mainline
+ 2014-08-12 Janis Johnson <janisjo@codesourcery.com>
+
+ * lib/target/supports.exp
+ (check_effective_target_arm_v8_neon_ok_nocache): Check for armv8
+ or later.
+
+ * gcc.dg/pr59418.c: Don't add ARM options for a Thumb1 multilib.
+
+ * gcc.target/arm/neon-vext-execute.c: Skip if the test won't run
+ on Neon hardware.
+
+ * gcc.target/arm/pr48784.c: Skip for thumb1 multilib.
+ * gcc.target/arm/pr59985.c: Likewise.
+
+2014-08-12 Igor Zamyatin <igor.zamyatin@intel.com>
+
+ PR other/61962
+ * c-c++-common/cilk-plus/AN/pr61962.c: New test.
+
+2014-08-12 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
+
+ Backport from mainline
+ 2014-06-16 Ganesh Gopalasubramanian
+ <Ganesh.Gopalasubramanian@amd.com>
+
+ * gcc.target/i386/xop-imul64-vector.c: Remove the check for
+ vpmacsdql instruction.
+
+2014-08-11 Janis Johnson <janisjo@codesourcery.com>
+
+ Backport from mainline
+ 2014-08-11 Janis Johnson <janisjo@codesourcery.com>
+
+ * lib/target-supports.exp (check_effective_target_arm_thumb1_ok,
+ check_effective_target_arm_thumb2_ok): Test with code that passes
+ an argument and returns a result.
+
+ * gcc.target/arm/frame-pointer-1.c: Skip if Thumb is not supported.
+ * gcc.target/arm/pr56184.C: Likewise.
+ * gcc.target/arm/pr59896.c: Likewise.
+ * gcc.target/arm/stack-red-zone.c: Likewise.
+ * gcc.target/arm/thumb-find-work-register.c: Likewise.
+
+2014-08-10 Thomas Koenig <tkoenig@gcc.gnu.org>
+
+ Backport from trunk
+ PR fortran/61999
+ * gfortran.dg/dot_product_3.f90: New test case.
+
+2014-08-07 John David Anglin <danglin@gcc.gnu.org>
+
+ PR tree-optimization/60707
+ * gfortran.dg/pr45636.f90: xfail on 32-bit hppa*-*-*.
+
+ * gcc.dg/atomic/c11-atomic-exec-4.c: Undefine _POSIX_C_SOURCE before
+ defining in dg-options.
+ * gcc.dg/atomic/c11-atomic-exec-5.c: Likewise.
+
+ * gcc.dg/atomic/stdatomic-flag.c: Add xfail comment.
+
+ * gcc.c-torture/compile/pr60655-1.c: Don't add -fdata-sections option
+ on 32-bit hppa-hpux.
+
+ * gcc.dg/pr57233.c: Add -fno-common option on hppa*-*-hpux*.
+
+2014-08-07 Petr Murzin <petr.murzin@intel.com>
+
+ * gcc.target/i386/avx512f-vfixupimmpd-2.c: Include float.h instead of
+ values.h, change MAXDOUBLE for DBL_MAX.
+ * gcc.target/i386/avx512f-vfixupimmsd-2.c: Ditto.
+ * gcc.target/i386/avx512f-vfixupimmps-2.c: Include float.h instead of
+ values.h, change MAXFLOAT for FLT_MAX.
+ * gcc.target/i386/avx512f-vfixupimmss-2.c: Ditto.
+ * gcc.target/i386/avx512f-vpermi2d-2.c: Do not include values.h.
+ * gcc.target/i386/avx512f-vpermi2pd-2.c: Ditto.
+ * gcc.target/i386/avx512f-vpermi2ps-2.c: Ditto.
+ * gcc.target/i386/avx512f-vpermi2q-2.c: Ditto.
+ * gcc.target/i386/avx512f-vpermt2d-2.c: Ditto.
+ * gcc.target/i386/avx512f-vpermt2pd-2.c: Ditto.
+ * gcc.target/i386/avx512f-vpermt2ps-2.c: Ditto.
+ * gcc.target/i386/avx512f-vpermt2q-2.c: Ditto.
+
+2014-08-06 Vladimir Makarov <vmakarov@redhat.com>
+
+ PR debug/61923
+ * gcc.target/i386/pr61923.c: New test.
+
+2014-08-06 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/61801
+ * gcc.target/i386/pr61801.c: Rewritten.
+
+2014-08-04 Rohit <rohitarulraj@freescale.com>
+
+ PR target/60102
+ * gcc.target/powerpc/pr60102.c: New testcase.
+
+2014-08-01 Igor Zamyatin <igor.zamyatin@intel.com>
+
+ PR other/61963
+ * c-c++-common/cilk-plus/AN/pr61963.c: New test.
+
+2014-08-01 Igor Zamyatin <igor.zamyatin@intel.com>
+
+ PR middle-end/61455
+ * c-c++-common/cilk-plus/AN/pr61455.c: New test.
+ * c-c++-common/cilk-plus/AN/pr61455-2.c: Likewise.
+
+2014-08-01 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ Backport from mainline
+ 2014-06-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ PR tree-optimization/61375
+ * gcc.c-torture/execute/pr61375-1.c: New test.
+
+2014-08-01 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/61964
+ * gcc.dg/torture/pr61964.c: New testcase.
+ * gcc.dg/pr51879-18.c: XFAIL.
+
2014-07-28 Richard Biener <rguenther@suse.de>
PR rtl-optimization/61801
diff --git a/gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61455-2.c b/gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61455-2.c
new file mode 100644
index 0000000..60b4248
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61455-2.c
@@ -0,0 +1,13 @@
+/* PR c++/61455 */
+/* { dg-options "-fcilkplus" } */
+
+int a[3] = {2, 3, 4};
+
+int main ()
+{
+ int c = 10;
+ int b = __sec_reduce_add(a[:]);
+ if (b+c != 19)
+ __builtin_abort();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61455.c b/gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61455.c
new file mode 100644
index 0000000..35a11b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61455.c
@@ -0,0 +1,9 @@
+/* PR c++/61455 */
+/* { dg-do compile } */
+/* { dg-options "-fcilkplus" } */
+
+void foo ()
+{
+ int a[2];
+ int b = a[:]; /* { dg-error "cannot be scalar" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61962.c b/gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61962.c
new file mode 100644
index 0000000..08d4fe2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61962.c
@@ -0,0 +1,14 @@
+/* PR other/61962 */
+/* { dg-do compile } */
+/* { dg-options "-fcilkplus" } */
+
+struct FloatStruct
+{
+ float *f;
+};
+
+/* Either SRC or DST must be a struct, otherwise the bug does not occur. */
+void f (struct FloatStruct* dst, float *src, unsigned int length)
+{
+ dst->f[0:length] = src[0:length];
+}
diff --git a/gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61963.c b/gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61963.c
new file mode 100644
index 0000000..dfa713c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr61963.c
@@ -0,0 +1,9 @@
+/* PR other/61963 */
+/* { dg-do compile } */
+/* { dg-options "-fcilkplus" } */
+
+void f (int * int *a) /* { dg-error "expected" } */
+{
+ a[0:64] = 0; /* { dg-error "was not declared" "" { target c++ } 7 } */
+ a[0:64] = 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr62008.c b/gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr62008.c
new file mode 100644
index 0000000..05734c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/c-c++-common/cilk-plus/AN/pr62008.c
@@ -0,0 +1,10 @@
+/* PR other/62008 */
+/* { dg-do compile } */
+/* { dg-options "-fcilkplus" } */
+
+void f(int *a, int w, int h)
+{
+ int tmp[w][h];
+ tmp[:][:] = a[0:w][0:h]; /* { dg-error "base of array section must be pointer or array type" } */
+ /* { dg-error "start-index and length fields necessary" "" { target c } 8 } */
+}
diff --git a/gcc-4.9/gcc/testsuite/c-c++-common/pr61741.c b/gcc-4.9/gcc/testsuite/c-c++-common/pr61741.c
new file mode 100644
index 0000000..a2bc4bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/c-c++-common/pr61741.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+
+int a = 1, b;
+
+void
+foo (void)
+{
+ signed char c = 0;
+ for (; a; a--)
+ for (; c >= 0; c++);
+ if (!c)
+ b = 1;
+}
+
+int
+main ()
+{
+ foo ();
+ if (b != 0)
+ __builtin_abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/constexpr-array7.C b/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/constexpr-array7.C
new file mode 100644
index 0000000..8f74675
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/constexpr-array7.C
@@ -0,0 +1,13 @@
+// PR c++/61994
+// { dg-do compile { target c++11 } }
+
+struct A { int i,j; };
+
+struct X {
+ A a = {1,1};
+};
+
+constexpr X table[1][1] = {{ {} }};
+
+#define SA(X) static_assert(X,#X)
+SA(table[0][0].a.i == 1);
diff --git a/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/constexpr-empty7.C b/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/constexpr-empty7.C
new file mode 100644
index 0000000..f491994
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/constexpr-empty7.C
@@ -0,0 +1,28 @@
+// PR c++/61959
+// { dg-do compile { target c++11 } }
+
+template <class Coord> struct BasePoint
+{
+ Coord x, y;
+ constexpr BasePoint (Coord, Coord) : x (0), y (0) {}
+};
+template <class T> struct BaseCoord
+{
+ int value;
+ constexpr BaseCoord (T) : value (1) {}
+};
+template <class units> struct IntCoordTyped : BaseCoord<int>, units
+{
+ typedef BaseCoord Super;
+ constexpr IntCoordTyped (int) : Super (0) {}
+};
+template <class units>
+struct IntPointTyped : BasePoint<IntCoordTyped<units> >, units
+{
+ typedef BasePoint<IntCoordTyped<units> > Super;
+ constexpr IntPointTyped (int, int) : Super (0, 0) {}
+};
+struct A
+{
+};
+IntPointTyped<A> a (0, 0);
diff --git a/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/constexpr-ptrmem3.C b/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/constexpr-ptrmem3.C
new file mode 100644
index 0000000..c5e2101
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/constexpr-ptrmem3.C
@@ -0,0 +1,16 @@
+// PR c++/62129
+// { dg-do compile { target c++11 } }
+
+class Evaluator
+{
+ int MakeChangelist ();
+ typedef int (Evaluator::*fac_t)();
+ struct CreatorEntry
+ {
+ const char *type;
+ fac_t factory;
+ };
+ static constexpr CreatorEntry kCreators[] = { "", &Evaluator::MakeChangelist };
+};
+
+constexpr Evaluator::CreatorEntry Evaluator::kCreators[];
diff --git a/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/initlist-array4.C b/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/initlist-array4.C
new file mode 100644
index 0000000..af2045d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/initlist-array4.C
@@ -0,0 +1,9 @@
+// PR c++/58636
+// { dg-do compile { target c++11 } }
+
+#include <initializer_list>
+
+// { dg-error "pointer to reference" "" { target *-*-* } 0 }
+int foo(std::initializer_list<int&&>);
+
+int i = foo({ 0 }); // { dg-error "std::initializer_list" }
diff --git a/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-template13.C b/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-template13.C
index adbb4db..79ab410 100644
--- a/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-template13.C
+++ b/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-template13.C
@@ -1,5 +1,6 @@
// PR c++/61566
// { dg-do compile { target c++11 } }
+// { dg-options "-fabi-version=0" }
struct function
{
@@ -7,6 +8,7 @@ struct function
function (_Functor);
};
+template <class U>
struct C
{
template <typename T>
@@ -15,6 +17,9 @@ struct C
void bar ()
{
- C c;
+ C<int> c;
c.foo (1);
}
+
+// { dg-final { scan-assembler "_ZN8functionC1IZN1CIiE3fooIiEEvT_S_Ed_UlvE_EET_" } }
+// { dg-final { scan-assembler-not "_ZZN1CIiE3fooIiEEvT_8functionEd_NKUlvE_clEv" } }
diff --git a/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/rv-cond1.C b/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/rv-cond1.C
new file mode 100644
index 0000000..a8f598f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/g++.dg/cpp0x/rv-cond1.C
@@ -0,0 +1,13 @@
+// PR c++/58714
+// { dg-do compile { target c++11 } }
+
+struct X {
+ X& operator=(const X&) = delete;
+ X& operator=(X&& ) = default;
+};
+
+void f(bool t) {
+ X a, b;
+ *(t ? &a : &b) = X();
+ (t ? a : b) = X();
+}
diff --git a/gcc-4.9/gcc/testsuite/g++.dg/expr/cond12.C b/gcc-4.9/gcc/testsuite/g++.dg/expr/cond12.C
new file mode 100644
index 0000000..9134f81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/g++.dg/expr/cond12.C
@@ -0,0 +1,12 @@
+// PR c++/58714
+// { dg-do run }
+
+struct X {
+ X& operator=(const X&){}
+ X& operator=(X&){__builtin_abort();}
+};
+
+int main(int argv,char**) {
+ X a, b;
+ ((argv > 2) ? a : b) = X();
+}
diff --git a/gcc-4.9/gcc/testsuite/g++.dg/ext/restrict2.C b/gcc-4.9/gcc/testsuite/g++.dg/ext/restrict2.C
new file mode 100644
index 0000000..f053210
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/g++.dg/ext/restrict2.C
@@ -0,0 +1,8 @@
+// PR c++/60872
+// { dg-options "" }
+
+typedef double *__restrict T;
+void f(T* p)
+{
+ void *p2 = p;
+}
diff --git a/gcc-4.9/gcc/testsuite/g++.dg/init/explicit2.C b/gcc-4.9/gcc/testsuite/g++.dg/init/explicit2.C
new file mode 100644
index 0000000..d1dbb39
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/g++.dg/init/explicit2.C
@@ -0,0 +1,8 @@
+// PR c++/60417
+
+struct A { explicit A(int = 0); };
+
+int main()
+{
+ A a[1] = { };
+}
diff --git a/gcc-4.9/gcc/testsuite/g++.dg/ipa/devirt-39.C b/gcc-4.9/gcc/testsuite/g++.dg/ipa/devirt-39.C
new file mode 100644
index 0000000..fbeea12
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/g++.dg/ipa/devirt-39.C
@@ -0,0 +1,28 @@
+// PR c++/61214
+/* { dg-options "-O2 -fdump-tree-optimized" } */
+
+struct Base
+{
+ virtual ~Base();
+ virtual Base* clone() {
+ return 0;
+ }
+};
+
+struct Foo : Base
+{
+ virtual ~Foo();
+ virtual Base* clone() {
+ return new Foo();
+ }
+};
+
+int main()
+{
+ Base* f = new Foo();
+ f->clone();
+ return 0;
+}
+
+/* { dg-final { scan-tree-dump-not "OBJ_TYPE_REF" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.9/gcc/testsuite/g++.dg/opt/pr62146.C b/gcc-4.9/gcc/testsuite/g++.dg/opt/pr62146.C
new file mode 100644
index 0000000..dbe4174
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/g++.dg/opt/pr62146.C
@@ -0,0 +1,51 @@
+/* PR rtl-optimization/62146 */
+/* { dg-do compile } */
+/* { dg-options "-O2 " } */
+class F
+{
+public:
+ virtual ~ F ();
+};
+template < class CL > class G:public F
+{
+ int *member_;
+public:
+ G ( int *b): member_ (0)
+ {
+ }
+};
+
+class D
+{
+public:
+ template < class CL > void RegisterNonTagCallback (int,
+ void (CL::
+ *p3) ())
+ {
+ InternalRegisterNonTag (p3 ? new G < CL > ( 0) : 0);
+ } void InternalRegisterNonTag (F *);
+};
+
+void fn1 ();
+class C1
+{
+ void foo();
+ class TokenType
+ {
+ public:
+ void AddToken ()
+ {
+ }
+ };
+ C1::TokenType bar_t;
+};
+D a;
+void C1::foo()
+{
+ if (&bar_t)
+ fn1 ();
+ for (int i = 0; i < sizeof 0; ++i)
+ a.RegisterNonTagCallback (0, &TokenType::AddToken);
+}
+
+/* { dg-final { scan-assembler-not "mov.*_ZN2C19TokenType8AddTokenEv, .\\\(" } } */
diff --git a/gcc-4.9/gcc/testsuite/g++.dg/tls/thread_local10.C b/gcc-4.9/gcc/testsuite/g++.dg/tls/thread_local10.C
new file mode 100644
index 0000000..48c1b86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/g++.dg/tls/thread_local10.C
@@ -0,0 +1,23 @@
+// PR c++/58624
+
+// { dg-do run { target c++11 } }
+// { dg-add-options tls }
+// { dg-require-effective-target tls_runtime }
+
+int i;
+
+template <typename> struct A
+{
+ static thread_local int s;
+
+ A () { i = s; }
+};
+
+int f() { return 42; }
+template <typename T> thread_local int A<T>::s = f();
+
+int main () {
+ A<void> a;
+ if (i != 42)
+ __builtin_abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.c-torture/compile/pr60655-1.c b/gcc-4.9/gcc/testsuite/gcc.c-torture/compile/pr60655-1.c
index 6f84f6e..1e1e460 100644
--- a/gcc-4.9/gcc/testsuite/gcc.c-torture/compile/pr60655-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.c-torture/compile/pr60655-1.c
@@ -1,4 +1,4 @@
-/* { dg-options "-fdata-sections" } */
+/* { dg-options "-fdata-sections" { target { ! { { hppa*-*-hpux* } && { ! lp64 } } } } } */
typedef unsigned char unit;
typedef unit *unitptr;
diff --git a/gcc-4.9/gcc/testsuite/gcc.c-torture/execute/20050316-3.x b/gcc-4.9/gcc/testsuite/gcc.c-torture/execute/20050316-3.x
new file mode 100644
index 0000000..cb7b119
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.c-torture/execute/20050316-3.x
@@ -0,0 +1,2 @@
+set additional_flags "-Wno-psabi"
+return 0
diff --git a/gcc-4.9/gcc/testsuite/gcc.c-torture/execute/bitfld-6.c b/gcc-4.9/gcc/testsuite/gcc.c-torture/execute/bitfld-6.c
new file mode 100644
index 0000000..50927dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.c-torture/execute/bitfld-6.c
@@ -0,0 +1,23 @@
+union U
+{
+ const int a;
+ unsigned b : 20;
+};
+
+static union U u = { 0x12345678 };
+
+/* Constant folding used to fail to account for endianness when folding a
+ union. */
+
+int
+main (void)
+{
+#ifdef __BYTE_ORDER__
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+ return u.b - 0x45678;
+#else
+ return u.b - 0x12345;
+#endif
+#endif
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.c-torture/execute/pr23135.x b/gcc-4.9/gcc/testsuite/gcc.c-torture/execute/pr23135.x
new file mode 100644
index 0000000..cb7b119
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.c-torture/execute/pr23135.x
@@ -0,0 +1,2 @@
+set additional_flags "-Wno-psabi"
+return 0
diff --git a/gcc-4.9/gcc/testsuite/gcc.c-torture/execute/pr61375.c b/gcc-4.9/gcc/testsuite/gcc.c-torture/execute/pr61375.c
new file mode 100644
index 0000000..6fb4693
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.c-torture/execute/pr61375.c
@@ -0,0 +1,35 @@
+#ifdef __UINT64_TYPE__
+typedef __UINT64_TYPE__ uint64_t;
+#else
+typedef unsigned long long uint64_t;
+#endif
+
+#ifndef __SIZEOF_INT128__
+#define __int128 long long
+#endif
+
+/* Some version of bswap optimization would ICE when analyzing a mask constant
+ too big for an HOST_WIDE_INT (PR61375). */
+
+__attribute__ ((noinline, noclone)) uint64_t
+uint128_central_bitsi_ior (unsigned __int128 in1, uint64_t in2)
+{
+ __int128 mask = (__int128)0xffff << 56;
+ return ((in1 & mask) >> 56) | in2;
+}
+
+int
+main (int argc)
+{
+ __int128 in = 1;
+#ifdef __SIZEOF_INT128__
+ in <<= 64;
+#endif
+ if (sizeof (uint64_t) * __CHAR_BIT__ != 64)
+ return 0;
+ if (sizeof (unsigned __int128) * __CHAR_BIT__ != 128)
+ return 0;
+ if (uint128_central_bitsi_ior (in, 2) != 0x102)
+ __builtin_abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-4.c b/gcc-4.9/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-4.c
index 1558200..b03d2c8 100644
--- a/gcc-4.9/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-4.c
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-4.c
@@ -2,7 +2,7 @@
operating properly when operations on the same variable are carried
out in two threads. */
/* { dg-do run } */
-/* { dg-options "-std=c11 -pedantic-errors -pthread -D_POSIX_C_SOURCE=200809L" } */
+/* { dg-options "-std=c11 -pedantic-errors -pthread -U_POSIX_C_SOURCE -D_POSIX_C_SOURCE=200809L" } */
/* { dg-additional-options "-D_XOPEN_SOURCE=600" { target *-*-solaris2.1[0-9]* } }
/* { dg-require-effective-target pthread } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-5.c b/gcc-4.9/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-5.c
index bc87de4..e3e0aae 100644
--- a/gcc-4.9/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-5.c
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/atomic/c11-atomic-exec-5.c
@@ -3,7 +3,7 @@
iterations of the compare-and-exchange loop are needed, exceptions
get properly cleared). */
/* { dg-do run } */
-/* { dg-options "-std=c11 -pedantic-errors -pthread -D_POSIX_C_SOURCE=200809L" } */
+/* { dg-options "-std=c11 -pedantic-errors -pthread -U_POSIX_C_SOURCE -D_POSIX_C_SOURCE=200809L" } */
/* { dg-additional-options "-D_XOPEN_SOURCE=600" { target *-*-solaris2.1[0-9]* } }
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-require-effective-target pthread } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/atomic/stdatomic-flag.c b/gcc-4.9/gcc/testsuite/gcc.dg/atomic/stdatomic-flag.c
index c1a63f1..515d5d8 100644
--- a/gcc-4.9/gcc/testsuite/gcc.dg/atomic/stdatomic-flag.c
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/atomic/stdatomic-flag.c
@@ -1,4 +1,5 @@
/* Test atomic_flag routines for existence and execution. */
+/* The test needs a lockless atomic implementation. */
/* { dg-do run { xfail hppa*-*-hpux* } } */
/* { dg-options "-std=c11 -pedantic-errors" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/lto/pr60449_0.c b/gcc-4.9/gcc/testsuite/gcc.dg/lto/pr60449_0.c
new file mode 100644
index 0000000..a430830
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/lto/pr60449_0.c
@@ -0,0 +1,30 @@
+/* { dg-lto-do link } */
+
+extern int printf (const char *__restrict __format, ...);
+typedef long int __time_t;
+typedef long int __suseconds_t;
+
+struct timeval
+ {
+ __time_t tv_sec;
+ __suseconds_t tv_usec;
+ };
+
+struct timezone
+ {
+ int tz_minuteswest;
+ int tz_dsttime;
+ };
+typedef struct timezone *__restrict __timezone_ptr_t;
+
+extern int gettimeofday (struct timeval *__restrict __tv, __timezone_ptr_t __tz);
+
+int bar (void)
+{
+ struct timeval tv;
+ struct timezone tz;
+
+ gettimeofday (&tv, &tz);
+ printf ("This is from bar %i\n", tz.tz_dsttime);
+ return 5;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/lto/pr60449_1.c b/gcc-4.9/gcc/testsuite/gcc.dg/lto/pr60449_1.c
new file mode 100644
index 0000000..ddc2529
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/lto/pr60449_1.c
@@ -0,0 +1,76 @@
+extern int printf (const char *__restrict __format, ...);
+typedef long int __time_t;
+typedef long int __suseconds_t;
+struct timeval
+ {
+ __time_t tv_sec;
+ __suseconds_t tv_usec;
+ };
+struct timezone
+ {
+ int tz_minuteswest;
+ int tz_dsttime;
+ };
+typedef struct timezone *__restrict __timezone_ptr_t;
+extern int gettimeofday (struct timeval *__restrict __tv,
+ __timezone_ptr_t __tz) __attribute__ ((__nothrow__ , __leaf__)) __attribute__ ((__nonnull__ (1)));
+
+typedef long int __jmp_buf[8];
+typedef struct
+ {
+ unsigned long int __val[(1024 / (8 * sizeof (unsigned long int)))];
+ } __sigset_t;
+struct __jmp_buf_tag
+ {
+ __jmp_buf __jmpbuf;
+ int __mask_was_saved;
+ __sigset_t __saved_mask;
+ };
+typedef struct __jmp_buf_tag jmp_buf[1];
+
+extern int setjmp (jmp_buf __env) __attribute__ ((__nothrow__));
+extern void longjmp (struct __jmp_buf_tag __env[1], int __val)
+ __attribute__ ((__nothrow__)) __attribute__ ((__noreturn__));
+
+extern int bar (void);
+
+int __attribute__ ((noinline, noclone))
+get_input (void)
+{
+ return 0;
+}
+
+static jmp_buf buf;
+
+int foo (void)
+{
+ if (get_input ())
+ longjmp(buf, 1);
+ return 0;
+}
+
+volatile int z;
+
+
+int main (void)
+{
+ struct timeval tv;
+ struct timezone tz;
+
+ bar();
+ if (setjmp (buf))
+ return 1;
+
+ if (!get_input ())
+ {
+ gettimeofday (&tv, &tz);
+ z = 0;
+ printf ("This is from main %i\n", tz.tz_dsttime);
+ }
+
+ foo ();
+ bar ();
+ bar ();
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/pr51879-18.c b/gcc-4.9/gcc/testsuite/gcc.dg/pr51879-18.c
index 95629f1..9b3cb80 100644
--- a/gcc-4.9/gcc/testsuite/gcc.dg/pr51879-18.c
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/pr51879-18.c
@@ -13,5 +13,5 @@ void bar (int c, int *p)
*q = foo ();
}
-/* { dg-final { scan-tree-dump-times "foo \\(" 1 "pre"} } */
+/* { dg-final { scan-tree-dump-times "foo \\(" 1 "pre" { xfail *-*-* } } } */
/* { dg-final { cleanup-tree-dump "pre" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/pr57233.c b/gcc-4.9/gcc/testsuite/gcc.dg/pr57233.c
index 58c0534..484844e 100644
--- a/gcc-4.9/gcc/testsuite/gcc.dg/pr57233.c
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/pr57233.c
@@ -1,6 +1,7 @@
/* PR tree-optimization/57233 */
/* { dg-do run { target { ilp32 || lp64 } } } */
/* { dg-options "-O2" } */
+/* { dg-additional-options "-fno-common" { target hppa*-*-hpux* } } */
typedef unsigned V4 __attribute__((vector_size(4 * sizeof (int))));
typedef unsigned V8 __attribute__((vector_size(8 * sizeof (int))));
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/pr59418.c b/gcc-4.9/gcc/testsuite/gcc.dg/pr59418.c
index 114c1d3..257ce79 100644
--- a/gcc-4.9/gcc/testsuite/gcc.dg/pr59418.c
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/pr59418.c
@@ -3,7 +3,7 @@
/* { dg-do compile } */
/* { dg-options "-Os -g" } */
-/* { dg-options "-march=armv7-a -mfloat-abi=hard -Os -g" { target arm*-*-* } } */
+/* { dg-options "-march=armv7-a -mfloat-abi=hard -Os -g" { target { arm*-*-* && { ! arm_thumb1 } } } } */
extern int printf (const char *__format, ...);
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/pr61756.c b/gcc-4.9/gcc/testsuite/gcc.dg/pr61756.c
new file mode 100644
index 0000000..4ca9044
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/pr61756.c
@@ -0,0 +1,14 @@
+/* PR target/61756 */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include <stdatomic.h>
+
+static volatile atomic_flag guard = ATOMIC_FLAG_INIT;
+
+void
+try_atomic_flag_test_and_set (void)
+{
+ atomic_flag_test_and_set (&guard);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/pr61776.c b/gcc-4.9/gcc/testsuite/gcc.dg/pr61776.c
new file mode 100644
index 0000000..8768c54
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/pr61776.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fprofile-generate" } */
+
+#include <setjmp.h>
+
+int cond1, cond2;
+
+int goo() __attribute__((noinline));
+
+int goo() {
+ if (cond1)
+ return 1;
+ else
+ return 2;
+}
+
+jmp_buf env;
+int foo() {
+ int a;
+
+ setjmp(env);
+ if (cond2)
+ a = goo();
+ else
+ a = 3;
+ return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/pr62004.c b/gcc-4.9/gcc/testsuite/gcc.dg/pr62004.c
new file mode 100644
index 0000000..c994a41
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/pr62004.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-tree-tail-merge" } */
+
+struct node
+{
+ struct node *next;
+ struct node *prev;
+};
+
+struct node node;
+
+struct head
+{
+ struct node *first;
+};
+
+struct head heads[5];
+
+int k = 2;
+
+struct head *head = &heads[2];
+
+int
+main ()
+{
+ struct node *p;
+
+ node.next = (void*)0;
+
+ node.prev = (void *)head;
+
+ head->first = &node;
+
+ struct node *n = head->first;
+
+ struct head *h = &heads[k];
+
+ heads[2].first = n->next;
+
+ if ((void*)n->prev == (void *)h)
+ p = h->first;
+ else
+ /* Dead tbaa-unsafe load from ((struct node *)&heads[2])->next. */
+ p = n->prev->next;
+
+ return !(p == (void*)0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/pr62030.c b/gcc-4.9/gcc/testsuite/gcc.dg/pr62030.c
new file mode 100644
index 0000000..b8baf93
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/pr62030.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+struct node
+{
+ struct node *next;
+ struct node *prev;
+};
+
+struct node node;
+
+struct head
+{
+ struct node *first;
+};
+
+struct head heads[5];
+
+int k = 2;
+
+struct head *head = &heads[2];
+
+static int __attribute__((noinline))
+foo (void)
+{
+ node.prev = (void *)head;
+ head->first = &node;
+
+ struct node *n = head->first;
+ struct head *h = &heads[k];
+ struct node *next = n->next;
+
+ if (n->prev == (void *)h)
+ h->first = next;
+ else
+ n->prev->next = next;
+
+ n->next = h->first;
+ return n->next == &node;
+}
+
+int
+main (void)
+{
+ if (foo ())
+ abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/torture/pr61964.c b/gcc-4.9/gcc/testsuite/gcc.dg/torture/pr61964.c
new file mode 100644
index 0000000..a03cfdc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/torture/pr61964.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+
+extern void abort (void);
+
+struct node { struct node *next, *prev; } node;
+struct head { struct node *first; } heads[5];
+int k = 2;
+struct head *head = &heads[2];
+
+static int __attribute__((noinline))
+foo()
+{
+ node.prev = (void *)head;
+ head->first = &node;
+
+ struct node *n = head->first;
+ struct head *h = &heads[k];
+
+ if (n->prev == (void *)h)
+ h->first = n->next;
+ else
+ n->prev->next = n->next;
+
+ n->next = h->first;
+ return n->next == &node;
+}
+
+int main()
+{
+ if (foo ())
+ abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/tree-ssa/ssa-copyprop-2.c b/gcc-4.9/gcc/testsuite/gcc.dg/tree-ssa/ssa-copyprop-2.c
new file mode 100644
index 0000000..9757013
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/tree-ssa/ssa-copyprop-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-Og -fdump-tree-optimized" } */
+
+extern long long __sdt_unsp;
+void
+f(void)
+{
+ for (;;)
+ __asm__ ("%0" :: "i" (((!__extension__ (__builtin_constant_p ((((unsigned long long) (__typeof (__builtin_choose_expr (((__builtin_classify_type (0) + 3) & -4) == 4, (0), 0U))) __sdt_unsp) ) == 0) )) ? 1 : -1) ));
+}
+
+/* { dg-final { scan-tree-dump-not "PHI" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/vect/pr62073.c b/gcc-4.9/gcc/testsuite/gcc.dg/vect/pr62073.c
new file mode 100644
index 0000000..15f2ad6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/vect/pr62073.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O1" } */
+
+struct S0
+{
+ int f7;
+};
+struct S0 g_50;
+int g_70;
+int g_76;
+
+int foo (long long p_56, int * p_57)
+{
+ int *l_77;
+ int l_101;
+
+ for (; g_70;)
+ {
+ int **l_78 = &l_77;
+ if (g_50.f7)
+ continue;
+ *l_78 = 0;
+ }
+ for (g_76 = 1; g_76 >= 0; g_76--)
+ {
+ int *l_90;
+ for (l_101 = 4; l_101 >= 0; l_101--)
+ if (l_101)
+ *l_90 = 0;
+ else
+ {
+ int **l_113 = &l_77;
+ *l_113 = p_57;
+ }
+ }
+
+ return *l_77;
+}
+
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/frame-pointer-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/frame-pointer-1.c
index bb1888e..c288fef 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/arm/frame-pointer-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/frame-pointer-1.c
@@ -1,6 +1,7 @@
/* Check local register variables using a register conventionally
used as the frame pointer aren't clobbered under high register pressure. */
/* { dg-do run } */
+/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } { "*" } { "" } } */
/* { dg-options "-Os -mthumb -fomit-frame-pointer" } */
#include <stdlib.h>
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext-execute.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext-execute.c
index 3d6c28c..8e44d9a 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext-execute.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext-execute.c
@@ -1,5 +1,6 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-require-effective-target arm_neon_hw } */
/* { dg-require-effective-target arm_little_endian } */
/* { dg-options "-O2" } */
/* { dg-add-options arm_neon } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56184.C b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56184.C
index d44c1b4..5d23c40 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56184.C
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56184.C
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } { "*" } { "" } } */
/* { dg-options "-fno-short-enums -O2 -mthumb -march=armv7-a -mfpu=neon -mfloat-abi=softfp -mtune=cortex-a9 -fno-section-anchors" } */
typedef unsigned int size_t;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58784.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58784.c
index e3ef950..9a1fcff 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58784.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58784.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-skip-if "incompatible options" { arm_thumb1 } { "*" } { "" } } */
/* { dg-options "-march=armv7-a -mfloat-abi=hard -mfpu=neon -marm -O2" } */
typedef struct __attribute__ ((__packed__))
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59896.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59896.c
index 5896e73..ea6dc24 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59896.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59896.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } { "*" } { "" } } */
/* { dg-options "-mthumb -O2" } */
typedef unsigned int size_t;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59985.C b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59985.C
index cc688a9..1351c48 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59985.C
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59985.C
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-skip-if "incompatible options" { arm_thumb1 } { "*" } { "" } } */
/* { dg-options "-g -fcompare-debug -O2 -march=armv7-a -mtune=cortex-a9 -mfpu=vfpv3-d16 -mfloat-abi=hard" } */
extern void *f1 (unsigned long, unsigned long);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-red-zone.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-red-zone.c
index b9f0f99..8db2e2c 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-red-zone.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-red-zone.c
@@ -1,4 +1,5 @@
/* No stack red zone. PR38644. */
+/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } { "*" } { "" } } */
/* { dg-options "-mthumb -O2" } */
/* { dg-final { scan-assembler "ldrb\[^\n\]*\\n\[\t \]*add\[\t \]*sp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c
index f2c0225..e67a627 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c
@@ -1,5 +1,6 @@
/* Wrong method to get number of arg reg will cause argument corruption. */
/* { dg-do run } */
+/* { dg-skip-if "incompatible options" { ! { arm_thumb1_ok || arm_thumb2_ok } } { "*" } { "" } } */
/* { dg-require-effective-target arm_eabi } */
/* { dg-options "-mthumb -O1" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmpd-2.c
index d4ddd32..995b446 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmpd-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmpd-2.c
@@ -10,7 +10,8 @@
#define SIZE (AVX512F_LEN / 64)
#include "avx512f-mask-type.h"
#include "math.h"
-#include "values.h"
+#include "float.h"
+
static void
CALC (double *r, double src, long long tbl)
@@ -60,10 +61,10 @@ CALC (double *r, double src, long long tbl)
*r = M_PI_2;
break;
case 14:
- *r = MAXDOUBLE;
+ *r = DBL_MAX;
break;
case 15:
- *r = -MAXDOUBLE;
+ *r = -DBL_MAX;
break;
default:
abort ();
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmps-2.c
index 6c2539d..edb149c 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmps-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmps-2.c
@@ -10,7 +10,7 @@
#define SIZE (AVX512F_LEN / 32)
#include "avx512f-mask-type.h"
#include "math.h"
-#include "values.h"
+#include "float.h"
static void
CALC (float *r, float src, int tbl)
@@ -60,10 +60,10 @@ CALC (float *r, float src, int tbl)
*r = M_PI_2;
break;
case 14:
- *r = MAXFLOAT;
+ *r = FLT_MAX;
break;
case 15:
- *r = -MAXFLOAT;
+ *r = -FLT_MAX;
break;
default:
abort ();
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmsd-2.c
index 1344c7f..1b66a98 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmsd-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmsd-2.c
@@ -6,7 +6,7 @@
#include "avx512f-check.h"
#include "avx512f-helper.h"
#include <math.h>
-#include <values.h>
+#include <float.h>
#include "avx512f-mask-type.h"
void
@@ -57,10 +57,10 @@ compute_fixupimmpd (double *r, double src, long long tbl)
*r = M_PI_2;
break;
case 14:
- *r = MAXDOUBLE;
+ *r = DBL_MAX;
break;
case 15:
- *r = -MAXDOUBLE;
+ *r = -DBL_MAX;
break;
default:
abort ();
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmss-2.c
index 25e165f..87883ba 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmss-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmss-2.c
@@ -6,7 +6,7 @@
#include "avx512f-check.h"
#include "avx512f-helper.h"
#include <math.h>
-#include <values.h>
+#include <float.h>
#include "avx512f-mask-type.h"
void
@@ -57,10 +57,10 @@ compute_fixupimmps (float *r, float src, int tbl)
*r = M_PI_2;
break;
case 14:
- *r = MAXFLOAT;
+ *r = FLT_MAX;
break;
case 15:
- *r = -MAXFLOAT;
+ *r = -FLT_MAX;
break;
default:
abort ();
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2d-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2d-2.c
index 9aa104b..6205cc5 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2d-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2d-2.c
@@ -9,7 +9,6 @@
#define SIZE (AVX512F_LEN / 32)
#include "avx512f-mask-type.h"
#include "math.h"
-#include "values.h"
static void
CALC (int *dst, int *src1, int *ind, int *src2)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2pd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2pd-2.c
index a2daca0..0bb5b4c 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2pd-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2pd-2.c
@@ -9,7 +9,6 @@
#define SIZE (AVX512F_LEN / 64)
#include "avx512f-mask-type.h"
#include "math.h"
-#include "values.h"
static void
CALC (double *dst, double *src1, long long *ind, double *src2)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2ps-2.c
index 56215cf..f8038ef 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2ps-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2ps-2.c
@@ -9,7 +9,6 @@
#define SIZE (AVX512F_LEN / 32)
#include "avx512f-mask-type.h"
#include "math.h"
-#include "values.h"
static void
CALC (float *dst, float *src1, int *ind, float *src2)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2q-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2q-2.c
index 9d7b9be..0268afb 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2q-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2q-2.c
@@ -9,7 +9,6 @@
#define SIZE (AVX512F_LEN / 64)
#include "avx512f-mask-type.h"
#include "math.h"
-#include "values.h"
static void
CALC (long long *dst, long long *src1, long long *ind, long long *src2)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2d-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2d-2.c
index ef8d195..bba108a 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2d-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2d-2.c
@@ -9,7 +9,6 @@
#define SIZE (AVX512F_LEN / 32)
#include "avx512f-mask-type.h"
#include "math.h"
-#include "values.h"
static void
CALC (int *dst, int *src1, int *ind, int *src2)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2pd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2pd-2.c
index 511a470..4891c85 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2pd-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2pd-2.c
@@ -9,7 +9,6 @@
#define SIZE (AVX512F_LEN / 64)
#include "avx512f-mask-type.h"
#include "math.h"
-#include "values.h"
static void
CALC (double *dst, double *src1, long long *ind, double *src2)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2ps-2.c
index cd35d12..a3d57c4 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2ps-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2ps-2.c
@@ -9,7 +9,6 @@
#define SIZE (AVX512F_LEN / 32)
#include "avx512f-mask-type.h"
#include "math.h"
-#include "values.h"
static void
CALC (float *dst, float *src1, int *ind, float *src2)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2q-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2q-2.c
index 5f449ad..57fe3d4 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2q-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2q-2.c
@@ -9,7 +9,6 @@
#define SIZE (AVX512F_LEN / 64)
#include "avx512f-mask-type.h"
#include "math.h"
-#include "values.h"
static void
CALC (long long *dst, long long *src1, long long *ind, long long *src2)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61794.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61794.c
new file mode 100644
index 0000000..5f8e7d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61794.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f" } */
+
+#include <x86intrin.h>
+
+__m512i zmm;
+__m128i xmm;
+
+void test (void)
+{
+ xmm = _mm512_extracti32x4_epi32 (zmm, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61801.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61801.c
new file mode 100644
index 0000000..d0d08cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61801.c
@@ -0,0 +1,21 @@
+/* PR rtl-optimization/61801 */
+/* { dg-do compile } */
+/* { dg-options "-Os -fcompare-debug" } */
+
+int a, c;
+int bar (void);
+void baz (void);
+
+void
+foo (void)
+{
+ int d;
+ if (bar ())
+ {
+ int e;
+ baz ();
+ asm volatile ("" : "=a" (e) : "0" (a), "i" (0));
+ d = e;
+ }
+ c = d;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61855.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61855.c
new file mode 100644
index 0000000..09c62ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61855.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f" } */
+
+#include <x86intrin.h>
+
+__m512 test (__m512 x)
+{
+ return _mm512_getmant_ps(x, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_zero);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61923.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61923.c
new file mode 100644
index 0000000..458158c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr61923.c
@@ -0,0 +1,36 @@
+/* PR debug/61923 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fcompare-debug" } */
+
+typedef struct
+{
+ struct
+ {
+ struct
+ {
+ char head;
+ } tickets;
+ };
+} arch_spinlock_t;
+struct ext4_map_blocks
+{
+ int m_lblk;
+ int m_len;
+ int m_flags;
+};
+int ext4_da_map_blocks_ei_0;
+void fn1 (int p1, struct ext4_map_blocks *p2)
+{
+ int ret;
+ if (p2->m_flags)
+ {
+ ext4_da_map_blocks_ei_0++;
+ arch_spinlock_t *lock;
+ switch (sizeof *&lock->tickets.head)
+ case 1:
+ asm("" : "+m"(*&lock->tickets.head) : ""(0));
+ __asm__("");
+ ret = 0;
+ }
+ fn2 (p2->m_lblk, p2->m_len);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c
index 382677e..97ef393 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c
@@ -33,4 +33,3 @@ int main ()
/* { dg-final { scan-assembler "vpmulld" } } */
/* { dg-final { scan-assembler "vphadddq" } } */
-/* { dg-final { scan-assembler "vpmacsdql" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr62030-octeon.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr62030-octeon.c
new file mode 100644
index 0000000..5e3d3b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr62030-octeon.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-options "-march=octeon" } */
+
+extern void abort (void);
+
+struct node
+{
+ struct node *next;
+ struct node *prev;
+};
+
+struct node node;
+
+struct head
+{
+ struct node *first;
+};
+
+struct head heads[5];
+
+int k = 2;
+
+struct head *head = &heads[2];
+
+static int __attribute__((noinline))
+foo (void)
+{
+ node.prev = (void *)head;
+ head->first = &node;
+
+ struct node *n = head->first;
+ struct head *h = &heads[k];
+ struct node *next = n->next;
+
+ if (n->prev == (void *)h)
+ h->first = next;
+ else
+ n->prev->next = next;
+
+ n->next = h->first;
+ return n->next == &node;
+}
+
+int
+main (void)
+{
+ if (foo ())
+ abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-warn-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-warn-1.c
new file mode 100644
index 0000000..6e0d548
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-warn-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-options "-mabi=elfv2" } */
+
+struct f8
+ {
+ float x[8];
+ };
+
+void test (struct f8 a, struct f8 b) /* { dg-message "note: the ABI of passing homogeneous float aggregates will change" } */
+{
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-warn-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-warn-2.c
new file mode 100644
index 0000000..c4820e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-warn-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+
+struct test
+ {
+ long a __attribute__((aligned (16)));
+ };
+
+void test (struct test a) /* { dg-message "note: the ABI of passing aggregates with 16-byte alignment will change" } */
+{
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-warn-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-warn-3.c
new file mode 100644
index 0000000..830de6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-warn-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+struct test
+ {
+ int a __attribute__((vector_size (8)));
+ }; /* { dg-message "note: the layout of aggregates containing vectors with 8-byte alignment will change" } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60102.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60102.c
new file mode 100644
index 0000000..d32e41d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60102.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+/* { dg-options "-mcpu=8548 -mspe -mabi=spe -g -mfloat-gprs=double" } */
+
+double
+pr60102 (double x, int m)
+{
+ double y;
+ y = m % 2 ? x : 1;
+ return y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr61996.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr61996.c
new file mode 100644
index 0000000..51a5f92
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr61996.c
@@ -0,0 +1,12 @@
+/* Check that the option -musermode has no effect on targets that do not
+ support user/privileged mode and that it does not interfere with option
+ -matomic-model=soft-imask. */
+/* { dg-do compile } */
+/* { dg-options "-matomic-model=soft-imask" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m1*" "-m2*" } } */
+
+int
+test (void)
+{
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gfortran.dg/array_assignment_5.f90 b/gcc-4.9/gcc/testsuite/gfortran.dg/array_assignment_5.f90
new file mode 100644
index 0000000..6d58527
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gfortran.dg/array_assignment_5.f90
@@ -0,0 +1,16 @@
+! { dg-do run }
+! { dg-options "-ffrontend-optimize" }
+! PR 62214 - this used to give the wrong result.
+! Original test case by Oliver Fuhrer
+PROGRAM test
+ IMPLICIT NONE
+ CHARACTER(LEN=20) :: fullNames(2)
+ CHARACTER(LEN=255) :: pathName
+ CHARACTER(LEN=5) :: fileNames(2)
+
+ pathName = "/dir1/dir2/"
+ fileNames = (/ "file1", "file2" /)
+ fullNames = SPREAD(TRIM(pathName),1,2) // fileNames
+ if (fullNames(1) /= '/dir1/dir2/file1' .or. &
+ & fullnames(2) /= '/dir1/dir2/file2') call abort
+END PROGRAM test
diff --git a/gcc-4.9/gcc/testsuite/gfortran.dg/array_constructor_49.f90 b/gcc-4.9/gcc/testsuite/gfortran.dg/array_constructor_49.f90
new file mode 100644
index 0000000..6a198d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gfortran.dg/array_constructor_49.f90
@@ -0,0 +1,13 @@
+! { dg-do run }
+! { dg-options "-ffrontend-optimize -fdump-tree-original" }
+! PR 62106 - this used to give wrong results because
+! of a bogus extra temporary variable.
+! Original test case by Martien Hulsen
+program t
+ integer :: ndim=2, ndfp=4, i
+ character (len=8) :: line
+ write (unit=line,fmt='(4I2)'), (/ ( i, i = 1, ndfp ) /) + ndim
+ if (line /= ' 3 4 5 6') call abort
+end program t
+! { dg-final { scan-tree-dump-times "__var" 3 "original" } }
+! { dg-final { cleanup-tree-dump "original" } }
diff --git a/gcc-4.9/gcc/testsuite/gfortran.dg/bessel_7.f90 b/gcc-4.9/gcc/testsuite/gfortran.dg/bessel_7.f90
index 7e63ed1..c6b5f74 100644
--- a/gcc-4.9/gcc/testsuite/gfortran.dg/bessel_7.f90
+++ b/gcc-4.9/gcc/testsuite/gfortran.dg/bessel_7.f90
@@ -16,7 +16,7 @@
implicit none
real,parameter :: values(*) = [0.0, 0.5, 1.0, 0.9, 1.8,2.0,3.0,4.0,4.25,8.0,34.53, 475.78]
real,parameter :: myeps(size(values)) = epsilon(0.0) &
- * [2, 3, 4, 5, 8, 2, 12, 6, 7, 6, 36, 168 ]
+ * [2, 3, 4, 5, 8, 2, 13, 6, 7, 6, 36, 168 ]
! The following is sufficient for me - the values above are a bit
! more tolerant
! * [0, 0, 0, 3, 3, 0, 9, 0, 2, 1, 22, 130 ]
diff --git a/gcc-4.9/gcc/testsuite/gfortran.dg/dependency_44.f90 b/gcc-4.9/gcc/testsuite/gfortran.dg/dependency_44.f90
new file mode 100644
index 0000000..ebfeec6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gfortran.dg/dependency_44.f90
@@ -0,0 +1,36 @@
+! { dg-do run }
+! Tests fix for PR61780 in which the loop reversal mechanism was
+! not accounting for the first index being an element so that no
+! loop in this dimension is created.
+!
+! Contributed by Manfred Tietze on clf.
+!
+program prgm3
+ implicit none
+ integer, parameter :: n = 10, k = 3
+ integer :: i, j
+ integer, dimension(n,n) :: y
+ integer :: res1(n), res2(n)
+
+1 format(10i5)
+
+!initialize
+ do i=1,n
+ do j=1,n
+ y(i,j) = n*i + j
+ end do
+ end do
+ res2 = y(k,:)
+
+!shift right
+ y(k,4:n) = y(k,3:n-1)
+ y(k,3) = 0
+ res1 = y(k,:)
+ y(k,:) = res2
+ y(k,n:4:-1) = y(k,n-1:3:-1)
+ y(k,3) = 0
+ res2 = y(k,:)
+! print *, res1
+! print *, res2
+ if (any(res1 /= res2)) call abort ()
+end program prgm3
diff --git a/gcc-4.9/gcc/testsuite/gfortran.dg/dot_product_3.f90 b/gcc-4.9/gcc/testsuite/gfortran.dg/dot_product_3.f90
new file mode 100644
index 0000000..6e11556
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gfortran.dg/dot_product_3.f90
@@ -0,0 +1,15 @@
+! { dg-do compile }
+! { dg-options "-fdump-tree-original" }
+! PR 61999 - this used to ICE.
+! Original test case by A. Kasahara
+program main
+ use, intrinsic:: iso_fortran_env, only: output_unit
+
+ implicit none
+
+ write(output_unit, *) dot_product([1, 2], [2.0, 3.0])
+
+ stop
+end program main
+! { dg-final { scan-tree-dump-times "8\\.0e\\+0" 1 "original" } }
+! { dg-final { cleanup-tree-dump "original" } }
diff --git a/gcc-4.9/gcc/testsuite/gfortran.dg/gomp/pr62131.f90 b/gcc-4.9/gcc/testsuite/gfortran.dg/gomp/pr62131.f90
new file mode 100644
index 0000000..8e88cd7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gfortran.dg/gomp/pr62131.f90
@@ -0,0 +1,19 @@
+! PR fortran/62131
+! { dg-do compile }
+! { dg-options "-fopenmp" }
+
+program pr62131
+ integer,allocatable :: nerrs(:,:)
+ allocate(nerrs(10,10))
+ nerrs(:,:) = 0
+!$omp parallel do
+ do k=1,10
+ call uperrs(k,1)
+ end do
+contains
+ subroutine uperrs(i,io)
+ integer,intent(in) :: i,io
+!$omp atomic
+ nerrs(i,io)=nerrs(i,io)+1
+ end subroutine
+end
diff --git a/gcc-4.9/gcc/testsuite/gfortran.dg/pr45636.f90 b/gcc-4.9/gcc/testsuite/gfortran.dg/pr45636.f90
index ee7cf38..c80dda4 100644
--- a/gcc-4.9/gcc/testsuite/gfortran.dg/pr45636.f90
+++ b/gcc-4.9/gcc/testsuite/gfortran.dg/pr45636.f90
@@ -10,5 +10,5 @@ program main
b = y
call sub(a, b)
end program main
-! { dg-final { scan-tree-dump-times "memset" 0 "forwprop2" { xfail { mips*-*-* && { ! nomips16 } } } } }
+! { dg-final { scan-tree-dump-times "memset" 0 "forwprop2" { xfail { { hppa*-*-* && { ! lp64 } } || { mips*-*-* && { ! nomips16 } } } } } }
! { dg-final { cleanup-tree-dump "forwprop2" } }
diff --git a/gcc-4.9/gcc/testsuite/gfortran.dg/realloc_on_assign_24.f90 b/gcc-4.9/gcc/testsuite/gfortran.dg/realloc_on_assign_24.f90
new file mode 100644
index 0000000..6f88c2b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gfortran.dg/realloc_on_assign_24.f90
@@ -0,0 +1,10 @@
+! { dg-do compile }
+! PR 62142 - this used to segfault
+! Original test case by Ondřej Čertík .
+program test_segfault
+ implicit none
+ real, allocatable :: X(:)
+ allocate (x(1))
+ x = 1.
+ X = floor(X)
+end program
diff --git a/gcc-4.9/gcc/testsuite/gnat.dg/pack20.adb b/gcc-4.9/gcc/testsuite/gnat.dg/pack20.adb
new file mode 100644
index 0000000..5ec3e93
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gnat.dg/pack20.adb
@@ -0,0 +1,9 @@
+package body Pack20 is
+
+ procedure Proc (A : Rec) is
+ Local : Rec := A;
+ begin
+ Modify (Local.Fixed);
+ end;
+
+end Pack20;
diff --git a/gcc-4.9/gcc/testsuite/gnat.dg/pack20.ads b/gcc-4.9/gcc/testsuite/gnat.dg/pack20.ads
new file mode 100644
index 0000000..ddfb9d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gnat.dg/pack20.ads
@@ -0,0 +1,15 @@
+-- { dg-do compile }
+
+with Pack20_Pkg; use Pack20_Pkg;
+
+package Pack20 is
+
+ type Rec is record
+ Simple_Type : Integer;
+ Fixed : String_Ptr;
+ end record;
+ pragma Pack (Rec);
+
+ procedure Proc (A : Rec);
+
+end Pack20;
diff --git a/gcc-4.9/gcc/testsuite/gnat.dg/pack20_pkg.ads b/gcc-4.9/gcc/testsuite/gnat.dg/pack20_pkg.ads
new file mode 100644
index 0000000..8f3c554
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gnat.dg/pack20_pkg.ads
@@ -0,0 +1,7 @@
+package Pack20_Pkg is
+
+ type String_Ptr is access all String;
+
+ procedure Modify (Fixed : in out String_Ptr);
+
+end Pack20_Pkg;
diff --git a/gcc-4.9/gcc/testsuite/lib/target-supports.exp b/gcc-4.9/gcc/testsuite/lib/target-supports.exp
index 902771b..0e226a2 100644
--- a/gcc-4.9/gcc/testsuite/lib/target-supports.exp
+++ b/gcc-4.9/gcc/testsuite/lib/target-supports.exp
@@ -2652,13 +2652,16 @@ proc check_effective_target_arm_v8_neon_ok_nocache { } {
if { [check_effective_target_arm32] } {
foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-fp-armv8" "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} {
if { [check_no_compiler_messages_nocache arm_v8_neon_ok object {
+ #if __ARM_ARCH < 8
+ #error not armv8 or later
+ #endif
#include "arm_neon.h"
void
foo ()
{
__asm__ volatile ("vrintn.f32 q0, q0");
}
- } "$flags"] } {
+ } "$flags -march=armv8-a"] } {
set et_arm_v8_neon_flags $flags
return 1
}
@@ -2835,6 +2838,7 @@ proc check_effective_target_arm_thumb1_ok { } {
#if !defined(__arm__) || !defined(__thumb__) || defined(__thumb2__)
#error FOO
#endif
+ int foo (int i) { return i; }
} "-mthumb"]
}
@@ -2846,6 +2850,7 @@ proc check_effective_target_arm_thumb2_ok { } {
#if !defined(__thumb2__)
#error FOO
#endif
+ int foo (int i) { return i; }
} "-mthumb"]
}
diff --git a/gcc-4.9/gcc/toplev.c b/gcc-4.9/gcc/toplev.c
index 9b8d313..4c8c965 100644
--- a/gcc-4.9/gcc/toplev.c
+++ b/gcc-4.9/gcc/toplev.c
@@ -153,11 +153,6 @@ HOST_WIDE_INT random_seed;
the support provided depends on the backend. */
rtx stack_limit_rtx;
-/* True if the user has tagged the function with the 'section'
- attribute. */
-
-bool user_defined_section_attribute = false;
-
struct target_flag_state default_target_flag_state;
#if SWITCHABLE_TARGET
struct target_flag_state *this_target_flag_state = &default_target_flag_state;
diff --git a/gcc-4.9/gcc/toplev.h b/gcc-4.9/gcc/toplev.h
index 0290be3..65e38e7 100644
--- a/gcc-4.9/gcc/toplev.h
+++ b/gcc-4.9/gcc/toplev.h
@@ -53,11 +53,6 @@ extern void target_reinit (void);
/* A unique local time stamp, might be zero if none is available. */
extern unsigned local_tick;
-/* True if the user has tagged the function with the 'section'
- attribute. */
-
-extern bool user_defined_section_attribute;
-
/* See toplev.c. */
extern int flag_rerun_cse_after_global_opts;
diff --git a/gcc-4.9/gcc/tree-cfg.c b/gcc-4.9/gcc/tree-cfg.c
index d9896e7..29aa8c7 100644
--- a/gcc-4.9/gcc/tree-cfg.c
+++ b/gcc-4.9/gcc/tree-cfg.c
@@ -112,7 +112,14 @@ static struct cfg_stats_d cfg_stats;
struct locus_discrim_map
{
location_t locus;
- int discriminator;
+ /* Different calls belonging to the same source line will be assigned
+ different discriminators. But we want to keep the discriminator of
+ the first call in the same source line to be 0, in order to reduce
+ the .debug_line section size. needs_increment is used for this
+ purpose. It is initialized as false and will be set to true after
+ the first call is seen. */
+ bool needs_increment:1;
+ int discriminator:31;
};
/* Hashtable helpers. */
@@ -164,6 +171,7 @@ static int gimple_verify_flow_info (void);
static void gimple_make_forwarder_block (edge);
static gimple first_non_label_stmt (basic_block);
static bool verify_gimple_transaction (gimple);
+static bool call_can_make_abnormal_goto (gimple);
/* Flowgraph optimization and cleanup. */
static void gimple_merge_blocks (basic_block, basic_block);
@@ -426,6 +434,32 @@ assert_unreachable_fallthru_edge_p (edge e)
}
+/* Initialize GF_CALL_CTRL_ALTERING flag, which indicates the call
+ could alter control flow except via eh. We initialize the flag at
+ CFG build time and only ever clear it later. */
+
+static void
+gimple_call_initialize_ctrl_altering (gimple stmt)
+{
+ int flags = gimple_call_flags (stmt);
+
+ /* A call alters control flow if it can make an abnormal goto. */
+ if (call_can_make_abnormal_goto (stmt)
+ /* A call also alters control flow if it does not return. */
+ || flags & ECF_NORETURN
+ /* TM ending statements have backedges out of the transaction.
+ Return true so we split the basic block containing them.
+ Note that the TM_BUILTIN test is merely an optimization. */
+ || ((flags & ECF_TM_BUILTIN)
+ && is_tm_ending_fndecl (gimple_call_fndecl (stmt)))
+ /* BUILT_IN_RETURN call is same as return statement. */
+ || gimple_call_builtin_p (stmt, BUILT_IN_RETURN))
+ gimple_call_set_ctrl_altering (stmt, true);
+ else
+ gimple_call_set_ctrl_altering (stmt, false);
+}
+
+
/* Build a flowgraph for the sequence of stmts SEQ. */
static void
@@ -444,6 +478,9 @@ make_blocks (gimple_seq seq)
prev_stmt = stmt;
stmt = gsi_stmt (i);
+ if (stmt && is_gimple_call (stmt))
+ gimple_call_initialize_ctrl_altering (stmt);
+
/* If the statement starts a new basic block or if we have determined
in a previous pass that we need to create a new block for STMT, do
so now. */
@@ -914,10 +951,15 @@ make_edges (void)
/* Find the next available discriminator value for LOCUS. The
discriminator distinguishes among several basic blocks that
share a common locus, allowing for more accurate sample-based
- profiling. */
+ profiling. If RETURN_NEXT is true, return the next discriminator
+ anyway. If RETURN_NEXT is not true, we may not increase the
+ discriminator if locus_discrim_map::needs_increment is false,
+ which is used when the stmt is the first call stmt in current
+ source line. locus_discrim_map::needs_increment will be set to
+ true after the first call is seen. */
static int
-next_discriminator_for_locus (location_t locus)
+next_discriminator_for_locus (location_t locus, bool return_next)
{
struct locus_discrim_map item;
struct locus_discrim_map **slot;
@@ -932,9 +974,13 @@ next_discriminator_for_locus (location_t locus)
*slot = XNEW (struct locus_discrim_map);
gcc_assert (*slot);
(*slot)->locus = locus;
+ (*slot)->needs_increment = false;
(*slot)->discriminator = 0;
}
- (*slot)->discriminator++;
+ if (return_next || (*slot)->needs_increment)
+ (*slot)->discriminator++;
+ else
+ (*slot)->needs_increment = true;
return (*slot)->discriminator;
}
@@ -974,7 +1020,7 @@ assign_discriminator (location_t locus, basic_block bb)
if (locus == UNKNOWN_LOCATION)
return;
- discriminator = next_discriminator_for_locus (locus);
+ discriminator = next_discriminator_for_locus (locus, true);
for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
{
@@ -1009,23 +1055,13 @@ assign_discriminators (void)
for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
{
gimple stmt = gsi_stmt (gsi);
- if (curr_locus == UNKNOWN_LOCATION)
- {
+ if (gimple_code (stmt) == GIMPLE_CALL)
+ {
curr_locus = gimple_location (stmt);
- }
- else if (!same_line_p (curr_locus, gimple_location (stmt)))
- {
- curr_locus = gimple_location (stmt);
- curr_discr = 0;
- }
- else if (curr_discr != 0)
- {
+ curr_discr = next_discriminator_for_locus (curr_locus, false);
gimple_set_location (stmt, location_with_discriminator (
- gimple_location (stmt), curr_discr));
+ curr_locus, curr_discr));
}
- /* Allocate a new discriminator for CALL stmt. */
- if (gimple_code (stmt) == GIMPLE_CALL)
- curr_discr = next_discriminator_for_locus (curr_locus);
}
if (locus == UNKNOWN_LOCATION)
@@ -2416,28 +2452,10 @@ is_ctrl_altering_stmt (gimple t)
switch (gimple_code (t))
{
case GIMPLE_CALL:
- {
- int flags = gimple_call_flags (t);
-
- /* A call alters control flow if it can make an abnormal goto. */
- if (call_can_make_abnormal_goto (t))
- return true;
-
- /* A call also alters control flow if it does not return. */
- if (flags & ECF_NORETURN)
- return true;
-
- /* TM ending statements have backedges out of the transaction.
- Return true so we split the basic block containing them.
- Note that the TM_BUILTIN test is merely an optimization. */
- if ((flags & ECF_TM_BUILTIN)
- && is_tm_ending_fndecl (gimple_call_fndecl (t)))
- return true;
-
- /* BUILT_IN_RETURN call is same as return statement. */
- if (gimple_call_builtin_p (t, BUILT_IN_RETURN))
- return true;
- }
+ /* Per stmt call flag indicates whether the call could alter
+ controlflow. */
+ if (gimple_call_ctrl_altering_p (t))
+ return true;
break;
case GIMPLE_EH_DISPATCH:
@@ -8579,6 +8597,8 @@ execute_fixup_cfg (void)
&& (!is_gimple_call (stmt)
|| (gimple_call_flags (stmt) & ECF_NORETURN) == 0)))
{
+ if (stmt && is_gimple_call (stmt))
+ gimple_call_set_ctrl_altering (stmt, false);
stmt = gimple_build_call
(builtin_decl_implicit (BUILT_IN_UNREACHABLE), 0);
gimple_stmt_iterator gsi = gsi_last_bb (bb);
@@ -8589,10 +8609,6 @@ execute_fixup_cfg (void)
if (count_scale != REG_BR_PROB_BASE)
compute_function_frequency ();
- /* We just processed all calls. */
- if (cfun->gimple_df)
- vec_free (MODIFIED_NORETURN_CALLS (cfun));
-
/* Dump a textual representation of the flowgraph. */
if (dump_file)
gimple_dump_cfg (dump_file, dump_flags);
diff --git a/gcc-4.9/gcc/tree-cfgcleanup.c b/gcc-4.9/gcc/tree-cfgcleanup.c
index b7882cf..51b764f 100644
--- a/gcc-4.9/gcc/tree-cfgcleanup.c
+++ b/gcc-4.9/gcc/tree-cfgcleanup.c
@@ -162,6 +162,23 @@ cleanup_control_expr_graph (basic_block bb, gimple_stmt_iterator gsi)
return retval;
}
+/* Cleanup the GF_CALL_CTRL_ALTERING flag according to
+ to updated gimple_call_flags. */
+
+static void
+cleanup_call_ctrl_altering_flag (gimple bb_end)
+{
+ if (!is_gimple_call (bb_end)
+ || !gimple_call_ctrl_altering_p (bb_end))
+ return;
+
+ int flags = gimple_call_flags (bb_end);
+ if (((flags & (ECF_CONST | ECF_PURE))
+ && !(flags & ECF_LOOPING_CONST_OR_PURE))
+ || (flags & ECF_LEAF))
+ gimple_call_set_ctrl_altering (bb_end, false);
+}
+
/* Try to remove superfluous control structures in basic block BB. Returns
true if anything changes. */
@@ -182,6 +199,9 @@ cleanup_control_flow_bb (basic_block bb)
stmt = gsi_stmt (gsi);
+ /* Try to cleanup ctrl altering flag for call which ends bb. */
+ cleanup_call_ctrl_altering_flag (stmt);
+
if (gimple_code (stmt) == GIMPLE_COND
|| gimple_code (stmt) == GIMPLE_SWITCH)
retval |= cleanup_control_expr_graph (bb, gsi);
@@ -594,30 +614,24 @@ fixup_noreturn_call (gimple stmt)
known not to return, and remove the unreachable code. */
static bool
-split_bbs_on_noreturn_calls (void)
+split_bb_on_noreturn_calls (basic_block bb)
{
bool changed = false;
- gimple stmt;
- basic_block bb;
+ gimple_stmt_iterator gsi;
- /* Detect cases where a mid-block call is now known not to return. */
- if (cfun->gimple_df)
- while (vec_safe_length (MODIFIED_NORETURN_CALLS (cfun)))
- {
- stmt = MODIFIED_NORETURN_CALLS (cfun)->pop ();
- bb = gimple_bb (stmt);
- /* BB might be deleted at this point, so verify first
- BB is present in the cfg. */
- if (bb == NULL
- || bb->index < NUM_FIXED_BLOCKS
- || bb->index >= last_basic_block_for_fn (cfun)
- || BASIC_BLOCK_FOR_FN (cfun, bb->index) != bb
- || !gimple_call_noreturn_p (stmt))
- continue;
+ for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
+ {
+ gimple stmt = gsi_stmt (gsi);
+ if (!is_gimple_call (stmt))
+ continue;
+
+ if (gimple_call_noreturn_p (stmt))
changed |= fixup_noreturn_call (stmt);
- }
+ }
+ if (changed)
+ bitmap_set_bit (cfgcleanup_altered_bbs, bb->index);
return changed;
}
@@ -655,8 +669,6 @@ cleanup_tree_cfg_1 (void)
basic_block bb;
unsigned i, n;
- retval |= split_bbs_on_noreturn_calls ();
-
/* Prepare the worklists of altered blocks. */
cfgcleanup_altered_bbs = BITMAP_ALLOC (NULL);
@@ -672,7 +684,10 @@ cleanup_tree_cfg_1 (void)
{
bb = BASIC_BLOCK_FOR_FN (cfun, i);
if (bb)
- retval |= cleanup_tree_cfg_bb (bb);
+ {
+ retval |= cleanup_tree_cfg_bb (bb);
+ retval |= split_bb_on_noreturn_calls (bb);
+ }
}
/* Now process the altered blocks, as long as any are available. */
@@ -689,9 +704,9 @@ cleanup_tree_cfg_1 (void)
retval |= cleanup_tree_cfg_bb (bb);
- /* Rerun split_bbs_on_noreturn_calls, in case we have altered any noreturn
+ /* Rerun split_bb_on_noreturn_calls, in case we have altered any noreturn
calls. */
- retval |= split_bbs_on_noreturn_calls ();
+ retval |= split_bb_on_noreturn_calls (bb);
}
end_recording_case_labels ();
diff --git a/gcc-4.9/gcc/tree-ssa-loop-ivopts.c b/gcc-4.9/gcc/tree-ssa-loop-ivopts.c
index 8bc4e8f..78f036e 100644
--- a/gcc-4.9/gcc/tree-ssa-loop-ivopts.c
+++ b/gcc-4.9/gcc/tree-ssa-loop-ivopts.c
@@ -1679,6 +1679,8 @@ may_be_unaligned_p (tree ref, tree step)
return false;
unsigned int align = TYPE_ALIGN (TREE_TYPE (ref));
+ if (GET_MODE_ALIGNMENT (TYPE_MODE (TREE_TYPE (ref))) > align)
+ align = GET_MODE_ALIGNMENT (TYPE_MODE (TREE_TYPE (ref)));
unsigned HOST_WIDE_INT bitpos;
unsigned int ref_align;
diff --git a/gcc-4.9/gcc/tree-ssa-math-opts.c b/gcc-4.9/gcc/tree-ssa-math-opts.c
index 292ced1..0e8d54d 100644
--- a/gcc-4.9/gcc/tree-ssa-math-opts.c
+++ b/gcc-4.9/gcc/tree-ssa-math-opts.c
@@ -1749,6 +1749,8 @@ find_bswap_1 (gimple stmt, struct symbolic_number *n, int limit)
size = TYPE_PRECISION (n->type);
if (size % BITS_PER_UNIT != 0)
return NULL_TREE;
+ if (size > HOST_BITS_PER_WIDEST_INT)
+ return NULL_TREE;
size /= BITS_PER_UNIT;
n->n = (sizeof (HOST_WIDEST_INT) < 8 ? 0 :
(unsigned HOST_WIDEST_INT)0x08070605 << 32 | 0x04030201);
@@ -1792,6 +1794,8 @@ find_bswap_1 (gimple stmt, struct symbolic_number *n, int limit)
type_size = TYPE_PRECISION (type);
if (type_size % BITS_PER_UNIT != 0)
return NULL_TREE;
+ if (type_size > (int) HOST_BITS_PER_WIDEST_INT)
+ return NULL_TREE;
/* Sign extension: result is dependent on the value. */
old_type_size = TYPE_PRECISION (n->type);
@@ -1932,7 +1936,7 @@ execute_optimize_bswap (void)
bool changed = false;
tree bswap16_type = NULL_TREE, bswap32_type = NULL_TREE, bswap64_type = NULL_TREE;
- if (BITS_PER_UNIT != 8)
+ if (BITS_PER_UNIT != 8 || CHAR_BIT != 8)
return 0;
if (sizeof (HOST_WIDEST_INT) < 8)
diff --git a/gcc-4.9/gcc/tree-ssa-operands.c b/gcc-4.9/gcc/tree-ssa-operands.c
index 6647801..c3d7158 100644
--- a/gcc-4.9/gcc/tree-ssa-operands.c
+++ b/gcc-4.9/gcc/tree-ssa-operands.c
@@ -1092,12 +1092,6 @@ update_stmt_operands (struct function *fn, gimple stmt)
timevar_push (TV_TREE_OPS);
- /* If the stmt is a noreturn call queue it to be processed by
- split_bbs_on_noreturn_calls during cfg cleanup. */
- if (is_gimple_call (stmt)
- && gimple_call_noreturn_p (stmt))
- vec_safe_push (MODIFIED_NORETURN_CALLS (fn), stmt);
-
gcc_assert (gimple_modified_p (stmt));
build_ssa_operands (fn, stmt);
gimple_set_modified (stmt, false);
diff --git a/gcc-4.9/gcc/tree-ssa-tail-merge.c b/gcc-4.9/gcc/tree-ssa-tail-merge.c
index aa7f829..09e9b24 100644
--- a/gcc-4.9/gcc/tree-ssa-tail-merge.c
+++ b/gcc-4.9/gcc/tree-ssa-tail-merge.c
@@ -1159,17 +1159,9 @@ gimple_equal_p (same_succ same_succ, gimple s1, gimple s2)
lhs2 = gimple_get_lhs (s2);
if (TREE_CODE (lhs1) != SSA_NAME
&& TREE_CODE (lhs2) != SSA_NAME)
- {
- /* If the vdef is the same, it's the same statement. */
- if (vn_valueize (gimple_vdef (s1))
- == vn_valueize (gimple_vdef (s2)))
- return true;
-
- /* Test for structural equality. */
- return (operand_equal_p (lhs1, lhs2, 0)
- && gimple_operand_equal_value_p (gimple_assign_rhs1 (s1),
- gimple_assign_rhs1 (s2)));
- }
+ return (operand_equal_p (lhs1, lhs2, 0)
+ && gimple_operand_equal_value_p (gimple_assign_rhs1 (s1),
+ gimple_assign_rhs1 (s2)));
else if (TREE_CODE (lhs1) == SSA_NAME
&& TREE_CODE (lhs2) == SSA_NAME)
return vn_valueize (lhs1) == vn_valueize (lhs2);
diff --git a/gcc-4.9/gcc/tree-ssanames.h b/gcc-4.9/gcc/tree-ssanames.h
index bb3b5e6..b8729ad 100644
--- a/gcc-4.9/gcc/tree-ssanames.h
+++ b/gcc-4.9/gcc/tree-ssanames.h
@@ -58,7 +58,6 @@ struct GTY (()) range_info_def {
#define SSANAMES(fun) (fun)->gimple_df->ssa_names
-#define MODIFIED_NORETURN_CALLS(fun) (fun)->gimple_df->modified_noreturn_calls
#define DEFAULT_DEFS(fun) (fun)->gimple_df->default_defs
#define num_ssa_names (vec_safe_length (cfun->gimple_df->ssa_names))
diff --git a/gcc-4.9/gcc/tree-vect-loop.c b/gcc-4.9/gcc/tree-vect-loop.c
index 4e57904..2ebb90b 100644
--- a/gcc-4.9/gcc/tree-vect-loop.c
+++ b/gcc-4.9/gcc/tree-vect-loop.c
@@ -2321,7 +2321,8 @@ vect_is_simple_reduction_1 (loop_vec_info loop_info, gimple phi,
}
def1 = SSA_NAME_DEF_STMT (op1);
- if (flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
+ if (gimple_bb (def1)
+ && flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
&& loop->inner
&& flow_bb_inside_loop_p (loop->inner, gimple_bb (def1))
&& is_gimple_assign (def1))
diff --git a/gcc-4.9/gcc/tree-vectorizer.h b/gcc-4.9/gcc/tree-vectorizer.h
index 7733faa..f84bec5 100644
--- a/gcc-4.9/gcc/tree-vectorizer.h
+++ b/gcc-4.9/gcc/tree-vectorizer.h
@@ -414,9 +414,9 @@ typedef struct _loop_vec_info {
#define LOOP_VINFO_SCALAR_LOOP(L) (L)->scalar_loop
#define LOOP_REQUIRES_VERSIONING_FOR_ALIGNMENT(L) \
- (L)->may_misalign_stmts.length () > 0
+ ((L)->may_misalign_stmts.length () > 0)
#define LOOP_REQUIRES_VERSIONING_FOR_ALIAS(L) \
- (L)->may_alias_ddrs.length () > 0
+ ((L)->may_alias_ddrs.length () > 0)
#define LOOP_VINFO_NITERS_KNOWN_P(L) \
(tree_fits_shwi_p ((L)->num_iters) && tree_to_shwi ((L)->num_iters) > 0)
diff --git a/gcc-4.9/gcc/tree.h b/gcc-4.9/gcc/tree.h
index b656b7b..f13366f 100644
--- a/gcc-4.9/gcc/tree.h
+++ b/gcc-4.9/gcc/tree.h
@@ -2405,6 +2405,11 @@ extern void decl_value_expr_insert (tree, tree);
#define DECL_HAS_IMPLICIT_SECTION_NAME_P(NODE) \
(DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.implicit_section_name_p)
+/* Specify whether the section name was explicitly set with decl_attributes. */
+#define DECL_HAS_EXPLICIT_SECTION_NAME_P(NODE) \
+ (DECL_SECTION_NAME(NODE) != NULL_TREE \
+ && !DECL_HAS_IMPLICIT_SECTION_NAME_P(NODE))
+
extern tree decl_debug_expr_lookup (tree);
extern void decl_debug_expr_insert (tree, tree);