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authorSteve Ellcey <Steve.Ellcey@imgtec.com>2014-07-03 20:28:53 (GMT)
committerSteve Ellcey <Steve.Ellcey@imgtec.com>2014-07-03 23:10:41 (GMT)
commite7af147f979e657fe2df00808e5b4319b0e088c6 (patch)
tree4f302235c4ef4c0dce52449576c1b65333433cd5 /gcc-4.9/gcc/testsuite/gcc.target
parent1610db7b1892fe4da05cf4b0f64d9653978507d8 (diff)
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Update GCC 4.9 to include mips32r6, mips64r6 and MSA changes.
Change-Id: I136290865b137531d55321987818fc954a65f5d6
Diffstat (limited to 'gcc-4.9/gcc/testsuite/gcc.target')
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/args-1.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/args-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-1.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-2.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-3.c23
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-4.c22
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-5.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-4.c32
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-5.c32
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-6.c32
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/dmult-1.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-1.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/madd-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/madd-9.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/mips.exp103
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-1.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/movdf-1.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/movdf-2.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/movdf-3.c12
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/msa-type.c254
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/msa.c151
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/msub-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-3.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-2.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-1.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-2.c10
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-3.c10
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-4.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-5.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-6.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-7.c10
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/pr37362.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/timode-1.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/umips-store16-1.c30
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/umips-store16-2.c22
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/mips/unaligned-1.c2
42 files changed, 894 insertions, 32 deletions
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/args-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-1.c
index 3a132de..643df24 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/args-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-1.c
@@ -5,7 +5,7 @@
const char *compiled_for = _MIPS_ARCH;
const char *optimized_for = _MIPS_TUNE;
-#if __mips_fpr != 32 && __mips_fpr != 64
+#if __mips_fpr != 32 && __mips_fpr != 64 && __mips_fpr != 0
#error Bad __mips_fpr
#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/args-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-3.c
index 6a79ce6..5eddabf 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/args-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-3.c
@@ -24,7 +24,7 @@ int foo (float inf, int64 in64, int32 in32)
abort ();
#endif
-#if (__mips == 4 || __mips == 32 || __mips == 64) && !defined (__mips16)
+#if (__mips == 4 || ((__mips == 32 || __mips == 64) && __mips_isa_rev < 6)) && !defined (__mips16)
__asm__ ("move %0,%.\n\tmovn %0,%1,%2"
: "=&r" (res32) : "r" (in32), "r" (in64 != 0));
if (res32 != 60)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-2.c
index 3b2c4a1..39e181f 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-2.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mbranch-cost=10 isa>=4" } */
+/* { dg-options "-mbranch-cost=10 isa>=4 forbid_cpu=mips.*r6" } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
NOMIPS16 int
foo (int x, int y, int z, int k)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-1.c
new file mode 100644
index 0000000..ecb994f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-1.c
@@ -0,0 +1,21 @@
+/* Check that we handle call-clobbered FPRs correctly. */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-options "isa>=2 -mabi=32 -ffixed-f0 -ffixed-f1 -ffixed-f2 -ffixed-f3 -ffixed-f4 -ffixed-f5 -ffixed-f6 -ffixed-f7 -ffixed-f8 -ffixed-f9 -ffixed-f10 -ffixed-f11 -ffixed-f12 -ffixed-f13 -ffixed-f14 -ffixed-f15 -ffixed-f16 -ffixed-f17 -ffixed-f18 -ffixed-f19" } */
+
+void bar (void);
+double a;
+double
+foo ()
+{
+ double b = a + 1.0;
+ bar();
+ return b;
+}
+/* { dg-final { scan-assembler-not "lwc1" } } */
+/* { dg-final { scan-assembler-not "swc1" } } */
+/* { dg-final { scan-assembler-times "sdc1" 2 } } */
+/* { dg-final { scan-assembler-times "ldc1" 4 } } */
+/* { dg-final { scan-assembler-not "mtc" } } */
+/* { dg-final { scan-assembler-not "mfc" } } */
+/* { dg-final { scan-assembler-not "mthc" } } */
+/* { dg-final { scan-assembler-not "mfhc" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-2.c
new file mode 100644
index 0000000..7d9278e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-2.c
@@ -0,0 +1,21 @@
+/* Check that we handle call-clobbered FPRs correctly. */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-options "-mabi=32 -modd-spreg -mfp32 -ffixed-f0 -ffixed-f1 -ffixed-f2 -ffixed-f3 -ffixed-f4 -ffixed-f5 -ffixed-f6 -ffixed-f7 -ffixed-f8 -ffixed-f9 -ffixed-f10 -ffixed-f11 -ffixed-f12 -ffixed-f13 -ffixed-f14 -ffixed-f15 -ffixed-f16 -ffixed-f17 -ffixed-f18 -ffixed-f19 -ffixed-f20 -ffixed-f22 -ffixed-f24 -ffixed-f26 -ffixed-f28 -ffixed-f30" } */
+
+void bar (void);
+float a;
+float
+foo ()
+{
+ float b = a + 1.0f;
+ bar();
+ return b;
+}
+/* { dg-final { scan-assembler-times "lwc1" 2 } } */
+/* { dg-final { scan-assembler-not "swc1" } } */
+/* { dg-final { scan-assembler-times "sdc1" 2 } } */
+/* { dg-final { scan-assembler-times "ldc1" 2 } } */
+/* { dg-final { scan-assembler-not "mtc" } } */
+/* { dg-final { scan-assembler-not "mfc" } } */
+/* { dg-final { scan-assembler-not "mthc" } } */
+/* { dg-final { scan-assembler-not "mfhc" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-3.c
new file mode 100644
index 0000000..1cb763a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-3.c
@@ -0,0 +1,23 @@
+/* Check that we handle call-clobbered FPRs correctly. */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* Refer to call-clobbered-4.c to see the expected output from -Os builds. */
+/* { dg-skip-if "uses callee-saved GPR" { *-*-* } { "-Os" } { "" } } */
+/* { dg-options "-mabi=32 -modd-spreg -mfpxx -ffixed-f0 -ffixed-f1 -ffixed-f2 -ffixed-f3 -ffixed-f4 -ffixed-f5 -ffixed-f6 -ffixed-f7 -ffixed-f8 -ffixed-f9 -ffixed-f10 -ffixed-f11 -ffixed-f12 -ffixed-f13 -ffixed-f14 -ffixed-f15 -ffixed-f16 -ffixed-f17 -ffixed-f18 -ffixed-f19 -ffixed-f20 -ffixed-f22 -ffixed-f24 -ffixed-f26 -ffixed-f28 -ffixed-f30" } */
+
+void bar (void);
+float a;
+float
+foo ()
+{
+ float b = a + 1.0f;
+ bar();
+ return b;
+}
+/* { dg-final { scan-assembler-times "lwc1" 3 } } */
+/* { dg-final { scan-assembler-times "swc1" 1 } } */
+/* { dg-final { scan-assembler-times "sdc1" 2 } } */
+/* { dg-final { scan-assembler-times "ldc1" 2 } } */
+/* { dg-final { scan-assembler-not "mtc" } } */
+/* { dg-final { scan-assembler-not "mfc" } } */
+/* { dg-final { scan-assembler-not "mthc" } } */
+/* { dg-final { scan-assembler-not "mfhc" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-4.c
new file mode 100644
index 0000000..b498a05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-4.c
@@ -0,0 +1,22 @@
+/* Check that we handle call-clobbered FPRs correctly.
+ This test differs from call-clobbered-3.c because when optimising for size
+ a callee-saved GPR is used for 'b' to cross the call. */
+/* { dg-skip-if "code quality test" { *-*-* } { "*" } { "-Os" } } */
+/* { dg-options "-mabi=32 -modd-spreg -mfpxx -ffixed-f0 -ffixed-f1 -ffixed-f2 -ffixed-f3 -ffixed-f4 -ffixed-f5 -ffixed-f6 -ffixed-f7 -ffixed-f8 -ffixed-f9 -ffixed-f10 -ffixed-f11 -ffixed-f12 -ffixed-f13 -ffixed-f14 -ffixed-f15 -ffixed-f16 -ffixed-f17 -ffixed-f18 -ffixed-f19 -ffixed-f20 -ffixed-f22 -ffixed-f24 -ffixed-f26 -ffixed-f28 -ffixed-f30" } */
+
+void bar (void);
+float a;
+float
+foo ()
+{
+ float b = a + 1.0f;
+ bar();
+ return b;
+}
+/* { dg-final { scan-assembler-times "lwc1" 2 } } */
+/* { dg-final { scan-assembler-times "sdc1" 2 } } */
+/* { dg-final { scan-assembler-times "ldc1" 2 } } */
+/* { dg-final { scan-assembler-times "mtc" 1 } } */
+/* { dg-final { scan-assembler-times "mfc" 1 } } */
+/* { dg-final { scan-assembler-not "mthc" } } */
+/* { dg-final { scan-assembler-not "mfhc" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-5.c
new file mode 100644
index 0000000..c7cd7ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-clobbered-5.c
@@ -0,0 +1,21 @@
+/* Check that we handle call-clobbered FPRs correctly. */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-options "-mabi=32 -mfp64 -ffixed-f0 -ffixed-f1 -ffixed-f2 -ffixed-f3 -ffixed-f4 -ffixed-f5 -ffixed-f6 -ffixed-f7 -ffixed-f8 -ffixed-f9 -ffixed-f10 -ffixed-f11 -ffixed-f12 -ffixed-f13 -ffixed-f14 -ffixed-f15 -ffixed-f16 -ffixed-f17 -ffixed-f18 -ffixed-f19 -ffixed-f20 -ffixed-f22 -ffixed-f24 -ffixed-f26 -ffixed-f28 -ffixed-f30" } */
+
+void bar (void);
+float a;
+float
+foo ()
+{
+ float b = a + 1.0f;
+ bar();
+ return b;
+}
+/* { dg-final { scan-assembler-times "lwc1" 3 } } */
+/* { dg-final { scan-assembler-times "swc1" 1 } } */
+/* { dg-final { scan-assembler-not "sdc1" } } */
+/* { dg-final { scan-assembler-not "ldc1" } } */
+/* { dg-final { scan-assembler-not "mtc" } } */
+/* { dg-final { scan-assembler-not "mfc" } } */
+/* { dg-final { scan-assembler-not "mthc" } } */
+/* { dg-final { scan-assembler-not "mfhc" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-4.c
new file mode 100644
index 0000000..e126175
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-4.c
@@ -0,0 +1,32 @@
+/* Check that we save the correct call-saved GPRs and FPRs. */
+/* { dg-options "isa>=2 -mabi=32 -mfp32" } */
+
+void bar (void);
+
+void
+foo (int x)
+{
+ __builtin_unwind_init ();
+ __builtin_eh_return (x, bar);
+}
+/* { dg-final { scan-assembler "\\\$16" } } */
+/* { dg-final { scan-assembler "\\\$17" } } */
+/* { dg-final { scan-assembler "\\\$18" } } */
+/* { dg-final { scan-assembler "\\\$19" } } */
+/* { dg-final { scan-assembler "\\\$20" } } */
+/* { dg-final { scan-assembler "\\\$21" } } */
+/* { dg-final { scan-assembler "\\\$22" } } */
+/* { dg-final { scan-assembler "\\\$23" } } */
+/* { dg-final { scan-assembler "\\\$(30|fp)" } } */
+/* { dg-final { scan-assembler "\\\$f20" } } */
+/* { dg-final { scan-assembler "\\\$f22" } } */
+/* { dg-final { scan-assembler "\\\$f24" } } */
+/* { dg-final { scan-assembler "\\\$f26" } } */
+/* { dg-final { scan-assembler "\\\$f28" } } */
+/* { dg-final { scan-assembler "\\\$f30" } } */
+/* { dg-final { scan-assembler-not "\\\$f21" } } */
+/* { dg-final { scan-assembler-not "\\\$f23" } } */
+/* { dg-final { scan-assembler-not "\\\$f25" } } */
+/* { dg-final { scan-assembler-not "\\\$f27" } } */
+/* { dg-final { scan-assembler-not "\\\$f29" } } */
+/* { dg-final { scan-assembler-not "\\\$f31" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-5.c
new file mode 100644
index 0000000..2937b31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-5.c
@@ -0,0 +1,32 @@
+/* Check that we save the correct call-saved GPRs and FPRs. */
+/* { dg-options "-mabi=32 -mfpxx" } */
+
+void bar (void);
+
+void
+foo (int x)
+{
+ __builtin_unwind_init ();
+ __builtin_eh_return (x, bar);
+}
+/* { dg-final { scan-assembler "\\\$16" } } */
+/* { dg-final { scan-assembler "\\\$17" } } */
+/* { dg-final { scan-assembler "\\\$18" } } */
+/* { dg-final { scan-assembler "\\\$19" } } */
+/* { dg-final { scan-assembler "\\\$20" } } */
+/* { dg-final { scan-assembler "\\\$21" } } */
+/* { dg-final { scan-assembler "\\\$22" } } */
+/* { dg-final { scan-assembler "\\\$23" } } */
+/* { dg-final { scan-assembler "\\\$(30|fp)" } } */
+/* { dg-final { scan-assembler "\\\$f20" } } */
+/* { dg-final { scan-assembler "\\\$f22" } } */
+/* { dg-final { scan-assembler "\\\$f24" } } */
+/* { dg-final { scan-assembler "\\\$f26" } } */
+/* { dg-final { scan-assembler "\\\$f28" } } */
+/* { dg-final { scan-assembler "\\\$f30" } } */
+/* { dg-final { scan-assembler-not "\\\$f21" } } */
+/* { dg-final { scan-assembler-not "\\\$f23" } } */
+/* { dg-final { scan-assembler-not "\\\$f25" } } */
+/* { dg-final { scan-assembler-not "\\\$f27" } } */
+/* { dg-final { scan-assembler-not "\\\$f29" } } */
+/* { dg-final { scan-assembler-not "\\\$f31" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-6.c
new file mode 100644
index 0000000..0d1a4c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-6.c
@@ -0,0 +1,32 @@
+/* Check that we save the correct call-saved GPRs and FPRs. */
+/* { dg-options "-mabi=32 -mfp64" } */
+
+void bar (void);
+
+void
+foo (int x)
+{
+ __builtin_unwind_init ();
+ __builtin_eh_return (x, bar);
+}
+/* { dg-final { scan-assembler "\\\$16" } } */
+/* { dg-final { scan-assembler "\\\$17" } } */
+/* { dg-final { scan-assembler "\\\$18" } } */
+/* { dg-final { scan-assembler "\\\$19" } } */
+/* { dg-final { scan-assembler "\\\$20" } } */
+/* { dg-final { scan-assembler "\\\$21" } } */
+/* { dg-final { scan-assembler "\\\$22" } } */
+/* { dg-final { scan-assembler "\\\$23" } } */
+/* { dg-final { scan-assembler "\\\$(30|fp)" } } */
+/* { dg-final { scan-assembler "\\\$f20" } } */
+/* { dg-final { scan-assembler "\\\$f22" } } */
+/* { dg-final { scan-assembler "\\\$f24" } } */
+/* { dg-final { scan-assembler "\\\$f26" } } */
+/* { dg-final { scan-assembler "\\\$f28" } } */
+/* { dg-final { scan-assembler "\\\$f30" } } */
+/* { dg-final { scan-assembler-not "\\\$f21" } } */
+/* { dg-final { scan-assembler-not "\\\$f23" } } */
+/* { dg-final { scan-assembler-not "\\\$f25" } } */
+/* { dg-final { scan-assembler-not "\\\$f27" } } */
+/* { dg-final { scan-assembler-not "\\\$f29" } } */
+/* { dg-final { scan-assembler-not "\\\$f31" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dmult-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dmult-1.c
index f8c0b8b..9257316 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/dmult-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dmult-1.c
@@ -1,4 +1,4 @@
-/* { dg-options "forbid_cpu=octeon.* -mgp64" } */
+/* { dg-options "isa_rev<=5 forbid_cpu=octeon.* -mgp64" } */
/* { dg-final { scan-assembler "\tdmult\t" } } */
/* { dg-final { scan-assembler "\tmflo\t" } } */
/* { dg-final { scan-assembler-not "\tdmul\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-1.c
index c0594ff..03c2f79 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-1.c
@@ -1,5 +1,5 @@
/* We used to use c.lt.fmt instead of c.ule.fmt here. */
-/* { dg-options "-mhard-float" } */
+/* { dg-options "isa_rev<=5 -mhard-float" } */
NOMIPS16 int f1 (float x, float y) { return __builtin_isless (x, y); }
NOMIPS16 int f2 (double x, double y) { return __builtin_isless (x, y); }
/* { dg-final { scan-assembler "\tc\\.ule\\.s\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-2.c
index 23d5cb0..6936b90 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-2.c
@@ -1,5 +1,5 @@
/* We used to use c.le.fmt instead of c.ult.fmt here. */
-/* { dg-options "-mhard-float" } */
+/* { dg-options "isa_rev<=5 -mhard-float" } */
NOMIPS16 int f1 (float x, float y) { return __builtin_islessequal (x, y); }
NOMIPS16 int f2 (double x, double y) { return __builtin_islessequal (x, y); }
/* { dg-final { scan-assembler "\tc\\.ult\\.s\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-3.c
index 29f4c9b..55e05e7 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "isa_rev>=1 -mgp32" } */
+/* { dg-options "isa_rev>=1 -mgp32 forbid_cpu=mips.*r6" } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
/* { dg-final { scan-assembler-times "\tmadd\t" 3 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-9.c
index 28681a9..d89a9fd 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-9.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "isa_rev>=1 -mgp32 -mtune=4kc" } */
+/* { dg-options "isa_rev>=1 -mgp32 -mtune=4kc forbid_cpu=mips.*r6" } */
/* References to X within the loop need to have a higher frequency than
references to X outside the loop, otherwise there is no reason
to prefer multiply/accumulator registers over GPRs. */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-3.c
index 27a7350..14278f2 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-3.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* This test requires widening_mul */
-/* { dg-options "isa_rev>=1 -mgp32 -fexpensive-optimizations" } */
+/* { dg-options "isa_rev>=1 -mgp32 -fexpensive-optimizations forbid_cpu=mips.*r6" } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
/* { dg-final { scan-assembler-times "\tmaddu\t" 3 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c
index f52cf91..e3b441b 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c
@@ -1,7 +1,7 @@
/* Test v2sf calculations. The nmadd and nmsub patterns need
-ffinite-math-only. */
/* { dg-do compile } */
-/* { dg-options "isa_rev>=2 -mgp32 -mpaired-single -ffinite-math-only" } */
+/* { dg-options "isa_rev>=2 -mgp32 -mpaired-single -ffinite-math-only forbid_cpu=mips.*r6" } */
/* { dg-skip-if "nmadd and nmsub need combine" { *-*-* } { "-O0" } { "" } } */
/* { dg-final { scan-assembler "\tcvt.ps.s\t" } } */
/* { dg-final { scan-assembler "\tmov.ps\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips.exp b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips.exp
index 8c72cff..ec0b6f8 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips.exp
@@ -235,7 +235,7 @@ set mips_option_groups {
endianness "-E(L|B)|-me(l|b)"
float "-m(hard|soft)-float"
forbid_cpu "forbid_cpu=.*"
- fp "-mfp(32|64)"
+ fp "-mfp(32|xx|64)"
gp "-mgp(32|64)"
long "-mlong(32|64)"
micromips "-mmicromips|-mno-micromips"
@@ -248,6 +248,10 @@ set mips_option_groups {
dump "-fdump-.*"
}
+for { set option 0 } { $option < 32 } { incr option } {
+ lappend mips_option_groups "fixed-f$option" "-ffixed-f$option"
+}
+
# Add -mfoo/-mno-foo options to mips_option_groups.
foreach option {
abicalls
@@ -270,6 +274,8 @@ foreach option {
synci
relax-pic-calls
mcount-ra-address
+ odd-spreg
+ msa
} {
lappend mips_option_groups $option "-m(no-|)$option"
}
@@ -722,8 +728,12 @@ proc mips-dg-init {} {
#if __mips_fpr == 64
"-mfp64",
#else
+ #if __mips_fpr == 0
+ "-mfpxx",
+ #else
"-mfp32",
#endif
+ #endif
#ifdef __mips64
"-mgp64",
@@ -755,6 +765,12 @@ proc mips-dg-init {} {
"-mno-paired-single",
#endif
+ #if _MIPS_SPFPSET == 32
+ "-modd-spreg",
+ #else
+ "-mno-odd-spreg",
+ #endif
+
#if __mips_abicalls
"-mabicalls",
#else
@@ -789,6 +805,12 @@ proc mips-dg-init {} {
"-mno-synci",
#endif
+ #ifdef __mips_msa
+ "-mmsa"
+ #else
+ "-mno-msa"
+ #endif
+
0
};
}]
@@ -840,6 +862,8 @@ proc mips-dg-finish {} {
# | |
# -mfp64 -mfp32
# | |
+# -modd-spreg -mno-odd-spreg
+# | |
# -mabs=2008/-mabs=legacy <no option>
# | |
# -mhard-float -msoft-float
@@ -929,6 +953,7 @@ proc mips-dg-options { args } {
mips_option_dependency options "-mips3d" "-mpaired-single"
mips_option_dependency options "-mpaired-single" "-mfp64"
mips_option_dependency options "-mfp64" "-mhard-float"
+ mips_option_dependency options "-mfp64" "-modd-spreg"
mips_option_dependency options "-mabs=2008" "-mhard-float"
mips_option_dependency options "-mabs=legacy" "-mhard-float"
mips_option_dependency options "-mrelax-pic-calls" "-mno-plt"
@@ -973,20 +998,25 @@ proc mips-dg-options { args } {
set arch "-march=loongson2f"
}
} else {
- if { ![regexp {^(isa(?:|_rev))(=|<=|>=)([0-9]*)$} \
- $spec dummy prop relation value nocpus] } {
+ if { ![regexp {^(isa(?:|_rev))(=|<=|>=)([0-9]*)-?([0-9]*)$} \
+ $spec dummy prop relation minvalue maxvalue nocpus] } {
error "Unrecognized isa specification: $spec"
}
+ if { ![string equal $maxvalue ""] && ![string equal $relation "="] } {
+ error "Unsupported use of isa ranges: $spec"
+ } else if { [string equal $maxvalue ""] } {
+ set maxvalue $minvalue
+ }
set current [mips_arch_info $arch $prop]
if { $force_generic_isa_p
- || ($current < $value && ![string equal $relation "<="])
- || ($current > $value && ![string equal $relation ">="])
+ || ($current < $minvalue && ![string equal $relation "<="])
+ || ($current > $maxvalue && ![string equal $relation ">="])
|| ([mips_have_test_option_p options "-mgp64"]
&& [mips_32bit_arch_p $arch]) } {
# The current setting is out of range; it cannot
# possibly be used. Find a replacement that can.
if { [string equal $prop "isa"] } {
- set arch "-mips$value"
+ set arch "-mips$maxvalue"
} elseif { $value == 0 } {
set arch "-mips4"
} else {
@@ -995,8 +1025,8 @@ proc mips-dg-options { args } {
} else {
set arch "-mips64"
}
- if { $value > 1 } {
- append arch "r$value"
+ if { $maxvalue > 1 } {
+ append arch "r$maxvalue"
}
}
}
@@ -1045,10 +1075,13 @@ proc mips-dg-options { args } {
# We need a MIPS32 or MIPS64 ISA for:
#
# - paired-single instructions(*)
+ # - odd numbered single precision registers
#
# (*) Note that we don't support MIPS V at the moment.
} elseif { $isa_rev < 1
- && [mips_have_test_option_p options "-mpaired-single"] } {
+ && ([mips_have_test_option_p options "-mpaired-single"]
+ || ([mips_have_test_option_p options "-modd-spreg"]
+ && ![mips_have_test_option_p options "-mfp64"]))} {
if { $gp_size == 32 } {
mips_make_test_option options "-mips32"
} else {
@@ -1070,8 +1103,30 @@ proc mips-dg-options { args } {
# (*) needed by both -mbranch-likely and -mfix-r10000
} elseif { $isa < 2
&& ([mips_have_test_option_p options "-mbranch-likely"]
- || [mips_have_test_option_p options "-mfix-r10000"]) } {
+ || [mips_have_test_option_p options "-mfix-r10000"]
+ || ($gp_size == 32
+ && [mips_have_test_option_p options "-mfpxx"])) } {
mips_make_test_option options "-mips2"
+ # Check whether we need to switch from mips*r6 down to mips*r5 due
+ # to options that are incompatible with mips*r6. If we do, use
+ # -mnan=2008 because r6 is nan2008 by default and without this flag
+ # tests that include stdlib.h will fail due to not finding
+ # stubs-o32_hard.h (r6 compilers only have stubs-o32_hard_2008.h)
+ } elseif { $isa_rev > 5
+ && ([mips_have_test_option_p options "-mdsp"]
+ || [mips_have_test_option_p options "-mdspr2"]
+ || [mips_have_test_option_p options "-mips16"]
+ || [mips_have_test_option_p options "-mfp32"]
+ || [mips_have_test_option_p options "-mfix-r10000"]
+ || [mips_have_test_option_p options "-mpaired-single"]
+ || [mips_have_test_option_p options "-mnan=legacy"]
+ || [mips_have_test_option_p options "-mabs=legacy"]) } {
+ if { $gp_size == 32 } {
+ mips_make_test_option options "-mips32r5"
+ } else {
+ mips_make_test_option options "-mips64r5"
+ }
+ mips_make_test_option options "-mnan=2008"
# Check whether we need to switch from a 32-bit processor to the
# "nearest" 64-bit processor.
} elseif { $gp_size == 64 && [mips_32bit_arch_p $arch] } {
@@ -1096,6 +1151,10 @@ proc mips-dg-options { args } {
unset isa_rev
}
+ # Re-calculate the isa_rev for use in the abi handling code below
+ set arch [mips_option options arch]
+ set isa_rev [mips_arch_info $arch isa_rev]
+
# Set an appropriate ABI, handling dependencies between the pre-abi
# options and the abi options. This should mirror the abi and post-abi
# code below.
@@ -1121,6 +1180,9 @@ proc mips-dg-options { args } {
} elseif { [mips_have_test_option_p options "-mlong64"]
&& [mips_long32_abi_p $abi] } {
set force_abi 1
+ } elseif { [mips_have_test_option_p options "-mfpxx"]
+ && ![mips_same_option_p $abi "-mabi=32"] } {
+ set force_abi 1
} else {
set force_abi 0
}
@@ -1157,8 +1219,8 @@ proc mips-dg-options { args } {
if { $abi_test_option_p } {
if { $eabi_p } {
mips_make_test_option options "-mno-abicalls"
- if { $gp_size == 32 } {
- mips_make_test_option options "-mfp32"
+ if { $isa_rev < 6 && $gp_size == 32 } {
+ mips_make_test_option options "-mfp32"
}
}
if { [mips_using_mips16_p options]
@@ -1192,6 +1254,7 @@ proc mips-dg-options { args } {
}
if { $isa_rev < 1 } {
mips_make_test_option options "-mno-paired-single"
+ mips_make_test_option options "-mno-odd-spreg"
}
if { $isa_rev < 2 } {
if { $gp_size == 32 } {
@@ -1200,6 +1263,17 @@ proc mips-dg-options { args } {
mips_make_test_option options "-mno-dsp"
mips_make_test_option options "-mno-synci"
}
+ if { $isa_rev > 5 } {
+ mips_make_test_option options "-mno-dsp"
+ mips_make_test_option options "-mno-mips16"
+ if { [mips_have_test_option_p options "-mdsp"] } {
+ mips_make_test_option options "-mfp64"
+ }
+ mips_make_test_option options "-mno-fix-r10000"
+ mips_make_test_option options "-mno-paired-single"
+ mips_make_test_option options "-mnan=2008"
+ mips_make_test_option options "-mabs=2008"
+ }
unset arch
unset isa
unset isa_rev
@@ -1222,6 +1296,7 @@ proc mips-dg-options { args } {
mips_option_dependency options "-mplt" "-mno-shared"
mips_option_dependency options "-mno-shared" "-fno-pic"
mips_option_dependency options "-mfp32" "-mno-paired-single"
+ mips_option_dependency options "-mfpxx" "-mno-paired-single"
mips_option_dependency options "-msoft-float" "-mno-paired-single"
mips_option_dependency options "-mno-paired-single" "-mno-mips3d"
@@ -1243,7 +1318,9 @@ proc mips-dg-options { args } {
foreach group $mips_abi_groups {
set old_option [mips_original_option $group]
set new_option [mips_option options $group]
- if { ![mips_same_option_p $old_option $new_option] } {
+ if { ![mips_same_option_p $old_option $new_option]
+ && ![mips_same_option_p $old_option "-mfpxx"]
+ && ![mips_same_option_p $new_option "-mfpxx"] } {
switch -- [lindex $do_what 0] {
link -
run {
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-1.c
index b3fe188..435e5fe 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "isa>=4" } */
+/* { dg-options "isa>=4 forbid_cpu=mips.*r6" } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
/* { dg-final { scan-assembler "\tmovz\t" } } */
/* { dg-final { scan-assembler "\tmovn\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-2.c
index 2638d51..95130eb 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "isa>=4" } */
+/* { dg-options "isa>=4 forbid_cpu=mips.*r6" } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
/* { dg-final { scan-assembler "\tmovz\t" } } */
/* { dg-final { scan-assembler "\tmovn\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-3.c
index f356465..07f06b4 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "isa>=4 -mhard-float" } */
+/* { dg-options "isa>=4 -mhard-float forbid_cpu=mips.*r6" } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
/* { dg-final { scan-assembler "\tmovt\t" } } */
/* { dg-final { scan-assembler "\tmovf\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/movdf-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/movdf-1.c
new file mode 100644
index 0000000..54a4634
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/movdf-1.c
@@ -0,0 +1,13 @@
+/* Check that we move DFmode values via memory between FP and GP. */
+/* { dg-options "-mabi=32 -mfpxx isa=2" } */
+
+void bar (void);
+
+double
+foo (int x, double a)
+{
+ return a;
+}
+/* { dg-final { scan-assembler-not "mthc1" } } */
+/* { dg-final { scan-assembler-not "mtc1" } } */
+/* { dg-final { scan-assembler-times "ldc1" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/movdf-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/movdf-2.c
new file mode 100644
index 0000000..0390843
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/movdf-2.c
@@ -0,0 +1,13 @@
+/* Check that we move DFmode values using mthc between FP and GP. */
+/* { dg-options "-mabi=32 -mfpxx isa_rev=2" } */
+
+void bar (void);
+
+double
+foo (int x, double a)
+{
+ return a;
+}
+/* { dg-final { scan-assembler "mthc1" } } */
+/* { dg-final { scan-assembler "mtc1" } } */
+/* { dg-final { scan-assembler-not "ldc1" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/movdf-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/movdf-3.c
new file mode 100644
index 0000000..f897473
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/movdf-3.c
@@ -0,0 +1,12 @@
+/* Check that we move DFmode values using mtc1 between FP and GP. */
+/* { dg-options "-mabi=32 -mfp32 isa=2" } */
+
+void bar (void);
+
+double
+foo (int x, double a)
+{
+ return a;
+}
+/* { dg-final { scan-assembler-times "mtc1" 2 } } */
+/* { dg-final { scan-assembler-not "ldc1" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msa-type.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msa-type.c
new file mode 100644
index 0000000..1d4817f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msa-type.c
@@ -0,0 +1,254 @@
+/* Test MIPS MSA ASE instructions */
+/* { dg-do compile } */
+/* { dg-options "-mfp64 -mhard-float -mmsa" } */
+/* { dg-skip-if "madd and msub need combine" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\taddv.b\t" 2 } } */
+/* { dg-final { scan-assembler-times "\taddv.h\t" 2 } } */
+/* { dg-final { scan-assembler-times "\taddv.w\t" 2 } } */
+/* { dg-final { scan-assembler-times "\taddv.d\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tfadd.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tfadd.d\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tsubv.b\t" 4 } } */
+/* { dg-final { scan-assembler-times "\tsubv.h\t" 4 } } */
+/* { dg-final { scan-assembler-times "\tsubv.w\t" 4 } } */
+/* { dg-final { scan-assembler-times "\tsubv.d\t" 4 } } */
+/* { dg-final { scan-assembler-times "\tfsub.w\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tfsub.d\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmulv.b\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmulv.h\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmulv.w\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmulv.d\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tfmul.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tfmul.d\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tdiv_s.b\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tdiv_s.h\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tdiv_s.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tdiv_s.d\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tfdiv.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tfdiv.d\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tdiv_u.b\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tdiv_u.h\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tdiv_u.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tdiv_u.d\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tmod_s.b\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tmod_s.h\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tmod_s.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tmod_s.d\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tmod_u.b\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tmod_u.h\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tmod_u.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tmod_u.d\t" 1 } } */
+/* { dg-final { scan-assembler-times "\txor.v\t" 8 } } */
+/* { dg-final { scan-assembler-times "\tor.v\t" 8 } } */
+/* { dg-final { scan-assembler-times "\tand.v\t" 8 } } */
+/* { dg-final { scan-assembler-times "\tsra.b\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tsra.h\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tsra.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tsra.d\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tsrl.b\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tsrl.h\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tsrl.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tsrl.d\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tsll.b\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tsll.h\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tsll.w\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tsll.d\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tldi.b\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tldi.h\t" 4 } } */
+/* { dg-final { scan-assembler-times "\tldi.w\t" 5 } } */
+/* { dg-final { scan-assembler-times "\tldi.d\t" 5 } } */
+/* { dg-final { scan-assembler-times "\tnor.v\t" 6 } } */
+/* { dg-final { scan-assembler-times "\tnori.b\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmaddv.b\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmaddv.h\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmaddv.w\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmaddv.d\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmove.v\t" 40 } } */
+/* { dg-final { scan-assembler-times "\tfmadd.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tfmadd.d\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tmsubv.b\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmsubv.h\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmsubv.w\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmsubv.d\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tfmsub.w\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tfmsub.d\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tvshf.b\t" 4 } } */
+/* { dg-final { scan-assembler-times "\tvshf.h\t" 4 } } */
+/* { dg-final { scan-assembler-times "\tvshf.w\t" 6 } } */
+/* { dg-final { scan-assembler-times "\tvshf.d\t" 6 } } */
+
+typedef signed char v16i8 __attribute__ ((vector_size(16)));
+typedef short v8i16 __attribute__ ((vector_size(16)));
+typedef int v4i32 __attribute__ ((vector_size(16)));
+typedef long long v2i64 __attribute__ ((vector_size(16)));
+typedef unsigned char v16u8 __attribute__ ((vector_size(16)));
+typedef unsigned short v8u16 __attribute__ ((vector_size(16)));
+typedef unsigned int v4u32 __attribute__ ((vector_size(16)));
+typedef unsigned long long v2u64 __attribute__ ((vector_size(16)));
+typedef float v4f32 __attribute__ ((vector_size(16)));
+typedef double v2f64 __attribute__ ((vector_size(16)));
+
+/*
+typedef signed char v8i8 __attribute__ ((vector_size(8)));
+typedef short v4i16 __attribute__ ((vector_size(8)));
+typedef int v2i32 __attribute__ ((vector_size(8)));
+typedef float v2f32 __attribute__ ((vector_size(8)));
+
+typedef signed char v4i8 __attribute__ ((vector_size(4)));
+typedef short v2i16 __attribute__ ((vector_size(4)));
+*/
+
+typedef long long i64;
+typedef int i32;
+typedef short i16;
+typedef signed char i8;
+typedef double f64;
+typedef float f32;
+
+#define DECLARE(TYPE) TYPE TYPE ## _0, TYPE ## _1, TYPE ## _2;
+#define RETURN(TYPE) NOMIPS16 TYPE test0_ ## TYPE () { return TYPE ## _0; }
+#define ASSIGN(TYPE) NOMIPS16 void test1_ ## TYPE (TYPE i) { TYPE ## _1 = i; }
+#define ADD(TYPE) NOMIPS16 TYPE test2_ ## TYPE (TYPE i, TYPE j) { return i + j; }
+#define SUB(TYPE) NOMIPS16 TYPE test3_ ## TYPE (TYPE i, TYPE j) { return i - j; }
+#define MUL(TYPE) NOMIPS16 TYPE test4_ ## TYPE (TYPE i, TYPE j) { return i * j; }
+#define DIV(TYPE) TYPE test5_ ## TYPE (TYPE i, TYPE j) { return i / j; }
+#define MOD(TYPE) TYPE test6_ ## TYPE (TYPE i, TYPE j) { return i % j; }
+#define MINUS(TYPE) TYPE test7_ ## TYPE (TYPE i) { return -i; }
+#define XOR(TYPE) TYPE test8_ ## TYPE (TYPE i, TYPE j) { return i ^ j; }
+#define OR(TYPE) TYPE test9_ ## TYPE (TYPE i, TYPE j) { return i | j; }
+#define AND(TYPE) TYPE test10_ ## TYPE (TYPE i, TYPE j) { return i & j; }
+#define BIT_COMPLEMENT(TYPE) TYPE test11_ ## TYPE (TYPE i) { return ~i; }
+#define SHIFT_RIGHT(TYPE) TYPE test12_ ## TYPE (TYPE i, TYPE j) { return i >> j; }
+#define SHIFT_LEFT(TYPE) TYPE test13_ ## TYPE (TYPE i, TYPE j) { return i << j; }
+#define EQ(TYPE) TYPE test14_ ## TYPE (TYPE i, TYPE j) { return i == j; }
+#define NEQ(TYPE) TYPE test15_ ## TYPE (TYPE i, TYPE j) { return i != j; }
+#define LT(TYPE) TYPE test16_ ## TYPE (TYPE i, TYPE j) { return i < j; }
+#define LEQ(TYPE) TYPE test17_ ## TYPE (TYPE i, TYPE j) { return i <= j; }
+#define GT(TYPE) TYPE test18_ ## TYPE (TYPE i, TYPE j) { return i > j; }
+#define GEQ(TYPE) TYPE test19_ ## TYPE (TYPE i, TYPE j) { return i >= j; }
+
+#define ADD_I(TYPE) TYPE test20_ ## TYPE (TYPE i) { return i + 37; }
+#define SUB_I(TYPE) TYPE test21_ ## TYPE (TYPE i) { return i - 37; }
+#define MUL_I(TYPE) TYPE test22_ ## TYPE (TYPE i) { return i * 37; }
+#define DIV_I(TYPE) TYPE test23_ ## TYPE (TYPE i) { return i / 37; }
+#define MOD_I(TYPE) TYPE test24_ ## TYPE (TYPE i) { return i % 37; }
+#define XOR_I(TYPE) TYPE test25_ ## TYPE (TYPE i) { return i ^ 37; }
+#define OR_I(TYPE) TYPE test26_ ## TYPE (TYPE i) { return i | 37; }
+#define AND_I(TYPE) TYPE test27_ ## TYPE (TYPE i) { return i & 37; }
+#define SHIFT_RIGHT_I(TYPE) TYPE test28_ ## TYPE (TYPE i) { return i >> 3; }
+#define SHIFT_LEFT_I(TYPE) TYPE test29_ ## TYPE (TYPE i) { return i << 3; }
+
+#define ADD_F(TYPE) TYPE test30_ ## TYPE (TYPE i) { return i + 37.0; }
+#define SUB_F(TYPE) TYPE test31_ ## TYPE (TYPE i) { return i - 37.0; }
+#define MUL_F(TYPE) TYPE test32_ ## TYPE (TYPE i) { return i * 37.0; }
+#define DIV_F(TYPE) TYPE test33_ ## TYPE (TYPE i) { return i / 37.0; }
+
+#define SHUFFLE1(TYPE) TYPE test34_ ## TYPE (TYPE i, TYPE mask) { return __builtin_shuffle (i, mask); }
+#define SHUFFLE2(TYPE) TYPE test35_ ## TYPE (TYPE i, TYPE j, TYPE mask) { return __builtin_shuffle (i, j, mask); }
+
+#define REAL_SHUFFLE1(TYPE, MASK_TYPE) TYPE test36_ ## TYPE (TYPE i, MASK_TYPE mask) { return __builtin_shuffle (i, mask); }
+#define REAL_SHUFFLE2(TYPE, MASK_TYPE) TYPE test37_ ## TYPE (TYPE i, TYPE j, MASK_TYPE mask) { return __builtin_shuffle (i, j, mask); }
+
+#define MADD(TYPE) TYPE test38_ ## TYPE (TYPE i, TYPE j, TYPE k) { return i * j + k; }
+#define MSUB(TYPE) TYPE test39_ ## TYPE (TYPE i, TYPE j, TYPE k) { return k - i * j; }
+
+#define ITERATE_FOR_ALL_INT_VECTOR_TYPES(FUNC) \
+ FUNC (v16i8) \
+ FUNC (v8i16) \
+ FUNC (v4i32) \
+ FUNC (v2i64) \
+ FUNC (v16u8) \
+ FUNC (v8u16) \
+ FUNC (v4u32) \
+ FUNC (v2u64)
+
+/*
+ FUNC (v8i8) \
+ FUNC (v4i16) \
+ FUNC (v2i32) \
+ FUNC (v4i8) \
+ FUNC (v2i16)
+*/
+
+#define ITERATE_FOR_ALL_INT_SCALAR_TYPES(FUNC) \
+ FUNC (i64) \
+ FUNC (i32) \
+ FUNC (i16) \
+ FUNC (i8)
+
+#define ITERATE_FOR_ALL_INT_TYPES(FUNC) \
+ ITERATE_FOR_ALL_INT_VECTOR_TYPES(FUNC) \
+
+/*
+ ITERATE_FOR_ALL_INT_SCALAR_TYPES(FUNC)
+*/
+
+#define ITERATE_FOR_ALL_REAL_VECTOR_TYPES(FUNC) \
+ FUNC (v4f32) \
+ FUNC (v2f64) \
+
+/*
+ FUNC (v2f32)
+*/
+
+#define ITERATE_FOR_ALL_REAL_SCALAR_TYPES(FUNC) \
+ FUNC (f64) \
+ FUNC (f32)
+
+#define ITERATE_FOR_ALL_REAL_TYPES(FUNC) \
+ ITERATE_FOR_ALL_REAL_VECTOR_TYPES(FUNC) \
+
+/*
+ ITERATE_FOR_ALL_REAL_SCALAR_TYPES(FUNC)
+*/
+
+#define ITERATE_FOR_ALL_TYPES(FUNC) \
+ ITERATE_FOR_ALL_INT_TYPES(FUNC) \
+ ITERATE_FOR_ALL_REAL_TYPES(FUNC)
+
+ITERATE_FOR_ALL_TYPES (ADD)
+ITERATE_FOR_ALL_TYPES (SUB)
+ITERATE_FOR_ALL_TYPES (MUL)
+ITERATE_FOR_ALL_TYPES (DIV)
+ITERATE_FOR_ALL_INT_TYPES (MOD)
+ITERATE_FOR_ALL_INT_TYPES (XOR)
+ITERATE_FOR_ALL_INT_TYPES (OR)
+ITERATE_FOR_ALL_INT_TYPES (AND)
+ITERATE_FOR_ALL_INT_TYPES (SHIFT_RIGHT)
+ITERATE_FOR_ALL_INT_TYPES (SHIFT_LEFT)
+ITERATE_FOR_ALL_TYPES (MINUS)
+ITERATE_FOR_ALL_INT_TYPES (BIT_COMPLEMENT)
+ITERATE_FOR_ALL_TYPES (MADD)
+ITERATE_FOR_ALL_TYPES (MSUB)
+ITERATE_FOR_ALL_INT_VECTOR_TYPES (SHUFFLE1)
+ITERATE_FOR_ALL_INT_VECTOR_TYPES (SHUFFLE2)
+REAL_SHUFFLE1 (v2f64, v2i64)
+REAL_SHUFFLE2 (v2f64, v2i64)
+REAL_SHUFFLE1 (v4f32, v4i32)
+REAL_SHUFFLE2 (v4f32, v4i32)
+
+/*
+ITERATE_FOR_ALL_TYPES (DECLARE)
+ITERATE_FOR_ALL_TYPES (RETURN)
+ITERATE_FOR_ALL_TYPES (ASSIGN)
+ITERATE_FOR_ALL_INT_TYPES (ADD_I)
+ITERATE_FOR_ALL_INT_TYPES (SUB_I)
+ITERATE_FOR_ALL_INT_TYPES (MUL_I)
+ITERATE_FOR_ALL_INT_TYPES (DIV_I)
+ITERATE_FOR_ALL_INT_TYPES (MOD_I)
+ITERATE_FOR_ALL_INT_TYPES (XOR_I)
+ITERATE_FOR_ALL_INT_TYPES (OR_I)
+ITERATE_FOR_ALL_INT_TYPES (AND_I)
+ITERATE_FOR_ALL_INT_TYPES (SHIFT_RIGHT_I)
+ITERATE_FOR_ALL_INT_TYPES (SHIFT_LEFT_I)
+ITERATE_FOR_ALL_REAL_TYPES (ADD_F)
+ITERATE_FOR_ALL_REAL_TYPES (SUB_F)
+ITERATE_FOR_ALL_REAL_TYPES (MUL_F)
+ITERATE_FOR_ALL_REAL_TYPES (DIV_F)
+ITERATE_FOR_ALL_TYPES (EQ)
+ITERATE_FOR_ALL_TYPES (NEQ)
+ITERATE_FOR_ALL_TYPES (LT)
+ITERATE_FOR_ALL_TYPES (LEQ)
+ITERATE_FOR_ALL_TYPES (GT)
+ITERATE_FOR_ALL_TYPES (GEQ)
+*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msa.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msa.c
new file mode 100644
index 0000000..19ecfe8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msa.c
@@ -0,0 +1,151 @@
+/* Test MIPS MSA ASE instructions */
+/* { dg-do compile } */
+/* { dg-options "-mips32r2 -mfp64 -mhard-float -mmsa" } */
+
+typedef signed char v16i8 __attribute__ ((vector_size(16)));
+typedef short v8i16 __attribute__ ((vector_size(16)));
+typedef int v4i32 __attribute__ ((vector_size(16)));
+typedef long long v2i64 __attribute__ ((vector_size(16)));
+typedef float v4f32 __attribute__ ((vector_size(16)));
+typedef double v2f64 __attribute__ ((vector_size(16)));
+
+typedef signed char v8i8 __attribute__ ((vector_size(8)));
+typedef short v4i16 __attribute__ ((vector_size(8)));
+typedef int v2i32 __attribute__ ((vector_size(8)));
+typedef float v2f32 __attribute__ ((vector_size(8)));
+
+typedef signed char v4i8 __attribute__ ((vector_size(4)));
+typedef short v2i16 __attribute__ ((vector_size(4)));
+
+typedef long long i64;
+typedef int i32;
+typedef short i16;
+typedef signed char i8;
+typedef double f64;
+typedef float f32;
+
+#define DECLARE(TYPE) TYPE TYPE ## _0, TYPE ## _1, TYPE ## _2;
+#define RETURN(TYPE) TYPE test0_ ## TYPE () { return TYPE ## _0; }
+#define ASSIGN(TYPE) void test1_ ## TYPE (TYPE i) { TYPE ## _1 = i; }
+#define ADD(TYPE) TYPE test2_ ## TYPE (TYPE i, TYPE j) { return i + j; }
+#define SUB(TYPE) TYPE test3_ ## TYPE (TYPE i, TYPE j) { return i - j; }
+#define MUL(TYPE) TYPE test4_ ## TYPE (TYPE i, TYPE j) { return i * j; }
+#define DIV(TYPE) TYPE test5_ ## TYPE (TYPE i, TYPE j) { return i / j; }
+#define MOD(TYPE) TYPE test6_ ## TYPE (TYPE i, TYPE j) { return i % j; }
+#define MINUS(TYPE) TYPE test7_ ## TYPE (TYPE i) { return -i; }
+#define XOR(TYPE) TYPE test8_ ## TYPE (TYPE i, TYPE j) { return i ^ j; }
+#define OR(TYPE) TYPE test9_ ## TYPE (TYPE i, TYPE j) { return i | j; }
+#define AND(TYPE) TYPE test10_ ## TYPE (TYPE i, TYPE j) { return i & j; }
+#define BIT_COMPLEMENT(TYPE) TYPE test11_ ## TYPE (TYPE i) { return ~i; }
+#define SHIFT_RIGHT(TYPE) TYPE test12_ ## TYPE (TYPE i, TYPE j) { return i >> j; }
+#define SHIFT_LEFT(TYPE) TYPE test13_ ## TYPE (TYPE i, TYPE j) { return i << j; }
+#define EQ(TYPE) TYPE test14_ ## TYPE (TYPE i, TYPE j) { return i == j; }
+#define NEQ(TYPE) TYPE test15_ ## TYPE (TYPE i, TYPE j) { return i != j; }
+#define LT(TYPE) TYPE test16_ ## TYPE (TYPE i, TYPE j) { return i < j; }
+#define LEQ(TYPE) TYPE test17_ ## TYPE (TYPE i, TYPE j) { return i <= j; }
+#define GT(TYPE) TYPE test18_ ## TYPE (TYPE i, TYPE j) { return i > j; }
+#define GEQ(TYPE) TYPE test19_ ## TYPE (TYPE i, TYPE j) { return i >= j; }
+
+#define ADD_I(TYPE) TYPE test20_ ## TYPE (TYPE i) { return i + 37; }
+#define SUB_I(TYPE) TYPE test21_ ## TYPE (TYPE i) { return i - 37; }
+#define MUL_I(TYPE) TYPE test22_ ## TYPE (TYPE i) { return i * 37; }
+#define DIV_I(TYPE) TYPE test23_ ## TYPE (TYPE i) { return i / 37; }
+#define MOD_I(TYPE) TYPE test24_ ## TYPE (TYPE i) { return i % 37; }
+#define XOR_I(TYPE) TYPE test25_ ## TYPE (TYPE i) { return i ^ 37; }
+#define OR_I(TYPE) TYPE test26_ ## TYPE (TYPE i) { return i | 37; }
+#define AND_I(TYPE) TYPE test27_ ## TYPE (TYPE i) { return i & 37; }
+#define SHIFT_RIGHT_I(TYPE) TYPE test28_ ## TYPE (TYPE i) { return i >> 3; }
+#define SHIFT_LEFT_I(TYPE) TYPE test29_ ## TYPE (TYPE i) { return i << 3; }
+
+#define ADD_F(TYPE) TYPE test30_ ## TYPE (TYPE i) { return i + 37.0; }
+#define SUB_F(TYPE) TYPE test31_ ## TYPE (TYPE i) { return i - 37.0; }
+#define MUL_F(TYPE) TYPE test32_ ## TYPE (TYPE i) { return i * 37.0; }
+#define DIV_F(TYPE) TYPE test33_ ## TYPE (TYPE i) { return i / 37.0; }
+
+#define SHUFFLE1(TYPE) TYPE test34_ ## TYPE (TYPE i, TYPE mask) { return __builtin_shuffle (i, mask); }
+#define SHUFFLE2(TYPE) TYPE test35_ ## TYPE (TYPE i, TYPE j, TYPE mask) { return __builtin_shuffle (i, j, mask); }
+
+#define REAL_SHUFFLE1(TYPE, MASK_TYPE) TYPE test36_ ## TYPE (TYPE i, MASK_TYPE mask) { return __builtin_shuffle (i, mask); }
+#define REAL_SHUFFLE2(TYPE, MASK_TYPE) TYPE test37_ ## TYPE (TYPE i, TYPE j, MASK_TYPE mask) { return __builtin_shuffle (i, j, mask); }
+
+#define ITERATE_FOR_ALL_INT_VECTOR_TYPES(FUNC) \
+ FUNC (v16i8) \
+ FUNC (v8i16) \
+ FUNC (v4i32) \
+ FUNC (v2i64) \
+ FUNC (v8i8) \
+ FUNC (v4i16) \
+ FUNC (v2i32) \
+ FUNC (v4i8) \
+ FUNC (v2i16)
+
+#define ITERATE_FOR_ALL_INT_SCALAR_TYPES(FUNC) \
+ FUNC (i64) \
+ FUNC (i32) \
+ FUNC (i16) \
+ FUNC (i8)
+
+#define ITERATE_FOR_ALL_INT_TYPES(FUNC) \
+ ITERATE_FOR_ALL_INT_VECTOR_TYPES(FUNC) \
+ ITERATE_FOR_ALL_INT_SCALAR_TYPES(FUNC)
+
+#define ITERATE_FOR_ALL_REAL_VECTOR_TYPES(FUNC) \
+ FUNC (v4f32) \
+ FUNC (v2f64) \
+ FUNC (v2f32)
+
+#define ITERATE_FOR_ALL_REAL_SCALAR_TYPES(FUNC) \
+ FUNC (f64) \
+ FUNC (f32)
+
+#define ITERATE_FOR_ALL_REAL_TYPES(FUNC) \
+ ITERATE_FOR_ALL_REAL_VECTOR_TYPES(FUNC) \
+ ITERATE_FOR_ALL_REAL_SCALAR_TYPES(FUNC)
+
+#define ITERATE_FOR_ALL_TYPES(FUNC) \
+ ITERATE_FOR_ALL_INT_TYPES(FUNC) \
+ ITERATE_FOR_ALL_REAL_TYPES(FUNC)
+
+ITERATE_FOR_ALL_TYPES (DECLARE)
+ITERATE_FOR_ALL_TYPES (RETURN)
+ITERATE_FOR_ALL_TYPES (ASSIGN)
+ITERATE_FOR_ALL_TYPES (ADD)
+ITERATE_FOR_ALL_TYPES (SUB)
+ITERATE_FOR_ALL_TYPES (MUL)
+ITERATE_FOR_ALL_TYPES (DIV)
+ITERATE_FOR_ALL_TYPES (MINUS)
+ITERATE_FOR_ALL_INT_TYPES (MOD)
+ITERATE_FOR_ALL_INT_TYPES (XOR)
+ITERATE_FOR_ALL_INT_TYPES (OR)
+ITERATE_FOR_ALL_INT_TYPES (AND)
+ITERATE_FOR_ALL_INT_TYPES (BIT_COMPLEMENT)
+ITERATE_FOR_ALL_INT_TYPES (SHIFT_RIGHT)
+ITERATE_FOR_ALL_INT_TYPES (SHIFT_LEFT)
+ITERATE_FOR_ALL_INT_TYPES (ADD_I)
+ITERATE_FOR_ALL_INT_TYPES (SUB_I)
+ITERATE_FOR_ALL_INT_TYPES (MUL_I)
+ITERATE_FOR_ALL_INT_TYPES (DIV_I)
+ITERATE_FOR_ALL_INT_TYPES (MOD_I)
+ITERATE_FOR_ALL_INT_TYPES (XOR_I)
+ITERATE_FOR_ALL_INT_TYPES (OR_I)
+ITERATE_FOR_ALL_INT_TYPES (AND_I)
+ITERATE_FOR_ALL_INT_TYPES (SHIFT_RIGHT_I)
+ITERATE_FOR_ALL_INT_TYPES (SHIFT_LEFT_I)
+ITERATE_FOR_ALL_REAL_TYPES (ADD_F)
+ITERATE_FOR_ALL_REAL_TYPES (SUB_F)
+ITERATE_FOR_ALL_REAL_TYPES (MUL_F)
+ITERATE_FOR_ALL_REAL_TYPES (DIV_F)
+ITERATE_FOR_ALL_INT_VECTOR_TYPES (SHUFFLE1)
+ITERATE_FOR_ALL_INT_VECTOR_TYPES (SHUFFLE2)
+REAL_SHUFFLE1 (v2f64, v2i64)
+REAL_SHUFFLE2 (v2f64, v2i64)
+REAL_SHUFFLE1 (v4f32, v4i32)
+REAL_SHUFFLE2 (v4f32, v4i32)
+REAL_SHUFFLE1 (v2f32, v2i32)
+REAL_SHUFFLE2 (v2f32, v2i32)
+ITERATE_FOR_ALL_TYPES (EQ)
+ITERATE_FOR_ALL_TYPES (NEQ)
+ITERATE_FOR_ALL_TYPES (LT)
+ITERATE_FOR_ALL_TYPES (LEQ)
+ITERATE_FOR_ALL_TYPES (GT)
+ITERATE_FOR_ALL_TYPES (GEQ)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-3.c
index aedd043..6284fe8 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-3.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* This test requires widening_mul */
-/* { dg-options "isa_rev>=1 -mgp32 -fexpensive-optimizations" } */
+/* { dg-options "isa_rev>=1 -mgp32 -fexpensive-optimizations forbid_cpu=mips.*r6" } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
/* { dg-final { scan-assembler-times "\tmsub\t" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-3.c
index 2e936eb..e6fc547 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-3.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-3.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* This test requires widening_mul */
-/* { dg-options "isa_rev>=1 -mgp32 -fexpensive-optimizations" } */
+/* { dg-options "isa_rev>=1 -mgp32 -fexpensive-optimizations forbid_cpu=mips.*r6" } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
/* { dg-final { scan-assembler-times "\tmsubu\t" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-2.c
index 435751e..59e797d 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-2.c
@@ -1,7 +1,7 @@
/* Make sure that we avoid abs.fmt and neg.fmt when the signs of NaNs
matter. */
/* { dg-do compile } */
-/* { dg-options "-mhard-float -fno-finite-math-only" } */
+/* { dg-options "isa_rev<=5 -mhard-float -fno-finite-math-only -mabs=legacy" } */
/* { dg-final { scan-assembler-not "\tneg.s\t" } } */
/* { dg-final { scan-assembler-not "\tneg.d\t" } } */
/* { dg-final { scan-assembler-not "\tabs.s\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-1.c
new file mode 100644
index 0000000..a9c6957
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-1.c
@@ -0,0 +1,13 @@
+/* Check that we enable odd-numbered single precision registers. */
+/* { dg-options "-mabi=32 -modd-spreg -mhard-float" } */
+
+#if _MIPS_SPFPSET != 32
+#error "Incorrect number of single-precision registers reported"
+#endif
+
+void
+foo ()
+{
+ register float foo asm ("$f1");
+ asm volatile ("" : "=f" (foo));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-2.c
new file mode 100644
index 0000000..e2e0a26
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-2.c
@@ -0,0 +1,10 @@
+/* Check that we disable odd-numbered single precision registers. */
+/* { dg-skip-if "needs asm output" { *-*-* } { "-fno-fat-lto-objects" } { "" } } */
+/* { dg-options "-mabi=32 -mno-odd-spreg -mhard-float" } */
+
+void
+foo ()
+{
+ register float foo asm ("$f1"); /* { dg-error "isn't suitable for" } */
+ asm volatile ("" : "=f" (foo));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-3.c
new file mode 100644
index 0000000..8a2eb63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-3.c
@@ -0,0 +1,10 @@
+/* Check that we disable odd-numbered single precision registers. */
+/* { dg-skip-if "needs asm output" { *-*-* } { "-fno-fat-lto-objects" } { "" } } */
+/* { dg-options "-mabi=32 -march=loongson3a -mhard-float" } */
+
+void
+foo ()
+{
+ register float foo asm ("$f1"); /* { dg-error "isn't suitable for" } */
+ asm volatile ("" : "=f" (foo));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-4.c
new file mode 100644
index 0000000..723424a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-4.c
@@ -0,0 +1,15 @@
+/* Check that we disable odd-numbered single precision registers and can
+ still generate code. */
+/* { dg-options "-mabi=32 -mno-odd-spreg -mhard-float" } */
+
+#if _MIPS_SPFPSET != 16
+#error "Incorrect number of single-precision registers reported"
+#endif
+
+float a;
+float
+foo ()
+{
+ float b = a + 1.0f;
+ return b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-5.c
new file mode 100644
index 0000000..2d1b129
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-5.c
@@ -0,0 +1,15 @@
+/* Check that we disable odd-numbered single precision registers and can
+ still generate code. */
+/* { dg-options "-mabi=64 -mno-odd-spreg -mhard-float" } */
+
+#if _MIPS_SPFPSET != 32
+#error "Incorrect number of single-precision registers reported"
+#endif
+
+float a;
+float
+foo ()
+{
+ float b = a + 1.0f;
+ return b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-6.c
new file mode 100644
index 0000000..b1e79c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-6.c
@@ -0,0 +1,13 @@
+/* Check that we enable odd-numbered single precision registers. */
+/* { dg-options "-mabi=32 -march=octeon -mhard-float" } */
+
+#if _MIPS_SPFPSET != 32
+#error "Incorrect number of single-precision registers reported"
+#endif
+
+void
+foo ()
+{
+ register float foo asm ("$f1");
+ asm volatile ("" : "=f" (foo));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-7.c
new file mode 100644
index 0000000..89480ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/oddspreg-7.c
@@ -0,0 +1,10 @@
+/* Check that we disable odd-numbered single precision registers for FPXX. */
+/* { dg-skip-if "needs asm output" { *-*-* } { "-fno-fat-lto-objects" } { "" } } */
+/* { dg-options "-mabi=32 -mips32r2 -mfpxx -mhard-float" } */
+
+void
+foo ()
+{
+ register float foo asm ("$f1"); /* { dg-error "isn't suitable for" } */
+ asm volatile ("" : "=f" (foo));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr37362.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr37362.c
index 848d879..2ad4e8d 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr37362.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr37362.c
@@ -1,5 +1,5 @@
/* mips*-sde-elf doesn't have 128-bit long doubles. */
-/* { dg-do compile { target { ! { mips*-sde-elf mips*-mti-elf } } } } */
+/* { dg-do compile { target { ! { mips*-sde-elf mips*-mti-elf mips*-img-elf } } } } */
/* { dg-options "-march=mips64r2 -mabi=n32" } */
typedef float TFtype __attribute__((mode(TF)));
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-1.c
index 606fee0..be3d317 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-1.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mgp64" } */
+/* { dg-options "isa_rev<=5 -mgp64" } */
/* { dg-skip-if "we deliberately use calls when optimizing for size" { *-*-* } { "-Os" } { "" } } */
typedef int int128_t __attribute__((mode(TI)));
typedef unsigned int uint128_t __attribute__((mode(TI)));
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-store16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-store16-1.c
new file mode 100644
index 0000000..6377e85
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-store16-1.c
@@ -0,0 +1,30 @@
+/* { dg-options "(-mmicromips)" } */
+/* { dg-do assemble } */
+
+register unsigned int global asm ("$16");
+
+extern void exit (int) __attribute__((noreturn));
+
+MICROMIPS void
+test_sb (unsigned char *ptr, void (*f) (void))
+{
+ ptr[0] = global;
+ f ();
+ exit (0);
+}
+
+MICROMIPS void
+test_sh (unsigned short *ptr, void (*f) (void))
+{
+ ptr[0] = global;
+ f ();
+ exit (0);
+}
+
+MICROMIPS void
+test_sw (unsigned int *ptr, void (*f) (void))
+{
+ ptr[0] = global;
+ f ();
+ exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-store16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-store16-2.c
new file mode 100644
index 0000000..0748edb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-store16-2.c
@@ -0,0 +1,22 @@
+/* { dg-options "(-mmicromips) -dp" } */
+
+MICROMIPS void
+f1 (unsigned char *ptr)
+{
+ *ptr = 0;
+}
+
+MICROMIPS void
+f2 (unsigned short *ptr)
+{
+ *ptr = 0;
+}
+
+MICROMIPS void
+f3 (unsigned int *ptr)
+{
+ *ptr = 0;
+}
+/* { dg-final { scan-assembler "\tsb\t\\\$0,0\\(\\\$\[0-9\]+\\)\[^\n\]*length = 2" } } */
+/* { dg-final { scan-assembler "\tsh\t\\\$0,0\\(\\\$\[0-9\]+\\)\[^\n\]*length = 2" } } */
+/* { dg-final { scan-assembler "\tsw\t\\\$0,0\\(\\\$\[0-9\]+\\)\[^\n\]*length = 2" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/unaligned-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/unaligned-1.c
index 938f52d..4888ca8 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/mips/unaligned-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/unaligned-1.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mgp64" } */
+/* { dg-options "isa_rev<=5 -mgp64" } */
/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
/* { dg-final { scan-assembler-times "\tsdl\t" 1 } } */
/* { dg-final { scan-assembler-times "\tsdr\t" 1 } } */