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authorYiran Wang <yiran@google.com>2015-06-23 22:33:17 (GMT)
committerYiran Wang <yiran@google.com>2015-06-29 17:56:28 (GMT)
commit1d9fec7937f45dde5e04cac966a2d9a12f2fc15a (patch)
tree3fbcd18a379a05fd6d43491a107e1f36bc61b185 /gcc-4.9/gcc/testsuite/gcc.target
parentf378ebf14df0952eae870c9865bab8326aa8f137 (diff)
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Synchronize with google/gcc-4_9 to r224707 (from r214835)
Change-Id: I3d6f06fc613c8f8b6a82143dc44b7338483aac5d
Diffstat (limited to 'gcc-4.9/gcc/testsuite/gcc.target')
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/madd_after_asm_1.c14
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62040.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62262.c20
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr63424.c39
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c366
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/sisd-shft-neg_1.c38
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c4
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c4
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c4
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr63633-ice-mult.c37
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/h8300/h8300.exp41
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr.c20
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr2.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-pr64286.c37
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c6
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c4
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi-2.c67
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-4.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/memset-strategy-2.c10
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-1.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-2.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-3.c12
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-4.c11
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-1.c11
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-2.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-3.c14
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-4.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr57003.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr59927.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr60516.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr63285.c28
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr63448.c120
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr63495.c6
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr63538.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr63661.c80
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr63947.c9
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr64409.c6
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/i386/pr64513.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-20.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-6.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/builtins-1.c166
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/builtins-2.c47
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr63335.c30
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr64505.c231
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-1.c35
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-10.c42
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-11.c53
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-12.c56
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-13.c54
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-14.c43
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-15.c51
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-16.c57
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-17.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-2.c41
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-3.c43
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-4.c45
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-5.c45
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-6.c32
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-7.c38
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-8.c40
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-9.c42
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c2
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c8
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/powerpc/warn-lvsl-lvsr.c14
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c6
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20.c10
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/sh/pr64507.c25
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr63783-1.c29
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr63783-2.c29
74 files changed, 2213 insertions, 312 deletions
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/madd_after_asm_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/madd_after_asm_1.c
index 523941d..321d8f0 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/madd_after_asm_1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/madd_after_asm_1.c
@@ -12,3 +12,17 @@ test (int a, double b, int c, int d, int e)
);
return c * d + e;
}
+/* { dg-do assemble } */
+/* { dg-options "-O2 -mfix-cortex-a53-835769" } */
+
+int
+test (int a, double b, int c, int d, int e)
+{
+ double result;
+ __asm__ __volatile ("// %0, %1"
+ : "=w" (result)
+ : "0" (b)
+ : /* No clobbers */
+ );
+ return c * d + e;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62040.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62040.c
index cfb4979..c6cae4d 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62040.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62040.c
@@ -19,3 +19,24 @@ foo ()
int32x4_t out = vtrn1q_s32 (xxx, xxx);
bar (out);
}
+/* { dg-do compile } */
+/* { dg-options "-g -Os" } */
+
+#include "arm_neon.h"
+
+extern void bar (int32x4_t);
+
+void
+foo ()
+{
+ int32x4x4_t rows;
+ uint64x2x2_t row01;
+
+ row01.val[0] = vreinterpretq_u64_s32 (rows.val[0]);
+ row01.val[1] = vreinterpretq_u64_s32 (rows.val[1]);
+ uint64x1_t row3l = vget_low_u64 (row01.val[0]);
+ row01.val[0] = vcombine_u64 (vget_low_u64 (row01.val[1]), row3l);
+ int32x4_t xxx = vreinterpretq_s32_u64 (row01.val[0]);
+ int32x4_t out = vtrn1q_s32 (xxx, xxx);
+ bar (out);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62262.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62262.c
index 5bf90bf..20763b4 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62262.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr62262.c
@@ -18,3 +18,23 @@ int foo(int value)
int packed = (unsigned)(value << 9) >> 9;
return packed;
}
+/* { dg-do compile } */
+/* { dg-options "-O2 -fprofile-use" } */
+
+static inline int CLZ(int mask) {
+ return mask ? __builtin_clz(mask) : 32;
+}
+
+int foo(int value)
+{
+ if (value == 0)
+ return 0;
+
+ int bias = CLZ(value);
+ value >>= bias;
+ int zeros = CLZ(value << 1);
+ value <<= zeros;
+
+ int packed = (unsigned)(value << 9) >> 9;
+ return packed;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr63424.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr63424.c
new file mode 100644
index 0000000..c6bd762
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr63424.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#include <stdint.h>
+
+uint32_t
+truncate_int (const unsigned long long value)
+{
+ if ( value < 0 )
+ {
+ return 0;
+ }
+ else if ( value > UINT32_MAX )
+ {
+ return UINT32_MAX;
+ }
+ else
+ return (uint32_t)value;
+}
+
+uint32_t
+mul (const unsigned long long x, const unsigned long long y)
+{
+ uint32_t value = truncate_int (x * y);
+ return value;
+}
+
+uint32_t *
+test(unsigned size, uint32_t *a, uint32_t s)
+{
+ unsigned i;
+
+ for (i = 0; i < size; i++)
+ {
+ a[i] = mul (a[i], s);
+ }
+
+ return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
index 782f6d1..d1980bc 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
@@ -195,20 +195,20 @@ test_vcltzd_s64 (int64x1_t a)
/* { dg-final { scan-assembler-times "aarch64_get_lanev16qi" 2 } } */
-int8x1_t
+int8_t
test_vdupb_lane_s8 (int8x16_t a)
{
- int8x1_t res;
+ int8_t res;
force_simd (a);
res = vdupb_laneq_s8 (a, 2);
force_simd (res);
return res;
}
-uint8x1_t
+uint8_t
test_vdupb_lane_u8 (uint8x16_t a)
{
- uint8x1_t res;
+ uint8_t res;
force_simd (a);
res = vdupb_laneq_u8 (a, 2);
force_simd (res);
@@ -217,20 +217,20 @@ test_vdupb_lane_u8 (uint8x16_t a)
/* { dg-final { scan-assembler-times "aarch64_get_lanev8hi" 2 } } */
-int16x1_t
+int16_t
test_vduph_lane_s16 (int16x8_t a)
{
- int16x1_t res;
+ int16_t res;
force_simd (a);
res = vduph_laneq_s16 (a, 2);
force_simd (res);
return res;
}
-uint16x1_t
+uint16_t
test_vduph_lane_u16 (uint16x8_t a)
{
- uint16x1_t res;
+ uint16_t res;
force_simd (a);
res = vduph_laneq_u16 (a, 2);
force_simd (res);
@@ -239,20 +239,20 @@ test_vduph_lane_u16 (uint16x8_t a)
/* { dg-final { scan-assembler-times "aarch64_get_lanev4si" 2 } } */
-int32x1_t
+int32_t
test_vdups_lane_s32 (int32x4_t a)
{
- int32x1_t res;
+ int32_t res;
force_simd (a);
res = vdups_laneq_s32 (a, 2);
force_simd (res);
return res;
}
-uint32x1_t
+uint32_t
test_vdups_lane_u32 (uint32x4_t a)
{
- uint32x1_t res;
+ uint32_t res;
force_simd (a);
res = vdups_laneq_u32 (a, 2);
force_simd (res);
@@ -322,24 +322,24 @@ test_vqaddd_u64 (uint64x1_t a, uint64x1_t b)
/* { dg-final { scan-assembler-times "\\tuqadd\\ts\[0-9\]+" 1 } } */
-uint32x1_t
-test_vqadds_u32 (uint32x1_t a, uint32x1_t b)
+uint32_t
+test_vqadds_u32 (uint32_t a, uint32_t b)
{
return vqadds_u32 (a, b);
}
/* { dg-final { scan-assembler-times "\\tuqadd\\th\[0-9\]+" 1 } } */
-uint16x1_t
-test_vqaddh_u16 (uint16x1_t a, uint16x1_t b)
+uint16_t
+test_vqaddh_u16 (uint16_t a, uint16_t b)
{
return vqaddh_u16 (a, b);
}
/* { dg-final { scan-assembler-times "\\tuqadd\\tb\[0-9\]+" 1 } } */
-uint8x1_t
-test_vqaddb_u8 (uint8x1_t a, uint8x1_t b)
+uint8_t
+test_vqaddb_u8 (uint8_t a, uint8_t b)
{
return vqaddb_u8 (a, b);
}
@@ -354,40 +354,40 @@ test_vqaddd_s64 (int64x1_t a, int64x1_t b)
/* { dg-final { scan-assembler-times "\\tsqadd\\ts\[0-9\]+, s\[0-9\]+" 1 } } */
-int32x1_t
-test_vqadds_s32 (int32x1_t a, int32x1_t b)
+int32_t
+test_vqadds_s32 (int32_t a, int32_t b)
{
return vqadds_s32 (a, b);
}
/* { dg-final { scan-assembler-times "\\tsqadd\\th\[0-9\]+, h\[0-9\]+" 1 } } */
-int16x1_t
-test_vqaddh_s16 (int16x1_t a, int16x1_t b)
+int16_t
+test_vqaddh_s16 (int16_t a, int16_t b)
{
return vqaddh_s16 (a, b);
}
/* { dg-final { scan-assembler-times "\\tsqadd\\tb\[0-9\]+, b\[0-9\]+" 1 } } */
-int8x1_t
-test_vqaddb_s8 (int8x1_t a, int8x1_t b)
+int8_t
+test_vqaddb_s8 (int8_t a, int8_t b)
{
return vqaddb_s8 (a, b);
}
/* { dg-final { scan-assembler-times "\\tsqdmlal\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
-int32x1_t
-test_vqdmlalh_s16 (int32x1_t a, int16x1_t b, int16x1_t c)
+int32_t
+test_vqdmlalh_s16 (int32_t a, int16_t b, int16_t c)
{
return vqdmlalh_s16 (a, b, c);
}
/* { dg-final { scan-assembler-times "\\tsqdmlal\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */
-int32x1_t
-test_vqdmlalh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c)
+int32_t
+test_vqdmlalh_lane_s16 (int32_t a, int16_t b, int16x4_t c)
{
return vqdmlalh_lane_s16 (a, b, c, 3);
}
@@ -395,7 +395,7 @@ test_vqdmlalh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c)
/* { dg-final { scan-assembler-times "\\tsqdmlal\\td\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
int64x1_t
-test_vqdmlals_s32 (int64x1_t a, int32x1_t b, int32x1_t c)
+test_vqdmlals_s32 (int64x1_t a, int32_t b, int32_t c)
{
return vqdmlals_s32 (a, b, c);
}
@@ -403,23 +403,23 @@ test_vqdmlals_s32 (int64x1_t a, int32x1_t b, int32x1_t c)
/* { dg-final { scan-assembler-times "\\tsqdmlal\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */
int64x1_t
-test_vqdmlals_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c)
+test_vqdmlals_lane_s32 (int64x1_t a, int32_t b, int32x2_t c)
{
return vqdmlals_lane_s32 (a, b, c, 1);
}
/* { dg-final { scan-assembler-times "\\tsqdmlsl\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
-int32x1_t
-test_vqdmlslh_s16 (int32x1_t a, int16x1_t b, int16x1_t c)
+int32_t
+test_vqdmlslh_s16 (int32_t a, int16_t b, int16_t c)
{
return vqdmlslh_s16 (a, b, c);
}
/* { dg-final { scan-assembler-times "\\tsqdmlsl\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */
-int32x1_t
-test_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c)
+int32_t
+test_vqdmlslh_lane_s16 (int32_t a, int16_t b, int16x4_t c)
{
return vqdmlslh_lane_s16 (a, b, c, 3);
}
@@ -427,7 +427,7 @@ test_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c)
/* { dg-final { scan-assembler-times "\\tsqdmlsl\\td\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
int64x1_t
-test_vqdmlsls_s32 (int64x1_t a, int32x1_t b, int32x1_t c)
+test_vqdmlsls_s32 (int64x1_t a, int32_t b, int32_t c)
{
return vqdmlsls_s32 (a, b, c);
}
@@ -435,55 +435,55 @@ test_vqdmlsls_s32 (int64x1_t a, int32x1_t b, int32x1_t c)
/* { dg-final { scan-assembler-times "\\tsqdmlsl\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */
int64x1_t
-test_vqdmlsls_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c)
+test_vqdmlsls_lane_s32 (int64x1_t a, int32_t b, int32x2_t c)
{
return vqdmlsls_lane_s32 (a, b, c, 1);
}
/* { dg-final { scan-assembler-times "\\tsqdmulh\\th\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
-int16x1_t
-test_vqdmulhh_s16 (int16x1_t a, int16x1_t b)
+int16_t
+test_vqdmulhh_s16 (int16_t a, int16_t b)
{
return vqdmulhh_s16 (a, b);
}
/* { dg-final { scan-assembler-times "\\tsqdmulh\\th\[0-9\]+, h\[0-9\]+, v" 1 } } */
-int16x1_t
-test_vqdmulhh_lane_s16 (int16x1_t a, int16x4_t b)
+int16_t
+test_vqdmulhh_lane_s16 (int16_t a, int16x4_t b)
{
return vqdmulhh_lane_s16 (a, b, 3);
}
/* { dg-final { scan-assembler-times "\\tsqdmulh\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
-int32x1_t
-test_vqdmulhs_s32 (int32x1_t a, int32x1_t b)
+int32_t
+test_vqdmulhs_s32 (int32_t a, int32_t b)
{
return vqdmulhs_s32 (a, b);
}
/* { dg-final { scan-assembler-times "\\tsqdmulh\\ts\[0-9\]+, s\[0-9\]+, v" 1 } } */
-int32x1_t
-test_vqdmulhs_lane_s32 (int32x1_t a, int32x2_t b)
+int32_t
+test_vqdmulhs_lane_s32 (int32_t a, int32x2_t b)
{
return vqdmulhs_lane_s32 (a, b, 1);
}
/* { dg-final { scan-assembler-times "\\tsqdmull\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
-int32x1_t
-test_vqdmullh_s16 (int16x1_t a, int16x1_t b)
+int32_t
+test_vqdmullh_s16 (int16_t a, int16_t b)
{
return vqdmullh_s16 (a, b);
}
/* { dg-final { scan-assembler-times "\\tsqdmull\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */
-int32x1_t
-test_vqdmullh_lane_s16 (int16x1_t a, int16x4_t b)
+int32_t
+test_vqdmullh_lane_s16 (int16_t a, int16x4_t b)
{
return vqdmullh_lane_s16 (a, b, 3);
}
@@ -491,7 +491,7 @@ test_vqdmullh_lane_s16 (int16x1_t a, int16x4_t b)
/* { dg-final { scan-assembler-times "\\tsqdmull\\td\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
int64x1_t
-test_vqdmulls_s32 (int32x1_t a, int32x1_t b)
+test_vqdmulls_s32 (int32_t a, int32_t b)
{
return vqdmulls_s32 (a, b);
}
@@ -499,63 +499,63 @@ test_vqdmulls_s32 (int32x1_t a, int32x1_t b)
/* { dg-final { scan-assembler-times "\\tsqdmull\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */
int64x1_t
-test_vqdmulls_lane_s32 (int32x1_t a, int32x2_t b)
+test_vqdmulls_lane_s32 (int32_t a, int32x2_t b)
{
return vqdmulls_lane_s32 (a, b, 1);
}
/* { dg-final { scan-assembler-times "\\tsqrdmulh\\th\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
-int16x1_t
-test_vqrdmulhh_s16 (int16x1_t a, int16x1_t b)
+int16_t
+test_vqrdmulhh_s16 (int16_t a, int16_t b)
{
return vqrdmulhh_s16 (a, b);
}
/* { dg-final { scan-assembler-times "\\tsqrdmulh\\th\[0-9\]+, h\[0-9\]+, v" 1 } } */
-int16x1_t
-test_vqrdmulhh_lane_s16 (int16x1_t a, int16x4_t b)
+int16_t
+test_vqrdmulhh_lane_s16 (int16_t a, int16x4_t b)
{
return vqrdmulhh_lane_s16 (a, b, 3);
}
/* { dg-final { scan-assembler-times "\\tsqrdmulh\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
-int32x1_t
-test_vqrdmulhs_s32 (int32x1_t a, int32x1_t b)
+int32_t
+test_vqrdmulhs_s32 (int32_t a, int32_t b)
{
return vqrdmulhs_s32 (a, b);
}
/* { dg-final { scan-assembler-times "\\tsqrdmulh\\ts\[0-9\]+, s\[0-9\]+, v" 1 } } */
-int32x1_t
-test_vqrdmulhs_lane_s32 (int32x1_t a, int32x2_t b)
+int32_t
+test_vqrdmulhs_lane_s32 (int32_t a, int32x2_t b)
{
return vqrdmulhs_lane_s32 (a, b, 1);
}
/* { dg-final { scan-assembler-times "\\tsuqadd\\tb\[0-9\]+" 1 } } */
-int8x1_t
-test_vuqaddb_s8 (int8x1_t a, int8x1_t b)
+int8_t
+test_vuqaddb_s8 (int8_t a, int8_t b)
{
return vuqaddb_s8 (a, b);
}
/* { dg-final { scan-assembler-times "\\tsuqadd\\th\[0-9\]+" 1 } } */
-int16x1_t
-test_vuqaddh_s16 (int16x1_t a, int8x1_t b)
+int16_t
+test_vuqaddh_s16 (int16_t a, int8_t b)
{
return vuqaddh_s16 (a, b);
}
/* { dg-final { scan-assembler-times "\\tsuqadd\\ts\[0-9\]+" 1 } } */
-int32x1_t
-test_vuqadds_s32 (int32x1_t a, int8x1_t b)
+int32_t
+test_vuqadds_s32 (int32_t a, int8_t b)
{
return vuqadds_s32 (a, b);
}
@@ -563,31 +563,31 @@ test_vuqadds_s32 (int32x1_t a, int8x1_t b)
/* { dg-final { scan-assembler-times "\\tsuqadd\\td\[0-9\]+" 1 } } */
int64x1_t
-test_vuqaddd_s64 (int64x1_t a, int8x1_t b)
+test_vuqaddd_s64 (int64x1_t a, int8_t b)
{
return vuqaddd_s64 (a, b);
}
/* { dg-final { scan-assembler-times "\\tusqadd\\tb\[0-9\]+" 1 } } */
-uint8x1_t
-test_vsqaddb_u8 (uint8x1_t a, int8x1_t b)
+uint8_t
+test_vsqaddb_u8 (uint8_t a, int8_t b)
{
return vsqaddb_u8 (a, b);
}
/* { dg-final { scan-assembler-times "\\tusqadd\\th\[0-9\]+" 1 } } */
-uint16x1_t
-test_vsqaddh_u16 (uint16x1_t a, int8x1_t b)
+uint16_t
+test_vsqaddh_u16 (uint16_t a, int8_t b)
{
return vsqaddh_u16 (a, b);
}
/* { dg-final { scan-assembler-times "\\tusqadd\\ts\[0-9\]+" 1 } } */
-uint32x1_t
-test_vsqadds_u32 (uint32x1_t a, int8x1_t b)
+uint32_t
+test_vsqadds_u32 (uint32_t a, int8_t b)
{
return vsqadds_u32 (a, b);
}
@@ -595,78 +595,78 @@ test_vsqadds_u32 (uint32x1_t a, int8x1_t b)
/* { dg-final { scan-assembler-times "\\tusqadd\\td\[0-9\]+" 1 } } */
uint64x1_t
-test_vsqaddd_u64 (uint64x1_t a, int8x1_t b)
+test_vsqaddd_u64 (uint64x1_t a, int8_t b)
{
return vsqaddd_u64 (a, b);
}
/* { dg-final { scan-assembler-times "\\tsqabs\\tb\[0-9\]+" 1 } } */
-int8x1_t
-test_vqabsb_s8 (int8x1_t a)
+int8_t
+test_vqabsb_s8 (int8_t a)
{
return vqabsb_s8 (a);
}
/* { dg-final { scan-assembler-times "\\tsqabs\\th\[0-9\]+" 1 } } */
-int16x1_t
-test_vqabsh_s16 (int16x1_t a)
+int16_t
+test_vqabsh_s16 (int16_t a)
{
return vqabsh_s16 (a);
}
/* { dg-final { scan-assembler-times "\\tsqabs\\ts\[0-9\]+" 1 } } */
-int32x1_t
-test_vqabss_s32 (int32x1_t a)
+int32_t
+test_vqabss_s32 (int32_t a)
{
return vqabss_s32 (a);
}
/* { dg-final { scan-assembler-times "\\tsqneg\\tb\[0-9\]+" 1 } } */
-int8x1_t
-test_vqnegb_s8 (int8x1_t a)
+int8_t
+test_vqnegb_s8 (int8_t a)
{
return vqnegb_s8 (a);
}
/* { dg-final { scan-assembler-times "\\tsqneg\\th\[0-9\]+" 1 } } */
-int16x1_t
-test_vqnegh_s16 (int16x1_t a)
+int16_t
+test_vqnegh_s16 (int16_t a)
{
return vqnegh_s16 (a);
}
/* { dg-final { scan-assembler-times "\\tsqneg\\ts\[0-9\]+" 1 } } */
-int32x1_t
-test_vqnegs_s32 (int32x1_t a)
+int32_t
+test_vqnegs_s32 (int32_t a)
{
return vqnegs_s32 (a);
}
/* { dg-final { scan-assembler-times "\\tsqxtun\\tb\[0-9\]+" 1 } } */
-int8x1_t
-test_vqmovunh_s16 (int16x1_t a)
+int8_t
+test_vqmovunh_s16 (int16_t a)
{
return vqmovunh_s16 (a);
}
/* { dg-final { scan-assembler-times "\\tsqxtun\\th\[0-9\]+" 1 } } */
-int16x1_t
-test_vqmovuns_s32 (int32x1_t a)
+int16_t
+test_vqmovuns_s32 (int32_t a)
{
return vqmovuns_s32 (a);
}
/* { dg-final { scan-assembler-times "\\tsqxtun\\ts\[0-9\]+" 1 } } */
-int32x1_t
+int32_t
test_vqmovund_s64 (int64x1_t a)
{
return vqmovund_s64 (a);
@@ -674,23 +674,23 @@ test_vqmovund_s64 (int64x1_t a)
/* { dg-final { scan-assembler-times "\\tsqxtn\\tb\[0-9\]+" 1 } } */
-int8x1_t
-test_vqmovnh_s16 (int16x1_t a)
+int8_t
+test_vqmovnh_s16 (int16_t a)
{
return vqmovnh_s16 (a);
}
/* { dg-final { scan-assembler-times "\\tsqxtn\\th\[0-9\]+" 1 } } */
-int16x1_t
-test_vqmovns_s32 (int32x1_t a)
+int16_t
+test_vqmovns_s32 (int32_t a)
{
return vqmovns_s32 (a);
}
/* { dg-final { scan-assembler-times "\\tsqxtn\\ts\[0-9\]+" 1 } } */
-int32x1_t
+int32_t
test_vqmovnd_s64 (int64x1_t a)
{
return vqmovnd_s64 (a);
@@ -698,23 +698,23 @@ test_vqmovnd_s64 (int64x1_t a)
/* { dg-final { scan-assembler-times "\\tuqxtn\\tb\[0-9\]+" 1 } } */
-uint8x1_t
-test_vqmovnh_u16 (uint16x1_t a)
+uint8_t
+test_vqmovnh_u16 (uint16_t a)
{
return vqmovnh_u16 (a);
}
/* { dg-final { scan-assembler-times "\\tuqxtn\\th\[0-9\]+" 1 } } */
-uint16x1_t
-test_vqmovns_u32 (uint32x1_t a)
+uint16_t
+test_vqmovns_u32 (uint32_t a)
{
return vqmovns_u32 (a);
}
/* { dg-final { scan-assembler-times "\\tuqxtn\\ts\[0-9\]+" 1 } } */
-uint32x1_t
+uint32_t
test_vqmovnd_u64 (uint64x1_t a)
{
return vqmovnd_u64 (a);
@@ -753,24 +753,24 @@ test_vqsubd_u64 (uint64x1_t a, uint64x1_t b)
/* { dg-final { scan-assembler-times "\\tuqsub\\ts\[0-9\]+" 1 } } */
-uint32x1_t
-test_vqsubs_u32 (uint32x1_t a, uint32x1_t b)
+uint32_t
+test_vqsubs_u32 (uint32_t a, uint32_t b)
{
return vqsubs_u32 (a, b);
}
/* { dg-final { scan-assembler-times "\\tuqsub\\th\[0-9\]+" 1 } } */
-uint16x1_t
-test_vqsubh_u16 (uint16x1_t a, uint16x1_t b)
+uint16_t
+test_vqsubh_u16 (uint16_t a, uint16_t b)
{
return vqsubh_u16 (a, b);
}
/* { dg-final { scan-assembler-times "\\tuqsub\\tb\[0-9\]+" 1 } } */
-uint8x1_t
-test_vqsubb_u8 (uint8x1_t a, uint8x1_t b)
+uint8_t
+test_vqsubb_u8 (uint8_t a, uint8_t b)
{
return vqsubb_u8 (a, b);
}
@@ -785,24 +785,24 @@ test_vqsubd_s64 (int64x1_t a, int64x1_t b)
/* { dg-final { scan-assembler-times "\\tsqsub\\ts\[0-9\]+" 1 } } */
-int32x1_t
-test_vqsubs_s32 (int32x1_t a, int32x1_t b)
+int32_t
+test_vqsubs_s32 (int32_t a, int32_t b)
{
return vqsubs_s32 (a, b);
}
/* { dg-final { scan-assembler-times "\\tsqsub\\th\[0-9\]+" 1 } } */
-int16x1_t
-test_vqsubh_s16 (int16x1_t a, int16x1_t b)
+int16_t
+test_vqsubh_s16 (int16_t a, int16_t b)
{
return vqsubh_s16 (a, b);
}
/* { dg-final { scan-assembler-times "\\tsqsub\\tb\[0-9\]+" 1 } } */
-int8x1_t
-test_vqsubb_s8 (int8x1_t a, int8x1_t b)
+int8_t
+test_vqsubb_s8 (int8_t a, int8_t b)
{
return vqsubb_s8 (a, b);
}
@@ -908,24 +908,24 @@ test_vrsrad_n_u64 (uint64x1_t a, uint64x1_t b)
/* { dg-final { scan-assembler-times "\\tsqrshl\\tb\[0-9\]+" 1 } } */
-int8x1_t
-test_vqrshlb_s8 (int8x1_t a, int8x1_t b)
+int8_t
+test_vqrshlb_s8 (int8_t a, int8_t b)
{
return vqrshlb_s8 (a, b);
}
/* { dg-final { scan-assembler-times "\\tsqrshl\\th\[0-9\]+" 1 } } */
-int16x1_t
-test_vqrshlh_s16 (int16x1_t a, int16x1_t b)
+int16_t
+test_vqrshlh_s16 (int16_t a, int16_t b)
{
return vqrshlh_s16 (a, b);
}
/* { dg-final { scan-assembler-times "\\tsqrshl\\ts\[0-9\]+" 1 } } */
-int32x1_t
-test_vqrshls_s32 (int32x1_t a, int32x1_t b)
+int32_t
+test_vqrshls_s32 (int32_t a, int32_t b)
{
return vqrshls_s32 (a, b);
}
@@ -940,24 +940,24 @@ test_vqrshld_s64 (int64x1_t a, int64x1_t b)
/* { dg-final { scan-assembler-times "\\tuqrshl\\tb\[0-9\]+" 1 } } */
-uint8x1_t
-test_vqrshlb_u8 (uint8x1_t a, uint8x1_t b)
+uint8_t
+test_vqrshlb_u8 (uint8_t a, uint8_t b)
{
return vqrshlb_u8 (a, b);
}
/* { dg-final { scan-assembler-times "\\tuqrshl\\th\[0-9\]+" 1 } } */
-uint16x1_t
-test_vqrshlh_u16 (uint16x1_t a, uint16x1_t b)
+uint16_t
+test_vqrshlh_u16 (uint16_t a, uint16_t b)
{
return vqrshlh_u16 (a, b);
}
/* { dg-final { scan-assembler-times "\\tuqrshl\\ts\[0-9\]+" 1 } } */
-uint32x1_t
-test_vqrshls_u32 (uint32x1_t a, uint32x1_t b)
+uint32_t
+test_vqrshls_u32 (uint32_t a, uint32_t b)
{
return vqrshls_u32 (a, b);
}
@@ -972,24 +972,24 @@ test_vqrshld_u64 (uint64x1_t a, uint64x1_t b)
/* { dg-final { scan-assembler-times "\\tsqshlu\\tb\[0-9\]+" 1 } } */
-int8x1_t
-test_vqshlub_n_s8 (int8x1_t a)
+int8_t
+test_vqshlub_n_s8 (int8_t a)
{
return vqshlub_n_s8 (a, 3);
}
/* { dg-final { scan-assembler-times "\\tsqshlu\\th\[0-9\]+" 1 } } */
-int16x1_t
-test_vqshluh_n_s16 (int16x1_t a)
+int16_t
+test_vqshluh_n_s16 (int16_t a)
{
return vqshluh_n_s16 (a, 4);
}
/* { dg-final { scan-assembler-times "\\tsqshlu\\ts\[0-9\]+" 1 } } */
-int32x1_t
-test_vqshlus_n_s32 (int32x1_t a)
+int32_t
+test_vqshlus_n_s32 (int32_t a)
{
return vqshlus_n_s32 (a, 5);
}
@@ -1004,42 +1004,42 @@ test_vqshlud_n_s64 (int64x1_t a)
/* { dg-final { scan-assembler-times "\\tsqshl\\tb\[0-9\]+" 2 } } */
-int8x1_t
-test_vqshlb_s8 (int8x1_t a, int8x1_t b)
+int8_t
+test_vqshlb_s8 (int8_t a, int8_t b)
{
return vqshlb_s8 (a, b);
}
-int8x1_t
-test_vqshlb_n_s8 (int8x1_t a)
+int8_t
+test_vqshlb_n_s8 (int8_t a)
{
return vqshlb_n_s8 (a, 2);
}
/* { dg-final { scan-assembler-times "\\tsqshl\\th\[0-9\]+" 2 } } */
-int16x1_t
-test_vqshlh_s16 (int16x1_t a, int16x1_t b)
+int16_t
+test_vqshlh_s16 (int16_t a, int16_t b)
{
return vqshlh_s16 (a, b);
}
-int16x1_t
-test_vqshlh_n_s16 (int16x1_t a)
+int16_t
+test_vqshlh_n_s16 (int16_t a)
{
return vqshlh_n_s16 (a, 3);
}
/* { dg-final { scan-assembler-times "\\tsqshl\\ts\[0-9\]+" 2 } } */
-int32x1_t
-test_vqshls_s32 (int32x1_t a, int32x1_t b)
+int32_t
+test_vqshls_s32 (int32_t a, int32_t b)
{
return vqshls_s32 (a, b);
}
-int32x1_t
-test_vqshls_n_s32 (int32x1_t a)
+int32_t
+test_vqshls_n_s32 (int32_t a)
{
return vqshls_n_s32 (a, 4);
}
@@ -1060,42 +1060,42 @@ test_vqshld_n_s64 (int64x1_t a)
/* { dg-final { scan-assembler-times "\\tuqshl\\tb\[0-9\]+" 2 } } */
-uint8x1_t
-test_vqshlb_u8 (uint8x1_t a, uint8x1_t b)
+uint8_t
+test_vqshlb_u8 (uint8_t a, uint8_t b)
{
return vqshlb_u8 (a, b);
}
-uint8x1_t
-test_vqshlb_n_u8 (uint8x1_t a)
+uint8_t
+test_vqshlb_n_u8 (uint8_t a)
{
return vqshlb_n_u8 (a, 2);
}
/* { dg-final { scan-assembler-times "\\tuqshl\\th\[0-9\]+" 2 } } */
-uint16x1_t
-test_vqshlh_u16 (uint16x1_t a, uint16x1_t b)
+uint16_t
+test_vqshlh_u16 (uint16_t a, uint16_t b)
{
return vqshlh_u16 (a, b);
}
-uint16x1_t
-test_vqshlh_n_u16 (uint16x1_t a)
+uint16_t
+test_vqshlh_n_u16 (uint16_t a)
{
return vqshlh_n_u16 (a, 3);
}
/* { dg-final { scan-assembler-times "\\tuqshl\\ts\[0-9\]+" 2 } } */
-uint32x1_t
-test_vqshls_u32 (uint32x1_t a, uint32x1_t b)
+uint32_t
+test_vqshls_u32 (uint32_t a, uint32_t b)
{
return vqshls_u32 (a, b);
}
-uint32x1_t
-test_vqshls_n_u32 (uint32x1_t a)
+uint32_t
+test_vqshls_n_u32 (uint32_t a)
{
return vqshls_n_u32 (a, 4);
}
@@ -1116,23 +1116,23 @@ test_vqshld_n_u64 (uint64x1_t a)
/* { dg-final { scan-assembler-times "\\tsqshrun\\tb\[0-9\]+" 1 } } */
-int8x1_t
-test_vqshrunh_n_s16 (int16x1_t a)
+int8_t
+test_vqshrunh_n_s16 (int16_t a)
{
return vqshrunh_n_s16 (a, 2);
}
/* { dg-final { scan-assembler-times "\\tsqshrun\\th\[0-9\]+" 1 } } */
-int16x1_t
-test_vqshruns_n_s32 (int32x1_t a)
+int16_t
+test_vqshruns_n_s32 (int32_t a)
{
return vqshruns_n_s32 (a, 3);
}
/* { dg-final { scan-assembler-times "\\tsqshrun\\ts\[0-9\]+" 1 } } */
-int32x1_t
+int32_t
test_vqshrund_n_s64 (int64x1_t a)
{
return vqshrund_n_s64 (a, 4);
@@ -1140,23 +1140,23 @@ test_vqshrund_n_s64 (int64x1_t a)
/* { dg-final { scan-assembler-times "\\tsqrshrun\\tb\[0-9\]+" 1 } } */
-int8x1_t
-test_vqrshrunh_n_s16 (int16x1_t a)
+int8_t
+test_vqrshrunh_n_s16 (int16_t a)
{
return vqrshrunh_n_s16 (a, 2);
}
/* { dg-final { scan-assembler-times "\\tsqrshrun\\th\[0-9\]+" 1 } } */
-int16x1_t
-test_vqrshruns_n_s32 (int32x1_t a)
+int16_t
+test_vqrshruns_n_s32 (int32_t a)
{
return vqrshruns_n_s32 (a, 3);
}
/* { dg-final { scan-assembler-times "\\tsqrshrun\\ts\[0-9\]+" 1 } } */
-int32x1_t
+int32_t
test_vqrshrund_n_s64 (int64x1_t a)
{
return vqrshrund_n_s64 (a, 4);
@@ -1164,23 +1164,23 @@ test_vqrshrund_n_s64 (int64x1_t a)
/* { dg-final { scan-assembler-times "\\tsqshrn\\tb\[0-9\]+" 1 } } */
-int8x1_t
-test_vqshrnh_n_s16 (int16x1_t a)
+int8_t
+test_vqshrnh_n_s16 (int16_t a)
{
return vqshrnh_n_s16 (a, 2);
}
/* { dg-final { scan-assembler-times "\\tsqshrn\\th\[0-9\]+" 1 } } */
-int16x1_t
-test_vqshrns_n_s32 (int32x1_t a)
+int16_t
+test_vqshrns_n_s32 (int32_t a)
{
return vqshrns_n_s32 (a, 3);
}
/* { dg-final { scan-assembler-times "\\tsqshrn\\ts\[0-9\]+" 1 } } */
-int32x1_t
+int32_t
test_vqshrnd_n_s64 (int64x1_t a)
{
return vqshrnd_n_s64 (a, 4);
@@ -1188,23 +1188,23 @@ test_vqshrnd_n_s64 (int64x1_t a)
/* { dg-final { scan-assembler-times "\\tuqshrn\\tb\[0-9\]+" 1 } } */
-uint8x1_t
-test_vqshrnh_n_u16 (uint16x1_t a)
+uint8_t
+test_vqshrnh_n_u16 (uint16_t a)
{
return vqshrnh_n_u16 (a, 2);
}
/* { dg-final { scan-assembler-times "\\tuqshrn\\th\[0-9\]+" 1 } } */
-uint16x1_t
-test_vqshrns_n_u32 (uint32x1_t a)
+uint16_t
+test_vqshrns_n_u32 (uint32_t a)
{
return vqshrns_n_u32 (a, 3);
}
/* { dg-final { scan-assembler-times "\\tuqshrn\\ts\[0-9\]+" 1 } } */
-uint32x1_t
+uint32_t
test_vqshrnd_n_u64 (uint64x1_t a)
{
return vqshrnd_n_u64 (a, 4);
@@ -1212,23 +1212,23 @@ test_vqshrnd_n_u64 (uint64x1_t a)
/* { dg-final { scan-assembler-times "\\tsqrshrn\\tb\[0-9\]+" 1 } } */
-int8x1_t
-test_vqrshrnh_n_s16 (int16x1_t a)
+int8_t
+test_vqrshrnh_n_s16 (int16_t a)
{
return vqrshrnh_n_s16 (a, 2);
}
/* { dg-final { scan-assembler-times "\\tsqrshrn\\th\[0-9\]+" 1 } } */
-int16x1_t
-test_vqrshrns_n_s32 (int32x1_t a)
+int16_t
+test_vqrshrns_n_s32 (int32_t a)
{
return vqrshrns_n_s32 (a, 3);
}
/* { dg-final { scan-assembler-times "\\tsqrshrn\\ts\[0-9\]+" 1 } } */
-int32x1_t
+int32_t
test_vqrshrnd_n_s64 (int64x1_t a)
{
return vqrshrnd_n_s64 (a, 4);
@@ -1236,23 +1236,23 @@ test_vqrshrnd_n_s64 (int64x1_t a)
/* { dg-final { scan-assembler-times "\\tuqrshrn\\tb\[0-9\]+" 1 } } */
-uint8x1_t
-test_vqrshrnh_n_u16 (uint16x1_t a)
+uint8_t
+test_vqrshrnh_n_u16 (uint16_t a)
{
return vqrshrnh_n_u16 (a, 2);
}
/* { dg-final { scan-assembler-times "\\tuqrshrn\\th\[0-9\]+" 1 } } */
-uint16x1_t
-test_vqrshrns_n_u32 (uint32x1_t a)
+uint16_t
+test_vqrshrns_n_u32 (uint32_t a)
{
return vqrshrns_n_u32 (a, 3);
}
/* { dg-final { scan-assembler-times "\\tuqrshrn\\ts\[0-9\]+" 1 } } */
-uint32x1_t
+uint32_t
test_vqrshrnd_n_u64 (uint64x1_t a)
{
return vqrshrnd_n_u64 (a, 4);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sisd-shft-neg_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sisd-shft-neg_1.c
new file mode 100644
index 0000000..c091657
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sisd-shft-neg_1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-inline" } */
+
+extern void abort (void);
+
+#define force_simd_si(v) asm volatile ("mov %s0, %1.s[0]" :"=w" (v) :"w" (v) :)
+
+unsigned int
+shft_add (unsigned int a, unsigned int b)
+{
+ unsigned int c;
+
+ force_simd_si (a);
+ force_simd_si (b);
+ c = a >> b;
+ force_simd_si (c);
+
+ return c + b;
+}
+
+int
+main (void)
+{
+ unsigned int i = 0;
+ unsigned int a = 0xdeadbeef;
+
+ for (i = 0; i < 32; i++)
+ {
+ unsigned int exp = (a / (1 << i) + i);
+ unsigned int got = shft_add (a, i);
+
+ if (exp != got)
+ abort ();
+ }
+
+ return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c
index 83f5af5..9ca041c 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c
@@ -5,8 +5,8 @@
#include "arm_neon.h"
-int32x1_t
-t_vqdmlalh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c)
+int32_t
+t_vqdmlalh_lane_s16 (int32_t a, int16_t b, int16x4_t c)
{
return vqdmlalh_lane_s16 (a, b, c, 0);
}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c
index ef94e95..40e4c9f 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c
@@ -6,7 +6,7 @@
#include "arm_neon.h"
int64x1_t
-t_vqdmlals_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c)
+t_vqdmlals_lane_s32 (int64x1_t a, int32_t b, int32x2_t c)
{
return vqdmlals_lane_s32 (a, b, c, 0);
}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c
index 056dfbb..b3bbc95 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c
@@ -5,8 +5,8 @@
#include "arm_neon.h"
-int32x1_t
-t_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c)
+int32_t
+t_vqdmlslh_lane_s16 (int32_t a, int16_t b, int16x4_t c)
{
return vqdmlslh_lane_s16 (a, b, c, 0);
}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c
index 9e351bc..5bd643a 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c
@@ -6,7 +6,7 @@
#include "arm_neon.h"
int64x1_t
-t_vqdmlsls_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c)
+t_vqdmlsls_lane_s32 (int64x1_t a, int32_t b, int32x2_t c)
{
return vqdmlsls_lane_s32 (a, b, c, 0);
}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c
index fd271e0..c3761df 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c
@@ -5,8 +5,8 @@
#include "arm_neon.h"
-int32x1_t
-t_vqdmullh_lane_s16 (int16x1_t a, int16x4_t b)
+int32_t
+t_vqdmullh_lane_s16 (int16_t a, int16x4_t b)
{
return vqdmullh_lane_s16 (a, b, 0);
}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c
index 1103333..6ed8e3a 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c
@@ -6,7 +6,7 @@
#include "arm_neon.h"
int64x1_t
-t_vqdmulls_lane_s32 (int32x1_t a, int32x2_t b)
+t_vqdmulls_lane_s32 (int32_t a, int32x2_t b)
{
return vqdmulls_lane_s32 (a, b, 0);
}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr63633-ice-mult.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr63633-ice-mult.c
new file mode 100644
index 0000000..a523424
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr63633-ice-mult.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+
+void ice_mult32 (int x)
+{
+ register long reg __asm ("22");
+ __asm volatile (" " :: "r" (reg = 0x12345 * x));
+}
+
+void ice_mult24 (int x)
+{
+ register __int24 reg __asm ("20");
+ __asm volatile (" " :: "r" (reg = 0x12345 * x));
+}
+
+void ice_sh24 (__int24 x)
+{
+ register __int24 reg __asm ("20");
+ __asm volatile (" " :: "r" (reg = x << 3));
+}
+
+void ice_sh24b (__int24 x)
+{
+ register __int24 reg __asm ("20");
+ __asm volatile (" " :: "r" (reg = x << 22));
+}
+
+void ice_s16s16 (int x)
+{
+ register long reg __asm ("20");
+ __asm volatile (" " :: "r" (reg = (long) x*x));
+}
+
+void ice_u16s16 (int x)
+{
+ register long reg __asm ("20");
+ __asm volatile (" " :: "r" (reg = (long) x*0x1234u));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/h8300/h8300.exp b/gcc-4.9/gcc/testsuite/gcc.target/h8300/h8300.exp
index 8523a12..63579f6 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/h8300/h8300.exp
+++ b/gcc-4.9/gcc/testsuite/gcc.target/h8300/h8300.exp
@@ -39,44 +39,3 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
# All done.
dg-finish
-# Copyright (C) 2013-2014 Free Software Foundation, Inc.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with GCC; see the file COPYING3. If not see
-# <http://www.gnu.org/licenses/>.
-
-# GCC testsuite that uses the `dg.exp' driver.
-
-# Exit immediately if this isn't a h8300 target.
-if ![istarget h8300*-*-*] then {
- return
-}
-
-# Load support procs.
-load_lib gcc-dg.exp
-
-# If a testcase doesn't have special options, use these.
-global DEFAULT_CFLAGS
-if ![info exists DEFAULT_CFLAGS] then {
- set DEFAULT_CFLAGS " -ansi -pedantic-errors"
-}
-
-# Initialize `dg'.
-dg-init
-
-# Main loop.
-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
- "" $DEFAULT_CFLAGS
-
-# All done.
-dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr.c b/gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr.c
index 24fba30..41bd78e 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr.c
@@ -18,23 +18,3 @@ isr2 (void)
{
foo ();
}
-/* Check whether rte is generated for two ISRs. */
-/* { dg-do compile { target h8300-*-* } } */
-/* { dg-options "-O3" } */
-/* { dg-final { scan-assembler-times "rte" 2} } */
-
-extern void foo (void);
-
-#pragma interrupt
-void
-isr1 (void)
-{
- foo ();
-}
-
-#pragma interrupt
-void
-isr2 (void)
-{
- foo ();
-}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr2.c b/gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr2.c
index 7c242ec..3d0a126 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr2.c
@@ -19,24 +19,3 @@ main (void)
{
return 0;
}
-/* Check whether rte is generated only for an ISR. */
-/* { dg-do compile { target h8300-*-* } } */
-/* { dg-options "-O" } */
-/* { dg-final { scan-assembler-times "rte" 1 } } */
-
-#pragma interrupt
-void
-isr (void)
-{
-}
-
-void
-delay (int a)
-{
-}
-
-int
-main (void)
-{
- return 0;
-}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-pr64286.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-pr64286.c
new file mode 100644
index 0000000..2edb321
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-pr64286.c
@@ -0,0 +1,37 @@
+/* PR rtl-optimization/64286 */
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include <string.h>
+#include <stdlib.h>
+#include <x86intrin.h>
+#include "avx2-check.h"
+
+__m128i v;
+__m256i w;
+
+__attribute__((noinline, noclone)) void
+foo (__m128i *p, __m128i *q)
+{
+ __m128i a = _mm_loadu_si128 (p);
+ __m128i b = _mm_xor_si128 (a, v);
+ w = _mm256_cvtepu8_epi16 (a);
+ *q = b;
+}
+
+static void
+avx2_test (void)
+{
+ v = _mm_set1_epi8 (0x40);
+ __m128i c = _mm_set_epi8 (16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
+ __m128i d;
+ foo (&c, &d);
+ __m128i e = _mm_set_epi8 (0x50, 0x4f, 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49,
+ 0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41);
+ __m256i f = _mm256_set_epi16 (16, 15, 14, 13, 12, 11, 10, 9,
+ 8, 7, 6, 5, 4, 3, 2, 1);
+ if (memcmp (&w, &f, sizeof (w)) != 0
+ || memcmp (&d, &e, sizeof (d)) != 0)
+ abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c
index ad16a53..d8730dc 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c
@@ -33,7 +33,7 @@ avx_test (void)
cp = mp;
dp = lp;
- for (i = N; i >= 0; i--)
+ for (i = N; i > 0; i--)
{
*cp++ = str;
*dp++ = str;
@@ -44,13 +44,13 @@ avx_test (void)
cp = mp;
dp = lp;
- for (i = N; i >= 0; i--)
+ for (i = N; i > 0; i--)
{
*ap++ = *cp++;
*bp++ = *dp++;
}
- for (i = N; i >= 0; i--)
+ for (i = N; i > 0; i--)
{
if (strcmp (*--ap, "STR") != 0)
abort ();
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c
index 4272dc3..5ec1494 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c
@@ -29,13 +29,13 @@ avx_test (void)
ap = ep;
bp = fp;
- for (i = N; i >= 0; i--)
+ for (i = N; i > 0; i--)
{
*ap++ = str;
*bp++ = str;
}
- for (i = N; i >= 0; i--)
+ for (i = N; i > 0; i--)
{
if (strcmp (*--ap, "STR") != 0)
abort ();
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi-2.c
new file mode 100644
index 0000000..34579d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi-2.c
@@ -0,0 +1,67 @@
+/* PR target/65368 */
+/* { dg-do assemble { target bmi2 } } */
+/* { dg-options "-O2 -mbmi2" } */
+
+#include <x86intrin.h>
+#include "bmi2-check.h"
+
+unsigned int a;
+unsigned long long b;
+
+#define A __attribute__((noinline, noclone))
+
+A unsigned int f1 (void) { return _bzhi_u32 (a, 0); }
+A unsigned int f2 (unsigned int x) { return _bzhi_u32 (x, 0); }
+A unsigned int f3 (void) { return _bzhi_u32 (a, 5); }
+A unsigned int f4 (unsigned int x) { return _bzhi_u32 (x, 5); }
+A unsigned int f5 (void) { return _bzhi_u32 (a, 31); }
+A unsigned int f6 (unsigned int x) { return _bzhi_u32 (x, 31); }
+A unsigned int f7 (void) { return _bzhi_u32 (a, 32); }
+A unsigned int f8 (unsigned int x) { return _bzhi_u32 (x, 32); }
+A unsigned int f9 (void) { return _bzhi_u32 (a, 37); }
+A unsigned int f10 (unsigned int x) { return _bzhi_u32 (x, 37); }
+A unsigned int f11 (void) { return _bzhi_u32 (a, 257); }
+A unsigned int f12 (unsigned int x) { return _bzhi_u32 (x, 257); }
+A unsigned int f13 (void) { return _bzhi_u32 (a, 289); }
+A unsigned int f14 (unsigned int x) { return _bzhi_u32 (x, 289); }
+#ifdef __x86_64__
+A unsigned long long f21 (void) { return _bzhi_u64 (b, 0); }
+A unsigned long long f22 (unsigned long long x) { return _bzhi_u64 (x, 0); }
+A unsigned long long f23 (void) { return _bzhi_u64 (b, 5); }
+A unsigned long long f24 (unsigned long long x) { return _bzhi_u64 (x, 5); }
+A unsigned long long f25 (void) { return _bzhi_u64 (b, 63); }
+A unsigned long long f26 (unsigned long long x) { return _bzhi_u64 (x, 63); }
+A unsigned long long f27 (void) { return _bzhi_u64 (b, 64); }
+A unsigned long long f28 (unsigned long long x) { return _bzhi_u64 (x, 64); }
+A unsigned long long f29 (void) { return _bzhi_u64 (b, 69); }
+A unsigned long long f30 (unsigned long long x) { return _bzhi_u64 (x, 69); }
+A unsigned long long f31 (void) { return _bzhi_u64 (b, 257); }
+A unsigned long long f32 (unsigned long long x) { return _bzhi_u64 (x, 257); }
+A unsigned long long f33 (void) { return _bzhi_u64 (b, 321); }
+A unsigned long long f34 (unsigned long long x) { return _bzhi_u64 (x, 321); }
+#endif
+
+static void
+bmi2_test ()
+{
+ a = -1U;
+ b = -1ULL;
+ if (f1 () != 0 || f2 (-1U) != 0
+ || f3 () != 0x1f || f4 (-1U) != 0x1f
+ || f5 () != 0x7fffffffU || f6 (-1U) != 0x7fffffffU
+ || f7 () != -1U || f8 (-1U) != -1U
+ || f9 () != -1U || f10 (-1U) != -1U
+ || f11 () != 1 || f12 (-1U) != 1
+ || f13 () != -1U || f14 (-1U) != -1U)
+ abort ();
+#ifdef __x86_64__
+ if (f21 () != 0 || f22 (-1ULL) != 0
+ || f23 () != 0x1f || f24 (-1ULL) != 0x1f
+ || f25 () != 0x7fffffffffffffffULL || f26 (-1ULL) != 0x7fffffffffffffffULL
+ || f27 () != -1ULL || f28 (-1ULL) != -1ULL
+ || f29 () != -1ULL || f30 (-1ULL) != -1ULL
+ || f31 () != 1 || f32 (-1ULL) != 1
+ || f33 () != -1ULL || f34 (-1ULL) != -1ULL)
+ abort ();
+#endif
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-4.c
new file mode 100644
index 0000000..5c51248
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-4.c
@@ -0,0 +1,21 @@
+/* PR target/64200 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=atom -mmemcpy-strategy=libcall:-1:align -minline-stringops-dynamically" } */
+
+#include <stdarg.h>
+
+extern void bar(char *x);
+
+void foo (int size, ...)
+{
+ struct
+ {
+ char x[size];
+ } d;
+
+ va_list ap;
+ va_start(ap, size);
+ d = va_arg(ap, typeof (d));
+ va_end(ap);
+ bar(d.x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-strategy-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-strategy-2.c
new file mode 100644
index 0000000..aafa54d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-strategy-2.c
@@ -0,0 +1,10 @@
+/* PR target/64108 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=atom -mmemset-strategy=libcall:-1:align -minline-all-stringops" } */
+
+char a[2048];
+void t (void)
+{
+ __builtin_memset (a, 1, 2048);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-1.c
new file mode 100644
index 0000000..d9e5d6e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target x86_64-*-linux* } } */
+/* { dg-options "-fno-pic" } */
+
+__attribute__ ((noplt))
+void foo();
+
+int main()
+{
+ foo();
+ return 0;
+}
+
+/* { dg-final { scan-assembler "call\[ \t\]\\*.*foo.*@GOTPCREL\\(%rip\\)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-2.c
new file mode 100644
index 0000000..4df0618
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target x86_64-*-linux* } } */
+/* { dg-options "-O2 -fno-pic" } */
+
+
+__attribute__ ((noplt))
+int foo();
+
+int main()
+{
+ return foo();
+}
+
+/* { dg-final { scan-assembler "jmp\[ \t\]\\*.*foo.*@GOTPCREL\\(%rip\\)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-3.c
new file mode 100644
index 0000000..e2a6f93
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target x86_64-*-linux* } } */
+/* { dg-options "-fno-pic -fno-plt" } */
+
+void foo();
+
+int main()
+{
+ foo();
+ return 0;
+}
+
+/* { dg-final { scan-assembler "call\[ \t\]\\*.*foo.*@GOTPCREL\\(%rip\\)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-4.c
new file mode 100644
index 0000000..d9039dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/noplt-4.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target x86_64-*-linux* } } */
+/* { dg-options "-O2 -fno-pic -fno-plt" } */
+
+int foo();
+
+int main()
+{
+ return foo();
+}
+
+/* { dg-final { scan-assembler "jmp\[ \t\]\\*.*foo.*@GOTPCREL\\(%rip\\)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-1.c
index ae339bd..7af851b 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-1.c
@@ -1,6 +1,7 @@
-/* Test if -mcopyrelocs does the right thing. */
-/* { dg-do compile } */
-/* { dg-options "-O2 -fpie -mcopyrelocs" } */
+/* Check that GOTPCREL isn't used to access glob_a. */
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-require-effective-target pie_copyreloc } */
+/* { dg-options "-O2 -fpie" } */
extern int glob_a;
@@ -9,5 +10,5 @@ int foo ()
return glob_a;
}
-/* glob_a should never be accessed with a GOTPCREL */
-/* { dg-final { scan-assembler-not "glob_a\\@GOTPCREL" { target { x86_64-*-* } } } } */
+/* glob_a should never be accessed with a GOTPCREL. */
+/* { dg-final { scan-assembler-not "glob_a@GOTPCREL" { target { ! ia32 } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-2.c
index ed60d03..19cb97e 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-2.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-2.c
@@ -1,13 +1,14 @@
-/* Test if -mno-copyrelocs does the right thing. */
-/* { dg-do compile } */
-/* { dg-options "-O2 -fpie -mno-copyrelocs" } */
+/* Check that GOTPCREL isn't used to access glob_a. */
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-require-effective-target pie_copyreloc } */
+/* { dg-options "-O2 -fpie" } */
-extern int glob_a;
+int glob_a;
int foo ()
{
return glob_a;
}
-/* glob_a should always be accessed via GOT */
-/* { dg-final { scan-assembler "glob_a\\@GOT" { target { x86_64-*-* } } } } */
+/* glob_a should never be accessed with a GOTPCREL. */
+/* { dg-final { scan-assembler-not "glob_a@GOTPCREL" { target { ! ia32 } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-3.c
new file mode 100644
index 0000000..c2fa896
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-3.c
@@ -0,0 +1,14 @@
+/* Check that PLT is used to access glob_a. */
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-require-effective-target pie_copyreloc } */
+/* { dg-options "-O2 -fpie" } */
+
+extern int glob_a (void);
+
+int foo ()
+{
+ return glob_a ();
+}
+
+/* glob_a should be accessed with a PLT. */
+/* { dg-final { scan-assembler "glob_a@PLT" { target { ! ia32 } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-4.c
new file mode 100644
index 0000000..413cdf3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pie-copyrelocs-4.c
@@ -0,0 +1,17 @@
+/* Check that GOTPCREL is used to access glob_a. */
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-require-effective-target pie_copyreloc } */
+/* { dg-options "-O2 -fpie" } */
+
+extern int glob_a __attribute__((weak));
+
+int foo ()
+{
+ if (&glob_a != 0)
+ return glob_a;
+ else
+ return 0;
+}
+
+/* weak glob_a should be accessed with a GOTPCREL. */
+/* { dg-final { scan-assembler "glob_a@GOTPCREL" { target { ! ia32 } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57003.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57003.c
index dfa6b8b..08a743d 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57003.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57003.c
@@ -1,5 +1,5 @@
/* PR rtl-optimization/57003 */
-/* { dg-do run } */
+/* { dg-do run { target { ! x32 } } } */
/* { dg-options "-O2" } */
#define N 2001
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59927.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59927.c
index 693c765..afb5306 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59927.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59927.c
@@ -1,5 +1,5 @@
/* PR target/59927 */
-/* { dg-do compile } */
+/* { dg-do compile { target { ! x32 } } } */
/* { dg-options "-O2 -g" } */
extern void baz (int) __attribute__ ((__ms_abi__));
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60516.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60516.c
index 575c8b6..d7e1116 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60516.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60516.c
@@ -1,5 +1,5 @@
/* PR target/60516 */
-/* { dg-do compile } */
+/* { dg-do compile { target { ! x32 } } } */
/* { dg-options "-O2" } */
struct S { char c[65536]; };
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63285.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63285.c
new file mode 100644
index 0000000..e4df8fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63285.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fcompare-debug" } */
+
+struct S { int a; };
+struct T { int b, c; } a;
+long b;
+int c, d;
+void bar (int, int);
+void baz (void *, int);
+
+void
+foo (struct S *x, int y, int z, void *f, int *p, struct T *e)
+{
+ while (x)
+ {
+ baz (f, &d > p);
+ if (z & 1)
+ bar (f > (void *) &f, z);
+ }
+ if (c)
+ {
+ asm ("" : "+m" (a) : "i" (0));
+ y--;
+ }
+ if (e->b == e->c)
+ c = y;
+ y--;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63448.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63448.c
new file mode 100644
index 0000000..3f8262e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63448.c
@@ -0,0 +1,120 @@
+/* PR rtl-optimization/63448 */
+/* { dg-do compile } */
+/* { dg-options "-O -std=c99" } */
+
+int a, d, e, g, h, j;
+float b, c, k, l, m, n;
+int *__restrict i;
+void
+foo (void)
+{
+ int o = e;
+ int *p;
+ float *q, *r = (float *) 0x1234000;
+ float s, t, u, v, w, x;
+ do
+ {
+ for (a = o; a; a--)
+ {
+ s += m;
+ t += n;
+ u += m;
+ v += n;
+ w += d;
+ x += d;
+ n = l;
+ s += r[1];
+ t += n;
+ v += r[1];
+ m = k * r[4];
+ n = q[0] * r[4];
+ s += m;
+ m = q[1] * r[4];
+ t += n;
+ q += g;
+ k = *q;
+ n = q[1] * r[4];
+ s += m;
+ t += n;
+ u += r[4];
+ m = q[8] * r[4];
+ q += 1;
+ n = q[1] * r[4];
+ s += m;
+ m = q[4];
+ t += n;
+ q += g;
+ w += m;
+ m = k * r[4];
+ s += m;
+ t += q[0];
+ m = q[1] * r[4];
+ v += q[0];
+ n = q[10] * r[4];
+ s += m;
+ t += n;
+ u += b;
+ m = q[8] * r[4];
+ n = q[2] * r[4];
+ s += m;
+ m = q[4] * r[4];
+ t += n;
+ q++;
+ n = q[2] * r[16];
+ s += m;
+ m = q[4];
+ t += n;
+ s += m;
+ t += r[6];
+ q += g;
+ k = *q;
+ w += m;
+ m = k * r[20];
+ x += r[16];
+ n = q[1] * r[20];
+ s += m;
+ t += n;
+ q += g;
+ k = *q;
+ w += m;
+ m = k * r[2];
+ n = q[1] * r[22];
+ s += m;
+ m = q[4];
+ t += n;
+ q += g;
+ s += m;
+ t += q[0];
+ s += m;
+ u += m;
+ n = q[1] * r[22];
+ s += m;
+ m = q[4] * r[22];
+ t += n;
+ q += g;
+ k = 1;
+ w += m;
+ c = q[10];
+ x += r[22];
+ s += m;
+ t += r[22];
+ u += m;
+ v += r[22];
+ n = q[10] * r[30];
+ d = r[32];
+ l = q[1];
+ b = 0;
+ w += m;
+ m = r[32];
+ x += n;
+ r = 0;
+ }
+ *i = s;
+ p[0] = t;
+ p[1] = u;
+ p[6] = v;
+ p[8] = w;
+ p[10] = x;
+ }
+ while (j);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63495.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63495.c
new file mode 100644
index 0000000..7f02f37
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63495.c
@@ -0,0 +1,6 @@
+/* PR c/63495 */
+/* { dg-do compile { target { i?86-*-linux* x86_64-*-linux* } } } */
+/* { dg-options "-std=gnu11" } */
+
+struct __attribute__ ((aligned (8))) S { char c; };
+_Static_assert (_Alignof (struct S) >= 8, "wrong alignment");
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63538.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63538.c
new file mode 100644
index 0000000..7b979c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63538.c
@@ -0,0 +1,13 @@
+/* PR target/63538 */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mcmodel=medium -mlarge-data-threshold=0" } */
+
+static char *str = "Hello World";
+
+char *foo ()
+{
+ return str;
+}
+
+/* { dg-final { scan-assembler "movabs" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63661.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63661.c
new file mode 100644
index 0000000..a5ffd2f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63661.c
@@ -0,0 +1,80 @@
+/* PR target/63661 */
+/* { dg-do run } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-mtune=nehalem -fPIC -O2" } */
+
+static void __attribute__((noinline,noclone,hot))
+foo (double a, double q, double *ff, double *gx, int e, int ni)
+{
+ union
+ {
+ double n;
+ unsigned long long o;
+ } punner;
+ double d;
+
+ punner.n = q;
+ __builtin_printf("B: 0x%016llx ---- %g\n", punner.o, q);
+
+ d = q - 5;
+ if(d < 0)
+ d = -d;
+ if (d > 0.1)
+ __builtin_abort();
+}
+
+static int __attribute__((noinline,noclone,hot))
+bar (int order, double q, double c[])
+{
+ int ni, nn, i, e;
+ double g2, x2, de, s, ratio, ff;
+
+ nn = 0;
+ e = order & 1;
+ s = 0;
+ ratio = 0;
+ x2 = 0;
+ g2 = 0;
+
+ if(q == 0.0)
+ return 0;
+
+ if (order < 5)
+ {
+ ratio = 1.0 / q;
+ nn = order;
+ }
+
+ ni = -nn;
+
+ while(1)
+ {
+ de = ratio - g2 - x2;
+
+ foo (0, q, &ff, &g2, e, ni);
+
+ if((int)de == 0)
+ break;
+ }
+
+ s += 2 * nn * c[nn];
+
+ for (i = 0; i < 1; i++)
+ {
+ c[0] = nn;
+ for (; i < 10; i++)
+ c[i] = 0.0;
+ c[0] /= s;
+ }
+
+ return 0;
+}
+
+int
+main ()
+{
+ double c[1000];
+
+ bar (1, 5.0, c);
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63947.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63947.c
new file mode 100644
index 0000000..3c0a67a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr63947.c
@@ -0,0 +1,9 @@
+/* PR target/63947 */
+/* { dg-do assemble } */
+/* { dg-options "-Os" } */
+/* { dg-additional-options "-march=i686" { target ia32 } } */
+
+long double foo (unsigned a, unsigned b)
+{
+ return a + b < a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr64409.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr64409.c
new file mode 100644
index 0000000..6a64b59
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr64409.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-require-effective-target maybe_x32 } */
+/* { dg-options "-O0 -mx32" } */
+
+int a;
+int* __attribute__ ((ms_abi)) fn1 () { return &a; } /* { dg-error "X32 does not support ms_abi attribute" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr64513.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr64513.c
new file mode 100644
index 0000000..0236496
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr64513.c
@@ -0,0 +1,17 @@
+/* PR target/64513 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mstack-arg-probe" } */
+
+struct A {};
+struct B { struct A y; };
+int foo (struct A);
+
+int
+bar (int x)
+{
+ struct B b;
+ int c;
+ while (x--)
+ c = foo (b.y);
+ return c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-20.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-20.c
index b2c29a9..1af8ed7 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-20.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-20.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target powerpc_altivec_ok } } */
-/* { dg-options "-maltivec -mcpu=G5 -O2" } */
+/* { dg-options "-maltivec -mcpu=G5 -O2 -Wno-deprecated" } */
#include <altivec.h>
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-6.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-6.c
index 51d4116..29856fd 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-6.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-6.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target powerpc*-*-* } } */
/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -O0 -Wall" } */
+/* { dg-options "-maltivec -O0 -Wall -Wno-deprecated" } */
#include <altivec.h>
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c
index 3689f97..b1ed8b8 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -O2" } */
+/* { dg-options "-maltivec -O2 -Wno-deprecated" } */
#include <altivec.h>
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/builtins-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/builtins-1.c
new file mode 100644
index 0000000..3da7146
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/builtins-1.c
@@ -0,0 +1,166 @@
+/* { dg-do compile { target { powerpc64le-*-* } } } */
+/* { dg-options "-mcpu=power8 -O0" } */
+
+/* Test that a number of newly added builtin overloads are accepted
+ by the compiler. */
+
+#include <altivec.h>
+
+vector double y = { 2.0, 4.0 };
+vector double z;
+
+int main ()
+{
+ vector float fa = {1.0, 2.0, 3.0, -4.0};
+ vector float fb = {-2.0, -3.0, -4.0, -5.0};
+ vector float fc = vec_cpsgn (fa, fb);
+
+ vector long long la = {5L, 14L};
+ vector long long lb = {3L, 86L};
+ vector long long lc = vec_and (la, lb);
+ vector bool long long ld = {0, -1};
+ vector long long le = vec_and (la, ld);
+ vector long long lf = vec_and (ld, lb);
+
+ vector unsigned long long ua = {5L, 14L};
+ vector unsigned long long ub = {3L, 86L};
+ vector unsigned long long uc = vec_and (ua, ub);
+ vector bool long long ud = {0, -1};
+ vector unsigned long long ue = vec_and (ua, ud);
+ vector unsigned long long uf = vec_and (ud, ub);
+
+ vector long long lg = vec_andc (la, lb);
+ vector long long lh = vec_andc (la, ld);
+ vector long long li = vec_andc (ld, lb);
+
+ vector unsigned long long ug = vec_andc (ua, ub);
+ vector unsigned long long uh = vec_andc (ua, ud);
+ vector unsigned long long ui = vec_andc (ud, ub);
+
+ vector double da = {1.0, -4.0};
+ vector double db = {-2.0, 5.0};
+ vector double dc = vec_cpsgn (da, db);
+
+ vector long long lj = vec_mergeh (la, lb);
+ vector long long lk = vec_mergeh (la, ld);
+ vector long long ll = vec_mergeh (ld, la);
+
+ vector unsigned long long uj = vec_mergeh (ua, ub);
+ vector unsigned long long uk = vec_mergeh (ua, ud);
+ vector unsigned long long ul = vec_mergeh (ud, ua);
+
+ vector long long lm = vec_mergel (la, lb);
+ vector long long ln = vec_mergel (la, ld);
+ vector long long lo = vec_mergel (ld, la);
+
+ vector unsigned long long um = vec_mergel (ua, ub);
+ vector unsigned long long un = vec_mergel (ua, ud);
+ vector unsigned long long uo = vec_mergel (ud, ua);
+
+ vector long long lp = vec_nor (la, lb);
+ vector long long lq = vec_nor (la, ld);
+ vector long long lr = vec_nor (ld, la);
+
+ vector unsigned long long up = vec_nor (ua, ub);
+ vector unsigned long long uq = vec_nor (ua, ud);
+ vector unsigned long long ur = vec_nor (ud, ua);
+
+ vector long long ls = vec_or (la, lb);
+ vector long long lt = vec_or (la, ld);
+ vector long long lu = vec_or (ld, la);
+
+ vector unsigned long long us = vec_or (ua, ub);
+ vector unsigned long long ut = vec_or (ua, ud);
+ vector unsigned long long uu = vec_or (ud, ua);
+
+ vector unsigned char ca = {0,4,8,1,5,9,2,6,10,3,7,11,15,12,14,13};
+ vector long long lv = vec_perm (la, lb, ca);
+ vector unsigned long long uv = vec_perm (ua, ub, ca);
+
+ vector long long lw = vec_sel (la, lb, lc);
+ vector long long lx = vec_sel (la, lb, uc);
+ vector long long ly = vec_sel (la, lb, ld);
+
+ vector unsigned long long uw = vec_sel (ua, ub, lc);
+ vector unsigned long long ux = vec_sel (ua, ub, uc);
+ vector unsigned long long uy = vec_sel (ua, ub, ld);
+
+ vector long long lz = vec_xor (la, lb);
+ vector long long l0 = vec_xor (la, ld);
+ vector long long l1 = vec_xor (ld, la);
+
+ vector unsigned long long uz = vec_xor (ua, ub);
+ vector unsigned long long u0 = vec_xor (ua, ud);
+ vector unsigned long long u1 = vec_xor (ud, ua);
+
+ int ia = vec_all_eq (ua, ub);
+ int ib = vec_all_ge (ua, ub);
+ int ic = vec_all_gt (ua, ub);
+ int id = vec_all_le (ua, ub);
+ int ie = vec_all_lt (ua, ub);
+ int ig = vec_all_ne (ua, ub);
+
+ int ih = vec_any_eq (ua, ub);
+ int ii = vec_any_ge (ua, ub);
+ int ij = vec_any_gt (ua, ub);
+ int ik = vec_any_le (ua, ub);
+ int il = vec_any_lt (ua, ub);
+ int im = vec_any_ne (ua, ub);
+
+ vector int sia = {9, 16, 25, 36};
+ vector int sib = {-8, -27, -64, -125};
+ vector int sic = vec_mergee (sia, sib);
+ vector int sid = vec_mergeo (sia, sib);
+
+ vector unsigned int uia = {9, 16, 25, 36};
+ vector unsigned int uib = {8, 27, 64, 125};
+ vector unsigned int uic = vec_mergee (uia, uib);
+ vector unsigned int uid = vec_mergeo (uia, uib);
+
+ vector bool int bia = {0, -1, -1, 0};
+ vector bool int bib = {-1, -1, 0, -1};
+ vector bool int bic = vec_mergee (bia, bib);
+ vector bool int bid = vec_mergeo (bia, bib);
+
+ vector unsigned int uie = vec_packsu (ua, ub);
+
+ vector long long l2 = vec_cntlz (la);
+ vector unsigned long long u2 = vec_cntlz (ua);
+ vector int sie = vec_cntlz (sia);
+ vector unsigned int uif = vec_cntlz (uia);
+ vector short ssa = {20, -40, -60, 80, 100, -120, -140, 160};
+ vector short ssb = vec_cntlz (ssa);
+ vector unsigned short usa = {81, 72, 63, 54, 45, 36, 27, 18};
+ vector unsigned short usb = vec_cntlz (usa);
+ vector signed char sca = {-4, 3, -9, 15, -31, 31, 0, 0,
+ 1, 117, -36, 99, 98, 97, 96, 95};
+ vector signed char scb = vec_cntlz (sca);
+ vector unsigned char cb = vec_cntlz (ca);
+
+ vector double dd = vec_xl (0, &y);
+ vec_xst (dd, 0, &z);
+
+ vector double de = vec_round (dd);
+
+ vector double df = vec_splat (de, 0);
+ vector double dg = vec_splat (de, 1);
+ vector long long l3 = vec_splat (l2, 0);
+ vector long long l4 = vec_splat (l2, 1);
+ vector unsigned long long u3 = vec_splat (u2, 0);
+ vector unsigned long long u4 = vec_splat (u2, 1);
+ vector bool long long l5 = vec_splat (ld, 0);
+ vector bool long long l6 = vec_splat (ld, 1);
+
+ vector long long l7 = vec_div (l3, l4);
+ vector unsigned long long u5 = vec_div (u3, u4);
+
+ vector long long l8 = vec_mul (l3, l4);
+ vector unsigned long long u6 = vec_mul (u3, u4);
+
+ vector double dh = vec_ctf (la, -2);
+ vector double di = vec_ctf (ua, 2);
+ vector long long l9 = vec_cts (dh, -2);
+ vector unsigned long long u7 = vec_ctu (di, 2);
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/builtins-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/builtins-2.c
new file mode 100644
index 0000000..7f4a392
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/builtins-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run { target { powerpc64le-*-* } } } */
+/* { dg-options "-mcpu=power8 " } */
+
+#include <altivec.h>
+
+void abort (void);
+
+int main ()
+{
+ vector long long sa = {27L, -14L};
+ vector long long sb = {-9L, -2L};
+
+ vector unsigned long long ua = {27L, 14L};
+ vector unsigned long long ub = {9L, 2L};
+
+ vector long long sc = vec_div (sa, sb);
+ vector unsigned long long uc = vec_div (ua, ub);
+
+ if (sc[0] != -3L || sc[1] != 7L || uc[0] != 3L || uc[1] != 7L)
+ abort ();
+
+ vector long long sd = vec_mul (sa, sb);
+ vector unsigned long long ud = vec_mul (ua, ub);
+
+ if (sd[0] != -243L || sd[1] != 28L || ud[0] != 243L || ud[1] != 28L)
+ abort ();
+
+ vector long long se = vec_splat (sa, 0);
+ vector long long sf = vec_splat (sa, 1);
+ vector unsigned long long ue = vec_splat (ua, 0);
+ vector unsigned long long uf = vec_splat (ua, 1);
+
+ if (se[0] != 27L || se[1] != 27L || sf[0] != -14L || sf[1] != -14L
+ || ue[0] != 27L || ue[1] != 27L || uf[0] != 14L || uf[1] != 14L)
+ abort ();
+
+ vector double da = vec_ctf (sa, -2);
+ vector double db = vec_ctf (ua, 2);
+ vector long long sg = vec_cts (da, -2);
+ vector unsigned long long ug = vec_ctu (db, 2);
+
+ if (da[0] != 108.0 || da[1] != -56.0 || db[0] != 6.75 || db[1] != 3.5
+ || sg[0] != 27L || sg[1] != -14L || ug[0] != 27L || ug[1] != 14L)
+ abort ();
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c
new file mode 100644
index 0000000..71dd0a2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c
@@ -0,0 +1,21 @@
+/* Test expected code generation for lvsl and lvsr on little endian.
+ Note that lvsl and lvsr are each produced once, but the filename
+ causes them to appear twice in the file. */
+
+/* { dg-do compile { target { powerpc64le-*-* } } } */
+/* { dg-options "-O0 -Wno-deprecated" } */
+/* { dg-final { scan-assembler-times "lvsl" 2 } } */
+/* { dg-final { scan-assembler-times "lvsr" 2 } } */
+/* { dg-final { scan-assembler-times "lxvd2x" 2 } } */
+/* { dg-final { scan-assembler-times "vperm" 2 } } */
+
+
+#include <altivec.h>
+
+float f[20];
+
+void foo ()
+{
+ vector unsigned char a = vec_lvsl (4, f);
+ vector unsigned char b = vec_lvsr (8, f);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr63335.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr63335.c
new file mode 100644
index 0000000..931a8b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr63335.c
@@ -0,0 +1,30 @@
+/* { dg-do run { target { powerpc64*-*-* } } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx" } */
+
+#include <altivec.h>
+
+void abort (void);
+
+vector double vec = (vector double) {99.0, 99.0};
+
+int main() {
+
+ int actual = vec_all_nge(vec, vec);
+ if ( actual != 0)
+ abort();
+
+ actual = vec_all_nle(vec, vec);
+ if ( actual != 0)
+ abort();
+
+ actual = vec_any_nge(vec, vec);
+ if ( actual != 0)
+ abort();
+
+ actual = vec_any_nle(vec, vec);
+ if ( actual != 0)
+ abort();
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr64505.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr64505.c
new file mode 100644
index 0000000..9991621
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr64505.c
@@ -0,0 +1,231 @@
+/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
+/* { dg-options "-O2 -mpowerpc64" } */
+
+/*
+ * (below is inlined and simplified from previously included headers)
+ */
+
+struct fltcom_st {
+ short fltbuf[950];
+} fltcom_ __attribute__((common)) ;
+#define CM_PLIBOR (*(((double *)&fltcom_ + 1)))
+#define CM_QMRG (*(((double *)&fltcom_ + 2)))
+
+struct fltcom2_st {
+ short fltbuf2[56];
+} fltcom2_ __attribute__((common)) ;
+#define CM_FLPRV ((short *)&fltcom2_ + 17)
+#define CM_FLNXT ((short *)&fltcom2_ + 20)
+#define CM_FLCPN (*(((double *)&fltcom2_)))
+#define CM_FLCNT (*(((short *)&fltcom2_ + 12)))
+
+struct aidatcm_st {
+ double cm_aid, cm_ext, cm_basis;
+ short cm_aiday, cm_exday, cm_dperd, cm_aiexf, cm_aidex, cm_aiok,
+ cm_aigdo, cm_aildo, cm_prev[3], cm_next[3], cm_aid_pad[2];
+ double cm_rvgfact, cm_ai1st, cm_ai2nd;
+ int cm_aieurok;
+} aidatcm_ __attribute__((common)) ;
+#define CM_EXDAY aidatcm_.cm_exday
+#define CM_BASIS aidatcm_.cm_basis
+#define CM_PREV aidatcm_.cm_prev
+
+struct cshfcm_st {
+ short bufff[10862];
+} cshfcm_ __attribute__((common)) ;
+#define CM_FNUM (*(((short *)&cshfcm_ + 9038)))
+#define CM_FIFLX ((double *)&cshfcm_ + 1)
+#define CM_FEXTX ((double *)&cshfcm_ + 1201)
+#define CM_FSHDT ((short *)&cshfcm_ + 7230)
+
+struct calctsdb_st {
+ short calctsdbbuff[115];
+} calctsdb_ __attribute__((common)) ;
+#define CM_CTUP_GOOD_TO_GO (*(((short *)&calctsdb_ + 16)))
+#define CM_PAYMENT_FREQUENCY (*(((short *)&calctsdb_ + 61)))
+#define CM_DISCOUNTING_DAYTYP (*(((short *)&calctsdb_ + 59)))
+
+struct cf600cm_st {
+ short bufcf[14404];
+} cf600cm_ __attribute__((common)) ;
+#define CM_FLT_RFIXRATES ((double *)&cf600cm_ + 600)
+
+typedef struct { int id; int type; const char *name; } bregdb_bitinfo_t;
+
+int
+bregdb_eval_bbitcxt_bool_rv(const bregdb_bitinfo_t * const bbit,
+ const int bbit_default,
+ const void * const bregucxt);
+
+static const bregdb_bitinfo_t bbit_calc_dr_d33 =
+ { 160667, 5, "bbit_calc_dr_d33" };
+#define bbit_calc_dr_d33__value() \
+ bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d33, 0, 0)
+static const bregdb_bitinfo_t bbit_calc_sx_b24 =
+ { 158854, 5, "bbit_calc_sx_b24" };
+#define bbit_calc_sx_b24__value() \
+ bregdb_eval_bbitcxt_bool_rv(&bbit_calc_sx_b24, 0, 0)
+static const bregdb_bitinfo_t bbit_calc_dr_d36 =
+ { 161244, 5, "bbit_calc_dr_d36" };
+#define bbit_calc_dr_d36__value() \
+ bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d36, 0, 0)
+static const bregdb_bitinfo_t bbit_calc_dr_d37 =
+ { 161315, 5, "bbit_calc_dr_d37" };
+#define bbit_calc_dr_d37__value() \
+ bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d37, 0, 0)
+static const bregdb_bitinfo_t bbit_calc_dr_d47 =
+ { 163259, 5, "bbit_calc_dr_d47" };
+#define bbit_calc_dr_d47__value() \
+ bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d47, 0, 0)
+static const bregdb_bitinfo_t bbit_calc_dr_d46 =
+ { 163239, 5, "bbit_calc_dr_d46" };
+#define bbit_calc_dr_d46__value() \
+ bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d46, 0, 0)
+static const bregdb_bitinfo_t bbit_calc_dr_d62 =
+ { 166603, 5, "bbit_calc_dr_d62" };
+#define bbit_calc_dr_d62__value() \
+ bregdb_eval_bbitcxt_bool_rv(&bbit_calc_dr_d62, 0, 0)
+
+
+
+int dtyp_is_actact_(short *daytyp);
+double rnd_trunc_numb(double in, short num_digits, short rnd_or_trunc);
+void datetrn_(const short* dt, short* dt2);
+short difday_(short* daytyp_in, short* srtdti, short* enddti, short* ercode);
+
+
+double pow(double x, double y);
+
+
+/*
+ * (above is inlined and simplified from previously included headers)
+ */
+
+
+void calc_1566(
+ short sCalcType,
+ short sDayType,
+ short sFreq,
+ short asSettleDt[3],
+ short asMtyDt[3],
+ short asIssueDt[3],
+ short asFCpnDt[3],
+ double dCpn,
+ short *psNoPer,
+ double *pdExt,
+ double *pdAI,
+ double *pdAI2,
+ double *pdFCpn,
+ short *psRcode)
+{
+
+ short ercode = 0;
+ int isactact;
+ short days_to_next_cpn = 0;
+ const short discDaytype = CM_DISCOUNTING_DAYTYP;
+ int j;
+
+ if(bbit_calc_sx_b24__value())
+ isactact = (dtyp_is_actact_(&sDayType) != 0);
+ else
+ isactact = (sDayType == 1 || sDayType == 10);
+
+ short days_in_current_period = difday_(&sDayType,CM_FLPRV,CM_FLNXT,&ercode);
+ const short sfreq1 = (CM_CTUP_GOOD_TO_GO == 1 && CM_PAYMENT_FREQUENCY == 1);
+
+ for (j = 0; j < CM_FNUM; j++) {
+
+ if(j == 0) {
+ days_to_next_cpn = difday_(&sDayType,asSettleDt,CM_FLNXT,&ercode);
+
+ if(isactact) {
+ CM_FIFLX[j] = CM_FLCPN / sFreq;
+ CM_FEXTX[j] = (double)days_to_next_cpn / (double)days_in_current_period;
+ }
+ else {
+ CM_FIFLX[j] = CM_FLCPN * days_in_current_period;
+ CM_FEXTX[j] = (double)days_to_next_cpn / (double)(1/sfreq1);
+ }
+
+ if(CM_FNUM == 1) {
+ CM_FEXTX[j] = (double)days_to_next_cpn / ((double)1/sfreq1);
+ }
+ }
+ else {
+
+ short days_from_settle, days_in_period;
+
+ if(bbit_calc_dr_d46__value()){
+ days_from_settle = difday_(&sDayType,asSettleDt,
+ &CM_FSHDT[j*3],&ercode);
+ days_in_period = difday_(&sDayType,&CM_FSHDT[(j-1)*3],
+ &CM_FSHDT[j*3],&ercode);
+ }
+
+ double cpn_rate = CM_PLIBOR;
+
+ if(bbit_calc_dr_d62__value()) {
+ if(j < CM_FLCNT && CM_FLT_RFIXRATES[j] != 0) cpn_rate = CM_FLT_RFIXRATES[j];
+ }
+ else {
+ if(j < CM_FLCNT ) cpn_rate = CM_FLT_RFIXRATES[j];
+ }
+
+ if(bbit_calc_dr_d37__value()&& j >= CM_FLCNT && sCalcType == 1570) {
+ cpn_rate = CM_PLIBOR + CM_QMRG;
+
+ if(bbit_calc_dr_d36__value()){
+ double projected_rate = pow((1 + CM_PLIBOR/100.0),
+ (days_in_period)) - 1;
+
+ projected_rate = projected_rate + CM_QMRG/100.0 * days_in_period;
+ cpn_rate = 100 * projected_rate * (1/days_in_period);
+ }
+ }
+
+
+ if(isactact) {
+ CM_FIFLX[j] = cpn_rate / sFreq;
+ CM_FEXTX[j] = CM_FEXTX[j-1] + 1;
+
+ if(bbit_calc_dr_d46__value() && discDaytype != 0) {
+ CM_FEXTX[j] = (double)days_from_settle / (double)(1/sfreq1);
+ }
+ }
+ else {
+ if(!bbit_calc_dr_d46__value()){
+ days_from_settle = difday_(&sDayType,asSettleDt,
+ &CM_FSHDT[j*3],&ercode);
+ days_in_period = difday_(&sDayType,&CM_FSHDT[(j-1)*3],
+ &CM_FSHDT[j*3],&ercode);
+
+ }
+
+ CM_FIFLX[j] = cpn_rate * days_in_period;
+ CM_FEXTX[j] = (double)days_from_settle / (double)(1/sfreq1);
+ }
+
+ }
+
+ if(bbit_calc_dr_d33__value() && CM_CTUP_GOOD_TO_GO != 0) {
+ CM_FIFLX[j] = rnd_trunc_numb (CM_FIFLX[j], 0, 0);
+ }
+
+ }
+
+
+ short accrued_days = difday_(&sDayType,CM_FLPRV,asSettleDt,&ercode);
+
+ if(!bbit_calc_dr_d47__value()) {
+ if(isactact) {
+ *pdAI = (CM_FLCPN / sFreq)* accrued_days / ((double)days_in_current_period);
+ }
+ else{
+ *pdAI = (CM_FLCPN / sFreq)* accrued_days / ((double)1/sFreq);
+ }
+ }
+
+ CM_EXDAY = days_to_next_cpn;
+ CM_BASIS = days_in_current_period;
+ datetrn_(CM_FLPRV,CM_PREV);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-1.c
new file mode 100644
index 0000000..ab85e91
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+/* { dg-final { scan-assembler "lxvd2x" } } */
+/* { dg-final { scan-assembler "stxvd2x" } } */
+/* { dg-final { scan-assembler-not "xxpermdi" } } */
+
+void abort();
+
+#define N 16
+
+signed char ca[N] __attribute__((aligned(16)));
+signed char cb[] __attribute__((aligned(16)))
+ = {8, 7, 6, 5, 4, 3, 2, 1, 0, -1, -2, -3, -4, -5, -6, -7};
+signed char cc[] __attribute__((aligned(16)))
+ = {1, 1, 2, 2, 3, 3, 2, 2, 1, 1, 0, 0, -1, -1, -2, -2};
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ for (i = 0; i < N; i++) {
+ ca[i] = cb[i] - cc[i];
+ }
+}
+
+int main ()
+{
+ signed char cd[] = {7, 6, 4, 3, 1, 0, 0, -1, -1, -2, -2, -3, -3, -4, -4, -5};
+ int i;
+ foo ();
+ for (i = 0; i < N; ++i)
+ if (ca[i] != cd[i])
+ abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-10.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-10.c
new file mode 100644
index 0000000..170649d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-10.c
@@ -0,0 +1,42 @@
+/* { dg-do run { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+
+void abort ();
+
+#define N 4096
+int ca[N] __attribute__((aligned(16)));
+int cb[N] __attribute__((aligned(16)));
+int cc[N] __attribute__((aligned(16)));
+int cd[N] __attribute__((aligned(16)));
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ for (i = 0; i < N; i++) {
+ ca[i] = ((cb[i] + cc[i]) * cd[i]) >> 3;
+ }
+}
+
+__attribute__((noinline)) void init ()
+{
+ int i;
+ for (i = 0; i < N; ++i) {
+ cb[i] = 3 * i - 2048;
+ cc[i] = -5 * i + 93;
+ cd[i] = i % 2 ? 1 : -1;
+ }
+}
+
+int main ()
+{
+ int i;
+ init ();
+ foo ();
+ for (i = 0; i < N; ++i)
+ if (i % 2 == 1 && ca[i] != (-2 * i - 1955) >> 3)
+ abort ();
+ else if (i % 2 == 0 && ca[i] != (1955 + 2 * i) >> 3)
+ abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-11.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-11.c
new file mode 100644
index 0000000..699b5ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-11.c
@@ -0,0 +1,53 @@
+/* { dg-do run { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+
+#include <altivec.h>
+void abort ();
+
+#define N 4096
+int ca[N] __attribute__((aligned(16)));
+int cb[N] __attribute__((aligned(16)));
+int cc[N] __attribute__((aligned(16)));
+int cd[N] __attribute__((aligned(16)));
+int hey;
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ vector int va, vb, vc, vd, tmp;
+ vector unsigned int threes = vec_splat_u32(3);
+ for (i = 0; i < N; i+=4) {
+ vb = vec_vsx_ld (0, &cb[i]);
+ vc = vec_vsx_ld (0, &cc[i]);
+ vd = vec_vsx_ld (0, &cd[i]);
+ tmp = vec_add (vb, vc);
+ tmp = vec_sub (tmp, vd);
+ tmp = vec_sra (tmp, threes);
+ hey = tmp[3];
+ vec_vsx_st (tmp, 0, &ca[i]);
+ }
+}
+
+__attribute__((noinline)) void init ()
+{
+ int i;
+ for (i = 0; i < N; ++i) {
+ cb[i] = 3 * i - 2048;
+ cc[i] = -5 * i + 93;
+ cd[i] = i + 14;
+ }
+}
+
+int main ()
+{
+ int i;
+ init ();
+ foo ();
+ for (i = 0; i < N; ++i)
+ if (ca[i] != (-3 * i - 1969) >> 3)
+ abort ();
+ if (hey != ca[N-1])
+ abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-12.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-12.c
new file mode 100644
index 0000000..529d03e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-12.c
@@ -0,0 +1,56 @@
+/* { dg-do compile { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+/* { dg-final { scan-assembler "lxvd2x" } } */
+/* { dg-final { scan-assembler "stxvd2x" } } */
+/* { dg-final { scan-assembler-not "xxpermdi" } } */
+
+#include "altivec.h"
+void abort ();
+
+#define N 4096
+int ca[N] __attribute__((aligned(16)));
+int cb[N] __attribute__((aligned(16)));
+int cc[N] __attribute__((aligned(16)));
+int cd[N] __attribute__((aligned(16)));
+int hey;
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ vector int va, vb, vc, vd, tmp;
+ vector unsigned int threes = vec_splat_u32(3);
+ for (i = 0; i < N; i+=4) {
+ vb = vec_vsx_ld (0, &cb[i]);
+ vc = vec_vsx_ld (0, &cc[i]);
+ vd = vec_vsx_ld (0, &cd[i]);
+ tmp = vec_add (vb, vc);
+ tmp = vec_sub (tmp, vd);
+ tmp = vec_sra (tmp, threes);
+ hey = tmp[3];
+ vec_vsx_st (tmp, 0, &ca[i]);
+ }
+}
+
+__attribute__((noinline)) void init ()
+{
+ int i;
+ for (i = 0; i < N; ++i) {
+ cb[i] = 3 * i - 2048;
+ cc[i] = -5 * i + 93;
+ cd[i] = i + 14;
+ }
+}
+
+int main ()
+{
+ int i;
+ init ();
+ foo ();
+ for (i = 0; i < N; ++i)
+ if (ca[i] != (-3 * i - 1969) >> 3)
+ abort ();
+ if (hey != ca[N-1])
+ abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-13.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-13.c
new file mode 100644
index 0000000..787b02e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-13.c
@@ -0,0 +1,54 @@
+/* { dg-do run { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+
+#include <altivec.h>
+void abort ();
+
+#define N 4096
+long long ca[N] __attribute__((aligned(16)));
+long long cb[N] __attribute__((aligned(16)));
+long long cc[N] __attribute__((aligned(16)));
+long long cd[N] __attribute__((aligned(16)));
+long long x;
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ vector long long va, vb, vc, vd, tmp;
+ volatile unsigned long long three = 3;
+ vector unsigned long long threes = vec_splats (three);
+ for (i = 0; i < N; i+=2) {
+ vb = vec_vsx_ld (0, (vector long long *)&cb[i]);
+ vc = vec_vsx_ld (0, (vector long long *)&cc[i]);
+ vd = vec_vsx_ld (0, (vector long long *)&cd[i]);
+ tmp = vec_add (vb, vc);
+ tmp = vec_sub (tmp, vd);
+ tmp = vec_sra (tmp, threes);
+ x = vec_extract (tmp, 0);
+ vec_vsx_st (tmp, 0, (vector long long *)&ca[i]);
+ }
+}
+
+__attribute__((noinline)) void init ()
+{
+ int i;
+ for (i = 0; i < N; ++i) {
+ cb[i] = 3 * i - 2048;
+ cc[i] = -5 * i + 93;
+ cd[i] = i + 14;
+ }
+}
+
+int main ()
+{
+ int i;
+ init ();
+ foo ();
+ for (i = 0; i < N; ++i)
+ if (ca[i] != (-3 * i - 1969) >> 3)
+ abort ();
+ if (x != ca[N-1])
+ abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-14.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-14.c
new file mode 100644
index 0000000..7ca6ad5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-14.c
@@ -0,0 +1,43 @@
+/* { dg-do compile { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+/* { dg-final { scan-assembler "lxvd2x" } } */
+/* { dg-final { scan-assembler "stxvd2x" } } */
+/* { dg-final { scan-assembler "stxsdx" } } */
+/* { dg-final { scan-assembler-times "xxpermdi" 1 } } */
+
+/* The only xxpermdi expected is for the vec_splats. */
+
+#include <altivec.h>
+void abort ();
+
+#define N 4096
+long long ca[N] __attribute__((aligned(16)));
+long long cb[N] __attribute__((aligned(16)));
+long long cc[N] __attribute__((aligned(16)));
+long long cd[N] __attribute__((aligned(16)));
+long long x;
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ vector long long va, vb, vc, vd, tmp;
+ volatile unsigned long long three = 3;
+ vector unsigned long long threes = vec_splats (three);
+ for (i = 0; i < N; i+=2) {
+ vb = vec_vsx_ld (0, (vector long long *)&cb[i]);
+ vc = vec_vsx_ld (0, (vector long long *)&cc[i]);
+ vd = vec_vsx_ld (0, (vector long long *)&cd[i]);
+ tmp = vec_add (vb, vc);
+ tmp = vec_sub (tmp, vd);
+ tmp = vec_sra (tmp, threes);
+ x = vec_extract (tmp, 0);
+ vec_vsx_st (tmp, 0, (vector long long *)&ca[i]);
+ }
+}
+
+int main ()
+{
+ foo ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-15.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-15.c
new file mode 100644
index 0000000..172e4bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-15.c
@@ -0,0 +1,51 @@
+/* { dg-do compile { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+/* { dg-final { scan-assembler "lxvd2x" } } */
+/* { dg-final { scan-assembler "stxvd2x" } } */
+/* { dg-final { scan-assembler "xxspltw" } } */
+
+/* Currently the analyze_swaps phase cannot optimize this loop because
+ of the presence of an UNSPEC_VSX_CVDPSPN. At such time as this is
+ handled, we need to add a 'scan-assembler-not "xxpermdi"' directive to
+ this test. */
+#include <altivec.h>
+void abort();
+
+#define N 4096
+#define M 10000000
+vector float ca[N][4] = {0};
+vector float cb[N][4] = {0};
+vector float cc[N][4] = {0};
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ for (i = 0; i < N; i++) {
+ cc[i][0] = vec_mul(vec_splats(cb[i][0][0]), ca[i][0]);
+ cc[i][0] = vec_madd(cc[i][0],vec_splats(cb[i][0][1]), ca[i][1]);
+ cc[i][0] = vec_madd(cc[i][0],vec_splats(cb[i][0][2]), ca[i][2]);
+ cc[i][0] = vec_madd(cc[i][0],vec_splats(cb[i][0][3]), ca[i][3]);
+
+ cc[i][1] = vec_mul(vec_splats(cb[i][1][0]), ca[i][0]);
+ cc[i][1] = vec_madd(cc[i][0],vec_splats(cb[i][1][1]), ca[i][1]);
+ cc[i][1] = vec_madd(cc[i][0],vec_splats(cb[i][1][2]), ca[i][2]);
+ cc[i][1] = vec_madd(cc[i][0],vec_splats(cb[i][1][3]), ca[i][3]);
+
+ cc[i][2] = vec_mul(vec_splats(cb[i][2][0]), ca[i][0]);
+ cc[i][2] = vec_madd(cc[i][0],vec_splats(cb[i][2][1]), ca[i][1]);
+ cc[i][2] = vec_madd(cc[i][0],vec_splats(cb[i][2][2]), ca[i][2]);
+ cc[i][2] = vec_madd(cc[i][0],vec_splats(cb[i][2][3]), ca[i][3]);
+
+ cc[i][3] = vec_mul(vec_splats(cb[i][3][0]), ca[i][0]);
+ cc[i][3] = vec_madd(cc[i][0],vec_splats(cb[i][3][1]), ca[i][1]);
+ cc[i][3] = vec_madd(cc[i][0],vec_splats(cb[i][3][2]), ca[i][2]);
+ cc[i][3] = vec_madd(cc[i][0],vec_splats(cb[i][3][3]), ca[i][3]);
+ }
+}
+
+int main ()
+{
+ foo ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-16.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-16.c
new file mode 100644
index 0000000..2b7f73c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-16.c
@@ -0,0 +1,57 @@
+/* { dg-do compile { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+/* { dg-final { scan-assembler "lxvd2x" } } */
+/* { dg-final { scan-assembler "stxvd2x" } } */
+/* { dg-final { scan-assembler "vspltw" } } */
+/* { dg-final { scan-assembler-not "xxpermdi" } } */
+
+#include <altivec.h>
+void abort();
+
+typedef struct xx {vector double l; vector double h;} xx;
+
+#define N 4096
+#define M 10000000
+vector float ca[N][4] = {0};
+vector float cb[N][4] = {0};
+vector float cc[N][4] = {0};
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ vector float brow;
+
+ for (i = 0; i < N; i++) {
+
+ brow = cb[i][0];
+ cc[i][0] = vec_mul(vec_splats(brow[0]), ca[i][0]);
+ cc[i][0] = vec_madd(cc[i][0],vec_splats(brow[1]), ca[i][1]);
+ cc[i][0] = vec_madd(cc[i][0],vec_splats(brow[2]), ca[i][2]);
+ cc[i][0] = vec_madd(cc[i][0],vec_splats(brow[3]), ca[i][3]);
+
+ brow = cb[i][1];
+ cc[i][1] = vec_mul(vec_splats(brow[0]), ca[i][0]);
+ cc[i][1] = vec_madd(cc[i][0],vec_splats(brow[1]), ca[i][1]);
+ cc[i][1] = vec_madd(cc[i][0],vec_splats(brow[2]), ca[i][2]);
+ cc[i][1] = vec_madd(cc[i][0],vec_splats(brow[3]), ca[i][3]);
+
+ brow = cb[i][2];
+ cc[i][2] = vec_mul(vec_splats(brow[0]), ca[i][0]);
+ cc[i][2] = vec_madd(cc[i][0],vec_splats(brow[1]), ca[i][1]);
+ cc[i][2] = vec_madd(cc[i][0],vec_splats(brow[2]), ca[i][2]);
+ cc[i][2] = vec_madd(cc[i][0],vec_splats(brow[3]), ca[i][3]);
+
+ brow = cb[i][3];
+ cc[i][3] = vec_mul(vec_splats(brow[0]), ca[i][0]);
+ cc[i][3] = vec_madd(cc[i][0],vec_splats(brow[1]), ca[i][1]);
+ cc[i][3] = vec_madd(cc[i][0],vec_splats(brow[2]), ca[i][2]);
+ cc[i][3] = vec_madd(cc[i][0],vec_splats(brow[3]), ca[i][3]);
+ }
+}
+
+int main ()
+{
+ foo ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-17.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-17.c
new file mode 100644
index 0000000..7a9cfbf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-17.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O1" } */
+/* { dg-final { scan-assembler "lxvd2x" } } */
+/* { dg-final { scan-assembler "xxpermdi" } } */
+
+/* Verify that we don't try to do permute removal in the presence of
+ vec_ste. This used to ICE. */
+#include <altivec.h>
+
+void f (void *p)
+{
+ vector unsigned int u32 = vec_vsx_ld (1, (const unsigned int *)p);
+ vec_ste (u32, 1, (unsigned int *)p);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-2.c
new file mode 100644
index 0000000..6ce041a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-2.c
@@ -0,0 +1,41 @@
+/* { dg-do compile { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+/* { dg-final { scan-assembler "lxvd2x" } } */
+/* { dg-final { scan-assembler "stxvd2x" } } */
+/* { dg-final { scan-assembler-not "xxpermdi" } } */
+
+void abort ();
+
+#define N 256
+signed char ca[N] __attribute__((aligned(16)));
+signed char cb[N] __attribute__((aligned(16)));
+signed char cc[N] __attribute__((aligned(16)));
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ for (i = 0; i < N; i++) {
+ ca[i] = cb[i] - cc[i];
+ }
+}
+
+__attribute__((noinline)) void init ()
+{
+ int i;
+ for (i = 0; i < N; ++i) {
+ cb[i] = i - 128;
+ cc[i] = i/2 - 64;
+ }
+}
+
+int main ()
+{
+ int i;
+ init ();
+ foo ();
+ for (i = 0; i < N; ++i)
+ if (ca[i] != i - i/2 - 64)
+ abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-3.c
new file mode 100644
index 0000000..35dacd4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-3.c
@@ -0,0 +1,43 @@
+/* { dg-do compile { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+/* { dg-final { scan-assembler "lxvd2x" } } */
+/* { dg-final { scan-assembler "stxvd2x" } } */
+/* { dg-final { scan-assembler-not "xxpermdi" } } */
+
+void abort ();
+
+#define N 4096
+signed char ca[N] __attribute__((aligned(16)));
+signed char cb[N] __attribute__((aligned(16)));
+signed char cc[N] __attribute__((aligned(16)));
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ for (i = 0; i < N; i++) {
+ ca[i] = cb[i] - cc[i];
+ }
+}
+
+__attribute__((noinline)) void init ()
+{
+ int i, ii;
+ for (i = 0, ii = 0; i < N; ++i, ii = (ii + 1) % 128) {
+ cb[i] = ii - 128;
+ cc[i] = ii/2 - 64;
+ }
+}
+
+int main ()
+{
+ int i, ii;
+ init ();
+ foo ();
+ for (i = 0; i < N; ++i) {
+ ii = i % 128;
+ if (ca[i] != ii - ii/2 - 64)
+ abort ();
+ }
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-4.c
new file mode 100644
index 0000000..61fe99b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-4.c
@@ -0,0 +1,45 @@
+/* { dg-do compile { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+/* { dg-final { scan-assembler "lxvd2x" } } */
+/* { dg-final { scan-assembler "stxvd2x" } } */
+/* { dg-final { scan-assembler-not "xxpermdi" } } */
+
+void abort ();
+
+#define N 4096
+int ca[N] __attribute__((aligned(16)));
+int cb[N] __attribute__((aligned(16)));
+int cc[N] __attribute__((aligned(16)));
+int cd[N] __attribute__((aligned(16)));
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ for (i = 0; i < N; i++) {
+ ca[i] = (cb[i] + cc[i]) * cd[i];
+ }
+}
+
+__attribute__((noinline)) void init ()
+{
+ int i;
+ for (i = 0; i < N; ++i) {
+ cb[i] = 3 * i - 2048;
+ cc[i] = -5 * i + 93;
+ cd[i] = i % 2 ? 1 : -1;
+ }
+}
+
+int main ()
+{
+ int i;
+ init ();
+ foo ();
+ for (i = 0; i < N; ++i)
+ if (i % 2 == 1 && ca[i] != -2 * i - 1955)
+ abort ();
+ else if (i % 2 == 0 && ca[i] != 1955 + 2 * i)
+ abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-5.c
new file mode 100644
index 0000000..b367fb6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-5.c
@@ -0,0 +1,45 @@
+/* { dg-do compile { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+/* { dg-final { scan-assembler "lxvd2x" } } */
+/* { dg-final { scan-assembler "stxvd2x" } } */
+/* { dg-final { scan-assembler-not "xxpermdi" } } */
+
+void abort ();
+
+#define N 4096
+int ca[N] __attribute__((aligned(16)));
+int cb[N] __attribute__((aligned(16)));
+int cc[N] __attribute__((aligned(16)));
+int cd[N] __attribute__((aligned(16)));
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ for (i = 0; i < N; i++) {
+ ca[i] = ((cb[i] + cc[i]) * cd[i]) >> 3;
+ }
+}
+
+__attribute__((noinline)) void init ()
+{
+ int i;
+ for (i = 0; i < N; ++i) {
+ cb[i] = 3 * i - 2048;
+ cc[i] = -5 * i + 93;
+ cd[i] = i % 2 ? 1 : -1;
+ }
+}
+
+int main ()
+{
+ int i;
+ init ();
+ foo ();
+ for (i = 0; i < N; ++i)
+ if (i % 2 == 1 && ca[i] != (-2 * i - 1955) >> 3)
+ abort ();
+ else if (i % 2 == 0 && ca[i] != (1955 + 2 * i) >> 3)
+ abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-6.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-6.c
new file mode 100644
index 0000000..f708452
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-6.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+
+void abort();
+
+#define N 16
+
+signed char ca[N] __attribute__((aligned(16)));
+signed char cb[] __attribute__((aligned(16)))
+ = {8, 7, 6, 5, 4, 3, 2, 1, 0, -1, -2, -3, -4, -5, -6, -7};
+signed char cc[] __attribute__((aligned(16)))
+ = {1, 1, 2, 2, 3, 3, 2, 2, 1, 1, 0, 0, -1, -1, -2, -2};
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ for (i = 0; i < N; i++) {
+ ca[i] = cb[i] - cc[i];
+ }
+}
+
+int main ()
+{
+ signed char cd[] = {7, 6, 4, 3, 1, 0, 0, -1, -1, -2, -2, -3, -3, -4, -4, -5};
+ int i;
+ foo ();
+ for (i = 0; i < N; ++i)
+ if (ca[i] != cd[i])
+ abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-7.c
new file mode 100644
index 0000000..27a31b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-7.c
@@ -0,0 +1,38 @@
+/* { dg-do run { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+
+void abort ();
+
+#define N 256
+signed char ca[N] __attribute__((aligned(16)));
+signed char cb[N] __attribute__((aligned(16)));
+signed char cc[N] __attribute__((aligned(16)));
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ for (i = 0; i < N; i++) {
+ ca[i] = cb[i] - cc[i];
+ }
+}
+
+__attribute__((noinline)) void init ()
+{
+ int i;
+ for (i = 0; i < N; ++i) {
+ cb[i] = i - 128;
+ cc[i] = i/2 - 64;
+ }
+}
+
+int main ()
+{
+ int i;
+ init ();
+ foo ();
+ for (i = 0; i < N; ++i)
+ if (ca[i] != i - i/2 - 64)
+ abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-8.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-8.c
new file mode 100644
index 0000000..7264d25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-8.c
@@ -0,0 +1,40 @@
+/* { dg-do run { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+
+void abort ();
+
+#define N 4096
+signed char ca[N] __attribute__((aligned(16)));
+signed char cb[N] __attribute__((aligned(16)));
+signed char cc[N] __attribute__((aligned(16)));
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ for (i = 0; i < N; i++) {
+ ca[i] = cb[i] - cc[i];
+ }
+}
+
+__attribute__((noinline)) void init ()
+{
+ int i, ii;
+ for (i = 0, ii = 0; i < N; ++i, ii = (ii + 1) % 128) {
+ cb[i] = ii - 128;
+ cc[i] = ii/2 - 64;
+ }
+}
+
+int main ()
+{
+ int i, ii;
+ init ();
+ foo ();
+ for (i = 0; i < N; ++i) {
+ ii = i % 128;
+ if (ca[i] != ii - ii/2 - 64)
+ abort ();
+ }
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-9.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-9.c
new file mode 100644
index 0000000..cdca070
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/swaps-p8-9.c
@@ -0,0 +1,42 @@
+/* { dg-do run { target { powerpc64le-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O3" } */
+
+void abort ();
+
+#define N 4096
+int ca[N] __attribute__((aligned(16)));
+int cb[N] __attribute__((aligned(16)));
+int cc[N] __attribute__((aligned(16)));
+int cd[N] __attribute__((aligned(16)));
+
+__attribute__((noinline)) void foo ()
+{
+ int i;
+ for (i = 0; i < N; i++) {
+ ca[i] = (cb[i] + cc[i]) * cd[i];
+ }
+}
+
+__attribute__((noinline)) void init ()
+{
+ int i;
+ for (i = 0; i < N; ++i) {
+ cb[i] = 3 * i - 2048;
+ cc[i] = -5 * i + 93;
+ cd[i] = i % 2 ? 1 : -1;
+ }
+}
+
+int main ()
+{
+ int i;
+ init ();
+ foo ();
+ for (i = 0; i < N; ++i)
+ if (i % 2 == 1 && ca[i] != -2 * i - 1955)
+ abort ();
+ else if (i % 2 == 0 && ca[i] != 1955 + 2 * i)
+ abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c
index 836b385..934cdad 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O3 -mcpu=power7" } */
+/* { dg-options "-O3 -mcpu=power7 -Wno-deprecated" } */
/* Test the various load/store varients. */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c
index e1f0ca8..c4e76e6 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-extract-1.c
@@ -7,10 +7,4 @@
#include <altivec.h>
-#if __LITTLE_ENDIAN__
-#define OFFSET 1
-#else
-#define OFFSET 0
-#endif
-
-double get_value (vector double *p) { return vec_extract (*p, OFFSET); }
+double get_value (vector double *p) { return vec_extract (*p, 0); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/warn-lvsl-lvsr.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/warn-lvsl-lvsr.c
new file mode 100644
index 0000000..bf889aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/warn-lvsl-lvsr.c
@@ -0,0 +1,14 @@
+/* Test for deprecation messages on use of lvsl and lvsr for little endian. */
+
+/* { dg-do compile { target { powerpc64le-*-* } } } */
+/* { dg-options "-O0 -Wdeprecated" } */
+
+#include <altivec.h>
+
+float f[20];
+
+void foo ()
+{
+ vector unsigned char a = vec_lvsl (4, f); /* { dg-warning "vec_lvsl is deprecated for little endian; use assignment for unaligned loads and stores" } */
+ vector unsigned char b = vec_lvsr (8, f); /* { dg-warning "vec_lvsr is deprecated for little endian; use assignment for unaligned loads and stores" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c
index f2cd2de..3208f93 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c
@@ -3,12 +3,12 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
-/* { dg-final { scan-assembler-times "tst" 5 } } */
-/* { dg-final { scan-assembler-times "movt" 0 } } */
+/* { dg-final { scan-assembler-times "tst" 6 } } */
+/* { dg-final { scan-assembler-times "movt" 1 } } */
/* { dg-final { scan-assembler-times "nott" 1 } } */
/* { dg-final { scan-assembler-times "cmp/eq" 2 } } */
/* { dg-final { scan-assembler-times "cmp/hi" 4 } } */
/* { dg-final { scan-assembler-times "cmp/gt" 3 } } */
-/* { dg-final { scan-assembler-times "not\t" 1 } } */
+/* { dg-final { scan-assembler-not "not\t" } } */
#include "pr51244-20.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20.c
index a9ded46..aad6a2f 100644
--- a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20.c
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20.c
@@ -1,15 +1,15 @@
/* Check that the SH specific sh_treg_combine RTL optimization pass works as
expected. On SH2A the expected insns are slightly different, see
- pr51244-21.c. */
+ pr51244-20-sh2a.c. */
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
-/* { dg-final { scan-assembler-times "tst" 6 } } */
-/* { dg-final { scan-assembler-times "movt" 1 } } */
+/* { dg-final { scan-assembler-times "tst" 7 } } */
+/* { dg-final { scan-assembler-times "movt" 2 } } */
/* { dg-final { scan-assembler-times "cmp/eq" 2 } } */
/* { dg-final { scan-assembler-times "cmp/hi" 4 } } */
/* { dg-final { scan-assembler-times "cmp/gt" 2 } } */
-/* { dg-final { scan-assembler-times "not\t" 1 } } */
+/* { dg-final { scan-assembler-not "not\t" } } */
/* non-SH2A: 2x tst, 1x movt, 2x cmp/eq, 1x cmp/hi
@@ -81,7 +81,7 @@ get_request_2 (int* q, int rw)
}
-/* 2x tst, 1x cmp/hi, 1x not */
+/* 3x tst, 1x movt, 1x cmp/hi, 1x not */
static inline int
blk_oversized_queue_5 (int* q)
{
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr64507.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr64507.c
new file mode 100644
index 0000000..d3d9384
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr64507.c
@@ -0,0 +1,25 @@
+/* Check that the __builtin_strnlen returns 0 with with
+ non-constant 0 length. */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern int snprintf(char *, int, const char *, ...);
+extern void abort (void);
+
+int main()
+ {
+ int i;
+ int cmp = 0;
+ char buffer[1024];
+ const char* s = "the string";
+
+ snprintf(buffer, 4, "%s", s);
+
+ for (i = 1; i < 4; i++)
+ cmp += __builtin_strncmp(buffer, s, i - 1);
+
+ if (cmp)
+ abort();
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr63783-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr63783-1.c
new file mode 100644
index 0000000..f18bead
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr63783-1.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-additional-options "-std=c99" } */
+
+#include <assert.h>
+
+int decision_result;
+int val;
+int truecount = 0;
+
+static void __attribute__((noinline))
+buggy (int flag)
+{
+ int condition;
+ if(flag == 0)
+ condition = val != 0;
+ else
+ condition = !decision_result;
+ if (condition)
+ truecount++;
+}
+
+int
+main (void)
+{
+ decision_result = 1;
+ buggy(1);
+ assert (truecount == 0);
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr63783-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr63783-2.c
new file mode 100644
index 0000000..c0bc911
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr63783-2.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-additional-options "-std=c99" } */
+
+#include <assert.h>
+
+long long decision_result;
+long long val;
+int truecount = 0;
+
+static void __attribute__((noinline))
+buggy (int flag)
+{
+ int condition;
+ if(flag == 0)
+ condition = val != 0;
+ else
+ condition = !decision_result;
+ if (condition)
+ truecount++;
+}
+
+int
+main (void)
+{
+ decision_result = 1;
+ buggy(1);
+ assert (truecount == 0);
+ return 0;
+}