diff options
author | Ben Cheng <bccheng@google.com> | 2014-03-25 22:37:19 -0700 |
---|---|---|
committer | Ben Cheng <bccheng@google.com> | 2014-03-25 22:37:19 -0700 |
commit | 1bc5aee63eb72b341f506ad058502cd0361f0d10 (patch) | |
tree | c607e8252f3405424ff15bc2d00aa38dadbb2518 /gcc-4.9/gcc/testsuite/gcc.target/arm/shiftable.c | |
parent | 283a0bf58fcf333c58a2a92c3ebbc41fb9eb1fdb (diff) | |
download | toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.tar.gz toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.tar.bz2 toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.zip |
Initial checkin of GCC 4.9.0 from trunk (r208799).
Change-Id: I48a3c08bb98542aa215912a75f03c0890e497dba
Diffstat (limited to 'gcc-4.9/gcc/testsuite/gcc.target/arm/shiftable.c')
-rw-r--r-- | gcc-4.9/gcc/testsuite/gcc.target/arm/shiftable.c | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/shiftable.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/shiftable.c new file mode 100644 index 000000000..f3080620a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/shiftable.c @@ -0,0 +1,63 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-require-effective-target arm32 } */ + +/* ARM has shift-and-alu insns. Depending on the ALU op GCC represents some + of these as a left shift, others as a multiply. Check that we match the + right one. */ + +int +plus (int a, int b) +{ + return (a * 64) + b; +} + +/* { dg-final { scan-assembler "add.*\[al]sl #6" } } */ + +int +minus (int a, int b) +{ + return a - (b * 64); +} + +/* { dg-final { scan-assembler "sub.*\[al]sl #6" } } */ + +int +ior (int a, int b) +{ + return (a * 64) | b; +} + +/* { dg-final { scan-assembler "orr.*\[al]sl #6" } } */ + +int +xor (int a, int b) +{ + return (a * 64) ^ b; +} + +/* { dg-final { scan-assembler "eor.*\[al]sl #6" } } */ + +int +and (int a, int b) +{ + return (a * 64) & b; +} + +/* { dg-final { scan-assembler "and.*\[al]sl #6" } } */ + +int +rsb (int a, int b) +{ + return (a * 64) - b; +} + +/* { dg-final { scan-assembler "rsb.*\[al]sl #6" } } */ + +int +mvn (int a, int b) +{ + return ~(a * 64); +} + +/* { dg-final { scan-assembler "mvn.*\[al]sl #6" } } */ |