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authorBen Cheng <bccheng@google.com>2014-03-26 05:37:19 (GMT)
committerBen Cheng <bccheng@google.com>2014-03-26 05:37:19 (GMT)
commit1bc5aee63eb72b341f506ad058502cd0361f0d10 (patch)
treec607e8252f3405424ff15bc2d00aa38dadbb2518 /gcc-4.9/gcc/testsuite/gcc.target/aarch64
parent283a0bf58fcf333c58a2a92c3ebbc41fb9eb1fdb (diff)
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Initial checkin of GCC 4.9.0 from trunk (r208799).
Change-Id: I48a3c08bb98542aa215912a75f03c0890e497dba
Diffstat (limited to 'gcc-4.9/gcc/testsuite/gcc.target/aarch64')
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/121127.c4
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp67
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-2.h101
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-common.h139
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.S59
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.h159
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c44
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c71
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c93
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c27
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_1.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_2.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_3.c16
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_4.c9
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_5.c20
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/macro-def.h286
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_1.c31
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_10.c26
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_11.c34
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_12.c44
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_13.c34
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_14.c35
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_15.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_16.c32
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_17.c37
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c34
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_19.c35
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_2.c16
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_20.c22
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_21.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_22.c19
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_23.c42
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_24.c22
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_25.c61
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_26.c54
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_3.c18
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_4.c20
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_5.c24
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_6.c26
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_7.c30
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_8.c24
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_9.c32
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-1.c126
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-2.c42
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-3.c46
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-4.c42
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_complex.c18
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_int128.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_quad_double.c26
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h157
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-1.c50
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-10.c29
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-11.c32
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-12.c60
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-2.c59
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-3.c86
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-4.c93
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-5.c47
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-6.c40
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-7.c31
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-8.c25
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-9.c31
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/validate_memory.h81
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aarch64.exp45
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/abs_1.c53
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/adc-1.c18
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/adc-2.c277
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds.c30
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds1.c149
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds2.c155
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds3.c61
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/aes_1.c40
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/ands_1.c151
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/ands_2.c157
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-1.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-2.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/arg-type-diagnostics-1.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-1.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-adder-clobber-lr.c23
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-adder-no-clobber-lr.c23
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x36
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x37
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x37
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x37
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x37
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c78
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x37
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c45
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x37
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x37
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x37
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x37
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/bfxil_1.c40
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/bfxil_2.c42
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/bics_1.c107
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/bics_2.c111
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/builtin-bswap-1.c18
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/builtin-bswap-2.c18
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template-2.c9
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template-3.c10
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template.c9
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/clrsb.c9
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/clz.c9
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn-neg.c33
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn-neg2.c34
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn.c24
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmp-1.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmp.c61
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-4.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinc-1.c72
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinc-2.c18
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinv-1.c50
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/csneg-1.c50
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/ctz.c11
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/dwarf-cfa-reg.c14
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/extend.c170
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/extr.c34
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fabd.c38
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt.x55
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c21
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/ffs.c12
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmadd.c55
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c116
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c117
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovd-zero.c10
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovd.c10
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovf-zero.c10
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-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint.x66
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-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic-compile.c11
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.c28
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.x27
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vclz.c574
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vdiv_f.c361
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c12
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs.c134
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs.x36
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-clz.c35
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-compile.c22
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv-compile.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv.c31
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv.x23
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c16
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c16
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c16
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c16
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm.x124
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin-compile.c7
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.c105
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.x32
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv-compile.c10
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv.x43
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovd.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovf-zero.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovf.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c14
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp.c148
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp.x60
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c13
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c18
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-fp.c51
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r.c65
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r.x15
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-movi.c74
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c24
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull.c138
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull.x49
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c128
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vca.c89
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vcvt.c132
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vfmaxv.c169
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c117
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vrnd.c117
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect.c97
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect.x154
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect_saddl_1.c315
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c325
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c803
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vfp-1.c109
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vld1-vst1_1.c52
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vmlsq_laneq.c158
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vmov_n_1.c349
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vneg_f.c270
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vneg_s.c309
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-1.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-2.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-3.c17
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vrecps.c144
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vrecpx.c54
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vsqrt.c72
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/aarch64/vsub_f64.c116
273 files changed, 18151 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/121127.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/121127.c
new file mode 100644
index 0000000..a7dca09
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/121127.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-g -femit-struct-debug-baseonly" } */
+
+typedef __builtin_va_list __gnuc_va_list;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp
new file mode 100644
index 0000000..195f977
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp
@@ -0,0 +1,67 @@
+# Copyright (C) 2009-2014 Free Software Foundation, Inc.
+# Contributed by ARM Ltd.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>. */
+
+load_lib c-torture.exp
+load_lib target-supports.exp
+load_lib torture-options.exp
+
+if { ![istarget aarch64*-*-*] } then {
+ return
+}
+
+torture-init
+set-torture-options $C_TORTURE_OPTIONS
+set additional_flags "-W -Wall -Wno-abi"
+
+# Test parameter passing.
+foreach src [lsort [glob -nocomplain $srcdir/$subdir/test_*.c]] {
+ if {[runtest_file_p $runtests $src]} {
+ c-torture-execute [list $src \
+ $srcdir/$subdir/abitest.S] \
+ $additional_flags
+ }
+}
+
+# Test unnamed argument retrieval via the va_arg macro.
+foreach src [lsort [glob -nocomplain $srcdir/$subdir/va_arg-*.c]] {
+ if {[runtest_file_p $runtests $src]} {
+ c-torture-execute [list $src \
+ $srcdir/$subdir/abitest.S] \
+ $additional_flags
+ }
+}
+
+# Test function return value.
+foreach src [lsort [glob -nocomplain $srcdir/$subdir/func-ret-*.c]] {
+ if {[runtest_file_p $runtests $src]} {
+ c-torture-execute [list $src \
+ $srcdir/$subdir/abitest.S] \
+ $additional_flags
+ }
+}
+
+# Test no internal compiler errors.
+foreach src [lsort [glob -nocomplain $srcdir/$subdir/ice_*.c]] {
+ if {[runtest_file_p $runtests $src]} {
+ c-torture [list $src] \
+ $additional_flags
+ }
+}
+
+torture-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-2.h b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-2.h
new file mode 100644
index 0000000..c56e7cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-2.h
@@ -0,0 +1,101 @@
+/* This header file should be included for the purpose of function return
+ value testing. */
+
+#include "abitest-common.h"
+#include "validate_memory.h"
+
+void (*testfunc_ptr)(char* stack);
+
+/* Helper macros to generate function name. Example of the function name:
+ func_return_val_1. */
+#define FUNC_BASE_NAME func_return_val_
+#define FUNC_NAME_COMBINE(base,suffix) base ## suffix
+#define FUNC_NAME_1(base,suffix) FUNC_NAME_COMBINE(base,suffix)
+#define FUNC_NAME(suffix) FUNC_NAME_1(FUNC_BASE_NAME,suffix)
+#define TEST_FUNC_BASE_NAME testfunc_
+#define TEST_FUNC_NAME(suffix) FUNC_NAME_1(TEST_FUNC_BASE_NAME,suffix)
+
+#undef DUMP_STATUS
+#ifdef DUMP_ENABLED
+#define DUMP_STATUS(type,val) printf ("### Checking "#type" "#val"\n");
+#else
+#define DUMP_STATUS(type,val)
+#endif
+
+/* Generate code to do memcmp to check if the returned value is in the
+ correct location and has the expected value.
+ Note that for value that is returned in the caller-allocated memory
+ block, we get the address from the saved x8 register. x8 is saved
+ just after the callee is returned; we assume that x8 has not been
+ clobbered at then, although there is no requirement for the callee
+ preserve the value stored in x8. Luckily, all test cases here are
+ simple enough that x8 doesn't normally get clobbered (although not
+ guaranteed). */
+#undef FUNC_VAL_CHECK
+#define FUNC_VAL_CHECK(id, type, val, offset, layout) \
+void TEST_FUNC_NAME(id)(char* stack) \
+{ \
+ type __x = val; \
+ char* addr; \
+ DUMP_STATUS(type,val) \
+ if (offset != X8) \
+ addr = stack + offset; \
+ else \
+ addr = *(char **)(stack + X8); \
+ if (validate_memory (&__x, addr, sizeof (type), layout) != 0) \
+ abort(); \
+}
+
+/* Composite larger than 16 bytes is replaced by a pointer to a copy prepared
+ by the caller, so here we extrat the pointer, deref it and compare the
+ content with that of the original one. */
+#define PTR(type, val, offset, ...) { \
+ type * ptr; \
+ DUMP_ARG(type,val) \
+ ptr = *(type **)(stack + offset); \
+ if (memcmp (ptr, &val, sizeof (type)) != 0) abort (); \
+}
+
+#include TESTFILE
+
+MYFUNCTYPE myfunc () PCSATTR;
+
+/* Define the function to return VAL of type TYPE. I and D in the
+ parameter list are two dummy parameters to help improve the detection
+ of bugs like a short vector being returned in X0 after copied from V0. */
+#undef FUNC_VAL_CHECK
+#define FUNC_VAL_CHECK(id, type, var, offset, layout) \
+__attribute__ ((noinline)) type FUNC_NAME (id) (int i, double d, type t) \
+ { \
+ asm (""::"r" (i),"r" (d)); /* asm prevents function from getting \
+ optimized away. Using i and d prevents \
+ warnings about unused parameters. \
+ */ \
+ return t; \
+ }
+#include TESTFILE
+
+
+/* Call the function to return value and call the checking function
+ to validate. See the comment above for the reason of having 0 and 0.0
+ in the function argument list. */
+#undef FUNC_VAL_CHECK
+#define FUNC_VAL_CHECK(id, type, var, offset, layout) \
+ { \
+ testfunc_ptr = TEST_FUNC_NAME(id); \
+ FUNC_NAME(id) (0, 0.0, var); \
+ myfunc (); \
+ }
+
+int main()
+{
+ which_kind_of_test = TK_RETURN;
+
+#ifdef HAS_DATA_INIT_FUNC
+ init_data ();
+#endif
+
+#include TESTFILE
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-common.h b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-common.h
new file mode 100644
index 0000000..4e2ef0d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-common.h
@@ -0,0 +1,139 @@
+#undef __AAPCS64_BIG_ENDIAN__
+#ifdef __GNUC__
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+#define __AAPCS64_BIG_ENDIAN__
+#endif
+#else
+#error unknown compiler
+#endif
+
+#define IN_FRAMEWORK
+
+#define D0 0
+#define D1 8
+#define D2 16
+#define D3 24
+#define D4 32
+#define D5 40
+#define D6 48
+#define D7 56
+
+#define S0 64
+#define S1 68
+#define S2 72
+#define S3 76
+#define S4 80
+#define S5 84
+#define S6 88
+#define S7 92
+
+#define W0 96
+#define W1 100
+#define W2 104
+#define W3 108
+#define W4 112
+#define W5 116
+#define W6 120
+#define W7 124
+
+#define X0 128
+#define X1 136
+#define X2 144
+#define X3 152
+#define X4 160
+#define X5 168
+#define X6 176
+#define X7 184
+
+#define Q0 192
+#define Q1 208
+#define Q2 224
+#define Q3 240
+#define Q4 256
+#define Q5 272
+#define Q6 288
+#define Q7 304
+
+#define X8 320
+#define X9 328
+
+#define STACK 336
+
+/* The type of test. 'myfunc' in abitest.S needs to know which kind of
+ test it is running to decide what to do at the runtime. Keep the
+ related code in abitest.S synchronized if anything is changed here. */
+enum aapcs64_test_kind
+{
+ TK_PARAM = 0, /* Test parameter passing. */
+ TK_VA_ARG, /* Test va_arg code generation. */
+ TK_RETURN /* Test function return value. */
+};
+
+int which_kind_of_test;
+
+extern int printf (const char*, ...);
+extern void abort (void);
+extern void dumpregs () __asm("myfunc");
+
+#ifndef MYFUNCTYPE
+#define MYFUNCTYPE void
+#endif
+
+#ifndef PCSATTR
+#define PCSATTR
+#endif
+
+
+#ifdef RUNTIME_ENDIANNESS_CHECK
+#ifndef RUNTIME_ENDIANNESS_CHECK_FUNCTION_DEFINED
+/* This helper function defined to detect whether there is any incompatibility
+ issue on endianness between compilation time and run-time environments.
+ TODO: review the implementation when the work of big-endian support in A64
+ GCC starts.
+ */
+static void rt_endian_check ()
+{
+ const char* msg_endian[2] = {"little-endian", "big-endian"};
+ const char* msg_env[2] = {"compile-time", "run-time"};
+ union
+ {
+ unsigned int ui;
+ unsigned char ch[4];
+ } u;
+ int flag = -1;
+
+ u.ui = 0xCAFEBABE;
+
+ printf ("u.ui=0x%X, u.ch[0]=0x%X\n", u.ui, u.ch[0]);
+
+ if (u.ch[0] == 0xBE)
+ {
+ /* Little-Endian at run-time */
+#ifdef __AAPCS64_BIG_ENDIAN__
+ /* Big-Endian at compile-time */
+ flag = 1;
+#endif
+ }
+ else
+ {
+ /* Big-Endian at run-time */
+#ifndef __AAPCS64_BIG_ENDIAN__
+ /* Little-Endian at compile-time */
+ flag = 0;
+#endif
+ }
+
+ if (flag != -1)
+ {
+ /* Endianness conflict exists */
+ printf ("Error: endianness conflicts between %s and %s:\n\
+\t%s: %s\n\t%s: %s\n", msg_env[0], msg_env[1], msg_env[0], msg_endian[flag],
+ msg_env[1], msg_endian[1-flag]);
+ abort ();
+ }
+
+ return;
+}
+#endif
+#define RUNTIME_ENDIANNESS_CHECK_FUNCTION_DEFINED
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.S b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.S
new file mode 100644
index 0000000..86ce7be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.S
@@ -0,0 +1,59 @@
+ .global dumpregs
+ .global myfunc
+ .type dumpregs,%function
+ .type myfunc,%function
+dumpregs:
+myfunc:
+ mov x16, sp
+ mov x17, sp
+ sub sp, sp, 352 // 336 for registers and 16 for old sp and lr
+
+ stp x8, x9, [x17, #-16]! //320
+
+ stp q6, q7, [x17, #-32]! //288
+ stp q4, q5, [x17, #-32]! //256
+ stp q2, q3, [x17, #-32]! //224
+ stp q0, q1, [x17, #-32]! //192
+
+ stp x6, x7, [x17, #-16]! //176
+ stp x4, x5, [x17, #-16]! //160
+ stp x2, x3, [x17, #-16]! //144
+ stp x0, x1, [x17, #-16]! //128
+
+ stp w6, w7, [x17, #-8]! //120
+ stp w4, w5, [x17, #-8]! //112
+ stp w2, w3, [x17, #-8]! //104
+ stp w0, w1, [x17, #-8]! // 96
+
+ stp s6, s7, [x17, #-8]! // 88
+ stp s4, s5, [x17, #-8]! // 80
+ stp s2, s3, [x17, #-8]! // 72
+ stp s0, s1, [x17, #-8]! // 64
+
+ stp d6, d7, [x17, #-16]! // 48
+ stp d4, d5, [x17, #-16]! // 32
+ stp d2, d3, [x17, #-16]! // 16
+ stp d0, d1, [x17, #-16]! // 0
+
+ add x0, sp, #16
+ stp x16, x30, [x17, #-16]!
+
+ adrp x9, which_kind_of_test // determine the type of test
+ add x9, x9, :lo12:which_kind_of_test
+ ldr w9, [x9, #0]
+ cmp w9, #1
+ bgt LABEL_TEST_FUNC_RETURN
+ bl testfunc // parameter passing test or va_arg code gen test
+ b LABEL_RET
+LABEL_TEST_FUNC_RETURN:
+ adrp x9, testfunc_ptr
+ add x9, x9, :lo12:testfunc_ptr
+ ldr x9, [x9, #0]
+ blr x9 // function return value test
+LABEL_RET:
+ ldp x0, x30, [sp]
+ mov sp, x0
+ ret
+
+.weak testfunc
+.weak testfunc_ptr
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.h b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.h
new file mode 100644
index 0000000..af70937
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.h
@@ -0,0 +1,159 @@
+/* This header file should be included for the purpose of parameter passing
+ testing and va_arg code gen testing.
+
+ To test va_arg code gen, #define AAPCS64_TEST_STDARG in the test case.
+
+ The parameter passing test is done by passing variables/constants to
+ 'myfunc', which pushes its incoming arguments to a memory block on the
+ stack and then passes the memory block address to 'testfunc'. It is inside
+ 'testfunc' that the real parameter passing check is carried out.
+
+ The function body of 'myfunc' is in abitest.S. The declaration of 'myfunc'
+ is constructed during the pre-processing stage.
+
+ The va_arg code gen test has a similar workflow, apart from an extra set-up
+ step before calling 'myfunc'. All arguments are passed to 'stdarg_func'
+ first, which assigned these arguments to its local variables via either
+ direct assignment or va_arg macro, depending on whether an argument is named
+ or not. Afterwards, 'stdarg_func' calls 'myfunc' with the aforementioned
+ local variables as the arguments to finish the remaining steps. */
+
+#include "abitest-common.h"
+#include "validate_memory.h"
+
+#ifdef AAPCS64_TEST_STDARG
+/* Generate va_start (ap, last_named_arg). Note that this requires
+ LAST_NAMED_ARG_ID to be defined/used correctly in the test file. */
+#ifndef LAST_NAMED_ARG_ID
+#define LAST_NAMED_ARG_ID 65535
+#endif
+#ifndef VA_START
+#undef VA_START_1
+#define VA_START_1(ap, id) va_start (ap, _f##id);
+#define VA_START(ap, id) VA_START_1 (ap, id);
+#endif
+#endif /* AAPCS64_TEST_STDARG */
+
+/* Some debugging facility. */
+#undef DUMP_ARG
+#ifdef DUMP_ENABLED
+#define DUMP_ARG(type,val) printf ("### Checking ARG "#type" "#val"\n")
+#else
+#define DUMP_ARG(type,val)
+#endif
+
+
+/* Function called from myfunc (defined in abitest.S) to check the arguments
+ passed to myfunc. myfunc has pushed all the arguments into the memory
+ block pointed by STACK. */
+void testfunc(char* stack)
+{
+#define AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS
+#include "macro-def.h"
+#include TESTFILE
+#undef AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS
+ return;
+}
+
+
+#ifndef AAPCS64_TEST_STDARG
+/* Test parameter passing. */
+
+/* Function declaration of myfunc. */
+MYFUNCTYPE myfunc(
+#define AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST
+#include "macro-def.h"
+#include TESTFILE
+#undef AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST
+) PCSATTR;
+
+#else /* AAPCS64_TEST_STDARG */
+/* Test stdarg macros, e.g. va_arg. */
+#include <stdarg.h>
+
+/* Dummy function to help reset parameter passing registers, i.e. X0-X7
+ and V0-V7 (by being passed 0 in W0-W7 and 0.f in S0-S7). */
+__attribute__ ((noinline)) void
+dummy_func (int w0, int w1, int w2, int w3, int w4, int w5, int w6, int w7,
+ float s0, float s1, float s2, float s3, float s4, float s5,
+ float s6, float s7)
+{
+ asm (""); /* Prevent function from getting optimized away */
+ return;
+}
+
+/* Function declaration of myfunc. */
+MYFUNCTYPE myfunc(
+#define AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST
+#include "macro-def.h"
+#include TESTFILE
+#undef AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST
+) PCSATTR;
+
+/* Function definition of stdarg_func.
+ stdarg_func is a variadic function; it retrieves all of its arguments,
+ both named and unnamed, and passes them to myfunc in the identical
+ order. myfunc will carry out the check on the passed values. Remember
+ that myfunc is not a variadic function. */
+MYFUNCTYPE stdarg_func(
+#define AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT
+#include "macro-def.h"
+#include TESTFILE
+#undef AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT
+) PCSATTR
+{
+ /* Start of the function body of stdarg_func. */
+ va_list ap;
+
+ VA_START (ap, LAST_NAMED_ARG_ID)
+ /* Zeroize the content of X0-X7 and V0-V7 to make sure that any va_arg
+ failure will not be hidden by the old data being in these registers. */
+ dummy_func (0, 0, 0, 0, 0, 0, 0, 0, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f);
+ /* A full memory barrier to ensure that compiler won't optimize away
+ va_arg code gen. */
+ __sync_synchronize ();
+ {
+ /* Assign all the function incoming arguments to local variables. */
+#define AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS
+#include "macro-def.h"
+#include TESTFILE
+#undef AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS
+
+ /* Call myfunc and pass in the local variables prepared above. */
+ myfunc (
+#define AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST
+#include "macro-def.h"
+#include TESTFILE
+#undef AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST
+);
+ }
+ va_end (ap);
+}
+
+#endif /* AAPCS64_TEST_STDARG */
+
+
+int main()
+{
+#ifdef RUNTIME_ENDIANNESS_CHECK
+ rt_endian_check();
+#endif
+#ifdef HAS_DATA_INIT_FUNC
+ init_data ();
+#endif
+
+#ifndef AAPCS64_TEST_STDARG
+ which_kind_of_test = TK_PARAM;
+ myfunc(
+#else
+ which_kind_of_test = TK_VA_ARG;
+ stdarg_func(
+#endif
+#define AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST
+#include "macro-def.h"
+#include TESTFILE
+#undef AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST
+);
+ return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c
new file mode 100644
index 0000000..16b5c1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c
@@ -0,0 +1,44 @@
+/* Test AAPCS64 function result return.
+
+ This test covers most fundamental data types as specified in
+ AAPCS64 \S 4.1. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+/* { dg-additional-sources "abitest.S" } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "func-ret-1.c"
+#include "type-def.h"
+
+vf2_t vf2 = (vf2_t){ 17.f, 18.f };
+vi4_t vi4 = (vi4_t){ 0xdeadbabe, 0xbabecafe, 0xcafebeef, 0xbeefdead };
+union int128_t qword;
+
+int *int_ptr = (int *)0xabcdef0123456789ULL;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ /* Init signed quad-word integer. */
+ qword.l64 = 0xfdb9753102468aceLL;
+ qword.h64 = 0xeca8642013579bdfLL;
+}
+
+#include "abitest-2.h"
+#else
+FUNC_VAL_CHECK (0, unsigned char , 0xfe , X0, i8in64)
+FUNC_VAL_CHECK (1, signed char , 0xed , X0, i8in64)
+FUNC_VAL_CHECK (2, unsigned short, 0xdcba , X0, i16in64)
+FUNC_VAL_CHECK (3, signed short, 0xcba9 , X0, i16in64)
+FUNC_VAL_CHECK (4, unsigned int , 0xdeadbeef, X0, i32in64)
+FUNC_VAL_CHECK (5, signed int , 0xcafebabe, X0, i32in64)
+FUNC_VAL_CHECK (6, unsigned long long, 0xba98765432101234ULL, X0, flat)
+FUNC_VAL_CHECK (7, signed long long, 0xa987654321012345LL, X0, flat)
+FUNC_VAL_CHECK (8, __int128, qword.i, X0, flat)
+FUNC_VAL_CHECK (9, float, 65432.12345f, S0, flat)
+FUNC_VAL_CHECK (10, double, 9876543.212345, D0, flat)
+FUNC_VAL_CHECK (11, long double, 98765432123456789.987654321L, Q0, flat)
+FUNC_VAL_CHECK (12, vf2_t, vf2, D0, f32in64)
+FUNC_VAL_CHECK (13, vi4_t, vi4, Q0, i32in128)
+FUNC_VAL_CHECK (14, int *, int_ptr, X0, flat)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c
new file mode 100644
index 0000000..6b171c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c
@@ -0,0 +1,71 @@
+/* Test AAPCS64 function result return.
+
+ This test covers most composite types as described in AAPCS64 \S 4.3.
+ Homogeneous floating-point aggregate types are covered in func-ret-3.c. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+/* { dg-additional-sources "abitest.S" } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "func-ret-2.c"
+
+struct x0
+{
+ char ch;
+ int i;
+} ys0 = { 'a', 12345 };
+
+struct x1
+{
+ int a;
+ unsigned int b;
+ unsigned int c;
+ unsigned int d;
+} ys1 = { 0xdeadbeef, 0xcafebabe, 0x87654321, 0xbcedf975 };
+
+struct x2
+{
+ long long a;
+ long long b;
+ char ch;
+} y2 = { 0x12, 0x34, 0x56 };
+
+union x3
+{
+ char ch;
+ int i;
+ long long ll;
+} y3;
+
+union x4
+{
+ int i;
+ struct x2 y2;
+} y4;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ /* Init small union. */
+ y3.ll = 0xfedcba98LL;
+
+ /* Init big union. */
+ y4.y2.a = 0x78;
+ y4.y2.b = 0x89;
+ y4.y2.ch= 0x9a;
+}
+
+
+#include "abitest-2.h"
+#else
+ /* Composite smaller than or equal to 16 bytes returned in X0 and X1. */
+FUNC_VAL_CHECK ( 0, struct x0, ys0, X0, flat)
+FUNC_VAL_CHECK ( 1, struct x1, ys1, X0, flat)
+FUNC_VAL_CHECK ( 2, union x3, y3, X0, flat)
+
+ /* Composite larger than 16 bytes returned in the caller-reserved memory
+ block of which the address is passed as an additional argument to the
+ function in X8. */
+FUNC_VAL_CHECK (10, struct x2, y2, X8, flat)
+FUNC_VAL_CHECK (11, union x4, y4, X8, flat)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c
new file mode 100644
index 0000000..ff9b7e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c
@@ -0,0 +1,93 @@
+/* Test AAPCS64 function result return.
+
+ This test covers homogeneous floating-point aggregate types as described
+ in AAPCS64 \S 4.3.5. */
+
+/* { dg-do run { target aarch64-*-* } } */
+/* { dg-additional-sources "abitest.S" } */
+/* { dg-require-effective-target aarch64_big_endian } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "func-ret-3.c"
+#include "type-def.h"
+
+struct hfa_fx1_t hfa_fx1 = {12.345f};
+struct hfa_fx2_t hfa_fx2 = {123.456f, 234.456f};
+struct hfa_dx2_t hfa_dx2 = {234.567, 345.678};
+struct hfa_dx4_t hfa_dx4 = {1234.123, 2345.234, 3456.345, 4567.456};
+struct hfa_ldx3_t hfa_ldx3 = {123456.7890, 234567.8901, 345678.9012};
+struct non_hfa_fx5_t non_hfa_fx5 = {456.789f, 567.890f, 678.901f, 789.012f, 890.123f};
+struct hfa_ffs_t hfa_ffs;
+struct non_hfa_ffs_t non_hfa_ffs;
+struct non_hfa_ffs_2_t non_hfa_ffs_2;
+struct hva_vf2x1_t hva_vf2x1;
+struct hva_vi4x1_t hva_vi4x1;
+struct non_hfa_ffd_t non_hfa_ffd = {23.f, 24.f, 25.0};
+struct non_hfa_ii_t non_hfa_ii = {26, 27};
+struct non_hfa_c_t non_hfa_c = {28};
+struct non_hfa_ffvf2_t non_hfa_ffvf2;
+struct non_hfa_fffd_t non_hfa_fffd = {33.f, 34.f, 35.f, 36.0};
+union hfa_union_t hfa_union;
+union non_hfa_union_t non_hfa_union;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ hva_vf2x1.a = (vf2_t){17.f, 18.f};
+ hva_vi4x1.a = (vi4_t){19, 20, 21, 22};
+
+ non_hfa_ffvf2.a = 29.f;
+ non_hfa_ffvf2.b = 30.f;
+ non_hfa_ffvf2.c = (vf2_t){31.f, 32.f};
+
+ hfa_union.s.a = 37.f;
+ hfa_union.s.b = 38.f;
+ hfa_union.c = 39.f;
+
+ non_hfa_union.a = 40.0;
+ non_hfa_union.b = 41.f;
+
+ hfa_ffs.a = 42.f;
+ hfa_ffs.b = 43.f;
+ hfa_ffs.c.a = 44.f;
+ hfa_ffs.c.b = 45.f;
+
+ non_hfa_ffs.a = 46.f;
+ non_hfa_ffs.b = 47.f;
+ non_hfa_ffs.c.a = 48.0;
+ non_hfa_ffs.c.b = 49.0;
+
+ non_hfa_ffs_2.s.a = 50;
+ non_hfa_ffs_2.s.b = 51;
+ non_hfa_ffs_2.c = 52.f;
+ non_hfa_ffs_2.d = 53.f;
+}
+
+#include "abitest-2.h"
+#else
+ /* HFA returned in fp/simd registers. */
+
+FUNC_VAL_CHECK ( 0, struct hfa_fx1_t , hfa_fx1 , S0, flat)
+FUNC_VAL_CHECK ( 1, struct hfa_fx2_t , hfa_fx2 , S0, flat)
+FUNC_VAL_CHECK ( 2, struct hfa_dx2_t , hfa_dx2 , D0, flat)
+
+FUNC_VAL_CHECK ( 3, struct hfa_dx4_t , hfa_dx4 , D0, flat)
+FUNC_VAL_CHECK ( 4, struct hfa_ldx3_t, hfa_ldx3 , Q0, flat)
+FUNC_VAL_CHECK ( 5, struct hfa_ffs_t , hfa_ffs , S0, flat)
+FUNC_VAL_CHECK ( 6, union hfa_union_t, hfa_union, S0, flat)
+
+FUNC_VAL_CHECK ( 7, struct hva_vf2x1_t, hva_vf2x1, D0, flat)
+FUNC_VAL_CHECK ( 8, struct hva_vi4x1_t, hva_vi4x1, Q0, flat)
+
+ /* Non-HFA returned in general registers or via a pointer in X8. */
+FUNC_VAL_CHECK (10, struct non_hfa_fx5_t , non_hfa_fx5 , X8, flat)
+FUNC_VAL_CHECK (13, struct non_hfa_ffd_t , non_hfa_ffd , X0, flat)
+FUNC_VAL_CHECK (14, struct non_hfa_ii_t , non_hfa_ii , X0, flat)
+FUNC_VAL_CHECK (15, struct non_hfa_c_t , non_hfa_c , X0, flat)
+FUNC_VAL_CHECK (16, struct non_hfa_ffvf2_t, non_hfa_ffvf2, X0, flat)
+FUNC_VAL_CHECK (17, struct non_hfa_fffd_t , non_hfa_fffd , X8, flat)
+FUNC_VAL_CHECK (18, struct non_hfa_ffs_t , non_hfa_ffs , X8, flat)
+FUNC_VAL_CHECK (19, struct non_hfa_ffs_2_t, non_hfa_ffs_2, X0, flat)
+FUNC_VAL_CHECK (20, union non_hfa_union_t, non_hfa_union, X0, flat)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c
new file mode 100644
index 0000000..af05fbe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c
@@ -0,0 +1,27 @@
+/* Test AAPCS64 function result return.
+
+ This test covers complex types. Complex floating-point types are treated
+ as homogeneous floating-point aggregates, while complex integral types
+ are treated as general composite types. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+/* { dg-additional-sources "abitest.S" } */
+/* { dg-require-effective-target aarch64_big_endian } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "func-ret-4.c"
+
+#include "abitest-2.h"
+#else
+ /* Complex floating-point types are passed in fp/simd registers. */
+FUNC_VAL_CHECK ( 0, _Complex float , 12.3f + 23.4fi, S0, flat)
+FUNC_VAL_CHECK ( 1, _Complex double, 34.56 + 45.67i, D0, flat)
+FUNC_VAL_CHECK ( 2, _Complex long double, 56789.01234 + 67890.12345i, Q0, flat)
+
+ /* Complex integral types are passed in general registers or via a pointer in
+ X8. */
+FUNC_VAL_CHECK (10, _Complex short , 12345 + 23456i, X0, flat)
+FUNC_VAL_CHECK (11, _Complex int , 34567 + 45678i, X0, flat)
+FUNC_VAL_CHECK (12, _Complex __int128, 567890 + 678901i, X8, flat)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_1.c
new file mode 100644
index 0000000..906cceb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_1.c
@@ -0,0 +1,21 @@
+/* Test AAPCS layout
+
+ Empty, i.e. zero-sized, small struct passing used to cause Internal Compiler
+ Error. */
+
+/* { dg-do compile { target aarch64*-*-* } } */
+
+struct AAAA
+{
+
+} aaaa;
+
+
+void named (int, struct AAAA);
+void unnamed (int, ...);
+
+void foo ()
+{
+ name (0, aaaa);
+ unnamed (0, aaaa);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_2.c
new file mode 100644
index 0000000..8d34f27
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_2.c
@@ -0,0 +1,13 @@
+/* Test AAPCS layout
+
+ Larger than machine-supported vector size. The behaviour is unspecified by
+ the AAPCS64 document; the implementation opts for pass by reference. */
+
+/* { dg-do compile { target aarch64*-*-* } } */
+
+typedef char A __attribute__ ((vector_size (64)));
+
+void
+foo (A a)
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_3.c
new file mode 100644
index 0000000..fb6816f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_3.c
@@ -0,0 +1,16 @@
+/* Test AAPCS layout
+
+/* { dg-do compile { target aarch64*-*-* } } */
+
+#define vector __attribute__((vector_size(16)))
+
+void
+foo(int a, ...);
+
+int
+main(void)
+{
+ foo (1, (vector unsigned int){10,11,12,13},
+ 2, (vector unsigned int){20,21,22,23});
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_4.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_4.c
new file mode 100644
index 0000000..44af079
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_4.c
@@ -0,0 +1,9 @@
+/* Test AAPCS layout
+
+/* { dg-do compile { target aarch64*-*-* } } */
+
+__complex__ long int
+ctest_long_int(__complex__ long int x)
+{
+ return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_5.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_5.c
new file mode 100644
index 0000000..da24ba8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_5.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target aarch64*-*-* } } */
+
+struct S
+{
+ union
+ {
+ long double b;
+ } a;
+};
+
+struct S s;
+
+extern struct S a[5];
+extern struct S check (struct S, struct S *, struct S);
+extern void checkx (struct S);
+
+void test (void)
+{
+ checkx (check (s, &a[1], a[2]));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/macro-def.h b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/macro-def.h
new file mode 100644
index 0000000..72a4706
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/macro-def.h
@@ -0,0 +1,286 @@
+/* This header file defines a set of macros to be used in the construction
+ of parameter passing and/or va_arg code gen tests during the
+ pre-processing stage. It is included inside abitest.h.
+
+ The following macros are defined here:
+
+ LAST_ARG
+ ARG
+ DOTS
+ ANON
+ LAST_ANON
+ PTR
+ PTR_ANON
+ LAST_ANONPTR
+
+ These macros are given different definitions depending on which one of
+ the following macros is defined.
+
+ AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS
+ AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST
+ AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST
+ AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST
+ AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT
+ AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS
+ AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST
+
+ Do not define more than one of the above macros. */
+
+
+/* AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS
+ Define macros to check the incoming arguments. */
+
+#ifdef AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#undef PTR
+#undef PTR_ANON
+#undef LAST_ANONPTR
+#undef ANON_PROMOTED
+
+/* Generate memcmp to check if the incoming args have the expected values. */
+#define LAST_ARG_NONFLAT(type, val, offset, layout, ...) \
+{ \
+ type __x = val; \
+ DUMP_ARG(type,val); \
+ if (validate_memory (&__x, stack + offset, sizeof (type), layout) != 0) \
+ abort(); \
+}
+#define LAST_ARG(type,val,offset,...) LAST_ARG_NONFLAT (type, val, offset, \
+ flat,__VA_ARGS__)
+#define ARG_NONFLAT(type,val,offset,layout,...) LAST_ARG_NONFLAT (type, val, \
+ offset, \
+ layout, \
+ __VA_ARGS__)
+#define ARG(type,val,offset,...) LAST_ARG_NONFLAT(type, val, offset, \
+ flat, __VA_ARGS__)
+#define ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define LAST_ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...) \
+ ANON(type_promoted, val_promoted, offset, __VA_ARGS__)
+/* Composite larger than 16 bytes is replaced by a pointer to a copy prepared
+ by the caller, so here we extrat the pointer, deref it and compare the
+ content with that of the original one. */
+#define PTR(type, val, offset, ...) { \
+ type * ptr; \
+ DUMP_ARG(type,val); \
+ ptr = *(type **)(stack + offset); \
+ if (memcmp (ptr, &val, sizeof (type)) != 0) abort (); \
+}
+#define PTR_ANON(type, val, offset, ...) PTR(type, val, offset, __VA_ARGS__)
+#define LAST_ANONPTR(type, val, offset, ...) PTR(type, val, offset, __VA_ARGS__)
+#define DOTS
+
+#endif /* AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS */
+
+
+/* AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST
+ Define macros to generate parameter type list. */
+
+#ifdef AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#undef PTR
+#undef PTR_ANON
+#undef LAST_ANONPTR
+
+/* Generate parameter type list (without identifiers). */
+#define LAST_ARG(type,val,offset) type
+#define LAST_ARG_NONFLAT(type, val, offset, layout) type
+#define ARG(type,val,offset) LAST_ARG(type, val, offset),
+#define ARG_NONFLAT(type, val, offset, layout) LAST_ARG (type, val, offset),
+#define DOTS ...
+#define ANON(type,val, offset)
+#define LAST_ANON(type,val, offset)
+#define PTR(type, val, offset) LAST_ARG(type, val, offset),
+#define PTR_ANON(type, val, offset)
+#define LAST_ANONPTR(type, val, offset)
+
+#endif /* AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST */
+
+
+/* AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST
+ Define macros to generate argument list. */
+
+#ifdef AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#undef PTR
+#undef PTR_ANON
+#undef LAST_ANONPTR
+#undef ANON_PROMOTED
+
+/* Generate the argument list; use VAL as the argument name. */
+#define LAST_ARG(type,val,offset,...) val
+#define LAST_ARG_NONFLAT(type,val,offset,layout,...) val
+#define ARG(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define ARG_NONFLAT(type, val, offset, layout,...) LAST_ARG (type, val, \
+ offset, \
+ __VA_ARGS__),
+#define DOTS
+#define LAST_ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define PTR(type, val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define PTR_ANON(type, val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define LAST_ANONPTR(type, val, offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...) \
+ LAST_ARG(type, val, offset, __VA_ARGS__),
+
+#endif /* AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST */
+
+
+/* AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST
+ Define variadic macros to generate parameter type list. */
+
+#ifdef AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#undef PTR
+#undef PTR_ANON
+#undef LAST_ANONPTR
+#undef ANON_PROMOTED
+
+/* Generate parameter type list (without identifiers). */
+#define LAST_ARG(type,val,offset,...) type
+#define LAST_ARG_NONFLAT(type, val, offset, layout, ...) type
+#define ARG(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define ARG_NONFLAT(type, val, offset, layout, ...) LAST_ARG (type, val, \
+ offset, \
+ __VA_ARGS__),
+#define DOTS
+#define ANON(type,val, offset,...) ARG(type,val,offset, __VA_ARGS__)
+#define LAST_ANON(type,val, offset,...) LAST_ARG(type,val, offset, __VA_ARGS__)
+#define PTR(type, val, offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define PTR_ANON(type, val, offset,...) PTR(type, val, offset, __VA_ARGS__)
+#define LAST_ANONPTR(type, val, offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...) \
+ LAST_ARG(type_promoted, val_promoted, offset, __VA_ARGS__),
+
+#endif /* AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST */
+
+
+/* AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT
+ Define variadic macros to generate parameter type list with
+ identifiers. */
+
+#ifdef AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#undef PTR
+#undef PTR_ANON
+#undef LAST_ANONPTR
+#undef ANON_PROMOTED
+
+/* Generate parameter type list (with identifiers).
+ The identifiers are named with prefix _f and suffix of the value of
+ __VA_ARGS__. */
+#define LAST_ARG(type,val,offset,...) type _f##__VA_ARGS__
+#define LAST_ARG_NONFLAT(type, val, offset, layout, ...) type _f##__VA_ARGS__
+#define ARG(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define ARG_NONFLAT(type, val, offset, layout, ...) LAST_ARG (type, val, \
+ offset, \
+ __VA_ARGS__),
+#define DOTS ...
+#define ANON(type,val, offset,...)
+#define LAST_ANON(type,val, offset,...)
+#define PTR(type, val, offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define PTR_ANON(type, val, offset,...)
+#define LAST_ANONPTR(type, val, offset,...)
+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...)
+
+#endif /* AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT */
+
+
+/* AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS
+ Define variadic macros to generate assignment from the function
+ incoming arguments to local variables. */
+
+#ifdef AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#undef PTR
+#undef PTR_ANON
+#undef LAST_ANONPTR
+#undef ANON_PROMOTED
+
+/* Generate assignment statements. For named args, direct assignment from
+ the formal parameter is generated; for unnamed args, va_arg is used.
+ The names of the local variables start with _x and end with the value of
+ __VA_ARGS__. */
+#define LAST_ARG(type,val,offset,...) type _x##__VA_ARGS__ = _f##__VA_ARGS__;
+#define LAST_ARG_NONFLAT(type, val, offset, layout, ...) \
+ type _x##__VA_ARGS__ = _f##__VA_ARGS__;
+#define ARG(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define ARG_NONFLAT(type,val,offset,layout,...) \
+ LAST_ARG (type, val, offset, __VA_ARGS__)
+#define ANON(type,val,offset,...) type _x##__VA_ARGS__ = va_arg (ap, type);
+#define LAST_ANON(type,val,offset,...) ANON(type, val, offset, __VA_ARGS__)
+#define PTR(type, val,offset,...) ARG(type, val, offset, __VA_ARGS__)
+#define PTR_ANON(type, val, offset,...) ANON(type, val,offset, __VA_ARGS__)
+#define LAST_ANONPTR(type, val, offset,...) ANON(type, val, offset, __VA_ARGS__)
+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...) \
+ ANON(type_promoted, val_promoted, offset, __VA_ARGS__)
+
+#define DOTS
+
+#endif /* AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS */
+
+
+/* AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST
+ Define variadic macros to generate argument list using the variables
+ generated during AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS. */
+
+#ifdef AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#undef PTR
+#undef PTR_ANON
+#undef LAST_ANONPTR
+#undef ANON_PROMOTED
+
+/* Generate the argument list; the names start with _x and end with the value of
+ __VA_ARGS__. All arguments (named or unnamed) in stdarg_func are passed to
+ myfunc as named arguments. */
+#define LAST_ARG(type,val,offset,...) _x##__VA_ARGS__
+#define LAST_ARG_NONFLAT(type, val, offset, layout, ...) _x##__VA_ARGS__
+#define ARG(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define ARG_NONFLAT(type, val, offset, layout, ...) \
+ LAST_ARG_NONFLAT (type, val, offset, layout, __VA_ARGS__),
+#define DOTS
+#define LAST_ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define PTR(type, val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define PTR_ANON(type, val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define LAST_ANONPTR(type, val, offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...) \
+ ANON(type_promoted, val_promoted, offset, __VA_ARGS__)
+
+#endif /* AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_1.c
new file mode 100644
index 0000000..545b056
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_1.c
@@ -0,0 +1,31 @@
+/* Test AAPCS64 layout */
+
+/* C.7 If the argument is an Integral Type, the size of the argument is
+ less than or equal to 8 bytes and the NGRN is less than 8, the
+ argument is copied to the least significant bits in x[NGRN]. The
+ NGRN is incremented by one. The argument has now been allocated. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_1.c"
+/* TODO: review if we need this */
+#define RUNTIME_ENDIANNESS_CHECK
+#include "abitest.h"
+#else
+ ARG(int, 4, W0)
+ ARG(double, 4.0, D0)
+ ARG(int, 3, W1)
+ /* TODO: review the way of memcpy char, short, etc. */
+#ifndef __AAPCS64_BIG_ENDIAN__
+ ARG(char, 0xEF, X2)
+ ARG(short, 0xBEEF, X3)
+ ARG(int, 0xDEADBEEF, X4)
+#else
+ /* TODO: need the model/qemu to be big-endian as well */
+ ARG(char, 0xEF, X2+7)
+ ARG(short, 0xBEEF, X3+6)
+ ARG(int, 0xDEADBEEF, X4+4)
+#endif
+ LAST_ARG(long long, 0xDEADBEEFCAFEBABELL, X5)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_10.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_10.c
new file mode 100644
index 0000000..c2f4815
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_10.c
@@ -0,0 +1,26 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_10.c"
+
+struct z
+{
+ double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+
+ ARG(int, 7, W0)
+ DOTS
+ ANON(struct z, a, D0)
+ ANON(struct z, b, D4)
+ ANON(double, 0.5, STACK)
+ LAST_ANON(double, 1.5, STACK+8)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_11.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_11.c
new file mode 100644
index 0000000..34cbe03
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_11.c
@@ -0,0 +1,34 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_11.c"
+
+__complex__ x = 1.0+2.0i;
+
+struct y
+{
+ int p;
+ int q;
+ int r;
+ int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+ double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+ ARG(double, 11.0, D0)
+ DOTS
+ ANON(struct z, a, D1)
+ ANON(struct z, b, STACK)
+ LAST_ANON(double, 0.5, STACK+32)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_12.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_12.c
new file mode 100644
index 0000000..d07bef8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_12.c
@@ -0,0 +1,44 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_12.c"
+
+
+struct y
+{
+ long p;
+ long q;
+ long r;
+ long s;
+} v = { 1, 2, 3, 4 };
+
+struct y1
+{
+ int p;
+ int q;
+ int r;
+ int s;
+} v1 = { 1, 2, 3, 4 };
+
+
+struct z
+{
+ double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#define MYFUNCTYPE struct y
+
+#include "abitest.h"
+#else
+ ARG(int, 7, W0)
+ ARG(struct y1, v1, X1)
+ ARG(struct z, a, D0)
+ ARG(struct z, b, D4)
+ LAST_ARG(double, 0.5, STACK)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_13.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_13.c
new file mode 100644
index 0000000..c73e6f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_13.c
@@ -0,0 +1,34 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+
+#define TESTFILE "test_13.c"
+
+
+struct y
+{
+ int p;
+ int q;
+ int r;
+ int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+ double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+ ARG(int, 7, W0)
+ ARG(struct y, v, X1)
+ ARG(struct z, a, D0)
+ ARG(double, 1.0, D4)
+ ARG(struct z, b, STACK)
+ LAST_ARG(double, 0.5, STACK+32)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_14.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_14.c
new file mode 100644
index 0000000..3c22b8a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_14.c
@@ -0,0 +1,35 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_14.c"
+
+
+struct y
+{
+ int p;
+ int q;
+ int r;
+ int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+ double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+ ARG(int, 7, W0)
+ ARG(int, 9, W1)
+ ARG(struct z, a, D0)
+ ARG(double, 1.0, D4)
+ ARG(struct z, b, STACK)
+ ARG(int, 4, W2)
+ LAST_ARG(double, 0.5, STACK+32)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_15.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_15.c
new file mode 100644
index 0000000..1a869ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_15.c
@@ -0,0 +1,21 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_15.c"
+
+#include "abitest.h"
+#else
+ ARG(double, 1.0, D0)
+ ARG(double, 2.0, D1)
+ ARG(double, 3.0, D2)
+ ARG(double, 4.0, D3)
+ ARG(double, 5.0, D4)
+ ARG(double, 6.0, D5)
+ ARG(double, 7.0, D6)
+ ARG(double, 8.0, D7)
+ ARG(double, 9.0, STACK)
+ LAST_ARG(double, 10.0, STACK+8)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_16.c
new file mode 100644
index 0000000..1aa9725
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_16.c
@@ -0,0 +1,32 @@
+/* Test AAPCS layout */
+/* C.5 If the argument is a Half- or Single- precision Floating-point type,
+ then the size of the argument is set to 8 bytes. The effect is as if
+ the argument had been copied to the least significant bits of a 64-bit
+ register and the remaining bits filled with unspecified values. */
+/* TODO: add the check of half-precision floating-point when it is supported
+ by the A64 GCC. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_16.c"
+
+#include "abitest.h"
+#else
+ ARG(float, 1.0, S0)
+ ARG(float, 2.0, S1)
+ ARG(float, 3.0, S2)
+ ARG(float, 4.0, S3)
+ ARG(float, 5.0, S4)
+ ARG(float, 6.0, S5)
+ ARG(float, 7.0, S6)
+ ARG(float, 8.0, S7)
+#ifndef __AAPCS64_BIG_ENDIAN__
+ ARG(float, 9.0, STACK)
+ LAST_ARG(float, 10.0, STACK+8)
+#else
+ ARG(float, 9.0, STACK+4)
+ LAST_ARG(float, 10.0, STACK+12)
+#endif
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_17.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_17.c
new file mode 100644
index 0000000..348ea28
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_17.c
@@ -0,0 +1,37 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_17.c"
+
+__complex__ x = 1.0+2.0i;
+
+struct y
+{
+ int p;
+ int q;
+ int r;
+ int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+ double x[4];
+};
+
+float f1 = 25.0;
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+ ARG(double, 11.0, D0)
+ DOTS
+ ANON(struct z, a, D1)
+ ANON(struct z, b, STACK)
+ ANON(int , 5, W0)
+ ANON(double, f1, STACK+32)
+ LAST_ANON(double, 0.5, STACK+40)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c
new file mode 100644
index 0000000..2ebecee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c
@@ -0,0 +1,34 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+
+#define TESTFILE "test_18.c"
+
+
+struct y
+{
+ long long p;
+ long long q;
+ long long r;
+ long long s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+ double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+ ARG(int, 7, W0)
+ PTR(struct y, v, X1)
+ ARG(struct z, a, D0)
+ ARG(double, 1.0, D4)
+ ARG(struct z, b, STACK)
+ LAST_ARG(double, 0.5, STACK+32)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_19.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_19.c
new file mode 100644
index 0000000..1a3f873
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_19.c
@@ -0,0 +1,35 @@
+/* Test AAPCS64 layout. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_19.c"
+
+struct y
+{
+ int p1;
+ int p2;
+ float q;
+ int r1;
+ int r2;
+ char x;
+} v = { -1, 1, 2.0f, 3, 18, 19, 20};
+
+struct z
+{
+ double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+ ARG(int, 7, W0)
+ DOTS
+ ANON(double, 4.0, D0)
+ ANON(struct z, a, D1)
+ ANON(struct z, b, STACK)
+ PTR_ANON(struct y, v, X1)
+ LAST_ANON(int, 10, W2)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_2.c
new file mode 100644
index 0000000..94817ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_2.c
@@ -0,0 +1,16 @@
+/* Test AAPCS64 layout */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_2.c"
+#include "abitest.h"
+
+#else
+ ARG(float, 1.0f, S0)
+ ARG(double, 4.0, D1)
+ ARG(float, 2.0f, S2)
+ ARG(double, 5.0, D3)
+ LAST_ARG(int, 3, W0)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_20.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_20.c
new file mode 100644
index 0000000..e4cc1a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_20.c
@@ -0,0 +1,22 @@
+/* Test AAPCS64 layout */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_20.c"
+
+#include "abitest.h"
+
+#else
+ ARG(int, 8, W0)
+ ARG(double, 1.0, D0)
+ ARG(double, 2.0, D1)
+ ARG(double, 3.0, D2)
+ ARG(double, 4.0, D3)
+ ARG(double, 5.0, D4)
+ ARG(double, 6.0, D5)
+ ARG(double, 7.0, D6)
+ DOTS
+ ANON(_Complex double, 1234.0 + 567.0i, STACK)
+ LAST_ANON(double, -987.0, STACK+16)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_21.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_21.c
new file mode 100644
index 0000000..b3a75e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_21.c
@@ -0,0 +1,21 @@
+/* Test AAPCS64 layout */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_21.c"
+
+#include "abitest.h"
+
+#else
+ ARG(int, 8, W0)
+ ARG(double, 1.0, D0)
+ ARG(double, 2.0, D1)
+ ARG(double, 3.0, D2)
+ ARG(double, 4.0, D3)
+ ARG(double, 5.0, D4)
+ ARG(double, 6.0, D5)
+ ARG(double, 7.0, D6)
+ ARG(_Complex double, 1234.0 + 567.0i, STACK)
+ LAST_ARG(double, -987.0, STACK+16)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_22.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_22.c
new file mode 100644
index 0000000..cb8a8ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_22.c
@@ -0,0 +1,19 @@
+/* Test AAPCS64 layout */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_22.c"
+
+struct y
+{
+ float p;
+ float q;
+} v = { 345.0f, 678.0f };
+
+#include "abitest.h"
+#else
+ ARG(float, 123.0f, S0)
+ ARG(struct y, v, S1)
+ LAST_ARG(float, 901.0f, S3)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_23.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_23.c
new file mode 100644
index 0000000..6993884
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_23.c
@@ -0,0 +1,42 @@
+/* Test AAPCS64 layout.
+
+ Larger than machine-supported vector size. The behaviour is unspecified by
+ the AAPCS64 document; the implementation opts for pass by reference. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_23.c"
+
+typedef char A __attribute__ ((vector_size (64)));
+
+struct y
+{
+ double df[8];
+};
+
+union u
+{
+ struct y x;
+ A a;
+} u;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ u.x.df[0] = 1.0;
+ u.x.df[1] = 2.0;
+ u.x.df[2] = 3.0;
+ u.x.df[3] = 4.0;
+ u.x.df[4] = 5.0;
+ u.x.df[5] = 6.0;
+ u.x.df[6] = 7.0;
+ u.x.df[7] = 8.0;
+}
+
+#include "abitest.h"
+#else
+ARG (float, 123.0f, S0)
+PTR (A, u.a, X0)
+LAST_ARG_NONFLAT (int, 0xdeadbeef, X1, i32in64)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_24.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_24.c
new file mode 100644
index 0000000..8655f6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_24.c
@@ -0,0 +1,22 @@
+/* Test AAPCS64 layout. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_24.c"
+
+typedef long double TFtype;
+
+#include "abitest.h"
+#else
+ ARG(TFtype, 1.0, Q0)
+ ARG(TFtype, 2.0, Q1)
+ ARG(TFtype, 3.0, Q2)
+ ARG(TFtype, 4.0, Q3)
+ ARG(TFtype, 5.0, Q4)
+ ARG(TFtype, 6.0, Q5)
+ ARG(TFtype, 7.0, Q6)
+ ARG(TFtype, 8.0, Q7)
+ ARG(double, 9.0, STACK)
+ LAST_ARG(TFtype, 10.0, STACK+16)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_25.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_25.c
new file mode 100644
index 0000000..2f942ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_25.c
@@ -0,0 +1,61 @@
+/* Test AAPCS64 layout
+
+ Test homogeneous floating-point aggregates and homogeneous short-vector
+ aggregates, which should be passed in SIMD/FP registers or via the
+ stack. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_25.c"
+
+typedef float vf2_t __attribute__((vector_size (8)));
+struct x0
+{
+ vf2_t v;
+} s0;
+struct x3
+{
+ vf2_t v[2];
+} s3;
+struct x4
+{
+ vf2_t v[3];
+} s4;
+
+typedef float vf4_t __attribute__((vector_size(16)));
+struct x1
+{
+ vf4_t v;
+} s1;
+
+struct x2
+{
+ double df[3];
+} s2;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ s0.v = (vf2_t){ 17.f, 18.f };
+ s1.v = (vf4_t){ 567.890f, 678.901f, 789.012f, 890.123f };
+ s2.df[0] = 123.456;
+ s2.df[1] = 234.567;
+ s2.df[2] = 345.678;
+ s3.v[0] = (vf2_t){ 19.f, 20.f, 21.f, 22.f };
+ s3.v[1] = (vf2_t){ 23.f, 24.f, 25.f, 26.f };
+ s4.v[0] = (vf2_t){ 27.f, 28.f, 29.f, 30.f };
+ s4.v[1] = (vf2_t){ 31.f, 32.f, 33.f, 34.f };
+ s4.v[2] = (vf2_t){ 35.f, 36.f, 37.f, 38.f };
+}
+
+#include "abitest.h"
+#else
+ARG_NONFLAT (struct x0, s0, Q0, f32in64)
+ARG (struct x2, s2, D1)
+ARG (struct x1, s1, Q4)
+ARG (struct x3, s3, D5)
+ARG (struct x4, s4, STACK)
+ARG_NONFLAT (int, 0xdeadbeef, X0, i32in64)
+LAST_ARG (double, 456.789, STACK+24)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_26.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_26.c
new file mode 100644
index 0000000..9b9a3a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_26.c
@@ -0,0 +1,54 @@
+/* Test AAPCS64 layout.
+
+ Test some small structures that should be passed in GPRs. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_26.c"
+
+struct y0
+{
+ char ch;
+} c0 = { 'A' };
+
+struct y2
+{
+ long long ll[2];
+} c2 = { 0xDEADBEEF, 0xCAFEBABE };
+
+struct y3
+{
+ int i[3];
+} c3 = { 56789, 67890, 78901 };
+
+typedef float vf2_t __attribute__((vector_size (8)));
+struct x0
+{
+ vf2_t v;
+} s0;
+
+typedef short vh4_t __attribute__((vector_size (8)));
+
+struct x1
+{
+ vh4_t v[2];
+} s1;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ s0.v = (vf2_t){ 17.f, 18.f };
+ s1.v[0] = (vh4_t){ 345, 456, 567, 678 };
+ s1.v[1] = (vh4_t){ 789, 890, 901, 123 };
+}
+
+#include "abitest.h"
+#else
+ARG (struct y0, c0, X0)
+ARG (struct y2, c2, X1)
+ARG (struct y3, c3, X3)
+ARG_NONFLAT (struct x0, s0, D0, f32in64)
+ARG (struct x1, s1, D1)
+LAST_ARG_NONFLAT (int, 89012, X5, i32in64)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_3.c
new file mode 100644
index 0000000..f05b8e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_3.c
@@ -0,0 +1,18 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_3.c"
+
+__complex__ x = 1.0+2.0i;
+
+#include "abitest.h"
+#else
+ARG (float, 1.0f, S0)
+ARG (__complex__ double, x, D1)
+ARG (float, 2.0f, S3)
+ARG (double, 5.0, D4)
+LAST_ARG_NONFLAT (int, 3, X0, i32in64)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_4.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_4.c
new file mode 100644
index 0000000..a37db56
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_4.c
@@ -0,0 +1,20 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_4.c"
+
+__complex__ float x = 1.0f + 2.0fi;
+#include "abitest.h"
+#else
+ARG (float, 1.0f, S0)
+ARG (__complex__ float, x, S1)
+ARG (float, 2.0f, S3)
+ARG (double, 5.0, D4)
+LAST_ARG_NONFLAT (int, 3, X0, i32in64)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_5.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_5.c
new file mode 100644
index 0000000..674efd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_5.c
@@ -0,0 +1,24 @@
+/* Test AAPCS64 layout */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_5.c"
+
+__complex__ float x = 1.0+2.0i;
+
+struct y
+{
+ long p;
+ long q;
+} v = { 1, 2};
+
+#include "abitest.h"
+#else
+ ARG(float, 1.0f, S0)
+ ARG(__complex__ float, x, S1)
+ ARG(float, 2.0f, S3)
+ ARG(double, 5.0, D4)
+ LAST_ARG(struct y, v, X0)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_6.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_6.c
new file mode 100644
index 0000000..95d44e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_6.c
@@ -0,0 +1,26 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_6.c"
+
+__complex__ double x = 1.0+2.0i;
+
+struct y
+{
+ int p;
+ int q;
+ int r;
+ int s;
+} v = { 1, 2, 3, 4 };
+
+#include "abitest.h"
+#else
+ ARG(struct y, v, X0)
+ ARG(float, 1.0f, S0)
+ ARG(__complex__ double, x, D1)
+ ARG(float, 2.0f, S3)
+ ARG(double, 5.0, D4)
+ LAST_ARG(int, 3, W2)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_7.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_7.c
new file mode 100644
index 0000000..4fb1fee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_7.c
@@ -0,0 +1,30 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_7.c"
+
+__complex__ float x = 1.0f + 2.0i;
+
+struct y
+{
+ int p;
+ int q;
+ int r;
+ int s;
+} v = { 1, 2, 3, 4 }, v1 = {5, 6, 7, 8}, v2 = {9, 10, 11, 12};
+
+#include "abitest.h"
+#else
+ARG (struct y, v, X0)
+ARG (struct y, v1, X2)
+ARG (struct y, v2, X4)
+ARG (int, 4, W6)
+ARG (float, 1.0f, S0)
+ARG (__complex__ float, x, S1)
+ARG (float, 2.0f, S3)
+ARG (double, 5.0, D4)
+ARG (int, 3, W7)
+LAST_ARG_NONFLAT (int, 5, STACK, i32in64)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_8.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_8.c
new file mode 100644
index 0000000..3d67ff5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_8.c
@@ -0,0 +1,24 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_8.c"
+
+struct z
+{
+ double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+ ARG(struct z, a, D0)
+ ARG(struct z, b, D4)
+ ARG(double, 0.5, STACK)
+ ARG(int, 7, W0)
+ LAST_ARG(int, 8, W1)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_9.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_9.c
new file mode 100644
index 0000000..fbe4245
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_9.c
@@ -0,0 +1,32 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_9.c"
+
+struct y
+{
+ int p;
+ int q;
+ int r;
+ int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+ double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+ ARG(int, 7, W0)
+ ARG(struct y, v, X1)
+ ARG(struct z, a, D0)
+ ARG(struct z, b, D4)
+ LAST_ARG(double, 0.5, STACK)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-1.c
new file mode 100644
index 0000000..f22fca6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-1.c
@@ -0,0 +1,126 @@
+/* Test AAPCS64 layout.
+
+ Test the comformance to the alignment and padding requirements.
+
+ B.4 If the argument type is a Composite Type then the size of the
+ argument is rounded up to the nearest multiple of 8 bytes.
+ C.4 If the argument is an HFA, a Quad-precision Floating-point or Short
+ Vector Type then the NSAA is rounded up to the larger of 8 or the
+ Natural Alignment of the argument's type.
+ C.12 The NSAA is rounded up to the larger of 8 or the Natural Alignment
+ of the argument's type.
+ C.14 If the size of the argument is less than 8 bytes then the size of
+ the argument is set ot 8 bytes. The effect is as if the argument
+ was copied to the least significant bits of a 64-bit register and
+ the remaining bits filled with unspecified values. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_align-1.c"
+#include "type-def.h"
+
+struct y
+{
+ int p;
+ int q;
+ int r;
+ int s;
+};
+
+struct y v1 = { 1, 2, 3, 4 };
+struct y v2 = { 5, 6, 7, 8 };
+struct y v3 = { 9, 10, 11, 12 };
+struct y v4 = { 13, 14, 15, 16 };
+
+struct z
+{
+ double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+vf4_t c = { 13.f, 14.f, 15.f, 16.f };
+
+struct x
+{
+ vf4_t v;
+} w;
+
+char ch='a';
+short sh=13;
+int i=14;
+long long ll=15;
+
+struct s1
+{
+ short sh[3];
+} s1;
+
+struct s2
+{
+ int i[2];
+ char c;
+} s2;
+
+struct ldx2_t
+{
+ long double ld[2];
+} ldx2 = { 12345.67890L, 23456.78901L };
+
+union u_t
+{
+ long double ld;
+ double d[2];
+} u;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ w.v = (vf4_t){ 17.f, 18.f, 19.f, 20.f };
+ s1.sh[0] = 16;
+ s1.sh[1] = 17;
+ s1.sh[2] = 18;
+ s2.i[0] = 19;
+ s2.i[1] = 20;
+ s2.c = 21;
+ u.ld = 34567.89012L;
+}
+
+#include "abitest.h"
+#else
+
+ ARG(struct y, v1, X0)
+ ARG(struct y, v2, X2)
+ ARG(struct y, v3, X4)
+ ARG(struct y, v4, X6)
+ ARG(struct z, a, D0)
+ ARG(struct z, b, D4)
+ ARG(double, 12.5, STACK)
+ ARG(vf4_t, c, STACK+16) /* [C.4] 16-byte aligned short vector */
+ ARG(double, 17.0, STACK+32)
+ ARG(struct x, w, STACK+48) /* [C.12] 16-byte aligned small struct */
+#ifndef __AAPCS64_BIG_ENDIAN__
+ ARG(char, ch, STACK+64) /* [C.14] char padded to the size of 8 bytes */
+ ARG(short, sh, STACK+72) /* [C.14] short padded to the size of 8 bytes */
+ ARG(int, i, STACK+80) /* [C.14] int padded to the size of 8 bytes */
+#else
+ ARG(char, ch, STACK+71)
+ ARG(short, sh, STACK+78)
+ ARG(int, i, STACK+84)
+#endif
+ ARG(long long, ll, STACK+88)
+ ARG(struct s1, s1, STACK+96) /* [B.4] small struct padded to the size of 8 bytes */
+ ARG(double, 18.0, STACK+104)
+ ARG(struct s2, s2, STACK+112) /* [B.4] small struct padded to the size of 16 bytes */
+ ARG(double, 19.0, STACK+128)
+ ARG(long double, 30.0L, STACK+144) /* [C.4] 16-byte aligned quad-precision */
+ ARG(double, 31.0, STACK+160)
+ ARG(struct ldx2_t, ldx2, STACK+176) /* [C.4] 16-byte aligned HFA */
+ ARG(double, 32.0, STACK+208)
+ ARG(__int128, 33, STACK+224) /* [C.12] 16-byte aligned 128-bit integer */
+ ARG(double, 34.0, STACK+240)
+ ARG(union u_t, u, STACK+256) /* [C.12] 16-byte aligned small composite (union in this case) */
+ LAST_ARG_NONFLAT (int, 35.0, STACK+272, i32in64)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-2.c
new file mode 100644
index 0000000..6c61948
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-2.c
@@ -0,0 +1,42 @@
+/* Test AAPCS64 layout.
+
+ C.8 If the argument has an alignment of 16 then the NGRN is rounded up
+ the next even number.
+
+ The case of a small struture containing only one 16-byte aligned
+ quad-word integer is covered in this test. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_align-2.c"
+#include "type-def.h"
+
+struct y
+{
+ union int128_t v;
+} w;
+
+struct x
+{
+ long long p;
+ int q;
+} s = {0xDEADBEEFCAFEBABELL, 0xFEEBDAED};
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ /* Init signed quad-word integer. */
+ w.v.l64 = 0xfdb9753102468aceLL;
+ w.v.h64 = 0xeca8642013579bdfLL;
+}
+
+#include "abitest.h"
+#else
+ ARG(int, 0xAB, W0)
+ ARG(struct y, w, X2)
+ ARG(int, 0xCD, W4)
+ ARG(struct x, s, X5)
+ LAST_ARG(int, 0xFF00FF00, W7)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-3.c
new file mode 100644
index 0000000..bf8bc74
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-3.c
@@ -0,0 +1,46 @@
+/* Test AAPCS64 layout.
+
+ C.8 If the argument has an alignment of 16 then the NGRN is rounded up
+ the next even number.
+ C.9 If the argument is an Integral Type, the size of the argument is
+ equal to 16 and the NGRN is less than 7, the argument is copied
+ to x[NGRN] and x[NGRN+1]. x[NGRN] shall contain the lower addressed
+ double-word of the memory representation of the argument. The
+ NGRN is incremented by two. The argument has now been allocated.
+
+ The case of passing a 128-bit integer in two general registers is covered
+ in this test. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_align-3.c"
+#include "type-def.h"
+
+union int128_t qword;
+
+int gInt[4];
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ /* Initialize the quadword integer via the union. */
+ qword.l64 = 0xDEADBEEFCAFEBABELL;
+ qword.h64 = 0x123456789ABCDEF0LL;
+
+ gInt[0] = 12345;
+ gInt[1] = 23456;
+ gInt[2] = 34567;
+ gInt[3] = 45678;
+}
+
+
+#include "abitest.h"
+#else
+ ARG(int, gInt[0], W0)
+ ARG(int, gInt[1], W1)
+ ARG(int, gInt[2], W2)
+ ARG(__int128, qword.i, X4)
+ LAST_ARG(int, gInt[3], W6)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-4.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-4.c
new file mode 100644
index 0000000..7834ed8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-4.c
@@ -0,0 +1,42 @@
+/* Test AAPCS64 layout.
+
+ C.3 If the argument is an HFA then the NSRN is set to 8 and the size
+ of the argument is rounded up to the nearest multiple of 8 bytes.
+
+ TODO: add the check of an HFA containing half-precision floating-point
+ when __f16 is supported in A64 GCC. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_align-4.c"
+
+struct z1
+{
+ double x[4];
+};
+
+struct z1 a = { 5.0, 6.0, 7.0, 8.0 };
+
+struct z2
+{
+ float x[3];
+};
+
+struct z2 b = { 13.f, 14.f, 15.f };
+struct z2 c = { 16.f, 17.f, 18.f };
+
+#include "abitest.h"
+#else
+
+ ARG(struct z1, a, D0)
+ ARG(double, 9.0, D4)
+ ARG(double, 10.0, D5)
+ ARG(struct z2, b, STACK) /* [C.3] on stack and size padded to 16 bytes */
+#ifndef __AAPCS64_BIG_ENDIAN__
+ ARG(float, 15.5f, STACK+16) /* [C.3] NSRN has been set to 8 */
+#else
+ ARG(float, 15.5f, STACK+20)
+#endif
+ LAST_ARG(struct z2, c, STACK+24)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_complex.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_complex.c
new file mode 100644
index 0000000..6bf9721
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_complex.c
@@ -0,0 +1,18 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_complex.c"
+
+__complex__ float x = 1.0+2.0i;
+__complex__ int y = 5 + 6i;
+__complex__ double z = 2.0 + 3.0i;
+
+#include "abitest.h"
+#else
+ ARG(__complex__ float, x, S0)
+ ARG(__complex__ int, y, X0)
+ ARG(__complex__ double, z, D2)
+ LAST_ARG (int, 5, W1)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_int128.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_int128.c
new file mode 100644
index 0000000..9df344f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_int128.c
@@ -0,0 +1,17 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_int128.c"
+
+typedef int TItype __attribute__ ((mode (TI)));
+
+TItype x = 0xcafecafecafecfeacfeacfea;
+TItype y = 0xcfeacfeacfeacafecafecafe;
+
+#include "abitest.h"
+#else
+ ARG (TItype, x, X0)
+ LAST_ARG (TItype, y, X2)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_quad_double.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_quad_double.c
new file mode 100644
index 0000000..109cea0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_quad_double.c
@@ -0,0 +1,26 @@
+/* Test AAPCS64 layout.
+
+ Test parameter passing of floating-point quad precision types. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_quad_double.c"
+
+typedef long double TFtype;
+typedef _Complex long double CTFtype;
+
+TFtype x = 1.0;
+TFtype y = 2.0;
+
+CTFtype cx = 3.0 + 4.0i;
+CTFtype cy = 5.0 + 6.0i;
+
+#include "abitest.h"
+#else
+ ARG ( TFtype, x, Q0)
+ ARG (CTFtype, cx, Q1)
+ DOTS
+ ANON (CTFtype, cy, Q3)
+ LAST_ANON ( TFtype, y, Q5)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h
new file mode 100644
index 0000000..a95d06a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h
@@ -0,0 +1,157 @@
+/* This header file defines some types that are used in the AAPCS64 tests. */
+
+
+/* 64-bit vector of 2 floats. */
+typedef float vf2_t __attribute__((vector_size (8)));
+
+/* 128-bit vector of 4 floats. */
+typedef float vf4_t __attribute__((vector_size (16)));
+
+/* 128-bit vector of 4 ints. */
+typedef int vi4_t __attribute__((vector_size (16)));
+
+/* signed quad-word (in an union for the convenience of initialization). */
+union int128_t
+{
+ __int128 i;
+ struct
+ {
+ signed long long l64;
+ signed long long h64;
+ };
+};
+
+/* Homogeneous floating-point composite types. */
+
+struct hfa_fx1_t
+{
+ float a;
+};
+
+struct hfa_fx2_t
+{
+ float a;
+ float b;
+};
+
+struct hfa_dx2_t
+{
+ double a;
+ double b;
+};
+
+struct hfa_dx4_t
+{
+ double a;
+ double b;
+ double c;
+ double d;
+};
+
+struct hfa_ldx3_t
+{
+ long double a;
+ long double b;
+ long double c;
+};
+
+struct hfa_ffs_t
+{
+ float a;
+ float b;
+ struct hfa_fx2_t c;
+};
+
+union hfa_union_t
+{
+ struct
+ {
+ float a;
+ float b;
+ } s;
+ float c;
+};
+
+/* Non homogeneous floating-point-composite types. */
+
+struct non_hfa_fx5_t
+{
+ float a;
+ float b;
+ float c;
+ float d;
+ float e;
+};
+
+struct non_hfa_ffs_t
+{
+ float a;
+ float b;
+ struct hfa_dx2_t c;
+};
+
+struct non_hfa_ffs_2_t
+{
+ struct
+ {
+ int a;
+ int b;
+ } s;
+ float c;
+ float d;
+};
+
+struct hva_vf2x1_t
+{
+ vf2_t a;
+};
+
+struct hva_vf2x2_t
+{
+ vf2_t a;
+ vf2_t b;
+};
+
+struct hva_vi4x1_t
+{
+ vi4_t a;
+};
+
+struct non_hfa_ffd_t
+{
+ float a;
+ float b;
+ double c;
+};
+
+struct non_hfa_ii_t
+{
+ int a;
+ int b;
+};
+
+struct non_hfa_c_t
+{
+ char a;
+};
+
+struct non_hfa_ffvf2_t
+{
+ float a;
+ float b;
+ vf2_t c;
+};
+
+struct non_hfa_fffd_t
+{
+ float a;
+ float b;
+ float c;
+ double d;
+};
+
+union non_hfa_union_t
+{
+ double a;
+ float b;
+};
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-1.c
new file mode 100644
index 0000000..4eb569e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-1.c
@@ -0,0 +1,50 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+ This test covers fundamental data types as specified in AAPCS64 \S 4.1.
+ It is focus on unnamed parameter passed in registers. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-1.c"
+#include "type-def.h"
+
+vf2_t vf2 = (vf2_t){ 17.f, 18.f };
+vi4_t vi4 = (vi4_t){ 0xdeadbabe, 0xbabecafe, 0xcafebeef, 0xbeefdead };
+union int128_t qword;
+signed char sc = 0xed;
+signed int sc_promoted = 0xffffffed;
+signed short ss = 0xcba9;
+signed int ss_promoted = 0xffffcba9;
+float fp = 65432.12345f;
+double fp_promoted = (double)65432.12345f;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ /* Init signed quad-word integer. */
+ qword.l64 = 0xfdb9753102468aceLL;
+ qword.h64 = 0xeca8642013579bdfLL;
+}
+
+#include "abitest.h"
+#else
+ ARG ( int , 0xff , X0, LAST_NAMED_ARG_ID)
+ DOTS
+ ANON_PROMOTED(unsigned char , 0xfe , unsigned int, 0xfe , X1, 1)
+ ANON_PROMOTED( signed char , sc , signed int, sc_promoted, X2, 2)
+ ANON_PROMOTED(unsigned short , 0xdcba, unsigned int, 0xdcba , X3, 3)
+ ANON_PROMOTED( signed short , ss , signed int, ss_promoted, X4, 4)
+ ANON (unsigned int , 0xdeadbeef, X5, 5)
+ ANON ( signed int , 0xcafebabe, X6, 6)
+ ANON (unsigned long long, 0xba98765432101234ULL, X7, 7)
+ ANON ( signed long long, 0xa987654321012345LL , STACK, 8)
+ ANON ( __int128, qword.i , STACK+16, 9)
+ ANON_PROMOTED( float , fp , double, fp_promoted, D0, 10)
+ ANON ( double , 9876543.212345, D1, 11)
+ ANON ( long double , 98765432123456789.987654321L, Q2, 12)
+ ANON ( vf2_t, vf2 , D3, 13)
+ ANON ( vi4_t, vi4 , Q4, 14)
+ LAST_ANON ( int , 0xeeee, STACK+32,15)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-10.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-10.c
new file mode 100644
index 0000000..50b7700
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-10.c
@@ -0,0 +1,29 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+ Miscellaneous test: Anonymous arguments passed on the stack. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-10.c"
+
+struct z
+{
+ double x[4];
+};
+
+double d1 = 25.0;
+double d2 = 103.0;
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+ ARG(struct z, a, D0, 0)
+ ARG(struct z, b, D4, LAST_NAMED_ARG_ID)
+ DOTS
+ ANON(double, d1, STACK, 2)
+ LAST_ANON(double, d2, STACK+8, 3)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-11.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-11.c
new file mode 100644
index 0000000..c1f1f8f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-11.c
@@ -0,0 +1,32 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+ Miscellaneous test: Anonymous arguments passed on the stack. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-11.c"
+
+struct z
+{
+ double x[2];
+};
+
+double d1 = 25.0;
+struct z a = { 5.0, 6.0 };
+
+#include "abitest.h"
+#else
+ ARG(double, 1.0, D0, 0)
+ ARG(double, 2.0, D1, 1)
+ ARG(double, 3.0, D2, 2)
+ ARG(double, 4.0, D3, 3)
+ ARG(double, 5.0, D4, 4)
+ ARG(double, 6.0, D5, 5)
+ ARG(double, 7.0, D6, LAST_NAMED_ARG_ID)
+ DOTS
+ ANON(struct z, a, STACK, 8)
+ LAST_ANON(double, d1, STACK+16, 9)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-12.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-12.c
new file mode 100644
index 0000000..a12ccfd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-12.c
@@ -0,0 +1,60 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+ Pass by reference. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-12.c"
+
+struct z
+{
+ char c;
+ short s;
+ int ia[4];
+};
+
+struct z a, b, c;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ a.c = 0x11;
+ a.s = 0x2222;
+ a.ia[0] = 0x33333333;
+ a.ia[1] = 0x44444444;
+ a.ia[2] = 0x55555555;
+ a.ia[3] = 0x66666666;
+
+ b.c = 0x77;
+ b.s = 0x8888;
+ b.ia[0] = 0x99999999;
+ b.ia[1] = 0xaaaaaaaa;
+ b.ia[2] = 0xbbbbbbbb;
+ b.ia[3] = 0xcccccccc;
+
+ c.c = 0xdd;
+ c.s = 0xeeee;
+ c.ia[0] = 0xffffffff;
+ c.ia[1] = 0x12121212;
+ c.ia[2] = 0x23232323;
+ c.ia[3] = 0x34343434;
+}
+
+#include "abitest.h"
+#else
+ PTR(struct z, a, X0, 0)
+ ARG(int, 0xdeadbeef, X1, 1)
+ ARG(int, 0xcafebabe, X2, 2)
+ ARG(int, 0xdeadbabe, X3, 3)
+ ARG(int, 0xcafebeef, X4, 4)
+ ARG(int, 0xbeefdead, X5, 5)
+ ARG(int, 0xbabecafe, X6, LAST_NAMED_ARG_ID)
+ DOTS
+ PTR_ANON(struct z, b, X7, 7)
+ PTR_ANON(struct z, c, STACK, 8)
+ ANON(int, 0xbabedead, STACK+8, 9)
+ LAST_ANON(double, 123.45, D0, 10)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-2.c
new file mode 100644
index 0000000..b6da677
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-2.c
@@ -0,0 +1,59 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+ This test covers fundamental data types as specified in AAPCS64 \S 4.1.
+ It is focus on unnamed parameter passed on stack. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-2.c"
+#include "type-def.h"
+
+vf2_t vf2 = (vf2_t){ 17.f, 18.f };
+vi4_t vi4 = (vi4_t){ 0xdeadbabe, 0xbabecafe, 0xcafebeef, 0xbeefdead };
+union int128_t qword;
+signed char sc = 0xed;
+signed int sc_promoted = 0xffffffed;
+signed short ss = 0xcba9;
+signed int ss_promoted = 0xffffcba9;
+float fp = 65432.12345f;
+double fp_promoted = (double)65432.12345f;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ /* Init signed quad-word integer. */
+ qword.l64 = 0xfdb9753102468aceLL;
+ qword.h64 = 0xeca8642013579bdfLL;
+}
+
+#include "abitest.h"
+#else
+ ARG ( int , 0xff , X0, 0)
+ ARG ( float , 1.0f , S0, 1)
+ ARG ( float , 1.0f , S1, 2)
+ ARG ( float , 1.0f , S2, 3)
+ ARG ( float , 1.0f , S3, 4)
+ ARG ( float , 1.0f , S4, 5)
+ ARG ( float , 1.0f , S5, 6)
+ ARG ( float , 1.0f , S6, 7)
+ ARG ( float , 1.0f , S7, LAST_NAMED_ARG_ID)
+ DOTS
+ ANON ( __int128, qword.i , X2, 8)
+ ANON ( signed long long, 0xa987654321012345LL , X4, 9)
+ ANON ( __int128, qword.i , X6, 10)
+ ANON_PROMOTED(unsigned char , 0xfe , unsigned int, 0xfe , STACK, 11)
+ ANON_PROMOTED( signed char , sc , signed int, sc_promoted, STACK+8, 12)
+ ANON_PROMOTED(unsigned short , 0xdcba, unsigned int, 0xdcba , STACK+16, 13)
+ ANON_PROMOTED( signed short , ss , signed int, ss_promoted, STACK+24, 14)
+ ANON (unsigned int , 0xdeadbeef, STACK+32, 15)
+ ANON ( signed int , 0xcafebabe, STACK+40, 16)
+ ANON (unsigned long long, 0xba98765432101234ULL, STACK+48, 17)
+ ANON_PROMOTED( float , fp , double, fp_promoted, STACK+56, 18)
+ ANON ( double , 9876543.212345, STACK+64, 19)
+ ANON ( long double , 98765432123456789.987654321L, STACK+80, 20)
+ ANON ( vf2_t, vf2 , STACK+96, 21)
+ ANON ( vi4_t, vi4 , STACK+112,22)
+ LAST_ANON ( int , 0xeeee, STACK+128,23)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-3.c
new file mode 100644
index 0000000..34978c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-3.c
@@ -0,0 +1,86 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+ This test covers most composite types as described in AAPCS64 \S 4.3.
+ Homogeneous floating-point aggregate types are covered in other tests. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-3.c"
+#include "type-def.h"
+
+struct x0
+{
+ char ch;
+ int i;
+} y0 = { 'a', 12345 };
+
+struct x1
+{
+ int a;
+ int b;
+ int c;
+ int d;
+} y1 = { 0xdeadbeef, 0xcafebabe, 0x87654321, 0xabcedf975 };
+
+struct x2
+{
+ long long a;
+ long long b;
+ char ch;
+} y2 = { 0x12, 0x34, 0x56 };
+
+union x3
+{
+ char ch;
+ int i;
+ long long ll;
+} y3;
+
+union x4
+{
+ int i;
+ struct x2 y2;
+} y4;
+
+struct x5
+{
+ union int128_t qword;
+} y5;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ /* Init small union. */
+ y3.ll = 0xfedcba98LL;
+
+ /* Init big union. */
+ y4.y2.a = 0x78;
+ y4.y2.b = 0x89;
+ y4.y2.ch= 0x9a;
+
+ /* Init signed quad-word integer. */
+ y5.qword.l64 = 0xfdb9753102468aceLL;
+ y5.qword.h64 = 0xeca8642013579bdfLL;
+}
+
+#include "abitest.h"
+#else
+ ARG (float ,1.0f, S0, LAST_NAMED_ARG_ID)
+ DOTS
+ ANON (struct x0, y0, X0, 1)
+ ANON (struct x1, y1, X1, 2)
+ PTR_ANON (struct x2, y2, X3, 3)
+ ANON (union x3, y3, X4, 4)
+ PTR_ANON (union x4, y4, X5, 5)
+ ANON (struct x5, y5, X6, 6)
+ ANON (struct x0, y0, STACK, 7)
+ ANON (struct x1, y1, STACK+8, 8)
+ PTR_ANON (struct x2, y2, STACK+24, 9)
+ ANON (union x3, y3, STACK+32, 10)
+ PTR_ANON (union x4, y4, STACK+40, 11)
+ ANON (int , 1, STACK+48, 12)
+ ANON (struct x5, y5, STACK+64, 13)
+ LAST_ANON(int , 2, STACK+80, 14)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-4.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-4.c
new file mode 100644
index 0000000..d0e18db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-4.c
@@ -0,0 +1,93 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+ This test covers homogeneous floating-point aggregate types and homogeneous
+ short-vector aggregate types as described in AAPCS64 \S 4.3.5. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-4.c"
+#include "type-def.h"
+
+struct hfa_fx1_t hfa_fx1 = {12.345f};
+struct hfa_fx2_t hfa_fx2 = {123.456f, 234.456f};
+struct hfa_dx2_t hfa_dx2 = {234.567, 345.678};
+struct hfa_dx4_t hfa_dx4 = {1234.123, 2345.234, 3456.345, 4567.456};
+struct hfa_ldx3_t hfa_ldx3 = {123456.7890, 234567.8901, 345678.9012};
+struct non_hfa_fx5_t non_hfa_fx5 = {456.789f, 567.890f, 678.901f, 789.012f, 890.123f};
+struct hfa_ffs_t hfa_ffs;
+struct non_hfa_ffs_t non_hfa_ffs;
+struct non_hfa_ffs_2_t non_hfa_ffs_2;
+struct hva_vf2x1_t hva_vf2x1;
+struct hva_vf2x2_t hva_vf2x2;
+struct hva_vi4x1_t hva_vi4x1;
+struct non_hfa_ffd_t non_hfa_ffd = {23.f, 24.f, 25.0};
+struct non_hfa_ii_t non_hfa_ii = {26, 27};
+struct non_hfa_c_t non_hfa_c = {28};
+struct non_hfa_ffvf2_t non_hfa_ffvf2;
+struct non_hfa_fffd_t non_hfa_fffd = {33.f, 34.f, 35.f, 36.0};
+union hfa_union_t hfa_union;
+union non_hfa_union_t non_hfa_union;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ hva_vf2x1.a = (vf2_t){17.f, 18.f};
+ hva_vf2x2.a = (vf2_t){19.f, 20.f};
+ hva_vf2x2.b = (vf2_t){21.f, 22.f};
+ hva_vi4x1.a = (vi4_t){19, 20, 21, 22};
+
+ non_hfa_ffvf2.a = 29.f;
+ non_hfa_ffvf2.b = 30.f;
+ non_hfa_ffvf2.c = (vf2_t){31.f, 32.f};
+
+ hfa_union.s.a = 37.f;
+ hfa_union.s.b = 38.f;
+ hfa_union.c = 39.f;
+
+ non_hfa_union.a = 40.0;
+ non_hfa_union.b = 41.f;
+
+ hfa_ffs.a = 42.f;
+ hfa_ffs.b = 43.f;
+ hfa_ffs.c.a = 44.f;
+ hfa_ffs.c.b = 45.f;
+
+ non_hfa_ffs.a = 46.f;
+ non_hfa_ffs.b = 47.f;
+ non_hfa_ffs.c.a = 48.0;
+ non_hfa_ffs.c.b = 49.0;
+
+ non_hfa_ffs_2.s.a = 50;
+ non_hfa_ffs_2.s.b = 51;
+ non_hfa_ffs_2.c = 52.f;
+ non_hfa_ffs_2.d = 53.f;
+}
+
+#include "abitest.h"
+#else
+ ARG (int , 1, X0, LAST_NAMED_ARG_ID)
+ DOTS
+ /* HFA or HVA passed in fp/simd registers or on stack. */
+ ANON (struct hfa_fx1_t , hfa_fx1 , S0 , 0)
+ ANON (struct hfa_fx2_t , hfa_fx2 , S1 , 1)
+ ANON (struct hfa_dx2_t , hfa_dx2 , D3 , 2)
+ ANON (struct hva_vf2x1_t, hva_vf2x1, D5 , 11)
+ ANON (struct hva_vi4x1_t, hva_vi4x1, Q6 , 12)
+ ANON (struct hfa_dx4_t , hfa_dx4 , STACK , 3)
+ ANON (struct hfa_ffs_t , hfa_ffs , STACK+32, 4)
+ ANON (union hfa_union_t, hfa_union, STACK+48, 5)
+ ANON (struct hfa_ldx3_t , hfa_ldx3 , STACK+64, 6)
+ /* Non-H[FV]A passed in general registers or on stack or via reference. */
+ PTR_ANON (struct non_hfa_fx5_t , non_hfa_fx5 , X1 , 10)
+ ANON (struct non_hfa_ffd_t , non_hfa_ffd , X2 , 13)
+ ANON (struct non_hfa_ii_t , non_hfa_ii , X4 , 14)
+ ANON (struct non_hfa_c_t , non_hfa_c , X5 , 15)
+ ANON (struct non_hfa_ffvf2_t, non_hfa_ffvf2, X6 , 16)
+ PTR_ANON (struct non_hfa_fffd_t , non_hfa_fffd , STACK+112, 17)
+ PTR_ANON (struct non_hfa_ffs_t , non_hfa_ffs , STACK+120, 18)
+ ANON (struct non_hfa_ffs_2_t, non_hfa_ffs_2, STACK+128, 19)
+ ANON (union non_hfa_union_t, non_hfa_union, STACK+144, 20)
+ LAST_ANON(int , 2 , STACK+152, 30)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-5.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-5.c
new file mode 100644
index 0000000..6b99a6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-5.c
@@ -0,0 +1,47 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+ This test is focus on certain unnamed homogeneous floating-point aggregate
+ types passed in fp/simd registers. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-5.c"
+#include "type-def.h"
+
+struct hfa_fx1_t hfa_fx1 = {12.345f};
+struct hfa_fx2_t hfa_fx2 = {123.456f, 234.456f};
+struct hfa_dx2_t hfa_dx2 = {234.567, 345.678};
+struct hfa_dx4_t hfa_dx4 = {1234.123, 2345.234, 3456.345, 4567.456};
+struct hfa_ldx3_t hfa_ldx3 = {123456.7890, 234567.8901, 345678.9012};
+struct hfa_ffs_t hfa_ffs;
+union hfa_union_t hfa_union;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ hfa_union.s.a = 37.f;
+ hfa_union.s.b = 38.f;
+ hfa_union.c = 39.f;
+
+ hfa_ffs.a = 42.f;
+ hfa_ffs.b = 43.f;
+ hfa_ffs.c.a = 44.f;
+ hfa_ffs.c.b = 45.f;
+}
+
+#include "abitest.h"
+#else
+ ARG (int, 1, X0, LAST_NAMED_ARG_ID)
+ DOTS
+ /* HFA passed in fp/simd registers or on stack. */
+ ANON (struct hfa_dx4_t , hfa_dx4 , D0 , 0)
+ ANON (struct hfa_ldx3_t , hfa_ldx3 , Q4 , 1)
+ ANON (struct hfa_ffs_t , hfa_ffs , STACK , 2)
+ ANON (union hfa_union_t, hfa_union, STACK+16, 3)
+ ANON (struct hfa_fx1_t , hfa_fx1 , STACK+24, 4)
+ ANON (struct hfa_fx2_t , hfa_fx2 , STACK+32, 5)
+ ANON (struct hfa_dx2_t , hfa_dx2 , STACK+40, 6)
+ LAST_ANON(double , 1.0 , STACK+56, 7)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-6.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-6.c
new file mode 100644
index 0000000..f94a54a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-6.c
@@ -0,0 +1,40 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+ This test is focus on certain unnamed homogeneous floating-point aggregate
+ types passed in fp/simd registers. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-6.c"
+#include "type-def.h"
+
+struct hfa_fx1_t hfa_fx1 = {12.345f};
+struct hfa_dx2_t hfa_dx2 = {234.567, 345.678};
+struct hfa_ffs_t hfa_ffs;
+union hfa_union_t hfa_union;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+ hfa_union.s.a = 37.f;
+ hfa_union.s.b = 38.f;
+ hfa_union.c = 39.f;
+
+ hfa_ffs.a = 42.f;
+ hfa_ffs.b = 43.f;
+ hfa_ffs.c.a = 44.f;
+ hfa_ffs.c.b = 45.f;
+}
+
+#include "abitest.h"
+#else
+ ARG (int, 1, X0, LAST_NAMED_ARG_ID)
+ DOTS
+ ANON (struct hfa_ffs_t , hfa_ffs , S0 , 0)
+ ANON (union hfa_union_t, hfa_union, S4 , 1)
+ ANON (struct hfa_dx2_t , hfa_dx2 , D6 , 2)
+ ANON (struct hfa_fx1_t , hfa_fx1 , STACK , 3)
+ LAST_ANON(double , 1.0 , STACK+8, 4)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-7.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-7.c
new file mode 100644
index 0000000..b82e7a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-7.c
@@ -0,0 +1,31 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+ This test covers complex types. Complex floating-point types are treated
+ as homogeneous floating-point aggregates, while complex integral types
+ are treated as general composite types. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-7.c"
+#include "type-def.h"
+
+_Complex __int128 complex_qword = 567890 + 678901i;
+
+#include "abitest.h"
+#else
+ ARG (int, 1, X0, LAST_NAMED_ARG_ID)
+ DOTS
+ /* Complex floating-point types are passed in fp/simd registers. */
+ ANON (_Complex float , 12.3f + 23.4fi , S0, 0)
+ ANON (_Complex double , 34.56 + 45.67i , D2, 1)
+ ANON (_Complex long double, 56789.01234L + 67890.12345Li, Q4, 2)
+
+ /* Complex integral types are passed in general registers or via reference. */
+ ANON (_Complex short , (short)12345 + (short)23456i, X1, 10)
+ ANON (_Complex int , 34567 + 45678i , X2, 11)
+ PTR_ANON (_Complex __int128 , complex_qword , X3, 12)
+
+ LAST_ANON(int , 1 , X4, 20)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-8.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-8.c
new file mode 100644
index 0000000..d148482
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-8.c
@@ -0,0 +1,25 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+ Miscellaneous test: HFA anonymous parameter passed in SIMD/FP regs. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-8.c"
+
+struct z
+{
+ double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+
+#include "abitest.h"
+#else
+ ARG(int, 0xdeadbeef, W0, LAST_NAMED_ARG_ID)
+ DOTS
+ ANON(double, 4.0, D0, 1)
+ LAST_ANON(struct z, a, D1, 2)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-9.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-9.c
new file mode 100644
index 0000000..a5183be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-9.c
@@ -0,0 +1,31 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+ Miscellaneous test: HFA anonymous parameter passed in SIMD/FP regs. */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-9.c"
+
+struct z
+{
+ double x[4];
+};
+
+double d1 = 25.0;
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+ ARG(double, 11.0, D0, LAST_NAMED_ARG_ID)
+ DOTS
+ ANON(int, 8, W0, 1)
+ ANON(struct z, a, D1, 2)
+ ANON(struct z, b, STACK, 3)
+ ANON(int, 5, W1, 4)
+ ANON(double, d1, STACK+32, 5)
+ LAST_ANON(double, 0.5, STACK+40, 6)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/validate_memory.h b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/validate_memory.h
new file mode 100644
index 0000000..24431c6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/validate_memory.h
@@ -0,0 +1,81 @@
+/* Memory validation functions for AArch64 procedure call standard.
+ Copyright (C) 2012 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef VALIDATE_MEMORY_H
+#define VALIDATE_MEMORY_H
+
+enum structure_type
+{
+ flat = 0,
+ i32in128,
+ f32in64,
+ i8in64,
+ i16in64,
+ i32in64,
+};
+
+/* Some explicit declarations as I can't include files outside the testsuite.
+ */
+typedef long unsigned int size_t;
+int memcmp (void *, void *, size_t);
+
+/* These two arrays contain element size and block size data for the enumeration
+ above. */
+const int element_size[] = { 1, 4, 4, 1, 2, 4 };
+const int block_reverse_size[] = { 1, 16, 8, 8, 8, 8 };
+
+int
+validate_memory (void *mem1, char *mem2, size_t size, enum structure_type type)
+{
+ /* In big-endian mode, the data in mem2 will have been byte-reversed in
+ register sized groups, while the data in mem1 will have been byte-reversed
+ according to the true structure of the data. To compare them, we need to
+ compare chunks of data in reverse order.
+
+ This is only implemented for homogeneous data layouts at the moment. For
+ hetrogeneous structures a custom compare case will need to be written. */
+
+ unsigned int i;
+ char *cmem1 = (char *) mem1;
+ switch (type)
+ {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+ case i8in64:
+ case i16in64:
+ case i32in64:
+ for (i = 0; i < size; i += element_size[type])
+ {
+ if (memcmp (cmem1 + i,
+ mem2 + block_reverse_size[type] - i - element_size[type],
+ element_size[type]))
+ return 1;
+ }
+ return 0;
+ break;
+#endif
+ case f32in64:
+ case i32in128:
+ default:
+ break;
+ }
+ return memcmp (mem1, mem2, size);
+}
+
+#endif /* VALIDATE_MEMORY_H. */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aarch64.exp b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aarch64.exp
new file mode 100644
index 0000000..2cd3b80
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aarch64.exp
@@ -0,0 +1,45 @@
+# Specific regression driver for AArch64.
+# Copyright (C) 2009-2014 Free Software Foundation, Inc.
+# Contributed by ARM Ltd.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>. */
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an AArch64 target.
+if {![istarget aarch64*-*-*] } then {
+ return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+ set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+ "" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/abs_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/abs_1.c
new file mode 100644
index 0000000..938bc84
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/abs_1.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-inline --save-temps" } */
+
+extern long long llabs (long long);
+extern void abort (void);
+
+long long
+abs64 (long long a)
+{
+ /* { dg-final { scan-assembler "eor\t" } } */
+ /* { dg-final { scan-assembler "sub\t" } } */
+ return llabs (a);
+}
+
+long long
+abs64_in_dreg (long long a)
+{
+ /* { dg-final { scan-assembler "abs\td\[0-9\]+, d\[0-9\]+" } } */
+ register long long x asm ("d8") = a;
+ register long long y asm ("d9");
+ asm volatile ("" : : "w" (x));
+ y = llabs (x);
+ asm volatile ("" : : "w" (y));
+ return y;
+}
+
+int
+main (void)
+{
+ volatile long long ll0 = 0LL, ll1 = 1LL, llm1 = -1LL;
+
+ if (abs64 (ll0) != 0LL)
+ abort ();
+
+ if (abs64 (ll1) != 1LL)
+ abort ();
+
+ if (abs64 (llm1) != 1LL)
+ abort ();
+
+ if (abs64_in_dreg (ll0) != 0LL)
+ abort ();
+
+ if (abs64_in_dreg (ll1) != 1LL)
+ abort ();
+
+ if (abs64_in_dreg (llm1) != 1LL)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adc-1.c
new file mode 100644
index 0000000..c19920c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adc-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+volatile unsigned int w0, w1, w2, w3, w4;
+volatile int result;
+
+void test_si() {
+ /* { dg-final { scan-assembler "adc\tw\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+ w0 = w1 + w2 + (w3 >= w4);
+}
+
+volatile unsigned long long int x0, x1, x2, x3, x4;
+
+void test_di() {
+ /* { dg-final { scan-assembler "adc\tx\[0-9\]*, x\[0-9\]*, x\[0-9\]*\n" } } */
+ x0 = x1 + x2 + (x3 >= x4);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adc-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adc-2.c
new file mode 100644
index 0000000..0f13619
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adc-2.c
@@ -0,0 +1,277 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+/* This series of tests looks for the optimization:
+ x = (a >= b) + c + d
+ =>
+ cmp a, b
+ adc x, c, d
+ */
+
+unsigned long
+ltu_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d)
+{
+ return (a < b) + c + d;
+}
+
+unsigned long
+gtu_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d)
+{
+ return (a > b) + c + d;
+}
+
+unsigned long
+leu_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d)
+{
+ return (a <= b) + c + d;
+}
+
+unsigned long
+geu_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d)
+{
+ return (a >= b) + c + d;
+}
+
+unsigned long
+equ_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d)
+{
+ return (a == b) + c + d;
+}
+
+unsigned long
+neu_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d)
+{
+ return (a != b) + c + d;
+}
+
+long
+lt_add ( long a, long b, long c, long d)
+{
+ return (a < b) + c + d;
+}
+
+long
+gt_add ( long a, long b, long c, long d)
+{
+ return (a > b) + c + d;
+}
+
+long
+le_add ( long a, long b, long c, long d)
+{
+ return (a <= b) + c + d;
+}
+
+long
+ge_add ( long a, long b, long c, long d)
+{
+ return (a >= b) + c + d;
+}
+
+long
+eq_add ( long a, long b, long c, long d)
+{
+ return (a == b) + c + d;
+}
+
+long
+ne_add ( long a, long b, long c, long d)
+{
+ return (a != b) + c + d;
+}
+
+
+int
+main ()
+{
+ if (ltu_add(1,2,3,4) != 8)
+ {
+ abort();
+ }
+
+ if (ltu_add(2,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (ltu_add(3,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (gtu_add(2,1,3,4) != 8)
+ {
+ abort();
+ }
+
+ if (gtu_add(2,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (gtu_add(1,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (leu_add(1,2,3,4) != 8)
+ {
+ abort();
+ }
+
+ if (leu_add(2,2,3,4) != 8)
+ {
+ abort();
+ }
+
+ if (leu_add(3,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (leu_add(2,1,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (geu_add(2,1,3,4) != 8)
+ {
+ abort();
+ }
+ if (geu_add(2,2,3,4) != 8)
+ {
+ abort();
+ }
+
+ if (geu_add(1,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (equ_add(1,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (equ_add(2,2,3,4) != 8)
+ {
+ abort();
+ }
+
+ if (equ_add(3,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (neu_add(1,2,3,4) != 8)
+ {
+ abort();
+ }
+
+ if (neu_add(2,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (neu_add(3,2,3,4) != 8)
+ {
+ abort();
+ }
+
+ if (lt_add(1,2,3,4) != 8)
+ {
+ abort();
+ }
+
+ if (lt_add(2,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (lt_add(3,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (gt_add(2,1,3,4) != 8)
+ {
+ abort();
+ }
+
+ if (gt_add(2,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (gt_add(1,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (le_add(1,2,3,4) != 8)
+ {
+ abort();
+ }
+
+ if (le_add(2,2,3,4) != 8)
+ {
+ abort();
+ }
+
+ if (le_add(3,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (le_add(2,1,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (ge_add(2,1,3,4) != 8)
+ {
+ abort();
+ }
+ if (ge_add(2,2,3,4) != 8)
+ {
+ abort();
+ }
+
+ if (ge_add(1,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (eq_add(1,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (eq_add(2,2,3,4) != 8)
+ {
+ abort();
+ }
+
+ if (eq_add(3,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (ne_add(1,2,3,4) != 8)
+ {
+ abort();
+ }
+
+ if (ne_add(2,2,3,4) != 7)
+ {
+ abort();
+ }
+
+ if (ne_add(3,2,3,4) != 8)
+ {
+ abort();
+ }
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds.c
new file mode 100644
index 0000000..aa42321
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int z;
+int
+foo (int x, int y)
+{
+ int l = x + y;
+ if (l == 0)
+ return 5;
+
+ /* { dg-final { scan-assembler "adds\tw\[0-9\]" } } */
+ z = l ;
+ return 25;
+}
+
+typedef long long s64;
+
+s64 zz;
+s64
+foo2 (s64 x, s64 y)
+{
+ s64 l = x + y;
+ if (l < 0)
+ return 5;
+
+ /* { dg-final { scan-assembler "adds\tx\[0-9\]" } } */
+ zz = l ;
+ return 25;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds1.c
new file mode 100644
index 0000000..eb19bbf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds1.c
@@ -0,0 +1,149 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+adds_si_test1 (int a, int b, int c)
+{
+ int d = a + b;
+
+ /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+adds_si_test2 (int a, int b, int c)
+{
+ int d = a + 0xff;
+
+ /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, 255" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+adds_si_test3 (int a, int b, int c)
+{
+ int d = a + (b << 3);
+
+ /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+adds_di_test1 (s64 a, s64 b, s64 c)
+{
+ s64 d = a + b;
+
+ /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+adds_di_test2 (s64 a, s64 b, s64 c)
+{
+ s64 d = a + 0xff;
+
+ /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, 255" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+adds_di_test3 (s64 a, s64 b, s64 c)
+{
+ s64 d = a + (b << 3);
+
+ /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int main ()
+{
+ int x;
+ s64 y;
+
+ x = adds_si_test1 (29, 4, 5);
+ if (x != 42)
+ abort ();
+
+ x = adds_si_test1 (5, 2, 20);
+ if (x != 29)
+ abort ();
+
+ x = adds_si_test2 (29, 4, 5);
+ if (x != 293)
+ abort ();
+
+ x = adds_si_test2 (1024, 2, 20);
+ if (x != 1301)
+ abort ();
+
+ x = adds_si_test3 (35, 4, 5);
+ if (x != 76)
+ abort ();
+
+ x = adds_si_test3 (5, 2, 20);
+ if (x != 43)
+ abort ();
+
+ y = adds_di_test1 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+
+ if (y != 0xc75050536)
+ abort ();
+
+ y = adds_di_test1 (0x5000500050005ll,
+ 0x2111211121112ll,
+ 0x0000000002020ll);
+ if (y != 0x9222922294249)
+ abort ();
+
+ y = adds_di_test2 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+ if (y != 0x955050631)
+ abort ();
+
+ y = adds_di_test2 (0x130002900ll,
+ 0x320000004ll,
+ 0x505050505ll);
+ if (y != 0x955052f08)
+ abort ();
+
+ y = adds_di_test3 (0x130000029ll,
+ 0x064000008ll,
+ 0x505050505ll);
+ if (y != 0x9b9050576)
+ abort ();
+
+ y = adds_di_test3 (0x130002900ll,
+ 0x088000008ll,
+ 0x505050505ll);
+ if (y != 0xafd052e4d)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds2.c
new file mode 100644
index 0000000..bd130a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds2.c
@@ -0,0 +1,155 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+adds_si_test1 (int a, int b, int c)
+{
+ int d = a + b;
+
+ /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+ /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+adds_si_test2 (int a, int b, int c)
+{
+ int d = a + 0xfff;
+
+ /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, 4095" } } */
+ /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, 4095" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+adds_si_test3 (int a, int b, int c)
+{
+ int d = a + (b << 3);
+
+ /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+adds_di_test1 (s64 a, s64 b, s64 c)
+{
+ s64 d = a + b;
+
+ /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+ /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+adds_di_test2 (s64 a, s64 b, s64 c)
+{
+ s64 d = a + 0x1000ll;
+
+ /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, 4096" } } */
+ /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, 4096" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+adds_di_test3 (s64 a, s64 b, s64 c)
+{
+ s64 d = a + (b << 3);
+
+ /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int main ()
+{
+ int x;
+ s64 y;
+
+ x = adds_si_test1 (29, 4, 5);
+ if (x != 42)
+ abort ();
+
+ x = adds_si_test1 (5, 2, 20);
+ if (x != 29)
+ abort ();
+
+ x = adds_si_test2 (29, 4, 5);
+ if (x != 4133)
+ abort ();
+
+ x = adds_si_test2 (1024, 2, 20);
+ if (x != 5141)
+ abort ();
+
+ x = adds_si_test3 (35, 4, 5);
+ if (x != 76)
+ abort ();
+
+ x = adds_si_test3 (5, 2, 20);
+ if (x != 43)
+ abort ();
+
+ y = adds_di_test1 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+
+ if (y != 0xc75050536)
+ abort ();
+
+ y = adds_di_test1 (0x5000500050005ll,
+ 0x2111211121112ll,
+ 0x0000000002020ll);
+ if (y != 0x9222922294249)
+ abort ();
+
+ y = adds_di_test2 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+ if (y != 0x955051532)
+ abort ();
+
+ y = adds_di_test2 (0x540004100ll,
+ 0x320000004ll,
+ 0x805050205ll);
+ if (y != 0x1065055309)
+ abort ();
+
+ y = adds_di_test3 (0x130000029ll,
+ 0x064000008ll,
+ 0x505050505ll);
+ if (y != 0x9b9050576)
+ abort ();
+
+ y = adds_di_test3 (0x130002900ll,
+ 0x088000008ll,
+ 0x505050505ll);
+ if (y != 0xafd052e4d)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds3.c
new file mode 100644
index 0000000..18efd1c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds3.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+typedef long long s64;
+
+int
+adds_ext (s64 a, int b, int c)
+{
+ s64 d = a + b;
+
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+adds_shift_ext (s64 a, int b, int c)
+{
+ s64 d = (a + ((s64)b << 3));
+
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int main ()
+{
+ int x;
+ s64 y;
+
+ x = adds_ext (0x13000002ll, 41, 15);
+ if (x != 318767203)
+ abort ();
+
+ x = adds_ext (0x50505050ll, 29, 4);
+ if (x != 1347440782)
+ abort ();
+
+ x = adds_ext (0x12121212121ll, 2, 14);
+ if (x != 555819315)
+ abort ();
+
+ x = adds_shift_ext (0x123456789ll, 4, 12);
+ if (x != 591751097)
+ abort ();
+
+ x = adds_shift_ext (0x02020202ll, 9, 8);
+ if (x != 33686107)
+ abort ();
+
+ x = adds_shift_ext (0x987987987987ll, 23, 41);
+ if (x != -2020050305)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aes_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aes_1.c
new file mode 100644
index 0000000..5fa6137
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aes_1.c
@@ -0,0 +1,40 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+crypto" } */
+
+#include "arm_neon.h"
+
+uint8x16_t
+test_vaeseq_u8 (uint8x16_t data, uint8x16_t key)
+{
+ return vaeseq_u8 (data, key);
+}
+
+/* { dg-final { scan-assembler-times "aese\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+uint8x16_t
+test_vaesdq_u8 (uint8x16_t data, uint8x16_t key)
+{
+ return vaesdq_u8 (data, key);
+}
+
+/* { dg-final { scan-assembler-times "aesd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+uint8x16_t
+test_vaesmcq_u8 (uint8x16_t data)
+{
+ return vaesmcq_u8 (data);
+}
+
+/* { dg-final { scan-assembler-times "aesmc\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+uint8x16_t
+test_vaesimcq_u8 (uint8x16_t data)
+{
+ return vaesimcq_u8 (data);
+}
+
+/* { dg-final { scan-assembler-times "aesimc\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ands_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ands_1.c
new file mode 100644
index 0000000..aace0b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ands_1.c
@@ -0,0 +1,151 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+ands_si_test1 (int a, int b, int c)
+{
+ int d = a & b;
+
+ /* { dg-final { scan-assembler-times "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+ands_si_test2 (int a, int b, int c)
+{
+ int d = a & 0xff;
+
+ /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, 255" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+ands_si_test3 (int a, int b, int c)
+{
+ int d = a & (b << 3);
+
+ /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+ands_di_test1 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & b;
+
+ /* { dg-final { scan-assembler-times "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+ands_di_test2 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & 0xff;
+
+ /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, 255" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+ands_di_test3 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & (b << 3);
+
+ /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+main ()
+{
+ int x;
+ s64 y;
+
+ x = ands_si_test1 (29, 4, 5);
+ if (x != 13)
+ abort ();
+
+ x = ands_si_test1 (5, 2, 20);
+ if (x != 25)
+ abort ();
+
+ x = ands_si_test2 (29, 4, 5);
+ if (x != 38)
+ abort ();
+
+ x = ands_si_test2 (1024, 2, 20);
+ if (x != 1044)
+ abort ();
+
+ x = ands_si_test3 (35, 4, 5);
+ if (x != 41)
+ abort ();
+
+ x = ands_si_test3 (5, 2, 20);
+ if (x != 25)
+ abort ();
+
+ y = ands_di_test1 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+
+ if (y != ((0x130000029ll & 0x320000004ll) + 0x320000004ll + 0x505050505ll))
+ abort ();
+
+ y = ands_di_test1 (0x5000500050005ll,
+ 0x2111211121112ll,
+ 0x0000000002020ll);
+ if (y != 0x5000500052025ll)
+ abort ();
+
+ y = ands_di_test2 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+ if (y != ((0x130000029ll & 0xff) + 0x320000004ll + 0x505050505ll))
+ abort ();
+
+ y = ands_di_test2 (0x130002900ll,
+ 0x320000004ll,
+ 0x505050505ll);
+ if (y != (0x130002900ll + 0x505050505ll))
+ abort ();
+
+ y = ands_di_test3 (0x130000029ll,
+ 0x064000008ll,
+ 0x505050505ll);
+ if (y != ((0x130000029ll & (0x064000008ll << 3))
+ + 0x064000008ll + 0x505050505ll))
+ abort ();
+
+ y = ands_di_test3 (0x130002900ll,
+ 0x088000008ll,
+ 0x505050505ll);
+ if (y != (0x130002900ll + 0x505050505ll))
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ands_2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ands_2.c
new file mode 100644
index 0000000..1c5b821
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ands_2.c
@@ -0,0 +1,157 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+ands_si_test1 (int a, int b, int c)
+{
+ int d = a & b;
+
+ /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+ /* { dg-final { scan-assembler-times "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+ands_si_test2 (int a, int b, int c)
+{
+ int d = a & 0x99999999;
+
+ /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
+ /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+ands_si_test3 (int a, int b, int c)
+{
+ int d = a & (b << 3);
+
+ /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+ands_di_test1 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & b;
+
+ /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+ /* { dg-final { scan-assembler-times "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+ands_di_test2 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & 0xaaaaaaaaaaaaaaaall;
+
+ /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
+ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+ands_di_test3 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & (b << 3);
+
+ /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+main ()
+{
+ int x;
+ s64 y;
+
+ x = ands_si_test1 (29, 4, 5);
+ if (x != 13)
+ abort ();
+
+ x = ands_si_test1 (5, 2, 20);
+ if (x != 25)
+ abort ();
+
+ x = ands_si_test2 (29, 4, 5);
+ if (x != 34)
+ abort ();
+
+ x = ands_si_test2 (1024, 2, 20);
+ if (x != 1044)
+ abort ();
+
+ x = ands_si_test3 (35, 4, 5);
+ if (x != 41)
+ abort ();
+
+ x = ands_si_test3 (5, 2, 20);
+ if (x != 25)
+ abort ();
+
+ y = ands_di_test1 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+
+ if (y != ((0x130000029ll & 0x320000004ll) + 0x320000004ll + 0x505050505ll))
+ abort ();
+
+ y = ands_di_test1 (0x5000500050005ll,
+ 0x2111211121112ll,
+ 0x0000000002020ll);
+ if (y != 0x5000500052025ll)
+ abort ();
+
+ y = ands_di_test2 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+ if (y != ((0x130000029ll & 0xaaaaaaaaaaaaaaaall) + 0x320000004ll + 0x505050505ll))
+ abort ();
+
+ y = ands_di_test2 (0x540004100ll,
+ 0x320000004ll,
+ 0x805050205ll);
+ if (y != (0x540004100ll + 0x805050205ll))
+ abort ();
+
+ y = ands_di_test3 (0x130000029ll,
+ 0x064000008ll,
+ 0x505050505ll);
+ if (y != ((0x130000029ll & (0x064000008ll << 3))
+ + 0x064000008ll + 0x505050505ll))
+ abort ();
+
+ y = ands_di_test3 (0x130002900ll,
+ 0x088000008ll,
+ 0x505050505ll);
+ if (y != (0x130002900ll + 0x505050505ll))
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-1.c
new file mode 100644
index 0000000..a0f5982
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-1.c
@@ -0,0 +1,7 @@
+/* { dg-error "unknown" "" {target "aarch64*-*-*" } } */
+/* { dg-options "-O2 -march=dummy" } */
+
+void f ()
+{
+ return;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-2.c
new file mode 100644
index 0000000..f1f3ea3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-2.c
@@ -0,0 +1,7 @@
+/* { dg-error "missing" "" {target "aarch64*-*-*" } } */
+/* { dg-options "-O2 -march=+dummy" } */
+
+void f ()
+{
+ return;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arg-type-diagnostics-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arg-type-diagnostics-1.c
new file mode 100644
index 0000000..55dd9f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arg-type-diagnostics-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { aarch64*-*-* } } } */
+/* { dg-options "-O2" } */
+
+#include "arm_neon.h"
+
+void foo ()
+{
+ int a;
+ int32x2_t arg1;
+ int32x2_t arg2;
+ int32x2_t result;
+ arg1 = vcreate_s32 (UINT64_C (0x0000ffffffffffff));
+ arg2 = vcreate_s32 (UINT64_C (0x16497fffffffffff));
+ result = __builtin_aarch64_srsra_nv2si (arg1, arg2, a); /* { dg-error "incompatible type for argument" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-1.c
new file mode 100644
index 0000000..bdfa450
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-1.c
@@ -0,0 +1,15 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+typedef struct
+{
+ int i;
+ int y;
+} __attribute__ ((aligned (16))) struct64_t;
+
+void foo ()
+{
+ struct64_t tmp;
+ asm volatile ("ldr q0, %[value]" : : [value]"m"(tmp));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-adder-clobber-lr.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-adder-clobber-lr.c
new file mode 100644
index 0000000..540c79b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-adder-clobber-lr.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+int
+adder (int a, int b)
+{
+ int result;
+ __asm__ ("add %w0,%w1,%w2" : "=r"(result) : "r"(a), "r"(b) : "x30");
+ return result;
+}
+
+int
+main (int argc, char** argv)
+{
+ int i;
+ int total = argc;
+ for (i = 0; i < 20; i++)
+ total = adder (total, i);
+
+ if (total != (190 + argc))
+ abort ();
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-adder-no-clobber-lr.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-adder-no-clobber-lr.c
new file mode 100644
index 0000000..2543d50
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-adder-no-clobber-lr.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+int
+adder (int a, int b)
+{
+ int result;
+ __asm__ ("add %w0,%w1,%w2" : "=r"(result) : "r"(a), "r"(b) : );
+ return result;
+}
+
+int
+main (int argc, char** argv)
+{
+ int i;
+ int total = argc;
+ for (i = 0; i < 20; i++)
+ total = adder (total, i);
+
+ if (total != (190 + argc))
+ abort ();
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c
new file mode 100644
index 0000000..9785bca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-comp-swap-release-acquire.x"
+
+/* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x
new file mode 100644
index 0000000..4403afd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x
@@ -0,0 +1,36 @@
+
+#define STRONG 0
+#define WEAK 1
+int v = 0;
+
+int
+atomic_compare_exchange_STRONG_RELEASE_ACQUIRE (int a, int b)
+{
+ return __atomic_compare_exchange (&v, &a, &b,
+ STRONG, __ATOMIC_RELEASE,
+ __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_compare_exchange_WEAK_RELEASE_ACQUIRE (int a, int b)
+{
+ return __atomic_compare_exchange (&v, &a, &b,
+ WEAK, __ATOMIC_RELEASE,
+ __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_compare_exchange_n_STRONG_RELEASE_ACQUIRE (int a, int b)
+{
+ return __atomic_compare_exchange_n (&v, &a, b,
+ STRONG, __ATOMIC_RELEASE,
+ __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_compare_exchange_n_WEAK_RELEASE_ACQUIRE (int a, int b)
+{
+ return __atomic_compare_exchange_n (&v, &a, b,
+ WEAK, __ATOMIC_RELEASE,
+ __ATOMIC_ACQUIRE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c
new file mode 100644
index 0000000..8569ac0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-acq_rel.x"
+
+/* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x
new file mode 100644
index 0000000..9970bbb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x
@@ -0,0 +1,37 @@
+int v = 0;
+
+int
+atomic_fetch_add_ACQ_REL (int a)
+{
+ return __atomic_fetch_add (&v, a, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_sub_ACQ_REL (int a)
+{
+ return __atomic_fetch_sub (&v, a, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_and_ACQ_REL (int a)
+{
+ return __atomic_fetch_and (&v, a, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_nand_ACQ_REL (int a)
+{
+ return __atomic_fetch_nand (&v, a, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_xor_ACQ_REL (int a)
+{
+ return __atomic_fetch_xor (&v, a, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_or_ACQ_REL (int a)
+{
+ return __atomic_fetch_or (&v, a, __ATOMIC_ACQ_REL);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c
new file mode 100644
index 0000000..57e6d57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-acquire.x"
+
+/* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x
new file mode 100644
index 0000000..7eeb7f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x
@@ -0,0 +1,37 @@
+int v = 0;
+
+int
+atomic_fetch_add_ACQUIRE (int a)
+{
+ return __atomic_fetch_add (&v, a, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_sub_ACQUIRE (int a)
+{
+ return __atomic_fetch_sub (&v, a, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_and_ACQUIRE (int a)
+{
+ return __atomic_fetch_and (&v, a, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_nand_ACQUIRE (int a)
+{
+ return __atomic_fetch_nand (&v, a, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_xor_ACQUIRE (int a)
+{
+ return __atomic_fetch_xor (&v, a, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_or_ACQUIRE (int a)
+{
+ return __atomic_fetch_or (&v, a, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c
new file mode 100644
index 0000000..d6c2aa5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-char.x"
+
+/* { dg-final { scan-assembler-times "ldxrb\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stxrb\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x
new file mode 100644
index 0000000..a543aa9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x
@@ -0,0 +1,37 @@
+char v = 0;
+
+char
+atomic_fetch_add_RELAXED (char a)
+{
+ return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
+}
+
+char
+atomic_fetch_sub_RELAXED (char a)
+{
+ return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
+}
+
+char
+atomic_fetch_and_RELAXED (char a)
+{
+ return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
+}
+
+char
+atomic_fetch_nand_RELAXED (char a)
+{
+ return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
+}
+
+char
+atomic_fetch_xor_RELAXED (char a)
+{
+ return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
+}
+
+char
+atomic_fetch_or_RELAXED (char a)
+{
+ return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c
new file mode 100644
index 0000000..38d6c2c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-consume.x"
+
+/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x
new file mode 100644
index 0000000..c6b0792
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x
@@ -0,0 +1,37 @@
+int v = 0;
+
+int
+atomic_fetch_add_CONSUME (int a)
+{
+ return __atomic_fetch_add (&v, a, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_sub_CONSUME (int a)
+{
+ return __atomic_fetch_sub (&v, a, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_and_CONSUME (int a)
+{
+ return __atomic_fetch_and (&v, a, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_nand_CONSUME (int a)
+{
+ return __atomic_fetch_nand (&v, a, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_xor_CONSUME (int a)
+{
+ return __atomic_fetch_xor (&v, a, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_or_CONSUME (int a)
+{
+ return __atomic_fetch_or (&v, a, __ATOMIC_CONSUME);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c
new file mode 100644
index 0000000..6c6f7e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c
@@ -0,0 +1,78 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int v = 0;
+
+int
+atomic_fetch_add_RELAXED ()
+{
+ return __atomic_fetch_add (&v, 4096, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_sub_ACQUIRE ()
+{
+ return __atomic_fetch_sub (&v, 4096, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_and_SEQ_CST ()
+{
+ return __atomic_fetch_and (&v, 4096, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_nand_ACQ_REL ()
+{
+ return __atomic_fetch_nand (&v, 4096, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_xor_CONSUME ()
+{
+ return __atomic_fetch_xor (&v, 4096, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_or_RELAXED ()
+{
+ return __atomic_fetch_or (&v, 4096, __ATOMIC_RELAXED);
+}
+
+int
+atomic_add_fetch_ACQUIRE ()
+{
+ return __atomic_add_fetch (&v, 4096, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_sub_fetch_RELAXED ()
+{
+ return __atomic_sub_fetch (&v, 4096, __ATOMIC_RELAXED);
+}
+
+int
+atomic_and_fetch_SEQ_CST ()
+{
+ return __atomic_and_fetch (&v, 4096, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_nand_fetch_ACQUIRE ()
+{
+ return __atomic_nand_fetch (&v, 4096, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_xor_fetch_RELEASE ()
+{
+ return __atomic_xor_fetch (&v, 4096, __ATOMIC_RELEASE);
+}
+
+int
+atomic_or_fetch_CONSUME ()
+{
+ return __atomic_or_fetch (&v, 4096, __ATOMIC_CONSUME);
+}
+
+/* { dg-final { scan-assembler-times "\tw\[0-9\]+, w\[0-9\]+, #*4096" 12 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c
new file mode 100644
index 0000000..9ad7a79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-int.x"
+
+/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x
new file mode 100644
index 0000000..74ab632
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x
@@ -0,0 +1,37 @@
+int v = 0;
+
+int
+atomic_fetch_add_RELAXED (int a)
+{
+ return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_sub_RELAXED (int a)
+{
+ return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_and_RELAXED (int a)
+{
+ return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_nand_RELAXED (int a)
+{
+ return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_xor_RELAXED (int a)
+{
+ return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_or_RELAXED (int a)
+{
+ return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
new file mode 100644
index 0000000..0672d48
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+long v = 0;
+
+long
+atomic_fetch_add_RELAXED (long a)
+{
+ return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
+}
+
+long
+atomic_fetch_sub_RELAXED (long a)
+{
+ return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
+}
+
+long
+atomic_fetch_and_RELAXED (long a)
+{
+ return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
+}
+
+long
+atomic_fetch_nand_RELAXED (long a)
+{
+ return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
+}
+
+long
+atomic_fetch_xor_RELAXED (long a)
+{
+ return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
+}
+
+long
+atomic_fetch_or_RELAXED (long a)
+{
+ return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
+}
+
+/* { dg-final { scan-assembler-times "ldxr\tx\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */
+/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, x\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c
new file mode 100644
index 0000000..cd3fe2c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-relaxed.x"
+
+/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x
new file mode 100644
index 0000000..74ab632
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x
@@ -0,0 +1,37 @@
+int v = 0;
+
+int
+atomic_fetch_add_RELAXED (int a)
+{
+ return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_sub_RELAXED (int a)
+{
+ return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_and_RELAXED (int a)
+{
+ return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_nand_RELAXED (int a)
+{
+ return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_xor_RELAXED (int a)
+{
+ return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_or_RELAXED (int a)
+{
+ return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c
new file mode 100644
index 0000000..2fc04b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-release.x"
+
+/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x
new file mode 100644
index 0000000..343f09b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x
@@ -0,0 +1,37 @@
+int v = 0;
+
+int
+atomic_fetch_add_RELEASE (int a)
+{
+ return __atomic_fetch_add (&v, a, __ATOMIC_RELEASE);
+}
+
+int
+atomic_fetch_sub_RELEASE (int a)
+{
+ return __atomic_fetch_sub (&v, a, __ATOMIC_RELEASE);
+}
+
+int
+atomic_fetch_and_RELEASE (int a)
+{
+ return __atomic_fetch_and (&v, a, __ATOMIC_RELEASE);
+}
+
+int
+atomic_fetch_nand_RELEASE (int a)
+{
+ return __atomic_fetch_nand (&v, a, __ATOMIC_RELEASE);
+}
+
+int
+atomic_fetch_xor_RELEASE (int a)
+{
+ return __atomic_fetch_xor (&v, a, __ATOMIC_RELEASE);
+}
+
+int
+atomic_fetch_or_RELEASE (int a)
+{
+ return __atomic_fetch_or (&v, a, __ATOMIC_RELEASE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c
new file mode 100644
index 0000000..202d471
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-seq_cst.x"
+
+/* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x
new file mode 100644
index 0000000..e654a74
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x
@@ -0,0 +1,37 @@
+int v = 0;
+
+int
+atomic_fetch_add_SEQ_CST (int a)
+{
+ return __atomic_fetch_add (&v, a, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_sub_SEQ_CST (int a)
+{
+ return __atomic_fetch_sub (&v, a, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_and_SEQ_CST (int a)
+{
+ return __atomic_fetch_and (&v, a, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_nand_SEQ_CST (int a)
+{
+ return __atomic_fetch_nand (&v, a, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_xor_SEQ_CST (int a)
+{
+ return __atomic_fetch_xor (&v, a, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_or_SEQ_CST (int a)
+{
+ return __atomic_fetch_or (&v, a, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c
new file mode 100644
index 0000000..39e71c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-short.x"
+
+/* { dg-final { scan-assembler-times "ldxrh\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stxrh\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x
new file mode 100644
index 0000000..2fd70f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x
@@ -0,0 +1,37 @@
+short v = 0;
+
+short
+atomic_fetch_add_RELAXED (short a)
+{
+ return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
+}
+
+short
+atomic_fetch_sub_RELAXED (short a)
+{
+ return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
+}
+
+short
+atomic_fetch_and_RELAXED (short a)
+{
+ return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
+}
+
+short
+atomic_fetch_nand_RELAXED (short a)
+{
+ return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
+}
+
+short
+atomic_fetch_xor_RELAXED (short a)
+{
+ return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
+}
+
+short
+atomic_fetch_or_RELAXED (short a)
+{
+ return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bfxil_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bfxil_1.c
new file mode 100644
index 0000000..b168347
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bfxil_1.c
@@ -0,0 +1,40 @@
+/* { dg-do run { target aarch64*-*-* } } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+/* { dg-require-effective-target aarch64_little_endian } */
+
+extern void abort (void);
+
+typedef struct bitfield
+{
+ unsigned short eight1: 8;
+ unsigned short four: 4;
+ unsigned short eight2: 8;
+ unsigned short seven: 7;
+ unsigned int sixteen: 16;
+} bitfield;
+
+bitfield
+bfxil (bitfield a)
+{
+ /* { dg-final { scan-assembler "bfxil\tx\[0-9\]+, x\[0-9\]+, 16, 8" } } */
+ a.eight1 = a.eight2;
+ return a;
+}
+
+int
+main (void)
+{
+ static bitfield a;
+ bitfield b;
+
+ a.eight1 = 9;
+ a.eight2 = 57;
+ b = bfxil (a);
+
+ if (b.eight1 != a.eight2)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bfxil_2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bfxil_2.c
new file mode 100644
index 0000000..4e4d610
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bfxil_2.c
@@ -0,0 +1,42 @@
+/* { dg-do run { target aarch64*-*-* } } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+/* { dg-require-effective-target aarch64_big_endian } */
+
+extern void abort (void);
+
+typedef struct bitfield
+{
+ unsigned short eight1: 8;
+ unsigned short four: 4;
+ unsigned short eight2: 8;
+ unsigned short seven: 7;
+ unsigned int sixteen: 16;
+ unsigned short eight3: 8;
+ unsigned short eight4: 8;
+} bitfield;
+
+bitfield
+bfxil (bitfield a)
+{
+ /* { dg-final { scan-assembler "bfxil\tx\[0-9\]+, x\[0-9\]+, 40, 8" } } */
+ a.eight4 = a.eight2;
+ return a;
+}
+
+int
+main (void)
+{
+ static bitfield a;
+ bitfield b;
+
+ a.eight4 = 9;
+ a.eight2 = 57;
+ b = bfxil (a);
+
+ if (b.eight4 != a.eight2)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bics_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bics_1.c
new file mode 100644
index 0000000..d62ea9a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bics_1.c
@@ -0,0 +1,107 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+bics_si_test1 (int a, int b, int c)
+{
+ int d = a & ~b;
+
+ /* { dg-final { scan-assembler-times "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+bics_si_test2 (int a, int b, int c)
+{
+ int d = a & ~(b << 3);
+
+ /* { dg-final { scan-assembler "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+bics_di_test1 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & ~b;
+
+ /* { dg-final { scan-assembler-times "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+bics_di_test2 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & ~(b << 3);
+
+ /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+main ()
+{
+ int x;
+ s64 y;
+
+ x = bics_si_test1 (29, ~4, 5);
+ if (x != ((29 & 4) + ~4 + 5))
+ abort ();
+
+ x = bics_si_test1 (5, ~2, 20);
+ if (x != 25)
+ abort ();
+
+ x = bics_si_test2 (35, ~4, 5);
+ if (x != ((35 & ~(~4 << 3)) + ~4 + 5))
+ abort ();
+
+ x = bics_si_test2 (96, ~2, 20);
+ if (x != 116)
+ abort ();
+
+ y = bics_di_test1 (0x130000029ll,
+ ~0x320000004ll,
+ 0x505050505ll);
+
+ if (y != ((0x130000029ll & 0x320000004ll) + ~0x320000004ll + 0x505050505ll))
+ abort ();
+
+ y = bics_di_test1 (0x5000500050005ll,
+ ~0x2111211121112ll,
+ 0x0000000002020ll);
+ if (y != 0x5000500052025ll)
+ abort ();
+
+ y = bics_di_test2 (0x130000029ll,
+ ~0x064000008ll,
+ 0x505050505ll);
+ if (y != ((0x130000029ll & ~(~0x064000008ll << 3))
+ + ~0x064000008ll + 0x505050505ll))
+ abort ();
+
+ y = bics_di_test2 (0x130002900ll,
+ ~0x088000008ll,
+ 0x505050505ll);
+ if (y != (0x130002900ll + 0x505050505ll))
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bics_2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bics_2.c
new file mode 100644
index 0000000..e33c748
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bics_2.c
@@ -0,0 +1,111 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+bics_si_test1 (int a, int b, int c)
+{
+ int d = a & ~b;
+
+ /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+ /* { dg-final { scan-assembler-times "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+bics_si_test2 (int a, int b, int c)
+{
+ int d = a & ~(b << 3);
+
+ /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+bics_di_test1 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & ~b;
+
+ /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+ /* { dg-final { scan-assembler-times "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+bics_di_test2 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & ~(b << 3);
+
+ /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+main ()
+{
+ int x;
+ s64 y;
+
+ x = bics_si_test1 (29, ~4, 5);
+ if (x != ((29 & 4) + ~4 + 5))
+ abort ();
+
+ x = bics_si_test1 (5, ~2, 20);
+ if (x != 25)
+ abort ();
+
+ x = bics_si_test2 (35, ~4, 5);
+ if (x != ((35 & ~(~4 << 3)) + ~4 + 5))
+ abort ();
+
+ x = bics_si_test2 (96, ~2, 20);
+ if (x != 116)
+ abort ();
+
+ y = bics_di_test1 (0x130000029ll,
+ ~0x320000004ll,
+ 0x505050505ll);
+
+ if (y != ((0x130000029ll & 0x320000004ll) + ~0x320000004ll + 0x505050505ll))
+ abort ();
+
+ y = bics_di_test1 (0x5000500050005ll,
+ ~0x2111211121112ll,
+ 0x0000000002020ll);
+ if (y != 0x5000500052025ll)
+ abort ();
+
+ y = bics_di_test2 (0x130000029ll,
+ ~0x064000008ll,
+ 0x505050505ll);
+ if (y != ((0x130000029ll & ~(~0x064000008ll << 3))
+ + ~0x064000008ll + 0x505050505ll))
+ abort ();
+
+ y = bics_di_test2 (0x130002900ll,
+ ~0x088000008ll,
+ 0x505050505ll);
+ if (y != (0x130002900ll + 0x505050505ll))
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/builtin-bswap-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/builtin-bswap-1.c
new file mode 100644
index 0000000..a6706e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/builtin-bswap-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-times "rev16\\t" 2 } } */
+
+/* rev16 */
+short
+swaps16 (short x)
+{
+ return __builtin_bswap16 (x);
+}
+
+/* rev16 */
+unsigned short
+swapu16 (unsigned short x)
+{
+ return __builtin_bswap16 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/builtin-bswap-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/builtin-bswap-2.c
new file mode 100644
index 0000000..6018b48
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/builtin-bswap-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-times "rev16\\t" 2 } } */
+
+/* rev16 */
+unsigned short
+swapu16_1 (unsigned short x)
+{
+ return (x << 8) | (x >> 8);
+}
+
+/* rev16 */
+unsigned short
+swapu16_2 (unsigned short x)
+{
+ return (x >> 8) | (x << 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template-2.c
new file mode 100644
index 0000000..ced96d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+
+void
+test (void)
+{
+ __asm__ ("@ %c0" : : "S" (test));
+}
+
+/* { dg-final { scan-assembler "@ test" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template-3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template-3.c
new file mode 100644
index 0000000..c28837c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-Wno-pointer-arith" } */
+
+void
+test (void)
+{
+ __asm__ ("@ %c0" : : "S" (&test + 4));
+}
+
+/* { dg-final { scan-assembler "@ test\\+4" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template.c
new file mode 100644
index 0000000..1b67c91
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+
+void
+test (void)
+{
+ __asm__ ("@ %c0" : : "i" (42));
+}
+
+/* { dg-final { scan-assembler "@ 42" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/clrsb.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/clrsb.c
new file mode 100644
index 0000000..ac8d2e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/clrsb.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int functest (unsigned int x)
+{
+ return __builtin_clrsb (x);
+}
+
+/* { dg-final { scan-assembler "cls\tw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/clz.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/clz.c
new file mode 100644
index 0000000..b650b13
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/clz.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int functest (unsigned int x)
+{
+ return __builtin_clz (x);
+}
+
+/* { dg-final { scan-assembler "clz\tw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn-neg.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn-neg.c
new file mode 100644
index 0000000..ab264e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn-neg.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+void __attribute__ ((noinline))
+foo_s32 (int a, int b)
+{
+ if (a == -b)
+ abort ();
+}
+/* { dg-final { scan-assembler "cmn\tw\[0-9\]" } } */
+
+void __attribute__ ((noinline))
+foo_s64 (long long a, long long b)
+{
+ if (a == -b)
+ abort ();
+}
+/* { dg-final { scan-assembler "cmn\tx\[0-9\]" } } */
+
+
+int
+main (void)
+{
+ int a = 30;
+ int b = 42;
+ foo_s32 (a, b);
+ foo_s64 (a, b);
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn-neg2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn-neg2.c
new file mode 100644
index 0000000..ca45a53
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn-neg2.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+/* It's unsafe to use CMN in these comparisons. */
+
+void __attribute__ ((noinline))
+foo_s32 (int a, int b)
+{
+ if (a < -b)
+ abort ();
+}
+
+void __attribute__ ((noinline))
+foo_s64 (unsigned long long a, unsigned long long b)
+{
+ if (a > -b)
+ abort ();
+}
+
+
+int
+main (void)
+{
+ int a = 30;
+ int b = 42;
+ foo_s32 (a, b);
+ foo_s64 (a, b);
+ return 0;
+}
+/* { dg-final { scan-assembler-not "cmn\t" } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn.c
new file mode 100644
index 0000000..1f06f57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+foo (int a, int b)
+{
+ if (a + b)
+ return 5;
+ else
+ return 2;
+ /* { dg-final { scan-assembler "cmn\tw\[0-9\]" } } */
+}
+
+typedef long long s64;
+
+s64
+foo2 (s64 a, s64 b)
+{
+ if (a + b)
+ return 5;
+ else
+ return 2;
+ /* { dg-final { scan-assembler "cmn\tx\[0-9\]" } } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmp-1.c
new file mode 100644
index 0000000..4c082b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmp-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int f(int a, int b)
+{
+ if(a<b)
+ return 1;
+ if(a>b)
+ return -1;
+ return 0;
+}
+
+/* We should optimize away the second cmp. */
+/* { dg-final { scan-assembler-times "cmp\tw" 1 } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmp.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmp.c
new file mode 100644
index 0000000..ee57dd2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmp.c
@@ -0,0 +1,61 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+cmp_si_test1 (int a, int b, int c)
+{
+ if (a > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+int
+cmp_si_test2 (int a, int b, int c)
+{
+ if ((a >> 3) > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+typedef long long s64;
+
+s64
+cmp_di_test1 (s64 a, s64 b, s64 c)
+{
+ if (a > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+s64
+cmp_di_test2 (s64 a, s64 b, s64 c)
+{
+ if ((a >> 3) > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+int
+cmp_di_test3 (int a, s64 b, s64 c)
+{
+ if (a > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+int
+cmp_di_test4 (int a, s64 b, s64 c)
+{
+ if (((s64)a << 3) > b)
+ return a + c;
+ else
+ return a + b + c;
+}
+
+/* { dg-final { scan-assembler-times "cmp\tw\[0-9\]+, w\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, x\[0-9\]+" 4 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c
new file mode 100644
index 0000000..de6b8a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c
@@ -0,0 +1,7 @@
+/* { dg-error "unknown" "" {target "aarch64*-*-*" } } */
+/* { dg-options "-O2 -mcpu=dummy" } */
+
+void f ()
+{
+ return;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c
new file mode 100644
index 0000000..2ca0065
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c
@@ -0,0 +1,7 @@
+/* { dg-error "missing" "" {target "aarch64*-*-*" } } */
+/* { dg-options "-O2 -mcpu=cortex-a53+no" } */
+
+void f ()
+{
+ return;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c
new file mode 100644
index 0000000..155def0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c
@@ -0,0 +1,7 @@
+/* { dg-error "unknown" "" {target "aarch64*-*-*" } } */
+/* { dg-options "-O2 -mcpu=cortex-a53+dummy" } */
+
+void f ()
+{
+ return;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-4.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-4.c
new file mode 100644
index 0000000..4c246eb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-4.c
@@ -0,0 +1,7 @@
+/* { dg-error "missing" "" {target "aarch64*-*-*" } } */
+/* { dg-options "-O2 -mcpu=+dummy" } */
+
+void f ()
+{
+ return;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinc-1.c
new file mode 100644
index 0000000..132a0f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinc-1.c
@@ -0,0 +1,72 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int
+test_csinc32_ifcvt(unsigned int w0,
+ unsigned int w1,
+ unsigned int w2) {
+ /* { dg-final { scan-assembler "csinc\tw\[0-9\]*.*ne" } } */
+ if (w0 == w1)
+ ++ w2;
+
+ return w2;
+}
+
+unsigned int
+test_csinc32_condasn1(unsigned int w0,
+ unsigned int w1,
+ unsigned int w2,
+ unsigned int w3) {
+ unsigned int w4;
+
+ /* { dg-final { scan-assembler "csinc\tw\[0-9\]*.*ne" } } */
+ w4 = (w0 == w1) ? (w3 + 1) : w2;
+ return w4;
+}
+
+unsigned int
+test_csinc32_condasn2(unsigned int w0,
+ unsigned int w1,
+ unsigned int w2,
+ unsigned int w3) {
+ unsigned int w4;
+
+ /* { dg-final { scan-assembler "csinc\tw\[0-9\]*.*eq" } } */
+ w4 = (w0 == w1) ? w2 : (w3 + 1);
+ return w4;
+}
+
+unsigned long long
+test_csinc64_ifcvt(unsigned long long x0,
+ unsigned long long x1,
+ unsigned long long x2) {
+ /* { dg-final { scan-assembler "csinc\tx\[0-9\]*.*ne" } } */
+ if (x0 == x1)
+ ++ x2;
+
+ return x2;
+}
+
+unsigned long long
+test_csinc64_condasn1(unsigned long long x0,
+ unsigned long long x1,
+ unsigned long long x2,
+ unsigned long long x3) {
+ unsigned long long x4;
+
+ /* { dg-final { scan-assembler "csinc\tx\[0-9\]*.*ne" } } */
+ x4 = (x0 == x1) ? (x3 + 1) : x2;
+ return x4;
+}
+
+unsigned long long
+test_csinc64_condasn2(unsigned long long x0,
+ unsigned long long x1,
+ unsigned long long x2,
+ unsigned long long x3) {
+ unsigned long long x4;
+
+ /* { dg-final { scan-assembler "csinc\tx\[0-9\]*.*eq" } } */
+ x4 = (x0 == x1) ? x2 : (x3 + 1);
+ return x4;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinc-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinc-2.c
new file mode 100644
index 0000000..9bd6861
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinc-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+foo (int a, int b)
+{
+ return (a < b) ? 1 : 7;
+ /* { dg-final { scan-assembler "csinc\tw\[0-9\].*wzr" } } */
+}
+
+typedef long long s64;
+
+s64
+foo2 (s64 a, s64 b)
+{
+ return (a == b) ? 7 : 1;
+ /* { dg-final { scan-assembler "csinc\tx\[0-9\].*xzr" } } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinv-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinv-1.c
new file mode 100644
index 0000000..8d44449
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinv-1.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int
+test_csinv32_condasn1(unsigned int w0,
+ unsigned int w1,
+ unsigned int w2,
+ unsigned int w3) {
+ unsigned int w4;
+
+ /* { dg-final { scan-assembler "csinv\tw\[0-9\]*.*ne" } } */
+ w4 = (w0 == w1) ? ~w3 : w2;
+ return w4;
+}
+
+unsigned int
+test_csinv32_condasn2(unsigned int w0,
+ unsigned int w1,
+ unsigned int w2,
+ unsigned int w3) {
+ unsigned int w4;
+
+ /* { dg-final { scan-assembler "csinv\tw\[0-9\]*.*eq" } } */
+ w4 = (w0 == w1) ? w3 : ~w2;
+ return w4;
+}
+
+unsigned long long
+test_csinv64_condasn1(unsigned long long x0,
+ unsigned long long x1,
+ unsigned long long x2,
+ unsigned long long x3) {
+ unsigned long long x4;
+
+ /* { dg-final { scan-assembler "csinv\tx\[0-9\]*.*ne" } } */
+ x4 = (x0 == x1) ? ~x3 : x2;
+ return x4;
+}
+
+unsigned long long
+test_csinv64_condasn2(unsigned long long x0,
+ unsigned long long x1,
+ unsigned long long x2,
+ unsigned long long x3) {
+ unsigned long long x4;
+
+ /* { dg-final { scan-assembler "csinv\tx\[0-9\]*.*eq" } } */
+ x4 = (x0 == x1) ? x3 : ~x2;
+ return x4;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csneg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csneg-1.c
new file mode 100644
index 0000000..08001af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csneg-1.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+test_csneg32_condasn1(int w0,
+ int w1,
+ int w2,
+ int w3) {
+ int w4;
+
+ /* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*ne" } } */
+ w4 = (w0 == w1) ? -w3 : w2;
+ return w4;
+}
+
+int
+test_csneg32_condasn2(int w0,
+ int w1,
+ int w2,
+ int w3) {
+ int w4;
+
+ /* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*eq" } } */
+ w4 = (w0 == w1) ? w3 : -w2;
+ return w4;
+}
+
+long long
+test_csneg64_condasn1(long long x0,
+ long long x1,
+ long long x2,
+ long long x3) {
+ long long x4;
+
+ /* { dg-final { scan-assembler "csneg\tx\[0-9\]*.*ne" } } */
+ x4 = (x0 == x1) ? -x3 : x2;
+ return x4;
+}
+
+long long
+test_csneg64_condasn2(long long x0,
+ long long x1,
+ long long x2,
+ long long x3) {
+ long long x4;
+
+ /* { dg-final { scan-assembler "csneg\tx\[0-9\]*.*eq" } } */
+ x4 = (x0 == x1) ? x3 : -x2;
+ return x4;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ctz.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ctz.c
new file mode 100644
index 0000000..89d6fb4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ctz.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int functest (unsigned int x)
+{
+ return __builtin_ctz (x);
+}
+
+/* { dg-final { scan-assembler "rbit\tw" } } */
+/* { dg-final { scan-assembler "clz\tw" } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/dwarf-cfa-reg.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/dwarf-cfa-reg.c
new file mode 100644
index 0000000..cce8815
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/dwarf-cfa-reg.c
@@ -0,0 +1,14 @@
+/* Verify that CFA register is restored to SP after FP is restored. */
+/* { dg-do compile } */
+/* { dg-options "-O0 -gdwarf-2" } */
+/* { dg-final { scan-assembler ".cfi_restore 30" } } */
+/* { dg-final { scan-assembler ".cfi_restore 29" } } */
+/* { dg-final { scan-assembler ".cfi_def_cfa 31, 0" } } */
+/* { dg-final { scan-assembler "ret" } } */
+
+int bar (unsigned int);
+
+int foo (void)
+{
+ return bar (0xcafe);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/extend.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/extend.c
new file mode 100644
index 0000000..f399e55
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/extend.c
@@ -0,0 +1,170 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+ldr_uxtw (int *arr, unsigned int i)
+{
+ /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*uxtw #?2]" } } */
+ return arr[i];
+}
+
+int
+ldr_uxtw0 (char *arr, unsigned int i)
+{
+ /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*uxtw]" } } */
+ return arr[i];
+}
+
+int
+ldr_sxtw (int *arr, int i)
+{
+ /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*sxtw #?2]" } } */
+ return arr[i];
+}
+
+int
+ldr_sxtw0 (char *arr, int i)
+{
+ /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*sxtw]" } } */
+ return arr[i];
+}
+
+unsigned long long
+adddi_uxtw (unsigned long long a, unsigned int i)
+{
+ /* { dg-final { scan-assembler "add\tx\[0-9\]+,.*uxtw #?3" } } */
+ return a + ((unsigned long long)i << 3);
+}
+
+unsigned long long
+adddi_uxtw0 (unsigned long long a, unsigned int i)
+{
+ /* { dg-final { scan-assembler "add\tx\[0-9\]+,.*uxtw\n" } } */
+ return a + i;
+}
+
+long long
+adddi_sxtw (long long a, int i)
+{
+ /* { dg-final { scan-assembler "add\tx\[0-9\]+,.*sxtw #?3" } } */
+ return a + ((long long)i << 3);
+}
+
+long long
+adddi_sxtw0 (long long a, int i)
+{
+ /* { dg-final { scan-assembler "add\tx\[0-9\]+,.*sxtw\n" } } */
+ return a + i;
+}
+
+unsigned long long
+subdi_uxtw (unsigned long long a, unsigned int i)
+{
+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*uxtw #?3" } } */
+ return a - ((unsigned long long)i << 3);
+}
+
+unsigned long long
+subdi_uxtw0 (unsigned long long a, unsigned int i)
+{
+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*uxtw\n" } } */
+ return a - i;
+}
+
+long long
+subdi_sxtw (long long a, int i)
+{
+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*sxtw #?3" } } */
+ return a - ((long long)i << 3);
+}
+
+long long
+subdi_sxtw0 (long long a, int i)
+{
+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*sxtw\n" } } */
+ return a - (long long)i;
+}
+
+unsigned long long
+subdi_uxth (unsigned long long a, unsigned short i)
+{
+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*uxth #?1" } } */
+ return a - ((unsigned long long)i << 1);
+}
+
+unsigned long long
+subdi_uxth0 (unsigned long long a, unsigned short i)
+{
+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*uxth\n" } } */
+ return a - i;
+}
+
+long long
+subdi_sxth (long long a, short i)
+{
+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*sxth #?1" } } */
+ return a - ((long long)i << 1);
+}
+
+long long
+subdi_sxth0 (long long a, short i)
+{
+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*sxth\n" } } */
+ return a - (long long)i;
+}
+
+unsigned int
+subsi_uxth (unsigned int a, unsigned short i)
+{
+ /* { dg-final { scan-assembler "sub\tw\[0-9\]+,.*uxth #?1" } } */
+ return a - ((unsigned int)i << 1);
+}
+
+unsigned int
+subsi_uxth0 (unsigned int a, unsigned short i)
+{
+ /* { dg-final { scan-assembler "sub\tw\[0-9\]+,.*uxth\n" } } */
+ return a - i;
+}
+
+int
+subsi_sxth (int a, short i)
+{
+ /* { dg-final { scan-assembler "sub\tw\[0-9\]+,.*sxth #?1" } } */
+ return a - ((int)i << 1);
+}
+
+int
+subsi_sxth0 (int a, short i)
+{
+ /* { dg-final { scan-assembler "sub\tw\[0-9\]+,.*sxth\n" } } */
+ return a - (int)i;
+}
+
+unsigned int
+addsi_uxth (unsigned int a, unsigned short i)
+{
+ /* { dg-final { scan-assembler "add\tw\[0-9\]+,.*uxth #?1" } } */
+ return a + ((unsigned int)i << 1);
+}
+
+unsigned int
+addsi_uxth0 (unsigned int a, unsigned short i)
+{
+ /* { dg-final { scan-assembler "add\tw\[0-9\]+,.*uxth\n" } } */
+ return a + i;
+}
+
+int
+addsi_sxth (int a, short i)
+{
+ /* { dg-final { scan-assembler "add\tw\[0-9\]+,.*sxth #?1" } } */
+ return a + ((int)i << 1);
+}
+
+int
+addsi_sxth0 (int a, short i)
+{
+ /* { dg-final { scan-assembler "add\tw\[0-9\]+,.*sxth\n" } } */
+ return a + (int)i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/extr.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/extr.c
new file mode 100644
index 0000000..a78dd8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/extr.c
@@ -0,0 +1,34 @@
+/* { dg-options "-O2 --save-temps" } */
+/* { dg-do run } */
+
+extern void abort (void);
+
+int
+test_si (int a, int b)
+{
+ /* { dg-final { scan-assembler "extr\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, 27\n" } } */
+ return (a << 5) | ((unsigned int) b >> 27);
+}
+
+long long
+test_di (long long a, long long b)
+{
+ /* { dg-final { scan-assembler "extr\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, 45\n" } } */
+ return (a << 19) | ((unsigned long long) b >> 45);
+}
+
+int
+main ()
+{
+ int v;
+ long long w;
+ v = test_si (0x00000004, 0x30000000);
+ if (v != 0x00000086)
+ abort();
+ w = test_di (0x0001040040040004ll, 0x0070050066666666ll);
+ if (w != 0x2002002000200380ll)
+ abort();
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fabd.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fabd.c
new file mode 100644
index 0000000..7206d5e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fabd.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O1 -fno-inline --save-temps" } */
+
+extern double fabs (double);
+extern float fabsf (float);
+extern void abort ();
+extern void exit (int);
+
+void
+fabd_d (double x, double y, double d)
+{
+ if ((fabs (x - y) - d) > 0.00001)
+ abort ();
+}
+
+/* { dg-final { scan-assembler "fabd\td\[0-9\]+" } } */
+
+void
+fabd_f (float x, float y, float d)
+{
+ if ((fabsf (x - y) - d) > 0.00001)
+ abort ();
+}
+
+/* { dg-final { scan-assembler "fabd\ts\[0-9\]+" } } */
+
+int
+main ()
+{
+ fabd_d (10.0, 5.0, 5.0);
+ fabd_d (5.0, 10.0, 5.0);
+ fabd_f (10.0, 5.0, 5.0);
+ fabd_f (5.0, 10.0, 5.0);
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt.x
new file mode 100644
index 0000000..be50ee5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt.x
@@ -0,0 +1,55 @@
+extern GPF SUFFIX(trunc) (GPF);
+extern GPF SUFFIX(ceil) (GPF);
+extern GPF SUFFIX(floor) (GPF);
+extern GPF SUFFIX(round) (GPF);
+
+GPI test1a (GPF x) {
+ return SUFFIX(__builtin_trunc)(x);
+}
+
+GPI test1b (GPF x)
+{
+ return SUFFIX(trunc)(x);
+}
+
+GPI test2a (GPF x)
+{
+ return SUFFIX(__builtin_lceil)(x);
+}
+
+GPI test2b (GPF x)
+{
+ return SUFFIX(ceil)(x);
+}
+
+GPI test2c (GPF x)
+{
+ return SUFFIX(__builtin_ceil)(x);
+}
+
+GPI test3a (GPF x)
+{
+ return SUFFIX(__builtin_lfloor)(x);
+}
+
+GPI test3b (GPF x)
+{
+ return SUFFIX(floor)(x);
+}
+
+GPI test3c (GPF x)
+{
+ return SUFFIX(__builtin_floor)(x);
+}
+
+GPI test4a (GPF x)
+{
+ return SUFFIX(__builtin_round)(x);
+}
+
+GPI test4b (GPF x)
+{
+ return SUFFIX(round)(x);
+}
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c
new file mode 100644
index 0000000..e539909
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF double
+#define SUFFIX(x) x
+#define GPI int
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *d\[0-9\]" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c
new file mode 100644
index 0000000..5eb36ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF double
+#define SUFFIX(x) x
+#define GPI long
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c
new file mode 100644
index 0000000..59be475
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF double
+#define SUFFIX(x) x
+#define GPI unsigned int
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *d\[0-9\]" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c
new file mode 100644
index 0000000..55723cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF double
+#define SUFFIX(x) x
+#define GPI unsigned long
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c
new file mode 100644
index 0000000..2e10e2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF float
+#define SUFFIX(x) x##f
+#define GPI int
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *s\[0-9\]" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c
new file mode 100644
index 0000000..1debf71
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF float
+#define SUFFIX(x) x##f
+#define GPI long
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c
new file mode 100644
index 0000000..c0b0c69
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF float
+#define SUFFIX(x) x##f
+#define GPI unsigned int
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *s\[0-9\]" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c
new file mode 100644
index 0000000..07309e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF float
+#define SUFFIX(x) x##f
+#define GPI unsigned long
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ffs.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ffs.c
new file mode 100644
index 0000000..a344761
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ffs.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int functest(unsigned int x)
+{
+ return __builtin_ffs(x);
+}
+
+/* { dg-final { scan-assembler "cmp\tw" } } */
+/* { dg-final { scan-assembler "rbit\tw" } } */
+/* { dg-final { scan-assembler "clz\tw" } } */
+/* { dg-final { scan-assembler "csinc\tw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmadd.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmadd.c
new file mode 100644
index 0000000..39975db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmadd.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+extern double fma (double, double, double);
+extern float fmaf (float, float, float);
+
+double test_fma1 (double x, double y, double z)
+{
+ return fma (x, y, z);
+}
+
+float test_fma2 (float x, float y, float z)
+{
+ return fmaf (x, y, z);
+}
+
+double test_fnma1 (double x, double y, double z)
+{
+ return fma (-x, y, z);
+}
+
+float test_fnma2 (float x, float y, float z)
+{
+ return fmaf (-x, y, z);
+}
+
+double test_fms1 (double x, double y, double z)
+{
+ return fma (x, y, -z);
+}
+
+float test_fms2 (float x, float y, float z)
+{
+ return fmaf (x, y, -z);
+}
+
+double test_fnms1 (double x, double y, double z)
+{
+ return fma (-x, y, -z);
+}
+
+float test_fnms2 (float x, float y, float z)
+{
+ return fmaf (-x, y, -z);
+}
+
+/* { dg-final { scan-assembler-times "fmadd\td\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fmadd\ts\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fmsub\td\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fmsub\ts\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fnmsub\td\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fnmsub\ts\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fnmadd\td\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fnmadd\ts\[0-9\]" 1 } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
new file mode 100644
index 0000000..0bf1b86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
@@ -0,0 +1,116 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+#define DELTA 0.0001
+
+extern double fabs (double);
+
+extern void abort (void);
+
+#define TEST_VMLA(q1, q2, size, in1_lanes, in2_lanes) \
+static void \
+test_vfma##q1##_lane##q2##_f##size (float##size##_t * res, \
+ const float##size##_t *in1, \
+ const float##size##_t *in2) \
+{ \
+ float##size##x##in1_lanes##_t a = vld1##q1##_f##size (res); \
+ float##size##x##in1_lanes##_t b = vld1##q1##_f##size (in1); \
+ float##size##x##in2_lanes##_t c; \
+ if (in2_lanes > 1) \
+ { \
+ c = vld1##q2##_f##size (in2); \
+ a = vfma##q1##_lane##q2##_f##size (a, b, c, 1); \
+ } \
+ else \
+ { \
+ c = vld1##q2##_f##size (in2 + 1); \
+ a = vfma##q1##_lane##q2##_f##size (a, b, c, 0); \
+ } \
+ vst1##q1##_f##size (res, a); \
+}
+
+#define BUILD_VARS(width, n_lanes, n_half_lanes) \
+TEST_VMLA ( , , width, n_half_lanes, n_half_lanes) \
+TEST_VMLA (q, , width, n_lanes, n_half_lanes) \
+TEST_VMLA ( , q, width, n_half_lanes, n_lanes) \
+TEST_VMLA (q, q, width, n_lanes, n_lanes) \
+
+BUILD_VARS (32, 4, 2)
+BUILD_VARS (64, 2, 1)
+
+#define POOL2 {0.0, 1.0}
+#define POOL4 {0.0, 1.0, 2.0, 3.0}
+#define EMPTY2 {0.0, 0.0}
+#define EMPTY4 {0.0, 0.0, 0.0, 0.0}
+
+#define BUILD_TEST(size, lanes) \
+static void \
+test_f##size (void) \
+{ \
+ int i; \
+ float##size##_t pool[lanes] = POOL##lanes; \
+ float##size##_t res[lanes] = EMPTY##lanes; \
+ float##size##_t res2[lanes] = EMPTY##lanes; \
+ float##size##_t res3[lanes] = EMPTY##lanes; \
+ float##size##_t res4[lanes] = EMPTY##lanes; \
+ \
+ /* Forecfully avoid optimization. */ \
+ asm volatile ("" : : : "memory"); \
+ test_vfma_lane_f##size (res, pool, pool); \
+ for (i = 0; i < lanes / 2; i++) \
+ if (fabs (res[i] - pool[i]) > DELTA) \
+ abort (); \
+ \
+ /* Forecfully avoid optimization. */ \
+ asm volatile ("" : : : "memory"); \
+ test_vfmaq_lane_f##size (res2, pool, pool); \
+ for (i = 0; i < lanes; i++) \
+ if (fabs (res2[i] - pool[i]) > DELTA) \
+ abort (); \
+ \
+ /* Forecfully avoid optimization. */ \
+ asm volatile ("" : : : "memory"); \
+ test_vfma_laneq_f##size (res3, pool, pool); \
+ for (i = 0; i < lanes / 2; i++) \
+ if (fabs (res3[i] - pool[i]) > DELTA) \
+ abort (); \
+ \
+ /* Forecfully avoid optimization. */ \
+ asm volatile ("" : : : "memory"); \
+ test_vfmaq_laneq_f##size (res4, pool, pool); \
+ for (i = 0; i < lanes; i++) \
+ if (fabs (res4[i] - pool[i]) > DELTA) \
+ abort (); \
+}
+
+BUILD_TEST (32, 4)
+BUILD_TEST (64, 2)
+
+int
+main (int argc, char **argv)
+{
+ test_f32 ();
+ test_f64 ();
+ return 0;
+}
+
+/* vfma_laneq_f32.
+ vfma_lane_f32. */
+/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */
+
+/* vfmaq_lane_f32.
+ vfmaq_laneq_f32. */
+/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */
+
+/* vfma_lane_f64. */
+/* { dg-final { scan-assembler-times "fmadd\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */
+
+/* vfmaq_lane_f64.
+ vfma_laneq_f64.
+ vfmaq_laneq_f64. */
+/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d\\\[\[0-9\]+\\\]" 3 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
new file mode 100644
index 0000000..8cc2942
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
@@ -0,0 +1,117 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+#define DELTA 0.0001
+
+extern double fabs (double);
+
+extern void abort (void);
+
+#define TEST_VMLS(q1, q2, size, in1_lanes, in2_lanes) \
+static void \
+test_vfms##q1##_lane##q2##_f##size (float##size##_t * res, \
+ const float##size##_t *in1, \
+ const float##size##_t *in2) \
+{ \
+ float##size##x##in1_lanes##_t a = vld1##q1##_f##size (res); \
+ float##size##x##in1_lanes##_t b = vld1##q1##_f##size (in1); \
+ float##size##x##in2_lanes##_t c; \
+ if (in2_lanes > 1) \
+ { \
+ c = vld1##q2##_f##size (in2); \
+ a = vfms##q1##_lane##q2##_f##size (a, b, c, 1); \
+ } \
+ else \
+ { \
+ c = vld1##q2##_f##size (in2 + 1); \
+ a = vfms##q1##_lane##q2##_f##size (a, b, c, 0); \
+ } \
+ vst1##q1##_f##size (res, a); \
+}
+
+#define BUILD_VARS(width, n_lanes, n_half_lanes) \
+TEST_VMLS ( , , width, n_half_lanes, n_half_lanes) \
+TEST_VMLS (q, , width, n_lanes, n_half_lanes) \
+TEST_VMLS ( , q, width, n_half_lanes, n_lanes) \
+TEST_VMLS (q, q, width, n_lanes, n_lanes) \
+
+BUILD_VARS (32, 4, 2)
+BUILD_VARS (64, 2, 1)
+
+#define POOL2 {0.0, 1.0}
+#define POOL4 {0.0, 1.0, 2.0, 3.0}
+#define EMPTY2 {0.0, 0.0}
+#define EMPTY4 {0.0, 0.0, 0.0, 0.0}
+
+#define BUILD_TEST(size, lanes) \
+static void \
+test_f##size (void) \
+{ \
+ int i; \
+ float##size##_t pool[lanes] = POOL##lanes; \
+ float##size##_t res[lanes] = EMPTY##lanes; \
+ float##size##_t res2[lanes] = EMPTY##lanes; \
+ float##size##_t res3[lanes] = EMPTY##lanes; \
+ float##size##_t res4[lanes] = EMPTY##lanes; \
+ \
+ /* Forecfully avoid optimization. */ \
+ asm volatile ("" : : : "memory"); \
+ test_vfms_lane_f##size (res, pool, pool); \
+ asm volatile ("" : :"Q" (res) : "memory"); \
+ for (i = 0; i < lanes / 2; i++) \
+ if (fabs (res[i] + pool[i]) > DELTA) \
+ abort (); \
+ \
+ /* Forecfully avoid optimization. */ \
+ test_vfmsq_lane_f##size (res2, pool, pool); \
+ asm volatile ("" : :"Q" (res2) : "memory"); \
+ for (i = 0; i < lanes; i++) \
+ if (fabs (res2[i] + pool[i]) > DELTA) \
+ abort (); \
+ \
+ /* Forecfully avoid optimization. */ \
+ test_vfms_laneq_f##size (res3, pool, pool); \
+ asm volatile ("" : :"Q" (res3) : "memory"); \
+ for (i = 0; i < lanes / 2; i++) \
+ if (fabs (res3[i] + pool[i]) > DELTA) \
+ abort (); \
+ \
+ /* Forecfully avoid optimization. */ \
+ test_vfmsq_laneq_f##size (res4, pool, pool); \
+ asm volatile ("" : :"Q" (res4) : "memory"); \
+ for (i = 0; i < lanes; i++) \
+ if (fabs (res4[i] + pool[i]) > DELTA) \
+ abort (); \
+}
+
+BUILD_TEST (32, 4)
+BUILD_TEST (64, 2)
+
+int
+main (int argc, char **argv)
+{
+ test_f32 ();
+ test_f64 ();
+ return 0;
+}
+
+/* vfms_laneq_f32.
+ vfms_lane_f32. */
+/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */
+
+/* vfmsq_lane_f32.
+ vfmsq_laneq_f32. */
+/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */
+
+/* vfms_lane_f64. */
+/* { dg-final { scan-assembler-times "fmsub\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */
+
+/* vfmsq_lane_f64.
+ vfms_laneq_f64.
+ vfmsq_laneq_f64. */
+/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d\\\[\[0-9\]+\\\]" 3 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovd-zero.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovd-zero.c
new file mode 100644
index 0000000..7e4590a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovd-zero.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+foo (double *output)
+{
+ *output = 0.0;
+}
+
+/* { dg-final { scan-assembler "fmov\\td\[0-9\]+, xzr" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovd.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovd.c
new file mode 100644
index 0000000..c50e74e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovd.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+foo (double *output)
+{
+ *output = 4.25;
+}
+
+/* { dg-final { scan-assembler "fmov\\td\[0-9\]+, 4\\.25" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovf-zero.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovf-zero.c
new file mode 100644
index 0000000..5050ac3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovf-zero.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+foo (float *output)
+{
+ *output = 0.0;
+}
+
+/* { dg-final { scan-assembler "fmov\\ts\[0-9\]+, wzr" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovf.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovf.c
new file mode 100644
index 0000000..0a9e215
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovf.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+foo (float *output)
+{
+ *output = 4.25;
+}
+
+/* { dg-final { scan-assembler "fmov\\ts\[0-9\]+, 4\\.25" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmul_intrinsic_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmul_intrinsic_1.c
new file mode 100644
index 0000000..f6e32f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmul_intrinsic_1.c
@@ -0,0 +1,116 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+#define DELTA 0.0001
+extern void abort (void);
+extern double fabs (double);
+
+#define TEST_VMUL(q1, q2, size, in1_lanes, in2_lanes) \
+static void \
+test_vmul##q1##_lane##q2##_f##size (float##size##_t * res, \
+ const float##size##_t *in1, \
+ const float##size##_t *in2) \
+{ \
+ float##size##x##in1_lanes##_t a = vld1##q1##_f##size (res); \
+ float##size##x##in1_lanes##_t b = vld1##q1##_f##size (in1); \
+ float##size##x##in2_lanes##_t c; \
+ if (in2_lanes > 1) \
+ { \
+ c = vld1##q2##_f##size (in2); \
+ a = vmul##q1##_lane##q2##_f##size (b, c, 1); \
+ } \
+ else \
+ { \
+ c = vld1##q2##_f##size (in2 + 1); \
+ a = vmul##q1##_lane##q2##_f##size (b, c, 0); \
+ } \
+ vst1##q1##_f##size (res, a); \
+}
+
+#define BUILD_VARS(width, n_lanes, n_half_lanes) \
+TEST_VMUL ( , , width, n_half_lanes, n_half_lanes) \
+TEST_VMUL (q, , width, n_lanes, n_half_lanes) \
+TEST_VMUL ( , q, width, n_half_lanes, n_lanes) \
+TEST_VMUL (q, q, width, n_lanes, n_lanes)
+
+BUILD_VARS (32, 4, 2)
+BUILD_VARS (64, 2, 1)
+
+#define POOL2 {0.0, 1.0}
+#define POOL4 {0.0, 1.0, 2.0, 3.0}
+#define EMPTY2 {0.0, 0.0}
+#define EMPTY4 {0.0, 0.0, 0.0, 0.0}
+
+#define BUILD_TEST(size, lanes) \
+static void \
+test_f##size (void) \
+{ \
+ int i; \
+ float##size##_t pool[lanes] = POOL##lanes; \
+ float##size##_t res[lanes] = EMPTY##lanes; \
+ float##size##_t res2[lanes] = EMPTY##lanes; \
+ float##size##_t res3[lanes] = EMPTY##lanes; \
+ float##size##_t res4[lanes] = EMPTY##lanes; \
+ \
+ /* Avoid constant folding the multiplication. */ \
+ asm volatile ("" : : : "memory"); \
+ test_vmul_lane_f##size (res, pool, pool); \
+ /* Avoid fusing multiplication and subtraction. */ \
+ asm volatile ("" : :"Q" (res) : "memory"); \
+ for (i = 0; i < lanes / 2; i++) \
+ if (fabs (res[i] - pool[i]) > DELTA) \
+ abort (); \
+ \
+ test_vmulq_lane_f##size (res2, pool, pool); \
+ /* Avoid fusing multiplication and subtraction. */ \
+ asm volatile ("" : :"Q" (res2) : "memory"); \
+ for (i = 0; i < lanes; i++) \
+ if (fabs (res2[i] - pool[i]) > DELTA) \
+ abort (); \
+ \
+ test_vmul_laneq_f##size (res3, pool, pool); \
+ /* Avoid fusing multiplication and subtraction. */ \
+ asm volatile ("" : :"Q" (res3) : "memory"); \
+ for (i = 0; i < lanes / 2; i++) \
+ if (fabs (res3[i] - pool[i]) > DELTA) \
+ abort (); \
+ \
+ test_vmulq_laneq_f##size (res4, pool, pool); \
+ /* Avoid fusing multiplication and subtraction. */ \
+ asm volatile ("" : :"Q" (res4) : "memory"); \
+ for (i = 0; i < lanes; i++) \
+ if (fabs (res4[i] - pool[i]) > DELTA) \
+ abort (); \
+}
+
+BUILD_TEST (32, 4)
+BUILD_TEST (64, 2)
+
+int
+main (int argc, char **argv)
+{
+ test_f32 ();
+ test_f64 ();
+ return 0;
+}
+
+/* vmul_laneq_f32.
+ vmul_lane_f32. */
+/* { dg-final { scan-assembler-times "fmul\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
+
+/* vmulq_lane_f32.
+ vmulq_laneq_f32. */
+/* { dg-final { scan-assembler-times "fmul\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
+
+/* vmul_lane_f64. */
+/* { dg-final { scan-assembler-times "fmul\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
+
+/* vmul_laneq_f64.
+ vmulq_lane_f64.
+ vmulq_laneq_f64. */
+/* { dg-final { scan-assembler-times "fmul\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fnmadd-fastmath.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fnmadd-fastmath.c
new file mode 100644
index 0000000..9c115df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fnmadd-fastmath.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math" } */
+
+extern double fma (double, double, double);
+extern float fmaf (float, float, float);
+
+double test_fma1 (double x, double y, double z)
+{
+ return - fma (x, y, z);
+}
+
+float test_fma2 (float x, float y, float z)
+{
+ return - fmaf (x, y, z);
+}
+
+/* { dg-final { scan-assembler-times "fnmadd\td\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fnmadd\ts\[0-9\]" 1 } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint.x
new file mode 100644
index 0000000..1403740
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint.x
@@ -0,0 +1,66 @@
+extern GPF SUFFIX(trunc) (GPF);
+extern GPF SUFFIX(ceil) (GPF);
+extern GPF SUFFIX(floor) (GPF);
+extern GPF SUFFIX(nearbyint) (GPF);
+extern GPF SUFFIX(rint) (GPF);
+extern GPF SUFFIX(round) (GPF);
+
+GPF test1a (GPF x)
+{
+ return SUFFIX(__builtin_trunc)(x);
+}
+
+GPF test1b (GPF x)
+{
+ return SUFFIX(trunc)(x);
+}
+
+GPF test2a (GPF x)
+{
+ return SUFFIX(__builtin_ceil)(x);
+}
+
+GPF test2b (GPF x)
+{
+ return SUFFIX(ceil)(x);
+}
+
+GPF test3a (GPF x)
+{
+ return SUFFIX(__builtin_floor)(x);
+}
+
+GPF test3b (GPF x)
+{
+ return SUFFIX(floor)(x);
+}
+
+GPF test4a (GPF x)
+{
+ return SUFFIX(__builtin_nearbyint)(x);
+}
+
+GPF test4b (GPF x)
+{
+ return SUFFIX(nearbyint)(x);
+}
+
+GPF test5a (GPF x)
+{
+ return SUFFIX(__builtin_rint)(x);
+}
+
+GPF test5b (GPF x)
+{
+ return SUFFIX(rint)(x);
+}
+
+GPF test6a (GPF x)
+{
+ return SUFFIX(__builtin_round)(x);
+}
+
+GPF test6b (GPF x)
+{
+ return SUFFIX(round)(x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint_double.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint_double.c
new file mode 100644
index 0000000..9613949
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint_double.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF double
+#define SUFFIX(x) x
+
+#include "frint.x"
+
+/* { dg-final { scan-assembler-times "frintz\td\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frintp\td\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frintm\td\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frinti\td\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frintx\td\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frinta\td\[0-9\]" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint_float.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint_float.c
new file mode 100644
index 0000000..493ec37
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint_float.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF float
+#define SUFFIX(x) x##f
+
+#include "frint.x"
+
+/* { dg-final { scan-assembler-times "frintz\ts\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frintp\ts\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frintm\ts\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frinti\ts\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frintx\ts\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frinta\ts\[0-9\]" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/index.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/index.c
new file mode 100644
index 0000000..582771b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/index.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "\[us\]xtw\t" } } */
+/* { dg-final { scan-assembler-not "\[us\]bfiz\t" } } */
+/* { dg-final { scan-assembler-not "lsl\t" } } */
+
+int
+load_scaled_sxtw (int *arr, int i)
+{
+ return arr[arr[i]];
+}
+
+unsigned int
+load_scaled_uxtw (unsigned int *arr, unsigned int i)
+{
+ return arr[arr[i]];
+}
+
+void
+store_scaled_sxtw (int *arr, int i)
+{
+ arr[arr[i]] = 0;
+}
+
+void
+store_scaled_uxtw (unsigned int *arr, unsigned int i)
+{
+ arr[arr[i]] = 0;
+}
+
+int
+load_unscaled_sxtw (signed char *arr, int i)
+{
+ return arr[arr[i]];
+}
+
+unsigned int
+load_unscaled_uxtw (unsigned char *arr, unsigned int i)
+{
+ return arr[arr[i]];
+}
+
+void
+store_unscaled_sxtw (signed char *arr, int i)
+{
+ arr[arr[i]] = 0;
+}
+
+void
+store_unscaled_uxtw (unsigned char *arr, unsigned int i)
+{
+ arr[arr[i]] = 0;
+}
+
+
+
+int
+load_scaled_tmp_sxtw (int *arr, int i)
+{
+ int j = arr[i];
+ return arr[j];
+}
+
+unsigned int
+load_scaled_tmp_uxtw (unsigned int *arr, unsigned int i)
+{
+ unsigned int j = arr[i];
+ return arr[j];
+}
+
+void
+store_scaled_tmp_sxtw (int *arr, int i)
+{
+ int j = arr[i];
+ arr[j] = 0;
+}
+
+void
+store_scaled_tmp_uxtw (unsigned int *arr, unsigned int i)
+{
+ unsigned int j = arr[i];
+ arr[j] = 0;
+}
+
+int
+load_unscaled_tmp_sxtw (signed char *arr, int i)
+{
+ signed char j = arr[i];
+ return arr[j];
+}
+
+unsigned int
+load_unscaled_tmp_uxtw (unsigned char *arr, unsigned int i)
+{
+ unsigned char j = arr[i];
+ return arr[j];
+}
+
+void
+store_unscaled_tmp_sxtw (signed char *arr, int i)
+{
+ signed char j = arr[i];
+ arr[j] = 0;
+}
+
+void
+store_unscaled_tmp_uxtw (unsigned char *arr, unsigned int i)
+{
+ unsigned char j = arr[i];
+ arr[j] = 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/insv_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/insv_1.c
new file mode 100644
index 0000000..6e3c7f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/insv_1.c
@@ -0,0 +1,85 @@
+/* { dg-do run { target aarch64*-*-* } } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+/* { dg-require-effective-target aarch64_little_endian } */
+
+extern void abort (void);
+
+typedef struct bitfield
+{
+ unsigned short eight: 8;
+ unsigned short four: 4;
+ unsigned short five: 5;
+ unsigned short seven: 7;
+ unsigned int sixteen: 16;
+} bitfield;
+
+bitfield
+bfi1 (bitfield a)
+{
+ /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 0, 8" } } */
+ a.eight = 3;
+ return a;
+}
+
+bitfield
+bfi2 (bitfield a)
+{
+ /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 16, 5" } } */
+ a.five = 7;
+ return a;
+}
+
+bitfield
+movk (bitfield a)
+{
+ /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x1d6b, lsl 32" } } */
+ a.sixteen = 7531;
+ return a;
+}
+
+bitfield
+set1 (bitfield a)
+{
+ /* { dg-final { scan-assembler "orr\tx\[0-9\]+, x\[0-9\]+, 2031616" } } */
+ a.five = 0x1f;
+ return a;
+}
+
+bitfield
+set0 (bitfield a)
+{
+ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -2031617" } } */
+ a.five = 0;
+ return a;
+}
+
+
+int
+main (int argc, char** argv)
+{
+ static bitfield a;
+ bitfield b = bfi1 (a);
+ bitfield c = bfi2 (b);
+ bitfield d = movk (c);
+
+ if (d.eight != 3)
+ abort ();
+
+ if (d.five != 7)
+ abort ();
+
+ if (d.sixteen != 7531)
+ abort ();
+
+ d = set1 (d);
+ if (d.five != 0x1f)
+ abort ();
+
+ d = set0 (d);
+ if (d.five != 0)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/insv_2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/insv_2.c
new file mode 100644
index 0000000..a7691a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/insv_2.c
@@ -0,0 +1,85 @@
+/* { dg-do run { target aarch64*-*-* } } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+/* { dg-require-effective-target aarch64_big_endian } */
+
+extern void abort (void);
+
+typedef struct bitfield
+{
+ unsigned short eight: 8;
+ unsigned short four: 4;
+ unsigned short five: 5;
+ unsigned short seven: 7;
+ unsigned int sixteen: 16;
+} bitfield;
+
+bitfield
+bfi1 (bitfield a)
+{
+ /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 56, 8" } } */
+ a.eight = 3;
+ return a;
+}
+
+bitfield
+bfi2 (bitfield a)
+{
+ /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 43, 5" } } */
+ a.five = 7;
+ return a;
+}
+
+bitfield
+movk (bitfield a)
+{
+ /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x1d6b, lsl 16" } } */
+ a.sixteen = 7531;
+ return a;
+}
+
+bitfield
+set1 (bitfield a)
+{
+ /* { dg-final { scan-assembler "orr\tx\[0-9\]+, x\[0-9\]+, 272678883688448" } } */
+ a.five = 0x1f;
+ return a;
+}
+
+bitfield
+set0 (bitfield a)
+{
+ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -272678883688449" } } */
+ a.five = 0;
+ return a;
+}
+
+
+int
+main (int argc, char** argv)
+{
+ static bitfield a;
+ bitfield b = bfi1 (a);
+ bitfield c = bfi2 (b);
+ bitfield d = movk (c);
+
+ if (d.eight != 3)
+ abort ();
+
+ if (d.five != 7)
+ abort ();
+
+ if (d.sixteen != 7531)
+ abort ();
+
+ d = set1 (d);
+ if (d.five != 0x1f)
+ abort ();
+
+ d = set0 (d);
+ if (d.five != 0)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c
new file mode 100644
index 0000000..fce4138
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c
@@ -0,0 +1,84 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+
+#define MAPs(size, xx) int##size##xx##_t
+#define MAPu(size, xx) uint##size##xx##_t
+
+
+#define TEST_VMLA(q, su, size, in1_lanes, in2_lanes) \
+static void \
+test_vmlaq_lane##q##_##su##size (MAP##su (size, ) * res, \
+ const MAP##su(size, ) *in1, \
+ const MAP##su(size, ) *in2) \
+{ \
+ MAP##su (size, x##in1_lanes) a = vld1q_##su##size (res); \
+ MAP##su (size, x##in1_lanes) b = vld1q_##su##size (in1); \
+ MAP##su (size, x##in2_lanes) c = vld1##q##_##su##size (in2); \
+ a = vmlaq_lane##q##_##su##size (a, b, c, 1); \
+ vst1q_##su##size (res, a); \
+}
+
+#define BUILD_VARS(width, n_lanes, n_half_lanes) \
+TEST_VMLA (, s, width, n_lanes, n_half_lanes) \
+TEST_VMLA (q, s, width, n_lanes, n_lanes) \
+TEST_VMLA (, u, width, n_lanes, n_half_lanes) \
+TEST_VMLA (q, u, width, n_lanes, n_lanes) \
+
+BUILD_VARS (32, 4, 2)
+BUILD_VARS (16, 8, 4)
+
+#define POOL4 {0, 1, 2, 3}
+#define POOL8 {0, 1, 2, 3, 4, 5, 6, 7}
+#define EMPTY4 {0, 0, 0, 0}
+#define EMPTY8 {0, 0, 0, 0, 0, 0, 0, 0}
+
+#define BUILD_TEST(su, size, lanes) \
+static void \
+test_##su##size (void) \
+{ \
+ int i; \
+ MAP##su (size,) pool[lanes] = POOL##lanes; \
+ MAP##su (size,) res[lanes] = EMPTY##lanes; \
+ MAP##su (size,) res2[lanes] = EMPTY##lanes; \
+ \
+ /* Forecfully avoid optimization. */ \
+ asm volatile ("" : : : "memory"); \
+ test_vmlaq_lane_##su##size (res, pool, pool); \
+ for (i = 0; i < lanes; i++) \
+ if (res[i] != pool[i]) \
+ abort (); \
+ \
+ /* Forecfully avoid optimization. */ \
+ asm volatile ("" : : : "memory"); \
+ test_vmlaq_laneq_##su##size (res2, pool, pool); \
+ for (i = 0; i < lanes; i++) \
+ if (res2[i] != pool[i]) \
+ abort (); \
+}
+
+#undef BUILD_VARS
+#define BUILD_VARS(size, lanes) \
+BUILD_TEST (s, size, lanes) \
+BUILD_TEST (u, size, lanes)
+
+BUILD_VARS (32, 4)
+BUILD_VARS (16, 8)
+
+int
+main (int argc, char **argv)
+{
+ test_s32 ();
+ test_u32 ();
+ test_s16 ();
+ test_u16 ();
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c
new file mode 100644
index 0000000..8bf95b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c
@@ -0,0 +1,89 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+
+#define MAPs(size, xx) int##size##xx##_t
+#define MAPu(size, xx) uint##size##xx##_t
+
+
+#define TEST_VMLS(q, su, size, in1_lanes, in2_lanes) \
+static void \
+test_vmlsq_lane##q##_##su##size (MAP##su (size, ) * res, \
+ const MAP##su(size, ) *in1, \
+ const MAP##su(size, ) *in2) \
+{ \
+ MAP##su (size, x##in1_lanes) a = vld1q_##su##size (res); \
+ MAP##su (size, x##in1_lanes) b = vld1q_##su##size (in1); \
+ MAP##su (size, x##in2_lanes) c = vld1##q##_##su##size (in2); \
+ a = vmlsq_lane##q##_##su##size (a, b, c, 1); \
+ vst1q_##su##size (res, a); \
+}
+
+#define BUILD_VARS(width, n_lanes, n_half_lanes) \
+TEST_VMLS (, s, width, n_lanes, n_half_lanes) \
+TEST_VMLS (q, s, width, n_lanes, n_lanes) \
+TEST_VMLS (, u, width, n_lanes, n_half_lanes) \
+TEST_VMLS (q, u, width, n_lanes, n_lanes) \
+
+BUILD_VARS (32, 4, 2)
+BUILD_VARS (16, 8, 4)
+
+#define MAP_OPs +
+#define MAP_OPu -
+
+#define POOL4 {0, 1, 2, 3}
+#define POOL8 {0, 1, 2, 3, 4, 5, 6, 7}
+#define EMPTY4s {0, 0, 0, 0}
+#define EMPTY8s {0, 0, 0, 0, 0, 0, 0, 0}
+#define EMPTY4u {0, 2, 4, 6}
+#define EMPTY8u {0, 2, 4, 6, 8, 10, 12, 14}
+
+#define BUILD_TEST(su, size, lanes) \
+static void \
+test_##su##size (void) \
+{ \
+ int i; \
+ MAP##su (size,) pool[lanes] = POOL##lanes; \
+ MAP##su (size,) res[lanes] = EMPTY##lanes##su; \
+ MAP##su (size,) res2[lanes] = EMPTY##lanes##su; \
+ \
+ /* Forecfully avoid optimization. */ \
+ asm volatile ("" : : : "memory"); \
+ test_vmlsq_lane_##su##size (res, pool, pool); \
+ for (i = 0; i < lanes; i++) \
+ if (res[i] MAP_OP##su pool[i] != 0) \
+ abort (); \
+ \
+ /* Forecfully avoid optimization. */ \
+ asm volatile ("" : : : "memory"); \
+ test_vmlsq_laneq_##su##size (res2, pool, pool); \
+ for (i = 0; i < lanes; i++) \
+ if (res2[i] MAP_OP##su pool[i] != 0) \
+ abort (); \
+}
+
+#undef BUILD_VARS
+#define BUILD_VARS(size, lanes) \
+BUILD_TEST (s, size, lanes) \
+BUILD_TEST (u, size, lanes)
+
+BUILD_VARS (32, 4)
+BUILD_VARS (16, 8)
+
+int
+main (int argc, char **argv)
+{
+ test_s32 ();
+ test_u32 ();
+ test_s16 ();
+ test_u16 ();
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-1.c
new file mode 100644
index 0000000..618854a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int r;
+
+void test (int a, int b)
+{
+ /* { dg-final { scan-assembler "mneg\tw\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+ r = (-a) * b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-2.c
new file mode 100644
index 0000000..25f817b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int r;
+
+void test (int a, int b)
+{
+ /* { dg-final { scan-assembler "mneg\tw\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+ r = a * (-b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-3.c
new file mode 100644
index 0000000..d9a1354
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int r;
+
+void test (int a, int b)
+{
+ /* { dg-final { scan-assembler "mneg\tw\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+ r = - (a * b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mnegl-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mnegl-1.c
new file mode 100644
index 0000000..b45debb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mnegl-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+long long r;
+
+void test_signed (int a, int b)
+{
+ /* { dg-final { scan-assembler "smnegl\tx\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+ r = (-((long long) a)) * ((long long) b);
+}
+
+void test_unsigned (unsigned int a, unsigned int b)
+{
+ /* { dg-final { scan-assembler "umnegl\tx\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+ r = (-((long long) a)) * ((long long) b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mnegl-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mnegl-2.c
new file mode 100644
index 0000000..1c5dc75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mnegl-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+long long r;
+
+void test_signed (int a, int b)
+{
+ /* { dg-final { scan-assembler "smnegl\tx\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+ r = ((long long) a) * (-((long long) b));
+}
+
+void test_unsigned (unsigned int a, unsigned int b)
+{
+ /* { dg-final { scan-assembler "umnegl\tx\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+ r = ((long long) a) * (-((long long) b));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movdi_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movdi_1.c
new file mode 100644
index 0000000..a22378d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movdi_1.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-inline" } */
+
+#include <arm_neon.h>
+
+void
+foo1 (uint64_t *a)
+{
+ uint64x1_t val18;
+ uint32x2_t val19;
+ uint64x1_t val20;
+ val19 = vcreate_u32 (0x800000004cf3dffbUL);
+ val20 = vrsra_n_u64 (val18, vreinterpret_u64_u32 (val19), 34);
+ vst1_u64 (a, val20);
+}
+
+void
+foo2 (uint64_t *a)
+{
+ uint64x1_t val18;
+ uint32x2_t val19;
+ uint64x1_t val20;
+ val19 = vcreate_u32 (0xdffbUL);
+ val20 = vrsra_n_u64 (val18, vreinterpret_u64_u32 (val19), 34);
+ vst1_u64 (a, val20);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movi_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movi_1.c
new file mode 100644
index 0000000..e2842b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movi_1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+dummy (short* b)
+{
+ /* { dg-final { scan-assembler "movi\tv\[0-9\]+\.4h, 0x4, lsl 8" } } */
+ /* { dg-final { scan-assembler-not "movi\tv\[0-9\]+\.4h, 0x400" } } */
+ /* { dg-final { scan-assembler-not "movi\tv\[0-9\]+\.4h, 1024" } } */
+ register short x asm ("h8") = 1024;
+ asm volatile ("" : : "w" (x));
+ *b = x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movk.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movk.c
new file mode 100644
index 0000000..e4b2209
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movk.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+long long int
+dummy_number_generator ()
+{
+ /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0xefff, lsl 16" } } */
+ /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0xc4cc, lsl 32" } } */
+ /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0xfffe, lsl 48" } } */
+ return -346565474575675;
+}
+
+int
+main (void)
+{
+
+ long long int num = dummy_number_generator ();
+ if (num > 0)
+ abort ();
+
+ /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x4667, lsl 16" } } */
+ /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x7a3d, lsl 32" } } */
+ if (num / 69313094915135 != -5)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mul_intrinsic_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mul_intrinsic_1.c
new file mode 100644
index 0000000..dabe10e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mul_intrinsic_1.c
@@ -0,0 +1,83 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+
+#define MAPs(size, xx) int##size##xx##_t
+#define MAPu(size, xx) uint##size##xx##_t
+
+
+#define TEST_VMUL(q, su, size, in1_lanes, in2_lanes) \
+static void \
+test_vmulq_lane##q##_##su##size (MAP##su (size, ) * res, \
+ const MAP##su(size, ) *in1, \
+ const MAP##su(size, ) *in2) \
+{ \
+ MAP##su (size, x##in1_lanes) a = vld1q_##su##size (in1); \
+ MAP##su (size, x##in2_lanes) b = vld1##q##_##su##size (in2); \
+ a = vmulq_lane##q##_##su##size (a, b, 1); \
+ vst1q_##su##size (res, a); \
+}
+
+#define BUILD_VARS(width, n_lanes, n_half_lanes) \
+TEST_VMUL (, s, width, n_lanes, n_half_lanes) \
+TEST_VMUL (q, s, width, n_lanes, n_lanes) \
+TEST_VMUL (, u, width, n_lanes, n_half_lanes) \
+TEST_VMUL (q, u, width, n_lanes, n_lanes) \
+
+BUILD_VARS (32, 4, 2)
+BUILD_VARS (16, 8, 4)
+
+#define POOL4 {0, 1, 2, 3}
+#define POOL8 {0, 1, 2, 3, 4, 5, 6, 7}
+#define EMPTY4 {0, 0, 0, 0}
+#define EMPTY8 {0, 0, 0, 0, 0, 0, 0, 0}
+
+#define BUILD_TEST(su, size, lanes) \
+static void \
+test_##su##size (void) \
+{ \
+ int i; \
+ MAP##su (size,) pool[lanes] = POOL##lanes; \
+ MAP##su (size,) res[lanes] = EMPTY##lanes; \
+ MAP##su (size,) res2[lanes] = EMPTY##lanes; \
+ \
+ /* Forecfully avoid optimization. */ \
+ asm volatile ("" : : : "memory"); \
+ test_vmulq_lane_##su##size (res, pool, pool); \
+ for (i = 0; i < lanes; i++) \
+ if (res[i] != pool[i]) \
+ abort (); \
+ \
+ /* Forecfully avoid optimization. */ \
+ asm volatile ("" : : : "memory"); \
+ test_vmulq_laneq_##su##size (res2, pool, pool); \
+ for (i = 0; i < lanes; i++) \
+ if (res2[i] != pool[i]) \
+ abort (); \
+}
+
+#undef BUILD_VARS
+#define BUILD_VARS(size, lanes) \
+BUILD_TEST (s, size, lanes) \
+BUILD_TEST (u, size, lanes)
+
+BUILD_VARS (32, 4)
+BUILD_VARS (16, 8)
+
+int
+main (int argc, char **argv)
+{
+ test_s32 ();
+ test_u32 ();
+ test_s16 ();
+ test_u16 ();
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "mul\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "mul\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.h\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/narrow_high-intrinsics.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/narrow_high-intrinsics.c
new file mode 100644
index 0000000..0f23cc9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/narrow_high-intrinsics.c
@@ -0,0 +1,125 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#include "arm_neon.h"
+
+#define TWO(name, rettype, rmwtype, intype, fs) \
+ rettype test_ ## name ## _ ## fs \
+ (rmwtype a, intype b, intype c) \
+ { \
+ return name ## _ ## fs (a, b, c); \
+ }
+
+TWO (vsubhn_high, int8x16_t, int8x8_t, int16x8_t, s16)
+TWO (vsubhn_high, int16x8_t, int16x4_t, int32x4_t, s32)
+TWO (vsubhn_high, int32x4_t, int32x2_t, int64x2_t, s64)
+TWO (vsubhn_high, uint8x16_t, uint8x8_t, uint16x8_t, u16)
+TWO (vsubhn_high, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWO (vsubhn_high, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+TWO (vaddhn_high, int8x16_t, int8x8_t, int16x8_t, s16)
+TWO (vaddhn_high, int16x8_t, int16x4_t, int32x4_t, s32)
+TWO (vaddhn_high, int32x4_t, int32x2_t, int64x2_t, s64)
+TWO (vaddhn_high, uint8x16_t, uint8x8_t, uint16x8_t, u16)
+TWO (vaddhn_high, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWO (vaddhn_high, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+TWO (vrsubhn_high, int8x16_t, int8x8_t, int16x8_t, s16)
+TWO (vrsubhn_high, int16x8_t, int16x4_t, int32x4_t, s32)
+TWO (vrsubhn_high, int32x4_t, int32x2_t, int64x2_t, s64)
+TWO (vrsubhn_high, uint8x16_t, uint8x8_t, uint16x8_t, u16)
+TWO (vrsubhn_high, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWO (vrsubhn_high, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+TWO (vraddhn_high, int8x16_t, int8x8_t, int16x8_t, s16)
+TWO (vraddhn_high, int16x8_t, int16x4_t, int32x4_t, s32)
+TWO (vraddhn_high, int32x4_t, int32x2_t, int64x2_t, s64)
+TWO (vraddhn_high, uint8x16_t, uint8x8_t, uint16x8_t, u16)
+TWO (vraddhn_high, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWO (vraddhn_high, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+#define TWOn(name, rettype, rmwtype, intype, fs) \
+ rettype test_ ## name ## _ ## fs \
+ (rmwtype a, intype b) \
+ { \
+ return name ## _ ## fs (a, b, 4); \
+ }
+
+TWOn (vrshrn_high_n, int8x16_t, int8x8_t, int16x8_t, s16)
+TWOn (vrshrn_high_n, int16x8_t, int16x4_t, int32x4_t, s32)
+TWOn (vrshrn_high_n, int32x4_t, int32x2_t, int64x2_t, s64)
+TWOn (vrshrn_high_n, uint8x16_t, uint8x8_t, uint16x8_t, u16)
+TWOn (vrshrn_high_n, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWOn (vrshrn_high_n, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+TWOn (vshrn_high_n, int8x16_t, int8x8_t, int16x8_t, s16)
+TWOn (vshrn_high_n, int16x8_t, int16x4_t, int32x4_t, s32)
+TWOn (vshrn_high_n, int32x4_t, int32x2_t, int64x2_t, s64)
+TWOn (vshrn_high_n, uint8x16_t, uint8x8_t, uint16x8_t, u16)
+TWOn (vshrn_high_n, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWOn (vshrn_high_n, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+TWOn (vqshrun_high_n, uint8x16_t, uint8x8_t, int16x8_t, s16)
+TWOn (vqshrun_high_n, uint16x8_t, uint16x4_t, int32x4_t, s32)
+TWOn (vqshrun_high_n, uint32x4_t, uint32x2_t, int64x2_t, s64)
+
+TWOn (vqrshrun_high_n, uint8x16_t, uint8x8_t, int16x8_t, s16)
+TWOn (vqrshrun_high_n, uint16x8_t, uint16x4_t, int32x4_t, s32)
+TWOn (vqrshrun_high_n, uint32x4_t, uint32x2_t, int64x2_t, s64)
+
+TWOn (vqshrn_high_n, int8x16_t, int8x8_t, int16x8_t, s16)
+TWOn (vqshrn_high_n, int16x8_t, int16x4_t, int32x4_t, s32)
+TWOn (vqshrn_high_n, int32x4_t, int32x2_t, int64x2_t, s64)
+TWOn (vqshrn_high_n, uint8x16_t, uint8x8_t, uint16x8_t, u16)
+TWOn (vqshrn_high_n, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWOn (vqshrn_high_n, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+TWOn (vqrshrn_high_n, int8x16_t, int8x8_t, int16x8_t, s16)
+TWOn (vqrshrn_high_n, int16x8_t, int16x4_t, int32x4_t, s32)
+TWOn (vqrshrn_high_n, int32x4_t, int32x2_t, int64x2_t, s64)
+TWOn (vqrshrn_high_n, uint8x16_t, uint8x8_t, uint16x8_t, u16)
+TWOn (vqrshrn_high_n, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWOn (vqrshrn_high_n, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+#define ONE(name, rettype, rmwtype, intype, fs) \
+ rettype test_ ## name ## _ ## fs \
+ (rmwtype a, intype b) \
+ { \
+ return name ## _ ## fs (a, b); \
+ }
+
+ONE (vqmovn_high, int8x16_t, int8x8_t, int16x8_t, s16)
+ONE (vqmovn_high, int16x8_t, int16x4_t, int32x4_t, s32)
+ONE (vqmovn_high, int32x4_t, int32x2_t, int64x2_t, s64)
+ONE (vqmovn_high, uint8x16_t, uint8x8_t, uint16x8_t, u16)
+ONE (vqmovn_high, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+ONE (vqmovn_high, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+ONE (vqmovun_high, uint8x16_t, uint8x8_t, int16x8_t, s16)
+ONE (vqmovun_high, uint16x8_t, uint16x4_t, int32x4_t, s32)
+ONE (vqmovun_high, uint32x4_t, uint32x2_t, int64x2_t, s64)
+
+ONE (vmovn_high, int8x16_t, int8x8_t, int16x8_t, s16)
+ONE (vmovn_high, int16x8_t, int16x4_t, int32x4_t, s32)
+ONE (vmovn_high, int32x4_t, int32x2_t, int64x2_t, s64)
+ONE (vmovn_high, uint8x16_t, uint8x8_t, uint16x8_t, u16)
+ONE (vmovn_high, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+ONE (vmovn_high, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+
+/* { dg-final { scan-assembler-times "\\tsubhn2 v" 6} } */
+/* { dg-final { scan-assembler-times "\\taddhn2\\tv" 6} } */
+/* { dg-final { scan-assembler-times "rsubhn2 v" 6} } */
+/* { dg-final { scan-assembler-times "raddhn2\\tv" 6} } */
+/* { dg-final { scan-assembler-times "\\trshrn2 v" 6} } */
+/* { dg-final { scan-assembler-times "\\tshrn2 v" 6} } */
+/* { dg-final { scan-assembler-times "sqshrun2 v" 3} } */
+/* { dg-final { scan-assembler-times "sqrshrun2 v" 3} } */
+/* { dg-final { scan-assembler-times "sqshrn2 v" 3} } */
+/* { dg-final { scan-assembler-times "uqshrn2 v" 3} } */
+/* { dg-final { scan-assembler-times "sqrshrn2 v" 3} } */
+/* { dg-final { scan-assembler-times "uqrshrn2 v" 3} } */
+/* { dg-final { scan-assembler-times "uqxtn2 v" 3} } */
+/* { dg-final { scan-assembler-times "sqxtn2 v" 3} } */
+/* { dg-final { scan-assembler-times "sqxtun2 v" 3} } */
+/* { dg-final { scan-assembler-times "\\txtn2 v" 6} } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/neg_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/neg_1.c
new file mode 100644
index 0000000..04b0fdd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/neg_1.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-inline --save-temps" } */
+
+extern void abort (void);
+
+long long
+neg64 (long long a)
+{
+ /* { dg-final { scan-assembler "neg\tx\[0-9\]+" } } */
+ return 0 - a;
+}
+
+long long
+neg64_in_dreg (long long a)
+{
+ /* { dg-final { scan-assembler "neg\td\[0-9\]+, d\[0-9\]+" } } */
+ register long long x asm ("d8") = a;
+ register long long y asm ("d9");
+ asm volatile ("" : : "w" (x));
+ y = 0 - x;
+ asm volatile ("" : : "w" (y));
+ return y;
+}
+
+int
+neg32 (int a)
+{
+ /* { dg-final { scan-assembler "neg\tw\[0-9\]+" } } */
+ return 0 - a;
+}
+
+int
+neg32_in_sreg (int a)
+{
+ /* { dg-final { scan-assembler "neg\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+ register int x asm ("s8") = a;
+ register int y asm ("s9");
+ asm volatile ("" : : "w" (x));
+ y = 0 - x;
+ asm volatile ("" : : "w" (y));
+ return y;
+}
+
+int
+main (void)
+{
+ long long a;
+ int b;
+ a = 61;
+ b = 313;
+
+ if (neg64 (a) != -61)
+ abort ();
+
+ if (neg64_in_dreg (a) != -61)
+ abort ();
+
+ if (neg32 (b) != -313)
+ abort ();
+
+ if (neg32_in_sreg (b) != -313)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/negs.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/negs.c
new file mode 100644
index 0000000..1c23041
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/negs.c
@@ -0,0 +1,108 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+int z;
+
+int
+negs_si_test1 (int a, int b, int c)
+{
+ int d = -b;
+
+ /* { dg-final { scan-assembler "negs\tw\[0-9\]+, w\[0-9\]+" } } */
+ if (d < 0)
+ return a + c;
+
+ z = d;
+ return b + c + d;
+}
+
+int
+negs_si_test3 (int a, int b, int c)
+{
+ int d = -(b) << 3;
+
+ /* { dg-final { scan-assembler "negs\tw\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ if (d == 0)
+ return a + c;
+
+ z = d;
+ return b + c + d;
+}
+
+typedef long long s64;
+s64 zz;
+
+s64
+negs_di_test1 (s64 a, s64 b, s64 c)
+{
+ s64 d = -b;
+
+ /* { dg-final { scan-assembler "negs\tx\[0-9\]+, x\[0-9\]+" } } */
+ if (d < 0)
+ return a + c;
+
+ zz = d;
+ return b + c + d;
+}
+
+s64
+negs_di_test3 (s64 a, s64 b, s64 c)
+{
+ s64 d = -(b) << 3;
+
+ /* { dg-final { scan-assembler "negs\tx\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ if (d == 0)
+ return a + c;
+
+ zz = d;
+ return b + c + d;
+}
+
+int main ()
+{
+ int x;
+ s64 y;
+
+ x = negs_si_test1 (2, 12, 5);
+ if (x != 7)
+ abort ();
+
+ x = negs_si_test1 (1, 2, 32);
+ if (x != 33)
+ abort ();
+
+ x = negs_si_test3 (13, 14, 5);
+ if (x != -93)
+ abort ();
+
+ x = negs_si_test3 (15, 21, 2);
+ if (x != -145)
+ abort ();
+
+ y = negs_di_test1 (0x20202020ll,
+ 0x65161611ll,
+ 0x42434243ll);
+ if (y != 0x62636263ll)
+ abort ();
+
+ y = negs_di_test1 (0x1010101010101ll,
+ 0x123456789abcdll,
+ 0x5555555555555ll);
+ if (y != 0x6565656565656ll)
+ abort ();
+
+ y = negs_di_test3 (0x62523781ll,
+ 0x64234978ll,
+ 0x12345123ll);
+ if (y != 0xfffffffd553d4edbll)
+ abort ();
+
+ y = negs_di_test3 (0x763526268ll,
+ 0x101010101ll,
+ 0x222222222ll);
+ if (y != 0xfffffffb1b1b1b1bll)
+ abort ();
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ngc.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ngc.c
new file mode 100644
index 0000000..3364321
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ngc.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+typedef unsigned int u32;
+
+u32
+ngc_si (u32 a, u32 b, u32 c, u32 d)
+{
+ a = -b - (c < d);
+ return a;
+}
+
+typedef unsigned long long u64;
+
+u64
+ngc_si_tst (u64 a, u32 b, u32 c, u32 d)
+{
+ a = -b - (c < d);
+ return a;
+}
+
+u64
+ngc_di (u64 a, u64 b, u64 c, u64 d)
+{
+ a = -b - (c < d);
+ return a;
+}
+
+int
+main ()
+{
+ int x;
+ u64 y;
+
+ x = ngc_si (29, 4, 5, 4);
+ if (x != -4)
+ abort ();
+
+ x = ngc_si (1024, 2, 20, 13);
+ if (x != -2)
+ abort ();
+
+ y = ngc_si_tst (0x130000029ll, 32, 50, 12);
+ if (y != 0xffffffe0)
+ abort ();
+
+ y = ngc_si_tst (0x5000500050005ll, 21, 2, 14);
+ if (y != 0xffffffea)
+ abort ();
+
+ y = ngc_di (0x130000029ll, 0x320000004ll, 0x505050505ll, 0x123123123ll);
+ if (y != 0xfffffffcdffffffc)
+ abort ();
+
+ y = ngc_di (0x5000500050005ll,
+ 0x2111211121112ll, 0x0000000002020ll, 0x1414575046477ll);
+ if (y != 0xfffdeeedeeedeeed)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "ngc\tw\[0-9\]+, w\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler-times "ngc\tx\[0-9\]+, x\[0-9\]+" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pic-constantpool1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pic-constantpool1.c
new file mode 100644
index 0000000..3109d9d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pic-constantpool1.c
@@ -0,0 +1,30 @@
+/* { dg-options "-O2 -mcmodel=small -fPIC" } */
+/* { dg-do compile } */
+
+extern int __finite (double __value) __attribute__ ((__nothrow__)) __attribute__ ((__const__));
+int
+__ecvt_r (value, ndigit, decpt, sign, buf, len)
+ double value;
+ int ndigit, *decpt, *sign;
+ char *buf;
+{
+ if ((sizeof (value) == sizeof (float) ? __finitef (value) : __finite (value)) && value != 0.0)
+ {
+ double d;
+ double f = 1.0;
+ d = -value;
+ if (d < 1.0e-307)
+ {
+ do
+ {
+ f *= 10.0;
+ }
+ while (d * f < 1.0);
+ }
+ }
+ if (ndigit <= 0 && len > 0)
+ {
+ buf[0] = '\0';
+ *sign = (sizeof (value) == sizeof (float) ? __finitef (value) : __finite (value)) ? (sizeof (value) == sizeof (float) ? __signbitf (value) : __signbit (value)) != 0 : 0;
+ }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pic-symrefplus.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pic-symrefplus.c
new file mode 100644
index 0000000..f277a52
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pic-symrefplus.c
@@ -0,0 +1,128 @@
+/* { dg-options "-O2 -mcmodel=small -fPIC -fno-builtin" } */
+/* { dg-do compile } */
+
+typedef long unsigned int size_t;
+enum
+{
+ __LC_TIME = 2,
+};
+enum
+{
+ ABDAY_1 = (((__LC_TIME) << 16) | (0)),
+ DAY_1,
+ ABMON_1,
+ MON_1,
+ D_T_FMT,
+};
+typedef struct __locale_struct
+{
+ struct locale_data *__locales[13];
+} *__locale_t;
+struct tm
+{
+ int tm_sec;
+ int tm_min;
+ int tm_hour;
+};
+struct locale_data
+{
+ const char *name;
+ struct
+ {
+ const char *string;
+ }
+ values [];
+};
+extern const struct locale_data _nl_C_LC_TIME __attribute__ ((visibility ("hidden")));
+char *
+__strptime_internal (rp, fmt, tmp, statep , locale)
+ const char *rp;
+ const char *fmt;
+ __locale_t locale;
+ void *statep;
+{
+ struct locale_data *const current = locale->__locales[__LC_TIME];
+ const char *rp_backup;
+ const char *rp_longest;
+ int cnt;
+ size_t val;
+ enum ptime_locale_status { not, loc, raw } decided_longest;
+ struct __strptime_state
+ {
+ enum ptime_locale_status decided : 2;
+ } s;
+ struct tm tmb;
+ struct tm *tm;
+ if (statep == ((void *)0))
+ {
+ memset (&s, 0, sizeof (s));
+ }
+ {
+ tm = &tmb;
+ }
+ while (*fmt != '\0')
+ {
+ if (*fmt != '%')
+ {
+ if (*fmt++ != *rp++) return ((void *)0);
+ continue;
+ }
+ if (statep != ((void *)0))
+ {
+ ++fmt;
+ }
+ rp_backup = rp;
+ switch (*fmt++)
+ {
+ case '%':
+ for (cnt = 0; cnt < 7; ++cnt)
+ {
+ const char *trp;
+ if (s.decided !=raw)
+ {
+ if (({ size_t len = strlen ((current->values[((int) (DAY_1 + cnt) & 0xffff)].string)); int result = __strncasecmp_l (((current->values[((int) (DAY_1 + cnt) & 0xffff)].string)), (trp), len, locale) == 0; if (result) (trp) += len; result; })
+ && trp > rp_longest)
+ {
+ }
+ if (({ size_t len = strlen ((current->values[((int) (ABDAY_1 + cnt) & 0xffff)].string)); int result = __strncasecmp_l (((current->values[((int) (ABDAY_1 + cnt) & 0xffff)].string)), (trp), len, locale) == 0; if (result) (trp) += len; result; })
+ && trp > rp_longest)
+ {
+ }
+ }
+ if (s.decided != loc
+ && (((trp = rp, ({ size_t len = strlen ((&_nl_C_LC_TIME.values[((int) (DAY_1) & 0xffff)].string)[cnt]); int result = __strncasecmp_l (((&_nl_C_LC_TIME.values[((int) (DAY_1) & 0xffff)].string)[cnt]), (trp), len, locale) == 0; if (result) (trp) += len; result; }))
+ && trp > rp_longest)
+ || ((trp = rp, ({ size_t len = strlen ((&_nl_C_LC_TIME.values[((int) (ABDAY_1) & 0xffff)].string)[cnt]); int result = __strncasecmp_l (((&_nl_C_LC_TIME.values[((int) (ABDAY_1) & 0xffff)].string)[cnt]), (rp), len, locale) == 0; if (result) (rp) += len; result; }))
+ && trp > rp_longest)))
+ {
+ }
+ }
+ {
+ const char *trp;
+ if (s.decided != loc
+ && (((trp = rp, ({ size_t len = strlen ((&_nl_C_LC_TIME.values[((int) (MON_1) & 0xffff)].string)[cnt]); int result = __strncasecmp_l (((&_nl_C_LC_TIME.values[((int) (MON_1) & 0xffff)].string)[cnt]), (trp), len, locale) == 0; if (result) (trp) += len; result; }))
+ && trp > rp_longest)
+ || ((trp = rp, ({ size_t len = strlen ((&_nl_C_LC_TIME.values[((int) (ABMON_1) & 0xffff)].string)[cnt]); int result = __strncasecmp_l (((&_nl_C_LC_TIME.values[((int) (ABMON_1) & 0xffff)].string)[cnt]), (trp), len, locale) == 0; if (result) (trp) += len; result; }))
+ && trp > rp_longest)))
+ {
+ }
+ }
+ case 'c':
+ {
+ if (!(*((current->values[((int) (D_T_FMT) & 0xffff)].string)) != '\0' && (rp = __strptime_internal (rp, ((current->values[((int) (D_T_FMT) & 0xffff)].string)), tm, &s , locale)) != ((void *)0)))
+ {
+ rp = rp_backup;
+ }
+ }
+ case 'C':
+ do { int __n = 2; val = 0; while (*rp == ' ') ++rp; if (*rp < '0' || *rp > '9') return ((void *)0); do { val *= 10; val += *rp++ - '0'; } while (--__n > 0 && val * 10 <= 99 && *rp >= '0' && *rp <= '9'); if (val < 0 || val > 99) return ((void *)0); } while (0);
+ case 'F':
+ if (!(*("%Y-%m-%d") != '\0' && (rp = __strptime_internal (rp, ("%Y-%m-%d"), tm, &s , locale)) != ((void *)0)))
+ tm->tm_hour = val % 12;
+ }
+ }
+}
+char *
+__strptime_l (buf, format, tm , locale)
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pmull_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pmull_1.c
new file mode 100644
index 0000000..bccaec1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pmull_1.c
@@ -0,0 +1,23 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+crypto" } */
+
+#include "arm_neon.h"
+
+poly128_t
+test_vmull_p64 (poly64_t a, poly64_t b)
+{
+ return vmull_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "pmull\\tv" 1 } } */
+
+poly128_t
+test_vmull_high_p64 (poly64x2_t a, poly64x2_t b)
+{
+ return vmull_high_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "pmull2\\tv" 1 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr58460.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr58460.c
new file mode 100644
index 0000000..a7e149a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr58460.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O" } */
+extern unsigned long x1;
+
+char *
+f (char *a, char *b)
+{
+ return a;
+}
+
+int
+g (char *a)
+{
+ return 2;
+}
+
+void
+h (char *p[])
+{
+ char n[x1][512];
+ char *l = f (p[1], " ");
+ if (g (p[0]))
+ n[0][0] = '\0';
+ while (l && *l)
+ {
+ }
+}
+
+unsigned long x1;
+
+int
+main ()
+{
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_large.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_large.c
new file mode 100644
index 0000000..0d7d4da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_large.c
@@ -0,0 +1,7 @@
+/* { dg-skip-if "Code model already defined" { aarch64_tiny || aarch64_small } } */
+
+#ifdef __AARCH64_CMODEL_LARGE__
+ int dummy;
+#else
+ #error
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_small.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_small.c
new file mode 100644
index 0000000..b136284
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_small.c
@@ -0,0 +1,7 @@
+/* { dg-skip-if "Code model already defined" { aarch64_tiny || aarch64_large } } */
+
+#ifdef __AARCH64_CMODEL_SMALL__
+ int dummy;
+#else
+ #error
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_tiny.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_tiny.c
new file mode 100644
index 0000000..d2c844b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_tiny.c
@@ -0,0 +1,7 @@
+/* { dg-skip-if "Code model already defined" { aarch64_small || aarch64_large } } */
+
+#ifdef __AARCH64_CMODEL_TINY__
+ int dummy;
+#else
+ #error
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c
new file mode 100644
index 0000000..b44e560
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c
@@ -0,0 +1,66 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcmodel=large -fno-builtin" } */
+/* { dg-skip-if "-mcmodel=large -fPIC not currently supported" { aarch64-*-* } { "-fPIC" } { "" } } */
+
+typedef long unsigned int size_t;
+typedef unsigned short int sa_family_t;
+
+struct sockaddr
+{
+ sa_family_t sa_family;
+ char sa_data[14];
+};
+struct arpreq
+{
+ int arp_flags;
+ struct sockaddr arp_netmask;
+};
+typedef struct _IO_FILE FILE;
+extern char *fgets (char *__restrict __s, int __n, FILE *__restrict __stream);
+extern struct _IO_FILE *stderr;
+extern int optind;
+struct aftype {
+ int (*input) (int type, char *bufp, struct sockaddr *);
+};
+struct aftype *ap;
+static int arp_set(char **args)
+{
+ char host[128];
+ struct arpreq req;
+ struct sockaddr sa;
+ memset((char *) &req, 0, sizeof(req));
+ if (*args == ((void *)0)) {
+ fprintf(stderr, ("arp: need host name\n"));
+ }
+ safe_strncpy(host, *args++, (sizeof host));
+ if (ap->input(0, host, &sa) < 0) {
+ }
+ while (*args != ((void *)0)) {
+ if (!__extension__ ({ size_t __s1_len, __s2_len; (__builtin_constant_p (*args) && __builtin_constant_p ("netmask") && (__s1_len = strlen (*args), __s2_len = strlen ("netmask"), (!((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) || __s1_len >= 4) && (!((size_t)(const void *)(("netmask") + 1) - (size_t)(const void *)("netmask") == 1) || __s2_len >= 4)) ? __builtin_strcmp (*args, "netmask") : (__builtin_constant_p (*args) && ((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) && (__s1_len = strlen (*args), __s1_len < 4) ? (__builtin_constant_p ("netmask") && ((size_t)(const void *)(("netmask") + 1) - (size_t)(const void *)("netmask") == 1) ? __builtin_strcmp (*args, "netmask") : (__extension__ ({ __const unsigned char *__s2 = (__const unsigned char *) (__const char *) ("netmask"); register int __result = (((__const unsigned char *) (__const char *) (*args))[0] - __s2[0]); if (__s1_len > 0 && __result == 0) { __result = (((__const unsigned char *) (__const char *) (*args))[1] - __s2[1]); if (__s1_len > 1 && __result == 0) { __result = (((__const unsigned char *) (__const char *) (*args))[2] - __s2[2]); if (__s1_len > 2 && __result == 0) __result = (((__const unsigned char *) (__const char *) (*args))[3] - __s2[3]); } } __result; }))) : (__builtin_constant_p ("netmask") && ((size_t)(const void *)(("netmask") + 1) - (size_t)(const void *)("netmask") == 1) && (__s2_len = strlen ("netmask"), __s2_len < 4) ? (__builtin_constant_p (*args) && ((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) ? __builtin_strcmp (*args, "netmask") : (__extension__ ({ __const unsigned char *__s1 = (__const unsigned char *) (__const char *) (*args); register int __result = __s1[0] - ((__const unsigned char *) (__const char *) ("netmask"))[0]; if (__s2_len > 0 && __result == 0) { __result = (__s1[1] - ((__const unsigned char *) (__const char *) ("netmask"))[1]); if (__s2_len > 1 && __result == 0) { __result = (__s1[2] - ((__const unsigned char *) (__const char *) ("netmask"))[2]); if (__s2_len > 2 && __result == 0) __result = (__s1[3] - ((__const unsigned char *) (__const char *) ("netmask"))[3]); } } __result; }))) : __builtin_strcmp (*args, "netmask")))); })) {
+ if (__extension__ ({ size_t __s1_len, __s2_len; (__builtin_constant_p (*args) && __builtin_constant_p ("255.255.255.255") && (__s1_len = strlen (*args), __s2_len = strlen ("255.255.255.255"), (!((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) || __s1_len >= 4) && (!((size_t)(const void *)(("255.255.255.255") + 1) - (size_t)(const void *)("255.255.255.255") == 1) || __s2_len >= 4)) ? __builtin_strcmp (*args, "255.255.255.255") : (__builtin_constant_p (*args) && ((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) && (__s1_len = strlen (*args), __s1_len < 4) ? (__builtin_constant_p ("255.255.255.255") && ((size_t)(const void *)(("255.255.255.255") + 1) - (size_t)(const void *)("255.255.255.255") == 1) ? __builtin_strcmp (*args, "255.255.255.255") : (__extension__ ({ __const unsigned char *__s2 = (__const unsigned char *) (__const char *) ("255.255.255.255"); register int __result = (((__const unsigned char *) (__const char *) (*args))[0] - __s2[0]); if (__s1_len > 0 && __result == 0) { __result = (((__const unsigned char *) (__const char *) (*args))[1] - __s2[1]); if (__s1_len > 1 && __result == 0) { __result = (((__const unsigned char *) (__const char *) (*args))[2] - __s2[2]); if (__s1_len > 2 && __result == 0) __result = (((__const unsigned char *) (__const char *) (*args))[3] - __s2[3]); } } __result; }))) : (__builtin_constant_p ("255.255.255.255") && ((size_t)(const void *)(("255.255.255.255") + 1) - (size_t)(const void *)("255.255.255.255") == 1) && (__s2_len = strlen ("255.255.255.255"), __s2_len < 4) ? (__builtin_constant_p (*args) && ((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) ? __builtin_strcmp (*args, "255.255.255.255") : (__extension__ ({ __const unsigned char *__s1 = (__const unsigned char *) (__const char *) (*args); register int __result = __s1[0] - ((__const unsigned char *) (__const char *) ("255.255.255.255"))[0]; if (__s2_len > 0 && __result == 0) { __result = (__s1[1] - ((__const unsigned char *) (__const char *) ("255.255.255.255"))[1]); if (__s2_len > 1 && __result == 0) { __result = (__s1[2] - ((__const unsigned char *) (__const char *) ("255.255.255.255"))[2]); if (__s2_len > 2 && __result == 0) __result = (__s1[3] - ((__const unsigned char *) (__const char *) ("255.255.255.255"))[3]); } } __result; }))) : __builtin_strcmp (*args, "255.255.255.255")))); }) != 0) {
+ memcpy((char *) &req.arp_netmask, (char *) &sa,
+ sizeof(struct sockaddr));
+ }
+ }
+ }
+}
+static int arp_file(char *name)
+{
+ char buff[1024];
+ char *sp, *args[32];
+ int linenr, argc;
+ FILE *fp;
+ while (fgets(buff, sizeof(buff), fp) != (char *) ((void *)0)) {
+ if (arp_set(args) != 0)
+ fprintf(stderr, ("arp: cannot set entry on line %u on line %u of etherfile %s !\n"),
+ linenr, name);
+ }
+}
+int main(int argc, char **argv)
+{
+ int i, lop, what;
+ switch (what) {
+ case 0:
+ what = arp_file(argv[optind] ? argv[optind] : "/etc/ethers");
+ }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ror.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ror.c
new file mode 100644
index 0000000..4d266f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ror.c
@@ -0,0 +1,34 @@
+/* { dg-options "-O2 --save-temps" } */
+/* { dg-do run } */
+
+extern void abort (void);
+
+int
+test_si (int a)
+{
+ /* { dg-final { scan-assembler "ror\tw\[0-9\]+, w\[0-9\]+, 27\n" } } */
+ return (a << 5) | ((unsigned int) a >> 27);
+}
+
+long long
+test_di (long long a)
+{
+ /* { dg-final { scan-assembler "ror\tx\[0-9\]+, x\[0-9\]+, 45\n" } } */
+ return (a << 19) | ((unsigned long long) a >> 45);
+}
+
+int
+main ()
+{
+ int v;
+ long long w;
+ v = test_si (0x0203050);
+ if (v != 0x4060a00)
+ abort();
+ w = test_di (0x0000020506010304ll);
+ if (w != 0x1028300818200000ll)
+ abort();
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sbc.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sbc.c
new file mode 100644
index 0000000..e479910
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sbc.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+typedef unsigned int u32int;
+typedef unsigned long long u64int;
+
+u32int
+test_si (u32int w1, u32int w2, u32int w3, u32int w4)
+{
+ u32int w0;
+ /* { dg-final { scan-assembler "sbc\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+\n" } } */
+ w0 = w1 - w2 - (w3 < w4);
+ return w0;
+}
+
+u64int
+test_di (u64int x1, u64int x2, u64int x3, u64int x4)
+{
+ u64int x0;
+ /* { dg-final { scan-assembler "sbc\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+\n" } } */
+ x0 = x1 - x2 - (x3 < x4);
+ return x0;
+}
+
+int
+main ()
+{
+ u32int x;
+ u64int y;
+ x = test_si (7, 8, 12, 15);
+ if (x != -2)
+ abort();
+ y = test_di (0x987654321ll, 0x123456789ll, 0x345345345ll, 0x123123123ll);
+ if (y != 0x8641fdb98ll)
+ abort();
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar-mov.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar-mov.c
new file mode 100644
index 0000000..5e53d87
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar-mov.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-g -mgeneral-regs-only" } */
+
+void
+foo (const char *c, ...)
+{
+ char buf[256];
+ buf[256 - 1] = '\0';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar-vca.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar-vca.c
new file mode 100644
index 0000000..b118814
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar-vca.c
@@ -0,0 +1,72 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+extern float fabsf (float);
+extern double fabs (double);
+
+#define NUM_TESTS 8
+
+float input_s1[] = {0.1f, -0.1f, 0.4f, 10.3f, 200.0f, -800.0f, -13.0f, -0.5f};
+float input_s2[] = {-0.2f, 0.4f, 0.04f, -100.3f, 2.0f, -80.0f, 13.0f, -0.5f};
+double input_d1[] = {0.1, -0.1, 0.4, 10.3, 200.0, -800.0, -13.0, -0.5};
+double input_d2[] = {-0.2, 0.4, 0.04, -100.3, 2.0, -80.0, 13.0, -0.5};
+
+#define TEST(TEST, CMP, SUFFIX, WIDTH, F) \
+int \
+test_fca##TEST##SUFFIX##_float##WIDTH##_t (void) \
+{ \
+ int ret = 0; \
+ int i = 0; \
+ uint##WIDTH##_t output[NUM_TESTS]; \
+ \
+ for (i = 0; i < NUM_TESTS; i++) \
+ { \
+ float##WIDTH##_t f1 = fabs##F (input_##SUFFIX##1[i]); \
+ float##WIDTH##_t f2 = fabs##F (input_##SUFFIX##2[i]); \
+ /* Inhibit optimization of our linear test loop. */ \
+ asm volatile ("" : : : "memory"); \
+ output[i] = f1 CMP f2 ? -1 : 0; \
+ } \
+ \
+ for (i = 0; i < NUM_TESTS; i++) \
+ { \
+ output[i] = vca##TEST##SUFFIX##_f##WIDTH (input_##SUFFIX##1[i], \
+ input_##SUFFIX##2[i]) \
+ ^ output[i]; \
+ /* Inhibit autovectorization of our scalar test loop. */ \
+ asm volatile ("" : : : "memory"); \
+ } \
+ \
+ for (i = 0; i < NUM_TESTS; i++) \
+ ret |= output[i]; \
+ \
+ return ret; \
+}
+
+TEST (ge, >=, s, 32, f)
+/* { dg-final { scan-assembler "facge\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */
+TEST (ge, >=, d, 64, )
+/* { dg-final { scan-assembler "facge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */
+TEST (gt, >, s, 32, f)
+/* { dg-final { scan-assembler "facgt\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */
+TEST (gt, >, d, 64, )
+/* { dg-final { scan-assembler "facgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */
+
+int
+main (int argc, char **argv)
+{
+ if (test_fcages_float32_t ())
+ abort ();
+ if (test_fcaged_float64_t ())
+ abort ();
+ if (test_fcagts_float32_t ())
+ abort ();
+ if (test_fcagtd_float64_t ())
+ abort ();
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
new file mode 100644
index 0000000..aa041cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
@@ -0,0 +1,1301 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -dp" } */
+
+#include <arm_neon.h>
+
+/* Used to force a variable to a SIMD register. */
+#define force_simd(V1) asm volatile ("mov %d0, %1.d[0]" \
+ : "=w"(V1) \
+ : "w"(V1) \
+ : /* No clobbers */);
+
+/* { dg-final { scan-assembler-times "\\tadd\\tx\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vaddd_u64 (uint64x1_t a, uint64x1_t b)
+{
+ return vaddd_u64 (a, b);
+}
+
+int64x1_t
+test_vaddd_s64 (int64x1_t a, int64x1_t b)
+{
+ return vaddd_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tadd\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vaddd_s64_2 (int64x1_t a, int64x1_t b, int64x1_t c, int64x1_t d)
+{
+ return vqaddd_s64 (vaddd_s64 (vqaddd_s64 (a, b), vqaddd_s64 (c, d)),
+ vqaddd_s64 (a, d));
+}
+
+/* { dg-final { scan-assembler-times "\\tabs\\td\[0-9\]+, d\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vabs_s64 (int64x1_t a)
+{
+ uint64x1_t res;
+ force_simd (a);
+ res = vabs_s64 (a);
+ force_simd (res);
+ return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vceqd_s64 (int64x1_t a, int64x1_t b)
+{
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vceqd_s64 (a, b);
+ force_simd (res);
+ return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
+
+uint64x1_t
+test_vceqzd_s64 (int64x1_t a)
+{
+ uint64x1_t res;
+ force_simd (a);
+ res = vceqzd_s64 (a);
+ force_simd (res);
+ return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vcged_s64 (int64x1_t a, int64x1_t b)
+{
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vcged_s64 (a, b);
+ force_simd (res);
+ return res;
+}
+
+uint64x1_t
+test_vcled_s64 (int64x1_t a, int64x1_t b)
+{
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vcled_s64 (a, b);
+ force_simd (res);
+ return res;
+}
+
+/* Idiom recognition will cause this testcase not to generate
+ the expected cmge instruction, so do not check for it. */
+
+uint64x1_t
+test_vcgezd_s64 (int64x1_t a)
+{
+ uint64x1_t res;
+ force_simd (a);
+ res = vcgezd_s64 (a);
+ force_simd (res);
+ return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmhs\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vcged_u64 (uint64x1_t a, uint64x1_t b)
+{
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vcged_u64 (a, b);
+ force_simd (res);
+ return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vcgtd_s64 (int64x1_t a, int64x1_t b)
+{
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vcgtd_s64 (a, b);
+ force_simd (res);
+ return res;
+}
+
+uint64x1_t
+test_vcltd_s64 (int64x1_t a, int64x1_t b)
+{
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vcltd_s64 (a, b);
+ force_simd (res);
+ return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
+
+uint64x1_t
+test_vcgtzd_s64 (int64x1_t a)
+{
+ uint64x1_t res;
+ force_simd (a);
+ res = vcgtzd_s64 (a);
+ force_simd (res);
+ return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmhi\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vcgtd_u64 (uint64x1_t a, uint64x1_t b)
+{
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vcgtd_u64 (a, b);
+ force_simd (res);
+ return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmle\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
+
+uint64x1_t
+test_vclezd_s64 (int64x1_t a)
+{
+ uint64x1_t res;
+ force_simd (a);
+ res = vclezd_s64 (a);
+ force_simd (res);
+ return res;
+}
+
+/* Idiom recognition will cause this testcase not to generate
+ the expected cmlt instruction, so do not check for it. */
+
+uint64x1_t
+test_vcltzd_s64 (int64x1_t a)
+{
+ uint64x1_t res;
+ force_simd (a);
+ res = vcltzd_s64 (a);
+ force_simd (res);
+ return res;
+}
+
+/* { dg-final { scan-assembler-times "aarch64_get_lanev16qi" 2 } } */
+
+int8x1_t
+test_vdupb_lane_s8 (int8x16_t a)
+{
+ int8x1_t res;
+ force_simd (a);
+ res = vdupb_laneq_s8 (a, 2);
+ force_simd (res);
+ return res;
+}
+
+uint8x1_t
+test_vdupb_lane_u8 (uint8x16_t a)
+{
+ uint8x1_t res;
+ force_simd (a);
+ res = vdupb_laneq_u8 (a, 2);
+ force_simd (res);
+ return res;
+}
+
+/* { dg-final { scan-assembler-times "aarch64_get_lanev8hi" 2 } } */
+
+int16x1_t
+test_vduph_lane_s16 (int16x8_t a)
+{
+ int16x1_t res;
+ force_simd (a);
+ res = vduph_laneq_s16 (a, 2);
+ force_simd (res);
+ return res;
+}
+
+uint16x1_t
+test_vduph_lane_u16 (uint16x8_t a)
+{
+ uint16x1_t res;
+ force_simd (a);
+ res = vduph_laneq_u16 (a, 2);
+ force_simd (res);
+ return res;
+}
+
+/* { dg-final { scan-assembler-times "aarch64_get_lanev4si" 2 } } */
+
+int32x1_t
+test_vdups_lane_s32 (int32x4_t a)
+{
+ int32x1_t res;
+ force_simd (a);
+ res = vdups_laneq_s32 (a, 2);
+ force_simd (res);
+ return res;
+}
+
+uint32x1_t
+test_vdups_lane_u32 (uint32x4_t a)
+{
+ uint32x1_t res;
+ force_simd (a);
+ res = vdups_laneq_u32 (a, 2);
+ force_simd (res);
+ return res;
+}
+
+/* { dg-final { scan-assembler-times "aarch64_get_lanev2di" 2 } } */
+
+int64x1_t
+test_vdupd_lane_s64 (int64x2_t a)
+{
+ int64x1_t res;
+ force_simd (a);
+ res = vdupd_laneq_s64 (a, 1);
+ force_simd (res);
+ return res;
+}
+
+uint64x1_t
+test_vdupd_lane_u64 (uint64x2_t a)
+{
+ uint64x1_t res;
+ force_simd (a);
+ res = vdupd_laneq_u64 (a, 1);
+ force_simd (res);
+ return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmtst\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
+
+int64x1_t
+test_vtst_s64 (int64x1_t a, int64x1_t b)
+{
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vtstd_s64 (a, b);
+ force_simd (res);
+ return res;
+}
+
+uint64x1_t
+test_vtst_u64 (uint64x1_t a, uint64x1_t b)
+{
+ uint64x1_t res;
+ force_simd (a);
+ force_simd (b);
+ res = vtstd_s64 (a, b);
+ force_simd (res);
+ return res;
+}
+
+/* { dg-final { scan-assembler-times "\\taddp\\td\[0-9\]+, v\[0-9\]+\.2d" 1 } } */
+
+test_vpaddd_s64 (int64x2_t a)
+{
+ return vpaddd_s64 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqadd\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vqaddd_u64 (uint64x1_t a, uint64x1_t b)
+{
+ return vqaddd_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqadd\\ts\[0-9\]+" 1 } } */
+
+uint32x1_t
+test_vqadds_u32 (uint32x1_t a, uint32x1_t b)
+{
+ return vqadds_u32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqadd\\th\[0-9\]+" 1 } } */
+
+uint16x1_t
+test_vqaddh_u16 (uint16x1_t a, uint16x1_t b)
+{
+ return vqaddh_u16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqadd\\tb\[0-9\]+" 1 } } */
+
+uint8x1_t
+test_vqaddb_u8 (uint8x1_t a, uint8x1_t b)
+{
+ return vqaddb_u8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqadd\\td\[0-9\]+" 5 } } */
+
+int64x1_t
+test_vqaddd_s64 (int64x1_t a, int64x1_t b)
+{
+ return vqaddd_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqadd\\ts\[0-9\]+, s\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqadds_s32 (int32x1_t a, int32x1_t b)
+{
+ return vqadds_s32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqadd\\th\[0-9\]+, h\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqaddh_s16 (int16x1_t a, int16x1_t b)
+{
+ return vqaddh_s16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqadd\\tb\[0-9\]+, b\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqaddb_s8 (int8x1_t a, int8x1_t b)
+{
+ return vqaddb_s8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqdmlalh_s16 (int32x1_t a, int16x1_t b, int16x1_t c)
+{
+ return vqdmlalh_s16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */
+
+int32x1_t
+test_vqdmlalh_lane_s16 (int32x1_t a, int16x1_t b, int16x8_t c)
+{
+ return vqdmlalh_lane_s16 (a, b, c, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\td\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vqdmlals_s32 (int64x1_t a, int32x1_t b, int32x1_t c)
+{
+ return vqdmlals_s32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */
+
+int64x1_t
+test_vqdmlals_lane_s32 (int64x1_t a, int32x1_t b, int32x4_t c)
+{
+ return vqdmlals_lane_s32 (a, b, c, 1);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqdmlslh_s16 (int32x1_t a, int16x1_t b, int16x1_t c)
+{
+ return vqdmlslh_s16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */
+
+int32x1_t
+test_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x8_t c)
+{
+ return vqdmlslh_lane_s16 (a, b, c, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\td\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vqdmlsls_s32 (int64x1_t a, int32x1_t b, int32x1_t c)
+{
+ return vqdmlsls_s32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */
+
+int64x1_t
+test_vqdmlsls_lane_s32 (int64x1_t a, int32x1_t b, int32x4_t c)
+{
+ return vqdmlsls_lane_s32 (a, b, c, 1);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmulh\\th\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqdmulhh_s16 (int16x1_t a, int16x1_t b)
+{
+ return vqdmulhh_s16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmulh\\th\[0-9\]+, h\[0-9\]+, v" 1 } } */
+
+int16x1_t
+test_vqdmulhh_lane_s16 (int16x1_t a, int16x8_t b)
+{
+ return vqdmulhh_lane_s16 (a, b, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmulh\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqdmulhs_s32 (int32x1_t a, int32x1_t b)
+{
+ return vqdmulhs_s32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmulh\\ts\[0-9\]+, s\[0-9\]+, v" 1 } } */
+
+int32x1_t
+test_vqdmulhs_lane_s32 (int32x1_t a, int32x4_t b)
+{
+ return vqdmulhs_lane_s32 (a, b, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqdmullh_s16 (int16x1_t a, int16x1_t b)
+{
+ return vqdmullh_s16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */
+
+int32x1_t
+test_vqdmullh_lane_s16 (int16x1_t a, int16x8_t b)
+{
+ return vqdmullh_lane_s16 (a, b, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\td\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vqdmulls_s32 (int32x1_t a, int32x1_t b)
+{
+ return vqdmulls_s32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */
+
+int64x1_t
+test_vqdmulls_lane_s32 (int32x1_t a, int32x4_t b)
+{
+ return vqdmulls_lane_s32 (a, b, 1);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrdmulh\\th\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqrdmulhh_s16 (int16x1_t a, int16x1_t b)
+{
+ return vqrdmulhh_s16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrdmulh\\th\[0-9\]+, h\[0-9\]+, v" 1 } } */
+
+int16x1_t
+test_vqrdmulhh_lane_s16 (int16x1_t a, int16x8_t b)
+{
+ return vqrdmulhh_lane_s16 (a, b, 6);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrdmulh\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqrdmulhs_s32 (int32x1_t a, int32x1_t b)
+{
+ return vqrdmulhs_s32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrdmulh\\ts\[0-9\]+, s\[0-9\]+, v" 1 } } */
+
+int32x1_t
+test_vqrdmulhs_lane_s32 (int32x1_t a, int32x4_t b)
+{
+ return vqrdmulhs_lane_s32 (a, b, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tsuqadd\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vuqaddb_s8 (int8x1_t a, int8x1_t b)
+{
+ return vuqaddb_s8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsuqadd\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vuqaddh_s16 (int16x1_t a, int8x1_t b)
+{
+ return vuqaddh_s16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsuqadd\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vuqadds_s32 (int32x1_t a, int8x1_t b)
+{
+ return vuqadds_s32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsuqadd\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vuqaddd_s64 (int64x1_t a, int8x1_t b)
+{
+ return vuqaddd_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tusqadd\\tb\[0-9\]+" 1 } } */
+
+uint8x1_t
+test_vsqaddb_u8 (uint8x1_t a, int8x1_t b)
+{
+ return vsqaddb_u8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tusqadd\\th\[0-9\]+" 1 } } */
+
+uint16x1_t
+test_vsqaddh_u16 (uint16x1_t a, int8x1_t b)
+{
+ return vsqaddh_u16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tusqadd\\ts\[0-9\]+" 1 } } */
+
+uint32x1_t
+test_vsqadds_u32 (uint32x1_t a, int8x1_t b)
+{
+ return vsqadds_u32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tusqadd\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vsqaddd_u64 (uint64x1_t a, int8x1_t b)
+{
+ return vsqaddd_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqabs\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqabsb_s8 (int8x1_t a)
+{
+ return vqabsb_s8 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqabs\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqabsh_s16 (int16x1_t a)
+{
+ return vqabsh_s16 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqabs\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqabss_s32 (int32x1_t a)
+{
+ return vqabss_s32 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqneg\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqnegb_s8 (int8x1_t a)
+{
+ return vqnegb_s8 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqneg\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqnegh_s16 (int16x1_t a)
+{
+ return vqnegh_s16 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqneg\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqnegs_s32 (int32x1_t a)
+{
+ return vqnegs_s32 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqxtun\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqmovunh_s16 (int16x1_t a)
+{
+ return vqmovunh_s16 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqxtun\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqmovuns_s32 (int32x1_t a)
+{
+ return vqmovuns_s32 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqxtun\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqmovund_s64 (int64x1_t a)
+{
+ return vqmovund_s64 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqxtn\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqmovnh_s16 (int16x1_t a)
+{
+ return vqmovnh_s16 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqxtn\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqmovns_s32 (int32x1_t a)
+{
+ return vqmovns_s32 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqxtn\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqmovnd_s64 (int64x1_t a)
+{
+ return vqmovnd_s64 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqxtn\\tb\[0-9\]+" 1 } } */
+
+uint8x1_t
+test_vqmovnh_u16 (uint16x1_t a)
+{
+ return vqmovnh_u16 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqxtn\\th\[0-9\]+" 1 } } */
+
+uint16x1_t
+test_vqmovns_u32 (uint32x1_t a)
+{
+ return vqmovns_u32 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqxtn\\ts\[0-9\]+" 1 } } */
+
+uint32x1_t
+test_vqmovnd_u64 (uint64x1_t a)
+{
+ return vqmovnd_u64 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsub\\tx\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vsubd_u64 (uint64x1_t a, uint64x1_t b)
+{
+ return vsubd_u64 (a, b);
+}
+
+int64x1_t
+test_vsubd_s64 (int64x1_t a, int64x1_t b)
+{
+ return vsubd_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsub\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vsubd_s64_2 (int64x1_t a, int64x1_t b, int64x1_t c, int64x1_t d)
+{
+ return vqsubd_s64 (vsubd_s64 (vqsubd_s64 (a, b), vqsubd_s64 (c, d)),
+ vqsubd_s64 (a, d));
+}
+
+/* { dg-final { scan-assembler-times "\\tuqsub\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vqsubd_u64 (uint64x1_t a, uint64x1_t b)
+{
+ return vqsubd_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqsub\\ts\[0-9\]+" 1 } } */
+
+uint32x1_t
+test_vqsubs_u32 (uint32x1_t a, uint32x1_t b)
+{
+ return vqsubs_u32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqsub\\th\[0-9\]+" 1 } } */
+
+uint16x1_t
+test_vqsubh_u16 (uint16x1_t a, uint16x1_t b)
+{
+ return vqsubh_u16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqsub\\tb\[0-9\]+" 1 } } */
+
+uint8x1_t
+test_vqsubb_u8 (uint8x1_t a, uint8x1_t b)
+{
+ return vqsubb_u8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqsub\\td\[0-9\]+" 5 } } */
+
+int64x1_t
+test_vqsubd_s64 (int64x1_t a, int64x1_t b)
+{
+ return vqsubd_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqsub\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqsubs_s32 (int32x1_t a, int32x1_t b)
+{
+ return vqsubs_s32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqsub\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqsubh_s16 (int16x1_t a, int16x1_t b)
+{
+ return vqsubh_s16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqsub\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqsubb_s8 (int8x1_t a, int8x1_t b)
+{
+ return vqsubb_s8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshl\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vshld_s64 (int64x1_t a, int64x1_t b)
+{
+ return vshld_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tushl\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vshld_u64 (uint64x1_t a, uint64x1_t b)
+{
+ return vshld_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsrshl\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vrshld_s64 (int64x1_t a, int64x1_t b)
+{
+ return vrshld_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\turshl\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vrshld_u64 (uint64x1_t a, uint64x1_t b)
+{
+ return vrshld_u64 (a, b);
+}
+
+/* Other intrinsics can generate an asr instruction (vcltzd, vcgezd),
+ so we cannot check scan-assembler-times. */
+
+/* { dg-final { scan-assembler "\\tasr\\tx\[0-9\]+" } } */
+
+int64x1_t
+test_vshrd_n_s64 (int64x1_t a)
+{
+ return vshrd_n_s64 (a, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\tlsr\\tx\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vshrd_n_u64 (uint64x1_t a)
+{
+ return vshrd_n_u64 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tssra\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vsrad_n_s64 (int64x1_t a, int64x1_t b)
+{
+ return vsrad_n_s64 (a, b, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tusra\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vsrad_n_u64 (uint64x1_t a, uint64x1_t b)
+{
+ return vsrad_n_u64 (a, b, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\tsrshr\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vrshrd_n_s64 (int64x1_t a)
+{
+ return vrshrd_n_s64 (a, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\turshr\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vrshrd_n_u64 (uint64x1_t a)
+{
+ return vrshrd_n_u64 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsrsra\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vrsrad_n_s64 (int64x1_t a, int64x1_t b)
+{
+ return vrsrad_n_s64 (a, b, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsrsra\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vrsrad_n_u64 (uint64x1_t a, uint64x1_t b)
+{
+ return vrsrad_n_u64 (a, b, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshl\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqrshlb_s8 (int8x1_t a, int8x1_t b)
+{
+ return vqrshlb_s8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshl\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqrshlh_s16 (int16x1_t a, int16x1_t b)
+{
+ return vqrshlh_s16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshl\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqrshls_s32 (int32x1_t a, int32x1_t b)
+{
+ return vqrshls_s32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshl\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vqrshld_s64 (int64x1_t a, int64x1_t b)
+{
+ return vqrshld_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqrshl\\tb\[0-9\]+" 1 } } */
+
+uint8x1_t
+test_vqrshlb_u8 (uint8x1_t a, uint8x1_t b)
+{
+ return vqrshlb_u8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqrshl\\th\[0-9\]+" 1 } } */
+
+uint16x1_t
+test_vqrshlh_u16 (uint16x1_t a, uint16x1_t b)
+{
+ return vqrshlh_u16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqrshl\\ts\[0-9\]+" 1 } } */
+
+uint32x1_t
+test_vqrshls_u32 (uint32x1_t a, uint32x1_t b)
+{
+ return vqrshls_u32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqrshl\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vqrshld_u64 (uint64x1_t a, uint64x1_t b)
+{
+ return vqrshld_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshlu\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqshlub_n_s8 (int8x1_t a)
+{
+ return vqshlub_n_s8 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshlu\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqshluh_n_s16 (int16x1_t a)
+{
+ return vqshluh_n_s16 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshlu\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqshlus_n_s32 (int32x1_t a)
+{
+ return vqshlus_n_s32 (a, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshlu\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vqshlud_n_s64 (int64x1_t a)
+{
+ return vqshlud_n_s64 (a, 6);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshl\\tb\[0-9\]+" 2 } } */
+
+int8x1_t
+test_vqshlb_s8 (int8x1_t a, int8x1_t b)
+{
+ return vqshlb_s8 (a, b);
+}
+
+int8x1_t
+test_vqshlb_n_s8 (int8x1_t a)
+{
+ return vqshlb_n_s8 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshl\\th\[0-9\]+" 2 } } */
+
+int16x1_t
+test_vqshlh_s16 (int16x1_t a, int16x1_t b)
+{
+ return vqshlh_s16 (a, b);
+}
+
+int16x1_t
+test_vqshlh_n_s16 (int16x1_t a)
+{
+ return vqshlh_n_s16 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshl\\ts\[0-9\]+" 2 } } */
+
+int32x1_t
+test_vqshls_s32 (int32x1_t a, int32x1_t b)
+{
+ return vqshls_s32 (a, b);
+}
+
+int32x1_t
+test_vqshls_n_s32 (int32x1_t a)
+{
+ return vqshls_n_s32 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshl\\td\[0-9\]+" 2 } } */
+
+int64x1_t
+test_vqshld_s64 (int64x1_t a, int64x1_t b)
+{
+ return vqshld_s64 (a, b);
+}
+
+int64x1_t
+test_vqshld_n_s64 (int64x1_t a)
+{
+ return vqshld_n_s64 (a, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqshl\\tb\[0-9\]+" 2 } } */
+
+uint8x1_t
+test_vqshlb_u8 (uint8x1_t a, uint8x1_t b)
+{
+ return vqshlb_u8 (a, b);
+}
+
+uint8x1_t
+test_vqshlb_n_u8 (uint8x1_t a)
+{
+ return vqshlb_n_u8 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqshl\\th\[0-9\]+" 2 } } */
+
+uint16x1_t
+test_vqshlh_u16 (uint16x1_t a, uint16x1_t b)
+{
+ return vqshlh_u16 (a, b);
+}
+
+uint16x1_t
+test_vqshlh_n_u16 (uint16x1_t a)
+{
+ return vqshlh_n_u16 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqshl\\ts\[0-9\]+" 2 } } */
+
+uint32x1_t
+test_vqshls_u32 (uint32x1_t a, uint32x1_t b)
+{
+ return vqshls_u32 (a, b);
+}
+
+uint32x1_t
+test_vqshls_n_u32 (uint32x1_t a)
+{
+ return vqshls_n_u32 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqshl\\td\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vqshld_u64 (uint64x1_t a, uint64x1_t b)
+{
+ return vqshld_u64 (a, b);
+}
+
+uint64x1_t
+test_vqshld_n_u64 (uint64x1_t a)
+{
+ return vqshld_n_u64 (a, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshrun\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqshrunh_n_s16 (int16x1_t a)
+{
+ return vqshrunh_n_s16 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshrun\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqshruns_n_s32 (int32x1_t a)
+{
+ return vqshruns_n_s32 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshrun\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqshrund_n_s64 (int64x1_t a)
+{
+ return vqshrund_n_s64 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshrun\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqrshrunh_n_s16 (int16x1_t a)
+{
+ return vqrshrunh_n_s16 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshrun\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqrshruns_n_s32 (int32x1_t a)
+{
+ return vqrshruns_n_s32 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshrun\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqrshrund_n_s64 (int64x1_t a)
+{
+ return vqrshrund_n_s64 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshrn\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqshrnh_n_s16 (int16x1_t a)
+{
+ return vqshrnh_n_s16 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshrn\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqshrns_n_s32 (int32x1_t a)
+{
+ return vqshrns_n_s32 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshrn\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqshrnd_n_s64 (int64x1_t a)
+{
+ return vqshrnd_n_s64 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqshrn\\tb\[0-9\]+" 1 } } */
+
+uint8x1_t
+test_vqshrnh_n_u16 (uint16x1_t a)
+{
+ return vqshrnh_n_u16 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqshrn\\th\[0-9\]+" 1 } } */
+
+uint16x1_t
+test_vqshrns_n_u32 (uint32x1_t a)
+{
+ return vqshrns_n_u32 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqshrn\\ts\[0-9\]+" 1 } } */
+
+uint32x1_t
+test_vqshrnd_n_u64 (uint64x1_t a)
+{
+ return vqshrnd_n_u64 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshrn\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqrshrnh_n_s16 (int16x1_t a)
+{
+ return vqrshrnh_n_s16 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshrn\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqrshrns_n_s32 (int32x1_t a)
+{
+ return vqrshrns_n_s32 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshrn\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqrshrnd_n_s64 (int64x1_t a)
+{
+ return vqrshrnd_n_s64 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqrshrn\\tb\[0-9\]+" 1 } } */
+
+uint8x1_t
+test_vqrshrnh_n_u16 (uint16x1_t a)
+{
+ return vqrshrnh_n_u16 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqrshrn\\th\[0-9\]+" 1 } } */
+
+uint16x1_t
+test_vqrshrns_n_u32 (uint32x1_t a)
+{
+ return vqrshrns_n_u32 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqrshrn\\ts\[0-9\]+" 1 } } */
+
+uint32x1_t
+test_vqrshrnd_n_u64 (uint64x1_t a)
+{
+ return vqrshrnd_n_u64 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tlsl\\tx\[0-9\]+" 2 } } */
+
+int64x1_t
+test_vshl_n_s64 (int64x1_t a)
+{
+ return vshld_n_s64 (a, 9);
+}
+
+uint64x1_t
+test_vshl_n_u64 (uint64x1_t a)
+{
+ return vshld_n_u64 (a, 9);
+}
+
+/* { dg-final { scan-assembler-times "\\tsli\\td\[0-9\]+" 2 } } */
+
+int64x1_t
+test_vsli_n_s64 (int64x1_t a, int64x1_t b)
+{
+ return vslid_n_s64 (a, b, 9);
+}
+
+uint64x1_t
+test_vsli_n_u64 (uint64x1_t a, uint64x1_t b)
+{
+ return vslid_n_u64 (a, b, 9);
+}
+
+/* { dg-final { scan-assembler-times "\\tsri\\td\[0-9\]+" 2 } } */
+
+int64x1_t
+test_vsri_n_s64 (int64x1_t a, int64x1_t b)
+{
+ return vsrid_n_s64 (a, b, 9);
+}
+
+uint64x1_t
+test_vsri_n_u64 (uint64x1_t a, uint64x1_t b)
+{
+ return vsrid_n_u64 (a, b, 9);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c
new file mode 100644
index 0000000..7cb17f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c
@@ -0,0 +1,263 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-inline -save-temps" } */
+
+extern void abort ();
+
+#define force_simd_di(v) asm volatile ("mov %d0, %1.d[0]" :"=w" (v) :"w" (v) :)
+#define force_simd_si(v) asm volatile ("mov %s0, %1.s[0]" :"=w" (v) :"w" (v) :)
+
+typedef unsigned long long int UInt64x1;
+typedef long long int Int64x1;
+typedef unsigned int UInt32x1;
+typedef int Int32x1;
+
+UInt64x1
+test_lshift_left_sisd_di (UInt64x1 b, UInt64x1 c)
+{
+ UInt64x1 a;
+
+ force_simd_di (b);
+ force_simd_di (c);
+ a = b << 8;
+ a = a << c;
+ force_simd_di (a);
+ return a;
+}
+/* { dg-final { scan-assembler "shl\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */
+/* { dg-final { scan-assembler "ushl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */
+
+UInt32x1
+test_lshift_left_sisd_si (UInt32x1 b, UInt32x1 c)
+{
+ UInt32x1 a;
+
+ force_simd_si (b);
+ force_simd_si (c);
+ a = b << 4;
+ a = a << c;
+ force_simd_si (a);
+ return a;
+}
+/* { dg-final { scan-assembler "shl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */
+/* "ushl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" (counted later) */
+
+UInt64x1
+test_lshift_right_sisd_di (UInt64x1 b, UInt64x1 c)
+{
+ UInt64x1 a;
+
+ force_simd_di (b);
+ force_simd_di (c);
+ a = b >> 8;
+ a = a >> c;
+ force_simd_di (a);
+ return a;
+}
+/* { dg-final { scan-assembler "ushr\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */
+/* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */
+/* { dg-final { scan-assembler "ushl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */
+
+UInt64x1
+test_lshift_right_sisd_si (UInt32x1 b, UInt32x1 c)
+{
+ UInt32x1 a;
+
+ force_simd_si (b);
+ force_simd_si (c);
+ a = b >> 4;
+ a = a >> c;
+ force_simd_si (a);
+ return a;
+}
+/* { dg-final { scan-assembler "ushr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */
+/* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */
+/* { dg-final { scan-assembler-times "ushl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" 2 } } */
+
+Int64x1
+test_ashift_right_sisd_di (Int64x1 b, Int64x1 c)
+{
+ Int64x1 a;
+
+ force_simd_di (b);
+ force_simd_di (c);
+ a = b >> 8;
+ a = a >> c;
+ force_simd_di (a);
+ return a;
+}
+/* { dg-final { scan-assembler "sshr\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */
+/* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */
+/* { dg-final { scan-assembler "sshl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */
+
+Int32x1
+test_ashift_right_sisd_si (Int32x1 b, Int32x1 c)
+{
+ Int32x1 a;
+
+ force_simd_si (b);
+ force_simd_si (c);
+ a = b >> 4;
+ a = a >> c;
+ force_simd_si (a);
+ return a;
+}
+/* { dg-final { scan-assembler "sshr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */
+/* { dg-final { scan-assembler-times "neg\td\[0-9\]+,\ d\[0-9\]+" 4 } } */
+/* { dg-final { scan-assembler "sshl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" } } */
+
+
+/* The following are to make sure if the integer instructions lsl/lsr/asr are
+ generated in non-vector scenarios */
+
+UInt64x1
+test_lshift_left_int_di (UInt64x1 b, UInt64x1 c)
+{
+ UInt64x1 a;
+
+ a = b << 8;
+ a = a << c;
+ return a;
+}
+/* { dg-final { scan-assembler "lsl\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */
+/* { dg-final { scan-assembler "lsl\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */
+
+UInt32x1
+test_lshift_left_int_si (UInt32x1 b, UInt32x1 c)
+{
+ UInt32x1 a;
+
+ a = b << 4;
+ a = a << c;
+ return a;
+}
+/* { dg-final { scan-assembler "lsl\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
+/* { dg-final { scan-assembler "lsl\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
+
+UInt64x1
+test_lshift_right_int_di (UInt64x1 b, UInt64x1 c)
+{
+ UInt64x1 a;
+
+ a = b >> 8;
+ a = a >> c;
+ return a;
+}
+/* { dg-final { scan-assembler "lsr\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */
+/* { dg-final { scan-assembler "lsr\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */
+
+UInt32x1
+test_lshift_right_int_si (UInt32x1 b, UInt32x1 c)
+{
+ UInt32x1 a;
+
+ a = b >> 4;
+ a = a >> c;
+ return a;
+}
+/* { dg-final { scan-assembler "lsr\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
+/* { dg-final { scan-assembler "lsr\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
+
+Int64x1
+test_ashift_right_int_di (Int64x1 b, Int64x1 c)
+{
+ Int64x1 a;
+
+ a = b >> 8;
+ a = a >> c;
+ return a;
+}
+/* { dg-final { scan-assembler "asr\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */
+/* { dg-final { scan-assembler "asr\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */
+
+Int32x1
+test_ashift_right_int_si (Int32x1 b, Int32x1 c)
+{
+ Int32x1 a;
+
+ a = b >> 4;
+ a = a >> c;
+ return a;
+}
+/* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
+/* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
+
+Int64x1
+test_corners_sisd_di (Int64x1 b)
+{
+ force_simd_di (b);
+ b = b >> 63;
+ b = b >> 0;
+ b += b >> 65; /* { dg-warning "right shift count >= width of type" } */
+ force_simd_di (b);
+
+ return b;
+}
+/* { dg-final { scan-assembler "sshr\td\[0-9\]+,\ d\[0-9\]+,\ 63" } } */
+/* { dg-final { scan-assembler "shl\td\[0-9\]+,\ d\[0-9\]+,\ 1" } } */
+
+Int32x1
+test_corners_sisd_si (Int32x1 b)
+{
+ force_simd_si (b);
+ b = b >> 31;
+ b = b >> 0;
+ b += b >> 33; /* { dg-warning "right shift count >= width of type" } */
+ force_simd_si (b);
+
+ return b;
+}
+/* { dg-final { scan-assembler "sshr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 31" } } */
+/* { dg-final { scan-assembler "shl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 1" } } */
+
+
+
+#define CHECK(var,val) \
+do \
+ { \
+ if (var != val) \
+ abort(); \
+ } \
+while(0)
+
+UInt64x1 x = 0xC01dDeadBeefFaceull;
+UInt32x1 y = 0xDeadBeef;
+
+int
+main ()
+{
+ x = test_lshift_left_sisd_di (x, 8);
+ CHECK (x, 0xdeadbeefface0000ull);
+ x = test_lshift_right_int_di (x, 8);
+ CHECK (x, 0x0000deadbeeffaceull);
+ x = test_lshift_right_sisd_di (x, 8);
+ CHECK (x, 0x00000000deadbeefull);
+ x = test_lshift_left_int_di (x, 8);
+ CHECK (x, 0x0000deadbeef0000ull);
+ x = ~x;
+ x = test_ashift_right_int_di (x, 8);
+ CHECK (x, 0xffffffff21524110ull);
+ x = test_ashift_right_sisd_di (x, 8);
+ CHECK (x, 0xffffffffffff2152ull);
+ x = test_corners_sisd_di (x);
+ CHECK (x, 0xfffffffffffffffeull);
+
+ y = test_lshift_left_sisd_si (y, 4);
+ CHECK (y, 0xadbeef00);
+ y = test_lshift_right_int_si (y, 4);
+ CHECK (y, 0x00adbeef);
+ y = test_lshift_right_sisd_si (y, 4);
+ CHECK (y, 0x0000adbe);
+ y = test_lshift_left_int_si (y, 4);
+ CHECK (y, 0x00adbe00);
+ y = ~y;
+ y = test_ashift_right_int_si (y, 4);
+ CHECK (y, 0xffff5241);
+ y = test_ashift_right_sisd_si (y, 4);
+ CHECK (y, 0xffffff52);
+ y = test_corners_sisd_si (y);
+ CHECK (y, 0xfffffffe);
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sha1_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sha1_1.c
new file mode 100644
index 0000000..776753d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sha1_1.c
@@ -0,0 +1,55 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+crypto" } */
+
+#include "arm_neon.h"
+
+uint32x4_t
+test_vsha1cq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+{
+ return vsha1cq_u32 (hash_abcd, hash_e, wk);
+}
+
+/* { dg-final { scan-assembler-times "sha1c\\tq" 1 } } */
+
+uint32x4_t
+test_vsha1mq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+{
+ return vsha1mq_u32 (hash_abcd, hash_e, wk);
+}
+
+/* { dg-final { scan-assembler-times "sha1m\\tq" 1 } } */
+
+uint32x4_t
+test_vsha1pq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+{
+ return vsha1pq_u32 (hash_abcd, hash_e, wk);
+}
+
+/* { dg-final { scan-assembler-times "sha1p\\tq" 1 } } */
+
+uint32_t
+test_vsha1h_u32 (uint32_t hash_e)
+{
+ return vsha1h_u32 (hash_e);
+}
+
+/* { dg-final { scan-assembler-times "sha1h\\ts" 1 } } */
+
+uint32x4_t
+test_vsha1su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11)
+{
+ return vsha1su0q_u32 (w0_3, w4_7, w8_11);
+}
+
+/* { dg-final { scan-assembler-times "sha1su0\\tv" 1 } } */
+
+uint32x4_t
+test_vsha1su1q_u32 (uint32x4_t tw0_3, uint32x4_t w12_15)
+{
+ return vsha1su1q_u32 (tw0_3, w12_15);
+}
+
+/* { dg-final { scan-assembler-times "sha1su1\\tv" 1 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sha256_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sha256_1.c
new file mode 100644
index 0000000..569817e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sha256_1.c
@@ -0,0 +1,40 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+crypto" } */
+
+#include "arm_neon.h"
+
+uint32x4_t
+test_vsha256hq_u32 (uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk)
+{
+ return vsha256hq_u32 (hash_abcd, hash_efgh, wk);
+}
+
+/* { dg-final { scan-assembler-times "sha256h\\tq" 1 } } */
+
+uint32x4_t
+test_vsha256h2q_u32 (uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk)
+{
+ return vsha256h2q_u32 (hash_efgh, hash_abcd, wk);
+}
+
+/* { dg-final { scan-assembler-times "sha256h2\\tq" 1 } } */
+
+uint32x4_t
+test_vsha256su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7)
+{
+ return vsha256su0q_u32 (w0_3, w4_7);
+}
+
+/* { dg-final { scan-assembler-times "sha256su0\\tv" 1 } } */
+
+uint32x4_t
+test_vsha256su1q_u32 (uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15)
+{
+ return vsha256su1q_u32 (tw0_3, w8_11, w12_15);
+}
+
+/* { dg-final { scan-assembler-times "sha256su1\\tv" 1 } } */
+
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sshr64_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sshr64_1.c
new file mode 100644
index 0000000..89c6096
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sshr64_1.c
@@ -0,0 +1,115 @@
+/* Test SIMD shift works correctly. */
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include "arm_neon.h"
+
+extern void abort (void);
+
+int __attribute__ ((noinline))
+test_sshr64 ()
+{
+ int64x1_t arg;
+ int64x1_t result;
+ int64_t got;
+ int64_t exp;
+ arg = vcreate_s64 (0x0000000080000000);
+ result = vshr_n_s64 (arg, 64);
+ got = vget_lane_s64 (result, 0);
+ exp = 0;
+ /* Expect: "result" = 0000000000000000. */
+ if (exp != got)
+ return 1;
+ return 0;
+}
+
+int __attribute__ ((noinline))
+test_sshr64_neg ()
+{
+ int64x1_t arg;
+ int64x1_t result;
+ int64_t got;
+ int64_t exp;
+ arg = vcreate_s64 (0xffffffff80000000);
+ result = vshr_n_s64 (arg, 64);
+ got = vget_lane_s64 (result, 0);
+ exp = 0xffffffffffffffff;
+ /* Expect: "result" = -1. */
+ if (exp != got)
+ return 1;
+ return 0;
+}
+
+int
+__attribute__ ((noinline))
+test_other ()
+{
+ int64x1_t arg;
+ int64x1_t result;
+ int64_t got;
+ int64_t exp;
+ arg = vcreate_s64 (0x0000000080000000);
+ result = vshr_n_s64 (arg, 4);
+ got = vget_lane_s64 (result, 0);
+ exp = 0x0000000008000000;
+ /* Expect: "result" = 0x0000000008000000. */
+ if (exp != got)
+ return 1;
+ return 0;
+}
+
+int __attribute__ ((noinline))
+test_other_neg ()
+{
+ int64x1_t arg;
+ int64x1_t result;
+ int64_t got;
+ int64_t exp;
+ arg = vcreate_s64 (0xffffffff80000000);
+ result = vshr_n_s64 (arg, 4);
+ got = vget_lane_s64 (result, 0);
+ exp = 0xfffffffff8000000;
+ /* Expect: "result" = 0xfffffffff8000000. */
+ if (exp != got)
+ return 1;
+ return 0;
+}
+
+int __attribute__ ((noinline))
+test_no_sshr0 ()
+{
+ int64x1_t arg;
+ int64x1_t result;
+ int64_t got;
+ int64_t exp;
+ arg = vcreate_s64 (0x0000000080000000);
+ result = vshr_n_s64 (arg, 0);
+ got = vget_lane_s64 (result, 0);
+ exp = 0x0000000080000000;
+ /* Expect: "result" = 0x0000000080000000. */
+ if (exp != got)
+ return 1;
+ return 0;
+}
+
+/* { dg-final { scan-assembler-not "sshr\\td\[0-9\]+, d\[0-9\]+, 0" } } */
+int
+main ()
+{
+ if (test_sshr64 ())
+ abort ();
+ if (test_other ())
+ abort ();
+
+ if (test_sshr64_neg ())
+ abort ();
+ if (test_other_neg ())
+ abort ();
+
+ if (test_no_sshr0 ())
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs.c
new file mode 100644
index 0000000..2bf1975
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int z;
+int
+foo (int x, int y)
+{
+ int l = x - y;
+ if (l == 0)
+ return 5;
+
+ /* { dg-final { scan-assembler "subs\tw\[0-9\]" } } */
+ z = l ;
+ return 25;
+}
+
+typedef long long s64;
+
+s64 zz;
+s64
+foo2 (s64 x, s64 y)
+{
+ s64 l = x - y;
+ if (l < 0)
+ return 5;
+
+ /* { dg-final { scan-assembler "subs\tx\[0-9\]" } } */
+ zz = l ;
+ return 25;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs1.c
new file mode 100644
index 0000000..7e4b2b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs1.c
@@ -0,0 +1,149 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+subs_si_test1 (int a, int b, int c)
+{
+ int d = a - c;
+
+ /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+subs_si_test2 (int a, int b, int c)
+{
+ int d = a - 0xff;
+
+ /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, #255" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+subs_si_test3 (int a, int b, int c)
+{
+ int d = a - (b << 3);
+
+ /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+subs_di_test1 (s64 a, s64 b, s64 c)
+{
+ s64 d = a - c;
+
+ /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+subs_di_test2 (s64 a, s64 b, s64 c)
+{
+ s64 d = a - 0xff;
+
+ /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, #255" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+subs_di_test3 (s64 a, s64 b, s64 c)
+{
+ s64 d = a - (b << 3);
+
+ /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int main ()
+{
+ int x;
+ s64 y;
+
+ x = subs_si_test1 (29, 4, 5);
+ if (x != 33)
+ abort ();
+
+ x = subs_si_test1 (5, 2, 20);
+ if (x != 7)
+ abort ();
+
+ x = subs_si_test2 (29, 4, 5);
+ if (x != -217)
+ abort ();
+
+ x = subs_si_test2 (1024, 2, 20);
+ if (x != 791)
+ abort ();
+
+ x = subs_si_test3 (35, 4, 5);
+ if (x != 12)
+ abort ();
+
+ x = subs_si_test3 (5, 2, 20);
+ if (x != 11)
+ abort ();
+
+ y = subs_di_test1 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+
+ if (y != 0x45000002d)
+ abort ();
+
+ y = subs_di_test1 (0x5000500050005ll,
+ 0x2111211121112ll,
+ 0x0000000002020ll);
+ if (y != 0x7111711171117)
+ abort ();
+
+ y = subs_di_test2 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+ if (y != 0x955050433)
+ abort ();
+
+ y = subs_di_test2 (0x130002900ll,
+ 0x320000004ll,
+ 0x505050505ll);
+ if (y != 0x955052d0a)
+ abort ();
+
+ y = subs_di_test3 (0x130000029ll,
+ 0x064000008ll,
+ 0x505050505ll);
+ if (y != 0x3790504f6)
+ abort ();
+
+ y = subs_di_test3 (0x130002900ll,
+ 0x088000008ll,
+ 0x505050505ll);
+ if (y != 0x27d052dcd)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs2.c
new file mode 100644
index 0000000..d90ead5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs2.c
@@ -0,0 +1,155 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+subs_si_test1 (int a, int b, int c)
+{
+ int d = a - b;
+
+ /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+ /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+subs_si_test2 (int a, int b, int c)
+{
+ int d = a - 0xfff;
+
+ /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, #4095" } } */
+ /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, #4095" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+subs_si_test3 (int a, int b, int c)
+{
+ int d = a - (b << 3);
+
+ /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+subs_di_test1 (s64 a, s64 b, s64 c)
+{
+ s64 d = a - b;
+
+ /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+subs_di_test2 (s64 a, s64 b, s64 c)
+{
+ s64 d = a - 0x1000ll;
+
+ /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, #4096" } } */
+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, #4096" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+subs_di_test3 (s64 a, s64 b, s64 c)
+{
+ s64 d = a - (b << 3);
+
+ /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int main ()
+{
+ int x;
+ s64 y;
+
+ x = subs_si_test1 (29, 4, 5);
+ if (x != 34)
+ abort ();
+
+ x = subs_si_test1 (5, 2, 20);
+ if (x != 25)
+ abort ();
+
+ x = subs_si_test2 (29, 4, 5);
+ if (x != 34)
+ abort ();
+
+ x = subs_si_test2 (1024, 2, 20);
+ if (x != 1044)
+ abort ();
+
+ x = subs_si_test3 (35, 4, 5);
+ if (x != 12)
+ abort ();
+
+ x = subs_si_test3 (5, 2, 20);
+ if (x != 25)
+ abort ();
+
+ y = subs_di_test1 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+
+ if (y != 0x63505052e)
+ abort ();
+
+ y = subs_di_test1 (0x5000500050005ll,
+ 0x2111211121112ll,
+ 0x0000000002020ll);
+ if (y != 0x5000500052025)
+ abort ();
+
+ y = subs_di_test2 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+ if (y != 0x95504f532)
+ abort ();
+
+ y = subs_di_test2 (0x540004100ll,
+ 0x320000004ll,
+ 0x805050205ll);
+ if (y != 0x1065053309)
+ abort ();
+
+ y = subs_di_test3 (0x130000029ll,
+ 0x064000008ll,
+ 0x505050505ll);
+ if (y != 0x63505052e)
+ abort ();
+
+ y = subs_di_test3 (0x130002900ll,
+ 0x088000008ll,
+ 0x505050505ll);
+ if (y != 0x635052e05)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs3.c
new file mode 100644
index 0000000..90f20b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs3.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+typedef long long s64;
+
+int
+subs_ext (s64 a, int b, int c)
+{
+ s64 d = a - b;
+
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+subs_shift_ext (s64 a, int b, int c)
+{
+ s64 d = (a - ((s64)b << 3));
+
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int main ()
+{
+ int x;
+ s64 y;
+
+ x = subs_ext (0x13000002ll, 41, 15);
+ if (x != 318767121)
+ abort ();
+
+ x = subs_ext (0x50505050ll, 29, 4);
+ if (x != 1347440724)
+ abort ();
+
+ x = subs_ext (0x12121212121ll, 2, 14);
+ if (x != 555819311)
+ abort ();
+
+ x = subs_shift_ext (0x123456789ll, 4, 12);
+ if (x != 591751033)
+ abort ();
+
+ x = subs_shift_ext (0x02020202ll, 9, 8);
+ if (x != 33685963)
+ abort ();
+
+ x = subs_shift_ext (0x987987987987ll, 23, 41);
+ if (x != -2020050673)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/table-intrinsics.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/table-intrinsics.c
new file mode 100644
index 0000000..6281cda
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/table-intrinsics.c
@@ -0,0 +1,439 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#include "arm_neon.h"
+
+int8x8_t
+tbl_tests8_ (int8x8_t tab, int8x8_t idx)
+{
+ return vtbl1_s8 (tab, idx);
+}
+
+uint8x8_t
+tbl_testu8_ (uint8x8_t tab, uint8x8_t idx)
+{
+ return vtbl1_u8 (tab, idx);
+}
+
+poly8x8_t
+tbl_testp8_ (poly8x8_t tab, uint8x8_t idx)
+{
+ return vtbl1_p8 (tab, idx);
+}
+
+int8x8_t
+tbl_tests8_2 (int8x8x2_t tab, int8x8_t idx)
+{
+ return vtbl2_s8 (tab, idx);
+}
+
+uint8x8_t
+tbl_testu8_2 (uint8x8x2_t tab, uint8x8_t idx)
+{
+ return vtbl2_u8 (tab, idx);
+}
+
+poly8x8_t
+tbl_testp8_2 (poly8x8x2_t tab, uint8x8_t idx)
+{
+ return vtbl2_p8 (tab, idx);
+}
+
+int8x8_t
+tbl_tests8_3 (int8x8x3_t tab, int8x8_t idx)
+{
+ return vtbl3_s8 (tab, idx);
+}
+
+uint8x8_t
+tbl_testu8_3 (uint8x8x3_t tab, uint8x8_t idx)
+{
+ return vtbl3_u8 (tab, idx);
+}
+
+poly8x8_t
+tbl_testp8_3 (poly8x8x3_t tab, uint8x8_t idx)
+{
+ return vtbl3_p8 (tab, idx);
+}
+
+int8x8_t
+tbl_tests8_4 (int8x8x4_t tab, int8x8_t idx)
+{
+ return vtbl4_s8 (tab, idx);
+}
+
+uint8x8_t
+tbl_testu8_4 (uint8x8x4_t tab, uint8x8_t idx)
+{
+ return vtbl4_u8 (tab, idx);
+}
+
+poly8x8_t
+tbl_testp8_4 (poly8x8x4_t tab, uint8x8_t idx)
+{
+ return vtbl4_p8 (tab, idx);
+}
+
+int8x8_t
+tb_tests8_ (int8x8_t r, int8x8_t tab, int8x8_t idx)
+{
+ return vtbx1_s8 (r, tab, idx);
+}
+
+uint8x8_t
+tb_testu8_ (uint8x8_t r, uint8x8_t tab, uint8x8_t idx)
+{
+ return vtbx1_u8 (r, tab, idx);
+}
+
+poly8x8_t
+tb_testp8_ (poly8x8_t r, poly8x8_t tab, uint8x8_t idx)
+{
+ return vtbx1_p8 (r, tab, idx);
+}
+
+int8x8_t
+tb_tests8_2 (int8x8_t r, int8x8x2_t tab, int8x8_t idx)
+{
+ return vtbx2_s8 (r, tab, idx);
+}
+
+uint8x8_t
+tb_testu8_2 (uint8x8_t r, uint8x8x2_t tab, uint8x8_t idx)
+{
+ return vtbx2_u8 (r, tab, idx);
+}
+
+poly8x8_t
+tb_testp8_2 (poly8x8_t r, poly8x8x2_t tab, uint8x8_t idx)
+{
+ return vtbx2_p8 (r, tab, idx);
+}
+
+int8x8_t
+tb_tests8_3 (int8x8_t r, int8x8x3_t tab, int8x8_t idx)
+{
+ return vtbx3_s8 (r, tab, idx);
+}
+
+uint8x8_t
+tb_testu8_3 (uint8x8_t r, uint8x8x3_t tab, uint8x8_t idx)
+{
+ return vtbx3_u8 (r, tab, idx);
+}
+
+poly8x8_t
+tb_testp8_3 (poly8x8_t r, poly8x8x3_t tab, uint8x8_t idx)
+{
+ return vtbx3_p8 (r, tab, idx);
+}
+
+int8x8_t
+tb_tests8_4 (int8x8_t r, int8x8x4_t tab, int8x8_t idx)
+{
+ return vtbx4_s8 (r, tab, idx);
+}
+
+uint8x8_t
+tb_testu8_4 (uint8x8_t r, uint8x8x4_t tab, uint8x8_t idx)
+{
+ return vtbx4_u8 (r, tab, idx);
+}
+
+poly8x8_t
+tb_testp8_4 (poly8x8_t r, poly8x8x4_t tab, uint8x8_t idx)
+{
+ return vtbx4_p8 (r, tab, idx);
+}
+
+int8x8_t
+qtbl_tests8_ (int8x16_t tab, uint8x8_t idx)
+{
+ return vqtbl1_s8 (tab, idx);
+}
+
+uint8x8_t
+qtbl_testu8_ (uint8x16_t tab, uint8x8_t idx)
+{
+ return vqtbl1_u8 (tab, idx);
+}
+
+poly8x8_t
+qtbl_testp8_ (poly8x16_t tab, uint8x8_t idx)
+{
+ return vqtbl1_p8 (tab, idx);
+}
+
+int8x8_t
+qtbl_tests8_2 (int8x16x2_t tab, uint8x8_t idx)
+{
+ return vqtbl2_s8 (tab, idx);
+}
+
+uint8x8_t
+qtbl_testu8_2 (uint8x16x2_t tab, uint8x8_t idx)
+{
+ return vqtbl2_u8 (tab, idx);
+}
+
+poly8x8_t
+qtbl_testp8_2 (poly8x16x2_t tab, uint8x8_t idx)
+{
+ return vqtbl2_p8 (tab, idx);
+}
+
+int8x8_t
+qtbl_tests8_3 (int8x16x3_t tab, uint8x8_t idx)
+{
+ return vqtbl3_s8 (tab, idx);
+}
+
+uint8x8_t
+qtbl_testu8_3 (uint8x16x3_t tab, uint8x8_t idx)
+{
+ return vqtbl3_u8 (tab, idx);
+}
+
+poly8x8_t
+qtbl_testp8_3 (poly8x16x3_t tab, uint8x8_t idx)
+{
+ return vqtbl3_p8 (tab, idx);
+}
+
+int8x8_t
+qtbl_tests8_4 (int8x16x4_t tab, uint8x8_t idx)
+{
+ return vqtbl4_s8 (tab, idx);
+}
+
+uint8x8_t
+qtbl_testu8_4 (uint8x16x4_t tab, uint8x8_t idx)
+{
+ return vqtbl4_u8 (tab, idx);
+}
+
+poly8x8_t
+qtbl_testp8_4 (poly8x16x4_t tab, uint8x8_t idx)
+{
+ return vqtbl4_p8 (tab, idx);
+}
+
+int8x8_t
+qtb_tests8_ (int8x8_t r, int8x16_t tab, uint8x8_t idx)
+{
+ return vqtbx1_s8 (r, tab, idx);
+}
+
+uint8x8_t
+qtb_testu8_ (uint8x8_t r, uint8x16_t tab, uint8x8_t idx)
+{
+ return vqtbx1_u8 (r, tab, idx);
+}
+
+poly8x8_t
+qtb_testp8_ (poly8x8_t r, poly8x16_t tab, uint8x8_t idx)
+{
+ return vqtbx1_p8 (r, tab, idx);
+}
+
+int8x8_t
+qtb_tests8_2 (int8x8_t r, int8x16x2_t tab, uint8x8_t idx)
+{
+ return vqtbx2_s8 (r, tab, idx);
+}
+
+uint8x8_t
+qtb_testu8_2 (uint8x8_t r, uint8x16x2_t tab, uint8x8_t idx)
+{
+ return vqtbx2_u8 (r, tab, idx);
+}
+
+poly8x8_t
+qtb_testp8_2 (poly8x8_t r, poly8x16x2_t tab, uint8x8_t idx)
+{
+ return vqtbx2_p8 (r, tab, idx);
+}
+
+int8x8_t
+qtb_tests8_3 (int8x8_t r, int8x16x3_t tab, uint8x8_t idx)
+{
+ return vqtbx3_s8 (r, tab, idx);
+}
+
+uint8x8_t
+qtb_testu8_3 (uint8x8_t r, uint8x16x3_t tab, uint8x8_t idx)
+{
+ return vqtbx3_u8 (r, tab, idx);
+}
+
+poly8x8_t
+qtb_testp8_3 (poly8x8_t r, poly8x16x3_t tab, uint8x8_t idx)
+{
+ return vqtbx3_p8 (r, tab, idx);
+}
+
+int8x8_t
+qtb_tests8_4 (int8x8_t r, int8x16x4_t tab, uint8x8_t idx)
+{
+ return vqtbx4_s8 (r, tab, idx);
+}
+
+uint8x8_t
+qtb_testu8_4 (uint8x8_t r, uint8x16x4_t tab, uint8x8_t idx)
+{
+ return vqtbx4_u8 (r, tab, idx);
+}
+
+poly8x8_t
+qtb_testp8_4 (poly8x8_t r, poly8x16x4_t tab, uint8x8_t idx)
+{
+ return vqtbx4_p8 (r, tab, idx);
+}
+
+int8x16_t
+qtblq_tests8_ (int8x16_t tab, uint8x16_t idx)
+{
+ return vqtbl1q_s8 (tab, idx);
+}
+
+uint8x16_t
+qtblq_testu8_ (uint8x16_t tab, uint8x16_t idx)
+{
+ return vqtbl1q_u8 (tab, idx);
+}
+
+poly8x16_t
+qtblq_testp8_ (poly8x16_t tab, uint8x16_t idx)
+{
+ return vqtbl1q_p8 (tab, idx);
+}
+
+int8x16_t
+qtblq_tests8_2 (int8x16x2_t tab, uint8x16_t idx)
+{
+ return vqtbl2q_s8 (tab, idx);
+}
+
+uint8x16_t
+qtblq_testu8_2 (uint8x16x2_t tab, uint8x16_t idx)
+{
+ return vqtbl2q_u8 (tab, idx);
+}
+
+poly8x16_t
+qtblq_testp8_2 (poly8x16x2_t tab, uint8x16_t idx)
+{
+ return vqtbl2q_p8 (tab, idx);
+}
+
+int8x16_t
+qtblq_tests8_3 (int8x16x3_t tab, uint8x16_t idx)
+{
+ return vqtbl3q_s8 (tab, idx);
+}
+
+uint8x16_t
+qtblq_testu8_3 (uint8x16x3_t tab, uint8x16_t idx)
+{
+ return vqtbl3q_u8 (tab, idx);
+}
+
+poly8x16_t
+qtblq_testp8_3 (poly8x16x3_t tab, uint8x16_t idx)
+{
+ return vqtbl3q_p8 (tab, idx);
+}
+
+int8x16_t
+qtblq_tests8_4 (int8x16x4_t tab, uint8x16_t idx)
+{
+ return vqtbl4q_s8 (tab, idx);
+}
+
+uint8x16_t
+qtblq_testu8_4 (uint8x16x4_t tab, uint8x16_t idx)
+{
+ return vqtbl4q_u8 (tab, idx);
+}
+
+poly8x16_t
+qtblq_testp8_4 (poly8x16x4_t tab, uint8x16_t idx)
+{
+ return vqtbl4q_p8 (tab, idx);
+}
+
+int8x16_t
+qtbxq_tests8_ (int8x16_t r, int8x16_t tab, uint8x16_t idx)
+{
+ return vqtbx1q_s8 (r, tab, idx);
+}
+
+uint8x16_t
+qtbxq_testu8_ (uint8x16_t r, uint8x16_t tab, uint8x16_t idx)
+{
+ return vqtbx1q_u8 (r, tab, idx);
+}
+
+poly8x16_t
+qtbxq_testp8_ (poly8x16_t r, poly8x16_t tab, uint8x16_t idx)
+{
+ return vqtbx1q_p8 (r, tab, idx);
+}
+
+int8x16_t
+qtbxq_tests8_2 (int8x16_t r, int8x16x2_t tab, uint8x16_t idx)
+{
+ return vqtbx2q_s8 (r, tab, idx);
+}
+
+uint8x16_t
+qtbxq_testu8_2 (uint8x16_t r, uint8x16x2_t tab, uint8x16_t idx)
+{
+ return vqtbx2q_u8 (r, tab, idx);
+}
+
+poly8x16_t
+qtbxq_testp8_2 (poly8x16_t r, poly8x16x2_t tab, uint8x16_t idx)
+{
+ return vqtbx2q_p8 (r, tab, idx);
+}
+
+int8x16_t
+qtbxq_tests8_3 (int8x16_t r, int8x16x3_t tab, uint8x16_t idx)
+{
+ return vqtbx3q_s8 (r, tab, idx);
+}
+
+uint8x16_t
+qtbxq_testu8_3 (uint8x16_t r, uint8x16x3_t tab, uint8x16_t idx)
+{
+ return vqtbx3q_u8 (r, tab, idx);
+}
+
+poly8x16_t
+qtbxq_testp8_3 (poly8x16_t r, poly8x16x3_t tab, uint8x16_t idx)
+{
+ return vqtbx3q_p8 (r, tab, idx);
+}
+
+int8x16_t
+qtbxq_tests8_4 (int8x16_t r, int8x16x4_t tab, uint8x16_t idx)
+{
+ return vqtbx4q_s8 (r, tab, idx);
+}
+
+uint8x16_t
+qtbxq_testu8_4 (uint8x16_t r, uint8x16x4_t tab, uint8x16_t idx)
+{
+ return vqtbx4q_u8 (r, tab, idx);
+}
+
+poly8x16_t
+qtbxq_testp8_4 (poly8x16_t r, poly8x16x4_t tab, uint8x16_t idx)
+{
+ return vqtbx4q_p8 (r, tab, idx);
+}
+
+/* { dg-final { scan-assembler-times "tbl v" 42} } */
+/* { dg-final { scan-assembler-times "tbx v" 30} } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-1.c
new file mode 100644
index 0000000..e44ca6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-1.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-no-clobber-lr.c"
+
+/* omit-frame-pointer is FALSE.
+ omit-leaf-frame-pointer is FALSE.
+ LR is not being clobbered in the leaf.
+
+ With no frame pointer omissions, we expect a frame record
+ for main and the leaf. */
+
+/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-2.c
new file mode 100644
index 0000000..40e4835
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-2.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fomit-frame-pointer -mno-omit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-no-clobber-lr.c"
+
+/* omit-frame-pointer is TRUE.
+ omit-leaf-frame-pointer is false, but irrelevant due to omit-frame-pointer.
+ LR is not being clobbered in the leaf.
+
+ Since we asked to have no frame pointers anywhere, we expect no frame
+ record in main or the leaf. */
+
+/* { dg-final { scan-assembler-not "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-3.c
new file mode 100644
index 0000000..98cb2e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-3.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fomit-frame-pointer -momit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-no-clobber-lr.c"
+
+/* omit-frame-pointer is TRUE.
+ omit-leaf-frame-pointer is true, but irrelevant due to omit-frame-pointer.
+ LR is not being clobbered in the leaf.
+
+ Since we asked to have no frame pointers anywhere, we expect no frame
+ record in main or the leaf. */
+
+/* { dg-final { scan-assembler-not "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-4.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-4.c
new file mode 100644
index 0000000..4143a7a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-4.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -momit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-no-clobber-lr.c"
+
+/* omit-frame-pointer is FALSE.
+ omit-leaf-frame-pointer is TRUE.
+ LR is not being clobbered in the leaf.
+
+ Unless we are removing all frame records, it's OK to remove the frame
+ record for a leaf where LR is not clobbered. Therefore, we expect a
+ frame record only in main. */
+
+/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-5.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-5.c
new file mode 100644
index 0000000..c22bdc3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-5.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-clobber-lr.c"
+
+/* omit-frame-pointer is FALSE.
+ omit-leaf-frame-pointer is FALSE.
+ LR is being clobbered in the leaf.
+
+ With no frame pointer omissions, we expect a frame record for main
+ and the leaf. */
+
+/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-6.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-6.c
new file mode 100644
index 0000000..e08ee43
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-6.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fomit-frame-pointer -mno-omit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-clobber-lr.c"
+
+/* omit-frame-pointer is TRUE.
+ omit-leaf-frame-pointer is false, but irrelevant due to omit-frame-pointer.
+ LR is being clobbered in the leaf.
+
+ Since we asked to have no frame pointers anywhere, we expect no frame
+ record in main or the leaf. */
+
+/* { dg-final { scan-assembler-not "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-7.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-7.c
new file mode 100644
index 0000000..e8f7cab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-7.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fomit-frame-pointer -momit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-clobber-lr.c"
+
+/* omit-frame-pointer is TRUE.
+ omit-leaf-frame-pointer is true, but irrelevant due to omit-frame-pointer.
+ LR is being clobbered in the leaf.
+
+ Since we asked to have no frame pointers anywhere, we expect no frame
+ record in main or the leaf. */
+
+/* { dg-final { scan-assembler-not "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-8.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-8.c
new file mode 100644
index 0000000..c09b687
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-8.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -momit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-clobber-lr.c"
+
+/* omit-frame-pointer is FALSE.
+ omit-leaf-frame-pointer is TRUE.
+ LR is being clobbered in the leaf.
+
+ Unless we are removing all frame records (which we aren't), it's
+ not OK to remove the frame record for a leaf where LR is clobbered.
+ Therefore, we expect a frame record in main and leaf. */
+
+/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-ptr-arg-on-stack-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-ptr-arg-on-stack-1.c
new file mode 100644
index 0000000..bb68e0a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-ptr-arg-on-stack-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-inline" } */
+
+/* Test pass-by-reference and pointer-typed argument passing on stack.
+ This test shall pass on any of the following four combinitions:
+ {big-endian, little-endian} {LP64, ILP32}. */
+
+struct s5
+{
+ double a;
+ double b;
+ double c;
+ double d;
+ double e;
+} gS = {1.0, 2.0, 3.0, 4.0, 5.0};
+
+double __attribute__ ((noinline))
+foo (struct s5 p1, struct s5 p2, struct s5 p3, struct s5 p4,
+ struct s5 p5, struct s5 p6, struct s5 p7, struct s5 p8,
+ struct s5 p9)
+{
+ asm ("");
+ return p9.c;
+}
+
+void abort (void);
+int printf (const char *, ...);
+
+int main (void)
+{
+ printf ("Here we print out some values and more importantly hope that"
+ " the stack is getting a bit dirty for the bug to manifest itself"
+ "\n\t%f, %f, %f, %f, %f\n", gS.a, gS.b, gS.c, gS.d, gS.e);
+
+ if (foo (gS, gS, gS, gS, gS, gS, gS, gS, gS) != 3.0)
+ abort ();
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst-1.c
new file mode 100644
index 0000000..b37c522
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst-1.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+volatile unsigned int w0, w1;
+volatile int result;
+
+void test_si() {
+ /* { dg-final { scan-assembler "tst\tw\[0-9\]*, w\[0-9\]*\n" } } */
+ result = !(w0 & w1);
+ /* { dg-final { scan-assembler "tst\tw\[0-9\]*, \(0x\[0-9a-fA-F\]+\)|\(\[0-9\]+\)" } } */
+ result = !(w0 & 0x00f0);
+ /* { dg-final { scan-assembler "tst\tw\[0-9\]*.*lsl 4" } } */
+ result = !(w0 & (w1 << 4));
+}
+
+void test_si_tbnz() {
+ /* { dg-final { scan-assembler "tbnz\t\[wx\]\[0-9\]*" } } */
+jumpto:
+ if (w0 & 0x08) goto jumpto;
+}
+
+void test_si_tbz() {
+ /* { dg-final { scan-assembler "tbz\t\[wx\]\[0-9\]*" } } */
+jumpto:
+ if (!(w1 & 0x08)) goto jumpto;
+}
+
+volatile unsigned long long x0, x1;
+
+void test_di() {
+ /* { dg-final { scan-assembler "tst\tx\[0-9\]*, x\[0-9\]*\n" } } */
+ result = !(x0 & x1);
+ /* { dg-final { scan-assembler "tst\tx\[0-9\]*, \(0x\[0-9a-fA-F\]+\)|\(\[0-9\]+\)" } } */
+ result = !(x0 & 0x00f0);
+ /* { dg-final { scan-assembler "tst\tx\[0-9\]*.*lsl 4" } } */
+ result = !(x0 & (x1 << 4));
+}
+
+void test_di_tbnz() {
+ /* { dg-final { scan-assembler "tbnz\tx\[0-9\]*" } } */
+jumpto:
+ if (x0 & 0x08) goto jumpto;
+}
+
+void test_di_tbz() {
+ /* { dg-final { scan-assembler "tbz\tx\[0-9\]*" } } */
+jumpto:
+ if (!(x1 & 0x08)) goto jumpto;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst_1.c
new file mode 100644
index 0000000..4838b1b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst_1.c
@@ -0,0 +1,150 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+tst_si_test1 (int a, int b, int c)
+{
+ int d = a & b;
+
+ /* { dg-final { scan-assembler-times "tst\tw\[0-9\]+, w\[0-9\]+" 2 } } */
+ if (d == 0)
+ return 12;
+ else
+ return 18;
+}
+
+int
+tst_si_test2 (int a, int b, int c)
+{
+ int d = a & 0x99999999;
+
+ /* { dg-final { scan-assembler "tst\tw\[0-9\]+, -1717986919" } } */
+ if (d == 0)
+ return 12;
+ else
+ return 18;
+}
+
+int
+tst_si_test3 (int a, int b, int c)
+{
+ int d = a & (b << 3);
+
+ /* { dg-final { scan-assembler "tst\tw\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ if (d == 0)
+ return 12;
+ else
+ return 18;
+}
+
+typedef long long s64;
+
+s64
+tst_di_test1 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & b;
+
+ /* { dg-final { scan-assembler-times "tst\tx\[0-9\]+, x\[0-9\]+" 2 } } */
+ if (d == 0)
+ return 12;
+ else
+ return 18;
+}
+
+s64
+tst_di_test2 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & 0xaaaaaaaaaaaaaaaall;
+
+ /* { dg-final { scan-assembler "tst\tx\[0-9\]+, -6148914691236517206" } } */
+ if (d == 0)
+ return 12;
+ else
+ return 18;
+}
+
+s64
+tst_di_test3 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & (b << 3);
+
+ /* { dg-final { scan-assembler "tst\tx\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ if (d == 0)
+ return 12;
+ else
+ return 18;
+}
+
+int
+main ()
+{
+ int x;
+ s64 y;
+
+ x = tst_si_test1 (29, 4, 5);
+ if (x != 18)
+ abort ();
+
+ x = tst_si_test1 (5, 2, 20);
+ if (x != 12)
+ abort ();
+
+ x = tst_si_test2 (29, 4, 5);
+ if (x != 18)
+ abort ();
+
+ x = tst_si_test2 (1024, 2, 20);
+ if (x != 12)
+ abort ();
+
+ x = tst_si_test3 (35, 4, 5);
+ if (x != 18)
+ abort ();
+
+ x = tst_si_test3 (5, 2, 20);
+ if (x != 12)
+ abort ();
+
+ y = tst_di_test1 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+
+ if (y != 18)
+ abort ();
+
+ y = tst_di_test1 (0x5000500050005ll,
+ 0x2111211121112ll,
+ 0x0000000002020ll);
+ if (y != 12)
+ abort ();
+
+ y = tst_di_test2 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+ if (y != 18)
+ abort ();
+
+ y = tst_di_test2 (0x540004100ll,
+ 0x320000004ll,
+ 0x805050205ll);
+ if (y != 12)
+ abort ();
+
+ y = tst_di_test3 (0x130000029ll,
+ 0x064000008ll,
+ 0x505050505ll);
+ if (y != 18)
+ abort ();
+
+ y = tst_di_test3 (0x130002900ll,
+ 0x088000008ll,
+ 0x505050505ll);
+ if (y != 12)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst_2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst_2.c
new file mode 100644
index 0000000..1e80904
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst_2.c
@@ -0,0 +1,156 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+tst_si_test1 (int a, int b, int c)
+{
+ int d = a & b;
+
+ /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+ /* { dg-final { scan-assembler-times "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+ if (d <= 0)
+ return 12;
+ else
+ return 18;
+}
+
+int
+tst_si_test2 (int a, int b, int c)
+{
+ int d = a & 0x99999999;
+
+ /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
+ /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
+ if (d <= 0)
+ return 12;
+ else
+ return 18;
+}
+
+int
+tst_si_test3 (int a, int b, int c)
+{
+ int d = a & (b << 3);
+
+ /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+ if (d <= 0)
+ return 12;
+ else
+ return 18;
+}
+
+typedef long long s64;
+
+s64
+tst_di_test1 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & b;
+
+ /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+ /* { dg-final { scan-assembler-times "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+ if (d <= 0)
+ return 12;
+ else
+ return 18;
+}
+
+s64
+tst_di_test2 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & 0xaaaaaaaaaaaaaaaall;
+
+ /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
+ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
+ if (d <= 0)
+ return 12;
+ else
+ return 18;
+}
+
+s64
+tst_di_test3 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & (b << 3);
+
+ /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+ if (d <= 0)
+ return 12;
+ else
+ return 18;
+}
+
+int
+main ()
+{
+ int x;
+ s64 y;
+
+ x = tst_si_test1 (29, 4, 5);
+ if (x != 18)
+ abort ();
+
+ x = tst_si_test1 (5, 2, 20);
+ if (x != 12)
+ abort ();
+
+ x = tst_si_test2 (29, 4, 5);
+ if (x != 18)
+ abort ();
+
+ x = tst_si_test2 (1024, 2, 20);
+ if (x != 12)
+ abort ();
+
+ x = tst_si_test3 (35, 4, 5);
+ if (x != 18)
+ abort ();
+
+ x = tst_si_test3 (5, 2, 20);
+ if (x != 12)
+ abort ();
+
+ y = tst_di_test1 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+
+ if (y != 18)
+ abort ();
+
+ y = tst_di_test1 (0x5000500050005ll,
+ 0x2111211121112ll,
+ 0x0000000002020ll);
+ if (y != 12)
+ abort ();
+
+ y = tst_di_test2 (0x130000029ll,
+ 0x320000004ll,
+ 0x505050505ll);
+ if (y != 18)
+ abort ();
+
+ y = tst_di_test2 (0x540004100ll,
+ 0x320000004ll,
+ 0x805050205ll);
+ if (y != 12)
+ abort ();
+
+ y = tst_di_test3 (0x130000029ll,
+ 0x064000008ll,
+ 0x505050505ll);
+ if (y != 18)
+ abort ();
+
+ y = tst_di_test3 (0x130002900ll,
+ 0x088000008ll,
+ 0x505050505ll);
+ if (y != 12)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ushr64_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ushr64_1.c
new file mode 100644
index 0000000..b1c741d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ushr64_1.c
@@ -0,0 +1,84 @@
+/* Test logical SIMD shift works correctly. */
+/* { dg-do run } */
+/* { dg-options "--save-temps" } */
+
+#include "arm_neon.h"
+
+extern void abort (void);
+
+int __attribute__ ((noinline))
+test_vshr_n_u64_64 (uint64x1_t passed, uint64_t expected)
+{
+ return vget_lane_u64 (vshr_n_u64 (passed, 64), 0) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vshr_n_u64_4 (uint64x1_t passed, uint64_t expected)
+{
+ return vget_lane_u64 (vshr_n_u64 (passed, 4), 0) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vshr_n_u64_0 (uint64x1_t passed, uint64_t expected)
+{
+ return vget_lane_u64 (vshr_n_u64 (passed, 0), 0) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vshrd_n_u64_64 (uint64_t passed, uint64_t expected)
+{
+ return vshrd_n_u64 (passed, 64) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vshrd_n_u64_4 (uint64_t passed, uint64_t expected)
+{
+ return vshrd_n_u64 (passed, 4) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vshrd_n_u64_0 (uint64_t passed, uint64_t expected)
+{
+ return vshrd_n_u64 (passed, 0) != expected;
+}
+
+/* { dg-final { scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 64" 2 } } */
+/* { dg-final { (scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 4" 2) || \
+ (scan-assembler-times "lsr\\tx\[0-9\]+, x\[0-9\]+, 4" 2) } } */
+/* { dg-final { scan-assembler-not "ushr\\td\[0-9\]+, d\[0-9\]+, 0" } } */
+
+int
+main (int argc, char *argv[])
+{
+ /* Testing vshr_n_u64. */
+ if (test_vshr_n_u64_64 (vcreate_u64 (0x0000000080000000), 0))
+ abort ();
+ if (test_vshr_n_u64_64 (vcreate_u64 (0xffffffff80000000), 0))
+ abort ();
+
+ if (test_vshr_n_u64_4 (vcreate_u64 (0x0000000080000000), 0x0000000008000000))
+ abort ();
+ if (test_vshr_n_u64_4 (vcreate_u64 (0xffffffff80000000), 0x0ffffffff8000000))
+ abort ();
+
+ if (test_vshr_n_u64_0 (vcreate_u64 (0x0000000080000000), 0x0000000080000000))
+ abort ();
+
+ /* Testing vshrd_n_u64. */
+ if (test_vshrd_n_u64_64 (0x0000000080000000, 0))
+ abort ();
+ if (test_vshrd_n_u64_64 (0xffffffff80000000, 0))
+ abort ();
+
+ if (test_vshrd_n_u64_4 (0x0000000080000000, 0x0000000008000000))
+ abort ();
+ if (test_vshrd_n_u64_4 (0xffffffff80000000, 0x0ffffffff8000000))
+ abort ();
+
+ if (test_vshrd_n_u64_0 (0x0000000080000000, 0x0000000080000000))
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vabs_intrinsic_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vabs_intrinsic_1.c
new file mode 100644
index 0000000..b34738c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vabs_intrinsic_1.c
@@ -0,0 +1,101 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+
+#define ETYPE(size) int##size##_t
+#define VTYPE(size, lanes) int##size##x##lanes##_t
+
+#define TEST_VABS(q, size, lanes) \
+static void \
+test_vabs##q##_##size (ETYPE (size) * res, \
+ const ETYPE (size) *in1) \
+{ \
+ VTYPE (size, lanes) a = vld1##q##_s##size (res); \
+ VTYPE (size, lanes) b = vld1##q##_s##size (in1); \
+ a = vabs##q##_s##size (b); \
+ vst1##q##_s##size (res, a); \
+}
+
+#define BUILD_VARS(width, n_lanes, n_half_lanes) \
+TEST_VABS (, width, n_half_lanes) \
+TEST_VABS (q, width, n_lanes) \
+
+BUILD_VARS (64, 2, 1)
+BUILD_VARS (32, 4, 2)
+BUILD_VARS (16, 8, 4)
+BUILD_VARS (8, 16, 8)
+
+#define POOL1 {-10}
+#define POOL2 {2, -10}
+#define POOL4 {0, -10, 2, -3}
+#define POOL8 {0, -10, 2, -3, 4, -50, 6, -70}
+#define POOL16 {0, -10, 2, -3, 4, -50, 6, -70, \
+ -5, 10, -2, 3, -4, 50, -6, 70}
+
+#define EXPECTED1 {10}
+#define EXPECTED2 {2, 10}
+#define EXPECTED4 {0, 10, 2, 3}
+#define EXPECTED8 {0, 10, 2, 3, 4, 50, 6, 70}
+#define EXPECTED16 {0, 10, 2, 3, 4, 50, 6, 70, \
+ 5, 10, 2, 3, 4, 50, 6, 70}
+
+#define BUILD_TEST(size, lanes_64, lanes_128) \
+static void \
+test_##size (void) \
+{ \
+ int i; \
+ ETYPE (size) pool1[lanes_64] = POOL##lanes_64; \
+ ETYPE (size) res1[lanes_64] = {0}; \
+ ETYPE (size) expected1[lanes_64] = EXPECTED##lanes_64; \
+ ETYPE (size) pool2[lanes_128] = POOL##lanes_128; \
+ ETYPE (size) res2[lanes_128] = {0}; \
+ ETYPE (size) expected2[lanes_128] = EXPECTED##lanes_128; \
+ \
+ /* Forcefully avoid optimization. */ \
+ asm volatile ("" : : : "memory"); \
+ test_vabs_##size (res1, pool1); \
+ for (i = 0; i < lanes_64; i++) \
+ if (res1[i] != expected1[i]) \
+ abort (); \
+ \
+ /* Forcefully avoid optimization. */ \
+ asm volatile ("" : : : "memory"); \
+ test_vabsq_##size (res2, pool2); \
+ for (i = 0; i < lanes_128; i++) \
+ if (res2[i] != expected2[i]) \
+ abort (); \
+}
+
+/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */
+/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+BUILD_TEST (8 , 8, 16)
+
+/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.4h, v\[0-9\]+\.4h" 1 } } */
+/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+BUILD_TEST (16, 4, 8)
+
+/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */
+/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+BUILD_TEST (32, 2, 4)
+
+/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
+BUILD_TEST (64, 1, 2)
+
+#undef BUILD_TEST
+
+#define BUILD_TEST(size) test_##size ()
+
+int
+main (int argc, char **argv)
+{
+ BUILD_TEST (8);
+ BUILD_TEST (16);
+ BUILD_TEST (32);
+ BUILD_TEST (64);
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vadd_f64.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vadd_f64.c
new file mode 100644
index 0000000..c3bf734
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vadd_f64.c
@@ -0,0 +1,114 @@
+/* Test vadd works correctly. */
+/* { dg-do run } */
+/* { dg-options "--save-temps" } */
+
+#include <arm_neon.h>
+
+#define FLT_EPSILON __FLT_EPSILON__
+#define DBL_EPSILON __DBL_EPSILON__
+
+#define TESTA0 0.33333
+#define TESTA1 -1.7777
+#define TESTA2 0
+#define TESTA3 1.23456
+/* 2^54, double has 53 significand bits
+ according to Double-precision floating-point format. */
+#define TESTA4 18014398509481984
+#define TESTA5 (1.0 / TESTA4)
+
+#define TESTB0 0.66667
+#define TESTB1 2
+#define TESTB2 0
+#define TESTB3 -2
+#define TESTB4 1.0
+#define TESTB5 2.0
+
+#define ANSW0 1
+#define ANSW1 0.2223
+#define ANSW2 0
+#define ANSW3 -0.76544
+#define ANSW4 TESTA4
+#define ANSW5 2.0
+
+extern void abort (void);
+
+#define EPSILON __DBL_EPSILON__
+#define ABS(a) __builtin_fabs (a)
+#define ISNAN(a) __builtin_isnan (a)
+#define FP_equals(a, b, epsilon) \
+ ( \
+ ((a) == (b)) \
+ || (ISNAN (a) && ISNAN (b)) \
+ || (ABS (a - b) < epsilon) \
+ )
+
+int
+test_vadd_f64 ()
+{
+ float64x1_t a;
+ float64x1_t b;
+ float64x1_t c;
+
+ a = TESTA0;
+ b = TESTB0;
+ c = ANSW0;
+
+ a = vadd_f64 (a, b);
+ if (!FP_equals (a, c, EPSILON))
+ return 1;
+
+ a = TESTA1;
+ b = TESTB1;
+ c = ANSW1;
+
+ a = vadd_f64 (a, b);
+ if (!FP_equals (a, c, EPSILON))
+ return 1;
+
+ a = TESTA2;
+ b = TESTB2;
+ c = ANSW2;
+
+ a = vadd_f64 (a, b);
+ if (!FP_equals (a, c, EPSILON))
+ return 1;
+
+ a = TESTA3;
+ b = TESTB3;
+ c = ANSW3;
+
+ a = vadd_f64 (a, b);
+ if (!FP_equals (a, c, EPSILON))
+ return 1;
+
+ a = TESTA4;
+ b = TESTB4;
+ c = ANSW4;
+
+ a = vadd_f64 (a, b);
+ if (!FP_equals (a, c, EPSILON))
+ return 1;
+
+ a = TESTA5;
+ b = TESTB5;
+ c = ANSW5;
+
+ a = vadd_f64 (a, b);
+ if (!FP_equals (a, c, EPSILON))
+ return 1;
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "fadd\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 6 } } */
+
+int
+main (int argc, char **argv)
+{
+ if (test_vadd_f64 ())
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic-compile.c
new file mode 100644
index 0000000..11fa984
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic-compile.c
@@ -0,0 +1,11 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#include "arm_neon.h"
+
+#include "vaddv-intrinsic.x"
+
+/* { dg-final { scan-assembler "faddp\\ts\[0-9\]+"} } */
+/* { dg-final { scan-assembler-times "faddp\\tv\[0-9\]+\.4s" 2} } */
+/* { dg-final { scan-assembler "faddp\\td\[0-9\]+"} } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.c
new file mode 100644
index 0000000..f6e0829
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.c
@@ -0,0 +1,28 @@
+
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#include "arm_neon.h"
+
+extern void abort (void);
+
+#include "vaddv-intrinsic.x"
+
+int
+main (void)
+{
+ const float32_t pool_v2sf[] = {4.0f, 9.0f};
+ const float32_t pool_v4sf[] = {4.0f, 9.0f, 16.0f, 25.0f};
+ const float64_t pool_v2df[] = {4.0, 9.0};
+
+ if (test_vaddv_v2sf (pool_v2sf) != 13.0f)
+ abort ();
+
+ if (test_vaddv_v4sf (pool_v4sf) != 54.0f)
+ abort ();
+
+ if (test_vaddv_v2df (pool_v2df) != 13.0)
+ abort ();
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.x
new file mode 100644
index 0000000..7bf38ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.x
@@ -0,0 +1,27 @@
+
+float32_t
+test_vaddv_v2sf (const float32_t *pool)
+{
+ float32x2_t val;
+
+ val = vld1_f32 (pool);
+ return vaddv_f32 (val);
+}
+
+float32_t
+test_vaddv_v4sf (const float32_t *pool)
+{
+ float32x4_t val;
+
+ val = vld1q_f32 (pool);
+ return vaddvq_f32 (val);
+}
+
+float64_t
+test_vaddv_v2df (const float64_t *pool)
+{
+ float64x2_t val;
+
+ val = vld1q_f64 (pool);
+ return vaddvq_f64 (val);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vclz.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vclz.c
new file mode 100644
index 0000000..006f80d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vclz.c
@@ -0,0 +1,574 @@
+/* Test vclz works correctly. */
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -O3 -Wno-div-by-zero --save-temps" } */
+#include <arm_neon.h>
+
+extern void abort (void);
+
+/* Tests in binary should look like:
+ 0
+ 1
+ 10
+ 101
+ 1010
+ 10101
+ etc. */
+
+#define TEST0 0
+#define TEST1 0x1
+#define TEST2 0x2
+#define TEST3 0x5
+#define TEST4 0xa
+#define TEST5 0x15
+#define TEST6 0x2a
+#define TEST7 0x55
+#define TEST8 0xaa
+#define TEST9 0x155
+#define TEST10 0x2aa
+#define TEST11 0x555
+#define TEST12 0xaaa
+#define TEST13 0x1555
+#define TEST14 0x2aaa
+#define TEST15 0x5555
+#define TEST16 0xaaaa
+#define TEST17 0x15555
+#define TEST18 0x2aaaa
+#define TEST19 0x55555
+#define TEST20 0xaaaaa
+#define TEST21 0x155555
+#define TEST22 0x2aaaaa
+#define TEST23 0x555555
+#define TEST24 0xaaaaaa
+#define TEST25 0x1555555
+#define TEST26 0x2aaaaaa
+#define TEST27 0x5555555
+#define TEST28 0xaaaaaaa
+#define TEST29 0x15555555
+#define TEST30 0x2aaaaaaa
+#define TEST31 0x55555555
+#define TEST32 0xaaaaaaaa
+
+#define INHIB_OPTIMIZATION asm volatile ("" : : : "memory")
+
+#define CONCAT(a, b) a##b
+#define CONCAT1(a, b) CONCAT (a, b)
+#define REG_INFEX64 _
+#define REG_INFEX128 q_
+#define SIGNED0 u
+#define SIGNED1 s
+#define SIGNED(x) SIGNED##x
+#define REG_INFEX(reg_len) REG_INFEX##reg_len
+#define POSTFIX(reg_len, data_len, is_signed) \
+ CONCAT1 (REG_INFEX (reg_len), CONCAT1 (SIGNED (is_signed), data_len))
+#define DATA_TYPE(data_len) DATA_TYPE_##data_len
+#define LOAD_INST(reg_len, data_len, is_signed) \
+ CONCAT1 (vld1, POSTFIX (reg_len, data_len, is_signed))
+#define CLZ_INST(reg_len, data_len, is_signed) \
+ CONCAT1 (vclz, POSTFIX (reg_len, data_len, is_signed))
+
+#define RUN_TEST(test_set, answ_set, reg_len, data_len, is_signed, n) \
+ a = LOAD_INST (reg_len, data_len, is_signed) (test_set); \
+ b = LOAD_INST (reg_len, data_len, is_signed) (answ_set); \
+ INHIB_OPTIMIZATION; \
+ a = CLZ_INST (reg_len, data_len, is_signed) (a); \
+ for (i = 0; i < n; i++) \
+ { \
+ INHIB_OPTIMIZATION; \
+ if (a [i] != b [i]) \
+ { \
+ return 1; \
+ } \
+ }
+
+int
+test_vclz_s8 ()
+{
+ int i;
+ int8x8_t a;
+ int8x8_t b;
+
+ int8_t test_set0[8] = {
+ TEST0, TEST1, TEST2, TEST3,
+ TEST4, TEST5, TEST6, TEST7
+ };
+ int8_t test_set1[8] = {
+ TEST8, TEST8, TEST8, TEST8,
+ TEST8, TEST8, TEST8, TEST8
+ };
+ int8_t answ_set0[8] = {
+ 8, 7, 6, 5,
+ 4, 3, 2, 1
+ };
+ int8_t answ_set1[8] = {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0
+ };
+ RUN_TEST (test_set0, answ_set0, 64, 8, 1, 8);
+ RUN_TEST (test_set1, answ_set1, 64, 8, 1, 1);
+
+ return 0;
+}
+
+/* Double scan-assembler-times to take account of unsigned functions. */
+/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 4 } } */
+
+int
+test_vclz_s16 ()
+{
+ int i;
+ int16x4_t a;
+ int16x4_t b;
+
+ int16_t test_set0[4] = { TEST0, TEST1, TEST2, TEST3 };
+ int16_t test_set1[4] = { TEST4, TEST5, TEST6, TEST7 };
+ int16_t test_set2[4] = { TEST8, TEST9, TEST10, TEST11 };
+ int16_t test_set3[4] = { TEST12, TEST13, TEST14, TEST15 };
+ int16_t test_set4[4] = { TEST16, TEST16, TEST16, TEST16 };
+
+ int16_t answ_set0[4] = { 16, 15, 14, 13 };
+ int16_t answ_set1[4] = { 12, 11, 10, 9 };
+ int16_t answ_set2[4] = { 8, 7, 6, 5 };
+ int16_t answ_set3[4] = { 4, 3, 2, 1 };
+ int16_t answ_set4[4] = { 0, 0, 0, 0 };
+
+ RUN_TEST (test_set0, answ_set0, 64, 16, 1, 4);
+ RUN_TEST (test_set1, answ_set1, 64, 16, 1, 4);
+ RUN_TEST (test_set2, answ_set2, 64, 16, 1, 4);
+ RUN_TEST (test_set3, answ_set3, 64, 16, 1, 4);
+ RUN_TEST (test_set4, answ_set4, 64, 16, 1, 1);
+
+ return 0;
+}
+
+/* Double scan-assembler-times to take account of unsigned functions. */
+/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.4h, v\[0-9\]+\.4h" 10} } */
+
+int
+test_vclz_s32 ()
+{
+ int i;
+ int32x2_t a;
+ int32x2_t b;
+
+ int32_t test_set0[2] = { TEST0, TEST1 };
+ int32_t test_set1[2] = { TEST2, TEST3 };
+ int32_t test_set2[2] = { TEST4, TEST5 };
+ int32_t test_set3[2] = { TEST6, TEST7 };
+ int32_t test_set4[2] = { TEST8, TEST9 };
+ int32_t test_set5[2] = { TEST10, TEST11 };
+ int32_t test_set6[2] = { TEST12, TEST13 };
+ int32_t test_set7[2] = { TEST14, TEST15 };
+ int32_t test_set8[2] = { TEST16, TEST17 };
+ int32_t test_set9[2] = { TEST18, TEST19 };
+ int32_t test_set10[2] = { TEST20, TEST21 };
+ int32_t test_set11[2] = { TEST22, TEST23 };
+ int32_t test_set12[2] = { TEST24, TEST25 };
+ int32_t test_set13[2] = { TEST26, TEST27 };
+ int32_t test_set14[2] = { TEST28, TEST29 };
+ int32_t test_set15[2] = { TEST30, TEST31 };
+ int32_t test_set16[2] = { TEST32, TEST32 };
+
+ int32_t answ_set0[2] = { 32, 31 };
+ int32_t answ_set1[2] = { 30, 29 };
+ int32_t answ_set2[2] = { 28, 27 };
+ int32_t answ_set3[2] = { 26, 25 };
+ int32_t answ_set4[2] = { 24, 23 };
+ int32_t answ_set5[2] = { 22, 21 };
+ int32_t answ_set6[2] = { 20, 19 };
+ int32_t answ_set7[2] = { 18, 17 };
+ int32_t answ_set8[2] = { 16, 15 };
+ int32_t answ_set9[2] = { 14, 13 };
+ int32_t answ_set10[2] = { 12, 11 };
+ int32_t answ_set11[2] = { 10, 9 };
+ int32_t answ_set12[2] = { 8, 7 };
+ int32_t answ_set13[2] = { 6, 5 };
+ int32_t answ_set14[2] = { 4, 3 };
+ int32_t answ_set15[2] = { 2, 1 };
+ int32_t answ_set16[2] = { 0, 0 };
+
+ RUN_TEST (test_set0, answ_set0, 64, 32, 1, 2);
+ RUN_TEST (test_set1, answ_set1, 64, 32, 1, 2);
+ RUN_TEST (test_set2, answ_set2, 64, 32, 1, 2);
+ RUN_TEST (test_set3, answ_set3, 64, 32, 1, 2);
+ RUN_TEST (test_set4, answ_set4, 64, 32, 1, 2);
+ RUN_TEST (test_set5, answ_set5, 64, 32, 1, 2);
+ RUN_TEST (test_set6, answ_set6, 64, 32, 1, 2);
+ RUN_TEST (test_set7, answ_set7, 64, 32, 1, 2);
+ RUN_TEST (test_set8, answ_set8, 64, 32, 1, 2);
+ RUN_TEST (test_set9, answ_set9, 64, 32, 1, 2);
+ RUN_TEST (test_set10, answ_set10, 64, 32, 1, 2);
+ RUN_TEST (test_set11, answ_set11, 64, 32, 1, 2);
+ RUN_TEST (test_set12, answ_set12, 64, 32, 1, 2);
+ RUN_TEST (test_set13, answ_set13, 64, 32, 1, 2);
+ RUN_TEST (test_set14, answ_set14, 64, 32, 1, 2);
+ RUN_TEST (test_set15, answ_set15, 64, 32, 1, 2);
+ RUN_TEST (test_set16, answ_set16, 64, 32, 1, 1);
+
+ return 0;
+}
+
+/* Double scan-assembler-times to take account of unsigned functions. */
+/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" 34 } } */
+
+int
+test_vclzq_s8 ()
+{
+ int i;
+ int8x16_t a;
+ int8x16_t b;
+
+ int8_t test_set0[16] = {
+ TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7,
+ TEST8, TEST8, TEST8, TEST8, TEST8, TEST8, TEST8, TEST8
+ };
+ int8_t answ_set0[16] = {
+ 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0
+ };
+ RUN_TEST (test_set0, answ_set0, 128, 8, 1, 9);
+ return 0;
+}
+
+/* Double scan-assembler-times to take account of unsigned functions. */
+/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */
+
+int
+test_vclzq_s16 ()
+{
+ int i;
+ int16x8_t a;
+ int16x8_t b;
+
+ int16_t test_set0[8] = {
+ TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7
+ };
+ int16_t test_set1[8] = {
+ TEST8, TEST9, TEST10, TEST11, TEST12, TEST13, TEST14, TEST15
+ };
+ int16_t test_set2[8] = {
+ TEST16, TEST16, TEST16, TEST16, TEST16, TEST16, TEST16, TEST16
+ };
+
+ int16_t answ_set0[8] = {
+ 16, 15, 14, 13, 12, 11, 10, 9
+ };
+ int16_t answ_set1[8] = {
+ 8, 7, 6, 5, 4, 3, 2, 1
+ };
+ int16_t answ_set2[8] = {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ };
+ RUN_TEST (test_set0, answ_set0, 128, 16, 1, 8);
+ RUN_TEST (test_set1, answ_set1, 128, 16, 1, 8);
+ RUN_TEST (test_set2, answ_set2, 128, 16, 1, 1);
+
+ return 0;
+}
+
+/* Double scan-assembler-times to take account of unsigned functions. */
+/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h" 6 } } */
+
+int
+test_vclzq_s32 ()
+{
+ int i;
+ int32x4_t a;
+ int32x4_t b;
+
+ int32_t test_set0[4] = { TEST0, TEST1, TEST2, TEST3 };
+ int32_t test_set1[4] = { TEST4, TEST5, TEST6, TEST7 };
+ int32_t test_set2[4] = { TEST8, TEST9, TEST10, TEST11 };
+ int32_t test_set3[4] = { TEST12, TEST13, TEST14, TEST15 };
+ int32_t test_set4[4] = { TEST16, TEST17, TEST18, TEST19 };
+ int32_t test_set5[4] = { TEST20, TEST21, TEST22, TEST23 };
+ int32_t test_set6[4] = { TEST24, TEST25, TEST26, TEST27 };
+ int32_t test_set7[4] = { TEST28, TEST29, TEST30, TEST31 };
+ int32_t test_set8[4] = { TEST32, TEST32, TEST32, TEST32 };
+
+ int32_t answ_set0[4] = { 32, 31, 30, 29 };
+ int32_t answ_set1[4] = { 28, 27, 26, 25 };
+ int32_t answ_set2[4] = { 24, 23, 22, 21 };
+ int32_t answ_set3[4] = { 20, 19, 18, 17 };
+ int32_t answ_set4[4] = { 16, 15, 14, 13 };
+ int32_t answ_set5[4] = { 12, 11, 10, 9 };
+ int32_t answ_set6[4] = { 8, 7, 6, 5 };
+ int32_t answ_set7[4] = { 4, 3, 2, 1 };
+ int32_t answ_set8[4] = { 0, 0, 0, 0 };
+
+ RUN_TEST (test_set0, answ_set0, 128, 32, 1, 4);
+ RUN_TEST (test_set1, answ_set1, 128, 32, 1, 4);
+ RUN_TEST (test_set2, answ_set2, 128, 32, 1, 4);
+ RUN_TEST (test_set3, answ_set3, 128, 32, 1, 4);
+ RUN_TEST (test_set4, answ_set4, 128, 32, 1, 1);
+
+ return 0;
+}
+
+/* Double scan-assembler-times to take account of unsigned functions. */
+/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" 10 } } */
+
+/* Unsigned versions. */
+
+int
+test_vclz_u8 ()
+{
+ int i;
+ uint8x8_t a;
+ uint8x8_t b;
+
+ uint8_t test_set0[8] = {
+ TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7
+ };
+ uint8_t test_set1[8] = {
+ TEST8, TEST8, TEST8, TEST8, TEST8, TEST8, TEST8, TEST8
+ };
+ uint8_t answ_set0[8] = {
+ 8, 7, 6, 5, 4, 3, 2, 1
+ };
+ uint8_t answ_set1[8] = {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ };
+
+ RUN_TEST (test_set0, answ_set0, 64, 8, 0, 8);
+ RUN_TEST (test_set1, answ_set1, 64, 8, 0, 1);
+
+ return 0;
+}
+
+/* ASM scan near test for signed version. */
+
+int
+test_vclz_u16 ()
+{
+ int i;
+ uint16x4_t a;
+ uint16x4_t b;
+
+ uint16_t test_set0[4] = { TEST0, TEST1, TEST2, TEST3 };
+ uint16_t test_set1[4] = { TEST4, TEST5, TEST6, TEST7 };
+ uint16_t test_set2[4] = { TEST8, TEST9, TEST10, TEST11 };
+ uint16_t test_set3[4] = { TEST12, TEST13, TEST14, TEST15 };
+ uint16_t test_set4[4] = { TEST16, TEST16, TEST16, TEST16 };
+
+ uint16_t answ_set0[4] = { 16, 15, 14, 13 };
+ uint16_t answ_set1[4] = { 12, 11, 10, 9 };
+ uint16_t answ_set2[4] = { 8, 7, 6, 5 };
+ uint16_t answ_set3[4] = { 4, 3, 2, 1 };
+ uint16_t answ_set4[4] = { 0, 0, 0, 0 };
+
+ RUN_TEST (test_set0, answ_set0, 64, 16, 0, 4);
+ RUN_TEST (test_set1, answ_set1, 64, 16, 0, 4);
+ RUN_TEST (test_set2, answ_set2, 64, 16, 0, 4);
+ RUN_TEST (test_set3, answ_set3, 64, 16, 0, 4);
+ RUN_TEST (test_set4, answ_set4, 64, 16, 0, 1);
+
+ return 0;
+}
+
+/* ASM scan near test for signed version. */
+
+int
+test_vclz_u32 ()
+{
+ int i;
+ uint32x2_t a;
+ uint32x2_t b;
+
+ uint32_t test_set0[2] = { TEST0, TEST1 };
+ uint32_t test_set1[2] = { TEST2, TEST3 };
+ uint32_t test_set2[2] = { TEST4, TEST5 };
+ uint32_t test_set3[2] = { TEST6, TEST7 };
+ uint32_t test_set4[2] = { TEST8, TEST9 };
+ uint32_t test_set5[2] = { TEST10, TEST11 };
+ uint32_t test_set6[2] = { TEST12, TEST13 };
+ uint32_t test_set7[2] = { TEST14, TEST15 };
+ uint32_t test_set8[2] = { TEST16, TEST17 };
+ uint32_t test_set9[2] = { TEST18, TEST19 };
+ uint32_t test_set10[2] = { TEST20, TEST21 };
+ uint32_t test_set11[2] = { TEST22, TEST23 };
+ uint32_t test_set12[2] = { TEST24, TEST25 };
+ uint32_t test_set13[2] = { TEST26, TEST27 };
+ uint32_t test_set14[2] = { TEST28, TEST29 };
+ uint32_t test_set15[2] = { TEST30, TEST31 };
+ uint32_t test_set16[2] = { TEST32, TEST32 };
+
+ uint32_t answ_set0[2] = { 32, 31 };
+ uint32_t answ_set1[2] = { 30, 29 };
+ uint32_t answ_set2[2] = { 28, 27 };
+ uint32_t answ_set3[2] = { 26, 25 };
+ uint32_t answ_set4[2] = { 24, 23 };
+ uint32_t answ_set5[2] = { 22, 21 };
+ uint32_t answ_set6[2] = { 20, 19 };
+ uint32_t answ_set7[2] = { 18, 17 };
+ uint32_t answ_set8[2] = { 16, 15 };
+ uint32_t answ_set9[2] = { 14, 13 };
+ uint32_t answ_set10[2] = { 12, 11 };
+ uint32_t answ_set11[2] = { 10, 9 };
+ uint32_t answ_set12[2] = { 8, 7 };
+ uint32_t answ_set13[2] = { 6, 5 };
+ uint32_t answ_set14[2] = { 4, 3 };
+ uint32_t answ_set15[2] = { 2, 1 };
+ uint32_t answ_set16[2] = { 0, 0 };
+
+ RUN_TEST (test_set0, answ_set0, 64, 32, 0, 2);
+ RUN_TEST (test_set1, answ_set1, 64, 32, 0, 2);
+ RUN_TEST (test_set2, answ_set2, 64, 32, 0, 2);
+ RUN_TEST (test_set3, answ_set3, 64, 32, 0, 2);
+ RUN_TEST (test_set4, answ_set4, 64, 32, 0, 2);
+ RUN_TEST (test_set5, answ_set5, 64, 32, 0, 2);
+ RUN_TEST (test_set6, answ_set6, 64, 32, 0, 2);
+ RUN_TEST (test_set7, answ_set7, 64, 32, 0, 2);
+ RUN_TEST (test_set8, answ_set8, 64, 32, 0, 2);
+ RUN_TEST (test_set9, answ_set9, 64, 32, 0, 2);
+ RUN_TEST (test_set10, answ_set10, 64, 32, 0, 2);
+ RUN_TEST (test_set11, answ_set11, 64, 32, 0, 2);
+ RUN_TEST (test_set12, answ_set12, 64, 32, 0, 2);
+ RUN_TEST (test_set13, answ_set13, 64, 32, 0, 2);
+ RUN_TEST (test_set14, answ_set14, 64, 32, 0, 2);
+ RUN_TEST (test_set15, answ_set15, 64, 32, 0, 2);
+ RUN_TEST (test_set16, answ_set16, 64, 32, 0, 1);
+
+ return 0;
+}
+
+/* ASM scan near test for signed version. */
+
+int
+test_vclzq_u8 ()
+{
+ int i;
+ uint8x16_t a;
+ uint8x16_t b;
+
+ uint8_t test_set0[16] = {
+ TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7,
+ TEST8, TEST8, TEST8, TEST8, TEST8, TEST8, TEST8, TEST8
+ };
+ uint8_t answ_set0[16] = {
+ 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0
+ };
+ RUN_TEST (test_set0, answ_set0, 128, 8, 0, 9);
+
+ return 0;
+}
+
+/* ASM scan near test for signed version. */
+
+int
+test_vclzq_u16 ()
+{
+ int i;
+ uint16x8_t a;
+ uint16x8_t b;
+
+ uint16_t test_set0[8] = {
+ TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7
+ };
+ uint16_t test_set1[8] = {
+ TEST8, TEST9, TEST10, TEST11, TEST12, TEST13, TEST14, TEST15
+ };
+ uint16_t test_set2[8] = {
+ TEST16, TEST16, TEST16, TEST16, TEST16, TEST16, TEST16, TEST16
+ };
+
+ uint16_t answ_set0[8] = {
+ 16, 15, 14, 13, 12, 11, 10, 9
+ };
+
+ uint16_t answ_set1[8] = {
+ 8, 7, 6, 5, 4, 3, 2, 1
+ };
+ uint16_t answ_set2[8] = {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ };
+
+ RUN_TEST (test_set0, answ_set0, 128, 16, 0, 8);
+ RUN_TEST (test_set1, answ_set1, 128, 16, 0, 8);
+ RUN_TEST (test_set2, answ_set2, 128, 16, 0, 1);
+
+ return 0;
+}
+
+/* ASM scan near test for signed version. */
+
+int
+test_vclzq_u32 ()
+{
+ int i;
+ uint32x4_t a;
+ uint32x4_t b;
+
+ uint32_t test_set0[4] = { TEST0, TEST1, TEST2, TEST3 };
+ uint32_t test_set1[4] = { TEST4, TEST5, TEST6, TEST7 };
+ uint32_t test_set2[4] = { TEST8, TEST9, TEST10, TEST11 };
+ uint32_t test_set3[4] = { TEST12, TEST13, TEST14, TEST15 };
+ uint32_t test_set4[4] = { TEST16, TEST17, TEST18, TEST19 };
+ uint32_t test_set5[4] = { TEST20, TEST21, TEST22, TEST23 };
+ uint32_t test_set6[4] = { TEST24, TEST25, TEST26, TEST27 };
+ uint32_t test_set7[4] = { TEST28, TEST29, TEST30, TEST31 };
+ uint32_t test_set8[4] = { TEST32, TEST32, TEST32, TEST32 };
+
+ uint32_t answ_set0[4] = { 32, 31, 30, 29 };
+ uint32_t answ_set1[4] = { 28, 27, 26, 25 };
+ uint32_t answ_set2[4] = { 24, 23, 22, 21 };
+ uint32_t answ_set3[4] = { 20, 19, 18, 17 };
+ uint32_t answ_set4[4] = { 16, 15, 14, 13 };
+ uint32_t answ_set5[4] = { 12, 11, 10, 9 };
+ uint32_t answ_set6[4] = { 8, 7, 6, 5 };
+ uint32_t answ_set7[4] = { 4, 3, 2, 1 };
+ uint32_t answ_set8[4] = { 0, 0, 0, 0 };
+
+ RUN_TEST (test_set0, answ_set0, 128, 32, 0, 4);
+ RUN_TEST (test_set1, answ_set1, 128, 32, 0, 4);
+ RUN_TEST (test_set2, answ_set2, 128, 32, 0, 4);
+ RUN_TEST (test_set3, answ_set3, 128, 32, 0, 4);
+ RUN_TEST (test_set4, answ_set4, 128, 32, 0, 1);
+
+ return 0;
+}
+
+/* ASM scan near test for signed version. */
+
+int
+main (int argc, char **argv)
+{
+
+ if (test_vclz_s8 ())
+ abort ();
+
+ if (test_vclz_s16 ())
+ abort ();
+
+ if (test_vclz_s32 ())
+ abort ();
+
+ if (test_vclzq_s8 ())
+ abort ();
+
+ if (test_vclzq_s16 ())
+ abort ();
+
+ if (test_vclzq_s32 ())
+ abort ();
+
+ if (test_vclz_u8 ())
+ abort ();
+
+ if (test_vclz_u16 ())
+ abort ();
+
+ if (test_vclz_u32 ())
+ abort ();
+
+ if (test_vclzq_u8 ())
+ abort ();
+
+ if (test_vclzq_u16 ())
+ abort ();
+
+ if (test_vclzq_u32 ())
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vdiv_f.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vdiv_f.c
new file mode 100644
index 0000000..cc3a957
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vdiv_f.c
@@ -0,0 +1,361 @@
+/* Test vdiv works correctly. */
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+#define FLT_INFINITY (__builtin_inff ())
+#define DBL_INFINITY (__builtin_inf ())
+
+#define NAN (0.0 / 0.0)
+
+#define PI 3.141592653589793
+#define PI_4 0.7853981633974483
+#define SQRT2 1.4142135623730951
+#define SQRT1_2 0.7071067811865475
+
+#define TESTA0 PI
+#define TESTA1 -PI
+#define TESTA2 PI
+#define TESTA3 -PI
+#define TESTA4 1.0
+#define TESTA5 -1.0
+#define TESTA6 1.0
+#define TESTA7 -1.0
+/* 2^25+1, float has 24 significand bits
+ according to Single-precision floating-point format. */
+#define TESTA8_FLT 33554433
+/* 2^54+1, double has 53 significand bits
+ according to Double-precision floating-point format. */
+#define TESTA8_DBL 18014398509481985
+#define TESTA9 -TESTA8
+#define TESTA10 TESTA8
+#define TESTA11 -TESTA8
+#define TESTA12 NAN
+#define TESTA13 1.0
+#define TESTA14 INFINITY
+#define TESTA15 -INFINITY
+#define TESTA16 INFINITY
+#define TESTA17 9.0
+#define TESTA18 11.0
+#define TESTA19 13.0
+
+#define TESTB0 4.0
+#define TESTB1 4.0
+#define TESTB2 -4.0
+#define TESTB3 -4.0
+#define TESTB4 SQRT2
+#define TESTB5 SQRT2
+#define TESTB6 -SQRT2
+#define TESTB7 -SQRT2
+#define TESTB8 2.0
+#define TESTB9 2.0
+#define TESTB10 -2.0
+#define TESTB11 -2.0
+#define TESTB12 3.0
+#define TESTB13 NAN
+#define TESTB14 5.0
+#define TESTB15 7.0
+#define TESTB16 INFINITY
+#define TESTB17 INFINITY
+#define TESTB18 -INFINITY
+#define TESTB19 0
+
+#define ANSW0 PI_4
+#define ANSW1 -PI_4
+#define ANSW2 -PI_4
+#define ANSW3 PI_4
+#define ANSW4 SQRT1_2
+#define ANSW5 -SQRT1_2
+#define ANSW6 -SQRT1_2
+#define ANSW7 SQRT1_2
+#define ANSW8_FLT 16777216
+#define ANSW8_DBL 9007199254740992
+#define ANSW9 -ANSW8
+#define ANSW10 -ANSW8
+#define ANSW11 ANSW8
+#define ANSW12 NAN
+#define ANSW13 NAN
+#define ANSW14 INFINITY
+#define ANSW15 -INFINITY
+#define ANSW16 NAN
+#define ANSW17 0
+#define ANSW18 0
+#define ANSW19 INFINITY
+
+#define CONCAT(a, b) a##b
+#define CONCAT1(a, b) CONCAT (a, b)
+#define REG_INFEX64 _
+#define REG_INFEX128 q_
+#define REG_INFEX(reg_len) REG_INFEX##reg_len
+#define POSTFIX(reg_len, data_len) \
+ CONCAT1 (REG_INFEX (reg_len), f##data_len)
+
+#define DATA_TYPE_32 float
+#define DATA_TYPE_64 double
+#define DATA_TYPE(data_len) DATA_TYPE_##data_len
+
+#define EPSILON_32 __FLT_EPSILON__
+#define EPSILON_64 __DBL_EPSILON__
+#define EPSILON(data_len) EPSILON_##data_len
+
+#define INDEX64_32 [i]
+#define INDEX64_64
+#define INDEX128_32 [i]
+#define INDEX128_64 [i]
+#define INDEX(reg_len, data_len) \
+ CONCAT1 (INDEX, reg_len##_##data_len)
+
+#define LOAD_INST(reg_len, data_len) \
+ CONCAT1 (vld1, POSTFIX (reg_len, data_len))
+#define DIV_INST(reg_len, data_len) \
+ CONCAT1 (vdiv, POSTFIX (reg_len, data_len))
+
+#define ABS(a) __builtin_fabs (a)
+#define ISNAN(a) __builtin_isnan (a)
+#define FP_equals(a, b, epsilon) \
+ ( \
+ ((a) == (b)) \
+ || (ISNAN (a) && ISNAN (b)) \
+ || (ABS (a - b) < epsilon) \
+ )
+
+#define INHIB_OPTIMIZATION asm volatile ("" : : : "memory")
+
+#define RUN_TEST(a, b, c, testseta, testsetb, answset, count, \
+ reg_len, data_len, n) \
+{ \
+ int i; \
+ INHIB_OPTIMIZATION; \
+ (a) = LOAD_INST (reg_len, data_len) (testseta[count]); \
+ (b) = LOAD_INST (reg_len, data_len) (testsetb[count]); \
+ (c) = LOAD_INST (reg_len, data_len) (answset[count]); \
+ INHIB_OPTIMIZATION; \
+ (a) = DIV_INST (reg_len, data_len) (a, b); \
+ for (i = 0; i < n; i++) \
+ { \
+ INHIB_OPTIMIZATION; \
+ if (!FP_equals ((a) INDEX (reg_len, data_len), \
+ (c) INDEX (reg_len, data_len), \
+ EPSILON (data_len))) \
+ return 1; \
+ } \
+}
+
+extern void abort (void);
+
+#define TESTA8 TESTA8_FLT
+#define ANSW8 ANSW8_FLT
+#define INFINITY FLT_INFINITY
+
+int
+test_vdiv_f32 ()
+{
+ int count;
+ float32x2_t a;
+ float32x2_t b;
+ float32x2_t c;
+
+ float32_t testseta[10][2] = {
+ { TESTA0, TESTA1 }, { TESTA2, TESTA3 },
+ { TESTA4, TESTA5 }, { TESTA6, TESTA7 },
+ { TESTA8, TESTA9 }, { TESTA10, TESTA11 },
+ { TESTA12, TESTA13 }, { TESTA14, TESTA15 },
+ { TESTA16, TESTA17 }, { TESTA18, TESTA19 }
+ };
+
+ float32_t testsetb[10][2] = {
+ { TESTB0, TESTB1 }, { TESTB2, TESTB3 },
+ { TESTB4, TESTB5 }, { TESTB6, TESTB7 },
+ { TESTB8, TESTB9 }, { TESTB10, TESTB11 },
+ { TESTB12, TESTB13 }, { TESTB14, TESTB15 },
+ { TESTB16, TESTB17 }, { TESTB18, TESTB19 }
+ };
+
+ float32_t answset[10][2] = {
+ { ANSW0, ANSW1 }, { ANSW2, ANSW3 },
+ { ANSW4, ANSW5 }, { ANSW6, ANSW7 },
+ { ANSW8, ANSW9 }, { ANSW10, ANSW11 },
+ { ANSW12, ANSW13 }, { ANSW14, ANSW15 },
+ { ANSW16, ANSW17 }, { ANSW18, ANSW19 }
+ };
+
+ for (count = 0; count < 10; count++)
+ {
+ RUN_TEST (a, b, c, testseta, testsetb, answset, count, 64, 32, 2);
+ }
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "fdiv\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */
+
+#undef TESTA8
+#undef ANSW8
+#undef INFINITY
+
+#define TESTA8 TESTA8_DBL
+#define ANSW8 ANSW8_DBL
+#define INFINITY DBL_INFINITY
+
+int
+test_vdiv_f64 ()
+{
+ int count;
+ float64x1_t a;
+ float64x1_t b;
+ float64x1_t c;
+
+ float64_t testseta[20][1] = {
+ { TESTA0 }, { TESTA1 }, { TESTA2 }, { TESTA3 },
+ { TESTA4 }, { TESTA5 }, { TESTA6 }, { TESTA7 },
+ { TESTA8 }, { TESTA9 }, { TESTA10 }, { TESTA11 },
+ { TESTA12 }, { TESTA13 }, { TESTA14 }, { TESTA15 },
+ { TESTA16 }, { TESTA17 }, { TESTA18 }, { TESTA19 }
+ };
+
+ float64_t testsetb[20][1] = {
+ { TESTB0 }, { TESTB1 }, { TESTB2 }, { TESTB3 },
+ { TESTB4 }, { TESTB5 }, { TESTB6 }, { TESTB7 },
+ { TESTB8 }, { TESTB9 }, { TESTB10 }, { TESTB11 },
+ { TESTB12 }, { TESTB13 }, { TESTB14 }, { TESTB15 },
+ { TESTB16 }, { TESTB17 }, { TESTB18 }, { TESTB19 }
+ };
+
+ float64_t answset[20][1] = {
+ { ANSW0 }, { ANSW1 }, { ANSW2 }, { ANSW3 },
+ { ANSW4 }, { ANSW5 }, { ANSW6 }, { ANSW7 },
+ { ANSW8 }, { ANSW9 }, { ANSW10 }, { ANSW11 },
+ { ANSW12 }, { ANSW13 }, { ANSW14 }, { ANSW15 },
+ { ANSW16 }, { ANSW17 }, { ANSW18 }, { ANSW19 }
+ };
+
+ for (count = 0; count < 20; count++)
+ {
+ RUN_TEST (a, b, c, testseta, testsetb, answset, count, 64, 64, 1);
+ }
+ return 0;
+}
+
+/* The following assembly should match 2 more times,
+ in 64bit NAN generation. */
+/* { dg-final { scan-assembler-times "fdiv\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 3 } } */
+
+#undef TESTA8
+#undef ANSW8
+#undef INFINITY
+
+#define TESTA8 TESTA8_FLT
+#define ANSW8 ANSW8_FLT
+#define INFINITY FLT_INFINITY
+
+int
+test_vdivq_f32 ()
+{
+ int count;
+ float32x4_t a;
+ float32x4_t b;
+ float32x4_t c;
+
+ float32_t testseta[5][4] = {
+ { TESTA0, TESTA1, TESTA2, TESTA3 },
+ { TESTA4, TESTA5, TESTA6, TESTA7 },
+ { TESTA8, TESTA9, TESTA10, TESTA11 },
+ { TESTA12, TESTA13, TESTA14, TESTA15 },
+ { TESTA16, TESTA17, TESTA18, TESTA19 }
+ };
+
+ float32_t testsetb[5][4] = {
+ { TESTB0, TESTB1, TESTB2, TESTB3 },
+ { TESTB4, TESTB5, TESTB6, TESTB7 },
+ { TESTB8, TESTB9, TESTB10, TESTB11 },
+ { TESTB12, TESTB13, TESTB14, TESTB15 },
+ { TESTB16, TESTB17, TESTB18, TESTB19 }
+ };
+
+ float32_t answset[5][4] = {
+ { ANSW0, ANSW1, ANSW2, ANSW3 },
+ { ANSW4, ANSW5, ANSW6, ANSW7 },
+ { ANSW8, ANSW9, ANSW10, ANSW11 },
+ { ANSW12, ANSW13, ANSW14, ANSW15 },
+ { ANSW16, ANSW17, ANSW18, ANSW19 }
+ };
+
+ for (count = 0; count < 5; count++)
+ {
+ RUN_TEST (a, b, c, testseta, testsetb, answset, count, 128, 32, 4);
+ }
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "fdiv\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+
+#undef TESTA8
+#undef ANSW8
+#undef INFINITY
+
+#define TESTA8 TESTA8_DBL
+#define ANSW8 ANSW8_DBL
+#define INFINITY DBL_INFINITY
+
+int
+test_vdivq_f64 ()
+{
+ int count;
+ float64x2_t a;
+ float64x2_t b;
+ float64x2_t c;
+
+ float64_t testseta[10][2] = {
+ { TESTA0, TESTA1 }, { TESTA2, TESTA3 },
+ { TESTA4, TESTA5 }, { TESTA6, TESTA7 },
+ { TESTA8, TESTA9 }, { TESTA10, TESTA11 },
+ { TESTA12, TESTA13 }, { TESTA14, TESTA15 },
+ { TESTA16, TESTA17 }, { TESTA18, TESTA19 }
+ };
+
+ float64_t testsetb[10][2] = {
+ { TESTB0, TESTB1 }, { TESTB2, TESTB3 },
+ { TESTB4, TESTB5 }, { TESTB6, TESTB7 },
+ { TESTB8, TESTB9 }, { TESTB10, TESTB11 },
+ { TESTB12, TESTB13 }, { TESTB14, TESTB15 },
+ { TESTB16, TESTB17 }, { TESTB18, TESTB19 }
+ };
+
+ float64_t answset[10][2] = {
+ { ANSW0, ANSW1 }, { ANSW2, ANSW3 },
+ { ANSW4, ANSW5 }, { ANSW6, ANSW7 },
+ { ANSW8, ANSW9 }, { ANSW10, ANSW11 },
+ { ANSW12, ANSW13 }, { ANSW14, ANSW15 },
+ { ANSW16, ANSW17 }, { ANSW18, ANSW19 }
+ };
+
+ for (count = 0; count < 10; count++)
+ {
+ RUN_TEST (a, b, c, testseta, testsetb, answset, count, 128, 64, 2);
+ }
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times "fdiv\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
+
+int
+main (int argc, char **argv)
+{
+ if (test_vdiv_f32 ())
+ abort ();
+
+ if (test_vdiv_f64 ())
+ abort ();
+
+ if (test_vdivq_f32 ())
+ abort ();
+
+ if (test_vdivq_f64 ())
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c
new file mode 100644
index 0000000..27146b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c
@@ -0,0 +1,12 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#define N 16
+
+#include "vect-abs.x"
+
+/* { dg-final { scan-assembler "abs\\tv\[0-9\]+\.16b" } } */
+/* { dg-final { scan-assembler "abs\\tv\[0-9\]+\.8h" } } */
+/* { dg-final { scan-assembler "abs\\tv\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "abs\\tv\[0-9\]+\.2d" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs.c
new file mode 100644
index 0000000..9e0ed99
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs.c
@@ -0,0 +1,134 @@
+
+/* { dg-do run } */
+/* { dg-options "-O3 -std=c99" } */
+
+#include "limits.h"
+
+extern void abort (void);
+
+#define N 16
+
+#include "vect-abs.x"
+
+#define SET_VEC(size, type) void set_vector_##size (pRINT##size a) \
+ { \
+ int i; \
+ for (i=0; i<N; i++) \
+ a[i] = (type##_MIN) + (i + 1); \
+ }
+
+#define SET_RVEC(size, type) void set_rvector_##size (pRINT##size a) \
+ { \
+ int i; \
+ for (i=0; i<N; i++) \
+ a[i] = type##_MAX - i; \
+ }
+
+#define CHECK_VEC(size) void check_vector_##size (pRINT##size a, \
+ pRINT##size b) \
+ { \
+ int i; \
+ for (i=0; i<N; i++) \
+ if (a[i] != b[i]) \
+ abort (); \
+ }
+
+
+SET_RVEC (8, SCHAR)
+SET_RVEC (16, SHRT)
+SET_RVEC (32, INT)
+SET_RVEC (64, LLONG)
+
+void
+set_rvector_long (pRLONG a)
+{
+ int i;
+ for (i=0; i<N; i++)
+ a[i] = (LONG_MAX) - i;
+}
+
+SET_VEC (8, SCHAR)
+SET_VEC (16, SHRT)
+SET_VEC (32, INT)
+SET_VEC (64, LLONG)
+
+void
+set_vector_long (long *__restrict__ a)
+{
+ long i;
+ for (i=0; i<N; i++)
+ a[i] = (LONG_MIN) + i + 1;
+}
+
+CHECK_VEC (8)
+CHECK_VEC (16)
+CHECK_VEC (32)
+CHECK_VEC (64)
+
+void
+check_vector_long (long *__restrict__ a, long *__restrict__ b)
+{
+ long i;
+ for (i=0; i<N; i++)
+ if (a[i] != b[i])
+ abort ();
+}
+
+int main (void)
+{
+
+ signed char a8[N];
+ short a16[N];
+ int a32[N];
+ long long a64[N];
+ /* abs () from stdlib. */
+ int alib32[N];
+ long alibl[N];
+
+
+ signed char b8[N];
+ short b16[N];
+ int b32[N];
+ long long b64[N];
+ /* abs () from stdlib. */
+ long blibl[N];
+
+ signed char abs_vector_8[N];
+ short abs_vector_16[N];
+ int abs_vector_32[N];
+ long long abs_vector_64[N];
+ long abs_vector_long[N];
+
+ /* Set up result vectors. */
+ set_rvector_8 (abs_vector_8);
+ set_rvector_16 (abs_vector_16);
+ set_rvector_32 (abs_vector_32);
+ set_rvector_long (abs_vector_long);
+ set_rvector_64 (abs_vector_64);
+
+ /* Set up inputs. */
+ set_vector_8 (b8);
+ set_vector_16 (b16);
+ set_vector_32 (b32);
+ set_vector_64 (b64);
+ set_vector_long (blibl);
+
+ /* Calculate their absolute values. */
+ absolute_s8 (a8, b8);
+ absolute_s16 (a16, b16);
+ absolute_s32 (a32, b32);
+ absolute_s64 (a64, b64);
+ /* abs () from stdlib. */
+ absolute_s32_lib (alib32, b32);
+ absolute_l32_lib (alibl, blibl);
+
+ /* Check. */
+ check_vector_8 (a8, abs_vector_8);
+ check_vector_16 (a16, abs_vector_16);
+ check_vector_32 (a32, abs_vector_32);
+ check_vector_64 (a64, abs_vector_64);
+ check_vector_32 (alib32, abs_vector_32);
+ check_vector_long (alibl, abs_vector_long);
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs.x
new file mode 100644
index 0000000..2e67cc2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs.x
@@ -0,0 +1,36 @@
+
+extern int abs (int);
+extern long labs (long);
+
+typedef signed char *__restrict__ pRINT8;
+typedef short *__restrict__ pRINT16;
+typedef int *__restrict__ pRINT32;
+typedef long *__restrict__ pRLONG;
+typedef long long *__restrict__ pRINT64;
+
+#define DEF_ABS(size) void absolute_s##size (pRINT##size a, pRINT##size b) \
+ { \
+ int i; \
+ for (i=0; i<N; i++) \
+ a[i] = (b[i] > 0 ? b[i] : -b[i]); \
+ }
+
+DEF_ABS (8);
+DEF_ABS (16);
+DEF_ABS (32);
+DEF_ABS (64);
+
+/* Test abs () vectorization. */
+void absolute_s32_lib (pRINT32 a, pRINT32 b)
+{
+ int i;
+ for (i=0; i<N; i++)
+ a[i] = abs (b[i]);
+}
+
+void absolute_l32_lib (pRLONG a, pRLONG b)
+{
+ int i;
+ for (i=0; i<N; i++)
+ a[i] = labs (b[i]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-clz.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-clz.c
new file mode 100644
index 0000000..8f1fe70
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-clz.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -save-temps -fno-inline" } */
+
+extern void abort ();
+
+void
+count_lz_v4si (unsigned *__restrict a, int *__restrict b)
+{
+ int i;
+
+ for (i = 0; i < 4; i++)
+ b[i] = __builtin_clz (a[i]);
+}
+
+/* { dg-final { scan-assembler "clz\tv\[0-9\]+\.4s" } } */
+
+int
+main ()
+{
+ unsigned int x[4] = { 0x0, 0xFFFF, 0x1FFFF, 0xFFFFFFFF };
+ int r[4] = { 32, 16, 15, 0 };
+ int d[4], i;
+
+ count_lz_v4si (x, d);
+
+ for (i = 0; i < 4; i++)
+ {
+ if (d[i] != r[i])
+ abort ();
+ }
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-compile.c
new file mode 100644
index 0000000..33130aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-compile.c
@@ -0,0 +1,22 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#include "vect.x"
+
+/* { dg-final { scan-assembler "orn\\tv" } } */
+/* { dg-final { scan-assembler "bic\\tv" } } */
+/* { dg-final { scan-assembler "mla\\tv" } } */
+/* { dg-final { scan-assembler "mls\\tv" } } */
+/* { dg-final { scan-assembler "smax\\tv" } } */
+/* { dg-final { scan-assembler "smin\\tv" } } */
+/* { dg-final { scan-assembler "umax\\tv" } } */
+/* { dg-final { scan-assembler "umin\\tv" } } */
+/* { dg-final { scan-assembler "umaxv" } } */
+/* { dg-final { scan-assembler "uminv" } } */
+/* { dg-final { scan-assembler "smaxv" } } */
+/* { dg-final { scan-assembler "sminv" } } */
+/* { dg-final { scan-assembler "sabd" } } */
+/* { dg-final { scan-assembler "saba" } } */
+/* { dg-final { scan-assembler-times "addv" 2} } */
+/* { dg-final { scan-assembler-times "addp" 2} } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv-compile.c
new file mode 100644
index 0000000..cce9240
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv-compile.c
@@ -0,0 +1,7 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O3 -ffast-math" } */
+
+#include "vect-faddv.x"
+
+/* { dg-final { scan-assembler-times "faddp\\tv" 2} } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv.c
new file mode 100644
index 0000000..f30bde8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv.c
@@ -0,0 +1,31 @@
+
+/* { dg-do run } */
+/* { dg-options "-O3 -ffast-math" } */
+
+extern void abort (void);
+
+#include "vect-faddv.x"
+
+int main (void)
+{
+ float addv_f32_value = -120.0f;
+ double addv_f64_value = 120.0;
+ float af32[16];
+ double af64[16];
+ int i;
+
+ /* Set up input vectors. */
+ for (i=0; i<16; i++)
+ {
+ af32[i] = (float)-i;
+ af64[i] = (double)i;
+ }
+
+ if (addv_f32 (af32) != addv_f32_value)
+ abort ();
+
+ if (addv_f64 (af64) != addv_f64_value)
+ abort ();
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv.x
new file mode 100644
index 0000000..d99ab21
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv.x
@@ -0,0 +1,23 @@
+
+typedef float *__restrict__ pRF32;
+typedef double *__restrict__ pRF64;
+
+float addv_f32 (pRF32 a)
+{
+ int i;
+ float s = 0.0;
+ for (i=0; i<16; i++)
+ s += a[i];
+
+ return s;
+}
+
+double addv_f64 (pRF64 a)
+{
+ int i;
+ double s = 0.0;
+ for (i=0; i<16; i++)
+ s += a[i];
+
+ return s;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c
new file mode 100644
index 0000000..6c2e2c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
+
+#define FTYPE double
+#define ITYPE long
+#define OP ==
+#define INV_OP !=
+
+#include "vect-fcm.x"
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */
+/* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c
new file mode 100644
index 0000000..5a2109c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
+
+#define FTYPE float
+#define ITYPE int
+#define OP ==
+#define INV_OP !=
+
+#include "vect-fcm.x"
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */
+/* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */
+/* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c
new file mode 100644
index 0000000..8fad799
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
+
+#define FTYPE double
+#define ITYPE long
+#define OP >=
+#define INV_OP <
+
+#include "vect-fcm.x"
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */
+/* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */
+/* { dg-final { scan-assembler "fcmlt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c
new file mode 100644
index 0000000..7aab9e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
+
+#define FTYPE float
+#define ITYPE int
+#define OP >=
+#define INV_OP <
+
+#include "vect-fcm.x"
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */
+/* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */
+/* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */
+/* { dg-final { scan-assembler "fcmlt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c
new file mode 100644
index 0000000..d26acaa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
+
+#define FTYPE double
+#define ITYPE long
+#define OP >
+#define INV_OP <=
+
+#include "vect-fcm.x"
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */
+/* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */
+/* { dg-final { scan-assembler "fcmle\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c
new file mode 100644
index 0000000..2797fd1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
+
+#define FTYPE float
+#define ITYPE int
+#define OP >
+#define INV_OP <=
+
+#include "vect-fcm.x"
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */
+/* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */
+/* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */
+/* { dg-final { scan-assembler "fcmle\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm.x
new file mode 100644
index 0000000..614f0de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm.x
@@ -0,0 +1,124 @@
+#include <stdlib.h>
+#define N 16
+
+FTYPE input1[N] =
+{2.0, 4.0, 8.0, 16.0,
+ 2.125, 4.25, 8.5, 17.0,
+ -2.0, -4.0, -8.0, -16.0,
+ -2.125, -4.25, -8.5, -17.0};
+
+FTYPE input2[N] =
+{-2.0, 4.0, -8.0, 16.0,
+ 2.125, -4.25, 8.5, -17.0,
+ 2.0, -4.0, 8.0, -16.0,
+ -2.125, 4.25, -8.5, 17.0};
+
+/* Float comparisons, float results. */
+
+void
+foo (FTYPE *in1, FTYPE *in2, FTYPE *output)
+{
+ int i = 0;
+ /* Vectorizable. */
+ for (i = 0; i < N; i++)
+ output[i] = (in1[i] OP in2[i]) ? 2.0 : 4.0;
+}
+
+void
+bar (FTYPE *in1, FTYPE *in2, FTYPE *output)
+{
+ int i = 0;
+ /* Vectorizable. */
+ for (i = 0; i < N; i++)
+ output[i] = (in1[i] INV_OP in2[i]) ? 4.0 : 2.0;
+}
+
+void
+foobar (FTYPE *in1, FTYPE *in2, FTYPE *output)
+{
+ int i = 0;
+ /* Vectorizable. */
+ for (i = 0; i < N; i++)
+ output[i] = (in1[i] OP 0.0) ? 4.0 : 2.0;
+}
+
+void
+foobarbar (FTYPE *in1, FTYPE *in2, FTYPE *output)
+{
+ int i = 0;
+ /* Vectorizable. */
+ for (i = 0; i < N; i++)
+ output[i] = (in1[i] INV_OP 0.0) ? 4.0 : 2.0;
+}
+
+/* Float comparisons, int results. */
+
+void
+foo_int (FTYPE *in1, FTYPE *in2, ITYPE *output)
+{
+ int i = 0;
+ /* Vectorizable. */
+ for (i = 0; i < N; i++)
+ output[i] = (in1[i] OP in2[i]) ? 2 : 4;
+}
+
+void
+bar_int (FTYPE *in1, FTYPE *in2, ITYPE *output)
+{
+ int i = 0;
+ /* Vectorizable. */
+ for (i = 0; i < N; i++)
+ output[i] = (in1[i] INV_OP in2[i]) ? 4 : 2;
+}
+
+void
+foobar_int (FTYPE *in1, FTYPE *in2, ITYPE *output)
+{
+ int i = 0;
+ /* Vectorizable. */
+ for (i = 0; i < N; i++)
+ output[i] = (in1[i] OP 0.0) ? 4 : 2;
+}
+
+void
+foobarbar_int (FTYPE *in1, FTYPE *in2, ITYPE *output)
+{
+ int i = 0;
+ /* Vectorizable. */
+ for (i = 0; i < N; i++)
+ output[i] = (in1[i] INV_OP 0.0) ? 4 : 2;
+}
+
+int
+main (int argc, char **argv)
+{
+ FTYPE out1[N];
+ FTYPE out2[N];
+ ITYPE outi1[N];
+ ITYPE outi2[N];
+
+ int i = 0;
+ foo (input1, input2, out1);
+ bar (input1, input2, out2);
+ for (i = 0; i < N; i++)
+ if (out1[i] != out2[i])
+ abort ();
+ foobar (input1, input2, out1);
+ foobarbar (input1, input2, out2);
+ for (i = 0; i < N; i++)
+ if (out1[i] == out2[i])
+ abort ();
+
+ foo_int (input1, input2, outi1);
+ bar_int (input1, input2, outi2);
+ for (i = 0; i < N; i++)
+ if (outi1[i] != outi2[i])
+ abort ();
+ foobar_int (input1, input2, outi1);
+ foobarbar_int (input1, input2, outi2);
+ for (i = 0; i < N; i++)
+ if (outi1[i] == outi2[i])
+ abort ();
+ return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin-compile.c
new file mode 100644
index 0000000..1285a50
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin-compile.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -ffast-math" } */
+
+#include "vect-fmax-fmin.x"
+
+/* { dg-final { scan-assembler "fmaxnm\\tv" } } */
+/* { dg-final { scan-assembler "fminnm\\tv" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.c
new file mode 100644
index 0000000..42600b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.c
@@ -0,0 +1,105 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -ffast-math" } */
+
+extern void abort (void);
+
+#include "vect-fmax-fmin.x"
+
+#include "vect-fmaxv-fminv.x"
+
+#define DEFN_SETV(type) \
+ set_vector_##type (pR##type a, type n) \
+ { \
+ int i; \
+ for (i=0; i<16; i++) \
+ a[i] = n; \
+ }
+
+#define DEFN_CHECKV(type) \
+ void check_vector_##type (pR##type a, pR##type vec) \
+ { \
+ int i; \
+ for (i=0; i<16; i++) \
+ if (a[i] != vec[i]) \
+ abort (); \
+ }
+
+#define TEST2(fname, type) \
+ set_vector_##type (c##type, 0.0); \
+ fname##_##type (a##type, b##type); \
+ check_vector_##type (c##type, fname##_##type##_vector);
+
+#define TEST3(fname, type) \
+ set_vector_##type (c##type, 0.0); \
+ fname##_##type (a##type, b##type, c##type); \
+ check_vector_##type (c##type, fname##_##type##_vector);
+
+#define TEST(fname, N) \
+ TEST##N (fname, F32); \
+ TEST##N (fname, F64);
+
+typedef float F32;
+typedef double F64;
+
+DEFN_SETV (F32)
+DEFN_SETV (F64)
+
+DEFN_CHECKV (F32)
+DEFN_CHECKV (F64)
+
+int main (void)
+{
+
+ F32 aF32[16];
+ F32 bF32[16];
+ F32 cF32[16];
+
+ F64 aF64[16];
+ F64 bF64[16];
+ F64 cF64[16];
+ int i;
+
+ /* Golden vectors. */
+ F32 max_F32_vector[] = { 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0,
+ 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0 };
+
+ F64 max_F64_vector[] = { 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0,
+ 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0 };
+
+ F32 min_F32_vector[] = { 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0,
+ 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0, 0.0 };
+
+ F64 min_F64_vector[] = { 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0,
+ 7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0, 0.0 };
+
+ F32 minv_F32_value = 0.0f;
+ F32 maxv_F32_value = 15.0f;
+
+ F64 minv_F64_value = 0.0;
+ F64 maxv_F64_value = 15.0;
+
+ /* Setup input vectors. */
+ for (i=0; i<16; i++)
+ {
+ aF32[i] = (float)(15-i);
+ bF32[i] = (float)i;
+ aF64[i] = (double)(15-i);
+ bF64[i] = (double)i;
+ }
+
+ TEST (max, 3);
+ TEST (min, 3);
+
+ /* Test across lanes ops. */
+ if (maxv_f32 (max_F32_vector) != maxv_F32_value)
+ abort ();
+ if (minv_f32 (min_F32_vector) != minv_F32_value)
+ abort ();
+
+ if (maxv_f64 (max_F64_vector) != maxv_F64_value)
+ abort ();
+ if (minv_f64 (min_F64_vector) != minv_F64_value)
+ abort ();
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.x
new file mode 100644
index 0000000..a894820
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.x
@@ -0,0 +1,32 @@
+
+typedef float *__restrict__ pRF32;
+typedef double *__restrict__ pRF64;
+
+
+void max_F32 (pRF32 a, pRF32 b, pRF32 c)
+{
+ int i;
+ for (i=0;i<16;i++)
+ c[i] = (a[i] > b[i] ? a[i] : b[i]);
+}
+
+void min_F32 (pRF32 a, pRF32 b, pRF32 c)
+{
+ int i;
+ for (i=0;i<16;i++)
+ c[i] = (a[i] < b[i] ? a[i] : b[i]);
+}
+
+void max_F64 (pRF64 a, pRF64 b, pRF64 c)
+{
+ int i;
+ for (i=0;i<16;i++)
+ c[i] = (a[i] > b[i] ? a[i] : b[i]);
+}
+
+void min_F64 (pRF64 a, pRF64 b, pRF64 c)
+{
+ int i;
+ for (i=0;i<16;i++)
+ c[i] = (a[i] < b[i] ? a[i] : b[i]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv-compile.c
new file mode 100644
index 0000000..975cef9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv-compile.c
@@ -0,0 +1,10 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O3 -ffast-math -fno-vect-cost-model" } */
+
+#include "vect-fmaxv-fminv.x"
+
+/* { dg-final { scan-assembler "fminnmv" } } */
+/* { dg-final { scan-assembler "fmaxnmv" } } */
+/* { dg-final { scan-assembler "fminnmp" } } */
+/* { dg-final { scan-assembler "fmaxnmp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv.x
new file mode 100644
index 0000000..0bc6ba4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv.x
@@ -0,0 +1,43 @@
+
+typedef float *__restrict__ pRF32;
+typedef double *__restrict__ pRF64;
+
+float maxv_f32 (pRF32 a)
+{
+ int i;
+ float s = a[0];
+ for (i=1;i<8;i++)
+ s = (s > a[i] ? s : a[i]);
+
+ return s;
+}
+
+float minv_f32 (pRF32 a)
+{
+ int i;
+ float s = a[0];
+ for (i=1;i<16;i++)
+ s = (s < a[i] ? s : a[i]);
+
+ return s;
+}
+
+double maxv_f64 (pRF64 a)
+{
+ int i;
+ double s = a[0];
+ for (i=1;i<8;i++)
+ s = (s > a[i] ? s : a[i]);
+
+ return s;
+}
+
+double minv_f64 (pRF64 a)
+{
+ int i;
+ double s = a[0];
+ for (i=1;i<16;i++)
+ s = (s < a[i] ? s : a[i]);
+
+ return s;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c
new file mode 100644
index 0000000..667d227
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
+
+#define N 32
+
+void
+foo (double *output)
+{
+ int i = 0;
+ /* Vectorizable. */
+ for (i = 0; i < N; i++)
+ output[i] = 0.0;
+}
+
+/* { dg-final { scan-assembler "movi\\tv\[0-9\]+\\.2d, 0" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovd.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovd.c
new file mode 100644
index 0000000..a0211c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovd.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
+
+#define N 32
+
+void
+foo (double *output)
+{
+ int i = 0;
+ /* Vectorizable. */
+ for (i = 0; i < N; i++)
+ output[i] = 4.25;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { scan-assembler "fmov\\tv\[0-9\]+\\.2d, 4\\.25" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovf-zero.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovf-zero.c
new file mode 100644
index 0000000..259a9d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovf-zero.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
+
+#define N 32
+
+void
+foo (float *output)
+{
+ int i = 0;
+ /* Vectorizable. */
+ for (i = 0; i < N; i++)
+ output[i] = 0.0;
+}
+
+/* { dg-final { scan-assembler "movi\\tv\[0-9\]+\\.\[24\]s, 0" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovf.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovf.c
new file mode 100644
index 0000000..0bd21dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovf.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
+
+#define N 32
+
+void
+foo (float *output)
+{
+ int i = 0;
+ /* Vectorizable. */
+ for (i = 0; i < N; i++)
+ output[i] = 4.25;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { scan-assembler "fmov\\tv\[0-9\]+\\.\[24\]s, 4\\.25" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c
new file mode 100644
index 0000000..47ef100
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c
@@ -0,0 +1,14 @@
+
+
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#include "vect-fp.x"
+
+/* { dg-final { scan-assembler "fadd\\tv" } } */
+/* { dg-final { scan-assembler "fsub\\tv" } } */
+/* { dg-final { scan-assembler "fmul\\tv" } } */
+/* { dg-final { scan-assembler "fdiv\\tv" } } */
+/* { dg-final { scan-assembler "fneg\\tv" } } */
+/* { dg-final { scan-assembler "fabs\\tv" } } */
+/* { dg-final { scan-assembler "fabd\\tv" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp.c
new file mode 100644
index 0000000..bcf9d9d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp.c
@@ -0,0 +1,148 @@
+
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+extern void abort (void);
+
+#include "vect-fp.x"
+
+
+#define DEFN_SETV(type) \
+ set_vector_##type (pR##type a, type n) \
+ { \
+ int i; \
+ for (i=0; i<16; i++) \
+ a[i] = n; \
+ }
+
+#define DEFN_CHECKV(type) \
+ void check_vector_##type (pR##type a, pR##type vec) \
+ { \
+ int i; \
+ for (i=0; i<16; i++) \
+ if (a[i] != vec[i]) \
+ abort (); \
+ }
+
+#define TEST2(fname, type) \
+ set_vector_##type (a##type, 0.0); \
+ fname##_##type (a##type, b##type); \
+ check_vector_##type (a##type, fname##_##type##_vector);
+
+#define TEST3(fname, type) \
+ set_vector_##type (a##type, 0.0); \
+ fname##_##type (a##type, b##type, c##type); \
+ check_vector_##type (a##type, fname##_##type##_vector);
+
+#define TEST(fname, N) \
+ TEST##N(fname, F32); \
+ TEST##N(fname, F64);
+
+DEFN_SETV (F32)
+DEFN_SETV (F64)
+
+DEFN_CHECKV (F32)
+DEFN_CHECKV (F64)
+
+int main (void)
+{
+ F32 aF32[16];
+ F32 bF32[16];
+ F32 cF32[16];
+
+ F64 aF64[16];
+ F64 bF64[16];
+ F64 cF64[16];
+ int i;
+
+ F32 add_F32_vector[] = { 3.0f, 5.0f, 7.0f, 9.0f, 11.0f,
+ 13.0f, 15.0f, 17.0f, 19.0f,
+ 21.0f, 23.0f, 25.0f, 27.0f,
+ 29.0f, 31.0f, 33.0f };
+
+ F64 add_F64_vector[] = { 3.0, 5.0, 7.0, 9.0, 11.0,
+ 13.0, 15.0, 17.0, 19.0,
+ 21.0, 23.0, 25.0, 27.0,
+ 29.0, 31.0, 33.0 };
+
+ F32 sub_F32_vector[] = { -1.0f, -1.0f, -1.0f, -1.0f, -1.0f,
+ -1.0f, -1.0f, -1.0f, -1.0f, -1.0f,
+ -1.0f, -1.0f, -1.0f, -1.0f, -1.0f,
+ -1.0f };
+
+ F64 sub_F64_vector[] = { -1.0, -1.0, -1.0, -1.0, -1.0,
+ -1.0, -1.0, -1.0, -1.0, -1.0,
+ -1.0, -1.0, -1.0, -1.0, -1.0,
+ -1.0 };
+
+ F32 mul_F32_vector[] = { 2.0f, 6.0f, 12.0f, 20.0f, 30.0f,
+ 42.0f, 56.0f, 72.0f, 90.0f,
+ 110.0f, 132.0f, 156.0f, 182.0f,
+ 210.0f, 240.0f, 272.0f };
+
+ F64 mul_F64_vector[] = { 2.0, 6.0, 12.0, 20.0, 30.0,
+ 42.0, 56.0, 72.0, 90.0,
+ 110.0, 132.0, 156.0, 182.0,
+ 210.0, 240.0, 272.0 };
+
+ F32 div_F32_vector[] = { 0.5f, (float)(2.0/3.0), 0.75f, 0.8f,
+ (float)(5.0/6.0), (float)(6.0/7.0), 0.875000f,
+ (float)(8.0/9.0), 0.900000f, (float)(10.0/11.0),
+ (float)(11.0/12.0), (float)(12.0/13.0),
+ (float)(13.0/14.0), (float)(14.0/15.0), 0.937500f,
+ (float)(16.0/17.0) };
+
+ F64 div_F64_vector[] = { 0.5, (2.0/3.0), 0.75, 0.8, (5.0/6.0),
+ (6.0/7.0), 0.875000, (8.0/9.0), 0.900000,
+ (10.0/11.0), (11.0/12.0), (12.0/13.0), (13.0/14.0),
+ (14.0/15.0), 0.937500, (16.0/17.0) };
+
+ F32 neg_F32_vector[] = { -1.0f, -2.0f, -3.0f, -4.0f,
+ -5.0f, -6.0f, -7.0f, -8.0f,
+ -9.0f, -10.0f, -11.0f, -12.0f,
+ -13.0f, -14.0f, -15.0f, -16.0f };
+
+ F64 neg_F64_vector[] = { -1.0, -2.0, -3.0, -4.0,
+ -5.0, -6.0, -7.0, -8.0,
+ -9.0, -10.0, -11.0, -12.0,
+ -13.0, -14.0, -15.0, -16.0 };
+
+ F32 abs_F32_vector[] = { 1.0f, 2.0f, 3.0f, 4.0f,
+ 5.0f, 6.0f, 7.0f, 8.0f,
+ 9.0f, 10.0f, 11.0f, 12.0f,
+ 13.0f, 14.0f, 15.0f, 16.0f };
+
+ F64 abs_F64_vector[] = { 1.0, 2.0, 3.0, 4.0,
+ 5.0, 6.0, 7.0, 8.0,
+ 9.0, 10.0, 11.0, 12.0,
+ 13.0, 14.0, 15.0, 16.0 };
+
+ F32 fabd_F32_vector[] = { 1.0f, 1.0f, 1.0f, 1.0f,
+ 1.0f, 1.0f, 1.0f, 1.0f,
+ 1.0f, 1.0f, 1.0f, 1.0f,
+ 1.0f, 1.0f, 1.0f, 1.0f };
+
+ F64 fabd_F64_vector[] = { 1.0, 1.0, 1.0, 1.0,
+ 1.0, 1.0, 1.0, 1.0,
+ 1.0, 1.0, 1.0, 1.0,
+ 1.0, 1.0, 1.0, 1.0 };
+
+ /* Setup input vectors. */
+ for (i=1; i<=16; i++)
+ {
+ bF32[i-1] = (float)i;
+ cF32[i-1] = (float)(i+1);
+ bF64[i-1] = (double)i;
+ cF64[i-1] = (double)(i+1);
+ }
+
+ TEST (add, 3);
+ TEST (sub, 3);
+ TEST (mul, 3);
+ TEST (div, 3);
+ TEST (neg, 2);
+ TEST (abs, 2);
+ TEST (fabd, 3);
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp.x
new file mode 100644
index 0000000..82d1b1c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp.x
@@ -0,0 +1,60 @@
+
+typedef float F32;
+typedef double F64;
+typedef float *__restrict__ pRF32;
+typedef double *__restrict__ pRF64;
+
+extern float fabsf (float);
+extern double fabs (double);
+
+#define DEF3a(fname, type, op) \
+ void fname##_##type (pR##type a, \
+ pR##type b, \
+ pR##type c) \
+ { \
+ int i; \
+ for (i = 0; i < 16; i++) \
+ a[i] = op (b[i] - c[i]); \
+ }
+
+#define DEF3(fname, type, op) \
+ void fname##_##type (pR##type a, \
+ pR##type b, \
+ pR##type c) \
+ { \
+ int i; \
+ for (i = 0; i < 16; i++) \
+ a[i] = b[i] op c[i]; \
+ }
+
+#define DEF2(fname, type, op) \
+ void fname##_##type (pR##type a, \
+ pR##type b) \
+ { \
+ int i; \
+ for (i = 0; i < 16; i++) \
+ a[i] = op(b[i]); \
+ }
+
+
+#define DEFN3a(fname, op) \
+ DEF3a (fname, F32, op) \
+ DEF3a (fname, F64, op)
+
+#define DEFN3(fname, op) \
+ DEF3 (fname, F32, op) \
+ DEF3 (fname, F64, op)
+
+#define DEFN2(fname, op) \
+ DEF2 (fname, F32, op) \
+ DEF2 (fname, F64, op)
+
+DEFN3 (add, +)
+DEFN3 (sub, -)
+DEFN3 (mul, *)
+DEFN3 (div, /)
+DEFN2 (neg, -)
+DEF2 (abs, F32, fabsf)
+DEF2 (abs, F64, fabs)
+DEF3a (fabd, F32, fabsf)
+DEF3a (fabd, F64, fabs)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c
new file mode 100644
index 0000000..66e0168
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fno-vect-cost-model" } */
+
+#include "stdint.h"
+#include "vect-ld1r.x"
+
+DEF (float)
+DEF (double)
+
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "ldr\\t\x\[0-9\]+"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.2d"} } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c
new file mode 100644
index 0000000..761777f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fno-vect-cost-model" } */
+
+#include "stdint.h"
+#include "vect-ld1r.x"
+
+DEF (int8_t)
+DEF (int16_t)
+DEF (int32_t)
+DEF (int64_t)
+
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.8b"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.16b"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4h"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.8h"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "ldr\\t\x\[0-9\]+"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.2d"} } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-fp.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-fp.c
new file mode 100644
index 0000000..5e384e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-fp.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+extern void abort (void);
+
+#include "stdint.h"
+#include "vect-ld1r.x"
+
+DEF (float)
+DEF (double)
+
+#define FOOD(TYPE) \
+ foo_ ## TYPE ## _d (&a_ ## TYPE, output_ ## TYPE)
+
+#define FOOQ(TYPE) \
+ foo_ ## TYPE ## _q (&a_ ## TYPE, output_ ## TYPE)
+
+#define CHECKD(TYPE) \
+ for (i = 0; i < 8 / sizeof (TYPE); i++) \
+ if (output_ ## TYPE[i] != a_ ## TYPE) \
+ abort ()
+
+#define CHECKQ(TYPE) \
+ for (i = 0; i < 32 / sizeof (TYPE); i++) \
+ if (output_ ## TYPE[i] != a_ ## TYPE) \
+ abort ()
+
+#define DECL(TYPE) \
+ TYPE output_ ## TYPE[32]; \
+ TYPE a_ ## TYPE = (TYPE)12.2
+
+int
+main (void)
+{
+
+ DECL(float);
+ DECL(double);
+ int i;
+
+ FOOD (float);
+ CHECKD (float);
+ FOOQ (float);
+ CHECKQ (float);
+
+ FOOD (double);
+ CHECKD (double);
+ FOOQ (double);
+ CHECKQ (double);
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r.c
new file mode 100644
index 0000000..f0571de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r.c
@@ -0,0 +1,65 @@
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+extern void abort (void);
+
+#include "stdint.h"
+#include "vect-ld1r.x"
+
+DEF (int8_t)
+DEF (int16_t)
+DEF (int32_t)
+DEF (int64_t)
+
+#define FOOD(TYPE) \
+ foo_ ## TYPE ## _d (&a_ ## TYPE, output_ ## TYPE)
+
+#define FOOQ(TYPE) \
+ foo_ ## TYPE ## _q (&a_ ## TYPE, output_ ## TYPE)
+
+#define CHECKD(TYPE) \
+ for (i = 0; i < 8 / sizeof (TYPE); i++) \
+ if (output_ ## TYPE[i] != a_ ## TYPE) \
+ abort ()
+
+#define CHECKQ(TYPE) \
+ for (i = 0; i < 32 / sizeof (TYPE); i++) \
+ if (output_ ## TYPE[i] != a_ ## TYPE) \
+ abort ()
+
+#define DECL(TYPE) \
+ TYPE output_ ## TYPE[32]; \
+ TYPE a_ ## TYPE = (TYPE)12
+
+int
+main (void)
+{
+
+ DECL(int8_t);
+ DECL(int16_t);
+ DECL(int32_t);
+ DECL(int64_t);
+ int i;
+
+ FOOD (int8_t);
+ CHECKD (int8_t);
+ FOOQ (int8_t);
+ CHECKQ (int8_t);
+
+ FOOD (int16_t);
+ CHECKD (int16_t);
+ FOOQ (int16_t);
+ CHECKQ (int16_t);
+
+ FOOD (int32_t);
+ CHECKD (int32_t);
+ FOOQ (int32_t);
+ CHECKQ (int32_t);
+
+ FOOD (int64_t);
+ CHECKD (int64_t);
+ FOOQ (int64_t);
+ CHECKQ (int64_t);
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r.x
new file mode 100644
index 0000000..680ce43
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r.x
@@ -0,0 +1,15 @@
+
+#define DEF(TYPE) \
+ void \
+ foo_ ## TYPE ## _d (TYPE *a, TYPE *output) \
+ { \
+ int i; \
+ for (i = 0; i < 8 / sizeof (TYPE); i++) \
+ output[i] = *a; \
+ } \
+ foo_ ## TYPE ## _q (TYPE *a, TYPE *output) \
+ { \
+ int i; \
+ for (i = 0; i < 32 / sizeof (TYPE); i++) \
+ output[i] = *a; \
+ }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-movi.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-movi.c
new file mode 100644
index 0000000..59a0bd5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-movi.c
@@ -0,0 +1,74 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+#define N 16
+
+static void
+movi_msl8 (int *__restrict a)
+{
+ int i;
+
+ /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.4s, 0xab, msl 8" } } */
+ for (i = 0; i < N; i++)
+ a[i] = 0xabff;
+}
+
+static void
+movi_msl16 (int *__restrict a)
+{
+ int i;
+
+ /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.4s, 0xab, msl 16" } } */
+ for (i = 0; i < N; i++)
+ a[i] = 0xabffff;
+}
+
+static void
+mvni_msl8 (int *__restrict a)
+{
+ int i;
+
+ /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.4s, 0xab, msl 8" } } */
+ for (i = 0; i < N; i++)
+ a[i] = 0xffff5400;
+}
+
+static void
+mvni_msl16 (int *__restrict a)
+{
+ int i;
+
+ /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.4s, 0xab, msl 16" } } */
+ for (i = 0; i < N; i++)
+ a[i] = 0xff540000;
+}
+
+int
+main (void)
+{
+ int a[N] = { 0 };
+ int i;
+
+#define CHECK_ARRAY(a, val) \
+ for (i = 0; i < N; i++) \
+ if (a[i] != val) \
+ abort ();
+
+ movi_msl8 (a);
+ CHECK_ARRAY (a, 0xabff);
+
+ movi_msl16 (a);
+ CHECK_ARRAY (a, 0xabffff);
+
+ mvni_msl8 (a);
+ CHECK_ARRAY (a, 0xffff5400);
+
+ mvni_msl16 (a);
+ CHECK_ARRAY (a, 0xff540000);
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c
new file mode 100644
index 0000000..e90c97f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c
@@ -0,0 +1,24 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#define N 16
+
+#include "vect-mull.x"
+
+DEF_MULL2 (DEF_MULLB)
+DEF_MULL2 (DEF_MULLH)
+DEF_MULL2 (DEF_MULLS)
+
+/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.8h"} } */
+/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.2d"} } */
+/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.8h"} } */
+/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.2d"} } */
+/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.8h"} } */
+/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.2d"} } */
+/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.8h"} } */
+/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.2d"} } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull.c
new file mode 100644
index 0000000..62a3552
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull.c
@@ -0,0 +1,138 @@
+
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#include "limits.h"
+
+extern void abort (void);
+
+#define N 16
+
+#include "vect-mull.x"
+
+#define SET_VEC(size, type, sign) \
+ void set_vector_##sign##size \
+ (pR##sign##INT##size b, \
+ pR##sign##INT##size c) \
+ { \
+ int i; \
+ for (i=0; i<N; i++) \
+ { \
+ b[i] = (type)((INT_MAX >> (32 - size)) - i); \
+ c[i] = (type)((INT_MAX >> (32 - size)) - i * 2); \
+ } \
+ }
+
+#define CHECK_VEC(size, sign) void check_vector_##sign##size (pR##sign##INT##size a, \
+ pR##sign##INT##size b) \
+ { \
+ int i; \
+ for (i=0; i<N; i++) \
+ if (a[i] != b[i]) \
+ abort (); \
+ }
+
+SET_VEC (8, signed char, S)
+SET_VEC (16, signed short, S)
+SET_VEC (32, signed int, S)
+
+SET_VEC (8, unsigned char, U)
+SET_VEC (16, unsigned short, U)
+SET_VEC (32, unsigned int, U)
+
+DEF_MULL2 (DEF_MULLB)
+DEF_MULL2 (DEF_MULLH)
+DEF_MULL2 (DEF_MULLS)
+
+CHECK_VEC (8, S)
+CHECK_VEC (8, U)
+CHECK_VEC (16, S)
+CHECK_VEC (16, U)
+CHECK_VEC (32, S)
+CHECK_VEC (32, U)
+CHECK_VEC (64, S)
+CHECK_VEC (64, U)
+
+int main (void)
+{
+
+#define DECL_VAR(name) signed char name##_S8[N]; \
+ signed short name##_S16[N]; \
+ signed int name##_S32[N]; \
+ unsigned char name##_U8[N]; \
+ unsigned short name##_U16[N]; \
+ unsigned int name##_U32[N];
+
+ DECL_VAR (output);
+ signed long long output_S64[N];
+ unsigned long long output_U64[N];
+
+ DECL_VAR (input1);
+ DECL_VAR (input2);
+
+ signed short expected_S16[] =
+ { 16129, 15750, 15375, 15004, 14637, 14274, 13915, 13560,
+ 13209, 12862, 12519, 12180, 11845, 11514, 11187, 10864 };
+
+ signed int expected_S32[] =
+ { 1073676289, 1073577990, 1073479695, 1073381404, 1073283117,
+ 1073184834, 1073086555, 1072988280, 1072890009, 1072791742,
+ 1072693479, 1072595220, 1072496965, 1072398714, 1072300467,
+ 1072202224 };
+
+ signed long long expected_S64[] =
+ { 4611686014132420609LL, 4611686007689969670LL,
+ 4611686001247518735LL, 4611685994805067804LL,
+ 4611685988362616877LL, 4611685981920165954LL,
+ 4611685975477715035LL, 4611685969035264120LL,
+ 4611685962592813209LL, 4611685956150362302LL,
+ 4611685949707911399LL, 4611685943265460500LL,
+ 4611685936823009605LL, 4611685930380558714LL,
+ 4611685923938107827LL, 4611685917495656944LL };
+
+ unsigned short expected_U16[] =
+ { 16129, 15750, 15375, 15004, 14637, 14274, 13915, 13560,
+ 13209, 12862, 12519, 12180, 11845, 11514, 11187, 10864 };
+
+ unsigned int expected_U32[] =
+ { 1073676289, 1073577990, 1073479695, 1073381404, 1073283117,
+ 1073184834, 1073086555, 1072988280, 1072890009, 1072791742,
+ 1072693479, 1072595220, 1072496965, 1072398714, 1072300467,
+ 1072202224 };
+
+ unsigned long long expected_U64[] =
+ { 4611686014132420609ULL, 4611686007689969670ULL,
+ 4611686001247518735ULL, 4611685994805067804ULL,
+ 4611685988362616877ULL, 4611685981920165954ULL,
+ 4611685975477715035ULL, 4611685969035264120ULL,
+ 4611685962592813209ULL, 4611685956150362302ULL,
+ 4611685949707911399ULL, 4611685943265460500ULL,
+ 4611685936823009605ULL, 4611685930380558714ULL,
+ 4611685923938107827ULL, 4611685917495656944ULL };
+
+ /* Set up input. */
+ set_vector_S8 (input1_S8, input2_S8);
+ set_vector_S16 (input1_S16, input2_S16);
+ set_vector_S32 (input1_S32, input2_S32);
+ set_vector_U8 (input1_U8, input2_U8);
+ set_vector_U16 (input1_U16, input2_U16);
+ set_vector_U32 (input1_U32, input2_U32);
+
+ /* Calculate actual results. */
+ widen_mult_Sb (output_S16, input1_S8, input2_S8);
+ widen_mult_Sh (output_S32, input1_S16, input2_S16);
+ widen_mult_Ss (output_S64, input1_S32, input2_S32);
+ widen_mult_Ub (output_U16, input1_U8, input2_U8);
+ widen_mult_Uh (output_U32, input1_U16, input2_U16);
+ widen_mult_Us (output_U64, input1_U32, input2_U32);
+
+ /* Check actual vs. expected. */
+ check_vector_S16 (expected_S16, output_S16);
+ check_vector_S32 (expected_S32, output_S32);
+ check_vector_S64 (expected_S64, output_S64);
+ check_vector_U16 (expected_U16, output_U16);
+ check_vector_U32 (expected_U32, output_U32);
+ check_vector_U64 (expected_U64, output_U64);
+
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull.x
new file mode 100644
index 0000000..39ec43d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull.x
@@ -0,0 +1,49 @@
+
+typedef signed char *__restrict__ pRSINT8;
+typedef signed short *__restrict__ pRSINT16;
+typedef signed int *__restrict__ pRSINT32;
+typedef signed long long *__restrict__ pRSINT64;
+
+typedef unsigned char *__restrict__ pRUINT8;
+typedef unsigned short *__restrict__ pRUINT16;
+typedef unsigned int *__restrict__ pRUINT32;
+typedef unsigned long long *__restrict__ pRUINT64;
+
+typedef signed short SH;
+typedef unsigned short UH;
+typedef signed int SS;
+typedef unsigned int US;
+typedef signed long long SLL;
+typedef unsigned long long ULL;
+
+#define DEF_MULLB(sign) \
+ void widen_mult_##sign##b (pR##sign##INT##16 a, \
+ pR##sign##INT##8 b, \
+ pR##sign##INT##8 c) \
+ { \
+ int i; \
+ for (i=0; i<N; i++) \
+ a[i] = (sign##H)b[i] * c[i]; \
+ }
+
+#define DEF_MULLH(sign) \
+ void widen_mult_##sign##h (pR##sign##INT##32 a, \
+ pR##sign##INT##16 b, \
+ pR##sign##INT##16 c) \
+ { \
+ int i; \
+ for (i=0; i<N; i++) \
+ a[i] = (sign##S)b[i] * c[i]; \
+ }
+#define DEF_MULLS(sign) \
+ void widen_mult_##sign##s (pR##sign##INT##64 a, \
+ pR##sign##INT##32 b, \
+ pR##sign##INT##32 c) \
+ { \
+ int i; \
+ for (i=0; i<N; i++) \
+ a[i] = (sign##LL)b[i] * c[i]; \
+ }
+
+#define DEF_MULL2(x) x (S) \
+ x (U)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c
new file mode 100644
index 0000000..7db1204
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c
@@ -0,0 +1,128 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps -ffast-math" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+extern float fabsf (float);
+extern double fabs (double);
+
+#define NUM_TESTS 16
+#define DELTA 0.000001
+
+int8_t input_int8[] = {1, 56, 2, -9, -90, 23, 54, 76,
+ -4, 34, 110, -110, 6, 4, 75, -34};
+int16_t input_int16[] = {1, 56, 2, -9, -90, 23, 54, 76,
+ -4, 34, 110, -110, 6, 4, 75, -34};
+int32_t input_int32[] = {1, 56, 2, -9, -90, 23, 54, 76,
+ -4, 34, 110, -110, 6, 4, 75, -34};
+int64_t input_int64[] = {1, 56, 2, -9, -90, 23, 54, 76,
+ -4, 34, 110, -110, 6, 4, 75, -34};
+
+uint8_t input_uint8[] = {1, 56, 2, 9, 90, 23, 54, 76,
+ 4, 34, 110, 110, 6, 4, 75, 34};
+uint16_t input_uint16[] = {1, 56, 2, 9, 90, 23, 54, 76,
+ 4, 34, 110, 110, 6, 4, 75, 34};
+uint32_t input_uint32[] = {1, 56, 2, 9, 90, 23, 54, 76,
+ 4, 34, 110, 110, 6, 4, 75, 34};
+
+uint64_t input_uint64[] = {1, 56, 2, 9, 90, 23, 54, 76,
+ 4, 34, 110, 110, 6, 4, 75, 34};
+
+float input_float32[] = {0.1f, -0.1f, 0.4f, 10.3f,
+ 200.0f, -800.0f, -13.0f, -0.5f,
+ 7.9f, -870.0f, 10.4f, 310.11f,
+ 0.0f, -865.0f, -2213.0f, -1.5f};
+
+double input_float64[] = {0.1, -0.1, 0.4, 10.3,
+ 200.0, -800.0, -13.0, -0.5,
+ 7.9, -870.0, 10.4, 310.11,
+ 0.0, -865.0, -2213.0, -1.5};
+
+#define EQUALF(a, b) (fabsf (a - b) < DELTA)
+#define EQUALD(a, b) (fabs (a - b) < DELTA)
+#define EQUALL(a, b) (a == b)
+
+#define TEST(SUFFIX, Q, TYPE, LANES, FLOAT) \
+int \
+test_vaddv##SUFFIX##_##TYPE##x##LANES##_t (void) \
+{ \
+ int i, j; \
+ int moves = (NUM_TESTS - LANES) + 1; \
+ TYPE##_t out_l[NUM_TESTS]; \
+ TYPE##_t out_v[NUM_TESTS]; \
+ \
+ /* Calculate linearly. */ \
+ for (i = 0; i < moves; i++) \
+ { \
+ out_l[i] = input_##TYPE[i]; \
+ for (j = 1; j < LANES; j++) \
+ out_l[i] += input_##TYPE[i + j]; \
+ } \
+ \
+ /* Calculate using vector reduction intrinsics. */ \
+ for (i = 0; i < moves; i++) \
+ { \
+ TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i); \
+ out_v[i] = vaddv##Q##_##SUFFIX (t1); \
+ } \
+ \
+ /* Compare. */ \
+ for (i = 0; i < moves; i++) \
+ { \
+ if (!EQUAL##FLOAT (out_v[i], out_l[i])) \
+ return 0; \
+ } \
+ return 1; \
+}
+
+#define BUILD_VARIANTS(TYPE, STYPE, W32, W64, F) \
+TEST (STYPE, , TYPE, W32, F) \
+TEST (STYPE, q, TYPE, W64, F) \
+
+BUILD_VARIANTS (int8, s8, 8, 16, L)
+BUILD_VARIANTS (uint8, u8, 8, 16, L)
+/* { dg-final { scan-assembler "addv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "addv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */
+BUILD_VARIANTS (int16, s16, 4, 8, L)
+BUILD_VARIANTS (uint16, u16, 4, 8, L)
+/* { dg-final { scan-assembler "addv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "addv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */
+BUILD_VARIANTS (int32, s32, 2, 4, L)
+BUILD_VARIANTS (uint32, u32, 2, 4, L)
+/* { dg-final { scan-assembler "addp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "addv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+TEST (s64, q, int64, 2, D)
+TEST (u64, q, uint64, 2, D)
+/* { dg-final { scan-assembler "addp\\td\[0-9\]+\, v\[0-9\]+\.2d" } } */
+
+BUILD_VARIANTS (float32, f32, 2, 4, F)
+/* { dg-final { scan-assembler "faddp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "faddp\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+TEST (f64, q, float64, 2, D)
+/* { dg-final { scan-assembler "faddp\\td\[0-9\]+\, v\[0-9\]+\.2d" } } */
+
+#undef TEST
+#define TEST(SUFFIX, Q, TYPE, LANES, FLOAT) \
+{ \
+ if (!test_vaddv##SUFFIX##_##TYPE##x##LANES##_t ()) \
+ abort (); \
+}
+
+int
+main (int argc, char **argv)
+{
+BUILD_VARIANTS (int8, s8, 8, 16, L)
+BUILD_VARIANTS (uint8, u8, 8, 16, L)
+BUILD_VARIANTS (int16, s16, 4, 8, L)
+BUILD_VARIANTS (uint16, u16, 4, 8, L)
+BUILD_VARIANTS (int32, s32, 2, 4, L)
+BUILD_VARIANTS (uint32, u32, 2, 4, L)
+
+BUILD_VARIANTS (float32, f32, 2, 4, F)
+TEST (f64, q, float64, 2, D)
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vca.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vca.c
new file mode 100644
index 0000000..c0cf2ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vca.c
@@ -0,0 +1,89 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+extern float fabsf (float);
+extern double fabs (double);
+
+#define NUM_TESTS 8
+
+float input_s1[] = {0.1f, -0.1f, 0.4f, 10.3f, 200.0f, -800.0f, -13.0f, -0.5f};
+float input_s2[] = {-0.2f, 0.4f, 0.04f, -100.3f, 2.0f, -80.0f, 13.0f, -0.5f};
+double input_d1[] = {0.1, -0.1, 0.4, 10.3, 200.0, -800.0, -13.0, -0.5};
+double input_d2[] = {-0.2, 0.4, 0.04, -100.3, 2.0, -80.0, 13.0, -0.5};
+
+#define TEST(T, CMP, SUFFIX, WIDTH, LANES, Q, F) \
+int \
+test_vca##T##_float##WIDTH##x##LANES##_t (void) \
+{ \
+ int ret = 0; \
+ int i = 0; \
+ uint##WIDTH##_t output[NUM_TESTS]; \
+ \
+ for (i = 0; i < NUM_TESTS; i++) \
+ { \
+ float##WIDTH##_t f1 = fabs##F (input_##SUFFIX##1[i]); \
+ float##WIDTH##_t f2 = fabs##F (input_##SUFFIX##2[i]); \
+ /* Inhibit optimization of our linear test loop. */ \
+ asm volatile ("" : : : "memory"); \
+ output[i] = f1 CMP f2 ? -1 : 0; \
+ } \
+ \
+ for (i = 0; i < NUM_TESTS; i += LANES) \
+ { \
+ float##WIDTH##x##LANES##_t in1 = \
+ vld1##Q##_f##WIDTH (input_##SUFFIX##1 + i); \
+ float##WIDTH##x##LANES##_t in2 = \
+ vld1##Q##_f##WIDTH (input_##SUFFIX##2 + i); \
+ uint##WIDTH##x##LANES##_t expected_out = \
+ vld1##Q##_u##WIDTH (output + i); \
+ uint##WIDTH##x##LANES##_t out = \
+ veor##Q##_u##WIDTH (vca##T##Q##_f##WIDTH (in1, in2), \
+ expected_out); \
+ vst1##Q##_u##WIDTH (output + i, out); \
+ } \
+ \
+ for (i = 0; i < NUM_TESTS; i++) \
+ ret |= output[i]; \
+ \
+ return ret; \
+}
+
+#define BUILD_VARIANTS(T, CMP) \
+TEST (T, CMP, s, 32, 2, , f) \
+TEST (T, CMP, s, 32, 4, q, f) \
+TEST (T, CMP, d, 64, 2, q, )
+
+BUILD_VARIANTS (ge, >=)
+/* { dg-final { scan-assembler "facge\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "facge\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "facge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+
+BUILD_VARIANTS (gt, >)
+/* { dg-final { scan-assembler "facgt\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "facgt\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "facgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+
+/* No need for another scan-assembler as these tests
+ also generate facge, facgt instructions. */
+BUILD_VARIANTS (le, <=)
+BUILD_VARIANTS (lt, <)
+
+#undef TEST
+#define TEST(T, CMP, SUFFIX, WIDTH, LANES, Q, F) \
+if (test_vca##T##_float##WIDTH##x##LANES##_t ()) \
+ abort ();
+
+int
+main (int argc, char **argv)
+{
+BUILD_VARIANTS (ge, >=)
+BUILD_VARIANTS (gt, >)
+BUILD_VARIANTS (le, <=)
+BUILD_VARIANTS (lt, <)
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vcvt.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vcvt.c
new file mode 100644
index 0000000..6066d7d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vcvt.c
@@ -0,0 +1,132 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps -ffast-math" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+extern double fabs (double);
+
+#define NUM_TESTS 8
+#define DELTA 0.000001
+
+float input_f32[] = {0.1f, -0.1f, 0.4f, 10.3f,
+ 200.0f, -800.0f, -13.0f, -0.5f};
+double input_f64[] = {0.1, -0.1, 0.4, 10.3,
+ 200.0, -800.0, -13.0, -0.5};
+
+#define TEST(SUFFIX, Q, WIDTH, LANES, S, U, D) \
+int \
+test_vcvt##SUFFIX##_##S##WIDTH##_f##WIDTH##x##LANES##_t (void) \
+{ \
+ int ret = 1; \
+ int i = 0; \
+ int nlanes = LANES; \
+ U##int##WIDTH##_t expected_out[NUM_TESTS]; \
+ U##int##WIDTH##_t actual_out[NUM_TESTS]; \
+ \
+ for (i = 0; i < NUM_TESTS; i++) \
+ { \
+ expected_out[i] \
+ = vcvt##SUFFIX##D##_##S##WIDTH##_f##WIDTH (input_f##WIDTH[i]); \
+ /* Don't vectorize this. */ \
+ asm volatile ("" : : : "memory"); \
+ } \
+ \
+ for (i = 0; i < NUM_TESTS; i+=nlanes) \
+ { \
+ U##int##WIDTH##x##LANES##_t out = \
+ vcvt##SUFFIX##Q##_##S##WIDTH##_f##WIDTH \
+ (vld1##Q##_f##WIDTH (input_f##WIDTH + i)); \
+ vst1##Q##_##S##WIDTH (actual_out + i, out); \
+ } \
+ \
+ for (i = 0; i < NUM_TESTS; i++) \
+ ret &= fabs (expected_out[i] - actual_out[i]) < DELTA; \
+ \
+ return ret; \
+} \
+
+
+#define BUILD_VARIANTS(SUFFIX) \
+TEST (SUFFIX, , 32, 2, s, ,s) \
+TEST (SUFFIX, q, 32, 4, s, ,s) \
+TEST (SUFFIX, q, 64, 2, s, ,d) \
+TEST (SUFFIX, , 32, 2, u,u,s) \
+TEST (SUFFIX, q, 32, 4, u,u,s) \
+TEST (SUFFIX, q, 64, 2, u,u,d) \
+
+BUILD_VARIANTS ( )
+/* { dg-final { scan-assembler "fcvtzs\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtzs\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcvtzu\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtzu\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (a)
+/* { dg-final { scan-assembler "fcvtas\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtas\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtas\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtas\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtas\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcvtau\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtau\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtau\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtau\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtau\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (m)
+/* { dg-final { scan-assembler "fcvtms\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtms\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtms\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtms\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtms\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcvtmu\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtmu\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtmu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtmu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtmu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (n)
+/* { dg-final { scan-assembler "fcvtns\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtns\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtns\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtns\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtns\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcvtnu\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtnu\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtnu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtnu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtnu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (p)
+/* { dg-final { scan-assembler "fcvtps\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtps\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtps\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtps\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtps\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcvtpu\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtpu\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtpu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtpu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtpu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+
+#undef TEST
+#define TEST(SUFFIX, Q, WIDTH, LANES, S, U, D) \
+{ \
+ if (!test_vcvt##SUFFIX##_##S##WIDTH##_f##WIDTH##x##LANES##_t ()) \
+ abort (); \
+}
+
+int
+main (int argc, char **argv)
+{
+ BUILD_VARIANTS ( )
+ BUILD_VARIANTS (a)
+ BUILD_VARIANTS (m)
+ BUILD_VARIANTS (n)
+ BUILD_VARIANTS (p)
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vfmaxv.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vfmaxv.c
new file mode 100644
index 0000000..58a57a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vfmaxv.c
@@ -0,0 +1,169 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps -ffast-math" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+
+extern float fabsf (float);
+extern double fabs (double);
+extern int isnan (double);
+extern float fmaxf (float, float);
+extern float fminf (float, float);
+extern double fmax (double, double);
+extern double fmin (double, double);
+
+#define NUM_TESTS 16
+#define DELTA 0.000001
+#define NAN (0.0 / 0.0)
+
+float input_float32[] = {0.1f, -0.1f, 0.4f, 10.3f,
+ 200.0f, -800.0f, -13.0f, -0.5f,
+ NAN, -870.0f, 10.4f, 310.11f,
+ 0.0f, -865.0f, -2213.0f, -1.5f};
+
+double input_float64[] = {0.1, -0.1, 0.4, 10.3,
+ 200.0, -800.0, -13.0, -0.5,
+ NAN, -870.0, 10.4, 310.11,
+ 0.0, -865.0, -2213.0, -1.5};
+
+#define EQUALF(a, b) (fabsf (a - b) < DELTA)
+#define EQUALD(a, b) (fabs (a - b) < DELTA)
+
+/* Floating point 'unordered' variants. */
+
+#undef TEST
+#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES, FLOAT) \
+int \
+test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t (void) \
+{ \
+ int i, j; \
+ int moves = (NUM_TESTS - LANES) + 1; \
+ TYPE##_t out_l[NUM_TESTS]; \
+ TYPE##_t out_v[NUM_TESTS]; \
+ \
+ /* Calculate linearly. */ \
+ for (i = 0; i < moves; i++) \
+ { \
+ out_l[i] = input_##TYPE[i]; \
+ for (j = 0; j < LANES; j++) \
+ { \
+ if (isnan (out_l[i])) \
+ continue; \
+ if (isnan (input_##TYPE[i + j]) \
+ || input_##TYPE[i + j] CMP_OP out_l[i]) \
+ out_l[i] = input_##TYPE[i + j]; \
+ } \
+ } \
+ \
+ /* Calculate using vector reduction intrinsics. */ \
+ for (i = 0; i < moves; i++) \
+ { \
+ TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i); \
+ out_v[i] = v##MAXMIN##v##Q##_##SUFFIX (t1); \
+ } \
+ \
+ /* Compare. */ \
+ for (i = 0; i < moves; i++) \
+ { \
+ if (!EQUAL##FLOAT (out_v[i], out_l[i]) \
+ && !(isnan (out_v[i]) && isnan (out_l[i]))) \
+ return 0; \
+ } \
+ return 1; \
+}
+
+#define BUILD_VARIANTS(TYPE, STYPE, W32, W64, F) \
+TEST (max, >, STYPE, , TYPE, W32, F) \
+TEST (max, >, STYPE, q, TYPE, W64, F) \
+TEST (min, <, STYPE, , TYPE, W32, F) \
+TEST (min, <, STYPE, q, TYPE, W64, F)
+
+BUILD_VARIANTS (float32, f32, 2, 4, F)
+/* { dg-final { scan-assembler "fmaxp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fminp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fmaxv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fminv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+TEST (max, >, f64, q, float64, 2, D)
+/* { dg-final { scan-assembler "fmaxp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */
+TEST (min, <, f64, q, float64, 2, D)
+/* { dg-final { scan-assembler "fminp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */
+
+/* Floating point 'nm' variants. */
+
+#undef TEST
+#define TEST(MAXMIN, F, SUFFIX, Q, TYPE, LANES, FLOAT) \
+int \
+test_v##MAXMIN##nmv##SUFFIX##_##TYPE##x##LANES##_t (void) \
+{ \
+ int i, j; \
+ int moves = (NUM_TESTS - LANES) + 1; \
+ TYPE##_t out_l[NUM_TESTS]; \
+ TYPE##_t out_v[NUM_TESTS]; \
+ \
+ /* Calculate linearly. */ \
+ for (i = 0; i < moves; i++) \
+ { \
+ out_l[i] = input_##TYPE[i]; \
+ for (j = 0; j < LANES; j++) \
+ out_l[i] = f##MAXMIN##F (input_##TYPE[i + j], out_l[i]); \
+ } \
+ \
+ /* Calculate using vector reduction intrinsics. */ \
+ for (i = 0; i < moves; i++) \
+ { \
+ TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i); \
+ out_v[i] = v##MAXMIN##nmv##Q##_##SUFFIX (t1); \
+ } \
+ \
+ /* Compare. */ \
+ for (i = 0; i < moves; i++) \
+ { \
+ if (!EQUAL##FLOAT (out_v[i], out_l[i])) \
+ return 0; \
+ } \
+ return 1; \
+}
+
+TEST (max, f, f32, , float32, 2, D)
+/* { dg-final { scan-assembler "fmaxnmp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */
+TEST (min, f, f32, , float32, 2, D)
+/* { dg-final { scan-assembler "fminnmp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */
+TEST (max, f, f32, q, float32, 4, D)
+/* { dg-final { scan-assembler "fmaxnmv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+TEST (min, f, f32, q, float32, 4, D)
+/* { dg-final { scan-assembler "fminnmv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+TEST (max, , f64, q, float64, 2, D)
+/* { dg-final { scan-assembler "fmaxnmp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */
+TEST (min, , f64, q, float64, 2, D)
+/* { dg-final { scan-assembler "fminnmp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */
+
+#undef TEST
+#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES, FLOAT) \
+{ \
+ if (!test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t ()) \
+ abort (); \
+}
+
+int
+main (int argc, char **argv)
+{
+ BUILD_VARIANTS (float32, f32, 2, 4, F)
+ TEST (max, >, f64, q, float64, 2, D)
+ TEST (min, <, f64, q, float64, 2, D)
+
+#undef TEST
+#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES, FLOAT) \
+{ \
+ if (!test_v##MAXMIN##nmv##SUFFIX##_##TYPE##x##LANES##_t ()) \
+ abort (); \
+}
+
+ BUILD_VARIANTS (float32, f32, 2, 4, F)
+ TEST (max, >, f64, q, float64, 2, D)
+ TEST (min, <, f64, q, float64, 2, D)
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c
new file mode 100644
index 0000000..212e133
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c
@@ -0,0 +1,117 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps -ffast-math" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+
+#define NUM_TESTS 16
+#define DELTA 0.000001
+
+int8_t input_int8[] = {1, 56, 2, -9, -90, 23, 54, 76,
+ -4, 34, 110, -110, 6, 4, 75, -34};
+int16_t input_int16[] = {1, 56, 2, -9, -90, 23, 54, 76,
+ -4, 34, 110, -110, 6, 4, 75, -34};
+int32_t input_int32[] = {1, 56, 2, -9, -90, 23, 54, 76,
+ -4, 34, 110, -110, 6, 4, 75, -34};
+
+uint8_t input_uint8[] = {1, 56, 2, 9, 90, 23, 54, 76,
+ 4, 34, 110, 110, 6, 4, 75, 34};
+uint16_t input_uint16[] = {1, 56, 2, 9, 90, 23, 54, 76,
+ 4, 34, 110, 110, 6, 4, 75, 34};
+uint32_t input_uint32[] = {1, 56, 2, 9, 90, 23, 54, 76,
+ 4, 34, 110, 110, 6, 4, 75, 34};
+
+#define EQUAL(a, b) (a == b)
+
+#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES) \
+int \
+test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t (void) \
+{ \
+ int i, j; \
+ int moves = (NUM_TESTS - LANES) + 1; \
+ TYPE##_t out_l[NUM_TESTS]; \
+ TYPE##_t out_v[NUM_TESTS]; \
+ \
+ /* Calculate linearly. */ \
+ for (i = 0; i < moves; i++) \
+ { \
+ out_l[i] = input_##TYPE[i]; \
+ for (j = 0; j < LANES; j++) \
+ out_l[i] = input_##TYPE[i + j] CMP_OP out_l[i] ? \
+ input_##TYPE[i + j] : out_l[i]; \
+ } \
+ \
+ /* Calculate using vector reduction intrinsics. */ \
+ for (i = 0; i < moves; i++) \
+ { \
+ TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i); \
+ out_v[i] = v##MAXMIN##v##Q##_##SUFFIX (t1); \
+ } \
+ \
+ /* Compare. */ \
+ for (i = 0; i < moves; i++) \
+ { \
+ if (!EQUAL (out_v[i], out_l[i])) \
+ return 0; \
+ } \
+ return 1; \
+}
+
+#define BUILD_VARIANTS(TYPE, STYPE, W32, W64) \
+TEST (max, >, STYPE, , TYPE, W32) \
+TEST (max, >, STYPE, q, TYPE, W64) \
+TEST (min, <, STYPE, , TYPE, W32) \
+TEST (min, <, STYPE, q, TYPE, W64)
+
+BUILD_VARIANTS (int8, s8, 8, 16)
+/* { dg-final { scan-assembler "smaxv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "sminv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "smaxv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */
+/* { dg-final { scan-assembler "sminv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */
+BUILD_VARIANTS (uint8, u8, 8, 16)
+/* { dg-final { scan-assembler "umaxv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "uminv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "umaxv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */
+/* { dg-final { scan-assembler "uminv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */
+BUILD_VARIANTS (int16, s16, 4, 8)
+/* { dg-final { scan-assembler "smaxv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "sminv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "smaxv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */
+/* { dg-final { scan-assembler "sminv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */
+BUILD_VARIANTS (uint16, u16, 4, 8)
+/* { dg-final { scan-assembler "umaxv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "uminv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "umaxv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */
+/* { dg-final { scan-assembler "uminv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */
+BUILD_VARIANTS (int32, s32, 2, 4)
+/* { dg-final { scan-assembler "smaxp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "sminp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "smaxv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "sminv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+BUILD_VARIANTS (uint32, u32, 2, 4)
+/* { dg-final { scan-assembler "umaxp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "uminp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "umaxv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "uminv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+
+#undef TEST
+#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES) \
+{ \
+ if (!test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t ()) \
+ abort (); \
+}
+
+int
+main (int argc, char **argv)
+{
+ BUILD_VARIANTS (int8, s8, 8, 16)
+ BUILD_VARIANTS (uint8, u8, 8, 16)
+ BUILD_VARIANTS (int16, s16, 4, 8)
+ BUILD_VARIANTS (uint16, u16, 4, 8)
+ BUILD_VARIANTS (int32, s32, 2, 4)
+ BUILD_VARIANTS (uint32, u32, 2, 4)
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vrnd.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vrnd.c
new file mode 100644
index 0000000..aa3fd9b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vrnd.c
@@ -0,0 +1,117 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+extern float fabsf (float);
+extern double fabs (double);
+
+extern double trunc (double);
+extern double round (double);
+extern double nearbyint (double);
+extern double floor (double);
+extern double ceil (double);
+extern double rint (double);
+
+extern float truncf (float);
+extern float roundf (float);
+extern float nearbyintf (float);
+extern float floorf (float);
+extern float ceilf (float);
+extern float rintf (float);
+
+#define NUM_TESTS 8
+#define DELTA 0.000001
+
+float input_f32[] = {0.1f, -0.1f, 0.4f, 10.3f,
+ 200.0f, -800.0f, -13.0f, -0.5f};
+double input_f64[] = {0.1, -0.1, 0.4, 10.3,
+ 200.0, -800.0, -13.0, -0.5};
+
+#define TEST(SUFFIX, Q, WIDTH, LANES, C_FN, F) \
+int \
+test_vrnd##SUFFIX##_float##WIDTH##x##LANES##_t (void) \
+{ \
+ int ret = 1; \
+ int i = 0; \
+ int nlanes = LANES; \
+ float##WIDTH##_t expected_out[NUM_TESTS]; \
+ float##WIDTH##_t actual_out[NUM_TESTS]; \
+ \
+ for (i = 0; i < NUM_TESTS; i++) \
+ { \
+ expected_out[i] = C_FN##F (input_f##WIDTH[i]); \
+ /* Don't vectorize this. */ \
+ asm volatile ("" : : : "memory"); \
+ } \
+ \
+ /* Prevent the compiler from noticing these two loops do the same \
+ thing and optimizing away the comparison. */ \
+ asm volatile ("" : : : "memory"); \
+ \
+ for (i = 0; i < NUM_TESTS; i+=nlanes) \
+ { \
+ float##WIDTH##x##LANES##_t out = \
+ vrnd##SUFFIX##Q##_f##WIDTH \
+ (vld1##Q##_f##WIDTH (input_f##WIDTH + i)); \
+ vst1##Q##_f##WIDTH (actual_out + i, out); \
+ } \
+ \
+ for (i = 0; i < NUM_TESTS; i++) \
+ ret &= fabs##F (expected_out[i] - actual_out[i]) < DELTA; \
+ \
+ return ret; \
+} \
+
+
+#define BUILD_VARIANTS(SUFFIX, C_FN) \
+TEST (SUFFIX, , 32, 2, C_FN, f) \
+TEST (SUFFIX, q, 32, 4, C_FN, f) \
+TEST (SUFFIX, q, 64, 2, C_FN, ) \
+
+BUILD_VARIANTS ( , trunc)
+/* { dg-final { scan-assembler "frintz\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "frintz\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "frintz\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (a, round)
+/* { dg-final { scan-assembler "frinta\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "frinta\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "frinta\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (i, nearbyint)
+/* { dg-final { scan-assembler "frinti\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "frinti\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "frinti\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (m, floor)
+/* { dg-final { scan-assembler "frintm\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "frintm\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "frintm\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (p, ceil)
+/* { dg-final { scan-assembler "frintp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "frintp\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "frintp\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (x, rint)
+/* { dg-final { scan-assembler "frintx\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "frintx\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "frintx\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+
+#undef TEST
+#define TEST(SUFFIX, Q, WIDTH, LANES, C_FN, F) \
+{ \
+ if (!test_vrnd##SUFFIX##_float##WIDTH##x##LANES##_t ()) \
+ abort (); \
+}
+
+int
+main (int argc, char **argv)
+{
+ BUILD_VARIANTS ( , trunc)
+ BUILD_VARIANTS (a, round)
+ BUILD_VARIANTS (i, nearbyint)
+ BUILD_VARIANTS (m, floor)
+ BUILD_VARIANTS (p, ceil)
+ BUILD_VARIANTS (x, rint)
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect.c
new file mode 100644
index 0000000..ff70cae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect.c
@@ -0,0 +1,97 @@
+
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#include "vect.x"
+
+extern void abort (void);
+
+void set_vector (int *a, int n)
+{
+ int i;
+ for (i=0; i<16; i++)
+ a[i] = n;
+}
+
+void check_vector (pRINT c, pRINT result, char *str)
+{
+ int i;
+ for (i=0; i<16 ; i++)
+ if (c[i] != result[i])
+ abort ();
+}
+
+#define TEST(func, sign) set_vector (sign##c, 0); \
+ func (sign##a, sign##b, sign##c); \
+ check_vector (sign##c, func##_vector, #func);
+
+
+#define TESTV(func, sign) \
+ if (func (sign##a) != func##_value) \
+ abort ();
+
+#define TESTVLL(func, sign) \
+ if (func (ll##sign##a) != func##_value) \
+ abort ();
+
+int main (void)
+{
+ int sa[16];
+ int sb[16];
+ int sc[16];
+ unsigned int ua[16];
+ unsigned int ub[16];
+ unsigned int uc[16];
+ long long llsa[16];
+ unsigned long long llua[16];
+ int i;
+
+ /* Table of standard values to compare against. */
+ unsigned int test_bic_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+ unsigned int test_orn_vector[] = {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1};
+ int mla_vector[] = {0, 1, 4, 9, 16, 25, 36, 49, 64, 81, 100, 121, 144, 169, 196, 225};
+ int mls_vector[] = {0, -1, -4, -9, -16, -25, -36, -49, -64, -81, -100, -121, -144, -169, -196, -225};
+ int smax_vector[] = {0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15};
+ int smin_vector[] = {0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15};
+ unsigned int umax_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
+ unsigned int umin_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
+ int sabd_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+ int saba_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+ int reduce_smax_value = 0;
+ int reduce_smin_value = -15;
+ unsigned int reduce_umax_value = 15;
+ unsigned int reduce_umin_value = 0;
+ unsigned int reduce_add_u32_value = 120;
+ int reduce_add_s32_value = -120;
+ long long reduce_add_s64_value = -120;
+ unsigned long long reduce_add_u64_value = 120;
+
+ /* Set up input vectors. */
+ for (i=0; i < 16; i++)
+ {
+ sa[i] = sb[i] = -i;
+ llsa[i] = (long long)-i;
+ ua[i] = ub[i] = i;
+ llua[i] = (unsigned long long)i;
+ }
+
+ TEST (test_bic, s);
+ TEST (test_orn, s);
+ TEST (mla, s);
+ TEST (mls, s);
+ TEST (smax, s);
+ TEST (smin, s);
+ TEST (umax, u);
+ TEST (umin, u);
+ TEST (sabd, s);
+ TEST (saba, s);
+ TESTV (reduce_smax, s);
+ TESTV (reduce_smin, s);
+ TESTV (reduce_umax, u);
+ TESTV (reduce_umin, u);
+ TESTV (reduce_add_u32, u);
+ TESTV (reduce_add_s32, s);
+ TESTVLL (reduce_add_u64, u);
+ TESTVLL (reduce_add_s64, s);
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect.x
new file mode 100644
index 0000000..c0f79b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect.x
@@ -0,0 +1,154 @@
+typedef int *__restrict__ pRINT;
+typedef unsigned int *__restrict__ pRUINT;
+typedef long long *__restrict__ pRINT64;
+typedef unsigned long long *__restrict__ pRUINT64;
+
+void test_orn (pRUINT a, pRUINT b, pRUINT c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ c[i] = a[i] | (~b[i]);
+}
+
+void test_bic (pRUINT a, pRUINT b, pRUINT c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ c[i] = a[i] & (~b[i]);
+}
+
+void mla (pRINT a, pRINT b, pRINT c)
+{
+ int i;
+ for (i=0;i<16;i++)
+ c[i] += a[i] * b[i];
+}
+
+void mls (pRINT a, pRINT b, pRINT c)
+{
+ int i;
+ for (i=0;i<16;i++)
+ c[i] -= a[i] * b[i];
+}
+
+void smax (pRINT a, pRINT b, pRINT c)
+{
+ int i;
+ for (i=0;i<16;i++)
+ c[i] = (a[i] > b[i] ? a[i] : b[i]);
+}
+
+void smin (pRINT a, pRINT b, pRINT c)
+{
+ int i;
+ for (i=0;i<16;i++)
+ c[i] = (a[i] < b[i] ? a[i] : b[i]);
+}
+
+void umax (pRUINT a, pRUINT b, pRUINT c)
+{
+ int i;
+ for (i=0;i<16;i++)
+ c[i] = (a[i] > b[i] ? a[i] : b[i]);
+}
+
+void umin (pRUINT a, pRUINT b, pRUINT c)
+{
+ int i;
+ for (i=0;i<16;i++)
+ c[i] = (a[i] < b[i] ? a[i] : b[i]);
+}
+
+unsigned int reduce_umax (pRUINT a)
+{
+ int i;
+ unsigned int s = a[0];
+ for (i = 1; i < 16; i++)
+ s = (s > a[i] ? s : a[i]);
+
+ return s;
+}
+
+unsigned int reduce_umin (pRUINT a)
+{
+ int i;
+ unsigned int s = a[0];
+ for (i = 1; i < 16; i++)
+ s = (s < a[i] ? s : a[i]);
+
+ return s;
+}
+
+int reduce_smax (pRINT a)
+{
+ int i;
+ int s = a[0];
+ for (i = 1; i < 16; i++)
+ s = (s > a[i] ? s : a[i]);
+
+ return s;
+}
+
+int reduce_smin (pRINT a)
+{
+ int i;
+ int s = a[0];
+ for (i = 1; i < 16; i++)
+ s = (s < a[i] ? s : a[i]);
+
+ return s;
+}
+
+unsigned int reduce_add_u32 (pRINT a)
+{
+ int i;
+ unsigned int s = 0;
+ for (i = 0; i < 16; i++)
+ s += a[i];
+
+ return s;
+}
+
+int reduce_add_s32 (pRINT a)
+{
+ int i;
+ int s = 0;
+ for (i = 0; i < 16; i++)
+ s += a[i];
+
+ return s;
+}
+
+unsigned long long reduce_add_u64 (pRUINT64 a)
+{
+ int i;
+ unsigned long long s = 0;
+ for (i = 0; i < 16; i++)
+ s += a[i];
+
+ return s;
+}
+
+long long reduce_add_s64 (pRINT64 a)
+{
+ int i;
+ long long s = 0;
+ for (i = 0; i < 16; i++)
+ s += a[i];
+
+ return s;
+}
+
+void sabd (pRINT a, pRINT b, pRINT c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ c[i] = abs (a[i] - b[i]);
+}
+
+void saba (pRINT a, pRINT b, pRINT c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ c[i] += abs (a[i] - b[i]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect_saddl_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect_saddl_1.c
new file mode 100644
index 0000000..ecbd8a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect_saddl_1.c
@@ -0,0 +1,315 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -fno-inline -save-temps -fno-vect-cost-model" } */
+
+typedef signed char S8_t;
+typedef signed short S16_t;
+typedef signed int S32_t;
+typedef signed long long S64_t;
+
+typedef signed char *__restrict__ pS8_t;
+typedef signed short *__restrict__ pS16_t;
+typedef signed int *__restrict__ pS32_t;
+typedef signed long long *__restrict__ pS64_t;
+
+typedef unsigned char U8_t;
+typedef unsigned short U16_t;
+typedef unsigned int U32_t;
+typedef unsigned long long U64_t;
+
+typedef unsigned char *__restrict__ pU8_t;
+typedef unsigned short *__restrict__ pU16_t;
+typedef unsigned int *__restrict__ pU32_t;
+typedef unsigned long long *__restrict__ pU64_t;
+
+extern void abort ();
+
+void
+test_addl_S64_S32_4 (pS64_t a, pS32_t b, pS32_t c)
+{
+ int i;
+ for (i = 0; i < 4; i++)
+ a[i] = (S64_t) b[i] + (S64_t) c[i];
+}
+/* "saddl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" */
+/* "saddl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" */
+
+/* a = -b + c => a = c - b */
+void
+test_addl_S64_S32_4_neg0 (pS64_t a, pS32_t b, pS32_t c)
+{
+ int i;
+ for (i = 0; i < 4; i++)
+ a[i] = -(S64_t) b[i] + (S64_t) c[i];
+}
+/* "ssubl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" */
+/* "ssubl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" */
+
+/* a = b + -c => a = b - c */
+void
+test_addl_S64_S32_4_neg1 (pS64_t a, pS32_t b, pS32_t c)
+{
+ int i;
+ for (i = 0; i < 4; i++)
+ a[i] = (S64_t) b[i] + -(S64_t) c[i];
+}
+/* "ssubl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" */
+/* "ssubl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" */
+
+void
+test_addl_S32_S16_8 (pS32_t a, pS16_t b, pS16_t c)
+{
+ int i;
+ for (i = 0; i < 8; i++)
+ a[i] = (S32_t) b[i] + (S32_t) c[i];
+}
+/* { dg-final { scan-assembler "saddl\tv\[0-9\]+\.4s,\ v\[0-9\]+\.4h,\ v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "saddl2\tv\[0-9\]+\.4s,\ v\[0-9\]+\.8h,\ v\[0-9\]+\.8h" } } */
+
+void
+test_addl_S16_S8_16 (pS16_t a, pS8_t b, pS8_t c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ a[i] = (S16_t) b[i] + (S16_t) c[i];
+}
+/* { dg-final { scan-assembler "saddl\tv\[0-9\]+\.8h,\ v\[0-9\]+\.8b,\ v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "saddl2\tv\[0-9\]+\.8h,\ v\[0-9\]+\.16b,\ v\[0-9\]+\.16b" } } */
+
+void
+test_addl_U64_U32_4 (pU64_t a, pU32_t b, pU32_t c)
+{
+ int i;
+ for (i = 0; i < 4; i++)
+ a[i] = (U64_t) b[i] + (U64_t) c[i];
+}
+/* { dg-final { scan-assembler "uaddl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "uaddl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" } } */
+
+void
+test_addl_U32_U16_8 (pU32_t a, pU16_t b, pU16_t c)
+{
+ int i;
+ for (i = 0; i < 8; i++)
+ a[i] = (U32_t) b[i] + (U32_t) c[i];
+}
+/* { dg-final { scan-assembler "uaddl\tv\[0-9\]+\.4s,\ v\[0-9\]+\.4h,\ v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "uaddl2\tv\[0-9\]+\.4s,\ v\[0-9\]+\.8h,\ v\[0-9\]+\.8h" } } */
+
+void
+test_addl_U16_U8_16 (pU16_t a, pU8_t b, pU8_t c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ a[i] = (U16_t) b[i] + (U16_t) c[i];
+}
+/* { dg-final { scan-assembler "uaddl\tv\[0-9\]+\.8h,\ v\[0-9\]+\.8b,\ v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "uaddl2\tv\[0-9\]+\.8h,\ v\[0-9\]+\.16b,\ v\[0-9\]+\.16b" } } */
+
+void
+test_subl_S64_S32_4 (pS64_t a, pS32_t b, pS32_t c)
+{
+ int i;
+ for (i = 0; i < 4; i++)
+ a[i] = (S64_t) b[i] - (S64_t) c[i];
+}
+/* "ssubl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" */
+/* "ssubl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" */
+
+/* a = b - -c => a = b + c */
+void
+test_subl_S64_S32_4_neg0 (pS64_t a, pS32_t b, pS32_t c)
+{
+ int i;
+ for (i = 0; i < 4; i++)
+ a[i] = (S64_t) b[i] - -(S64_t) c[i];
+}
+/* { dg-final { scan-assembler-times "saddl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" 2 } } */
+/* { dg-final { scan-assembler-times "saddl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" 2 } } */
+
+/* a = -b - -c => a = c - b */
+void
+test_subl_S64_S32_4_neg1 (pS64_t a, pS32_t b, pS32_t c)
+{
+ int i;
+ for (i = 0; i < 4; i++)
+ a[i] = -(S64_t) b[i] - -(S64_t) c[i];
+}
+/* "ssubl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" */
+/* "ssubl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" */
+
+/* a = -(b - c) => a = c - b */
+void
+test_subl_S64_S32_4_neg2 (pS64_t a, pS32_t b, pS32_t c)
+{
+ int i;
+ for (i = 0; i < 4; i++)
+ a[i] = -((S64_t) b[i] - (S64_t) c[i]);
+}
+/* { dg-final { scan-assembler-times "ssubl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" 5 } } */
+/* { dg-final { scan-assembler-times "ssubl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" 5 } } */
+
+void
+test_subl_S32_S16_8 (pS32_t a, pS16_t b, pS16_t c)
+{
+ int i;
+ for (i = 0; i < 8; i++)
+ a[i] = (S32_t) b[i] - (S32_t) c[i];
+}
+/* { dg-final { scan-assembler "ssubl\tv\[0-9\]+\.4s,\ v\[0-9\]+\.4h,\ v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "ssubl2\tv\[0-9\]+\.4s,\ v\[0-9\]+\.8h,\ v\[0-9\]+\.8h" } } */
+
+void
+test_subl_S16_S8_16 (pS16_t a, pS8_t b, pS8_t c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ a[i] = (S16_t) b[i] - (S16_t) c[i];
+}
+/* { dg-final { scan-assembler "ssubl\tv\[0-9\]+\.8h,\ v\[0-9\]+\.8b,\ v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "ssubl2\tv\[0-9\]+\.8h,\ v\[0-9\]+\.16b,\ v\[0-9\]+\.16b" } } */
+
+void
+test_subl_U64_U32_4 (pU64_t a, pU32_t b, pU32_t c)
+{
+ int i;
+ for (i = 0; i < 4; i++)
+ a[i] = (U64_t) b[i] - (U64_t) c[i];
+}
+/* { dg-final { scan-assembler "usubl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "usubl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" } } */
+
+void
+test_subl_U32_U16_8 (pU32_t a, pU16_t b, pU16_t c)
+{
+ int i;
+ for (i = 0; i < 8; i++)
+ a[i] = (U32_t) b[i] - (U32_t) c[i];
+}
+/* { dg-final { scan-assembler "usubl\tv\[0-9\]+\.4s,\ v\[0-9\]+\.4h,\ v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "usubl2\tv\[0-9\]+\.4s,\ v\[0-9\]+\.8h,\ v\[0-9\]+\.8h" } } */
+
+void
+test_subl_U16_U8_16 (pU16_t a, pU8_t b, pU8_t c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ a[i] = (U16_t) b[i] - (U16_t) c[i];
+}
+/* { dg-final { scan-assembler "usubl\tv\[0-9\]+\.8h,\ v\[0-9\]+\.8b,\ v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "usubl2\tv\[0-9\]+\.8h,\ v\[0-9\]+\.16b,\ v\[0-9\]+\.16b" } } */
+
+/* input values */
+
+S64_t S64_ta[4];
+S32_t S32_tb[4] = { 0, 1, 2, 3 };
+S32_t S32_tc[4] = { 2, 2, -2, -2 };
+
+S32_t S32_ta[8];
+S16_t S16_tb[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+S16_t S16_tc[8] = { 2, 2, -2, -2, 2, 2, -2, -2 };
+
+S16_t S16_ta[16];
+S8_t S8_tb[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+S8_t S8_tc[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 };
+
+/* expected output */
+
+S64_t addl_rS64[] = { 2, 3, 0, 1 };
+S64_t neg_r[] = { 2, 1, -4, -5 };
+S32_t addl_rS32[] = { 2, 3, 0, 1, 6, 7, 4, 5 };
+S16_t addl_rS16[] = { 2, 3, 0, 1, 6, 7, 4, 5, 10, 11, 8, 9, 14, 15, 12, 13 };
+S64_t subl_rS64[] = { -2, -1, 4, 5 };
+S32_t subl_rS32[] = { -2, -1, 4, 5, 2, 3, 8, 9 };
+S16_t subl_rS16[] =
+ { -2, -1, 4, 5, 2, 3, 8, 9, 6, 7, 12, 13, 10, 11, 16, 17 };
+U64_t addl_rU64[] = { 2, 3, 0x100000000, 0x100000001 };
+U32_t addl_rU32[] = { 2, 3, 0x10000, 0x10001, 6, 7, 0x10004, 0x10005 };
+U16_t addl_rU16[] =
+{
+ 0x0002, 0x0003, 0x0100, 0x0101, 0x0006, 0x0007, 0x0104, 0x0105,
+ 0x000a, 0x000b, 0x0108, 0x0109, 0x000e, 0x000f, 0x010c, 0x010d
+};
+U64_t subl_rU64[] =
+{
+ 0xfffffffffffffffe, 0xffffffffffffffff,
+ 0xffffffff00000004, 0xffffffff00000005
+};
+U32_t subl_rU32[] =
+{
+ 0xfffffffe, 0xffffffff, 0xffff0004, 0xffff0005,
+ 0x00000002, 0x00000003, 0xffff0008, 0xffff0009
+};
+U16_t subl_rU16[] =
+{
+ 0xfffe, 0xffff, 0xff04, 0xff05, 0x0002, 0x0003, 0xff08, 0xff09,
+ 0x0006, 0x0007, 0xff0c, 0xff0d, 0x000a, 0x000b, 0xff10, 0xff11
+};
+
+#define CHECK(T,N,AS,US) \
+do \
+ { \
+ for (i = 0; i < N; i++) \
+ if ((US##T##_t)S##T##_ta[i] != AS##_##r##US##T[i]) \
+ abort(); \
+ } \
+while (0)
+
+#define NCHECK(RES) \
+do \
+ { \
+ for (i = 0; i < 4; i++) \
+ if (S64_ta[i] != RES[i]) \
+ abort (); \
+ } \
+while (0)
+
+#define SCHECK(T,N,AS) CHECK(T,N,AS,S)
+#define UCHECK(T,N,AS) CHECK(T,N,AS,U)
+
+int
+main ()
+{
+ int i;
+
+ test_addl_S64_S32_4 (S64_ta, S32_tb, S32_tc);
+ SCHECK (64, 4, addl);
+ test_addl_S32_S16_8 (S32_ta, S16_tb, S16_tc);
+ SCHECK (32, 8, addl);
+ test_addl_S16_S8_16 (S16_ta, S8_tb, S8_tc);
+ SCHECK (16, 16, addl);
+ test_subl_S64_S32_4 (S64_ta, S32_tb, S32_tc);
+ SCHECK (64, 4, subl);
+ test_subl_S32_S16_8 (S32_ta, S16_tb, S16_tc);
+ SCHECK (32, 8, subl);
+ test_subl_S16_S8_16 (S16_ta, S8_tb, S8_tc);
+ SCHECK (16, 16, subl);
+
+ test_addl_U64_U32_4 (S64_ta, S32_tb, S32_tc);
+ UCHECK (64, 4, addl);
+ test_addl_U32_U16_8 (S32_ta, S16_tb, S16_tc);
+ UCHECK (32, 8, addl);
+ test_addl_U16_U8_16 (S16_ta, S8_tb, S8_tc);
+ UCHECK (16, 16, addl);
+ test_subl_U64_U32_4 (S64_ta, S32_tb, S32_tc);
+ UCHECK (64, 4, subl);
+ test_subl_U32_U16_8 (S32_ta, S16_tb, S16_tc);
+ UCHECK (32, 8, subl);
+ test_subl_U16_U8_16 (S16_ta, S8_tb, S8_tc);
+ UCHECK (16, 16, subl);
+
+ test_addl_S64_S32_4_neg0 (S64_ta, S32_tb, S32_tc);
+ NCHECK (neg_r);
+ test_addl_S64_S32_4_neg1 (S64_ta, S32_tb, S32_tc);
+ NCHECK (subl_rS64);
+ test_subl_S64_S32_4_neg0 (S64_ta, S32_tb, S32_tc);
+ NCHECK (addl_rS64);
+ test_subl_S64_S32_4_neg1 (S64_ta, S32_tb, S32_tc);
+ NCHECK (neg_r);
+ test_subl_S64_S32_4_neg2 (S64_ta, S32_tb, S32_tc);
+ NCHECK (neg_r);
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
new file mode 100644
index 0000000..b70be4c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
@@ -0,0 +1,325 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -fno-inline -save-temps -fno-vect-cost-model" } */
+
+typedef signed char S8_t;
+typedef signed short S16_t;
+typedef signed int S32_t;
+typedef signed long long S64_t;
+typedef signed char *__restrict__ pS8_t;
+typedef signed short *__restrict__ pS16_t;
+typedef signed int *__restrict__ pS32_t;
+typedef signed long long *__restrict__ pS64_t;
+typedef unsigned char U8_t;
+typedef unsigned short U16_t;
+typedef unsigned int U32_t;
+typedef unsigned long long U64_t;
+typedef unsigned char *__restrict__ pU8_t;
+typedef unsigned short *__restrict__ pU16_t;
+typedef unsigned int *__restrict__ pU32_t;
+typedef unsigned long long *__restrict__ pU64_t;
+
+extern void abort ();
+
+void
+test_addS64_tS32_t4 (pS64_t a, pS32_t b, pS32_t c)
+{
+ int i;
+ for (i = 0; i < 4; i++)
+ a[i] += (S64_t) b[i] * (S64_t) c[i];
+}
+
+/* { dg-final { scan-assembler "smlal\tv\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "smlal2\tv\[0-9\]+\.2d" } } */
+
+void
+test_addS32_tS16_t8 (pS32_t a, pS16_t b, pS16_t c)
+{
+ int i;
+ for (i = 0; i < 8; i++)
+ a[i] += (S32_t) b[i] * (S32_t) c[i];
+}
+
+/* { dg-final { scan-assembler "smlal\tv\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "smlal2\tv\[0-9\]+\.4s" } } */
+
+void
+test_addS16_tS8_t16 (pS16_t a, pS8_t b, pS8_t c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ a[i] += (S16_t) b[i] * (S16_t) c[i];
+}
+
+void
+test_addS16_tS8_t16_neg0 (pS16_t a, pS8_t b, pS8_t c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ a[i] += (S16_t) -b[i] * (S16_t) -c[i];
+}
+
+void
+test_addS16_tS8_t16_neg1 (pS16_t a, pS8_t b, pS8_t c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ a[i] -= (S16_t) b[i] * (S16_t) -c[i];
+}
+
+void
+test_addS16_tS8_t16_neg2 (pS16_t a, pS8_t b, pS8_t c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ a[i] -= (S16_t) -b[i] * (S16_t) c[i];
+}
+
+/* { dg-final { scan-assembler-times "smlal\tv\[0-9\]+\.8h" 4 } } */
+/* { dg-final { scan-assembler-times "smlal2\tv\[0-9\]+\.8h" 4 } } */
+
+void
+test_subS64_tS32_t4 (pS64_t a, pS32_t b, pS32_t c)
+{
+ int i;
+ for (i = 0; i < 4; i++)
+ a[i] -= (S64_t) b[i] * (S64_t) c[i];
+}
+
+/* { dg-final { scan-assembler "smlsl\tv\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "smlsl2\tv\[0-9\]+\.2d" } } */
+
+void
+test_subS32_tS16_t8 (pS32_t a, pS16_t b, pS16_t c)
+{
+ int i;
+ for (i = 0; i < 8; i++)
+ a[i] -= (S32_t) b[i] * (S32_t) c[i];
+}
+
+/* { dg-final { scan-assembler "smlsl\tv\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "smlsl2\tv\[0-9\]+\.4s" } } */
+
+void
+test_subS16_tS8_t16 (pS16_t a, pS8_t b, pS8_t c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ a[i] -= (S16_t) b[i] * (S16_t) c[i];
+}
+
+void
+test_subS16_tS8_t16_neg0 (pS16_t a, pS8_t b, pS8_t c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ a[i] += (S16_t) -b[i] * (S16_t) c[i];
+}
+
+void
+test_subS16_tS8_t16_neg1 (pS16_t a, pS8_t b, pS8_t c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ a[i] += (S16_t) b[i] * (S16_t) -c[i];
+}
+
+void
+test_subS16_tS8_t16_neg2 (pS16_t a, pS8_t b, pS8_t c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ a[i] += -((S16_t) b[i] * (S16_t) c[i]);
+}
+
+void
+test_subS16_tS8_t16_neg3 (pS16_t a, pS8_t b, pS8_t c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ a[i] -= (S16_t) -b[i] * (S16_t) -c[i];
+}
+
+/* { dg-final { scan-assembler-times "smlsl\tv\[0-9\]+\.8h" 5 } } */
+/* { dg-final { scan-assembler-times "smlsl2\tv\[0-9\]+\.8h" 5 } } */
+
+void
+test_addU64_tU32_t4 (pU64_t a, pU32_t b, pU32_t c)
+{
+ int i;
+ for (i = 0; i < 4; i++)
+ a[i] += (U64_t) b[i] * (U64_t) c[i];
+}
+
+/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.2d" } } */
+
+void
+test_addU32_tU16_t8 (pU32_t a, pU16_t b, pU16_t c)
+{
+ int i;
+ for (i = 0; i < 8; i++)
+ a[i] += (U32_t) b[i] * (U32_t) c[i];
+}
+
+/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.4s" } } */
+
+void
+test_addU16_tU8_t16 (pU16_t a, pU8_t b, pU8_t c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ a[i] += (U16_t) b[i] * (U16_t) c[i];
+}
+
+/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.8h" } } */
+/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.8h" } } */
+
+void
+test_subU64_tU32_t4 (pU64_t a, pU32_t b, pU32_t c)
+{
+ int i;
+ for (i = 0; i < 4; i++)
+ a[i] -= (U64_t) b[i] * (U64_t) c[i];
+}
+
+/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.2d" } } */
+
+void
+test_subU32_tU16_t8 (pU32_t a, pU16_t b, pU16_t c)
+{
+ int i;
+ for (i = 0; i < 8; i++)
+ a[i] -= (U32_t) b[i] * (U32_t) c[i];
+}
+
+/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.4s" } } */
+
+void
+test_subU16_tU8_t16 (pU16_t a, pU8_t b, pU8_t c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ a[i] -= (U16_t) b[i] * (U16_t) c[i];
+}
+
+/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.8h" } } */
+/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.8h" } } */
+
+
+S64_t add_rS64[4] = { 6, 7, -4, -3 };
+S32_t add_rS32[8] = { 6, 7, -4, -3, 10, 11, 0, 1 };
+S16_t add_rS16[16] =
+ { 6, 7, -4, -3, 10, 11, 0, 1, 14, 15, 4, 5, 18, 19, 8, 9 };
+
+S64_t sub_rS64[4] = { 0, 1, 2, 3 };
+S32_t sub_rS32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+S16_t sub_rS16[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+
+U64_t add_rU64[4] = { 0x6, 0x7, 0x2fffffffc, 0x2fffffffd };
+
+U32_t add_rU32[8] =
+{
+ 0x6, 0x7, 0x2fffc, 0x2fffd,
+ 0xa, 0xb, 0x30000, 0x30001
+};
+
+U16_t add_rU16[16] =
+{
+ 0x6, 0x7, 0x2fc, 0x2fd, 0xa, 0xb, 0x300, 0x301,
+ 0xe, 0xf, 0x304, 0x305, 0x12, 0x13, 0x308, 0x309
+};
+
+U64_t sub_rU64[4] = { 0, 1, 2, 3 };
+U32_t sub_rU32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+U16_t sub_rU16[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+
+S8_t neg_r[16] = { -6, -5, 8, 9, -2, -1, 12, 13, 2, 3, 16, 17, 6, 7, 20, 21 };
+
+S64_t S64_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+S32_t S32_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 };
+S32_t S32_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 };
+
+S32_t S32_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+S16_t S16_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 };
+S16_t S16_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 };
+
+S16_t S16_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+S8_t S8_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 };
+S8_t S8_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 };
+
+
+#define CHECK(T,N,AS,US) \
+do \
+ { \
+ for (i = 0; i < N; i++) \
+ if (S##T##_ta[i] != AS##_r##US##T[i]) \
+ abort (); \
+ } \
+while (0)
+
+#define SCHECK(T,N,AS) CHECK(T,N,AS,S)
+#define UCHECK(T,N,AS) CHECK(T,N,AS,U)
+
+#define NCHECK(RES) \
+do \
+ { \
+ for (i = 0; i < 16; i++) \
+ if (S16_ta[i] != RES[i]) \
+ abort (); \
+ } \
+while (0)
+
+
+int
+main ()
+{
+ int i;
+
+ test_addS64_tS32_t4 (S64_ta, S32_tb, S32_tc);
+ SCHECK (64, 4, add);
+ test_addS32_tS16_t8 (S32_ta, S16_tb, S16_tc);
+ SCHECK (32, 8, add);
+ test_addS16_tS8_t16 (S16_ta, S8_tb, S8_tc);
+ SCHECK (16, 16, add);
+ test_subS64_tS32_t4 (S64_ta, S32_tb, S32_tc);
+ SCHECK (64, 4, sub);
+ test_subS32_tS16_t8 (S32_ta, S16_tb, S16_tc);
+ SCHECK (32, 8, sub);
+ test_subS16_tS8_t16 (S16_ta, S8_tb, S8_tc);
+ SCHECK (16, 16, sub);
+
+ test_addU64_tU32_t4 (S64_ta, S32_tb, S32_tc);
+ UCHECK (64, 4, add);
+ test_addU32_tU16_t8 (S32_ta, S16_tb, S16_tc);
+ UCHECK (32, 8, add);
+ test_addU16_tU8_t16 (S16_ta, S8_tb, S8_tc);
+ UCHECK (16, 16, add);
+ test_subU64_tU32_t4 (S64_ta, S32_tb, S32_tc);
+ UCHECK (64, 4, sub);
+ test_subU32_tU16_t8 (S32_ta, S16_tb, S16_tc);
+ UCHECK (32, 8, sub);
+ test_subU16_tU8_t16 (S16_ta, S8_tb, S8_tc);
+ UCHECK (16, 16, sub);
+
+ test_addS16_tS8_t16_neg0 (S16_ta, S8_tb, S8_tc);
+ NCHECK (add_rS16);
+ test_subS16_tS8_t16_neg0 (S16_ta, S8_tb, S8_tc);
+ NCHECK (sub_rS16);
+ test_addS16_tS8_t16_neg1 (S16_ta, S8_tb, S8_tc);
+ NCHECK (add_rS16);
+ test_subS16_tS8_t16_neg1 (S16_ta, S8_tb, S8_tc);
+ NCHECK (sub_rS16);
+ test_addS16_tS8_t16_neg2 (S16_ta, S8_tb, S8_tc);
+ NCHECK (add_rS16);
+ test_subS16_tS8_t16_neg2 (S16_ta, S8_tb, S8_tc);
+ NCHECK (sub_rS16);
+ test_subS16_tS8_t16_neg3 (S16_ta, S8_tb, S8_tc);
+ NCHECK (neg_r);
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c
new file mode 100644
index 0000000..affb8a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c
@@ -0,0 +1,803 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "../../../config/aarch64/arm_neon.h"
+
+
+/* { dg-final { scan-assembler-times "\\tfmax\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */
+
+float32x2_t
+test_vmax_f32 (float32x2_t __a, float32x2_t __b)
+{
+ return vmax_f32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.8b, v\[0-9\].8b, v\[0-9\].8b" 1 } } */
+
+int8x8_t
+test_vmax_s8 (int8x8_t __a, int8x8_t __b)
+{
+ return vmax_s8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.8b, v\[0-9\].8b, v\[0-9\].8b" 1 } } */
+
+uint8x8_t
+test_vmax_u8 (uint8x8_t __a, uint8x8_t __b)
+{
+ return vmax_u8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.4h, v\[0-9\].4h, v\[0-9\].4h" 1 } } */
+
+int16x4_t
+test_vmax_s16 (int16x4_t __a, int16x4_t __b)
+{
+ return vmax_s16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.4h, v\[0-9\].4h, v\[0-9\].4h" 1 } } */
+
+uint16x4_t
+test_vmax_u16 (uint16x4_t __a, uint16x4_t __b)
+{
+ return vmax_u16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */
+
+int32x2_t
+test_vmax_s32 (int32x2_t __a, int32x2_t __b)
+{
+ return vmax_s32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */
+
+uint32x2_t
+test_vmax_u32 (uint32x2_t __a, uint32x2_t __b)
+{
+ return vmax_u32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tfmax\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */
+
+float32x4_t
+test_vmaxq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return vmaxq_f32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tfmax\\tv\[0-9\]+\.2d, v\[0-9\].2d, v\[0-9\].2d" 1 } } */
+
+float64x2_t
+test_vmaxq_f64 (float64x2_t __a, float64x2_t __b)
+{
+ return vmaxq_f64(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.16b, v\[0-9\].16b, v\[0-9\].16b" 1 } } */
+
+int8x16_t
+test_vmaxq_s8 (int8x16_t __a, int8x16_t __b)
+{
+ return vmaxq_s8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.16b, v\[0-9\].16b, v\[0-9\].16b" 1 } } */
+
+uint8x16_t
+test_vmaxq_u8 (uint8x16_t __a, uint8x16_t __b)
+{
+ return vmaxq_u8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.8h, v\[0-9\].8h, v\[0-9\].8h" 1 } } */
+
+int16x8_t
+test_vmaxq_s16 (int16x8_t __a, int16x8_t __b)
+{
+ return vmaxq_s16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.8h, v\[0-9\].8h, v\[0-9\].8h" 1 } } */
+
+uint16x8_t
+test_vmaxq_u16 (uint16x8_t __a, uint16x8_t __b)
+{
+ return vmaxq_u16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */
+
+int32x4_t
+test_vmaxq_s32 (int32x4_t __a, int32x4_t __b)
+{
+ return vmaxq_s32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */
+
+uint32x4_t
+test_vmaxq_u32 (uint32x4_t __a, uint32x4_t __b)
+{
+ return vmaxq_u32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tfmin\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */
+
+float32x2_t
+test_vmin_f32 (float32x2_t __a, float32x2_t __b)
+{
+ return vmin_f32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.8b, v\[0-9\].8b, v\[0-9\].8b" 1 } } */
+
+int8x8_t
+test_vmin_s8 (int8x8_t __a, int8x8_t __b)
+{
+ return vmin_s8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.8b, v\[0-9\].8b, v\[0-9\].8b" 1 } } */
+
+uint8x8_t
+test_vmin_u8 (uint8x8_t __a, uint8x8_t __b)
+{
+ return vmin_u8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.4h, v\[0-9\].4h, v\[0-9\].4h" 1 } } */
+
+int16x4_t
+test_vmin_s16 (int16x4_t __a, int16x4_t __b)
+{
+ return vmin_s16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.4h, v\[0-9\].4h, v\[0-9\].4h" 1 } } */
+
+uint16x4_t
+test_vmin_u16 (uint16x4_t __a, uint16x4_t __b)
+{
+ return vmin_u16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */
+
+int32x2_t
+test_vmin_s32 (int32x2_t __a, int32x2_t __b)
+{
+ return vmin_s32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */
+
+uint32x2_t
+test_vmin_u32 (uint32x2_t __a, uint32x2_t __b)
+{
+ return vmin_u32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tfmin\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */
+
+float32x4_t
+test_vminq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return vminq_f32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tfmin\\tv\[0-9\]+\.2d, v\[0-9\].2d, v\[0-9\].2d" 1 } } */
+
+float64x2_t
+test_vminq_f64 (float64x2_t __a, float64x2_t __b)
+{
+ return vminq_f64(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.16b, v\[0-9\].16b, v\[0-9\].16b" 1 } } */
+
+int8x16_t
+test_vminq_s8 (int8x16_t __a, int8x16_t __b)
+{
+ return vminq_s8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.16b, v\[0-9\].16b, v\[0-9\].16b" 1 } } */
+
+uint8x16_t
+test_vminq_u8 (uint8x16_t __a, uint8x16_t __b)
+{
+ return vminq_u8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.8h, v\[0-9\].8h, v\[0-9\].8h" 1 } } */
+
+int16x8_t
+test_vminq_s16 (int16x8_t __a, int16x8_t __b)
+{
+ return vminq_s16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.8h, v\[0-9\].8h, v\[0-9\].8h" 1 } } */
+
+uint16x8_t
+test_vminq_u16 (uint16x8_t __a, uint16x8_t __b)
+{
+ return vminq_u16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */
+
+int32x4_t
+test_vminq_s32 (int32x4_t __a, int32x4_t __b)
+{
+ return vminq_s32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */
+
+uint32x4_t
+test_vminq_u32 (uint32x4_t __a, uint32x4_t __b)
+{
+ return vminq_u32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\taddp\\tv\[0-9\]+\.8b, v\[0-9\].8b, v\[0-9\].8b" 2 } } */
+
+int8x8_t
+test_vpadd_s8 (int8x8_t __a, int8x8_t __b)
+{
+ return vpadd_s8(__a, __b);
+}
+
+uint8x8_t
+test_vpadd_u8 (uint8x8_t __a, uint8x8_t __b)
+{
+ return vpadd_u8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\taddp\\tv\[0-9\]+\.4h, v\[0-9\].4h, v\[0-9\].4h" 2 } } */
+
+int16x4_t
+test_vpadd_s16 (int16x4_t __a, int16x4_t __b)
+{
+ return vpadd_s16(__a, __b);
+}
+
+uint16x4_t
+test_vpadd_u16 (uint16x4_t __a, uint16x4_t __b)
+{
+ return vpadd_u16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\taddp\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 2 } } */
+
+int32x2_t
+test_vpadd_s32 (int32x2_t __a, int32x2_t __b)
+{
+ return vpadd_s32(__a, __b);
+}
+
+uint32x2_t
+test_vpadd_u32 (uint32x2_t __a, uint32x2_t __b)
+{
+ return vpadd_u32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 1 } } */
+
+int32x4_t
+test_vqdmlal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+{
+ return vqdmlal_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+
+int32x4_t
+test_vqdmlal_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
+{
+ return vqdmlal_high_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.h" 3 } } */
+
+int32x4_t
+test_vqdmlal_high_lane_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+{
+ return vqdmlal_high_lane_s16 (a, b, c, 3);
+}
+
+int32x4_t
+test_vqdmlal_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+{
+ return vqdmlal_high_laneq_s16 (a, b, c, 6);
+}
+
+int32x4_t
+test_vqdmlal_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c)
+{
+ return vqdmlal_high_n_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.h" 3 } } */
+
+int32x4_t
+test_vqdmlal_lane_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
+{
+ return vqdmlal_lane_s16 (a, b, c, 3);
+}
+
+int32x4_t
+test_vqdmlal_laneq_s16 (int32x4_t a, int16x4_t b, int16x8_t c)
+{
+ return vqdmlal_laneq_s16 (a, b, c, 6);
+}
+
+int32x4_t
+test_vqdmlal_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+{
+ return vqdmlal_n_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */
+
+int64x2_t
+test_vqdmlal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+{
+ return vqdmlal_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+
+int64x2_t
+test_vqdmlal_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+{
+ return vqdmlal_high_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.s" 3 } } */
+
+int64x2_t
+test_vqdmlal_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+{
+ return vqdmlal_high_lane_s32 (__a, __b, __c, 1);
+}
+
+int64x2_t
+test_vqdmlal_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+{
+ return vqdmlal_high_laneq_s32 (__a, __b, __c, 3);
+}
+
+int64x2_t
+test_vqdmlal_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c)
+{
+ return vqdmlal_high_n_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.s" 3 } } */
+
+int64x2_t
+test_vqdmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+{
+ return vqdmlal_lane_s32 (__a, __b, __c, 1);
+}
+
+int64x2_t
+test_vqdmlal_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c)
+{
+ return vqdmlal_laneq_s32 (__a, __b, __c, 3);
+}
+
+int64x2_t
+test_vqdmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+{
+ return vqdmlal_n_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 1 } } */
+
+int32x4_t
+test_vqdmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+{
+ return vqdmlsl_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+
+int32x4_t
+test_vqdmlsl_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
+{
+ return vqdmlsl_high_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.h" 3 } } */
+
+int32x4_t
+test_vqdmlsl_high_lane_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+{
+ return vqdmlsl_high_lane_s16 (a, b, c, 3);
+}
+
+int32x4_t
+test_vqdmlsl_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+{
+ return vqdmlsl_high_laneq_s16 (a, b, c, 6);
+}
+
+int32x4_t
+test_vqdmlsl_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c)
+{
+ return vqdmlsl_high_n_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.h" 3 } } */
+
+int32x4_t
+test_vqdmlsl_lane_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
+{
+ return vqdmlsl_lane_s16 (a, b, c, 3);
+}
+
+int32x4_t
+test_vqdmlsl_laneq_s16 (int32x4_t a, int16x4_t b, int16x8_t c)
+{
+ return vqdmlsl_laneq_s16 (a, b, c, 6);
+}
+
+int32x4_t
+test_vqdmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+{
+ return vqdmlsl_n_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */
+
+int64x2_t
+test_vqdmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+{
+ return vqdmlsl_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+
+int64x2_t
+test_vqdmlsl_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+{
+ return vqdmlsl_high_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.s" 3 } } */
+
+int64x2_t
+test_vqdmlsl_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+{
+ return vqdmlsl_high_lane_s32 (__a, __b, __c, 1);
+}
+
+int64x2_t
+test_vqdmlsl_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+{
+ return vqdmlsl_high_laneq_s32 (__a, __b, __c, 3);
+}
+
+int64x2_t
+test_vqdmlsl_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c)
+{
+ return vqdmlsl_high_n_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.s" 3 } } */
+
+int64x2_t
+test_vqdmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+{
+ return vqdmlsl_lane_s32 (__a, __b, __c, 1);
+}
+
+int64x2_t
+test_vqdmlsl_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c)
+{
+ return vqdmlsl_laneq_s32 (__a, __b, __c, 3);
+}
+
+int64x2_t
+test_vqdmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+{
+ return vqdmlsl_n_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 1 } } */
+
+int32x4_t
+test_vqdmull_s16 (int16x4_t __a, int16x4_t __b)
+{
+ return vqdmull_s16 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+
+int32x4_t
+test_vqdmull_high_s16 (int16x8_t __a, int16x8_t __b)
+{
+ return vqdmull_high_s16 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.h" 3 } } */
+
+int32x4_t
+test_vqdmull_high_lane_s16 (int16x8_t a, int16x8_t b)
+{
+ return vqdmull_high_lane_s16 (a, b, 3);
+}
+
+int32x4_t
+test_vqdmull_high_laneq_s16 (int16x8_t a, int16x8_t b)
+{
+ return vqdmull_high_laneq_s16 (a, b, 6);
+}
+
+int32x4_t
+test_vqdmull_high_n_s16 (int16x8_t __a, int16_t __b)
+{
+ return vqdmull_high_n_s16 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.h" 3 } } */
+
+int32x4_t
+test_vqdmull_lane_s16 (int16x4_t a, int16x4_t b)
+{
+ return vqdmull_lane_s16 (a, b, 3);
+}
+
+int32x4_t
+test_vqdmull_laneq_s16 (int16x4_t a, int16x8_t b)
+{
+ return vqdmull_laneq_s16 (a, b, 6);
+}
+
+int32x4_t
+test_vqdmull_n_s16 (int16x4_t __a, int16_t __b)
+{
+ return vqdmull_n_s16 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */
+
+int64x2_t
+test_vqdmull_s32 (int32x2_t __a, int32x2_t __b)
+{
+ return vqdmull_s32 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+
+int64x2_t
+test_vqdmull_high_s32 (int32x4_t __a, int32x4_t __b)
+{
+ return vqdmull_high_s32 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.s" 3 } } */
+
+int64x2_t
+test_vqdmull_high_lane_s32 (int32x4_t __a, int32x4_t __b)
+{
+ return vqdmull_high_lane_s32 (__a, __b, 1);
+}
+
+int64x2_t
+test_vqdmull_high_laneq_s32 (int32x4_t __a, int32x4_t __b)
+{
+ return vqdmull_high_laneq_s32 (__a, __b, 3);
+}
+
+int64x2_t
+test_vqdmull_high_n_s32 (int32x4_t __a, int32_t __b)
+{
+ return vqdmull_high_n_s32 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.s" 3 } } */
+
+int64x2_t
+test_vqdmull_lane_s32 (int32x2_t __a, int32x2_t __b)
+{
+ return vqdmull_lane_s32 (__a, __b, 1);
+}
+
+int64x2_t
+test_vqdmull_laneq_s32 (int32x2_t __a, int32x4_t __b)
+{
+ return vqdmull_laneq_s32 (__a, __b, 1);
+}
+
+int64x2_t
+test_vqdmull_n_s32 (int32x2_t __a, int32_t __b)
+{
+ return vqdmull_n_s32 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshll\\tv\[0-9\]+\.2d" 1 } } */
+
+int64x2_t
+test_vshll_n_s32 (int32x2_t __a)
+{
+ return vshll_n_s32 (__a, 9);
+}
+
+/* { dg-final { scan-assembler-times "\\tushll\\tv\[0-9\]+\.2d" 1 } } */
+
+uint64x2_t
+test_vshll_n_u32 (uint32x2_t __a)
+{
+ return vshll_n_u32 (__a, 9);
+}
+
+/* { dg-final { scan-assembler-times "\\tshll\\tv\[0-9\]+\.2d" 2 } } */
+
+int64x2_t
+test_vshll_n_s32_2 (int32x2_t __a)
+{
+ return vshll_n_s32 (__a, 32);
+}
+
+uint64x2_t
+test_vshll_n_u32_2 (uint32x2_t __a)
+{
+ return vshll_n_u32 (__a, 32);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshll\\tv\[0-9\]+\.4s" 1 } } */
+
+int32x4_t
+test_vshll_n_s16 (int16x4_t __a)
+{
+ return vshll_n_s16 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tushll\\tv\[0-9\]+\.4s" 1 } } */
+
+uint32x4_t
+test_vshll_n_u16 (uint16x4_t __a)
+{
+ return vshll_n_u16 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tshll\\tv\[0-9\]+\.4s" 2 } } */
+
+int32x4_t
+test_vshll_n_s16_2 (int16x4_t __a)
+{
+ return vshll_n_s16 (__a, 16);
+}
+
+uint32x4_t
+test_vshll_n_u16_2 (uint16x4_t __a)
+{
+ return vshll_n_u16 (__a, 16);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshll\\tv\[0-9\]+\.8h" 1 } } */
+
+int16x8_t
+test_vshll_n_s8 (int8x8_t __a)
+{
+ return vshll_n_s8 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tushll\\tv\[0-9\]+\.8h" 1 } } */
+
+uint16x8_t
+test_vshll_n_u8 (uint8x8_t __a)
+{
+ return vshll_n_u8 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tshll\\tv\[0-9\]+\.8h" 2 } } */
+
+int16x8_t
+test_vshll_n_s8_2 (int8x8_t __a)
+{
+ return vshll_n_s8 (__a, 8);
+}
+
+uint16x8_t
+test_vshll_n_u8_2 (uint8x8_t __a)
+{
+ return vshll_n_u8 (__a, 8);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshll2\\tv\[0-9\]+\.2d" 1 } } */
+
+int64x2_t
+test_vshll_high_n_s32 (int32x4_t __a)
+{
+ return vshll_high_n_s32 (__a, 9);
+}
+
+/* { dg-final { scan-assembler-times "\\tushll2\\tv\[0-9\]+\.2d" 1 } } */
+
+uint64x2_t
+test_vshll_high_n_u32 (uint32x4_t __a)
+{
+ return vshll_high_n_u32 (__a, 9);
+}
+
+/* { dg-final { scan-assembler-times "\\tshll2\\tv\[0-9\]+\.2d" 2 } } */
+
+int64x2_t
+test_vshll_high_n_s32_2 (int32x4_t __a)
+{
+ return vshll_high_n_s32 (__a, 32);
+}
+
+uint64x2_t
+test_vshll_high_n_u32_2 (uint32x4_t __a)
+{
+ return vshll_high_n_u32 (__a, 32);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshll2\\tv\[0-9\]+\.4s" 1 } } */
+
+int32x4_t
+test_vshll_high_n_s16 (int16x8_t __a)
+{
+ return vshll_high_n_s16 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tushll2\\tv\[0-9\]+\.4s" 1 } } */
+
+uint32x4_t
+test_vshll_high_n_u16 (uint16x8_t __a)
+{
+ return vshll_high_n_u16 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tshll2\\tv\[0-9\]+\.4s" 2 } } */
+
+int32x4_t
+test_vshll_high_n_s16_2 (int16x8_t __a)
+{
+ return vshll_high_n_s16 (__a, 16);
+}
+
+uint32x4_t
+test_vshll_high_n_u16_2 (uint16x8_t __a)
+{
+ return vshll_high_n_u16 (__a, 16);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshll2\\tv\[0-9\]+\.8h" 1 } } */
+
+int16x8_t
+test_vshll_high_n_s8 (int8x16_t __a)
+{
+ return vshll_high_n_s8 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tushll2\\tv\[0-9\]+\.8h" 1 } } */
+
+uint16x8_t
+test_vshll_high_n_u8 (uint8x16_t __a)
+{
+ return vshll_high_n_u8 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tshll2\\tv\[0-9\]+\.8h" 2 } } */
+
+int16x8_t
+test_vshll_high_n_s8_2 (int8x16_t __a)
+{
+ return vshll_high_n_s8 (__a, 8);
+}
+
+uint16x8_t
+test_vshll_high_n_u8_2 (uint8x16_t __a)
+{
+ return vshll_high_n_u8 (__a, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vfp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vfp-1.c
new file mode 100644
index 0000000..79c5714
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vfp-1.c
@@ -0,0 +1,109 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+extern float fabsf (float);
+extern float sqrtf (float);
+extern double fabs (double);
+extern double sqrt (double);
+
+volatile float f1, f2, f3;
+volatile int cond1, cond2;
+
+void test_sf() {
+ /* abssf2 */
+ /* { dg-final { scan-assembler "fabs\ts\[0-9\]*" } } */
+ f1 = fabsf (f1);
+ /* negsf2 */
+ /* { dg-final { scan-assembler "fneg\ts\[0-9\]*" } } */
+ f1 = -f1;
+ /* addsf3 */
+ /* { dg-final { scan-assembler "fadd\ts\[0-9\]*" } } */
+ f1 = f2 + f3;
+ /* subsf3 */
+ /* { dg-final { scan-assembler "fsub\ts\[0-9\]*" } } */
+ f1 = f2 - f3;
+ /* divsf3 */
+ /* { dg-final { scan-assembler "fdiv\ts\[0-9\]*" } } */
+ f1 = f2 / f3;
+ /* mulsf3 */
+ /* { dg-final { scan-assembler "fmul\ts\[0-9\]*" } } */
+ f1 = f2 * f3;
+ /* sqrtsf2 */
+ /* { dg-final { scan-assembler "fsqrt\ts\[0-9\]*" } } */
+ f1 = sqrtf (f1);
+ /* cmpsf */
+ /* { dg-final { scan-assembler "fcmp\ts\[0-9\]*" } } */
+ if (f1 < f2)
+ cond1 = 1;
+ else
+ cond2 = 1;
+}
+
+volatile double d1, d2, d3;
+
+void test_df() {
+ /* absdf2 */
+ /* { dg-final { scan-assembler "fabs\td\[0-9\]*" } } */
+ d1 = fabs (d1);
+ /* negdf2 */
+ /* { dg-final { scan-assembler "fneg\td\[0-9\]*" } } */
+ d1 = -d1;
+ /* adddf3 */
+ /* { dg-final { scan-assembler "fadd\td\[0-9\]*" } } */
+ d1 = d2 + d3;
+ /* subdf3 */
+ /* { dg-final { scan-assembler "fsub\td\[0-9\]*" } } */
+ d1 = d2 - d3;
+ /* divdf3 */
+ /* { dg-final { scan-assembler "fdiv\td\[0-9\]*" } } */
+ d1 = d2 / d3;
+ /* muldf3 */
+ /* { dg-final { scan-assembler "fmul\td\[0-9\]*" } } */
+ d1 = d2 * d3;
+ /* sqrtdf2 */
+ /* { dg-final { scan-assembler "fsqrt\td\[0-9\]*" } } */
+ d1 = sqrt (d1);
+ /* cmpdf */
+ /* { dg-final { scan-assembler "fcmp\td\[0-9\]*" } } */
+ if (d1 < d2)
+ cond1 = 1;
+ else
+ cond2 = 1;
+}
+
+volatile int i1;
+volatile unsigned int u1;
+
+void test_convert () {
+ /* extendsfdf2 */
+ /* { dg-final { scan-assembler "fcvt\td\[0-9\]*" } } */
+ d1 = f1;
+ /* truncdfsf2 */
+ /* { dg-final { scan-assembler "fcvt\ts\[0-9\]*" } } */
+ f1 = d1;
+ /* fixsfsi2 */
+ /* { dg-final { scan-assembler "fcvtzs\tw\[0-9\], s\[0-9\]*" } } */
+ i1 = f1;
+ /* fixdfsi2 */
+ /* { dg-final { scan-assembler "fcvtzs\tw\[0-9\], d\[0-9\]*" } } */
+ i1 = d1;
+ /* fixunsfsi2 */
+ /* { dg-final { scan-assembler "fcvtzu\tw\[0-9\], s\[0-9\]*" } } */
+ u1 = f1;
+ /* fixunsdfsi2 */
+ /* { dg-final { scan-assembler "fcvtzu\tw\[0-9\], d\[0-9\]*" } } */
+ u1 = d1;
+ /* floatsisf2 */
+ /* { dg-final { scan-assembler "scvtf\ts\[0-9\]*" } } */
+ f1 = i1;
+ /* floatsidf2 */
+ /* { dg-final { scan-assembler "scvtf\td\[0-9\]*" } } */
+ d1 = i1;
+ /* floatunssisf2 */
+ /* { dg-final { scan-assembler "ucvtf\ts\[0-9\]*" } } */
+ f1 = u1;
+ /* floatunssidf2 */
+ /* { dg-final { scan-assembler "ucvtf\td\[0-9\]*" } } */
+ d1 = u1;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vld1-vst1_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vld1-vst1_1.c
new file mode 100644
index 0000000..d1834a2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vld1-vst1_1.c
@@ -0,0 +1,52 @@
+/* Test vld1 and vst1 maintain consistent indexing. */
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+#include <arm_neon.h>
+
+extern void abort (void);
+
+int __attribute__ ((noinline))
+test_vld1_vst1 ()
+{
+ int8x8_t a;
+ int8x8_t b;
+ int i = 0;
+ int8_t c[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+ int8_t d[8];
+ a = vld1_s8 (c);
+ asm volatile ("":::"memory");
+ vst1_s8 (d, a);
+ asm volatile ("":::"memory");
+ for (; i < 8; i++)
+ if (c[i] != d[i])
+ return 1;
+ return 0;
+}
+
+int __attribute__ ((noinline))
+test_vld1q_vst1q ()
+{
+ int16x8_t a;
+ int16x8_t b;
+ int i = 0;
+ int16_t c[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+ int16_t d[8];
+ a = vld1q_s16 (c);
+ asm volatile ("":::"memory");
+ vst1q_s16 (d, a);
+ asm volatile ("":::"memory");
+ for (; i < 8; i++)
+ if (c[i] != d[i])
+ return 1;
+ return 0;
+}
+
+int
+main ()
+{
+ if (test_vld1_vst1 ())
+ abort ();
+ if (test_vld1q_vst1q ())
+ abort ();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vmlsq_laneq.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vmlsq_laneq.c
new file mode 100644
index 0000000..dd3fb81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vmlsq_laneq.c
@@ -0,0 +1,158 @@
+
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#include "arm_neon.h"
+
+extern void abort (void);
+
+void
+test1 ()
+{
+ int16x8_t val1, val2, val3;
+ int16x8_t result;
+ uint64_t act, exp;
+
+ val1 = vcombine_s16 (vcreate_s16 (UINT64_C (0xffff9ab680000000)),
+ vcreate_s16 (UINT64_C (0x00000000ffff0000)));
+ val2 = vcombine_s16 (vcreate_s16 (UINT64_C (0x32b77fffffff7fff)),
+ vcreate_s16 (UINT64_C (0x0000ffff00007fff)));
+ val3 = vcombine_s16 (v