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authorBen Cheng <bccheng@google.com>2014-03-25 22:37:19 -0700
committerBen Cheng <bccheng@google.com>2014-03-25 22:37:19 -0700
commit1bc5aee63eb72b341f506ad058502cd0361f0d10 (patch)
treec607e8252f3405424ff15bc2d00aa38dadbb2518 /gcc-4.9/gcc/testsuite/gcc.dg/pr33619.c
parent283a0bf58fcf333c58a2a92c3ebbc41fb9eb1fdb (diff)
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Initial checkin of GCC 4.9.0 from trunk (r208799).
Change-Id: I48a3c08bb98542aa215912a75f03c0890e497dba
Diffstat (limited to 'gcc-4.9/gcc/testsuite/gcc.dg/pr33619.c')
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.dg/pr33619.c45
1 files changed, 45 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/testsuite/gcc.dg/pr33619.c b/gcc-4.9/gcc/testsuite/gcc.dg/pr33619.c
new file mode 100644
index 000000000..8011e69e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.dg/pr33619.c
@@ -0,0 +1,45 @@
+/* PR tree-optimization/33619 */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#ifdef __powerpc__
+# define REG1 __asm__ ("3")
+# define REG2 __asm__ ("4")
+#elif defined __x86_64__
+# define REG1 __asm__ ("rdi")
+# define REG2 __asm__ ("rsi")
+#else
+# define REG1
+# define REG2
+#endif
+
+static inline void
+bar (unsigned long x, int y)
+{
+ register unsigned long p1 REG1 = x;
+ register unsigned long p2 REG2 = y;
+ __asm__ volatile ("" : "=r" (p1), "=r" (p2) : "0" (p1), "1" (p2) : "memory");
+ if (p1 != 0xdeadUL || p2 != 0xbefUL)
+ __builtin_abort ();
+}
+
+__attribute__((const, noinline)) int
+baz (int x)
+{
+ return x;
+}
+
+__attribute__((noinline)) void
+foo (unsigned long *x, int y)
+{
+ unsigned long a = *x;
+ bar (a, baz (y));
+}
+
+int
+main (void)
+{
+ unsigned long a = 0xdeadUL;
+ foo (&a, 0xbefUL);
+ return 0;
+}