[4.9] Refresh GCC 4.9 to the 20140514 snapshot.

For critical bug fixes including devirtualization and codegen.

Change-Id: I8138d3dc408fc12db5eecb01d2753d39219712f2

4 files changed, 128 insertions, 7 deletions

diff --git a/gcc-4.9/gcc/doc/extend.texi b/gcc-4.9/gcc/doc/extend.texi
index 347a94a3a..9780d9238 100644
--- a/gcc-4.9/gcc/doc/extend.texi
+++ b/gcc-4.9/gcc/doc/extend.texi
@@ -12787,9 +12787,12 @@ float __builtin_recipdivf (float, float);
 float __builtin_rsqrtf (float);
 double __builtin_recipdiv (double, double);
 double __builtin_rsqrt (double);
-long __builtin_bpermd (long, long);
 uint64_t __builtin_ppc_get_timebase ();
 unsigned long __builtin_ppc_mftb ();
+double __builtin_unpack_longdouble (long double, int);
+double __builtin_longdouble_dw0 (long double);
+double __builtin_longdouble_dw1 (long double);
+long double __builtin_pack_longdouble (double, double);
 @end smallexample
 
 The @code{vec_rsqrt}, @code{__builtin_rsqrt}, and
@@ -12809,6 +12812,57 @@ The @code{__builtin_ppc_mftb} function always generates one instruction and
 returns the Time Base Register value as an unsigned long, throwing away
 the most significant word on 32-bit environments.
 
+The following built-in functions are available for the PowerPC family
+of processors, starting with ISA 2.06 or later (@option{-mcpu=power7}
+or @option{-mpopcntd}):
+@smallexample
+long __builtin_bpermd (long, long);
+int __builtin_divwe (int, int);
+int __builtin_divweo (int, int);
+unsigned int __builtin_divweu (unsigned int, unsigned int);
+unsigned int __builtin_divweuo (unsigned int, unsigned int);
+long __builtin_divde (long, long);
+long __builtin_divdeo (long, long);
+unsigned long __builtin_divdeu (unsigned long, unsigned long);
+unsigned long __builtin_divdeuo (unsigned long, unsigned long);
+unsigned int cdtbcd (unsigned int);
+unsigned int cbcdtd (unsigned int);
+unsigned int addg6s (unsigned int, unsigned int);
+@end smallexample
+
+The @code{__builtin_divde}, @code{__builtin_divdeo},
+@code{__builitin_divdeu}, @code{__builtin_divdeou} functions require a
+64-bit environment support ISA 2.06 or later.
+
+The following built-in functions are available for the PowerPC family
+of processors when hardware decimal floating point
+(@option{-mhard-dfp}) is available:
+@smallexample
+_Decimal64 __builtin_dxex (_Decimal64);
+_Decimal128 __builtin_dxexq (_Decimal128);
+_Decimal64 __builtin_ddedpd (int, _Decimal64);
+_Decimal128 __builtin_ddedpdq (int, _Decimal128);
+_Decimal64 __builtin_denbcd (int, _Decimal64);
+_Decimal128 __builtin_denbcdq (int, _Decimal128);
+_Decimal64 __builtin_diex (_Decimal64, _Decimal64);
+_Decimal128 _builtin_diexq (_Decimal128, _Decimal128);
+_Decimal64 __builtin_dscli (_Decimal64, int);
+_Decimal128 __builitn_dscliq (_Decimal128, int);
+_Decimal64 __builtin_dscri (_Decimal64, int);
+_Decimal128 __builitn_dscriq (_Decimal128, int);
+unsigned long long __builtin_unpack_dec128 (_Decimal128, int);
+_Decimal128 __builtin_pack_dec128 (unsigned long long, unsigned long long);
+@end smallexample
+
+The following built-in functions are available for the PowerPC family
+of processors when the Vector Scalar (vsx) instruction set is
+available:
+@smallexample
+unsigned long long __builtin_unpack_vector_int128 (vector __int128_t, int);
+vector __int128_t __builtin_pack_vector_int128 (unsigned long long,
+                                                unsigned long long);
+@end smallexample
+
 @node PowerPC AltiVec/VSX Built-in Functions
 @subsection PowerPC AltiVec Built-in Functions
 
@@ -15220,6 +15274,17 @@ vector __uint128_t vec_vsubcuq (vector __uint128_t, vector __uint128_t);
 
 __int128_t vec_vsubuqm (__int128_t, __int128_t);
 __uint128_t vec_vsubuqm (__uint128_t, __uint128_t);
+
+vector __int128_t __builtin_bcdadd (vector __int128_t, vector__int128_t);
+int __builtin_bcdadd_lt (vector __int128_t, vector__int128_t);
+int __builtin_bcdadd_eq (vector __int128_t, vector__int128_t);
+int __builtin_bcdadd_gt (vector __int128_t, vector__int128_t);
+int __builtin_bcdadd_ov (vector __int128_t, vector__int128_t);
+vector __int128_t bcdsub (vector __int128_t, vector__int128_t);
+int __builtin_bcdsub_lt (vector __int128_t, vector__int128_t);
+int __builtin_bcdsub_eq (vector __int128_t, vector__int128_t);
+int __builtin_bcdsub_gt (vector __int128_t, vector__int128_t);
+int __builtin_bcdsub_ov (vector __int128_t, vector__int128_t);
 @end smallexample
 
 If the cryptographic instructions are enabled (@option{-mcrypto} or
diff --git a/gcc-4.9/gcc/doc/install.texi b/gcc-4.9/gcc/doc/install.texi
index c32f1f90e..6b45e9d0d 100644
--- a/gcc-4.9/gcc/doc/install.texi
+++ b/gcc-4.9/gcc/doc/install.texi
@@ -2544,8 +2544,7 @@ Finally a @code{stagefeedback} compiler is built using the information collected
 
 Unlike standard bootstrap, several additional restrictions apply.  The
 compiler used to build @code{stage1} needs to support a 64-bit integral type.
-It is recommended to only use GCC for this.  Also parallel make is currently
-not supported since collisions in profile collecting may occur.
+It is recommended to only use GCC for this.
 
 @html
 <hr />
diff --git a/gcc-4.9/gcc/doc/invoke.texi b/gcc-4.9/gcc/doc/invoke.texi
index 8ecb44565..0324a8571 100644
--- a/gcc-4.9/gcc/doc/invoke.texi
+++ b/gcc-4.9/gcc/doc/invoke.texi
@@ -825,7 +825,8 @@ Objective-C and Objective-C++ Dialects}.
 @gccoptlist{-meb -mel -mno-crt0}
 
 @emph{MSP430 Options}
-@gccoptlist{-msim -masm-hex -mmcu= -mcpu= -mlarge -msmall -mrelax}
+@gccoptlist{-msim -masm-hex -mmcu= -mcpu= -mlarge -msmall -mrelax @gol
+-mhwmult=}
 
 @emph{NDS32 Options}
 @gccoptlist{-mbig-endian -mlittle-endian @gol
@@ -991,6 +992,7 @@ See RS/6000 and PowerPC Options.
 -mhard-quad-float  -msoft-quad-float @gol
 -mstack-bias  -mno-stack-bias @gol
 -munaligned-doubles  -mno-unaligned-doubles @gol
+-muser-mode  -mno-user-mode @gol
 -mv8plus  -mno-v8plus  -mvis  -mno-vis @gol
 -mvis2  -mno-vis2  -mvis3  -mno-vis3 @gol
 -mcbcond -mno-cbcond @gol
@@ -18218,6 +18220,28 @@ This option is passed to the assembler and linker, and allows the
 linker to perform certain optimizations that cannot be done until
 the final link.
 
+@item mhwmult=
+@opindex mhwmult=
+Describes the type of hardware multiply supported by the target.
+Accepted values are @code{none} for no hardware multiply, @code{16bit}
+for the original 16-bit-only multiply supported by early MCUs.
+@code{32bit} for the 16/32-bit multiply supported by later MCUs and
+@code{f5series} for the 16/32-bit multiply supported by F5-series MCUs.
+A value of @code{auto} can also be given.  This tells GCC to deduce
+the hardware multiply support based upon the MCU name provided by the
+@option{-mmcu} option.  If no @option{-mmcu} option is specified then
+@code{32bit} hardware multiply support is assumed.  @code{auto} is the
+default setting.
+
+Hardware multiplies are normally performed by calling a library
+routine.  This saves space in the generated code.  When compiling at
+@code{-O3} or higher however the hardware multiplier is invoked
+inline.  This makes for bigger, but faster code.
+
+The hardware multiply routines disable interrupts whilst running and
+restore the previous interrupt state when they finish.  This makes
+them safe to use inside interrupt handlers as well as in normal code.
+
 @end table
 
 @node NDS32 Options
@@ -20908,6 +20932,14 @@ Specifying this option avoids some rare compatibility problems with code
 generated by other compilers.  It is not the default because it results
 in a performance loss, especially for floating-point code.
 
+@item -muser-mode
+@itemx -mno-user-mode
+@opindex muser-mode
+@opindex mno-user-mode
+Do not generate code that can only run in supervisor mode.  This is relevant
+only for the @code{casa} instruction emitted for the LEON3 processor.  The
+default is @option{-mno-user-mode}.
+
 @item -mno-faster-structs
 @itemx -mfaster-structs
 @opindex mno-faster-structs
diff --git a/gcc-4.9/gcc/doc/sourcebuild.texi b/gcc-4.9/gcc/doc/sourcebuild.texi
index 914860813..7438980f0 100644
--- a/gcc-4.9/gcc/doc/sourcebuild.texi
+++ b/gcc-4.9/gcc/doc/sourcebuild.texi
@@ -1601,6 +1601,13 @@ MIPS target supports @code{-mpaired-single}.
 @subsubsection PowerPC-specific attributes
 
 @table @code
+
+@item dfp_hw
+PowerPC target supports executing hardware DFP instructions.
+
+@item p8vector_hw
+PowerPC target supports executing VSX instructions (ISA 2.07).
+
 @item powerpc64
 Test system supports executing 64-bit instructions.
 
@@ -1610,12 +1617,24 @@ PowerPC target supports AltiVec.
 @item powerpc_altivec_ok
 PowerPC target supports @code{-maltivec}.
 
+@item powerpc_eabi_ok
+PowerPC target supports @code{-meabi}.
+
+@item powerpc_elfv2
+PowerPC target supports @code{-mabi=elfv2}.
+
 @item powerpc_fprs
 PowerPC target supports floating-point registers.
 
 @item powerpc_hard_double
 PowerPC target supports hardware double-precision floating-point.
 
+@item powerpc_htm_ok
+PowerPC target supports @code{-mhtm}
+
+@item powerpc_p8vector_ok
+PowerPC target supports @code{-mpower8-vector}
+
 @item powerpc_ppu_ok
 PowerPC target supports @code{-mcpu=cell}.
 
@@ -1629,9 +1648,6 @@ PowerPC target supports PowerPC SPE.
 @item powerpc_spu
 PowerPC target supports PowerPC SPU.
 
-@item spu_auto_overlay
-SPU target has toolchain that supports automatic overlay generation.
-
 @item powerpc_vsx_ok
 PowerPC target supports @code{-mvsx}.
 
@@ -1639,8 +1655,17 @@ PowerPC target supports @code{-mvsx}.
 Including the options used to compile this particular test, the
 PowerPC target supports PowerPC 405.
 
+@item ppc_recip_hw
+PowerPC target supports executing reciprocal estimate instructions.
+
+@item spu_auto_overlay
+SPU target has toolchain that supports automatic overlay generation.
+
 @item vmx_hw
 PowerPC target supports executing AltiVec instructions.
+
+@item vsx_hw
+PowerPC target supports executing VSX instructions (ISA 2.06).
 @end table
 
 @subsubsection Other hardware attributes