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author | Steve Ellcey <Steve.Ellcey@imgtec.com> | 2015-03-19 15:09:08 -0700 |
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committer | Steve Ellcey <Steve.Ellcey@imgtec.com> | 2015-03-19 15:09:08 -0700 |
commit | 9f57376006c7afb1561fe3e7a8d8be64f3196acd (patch) | |
tree | 67be4e16ff59195e9a80737ebf6b262e2ab92911 /gcc-4.9/gcc/doc/invoke.texi | |
parent | 3951a3654b8197466bee3e6732b3bc94e4018f68 (diff) | |
download | toolchain_gcc-9f57376006c7afb1561fe3e7a8d8be64f3196acd.tar.gz toolchain_gcc-9f57376006c7afb1561fe3e7a8d8be64f3196acd.tar.bz2 toolchain_gcc-9f57376006c7afb1561fe3e7a8d8be64f3196acd.zip |
Update MSA Support in MIPS GCC.
Change-Id: Id87035be4552719dc05096bb98b49d4bed91a07a
Diffstat (limited to 'gcc-4.9/gcc/doc/invoke.texi')
-rw-r--r-- | gcc-4.9/gcc/doc/invoke.texi | 29 |
1 files changed, 23 insertions, 6 deletions
diff --git a/gcc-4.9/gcc/doc/invoke.texi b/gcc-4.9/gcc/doc/invoke.texi index ed64aae13..bee61f058 100644 --- a/gcc-4.9/gcc/doc/invoke.texi +++ b/gcc-4.9/gcc/doc/invoke.texi @@ -784,7 +784,7 @@ Objective-C and Objective-C++ Dialects}. -minterlink-mips16 -mno-interlink-mips16 @gol -mabi=@var{abi} -mabicalls -mno-abicalls @gol -mshared -mno-shared -mplt -mno-plt -mxgot -mno-xgot @gol --mgp32 -mgp64 -mfp32 -mfp64 -mhard-float -msoft-float @gol +-mgp32 -mgp64 -mfp32 -mfpxx -mfp64 -mhard-float -msoft-float @gol -mno-float -msingle-float -mdouble-float @gol -modd-spreg -mno-odd-spreg @gol -mabs=@var{mode} -mnan=@var{encoding} @gol @@ -17380,7 +17380,7 @@ The processor names are: @samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, -@samp{octeon}, @samp{octeon+}, @samp{octeon2}, +@samp{octeon}, @samp{octeon+}, @samp{octeon2}, @samp{octeon3}, @samp{orion}, @samp{p5600}, @samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400}, @@ -17564,7 +17564,20 @@ same, but each scalar value is passed in a single 64-bit register rather than a pair of 32-bit registers. For example, scalar floating-point values are returned in @samp{$f0} only, not a @samp{$f0}/@samp{$f1} pair. The set of call-saved registers also -remains the same, but all 64 bits are saved. +remains the same in that the even-numbered double-precision registers +are saved. + +Two additional variants of the o32 ABI are supported to enable +a transition from 32-bit to 64-bit registers. These are FPXX +(@option{-mfpxx}) and FP64A (@option{-mfp64} @option{-mno-odd-spreg}). +The FPXX extension mandates that all code must execute correctly +when run using 32-bit or 64-bit registers. The code can be interlinked +with either FP32 or FP64, but not both. +The FP64A extension is similar to the FP64 extension but forbids the +use of odd-numbered single-precision registers. This can be used +in conjunction with the @code{FRE} mode of FPUs in MIPS32R5 +processors and allows both FP32 and FP64A code to interlink and +run in the same process without changing FPU modes. @item -mabicalls @itemx -mno-abicalls @@ -17653,6 +17666,10 @@ Assume that floating-point registers are 32 bits wide. @opindex mfp64 Assume that floating-point registers are 64 bits wide. +@item -mfpxx +@opindex mfpxx +Do not assume the width of floating-point registers. + @item -mhard-float @opindex mhard-float Use floating-point coprocessor instructions. @@ -17689,9 +17706,9 @@ operations. This is the default. @opindex modd-spreg @opindex mno-odd-spreg Enable the use of odd-numbered single-precision floating-point registers -for the O32 ABI. This is the default for specific processors that are -known to support these registers. The O32 FPXX extension sets -@code{-mno-odd-spreg} by default when targetting generic architectures. +for the o32 ABI. This is the default for processors that are known to +support these registers. When using the o32 FPXX ABI, @code{-mno-odd-spreg} +is set by default. @item -mabs=2008 @itemx -mabs=legacy |