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authorRong Xu <xur@google.com>2014-09-05 20:22:13 -0700
committerRong Xu <xur@google.com>2014-09-05 20:22:13 -0700
commit142855c94b3bc9e140a1b55c1a424259285d751c (patch)
tree8b4f309643aab7f51e85b9cc66b05f209426c5d3 /gcc-4.9/gcc/config
parent4254ad78d813b8c4cfc6c07218aee6b1be554f23 (diff)
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[gcc-4.9] Backport fix for PR62040 and PR62262
Backport two patches from upstream gcc 4.9 branch that fix PR62040 and PR62262 Change-Id: If4f557a650e00261b9bc83e008eb63b13ca798cb
Diffstat (limited to 'gcc-4.9/gcc/config')
-rw-r--r--gcc-4.9/gcc/config/aarch64/aarch64-simd.md40
-rw-r--r--gcc-4.9/gcc/config/aarch64/aarch64.md3
-rw-r--r--gcc-4.9/gcc/config/aarch64/iterators.md6
3 files changed, 44 insertions, 5 deletions
diff --git a/gcc-4.9/gcc/config/aarch64/aarch64-simd.md b/gcc-4.9/gcc/config/aarch64/aarch64-simd.md
index 1f827b57d..851e77a02 100644
--- a/gcc-4.9/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc-4.9/gcc/config/aarch64/aarch64-simd.md
@@ -945,8 +945,8 @@
;; On big-endian this is { zeroes, operand }
(define_insn "move_lo_quad_internal_<mode>"
- [(set (match_operand:VQ 0 "register_operand" "=w,w,w")
- (vec_concat:VQ
+ [(set (match_operand:VQ_NO2E 0 "register_operand" "=w,w,w")
+ (vec_concat:VQ_NO2E
(match_operand:<VHALF> 1 "register_operand" "w,r,r")
(vec_duplicate:<VHALF> (const_int 0))))]
"TARGET_SIMD && !BYTES_BIG_ENDIAN"
@@ -960,9 +960,25 @@
(set_attr "length" "4")]
)
+(define_insn "move_lo_quad_internal_<mode>"
+ [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w")
+ (vec_concat:VQ_2E
+ (match_operand:<VHALF> 1 "register_operand" "w,r,r")
+ (const_int 0)))]
+ "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+ "@
+ dup\\t%d0, %1.d[0]
+ fmov\\t%d0, %1
+ dup\\t%d0, %1"
+ [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>")
+ (set_attr "simd" "yes,*,yes")
+ (set_attr "fp" "*,yes,*")
+ (set_attr "length" "4")]
+)
+
(define_insn "move_lo_quad_internal_be_<mode>"
- [(set (match_operand:VQ 0 "register_operand" "=w,w,w")
- (vec_concat:VQ
+ [(set (match_operand:VQ_NO2E 0 "register_operand" "=w,w,w")
+ (vec_concat:VQ_NO2E
(vec_duplicate:<VHALF> (const_int 0))
(match_operand:<VHALF> 1 "register_operand" "w,r,r")))]
"TARGET_SIMD && BYTES_BIG_ENDIAN"
@@ -976,6 +992,22 @@
(set_attr "length" "4")]
)
+(define_insn "move_lo_quad_internal_be_<mode>"
+ [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w")
+ (vec_concat:VQ_2E
+ (const_int 0)
+ (match_operand:<VHALF> 1 "register_operand" "w,r,r")))]
+ "TARGET_SIMD && BYTES_BIG_ENDIAN"
+ "@
+ dup\\t%d0, %1.d[0]
+ fmov\\t%d0, %1
+ dup\\t%d0, %1"
+ [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>")
+ (set_attr "simd" "yes,*,yes")
+ (set_attr "fp" "*,yes,*")
+ (set_attr "length" "4")]
+)
+
(define_expand "move_lo_quad_<mode>"
[(match_operand:VQ 0 "register_operand")
(match_operand:VQ 1 "register_operand")]
diff --git a/gcc-4.9/gcc/config/aarch64/aarch64.md b/gcc-4.9/gcc/config/aarch64/aarch64.md
index df81045e9..319f80591 100644
--- a/gcc-4.9/gcc/config/aarch64/aarch64.md
+++ b/gcc-4.9/gcc/config/aarch64/aarch64.md
@@ -3157,7 +3157,8 @@
(and:GPI (ashift:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand 2 "const_int_operand" "n"))
(match_operand 3 "const_int_operand" "n")))]
- "exact_log2 ((INTVAL (operands[3]) >> INTVAL (operands[2])) + 1) >= 0
+ "(INTVAL (operands[2]) < (<GPI:sizen>))
+ && exact_log2 ((INTVAL (operands[3]) >> INTVAL (operands[2])) + 1) >= 0
&& (INTVAL (operands[3]) & ((1 << INTVAL (operands[2])) - 1)) == 0"
"ubfiz\\t%<w>0, %<w>1, %2, %P3"
[(set_attr "type" "bfm")]
diff --git a/gcc-4.9/gcc/config/aarch64/iterators.md b/gcc-4.9/gcc/config/aarch64/iterators.md
index e76e3ef10..cfb181197 100644
--- a/gcc-4.9/gcc/config/aarch64/iterators.md
+++ b/gcc-4.9/gcc/config/aarch64/iterators.md
@@ -66,6 +66,12 @@
;; Quad vector modes.
(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V4SF V2DF])
+;; VQ without 2 element modes.
+(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V4SF])
+
+;; Quad vector with only 2 element modes.
+(define_mode_iterator VQ_2E [V2DI V2DF])
+
;; All vector modes, except double.
(define_mode_iterator VQ_S [V8QI V16QI V4HI V8HI V2SI V4SI])