diff options
| author | Ben Cheng <bccheng@google.com> | 2014-04-22 13:33:12 -0700 |
|---|---|---|
| committer | Ben Cheng <bccheng@google.com> | 2014-04-22 13:33:12 -0700 |
| commit | e3cc64dec20832769406aa38cde83c7dd4194bf4 (patch) | |
| tree | ef8e39be37cfe0cb69d850043b7924389ff17164 /gcc-4.9/gcc/config | |
| parent | f33c7b3122b1d7950efa88067c9a156229ba647b (diff) | |
| download | toolchain_gcc-e3cc64dec20832769406aa38cde83c7dd4194bf4.tar.gz toolchain_gcc-e3cc64dec20832769406aa38cde83c7dd4194bf4.tar.bz2 toolchain_gcc-e3cc64dec20832769406aa38cde83c7dd4194bf4.zip | |
[4.9] GCC 4.9.0 official release refresh
Change-Id: Ic99a7da8b44b789a48aeec93b33e93944d6e6767
Diffstat (limited to 'gcc-4.9/gcc/config')
51 files changed, 1407 insertions, 632 deletions
diff --git a/gcc-4.9/gcc/config/aarch64/aarch64-simd.md b/gcc-4.9/gcc/config/aarch64/aarch64-simd.md index 6048d605c..73aee2c3d 100644 --- a/gcc-4.9/gcc/config/aarch64/aarch64-simd.md +++ b/gcc-4.9/gcc/config/aarch64/aarch64-simd.md @@ -4250,7 +4250,7 @@ CRYPTO_AES))] "TARGET_SIMD && TARGET_CRYPTO" "aes<aes_op>\\t%0.16b, %2.16b" - [(set_attr "type" "crypto_aes")] + [(set_attr "type" "crypto_aese")] ) (define_insn "aarch64_crypto_aes<aesmc_op>v16qi" @@ -4259,7 +4259,7 @@ CRYPTO_AESMC))] "TARGET_SIMD && TARGET_CRYPTO" "aes<aesmc_op>\\t%0.16b, %1.16b" - [(set_attr "type" "crypto_aes")] + [(set_attr "type" "crypto_aesmc")] ) ;; sha1 diff --git a/gcc-4.9/gcc/config/aarch64/aarch64.c b/gcc-4.9/gcc/config/aarch64/aarch64.c index ebd58c007..7b6c2b38e 100644 --- a/gcc-4.9/gcc/config/aarch64/aarch64.c +++ b/gcc-4.9/gcc/config/aarch64/aarch64.c @@ -315,10 +315,6 @@ static GTY(()) int gty_dummy; #define AARCH64_NUM_BITMASKS 5334 static unsigned HOST_WIDE_INT aarch64_bitmasks[AARCH64_NUM_BITMASKS]; -/* Did we set flag_omit_frame_pointer just so - aarch64_frame_pointer_required would be called? */ -static bool faked_omit_frame_pointer; - typedef enum aarch64_cond_code { AARCH64_EQ = 0, AARCH64_NE, AARCH64_CS, AARCH64_CC, AARCH64_MI, AARCH64_PL, @@ -1694,17 +1690,15 @@ aarch64_frame_pointer_required (void) if (cfun->calls_alloca) return true; - /* We may have turned flag_omit_frame_pointer on in order to have this - function called; if we did, we also set the 'faked_omit_frame_pointer' flag - and we'll check it here. - If we really did set flag_omit_frame_pointer normally, then we return false - (no frame pointer required) in all cases. */ + /* In aarch64_override_options_after_change + flag_omit_leaf_frame_pointer turns off the frame pointer by + default. Turn it back on now if we've not got a leaf + function. */ + if (flag_omit_leaf_frame_pointer + && (!crtl->is_leaf || df_regs_ever_live_p (LR_REGNUM))) + return true; - if (flag_omit_frame_pointer && !faked_omit_frame_pointer) - return false; - else if (flag_omit_leaf_frame_pointer) - return !crtl->is_leaf || df_regs_ever_live_p (LR_REGNUM); - return true; + return false; } /* Mark the registers that need to be saved by the callee and calculate @@ -3202,6 +3196,9 @@ aarch64_classify_address (struct aarch64_address_info *info, } else if (SYMBOL_REF_DECL (sym)) align = DECL_ALIGN (SYMBOL_REF_DECL (sym)); + else if (SYMBOL_REF_HAS_BLOCK_INFO_P (sym) + && SYMBOL_REF_BLOCK (sym) != NULL) + align = SYMBOL_REF_BLOCK (sym)->alignment; else align = BITS_PER_UNIT; @@ -4132,23 +4129,8 @@ aarch64_can_eliminate (const int from, const int to) return true; if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) return true; - return false; - } - else - { - /* If we decided that we didn't need a leaf frame pointer but then used - LR in the function, then we'll want a frame pointer after all, so - prevent this elimination to ensure a frame pointer is used. - - NOTE: the original value of flag_omit_frame_pointer gets trashed - IFF flag_omit_leaf_frame_pointer is true, so we check the value - of faked_omit_frame_pointer here (which is true when we always - wish to keep non-leaf frame pointers but only wish to keep leaf frame - pointers when LR is clobbered). */ - if (to == STACK_POINTER_REGNUM - && df_regs_ever_live_p (LR_REGNUM) - && faked_omit_frame_pointer) - return false; + + return false; } return true; @@ -4865,9 +4847,11 @@ aarch64_address_cost (rtx x ATTRIBUTE_UNUSED, } static int -aarch64_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, - reg_class_t from, reg_class_t to) +aarch64_register_move_cost (enum machine_mode mode, + reg_class_t from_i, reg_class_t to_i) { + enum reg_class from = (enum reg_class) from_i; + enum reg_class to = (enum reg_class) to_i; const struct cpu_regmove_cost *regmove_cost = aarch64_tune_params->regmove_cost; @@ -4893,8 +4877,7 @@ aarch64_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, secondary reload. A general register is used as a scratch to move the upper DI value and the lower DI value is moved directly, hence the cost is the sum of three moves. */ - - if (! TARGET_SIMD && GET_MODE_SIZE (from) == 128 && GET_MODE_SIZE (to) == 128) + if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 128) return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP; return regmove_cost->FP2FP; @@ -5278,17 +5261,10 @@ aarch64_override_options (void) static void aarch64_override_options_after_change (void) { - faked_omit_frame_pointer = false; - - /* To omit leaf frame pointers, we need to turn flag_omit_frame_pointer on so - that aarch64_frame_pointer_required will be called. We need to remember - whether flag_omit_frame_pointer was turned on normally or just faked. */ - - if (flag_omit_leaf_frame_pointer && !flag_omit_frame_pointer) - { - flag_omit_frame_pointer = true; - faked_omit_frame_pointer = true; - } + if (flag_omit_frame_pointer) + flag_omit_leaf_frame_pointer = false; + else if (flag_omit_leaf_frame_pointer) + flag_omit_frame_pointer = true; } static struct machine_function * @@ -6566,7 +6542,9 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, bool inverse, /* Splat vector constant out into a byte vector. */ for (i = 0; i < n_elts; i++) { - rtx el = CONST_VECTOR_ELT (op, i); + /* The vector is provided in gcc endian-neutral fashion. For aarch64_be, + it must be laid out in the vector register in reverse order. */ + rtx el = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? (n_elts - 1 - i) : i); unsigned HOST_WIDE_INT elpart; unsigned int part, parts; diff --git a/gcc-4.9/gcc/config/arm/aarch-common-protos.h b/gcc-4.9/gcc/config/arm/aarch-common-protos.h index a5ff6b4f9..3e6e2429f 100644 --- a/gcc-4.9/gcc/config/arm/aarch-common-protos.h +++ b/gcc-4.9/gcc/config/arm/aarch-common-protos.h @@ -23,6 +23,7 @@ #ifndef GCC_AARCH_COMMON_PROTOS_H #define GCC_AARCH_COMMON_PROTOS_H +extern int aarch_crypto_can_dual_issue (rtx, rtx); extern int arm_early_load_addr_dep (rtx, rtx); extern int arm_early_store_addr_dep (rtx, rtx); extern int arm_mac_accumulator_is_mul_result (rtx, rtx); diff --git a/gcc-4.9/gcc/config/arm/aarch-common.c b/gcc-4.9/gcc/config/arm/aarch-common.c index c11f7e954..af8fc9996 100644 --- a/gcc-4.9/gcc/config/arm/aarch-common.c +++ b/gcc-4.9/gcc/config/arm/aarch-common.c @@ -31,6 +31,42 @@ #include "c-family/c-common.h" #include "rtl.h" +/* In ARMv8-A there's a general expectation that AESE/AESMC + and AESD/AESIMC sequences of the form: + + AESE Vn, _ + AESMC Vn, Vn + + will issue both instructions in a single cycle on super-scalar + implementations. This function identifies such pairs. */ + +int +aarch_crypto_can_dual_issue (rtx producer, rtx consumer) +{ + rtx producer_src, consumer_src; + + producer = single_set (producer); + consumer = single_set (consumer); + + producer_src = producer ? SET_SRC (producer) : NULL; + consumer_src = consumer ? SET_SRC (consumer) : NULL; + + if (producer_src && consumer_src + && GET_CODE (producer_src) == UNSPEC && GET_CODE (consumer_src) == UNSPEC + && ((XINT (producer_src, 1) == UNSPEC_AESE + && XINT (consumer_src, 1) == UNSPEC_AESMC) + || (XINT (producer_src, 1) == UNSPEC_AESD + && XINT (consumer_src, 1) == UNSPEC_AESIMC))) + { + unsigned int regno = REGNO (SET_DEST (producer)); + + return REGNO (SET_DEST (consumer)) == regno + && REGNO (XVECEXP (consumer_src, 0, 0)) == regno; + } + + return 0; +} + typedef struct { rtx_code search_code; diff --git a/gcc-4.9/gcc/config/arm/arm.c b/gcc-4.9/gcc/config/arm/arm.c index 0240cc70e..e5cf50366 100644 --- a/gcc-4.9/gcc/config/arm/arm.c +++ b/gcc-4.9/gcc/config/arm/arm.c @@ -72,6 +72,7 @@ struct four_ints }; /* Forward function declarations. */ +static bool arm_const_not_ok_for_debug_p (rtx); static bool arm_lra_p (void); static bool arm_needs_doubleword_align (enum machine_mode, const_tree); static int arm_compute_static_chain_stack_bytes (void); @@ -674,6 +675,9 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_CAN_USE_DOLOOP_P #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost +#undef TARGET_CONST_NOT_OK_FOR_DEBUG_P +#define TARGET_CONST_NOT_OK_FOR_DEBUG_P arm_const_not_ok_for_debug_p + struct gcc_target targetm = TARGET_INITIALIZER; /* Obstack for minipool constant handling. */ @@ -31116,4 +31120,46 @@ arm_asan_shadow_offset (void) return (unsigned HOST_WIDE_INT) 1 << 29; } + +/* This is a temporary fix for PR60655. Ideally we need + to handle most of these cases in the generic part but + currently we reject minus (..) (sym_ref). We try to + ameliorate the case with minus (sym_ref1) (sym_ref2) + where they are in the same section. */ + +static bool +arm_const_not_ok_for_debug_p (rtx p) +{ + tree decl_op0 = NULL; + tree decl_op1 = NULL; + + if (GET_CODE (p) == MINUS) + { + if (GET_CODE (XEXP (p, 1)) == SYMBOL_REF) + { + decl_op1 = SYMBOL_REF_DECL (XEXP (p, 1)); + if (decl_op1 + && GET_CODE (XEXP (p, 0)) == SYMBOL_REF + && (decl_op0 = SYMBOL_REF_DECL (XEXP (p, 0)))) + { + if ((TREE_CODE (decl_op1) == VAR_DECL + || TREE_CODE (decl_op1) == CONST_DECL) + && (TREE_CODE (decl_op0) == VAR_DECL + || TREE_CODE (decl_op0) == CONST_DECL)) + return (get_variable_section (decl_op1, false) + != get_variable_section (decl_op0, false)); + + if (TREE_CODE (decl_op1) == LABEL_DECL + && TREE_CODE (decl_op0) == LABEL_DECL) + return (DECL_CONTEXT (decl_op1) + != DECL_CONTEXT (decl_op0)); + } + + return true; + } + } + + return false; +} + #include "gt-arm.h" diff --git a/gcc-4.9/gcc/config/arm/arm.h b/gcc-4.9/gcc/config/arm/arm.h index 7ca47a7ec..597e69c6e 100644 --- a/gcc-4.9/gcc/config/arm/arm.h +++ b/gcc-4.9/gcc/config/arm/arm.h @@ -937,13 +937,13 @@ extern int arm_arch_crc; #ifndef ARM_TARGET2_DWARF_FORMAT #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel +#endif /* ttype entries (the only interesting data references used) use TARGET2 relocations. */ #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ : DW_EH_PE_absptr) -#endif /* The native (Norcroft) Pascal compiler for the ARM passes the static chain as an invisible last argument (possible since varargs don't exist in @@ -2194,14 +2194,9 @@ extern int making_const_table; #undef ASM_OUTPUT_BEFORE_CASE_LABEL #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ -/* Make sure subsequent insns are aligned after a TBB. */ -#define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ - do \ - { \ - if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \ - ASM_OUTPUT_ALIGN (FILE, 1); \ - } \ - while (0) +#define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ + (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ + ? 1 : 0) #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ do \ diff --git a/gcc-4.9/gcc/config/arm/arm.md b/gcc-4.9/gcc/config/arm/arm.md index 2ddda0208..4b81ee272 100644 --- a/gcc-4.9/gcc/config/arm/arm.md +++ b/gcc-4.9/gcc/config/arm/arm.md @@ -262,105 +262,6 @@ ; initialized by arm_option_override() (define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched"))) -; YES if the "type" attribute assigned to the insn denotes an -; Advanced SIMD instruction, NO otherwise. -(define_attr "is_neon_type" "yes,no" - (if_then_else (eq_attr "type" - "neon_add, neon_add_q, neon_add_widen, neon_add_long,\ - neon_qadd, neon_qadd_q, neon_add_halve, neon_add_halve_q,\ - neon_add_halve_narrow_q,\ - neon_sub, neon_sub_q, neon_sub_widen, neon_sub_long, neon_qsub,\ - neon_qsub_q, neon_sub_halve, neon_sub_halve_q,\ - neon_sub_halve_narrow_q,\ - neon_abs, neon_abs_q, neon_neg, neon_neg_q, neon_qneg,\ - neon_qneg_q, neon_qabs, neon_qabs_q, neon_abd, neon_abd_q,\ - neon_abd_long, neon_minmax, neon_minmax_q, neon_compare,\ - neon_compare_q, neon_compare_zero, neon_compare_zero_q,\ - neon_arith_acc, neon_arith_acc_q, neon_reduc_add,\ - neon_reduc_add_q, neon_reduc_add_long, neon_reduc_add_acc,\ - neon_reduc_add_acc_q, neon_reduc_minmax, neon_reduc_minmax_q,\ - neon_logic, neon_logic_q, neon_tst, neon_tst_q,\ - neon_shift_imm, neon_shift_imm_q, neon_shift_imm_narrow_q,\ - neon_shift_imm_long, neon_shift_reg, neon_shift_reg_q,\ - neon_shift_acc, neon_shift_acc_q, neon_sat_shift_imm,\ - neon_sat_shift_imm_q, neon_sat_shift_imm_narrow_q,\ - neon_sat_shift_reg, neon_sat_shift_reg_q,\ - neon_ins, neon_ins_q, neon_move, neon_move_q, neon_move_narrow_q,\ - neon_permute, neon_permute_q, neon_zip, neon_zip_q, neon_tbl1,\ - neon_tbl1_q, neon_tbl2, neon_tbl2_q, neon_tbl3, neon_tbl3_q,\ - neon_tbl4, neon_tbl4_q, neon_bsl, neon_bsl_q, neon_cls,\ - neon_cls_q, neon_cnt, neon_cnt_q, neon_dup, neon_dup_q,\ - neon_ext, neon_ext_q, neon_rbit, neon_rbit_q,\ - neon_rev, neon_rev_q, neon_mul_b, neon_mul_b_q, neon_mul_h,\ - neon_mul_h_q, neon_mul_s, neon_mul_s_q, neon_mul_b_long,\ - neon_mul_h_long, neon_mul_s_long, neon_mul_d_long, neon_mul_h_scalar,\ - neon_mul_h_scalar_q, neon_mul_s_scalar, neon_mul_s_scalar_q,\ - neon_mul_h_scalar_long, neon_mul_s_scalar_long, neon_sat_mul_b,\ - neon_sat_mul_b_q, neon_sat_mul_h, neon_sat_mul_h_q,\ - neon_sat_mul_s, neon_sat_mul_s_q, neon_sat_mul_b_long,\ - neon_sat_mul_h_long, neon_sat_mul_s_long, neon_sat_mul_h_scalar,\ - neon_sat_mul_h_scalar_q, neon_sat_mul_s_scalar,\ - neon_sat_mul_s_scalar_q, neon_sat_mul_h_scalar_long,\ - neon_sat_mul_s_scalar_long, neon_mla_b, neon_mla_b_q, neon_mla_h,\ - neon_mla_h_q, neon_mla_s, neon_mla_s_q, neon_mla_b_long,\ - neon_mla_h_long, neon_mla_s_long, neon_mla_h_scalar,\ - neon_mla_h_scalar_q, neon_mla_s_scalar, neon_mla_s_scalar_q,\ - neon_mla_h_scalar_long, neon_mla_s_scalar_long,\ - neon_sat_mla_b_long, neon_sat_mla_h_long,\ - neon_sat_mla_s_long, neon_sat_mla_h_scalar_long,\ - neon_sat_mla_s_scalar_long,\ - neon_to_gp, neon_to_gp_q, neon_from_gp, neon_from_gp_q,\ - neon_ldr, neon_load1_1reg, neon_load1_1reg_q, neon_load1_2reg,\ - neon_load1_2reg_q, neon_load1_3reg, neon_load1_3reg_q,\ - neon_load1_4reg, neon_load1_4reg_q, neon_load1_all_lanes,\ - neon_load1_all_lanes_q, neon_load1_one_lane, neon_load1_one_lane_q,\ - neon_load2_2reg, neon_load2_2reg_q, neon_load2_4reg,\ - neon_load2_4reg_q, neon_load2_all_lanes, neon_load2_all_lanes_q,\ - neon_load2_one_lane, neon_load2_one_lane_q,\ - neon_load3_3reg, neon_load3_3reg_q, neon_load3_all_lanes,\ - neon_load3_all_lanes_q, neon_load3_one_lane, neon_load3_one_lane_q,\ - neon_load4_4reg, neon_load4_4reg_q, neon_load4_all_lanes,\ - neon_load4_all_lanes_q, neon_load4_one_lane, neon_load4_one_lane_q,\ - neon_str, neon_store1_1reg, neon_store1_1reg_q, neon_store1_2reg,\ - neon_store1_2reg_q, neon_store1_3reg, neon_store1_3reg_q,\ - neon_store1_4reg, neon_store1_4reg_q, neon_store1_one_lane,\ - neon_store1_one_lane_q, neon_store2_2reg, neon_store2_2reg_q,\ - neon_store2_4reg, neon_store2_4reg_q, neon_store2_one_lane,\ - neon_store2_one_lane_q, neon_store3_3reg, neon_store3_3reg_q,\ - neon_store3_one_lane, neon_store3_one_lane_q, neon_store4_4reg,\ - neon_store4_4reg_q, neon_store4_one_lane, neon_store4_one_lane_q,\ - neon_fp_abd_s, neon_fp_abd_s_q, neon_fp_abd_d, neon_fp_abd_d_q,\ - neon_fp_addsub_s, neon_fp_addsub_s_q, neon_fp_addsub_d,\ - neon_fp_addsub_d_q, neon_fp_compare_s, neon_fp_compare_s_q,\ - neon_fp_compare_d, neon_fp_compare_d_q, neon_fp_minmax_s,\ - neon_fp_minmax_s_q, neon_fp_minmax_d, neon_fp_minmax_d_q,\ - neon_fp_reduc_add_s, neon_fp_reduc_add_s_q, neon_fp_reduc_add_d,\ - neon_fp_reduc_add_d_q, neon_fp_reduc_minmax_s, - neon_fp_reduc_minmax_s_q, neon_fp_reduc_minmax_d,\ - neon_fp_reduc_minmax_d_q,\ - neon_fp_cvt_narrow_s_q, neon_fp_cvt_narrow_d_q,\ - neon_fp_cvt_widen_h, neon_fp_cvt_widen_s, neon_fp_to_int_s,\ - neon_fp_to_int_s_q, neon_int_to_fp_s, neon_int_to_fp_s_q,\ - neon_fp_round_s, neon_fp_round_s_q, neon_fp_recpe_s,\ - neon_fp_recpe_s_q,\ - neon_fp_recpe_d, neon_fp_recpe_d_q, neon_fp_recps_s,\ - neon_fp_recps_s_q, neon_fp_recps_d, neon_fp_recps_d_q,\ - neon_fp_recpx_s, neon_fp_recpx_s_q, neon_fp_recpx_d,\ - neon_fp_recpx_d_q, neon_fp_rsqrte_s, neon_fp_rsqrte_s_q,\ - neon_fp_rsqrte_d, neon_fp_rsqrte_d_q, neon_fp_rsqrts_s,\ - neon_fp_rsqrts_s_q, neon_fp_rsqrts_d, neon_fp_rsqrts_d_q,\ - neon_fp_mul_s, neon_fp_mul_s_q, neon_fp_mul_s_scalar,\ - neon_fp_mul_s_scalar_q, neon_fp_mul_d, neon_fp_mul_d_q,\ - neon_fp_mul_d_scalar_q, neon_fp_mla_s, neon_fp_mla_s_q,\ - neon_fp_mla_s_scalar, neon_fp_mla_s_scalar_q, neon_fp_mla_d,\ - neon_fp_mla_d_q, neon_fp_mla_d_scalar_q, neon_fp_sqrt_s,\ - neon_fp_sqrt_s_q, neon_fp_sqrt_d, neon_fp_sqrt_d_q,\ - neon_fp_div_s, neon_fp_div_s_q, neon_fp_div_d, neon_fp_div_d_q, crypto_aes,\ - crypto_sha1_xor, crypto_sha1_fast, crypto_sha1_slow, crypto_sha256_fast,\ - crypto_sha256_slow") - (const_string "yes") - (const_string "no"))) - ; condition codes: this one is used by final_prescan_insn to speed up ; conditionalizing instructions. It saves having to scan the rtl to see if ; it uses or alters the condition codes. @@ -2883,8 +2784,8 @@ (define_insn "insv_zero" [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r") - (match_operand:SI 1 "const_int_operand" "M") - (match_operand:SI 2 "const_int_operand" "M")) + (match_operand:SI 1 "const_int_M_operand" "M") + (match_operand:SI 2 "const_int_M_operand" "M")) (const_int 0))] "arm_arch_thumb2" "bfc%?\t%0, %2, %1" @@ -2896,8 +2797,8 @@ (define_insn "insv_t2" [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r") - (match_operand:SI 1 "const_int_operand" "M") - (match_operand:SI 2 "const_int_operand" "M")) + (match_operand:SI 1 "const_int_M_operand" "M") + (match_operand:SI 2 "const_int_M_operand" "M")) (match_operand:SI 3 "s_register_operand" "r"))] "arm_arch_thumb2" "bfi%?\t%0, %3, %2, %1" @@ -4579,8 +4480,8 @@ (define_insn "*extv_reg" [(set (match_operand:SI 0 "s_register_operand" "=r") (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "const_int_operand" "M") - (match_operand:SI 3 "const_int_operand" "M")))] + (match_operand:SI 2 "const_int_M_operand" "M") + (match_operand:SI 3 "const_int_M_operand" "M")))] "arm_arch_thumb2" "sbfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") @@ -4592,8 +4493,8 @@ (define_insn "extzv_t2" [(set (match_operand:SI 0 "s_register_operand" "=r") (zero_extract:SI (match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "const_int_operand" "M") - (match_operand:SI 3 "const_int_operand" "M")))] + (match_operand:SI 2 "const_int_M_operand" "M") + (match_operand:SI 3 "const_int_M_operand" "M")))] "arm_arch_thumb2" "ubfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") @@ -12172,7 +12073,7 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 1 "s_register_operand" "+rk") (plus:SI (match_dup 1) - (match_operand:SI 2 "const_int_operand" "I"))) + (match_operand:SI 2 "const_int_I_operand" "I"))) (set (match_operand:SI 3 "s_register_operand" "=rk") (mem:SI (match_dup 1))) ])] @@ -12201,7 +12102,7 @@ [(return) (set (match_operand:SI 1 "s_register_operand" "+rk") (plus:SI (match_dup 1) - (match_operand:SI 2 "const_int_operand" "I"))) + (match_operand:SI 2 "const_int_I_operand" "I"))) (set (match_operand:SI 3 "s_register_operand" "=rk") (mem:SI (match_dup 1))) ])] @@ -12254,7 +12155,7 @@ [(match_parallel 0 "pop_multiple_fp" [(set (match_operand:SI 1 "s_register_operand" "+rk") (plus:SI (match_dup 1) - (match_operand:SI 2 "const_int_operand" "I"))) + (match_operand:SI 2 "const_int_I_operand" "I"))) (set (match_operand:DF 3 "vfp_hard_register_operand" "") (mem:DF (match_dup 1)))])] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" diff --git a/gcc-4.9/gcc/config/arm/cortex-a53.md b/gcc-4.9/gcc/config/arm/cortex-a53.md index deae8eba5..a629bd61d 100644 --- a/gcc-4.9/gcc/config/arm/cortex-a53.md +++ b/gcc-4.9/gcc/config/arm/cortex-a53.md @@ -61,6 +61,11 @@ (define_cpu_unit "cortex_a53_fp_div_sqrt" "cortex_a53") +;; The Advanced SIMD pipelines. + +(define_cpu_unit "cortex_a53_simd0" "cortex_a53") +(define_cpu_unit "cortex_a53_simd1" "cortex_a53") + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ALU instructions. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -240,12 +245,45 @@ (define_insn_reservation "cortex_a53_fdivs" 14 (and (eq_attr "tune" "cortexa53") (eq_attr "type" "fdivs, fsqrts")) - "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 13") + "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 5") (define_insn_reservation "cortex_a53_fdivd" 29 (and (eq_attr "tune" "cortexa53") (eq_attr "type" "fdivd, fsqrtd")) - "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 28") + "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 8") + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; ARMv8-A Cryptographic extensions. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define_insn_reservation "cortex_a53_crypto_aese" 2 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "crypto_aese")) + "cortex_a53_simd0") + +(define_insn_reservation "cortex_a53_crypto_aesmc" 2 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "crypto_aesmc")) + "cortex_a53_simd0 | cortex_a53_simd1") + +(define_insn_reservation "cortex_a53_crypto_sha1_fast" 2 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "crypto_sha1_fast, crypto_sha256_fast")) + "cortex_a53_simd0") + +(define_insn_reservation "cortex_a53_crypto_sha1_xor" 3 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "crypto_sha1_xor")) + "cortex_a53_simd0") + +(define_insn_reservation "cortex_a53_crypto_sha_slow" 5 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "crypto_sha1_slow, crypto_sha256_slow")) + "cortex_a53_simd0") + +(define_bypass 0 "cortex_a53_crypto_aese" + "cortex_a53_crypto_aesmc" + "aarch_crypto_can_dual_issue") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; VFP to/from core transfers. @@ -284,6 +322,16 @@ (eq_attr "type" "f_loadd")) "cortex_a53_slot0") +(define_insn_reservation "cortex_a53_f_load_2reg" 5 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "neon_load2_2reg_q")) + "(cortex_a53_slot_any+cortex_a53_ls)*2") + +(define_insn_reservation "cortex_a53_f_loadq" 5 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "neon_load1_1reg_q")) + "cortex_a53_slot_any+cortex_a53_ls") + (define_insn_reservation "cortex_a53_f_stores" 0 (and (eq_attr "tune" "cortexa53") (eq_attr "type" "f_stores")) @@ -307,3 +355,11 @@ cortex_a53_fdivs, cortex_a53_fdivd,\ cortex_a53_f2r") +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; Crude Advanced SIMD approximation. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define_insn_reservation "cortex_53_advsimd" 4 + (and (eq_attr "tune" "cortexa53") + (eq_attr "is_neon_type" "yes")) + "cortex_a53_simd0") diff --git a/gcc-4.9/gcc/config/arm/iterators.md b/gcc-4.9/gcc/config/arm/iterators.md index 33e09e4ce..aebab9340 100644 --- a/gcc-4.9/gcc/config/arm/iterators.md +++ b/gcc-4.9/gcc/config/arm/iterators.md @@ -551,8 +551,8 @@ (UNSPEC_SHA256SU1 "sha256su1")]) (define_int_attr crypto_type - [(UNSPEC_AESE "crypto_aes") (UNSPEC_AESD "crypto_aes") - (UNSPEC_AESMC "crypto_aes") (UNSPEC_AESIMC "crypto_aes") + [(UNSPEC_AESE "crypto_aese") (UNSPEC_AESD "crypto_aese") + (UNSPEC_AESMC "crypto_aesmc") (UNSPEC_AESIMC "crypto_aesmc") (UNSPEC_SHA1C "crypto_sha1_slow") (UNSPEC_SHA1P "crypto_sha1_slow") (UNSPEC_SHA1M "crypto_sha1_slow") (UNSPEC_SHA1SU1 "crypto_sha1_fast") (UNSPEC_SHA1SU0 "crypto_sha1_xor") (UNSPEC_SHA256H "crypto_sha256_slow") diff --git a/gcc-4.9/gcc/config/arm/predicates.md b/gcc-4.9/gcc/config/arm/predicates.md index ce5c9a830..6273e8820 100644 --- a/gcc-4.9/gcc/config/arm/predicates.md +++ b/gcc-4.9/gcc/config/arm/predicates.md @@ -153,6 +153,14 @@ (ior (match_operand 0 "arm_rhs_operand") (match_operand 0 "memory_operand"))) +(define_predicate "const_int_I_operand" + (and (match_operand 0 "const_int_operand") + (match_test "satisfies_constraint_I (op)"))) + +(define_predicate "const_int_M_operand" + (and (match_operand 0 "const_int_operand") + (match_test "satisfies_constraint_M (op)"))) + ;; This doesn't have to do much because the constant is already checked ;; in the shift_operator predicate. (define_predicate "shift_amount_operand" diff --git a/gcc-4.9/gcc/config/arm/t-aprofile b/gcc-4.9/gcc/config/arm/t-aprofile index b968711c1..ff9e2e1b3 100644 --- a/gcc-4.9/gcc/config/arm/t-aprofile +++ b/gcc-4.9/gcc/config/arm/t-aprofile @@ -81,7 +81,8 @@ MULTILIB_EXCEPTIONS += *march=armv7ve/*mfpu=neon-fp-armv8* MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a8 MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a9 MULTILIB_MATCHES += march?armv7-a=mcpu?cortex-a5 -MULTILIB_MATCHES += march?armv7ve=mcpu?cortex-a15=mcpu?cortex-a12 +MULTILIB_MATCHES += march?armv7ve=mcpu?cortex-a15 +MULTILIB_MATCHES += march?armv7ve=mcpu?cortex-a12 MULTILIB_MATCHES += march?armv7ve=mcpu?cortex-a15.cortex-a7 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a53 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57 diff --git a/gcc-4.9/gcc/config/arm/types.md b/gcc-4.9/gcc/config/arm/types.md index cc39cd11f..efbf7a753 100644 --- a/gcc-4.9/gcc/config/arm/types.md +++ b/gcc-4.9/gcc/config/arm/types.md @@ -524,7 +524,8 @@ ; ; The classification below is for Crypto instructions. ; -; crypto_aes +; crypto_aese +; crypto_aesmc ; crypto_sha1_xor ; crypto_sha1_fast ; crypto_sha1_slow @@ -1051,7 +1052,8 @@ neon_fp_div_d,\ neon_fp_div_d_q,\ \ - crypto_aes,\ + crypto_aese,\ + crypto_aesmc,\ crypto_sha1_xor,\ crypto_sha1_fast,\ crypto_sha1_slow,\ @@ -1075,3 +1077,102 @@ "smlalxy,umull,umulls,umaal,umlal,umlals,smull,smulls,smlal,smlals") (const_string "yes") (const_string "no"))) + +; YES if the "type" attribute assigned to the insn denotes an +; Advanced SIMD instruction, NO otherwise. +(define_attr "is_neon_type" "yes,no" + (if_then_else (eq_attr "type" + "neon_add, neon_add_q, neon_add_widen, neon_add_long,\ + neon_qadd, neon_qadd_q, neon_add_halve, neon_add_halve_q,\ + neon_add_halve_narrow_q,\ + neon_sub, neon_sub_q, neon_sub_widen, neon_sub_long, neon_qsub,\ + neon_qsub_q, neon_sub_halve, neon_sub_halve_q,\ + neon_sub_halve_narrow_q,\ + neon_abs, neon_abs_q, neon_neg, neon_neg_q, neon_qneg,\ + neon_qneg_q, neon_qabs, neon_qabs_q, neon_abd, neon_abd_q,\ + neon_abd_long, neon_minmax, neon_minmax_q, neon_compare,\ + neon_compare_q, neon_compare_zero, neon_compare_zero_q,\ + neon_arith_acc, neon_arith_acc_q, neon_reduc_add,\ + neon_reduc_add_q, neon_reduc_add_long, neon_reduc_add_acc,\ + neon_reduc_add_acc_q, neon_reduc_minmax, neon_reduc_minmax_q,\ + neon_logic, neon_logic_q, neon_tst, neon_tst_q,\ + neon_shift_imm, neon_shift_imm_q, neon_shift_imm_narrow_q,\ + neon_shift_imm_long, neon_shift_reg, neon_shift_reg_q,\ + neon_shift_acc, neon_shift_acc_q, neon_sat_shift_imm,\ + neon_sat_shift_imm_q, neon_sat_shift_imm_narrow_q,\ + neon_sat_shift_reg, neon_sat_shift_reg_q,\ + neon_ins, neon_ins_q, neon_move, neon_move_q, neon_move_narrow_q,\ + neon_permute, neon_permute_q, neon_zip, neon_zip_q, neon_tbl1,\ + neon_tbl1_q, neon_tbl2, neon_tbl2_q, neon_tbl3, neon_tbl3_q,\ + neon_tbl4, neon_tbl4_q, neon_bsl, neon_bsl_q, neon_cls,\ + neon_cls_q, neon_cnt, neon_cnt_q, neon_dup, neon_dup_q,\ + neon_ext, neon_ext_q, neon_rbit, neon_rbit_q,\ + neon_rev, neon_rev_q, neon_mul_b, neon_mul_b_q, neon_mul_h,\ + neon_mul_h_q, neon_mul_s, neon_mul_s_q, neon_mul_b_long,\ + neon_mul_h_long, neon_mul_s_long, neon_mul_d_long, neon_mul_h_scalar,\ + neon_mul_h_scalar_q, neon_mul_s_scalar, neon_mul_s_scalar_q,\ + neon_mul_h_scalar_long, neon_mul_s_scalar_long, neon_sat_mul_b,\ + neon_sat_mul_b_q, neon_sat_mul_h, neon_sat_mul_h_q,\ + neon_sat_mul_s, neon_sat_mul_s_q, neon_sat_mul_b_long,\ + neon_sat_mul_h_long, neon_sat_mul_s_long, neon_sat_mul_h_scalar,\ + neon_sat_mul_h_scalar_q, neon_sat_mul_s_scalar,\ + neon_sat_mul_s_scalar_q, neon_sat_mul_h_scalar_long,\ + neon_sat_mul_s_scalar_long, neon_mla_b, neon_mla_b_q, neon_mla_h,\ + neon_mla_h_q, neon_mla_s, neon_mla_s_q, neon_mla_b_long,\ + neon_mla_h_long, neon_mla_s_long, neon_mla_h_scalar,\ + neon_mla_h_scalar_q, neon_mla_s_scalar, neon_mla_s_scalar_q,\ + neon_mla_h_scalar_long, neon_mla_s_scalar_long,\ + neon_sat_mla_b_long, neon_sat_mla_h_long,\ + neon_sat_mla_s_long, neon_sat_mla_h_scalar_long,\ + neon_sat_mla_s_scalar_long,\ + neon_to_gp, neon_to_gp_q, neon_from_gp, neon_from_gp_q,\ + neon_ldr, neon_load1_1reg, neon_load1_1reg_q, neon_load1_2reg,\ + neon_load1_2reg_q, neon_load1_3reg, neon_load1_3reg_q,\ + neon_load1_4reg, neon_load1_4reg_q, neon_load1_all_lanes,\ + neon_load1_all_lanes_q, neon_load1_one_lane, neon_load1_one_lane_q,\ + neon_load2_2reg, neon_load2_2reg_q, neon_load2_4reg,\ + neon_load2_4reg_q, neon_load2_all_lanes, neon_load2_all_lanes_q,\ + neon_load2_one_lane, neon_load2_one_lane_q,\ + neon_load3_3reg, neon_load3_3reg_q, neon_load3_all_lanes,\ + neon_load3_all_lanes_q, neon_load3_one_lane, neon_load3_one_lane_q,\ + neon_load4_4reg, neon_load4_4reg_q, neon_load4_all_lanes,\ + neon_load4_all_lanes_q, neon_load4_one_lane, neon_load4_one_lane_q,\ + neon_str, neon_store1_1reg, neon_store1_1reg_q, neon_store1_2reg,\ + neon_store1_2reg_q, neon_store1_3reg, neon_store1_3reg_q,\ + neon_store1_4reg, neon_store1_4reg_q, neon_store1_one_lane,\ + neon_store1_one_lane_q, neon_store2_2reg, neon_store2_2reg_q,\ + neon_store2_4reg, neon_store2_4reg_q, neon_store2_one_lane,\ + neon_store2_one_lane_q, neon_store3_3reg, neon_store3_3reg_q,\ + neon_store3_one_lane, neon_store3_one_lane_q, neon_store4_4reg,\ + neon_store4_4reg_q, neon_store4_one_lane, neon_store4_one_lane_q,\ + neon_fp_abd_s, neon_fp_abd_s_q, neon_fp_abd_d, neon_fp_abd_d_q,\ + neon_fp_addsub_s, neon_fp_addsub_s_q, neon_fp_addsub_d,\ + neon_fp_addsub_d_q, neon_fp_compare_s, neon_fp_compare_s_q,\ + neon_fp_compare_d, neon_fp_compare_d_q, neon_fp_minmax_s,\ + neon_fp_minmax_s_q, neon_fp_minmax_d, neon_fp_minmax_d_q,\ + neon_fp_reduc_add_s, neon_fp_reduc_add_s_q, neon_fp_reduc_add_d,\ + neon_fp_reduc_add_d_q, neon_fp_reduc_minmax_s, + neon_fp_reduc_minmax_s_q, neon_fp_reduc_minmax_d,\ + neon_fp_reduc_minmax_d_q,\ + neon_fp_cvt_narrow_s_q, neon_fp_cvt_narrow_d_q,\ + neon_fp_cvt_widen_h, neon_fp_cvt_widen_s, neon_fp_to_int_s,\ + neon_fp_to_int_s_q, neon_int_to_fp_s, neon_int_to_fp_s_q,\ + neon_fp_round_s, neon_fp_round_s_q, neon_fp_recpe_s,\ + neon_fp_recpe_s_q,\ + neon_fp_recpe_d, neon_fp_recpe_d_q, neon_fp_recps_s,\ + neon_fp_recps_s_q, neon_fp_recps_d, neon_fp_recps_d_q,\ + neon_fp_recpx_s, neon_fp_recpx_s_q, neon_fp_recpx_d,\ + neon_fp_recpx_d_q, neon_fp_rsqrte_s, neon_fp_rsqrte_s_q,\ + neon_fp_rsqrte_d, neon_fp_rsqrte_d_q, neon_fp_rsqrts_s,\ + neon_fp_rsqrts_s_q, neon_fp_rsqrts_d, neon_fp_rsqrts_d_q,\ + neon_fp_mul_s, neon_fp_mul_s_q, neon_fp_mul_s_scalar,\ + neon_fp_mul_s_scalar_q, neon_fp_mul_d, neon_fp_mul_d_q,\ + neon_fp_mul_d_scalar_q, neon_fp_mla_s, neon_fp_mla_s_q,\ + neon_fp_mla_s_scalar, neon_fp_mla_s_scalar_q, neon_fp_mla_d,\ + neon_fp_mla_d_q, neon_fp_mla_d_scalar_q, neon_fp_sqrt_s,\ + neon_fp_sqrt_s_q, neon_fp_sqrt_d, neon_fp_sqrt_d_q,\ + neon_fp_div_s, neon_fp_div_s_q, neon_fp_div_d, neon_fp_div_d_q, crypto_aese,\ + crypto_aesmc, crypto_sha1_xor, crypto_sha1_fast, crypto_sha1_slow,\ + crypto_sha256_fast, crypto_sha256_slow") + (const_string "yes") + (const_string "no"))) diff --git a/gcc-4.9/gcc/config/avr/avr-arch.h b/gcc-4.9/gcc/config/avr/avr-arch.h index 6357e997c..b3c7cc085 100644 --- a/gcc-4.9/gcc/config/avr/avr-arch.h +++ b/gcc-4.9/gcc/config/avr/avr-arch.h @@ -100,32 +100,12 @@ typedef struct /* Index in avr_arch_types[]. */ enum avr_arch arch; + /* device specific feature */ + int dev_attribute; + /* Must lie outside user's namespace. NULL == no macro. */ const char *const macro; - /* Stack pointer have 8 bits width. */ - int short_sp; - - /* Some AVR devices have a core erratum when skipping a 2-word instruction. - Skip instructions are: SBRC, SBRS, SBIC, SBIS, CPSE. - Problems will occur with return address is IRQ executes during the - skip sequence. - - A support ticket from Atmel returned the following information: - - Subject: (ATTicket:644469) On AVR skip-bug core Erratum - From: avr@atmel.com Date: 2011-07-27 - (Please keep the subject when replying to this mail) - - This errata exists only in AT90S8515 and ATmega103 devices. - - For information please refer the following respective errata links - http://www.atmel.com/dyn/resources/prod_documents/doc2494.pdf - http://www.atmel.com/dyn/resources/prod_documents/doc1436.pdf */ - - /* Core Erratum: Must not skip 2-word instruction. */ - int errata_skip; - /* Start of data section. */ int data_section_start; @@ -136,6 +116,42 @@ typedef struct const char *const library_name; } avr_mcu_t; +/* AVR device specific features. + +AVR_ISA_RMW + Only few avr devices have Read-Modify-Write (RMW) instructions + (XCH, LAC, LAS and LAT) + +AVR_SHORT_SP + Stack Pointer has only 8 bit width. + The device / multilib has an 8-bit stack pointer (no SPH). + +AVR_ERRATA_SKIP + Some AVR devices have a core erratum when skipping a 2-word instruction. + Skip instructions are: SBRC, SBRS, SBIC, SBIS, CPSE. + Problems will occur with return address is IRQ executes during the + skip sequence. + + A support ticket from Atmel returned the following information: + + Subject: (ATTicket:644469) On AVR skip-bug core Erratum + From: avr@atmel.com Date: 2011-07-27 + (Please keep the subject when replying to this mail) + + This errata exists only in AT90S8515 and ATmega103 devices. + + For information please refer the following respective errata links + http://www.atmel.com/dyn/resources/prod_documents/doc2494.pdf + http://www.atmel.com/dyn/resources/prod_documents/doc1436.pdf */ + +enum avr_device_specific_features +{ + AVR_ISA_NONE, + AVR_ISA_RMW = 0x1, /* device has RMW instructions. */ + AVR_SHORT_SP = 0x2, /* Stack Pointer has 8 bits width. */ + AVR_ERRATA_SKIP = 0x4 /* device has a core erratum. */ +}; + /* Map architecture to its texinfo string. */ typedef struct diff --git a/gcc-4.9/gcc/config/avr/avr-c.c b/gcc-4.9/gcc/config/avr/avr-c.c index 101d28092..c6a2f1f94 100644 --- a/gcc-4.9/gcc/config/avr/avr-c.c +++ b/gcc-4.9/gcc/config/avr/avr-c.c @@ -347,7 +347,7 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile) if (TARGET_NO_INTERRUPTS) cpp_define (pfile, "__NO_INTERRUPTS__"); - if (avr_current_device->errata_skip) + if (avr_current_device->dev_attribute & AVR_ERRATA_SKIP) { cpp_define (pfile, "__AVR_ERRATA_SKIP__"); @@ -355,6 +355,9 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile) cpp_define (pfile, "__AVR_ERRATA_SKIP_JMP_CALL__"); } + if (avr_current_device->dev_attribute & AVR_ISA_RMW) + cpp_define (pfile, "__AVR_ISA_RMW__"); + cpp_define_formatted (pfile, "__AVR_SFR_OFFSET__=0x%x", avr_current_arch->sfr_offset); diff --git a/gcc-4.9/gcc/config/avr/avr-devices.c b/gcc-4.9/gcc/config/avr/avr-devices.c index 177f1961f..2485cad65 100644 --- a/gcc-4.9/gcc/config/avr/avr-devices.c +++ b/gcc-4.9/gcc/config/avr/avr-devices.c @@ -104,11 +104,11 @@ avr_texinfo[] = const avr_mcu_t avr_mcu_types[] = { -#define AVR_MCU(NAME, ARCH, MACRO, SP8, ERR_SKIP, DATA_SEC, N_FLASH, LIBNAME)\ - { NAME, ARCH, MACRO, SP8, ERR_SKIP, DATA_SEC, N_FLASH, LIBNAME }, +#define AVR_MCU(NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, N_FLASH, LIBNAME)\ + { NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, N_FLASH, LIBNAME }, #include "avr-mcus.def" #undef AVR_MCU /* End of list. */ - { NULL, ARCH_UNKNOWN, NULL, 0, 0, 0, 0, NULL } + { NULL, ARCH_UNKNOWN, AVR_ISA_NONE, NULL, 0, 0, NULL } }; diff --git a/gcc-4.9/gcc/config/avr/avr-mcus.def b/gcc-4.9/gcc/config/avr/avr-mcus.def index d068f5e80..3cf2fcd41 100644 --- a/gcc-4.9/gcc/config/avr/avr-mcus.def +++ b/gcc-4.9/gcc/config/avr/avr-mcus.def @@ -33,291 +33,288 @@ Before including this file, define a macro: - AVR_MCU (NAME, ARCH, MACRO, SHORT_SP, ERRATA_SKIP, DATA_SEC, N_FLASH, - LIBRARY_NAME) + AVR_MCU (NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, N_FLASH, LIBRARY_NAME) where the arguments are the fields of avr_mcu_t: - NAME Accept -mmcu=<NAME> + NAME Accept -mmcu=<NAME> - ARCH Specifies the multilib variant together with SHORT_SP + ARCH Specifies the multilib variant together with SHORT_SP - MACRO If NULL, this is a core and not a device. If non-NULL, - supply respective built-in macro. + DEV_ATTRIBUTE Specifies the device specific features + - additional ISA, short SP, errata skip etc., - SHORT_SP The device / multilib has an 8-bit stack pointer (no SPH). + MACRO If NULL, this is a core and not a device. If non-NULL, + supply respective built-in macro. - ERRATA_SKIP Apply work-around for the "skip 32-bit instruction" - silicon bug: Don't skip 32-bit instrctions. + DATA_SEC First address of SRAM, used in -Tdata= by the driver. - DATA_SEC First address of SRAM, used in -Tdata= by the driver. + N_FLASH Number of 64 KiB flash segments, rounded up. - N_FLASH Number of 64 KiB flash segments, rounded up. - - LIBRARY_NAME Used by the driver to linke startup code from avr-libc - as of crt<LIBRARY_NAME>.o + LIBRARY_NAME Used by the driver to linke startup code from avr-libc + as of crt<LIBRARY_NAME>.o "avr2" must be first for the "0" default to work as intended. */ /* Classic, <= 8K. */ -AVR_MCU ("avr2", ARCH_AVR2, NULL, 0, 1, 0x0060, 6, "s8515") -AVR_MCU ("at90s2313", ARCH_AVR2, "__AVR_AT90S2313__", 1, 0, 0x0060, 1, "s2313") -AVR_MCU ("at90s2323", ARCH_AVR2, "__AVR_AT90S2323__", 1, 0, 0x0060, 1, "s2323") -AVR_MCU ("at90s2333", ARCH_AVR2, "__AVR_AT90S2333__", 1, 0, 0x0060, 1, "s2333") -AVR_MCU ("at90s2343", ARCH_AVR2, "__AVR_AT90S2343__", 1, 0, 0x0060, 1, "s2343") -AVR_MCU ("attiny22", ARCH_AVR2, "__AVR_ATtiny22__", 1, 0, 0x0060, 1, "tn22") -AVR_MCU ("attiny26", ARCH_AVR2, "__AVR_ATtiny26__", 1, 0, 0x0060, 1, "tn26") -AVR_MCU ("at90s4414", ARCH_AVR2, "__AVR_AT90S4414__", 0, 0, 0x0060, 1, "s4414") -AVR_MCU ("at90s4433", ARCH_AVR2, "__AVR_AT90S4433__", 1, 0, 0x0060, 1, "s4433") -AVR_MCU ("at90s4434", ARCH_AVR2, "__AVR_AT90S4434__", 0, 0, 0x0060, 1, "s4434") -AVR_MCU ("at90s8515", ARCH_AVR2, "__AVR_AT90S8515__", 0, 1, 0x0060, 1, "s8515") -AVR_MCU ("at90c8534", ARCH_AVR2, "__AVR_AT90C8534__", 0, 0, 0x0060, 1, "c8534") -AVR_MCU ("at90s8535", ARCH_AVR2, "__AVR_AT90S8535__", 0, 0, 0x0060, 1, "s8535") +AVR_MCU ("avr2", ARCH_AVR2, AVR_ERRATA_SKIP, NULL, 0x0060, 6, "s8515") +AVR_MCU ("at90s2313", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2313__", 0x0060, 1, "s2313") +AVR_MCU ("at90s2323", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2323__", 0x0060, 1, "s2323") +AVR_MCU ("at90s2333", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2333__", 0x0060, 1, "s2333") +AVR_MCU ("at90s2343", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2343__", 0x0060, 1, "s2343") +AVR_MCU ("attiny22", ARCH_AVR2, AVR_SHORT_SP, "__AVR_ATtiny22__", 0x0060, 1, "tn22") +AVR_MCU ("attiny26", ARCH_AVR2, AVR_SHORT_SP, "__AVR_ATtiny26__", 0x0060, 1, "tn26") +AVR_MCU ("at90s4414", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90S4414__", 0x0060, 1, "s4414") +AVR_MCU ("at90s4433", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S4433__", 0x0060, 1, "s4433") +AVR_MCU ("at90s4434", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90S4434__", 0x0060, 1, "s4434") +AVR_MCU ("at90s8515", ARCH_AVR2, AVR_ERRATA_SKIP, "__AVR_AT90S8515__", 0x0060, 1, "s8515") +AVR_MCU ("at90c8534", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90C8534__", 0x0060, 1, "c8534") +AVR_MCU ("at90s8535", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90S8535__", 0x0060, 1, "s8535") /* Classic + MOVW, <= 8K. */ -AVR_MCU ("avr25", ARCH_AVR25, NULL, 0, 0, 0x0060, 1, "tn85") -AVR_MCU ("ata6289", ARCH_AVR25, "__AVR_ATA6289__", 0, 0, 0x0100, 1, "a6289") -AVR_MCU ("ata5272", ARCH_AVR25, "__AVR_ATA5272__", 0, 0, 0x0100, 1, "a5272") -AVR_MCU ("attiny13", ARCH_AVR25, "__AVR_ATtiny13__", 1, 0, 0x0060, 1, "tn13") -AVR_MCU ("attiny13a", ARCH_AVR25, "__AVR_ATtiny13A__", 1, 0, 0x0060, 1, "tn13a") -AVR_MCU ("attiny2313", ARCH_AVR25, "__AVR_ATtiny2313__", 1, 0, 0x0060, 1, "tn2313") -AVR_MCU ("attiny2313a", ARCH_AVR25, "__AVR_ATtiny2313A__", 1, 0, 0x0060, 1, "tn2313a") -AVR_MCU ("attiny24", ARCH_AVR25, "__AVR_ATtiny24__", 1, 0, 0x0060, 1, "tn24") -AVR_MCU ("attiny24a", ARCH_AVR25, "__AVR_ATtiny24A__", 1, 0, 0x0060, 1, "tn24a") -AVR_MCU ("attiny4313", ARCH_AVR25, "__AVR_ATtiny4313__", 0, 0, 0x0060, 1, "tn4313") -AVR_MCU ("attiny44", ARCH_AVR25, "__AVR_ATtiny44__", 0, 0, 0x0060, 1, "tn44") -AVR_MCU ("attiny44a", ARCH_AVR25, "__AVR_ATtiny44A__", 0, 0, 0x0060, 1, "tn44a") -AVR_MCU ("attiny84", ARCH_AVR25, "__AVR_ATtiny84__", 0, 0, 0x0060, 1, "tn84") -AVR_MCU ("attiny84a", ARCH_AVR25, "__AVR_ATtiny84A__", 0, 0, 0x0060, 1, "tn84") -AVR_MCU ("attiny25", ARCH_AVR25, "__AVR_ATtiny25__", 1, 0, 0x0060, 1, "tn25") -AVR_MCU ("attiny45", ARCH_AVR25, "__AVR_ATtiny45__", 0, 0, 0x0060, 1, "tn45") -AVR_MCU ("attiny85", ARCH_AVR25, "__AVR_ATtiny85__", 0, 0, 0x0060, 1, "tn85") -AVR_MCU ("attiny261", ARCH_AVR25, "__AVR_ATtiny261__", 1, 0, 0x0060, 1, "tn261") -AVR_MCU ("attiny261a", ARCH_AVR25, "__AVR_ATtiny261A__", 1, 0, 0x0060, 1, "tn261a") -AVR_MCU ("attiny461", ARCH_AVR25, "__AVR_ATtiny461__", 0, 0, 0x0060, 1, "tn461") -AVR_MCU ("attiny461a", ARCH_AVR25, "__AVR_ATtiny461A__", 0, 0, 0x0060, 1, "tn461a") -AVR_MCU ("attiny861", ARCH_AVR25, "__AVR_ATtiny861__", 0, 0, 0x0060, 1, "tn861") -AVR_MCU ("attiny861a", ARCH_AVR25, "__AVR_ATtiny861A__", 0, 0, 0x0060, 1, "tn861a") -AVR_MCU ("attiny43u", ARCH_AVR25, "__AVR_ATtiny43U__", 0, 0, 0x0060, 1, "tn43u") -AVR_MCU ("attiny87", ARCH_AVR25, "__AVR_ATtiny87__", 0, 0, 0x0100, 1, "tn87") -AVR_MCU ("attiny48", ARCH_AVR25, "__AVR_ATtiny48__", 0, 0, 0x0100, 1, "tn48") -AVR_MCU ("attiny88", ARCH_AVR25, "__AVR_ATtiny88__", 0, 0, 0x0100, 1, "tn88") -AVR_MCU ("at86rf401", ARCH_AVR25, "__AVR_AT86RF401__", 0, 0, 0x0060, 1, "86401") +AVR_MCU ("avr25", ARCH_AVR25, AVR_ISA_NONE, NULL, 0x0060, 1, "tn85") +AVR_MCU ("ata6289", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATA6289__", 0x0100, 1, "a6289") +AVR_MCU ("ata5272", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATA5272__", 0x0100, 1, "a5272") +AVR_MCU ("attiny13", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny13__", 0x0060, 1, "tn13") +AVR_MCU ("attiny13a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny13A__", 0x0060, 1, "tn13a") +AVR_MCU ("attiny2313", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny2313__", 0x0060, 1, "tn2313") +AVR_MCU ("attiny2313a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny2313A__", 0x0060, 1, "tn2313a") +AVR_MCU ("attiny24", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny24__", 0x0060, 1, "tn24") +AVR_MCU ("attiny24a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny24A__", 0x0060, 1, "tn24a") +AVR_MCU ("attiny4313", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny4313__", 0x0060, 1, "tn4313") +AVR_MCU ("attiny44", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny44__", 0x0060, 1, "tn44") +AVR_MCU ("attiny44a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny44A__", 0x0060, 1, "tn44a") +AVR_MCU ("attiny84", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny84__", 0x0060, 1, "tn84") +AVR_MCU ("attiny84a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny84A__", 0x0060, 1, "tn84") +AVR_MCU ("attiny25", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny25__", 0x0060, 1, "tn25") +AVR_MCU ("attiny45", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny45__", 0x0060, 1, "tn45") +AVR_MCU ("attiny85", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny85__", 0x0060, 1, "tn85") +AVR_MCU ("attiny261", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny261__", 0x0060, 1, "tn261") +AVR_MCU ("attiny261a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny261A__", 0x0060, 1, "tn261a") +AVR_MCU ("attiny461", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny461__", 0x0060, 1, "tn461") +AVR_MCU ("attiny461a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny461A__", 0x0060, 1, "tn461a") +AVR_MCU ("attiny861", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny861__", 0x0060, 1, "tn861") +AVR_MCU ("attiny861a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny861A__", 0x0060, 1, "tn861a") +AVR_MCU ("attiny43u", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny43U__", 0x0060, 1, "tn43u") +AVR_MCU ("attiny87", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny87__", 0x0100, 1, "tn87") +AVR_MCU ("attiny48", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny48__", 0x0100, 1, "tn48") +AVR_MCU ("attiny88", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny88__", 0x0100, 1, "tn88") +AVR_MCU ("at86rf401", ARCH_AVR25, AVR_ISA_NONE, "__AVR_AT86RF401__", 0x0060, 1, "86401") /* Classic, > 8K, <= 64K. */ -AVR_MCU ("avr3", ARCH_AVR3, NULL, 0, 0, 0x0060, 1, "43355") -AVR_MCU ("at43usb355", ARCH_AVR3, "__AVR_AT43USB355__", 0, 0, 0x0060, 1, "43355") -AVR_MCU ("at76c711", ARCH_AVR3, "__AVR_AT76C711__", 0, 0, 0x0060, 1, "76711") +AVR_MCU ("avr3", ARCH_AVR3, AVR_ISA_NONE, NULL, 0x0060, 1, "43355") +AVR_MCU ("at43usb355", ARCH_AVR3, AVR_ISA_NONE, "__AVR_AT43USB355__", 0x0060, 1, "43355") +AVR_MCU ("at76c711", ARCH_AVR3, AVR_ISA_NONE, "__AVR_AT76C711__", 0x0060, 1, "76711") /* Classic, == 128K. */ -AVR_MCU ("avr31", ARCH_AVR31, NULL, 0, 1, 0x0060, 2, "m103") -AVR_MCU ("atmega103", ARCH_AVR31, "__AVR_ATmega103__", 0, 1, 0x0060, 2, "m103") -AVR_MCU ("at43usb320", ARCH_AVR31, "__AVR_AT43USB320__", 0, 0, 0x0060, 2, "43320") +AVR_MCU ("avr31", ARCH_AVR31, AVR_ERRATA_SKIP, NULL, 0x0060, 2, "m103") +AVR_MCU ("atmega103", ARCH_AVR31, AVR_ERRATA_SKIP, "__AVR_ATmega103__", 0x0060, 2, "m103") +AVR_MCU ("at43usb320", ARCH_AVR31, AVR_ISA_NONE, "__AVR_AT43USB320__", 0x0060, 2, "43320") /* Classic + MOVW + JMP/CALL. */ -AVR_MCU ("avr35", ARCH_AVR35, NULL, 0, 0, 0x0100, 1, "usb162") -AVR_MCU ("ata5505", ARCH_AVR35, "__AVR_ATA5505__", 0, 0, 0x0100, 1, "a5505") -AVR_MCU ("at90usb82", ARCH_AVR35, "__AVR_AT90USB82__", 0, 0, 0x0100, 1, "usb82") -AVR_MCU ("at90usb162", ARCH_AVR35, "__AVR_AT90USB162__", 0, 0, 0x0100, 1, "usb162") -AVR_MCU ("atmega8u2", ARCH_AVR35, "__AVR_ATmega8U2__", 0, 0, 0x0100, 1, "m8u2") -AVR_MCU ("atmega16u2", ARCH_AVR35, "__AVR_ATmega16U2__", 0, 0, 0x0100, 1, "m16u2") -AVR_MCU ("atmega32u2", ARCH_AVR35, "__AVR_ATmega32U2__", 0, 0, 0x0100, 1, "m32u2") -AVR_MCU ("attiny167", ARCH_AVR35, "__AVR_ATtiny167__", 0, 0, 0x0100, 1, "tn167") -AVR_MCU ("attiny1634", ARCH_AVR35, "__AVR_ATtiny1634__", 0, 0, 0x0100, 1, "tn1634") +AVR_MCU ("avr35", ARCH_AVR35, AVR_ISA_NONE, NULL, 0x0100, 1, "usb162") +AVR_MCU ("ata5505", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATA5505__", 0x0100, 1, "a5505") +AVR_MCU ("at90usb82", ARCH_AVR35, AVR_ISA_NONE, "__AVR_AT90USB82__", 0x0100, 1, "usb82") +AVR_MCU ("at90usb162", ARCH_AVR35, AVR_ISA_NONE, "__AVR_AT90USB162__", 0x0100, 1, "usb162") +AVR_MCU ("atmega8u2", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATmega8U2__", 0x0100, 1, "m8u2") +AVR_MCU ("atmega16u2", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATmega16U2__", 0x0100, 1, "m16u2") +AVR_MCU ("atmega32u2", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATmega32U2__", 0x0100, 1, "m32u2") +AVR_MCU ("attiny167", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATtiny167__", 0x0100, 1, "tn167") +AVR_MCU ("attiny1634", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATtiny1634__", 0x0100, 1, "tn1634") /* Enhanced, <= 8K. */ -AVR_MCU ("avr4", ARCH_AVR4, NULL, 0, 0, 0x0060, 1, "m8") -AVR_MCU ("ata6285", ARCH_AVR4, "__AVR_ATA6285__", 0, 0, 0x0100, 1, "a6285") -AVR_MCU ("ata6286", ARCH_AVR4, "__AVR_ATA6286__", 0, 0, 0x0100, 1, "a6286") -AVR_MCU ("atmega8", ARCH_AVR4, "__AVR_ATmega8__", 0, 0, 0x0060, 1, "m8") -AVR_MCU ("atmega8a", ARCH_AVR4, "__AVR_ATmega8A__", 0, 0, 0x0060, 1, "m8a") -AVR_MCU ("atmega48", ARCH_AVR4, "__AVR_ATmega48__", 0, 0, 0x0100, 1, "m48") -AVR_MCU ("atmega48a", ARCH_AVR4, "__AVR_ATmega48A__", 0, 0, 0x0100, 1, "m48a") -AVR_MCU ("atmega48p", ARCH_AVR4, "__AVR_ATmega48P__", 0, 0, 0x0100, 1, "m48p") -AVR_MCU ("atmega48pa", ARCH_AVR4, "__AVR_ATmega48PA__", 0, 0, 0x0100, 1, "m48pa") -AVR_MCU ("atmega88", ARCH_AVR4, "__AVR_ATmega88__", 0, 0, 0x0100, 1, "m88") -AVR_MCU ("atmega88a", ARCH_AVR4, "__AVR_ATmega88A__", 0, 0, 0x0100, 1, "m88a") -AVR_MCU ("atmega88p", ARCH_AVR4, "__AVR_ATmega88P__", 0, 0, 0x0100, 1, "m88p") -AVR_MCU ("atmega88pa", ARCH_AVR4, "__AVR_ATmega88PA__", 0, 0, 0x0100, 1, "m88pa") -AVR_MCU ("atmega8515", ARCH_AVR4, "__AVR_ATmega8515__", 0, 0, 0x0060, 1, "m8515") -AVR_MCU ("atmega8535", ARCH_AVR4, "__AVR_ATmega8535__", 0, 0, 0x0060, 1, "m8535") -AVR_MCU ("atmega8hva", ARCH_AVR4, "__AVR_ATmega8HVA__", 0, 0, 0x0100, 1, "m8hva") -AVR_MCU ("at90pwm1", ARCH_AVR4, "__AVR_AT90PWM1__", 0, 0, 0x0100, 1, "90pwm1") -AVR_MCU ("at90pwm2", ARCH_AVR4, "__AVR_AT90PWM2__", 0, 0, 0x0100, 1, "90pwm2") -AVR_MCU ("at90pwm2b", ARCH_AVR4, "__AVR_AT90PWM2B__", 0, 0, 0x0100, 1, "90pwm2b") -AVR_MCU ("at90pwm3", ARCH_AVR4, "__AVR_AT90PWM3__", 0, 0, 0x0100, 1, "90pwm3") -AVR_MCU ("at90pwm3b", ARCH_AVR4, "__AVR_AT90PWM3B__", 0, 0, 0x0100, 1, "90pwm3b") -AVR_MCU ("at90pwm81", ARCH_AVR4, "__AVR_AT90PWM81__", 0, 0, 0x0100, 1, "90pwm81") +AVR_MCU ("avr4", ARCH_AVR4, AVR_ISA_NONE, NULL, 0x0060, 1, "m8") +AVR_MCU ("ata6285", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATA6285__", 0x0100, 1, "a6285") +AVR_MCU ("ata6286", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATA6286__", 0x0100, 1, "a6286") +AVR_MCU ("atmega8", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8__", 0x0060, 1, "m8") +AVR_MCU ("atmega8a", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8A__", 0x0060, 1, "m8a") +AVR_MCU ("atmega48", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48__", 0x0100, 1, "m48") +AVR_MCU ("atmega48a", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48A__", 0x0100, 1, "m48a") +AVR_MCU ("atmega48p", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48P__", 0x0100, 1, "m48p") +AVR_MCU ("atmega48pa", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48PA__", 0x0100, 1, "m48pa") +AVR_MCU ("atmega88", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88__", 0x0100, 1, "m88") +AVR_MCU ("atmega88a", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88A__", 0x0100, 1, "m88a") +AVR_MCU ("atmega88p", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88P__", 0x0100, 1, "m88p") +AVR_MCU ("atmega88pa", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88PA__", 0x0100, 1, "m88pa") +AVR_MCU ("atmega8515", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8515__", 0x0060, 1, "m8515") +AVR_MCU ("atmega8535", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8535__", 0x0060, 1, "m8535") +AVR_MCU ("atmega8hva", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8HVA__", 0x0100, 1, "m8hva") +AVR_MCU ("at90pwm1", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM1__", 0x0100, 1, "90pwm1") +AVR_MCU ("at90pwm2", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM2__", 0x0100, 1, "90pwm2") +AVR_MCU ("at90pwm2b", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM2B__", 0x0100, 1, "90pwm2b") +AVR_MCU ("at90pwm3", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM3__", 0x0100, 1, "90pwm3") +AVR_MCU ("at90pwm3b", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM3B__", 0x0100, 1, "90pwm3b") +AVR_MCU ("at90pwm81", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM81__", 0x0100, 1, "90pwm81") /* Enhanced, > 8K, <= 64K. */ -AVR_MCU ("avr5", ARCH_AVR5, NULL, 0, 0, 0x0060, 1, "m16") -AVR_MCU ("ata5790", ARCH_AVR5, "__AVR_ATA5790__", 0, 0, 0x0100, 1, "a5790") -AVR_MCU ("ata5790n", ARCH_AVR5, "__AVR_ATA5790N__", 0, 0, 0x0100, 1, "a5790n") -AVR_MCU ("ata5795", ARCH_AVR5, "__AVR_ATA5795__", 0, 0, 0x0100, 1, "a5795") -AVR_MCU ("atmega16", ARCH_AVR5, "__AVR_ATmega16__", 0, 0, 0x0060, 1, "m16") -AVR_MCU ("atmega16a", ARCH_AVR5, "__AVR_ATmega16A__", 0, 0, 0x0060, 1, "m16a") -AVR_MCU ("atmega161", ARCH_AVR5, "__AVR_ATmega161__", 0, 0, 0x0060, 1, "m161") -AVR_MCU ("atmega162", ARCH_AVR5, "__AVR_ATmega162__", 0, 0, 0x0100, 1, "m162") -AVR_MCU ("atmega163", ARCH_AVR5, "__AVR_ATmega163__", 0, 0, 0x0060, 1, "m163") -AVR_MCU ("atmega164a", ARCH_AVR5, "__AVR_ATmega164A__", 0, 0, 0x0100, 1, "m164a") -AVR_MCU ("atmega164p", ARCH_AVR5, "__AVR_ATmega164P__", 0, 0, 0x0100, 1, "m164p") -AVR_MCU ("atmega164pa", ARCH_AVR5, "__AVR_ATmega164PA__", 0, 0, 0x0100, 1, "m164pa") -AVR_MCU ("atmega165", ARCH_AVR5, "__AVR_ATmega165__", 0, 0, 0x0100, 1, "m165") -AVR_MCU ("atmega165a", ARCH_AVR5, "__AVR_ATmega165A__", 0, 0, 0x0100, 1, "m165a") -AVR_MCU ("atmega165p", ARCH_AVR5, "__AVR_ATmega165P__", 0, 0, 0x0100, 1, "m165p") -AVR_MCU ("atmega165pa", ARCH_AVR5, "__AVR_ATmega165PA__", 0, 0, 0x0100, 1, "m165pa") -AVR_MCU ("atmega168", ARCH_AVR5, "__AVR_ATmega168__", 0, 0, 0x0100, 1, "m168") -AVR_MCU ("atmega168a", ARCH_AVR5, "__AVR_ATmega168A__", 0, 0, 0x0100, 1, "m168a") -AVR_MCU ("atmega168p", ARCH_AVR5, "__AVR_ATmega168P__", 0, 0, 0x0100, 1, "m168p") -AVR_MCU ("atmega168pa", ARCH_AVR5, "__AVR_ATmega168PA__", 0, 0, 0x0100, 1, "m168pa") -AVR_MCU ("atmega169", ARCH_AVR5, "__AVR_ATmega169__", 0, 0, 0x0100, 1, "m169") -AVR_MCU ("atmega169a", ARCH_AVR5, "__AVR_ATmega169A__", 0, 0, 0x0100, 1, "m169a") -AVR_MCU ("atmega169p", ARCH_AVR5, "__AVR_ATmega169P__", 0, 0, 0x0100, 1, "m169p") -AVR_MCU ("atmega169pa", ARCH_AVR5, "__AVR_ATmega169PA__", 0, 0, 0x0100, 1, "m169pa") -AVR_MCU ("atmega16hvb", ARCH_AVR5, "__AVR_ATmega16HVB__", 0, 0, 0x0100, 1, "m16hvb") -AVR_MCU ("atmega16hvbrevb", ARCH_AVR5, "__AVR_ATmega16HVBREVB__", 0, 0, 0x0100, 1, "m16hvbrevb") -AVR_MCU ("atmega16m1", ARCH_AVR5, "__AVR_ATmega16M1__", 0, 0, 0x0100, 1, "m16m1") -AVR_MCU ("atmega16u4", ARCH_AVR5, "__AVR_ATmega16U4__", 0, 0, 0x0100, 1, "m16u4") -AVR_MCU ("atmega26hvg", ARCH_AVR5, "__AVR_ATmega26HVG__", 0, 0, 0x0100, 1, "m26hvg") -AVR_MCU ("atmega32a", ARCH_AVR5, "__AVR_ATmega32A__", 0, 0, 0x0060, 1, "m32a") -AVR_MCU ("atmega32", ARCH_AVR5, "__AVR_ATmega32__", 0, 0, 0x0060, 1, "m32") -AVR_MCU ("atmega323", ARCH_AVR5, "__AVR_ATmega323__", 0, 0, 0x0060, 1, "m323") -AVR_MCU ("atmega324a", ARCH_AVR5, "__AVR_ATmega324A__", 0, 0, 0x0100, 1, "m324a") -AVR_MCU ("atmega324p", ARCH_AVR5, "__AVR_ATmega324P__", 0, 0, 0x0100, 1, "m324p") -AVR_MCU ("atmega324pa", ARCH_AVR5, "__AVR_ATmega324PA__", 0, 0, 0x0100, 1, "m324pa") -AVR_MCU ("atmega325", ARCH_AVR5, "__AVR_ATmega325__", 0, 0, 0x0100, 1, "m325") -AVR_MCU ("atmega325a", ARCH_AVR5, "__AVR_ATmega325A__", 0, 0, 0x0100, 1, "m325a") -AVR_MCU ("atmega325p", ARCH_AVR5, "__AVR_ATmega325P__", 0, 0, 0x0100, 1, "m325p") -AVR_MCU ("atmega3250", ARCH_AVR5, "__AVR_ATmega3250__", 0, 0, 0x0100, 1, "m3250") -AVR_MCU ("atmega3250a", ARCH_AVR5, "__AVR_ATmega3250A__", 0, 0, 0x0100, 1, "m3250a") -AVR_MCU ("atmega3250p", ARCH_AVR5, "__AVR_ATmega3250P__", 0, 0, 0x0100, 1, "m3250p") -AVR_MCU ("atmega3250pa", ARCH_AVR5, "__AVR_ATmega3250PA__", 0, 0, 0x0100, 1, "m3250pa") -AVR_MCU ("atmega328", ARCH_AVR5, "__AVR_ATmega328__", 0, 0, 0x0100, 1, "m328") -AVR_MCU ("atmega328p", ARCH_AVR5, "__AVR_ATmega328P__", 0, 0, 0x0100, 1, "m328p") -AVR_MCU ("atmega329", ARCH_AVR5, "__AVR_ATmega329__", 0, 0, 0x0100, 1, "m329") -AVR_MCU ("atmega329a", ARCH_AVR5, "__AVR_ATmega329A__", 0, 0, 0x0100, 1, "m329a") -AVR_MCU ("atmega329p", ARCH_AVR5, "__AVR_ATmega329P__", 0, 0, 0x0100, 1, "m329p") -AVR_MCU ("atmega329pa", ARCH_AVR5, "__AVR_ATmega329PA__", 0, 0, 0x0100, 1, "m329pa") -AVR_MCU ("atmega3290", ARCH_AVR5, "__AVR_ATmega3290__", 0, 0, 0x0100, 1, "m3290") -AVR_MCU ("atmega3290a", ARCH_AVR5, "__AVR_ATmega3290A__", 0, 0, 0x0100, 1, "m3290a") -AVR_MCU ("atmega3290p", ARCH_AVR5, "__AVR_ATmega3290P__", 0, 0, 0x0100, 1, "m3290p") -AVR_MCU ("atmega3290pa", ARCH_AVR5, "__AVR_ATmega3290PA__", 0, 0, 0x0100, 1, "m3290pa") -AVR_MCU ("atmega32c1", ARCH_AVR5, "__AVR_ATmega32C1__", 0, 0, 0x0100, 1, "m32c1") -AVR_MCU ("atmega32m1", ARCH_AVR5, "__AVR_ATmega32M1__", 0, 0, 0x0100, 1, "m32m1") -AVR_MCU ("atmega32u4", ARCH_AVR5, "__AVR_ATmega32U4__", 0, 0, 0x0100, 1, "m32u4") -AVR_MCU ("atmega32u6", ARCH_AVR5, "__AVR_ATmega32U6__", 0, 0, 0x0100, 1, "m32u6") -AVR_MCU ("atmega406", ARCH_AVR5, "__AVR_ATmega406__", 0, 0, 0x0100, 1, "m406") -AVR_MCU ("atmega64", ARCH_AVR5, "__AVR_ATmega64__", 0, 0, 0x0100, 1, "m64") -AVR_MCU ("atmega64a", ARCH_AVR5, "__AVR_ATmega64A__", 0, 0, 0x0100, 1, "m64a") -AVR_MCU ("atmega640", ARCH_AVR5, "__AVR_ATmega640__", 0, 0, 0x0200, 1, "m640") -AVR_MCU ("atmega644", ARCH_AVR5, "__AVR_ATmega644__", 0, 0, 0x0100, 1, "m644") -AVR_MCU ("atmega644a", ARCH_AVR5, "__AVR_ATmega644A__", 0, 0, 0x0100, 1, "m644a") -AVR_MCU ("atmega644p", ARCH_AVR5, "__AVR_ATmega644P__", 0, 0, 0x0100, 1, "m644p") -AVR_MCU ("atmega644pa", ARCH_AVR5, "__AVR_ATmega644PA__", 0, 0, 0x0100, 1, "m644pa") -AVR_MCU ("atmega645", ARCH_AVR5, "__AVR_ATmega645__", 0, 0, 0x0100, 1, "m645") -AVR_MCU ("atmega645a", ARCH_AVR5, "__AVR_ATmega645A__", 0, 0, 0x0100, 1, "m645a") -AVR_MCU ("atmega645p", ARCH_AVR5, "__AVR_ATmega645P__", 0, 0, 0x0100, 1, "m645p") -AVR_MCU ("atmega6450", ARCH_AVR5, "__AVR_ATmega6450__", 0, 0, 0x0100, 1, "m6450") -AVR_MCU ("atmega6450a", ARCH_AVR5, "__AVR_ATmega6450A__", 0, 0, 0x0100, 1, "m6450a") -AVR_MCU ("atmega6450p", ARCH_AVR5, "__AVR_ATmega6450P__", 0, 0, 0x0100, 1, "m6450p") -AVR_MCU ("atmega649", ARCH_AVR5, "__AVR_ATmega649__", 0, 0, 0x0100, 1, "m649") -AVR_MCU ("atmega649a", ARCH_AVR5, "__AVR_ATmega649A__", 0, 0, 0x0100, 1, "m649a") -AVR_MCU ("atmega649p", ARCH_AVR5, "__AVR_ATmega649P__", 0, 0, 0x0100, 1, "m649p") -AVR_MCU ("atmega6490", ARCH_AVR5, "__AVR_ATmega6490__", 0, 0, 0x0100, 1, "m6490") -AVR_MCU ("atmega16hva", ARCH_AVR5, "__AVR_ATmega16HVA__", 0, 0, 0x0100, 1, "m16hva") -AVR_MCU ("atmega16hva2", ARCH_AVR5, "__AVR_ATmega16HVA2__", 0, 0, 0x0100, 1, "m16hva2") -AVR_MCU ("atmega32hvb", ARCH_AVR5, "__AVR_ATmega32HVB__", 0, 0, 0x0100, 1, "m32hvb") -AVR_MCU ("atmega6490a", ARCH_AVR5, "__AVR_ATmega6490A__", 0, 0, 0x0100, 1, "m6490a") -AVR_MCU ("atmega6490p", ARCH_AVR5, "__AVR_ATmega6490P__", 0, 0, 0x0100, 1, "m6490p") -AVR_MCU ("atmega64c1", ARCH_AVR5, "__AVR_ATmega64C1__", 0, 0, 0x0100, 1, "m64c1") -AVR_MCU ("atmega64m1", ARCH_AVR5, "__AVR_ATmega64M1__", 0, 0, 0x0100, 1, "m64m1") -AVR_MCU ("atmega64hve", ARCH_AVR5, "__AVR_ATmega64HVE__", 0, 0, 0x0100, 1, "m64hve") -AVR_MCU ("atmega64rfa2", ARCH_AVR5, "__AVR_ATmega64RFA2__", 0, 0, 0x0200, 1, "m64rfa2") -AVR_MCU ("atmega64rfr2", ARCH_AVR5, "__AVR_ATmega64RFR2__", 0, 0, 0x0200, 1, "m64rfr2") -AVR_MCU ("atmega32hvbrevb", ARCH_AVR5, "__AVR_ATmega32HVBREVB__", 0, 0, 0x0100, 1, "m32hvbrevb") -AVR_MCU ("atmega48hvf", ARCH_AVR5, "__AVR_ATmega48HVF__", 0, 0, 0x0100, 1, "m48hvf") -AVR_MCU ("at90can32", ARCH_AVR5, "__AVR_AT90CAN32__", 0, 0, 0x0100, 1, "can32") -AVR_MCU ("at90can64", ARCH_AVR5, "__AVR_AT90CAN64__", 0, 0, 0x0100, 1, "can64") -AVR_MCU ("at90pwm161", ARCH_AVR5, "__AVR_AT90PWM161__", 0, 0, 0x0100, 1, "90pwm161") -AVR_MCU ("at90pwm216", ARCH_AVR5, "__AVR_AT90PWM216__", 0, 0, 0x0100, 1, "90pwm216") -AVR_MCU ("at90pwm316", ARCH_AVR5, "__AVR_AT90PWM316__", 0, 0, 0x0100, 1, "90pwm316") -AVR_MCU ("at90scr100", ARCH_AVR5, "__AVR_AT90SCR100__", 0, 0, 0x0100, 1, "90scr100") -AVR_MCU ("at90usb646", ARCH_AVR5, "__AVR_AT90USB646__", 0, 0, 0x0100, 1, "usb646") -AVR_MCU ("at90usb647", ARCH_AVR5, "__AVR_AT90USB647__", 0, 0, 0x0100, 1, "usb647") -AVR_MCU ("at94k", ARCH_AVR5, "__AVR_AT94K__", 0, 0, 0x0060, 1, "at94k") -AVR_MCU ("m3000", ARCH_AVR5, "__AVR_M3000__", 0, 0, 0x1000, 1, "m3000") +AVR_MCU ("avr5", ARCH_AVR5, AVR_ISA_NONE, NULL, 0x0060, 1, "m16") +AVR_MCU ("ata5790", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5790__", 0x0100, 1, "a5790") +AVR_MCU ("ata5790n", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5790N__", 0x0100, 1, "a5790n") +AVR_MCU ("ata5795", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5795__", 0x0100, 1, "a5795") +AVR_MCU ("atmega16", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16__", 0x0060, 1, "m16") +AVR_MCU ("atmega16a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16A__", 0x0060, 1, "m16a") +AVR_MCU ("atmega161", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega161__", 0x0060, 1, "m161") +AVR_MCU ("atmega162", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega162__", 0x0100, 1, "m162") +AVR_MCU ("atmega163", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega163__", 0x0060, 1, "m163") +AVR_MCU ("atmega164a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega164A__", 0x0100, 1, "m164a") +AVR_MCU ("atmega164p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega164P__", 0x0100, 1, "m164p") +AVR_MCU ("atmega164pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega164PA__", 0x0100, 1, "m164pa") +AVR_MCU ("atmega165", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165__", 0x0100, 1, "m165") +AVR_MCU ("atmega165a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165A__", 0x0100, 1, "m165a") +AVR_MCU ("atmega165p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165P__", 0x0100, 1, "m165p") +AVR_MCU ("atmega165pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165PA__", 0x0100, 1, "m165pa") +AVR_MCU ("atmega168", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168__", 0x0100, 1, "m168") +AVR_MCU ("atmega168a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168A__", 0x0100, 1, "m168a") +AVR_MCU ("atmega168p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168P__", 0x0100, 1, "m168p") +AVR_MCU ("atmega168pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168PA__", 0x0100, 1, "m168pa") +AVR_MCU ("atmega169", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169__", 0x0100, 1, "m169") +AVR_MCU ("atmega169a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169A__", 0x0100, 1, "m169a") +AVR_MCU ("atmega169p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169P__", 0x0100, 1, "m169p") +AVR_MCU ("atmega169pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169PA__", 0x0100, 1, "m169pa") +AVR_MCU ("atmega16hvb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVB__", 0x0100, 1, "m16hvb") +AVR_MCU ("atmega16hvbrevb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVBREVB__", 0x0100, 1, "m16hvbrevb") +AVR_MCU ("atmega16m1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16M1__", 0x0100, 1, "m16m1") +AVR_MCU ("atmega16u4", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16U4__", 0x0100, 1, "m16u4") +AVR_MCU ("atmega26hvg", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega26HVG__", 0x0100, 1, "m26hvg") +AVR_MCU ("atmega32a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32A__", 0x0060, 1, "m32a") +AVR_MCU ("atmega32", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32__", 0x0060, 1, "m32") +AVR_MCU ("atmega323", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega323__", 0x0060, 1, "m323") +AVR_MCU ("atmega324a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega324A__", 0x0100, 1, "m324a") +AVR_MCU ("atmega324p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega324P__", 0x0100, 1, "m324p") +AVR_MCU ("atmega324pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega324PA__", 0x0100, 1, "m324pa") +AVR_MCU ("atmega325", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega325__", 0x0100, 1, "m325") +AVR_MCU ("atmega325a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega325A__", 0x0100, 1, "m325a") +AVR_MCU ("atmega325p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega325P__", 0x0100, 1, "m325p") +AVR_MCU ("atmega3250", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250__", 0x0100, 1, "m3250") +AVR_MCU ("atmega3250a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250A__", 0x0100, 1, "m3250a") +AVR_MCU ("atmega3250p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250P__", 0x0100, 1, "m3250p") +AVR_MCU ("atmega3250pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250PA__", 0x0100, 1, "m3250pa") +AVR_MCU ("atmega328", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega328__", 0x0100, 1, "m328") +AVR_MCU ("atmega328p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega328P__", 0x0100, 1, "m328p") +AVR_MCU ("atmega329", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329__", 0x0100, 1, "m329") +AVR_MCU ("atmega329a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329A__", 0x0100, 1, "m329a") +AVR_MCU ("atmega329p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329P__", 0x0100, 1, "m329p") +AVR_MCU ("atmega329pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329PA__", 0x0100, 1, "m329pa") +AVR_MCU ("atmega3290", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290__", 0x0100, 1, "m3290") +AVR_MCU ("atmega3290a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290A__", 0x0100, 1, "m3290a") +AVR_MCU ("atmega3290p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290P__", 0x0100, 1, "m3290p") +AVR_MCU ("atmega3290pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290PA__", 0x0100, 1, "m3290pa") +AVR_MCU ("atmega32c1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32C1__", 0x0100, 1, "m32c1") +AVR_MCU ("atmega32m1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32M1__", 0x0100, 1, "m32m1") +AVR_MCU ("atmega32u4", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32U4__", 0x0100, 1, "m32u4") +AVR_MCU ("atmega32u6", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32U6__", 0x0100, 1, "m32u6") +AVR_MCU ("atmega406", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega406__", 0x0100, 1, "m406") +AVR_MCU ("atmega64", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64__", 0x0100, 1, "m64") +AVR_MCU ("atmega64a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64A__", 0x0100, 1, "m64a") +AVR_MCU ("atmega640", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega640__", 0x0200, 1, "m640") +AVR_MCU ("atmega644", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644__", 0x0100, 1, "m644") +AVR_MCU ("atmega644a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644A__", 0x0100, 1, "m644a") +AVR_MCU ("atmega644p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644P__", 0x0100, 1, "m644p") +AVR_MCU ("atmega644pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644PA__", 0x0100, 1, "m644pa") +AVR_MCU ("atmega645", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega645__", 0x0100, 1, "m645") +AVR_MCU ("atmega645a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega645A__", 0x0100, 1, "m645a") +AVR_MCU ("atmega645p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega645P__", 0x0100, 1, "m645p") +AVR_MCU ("atmega6450", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6450__", 0x0100, 1, "m6450") +AVR_MCU ("atmega6450a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6450A__", 0x0100, 1, "m6450a") +AVR_MCU ("atmega6450p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6450P__", 0x0100, 1, "m6450p") +AVR_MCU ("atmega649", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega649__", 0x0100, 1, "m649") +AVR_MCU ("atmega649a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega649A__", 0x0100, 1, "m649a") +AVR_MCU ("atmega649p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega649P__", 0x0100, 1, "m649p") +AVR_MCU ("atmega6490", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6490__", 0x0100, 1, "m6490") +AVR_MCU ("atmega16hva", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVA__", 0x0100, 1, "m16hva") +AVR_MCU ("atmega16hva2", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVA2__", 0x0100, 1, "m16hva2") +AVR_MCU ("atmega32hvb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32HVB__", 0x0100, 1, "m32hvb") +AVR_MCU ("atmega6490a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6490A__", 0x0100, 1, "m6490a") +AVR_MCU ("atmega6490p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6490P__", 0x0100, 1, "m6490p") +AVR_MCU ("atmega64c1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64C1__", 0x0100, 1, "m64c1") +AVR_MCU ("atmega64m1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64M1__", 0x0100, 1, "m64m1") +AVR_MCU ("atmega64hve", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64HVE__", 0x0100, 1, "m64hve") +AVR_MCU ("atmega64rfa2", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64RFA2__", 0x0200, 1, "m64rfa2") +AVR_MCU ("atmega64rfr2", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64RFR2__", 0x0200, 1, "m64rfr2") +AVR_MCU ("atmega32hvbrevb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32HVBREVB__", 0x0100, 1, "m32hvbrevb") +AVR_MCU ("atmega48hvf", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega48HVF__", 0x0100, 1, "m48hvf") +AVR_MCU ("at90can32", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90CAN32__", 0x0100, 1, "can32") +AVR_MCU ("at90can64", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90CAN64__", 0x0100, 1, "can64") +AVR_MCU ("at90pwm161", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90PWM161__", 0x0100, 1, "90pwm161") +AVR_MCU ("at90pwm216", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90PWM216__", 0x0100, 1, "90pwm216") +AVR_MCU ("at90pwm316", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90PWM316__", 0x0100, 1, "90pwm316") +AVR_MCU ("at90scr100", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90SCR100__", 0x0100, 1, "90scr100") +AVR_MCU ("at90usb646", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90USB646__", 0x0100, 1, "usb646") +AVR_MCU ("at90usb647", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90USB647__", 0x0100, 1, "usb647") +AVR_MCU ("at94k", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT94K__", 0x0060, 1, "at94k") +AVR_MCU ("m3000", ARCH_AVR5, AVR_ISA_NONE, "__AVR_M3000__", 0x1000, 1, "m3000") /* Enhanced, == 128K. */ -AVR_MCU ("avr51", ARCH_AVR51, NULL, 0, 0, 0x0100, 2, "m128") -AVR_MCU ("atmega128", ARCH_AVR51, "__AVR_ATmega128__", 0, 0, 0x0100, 2, "m128") -AVR_MCU ("atmega128a", ARCH_AVR51, "__AVR_ATmega128A__", 0, 0, 0x0100, 2, "m128a") -AVR_MCU ("atmega1280", ARCH_AVR51, "__AVR_ATmega1280__", 0, 0, 0x0200, 2, "m1280") -AVR_MCU ("atmega1281", ARCH_AVR51, "__AVR_ATmega1281__", 0, 0, 0x0200, 2, "m1281") -AVR_MCU ("atmega1284", ARCH_AVR51, "__AVR_ATmega1284__", 0, 0, 0x0100, 2, "m1284") -AVR_MCU ("atmega1284p", ARCH_AVR51, "__AVR_ATmega1284P__", 0, 0, 0x0100, 2, "m1284p") -AVR_MCU ("atmega128rfa1", ARCH_AVR51, "__AVR_ATmega128RFA1__", 0, 0, 0x0200, 2, "m128rfa1") -AVR_MCU ("at90can128", ARCH_AVR51, "__AVR_AT90CAN128__", 0, 0, 0x0100, 2, "can128") -AVR_MCU ("at90usb1286", ARCH_AVR51, "__AVR_AT90USB1286__", 0, 0, 0x0100, 2, "usb1286") -AVR_MCU ("at90usb1287", ARCH_AVR51, "__AVR_AT90USB1287__", 0, 0, 0x0100, 2, "usb1287") +AVR_MCU ("avr51", ARCH_AVR51, AVR_ISA_NONE, NULL, 0x0100, 2, "m128") +AVR_MCU ("atmega128", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega128__", 0x0100, 2, "m128") +AVR_MCU ("atmega128a", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega128A__", 0x0100, 2, "m128a") +AVR_MCU ("atmega1280", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1280__", 0x0200, 2, "m1280") +AVR_MCU ("atmega1281", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1281__", 0x0200, 2, "m1281") +AVR_MCU ("atmega1284", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1284__", 0x0100, 2, "m1284") +AVR_MCU ("atmega1284p", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1284P__", 0x0100, 2, "m1284p") +AVR_MCU ("atmega128rfa1", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega128RFA1__", 0x0200, 2, "m128rfa1") +AVR_MCU ("at90can128", ARCH_AVR51, AVR_ISA_NONE, "__AVR_AT90CAN128__", 0x0100, 2, "can128") +AVR_MCU ("at90usb1286", ARCH_AVR51, AVR_ISA_NONE, "__AVR_AT90USB1286__", 0x0100, 2, "usb1286") +AVR_MCU ("at90usb1287", ARCH_AVR51, AVR_ISA_NONE, "__AVR_AT90USB1287__", 0x0100, 2, "usb1287") /* 3-Byte PC. */ -AVR_MCU ("avr6", ARCH_AVR6, NULL, 0, 0, 0x0200, 4, "m2561") -AVR_MCU ("atmega2560", ARCH_AVR6, "__AVR_ATmega2560__", 0, 0, 0x0200, 4, "m2560") -AVR_MCU ("atmega2561", ARCH_AVR6, "__AVR_ATmega2561__", 0, 0, 0x0200, 4, "m2561") +AVR_MCU ("avr6", ARCH_AVR6, AVR_ISA_NONE, NULL, 0x0200, 4, "m2561") +AVR_MCU ("atmega2560", ARCH_AVR6, AVR_ISA_NONE, "__AVR_ATmega2560__", 0x0200, 4, "m2560") +AVR_MCU ("atmega2561", ARCH_AVR6, AVR_ISA_NONE, "__AVR_ATmega2561__", 0x0200, 4, "m2561") /* Xmega, 16K <= Flash < 64K, RAM <= 64K */ -AVR_MCU ("avrxmega2", ARCH_AVRXMEGA2, NULL, 0, 0, 0x2000, 1, "x32a4") -AVR_MCU ("atxmega16a4", ARCH_AVRXMEGA2, "__AVR_ATxmega16A4__", 0, 0, 0x2000, 1, "x16a4") -AVR_MCU ("atxmega16d4", ARCH_AVRXMEGA2, "__AVR_ATxmega16D4__", 0, 0, 0x2000, 1, "x16d4") -AVR_MCU ("atxmega32a4", ARCH_AVRXMEGA2, "__AVR_ATxmega32A4__", 0, 0, 0x2000, 1, "x32a4") -AVR_MCU ("atxmega32d4", ARCH_AVRXMEGA2, "__AVR_ATxmega32D4__", 0, 0, 0x2000, 1, "x32d4") -AVR_MCU ("atxmega32x1", ARCH_AVRXMEGA2, "__AVR_ATxmega32X1__", 0, 0, 0x2000, 1, "x32x1") -AVR_MCU ("atmxt112sl", ARCH_AVRXMEGA2, "__AVR_ATMXT112SL__", 0, 0, 0x2000, 1, "mxt112sl") -AVR_MCU ("atmxt224", ARCH_AVRXMEGA2, "__AVR_ATMXT224__", 0, 0, 0x2000, 1, "mxt224") -AVR_MCU ("atmxt224e", ARCH_AVRXMEGA2, "__AVR_ATMXT224E__", 0, 0, 0x2000, 1, "mxt224e") -AVR_MCU ("atmxt336s", ARCH_AVRXMEGA2, "__AVR_ATMXT336S__", 0, 0, 0x2000, 1, "mxt336s") -AVR_MCU ("atxmega16a4u", ARCH_AVRXMEGA2, "__AVR_ATxmega16A4U__", 0, 0, 0x2000, 1, "x16a4u") -AVR_MCU ("atxmega16c4", ARCH_AVRXMEGA2, "__AVR_ATxmega16C4__", 0, 0, 0x2000, 1, "x16c4") -AVR_MCU ("atxmega32a4u", ARCH_AVRXMEGA2, "__AVR_ATxmega32A4U__", 0, 0, 0x2000, 1, "x32a4u") -AVR_MCU ("atxmega32c4", ARCH_AVRXMEGA2, "__AVR_ATxmega32C4__", 0, 0, 0x2000, 1, "x32c4") -AVR_MCU ("atxmega32e5", ARCH_AVRXMEGA2, "__AVR_ATxmega32E5__", 0, 0, 0x2000, 1, "x32e5") +AVR_MCU ("avrxmega2", ARCH_AVRXMEGA2, AVR_ISA_NONE, NULL, 0x2000, 1, "x32a4") +AVR_MCU ("atxmega16a4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega16A4__", 0x2000, 1, "x16a4") +AVR_MCU ("atxmega16d4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega16D4__", 0x2000, 1, "x16d4") +AVR_MCU ("atxmega32a4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32A4__", 0x2000, 1, "x32a4") +AVR_MCU ("atxmega32d4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32D4__", 0x2000, 1, "x32d4") +AVR_MCU ("atxmega32x1", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32X1__", 0x2000, 1, "x32x1") +AVR_MCU ("atmxt112sl", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATMXT112SL__", 0x2000, 1, "mxt112sl") +AVR_MCU ("atmxt224", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATMXT224__", 0x2000, 1, "mxt224") +AVR_MCU ("atmxt224e", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATMXT224E__", 0x2000, 1, "mxt224e") +AVR_MCU ("atmxt336s", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATMXT336S__", 0x2000, 1, "mxt336s") +AVR_MCU ("atxmega16a4u", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega16A4U__", 0x2000, 1, "x16a4u") +AVR_MCU ("atxmega16c4", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega16C4__", 0x2000, 1, "x16c4") +AVR_MCU ("atxmega32a4u", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega32A4U__", 0x2000, 1, "x32a4u") +AVR_MCU ("atxmega32c4", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega32C4__", 0x2000, 1, "x32c4") +AVR_MCU ("atxmega32e5", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32E5__", 0x2000, 1, "x32e5") /* Xmega, 64K < Flash <= 128K, RAM <= 64K */ -AVR_MCU ("avrxmega4", ARCH_AVRXMEGA4, NULL, 0, 0, 0x2000, 2, "x64a4") -AVR_MCU ("atxmega64a3", ARCH_AVRXMEGA4, "__AVR_ATxmega64A3__", 0, 0, 0x2000, 2, "x64a3") -AVR_MCU ("atxmega64d3", ARCH_AVRXMEGA4, "__AVR_ATxmega64D3__", 0, 0, 0x2000, 2, "x64d3") -AVR_MCU ("atxmega64a3u", ARCH_AVRXMEGA4, "__AVR_ATxmega64A3U__", 0, 0, 0x2000, 2, "x64a3u") -AVR_MCU ("atxmega64a4u", ARCH_AVRXMEGA4, "__AVR_ATxmega64A4U__", 0, 0, 0x2000, 2, "x64a4u") -AVR_MCU ("atxmega64b1", ARCH_AVRXMEGA4, "__AVR_ATxmega64B1__", 0, 0, 0x2000, 2, "x64b1") -AVR_MCU ("atxmega64b3", ARCH_AVRXMEGA4, "__AVR_ATxmega64B3__", 0, 0, 0x2000, 2, "x64b3") -AVR_MCU ("atxmega64c3", ARCH_AVRXMEGA4, "__AVR_ATxmega64C3__", 0, 0, 0x2000, 2, "x64c3") -AVR_MCU ("atxmega64d4", ARCH_AVRXMEGA4, "__AVR_ATxmega64D4__", 0, 0, 0x2000, 2, "x64d4") +AVR_MCU ("avrxmega4", ARCH_AVRXMEGA4, AVR_ISA_NONE, NULL, 0x2000, 2, "x64a4") +AVR_MCU ("atxmega64a3", ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_ATxmega64A3__", 0x2000, 2, "x64a3") +AVR_MCU ("atxmega64d3", ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_ATxmega64D3__", 0x2000, 2, "x64d3") +AVR_MCU ("atxmega64a3u", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64A3U__", 0x2000, 2, "x64a3u") +AVR_MCU ("atxmega64a4u", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64A4U__", 0x2000, 2, "x64a4u") +AVR_MCU ("atxmega64b1", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64B1__", 0x2000, 2, "x64b1") +AVR_MCU ("atxmega64b3", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64B3__", 0x2000, 2, "x64b3") +AVR_MCU ("atxmega64c3", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64C3__", 0x2000, 2, "x64c3") +AVR_MCU ("atxmega64d4", ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_ATxmega64D4__", 0x2000, 2, "x64d4") /* Xmega, 64K < Flash <= 128K, RAM > 64K */ -AVR_MCU ("avrxmega5", ARCH_AVRXMEGA5, NULL, 0, 0, 0x2000, 2, "x64a1") -AVR_MCU ("atxmega64a1", ARCH_AVRXMEGA5, "__AVR_ATxmega64A1__", 0, 0, 0x2000, 2, "x64a1") -AVR_MCU ("atxmega64a1u", ARCH_AVRXMEGA5, "__AVR_ATxmega64A1U__", 0, 0, 0x2000, 2, "x64a1u") +AVR_MCU ("avrxmega5", ARCH_AVRXMEGA5, AVR_ISA_NONE, NULL, 0x2000, 2, "x64a1") +AVR_MCU ("atxmega64a1", ARCH_AVRXMEGA5, AVR_ISA_NONE, "__AVR_ATxmega64A1__", 0x2000, 2, "x64a1") +AVR_MCU ("atxmega64a1u", ARCH_AVRXMEGA5, AVR_ISA_RMW, "__AVR_ATxmega64A1U__", 0x2000, 2, "x64a1u") /* Xmega, 128K < Flash, RAM <= 64K */ -AVR_MCU ("avrxmega6", ARCH_AVRXMEGA6, NULL, 0, 0, 0x2000, 6, "x128a3") -AVR_MCU ("atxmega128a3", ARCH_AVRXMEGA6, "__AVR_ATxmega128A3__", 0, 0, 0x2000, 3, "x128a3") -AVR_MCU ("atxmega128d3", ARCH_AVRXMEGA6, "__AVR_ATxmega128D3__", 0, 0, 0x2000, 3, "x128d3") -AVR_MCU ("atxmega192a3", ARCH_AVRXMEGA6, "__AVR_ATxmega192A3__", 0, 0, 0x2000, 4, "x192a3") -AVR_MCU ("atxmega192d3", ARCH_AVRXMEGA6, "__AVR_ATxmega192D3__", 0, 0, 0x2000, 4, "x192d3") -AVR_MCU ("atxmega256a3", ARCH_AVRXMEGA6, "__AVR_ATxmega256A3__", 0, 0, 0x2000, 5, "x256a3") -AVR_MCU ("atxmega256a3b", ARCH_AVRXMEGA6, "__AVR_ATxmega256A3B__", 0, 0, 0x2000, 5, "x256a3b") -AVR_MCU ("atxmega256a3bu", ARCH_AVRXMEGA6, "__AVR_ATxmega256A3BU__", 0, 0, 0x2000, 5, "x256a3bu") -AVR_MCU ("atxmega256d3", ARCH_AVRXMEGA6, "__AVR_ATxmega256D3__", 0, 0, 0x2000, 5, "x256d3") -AVR_MCU ("atxmega128a3u", ARCH_AVRXMEGA6, "__AVR_ATxmega128A3U__", 0, 0, 0x2000, 3, "x128a3u") -AVR_MCU ("atxmega128b1", ARCH_AVRXMEGA6, "__AVR_ATxmega128B1__", 0, 0, 0x2000, 3, "x128b1") -AVR_MCU ("atxmega128b3", ARCH_AVRXMEGA6, "__AVR_ATxmega128B3__", 0, 0, 0x2000, 3, "x128b3") -AVR_MCU ("atxmega128c3", ARCH_AVRXMEGA6, "__AVR_ATxmega128C3__", 0, 0, 0x2000, 3, "x128c3") -AVR_MCU ("atxmega128d4", ARCH_AVRXMEGA6, "__AVR_ATxmega128D4__", 0, 0, 0x2000, 3, "x128d4") -AVR_MCU ("atmxt540s", ARCH_AVRXMEGA6, "__AVR_ATMXT540S__", 0, 0, 0x2000, 2, "mxt540s") -AVR_MCU ("atmxt540sreva", ARCH_AVRXMEGA6, "__AVR_ATMXT540SREVA__", 0, 0, 0x2000, 2, "mxt540sreva") -AVR_MCU ("atxmega192a3u", ARCH_AVRXMEGA6, "__AVR_ATxmega192A3U__", 0, 0, 0x2000, 4, "x192a3u") -AVR_MCU ("atxmega192c3", ARCH_AVRXMEGA6, "__AVR_ATxmega192C3__", 0, 0, 0x2000, 4, "x192c3") -AVR_MCU ("atxmega256a3u", ARCH_AVRXMEGA6, "__AVR_ATxmega256A3U__", 0, 0, 0x2000, 5, "x256a3u") -AVR_MCU ("atxmega256c3", ARCH_AVRXMEGA6, "__AVR_ATxmega256C3__", 0, 0, 0x2000, 5, "x256c3") -AVR_MCU ("atxmega384c3", ARCH_AVRXMEGA6, "__AVR_ATxmega384C3__", 0, 0, 0x2000, 6, "x384c3") -AVR_MCU ("atxmega384d3", ARCH_AVRXMEGA6, "__AVR_ATxmega384D3__", 0, 0, 0x2000, 6, "x384d3") +AVR_MCU ("avrxmega6", ARCH_AVRXMEGA6, AVR_ISA_NONE, NULL, 0x2000, 6, "x128a3") +AVR_MCU ("atxmega128a3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega128A3__", 0x2000, 3, "x128a3") +AVR_MCU ("atxmega128d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega128D3__", 0x2000, 3, "x128d3") +AVR_MCU ("atxmega192a3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega192A3__", 0x2000, 4, "x192a3") +AVR_MCU ("atxmega192d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega192D3__", 0x2000, 4, "x192d3") +AVR_MCU ("atxmega256a3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256A3__", 0x2000, 5, "x256a3") +AVR_MCU ("atxmega256a3b", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256A3B__", 0x2000, 5, "x256a3b") +AVR_MCU ("atxmega256a3bu", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega258A3BU__", 0x2000, 5, "x256a3bu") +AVR_MCU ("atxmega256d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256D3__", 0x2000, 5, "x256d3") +AVR_MCU ("atxmega128a3u", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128A3U__", 0x2000, 3, "x128a3u") +AVR_MCU ("atxmega128b1", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128B1__", 0x2000, 3, "x128b1") +AVR_MCU ("atxmega128b3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128B3__", 0x2000, 3, "x128b3") +AVR_MCU ("atxmega128c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128C3__", 0x2000, 3, "x128c3") +AVR_MCU ("atxmega128d4", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega128D4__", 0x2000, 3, "x128d4") +AVR_MCU ("atmxt540s", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATMXT540S__", 0x2000, 2, "mxt540s") +AVR_MCU ("atmxt540sreva", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATMXT540SREVA__", 0x2000, 2, "mxt540sreva") +AVR_MCU ("atxmega192a3u", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega192A3U__", 0x2000, 4, "x192a3u") +AVR_MCU ("atxmega192c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega192C3__", 0x2000, 4, "x192c3") +AVR_MCU ("atxmega256a3u", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega256A3U__", 0x2000, 5, "x256a3u") +AVR_MCU ("atxmega256c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega256C3__", 0x2000, 5, "x256c3") +AVR_MCU ("atxmega384c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega384C3__", 0x2000, 6, "x384c3") +AVR_MCU ("atxmega384d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega384D3__", 0x2000, 6, "x384d3") /* Xmega, 128K < Flash, RAM > 64K RAM. */ -AVR_MCU ("avrxmega7", ARCH_AVRXMEGA7, NULL, 0, 0, 0x2000, 3, "x128a1") -AVR_MCU ("atxmega128a1", ARCH_AVRXMEGA7, "__AVR_ATxmega128A1__", 0, 0, 0x2000, 3, "x128a1") -AVR_MCU ("atxmega128a1u", ARCH_AVRXMEGA7, "__AVR_ATxmega128A1U__", 0, 0, 0x2000, 3, "x128a1u") -AVR_MCU ("atxmega128a4u", ARCH_AVRXMEGA7, "__AVR_ATxmega128A4U__", 0, 0, 0x2000, 3, "x128a4u") +AVR_MCU ("avrxmega7", ARCH_AVRXMEGA7, AVR_ISA_NONE, NULL, 0x2000, 3, "x128a1") +AVR_MCU ("atxmega128a1", ARCH_AVRXMEGA7, AVR_ISA_NONE, "__AVR_ATxmega128A1__", 0x2000, 3, "x128a1") +AVR_MCU ("atxmega128a1u", ARCH_AVRXMEGA7, AVR_ISA_RMW, "__AVR_ATxmega128A1U__", 0x2000, 3, "x128a1u") +AVR_MCU ("atxmega128a4u", ARCH_AVRXMEGA7, AVR_ISA_RMW, "__AVR_ATxmega128A4U__", 0x2000, 3, "x128a4u") /* Assembler only. */ -AVR_MCU ("avr1", ARCH_AVR1, NULL, 0, 0, 0x0060, 1, "s1200") -AVR_MCU ("at90s1200", ARCH_AVR1, "__AVR_AT90S1200__", 0, 0, 0x0060, 1, "s1200") -AVR_MCU ("attiny11", ARCH_AVR1, "__AVR_ATtiny11__", 0, 0, 0x0060, 1, "tn11") -AVR_MCU ("attiny12", ARCH_AVR1, "__AVR_ATtiny12__", 0, 0, 0x0060, 1, "tn12") -AVR_MCU ("attiny15", ARCH_AVR1, "__AVR_ATtiny15__", 0, 0, 0x0060, 1, "tn15") -AVR_MCU ("attiny28", ARCH_AVR1, "__AVR_ATtiny28__", 0, 0, 0x0060, 1, "tn28") +AVR_MCU ("avr1", ARCH_AVR1, AVR_ISA_NONE, NULL, 0x0060, 1, "s1200") +AVR_MCU ("at90s1200", ARCH_AVR1, AVR_ISA_NONE, "__AVR_AT90S1200__", 0x0060, 1, "s1200") +AVR_MCU ("attiny11", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny11__", 0x0060, 1, "tn11") +AVR_MCU ("attiny12", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny12__", 0x0060, 1, "tn12") +AVR_MCU ("attiny15", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny15__", 0x0060, 1, "tn15") +AVR_MCU ("attiny28", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny28__", 0x0060, 1, "tn28") diff --git a/gcc-4.9/gcc/config/avr/avr.c b/gcc-4.9/gcc/config/avr/avr.c index 8ca7de0b3..99644ec92 100644 --- a/gcc-4.9/gcc/config/avr/avr.c +++ b/gcc-4.9/gcc/config/avr/avr.c @@ -10120,7 +10120,7 @@ test_hard_reg_class (enum reg_class rclass, rtx x) static bool avr_2word_insn_p (rtx insn) { - if (avr_current_device->errata_skip + if ((avr_current_device->dev_attribute & AVR_ERRATA_SKIP) || !insn || 2 != get_attr_length (insn)) { diff --git a/gcc-4.9/gcc/config/avr/avr.h b/gcc-4.9/gcc/config/avr/avr.h index 74be83c8a..78434ec5e 100644 --- a/gcc-4.9/gcc/config/avr/avr.h +++ b/gcc-4.9/gcc/config/avr/avr.h @@ -88,8 +88,9 @@ enum __AVR_HAVE_8BIT_SP__ and __AVR_HAVE_16BIT_SP__. During multilib generation there is always __AVR_SP8__ == __AVR_HAVE_8BIT_SP__. */ -#define AVR_HAVE_8BIT_SP \ - (avr_current_device->short_sp || TARGET_TINY_STACK || avr_sp8) +#define AVR_HAVE_8BIT_SP \ + ((avr_current_device->dev_attribute & AVR_SHORT_SP) || \ + TARGET_TINY_STACK || avr_sp8) #define AVR_HAVE_SPH (!avr_sp8) diff --git a/gcc-4.9/gcc/config/avr/avr.md b/gcc-4.9/gcc/config/avr/avr.md index f2d8605cd..d7baa4a83 100644 --- a/gcc-4.9/gcc/config/avr/avr.md +++ b/gcc-4.9/gcc/config/avr/avr.md @@ -5342,7 +5342,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "!AVR_HAVE_JMP_CALL - || !avr_current_device->errata_skip" + || !(avr_current_device->dev_attribute & AVR_ERRATA_SKIP)" { if (operands[2] == CONST0_RTX (<MODE>mode)) operands[2] = zero_reg_rtx; diff --git a/gcc-4.9/gcc/config/avr/driver-avr.c b/gcc-4.9/gcc/config/avr/driver-avr.c index cb5dd1d1d..76c8b3980 100644 --- a/gcc-4.9/gcc/config/avr/driver-avr.c +++ b/gcc-4.9/gcc/config/avr/driver-avr.c @@ -59,8 +59,8 @@ avr_device_to_as (int argc, const char **argv) avr_set_current_device (argv[0]); return concat ("-mmcu=", avr_current_arch->arch_name, - avr_current_device->errata_skip ? "" : " -mno-skip-bug", - NULL); + avr_current_device->dev_attribute & AVR_ERRATA_SKIP ? "" : " -mno-skip-bug", + avr_current_device->dev_attribute & AVR_ISA_RMW ? " -mrmw" : "", NULL); } /* Returns command line parameters to pass to ld. */ @@ -144,7 +144,7 @@ avr_device_to_sp8 (int argc, const char **argv) || avr_current_device->arch == ARCH_AVR25)) return ""; - return avr_current_device->short_sp + return (avr_current_device->dev_attribute & AVR_SHORT_SP) ? "-msp8" : "%<msp8"; } diff --git a/gcc-4.9/gcc/config/avr/genmultilib.awk b/gcc-4.9/gcc/config/avr/genmultilib.awk index 90e5e5cfd..1dfeabbee 100644 --- a/gcc-4.9/gcc/config/avr/genmultilib.awk +++ b/gcc-4.9/gcc/config/avr/genmultilib.awk @@ -86,7 +86,7 @@ BEGIN { name = $2 gsub ("\"", "", name) - if ($4 == "NULL") + if ($5 == "NULL") { core = name @@ -106,7 +106,17 @@ BEGIN { if (core == "avr1") next - tiny_stack[name] = $5 + # split device specific feature list + n = split($4,dev_attribute,"|") + + # set tiny_stack false by default + tiny_stack[name] = 0 + for (i=1; i <= n; i++) + if (dev_attribute[i] == "AVR_SHORT_SP") { + tiny_stack[name] = 1 + break + } + mcu[n_mcu] = name n_mcu++ option[name] = "mmcu=" name diff --git a/gcc-4.9/gcc/config/elfos.h b/gcc-4.9/gcc/config/elfos.h index 1fce7011b..c1d555312 100644 --- a/gcc-4.9/gcc/config/elfos.h +++ b/gcc-4.9/gcc/config/elfos.h @@ -287,7 +287,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* Write the extra assembler code needed to declare an object properly. */ #ifdef HAVE_GAS_GNU_UNIQUE_OBJECT -#define USE_GNU_UNIQUE_OBJECT 1 +#define USE_GNU_UNIQUE_OBJECT flag_gnu_unique #else #define USE_GNU_UNIQUE_OBJECT 0 #endif diff --git a/gcc-4.9/gcc/config/i386/avx512fintrin.h b/gcc-4.9/gcc/config/i386/avx512fintrin.h index 960286618..314895ad7 100644 --- a/gcc-4.9/gcc/config/i386/avx512fintrin.h +++ b/gcc-4.9/gcc/config/i386/avx512fintrin.h @@ -39,6 +39,8 @@ typedef double __v8df __attribute__ ((__vector_size__ (64))); typedef float __v16sf __attribute__ ((__vector_size__ (64))); typedef long long __v8di __attribute__ ((__vector_size__ (64))); typedef int __v16si __attribute__ ((__vector_size__ (64))); +typedef short __v32hi __attribute__ ((__vector_size__ (64))); +typedef char __v64qi __attribute__ ((__vector_size__ (64))); /* The Intel API is flexible enough that we must allow aliasing with other vector types, and their scalar components. */ @@ -130,6 +132,32 @@ _mm512_undefined_si512 (void) return __Y; } +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_set1_epi8 (char __A) +{ + return __extension__ (__m512i)(__v64qi) + { __A, __A, __A, __A, __A, __A, __A, __A, + __A, __A, __A, __A, __A, __A, __A, __A, + __A, __A, __A, __A, __A, __A, __A, __A, + __A, __A, __A, __A, __A, __A, __A, __A, + __A, __A, __A, __A, __A, __A, __A, __A, + __A, __A, __A, __A, __A, __A, __A, __A, + __A, __A, __A, __A, __A, __A, __A, __A, + __A, __A, __A, __A, __A, __A, __A, __A }; +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_set1_epi16 (short __A) +{ + return __extension__ (__m512i)(__v32hi) + { __A, __A, __A, __A, __A, __A, __A, __A, + __A, __A, __A, __A, __A, __A, __A, __A, + __A, __A, __A, __A, __A, __A, __A, __A, + __A, __A, __A, __A, __A, __A, __A, __A }; +} + extern __inline __m512d __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm512_set1_pd (double __A) @@ -152,6 +180,54 @@ _mm512_set1_ps (float __A) (__mmask16) -1); } +/* Create the vector [A B C D A B C D A B C D A B C D]. */ +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_set4_epi32 (int __A, int __B, int __C, int __D) +{ + return __extension__ (__m512i)(__v16si) + { __D, __C, __B, __A, __D, __C, __B, __A, + __D, __C, __B, __A, __D, __C, __B, __A }; +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_set4_epi64 (long long __A, long long __B, long long __C, + long long __D) +{ + return __extension__ (__m512i) (__v8di) + { __D, __C, __B, __A, __D, __C, __B, __A }; +} + +extern __inline __m512d +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_set4_pd (double __A, double __B, double __C, double __D) +{ + return __extension__ (__m512d) + { __D, __C, __B, __A, __D, __C, __B, __A }; +} + +extern __inline __m512 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_set4_ps (float __A, float __B, float __C, float __D) +{ + return __extension__ (__m512) + { __D, __C, __B, __A, __D, __C, __B, __A, + __D, __C, __B, __A, __D, __C, __B, __A }; +} + +#define _mm512_setr4_epi64(e0,e1,e2,e3) \ + _mm512_set4_epi64(e3,e2,e1,e0) + +#define _mm512_setr4_epi32(e0,e1,e2,e3) \ + _mm512_set4_epi32(e3,e2,e1,e0) + +#define _mm512_setr4_pd(e0,e1,e2,e3) \ + _mm512_set4_pd(e3,e2,e1,e0) + +#define _mm512_setr4_ps(e0,e1,e2,e3) \ + _mm512_set4_ps(e3,e2,e1,e0) + extern __inline __m512 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm512_setzero_ps (void) @@ -169,6 +245,13 @@ _mm512_setzero_pd (void) extern __inline __m512i __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_setzero_epi32 (void) +{ + return __extension__ (__m512i)(__v8di){ 0, 0, 0, 0, 0, 0, 0, 0 }; +} + +extern __inline __m512i +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm512_setzero_si512 (void) { return __extension__ (__m512i)(__v8di){ 0, 0, 0, 0, 0, 0, 0, 0 }; diff --git a/gcc-4.9/gcc/config/i386/bmiintrin.h b/gcc-4.9/gcc/config/i386/bmiintrin.h index b86adf179..b2d7c60ea 100644 --- a/gcc-4.9/gcc/config/i386/bmiintrin.h +++ b/gcc-4.9/gcc/config/i386/bmiintrin.h @@ -40,7 +40,6 @@ __tzcnt_u16 (unsigned short __X) return __builtin_ctzs (__X); } - extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __andn_u32 (unsigned int __X, unsigned int __Y) { @@ -66,17 +65,34 @@ __blsi_u32 (unsigned int __X) } extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsi_u32 (unsigned int __X) +{ + return __blsi_u32 (__X); +} + +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsmsk_u32 (unsigned int __X) { return __X ^ (__X - 1); } extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsmsk_u32 (unsigned int __X) +{ + return __blsmsk_u32 (__X); +} + +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsr_u32 (unsigned int __X) { return __X & (__X - 1); } +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsr_u32 (unsigned int __X) +{ + return __blsr_u32 (__X); +} extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __tzcnt_u32 (unsigned int __X) @@ -84,6 +100,12 @@ __tzcnt_u32 (unsigned int __X) return __builtin_ctz (__X); } +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_tzcnt_u32 (unsigned int __X) +{ + return __builtin_ctz (__X); +} + #ifdef __x86_64__ extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -111,23 +133,47 @@ __blsi_u64 (unsigned long long __X) } extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsi_u64 (unsigned long long __X) +{ + return __blsi_u64 (__X); +} + +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsmsk_u64 (unsigned long long __X) { return __X ^ (__X - 1); } extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsmsk_u64 (unsigned long long __X) +{ + return __blsmsk_u64 (__X); +} + +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsr_u64 (unsigned long long __X) { return __X & (__X - 1); } extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsr_u64 (unsigned long long __X) +{ + return __blsr_u64 (__X); +} + +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __tzcnt_u64 (unsigned long long __X) { return __builtin_ctzll (__X); } +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_tzcnt_u64 (unsigned long long __X) +{ + return __builtin_ctzll (__X); +} + #endif /* __x86_64__ */ #ifdef __DISABLE_BMI__ diff --git a/gcc-4.9/gcc/config/i386/constraints.md b/gcc-4.9/gcc/config/i386/constraints.md index 65335f128..567e70564 100644 --- a/gcc-4.9/gcc/config/i386/constraints.md +++ b/gcc-4.9/gcc/config/i386/constraints.md @@ -220,6 +220,13 @@ ;; We use W prefix to denote any number of ;; constant-or-symbol-reference constraints +(define_constraint "We" + "32-bit signed integer constant, or a symbolic reference known + to fit that range (for sign-extending conversion operations that + require non-VOIDmode immediate operands)." + (and (match_operand 0 "x86_64_immediate_operand") + (match_test "GET_MODE (op) != VOIDmode"))) + (define_constraint "Wz" "32-bit unsigned integer constant, or a symbolic reference known to fit that range (for zero-extending conversion operations that diff --git a/gcc-4.9/gcc/config/i386/i386.c b/gcc-4.9/gcc/config/i386/i386.c index 842be686d..3eefe4ac5 100644 --- a/gcc-4.9/gcc/config/i386/i386.c +++ b/gcc-4.9/gcc/config/i386/i386.c @@ -13925,13 +13925,13 @@ ix86_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, if (GET_CODE (XEXP (x, 0)) == MULT) { changed = 1; - XEXP (x, 0) = force_operand (XEXP (x, 0), 0); + XEXP (x, 0) = copy_addr_to_reg (XEXP (x, 0)); } if (GET_CODE (XEXP (x, 1)) == MULT) { changed = 1; - XEXP (x, 1) = force_operand (XEXP (x, 1), 0); + XEXP (x, 1) = copy_addr_to_reg (XEXP (x, 1)); } if (changed @@ -22755,7 +22755,7 @@ counter_mode (rtx count_exp) static rtx ix86_copy_addr_to_reg (rtx addr) { - if (GET_MODE (addr) == Pmode) + if (GET_MODE (addr) == Pmode || GET_MODE (addr) == VOIDmode) return copy_addr_to_reg (addr); else { diff --git a/gcc-4.9/gcc/config/i386/i386.md b/gcc-4.9/gcc/config/i386/i386.md index 4a8b46388..25e2e93e3 100644 --- a/gcc-4.9/gcc/config/i386/i386.md +++ b/gcc-4.9/gcc/config/i386/i386.md @@ -971,6 +971,15 @@ (DI "x86_64_general_operand") (TI "x86_64_general_operand")]) +;; General sign extend operand predicate for integer modes, +;; which disallows VOIDmode operands and thus it is suitable +;; for use inside sign_extend. +(define_mode_attr general_sext_operand + [(QI "sext_operand") + (HI "sext_operand") + (SI "x86_64_sext_operand") + (DI "x86_64_sext_operand")]) + ;; General sign/zero extend operand predicate for integer modes. (define_mode_attr general_szext_operand [(QI "general_operand") @@ -4730,8 +4739,13 @@ && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <SWI48:MODE>mode)") (eq_attr "alternative" "1") + /* ??? For sched1 we need constrain_operands to be able to + select an alternative. Leave this enabled before RA. */ (symbol_ref "TARGET_INTER_UNIT_CONVERSIONS - || optimize_function_for_size_p (cfun)") + || optimize_function_for_size_p (cfun) + || !(reload_completed + || reload_in_progress + || lra_in_progress)") ] (symbol_ref "true"))) ]) @@ -5821,10 +5835,11 @@ (eq:CCO (plus:<DWI> (sign_extend:<DWI> (match_operand:SWI 1 "nonimmediate_operand")) - (sign_extend:<DWI> - (match_operand:SWI 2 "<general_operand>"))) + (match_dup 4)) (sign_extend:<DWI> - (plus:SWI (match_dup 1) (match_dup 2))))) + (plus:SWI (match_dup 1) + (match_operand:SWI 2 + "<general_operand>"))))) (set (match_operand:SWI 0 "register_operand") (plus:SWI (match_dup 1) (match_dup 2)))]) (set (pc) (if_then_else @@ -5832,7 +5847,13 @@ (label_ref (match_operand 3)) (pc)))] "" - "ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);") +{ + ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands); + if (CONST_INT_P (operands[2])) + operands[4] = operands[2]; + else + operands[4] = gen_rtx_SIGN_EXTEND (<DWI>mode, operands[2]); +}) (define_insn "*addv<mode>4" [(set (reg:CCO FLAGS_REG) @@ -5840,7 +5861,8 @@ (sign_extend:<DWI> (match_operand:SWI 1 "nonimmediate_operand" "%0,0")) (sign_extend:<DWI> - (match_operand:SWI 2 "<general_operand>" "<g>,<r><i>"))) + (match_operand:SWI 2 "<general_sext_operand>" + "<r>mWe,<r>We"))) (sign_extend:<DWI> (plus:SWI (match_dup 1) (match_dup 2))))) (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m") @@ -5850,6 +5872,31 @@ [(set_attr "type" "alu") (set_attr "mode" "<MODE>")]) +(define_insn "*addv<mode>4_1" + [(set (reg:CCO FLAGS_REG) + (eq:CCO (plus:<DWI> + (sign_extend:<DWI> + (match_operand:SWI 1 "nonimmediate_operand" "0")) + (match_operand:<DWI> 3 "const_int_operand" "i")) + (sign_extend:<DWI> + (plus:SWI (match_dup 1) + (match_operand:SWI 2 "x86_64_immediate_operand" + "<i>"))))) + (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m") + (plus:SWI (match_dup 1) (match_dup 2)))] + "ix86_binary_operator_ok (PLUS, <MODE>mode, operands) + && CONST_INT_P (operands[2]) + && INTVAL (operands[2]) == INTVAL (operands[3])" + "add{<imodesuffix>}\t{%2, %0|%0, %2}" + [(set_attr "type" "alu") + (set_attr "mode" "<MODE>") + (set (attr "length_immediate") + (cond [(match_test "IN_RANGE (INTVAL (operands[2]), -128, 127)") + (const_string "1") + (match_test "<MODE_SIZE> == 8") + (const_string "4")] + (const_string "<MODE_SIZE>")))]) + ;; The lea patterns for modes less than 32 bits need to be matched by ;; several insns converted to real lea by splitters. @@ -6093,10 +6140,11 @@ (eq:CCO (minus:<DWI> (sign_extend:<DWI> (match_operand:SWI 1 "nonimmediate_operand")) - (sign_extend:<DWI> - (match_operand:SWI 2 "<general_operand>"))) + (match_dup 4)) (sign_extend:<DWI> - (minus:SWI (match_dup 1) (match_dup 2))))) + (minus:SWI (match_dup 1) + (match_operand:SWI 2 + "<general_operand>"))))) (set (match_operand:SWI 0 "register_operand") (minus:SWI (match_dup 1) (match_dup 2)))]) (set (pc) (if_then_else @@ -6104,7 +6152,13 @@ (label_ref (match_operand 3)) (pc)))] "" - "ix86_fixup_binary_operands_no_copy (MINUS, <MODE>mode, operands);") +{ + ix86_fixup_binary_operands_no_copy (MINUS, <MODE>mode, operands); + if (CONST_INT_P (operands[2])) + operands[4] = operands[2]; + else + operands[4] = gen_rtx_SIGN_EXTEND (<DWI>mode, operands[2]); +}) (define_insn "*subv<mode>4" [(set (reg:CCO FLAGS_REG) @@ -6112,7 +6166,8 @@ (sign_extend:<DWI> (match_operand:SWI 1 "nonimmediate_operand" "0,0")) (sign_extend:<DWI> - (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))) + (match_operand:SWI 2 "<general_sext_operand>" + "<r>We,<r>m"))) (sign_extend:<DWI> (minus:SWI (match_dup 1) (match_dup 2))))) (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>") @@ -6122,6 +6177,31 @@ [(set_attr "type" "alu") (set_attr "mode" "<MODE>")]) +(define_insn "*subv<mode>4_1" + [(set (reg:CCO FLAGS_REG) + (eq:CCO (minus:<DWI> + (sign_extend:<DWI> + (match_operand:SWI 1 "nonimmediate_operand" "0")) + (match_operand:<DWI> 3 "const_int_operand" "i")) + (sign_extend:<DWI> + (minus:SWI (match_dup 1) + (match_operand:SWI 2 "x86_64_immediate_operand" + "<i>"))))) + (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m") + (minus:SWI (match_dup 1) (match_dup 2)))] + "ix86_binary_operator_ok (MINUS, <MODE>mode, operands) + && CONST_INT_P (operands[2]) + && INTVAL (operands[2]) == INTVAL (operands[3])" + "sub{<imodesuffix>}\t{%2, %0|%0, %2}" + [(set_attr "type" "alu") + (set_attr "mode" "<MODE>") + (set (attr "length_immediate") + (cond [(match_test "IN_RANGE (INTVAL (operands[2]), -128, 127)") + (const_string "1") + (match_test "<MODE_SIZE> == 8") + (const_string "4")] + (const_string "<MODE_SIZE>")))]) + (define_insn "*sub<mode>_3" [(set (reg FLAGS_REG) (compare (match_operand:SWI 1 "nonimmediate_operand" "0,0") @@ -6442,52 +6522,98 @@ (eq:CCO (mult:<DWI> (sign_extend:<DWI> (match_operand:SWI48 1 "register_operand")) - (sign_extend:<DWI> - (match_operand:SWI48 2 "<general_operand>"))) + (match_dup 4)) (sign_extend:<DWI> - (mult:SWI48 (match_dup 1) (match_dup 2))))) + (mult:SWI48 (match_dup 1) + (match_operand:SWI48 2 + "<general_operand>"))))) (set (match_operand:SWI48 0 "register_operand") (mult:SWI48 (match_dup 1) (match_dup 2)))]) (set (pc) (if_then_else (eq (reg:CCO FLAGS_REG) (const_int 0)) (label_ref (match_operand 3)) - (pc)))]) + (pc)))] + "" +{ + if (CONST_INT_P (operands[2])) + operands[4] = operands[2]; + else + operands[4] = gen_rtx_SIGN_EXTEND (<DWI>mode, operands[2]); +}) (define_insn "*mulv<mode>4" [(set (reg:CCO FLAGS_REG) (eq:CCO (mult:<DWI> (sign_extend:<DWI> - (match_operand:SWI 1 "nonimmediate_operand" "%rm,rm,0")) + (match_operand:SWI48 1 "nonimmediate_operand" "%rm,0")) (sign_extend:<DWI> - (match_operand:SWI 2 "<general_operand>" "K,<i>,mr"))) + (match_operand:SWI48 2 "<general_sext_operand>" + "We,mr"))) (sign_extend:<DWI> - (mult:SWI (match_dup 1) (match_dup 2))))) - (set (match_operand:SWI 0 "register_operand" "=r,r,r") - (mult:SWI (match_dup 1) (match_dup 2)))] + (mult:SWI48 (match_dup 1) (match_dup 2))))) + (set (match_operand:SWI48 0 "register_operand" "=r,r") + (mult:SWI48 (match_dup 1) (match_dup 2)))] "!(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2} - imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2} imul{<imodesuffix>}\t{%2, %0|%0, %2}" [(set_attr "type" "imul") - (set_attr "prefix_0f" "0,0,1") + (set_attr "prefix_0f" "0,1") (set (attr "athlon_decode") (cond [(eq_attr "cpu" "athlon") (const_string "vector") - (eq_attr "alternative" "1") + (eq_attr "alternative" "0") (const_string "vector") - (and (eq_attr "alternative" "2") + (and (eq_attr "alternative" "1") (match_operand 1 "memory_operand")) (const_string "vector")] (const_string "direct"))) (set (attr "amdfam10_decode") - (cond [(and (eq_attr "alternative" "0,1") + (cond [(and (eq_attr "alternative" "1") (match_operand 1 "memory_operand")) (const_string "vector")] (const_string "direct"))) (set_attr "bdver1_decode" "direct") (set_attr "mode" "<MODE>")]) +(define_insn "*mulv<mode>4_1" + [(set (reg:CCO FLAGS_REG) + (eq:CCO (mult:<DWI> + (sign_extend:<DWI> + (match_operand:SWI48 1 "nonimmediate_operand" "rm,rm")) + (match_operand:<DWI> 3 "const_int_operand" "K,i")) + (sign_extend:<DWI> + (mult:SWI48 (match_dup 1) + (match_operand:SWI 2 "x86_64_immediate_operand" + "K,<i>"))))) + (set (match_operand:SWI48 0 "register_operand" "=r,r") + (mult:SWI48 (match_dup 1) (match_dup 2)))] + "!(MEM_P (operands[1]) && MEM_P (operands[2])) + && CONST_INT_P (operands[2]) + && INTVAL (operands[2]) == INTVAL (operands[3])" + "@ + imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2} + imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "imul") + (set (attr "athlon_decode") + (cond [(eq_attr "cpu" "athlon") + (const_string "vector") + (eq_attr "alternative" "1") + (const_string "vector")] + (const_string "direct"))) + (set (attr "amdfam10_decode") + (cond [(match_operand 1 "memory_operand") + (const_string "vector")] + (const_string "direct"))) + (set_attr "bdver1_decode" "direct") + (set_attr "mode" "<MODE>") + (set (attr "length_immediate") + (cond [(match_test "IN_RANGE (INTVAL (operands[2]), -128, 127)") + (const_string "1") + (match_test "<MODE_SIZE> == 8") + (const_string "4")] + (const_string "<MODE_SIZE>")))]) + (define_expand "<u>mul<mode><dwi>3" [(parallel [(set (match_operand:<DWI> 0 "register_operand") (mult:<DWI> diff --git a/gcc-4.9/gcc/config/i386/predicates.md b/gcc-4.9/gcc/config/i386/predicates.md index 0492241fd..2ef138424 100644 --- a/gcc-4.9/gcc/config/i386/predicates.md +++ b/gcc-4.9/gcc/config/i386/predicates.md @@ -338,6 +338,20 @@ (match_operand 0 "x86_64_immediate_operand")) (match_operand 0 "general_operand"))) +;; Return true if OP is non-VOIDmode general operand representable +;; on x86_64. This predicate is used in sign-extending conversion +;; operations that require non-VOIDmode immediate operands. +(define_predicate "x86_64_sext_operand" + (and (match_test "GET_MODE (op) != VOIDmode") + (match_operand 0 "x86_64_general_operand"))) + +;; Return true if OP is non-VOIDmode general operand. This predicate +;; is used in sign-extending conversion operations that require +;; non-VOIDmode immediate operands. +(define_predicate "sext_operand" + (and (match_test "GET_MODE (op) != VOIDmode") + (match_operand 0 "general_operand"))) + ;; Return true if OP is representable on x86_64 as zero-extended operand. ;; This predicate is used in zero-extending conversion operations that ;; require non-VOIDmode immediate operands. diff --git a/gcc-4.9/gcc/config/i386/sse.md b/gcc-4.9/gcc/config/i386/sse.md index f30b27e86..72a4d6d07 100644 --- a/gcc-4.9/gcc/config/i386/sse.md +++ b/gcc-4.9/gcc/config/i386/sse.md @@ -2712,50 +2712,46 @@ (fma:FMAMODEM (match_operand:FMAMODEM 1 "nonimmediate_operand") (match_operand:FMAMODEM 2 "nonimmediate_operand") - (match_operand:FMAMODEM 3 "nonimmediate_operand")))] - "") + (match_operand:FMAMODEM 3 "nonimmediate_operand")))]) (define_expand "fms<mode>4" [(set (match_operand:FMAMODEM 0 "register_operand") (fma:FMAMODEM (match_operand:FMAMODEM 1 "nonimmediate_operand") (match_operand:FMAMODEM 2 "nonimmediate_operand") - (neg:FMAMODEM (match_operand:FMAMODEM 3 "nonimmediate_operand"))))] - "") + (neg:FMAMODEM (match_operand:FMAMODEM 3 "nonimmediate_operand"))))]) (define_expand "fnma<mode>4" [(set (match_operand:FMAMODEM 0 "register_operand") (fma:FMAMODEM (neg:FMAMODEM (match_operand:FMAMODEM 1 "nonimmediate_operand")) (match_operand:FMAMODEM 2 "nonimmediate_operand") - (match_operand:FMAMODEM 3 "nonimmediate_operand")))] - "") + (match_operand:FMAMODEM 3 "nonimmediate_operand")))]) (define_expand "fnms<mode>4" [(set (match_operand:FMAMODEM 0 "register_operand") (fma:FMAMODEM (neg:FMAMODEM (match_operand:FMAMODEM 1 "nonimmediate_operand")) (match_operand:FMAMODEM 2 "nonimmediate_operand") - (neg:FMAMODEM (match_operand:FMAMODEM 3 "nonimmediate_operand"))))] - "") + (neg:FMAMODEM (match_operand:FMAMODEM 3 "nonimmediate_operand"))))]) ;; The builtins for intrinsics are not constrained by SSE math enabled. -(define_mode_iterator FMAMODE [(SF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F") - (DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F") - (V4SF "TARGET_FMA || TARGET_FMA4") - (V2DF "TARGET_FMA || TARGET_FMA4") - (V8SF "TARGET_FMA || TARGET_FMA4") - (V4DF "TARGET_FMA || TARGET_FMA4") - (V16SF "TARGET_AVX512F") - (V8DF "TARGET_AVX512F")]) +(define_mode_iterator FMAMODE + [(SF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F") + (DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F") + (V4SF "TARGET_FMA || TARGET_FMA4") + (V2DF "TARGET_FMA || TARGET_FMA4") + (V8SF "TARGET_FMA || TARGET_FMA4") + (V4DF "TARGET_FMA || TARGET_FMA4") + (V16SF "TARGET_AVX512F") + (V8DF "TARGET_AVX512F")]) (define_expand "fma4i_fmadd_<mode>" [(set (match_operand:FMAMODE 0 "register_operand") (fma:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand") (match_operand:FMAMODE 2 "nonimmediate_operand") - (match_operand:FMAMODE 3 "nonimmediate_operand")))] - "") + (match_operand:FMAMODE 3 "nonimmediate_operand")))]) (define_expand "avx512f_fmadd_<mode>_maskz<round_expand_name>" [(match_operand:VF_512 0 "register_operand") @@ -2771,12 +2767,20 @@ DONE; }) +(define_mode_iterator FMAMODE_NOVF512 + [(SF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F") + (DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F") + (V4SF "TARGET_FMA || TARGET_FMA4") + (V2DF "TARGET_FMA || TARGET_FMA4") + (V8SF "TARGET_FMA || TARGET_FMA4") + (V4DF "TARGET_FMA || TARGET_FMA4")]) + (define_insn "<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name><round_name>" - [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") - (fma:FMAMODE - (match_operand:FMAMODE 1 "<round_nimm_predicate>" "%0,0,v,x,x") - (match_operand:FMAMODE 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>,x,m") - (match_operand:FMAMODE 3 "<round_nimm_predicate>" "v,<round_constraint>,0,xm,x")))] + [(set (match_operand:FMAMODE_NOVF512 0 "register_operand" "=v,v,v,x,x") + (fma:FMAMODE_NOVF512 + (match_operand:FMAMODE_NOVF512 1 "<round_nimm_predicate>" "%0,0,v,x,x") + (match_operand:FMAMODE_NOVF512 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>,x,m") + (match_operand:FMAMODE_NOVF512 3 "<round_nimm_predicate>" "v,<round_constraint>,0,xm,x")))] "<sd_mask_mode512bit_condition> && <round_mode512bit_condition>" "@ vfmadd132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>} @@ -2788,6 +2792,21 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "<MODE>")]) +(define_insn "<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name><round_name>" + [(set (match_operand:VF_512 0 "register_operand" "=v,v,v") + (fma:VF_512 + (match_operand:VF_512 1 "<round_nimm_predicate>" "%0,0,v") + (match_operand:VF_512 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>") + (match_operand:VF_512 3 "<round_nimm_predicate>" "v,<round_constraint>,0")))] + "<sd_mask_mode512bit_condition> && <round_mode512bit_condition>" + "@ + vfmadd132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>} + vfmadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>} + vfmadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}" + [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f") + (set_attr "type" "ssemuladd") + (set_attr "mode" "<MODE>")]) + (define_insn "avx512f_fmadd_<mode>_mask<round_name>" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 @@ -2821,12 +2840,12 @@ (set_attr "mode" "<MODE>")]) (define_insn "<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name><round_name>" - [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") - (fma:FMAMODE - (match_operand:FMAMODE 1 "<round_nimm_predicate>" "%0, 0, v, x,x") - (match_operand:FMAMODE 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>,x,m") - (neg:FMAMODE - (match_operand:FMAMODE 3 "<round_nimm_predicate>" "v,<round_constraint>,0,xm,x"))))] + [(set (match_operand:FMAMODE_NOVF512 0 "register_operand" "=v,v,v,x,x") + (fma:FMAMODE_NOVF512 + (match_operand:FMAMODE_NOVF512 1 "<round_nimm_predicate>" "%0,0,v,x,x") + (match_operand:FMAMODE_NOVF512 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>,x,m") + (neg:FMAMODE_NOVF512 + (match_operand:FMAMODE_NOVF512 3 "<round_nimm_predicate>" "v,<round_constraint>,0,xm,x"))))] "<sd_mask_mode512bit_condition> && <round_mode512bit_condition>" "@ vfmsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>} @@ -2838,6 +2857,22 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "<MODE>")]) +(define_insn "<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name><round_name>" + [(set (match_operand:VF_512 0 "register_operand" "=v,v,v") + (fma:VF_512 + (match_operand:VF_512 1 "<round_nimm_predicate>" "%0,0,v") + (match_operand:VF_512 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>") + (neg:VF_512 + (match_operand:VF_512 3 "<round_nimm_predicate>" "v,<round_constraint>,0"))))] + "<sd_mask_mode512bit_condition> && <round_mode512bit_condition>" + "@ + vfmsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>} + vfmsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>} + vfmsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}" + [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f") + (set_attr "type" "ssemuladd") + (set_attr "mode" "<MODE>")]) + (define_insn "avx512f_fmsub_<mode>_mask<round_name>" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 @@ -2873,12 +2908,12 @@ (set_attr "mode" "<MODE>")]) (define_insn "<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name><round_name>" - [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") - (fma:FMAMODE - (neg:FMAMODE - (match_operand:FMAMODE 1 "<round_nimm_predicate>" "%0,0,v,x,x")) - (match_operand:FMAMODE 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>,x,m") - (match_operand:FMAMODE 3 "<round_nimm_predicate>" "v,<round_constraint>,0,xm,x")))] + [(set (match_operand:FMAMODE_NOVF512 0 "register_operand" "=v,v,v,x,x") + (fma:FMAMODE_NOVF512 + (neg:FMAMODE_NOVF512 + (match_operand:FMAMODE_NOVF512 1 "<round_nimm_predicate>" "%0,0,v,x,x")) + (match_operand:FMAMODE_NOVF512 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>,x,m") + (match_operand:FMAMODE_NOVF512 3 "<round_nimm_predicate>" "v,<round_constraint>,0,xm,x")))] "<sd_mask_mode512bit_condition> && <round_mode512bit_condition>" "@ vfnmadd132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>} @@ -2890,6 +2925,22 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "<MODE>")]) +(define_insn "<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name><round_name>" + [(set (match_operand:VF_512 0 "register_operand" "=v,v,v") + (fma:VF_512 + (neg:VF_512 + (match_operand:VF_512 1 "<round_nimm_predicate>" "%0,0,v")) + (match_operand:VF_512 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>") + (match_operand:VF_512 3 "<round_nimm_predicate>" "v,<round_constraint>,0")))] + "<sd_mask_mode512bit_condition> && <round_mode512bit_condition>" + "@ + vfnmadd132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>} + vfnmadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>} + vfnmadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}" + [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f") + (set_attr "type" "ssemuladd") + (set_attr "mode" "<MODE>")]) + (define_insn "avx512f_fnmadd_<mode>_mask<round_name>" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 @@ -2925,13 +2976,13 @@ (set_attr "mode" "<MODE>")]) (define_insn "<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name><round_name>" - [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") - (fma:FMAMODE - (neg:FMAMODE - (match_operand:FMAMODE 1 "<round_nimm_predicate>" "%0,0,v,x,x")) - (match_operand:FMAMODE 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>,x,m") - (neg:FMAMODE - (match_operand:FMAMODE 3 "<round_nimm_predicate>" "v,<round_constraint>,0,xm,x"))))] + [(set (match_operand:FMAMODE_NOVF512 0 "register_operand" "=v,v,v,x,x") + (fma:FMAMODE_NOVF512 + (neg:FMAMODE_NOVF512 + (match_operand:FMAMODE_NOVF512 1 "<round_nimm_predicate>" "%0,0,v,x,x")) + (match_operand:FMAMODE_NOVF512 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>,x,m") + (neg:FMAMODE_NOVF512 + (match_operand:FMAMODE_NOVF512 3 "<round_nimm_predicate>" "v,<round_constraint>,0,xm,x"))))] "<sd_mask_mode512bit_condition> && <round_mode512bit_condition>" "@ vfnmsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>} @@ -2943,6 +2994,23 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "<MODE>")]) +(define_insn "<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name><round_name>" + [(set (match_operand:VF_512 0 "register_operand" "=v,v,v") + (fma:VF_512 + (neg:VF_512 + (match_operand:VF_512 1 "<round_nimm_predicate>" "%0,0,v")) + (match_operand:VF_512 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>") + (neg:VF_512 + (match_operand:VF_512 3 "<round_nimm_predicate>" "v,<round_constraint>,0"))))] + "<sd_mask_mode512bit_condition> && <round_mode512bit_condition>" + "@ + vfnmsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>} + vfnmsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>} + vfnmsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}" + [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f") + (set_attr "type" "ssemuladd") + (set_attr "mode" "<MODE>")]) + (define_insn "avx512f_fnmsub_<mode>_mask<round_name>" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 @@ -3014,11 +3082,11 @@ }) (define_insn "<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>" - [(set (match_operand:VF 0 "register_operand" "=v,v,v,x,x") - (unspec:VF - [(match_operand:VF 1 "<round_nimm_predicate>" "%0,0,v,x,x") - (match_operand:VF 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>,x,m") - (match_operand:VF 3 "<round_nimm_predicate>" "v,<round_constraint>,0,xm,x")] + [(set (match_operand:VF_128_256 0 "register_operand" "=v,v,v,x,x") + (unspec:VF_128_256 + [(match_operand:VF_128_256 1 "<round_nimm_predicate>" "%0,0,v,x,x") + (match_operand:VF_128_256 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>,x,m") + (match_operand:VF_128_256 3 "<round_nimm_predicate>" "v,<round_constraint>,0,xm,x")] UNSPEC_FMADDSUB))] "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F) && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>" "@ @@ -3031,6 +3099,22 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "<MODE>")]) +(define_insn "<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>" + [(set (match_operand:VF_512 0 "register_operand" "=v,v,v") + (unspec:VF_512 + [(match_operand:VF_512 1 "<round_nimm_predicate>" "%0,0,v") + (match_operand:VF_512 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>") + (match_operand:VF_512 3 "<round_nimm_predicate>" "v,<round_constraint>,0")] + UNSPEC_FMADDSUB))] + "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>" + "@ + vfmaddsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>} + vfmaddsub213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>} + vfmaddsub231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}" + [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f") + (set_attr "type" "ssemuladd") + (set_attr "mode" "<MODE>")]) + (define_insn "avx512f_fmaddsub_<mode>_mask<round_name>" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 @@ -3066,12 +3150,12 @@ (set_attr "mode" "<MODE>")]) (define_insn "<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>" - [(set (match_operand:VF 0 "register_operand" "=v,v,v,x,x") - (unspec:VF - [(match_operand:VF 1 "<round_nimm_predicate>" "%0,0,v,x,x") - (match_operand:VF 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>,x,m") - (neg:VF - (match_operand:VF 3 "<round_nimm_predicate>" "v,<round_constraint>,0,xm,x"))] + [(set (match_operand:VF_128_256 0 "register_operand" "=v,v,v,x,x") + (unspec:VF_128_256 + [(match_operand:VF_128_256 1 "<round_nimm_predicate>" "%0,0,v,x,x") + (match_operand:VF_128_256 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>,x,m") + (neg:VF_128_256 + (match_operand:VF_128_256 3 "<round_nimm_predicate>" "v,<round_constraint>,0,xm,x"))] UNSPEC_FMADDSUB))] "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F) && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>" "@ @@ -3084,6 +3168,23 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "<MODE>")]) +(define_insn "<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>" + [(set (match_operand:VF_512 0 "register_operand" "=v,v,v") + (unspec:VF_512 + [(match_operand:VF_512 1 "<round_nimm_predicate>" "%0,0,v") + (match_operand:VF_512 2 "<round_nimm_predicate>" "<round_constraint>,v,<round_constraint>") + (neg:VF_512 + (match_operand:VF_512 3 "<round_nimm_predicate>" "v,<round_constraint>,0"))] + UNSPEC_FMADDSUB))] + "TARGET_AVX512F && <sd_mask_mode512bit_condition> && <round_mode512bit_condition>" + "@ + vfmsubadd132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>} + vfmsubadd213<ssemodesuffix>\t{<round_sd_mask_op4>%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3<round_sd_mask_op4>} + vfmsubadd231<ssemodesuffix>\t{<round_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_sd_mask_op4>}" + [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f") + (set_attr "type" "ssemuladd") + (set_attr "mode" "<MODE>")]) + (define_insn "avx512f_fmsubadd_<mode>_mask<round_name>" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 diff --git a/gcc-4.9/gcc/config/mips/netbsd.h b/gcc-4.9/gcc/config/mips/netbsd.h index 0313345fd..efa28869b 100644 --- a/gcc-4.9/gcc/config/mips/netbsd.h +++ b/gcc-4.9/gcc/config/mips/netbsd.h @@ -32,7 +32,9 @@ along with GCC; see the file COPYING3. If not see if (TARGET_ABICALLS) \ builtin_define ("__ABICALLS__"); \ \ - if (mips_abi == ABI_EABI) \ + if (mips_abi == ABI_32) \ + builtin_define ("__mips_o32"); \ + else if (mips_abi == ABI_EABI) \ builtin_define ("__mips_eabi"); \ else if (mips_abi == ABI_N32) \ builtin_define ("__mips_n32"); \ diff --git a/gcc-4.9/gcc/config/moxie/moxie.h b/gcc-4.9/gcc/config/moxie/moxie.h index 5379a4311..3a01dbab4 100644 --- a/gcc-4.9/gcc/config/moxie/moxie.h +++ b/gcc-4.9/gcc/config/moxie/moxie.h @@ -59,7 +59,7 @@ #define DOUBLE_TYPE_SIZE 64 #define LONG_DOUBLE_TYPE_SIZE 64 -#define DEFAULT_SIGNED_CHAR 1 +#define DEFAULT_SIGNED_CHAR 0 #undef SIZE_TYPE #define SIZE_TYPE "unsigned int" @@ -68,7 +68,7 @@ #define PTRDIFF_TYPE "int" #undef WCHAR_TYPE -#define WCHAR_TYPE "long int" +#define WCHAR_TYPE "unsigned int" #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE BITS_PER_WORD diff --git a/gcc-4.9/gcc/config/moxie/moxie.md b/gcc-4.9/gcc/config/moxie/moxie.md index 713f9b65d..793cac3f8 100644 --- a/gcc-4.9/gcc/config/moxie/moxie.md +++ b/gcc-4.9/gcc/config/moxie/moxie.md @@ -239,6 +239,56 @@ ldo.l %0, %1" [(set_attr "length" "2,2,6,2,6,2,6,6,6")]) +(define_insn_and_split "zero_extendqisi2" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,W,A,B")))] + "" + "@ + ; + ld.b %0, %1 + lda.b %0, %1 + ldo.b %0, %1" + "reload_completed" + [(set (match_dup 2) (match_dup 1)) + (set (match_dup 0) (zero_extend:SI (match_dup 2)))] +{ + operands[2] = gen_lowpart (QImode, operands[0]); +} + [(set_attr "length" "0,2,6,6")]) + +(define_insn_and_split "zero_extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,W,A,B")))] + "" + "@ + ; + ld.s %0, %1 + lda.s %0, %1 + ldo.s %0, %1" + "reload_completed" + [(set (match_dup 2) (match_dup 1)) + (set (match_dup 0) (zero_extend:SI (match_dup 2)))] +{ + operands[2] = gen_lowpart (HImode, operands[0]); +} + [(set_attr "length" "0,2,6,6")]) + +(define_insn "extendqisi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r")))] + "" + "@ + sex.b %0, %1" + [(set_attr "length" "2")]) + +(define_insn "extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r")))] + "" + "@ + sex.s %0, %1" + [(set_attr "length" "2")]) + (define_expand "movqi" [(set (match_operand:QI 0 "general_operand" "") (match_operand:QI 1 "general_operand" ""))] diff --git a/gcc-4.9/gcc/config/nios2/linux.h b/gcc-4.9/gcc/config/nios2/linux.h index 47976f85b..3e77ca6c9 100644 --- a/gcc-4.9/gcc/config/nios2/linux.h +++ b/gcc-4.9/gcc/config/nios2/linux.h @@ -26,11 +26,16 @@ } \ while (0) +#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-nios2.so.1" + #undef LINK_SPEC #define LINK_SPEC LINK_SPEC_ENDIAN \ - " %{shared:-shared} \ - %{static:-Bstatic} \ - %{rdynamic:-export-dynamic}" + "%{shared:-shared} \ + %{!shared: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ + -dynamic-linker " GNU_USER_DYNAMIC_LINKER "} \ + %{static:-static}}" /* This toolchain implements the ABI for Linux Systems documented in the Nios II Processor Reference Handbook. */ diff --git a/gcc-4.9/gcc/config/nios2/nios2.c b/gcc-4.9/gcc/config/nios2/nios2.c index edf9a618b..cdd2e6bc9 100644 --- a/gcc-4.9/gcc/config/nios2/nios2.c +++ b/gcc-4.9/gcc/config/nios2/nios2.c @@ -695,7 +695,7 @@ nios2_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED) fprintf (file, "\taddi\tr3, r3, %%lo(_gp_got - 1b)\n"); fprintf (file, "\tadd\tr2, r2, r3\n"); fprintf (file, "\tmovhi\tr3, %%call_hiadj(_mcount)\n"); - fprintf (file, "\taddi\tr3, %%call_lo(_mcount)\n"); + fprintf (file, "\taddi\tr3, r3, %%call_lo(_mcount)\n"); fprintf (file, "\tadd\tr3, r2, r3\n"); fprintf (file, "\tldw\tr2, 0(r3)\n"); fprintf (file, "\tcallr\tr2\n"); @@ -1183,7 +1183,7 @@ nios2_unspec_offset (rtx loc, int unspec) /* Generate GOT pointer based address with large offset. */ static rtx -nios2_large_got_address (rtx sym, rtx offset) +nios2_large_got_address (rtx offset) { rtx addr = gen_reg_rtx (Pmode); emit_insn (gen_add3_insn (addr, pic_offset_table_rtx, @@ -1199,7 +1199,7 @@ nios2_got_address (rtx loc, int unspec) crtl->uses_pic_offset_table = 1; if (nios2_large_offset_p (unspec)) - return nios2_large_got_address (loc, offset); + return nios2_large_got_address (offset); return gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset); } @@ -1805,6 +1805,30 @@ nios2_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, return x; } +static rtx +nios2_delegitimize_address (rtx x) +{ + x = delegitimize_mem_from_attrs (x); + + if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == UNSPEC) + { + switch (XINT (XEXP (x, 0), 1)) + { + case UNSPEC_PIC_SYM: + case UNSPEC_PIC_CALL_SYM: + case UNSPEC_PIC_GOTOFF_SYM: + case UNSPEC_ADD_TLS_GD: + case UNSPEC_ADD_TLS_LDM: + case UNSPEC_LOAD_TLS_IE: + case UNSPEC_ADD_TLS_LE: + x = XVECEXP (XEXP (x, 0), 0, 0); + gcc_assert (GET_CODE (x) == SYMBOL_REF); + break; + } + } + return x; +} + /* Main expander function for RTL moves. */ int nios2_emit_move_sequence (rtx *operands, enum machine_mode mode) @@ -3259,6 +3283,9 @@ nios2_merge_decl_attributes (tree olddecl, tree newdecl) #undef TARGET_LEGITIMIZE_ADDRESS #define TARGET_LEGITIMIZE_ADDRESS nios2_legitimize_address +#undef TARGET_DELEGITIMIZE_ADDRESS +#define TARGET_DELEGITIMIZE_ADDRESS nios2_delegitimize_address + #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P nios2_legitimate_address_p diff --git a/gcc-4.9/gcc/config/nios2/nios2.md b/gcc-4.9/gcc/config/nios2/nios2.md index b5b599ece..929d61e1f 100644 --- a/gcc-4.9/gcc/config/nios2/nios2.md +++ b/gcc-4.9/gcc/config/nios2/nios2.md @@ -74,8 +74,6 @@ UNSPEC_PIC_SYM UNSPEC_PIC_CALL_SYM UNSPEC_PIC_GOTOFF_SYM - UNSPEC_TLS - UNSPEC_TLS_LDM UNSPEC_LOAD_TLS_IE UNSPEC_ADD_TLS_LE UNSPEC_ADD_TLS_GD diff --git a/gcc-4.9/gcc/config/pa/pa.c b/gcc-4.9/gcc/config/pa/pa.c index fb698d20d..871e4e5c6 100644 --- a/gcc-4.9/gcc/config/pa/pa.c +++ b/gcc-4.9/gcc/config/pa/pa.c @@ -4187,13 +4187,17 @@ pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) if (TARGET_SOM && TARGET_GAS) { - /* We done with this subspace except possibly for some additional + /* We are done with this subspace except possibly for some additional debug information. Forget that we are in this subspace to ensure that the next function is output in its own subspace. */ in_section = NULL; cfun->machine->in_nsubspa = 2; } + /* Thunks do their own accounting. */ + if (cfun->is_thunk) + return; + if (INSN_ADDRESSES_SET_P ()) { insn = get_last_nonnote_insn (); @@ -8259,8 +8263,7 @@ pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0); xoperands[2] = GEN_INT (delta); - ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0)); - fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n"); + final_start_function (emit_barrier (), file, 1); /* Output the thunk. We know that the function is in the same translation unit (i.e., the same space) as the thunk, and that @@ -8466,16 +8469,7 @@ pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, } } - fprintf (file, "\t.EXIT\n\t.PROCEND\n"); - - if (TARGET_SOM && TARGET_GAS) - { - /* We done with this subspace except possibly for some additional - debug information. Forget that we are in this subspace to ensure - that the next function is output in its own subspace. */ - in_section = NULL; - cfun->machine->in_nsubspa = 2; - } + final_end_function (); if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) { diff --git a/gcc-4.9/gcc/config/rl78/rl78-expand.md b/gcc-4.9/gcc/config/rl78/rl78-expand.md index f794d7cb1..f61e444b5 100644 --- a/gcc-4.9/gcc/config/rl78/rl78-expand.md +++ b/gcc-4.9/gcc/config/rl78/rl78-expand.md @@ -30,18 +30,23 @@ if (rl78_far_p (operands[0]) && rl78_far_p (operands[1])) operands[1] = copy_to_mode_reg (QImode, operands[1]); - /* FIXME: Not sure how GCC can generate (SUBREG (SYMBOL_REF)), - but it does. Since this makes no sense, reject it here. */ + /* GCC can generate (SUBREG (SYMBOL_REF)) when it has to store a symbol + into a bitfield, or a packed ordinary field. We can handle this + provided that the destination is a register. If not, then load the + source into a register first. */ if (GET_CODE (operands[1]) == SUBREG - && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) - FAIL; + && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF + && ! REG_P (operands[0])) + operands[1] = copy_to_mode_reg (QImode, operands[1]); + /* Similarly for (SUBREG (CONST (PLUS (SYMBOL_REF)))). cf. g++.dg/abi/packed.C. */ if (GET_CODE (operands[1]) == SUBREG && GET_CODE (XEXP (operands[1], 0)) == CONST && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == PLUS - && GET_CODE (XEXP (XEXP (XEXP (operands[1], 0), 0), 0)) == SYMBOL_REF) - FAIL; + && GET_CODE (XEXP (XEXP (XEXP (operands[1], 0), 0), 0)) == SYMBOL_REF + && ! REG_P (operands[0])) + operands[1] = copy_to_mode_reg (QImode, operands[1]); if (CONST_INT_P (operands[1]) && ! IN_RANGE (INTVAL (operands[1]), (-1 << 8) + 1, (1 << 8) - 1)) FAIL; diff --git a/gcc-4.9/gcc/config/rs6000/altivec.h b/gcc-4.9/gcc/config/rs6000/altivec.h index 49c250c84..129cf6fa1 100644 --- a/gcc-4.9/gcc/config/rs6000/altivec.h +++ b/gcc-4.9/gcc/config/rs6000/altivec.h @@ -319,6 +319,11 @@ #define vec_sqrt __builtin_vec_sqrt #define vec_vsx_ld __builtin_vec_vsx_ld #define vec_vsx_st __builtin_vec_vsx_st + +/* Note, xxsldi and xxpermdi were added as __builtin_vsx_<xxx> functions + instead of __builtin_vec_<xxx> */ +#define vec_xxsldwi __builtin_vsx_xxsldwi +#define vec_xxpermdi __builtin_vsx_xxpermdi #endif #ifdef _ARCH_PWR8 @@ -329,6 +334,7 @@ #define vec_vaddcuq __builtin_vec_vaddcuq #define vec_vaddudm __builtin_vec_vaddudm #define vec_vadduqm __builtin_vec_vadduqm +#define vec_vbpermq __builtin_vec_vbpermq #define vec_vclz __builtin_vec_vclz #define vec_vclzb __builtin_vec_vclzb #define vec_vclzd __builtin_vec_vclzd diff --git a/gcc-4.9/gcc/config/rs6000/altivec.md b/gcc-4.9/gcc/config/rs6000/altivec.md index faa88d007..674cb40bf 100644 --- a/gcc-4.9/gcc/config/rs6000/altivec.md +++ b/gcc-4.9/gcc/config/rs6000/altivec.md @@ -142,6 +142,7 @@ UNSPEC_VSUBCUQ UNSPEC_VSUBEUQM UNSPEC_VSUBECUQ + UNSPEC_VBPERMQ ]) (define_c_enum "unspecv" @@ -3322,3 +3323,14 @@ [(set_attr "length" "4") (set_attr "type" "vecsimple")]) +;; We use V2DI as the output type to simplify converting the permute +;; bits into an integer +(define_insn "altivec_vbpermq" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] + UNSPEC_VBPERMQ))] + "TARGET_P8_VECTOR" + "vbpermq %0,%1,%2" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) diff --git a/gcc-4.9/gcc/config/rs6000/constraints.md b/gcc-4.9/gcc/config/rs6000/constraints.md index 50fb101e8..9d6a3bbe7 100644 --- a/gcc-4.9/gcc/config/rs6000/constraints.md +++ b/gcc-4.9/gcc/config/rs6000/constraints.md @@ -106,6 +106,11 @@ (define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]" "Floating point register if the LFIWZX instruction is enabled or NO_REGS.") +(define_constraint "wD" + "Int constant that is the element number of the 64-bit scalar in a vector." + (and (match_code "const_int") + (match_test "TARGET_VSX && (ival == VECTOR_ELEMENT_SCALAR_64BIT)"))) + ;; Lq/stq validates the address for load/store quad (define_memory_constraint "wQ" "Memory operand suitable for the load/store quad instructions" diff --git a/gcc-4.9/gcc/config/rs6000/predicates.md b/gcc-4.9/gcc/config/rs6000/predicates.md index 7b1121ddb..28f4f5d98 100644 --- a/gcc-4.9/gcc/config/rs6000/predicates.md +++ b/gcc-4.9/gcc/config/rs6000/predicates.md @@ -981,6 +981,14 @@ (ior (match_operand 0 "zero_fp_constant") (match_operand 0 "reg_or_mem_operand"))) +;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit +;; data types inside of a vector that scalar instructions operate on +(define_predicate "vsx_scalar_64bit" + (match_code "const_int") +{ + return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT); +}) + ;; Return 1 if the operand is a general register or memory operand without ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC ;; lwa instruction. diff --git a/gcc-4.9/gcc/config/rs6000/rs6000-builtin.def b/gcc-4.9/gcc/config/rs6000/rs6000-builtin.def index 9226035a3..83351691f 100644 --- a/gcc-4.9/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc-4.9/gcc/config/rs6000/rs6000-builtin.def @@ -1374,6 +1374,7 @@ BU_P8V_AV_2 (VMINUD, "vminud", CONST, uminv2di3) BU_P8V_AV_2 (VMAXUD, "vmaxud", CONST, umaxv2di3) BU_P8V_AV_2 (VMRGEW, "vmrgew", CONST, p8_vmrgew) BU_P8V_AV_2 (VMRGOW, "vmrgow", CONST, p8_vmrgow) +BU_P8V_AV_2 (VBPERMQ, "vbpermq", CONST, altivec_vbpermq) BU_P8V_AV_2 (VPKUDUM, "vpkudum", CONST, altivec_vpkudum) BU_P8V_AV_2 (VPKSDSS, "vpksdss", CONST, altivec_vpksdss) BU_P8V_AV_2 (VPKUDUS, "vpkudus", CONST, altivec_vpkudus) @@ -1448,6 +1449,7 @@ BU_P8V_OVERLOAD_2 (ORC, "orc") BU_P8V_OVERLOAD_2 (VADDCUQ, "vaddcuq") BU_P8V_OVERLOAD_2 (VADDUDM, "vaddudm") BU_P8V_OVERLOAD_2 (VADDUQM, "vadduqm") +BU_P8V_OVERLOAD_2 (VBPERMQ, "vbpermq") BU_P8V_OVERLOAD_2 (VMAXSD, "vmaxsd") BU_P8V_OVERLOAD_2 (VMAXUD, "vmaxud") BU_P8V_OVERLOAD_2 (VMINSD, "vminsd") diff --git a/gcc-4.9/gcc/config/rs6000/rs6000-c.c b/gcc-4.9/gcc/config/rs6000/rs6000-c.c index 0f1dafc5a..46c4a9d8c 100644 --- a/gcc-4.9/gcc/config/rs6000/rs6000-c.c +++ b/gcc-4.9/gcc/config/rs6000/rs6000-c.c @@ -3778,6 +3778,12 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0 }, + { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, + RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, + { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V16QI, 0 }, + { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, diff --git a/gcc-4.9/gcc/config/rs6000/rs6000.c b/gcc-4.9/gcc/config/rs6000/rs6000.c index fc837352c..494efc562 100644 --- a/gcc-4.9/gcc/config/rs6000/rs6000.c +++ b/gcc-4.9/gcc/config/rs6000/rs6000.c @@ -2310,6 +2310,10 @@ rs6000_debug_reg_global (void) (int)END_BUILTINS); fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins", (int)RS6000_BUILTIN_COUNT); + + if (TARGET_VSX) + fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit scalar element", + (int)VECTOR_ELEMENT_SCALAR_64BIT); } @@ -5632,11 +5636,15 @@ rs6000_expand_vector_set (rtx target, rtx val, int elt) UNSPEC_VPERM); else { - /* Invert selector. */ + /* Invert selector. We prefer to generate VNAND on P8 so + that future fusion opportunities can kick in, but must + generate VNOR elsewhere. */ rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x)); - rtx andx = gen_rtx_AND (V16QImode, notx, notx); + rtx iorx = (TARGET_P8_VECTOR + ? gen_rtx_IOR (V16QImode, notx, notx) + : gen_rtx_AND (V16QImode, notx, notx)); rtx tmp = gen_reg_rtx (V16QImode); - emit_move_insn (tmp, andx); + emit_insn (gen_rtx_SET (VOIDmode, tmp, iorx)); /* Permute with operands reversed and adjusted selector. */ x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp), @@ -30209,12 +30217,12 @@ altivec_expand_vec_perm_const_le (rtx operands[4]) /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the permute control vector. But here it's not a constant, so we must - generate a vector NOR to do the adjustment. */ + generate a vector NAND or NOR to do the adjustment. */ void altivec_expand_vec_perm_le (rtx operands[4]) { - rtx notx, andx, unspec; + rtx notx, iorx, unspec; rtx target = operands[0]; rtx op0 = operands[1]; rtx op1 = operands[2]; @@ -30233,10 +30241,13 @@ altivec_expand_vec_perm_le (rtx operands[4]) if (!REG_P (target)) tmp = gen_reg_rtx (mode); - /* Invert the selector with a VNOR. */ + /* Invert the selector with a VNAND if available, else a VNOR. + The VNAND is preferred for future fusion opportunities. */ notx = gen_rtx_NOT (V16QImode, sel); - andx = gen_rtx_AND (V16QImode, notx, notx); - emit_move_insn (norreg, andx); + iorx = (TARGET_P8_VECTOR + ? gen_rtx_IOR (V16QImode, notx, notx) + : gen_rtx_AND (V16QImode, notx, notx)); + emit_insn (gen_rtx_SET (VOIDmode, norreg, iorx)); /* Permute with operands reversed and adjusted selector. */ unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg), @@ -32519,6 +32530,11 @@ fusion_gpr_load_p (rtx *operands, bool peep2_p) if (!peep2_reg_dead_p (2, addis_reg)) return false; + + /* If the target register being loaded is the stack pointer, we must + avoid loading any other value into it, even temporarily. */ + if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM) + return false; } base_reg = XEXP (addr, 0); diff --git a/gcc-4.9/gcc/config/rs6000/rs6000.h b/gcc-4.9/gcc/config/rs6000/rs6000.h index a6afb6c37..9ec3647fe 100644 --- a/gcc-4.9/gcc/config/rs6000/rs6000.h +++ b/gcc-4.9/gcc/config/rs6000/rs6000.h @@ -477,6 +477,10 @@ extern int rs6000_vector_align[]; #define VECTOR_ELT_ORDER_BIG \ (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) +/* Element number of the 64-bit value in a 128-bit vector that can be accessed + with scalar instructions. */ +#define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) + /* Alignment options for fields in structures for sub-targets following AIX-like ABI. ALIGN_POWER word-aligns FP doubles (default AIX ABI). diff --git a/gcc-4.9/gcc/config/rs6000/rs6000.md b/gcc-4.9/gcc/config/rs6000/rs6000.md index 4bab9591e..64c9e7c10 100644 --- a/gcc-4.9/gcc/config/rs6000/rs6000.md +++ b/gcc-4.9/gcc/config/rs6000/rs6000.md @@ -10028,13 +10028,16 @@ rtx op0 = operands[0]; rtx op1 = operands[1]; rtx op2 = operands[2]; - rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0); + /* Also use the destination register to hold the unconverted DImode value. + This is conceptually a separate value from OP0, so we use gen_rtx_REG + rather than simplify_gen_subreg. */ + rtx op0_di = gen_rtx_REG (DImode, REGNO (op0)); rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0); /* Move SF value to upper 32-bits for xscvspdpn. */ emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32))); emit_move_insn (op0_di, op2); - emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); + emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di)); DONE; } [(set_attr "length" "8") diff --git a/gcc-4.9/gcc/config/rs6000/vsx.md b/gcc-4.9/gcc/config/rs6000/vsx.md index 93c8c3b29..d83cdc3df 100644 --- a/gcc-4.9/gcc/config/rs6000/vsx.md +++ b/gcc-4.9/gcc/config/rs6000/vsx.md @@ -1223,7 +1223,7 @@ ;; Used by direct move to move a SFmode value from GPR to VSX register (define_insn "vsx_xscvspdpn_directmove" [(set (match_operand:SF 0 "vsx_register_operand" "=wa") - (unspec:SF [(match_operand:SF 1 "vsx_register_operand" "wa")] + (unspec:SF [(match_operand:DI 1 "vsx_register_operand" "wa")] UNSPEC_VSX_CVSPDPN))] "TARGET_XSCVSPDPN" "xscvspdpn %x0,%x1" @@ -1531,52 +1531,129 @@ [(set_attr "type" "vecperm")]) ;; Extract a DF/DI element from V2DF/V2DI -(define_insn "vsx_extract_<mode>" - [(set (match_operand:<VS_scalar> 0 "vsx_register_operand" "=ws,d,?wa") - (vec_select:<VS_scalar> (match_operand:VSX_D 1 "vsx_register_operand" "wd,wd,wa") +(define_expand "vsx_extract_<mode>" + [(set (match_operand:<VS_scalar> 0 "register_operand" "") + (vec_select:<VS_scalar> (match_operand:VSX_D 1 "register_operand" "") (parallel - [(match_operand:QI 2 "u5bit_cint_operand" "i,i,i")])))] + [(match_operand:QI 2 "u5bit_cint_operand" "")])))] "VECTOR_MEM_VSX_P (<MODE>mode)" + "") + +;; Optimize cases were we can do a simple or direct move. +;; Or see if we can avoid doing the move at all +(define_insn "*vsx_extract_<mode>_internal1" + [(set (match_operand:<VS_scalar> 0 "register_operand" "=d,ws,?wa,r") + (vec_select:<VS_scalar> + (match_operand:VSX_D 1 "register_operand" "d,wd,wa,wm") + (parallel + [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD,wD")])))] + "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64 && TARGET_DIRECT_MOVE" +{ + int op0_regno = REGNO (operands[0]); + int op1_regno = REGNO (operands[1]); + + if (op0_regno == op1_regno) + return "nop"; + + if (INT_REGNO_P (op0_regno)) + return "mfvsrd %0,%x1"; + + if (FP_REGNO_P (op0_regno) && FP_REGNO_P (op1_regno)) + return "fmr %0,%1"; + + return "xxlor %x0,%x1,%x1"; +} + [(set_attr "type" "fp,vecsimple,vecsimple,mftgpr") + (set_attr "length" "4")]) + +(define_insn "*vsx_extract_<mode>_internal2" + [(set (match_operand:<VS_scalar> 0 "vsx_register_operand" "=d,ws,ws,?wa") + (vec_select:<VS_scalar> + (match_operand:VSX_D 1 "vsx_register_operand" "d,wd,wd,wa") + (parallel [(match_operand:QI 2 "u5bit_cint_operand" "wD,wD,i,i")])))] + "VECTOR_MEM_VSX_P (<MODE>mode) + && (!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE + || INTVAL (operands[2]) != VECTOR_ELEMENT_SCALAR_64BIT)" { int fldDM; gcc_assert (UINTVAL (operands[2]) <= 1); + + if (INTVAL (operands[2]) == VECTOR_ELEMENT_SCALAR_64BIT) + { + int op0_regno = REGNO (operands[0]); + int op1_regno = REGNO (operands[1]); + + if (op0_regno == op1_regno) + return "nop"; + + if (FP_REGNO_P (op0_regno) && FP_REGNO_P (op1_regno)) + return "fmr %0,%1"; + + return "xxlor %x0,%x1,%x1"; + } + fldDM = INTVAL (operands[2]) << 1; if (!BYTES_BIG_ENDIAN) fldDM = 3 - fldDM; operands[3] = GEN_INT (fldDM); - return \"xxpermdi %x0,%x1,%x1,%3\"; + return "xxpermdi %x0,%x1,%x1,%3"; } - [(set_attr "type" "vecperm")]) + [(set_attr "type" "fp,vecsimple,vecperm,vecperm") + (set_attr "length" "4")]) -;; Optimize extracting element 0 from memory -(define_insn "*vsx_extract_<mode>_zero" - [(set (match_operand:<VS_scalar> 0 "vsx_register_operand" "=ws,d,?wa") +;; Optimize extracting a single scalar element from memory if the scalar is in +;; the correct location to use a single load. +(define_insn "*vsx_extract_<mode>_load" + [(set (match_operand:<VS_scalar> 0 "register_operand" "=d,wv,wr") (vec_select:<VS_scalar> - (match_operand:VSX_D 1 "indexed_or_indirect_operand" "Z,Z,Z") - (parallel [(const_int 0)])))] - "VECTOR_MEM_VSX_P (<MODE>mode) && WORDS_BIG_ENDIAN" - "lxsd%U1x %x0,%y1" - [(set (attr "type") - (if_then_else - (match_test "update_indexed_address_mem (operands[1], VOIDmode)") - (const_string "fpload_ux") - (const_string "fpload"))) - (set_attr "length" "4")]) - -;; Optimize extracting element 1 from memory for little endian -(define_insn "*vsx_extract_<mode>_one_le" - [(set (match_operand:<VS_scalar> 0 "vsx_register_operand" "=ws,d,?wa") + (match_operand:VSX_D 1 "memory_operand" "m,Z,m") + (parallel [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))] + "VECTOR_MEM_VSX_P (<MODE>mode)" + "@ + lfd%U1%X1 %0,%1 + lxsd%U1x %x0,%y1 + ld%U1%X1 %0,%1" + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "fpload_u") + (const_string "fpload"))) + (const_string "fpload") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load")))]) + (set_attr "length" "4")]) + +;; Optimize storing a single scalar element that is the right location to +;; memory +(define_insn "*vsx_extract_<mode>_store" + [(set (match_operand:<VS_scalar> 0 "memory_operand" "=m,Z,?Z") (vec_select:<VS_scalar> - (match_operand:VSX_D 1 "indexed_or_indirect_operand" "Z,Z,Z") - (parallel [(const_int 1)])))] - "VECTOR_MEM_VSX_P (<MODE>mode) && !WORDS_BIG_ENDIAN" - "lxsd%U1x %x0,%y1" - [(set (attr "type") - (if_then_else - (match_test "update_indexed_address_mem (operands[1], VOIDmode)") - (const_string "fpload_ux") - (const_string "fpload"))) - (set_attr "length" "4")]) + (match_operand:VSX_D 1 "register_operand" "d,wd,wa") + (parallel [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))] + "VECTOR_MEM_VSX_P (<MODE>mode)" + "@ + stfd%U0%X0 %1,%0 + stxsd%U0x %x1,%y0 + stxsd%U0x %x1,%y0" + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_u") + (const_string "fpstore"))) + (const_string "fpstore") + (const_string "fpstore")]) + (set_attr "length" "4")]) ;; Extract a SF element from V4SF (define_insn_and_split "vsx_extract_v4sf" diff --git a/gcc-4.9/gcc/config/s390/s390.c b/gcc-4.9/gcc/config/s390/s390.c index 7a79286c9..aac8de848 100644 --- a/gcc-4.9/gcc/config/s390/s390.c +++ b/gcc-4.9/gcc/config/s390/s390.c @@ -4613,7 +4613,7 @@ s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src) int smode_bsize, mode_bsize; rtx op, clobber; - if (bitsize + bitpos > GET_MODE_SIZE (mode)) + if (bitsize + bitpos > GET_MODE_BITSIZE (mode)) return false; /* Generate INSERT IMMEDIATE (IILL et al). */ @@ -9225,6 +9225,13 @@ s390_can_use_return_insn (void) if (cfun_gpr_save_slot (i)) return false; + /* For 31 bit this is not covered by the frame_size check below + since f4, f6 are saved in the register save area without needing + additional stack space. */ + if (!TARGET_64BIT + && (cfun_fpr_save_p (FPR4_REGNUM) || cfun_fpr_save_p (FPR6_REGNUM))) + return false; + if (cfun->machine->base_reg && !call_really_used_regs[REGNO (cfun->machine->base_reg)]) return false; diff --git a/gcc-4.9/gcc/config/s390/s390.md b/gcc-4.9/gcc/config/s390/s390.md index 7d9d1ad7e..b17c1fac8 100644 --- a/gcc-4.9/gcc/config/s390/s390.md +++ b/gcc-4.9/gcc/config/s390/s390.md @@ -7001,6 +7001,21 @@ "" "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") +; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing +; simplifications. So its better to have something matching. +(define_split + [(set (match_operand:INT 0 "nonimmediate_operand" "") + (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] + "" + [(parallel + [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) + (clobber (reg:CC CC_REGNUM))])] +{ + operands[2] = constm1_rtx; + if (!s390_logical_operator_ok_p (operands)) + FAIL; +}) + ; ; xordi3 instruction pattern(s). ; diff --git a/gcc-4.9/gcc/config/spu/spu.c b/gcc-4.9/gcc/config/spu/spu.c index 302d7e06b..88e3f5e59 100644 --- a/gcc-4.9/gcc/config/spu/spu.c +++ b/gcc-4.9/gcc/config/spu/spu.c @@ -2064,7 +2064,7 @@ pad_bb(void) } hbr_insn = insn; } - if (INSN_CODE (insn) == CODE_FOR_blockage) + if (INSN_CODE (insn) == CODE_FOR_blockage && next_insn) { if (GET_MODE (insn) == TImode) PUT_MODE (next_insn, TImode); diff --git a/gcc-4.9/gcc/config/spu/spu.md b/gcc-4.9/gcc/config/spu/spu.md index 228b22859..3ac4bfc0b 100644 --- a/gcc-4.9/gcc/config/spu/spu.md +++ b/gcc-4.9/gcc/config/spu/spu.md @@ -2851,7 +2851,13 @@ (match_operand:SI 2 "const_int_operand" "")) (match_operand 3 "nonmemory_operand" ""))] "" - { spu_expand_insv(operands); DONE; }) + { + if (INTVAL (operands[1]) + INTVAL (operands[2]) + > GET_MODE_BITSIZE (GET_MODE (operands[0]))) + FAIL; + spu_expand_insv(operands); + DONE; + }) ;; Simplify a number of patterns that get generated by extv, extzv, ;; insv, and loads. |