aboutsummaryrefslogtreecommitdiffstats
path: root/gcc-4.9/gcc/config/tilegx/tilegx.opt
diff options
context:
space:
mode:
authorBen Cheng <bccheng@google.com>2014-03-25 22:37:19 -0700
committerBen Cheng <bccheng@google.com>2014-03-25 22:37:19 -0700
commit1bc5aee63eb72b341f506ad058502cd0361f0d10 (patch)
treec607e8252f3405424ff15bc2d00aa38dadbb2518 /gcc-4.9/gcc/config/tilegx/tilegx.opt
parent283a0bf58fcf333c58a2a92c3ebbc41fb9eb1fdb (diff)
downloadtoolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.tar.gz
toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.tar.bz2
toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.zip
Initial checkin of GCC 4.9.0 from trunk (r208799).
Change-Id: I48a3c08bb98542aa215912a75f03c0890e497dba
Diffstat (limited to 'gcc-4.9/gcc/config/tilegx/tilegx.opt')
-rw-r--r--gcc-4.9/gcc/config/tilegx/tilegx.opt63
1 files changed, 63 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/config/tilegx/tilegx.opt b/gcc-4.9/gcc/config/tilegx/tilegx.opt
new file mode 100644
index 000000000..37c12fe1f
--- /dev/null
+++ b/gcc-4.9/gcc/config/tilegx/tilegx.opt
@@ -0,0 +1,63 @@
+; Options for the TILE-Gx port of the compiler.
+; Copyright (C) 2011-2014 Free Software Foundation, Inc.
+; Contributed by Walter Lee (walt@tilera.com)
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 3, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+; for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING3. If not see
+; <http://www.gnu.org/licenses/>.
+
+HeaderInclude
+config/tilegx/tilegx-opts.h
+
+mcpu=
+Target RejectNegative Joined Enum(tilegx_cpu) Var(tilegx_cpu) Init(0)
+-mcpu=CPU Use features of and schedule code for given CPU
+
+Enum
+Name(tilegx_cpu) Type(int)
+Known TILE-Gx CPUs (for use with the -mcpu= option):
+
+EnumValue
+Enum(tilegx_cpu) String(tilegx) Value(0)
+
+m32
+Target Report RejectNegative Negative(m64) Mask(32BIT)
+Compile with 32 bit longs and pointers.
+
+m64
+Target Report RejectNegative Negative(m32) InverseMask(32BIT, 64BIT)
+Compile with 64 bit longs and pointers.
+
+mbig-endian
+Target Report RejectNegative Mask(BIG_ENDIAN)
+Use big-endian byte order.
+
+mlittle-endian
+Target Report RejectNegative InverseMask(BIG_ENDIAN)
+Use little-endian byte order.
+
+mcmodel=
+Target RejectNegative Joined Enum(cmodel) Var(tilegx_cmodel) Init(CM_SMALL)
+Use given TILE-Gx code model
+
+Enum
+Name(cmodel) Type(enum cmodel)
+Known code models (for use with the -mcmodel= option):
+
+EnumValue
+Enum(cmodel) String(small) Value(CM_SMALL)
+
+EnumValue
+Enum(cmodel) String(large) Value(CM_LARGE)