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| author | Rong Xu <xur@google.com> | 2014-09-02 15:29:57 -0700 |
|---|---|---|
| committer | Rong Xu <xur@google.com> | 2014-09-02 15:29:57 -0700 |
| commit | e97c99f15937e5762a973b25192aab824126a6d3 (patch) | |
| tree | 7f0be3ff7c7d976af06887dc50accd68f7630a7f /gcc-4.9/gcc/config/rs6000/constraints.md | |
| parent | f1c18afafc2b321465ae6b07ede127095942d7dc (diff) | |
| download | toolchain_gcc-e97c99f15937e5762a973b25192aab824126a6d3.tar.gz toolchain_gcc-e97c99f15937e5762a973b25192aab824126a6d3.tar.bz2 toolchain_gcc-e97c99f15937e5762a973b25192aab824126a6d3.zip | |
[gcc-4.9] Merge svn r214745 from google/gcc-4_9 branch.
Merge gcc-4_9 source r214745 from google/gcc-4_9 branch.
Change-Id: Ie6fa0fd72f4b4eec3adc4db4bb922e652d1c2605
Diffstat (limited to 'gcc-4.9/gcc/config/rs6000/constraints.md')
| -rw-r--r-- | gcc-4.9/gcc/config/rs6000/constraints.md | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/gcc-4.9/gcc/config/rs6000/constraints.md b/gcc-4.9/gcc/config/rs6000/constraints.md index 9d6a3bbe7..78a3ff0d2 100644 --- a/gcc-4.9/gcc/config/rs6000/constraints.md +++ b/gcc-4.9/gcc/config/rs6000/constraints.md @@ -68,6 +68,20 @@ (define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" "If -mmfpgpr was used, a floating point register or NO_REGS.") +(define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]" + "Floating point register if direct moves are available, or NO_REGS.") + +;; At present, DImode is not allowed in the Altivec registers. If in the +;; future it is allowed, wi/wj can be set to VSX_REGS instead of FLOAT_REGS. +(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" + "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.") + +(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]" + "FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.") + +(define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]" + "FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.") + (define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]" "Floating point register if the LFIWAX instruction is enabled or NO_REGS.") @@ -101,7 +115,7 @@ "Floating point register if the STFIWX instruction is enabled or NO_REGS.") (define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]" - "VSX vector register to hold scalar float values or NO_REGS.") + "FP or VSX register to perform ISA 2.07 float ops or NO_REGS.") (define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]" "Floating point register if the LFIWZX instruction is enabled or NO_REGS.") |