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| author | Rong Xu <xur@google.com> | 2014-09-02 15:29:57 -0700 |
|---|---|---|
| committer | Rong Xu <xur@google.com> | 2014-09-02 15:29:57 -0700 |
| commit | e97c99f15937e5762a973b25192aab824126a6d3 (patch) | |
| tree | 7f0be3ff7c7d976af06887dc50accd68f7630a7f /gcc-4.9/gcc/config/i386/i386.c | |
| parent | f1c18afafc2b321465ae6b07ede127095942d7dc (diff) | |
| download | toolchain_gcc-e97c99f15937e5762a973b25192aab824126a6d3.tar.gz toolchain_gcc-e97c99f15937e5762a973b25192aab824126a6d3.tar.bz2 toolchain_gcc-e97c99f15937e5762a973b25192aab824126a6d3.zip | |
[gcc-4.9] Merge svn r214745 from google/gcc-4_9 branch.
Merge gcc-4_9 source r214745 from google/gcc-4_9 branch.
Change-Id: Ie6fa0fd72f4b4eec3adc4db4bb922e652d1c2605
Diffstat (limited to 'gcc-4.9/gcc/config/i386/i386.c')
| -rw-r--r-- | gcc-4.9/gcc/config/i386/i386.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/gcc-4.9/gcc/config/i386/i386.c b/gcc-4.9/gcc/config/i386/i386.c index 70f18ad7b..85ceff337 100644 --- a/gcc-4.9/gcc/config/i386/i386.c +++ b/gcc-4.9/gcc/config/i386/i386.c @@ -3259,12 +3259,13 @@ ix86_option_override_internal (bool main_args_p, | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE}, {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4, - PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 - | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 - | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 + | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2 | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR - | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE}, + | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND + | PTA_MOVBE}, {"btver1", PROCESSOR_BTVER1, CPU_GENERIC, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW @@ -45348,8 +45349,10 @@ ix86_expand_sse2_mulvxdi3 (rtx op0, rtx op1, rtx op2) /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */ emit_insn (gen_ashlv2di3 (t4, t3, GEN_INT (32))); - /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */ - emit_insn (gen_xop_pmacsdql (op0, op1, op2, t4)); + /* Multiply lower parts and add all */ + t5 = gen_reg_rtx (V2DImode); + emit_insn (gen_vec_widen_umult_even_v4si (t5, gen_lowpart (V4SImode, op1), gen_lowpart (V4SImode, op2))); + op0 = expand_binop (mode, add_optab, t5, t4, op0, 1, OPTAB_DIRECT); } else { |