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author | Ben Cheng <bccheng@google.com> | 2014-04-22 13:33:12 -0700 |
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committer | Ben Cheng <bccheng@google.com> | 2014-04-22 13:33:12 -0700 |
commit | e3cc64dec20832769406aa38cde83c7dd4194bf4 (patch) | |
tree | ef8e39be37cfe0cb69d850043b7924389ff17164 /gcc-4.9/gcc/config/aarch64 | |
parent | f33c7b3122b1d7950efa88067c9a156229ba647b (diff) | |
download | toolchain_gcc-e3cc64dec20832769406aa38cde83c7dd4194bf4.tar.gz toolchain_gcc-e3cc64dec20832769406aa38cde83c7dd4194bf4.tar.bz2 toolchain_gcc-e3cc64dec20832769406aa38cde83c7dd4194bf4.zip |
[4.9] GCC 4.9.0 official release refresh
Change-Id: Ic99a7da8b44b789a48aeec93b33e93944d6e6767
Diffstat (limited to 'gcc-4.9/gcc/config/aarch64')
-rw-r--r-- | gcc-4.9/gcc/config/aarch64/aarch64-simd.md | 4 | ||||
-rw-r--r-- | gcc-4.9/gcc/config/aarch64/aarch64.c | 72 |
2 files changed, 27 insertions, 49 deletions
diff --git a/gcc-4.9/gcc/config/aarch64/aarch64-simd.md b/gcc-4.9/gcc/config/aarch64/aarch64-simd.md index 6048d605c..73aee2c3d 100644 --- a/gcc-4.9/gcc/config/aarch64/aarch64-simd.md +++ b/gcc-4.9/gcc/config/aarch64/aarch64-simd.md @@ -4250,7 +4250,7 @@ CRYPTO_AES))] "TARGET_SIMD && TARGET_CRYPTO" "aes<aes_op>\\t%0.16b, %2.16b" - [(set_attr "type" "crypto_aes")] + [(set_attr "type" "crypto_aese")] ) (define_insn "aarch64_crypto_aes<aesmc_op>v16qi" @@ -4259,7 +4259,7 @@ CRYPTO_AESMC))] "TARGET_SIMD && TARGET_CRYPTO" "aes<aesmc_op>\\t%0.16b, %1.16b" - [(set_attr "type" "crypto_aes")] + [(set_attr "type" "crypto_aesmc")] ) ;; sha1 diff --git a/gcc-4.9/gcc/config/aarch64/aarch64.c b/gcc-4.9/gcc/config/aarch64/aarch64.c index ebd58c007..7b6c2b38e 100644 --- a/gcc-4.9/gcc/config/aarch64/aarch64.c +++ b/gcc-4.9/gcc/config/aarch64/aarch64.c @@ -315,10 +315,6 @@ static GTY(()) int gty_dummy; #define AARCH64_NUM_BITMASKS 5334 static unsigned HOST_WIDE_INT aarch64_bitmasks[AARCH64_NUM_BITMASKS]; -/* Did we set flag_omit_frame_pointer just so - aarch64_frame_pointer_required would be called? */ -static bool faked_omit_frame_pointer; - typedef enum aarch64_cond_code { AARCH64_EQ = 0, AARCH64_NE, AARCH64_CS, AARCH64_CC, AARCH64_MI, AARCH64_PL, @@ -1694,17 +1690,15 @@ aarch64_frame_pointer_required (void) if (cfun->calls_alloca) return true; - /* We may have turned flag_omit_frame_pointer on in order to have this - function called; if we did, we also set the 'faked_omit_frame_pointer' flag - and we'll check it here. - If we really did set flag_omit_frame_pointer normally, then we return false - (no frame pointer required) in all cases. */ + /* In aarch64_override_options_after_change + flag_omit_leaf_frame_pointer turns off the frame pointer by + default. Turn it back on now if we've not got a leaf + function. */ + if (flag_omit_leaf_frame_pointer + && (!crtl->is_leaf || df_regs_ever_live_p (LR_REGNUM))) + return true; - if (flag_omit_frame_pointer && !faked_omit_frame_pointer) - return false; - else if (flag_omit_leaf_frame_pointer) - return !crtl->is_leaf || df_regs_ever_live_p (LR_REGNUM); - return true; + return false; } /* Mark the registers that need to be saved by the callee and calculate @@ -3202,6 +3196,9 @@ aarch64_classify_address (struct aarch64_address_info *info, } else if (SYMBOL_REF_DECL (sym)) align = DECL_ALIGN (SYMBOL_REF_DECL (sym)); + else if (SYMBOL_REF_HAS_BLOCK_INFO_P (sym) + && SYMBOL_REF_BLOCK (sym) != NULL) + align = SYMBOL_REF_BLOCK (sym)->alignment; else align = BITS_PER_UNIT; @@ -4132,23 +4129,8 @@ aarch64_can_eliminate (const int from, const int to) return true; if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) return true; - return false; - } - else - { - /* If we decided that we didn't need a leaf frame pointer but then used - LR in the function, then we'll want a frame pointer after all, so - prevent this elimination to ensure a frame pointer is used. - - NOTE: the original value of flag_omit_frame_pointer gets trashed - IFF flag_omit_leaf_frame_pointer is true, so we check the value - of faked_omit_frame_pointer here (which is true when we always - wish to keep non-leaf frame pointers but only wish to keep leaf frame - pointers when LR is clobbered). */ - if (to == STACK_POINTER_REGNUM - && df_regs_ever_live_p (LR_REGNUM) - && faked_omit_frame_pointer) - return false; + + return false; } return true; @@ -4865,9 +4847,11 @@ aarch64_address_cost (rtx x ATTRIBUTE_UNUSED, } static int -aarch64_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, - reg_class_t from, reg_class_t to) +aarch64_register_move_cost (enum machine_mode mode, + reg_class_t from_i, reg_class_t to_i) { + enum reg_class from = (enum reg_class) from_i; + enum reg_class to = (enum reg_class) to_i; const struct cpu_regmove_cost *regmove_cost = aarch64_tune_params->regmove_cost; @@ -4893,8 +4877,7 @@ aarch64_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, secondary reload. A general register is used as a scratch to move the upper DI value and the lower DI value is moved directly, hence the cost is the sum of three moves. */ - - if (! TARGET_SIMD && GET_MODE_SIZE (from) == 128 && GET_MODE_SIZE (to) == 128) + if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 128) return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP; return regmove_cost->FP2FP; @@ -5278,17 +5261,10 @@ aarch64_override_options (void) static void aarch64_override_options_after_change (void) { - faked_omit_frame_pointer = false; - - /* To omit leaf frame pointers, we need to turn flag_omit_frame_pointer on so - that aarch64_frame_pointer_required will be called. We need to remember - whether flag_omit_frame_pointer was turned on normally or just faked. */ - - if (flag_omit_leaf_frame_pointer && !flag_omit_frame_pointer) - { - flag_omit_frame_pointer = true; - faked_omit_frame_pointer = true; - } + if (flag_omit_frame_pointer) + flag_omit_leaf_frame_pointer = false; + else if (flag_omit_leaf_frame_pointer) + flag_omit_frame_pointer = true; } static struct machine_function * @@ -6566,7 +6542,9 @@ aarch64_simd_valid_immediate (rtx op, enum machine_mode mode, bool inverse, /* Splat vector constant out into a byte vector. */ for (i = 0; i < n_elts; i++) { - rtx el = CONST_VECTOR_ELT (op, i); + /* The vector is provided in gcc endian-neutral fashion. For aarch64_be, + it must be laid out in the vector register in reverse order. */ + rtx el = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? (n_elts - 1 - i) : i); unsigned HOST_WIDE_INT elpart; unsigned int part, parts; |