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authorktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4>2015-04-30 16:59:50 +0000
committerDan Albert <danalbert@google.com>2015-09-09 21:23:35 +0000
commita981e4500a6364a7af778544cbcbc22bffc4cb58 (patch)
tree61eb6d9470c2d229b91337a7659e90ef21f505b8 /gcc-4.9/gcc/config/aarch64/aarch64.md
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[4.9] Add several improvements for AArch64
Backported from GCC 5. 2015-04-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com> Properly handle mvn-register and add EON+shift pattern and cost appropriately * config/aarch64/aarch64.md (*eor_one_cmpl_<SHIFT:optab><mode>3_alt): New pattern. (*eor_one_cmpl_<SHIFT:optab>sidi3_alt_ze): Likewise. * config/aarch64/aarch64.c (aarch64_rtx_costs): Handle MVN-shift appropriately. Handle alternative EON form. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222637 138bc75d-0d04-0410-961f-82ee72b054a4 2015-04-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com> Properly cost FABD pattern * config/aarch64/aarch64.c (aarch64_rtx_costs): Handle pattern for fabd in ABS case. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222638 138bc75d-0d04-0410-961f-82ee72b054a4 2015-05-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com> Remember to cost operand 0 in FP compare-with-0.0 case * config/aarch64/aarch64.c (aarch64_rtx_costs, COMPARE case): Add cost of op0 in the compare-with-fpzero case. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222673 138bc75d-0d04-0410-961f-82ee72b054a4 2015-05-01 Wilco Dijkstra <wdijkstr@arm.com> Fix aarch64_rtx_costs of PLUS/MINUS * gcc/config/aarch64/aarch64.c (aarch64_rtx_costs): Calculate cost of op0 and op1 in PLUS and MINUS cases. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222676 138bc75d-0d04-0410-961f-82ee72b054a4 2015-07-27 Wilco Dijkstra <wdijkstr@arm.com> Improve spill code - swap order in shl pattern * config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_<mode>3): Place integer variant first. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226247 138bc75d-0d04-0410-961f-82ee72b054a4 2015-07-27 Wilco Dijkstra <wdijkstr@arm.com> Improve spill code - swap order in shr patterns * gcc/config/aarch64/aarch64.md (aarch64_lshr_sisd_or_int_<mode>3): Place integer variant first. (aarch64_ashr_sisd_or_int_<mode>3): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226253 138bc75d-0d04-0410-961f-82ee72b054a4 2015-08-04 Pawel Kupidura <pawel.kupidura@arm.com> * config/aarch64/aarch64.c: Change inner loop statement cost to be consistent with other targets. Change-Id: If5b10466302d733fcae6eacc9d128fdb8f95c0de git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226575 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc-4.9/gcc/config/aarch64/aarch64.md')
-rw-r--r--gcc-4.9/gcc/config/aarch64/aarch64.md67
1 files changed, 47 insertions, 20 deletions
diff --git a/gcc-4.9/gcc/config/aarch64/aarch64.md b/gcc-4.9/gcc/config/aarch64/aarch64.md
index dc88f8b10..fe68bfea1 100644
--- a/gcc-4.9/gcc/config/aarch64/aarch64.md
+++ b/gcc-4.9/gcc/config/aarch64/aarch64.md
@@ -2571,6 +2571,32 @@
[(set_attr "type" "logics_shift_imm")]
)
+(define_insn "*eor_one_cmpl_<SHIFT:optab><mode>3_alt"
+ [(set (match_operand:GPI 0 "register_operand" "=r")
+ (not:GPI (xor:GPI
+ (SHIFT:GPI
+ (match_operand:GPI 1 "register_operand" "r")
+ (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))
+ (match_operand:GPI 3 "register_operand" "r"))))]
+ ""
+ "eon\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
+ [(set_attr "type" "logic_shift_imm")]
+)
+
+;; Zero-extend version of the above.
+(define_insn "*eor_one_cmpl_<SHIFT:optab>sidi3_alt_ze"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (not:SI (xor:SI
+ (SHIFT:SI
+ (match_operand:SI 1 "register_operand" "r")
+ (match_operand:QI 2 "aarch64_shift_imm_si" "n"))
+ (match_operand:SI 3 "register_operand" "r")))))]
+ ""
+ "eon\\t%w0, %w3, %w1, <SHIFT:shift> %2"
+ [(set_attr "type" "logic_shift_imm")]
+)
+
(define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
@@ -2771,32 +2797,33 @@
;; Logical left shift using SISD or Integer instruction
(define_insn "*aarch64_ashl_sisd_or_int_<mode>3"
- [(set (match_operand:GPI 0 "register_operand" "=w,w,r")
+ [(set (match_operand:GPI 0 "register_operand" "=r,w,w")
(ashift:GPI
- (match_operand:GPI 1 "register_operand" "w,w,r")
- (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,w,rUs<cmode>")))]
+ (match_operand:GPI 1 "register_operand" "r,w,w")
+ (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "rUs<cmode>,Us<cmode>,w")))]
""
"@
+ lsl\t%<w>0, %<w>1, %<w>2
shl\t%<rtn>0<vas>, %<rtn>1<vas>, %2
- ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>
- lsl\t%<w>0, %<w>1, %<w>2"
- [(set_attr "simd" "yes,yes,no")
- (set_attr "type" "neon_shift_imm<q>, neon_shift_reg<q>,shift_reg")]
+ ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>"
+ [(set_attr "simd" "no,yes,yes")
+ (set_attr "type" "shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")]
)
;; Logical right shift using SISD or Integer instruction
(define_insn "*aarch64_lshr_sisd_or_int_<mode>3"
- [(set (match_operand:GPI 0 "register_operand" "=w,&w,r")
+ [(set (match_operand:GPI 0 "register_operand" "=r,w,&w,&w")
(lshiftrt:GPI
- (match_operand:GPI 1 "register_operand" "w,w,r")
- (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,w,rUs<cmode>")))]
+ (match_operand:GPI 1 "register_operand" "r,w,w,w")
+ (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "rUs<cmode>,Us<cmode>,w,0")))]
""
"@
+ lsr\t%<w>0, %<w>1, %<w>2
ushr\t%<rtn>0<vas>, %<rtn>1<vas>, %2
#
- lsr\t%<w>0, %<w>1, %<w>2"
- [(set_attr "simd" "yes,yes,no")
- (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,shift_reg")]
+ #"
+ [(set_attr "simd" "no,yes,yes,yes")
+ (set_attr "type" "shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
)
(define_split
@@ -2831,18 +2858,18 @@
;; Arithmetic right shift using SISD or Integer instruction
(define_insn "*aarch64_ashr_sisd_or_int_<mode>3"
- [(set (match_operand:GPI 0 "register_operand" "=w,&w,&w,r")
+ [(set (match_operand:GPI 0 "register_operand" "=r,w,&w,&w")
(ashiftrt:GPI
- (match_operand:GPI 1 "register_operand" "w,w,w,r")
- (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "Us<cmode>,w,0,rUs<cmode>")))]
+ (match_operand:GPI 1 "register_operand" "r,w,w,w")
+ (match_operand:QI 2 "aarch64_reg_or_shift_imm_di" "rUs<cmode>,Us<cmode>,w,0")))]
""
"@
+ asr\t%<w>0, %<w>1, %<w>2
sshr\t%<rtn>0<vas>, %<rtn>1<vas>, %2
#
- #
- asr\t%<w>0, %<w>1, %<w>2"
- [(set_attr "simd" "yes,yes,yes,no")
- (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>,shift_reg")]
+ #"
+ [(set_attr "simd" "no,yes,yes,yes")
+ (set_attr "type" "shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
)
(define_split