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| author | Rong Xu <xur@google.com> | 2014-09-05 20:22:13 -0700 |
|---|---|---|
| committer | Rong Xu <xur@google.com> | 2014-09-05 20:22:13 -0700 |
| commit | 142855c94b3bc9e140a1b55c1a424259285d751c (patch) | |
| tree | 8b4f309643aab7f51e85b9cc66b05f209426c5d3 /gcc-4.9/gcc/config/aarch64/aarch64-simd.md | |
| parent | 4254ad78d813b8c4cfc6c07218aee6b1be554f23 (diff) | |
| download | toolchain_gcc-142855c94b3bc9e140a1b55c1a424259285d751c.tar.gz toolchain_gcc-142855c94b3bc9e140a1b55c1a424259285d751c.tar.bz2 toolchain_gcc-142855c94b3bc9e140a1b55c1a424259285d751c.zip | |
[gcc-4.9] Backport fix for PR62040 and PR62262
Backport two patches from upstream gcc 4.9 branch that fix PR62040 and PR62262
Change-Id: If4f557a650e00261b9bc83e008eb63b13ca798cb
Diffstat (limited to 'gcc-4.9/gcc/config/aarch64/aarch64-simd.md')
| -rw-r--r-- | gcc-4.9/gcc/config/aarch64/aarch64-simd.md | 40 |
1 files changed, 36 insertions, 4 deletions
diff --git a/gcc-4.9/gcc/config/aarch64/aarch64-simd.md b/gcc-4.9/gcc/config/aarch64/aarch64-simd.md index 1f827b57d..851e77a02 100644 --- a/gcc-4.9/gcc/config/aarch64/aarch64-simd.md +++ b/gcc-4.9/gcc/config/aarch64/aarch64-simd.md @@ -945,8 +945,8 @@ ;; On big-endian this is { zeroes, operand } (define_insn "move_lo_quad_internal_<mode>" - [(set (match_operand:VQ 0 "register_operand" "=w,w,w") - (vec_concat:VQ + [(set (match_operand:VQ_NO2E 0 "register_operand" "=w,w,w") + (vec_concat:VQ_NO2E (match_operand:<VHALF> 1 "register_operand" "w,r,r") (vec_duplicate:<VHALF> (const_int 0))))] "TARGET_SIMD && !BYTES_BIG_ENDIAN" @@ -960,9 +960,25 @@ (set_attr "length" "4")] ) +(define_insn "move_lo_quad_internal_<mode>" + [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w") + (vec_concat:VQ_2E + (match_operand:<VHALF> 1 "register_operand" "w,r,r") + (const_int 0)))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "@ + dup\\t%d0, %1.d[0] + fmov\\t%d0, %1 + dup\\t%d0, %1" + [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") + (set_attr "simd" "yes,*,yes") + (set_attr "fp" "*,yes,*") + (set_attr "length" "4")] +) + (define_insn "move_lo_quad_internal_be_<mode>" - [(set (match_operand:VQ 0 "register_operand" "=w,w,w") - (vec_concat:VQ + [(set (match_operand:VQ_NO2E 0 "register_operand" "=w,w,w") + (vec_concat:VQ_NO2E (vec_duplicate:<VHALF> (const_int 0)) (match_operand:<VHALF> 1 "register_operand" "w,r,r")))] "TARGET_SIMD && BYTES_BIG_ENDIAN" @@ -976,6 +992,22 @@ (set_attr "length" "4")] ) +(define_insn "move_lo_quad_internal_be_<mode>" + [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w") + (vec_concat:VQ_2E + (const_int 0) + (match_operand:<VHALF> 1 "register_operand" "w,r,r")))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "@ + dup\\t%d0, %1.d[0] + fmov\\t%d0, %1 + dup\\t%d0, %1" + [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>") + (set_attr "simd" "yes,*,yes") + (set_attr "fp" "*,yes,*") + (set_attr "length" "4")] +) + (define_expand "move_lo_quad_<mode>" [(match_operand:VQ 0 "register_operand") (match_operand:VQ 1 "register_operand")] |