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author | Ben Cheng <bccheng@google.com> | 2013-03-28 11:14:20 -0700 |
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committer | Ben Cheng <bccheng@google.com> | 2013-03-28 12:40:33 -0700 |
commit | af0c51ac87ab2a87caa03fa108f0d164987a2764 (patch) | |
tree | 4b8b470f7c5b69642fdab8d0aa1fbc148d02196b /gcc-4.8/libjava/sysdep/mips | |
parent | d87cae247d39ebf4f5a6bf25c932a14d2fdb9384 (diff) | |
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[GCC 4.8] Initial check-in of GCC 4.8.0
Change-Id: I0719d8a6d0f69b367a6ab6f10eb75622dbf12771
Diffstat (limited to 'gcc-4.8/libjava/sysdep/mips')
-rw-r--r-- | gcc-4.8/libjava/sysdep/mips/locks.h | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/gcc-4.8/libjava/sysdep/mips/locks.h b/gcc-4.8/libjava/sysdep/mips/locks.h new file mode 100644 index 000000000..c8e30cf68 --- /dev/null +++ b/gcc-4.8/libjava/sysdep/mips/locks.h @@ -0,0 +1,68 @@ +// locks.h - Thread synchronization primitives. MIPS implementation. + +/* Copyright (C) 2003 Free Software Foundation + + This file is part of libgcj. + +This software is copyrighted work licensed under the terms of the +Libgcj License. Please consult the file "LIBGCJ_LICENSE" for +details. */ + +#ifndef __SYSDEP_LOCKS_H__ +#define __SYSDEP_LOCKS_H__ + +/* Integer type big enough for object address. */ +typedef unsigned obj_addr_t __attribute__((__mode__(__pointer__))); + + +// Atomically replace *addr by new_val if it was initially equal to old. +// Return true if the comparison succeeded. +// Assumed to have acquire semantics, i.e. later memory operations +// cannot execute before the compare_and_swap finishes. +inline static bool +compare_and_swap(volatile obj_addr_t *addr, + obj_addr_t old, + obj_addr_t new_val) +{ + return __sync_bool_compare_and_swap(addr, old, new_val); +} + +// Set *addr to new_val with release semantics, i.e. making sure +// that prior loads and stores complete before this +// assignment. +inline static void +release_set(volatile obj_addr_t *addr, obj_addr_t new_val) +{ + __sync_synchronize(); + *(addr) = new_val; +} + +// Compare_and_swap with release semantics instead of acquire semantics. +// On many architecture, the operation makes both guarantees, so the +// implementation can be the same. +inline static bool +compare_and_swap_release(volatile obj_addr_t *addr, + obj_addr_t old, + obj_addr_t new_val) +{ + return __sync_bool_compare_and_swap(addr, old, new_val); +} + +// Ensure that subsequent instructions do not execute on stale +// data that was loaded from memory before the barrier. +// On X86, the hardware ensures that reads are properly ordered. +inline static void +read_barrier() +{ + __sync_synchronize(); +} + +// Ensure that prior stores to memory are completed with respect to other +// processors. +inline static void +write_barrier() +{ + __sync_synchronize(); +} + +#endif // __SYSDEP_LOCKS_H__ |