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authorIceberg Fu <Chao-Ying.Fu@imgtec.com>2013-08-30 09:41:37 +0800
committerAndrew Hsieh <andrewhsieh@google.com>2013-08-30 09:57:31 +0800
commit79ba8bc76c0534e9f2544af2d1943b1581c84c77 (patch)
treebb1c0b63b4c12af5ea0947ac68f064e41ea917c3 /gcc-4.8/libffi/src/powerpc/ffi.c
parent045de201af2aad6c6ce79dce5e9f95283df3b5be (diff)
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Extend MIPS GCC4.6/4.7/4.8 -mldc1-sdc1 to control ldxc1/sdxc1 too
-mldc1-sdc1 now also controls codegen of ldxc1/sdxc1, the indexed versions (where address of load/store is computed from sum of two registers) of ldc1/sdc1 which are already controlled by this option. Although double (or struct containing double) is always aligned and the stock does guarantee 8-byte alignment, this option is to workaround issue when double is allocated from a custom allocator w/o honoring 8-byte minimal alignment. Change-Id: I79433976509b885b5699d62693fd3154bb752abf
Diffstat (limited to 'gcc-4.8/libffi/src/powerpc/ffi.c')
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