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author | Andrew Hsieh <andrewhsieh@google.com> | 2014-06-18 13:00:04 -0700 |
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committer | Pavel Chupin <pavel.v.chupin@intel.com> | 2014-06-19 22:38:42 +0400 |
commit | f190d6284359da8ae8694b2d2e14b01602a959ed (patch) | |
tree | d4e0548e7cec02d60b1082368032e66a1c509a02 /gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-av.c | |
parent | 4ff2f42147bc128ce38789071d98e55844cd3a5e (diff) | |
download | toolchain_gcc-f190d6284359da8ae8694b2d2e14b01602a959ed.tar.gz toolchain_gcc-f190d6284359da8ae8694b2d2e14b01602a959ed.tar.bz2 toolchain_gcc-f190d6284359da8ae8694b2d2e14b01602a959ed.zip |
Merge GCC 4.8.3
Change-Id: I0abe59f7705b3eccc6b2f123af75b2e30917696a
Diffstat (limited to 'gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-av.c')
-rw-r--r-- | gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-av.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-av.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-av.c new file mode 100644 index 000000000..d4aac786b --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-av.c @@ -0,0 +1,37 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -mcpu=power6 -mabi=altivec -maltivec -mno-vsx" } */ +/* { dg-final { scan-assembler "\[ \t\]and " } } */ +/* { dg-final { scan-assembler "\[ \t\]or " } } */ +/* { dg-final { scan-assembler "\[ \t\]xor " } } */ +/* { dg-final { scan-assembler "\[ \t\]nor " } } */ +/* { dg-final { scan-assembler "\[ \t\]andc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */ + +/* On altivec, for 128-bit types, ORC/ANDC/EQV might not show up, since the + vector unit doesn't support these, so the appropriate combine patterns may + not be generated. */ + +#ifndef TYPE +#ifdef _ARCH_PPC64 +#define TYPE __int128_t +#else +typedef int v4si __attribute__ ((vector_size (16))); +#define TYPE v4si +#endif +#endif + +#include "bool3.h" |