[4.8] Merge GCC 4.8.1

Change-Id: Ic8a60b7563f5172440fd40788605163a0cca6e30

4 files changed, 162 insertions, 62 deletions

diff --git a/gcc-4.8/gcc/config/tilegx/tilegx-builtins.h b/gcc-4.8/gcc/config/tilegx/tilegx-builtins.h
index 31f1cebff..2edf05ee7 100644
--- a/gcc-4.8/gcc/config/tilegx/tilegx-builtins.h
+++ b/gcc-4.8/gcc/config/tilegx/tilegx-builtins.h
@@ -193,6 +193,7 @@ enum tilegx_builtin
   TILEGX_INSN_SHRU,
   TILEGX_INSN_SHRUX,
   TILEGX_INSN_SHUFFLEBYTES,
+  TILEGX_INSN_SHUFFLEBYTES1,
   TILEGX_INSN_ST,
   TILEGX_INSN_ST1,
   TILEGX_INSN_ST2,
diff --git a/gcc-4.8/gcc/config/tilegx/tilegx.c b/gcc-4.8/gcc/config/tilegx/tilegx.c
index 98f53f199..beb1012cf 100644
--- a/gcc-4.8/gcc/config/tilegx/tilegx.c
+++ b/gcc-4.8/gcc/config/tilegx/tilegx.c
@@ -1429,14 +1429,16 @@ expand_set_cint64_one_inst (rtx dest_reg,
     }
   else if (!three_wide_only)
     {
-      rtx imm_op = GEN_INT (val);
-
-      if (satisfies_constraint_J (imm_op)
-	  || satisfies_constraint_K (imm_op)
-	  || satisfies_constraint_N (imm_op)
-	  || satisfies_constraint_P (imm_op))
+      /* Test for the following constraints: J, K, N, P.  We avoid
+	 generating an rtx and using existing predicates because we
+	 can be testing and rejecting a lot of constants, and GEN_INT
+	 is O(N).  */
+      if ((val >= -32768 && val <= 65535)
+	  || ((val == (val & 0xFF) * 0x0101010101010101LL))
+	  || (val == ((trunc_int_for_mode (val, QImode) & 0xFFFF)
+		      * 0x0001000100010001LL)))
 	{
-	  emit_move_insn (dest_reg, imm_op);
+	  emit_move_insn (dest_reg, GEN_INT (val));
 	  return true;
 	}
     }
@@ -2895,6 +2897,7 @@ static struct tile_builtin_info tilegx_builtin_info[TILEGX_BUILTIN_max] = {
   { CODE_FOR_lshrdi3,                   NULL }, /* shru */
   { CODE_FOR_lshrsi3,                   NULL }, /* shrux */
   { CODE_FOR_insn_shufflebytes,         NULL }, /* shufflebytes */
+  { CODE_FOR_insn_shufflebytes1,        NULL }, /* shufflebytes1 */
   { CODE_FOR_insn_st,                   NULL }, /* st */
   { CODE_FOR_insn_st1,                  NULL }, /* st1 */
   { CODE_FOR_insn_st2,                  NULL }, /* st2 */
@@ -3223,6 +3226,7 @@ static const struct tilegx_builtin_def tilegx_builtins[] = {
   { "__insn_shrux",              TILEGX_INSN_SHRUX,              true,  "iii"  },
   { "__insn_shruxi",             TILEGX_INSN_SHRUX,              true,  "iii"  },
   { "__insn_shufflebytes",       TILEGX_INSN_SHUFFLEBYTES,       true,  "llll" },
+  { "__insn_shufflebytes1",      TILEGX_INSN_SHUFFLEBYTES1,      true,  "lll"  },
   { "__insn_st",                 TILEGX_INSN_ST,                 false, "vpl"  },
   { "__insn_st1",                TILEGX_INSN_ST1,                false, "vpl"  },
   { "__insn_st2",                TILEGX_INSN_ST2,                false, "vpl"  },
@@ -3995,11 +3999,10 @@ tilegx_expand_prologue (void)
 
 	if (r == NULL_RTX)
 	  {
-	    rtx p = compute_frame_addr (offset, &next_scratch_regno);
-	    r = gen_rtx_REG (Pmode, next_scratch_regno--);
-	    reg_save_addr[which_scratch] = r;
-
-	    emit_insn (gen_rtx_SET (VOIDmode, r, p));
+	    int prev_scratch_regno = next_scratch_regno;
+	    r = compute_frame_addr (offset, &next_scratch_regno);
+	    if (prev_scratch_regno != next_scratch_regno)
+	      reg_save_addr[which_scratch] = r;
 	  }
 	else
 	  {
@@ -4786,13 +4789,8 @@ tilegx_reorg (void)
 int
 tilegx_asm_preferred_eh_data_format (int code ATTRIBUTE_UNUSED, int global)
 {
-  if (flag_pic)
-    {
-      int type = TARGET_32BIT ? DW_EH_PE_sdata4 : DW_EH_PE_sdata8;
-      return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
-    }
-  else
-    return DW_EH_PE_absptr;
+  int type = TARGET_32BIT ? DW_EH_PE_sdata4 : DW_EH_PE_sdata8;
+  return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
 }
 
 
diff --git a/gcc-4.8/gcc/config/tilegx/tilegx.h b/gcc-4.8/gcc/config/tilegx/tilegx.h
index 32c20df80..6f4734537 100644
--- a/gcc-4.8/gcc/config/tilegx/tilegx.h
+++ b/gcc-4.8/gcc/config/tilegx/tilegx.h
@@ -287,6 +287,8 @@ enum reg_class
 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
   ((OFFSET) = tilegx_initial_elimination_offset((FROM),(TO)))
 
+#define PROFILE_BEFORE_PROLOGUE 1
+
 #define FUNCTION_PROFILER(FILE, LABELNO) \
   tilegx_function_profiler (FILE, LABELNO)
 
@@ -446,7 +448,7 @@ enum reg_class
     {								\
       char label[256];						\
       ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE));	\
-      fprintf (FILE, "\t%s ",					\
+      fprintf (FILE, "%s ",					\
                integer_asm_op (GET_MODE_SIZE (Pmode), TRUE));	\
       assemble_name (FILE, label);				\
       fprintf (FILE, "\n");					\
@@ -458,7 +460,7 @@ enum reg_class
     {								\
       char label[256];						\
       ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE));	\
-      fprintf (FILE, "\t%s ", 					\
+      fprintf (FILE, "%s ", 					\
                integer_asm_op (GET_MODE_SIZE (Pmode), TRUE));	\
       assemble_name (FILE, label);				\
       ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL));		\
diff --git a/gcc-4.8/gcc/config/tilegx/tilegx.md b/gcc-4.8/gcc/config/tilegx/tilegx.md
index da1155395..8dfcff603 100644
--- a/gcc-4.8/gcc/config/tilegx/tilegx.md
+++ b/gcc-4.8/gcc/config/tilegx/tilegx.md
@@ -2490,7 +2490,7 @@
   "@
    jr\t%r0
    j\t%p0"
-  [(set_attr "type" "X1,X1")])
+  [(set_attr "type" "Y1,X1")])
 
 (define_expand "sibcall_value"
   [(parallel [(set (match_operand 0 "" "")
@@ -2509,7 +2509,7 @@
   "@
    jr\t%r1
    j\t%p1"
-  [(set_attr "type" "X1,X1")])
+  [(set_attr "type" "Y1,X1")])
 
 (define_insn "jump"
   [(set (pc) (label_ref (match_operand 0 "" "")))]
@@ -3857,6 +3857,15 @@
   "shufflebytes\t%0, %r2, %r3"
   [(set_attr "type" "X0")])
 
+(define_insn "insn_shufflebytes1"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rO")
+                    (match_operand:DI 2 "reg_or_0_operand" "rO")]
+                   UNSPEC_INSN_SHUFFLEBYTES))]
+  ""
+  "shufflebytes\t%0, %r1, %r2"
+  [(set_attr "type" "X0")])
+
 ;; stores
 
 (define_expand "insn_st"
@@ -4486,57 +4495,147 @@
 ;; insn_v1mz
 ;; insn_v2mnz
 ;; insn_v2mz
-(define_insn "insn_mnz_<mode>"
-  [(set (match_operand:VEC48MODE 0 "register_operand" "=r")
-	(if_then_else:VEC48MODE
-         (ne:VEC48MODE
-	  (match_operand:VEC48MODE 1 "reg_or_0_operand" "rO")
-	  (const_int 0))
-         (match_operand:VEC48MODE 2 "reg_or_0_operand" "rO")
-         (const_int 0)))]
-  ""
-  "v<n>mnz\t%0, %r1, %r2"
+(define_insn "insn_mnz_v8qi"
+  [(set (match_operand:V8QI 0 "register_operand" "=r")
+	(if_then_else:V8QI
+         (ne:V8QI
+	  (match_operand:V8QI 1 "reg_or_0_operand" "rO")
+	  (const_vector:V8QI [(const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)]))
+         (match_operand:V8QI 2 "reg_or_0_operand" "rO")
+	 (const_vector:V8QI [(const_int 0) (const_int 0)
+			     (const_int 0) (const_int 0)
+			     (const_int 0) (const_int 0)
+			     (const_int 0) (const_int 0)])))]
+  ""
+  "v1mnz\t%0, %r1, %r2"
   [(set_attr "type" "X01")])
 
-(define_expand "insn_v<n>mnz"
+(define_expand "insn_v1mnz"
   [(set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:VEC48MODE
-         (ne:VEC48MODE
+	(if_then_else:V8QI
+         (ne:V8QI
 	  (match_operand:DI 1 "reg_or_0_operand" "")
-	  (const_int 0))
+	  (const_vector:V8QI [(const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)])
+	  )
          (match_operand:DI 2 "reg_or_0_operand" "")
-         (const_int 0)))]
+	 (const_vector:V8QI [(const_int 0) (const_int 0)
+			     (const_int 0) (const_int 0)
+			     (const_int 0) (const_int 0)
+			     (const_int 0) (const_int 0)])))]
   ""
 {
-  tilegx_expand_builtin_vector_binop (gen_insn_mnz_<mode>, <MODE>mode,
-                                      operands[0], <MODE>mode, operands[1],
+  tilegx_expand_builtin_vector_binop (gen_insn_mnz_v8qi, V8QImode,
+                                      operands[0], V8QImode, operands[1],
 				      operands[2], true);
   DONE;
 })
 
-(define_insn "insn_mz_<mode>"
-  [(set (match_operand:VEC48MODE 0 "register_operand" "=r")
-	(if_then_else:VEC48MODE
-         (ne:VEC48MODE
-	  (match_operand:VEC48MODE 1 "reg_or_0_operand" "rO")
-	  (const_int 0))
-         (const_int 0)
-         (match_operand:VEC48MODE 2 "reg_or_0_operand" "rO")))]
+(define_insn "insn_mz_v8qi"
+  [(set (match_operand:V8QI 0 "register_operand" "=r")
+	(if_then_else:V8QI
+         (ne:V8QI
+	  (match_operand:V8QI 1 "reg_or_0_operand" "rO")
+	  (const_vector:V8QI [(const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)]))
+	 (const_vector:V8QI [(const_int 0) (const_int 0)
+			     (const_int 0) (const_int 0)
+			     (const_int 0) (const_int 0)
+			     (const_int 0) (const_int 0)])
+         (match_operand:V8QI 2 "reg_or_0_operand" "rO")))]
+  ""
+  "v1mz\t%0, %r1, %r2"
+  [(set_attr "type" "X01")])
+
+(define_expand "insn_v1mz"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(if_then_else:V8QI
+         (ne:V8QI
+	  (match_operand:DI 1 "reg_or_0_operand" "")
+	  (const_vector:V8QI [(const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)]))
+	 (const_vector:V8QI [(const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)])
+         (match_operand:DI 2 "reg_or_0_operand" "")))]
   ""
-  "v<n>mz\t%0, %r1, %r2"
+{
+  tilegx_expand_builtin_vector_binop (gen_insn_mz_v8qi, V8QImode,
+                                      operands[0], V8QImode, operands[1],
+				      operands[2], true);
+  DONE;
+})
+
+(define_insn "insn_mnz_v4hi"
+  [(set (match_operand:V4HI 0 "register_operand" "=r")
+	(if_then_else:V4HI
+         (ne:V4HI
+	  (match_operand:V4HI 1 "reg_or_0_operand" "rO")
+	  (const_vector:V4HI [(const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)]))
+         (match_operand:V4HI 2 "reg_or_0_operand" "rO")
+	 (const_vector:V4HI [(const_int 0) (const_int 0)
+			     (const_int 0) (const_int 0)])))]
+  ""
+  "v2mnz\t%0, %r1, %r2"
+  [(set_attr "type" "X01")])
+
+(define_expand "insn_v2mnz"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(if_then_else:V4HI
+         (ne:V4HI
+	  (match_operand:DI 1 "reg_or_0_operand" "")
+	  (const_vector:V4HI [(const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)]))
+         (match_operand:DI 2 "reg_or_0_operand" "")
+	 (const_vector:V4HI [(const_int 0) (const_int 0)
+			     (const_int 0) (const_int 0)])))]
+  ""
+{
+  tilegx_expand_builtin_vector_binop (gen_insn_mnz_v4hi, V4HImode,
+                                      operands[0], V4HImode, operands[1],
+				      operands[2], true);
+  DONE;
+})
+
+(define_insn "insn_mz_v4hi"
+  [(set (match_operand:V4HI 0 "register_operand" "=r")
+	(if_then_else:V4HI
+         (ne:V4HI
+	  (match_operand:V4HI 1 "reg_or_0_operand" "rO")
+	  (const_vector:V4HI [(const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)]))
+	 (const_vector:V4HI [(const_int 0) (const_int 0)
+			     (const_int 0) (const_int 0)])
+         (match_operand:V4HI 2 "reg_or_0_operand" "rO")))]
+  ""
+  "v2mz\t%0, %r1, %r2"
   [(set_attr "type" "X01")])
-(define_expand "insn_v<n>mz"
+
+(define_expand "insn_v2mz"
   [(set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:VEC48MODE
-         (ne:VEC48MODE
+	(if_then_else:V4HI
+         (ne:V4HI
 	  (match_operand:DI 1 "reg_or_0_operand" "")
-	  (const_int 0))
-         (const_int 0)
+	  (const_vector:V4HI [(const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)]))
+	 (const_vector:V4HI [(const_int 0) (const_int 0)
+			      (const_int 0) (const_int 0)])
          (match_operand:DI 2 "reg_or_0_operand" "")))]
   ""
 {
-  tilegx_expand_builtin_vector_binop (gen_insn_mz_<mode>, <MODE>mode,
-                                      operands[0], <MODE>mode, operands[1],
+  tilegx_expand_builtin_vector_binop (gen_insn_mz_v4hi, V4HImode,
+                                      operands[0], V4HImode, operands[1],
 				      operands[2], true);
   DONE;
 })
@@ -4561,8 +4660,8 @@
 
 (define_expand "insn_v1mulu"
   [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_0_operand" "")]
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
 {
   tilegx_expand_builtin_vector_binop (gen_vec_widen_umult_lo_v8qi, V4HImode,
@@ -4591,8 +4690,8 @@
 
 (define_expand "insn_v1mulus"
   [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_0_operand" "")]
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
 {
   tilegx_expand_builtin_vector_binop (gen_vec_widen_usmult_lo_v8qi, V4HImode,
@@ -4619,8 +4718,8 @@
 
 (define_expand "insn_v2muls"
   [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_0_operand" "")]
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
 {
   tilegx_expand_builtin_vector_binop (gen_vec_widen_smult_lo_v4qi, V2SImode,