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author | Ben Cheng <bccheng@google.com> | 2012-10-01 10:30:31 -0700 |
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committer | Ben Cheng <bccheng@google.com> | 2012-10-01 10:30:31 -0700 |
commit | 82bcbebce43f0227f506d75a5b764b6847041bae (patch) | |
tree | fe9f8597b48a430c4daeb5123e3e8eb28e6f9da9 /gcc-4.7/gcc/config/mips/mips-modes.def | |
parent | 3c052de3bb16ac53b6b6ed659ec7557eb84c7590 (diff) | |
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Initial check-in of gcc 4.7.2.
Change-Id: I4a2f5a921c21741a0e18bda986d77e5f1bef0365
Diffstat (limited to 'gcc-4.7/gcc/config/mips/mips-modes.def')
-rw-r--r-- | gcc-4.7/gcc/config/mips/mips-modes.def | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/gcc-4.7/gcc/config/mips/mips-modes.def b/gcc-4.7/gcc/config/mips/mips-modes.def new file mode 100644 index 000000000..187c651bb --- /dev/null +++ b/gcc-4.7/gcc/config/mips/mips-modes.def @@ -0,0 +1,54 @@ +/* MIPS extra machine modes. + Copyright (C) 2003, 2004, 2007, 2008 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +/* MIPS has a quirky almost-IEEE format for all its + floating point. */ +RESET_FLOAT_FORMAT (SF, mips_single_format); +RESET_FLOAT_FORMAT (DF, mips_double_format); + +/* Irix6 will override this via MIPS_TFMODE_FORMAT. */ +FLOAT_MODE (TF, 16, mips_quad_format); + +/* Vector modes. */ +VECTOR_MODES (INT, 4); /* V4QI V2HI */ +VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */ +VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */ + +/* Double-sized vector modes for vec_concat. */ +VECTOR_MODE (INT, QI, 16); /* V16QI */ +VECTOR_MODE (INT, HI, 8); /* V8HI */ +VECTOR_MODE (INT, SI, 4); /* V4SI */ +VECTOR_MODE (FLOAT, SF, 4); /* V4SF */ + +VECTOR_MODES (FRACT, 4); /* V4QQ V2HQ */ +VECTOR_MODES (UFRACT, 4); /* V4UQQ V2UHQ */ +VECTOR_MODES (ACCUM, 4); /* V2HA */ +VECTOR_MODES (UACCUM, 4); /* V2UHA */ + +/* Paired single comparison instructions use 2 or 4 CC. */ +CC_MODE (CCV2); +ADJUST_BYTESIZE (CCV2, 8); +ADJUST_ALIGNMENT (CCV2, 8); + +CC_MODE (CCV4); +ADJUST_BYTESIZE (CCV4, 16); +ADJUST_ALIGNMENT (CCV4, 16); + +/* For MIPS DSP control registers. */ +CC_MODE (CCDSP); |