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author | Ben Cheng <bccheng@google.com> | 2012-10-01 10:30:31 -0700 |
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committer | Ben Cheng <bccheng@google.com> | 2012-10-01 10:30:31 -0700 |
commit | 82bcbebce43f0227f506d75a5b764b6847041bae (patch) | |
tree | fe9f8597b48a430c4daeb5123e3e8eb28e6f9da9 /gcc-4.7/gcc/config/mips/4600.md | |
parent | 3c052de3bb16ac53b6b6ed659ec7557eb84c7590 (diff) | |
download | toolchain_gcc-82bcbebce43f0227f506d75a5b764b6847041bae.tar.gz toolchain_gcc-82bcbebce43f0227f506d75a5b764b6847041bae.tar.bz2 toolchain_gcc-82bcbebce43f0227f506d75a5b764b6847041bae.zip |
Initial check-in of gcc 4.7.2.
Change-Id: I4a2f5a921c21741a0e18bda986d77e5f1bef0365
Diffstat (limited to 'gcc-4.7/gcc/config/mips/4600.md')
-rw-r--r-- | gcc-4.7/gcc/config/mips/4600.md | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/gcc-4.7/gcc/config/mips/4600.md b/gcc-4.7/gcc/config/mips/4600.md new file mode 100644 index 000000000..c645cbc5d --- /dev/null +++ b/gcc-4.7/gcc/config/mips/4600.md @@ -0,0 +1,87 @@ +;; R4600 and R4650 pipeline description. +;; Copyright (C) 2004, 2005, 2007 Free Software Foundation, Inc. +;; +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + + +;; This file overrides parts of generic.md. It is derived from the +;; old define_function_unit description. +;; +;; We handle the R4600 and R4650 in much the same way. The only difference +;; is in the integer multiplication and division costs. + +(define_insn_reservation "r4600_imul" 10 + (and (eq_attr "cpu" "r4600") + (eq_attr "type" "imul,imul3,imadd")) + "imuldiv*10") + +(define_insn_reservation "r4600_idiv" 42 + (and (eq_attr "cpu" "r4600") + (eq_attr "type" "idiv")) + "imuldiv*42") + + +(define_insn_reservation "r4650_imul" 4 + (and (eq_attr "cpu" "r4650") + (eq_attr "type" "imul,imul3,imadd")) + "imuldiv*4") + +(define_insn_reservation "r4650_idiv" 36 + (and (eq_attr "cpu" "r4650") + (eq_attr "type" "idiv")) + "imuldiv*36") + + +(define_insn_reservation "r4600_load" 2 + (and (eq_attr "cpu" "r4600,r4650") + (eq_attr "type" "load,fpload,fpidxload")) + "alu") + +(define_insn_reservation "r4600_fmove" 1 + (and (eq_attr "cpu" "r4600,r4650") + (eq_attr "type" "fabs,fneg,fmove")) + "alu") + +(define_insn_reservation "r4600_fmul_single" 8 + (and (eq_attr "cpu" "r4600,r4650") + (and (eq_attr "type" "fmul,fmadd") + (eq_attr "mode" "SF"))) + "alu") + +(define_insn_reservation "r4600_fdiv_single" 32 + (and (eq_attr "cpu" "r4600,r4650") + (and (eq_attr "type" "fdiv,frdiv") + (eq_attr "mode" "SF"))) + "alu") + +(define_insn_reservation "r4600_fdiv_double" 61 + (and (eq_attr "cpu" "r4600,r4650") + (and (eq_attr "type" "fdiv,frdiv") + (eq_attr "mode" "DF"))) + "alu") + +(define_insn_reservation "r4600_fsqrt_single" 31 + (and (eq_attr "cpu" "r4600,r4650") + (and (eq_attr "type" "fsqrt,frsqrt") + (eq_attr "mode" "SF"))) + "alu") + +(define_insn_reservation "r4600_fsqrt_double" 60 + (and (eq_attr "cpu" "r4600,r4650") + (and (eq_attr "type" "fsqrt,frsqrt") + (eq_attr "mode" "DF"))) + "alu") |