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author | Andrew Hsieh <andrewhsieh@google.com> | 2013-04-26 12:56:39 +0800 |
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committer | Andrew Hsieh <andrewhsieh@google.com> | 2013-04-26 12:56:39 +0800 |
commit | 6e6510c702f12bc6320681075cc0ba8dc2c814a7 (patch) | |
tree | 35f3b59aa003a1ddb2dbd0b2fac2365e5011f817 /gcc-4.6 | |
parent | 4d986177b7a40bd4d1b3b49a33adc90da13cc017 (diff) | |
download | toolchain_gcc-6e6510c702f12bc6320681075cc0ba8dc2c814a7.tar.gz toolchain_gcc-6e6510c702f12bc6320681075cc0ba8dc2c814a7.tar.bz2 toolchain_gcc-6e6510c702f12bc6320681075cc0ba8dc2c814a7.zip |
Add new GCC/MIPS option -mldc1-sdc1
ldc1/sdc1 needs memory to be 8-byte aligned.
This option is on by default for arch supports it, but can be turned
off by "-mno-ldc1-sdc1" to workaround issue, for example.
Change-Id: I14291dc4280e75f6c765c933b60eb1b7cd44f974
Diffstat (limited to 'gcc-4.6')
-rw-r--r-- | gcc-4.6/gcc/config/mips/mips.h | 2 | ||||
-rw-r--r-- | gcc-4.6/gcc/config/mips/mips.opt | 4 |
2 files changed, 5 insertions, 1 deletions
diff --git a/gcc-4.6/gcc/config/mips/mips.h b/gcc-4.6/gcc/config/mips/mips.h index 6e34a2a00..79b806dd2 100644 --- a/gcc-4.6/gcc/config/mips/mips.h +++ b/gcc-4.6/gcc/config/mips/mips.h @@ -850,7 +850,7 @@ enum mips_code_readable_setting { #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF) /* ISA has LDC1 and SDC1. */ -#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16) +#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16 && TARGET_LDC1_SDC1) /* ISA has the mips4 FP condition code instructions: FP-compare to CC, branch on CC, and move (both FP and non-FP) on CC. */ diff --git a/gcc-4.6/gcc/config/mips/mips.opt b/gcc-4.6/gcc/config/mips/mips.opt index 20b0b6cde..4be40b1d6 100644 --- a/gcc-4.6/gcc/config/mips/mips.opt +++ b/gcc-4.6/gcc/config/mips/mips.opt @@ -194,6 +194,10 @@ mips3d Target Report RejectNegative Mask(MIPS3D) Use MIPS-3D instructions +mldc1-sdc1 +Target Report Var(TARGET_LDC1_SDC1) Init(1) +Use ldc1 and sdc1 instruction + mllsc Target Report Mask(LLSC) Use ll, sc and sync instructions |