Fix ARM internal compiler error reload1.c:3633 compiling Earth

ARM GCC 4.6 experiences ICE when compiles Earth in debug build
  libs/evll/database/quadtreecachetype.cc:237:1: internal compiler
     error: in elimination_costs_in_insn, at reload1.c:3633

The reason is that ARM back-end expects wrong operand type
sign-extend from char.

Back port fix from
  http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50099

Change-Id: Ia235b76c6f0bada472a741a763d087789a41db8e

4 files changed, 28 insertions, 5 deletions

diff --git a/gcc-4.6/gcc/config/arm/arm.md b/gcc-4.6/gcc/config/arm/arm.md
index 90adc2e55..df2e63949 100644
--- a/gcc-4.6/gcc/config/arm/arm.md
+++ b/gcc-4.6/gcc/config/arm/arm.md
@@ -4045,8 +4045,8 @@
 
 (define_insn "zero_extend<mode>di2"
   [(set (match_operand:DI 0 "s_register_operand" "=r")
-        (zero_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
-					    "<qhs_extenddi_cstr>")))]
+        (zero_extend:DI (match_operand:QHSI 1 "<qhs_zextenddi_op>"
+					    "<qhs_zextenddi_cstr>")))]
   "TARGET_32BIT <qhs_zextenddi_cond>"
   "#"
   [(set_attr "length" "8")
diff --git a/gcc-4.6/gcc/config/arm/iterators.md b/gcc-4.6/gcc/config/arm/iterators.md
index 887c962ba..38faa59c8 100644
--- a/gcc-4.6/gcc/config/arm/iterators.md
+++ b/gcc-4.6/gcc/config/arm/iterators.md
@@ -381,10 +381,14 @@
 (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
 (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
 				      (QI "&& arm_arch6")])
-(define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
+(define_mode_attr qhs_zextenddi_op [(SI "s_register_operand")
 				   (HI "nonimmediate_operand")
 				   (QI "nonimmediate_operand")])
-(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
+(define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
+				   (HI "nonimmediate_operand")
+				   (QI "arm_reg_or_extendqisi_mem_op")])
+(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rUq")])
+(define_mode_attr qhs_zextenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
 
 ;;----------------------------------------------------------------------------
 ;; Code attributes
diff --git a/gcc-4.6/gcc/config/arm/predicates.md b/gcc-4.6/gcc/config/arm/predicates.md
index e34b46da0..7f20106ba 100644
--- a/gcc-4.6/gcc/config/arm/predicates.md
+++ b/gcc-4.6/gcc/config/arm/predicates.md
@@ -129,6 +129,8 @@
   (ior (match_operand 0 "arm_rhs_operand")
        (match_operand 0 "memory_operand")))
 
+;; This doesn't have to do much because the constant is already checked
+;; in the shift_operator predicate.
 (define_predicate "shift_amount_operand"
   (ior (and (match_test "TARGET_ARM")
 	    (match_operand 0 "s_register_operand"))
@@ -218,13 +220,20 @@
        (match_test "mode == GET_MODE (op)")))
 
 ;; True for shift operators.
+;; Notes:
+;;  * mult is only permitted with a constant shift amount
+;;  * patterns that permit register shift amounts only in ARM mode use
+;;    shift_amount_operand, patterns that always allow registers do not,
+;;    so we don't have to worry about that sort of thing here.
 (define_special_predicate "shift_operator"
   (and (ior (ior (and (match_code "mult")
 		      (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
 		 (and (match_code "rotate")
 		      (match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
 				   && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
-	    (match_code "ashift,ashiftrt,lshiftrt,rotatert"))
+	    (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
+		 (match_test "GET_CODE (XEXP (op, 1)) != CONST_INT
+			      || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
        (match_test "mode == GET_MODE (op)")))
 
 ;; True for MULT, to identify which variant of shift_operator is in use.
diff --git a/gcc-4.6/gcc/testsuite/gcc.target/arm/pr50099.c b/gcc-4.6/gcc/testsuite/gcc.target/arm/pr50099.c
new file mode 100644
index 000000000..c0d143dd5
--- /dev/null
+++ b/gcc-4.6/gcc/testsuite/gcc.target/arm/pr50099.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+long long foo (signed char * arg)
+{
+  long long temp_1;
+
+  temp_1 = arg[256]; 
+  return temp_1;
+}