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authorIceberg Fu <Chao-Ying.Fu@imgtec.com>2013-08-30 09:41:37 +0800
committerAndrew Hsieh <andrewhsieh@google.com>2013-08-30 09:57:31 +0800
commit79ba8bc76c0534e9f2544af2d1943b1581c84c77 (patch)
treebb1c0b63b4c12af5ea0947ac68f064e41ea917c3 /gcc-4.6
parent045de201af2aad6c6ce79dce5e9f95283df3b5be (diff)
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Extend MIPS GCC4.6/4.7/4.8 -mldc1-sdc1 to control ldxc1/sdxc1 too
-mldc1-sdc1 now also controls codegen of ldxc1/sdxc1, the indexed versions (where address of load/store is computed from sum of two registers) of ldc1/sdc1 which are already controlled by this option. Although double (or struct containing double) is always aligned and the stock does guarantee 8-byte alignment, this option is to workaround issue when double is allocated from a custom allocator w/o honoring 8-byte minimal alignment. Change-Id: I79433976509b885b5699d62693fd3154bb752abf
Diffstat (limited to 'gcc-4.6')
-rw-r--r--gcc-4.6/gcc/config/mips/mips.md4
-rw-r--r--gcc-4.6/gcc/config/mips/mips.opt2
2 files changed, 3 insertions, 3 deletions
diff --git a/gcc-4.6/gcc/config/mips/mips.md b/gcc-4.6/gcc/config/mips/mips.md
index 3913df8..27ea6c1 100644
--- a/gcc-4.6/gcc/config/mips/mips.md
+++ b/gcc-4.6/gcc/config/mips/mips.md
@@ -4194,7 +4194,7 @@
[(set (match_operand:ANYF 0 "register_operand" "=f")
(mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
(match_operand:P 2 "register_operand" "d"))))]
- "ISA_HAS_FP4"
+ "ISA_HAS_FP4 && (<MODE>mode == SFmode || TARGET_LDC1_SDC1)"
"<ANYF:loadx>\t%0,%1(%2)"
[(set_attr "type" "fpidxload")
(set_attr "mode" "<ANYF:UNITMODE>")])
@@ -4203,7 +4203,7 @@
[(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
(match_operand:P 2 "register_operand" "d")))
(match_operand:ANYF 0 "register_operand" "f"))]
- "ISA_HAS_FP4"
+ "ISA_HAS_FP4 && (<MODE>mode == SFmode || TARGET_LDC1_SDC1)"
"<ANYF:storex>\t%0,%1(%2)"
[(set_attr "type" "fpidxstore")
(set_attr "mode" "<ANYF:UNITMODE>")])
diff --git a/gcc-4.6/gcc/config/mips/mips.opt b/gcc-4.6/gcc/config/mips/mips.opt
index cb4bbbe..bf09ef0 100644
--- a/gcc-4.6/gcc/config/mips/mips.opt
+++ b/gcc-4.6/gcc/config/mips/mips.opt
@@ -196,7 +196,7 @@ Use MIPS-3D instructions
mldc1-sdc1
Target Report Var(TARGET_LDC1_SDC1) Init(1)
-Use ldc1 and sdc1 instruction
+Use ldc1/ldxc1 and sdc1/sdxc1 instruction
mllsc
Target Report Mask(LLSC)