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authorChao-ying Fu <fu@mips.com>2012-12-10 15:48:15 -0800
committerAndrew Hsieh <andrewhsieh@google.com>2012-12-11 13:48:05 +0800
commit7609f724df8ca390935f63243fa72e1de39d00c6 (patch)
tree6c0cdf4fe21db474e175ceb2f9d86af84e3de888 /gcc-4.6
parent081453273c622c16a2d87b61f87a861261a08f07 (diff)
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Enable MIPS floating-point madd/msub/nmadd/nmsub/recip/rsqrt with 32-bit FPU.
Diffstat (limited to 'gcc-4.6')
-rw-r--r--gcc-4.6/gcc/config/mips/mips.h7
-rw-r--r--gcc-4.6/gcc/config/mips/mips.md6
2 files changed, 4 insertions, 9 deletions
diff --git a/gcc-4.6/gcc/config/mips/mips.h b/gcc-4.6/gcc/config/mips/mips.h
index 9600dcb..6e34a2a 100644
--- a/gcc-4.6/gcc/config/mips/mips.h
+++ b/gcc-4.6/gcc/config/mips/mips.h
@@ -864,7 +864,7 @@ enum mips_code_readable_setting {
FP madd and msub instructions, and the FP recip and recip sqrt
instructions. */
#define ISA_HAS_FP4 ((ISA_MIPS4 \
- || (ISA_MIPS32R2 && TARGET_FLOAT64) \
+ || ISA_MIPS32R2 \
|| ISA_MIPS64 \
|| ISA_MIPS64R2) \
&& !TARGET_MIPS16)
@@ -895,10 +895,7 @@ enum mips_code_readable_setting {
/* ISA has floating-point nmadd and nmsub instructions
'd = -((a * b) [+-] c)'. */
#define ISA_HAS_NMADD4_NMSUB4(MODE) \
- ((ISA_MIPS4 \
- || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
- || ISA_MIPS64 \
- || ISA_MIPS64R2) \
+ (ISA_HAS_FP4 \
&& (!TARGET_MIPS5400 || TARGET_MAD) \
&& !TARGET_MIPS16)
diff --git a/gcc-4.6/gcc/config/mips/mips.md b/gcc-4.6/gcc/config/mips/mips.md
index bb87103..3913df8 100644
--- a/gcc-4.6/gcc/config/mips/mips.md
+++ b/gcc-4.6/gcc/config/mips/mips.md
@@ -729,12 +729,10 @@
[(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
-;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
-;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
-;; so for safety's sake, we apply this restriction to all targets.
+;; instructions can be used.
(define_mode_attr recip_condition
[(SF "ISA_HAS_FP4")
- (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
+ (DF "ISA_HAS_FP4")
(V2SF "TARGET_SB1")])
;; This code iterator allows signed and unsigned widening multiplications