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author | Andrew Hsieh <andrewhsieh@google.com> | 2012-11-28 17:27:40 -0800 |
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committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | 2012-11-28 17:27:41 -0800 |
commit | 5bd430abc2568af86ea97f8133c23ca8dc383cd8 (patch) | |
tree | 0a3a082d16f2c3c8a241228cf68165e6403f9a9d /gcc-4.4.3 | |
parent | ab71b16e5ca5d6bfb9f298a5bf01db312047512d (diff) | |
parent | e9e89d212eb19a7cd0c503b9de93086d4c886257 (diff) | |
download | toolchain_gcc-5bd430abc2568af86ea97f8133c23ca8dc383cd8.tar.gz toolchain_gcc-5bd430abc2568af86ea97f8133c23ca8dc383cd8.tar.bz2 toolchain_gcc-5bd430abc2568af86ea97f8133c23ca8dc383cd8.zip |
Merge "Fix GCC 4.4.3 ARM ICE at postreload.c:396"
Diffstat (limited to 'gcc-4.4.3')
-rw-r--r-- | gcc-4.4.3/gcc/config/arm/arm-protos.h | 2 | ||||
-rw-r--r-- | gcc-4.4.3/gcc/config/arm/arm.c | 52 | ||||
-rw-r--r-- | gcc-4.4.3/gcc/config/arm/constraints.md | 13 | ||||
-rw-r--r-- | gcc-4.4.3/gcc/config/arm/neon.md | 2 |
4 files changed, 48 insertions, 21 deletions
diff --git a/gcc-4.4.3/gcc/config/arm/arm-protos.h b/gcc-4.4.3/gcc/config/arm/arm-protos.h index ee0a34393..5b94ba040 100644 --- a/gcc-4.4.3/gcc/config/arm/arm-protos.h +++ b/gcc-4.4.3/gcc/config/arm/arm-protos.h @@ -88,7 +88,7 @@ extern bool arm_cannot_force_const_mem (rtx); extern int cirrus_memory_offset (rtx); extern int arm_coproc_mem_operand (rtx, bool); -extern int neon_vector_mem_operand (rtx, bool); +extern int neon_vector_mem_operand (rtx, int); extern int neon_struct_mem_operand (rtx); extern int arm_no_early_store_addr_dep (rtx, rtx); extern int arm_no_early_alu_shift_dep (rtx, rtx); diff --git a/gcc-4.4.3/gcc/config/arm/arm.c b/gcc-4.4.3/gcc/config/arm/arm.c index 1be200980..054383ca0 100644 --- a/gcc-4.4.3/gcc/config/arm/arm.c +++ b/gcc-4.4.3/gcc/config/arm/arm.c @@ -8120,10 +8120,13 @@ arm_coproc_mem_operand (rtx op, bool wb) } /* Return TRUE if OP is a memory operand which we can load or store a vector - to/from. If CORE is true, we're moving from ARM registers not Neon - registers. */ + to/from. TYPE is one of the following values: + 0 - Vector load/stor (vldr) + 1 - Core registers (ldm) + 2 - Element/structure loads (vld1) + */ int -neon_vector_mem_operand (rtx op, bool core) +neon_vector_mem_operand (rtx op, int type) { rtx ind; @@ -8156,23 +8159,15 @@ neon_vector_mem_operand (rtx op, bool core) return arm_address_register_rtx_p (ind, 0); /* Allow post-increment with Neon registers. */ - if (!core && GET_CODE (ind) == POST_INC) + if (type != 1 && (GET_CODE (ind) == POST_INC || GET_CODE (ind) == PRE_DEC)) return arm_address_register_rtx_p (XEXP (ind, 0), 0); -#if 0 - /* FIXME: We can support this too if we use VLD1/VST1. */ - if (!core - && GET_CODE (ind) == POST_MODIFY - && arm_address_register_rtx_p (XEXP (ind, 0), 0) - && GET_CODE (XEXP (ind, 1)) == PLUS - && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0))) - ind = XEXP (ind, 1); -#endif + /* FIXME: vld1 allows register post-modify. */ /* Match: (plus (reg) (const)). */ - if (!core + if (type == 0 && GET_CODE (ind) == PLUS && GET_CODE (XEXP (ind, 0)) == REG && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) @@ -8242,7 +8237,7 @@ coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb) if (TARGET_NEON && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) - && neon_vector_mem_operand (x, FALSE)) + && neon_vector_mem_operand (x, 0)) return NO_REGS; if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode)) @@ -12031,7 +12026,7 @@ output_move_double (rtx *operands) } /* Output a move, load or store for quad-word vectors in ARM registers. Only - handles MEMs accepted by neon_vector_mem_operand with CORE=true. */ + handles MEMs accepted by neon_vector_mem_operand with TYPE=1. */ const char * output_move_quad (rtx *operands) @@ -12227,6 +12222,13 @@ output_move_neon (rtx *operands) ops[1] = reg; break; + case PRE_DEC: + /* FIXME: We should be using vld1/vst1 here in BE mode? */ + templ = "v%smdb%%?\t%%0!, %%h1"; + ops[0] = XEXP (addr, 0); + ops[1] = reg; + break; + case POST_MODIFY: /* FIXME: Not currently enabled in neon_vector_mem_operand. */ gcc_unreachable (); @@ -15094,6 +15096,24 @@ arm_print_operand (FILE *stream, rtx x, int code) } return; + /* Memory operand for vld1/vst1 instruction. */ + case 'A': + { + rtx addr; + bool postinc = FALSE; + gcc_assert (GET_CODE (x) == MEM); + addr = XEXP (x, 0); + if (GET_CODE (addr) == POST_INC) + { + postinc = 1; + addr = XEXP (addr, 0); + } + asm_fprintf (stream, "[%r]", REGNO (addr)); + if (postinc) + fputs("!", stream); + } + return; + default: if (x == 0) { diff --git a/gcc-4.4.3/gcc/config/arm/constraints.md b/gcc-4.4.3/gcc/config/arm/constraints.md index 8cab39a66..9bb29fd57 100644 --- a/gcc-4.4.3/gcc/config/arm/constraints.md +++ b/gcc-4.4.3/gcc/config/arm/constraints.md @@ -34,7 +34,7 @@ ;; in Thumb-2 state: Ps, Pt, Pw, Px ;; The following memory constraints have been used: -;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Us +;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us ;; in ARM state: Uq @@ -255,17 +255,24 @@ (define_memory_constraint "Un" "@internal + In ARM/Thumb-2 state a valid address for Neon doubleword vector + load/store instructions." + (and (match_code "mem") + (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0)"))) + +(define_memory_constraint "Um" + "@internal In ARM/Thumb-2 state a valid address for Neon element and structure load/store instructions." (and (match_code "mem") - (match_test "TARGET_32BIT && neon_vector_mem_operand (op, FALSE)"))) + (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)"))) (define_memory_constraint "Us" "@internal In ARM/Thumb-2 state a valid address for non-offset loads/stores of quad-word values in four ARM registers." (and (match_code "mem") - (match_test "TARGET_32BIT && neon_vector_mem_operand (op, TRUE)"))) + (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1)"))) (define_memory_constraint "Uq" "@internal diff --git a/gcc-4.4.3/gcc/config/arm/neon.md b/gcc-4.4.3/gcc/config/arm/neon.md index a3d3e73d2..01d84d814 100644 --- a/gcc-4.4.3/gcc/config/arm/neon.md +++ b/gcc-4.4.3/gcc/config/arm/neon.md @@ -481,7 +481,7 @@ /* FIXME: If the memory layout is changed in big-endian mode, output_move_vfp below must be changed to output_move_neon (which will use the - element/structure loads/stores), and the constraint changed to 'Un' instead + element/structure loads/stores), and the constraint changed to 'Um' instead of 'Uv'. */ switch (which_alternative) |