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| author | Iceberg Fu <fu@mips.com> | 2013-04-02 19:37:06 +0800 |
|---|---|---|
| committer | Andrew Hsieh <andrewhsieh@google.com> | 2013-04-02 20:35:29 +0800 |
| commit | fa511ab381bbecc4d999047a8de3f164ac99b908 (patch) | |
| tree | ece85273bd9519c8ec7a1b79377e8f66312191b0 | |
| parent | eceb576ea5b15a7f8f179f131b665afeeba1c6ad (diff) | |
| download | toolchain_gcc-fa511ab381bbecc4d999047a8de3f164ac99b908.tar.gz toolchain_gcc-fa511ab381bbecc4d999047a8de3f164ac99b908.tar.bz2 toolchain_gcc-fa511ab381bbecc4d999047a8de3f164ac99b908.zip | |
[4.8] Enable MIPS floating-point madd/msub/nmadd/nmsub/recip/rsqrt with 32-bit FPU.
See 7609f724df8ca390935f63243fa72e1de39d00c6
Change-Id: Id77b56a1cf886584020cf30a4211de0a87b4f56e
| -rw-r--r-- | gcc-4.8/gcc/config/mips/mips.h | 7 | ||||
| -rw-r--r-- | gcc-4.8/gcc/config/mips/mips.md | 6 |
2 files changed, 4 insertions, 9 deletions
diff --git a/gcc-4.8/gcc/config/mips/mips.h b/gcc-4.8/gcc/config/mips/mips.h index 0acce14bd..798a3cce9 100644 --- a/gcc-4.8/gcc/config/mips/mips.h +++ b/gcc-4.8/gcc/config/mips/mips.h @@ -855,7 +855,7 @@ struct mips_cpu_info { FP madd and msub instructions, and the FP recip and recip sqrt instructions. */ #define ISA_HAS_FP4 ((ISA_MIPS4 \ - || (ISA_MIPS32R2 && TARGET_FLOAT64) \ + || ISA_MIPS32R2 \ || ISA_MIPS64 \ || ISA_MIPS64R2) \ && !TARGET_MIPS16) @@ -886,10 +886,7 @@ struct mips_cpu_info { /* ISA has floating-point nmadd and nmsub instructions 'd = -((a * b) [+-] c)'. */ #define ISA_HAS_NMADD4_NMSUB4(MODE) \ - ((ISA_MIPS4 \ - || (ISA_MIPS32R2 && (MODE) == V2SFmode) \ - || ISA_MIPS64 \ - || ISA_MIPS64R2) \ + (ISA_HAS_FP4 \ && (!TARGET_MIPS5400 || TARGET_MAD) \ && !TARGET_MIPS16) diff --git a/gcc-4.8/gcc/config/mips/mips.md b/gcc-4.8/gcc/config/mips/mips.md index 7aa461dbd..3ca9d76a9 100644 --- a/gcc-4.8/gcc/config/mips/mips.md +++ b/gcc-4.8/gcc/config/mips/mips.md @@ -855,12 +855,10 @@ [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")]) ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt -;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D -;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs, -;; so for safety's sake, we apply this restriction to all targets. +;; instructions can be used. (define_mode_attr recip_condition [(SF "ISA_HAS_FP4") - (DF "ISA_HAS_FP4 && TARGET_FLOAT64") + (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")]) ;; This code iterator allows signed and unsigned widening multiplications |