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authorAndrew Hsieh <andrewhsieh@google.com>2012-11-02 09:54:19 -0700
committerGerrit Code Review <noreply-gerritcodereview@google.com>2012-11-02 09:54:20 -0700
commit09772f4a91b356043edd309ab37c8661c647fd23 (patch)
treeacbd1f009d96a8cae382b49339a5b4cd6301e051
parent6d08dc702e910635ad2a49e40b0b7e34f4f2090a (diff)
parent56ee0e6d36e35bbd4a1cda777359dcb7eaadb232 (diff)
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Merge "Add -mstack-protector-guard= to x86 compilers"
-rw-r--r--gcc-4.4.3/gcc/config/i386/i386.c19
-rw-r--r--gcc-4.4.3/gcc/config/i386/i386.h7
-rw-r--r--gcc-4.4.3/gcc/config/i386/i386.md6
-rw-r--r--gcc-4.4.3/gcc/config/i386/i386.opt4
-rw-r--r--gcc-4.6/gcc/config/i386/i386.c19
-rw-r--r--gcc-4.6/gcc/config/i386/i386.h6
-rw-r--r--gcc-4.6/gcc/config/i386/i386.md8
-rw-r--r--gcc-4.6/gcc/config/i386/i386.opt4
-rw-r--r--gcc-4.7/gcc/config/i386/i386-opts.h5
-rw-r--r--gcc-4.7/gcc/config/i386/i386.c6
-rw-r--r--gcc-4.7/gcc/config/i386/i386.md8
-rw-r--r--gcc-4.7/gcc/config/i386/i386.opt15
12 files changed, 96 insertions, 11 deletions
diff --git a/gcc-4.4.3/gcc/config/i386/i386.c b/gcc-4.4.3/gcc/config/i386/i386.c
index 31ce38a58..2ca822040 100644
--- a/gcc-4.4.3/gcc/config/i386/i386.c
+++ b/gcc-4.4.3/gcc/config/i386/i386.c
@@ -1810,6 +1810,9 @@ extern int ix86_force_align_arg_pointer;
static const char ix86_force_align_arg_pointer_string[]
= "force_align_arg_pointer";
+/* Stack protector option. */
+enum stack_protector_guard ix86_stack_protector_guard;
+
static rtx (*ix86_gen_leave) (void);
static rtx (*ix86_gen_pop1) (rtx);
static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
@@ -3435,6 +3438,22 @@ override_options (bool main_args_p)
flag_stack_check = 0;
target_flags |= MASK_STACK_PROBE;
}
+
+ /* Handle stack protector */
+ if (ix86_stack_protector_guard_string != 0)
+ {
+ if (!strcmp (ix86_stack_protector_guard_string, "tls"))
+ ix86_stack_protector_guard = SSP_TLS;
+ else if (!strcmp (ix86_stack_protector_guard_string, "global"))
+ ix86_stack_protector_guard = SSP_GLOBAL;
+ else
+ error ("bad value (%s) for %sstack-protector-guard=%s %s",
+ ix86_stack_protector_guard, prefix, suffix, sw);
+ }
+ else
+ {
+ ix86_stack_protector_guard = TARGET_HAS_BIONIC? SSP_GLOBAL : SSP_TLS;
+ }
}
/* Update register usage after having seen the compiler flags. */
diff --git a/gcc-4.4.3/gcc/config/i386/i386.h b/gcc-4.4.3/gcc/config/i386/i386.h
index d7cb8ac3c..d611fe632 100644
--- a/gcc-4.4.3/gcc/config/i386/i386.h
+++ b/gcc-4.4.3/gcc/config/i386/i386.h
@@ -2517,6 +2517,13 @@ struct machine_function GTY(())
#undef TARG_COND_NOT_TAKEN_BRANCH_COST
#define TARG_COND_NOT_TAKEN_BRANCH_COST ix86_cost->cond_not_taken_branch_cost
+enum stack_protector_guard {
+ SSP_TLS, /* per-thread canary at %gs:20 */
+ SSP_GLOBAL, /* global canary */
+};
+
+extern enum stack_protector_guard ix86_stack_protector_guard;
+
/*
Local variables:
version-control: t
diff --git a/gcc-4.4.3/gcc/config/i386/i386.md b/gcc-4.4.3/gcc/config/i386/i386.md
index 7989c31db..a1d7bcba2 100644
--- a/gcc-4.4.3/gcc/config/i386/i386.md
+++ b/gcc-4.4.3/gcc/config/i386/i386.md
@@ -21926,7 +21926,7 @@
(define_expand "stack_protect_set"
[(match_operand 0 "memory_operand" "")
(match_operand 1 "memory_operand" "")]
- ""
+ "ix86_stack_protector_guard == SSP_TLS"
{
#ifdef TARGET_THREAD_SSP_OFFSET
if (TARGET_64BIT)
@@ -21949,7 +21949,7 @@
(unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
(set (match_scratch:SI 2 "=&r") (const_int 0))
(clobber (reg:CC FLAGS_REG))]
- ""
+ "ix86_stack_protector_guard == SSP_TLS"
"mov{l}\t{%1, %2|%2, %1}\;mov{l}\t{%2, %0|%0, %2}\;xor{l}\t%2, %2"
[(set_attr "type" "multi")])
@@ -21992,7 +21992,7 @@
[(match_operand 0 "memory_operand" "")
(match_operand 1 "memory_operand" "")
(match_operand 2 "" "")]
- ""
+ "ix86_stack_protector_guard == SSP_TLS"
{
rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG);
ix86_compare_op0 = operands[0];
diff --git a/gcc-4.4.3/gcc/config/i386/i386.opt b/gcc-4.4.3/gcc/config/i386/i386.opt
index c2562e48d..880fc98ca 100644
--- a/gcc-4.4.3/gcc/config/i386/i386.opt
+++ b/gcc-4.4.3/gcc/config/i386/i386.opt
@@ -362,3 +362,7 @@ Support PCLMUL built-in functions and code generation
msse2avx
Target Report Var(ix86_sse2avx)
Encode SSE instructions with VEX prefix
+
+mstack-protector-guard=
+Target RejectNegative Joined Var(ix86_stack_protector_guard_string)
+Use given stack-protector guard
diff --git a/gcc-4.6/gcc/config/i386/i386.c b/gcc-4.6/gcc/config/i386/i386.c
index b99d31150..6e7eb6183 100644
--- a/gcc-4.6/gcc/config/i386/i386.c
+++ b/gcc-4.6/gcc/config/i386/i386.c
@@ -2369,6 +2369,9 @@ static int ix86_regparm;
static const char ix86_force_align_arg_pointer_string[]
= "force_align_arg_pointer";
+/* Stack protector option. */
+enum stack_protector_guard ix86_stack_protector_guard;
+
static rtx (*ix86_gen_leave) (void);
static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
@@ -4360,6 +4363,22 @@ ix86_option_override_internal (bool main_args_p)
}
free (token);
}
+
+ /* Handle stack protector */
+ if (ix86_stack_protector_guard_string != 0)
+ {
+ if (!strcmp (ix86_stack_protector_guard_string, "tls"))
+ ix86_stack_protector_guard = SSP_TLS;
+ else if (!strcmp (ix86_stack_protector_guard_string, "global"))
+ ix86_stack_protector_guard = SSP_GLOBAL;
+ else
+ error ("bad value (%s) for %sstack-protector-guard=%s %s",
+ ix86_stack_protector_guard, prefix, suffix, sw);
+ }
+ else
+ {
+ ix86_stack_protector_guard = TARGET_HAS_BIONIC? SSP_GLOBAL : SSP_TLS;
+ }
}
/* Return TRUE if VAL is passed in register with 256bit AVX modes. */
diff --git a/gcc-4.6/gcc/config/i386/i386.h b/gcc-4.6/gcc/config/i386/i386.h
index 678071f27..d7714f7e4 100644
--- a/gcc-4.6/gcc/config/i386/i386.h
+++ b/gcc-4.6/gcc/config/i386/i386.h
@@ -2378,6 +2378,12 @@ extern void debug_dispatch_window (int);
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI)
+enum stack_protector_guard {
+ SSP_TLS, /* per-thread canary at %gs:20 */
+ SSP_GLOBAL, /* global canary */
+};
+
+extern enum stack_protector_guard ix86_stack_protector_guard;
/*
Local variables:
diff --git a/gcc-4.6/gcc/config/i386/i386.md b/gcc-4.6/gcc/config/i386/i386.md
index b1d7e5eba..dcc2a21b2 100644
--- a/gcc-4.6/gcc/config/i386/i386.md
+++ b/gcc-4.6/gcc/config/i386/i386.md
@@ -17955,7 +17955,7 @@
(define_expand "stack_protect_set"
[(match_operand 0 "memory_operand" "")
(match_operand 1 "memory_operand" "")]
- ""
+ "ix86_stack_protector_guard == SSP_TLS"
{
rtx (*insn)(rtx, rtx);
@@ -17979,7 +17979,7 @@
(unspec:P [(match_operand:P 1 "memory_operand" "m")] UNSPEC_SP_SET))
(set (match_scratch:P 2 "=&r") (const_int 0))
(clobber (reg:CC FLAGS_REG))]
- ""
+ "ix86_stack_protector_guard == SSP_TLS"
"mov{<imodesuffix>}\t{%1, %2|%2, %1}\;mov{<imodesuffix>}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
[(set_attr "type" "multi")])
@@ -17997,7 +17997,7 @@
[(match_operand 0 "memory_operand" "")
(match_operand 1 "memory_operand" "")
(match_operand 2 "" "")]
- ""
+ "ix86_stack_protector_guard == SSP_TLS"
{
rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG);
@@ -18027,7 +18027,7 @@
(match_operand:P 2 "memory_operand" "m")]
UNSPEC_SP_TEST))
(clobber (match_scratch:P 3 "=&r"))]
- ""
+ "ix86_stack_protector_guard == SSP_TLS"
"mov{<imodesuffix>}\t{%1, %3|%3, %1}\;xor{<imodesuffix>}\t{%2, %3|%3, %2}"
[(set_attr "type" "multi")])
diff --git a/gcc-4.6/gcc/config/i386/i386.opt b/gcc-4.6/gcc/config/i386/i386.opt
index 9deba3e01..3f0e3f718 100644
--- a/gcc-4.6/gcc/config/i386/i386.opt
+++ b/gcc-4.6/gcc/config/i386/i386.opt
@@ -435,3 +435,7 @@ Split 32-byte AVX unaligned load
mavx256-split-unaligned-store
Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
Split 32-byte AVX unaligned store
+
+mstack-protector-guard=
+Target RejectNegative Joined Var(ix86_stack_protector_guard_string)
+Use given stack-protector guard
diff --git a/gcc-4.7/gcc/config/i386/i386-opts.h b/gcc-4.7/gcc/config/i386/i386-opts.h
index 3cc2253c3..8904491de 100644
--- a/gcc-4.7/gcc/config/i386/i386-opts.h
+++ b/gcc-4.7/gcc/config/i386/i386-opts.h
@@ -82,4 +82,9 @@ enum ix86_veclibabi {
ix86_veclibabi_type_acml
};
+enum stack_protector_guard {
+ SSP_TLS, /* per-thread canary at %gs:20 */
+ SSP_GLOBAL, /* global canary */
+};
+
#endif
diff --git a/gcc-4.7/gcc/config/i386/i386.c b/gcc-4.7/gcc/config/i386/i386.c
index adf911c64..c21cb81c1 100644
--- a/gcc-4.7/gcc/config/i386/i386.c
+++ b/gcc-4.7/gcc/config/i386/i386.c
@@ -3890,6 +3890,12 @@ ix86_option_override_internal (bool main_args_p)
if (main_args_p)
target_option_default_node = target_option_current_node
= build_target_option_node ();
+
+ /* Handle stack protector */
+ if (!global_options_set.x_ix86_stack_protector_guard)
+ {
+ ix86_stack_protector_guard = TARGET_HAS_BIONIC? SSP_GLOBAL : SSP_TLS;
+ }
}
/* Return TRUE if VAL is passed in register with 256bit AVX modes. */
diff --git a/gcc-4.7/gcc/config/i386/i386.md b/gcc-4.7/gcc/config/i386/i386.md
index d8deee8da..e006cc8fb 100644
--- a/gcc-4.7/gcc/config/i386/i386.md
+++ b/gcc-4.7/gcc/config/i386/i386.md
@@ -17722,7 +17722,7 @@
(define_expand "stack_protect_set"
[(match_operand 0 "memory_operand" "")
(match_operand 1 "memory_operand" "")]
- ""
+ "ix86_stack_protector_guard == SSP_TLS"
{
rtx (*insn)(rtx, rtx);
@@ -17747,7 +17747,7 @@
UNSPEC_SP_SET))
(set (match_scratch:PTR 2 "=&r") (const_int 0))
(clobber (reg:CC FLAGS_REG))]
- ""
+ "ix86_stack_protector_guard == SSP_TLS"
"mov{<imodesuffix>}\t{%1, %2|%2, %1}\;mov{<imodesuffix>}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
[(set_attr "type" "multi")])
@@ -17765,7 +17765,7 @@
[(match_operand 0 "memory_operand" "")
(match_operand 1 "memory_operand" "")
(match_operand 2 "" "")]
- ""
+ "ix86_stack_protector_guard == SSP_TLS"
{
rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG);
@@ -17795,7 +17795,7 @@
(match_operand:PTR 2 "memory_operand" "m")]
UNSPEC_SP_TEST))
(clobber (match_scratch:PTR 3 "=&r"))]
- ""
+ "ix86_stack_protector_guard == SSP_TLS"
"mov{<imodesuffix>}\t{%1, %3|%3, %1}\;xor{<imodesuffix>}\t{%2, %3|%3, %2}"
[(set_attr "type" "multi")])
diff --git a/gcc-4.7/gcc/config/i386/i386.opt b/gcc-4.7/gcc/config/i386/i386.opt
index 4008fd0fe..492490f14 100644
--- a/gcc-4.7/gcc/config/i386/i386.opt
+++ b/gcc-4.7/gcc/config/i386/i386.opt
@@ -581,3 +581,18 @@ Split 32-byte AVX unaligned load
mavx256-split-unaligned-store
Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
Split 32-byte AVX unaligned store
+
+mstack-protector-guard=
+Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS)
+Use given stack-protector guard
+
+Enum
+Name(stack_protector_guard) Type(enum stack_protector_guard)
+Known stack protector guard (for use with the -mstack-protector-guard= option):
+
+EnumValue
+Enum(stack_protector_guard) String(tls) Value(SSP_TLS)
+
+EnumValue
+Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
+