From 5e8c1cf25beccac1d22d10dc866912394f42771b Mon Sep 17 00:00:00 2001 From: Andrew Hsieh Date: Tue, 9 Dec 2014 17:57:18 +0800 Subject: [2.25] sync to a30720e3e633f275250e26f85ccae5dbdddfb6c6 local patches will be re-applied later commit a30720e3e633f275250e26f85ccae5dbdddfb6c6 Author: Alan Modra Date: Wed Nov 19 10:30:16 2014 +1030 daily update Change-Id: Ieb2a3f4dd2ecb289ac5305ff08d428b2847494ab --- binutils-2.25/include/opcode/sparc.h | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) (limited to 'binutils-2.25/include/opcode/sparc.h') diff --git a/binutils-2.25/include/opcode/sparc.h b/binutils-2.25/include/opcode/sparc.h index f05909fe..cf4ff1c6 100644 --- a/binutils-2.25/include/opcode/sparc.h +++ b/binutils-2.25/include/opcode/sparc.h @@ -1,6 +1,5 @@ /* Definitions for opcode table for the sparc. - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, - 2003, 2005, 2010, 2011 Free Software Foundation, Inc. + Copyright (C) 1989-2014 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and the GNU Binutils. @@ -101,6 +100,7 @@ typedef struct sparc_opcode /* This was called "delayed" in versions before the flags. */ unsigned int flags; unsigned int hwcaps; + unsigned int hwcaps2; short architecture; /* Bitmask of sparc_opcode_arch_val's. */ } sparc_opcode; @@ -116,7 +116,8 @@ typedef struct sparc_opcode #define F_PREF_ALIAS (F_ALIAS|F_PREFERRED) -/* These must match the HWCAP_* values precisely. */ +/* These must match the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_* + values precisely. See include/elf/sparc.h. */ #define HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */ #define HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */ #define HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */ @@ -149,6 +150,20 @@ typedef struct sparc_opcode #define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */ #define HWCAP_CRC32C 0x20000000 /* CRC32C insn */ +#define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */ +#define HWCAP2_VIS3B 0x00000002 /* VIS3 present on multiple chips */ +#define HWCAP2_ADP 0x00000004 /* Application Data Protection */ +#define HWCAP2_SPARC5 0x00000008 /* The 29 new fp and sub instructions */ +#define HWCAP2_MWAIT 0x00000010 /* mwait instruction and load/monitor ASIs */ +#define HWCAP2_XMPMUL 0x00000020 /* XOR multiple precision multiply */ +#define HWCAP2_XMONT 0x00000040 /* XOR Montgomery mult/sqr instructions */ +#define HWCAP2_NSEC \ + 0x00000080 /* pause insn with support for nsec timings */ +#define HWCAP2_FJATHHPC 0x00001000 /* Fujitsu HPC instrs */ +#define HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */ +#define HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */ + + /* All sparc opcodes are 32 bits, except for the `set' instruction (really a macro), which is 64 bits. It is handled as a special case. @@ -174,6 +189,7 @@ typedef struct sparc_opcode g frsd floating point register. H frsd floating point register (double/even). J frsd floating point register (quad/multiple of 4). + } frsd floating point register (double/even) that is == frs2 b crs1 coprocessor register c crs2 coprocessor register D crsd coprocessor register @@ -215,6 +231,7 @@ typedef struct sparc_opcode s %fprs. (v9) P %pc. (v9) W %tick. (v9) + { %mcdper. (v9b) o %asi. (v9) 6 %fcc0. (v9) 7 %fcc1. (v9) -- cgit v1.2.3