| Commit message (Collapse) | Author | Age | Files | Lines |
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About source code - The base version of this binutils is newer than that
of aosp/binutils-2.25, it is based on the binutils that is used to build
google products and ChromiumOS. And it contains *all* local Android
patches as well as all patches that are cherry-picked from upstream for
aosp/binutils-2.25 tree (up to Nov. 5 - 932d71b85). You may find the
detailed development history for this binutils tree here -
https://chromium.googlesource.com/chromiumos/third_party/binutils/+log/unification
(This CL is a combination of all the CLs in it. After this CL is
submitted the tree will be identical to
https://chromium.googlesource.com/chromiumos/third_party/binutils/+log/unification
at 2865a3615d80bd5f82d14d7e0484e84dc052596a)
About testing - We tested this binutils for both ChromiumOS and
Android. For android, we tested building N4, N5X, N6, N7, N9 using new
binutils, we also did a full-build of toolchain (by build.py) and built
a N5X image; for ChromiumOS - it passed ChromiumOS toolchain release
tests on all 4 platforms (x86, x86_64, arm32 and arm64).
Change-Id: I2bb2cf579f9458d0a8bc9612331dc7d5043e3d82
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Some early revisions of the Cortex-A53 have an erratum (843419).
The details of the erratum are quite complex and involve dynamic
conditions. For the purposes of the workaround we have simplified
the static conditions to an ADRP in the last two instructions of a
4KByte page, followed within four instructions by a load/store dependent
on the ADRP.
This patch adds support to conservatively scan for and workaround the erratum.
There are two different workaround strategies used. The first is to rewrite
ADRP instructions which form part of an erratum sequence with an ADR instruction.
In situations where the ADR provides insufficient offset the dependent
load or store instruction from the sequence is moved to a stub section
and branches are inserted from the original sequence to the relocated
instruction and back again.
Stub section sizes are rounded up to a multiple of 4096 in order to ensure
that the act of inserting work around stubs does not create more errata sequences.
Workaround stubs are always inserted into the stub section associated
with the input section containing the erratum sequence. This ensures that the
fully relocated form of the veneered load store instruction is available at the
point in time when the stub section is written.
2015-03-30 Tejas Belagod <tejas.belagod@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
Jiong Wang <jiong.wang@arm.com>
* bfd-in.h (bfd_elf64_aarch64_set_options)
(bfd_elf32_aarch64_set_options): Add parameter.
* bfd-in2.h: Regenerated.
* elfnn-aarch64.c (aarch64_erratum_843419_stub)
(_bfd_aarch64_adrp_p, _bfd_aarch64_erratum_843419_sequence_p)
(_bfd_aarch64_erratum_843419_stub_name)
(_bfd_aarch64_erratum_843419_fixup)
(_bfd_aarch64_erratum_843419_scan)
(_bfd_aarch64_erratum_843419_branch_to_stub)
(_bfd_aarch64_erratum_843419_p): Define.
(enum elf_aarch64_stub_type): Define
aarch64_stub_erratum_843419_veneer.
(struct elf_aarch64_stub_hash_entry): Define adrp_offset.
(struct elf_aarch64_link_hash_table): Define fix_erratum_843419
and fix_erratum_843419_adr.
(stub_hash_newfunc): Initialize adrp_offset;
(_bfd_aarch64_add_stub_entry_after): Define.
(aarch64_map_one_stub, aarch64_build_one_stub)
(aarch64_size_one_stub): Handle
aarch64_stub_erratum_843419_veneer.
(_bfd_aarch64_resize_stubs): Round stub section size.
(elfNN_aarch64_size_stubs): Add scan for 843419.
(bfd_elfNN_aarch64_set_options): Add parameter. Initialize
fix_erratum_843419 and fix_erratum_843419_adr.
(struct erratum_835769_branch_to_stub_data): Add info.
(elfNN_aarch64_write_section): Initialise info. Handle 843419.
(elfNN_aarch64_size_dynamic_sections): Handle 843419.
* elfxx-aarch64.c (_bfd_aarch64_decode_adrp_imm)
(_bfd_aarch64_sign_extend): Define.
(reencode_adr_imm): Remove static. Rename to:
(_bfd_aarch64_reencode_adr_imm): Define.
(_bfd_aarch64_elf_put_addend): Call _bfd_aarch64_reencode_adr_imm.
* elfxx-aarch64.h (AARCH64_ADR_OP, AARCH64_ADRP_OP)
(AARCH64_ADRP_OP_MASK, _bfd_aarch64_sign_extend)
(_bfd_aarch64_decode_adrp_imm, _bfd_aarch64_reencode_adr_imm):
Define.
ld/testsuite:
2015-03-24 Tejas Belagod <tejas.belagod@arm.com>
* emultempl/aarch64elf.em
(aarch64_elf_create_output_section_statements): Add parameter in
bfd_elf${ELFSIZE}_aarch64_set_options call.
(OPTION_FIX_ERRATUM_843419): Define.
(PARSE_AND_LIST_LONGOPTS): Add fix-cortex-a53-843419.
(PARSE_AND_LIST_ARGS_CASES): Add OPTION_FIX_ERRATUM_843419.
Change-Id: I758b04c90d431f4e72a978871d5a66676c413d92
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Ensure that injection of a stub section does not break a link where
there is an xpectation that flow of control can pass from one input
section to another simply by linking the input sections in series.
The solution here is to allow stub sections to be inserted after any
input section (existing behaviour), but inject an additional branch at
the start of each stub section such that control flow falling into the
stub section will branch over the stub section.
Change-Id: I8ccadcfb2f43e6409cb5a649087a47c0c8826b15
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Lower stub alignment from 8 to 4 bytes thus removing padding between
input section content and stub section content.
Change-Id: Ic3afff9bc2f013b4b47e181b269b40231385080a
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MXU support, and a fix to needed by gdbserver.
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local patches will be re-applied later
commit a30720e3e633f275250e26f85ccae5dbdddfb6c6
Author: Alan Modra <amodra@gmail.com>
Date: Wed Nov 19 10:30:16 2014 +1030
daily update
Change-Id: Ieb2a3f4dd2ecb289ac5305ff08d428b2847494ab
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For MIPS -mmsa support
Change-Id: I08c4f002fa7b33dec85ed75956e6ab551bb03c96
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