321 files changed, 96208 insertions, 0 deletions

diff --git a/binutils-2.25/include/COPYING b/binutils-2.25/include/COPYING
new file mode 100644
index 00000000..623b6258
--- /dev/null
+++ b/binutils-2.25/include/COPYING
@@ -0,0 +1,340 @@
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+     51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users.  This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it.  (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.)  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+  To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+  For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have.  You must make sure that they, too, receive or can get the
+source code.  And you must show them these terms so they know their
+rights.
+
+  We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+  Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software.  If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
+that any problems introduced by others will not reflect on the original
+authors' reputations.
+
+  Finally, any free program is threatened constantly by software
+patents.  We wish to avoid the danger that redistributors of a free
+program will individually obtain patent licenses, in effect making the
+program proprietary.  To prevent this, we have made it clear that any
+patent must be licensed for everyone's free use or not licensed at all.
+
+  The precise terms and conditions for copying, distribution and
+modification follow.
+
+		    GNU GENERAL PUBLIC LICENSE
+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+  0. This License applies to any program or other work which contains
+a notice placed by the copyright holder saying it may be distributed
+under the terms of this General Public License.  The "Program", below,
+refers to any such program or work, and a "work based on the Program"
+means either the Program or any derivative work under copyright law:
+that is to say, a work containing the Program or a portion of it,
+either verbatim or with modifications and/or translated into another
+language.  (Hereinafter, translation is included without limitation in
+the term "modification".)  Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope.  The act of
+running the Program is not restricted, and the output from the Program
+is covered only if its contents constitute a work based on the
+Program (independent of having been made by running the Program).
+Whether that is true depends on what the Program does.
+
+  1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
+conspicuously and appropriately publish on each copy an appropriate
+copyright notice and disclaimer of warranty; keep intact all the
+notices that refer to this License and to the absence of any warranty;
+and give any other recipients of the Program a copy of this License
+along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and
+you may at your option offer warranty protection in exchange for a fee.
+
+  2. You may modify your copy or copies of the Program or any portion
+of it, thus forming a work based on the Program, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+    a) You must cause the modified files to carry prominent notices
+    stating that you changed the files and the date of any change.
+
+    b) You must cause any work that you distribute or publish, that in
+    whole or in part contains or is derived from the Program or any
+    part thereof, to be licensed as a whole at no charge to all third
+    parties under the terms of this License.
+
+    c) If the modified program normally reads commands interactively
+    when run, you must cause it, when started running for such
+    interactive use in the most ordinary way, to print or display an
+    announcement including an appropriate copyright notice and a
+    notice that there is no warranty (or else, saying that you provide
+    a warranty) and that users may redistribute the program under
+    these conditions, and telling the user how to view a copy of this
+    License.  (Exception: if the Program itself is interactive but
+    does not normally print such an announcement, your work based on
+    the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole.  If
+identifiable sections of that work are not derived from the Program,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works.  But when you
+distribute the same sections as part of a whole which is a work based
+on the Program, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Program.
+
+In addition, mere aggregation of another work not based on the Program
+with the Program (or with a work based on the Program) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+  3. You may copy and distribute the Program (or a work based on it,
+under Section 2) in object code or executable form under the terms of
+Sections 1 and 2 above provided that you also do one of the following:
+
+    a) Accompany it with the complete corresponding machine-readable
+    source code, which must be distributed under the terms of Sections
+    1 and 2 above on a medium customarily used for software interchange; or,
+
+    b) Accompany it with a written offer, valid for at least three
+    years, to give any third party, for a charge no more than your
+    cost of physically performing source distribution, a complete
+    machine-readable copy of the corresponding source code, to be
+    distributed under the terms of Sections 1 and 2 above on a medium
+    customarily used for software interchange; or,
+
+    c) Accompany it with the information you received as to the offer
+    to distribute corresponding source code.  (This alternative is
+    allowed only for noncommercial distribution and only if you
+    received the program in object code or executable form with such
+    an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for
+making modifications to it.  For an executable work, complete source
+code means all the source code for all modules it contains, plus any
+associated interface definition files, plus the scripts used to
+control compilation and installation of the executable.  However, as a
+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
+form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component
+itself accompanies the executable.
+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+  4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License.  Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+  5. You are not required to accept this License, since you have not
+signed it.  However, nothing else grants you permission to modify or
+distribute the Program or its derivative works.  These actions are
+prohibited by law if you do not accept this License.  Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+  6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions.  You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+  7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License.  If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all.  For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices.  Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+  8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded.  In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+  9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time.  Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number.  If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation.  If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+  10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission.  For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this.  Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+			    NO WARRANTY
+
+  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+		     END OF TERMS AND CONDITIONS
+
+	    How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) <year>  <name of author>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+    Gnomovision version 69, Copyright (C) year  name of author
+    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary.  Here is a sample; alter the names:
+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  <signature of Ty Coon>, 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs.  If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library.  If this is what you want to do, use the GNU Library General
+Public License instead of this License.
diff --git a/binutils-2.25/include/COPYING3 b/binutils-2.25/include/COPYING3
new file mode 100644
index 00000000..94a9ed02
--- /dev/null
+++ b/binutils-2.25/include/COPYING3
@@ -0,0 +1,674 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+                            Preamble
+
+  The GNU General Public License is a free, copyleft license for
+software and other kinds of works.
+
+  The licenses for most software and other practical works are designed
+to take away your freedom to share and change the works.  By contrast,
+the GNU General Public License is intended to guarantee your freedom to
+share and change all versions of a program--to make sure it remains free
+software for all its users.  We, the Free Software Foundation, use the
+GNU General Public License for most of our software; it applies also to
+any other work released this way by its authors.  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+them if you wish), that you receive source code or can get it if you
+want it, that you can change the software or use pieces of it in new
+free programs, and that you know you can do these things.
+
+  To protect your rights, we need to prevent others from denying you
+these rights or asking you to surrender the rights.  Therefore, you have
+certain responsibilities if you distribute copies of the software, or if
+you modify it: responsibilities to respect the freedom of others.
+
+  For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must pass on to the recipients the same
+freedoms that you received.  You must make sure that they, too, receive
+or can get the source code.  And you must show them these terms so they
+know their rights.
+
+  Developers that use the GNU GPL protect your rights with two steps:
+(1) assert copyright on the software, and (2) offer you this License
+giving you legal permission to copy, distribute and/or modify it.
+
+  For the developers' and authors' protection, the GPL clearly explains
+that there is no warranty for this free software.  For both users' and
+authors' sake, the GPL requires that modified versions be marked as
+changed, so that their problems will not be attributed erroneously to
+authors of previous versions.
+
+  Some devices are designed to deny users access to install or run
+modified versions of the software inside them, although the manufacturer
+can do so.  This is fundamentally incompatible with the aim of
+protecting users' freedom to change the software.  The systematic
+pattern of such abuse occurs in the area of products for individuals to
+use, which is precisely where it is most unacceptable.  Therefore, we
+have designed this version of the GPL to prohibit the practice for those
+products.  If such problems arise substantially in other domains, we
+stand ready to extend this provision to those domains in future versions
+of the GPL, as needed to protect the freedom of users.
+
+  Finally, every program is threatened constantly by software patents.
+States should not allow patents to restrict development and use of
+software on general-purpose computers, but in those that do, we wish to
+avoid the special danger that patents applied to a free program could
+make it effectively proprietary.  To prevent this, the GPL assures that
+patents cannot be used to render the program non-free.
+
+  The precise terms and conditions for copying, distribution and
+modification follow.
+
+                       TERMS AND CONDITIONS
+
+  0. Definitions.
+
+  "This License" refers to version 3 of the GNU General Public License.
+
+  "Copyright" also means copyright-like laws that apply to other kinds of
+works, such as semiconductor masks.
+
+  "The Program" refers to any copyrightable work licensed under this
+License.  Each licensee is addressed as "you".  "Licensees" and
+"recipients" may be individuals or organizations.
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+in a fashion requiring copyright permission, other than the making of an
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+earlier work or a work "based on" the earlier work.
+
+  A "covered work" means either the unmodified Program or a work based
+on the Program.
+
+  To "propagate" a work means to do anything with it that, without
+permission, would make you directly or secondarily liable for
+infringement under applicable copyright law, except executing it on a
+computer or modifying a private copy.  Propagation includes copying,
+distribution (with or without modification), making available to the
+public, and in some countries other activities as well.
+
+  To "convey" a work means any kind of propagation that enables other
+parties to make or receive copies.  Mere interaction with a user through
+a computer network, with no transfer of a copy, is not conveying.
+
+  An interactive user interface displays "Appropriate Legal Notices"
+to the extent that it includes a convenient and prominently visible
+feature that (1) displays an appropriate copyright notice, and (2)
+tells the user that there is no warranty for the work (except to the
+extent that warranties are provided), that licensees may convey the
+work under this License, and how to view a copy of this License.  If
+the interface presents a list of user commands or options, such as a
+menu, a prominent item in the list meets this criterion.
+
+  1. Source Code.
+
+  The "source code" for a work means the preferred form of the work
+for making modifications to it.  "Object code" means any non-source
+form of a work.
+
+  A "Standard Interface" means an interface that either is an official
+standard defined by a recognized standards body, or, in the case of
+interfaces specified for a particular programming language, one that
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+
+  The "System Libraries" of an executable work include anything, other
+than the work as a whole, that (a) is included in the normal form of
+packaging a Major Component, but which is not part of that Major
+Component, and (b) serves only to enable use of the work with that
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+"Major Component", in this context, means a major essential component
+(kernel, window system, and so on) of the specific operating system
+(if any) on which the executable work runs, or a compiler used to
+produce the work, or an object code interpreter used to run it.
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+  The "Corresponding Source" for a work in object code form means all
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+includes interface definition files associated with source files for
+the work, and the source code for shared libraries and dynamically
+linked subprograms that the work is specifically designed to require,
+such as by intimate data communication or control flow between those
+subprograms and other parts of the work.
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+  The Corresponding Source need not include anything that users
+can regenerate automatically from other parts of the Corresponding
+Source.
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+  The Corresponding Source for a work in source code form is that
+same work.
+
+  2. Basic Permissions.
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+  All rights granted under this License are granted for the term of
+copyright on the Program, and are irrevocable provided the stated
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+  You may make, run and propagate covered works that you do not
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+for you must do so exclusively on your behalf, under your direction
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+users, your or third parties' legal rights to forbid circumvention of
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+  You may convey verbatim copies of the Program's source code as you
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+keep intact all notices of the absence of any warranty; and give all
+recipients a copy of this License along with the Program.
+
+  You may charge any price or no price for each copy that you convey,
+and you may offer support or warranty protection for a fee.
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+  5. Conveying Modified Source Versions.
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+  You may convey a work based on the Program, or the modifications to
+produce it from the Program, in the form of source code under the
+terms of section 4, provided that you also meet all of these conditions:
+
+    a) The work must carry prominent notices stating that you modified
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+    7.  This requirement modifies the requirement in section 4 to
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+    c) You must license the entire work, as a whole, under this
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+    invalidate such permission if you have separately received it.
+
+    d) If the work has interactive user interfaces, each must display
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+beyond what the individual works permit.  Inclusion of a covered work
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diff --git a/binutils-2.25/include/ChangeLog b/binutils-2.25/include/ChangeLog
new file mode 100644
index 00000000..f8ddfb25
--- /dev/null
+++ b/binutils-2.25/include/ChangeLog
@@ -0,0 +1,2007 @@
+2014-01-21  Tom Tromey  <tromey@redhat.com>
+
+	* ansidecl.h (ANSI_PROTOTYPES, PTRCONST, LONG_DOUBLE, PARAMS)
+	(VPARAMS, VA_START, VA_OPEN, VA_CLOSE, VA_FIXEDARG, CONST)
+	(VOLATILE, SIGNED, PROTO, EXFUN, DEFUN, DEFUN_VOID, AND, DOTS)
+	(NOARGS): Don't define.
+	* libiberty.h (expandargv, writeargv): Don't use PARAMS.
+
+2013-12-23  Bill Maddox  <maddox@google.com>
+
+	* demangle.h (enum gnu_v3_ctor_kinds):
+	Added literal gnu_v3_unified_ctor.
+	(enum gnu_v3_ctor_kinds):
+	Added literal gnu_v3_unified_dtor.
+
+2013-12-04  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* longlong.h: New file.
+
+2013-10-29  Marc Glisse  <marc.glisse@inria.fr>
+
+	PR tree-optimization/58689
+	* ansidecl.h (ATTRIBUTE_RETURNS_NONNULL): New macro.
+	* libiberty.h (basename, lbasename, dos_lbasename, unix_lbasename,
+	concat_copy): Mark with attributes nonnull(1) and returns_nonnull.
+	(concat, reconcat, concat_copy2, choose_temp_base, xstrerror,
+	xmalloc, xrealloc, xcalloc, xstrdup, xstrndup, xmemdup, pex_init):
+	Mark with attribute returns_nonnull.
+
+2013-10-22  Sterling Augustine  <saugustine@google.com>
+
+	* gdb/gdb-index.h: Merge from gdb tree.
+
+2013-10-10  Sean Keys <skeys@ipdatasys.com>
+
+	* xgate.h : Cleanup after opcode
+        table modification..
+
+2013-08-20  Alan Modra  <amodra@gmail.com>
+
+	* floatformat.h (floatformat_ibm_long_double): Delete.
+	(floatformat_ibm_long_double_big): Declare.
+	(floatformat_ibm_long_double_little): Declare.
+
+2013-08-19  Dehao Chen  <dehao@google.com>
+
+	* dwarf2.def (DW_AT_GNU_discriminator): New attribute.
+
+2013-08-02  Caroline Tice  <cmtice@google.com>
+
+	* vtv-change-permission.h: New file.
+
+2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
+            Konrad Eisele  <konrad@gaisler.com>
+
+	* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_LEON.
+
+2013-06-08  Catherine Moore  <clm@codesourcery.com>
+
+	* opcode/mips.h (mips_opcode): Add ase field.
+	(INSN_ASE_MASK): Delete.
+	(INSN_DSP): Rename to ASE_DSP.  Provide new value.
+	(INSN_DSPR2): Rename to ASE_DSPR2.  Provide new value.
+	(INSN_MCU): Rename to ASE_MCU.  Provide new value.
+	(INSN_MDMX): Rename to ASE_MDMX.  Provide new value.
+	(INSN_MIPS3d): Rename to ASE_MIPS3D.  Provide new value.
+	(INSN_MT): Rename to ASE_MT.  Provide new value.
+	(INSN_SMARTMIPS): Rename to ASE_SMARTMIPS.  Provide new value.
+	(INSN_VIRT): Rename to ASE_VIRT.  Provide new value.
+	(INSN_VIRT64): Rename to ASE_VIRT64.  Provide new value.
+	(opcode_is_member): Add ase argument.  Check ase.
+
+2013-05-06  Paul Brook  <paul@codesourcery.com>
+
+        include/elf/
+        * mips.h (R_MIPS_PC32): Update comment.
+
+2013-04-03  Jason Merrill  <jason@redhat.com>
+
+	Demangle C++11 ref-qualifier.
+	* demangle.h (enum demangle_component_type): Add
+	DEMANGLE_COMPONENT_REFERENCE_THIS,
+	DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS.
+
+2013-03-12  Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* opcode/nios2.h: Edit comment.
+
+2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* opcode/nios2.h (OPX_WRPRS): New define.
+	(OP_MATCH_WRPRS): Likewise.
+
+2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* opcode/nios2.h (OP_RDPRS): New define.
+	(OP_MATCH_RDPRS): Likewise.
+
+2013-03-01  Cary Coutant  <ccoutant@google.com>
+
+	* dwarf2.h (enum dwarf_sect): New enum type.
+
+2013-02-19  Alan Modra  <amodra@gmail.com>
+
+	* bfdlink.h (struct bfd_link_info): Delete emit_note_gnu_build_id.
+
+2013-02-11  Sriraman Tallam  <tmsriram@google.com>
+
+	* plugin-api.h (enum ld_plugin_level): Assign integers
+	explicitly for all values.
+
+2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
+            Andrew Jenner <andrew@codesourcery.com>
+
+	Based on patches from Altera Corporation.
+
+	* dis-asm.h (print_insn_big_nios2): Declare.
+	(print_insn_little_nios2): Declare.
+
+2013-01-30  Kai Tietz  <ktietz@redhat.com>
+
+	PR other/54620
+	PR target/39064
+	* md5.h (md5_uintptr, md5_uint32): Define as uintptr_t/uint32_t if
+	stdint.h and sys/types.h headers are present.
+	* sha1.h (sha1_uintptr, sha1_uint32): Likewise.
+
+2013-01-10  Will Newton <will.newton@imgtec.com>
+
+	* dis-asm.h (print_insn_metag): New declaration.
+
+2012-12-18  Aldy Hernandez  <aldyh@redhat.com>
+
+	PR other/54324
+	* ansidecl.h (ATTRIBUTE_UNUSED): Do not set __attribute__ for GCC
+	< 3.4.
+
+2012-12-17  Nick Clifton  <nickc@redhat.com>
+
+	* MAINTAINERS: Add copyright notice.
+	* alloca-conf.h: Likewise.
+	* fopen-bin.h: Likewise.
+	* fopen-same.h: Likewise.
+	* fopen-vms.h: Likewise.
+	* aout/hppa.h: Likewise.
+	* opcode/tahoe.h: Likewise.
+
+2012-12-11  Edgar E. Iglesias <edgar.iglesias@gmail.com>
+
+	* elf/microblaze.h: Add TLS relocs to START_RELOC_NUMBERS
+
+2012-11-09  Jason Merrill  <jason@redhat.com>
+
+	* demangle.h (enum demangle_component_type): Add
+	DEMANGLE_COMPONENT_TAGGED_NAME.
+
+2012-10-29  Sterling Augustine <saugustine@google.com>
+            Cary Coutant <ccoutant@google.com>
+
+	* dwarf2.h (dwarf_location_list_entry_type): New enum with fields
+	DW_LLE_GNU_end_of_list_entry, DW_LLE_GNU_base_address_selection_entry,
+	DW_LLE_GNU_start_end_entry and DW_LLE_GNU_start_length_entry.
+
+
+2012-10-26  Shinichiro Hamaji  <shinichiro.hamaji@gmail.com>
+
+	* dwarf2.h (DW_AT_APPLE_optimized, DW_AT_APPLE_flags)
+	(DW_AT_APPLE_isa, DW_AT_APPLE_block)
+	(DW_AT_APPLE_major_runtime_vers, DW_AT_APPLE_runtime_class)
+	(DW_AT_APPLE_omit_frame_ptr, DW_AT_APPLE_property_name)
+	(DW_AT_APPLE_property_getter, DW_AT_APPLE_property_setter)
+	(DW_AT_APPLE_property_attribute, DW_AT_APPLE_objc_complete_type)
+	(DW_AT_APPLE_property, DW_OP_GNU_entry_value): New macros.
+
+2012-10-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* bfdlink.h (bfd_link_info): Add
+	disable_target_specific_optimizations.
+
+2012-10-23  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* bfdlink.h (struct bfd_link_info): Add stacksize option.
+
+2012-10-22  Jan Beich  <jbeich@tormail.org>
+
+	PR ld/14426
+	* bfdlink.h (bfd_link_info): Add ignore_hash.
+
+2012-10-08  Jason Merrill  <jason@redhat.com>
+
+	* demangle.h (enum demangle_component_type): Add
+	DEMANGLE_COMPONENT_TLS_INIT and DEMANGLE_COMPONENT_TLS_WRAPPER.
+
+2012-09-18  Florian Weimer  <fweimer@redhat.com>
+
+	PR other/54411
+	* objalloc.h (objalloc_alloc): Do not use fast path on wraparound.
+
+2012-09-27  Anthony Green  <green@moxielogic.com>
+
+	* opcode/moxie.h (MOXIE_BAD): New define.
+
+2012-09-12  Chris Schlumberger-Socha  <chris.schlumberger-socha@arm.com>
+
+	* elf/aarch64.h (R_AARCH64_GOT_LD_PREL19): New reloc.
+
+2012-09-06  Cary Coutant  <ccoutant@google.com>
+
+	* dwarf2.def: Edit comment.
+
+2012-08-24  Sriraman Tallam  <tmsriram@google.com>
+
+	* plugin-api.h (ld_plugin_allow_unique_segment_for_sections):
+	New interface.
+	(ld_plugin_unique_segment_for_sections): New interface.
+	(LDPT_ALLOW_UNIQUE_SEGMENT_FOR_SECTIONS): New enum val.
+	(LDPT_UNIQUE_SEGMENT_FOR_SECTIONS): New enum val.
+	(tv_allow_unique_segment_for_sections): New member.
+	(tv_unique_segment_for_sections): New member.
+
+2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+	* opcode/arm.h (ARM_CPU_IS_ANY): New define.
+
+2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+	* elf/arm.h (TAG_CPU_ARCH_V8): New define.
+	(MAX_TAG_CPU_ARCH): Update.
+	* opcode/arm.h (ARM_EXT_V8): New define.
+	(FPU_VFP_EXT_ARMV8): Likewise.
+	(FPU_NEON_EXT_ARMV8): Likewise.
+	(FPU_CRYPTO_EXT_ARMV8): Likewise.
+	(ARM_AEXT_V8A): Likewise.
+	(FPU_VFP_ARMV8): Likwise.
+	(FPU_NEON_ARMV8): Likewise.
+	(FPU_CRYPTO_ARMV8): Likewise.
+	(FPU_ARCH_VFP_ARMV8): Likewise.
+	(FPU_ARCH_NEON_VFP_ARMV8): Likewise.
+	(FPU_ARCH_CRYPTO_NEON_VFP_ARMV8): Likewise.
+	(ARM_ARCH_V8A): Likwise.
+	(ARM_ARCH_V8A_FP): Likewise.
+	(ARM_ARCH_V8A_SIMD): Likewise.
+	(ARM_ARCH_V8A_CRYPTO): Likewise.
+
+2012-08-13  Ian Bolton  <ian.bolton@arm.com>
+            Laurent Desnogues  <laurent.desnogues@arm.com>
+            Jim MacArthur  <jim.macarthur@arm.com>
+            Marcus Shawcroft  <marcus.shawcroft@arm.com>
+            Nigel Stephens  <nigel.stephens@arm.com>
+            Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+            Richard Earnshaw  <rearnsha@arm.com>
+            Sofiane Naci  <sofiane.naci@arm.com>
+            Tejas Belagod  <tejas.belagod@arm.com>
+            Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* dis-asm.h (print_insn_aarch64): New declaration.
+	(print_aarch64_disassembler_options): New declaration.
+	(aarch64_symbol_is_valid): New declaration.
+
+2012-08-02  Sean Keys  <skeys@ipdatasys.com>
+
+	* elf/m68hc11.h: #define E_M68HC11_NO_BANK_WARNING 0x000000200
+
+2012-07-24  Stephan McCamant  <smcc@cs.berkeley.edu>
+            Dr David Alan Gilbert  <dave@treblig.org>
+
+	PR binutils/13135
+	* dis-asm.h (fprintf_ftype): Add ATTRIBUTE_FPTR_PRINTF_2.
+
+2012-07-13  Doug Evans  <dje@google.com>
+
+	* filenames.h: #include "hashtab.h".
+	(filename_hash, filename_eq): Declare.
+
+2012-07-13  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* elf/s390.h (START_RELOC_NUMBERS): Define R_390_IRELATIVE reloc.
+
+2012-07-05  Sean Keys  <skeys@ipdatasys.com>
+
+	* opcode/xgate.h: Changed the format string for mode
+	XGATE_OP_DYA_MON.
+
+2012-06-18  Doug Evans  <dje@google.com>
+
+	* dwarf2.def (DW_OP): Add DW_OP_GNU_const_index.
+
+2012-06-12  Rafael �vila de Espíndola <respindola@mozilla.com>
+
+	* plugin-api.h (ld_plugin_output_file_type): Add LDPO_PIE.
+
+2012-06-08  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2.def (DW_FORM_GNU_ref_alt, DW_FORM_GNU_strp_alt): New
+	forms.
+	* dwarf2.h (enum dwarf_macro_record_type): Add
+	DW_MACRO_GNU_define_indirect_alt, DW_MACRO_GNU_undef_indirect_alt
+	and DW_MACRO_GNU_transparent_include_alt.
+
+2012-05-23  Doug Evans  <dje@google.com>
+
+	* leb128.h: #include stdint.h, inttypes.h.
+	(read_uleb128_to_uint64): Renamed from read_uleb128_to_ull.
+	Change to take a uint64_t * argument instead of unsigned long long.
+	(read_sleb128_to_uint64): Renamed from read_sleb128_to_ll.
+	Change to take an int64_t * argument instead of long long.
+
+2012-05-22  Doug Evans  <dje@google.com>
+
+	* leb128.h: New file.
+
+2012-05-19  Gary Funck  <gary@intrepid.com>
+
+	* dwarf2.def: Update comment re: UPC extensions to reference
+	DWARF4 specification.
+
+2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
+
+	* dis-asm.h (print_insn_m9s12x): Prototype.
+	(print_insn_m9s12xg): Prototype.
+
+2012-05-03  Sean Keys  <skeys@ipdatasys.com>
+
+	* dis-asm.h (print_insn_xgate): Define.
+	(print_insn_xgate): Ditto.
+	Added new files for XGATE port.
+
+2012-05-02  Cary Coutant  <ccoutant@google.com>
+
+	* dwarf2.def: Remove DW_FORM_GNU_ref_index,
+	replace DW_AT_GNU_ref_base with DW_AT_GNU_ranges_base.
+
+2012-04-28  Doug Evans  <dje@google.com>
+
+	* dwarf2.def (DW_OP): Add DW_OP_GNU_addr_index.
+
+2012-04-27  Tom Tromey  <tromey@redhat.com>
+
+	* dwarf2.h: Wrap function declarations in extern "C".
+
+2012-04-27  Tom Tromey  <tromey@redhat.com>
+
+	* dwarf2.h (enum dwarf_tag, enum dwarf_form, enum dwarf_attribute)
+	(enum dwarf_location_atom, enum dwarf_type, enum
+	dwarf_call_frame_info): Remove.
+	(DW_TAG, DW_TAG_DUP, DW_FORM, DW_AT, DW_AT_DUP, DW_OP)
+	(DW_OP_DUP, DW_ATE, DW_ATE_DUP, DW_CFA): New macros.
+	Include dwarf2.def.
+	(get_DW_TAG_name, get_DW_AT_name, get_DW_FORM_name)
+	(get_DW_OP_name, get_DW_ATE_name): Declare.
+	* dwarf2.def: New file, from dwarf2.h.
+
+2012-04-12  David S. Miller  <davem@davemloft.net>
+
+	* elf/sparc.h (R_SPARC_WDISP10): New reloc.
+	* opcode/sparc.h: Define '=' as generating R_SPARC_WDISP10.
+
+2012-04-10  Tristan Gingold  <gingold@adacore.com>
+
+	* splay-tree.h: Conditionnaly includes stdint.h and inttypes.h
+	(libi_uhostptr_t, libi_shostptr_t): Remove, replaced by uintptr_t.
+
+2012-04-09  Roland McGrath  <mcgrathr@google.com>
+
+	* bfdlink.h (struct bfd_link_info): Add new member user_phdrs.
+
+2012-03-15  Alan Modra  <amodra@gmail.com>
+
+	* dis-asm.h (disassemble_init_powerpc): Declare.
+
+2009-11-06  Jonas Maebe  <jonas.maebe@elis.ugent.be>
+
+	Add DWARF attribute value for the "Borland fastcall" calling
+	convention.
+	* elf/dwarf2.h: Add DW_CC_GNU_borland_fastcall_i386 constant.
+
+2012-01-31  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/13616
+	* bfdlink.h (bfd_link_order): Update comments on data size.
+
+2012-01-26  Cary Coutant  <ccoutant@google.com>
+
+	* dwarf2.h (enum dwarf_form): Add Fission extensions.
+	(enum dwarf_attribute): Likewise.
+
+2012-01-06  Jason Merrill  <jason@redhat.com>
+
+	PR c++/6057
+	PR c++/48051
+	PR c++/50855
+	PR c++/51322
+	* demangle.h (enum demangle_component_type): Add
+	DEMANGLE_COMPONENT_INITIALIZER_LIST, DEMANGLE_COMPONENT_NULLARY.
+
+2011-12-14  Iain Sandoe  <iains@gcc.gnu.org>
+
+	* mach-o/loader.h (bfd_mach_o_section_type): define
+	BFD_MACH_O_S_ATTR_NONE to 0.
+
+2011-11-07  Richard Henderson  <rth@redhat.com>
+
+	Merged from transactional-memory.
+
+	* demangle.h (enum gnu_v3_ctor_kinds): Add gnu_v3_object_ctor_group.
+	(enum gnu_v3_dtor_kinds): Add gnu_v3_object_dtor_group.
+	(DEMANGLE_COMPONENT_TRANSACTION_CLONE): New.
+	(DEMANGLE_COMPONENT_NONTRANSACTION_CLONE): New.
+
+2011-11-01  DJ Delorie  <dj@redhat.com>
+
+	* dis-asm.h (print_insn_rl78): Declare.
+
+2011-10-25  Joern Rennecke  <joern.rennecke@embecosm.com>
+
+	* dis-asm.h (print_insn_epiphany): Declare.
+
+2011-10-21  Ulrich Drepper  <drepper@gmail.com>
+
+	* obstack.h [!GNUC] (obstack_free): Avoid cast to int.
+
+2011-10-21  Marc Glisse  <marc.glisse@inria.fr>
+
+	* ansidecl.h (ENUM_BITFIELD): Always use enum in C++
+
+2011-10-19  Alan Modra  <amodra@gmail.com>
+
+	PR ld/13254
+	* bfdlink.h (struct bfd_link_info): Add error_textrel.
+
+2011-09-28  Doug Evans  <dje@google.com>
+
+	* timeval-utils.h: New file.
+
+	* libiberty.h (countargv): Declare.
+
+2011-09-26  Cary Coutant  <ccoutant@google.com>
+
+	gcc PR lto/47247
+	* plugin-api.h (enum ld_plugin_symbol_resolution): Add
+	LDPR_PREVAILING_DEF_IRONLY_EXP.
+	(enum ld_plugin_tag): Add LDPT_GET_SYMBOLS_V2.
+
+2011-09-23  Cary Coutant  <ccoutant@google.com>
+
+	PR 40831
+	* demangle.h (enum demangle_component_type): Add
+	DEMANGLE_COMPONENT_CLONE.
+
+2011-09-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/12975
+	* bfdlink.h (bfd_link_info): Add version_info.
+
+2011-07-25  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+	* xregex.h (regoff_t): Define.
+
+2011-07-22  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2.h (DW_AT_GNU_macros): New.
+	(enum dwarf_macro_record_type): New enum.  Add DW_MACRO_GNU_*.
+
+	PR c++/49756
+	* libiberty.h (stack_limit_increase): New prototype.
+
+2011-07-13  Sriraman Tallam  <tmsriram@google.com>
+
+	* plugin-api.h
+	(ld_plugin_section): New struct.
+	(ld_plugin_get_section_count): New typedef.
+	(ld_plugin_get_section_type): New typedef.
+	(ld_plugin_get_section_name): New typedef.
+	(ld_plugin_get_section_contents): New typedef.
+	(ld_plugin_update_section_order): New typedef.
+	(ld_plugin_allow_section_ordering): New typedef.
+	(LDPT_GET_SECTION_COUNT): New enum value.
+	(LDPT_GET_SECTION_TYPE): New enum value.
+	(LDPT_GET_SECTION_NAME): New enum value.
+	(LDPT_GET_SECTION_CONTENTS): New enum value.
+	(LDPT_UPDATE_SECTION_ORDER): New enum value.
+	(LDPT_ALLOW_SECTION_ORDERING): New enum value.
+	(tv_get_section_count): New struct members.
+	(tv_get_section_type): New struct members.
+	(tv_get_section_name): New struct members.
+	(tv_get_section_contents): New struct members.
+	(tv_update_section_order): New struct members.
+	(tv_allow_section_ordering): New struct members.
+
+2011-07-15  Alan Modra  <amodra@gmail.com>
+
+	* bfdlink.h (struct bfd_link_info): Use ENUM_BITFIELD for strip,
+	discard, common_skip_ar_symbols, unresolved_syms_in_objects, and
+	unresolved_syms_in_shared_libs fields.  Move emit_note_gnu_build_id
+	out of bitfields.  Reorder bitfields.
+
+2011-07-13  Sriraman Tallam  <tmsriram@google.com>
+
+	* plugin-api.h (ld_plugin_section): New struct.
+	(ld_plugin_get_section_count): New typedef.
+	(ld_plugin_get_section_type): New typedef.
+	(ld_plugin_get_section_name): New typedef.
+	(ld_plugin_get_section_contents): New typedef.
+	(ld_plugin_update_section_order): New typedef.
+	(ld_plugin_allow_section_ordering): New typedef.
+	(LDPT_GET_SECTION_COUNT): New enum value.
+	(LDPT_GET_SECTION_TYPE): New enum value.
+	(LDPT_GET_SECTION_NAME): New enum value.
+	(LDPT_GET_SECTION_CONTENTS): New enum value.
+	(LDPT_UPDATE_SECTION_ORDER): New enum value.
+	(LDPT_ALLOW_SECTION_ORDERING): New enum value.
+	(tv_get_section_count): New struct members.
+	(tv_get_section_type): New struct members.
+	(tv_get_section_name): New struct members.
+	(tv_get_section_contents): New struct members.
+	(tv_update_section_order): New struct members.
+	(tv_allow_section_ordering): New struct members.
+
+2011-07-11  Catherine Moore  <clm@codesourcery.com>
+
+	* bfdlink.h (flag_type): New enumeration.
+	(flag_info_list): New structure.
+	(flag_info): New structure.
+
+2011-07-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/12942
+	* bfdlink.h (bfd_link_info): Add loading_lto_outputs.
+
+2011-07-01  Joel Brobecker  <brobecker@adacore.com>
+
+	* filenames.h (HAVE_CASE_INSENSITIVE_FILE_SYSTEM): Define
+	on Darwin, as well as on the systems that use a DOS-like
+	filesystem.
+
+2011-06-22  Jakub Jelinek  <jakub@redhat.com>
+
+	PR debug/47858
+	* dwarf2.h (enum dwarf_location_atom): Add DW_OP_GNU_parameter_ref.
+
+2011-06-22  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2.h (enum dwarf_location_atom): Add DW_OP_GNU_parameter_ref.
+
+2011-06-20  Jakub Jelinek  <jakub@redhat.com>
+
+	PR ld/12570
+	* bfdlink.h (struct bfd_link_info): Add no_ld_generated_unwind_info
+	option.
+
+2011-06-13  Jan Kratochvil  <jan.kratochvil@redhat.com>
+
+	* demangle.h (DMGL_RET_POSTFIX): Extend the comment.
+	(DMGL_RET_DROP): New.
+
+2011-06-13  Walter Lee  <walt@tilera.com>
+
+	* dis-asm.h (print_insn_tilegx): Declare.
+	(print_insn_tilepro): Likewise.
+
+2011-05-17  Alan Modra  <amodra@gmail.com>
+
+	PR ld/12760
+	* bfdlink.h (struct bfd_link_callbacks <notice>): Add "flags" and
+	"string" param.
+
+2011-05-16  Alan Modra  <amodra@gmail.com>
+
+	* bfdlink.h (struct bfd_link_hash_entry): Remove u.undef.weak field.
+
+2011-04-30  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2.h (DW_OP_GNU_const_type, DW_OP_GNU_regval_type,
+	DW_OP_GNU_deref_type, DW_OP_GNU_convert, DW_OP_GNU_reinterpret): New.
+
+2011-04-25  Jan Kratochvil  <jan.kratochvil@redhat.com>
+
+	* bfdlink.h (ENUM_BITFIELD): Remove.
+
+2011-04-25  Jan Kratochvil  <jan.kratochvil@redhat.com>
+
+	* ansidecl.h (ENUM_BITFIELD): New, from gcc/system.h.
+
+2011-04-24  Alan Modra  <amodra@gmail.com>
+
+	PR ld/12365
+	PR ld/12696
+	* bfdlink.h (ENUM_BITFIELD): Define.
+	(struct bfd_link_hash_entry): Make "type" a bitfield.  Add "non_ir_ref".
+	(struct bfd_link_callbacks <notice>): Pass bfd_link_hash_entry pointer
+	rather than "name".
+
+2011-04-20  Alan Modra  <amodra@gmail.com>
+
+	PR ld/12365
+	* bfdlink.h (struct bfd_link_callbacks): Modify multiple_definition
+	and multiple_common parameters to pass in a bfd_link_hash_entry
+	pointer rather than name,bfd etc. found in the hash entry.
+
+2011-03-31  Tristan Gingold  <gingold@adacore.com>
+
+	* dwarf2.h (dwarf_line_number_hp_sfc_ops): New enum.
+
+2011-03-24  Mark Wielaard  <mjw@redhat.com>
+
+	* dwarf2.h (dwarf_form): Remove deprecated DW_FORM_sig8 define.
+
+2010-03-23  Rafael �vila de Espíndola <respindola@mozilla.com>
+
+	* plugin-api.h (ld_plugin_get_view): New.
+	(ld_plugin_tag): Add LDPT_GET_VIEW.
+	(ld_plugin_tv): Add tv_get_view.
+
+2011-03-16  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2.h (DW_TAG_GNU_call_site, DW_TAG_GNU_call_site_parameter,
+	DW_AT_GNU_call_site_value, DW_AT_GNU_call_site_data_value,
+	DW_AT_GNU_call_site_target, DW_AT_GNU_call_site_target_clobbered,
+	DW_AT_GNU_tail_call, DW_AT_GNU_all_tail_call_sites,
+	DW_AT_GNU_all_call_sites,, DW_AT_GNU_all_source_call_sites,
+	DW_OP_GNU_entry_value): New.
+
+2011-02-28  Kai Tietz  <kai.tietz@onevision.com>
+
+	* filenames.h (filename_ncmp): New prototype.
+
+2011-02-23  Kai Tietz  <kai.tietz@onevision.com>
+
+	* dwarf2.h (_ELF_DWARF2_H): Renamed to
+	_DWARF2_H.
+	(DWARF2_External_LineInfo, DWARF2_Internal_LineInfo,
+	DWARF2_External_PubNames, DWARF2_Internal_PubNames,
+	DWARF2_External_CompUnit, DWARF2_Internal_CompUnit,
+	DWARF2_External_ARange, DWARF2_Internal_ARange): Removed.
+
+2011-02-08  Ulrich Weigand  <uweigand@de.ibm.com>
+
+	* dwarf2.h (enum dwarf_calling_convention): Add DW_CC_GDB_IBM_OpenCL.
+
+2011-01-12  Iain Sandoe  <iains@gcc.gnu.org>
+
+	* dwarf2.h: Update value for DW_AT_hi_user.
+
+2010-11-16  Ian Lance Taylor  <iant@google.com>
+
+	* simple-object.h (simple_object_attributes_merge): Declare,
+	replacing simple_object_attributes_compare.
+
+2010-11-04  Ian Lance Taylor  <iant@google.com>
+
+	* dwarf2.h (enum dwarf_source_language): Add DW_LANG_Go.
+
+2010-11-02  Ian Lance Taylor  <iant@google.com>
+
+	* simple-object.h: New file.
+
+2010-10-15  Dave Korn  <dave.korn.cygwin@gmail.com>
+
+	Sync LD plugin patch series (part 1/6) with src/include/.
+	* plugin-api.h (LDPT_GNU_LD_VERSION): New ld_plugin_tag enum member.
+
+2010-10-14  Dave Korn  <dave.korn.cygwin@gmail.com>
+
+	Apply LD plugin patch series (part 6/6).
+	* bfdlink.h (struct_bfd_link_callbacks): Document new argument
+	to add_archive_element callback used to return a replacement bfd which
+	is to be added to the hash table in place of the original element.
+
+2010-10-14  Dave Korn  <dave.korn.cygwin@gmail.com>
+
+	Apply LD plugin patch series (part 1/6).
+	* plugin-api.h (LDPT_GNU_LD_VERSION): New ld_plugin_tag enum member.
+
+2010-10-06  Andi Kleen <ak@linux.intel.com>
+
+	* libiberty.h (setproctitle): Add prototype.
+
+2010-09-29  Bernd Schmidt  <bernds@codesourcery.com>
+
+	* opcode/tic6x-control-registers.h (tscl): Now read_write.
+
+2010-09-27  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* opcode/s390.h: Add S390_OPCODE_Z196 to enum s390_opcode_cpu_val.
+
+2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+	* arm.h (ARM_EXT_V6Z): Remove.
+	(ARM_EXT_SEC): New define.
+	(ARM_AEXT_V6Z): Use Security Extensions.
+	(ARM_AEXT_V6ZK): Likeiwse.
+	(ARM_AEXT_V6ZT2): Likewise.
+	(ARM_AEXT_V6ZKT2): Likewise.
+	(ARM_AEXT_V7_ARM): Base v7 does not have Security Extensions.
+	(ARM_ARCH_V7A_SEC): New define.
+	(ARM_ARCH_V7A_MP): Rename...
+	(ARM_ARCH_V7A_MP_SEC): ...to this and add Security Extensions.
+
+2010-09-09  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2.h (DW_OP_GNU_implicit_pointer): New.
+
+2010-07-06  Ken Werner  <ken.werner@de.ibm.com>
+
+	* floatformat.h (floatformat_ieee_half_big): Add declaration.
+	(floatformat_ieee_half_little): Likewise.
+
+2010-06-29  Alan Modra  <amodra@gmail.com>
+
+	* dis-asm.h: Remove references to maxq.
+
+2010-06-21  Rafael Espindola  <espindola@google.com>
+
+	* plugin-api.h (ld_plugin_set_extra_library_path): New.
+	(ld_plugin_tag): Add LDPT_SET_EXTRA_LIBRARY_PATH.
+	(ld_plugin_tv): Add tv_set_extra_library_path.
+
+2010-06-21  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2.h (enum dwarf_type): Add DW_ATE_UTF.
+
+2010-06-18  Rafael Espindola  <espindola@google.com>
+
+	* plugin.h (ld_plugin_add_input_file, ld_plugin_add_input_library):
+	Make argument const.
+
+2010-06-08  Laurynas Biveinis  <laurynas.biveinis@gmail.com>
+
+	* splay-tree.h: Update copyright years.
+	(splay_tree_s): Document fields.
+	(splay_tree_new_typed_alloc): New.
+
+	* hashtab.h: Update copyright years.
+	(htab_create_typed_alloc): New.
+
+2010-06-10  Tristan Gingold  <gingold@adacore.com>
+
+	* dwarf2.h (enum dwarf_tag): Add DW_TAG_HP_Bliss_field and
+	DW_TAG_HP_Bliss_field_set.
+	(enum dwarf_attribute): Add DW_AT_HP_prologue, DW_AT_HP_epilogue,
+	DW_AT_HP_unit_name, DW_AT_HP_unit_size, DW_AT_HP_widened_byte_size,
+	DW_AT_HP_definition_points, DW_AT_HP_default_location and
+	DW_AT_HP_is_result_param.
+	(enum dwarf_type): Add DW_ATE_HP_VAX_float, DW_ATE_HP_VAX_float_d,
+	DW_ATE_HP_packed_decimal, DW_ATE_HP_zoned_decimal, DW_ATE_HP_edited,
+	DW_ATE_HP_signed_fixed, DW_ATE_HP_unsigned_fixed,
+	DW_ATE_HP_VAX_complex_float and DW_ATE_HP_VAX_complex_float_d.
+	(enum dwarf_line_number_x_ops): Add
+	DW_LNE_HP_source_file_correlation.
+	(enum dwarf_source_language): Add DW_LANG_HP_Bliss,
+	DW_LANG_HP_Basic91, DW_LANG_HP_Pascal91, DW_LANG_HP_IMacro,
+	DW_LANG_HP_Assembler.
+
+2010-06-01  Rafael Espindola  <espindola@google.com>
+
+	* plugin-api.h (ld_plugin_tag): Add LDPT_OUTPUT_NAME.
+
+2010-04-26  Pedro Alves  <pedro@codesourcery.com>
+
+	* filenames.h (PATH_SEPARATOR): Delete.
+
+2010-04-23  Pedro Alves  <pedro@codesourcery.com>
+
+	* filenames.h (IS_DIR_SEPARATOR_1): Rename from IS_DIR_SEPARATOR,
+	always define it independently of host, add `dos_based' parameter,
+	and handle it.
+	(PATH_SEPARATOR): Define.
+	(HAS_DRIVE_SPEC_1): Rename from HAS_DRIVE_SPEC, always define it
+	independently of host, add `dos_based' parameter, and handle it.
+	(IS_ABSOLUTE_PATH_1): Rename from IS_ABSOLUTE_PATH, always define
+	it independently of host, add `dos_based' parameter, and handle
+	it.
+	(IS_DOS_DIR_SEPARATOR, IS_DOS_ABSOLUTE_PATH)
+	(IS_UNIX_DIR_SEPARATOR, IS_UNIX_ABSOLUTE_PATH)
+	(HAS_DOS_DRIVE_SPEC): New.
+	(HAS_DRIVE_SPEC): Reimplement on top of HAS_DRIVE_SPEC_1.
+	(IS_DIR_SEPARATOR): Reimplement on top of IS_DIR_SEPARATOR_1.
+	(IS_ABSOLUTE_PATH): Reimplement on top of IS_ABSOLUTE_PATH_1.
+	* libiberty.h (dos_lbasename, unix_lbasename): Declare.
+
+2009-05-31  Ian Lance Taylor  <iant@google.com>
+
+	* ansidecl.h: Add extern "C" when compiling with C++.  Treat C++
+	the way we treat an ISO C compiler.  Don't define inline as a
+	macro when compiling with C++.
+	* dyn-string.h: Add header guard DYN_STRING_H.  Add extern "C"
+	when compiling with C++.
+	* fibheap.h: Add extern "C" when compiling with C++.
+
+2010-04-23  Pedro Alves  <pedro@codesourcery.com>
+
+	* filenames.h (IS_DIR_SEPARATOR_1): Rename from IS_DIR_SEPARATOR,
+	always define it independently of host, add `dos_based' parameter,
+	and handle it.
+	(HAS_DRIVE_SPEC_1): Rename from HAS_DRIVE_SPEC, always define it
+	independently of host, add `dos_based' parameter, and handle it.
+	(IS_ABSOLUTE_PATH_1): Rename from IS_ABSOLUTE_PATH, always define
+	it independently of host, add `dos_based' parameter, and handle
+	it.
+	(IS_DOS_DIR_SEPARATOR, IS_DOS_ABSOLUTE_PATH)
+	(IS_UNIX_DIR_SEPARATOR, IS_UNIX_ABSOLUTE_PATH)
+	(HAS_DOS_DRIVE_SPEC): New.
+	(HAS_DRIVE_SPEC): Reimplement on top of HAS_DRIVE_SPEC_1.
+	(IS_DIR_SEPARATOR): Reimplement on top of IS_DIR_SEPARATOR_1.
+	(IS_ABSOLUTE_PATH): Reimplement on top of IS_ABSOLUTE_PATH_1.
+	* libiberty.h (dos_lbasename, unix_lbasename): Declare.
+
+2010-04-20  Nick Clifton  <nickc@redhat.com>
+
+	* sha1.h: Update copyright notice to use GPLv3.
+
+2010-04-15  Nick Clifton  <nickc@redhat.com>
+
+	* bout.h: Update copyright notice to use GPLv3.
+	* hp-symtab.h: Likewise.
+	* oasys.h: Likewise.
+	* progress.h: Likewise.
+	* sha1.h: Likewise.
+	* xtensa-isa-internal.h: Likewise.
+	* xtensa-isa.h: Likewise.
+
+2010-04-14  Doug Evans  <dje@google.com>
+
+	* filenames.h (HAS_DRIVE_SPEC, STRIP_DRIVE_SPEC): New macros.
+
+2010-04-05  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2.h (DWARF2_Internal_LineInfo): Add li_max_ops_per_insn
+	field.
+
+2010-03-25  Joseph Myers  <joseph@codesourcery.com>
+
+	* dis-asm.h (print_insn_tic6x): Declare.
+
+2010-03-23  Joseph Myers  <joseph@codesourcery.com>
+
+	* symcat.h (CONCAT5, CONCAT6, XCONCAT5, XCONCAT6): Define.
+
+2010-01-13  Joel Brobecker  <brobecker@adacore.com>
+
+	Add new DW_AT_use_GNAT_descriptive_type CU attribute.
+	* dwarf2.h (dwarf_attribute): Add DW_AT_use_GNAT_descriptive_type.
+
+2010-01-11  Tristan Gingold  <gingold@adacore.com>
+
+	* demangle.h (ada_demangle): Add prototype.
+
+2010-01-05  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+	PR bootstrap/41771
+	* ansidecl.h: Fix inline test for C99 and Sun Studio cc.
+
+2009-12-29  Joel Brobecker  <brobecker@adacore.com>
+
+	* dwarf2.h (enum dwarf_attribute): Add DW_AT_GNAT_descriptive_type.
+
+2009-12-14  Doug Kwan  <dougkwan@google.com>
+
+	* bfdlink.h (struct bfd_link_callbacks): Rename function parameters
+	to avoid shadowed variable warnings.
+	* dis-asm.h (struct disassemble_info): Ditto.
+	(disassemble_init_for_target): Ditto.
+	(init_disassemble_info): Ditto.
+
+2009-11-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* alloca-conf.h: Clarify comment.
+
+2009-11-06  Jonas Maebe  <jonas.maebe@elis.ugent.be>
+
+	Add DWARF attribute value for the "Borland fastcall" calling
+	convention.
+	* dwarf2.h: Add DW_CC_GNU_borland_fastcall_i386 constant.
+
+2009-10-23  Kai Tietz  <kai.tietz@onevision.com>
+
+	* splay-tree.h (libi_uhostptr_t): Add gcc specific
+	__extension__ for long long type case to silent cX9.
+	(libi_shostptr_t): Likewise.
+
+2009-10-19  Rafael Avila de Espindola  <espindola@google.com>
+
+	PR40790
+	* plugin-api.h: Don't include stdint.h unconditionally.
+
+2009-10-15  Jakub Jelinek  <jakub@redhat.com>
+
+	* include/dwarf2.h (DW_LANG_Python): Add comment that it is
+	a DWARF 4 addition.
+
+2009-10-14  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (enum bfd_link_common_skip_ar_symbols): Rename from
+	bfd_link_common_skip_ar_aymbols.
+	(struct bfd_link_info): Here too.
+
+2009-10-09  Rafael Espindola  <espindola@google.com>
+
+	* plugin-api.h (ld_plugin_add_input_library): Change argument name to
+	libname.
+
+2008-10-03  Rafael Espindola  <espindola@google.com>
+
+	* plugin-api.h: New.
+	* lto-symtab.h: New.
+
+2009-10-05   Rafael Espindola  <espindola@google.com>
+
+	* plugin-api.h (ld_plugin_status): Add LDPS_BAD_HANDLE.
+	(ld_plugin_get_input_file): New.
+	(ld_plugin_release_input_file): New.
+	(ld_plugin_add_input_library): New.
+	(ld_plugin_message): Mark format const.
+	(ld_plugin_level): Add LDPT_GET_INPUT_FILE, LDPT_RELEASE_INPUT_FILE and
+	LDPT_ADD_INPUT_LIBRARY.
+	(ld_plugin_tv): Add tv_get_input_file, tv_release_input_file and
+	tv_add_input_library.
+
+2009-10-04  Jerry Quinn  <jlquinn@optonline.net>
+
+	* plugin-api.h: Fix compile.
+
+2009-09-29  Jason Merrill  <jason@redhat.com>
+
+	* demangle.h (enum demangle_component_type): Add
+	DEMANGLE_COMPONENT_LAMBDA, DEMANGLE_COMPONENT_DEFAULT_ARG,
+	DEMANGLE_COMPONENT_UNNAMED_TYPE.
+	(struct demangle_component): Add s_unary_num.
+
+2009-09-29  DJ Delorie  <dj@redhat.com>
+
+	* dis-asm.h: Add prototype for print_insn_rx.
+
+2009-09-25  Dodji Seketeli  <dodji@redhat.com>
+
+	* dwarf2.h (enum dwarf_tag): Rename DW_TAG_template_parameter_pack and
+	DW_TAG_formal_parameter_pack into DW_TAG_GNU_template_parameter_pack
+	and DW_TAG_formal_parameter_pack until DWARF 5 is out.
+
+2009-09-25  Cary Coutant  <ccoutant@google.com>
+
+	Add rest of new values from DWARF Version 4.
+	* dwarf2.h (DW_TAG_rvalue_reference_type, DW_TAG_template_alias):
+	New tags.
+	(DW_FORM_ref_sig8): New name for DW_FORM_sig8.
+	(DW_AT_main_subprogram, DW_AT_data_bit_offset, DW_AT_const_expr,
+	DW_AT_enum_class, DW_AT_linkage_name, DW_AT_GNU_guarded_by,
+	DW_AT_GNU_pt_guarded_by, DW_AT_GNU_guarded, DW_AT_GNU_pt_guarded,
+	DW_AT_GNU_locks_excluded, DW_AT_GNU_exclusive_locks_required,
+	DW_AT_GNU_shared_locks_required, DW_AT_GNU_odr_signature): New
+	attributes.
+	(DW_LANG_Python): New language.
+
+2009-09-24  Cary Coutant  <ccoutant@google.com>
+
+	* dwarf2.h (DW_TAG_rvalue_reference_type, DW_TAG_template_alias):
+	New tags.
+	(DW_FORM_ref_sig8): New name for DW_FORM_sig8.
+	(DW_AT_main_subprogram, DW_AT_data_bit_offset, DW_AT_const_expr,
+	DW_AT_enum_class, DW_AT_linkage_name, DW_AT_GNU_guarded_by,
+	DW_AT_GNU_pt_guarded_by, DW_AT_GNU_guarded, DW_AT_GNU_pt_guarded,
+	DW_AT_GNU_locks_excluded, DW_AT_GNU_exclusive_locks_required,
+	DW_AT_GNU_shared_locks_required, DW_AT_GNU_odr_signature): New
+	attributes.
+	(DW_LANG_Python): New language.
+
+2009-09-22  Dodji Seketeli  <dodji@redhat.com>
+
+	* dwarf2.h (enum dwarf_tag): Add
+	DW_TAG_template_parameter_pack and DW_TAG_formal_parameter_pack.
+
+2009-09-09  Martin Thuresson  <martin@mtme.org>
+
+	* bfdlink.h (struct bfd_link_hash_common_entry): Move to top
+	level.
+
+2009-09-04  Jie Zhang  <jie.zhang@analog.com>
+
+	* opcode/bfin.h (PseudoDbg_Assert): Add bits_grp and mask_grp.
+	(PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask): Define.
+	(PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask,
+	PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask):
+	Adjust accordingly.
+	(init_PseudoDbg_Assert): Add PseudoDbg_Assert_grp_bits and
+	PseudoDbg_Assert_grp_mask.
+
+2009-08-06  Michael Eager <eager@eagercon.com>
+
+	* dis-asm.h: Decl print_insn_microblaze().
+
+2009-07-24  Ian Lance Taylor  <iant@google.com>
+
+	* libiberty.h (crc32): Declare.
+
+2009-07-20  Cary Coutant  <ccoutant@google.com>
+	    Doug Evans  <dje@google.com>
+
+	Add some dwarf4 values.
+	* dwarf2.h (enum dwarf_tag): Add DW_TAG_type_unit.
+	(enum dwarf_form): Add DW_FORM_sec_offset, DW_FORM_exprloc,
+	DW_FORM_flag_present, DW_FORM_sig8.
+	(enum dwarf_attribute): Add DW_AT_signature.
+
+2009-07-17  Jan Kratochvil  <jan.kratochvil@redhat.com>
+
+	* demangle.h
+	(enum demangle_component_type <DEMANGLE_COMPONENT_GLOBAL_CONSTRUCTORS>)
+	(enum demangle_component_type <DEMANGLE_COMPONENT_GLOBAL_DESTRUCTORS>):
+	New.
+
+2009-07-10  Tom Tromey  <tromey@redhat.com>
+
+	* dwarf2.h: New file, moved from elf/.
+
+2009-07-09  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2.h (enum dwarf_location_atom): Add DW_OP_implicit_value
+	and DW_OP_stack_value.
+
+2009-07-09  Tom Tromey  <tromey@redhat.com>
+
+	* elf/dwarf2.h: Remove, renaming to...
+	* dwarf2.h: ... this.
+
+2009-06-29  Tom Tromey  <tromey@redhat.com>
+
+	* elf/dwarf2.h: New file.  Merged with gdb.
+
+2009-06-18  Nick Clifton  <nickc@redhat.com>
+
+	* dis-asm.h (USER_SPECIFIED_MACHINE_TYPE): New value for the flags
+	field of struct disassemble_info.
+
+2009-06-09  Ian Lance Taylor  <ian@airs.com>
+
+	* ansidecl.h (ATTRIBUTE_UNUSED_LABEL): Define for C++.
+
+2009-06-15  Nick Clifton  <nickc@redhat.com>
+
+	* dis-asm.h (DISASSEMBLE_DATA): New value for the flags field of
+	struct disassemble_info.
+
+2009-06-02  Ian Lance Taylor  <iant@google.com>
+
+	* ansidecl.h (EXPORTED_CONST): Define.
+
+2009-05-31  Ian Lance Taylor  <iant@google.com>
+
+	* ansidecl.h: Add extern "C" when compiling with C++.  Treat C++
+	the way we treat an ISO C compiler.  Don't define inline as a
+	macdro when compiling with C++.
+	* dyn-string.h: Add header guard DYN_STRING_H.  Add extern "C"
+	when compiling with C++.
+	* fibheap.h: Add extern "C" when compiling with C++.
+
+2009-05-25  Tristan Gingold  <gingold@adacore.com>
+
+	* fopen-vms.h (FOPEN_RB, FOPEN_WB, FOPEN_AB, FOPEN_RUB, FOPEN_WUB,
+	FOPEN_AUB): Use "rfm=udf,rat=none" attribute.
+
+2009-04-22  Taras Glek <tglek@mozilla.com>
+
+	* hashtab.h: Update GTY annotations to new syntax.
+	* splay-tree.h: Likewise.
+
+2009-04-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* bfdlink.h (bfd_link_info): Add warn_alternate_em.
+
+2009-03-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* alloca-conf.h: Revise based on autoconf-2.61, autoconf-2.13
+	documentation.
+
+2009-03-17  Jason Merrill  <jason@redhat.com>
+
+	* demangle.h (enum demangle_component_type): Add
+	DEMANGLE_COMPONENT_FUNCTION_PARAM.
+
+2008-12-01  Cary Coutant  <ccoutant@google.com>
+
+	* plugin-api.h (LDPS_BAD_HANDLE): New constant.
+	(ld_plugin_get_input_file): New typedef.
+	(ld_plugin_release_input_file): New typedef.
+	(LDPT_GET_INPUT_FILE, LDPT_RELEASE_INPUT_FILE): New constants.
+	(struct ld_plugin_tv): Add two new fields.
+
+2008-12-23  Jon Beniston <jon@beniston.com>
+
+	* dis-asm.h: Add LM32 disassembler function prototype.
+
+2008-12-10  Jason Merrill  <jason@redhat.com>
+
+	* demangle.h (enum demangle_component_type): Add
+	DEMANGLE_COMPONENT_FIXED_TYPE.
+
+2008-12-01  Cary Coutant  <ccoutant@google.com>
+
+	* plugin-api.h (ld_plugin_message): Change format parameter to const.
+
+2008-12-01  Cary Coutant  <ccoutant@google.com>
+
+	* plugin-api.h: Fix syntax error when compiling with C++.
+
+2008-11-26  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 7047
+	* bfdlink.h (struct bfd_elf_version_expr): Delete "symbol".
+	Add "literal".
+
+2008-11-21  Sterling Augustine  <sterling@tensilica.com>
+
+	* xtensa-isa-internal.h (XTENSA_STATE_IS_SHARED_OR): New flag.
+	* xtensa-isa.h (xtensa_state_is_shared_or): New prototype.
+
+2008-11-19  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa-config.h (XCHAL_HAVE_MUL16, XCHAL_HAVE_MUL32, XCHAL_HAVE_DIV32)
+	(XCHAL_HAVE_MINMAX, XCHAL_HAVE_SEXT, XCHAL_HAVE_THREADPTR)
+	(XCHAL_HAVE_RELEASE_SYNC, XCHAL_HAVE_S32C1I): Change to 1.
+	(XCHAL_NUM_AREGS): Change to 32.
+	(XCHAL_ICACHE_SIZE, XCHAL_DCACHE_SIZE): Change to 16K.
+	(XCHAL_ICACHE_LINESIZE, XCHAL_DCACHE_LINESIZE): Change to 32.
+	(XCHAL_ICACHE_LINEWIDTH, XCHAL_DCACHE_LINEWIDTH): Change to 5.
+	(XCHAL_DCACHE_IS_WRITEBACK): Change to 1.
+	(XCHAL_DEBUGLEVEL): Change to 6.
+
+2008-11-14  Tristan Gingold  <gingold@adacore.com>
+
+	* fopen-vms.h (FOPEN_RB): Use a single string to match the
+	standard prototype.
+	(FOPEN_WB): Ditto.
+	(FOPEN_AB): Ditto.
+	(FOPEN_RUB): Ditto.
+	(FOPEN_WUB): Ditto.
+	(FOPEN_AUB): Ditto.
+
+2008-10-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* obstack.h (obstack_finish <!__GNUC__>): Cast result to void *.
+
+2008-10-06  Jason Merrill  <jason@redhat.com>
+
+	* demangle.h (enum demangle_component_type): Add
+	DEMANGLE_COMPONENT_PACK_EXPANSION.
+
+2008-09-24  Richard Henderson  <rth@redhat.com>
+
+	* elf/dwarf2.h (DW_OP_GNU_encoded_addr): New.
+
+2008-09-22 Rafael Espindola  <espindola@google.com>
+
+	* plugin-api.h (ld_plugin_status): Remove comma from the last item.
+	Use C style comment.
+	(ld_plugin_api_version, ld_plugin_output_file_type,
+	ld_plugin_symbol_kind, ld_plugin_symbol_visibility,
+	ld_plugin_symbol_resolution, ld_plugin_level, ld_plugin_tag): Remove
+	comma from the last item.
+
+2008-09-18  Cary Coutant  <ccoutant@google.com>
+
+	Add plugin functionality for link-time optimization (LTO).
+	* plugin-api.h: New file.
+
+2008-09-09  Jason Merrill  <jason@redhat.com>
+
+	* demangle.h (enum demangle_component_type): Add
+	DEMANGLE_COMPONENT_DECLTYPE.
+
+2008-08-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* binary-io.h: New file, imported from gnulib, but don't
+	#include <fcntl.h> or <stdio.h>.
+
+2008-08-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (bfd_generic_link_read_symbols): Declare.
+
+2008-08-08  Anatoly Sokolov  <aesok@post.ru>
+
+	* elf/avr.h (E_AVR_MACH_AVR25, E_AVR_MACH_AVR31,
+	E_AVR_MACH_AVR35, E_AVR_MACH_AVR51): Define.
+	(EF_AVR_MACH): Redefine to 0x7F.
+	* opcode/avr.h (AVR_ISA_TINY3, AVR_ISA_ALL, AVR_ISA_USB162): Remove.
+	(AVR_ISA_AVR3): Redefine.
+	(AVR_ISA_AVR1, AVR_ISA_AVR2, AVR_ISA_AVR31, AVR_ISA_AVR35,
+	AVR_ISA_AVR3_ALL, AVR_ISA_AVR4, AVR_ISA_AVR5, AVR_ISA_AVR51,
+	AVR_ISA_AVR6): Define.
+
+2008-07-12  Jie Zhang  <jie.zhang@analog.com>
+
+	Revert
+	2008-07-12  Jie Zhang  <jie.zhang@analog.com>
+	* bfdlink.h (struct bfd_link_info): Add sep_code member
+	variable.
+	* elf/bfin.h (EF_BFIN_CODE_IN_L1): Define.
+	(EF_BFIN_DATA_IN_L1): Define.
+
+2008-07-12  Jie Zhang  <jie.zhang@analog.com>
+
+	* bfdlink.h (struct bfd_link_info): Add sep_code member
+	variable.
+	* elf/bfin.h (EF_BFIN_CODE_IN_L1): Define.
+	(EF_BFIN_DATA_IN_L1): Define.
+
+2008-07-07  Stan Shebs  <stan@codesourcery.com>
+
+	* dis-asm.h (struct disassemble_info): Add endian_code field.
+
+2008-07-07  Joel Brobecker  <brobecker@adacore.com>
+
+	* safe-ctype.h: Add #include of ctype.h before redefining
+	the ctype.h macros.
+
+2008-07-04  Joel Brobecker  <brobecker@adacore.com>
+
+	* safe-ctype.h: Remove #error when detecting that ctype.h has been
+	included. Redefine the various macros provided by ctype.h as
+	undefined variables.
+
+2008-06-23  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (XALLOCA, XDUP, XALLOCAVEC, XDUPVEC, XALLOCAVAR,
+	XDUPVAR, XOBNEWVEC, XOBNEWVAR): New.
+
+2008-06-06  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_info): Add "path_separator".
+
+2008-04-10  Andreas Krebbel  <krebbel1@de.ibm.com>
+
+	* dis-asm.h (print_s390_disassembler_options):
+	Prototype added.
+
+2008-03-24  Ian Lance Taylor  <iant@google.com>
+
+	* sha1.h: New file, from gnulib.
+
+	* md5.h: Add extern "C" when compiled with C++.
+
+2008-03-24  Ian Lance Taylor  <iant@google.com>
+
+	* md5.h: Add extern "C" when compiled with C++.
+
+2008-03-21  Ian Lance Taylor  <iant@google.com>
+
+	* filenames.h: Add extern "C" when compiled with C++.
+
+2008-02-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_hash_table): Delete creator field.
+	(struct bfd_link_info): Add output_bfd.
+
+2008-02-11  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa-config.h (XCHAL_HAVE_THREADPTR): Redefine to zero.
+	(XCHAL_NUM_AREGS, XCHAL_MAX_INSTRUCTION_SIZE): New.
+
+2008-01-26  David Daney  <ddaney@avtrex.com>
+
+	* demangle.h (demangle_component_type):  Add
+	DEMANGLE_COMPONENT_JAVA_RESOURCE,
+	DEMANGLE_COMPONENT_COMPOUND_NAME, and
+	DEMANGLE_COMPONENT_CHARACTER as new enum values.
+	(demangle_component): Add struct s_character to union u.
+
+2007-11-07  Joseph Myers  <joseph@codesourcery.com>
+	    Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* floatformat.h (struct floatformat): Add split_half field.
+	(floatformat_ibm_long_double): New.
+
+2007-09-06  Tom Tromey  <tromey@redhat.com>
+
+	* libiberty.h (pex_free): Document process killing.
+
+2007-08-31  Douglas Gregor  <doug.gregor@gmail.com>
+
+	* demangle.h (enum demangle_component_type): Add
+	DEMANGLE_COMPONENT_RVALUE_REFERENCE.
+
+2007-07-25  Ben Elliston  <bje@au.ibm.com>
+
+	* ternary.h: Remove.
+
+2007-07-18  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa-config.h (XCHAL_HAVE_THREADPTR): New.
+	(XCHAL_HAVE_RELEASE_SYNC, XCHAL_HAVE_S32C1I): New.
+
+2007-07-17  Nick Clifton  <nickc@redhat.com>
+
+	* COPYING3: New file.  Contains version 3 of the GNU General
+	Public License.
+
+2007-07-12  Kai Tietz   <kai.tietz@onevision.com>
+
+	* splay-tree.h (libi_uhostptr_t, libi_shostptr_t): Adjust types
+	work-a-round whitespace problem in gcc gengtype.
+
+	* splay-tree.h (libi_uhostptr_t, libi_shostptr_t): New types,
+	needed for WIN64 when a long is not wide enough for a pointer.
+	(splay_tree_key, splay_tree_value): Use the new types.
+
+2007-07-09  Roland McGrath  <roland@redhat.com>
+
+	* bfdlink.h (struct bfd_link_info): Add member emit_note_gnu_build_id.
+
+2007-07-06  Nick Clifton  <nickc@redhat.com>
+
+	* bfdlink.h: Update copyright notice to refer to GPLv3.
+
+2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
+
+	* dis-asm.h (print_insn_cr16): New prototype.
+
+2007-06-01  Noah Misch  <noah@cs.caltech.edu>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_info): Add input_bfds_tail.
+
+2007-05-07  Nathan Froyd  <froydnj@codesourcery.com>
+
+	* libiberty.h (writeargv): Declare.
+
+2007-04-30  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_info): Add "info" and "minfo".
+
+2007-04-25  Mark Mitchell  <mark@codesourcery.com>
+
+	* demangle.h: Change license to LGPL + exception.
+
+2007-04-10  Richard Henderson  <rth@redhat.com>
+
+	* bfdlink.h (struct bfd_link_info): Add relax_trip.
+
+2007-03-29  Joel Brobecker  <brobecker@adacore.com>
+
+	* filenames.h (FILENAME_CMP): Adjust define to call filename_cmp
+	regardless of the type of file system.
+
+2007-03-06  Jan Hubicka  <jh@suse.cz>
+
+	* ansidecl.h (ATTRIBUTE_COLD, ATTRIBUTE_HOT): New.
+
+2007-02-21  Nick Clifton  <nickc@redhat.com>
+
+	* bfdlink.h (struct bfd_link_callbacks): Add
+	override_segment_assignment field.
+
+2007-02-17  Mark Mitchell  <mark@codesourcery.com>
+            Nathan Sidwell  <nathan@codesourcery.com>
+            Vladimir Prus  <vladimir@codesourcery.com
+            Joseph Myers  <joseph@codesourcery.com>
+
+	* bin-bugs.h: Remove.
+
+2007-02-09  Joseph S. Myers  <joseph@codesourcery.com>
+
+	* libiberty.h (pex_write_input): Remove prototype.
+
+2007-02-05  Dave Brolley  <brolley@redhat.com>
+
+	* Contribute the following changes:
+	2001-03-26  Ben Elliston  <bje@redhat.com>
+
+	* dis-asm.h (print_insn_mep): Declare.
+
+2007-02-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* dis-asm.h (print_i386_disassembler_options): New.
+
+2007-01-31  Vladimir Prus  <vladimir@codesourcery.com>
+
+	* libiberty.h (PEX_STDERR_TO_PIPE): New define.
+	(PEX_BINARY_ERROR): New define.
+	(pex_read_err): New function.
+
+2007-01-29  Simon Baldwin <simonb@google.com>
+
+	* demangle.h: New cplus_demangle_print_callback,
+	cplus_demangle_v3_callback, and java_demangle_v3_callback function
+	prototypes, and demangle_callbackref type definition.
+
+2007-01-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/3831
+	* bfdlink.h (bfd_link_info): Rename dynamic to dynamic_list.
+	Add dynamic and dynamic_data.
+
+2006-12-05  Michael Tautschnig  <tautschn@model.in.tum.de>
+	    Nick Clifton  <nickc@redhat.com>
+
+	* ansidecl.h (ATTRIBUTE_PACKED): Define.
+
+2006-11-30  Andrew Stubbs  <andrew.stubbs@st.com>
+	    J"orn Rennecke <joern.rennecke@st.com>
+
+	PR driver/29931
+	* libiberty.h (make_relative_prefix_ignore_links): Declare.
+
+2006-11-27  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa-config.h (XSHAL_ABI): New.
+	(XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New.
+
+2006-11-27  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa-isa.h (STATIC_LIBISA): Delete.
+
+2006-10-30  Paul Brook  <paul@codesourcery.com>
+
+	* dis-asm.h (disassemble_info): Add symtab, symtab_pos and
+	symtab_size.
+
+2006-10-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/3111
+	* bfdlink.h (bfd_link_info): Add reduce_memory_overheads.
+
+2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
+	    Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
+	    Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
+	    Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* dis-asm.h (print_insn_spu): Declare.
+
+2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* dis-asm.h: Add prototypes for Score disassembler routines.
+
+2006-09-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* bfdlink.h (bfd_elf_dynamic_list): New.
+	(bfd_link_info): Add a dynamic field.
+
+2006-08-04  Marcelo Tosatti  <marcelo@kvack.org>
+
+	* bfdlink.h (struct bfd_link_info): New field: print_gc_sections.
+
+2006-07-10  Jakub Jelinek  <jakub@redhat.com>
+
+	* bfdlink.h (struct bfd_link_info): Add emit_hash and
+	emit_gnu_hash bitfields.
+
+2006-04-11  Jim Blandy  <jimb@codesourcery.com>
+
+	* libiberty.h (pex_input_file, pex_input_pipe): New declarations.
+
+2006-04-06  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* bfdlink.h (bfd_link_info): Replace need_relax_finalize with
+	relax_pass.
+
+2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
+            Anil Paranjape   <anilp1@kpitcummins.com>
+            Shilin Shakti    <shilins@kpitcummins.com>
+
+	* dis-asm.h (print_insn_xc16c): New prototype.
+
+2006-01-18  DJ Delorie  <dj@redhat.com>
+
+	* md5.h: Include ansidecl.h
+
+2006-01-17  Andreas Schwab  <schwab@suse.de>
+
+	PR binutils/1486
+	* dis-asm.h (struct disassemble_info): Add
+	disassembler_needs_relocs.
+
+2006-01-09  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa-config.h (XCHAL_HAVE_MUL32_HIGH): Define.
+
+2005-12-30  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa-config.h (XCHAL_HAVE_WIDE_BRANCHES): New.
+
+2005-12-16  Nathan Sidwell  <nathan@codesourcery.com>
+
+	Second part of ms1 to mt renaming.
+	* dis-asm.h (print_insn_mt): Renamed.
+
+2005-12-10  Terry Laurenzo  <tlaurenzo@gmail.com>
+
+	PR java/9861
+	* demangle.h : Add DMGL_RET_POSTFIX define to enable alternative
+	output format for return types
+
+2005-11-03  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_order): Tweak comment.
+
+2005-10-31  Mark Kettenis  <kettenis@gnu.org>
+
+	* floatformat.h (enum floatformat_byteorders): Add
+	floatformat_vax.
+	(floatformat_vax_aingle, floatformat_vax_double): Declare.
+
+2005-10-28  Dave Brolley  <brolley@redhat.com>
+
+	Contribute the following changes:
+	2003-09-29  Dave Brolley  <brolley@redhat.com>
+
+	* dis-asm.h (disassemble_info): insn_sets now (void *) to allow for
+	more exotic underlying types to be used.
+
+2005-10-25  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	disasm.h: Add declaration for print_insn_z80
+
+2005-09-30  Catherine Moore  <clm@cm00re.com>
+
+	* dis-asm.h (print_insn_bfin): Declare.
+
+2005-09-26  Mark Mitchell  <mark@codesourcery.com>
+
+	* libiberty.h (expandargv): New function.
+
+2005-08-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h: Remove mention of a29k.
+	* dis-asm.h: Remove a29k support.
+
+2005-08-17  Mark Kettenis  <kettenis@gnu.org>
+
+	* floatformat.h (struct floatformat): Change type of large
+	argument for is_valid member to `const void *'.
+	(floatformat_to_double): Change type of second argument to `const
+	void *'.
+	(floatformat_from_double): Change type of last argument to `void
+	*'.
+	(floatformat_is_valid): Change type of last argument to `const
+	void *'.
+
+2005-07-14  Jim Blandy  <jimb@redhat.com>
+
+	* dis-asm.h (print_insn_m32c): New declaration.
+
+2005-07-12  Ben Elliston  <bje@au.ibm.com>
+
+	* xregex2.h (regexec): Qualify this prototype with __extension__
+	when compiling with GNU C.
+
+2005-07-07  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* dis-asm.h (fprintf_ftype): Add format attribute.
+
+2005-07-03  Steve Ellcey  <sje@cup.hp.com>
+
+	PR other/13906
+	* ansidecl.h (ATTRIBUTE_ALIGNED_ALIGNOF): New.
+	* md5.h (md5_uintptr): New.
+	(md5_ctx): Align buffer field.
+
+2005-06-30  Daniel Berlin  <dberlin@dberlin.org>
+
+	* hashtab.h (HTAB_DELETED_ENTRY): New macro.
+	(HTAB_EMPTY_ENTRY): New macro.
+
+2005-06-20  Geoffrey Keating  <geoffk@apple.com>
+
+	* libiberty.h (strverscmp): Prototype.
+
+2005-06-17  Jakub Jelinek  <jakub@redhat.com>
+
+	* elf/external.h (GRP_ENTRY_SIZE): Define.
+
+2005-06-08  Zack Weinberg  <zack@codesourcery.com>
+
+	* dis-asm.h (get_arm_regnames): Update prototype.
+
+2005-06-07  Aldy Hernandez  <aldyh@redhat.com>
+	    Michael Snyder  <msnyder@redhat.com>
+	    Stan Cox  <scox@redhat.com>
+
+	* dis-asm.h: Externalize print_insn_ms1.
+
+2005-06-06  Gabriel Dos Reis  <gdr@integrable-solutions.net>
+
+	* libiberty.h (XOBFINISH): New.
+
+2005-06-03  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_callbacks): Add einfo.
+
+2005-06-01  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (vsnprintf): Add format attribute.
+
+2005-05-29  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* ansidecl.h: Add ATTRIBUTE_FPTR_PRINTF.
+
+2005-05-28  Eli Zaretskii  <eliz@gnu.org>
+
+	* libiberty.h: (snprintf) [!HAVE_DECL_SNPRINTF]: Declare if
+	needed.
+	(vsnprintf) [!HAVE_DECL_VSNPRINTF]: Declare if needed.
+
+2005-05-25  Richard Henderson  <rth@redhat.com>
+
+	* demangle.h (DEMANGLE_COMPONENT_HIDDEN_ALIAS): New.
+
+2005-05-24  Gabriel Dos Reis  <gdr@integrable-solutions.net>
+
+	* libiberty.h (ACONCAT): Properly cast value of alloca().
+
+	* ansidecl.h (ATTRIBUTE_UNUSED_LABEL): Don't define if
+	__cplusplus.
+
+2005-05-12  Steve Ellcey  <sje@cup.hp.com>
+
+	libiberty.h: Do not define empty basename prototype.
+
+2005-05-10  Nick Clifton  <nickc@redhat.com>
+
+	* Update the address and phone number of the FSF organization in
+	the GPL notices in the following files:
+	COPYING, ansidecl.h, bfdlink.h, bout.h, demangle.h, dis-asm.h,
+	dyn-string.h, fibheap.h, filenames.h, floatformat.h,
+	fnmatch.h, gdbm.h, getopt.h, hashtab.h, hp-symtab.h, ieee.h,
+	libiberty.h, md5.h, oasys.h, objalloc.h, obstack.h, os9k.h,
+	partition.h, progress.h, safe-ctype.h, sort.h, splay-tree.h,
+	symcat.h, ternary.h, xregex2.h, xtensa-config.h,
+	xtensa-isa-internal.h, xtensa-isa.h
+
+2005-04-25  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (unlock_std_streams): New.
+
+2005-04-19  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* hashtab.h, libiberty.h, objalloc.h, splay-tree.h, ternary.h:
+	Don't use the PTR macro.
+
+	* sort.h: Don't use the PARAMS macro.
+
+2005-04-16  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (unlock_stream): New.
+
+2005-04-13  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (fopen_unlocked, fdopen_unlocked, freopen_unlocked):
+	Remove parameter names.
+
+2005-04-11  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (fopen_unlocked, fdopen_unlocked, freopen_unlocked):
+	Provide prototypes for new functions.
+
+2005-03-29  Ian Lance Taylor  <ian@airs.com>
+
+	* libiberty.h: Fix indentation.
+
+2005-03-28  Ian Lance Taylor  <ian@airs.com>
+
+	* libiberty.h: Include <stdio.h>.
+	(PEX_RECORD_TIMES, PEX_USE_PIPES, PEX_SAVE_TEMPS): Define.
+	(PEX_LAST, PEX_SEARCH, PEX_SUFFIX, PEX_STDERR_TO_STDOUT): Define.
+	(PEX_BINARY_INPUT, PEX_BINARY_OUTPUT): Define.
+	(pex_init, pex_run, pex_read_output): Declare.
+	(pex_get_status, pex_get_times, pex_free, pex_one): Declare.
+	(struct pex_time): Define.
+
+2005-03-28  Mark Mitchell <mark@codesourcery.com>
+
+	* libiberty.h (ffs): Declare, if necessary.
+
+2005-03-27  Gabriel Dos Reis  <gdr@integreable-solutions.net>
+
+	* ternary.h: Don't use PARAMS anymore.
+
+2005-03-27  Gabriel Dos Reis  <gdr@integrable-solutions.net>
+
+	* md5.h: Remove definition and uses of __P.
+	* dyn-string.h: Remove uses of PARAMS.
+	* fibheap.h: Likewise.
+	* floatformat.h: Likewise.
+	* hashtab.h: Likewise.
+
+2005-03-26  Gabriel Dos Reis  <gdr@integrable-solutions.net>
+
+	* demangle.h: Remove uses of PARAMS.
+
+	* libiberty.h (ANSI_PROTOTYPES): Remove guard since
+	ANSI_PROTOTYPES is always assumed.
+	Remove uses of PARAMS throughout.
+
+2005-03-24  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (xstrndup): Declare.
+
+2005-03-22  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (make_relative_prefix): Add ATTRIBUTE_MALLOC.
+
+2005-03-22  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa-isa.h: Update a comment and whitespace.
+
+2005-03-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* bfdlink.h (bfd_link_info): Add gc_sections.
+
+2005-03-09  Mark Mitchell  <mark@codesourcery.com>
+
+	* libiberty.h (gettimeofday): Declare.
+
+2005-03-01  Jan Beulich  <jbeulich@novell.com>
+
+	* libiberty.h: Declare unlink_if_ordinary.
+
+2005-02-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* xtensa-isa-internal.h (xtensa_length_decode_fn): Warning fix.
+	* xtensa-isa.h (xtensa_insnbuf_to_chars): Likewise.
+	(xtensa_insnbuf_from_chars, xtensa_isa_length_from_chars): Likewise.
+
+2005-02-14  Paolo Bonzini  <bonzini@gnu.org>
+
+	PR bootstrap/19818
+	* ansidecl.h (PARAMS): Guard from redefinition.
+
+2005-02-03  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_hash_entry): Add u.undef.weak.
+
+2005-02-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (bfd_link_repair_undef_list): Declare.
+
+2005-01-10  Andreas Schwab  <schwab@suse.de>
+
+	* dis-asm.h (struct disassemble_info): Add skip_zeroes and
+	skip_zeroes_at_end.
+
+2004-12-11  Ben Elliston  <bje@au.ibm.com>
+
+	* fibheap.h (struct fibnode): Only use unsigned long bitfields
+	when __GNUC__ is defined and ints are less than 32-bits wide.
+
+2004-11-04  Paul Brook  <paul@codesourcery.com>
+
+	* bfdlink.h (bfd_link_info): Add default_imported_symver.
+
+2004-11-12  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa-isa-internal.h (xtensa_interface_internal): Add class_id.
+	* xtensa-isa.h (xtensa_interface_class_id): New prototype.
+
+2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
+	    Vineet Sharma      <vineets@noida.hcltech.com>
+
+	* dis-asm.h: Add prototype for print_insn_maxq_little.
+
+2004-10-26  Paul Brook  <paul@codesourcery.com>
+
+	* bfdlink.h (struct bfd_link_info): Add create_default_symver.
+
+2004-10-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 463
+	* bfdlink.h (bfd_link_callbacks): Add a pointer to struct
+	bfd_link_hash_entry to reloc_overflow.
+
+2004-10-07  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa-config.h (XSHAL_USE_ABSOLUTE_LITERALS,
+	XCHAL_HAVE_PREDICTED_BRANCHES, XCHAL_INST_FETCH_WIDTH): New.
+	(XCHAL_EXTRA_SA_SIZE, XCHAL_EXTRA_SA_ALIGN): Delete.
+
+	* xtensa-isa-internal.h (ISA_INTERFACE_VERSION): Delete.
+	(config_sturct struct): Delete.
+	(XTENSA_OPERAND_IS_REGISTER, XTENSA_OPERAND_IS_PCRELATIVE,
+	XTENSA_OPERAND_IS_INVISIBLE, XTENSA_OPERAND_IS_UNKNOWN,
+	XTENSA_OPCODE_IS_BRANCH, XTENSA_OPCODE_IS_JUMP,
+	XTENSA_OPCODE_IS_LOOP, XTENSA_OPCODE_IS_CALL,
+	XTENSA_STATE_IS_EXPORTED, XTENSA_INTERFACE_HAS_SIDE_EFFECT): Define.
+	(xtensa_format_encode_fn, xtensa_get_slot_fn, xtensa_set_slot_fn): New.
+	(xtensa_insn_decode_fn): Rename to ...
+	(xtensa_opcode_decode_fn): ... this.
+	(xtensa_immed_decode_fn, xtensa_immed_encode_fn, xtensa_do_reloc_fn,
+	xtensa_undo_reloc_fn): Update.
+	(xtensa_encoding_template_fn): Delete.
+	(xtensa_opcode_encode_fn, xtensa_format_decode_fn,
+	xtensa_length_decode_fn): New.
+	(xtensa_format_internal, xtensa_slot_internal): New types.
+	(xtensa_operand_internal): Delete operand_kind, inout, isPCRelative,
+	get_field, and set_field fields.  Add name, field_id, regfile,
+	num_regs, and flags fields.
+	(xtensa_arg_internal): New type.
+	(xtensa_iclass_internal): Change operands field to array of
+	xtensa_arg_internal.  Add num_stateOperands, stateOperands,
+	num_interfaceOperands, and interfaceOperands fields.
+	(xtensa_opcode_internal): Delete length, template, and iclass fields.
+	Add iclass_id, flags, encode_fns, num_funcUnit_uses, and funcUnit_uses.
+	(opname_lookup_entry): Delete.
+	(xtensa_regfile_internal, xtensa_interface_internal,
+	xtensa_funcUnit_internal, xtensa_state_internal,
+	xtensa_sysreg_internal, xtensa_lookup_entry): New.
+	(xtensa_isa_internal): Replace opcode_table field with opcodes field.
+	Change type of opname_lookup_table.  Delete num_modules,
+	module_opcode_base, module_decode_fn, config, and has_density fields.
+	Add num_formats, formats, format_decode_fn, length_decode_fn,
+	num_slots, slots, num_fields, num_operands, operands, num_iclasses,
+	iclasses, num_regfiles, regfiles, num_states, states,
+	state_lookup_table, num_sysregs, sysregs, sysreg_lookup_table,
+	max_sysreg_num, sysreg_table, num_interfaces, interfaces,
+	interface_lookup_table, num_funcUnits, funcUnits and
+	funcUnit_lookup_table fields.
+	(xtensa_isa_module, xtensa_isa_modules): Delete.
+	(xtensa_isa_name_compare): New prototype.
+	(xtisa_errno, xtisa_error_msg): New.
+	* xtensa-isa.h (XTENSA_ISA_VERSION): Define.
+	(xtensa_isa): Change type.
+	(xtensa_operand): Delete.
+	(xtensa_format, xtensa_regfile, xtensa_state, xtensa_sysreg,
+	xtensa_interface, xtensa_funcUnit, xtensa_isa_status,
+	xtensa_funcUnit_use): New types.
+	(libisa_module_specifier): Delete.
+	(xtensa_isa_errno, xtensa_isa_error_msg): New prototypes.
+	(xtensa_insnbuf_free, xtensa_insnbuf_to_chars,
+	xtensa_insnbuf_from_chars): Update prototypes.
+	(xtensa_load_isa, xtensa_extend_isa, xtensa_default_isa,
+	xtensa_insn_maxlength, xtensa_num_opcodes, xtensa_decode_insn,
+	xtensa_encode_insn, xtensa_insn_length,
+	xtensa_insn_length_from_first_byte, xtensa_num_operands,
+	xtensa_operand_kind, xtensa_encode_result,
+	xtensa_operand_isPCRelative): Delete.
+	(xtensa_isa_init, xtensa_operand_inout, xtensa_operand_get_field,
+	xtensa_operand_set_field, xtensa_operand_encode,
+	xtensa_operand_decode, xtensa_operand_do_reloc,
+	xtensa_operand_undo_reloc): Update prototypes.
+	(xtensa_isa_maxlength, xtensa_isa_length_from_chars,
+	xtensa_isa_num_pipe_stages, xtensa_isa_num_formats,
+	xtensa_isa_num_opcodes, xtensa_isa_num_regfiles, xtensa_isa_num_states,
+	xtensa_isa_num_sysregs, xtensa_isa_num_interfaces,
+	xtensa_isa_num_funcUnits, xtensa_format_name, xtensa_format_lookup,
+	xtensa_format_decode, xtensa_format_encode, xtensa_format_length,
+	xtensa_format_num_slots, xtensa_format_slot_nop_opcode,
+	xtensa_format_get_slot, xtensa_format_set_slot, xtensa_opcode_decode,
+	xtensa_opcode_encode, xtensa_opcode_is_branch, xtensa_opcode_is_jump,
+	xtensa_opcode_is_loop, xtensa_opcode_is_call,
+	xtensa_opcode_num_operands, xtensa_opcode_num_stateOperands,
+	xtensa_opcode_num_interfaceOperands, xtensa_opcode_num_funcUnit_uses,
+	xtensa_opcode_funcUnit_use, xtensa_operand_name,
+	xtensa_operand_is_visible, xtensa_operand_is_register,
+	xtensa_operand_regfile, xtensa_operand_num_regs,
+	xtensa_operand_is_known_reg, xtensa_operand_is_PCrelative,
+	xtensa_stateOperand_state, xtensa_stateOperand_inout,
+	xtensa_interfaceOperand_interface, xtensa_regfile_lookup,
+	xtensa_regfile_lookup_shortname, xtensa_regfile_name,
+	xtensa_regfile_shortname, xtensa_regfile_view_parent,
+	xtensa_regfile_num_bits, xtensa_regfile_num_entries,
+	xtensa_state_lookup, xtensa_state_name, xtensa_state_num_bits,
+	xtensa_state_is_exported, xtensa_sysreg_lookup,
+	xtensa_sysreg_lookup_name, xtensa_sysreg_name, xtensa_sysreg_number,
+	xtensa_sysreg_is_user, xtensa_interface_lookup, xtensa_interface_name,
+	xtensa_interface_num_bits, xtensa_interface_inout,
+	xtensa_interface_has_side_effect, xtensa_funcUnit_lookup,
+	xtensa_funcUnit_name, xtensa_funcUnit_num_copies): New prototypes.
+2004-10-07  Jeff Baker  <jbaker@qnx.com>
+
+	* bfdlink.h (bfd_link_info): Add bitfield: warn_shared_textrel.
+
+2004-09-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_hash_entry): Move und_next into elements
+	of union.
+
+2004-09-13  Aaron W. LaFramboise  <aaronavay62@aaronwl.com>
+
+	* libiberty.h (basename): Prototype for __MINGW32__.
+
+2004-09-04  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* ansidecl.h (ATTRIBUTE_SENTINEL): Define.
+	* libiberty.h (concat, reconcat, concat_length, concat_copy,
+	concat_copy2): Use ATTRIBUTE_SENTINEL.
+
+2004-08-13  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_callbacks): Remove "error_handler".
+	(LD_DEFINITION_IN_DISCARDED_SECTION): Delete.
+
+2004-08-02  Gabriel Dos Reis  <gdr@integrable-solutions.net>
+
+	* libiberty.h (XDELETE, XDELETEVEC, XRESIZEVEC): Remove any
+	const-qualification before disposal.
+
+2004-07-24  Bernardo Innocenti  <bernie@develer.com>
+
+	* ansidecl.h (ARG_UNUSED): New Macro.
+
+2004-07-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* bin-bugs.h (REPORT_BUGS_TO): Set to
+	"<URL:http://www.sourceware.org/bugzilla/>".
+
+2004-07-21  Paolo Bonzini  <bonzini@gnu.org>
+
+	* ansidecl.h (ATTRIBUTE_PURE): New.
+
+2004-07-13  Bernardo Innocenti  <bernie@develer.com>
+
+	* libiberty.h (XNEW, XCNEW, XNEWVEC, XCNEWVEC, XOBNEW): Move here from
+	libcpp/internal.h.
+	(XDELETE, XRESIZEVEC, XDELETEVEC, XNEWVAR, XCNEWVAR, XRESIZEVAR): New
+	macros.
+
+2004-07-13  Bernardo Innocenti  <bernie@develer.com>
+
+	* libiberty.h (ASTRDUP): Add casts required for stricter
+	type conversion rules of C++.
+	* obstack.h (obstack_free): Likewise.
+
+2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* dis-asm.h (print_insn_crx): Declare.
+
+2004-06-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_order): Update comment.
+
+2004-05-11  Jakub Jelinek  <jakub@redhat.com>
+
+	* bfdlink.h (struct bfd_link_info): Add relro, relro_start and
+	relro_end fields.
+
+2004-05-04  Andreas Jaeger  <aj@suse.de>
+
+	* demangle.h: Do not use C++ reserved keyword typename as
+	parameter for cplus_demangle_fill_builtin_type.
+
+2004-04-22  Richard Henderson  <rth@redhat.com>
+
+	* hashtab.h (struct htab): Add size_prime_index.
+
+2004-04-13  Jeff Law  <law@redhat.com>
+
+	* hashtab.h (htab_remove_elt_with_hash): Prototype new function.
+
+2004-03-30  Zack Weinberg  <zack@codesourcery.com>
+
+	* hashtab.h, splay-tree.h: Use new shorter form of GTY markers.
+
+2004-03-25  Stan Shebs  <shebs@apple.com>
+
+	* mpw/: Remove subdirectory and everything in it.
+
+2004-03-23  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 51.
+	* bfdlink.h (struct bfd_link_info): Add wrap_char.
+
+2004-03-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* bfdlink.h (bfd_link_info): Correct comments for the
+	unresolved_syms_in_objects field.
+
+2004-02-24  Ian Lance Taylor  <ian@wasabisystems.com>
+
+	* dyn-string.h: Update copyright date.
+
+2004-02-23  Ian Lance Taylor  <ian@wasabisystems.com>
+
+	* dyn-string.h: Remove test of IN_LIBGCC2 and IN_GLIBCPP_V3 and
+	the associated #defines.
+
+2004-01-12  Ian Lance Taylor  <ian@wasabisystems.com>
+
+	* demangle.h: Instead of checking ANSI_PROTOTYPES, just include
+	"libiberty.h".
+
+	* demangle.h: If ANSI_PROTOTYPES is defined, include <stddef.h>.
+
+	* demangle.h (enum demangle_component_type): Define.
+	(struct demangle_operator_info): Declare.
+	(struct demangle_builtin_type_info): Declare.
+	(struct demangle_component): Define.
+	(cplus_demangle_fill_component): Declare.
+	(cplus_demangle_fill_name): Declare.
+	(cplus_demangle_fill_builtin_type): Declare.
+	(cplus_demangle_fill_operator): Declare.
+	(cplus_demangle_fill_extended_operator): Declare.
+	(cplus_demangle_fill_ctor, cplus_demangle_fill_dtor): Declare.
+	(cplus_demangle_v3_components): Declare.
+	(cplus_demangle_print): Declare.
+
+For older changes see ChangeLog-9103
+
+Copyright (C) 2004-2012 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.25/include/ChangeLog-9103 b/binutils-2.25/include/ChangeLog-9103
new file mode 100644
index 00000000..bac53022
--- /dev/null
+++ b/binutils-2.25/include/ChangeLog-9103
@@ -0,0 +1,2688 @@
+2003-12-19  Andreas Tobler  <a.tobler@schweiz.ch>
+
+	* include/fibheap.h (fibnode): Use __extension__ for
+	bit-fields mark and degree if __GNUC__.
+
+2003-12-18  Kazu Hirata  <kazu@cs.umass.edu>
+
+	* include/fibheap.h (fibnode): Use unsigned long int for
+	bit-fields if __GNUC__ is defined.
+
+2003-12-19  Andreas Tobler  <a.tobler@schweiz.ch>
+
+	* fibheap.h (fibnode): Use __extension__ for
+	bit-fields mark and degree if __GNUC__.
+
+2003-12-18  Kazu Hirata  <kazu@cs.umass.edu>
+
+	* fibheap.h (fibnode): Use unsigned long int for
+	bit-fields if __GNUC__ is defined.
+
+2003-12-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* bfdlink.h (bfd_link_info): Change relax_finalizing to
+	need_relax_finalize.
+
+2003-12-03  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_hash_entry): Rename "next" to "und_next".
+
+2003-12-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_info): Remove mpc860c0 field.
+
+2003-11-14  Nick Clifton  <nickc@redhat.com>
+
+	* dis-asm.h (struct disassemble_info): Add new field
+	'symbol_is_valid' which is a function which can tell the
+	disassembler to skip certain symbols as they should not be
+	displayed to the user.
+	(arm_symbol_is_valid): New prototype.  This is the ARM
+	specific function for the symbol_is_valid field.
+	(generic_symbol_is_valid): New prototype.  This is the default
+	function pointed to by the symbol_is_valid field.
+
+2003-11-06  Bruno Rohee  <bruno@rohee.com>
+
+	* hp-symtab.h: Fix "the the" typo.
+
+2003-10-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* bfdlink.h (bfd_elf_version_expr): Add "symbol" and remove
+	"wildcard".
+
+2003-10-22  Joseph S. Myers  <jsm@polyomino.org.uk>
+
+	* obstack.h: Merge the following change from gnulib:
+	2003-10-21  Paul Eggert  <eggert@twinsun.com>
+	* obstack.h (obstack_1grow_fast): Properly parenthesize arg.
+	(obstack_ptr_grow_fast, obstack_int_grow_fast):
+	Don't use lvalue casts, as GCC plans to remove support for them
+	in GCC 3.5.  Reported by Joseph S. Myers.  This bug
+	was also present in the non-GCC version, indicating that this
+	code had always been buggy and had never been widely used.
+	(obstack_1grow, obstack_ptr_grow, obstack_int_grow, obstack_blank):
+	Use the fast variant of each macro, rather than copying the
+	definiens of the fast variant; that way, we'll be more likely to
+	catch future bugs in the fast variants.
+
+2003-10-22  Jakub Jelinek  <jakub@redhat.com>
+
+	* bfdlink.h (struct bfd_elf_version_expr): Remove match field.
+	Add wildcard and mask fields.
+	(BFD_ELF_VERSION_C_TYPE): Define.
+	(BFD_ELF_VERSION_CXX_TYPE): Likewise.
+	(BFD_ELF_VERSION_JAVA_TYPE): Likewise.
+	(struct bfd_elf_version_expr_head): New.
+	(struct bfd_elf_version_tree): Add match field.
+	Change type of globals and locals fields
+	to struct bfd_elf_version_expr_head.
+
+2003-09-22  Andrew Cagney  <cagney@redhat.com>
+
+	* floatformat.h (struct floatformat): Add field "is_valid".
+
+2003-09-15  Andrew Cagney  <cagney@redhat.com>
+
+	* floatformat.h (floatformat_to_double): Make input buffer constant.
+	(floatformat_from_double, floatformat_is_valid): Ditto.
+
+2003-09-15  Andrew Cagney  <cagney@redhat.com>
+
+	* floatformat.h (struct floatformat): Make "exp_bias" signed.
+
+2003-09-15  Daniel Jacobowitz  <drow@mvista.com>
+
+	* floatformat.h (floatformat_is_valid): Add prototype.
+
+2003-08-27  Andrew Cagney  <cagney@redhat.com>
+
+	* dis-asm.h (init_disassemble_info): Declare.
+	(INIT_DISASSEMBLE_INFO): Redefine as a call to
+	init_disassemble_info.
+	(INIT_DISASSEMBLE_INFO_NO_ARCH): Ditto.
+
+2003-08-20  Nick Clifton  <nickc@redhat.com>
+
+	* bfdlink.h (enum report_method): New enum.  Describes how to
+	report something.
+	(struct bfd_link_info): Delete fields 'no_undefined' and
+	'allow_shlib_undefined'.  Replace with
+	'unresolved_symbols_in_objects' and
+	'unresolved_symbols_in_shared_libs'.
+
+2003-08-07  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h: Remove PARAMS macro.  Replace PTR with void *.
+	* dis-asm.h: Likewise.
+
+2003-07-09  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa-config.h: Undef all macros before defining them.
+
+2003-07-06  H.J. Lu <hongjiu.lu@intel.com>
+
+	* demangle.h: Support C++.
+
+2003-07-01  Zack Weinberg  <zack@codesourcery.com>
+
+	* filenames.h: New file imported from binutils.
+
+2003-06-30  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa-config.h: New file imported from binutils.
+
+2003-06-30  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa-config.h (XCHAL_HAVE_CONST16, XCHAL_HAVE_ABS,
+	XCHAL_HAVE_ADDX, XCHAL_HAVE_L32R): Define.
+
+2003-06-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h: Correct spelling of "relocatable".
+
+2003-06-22  Zack Weinberg  <zack@codesourcery.com>
+
+	* safe-ctype.h (HC_UNKNOWN, HC_ASCII, HC_EBCDIC): Rename to
+	HOST_CHARSET_UNKNOWN, HOST_CHARSET_ASCII, HOST_CHARSET_EBCDIC
+	respectively.
+
+2003-06-21  Zack Weinberg  <zack@codesourcery.com>
+
+	* safe-ctype.h (HC_UNKNOWN, HC_ASCII, HC_EBCDIC, HOST_CHARSET):
+	New #defines.
+
+2003-06-17  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* ansidecl.h: Delete HAVE_LONG_DOUBLE GCC bootstrap support.
+
+2003-05-23  Jakub Jelinek  <jakub@redhat.com>
+
+	* bfdlink.h (struct bfd_link_info): Add execstack and noexecstack.
+
+2003-06-03  H.J. Lu <hongjiu.lu@intel.com>
+
+	* bfdlink.h (LD_DEFINITION_IN_DISCARDED_SECTION): New.
+
+2003-05-30  Ulrich Drepper  <drepper@redhat.com>
+	    Jakub Jelinek  <jakub@redhat.com>
+
+	* bfdlink.h (struct bfd_link_info): Add pie and executable
+	bits.
+
+2003-05-21  Nick Clifton  <nickc@redhat.com>
+
+	* bfdlink.h (struct bfd_link_hash_table): Fix typo in comment.
+
+2003-05-15  Jim Blandy  <jimb@redhat.com>
+
+	* libiberty.h (hex_value): Make the value an unsigned int, to
+	avoid unexpected sign-extension when cast to unsigned types larger
+	than int --- like bfd_vma, on some platforms.
+	(_hex_value): Update declaration.
+
+2003-05-09  Alan Modra  <amodra@bigpond.net.au>
+
+	* xtensa-isa-internal.h (xtensa_isa_module_struct): Remove const on
+	gen_num_opcodes_fn return type.
+
+2003-05-07  Jason Merrill  <jason@redhat.com>
+
+	* hashtab.h (iterative_hash): Prototype.
+	(iterative_hash_object): New macro.
+
+2003-04-28  H.J. Lu <hjl@gnu.org>
+
+	* bfdlink.h (bfd_link_info): Add relax_finalizing.
+
+2003-04-23  H.J. Lu <hjl@gnu.org>
+
+	* bfdlink.h (bfd_link_callbacks): Add error_handler.
+
+2003-04-02  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa-config.h: Remove comment indicating that this is a
+	generated file.
+
+2003-04-01  Bob Wilson  <bob.wilson@acm.org>
+
+	* dis-asm.h (print_insn_xtensa): Declare.
+	* xtensa-config.h: New file.
+	* xtensa-isa-internal.h: Likewise.
+	* xtensa-isa.h: Likewise.
+
+2003-03-17  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* ansidecl.h (ATTRIBUTE_NONNULL, ATTRIBUTE_NULL_PRINTF,
+	ATTRIBUTE_NULL_PRINTF_1, ATTRIBUTE_NULL_PRINTF_2,
+	ATTRIBUTE_NULL_PRINTF_3, ATTRIBUTE_NULL_PRINTF_4,
+	ATTRIBUTE_NULL_PRINTF_5): New.
+	(ATTRIBUTE_PRINTF): Add ATTRIBUTE_NONNULL.
+
+2003-03-17  Jan Hubicka  <jh@suse.cz>
+
+	* hashtab.h (htab_traverse_noresize): Declare.
+
+2003-02-27  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h: Document return value of physmem routines.
+
+2003-02-20  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (physmem_total, physmem_available): Prototype.
+
+2003-02-20  Daniel Jacobowitz  <drow@mvista.com>
+
+	* libiberty.h (lrealpath): Add declaration.
+
+2003-01-31  Grant Grundler  <grundler@dsl2.external.hp.com>
+
+	* hppa.h (ldwa, ldda): Add ordered opcodes.
+
+2003-01-26  Daniel Jacobowitz  <drow@mvista.com>
+
+	* hashtab.h (htab_alloc_with_arg, htab_free_with_arg): Add new types.
+	(struct htab): Add alloc_arg, alloc_with_arg_f, free_with_arg_f.
+	(htab_create_alloc_ex): New prototype.
+	(htab_set_functions_ex): New prototype.
+
+2002-07-17  Geoffrey Keating  <geoffk@redhat.com>
+
+	* splay-tree.h (GTY): Define if undefined.
+	(splay_tree_allocate_fn): Return PTR for compatibility, not void *.
+	(struct splay_tree_node_s): Support gengtype.
+	(struct splay_tree_s): Likewise.  Make allocate_data a PTR,
+	not a void *.
+
+2002-01-02  Ben Elliston  <bje@redhat.com>
+
+	* dis-asm.h (print_insn_iq2000): Declare.
+
+2002-12-24    Dmitry Diky <diwil@mail.ru>
+
+	* dis-asm.h: Add msp430 disassembler prototype.
+
+2002-12-27  Chris Demetriou  <cgd@broadcom.com>
+
+	* dis-asm.h (print_mips_disassembler_options): Prototype.
+
+2002-12-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_info): Add "strip_discarded".
+
+2002-12-20  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_link_info): Replace bfd_boolean fields with
+	bit-fields.  Rearrange to put all like types together.
+
+2002-11-30  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h: Replace boolean with bfd_boolean.  Formatting.
+
+2002-11-23  Simon Burge  <simonb@wasabisystems.com>
+
+	* libiberty.h (basename): Add NetBSD to the list.
+
+2002-11-22  Daniel Jacobowitz  <drow@mvista.com>
+
+	* libiberty.h (make_relative_prefix): Add prototype.
+
+2002-11-14  Egor Duda  <deo@logos-m.ru>
+
+	* bfdlink.h (struct bfd_link_info): Add new boolean
+	field pei386_runtime_pseudo_reloc.
+
+2002-10-26  Roger Sayle  <roger@eyesopen.com>
+
+	* partition.h:  Close the extern "C" scope when compiling with C++.
+
+2002-10-26  Roger Sayle  <roger@eyesopen.com>
+	    DJ Delorie <dj@redhat.com>
+
+	PR bootstrap/8351
+	* getopt.h: Avoid prototyping getopt with no arguments in C++.
+
+2002-10-24  Nathan Tallent  <eraxxon@alumni.rice.edu>
+
+	* ansidecl.h (__STDC__): Add (__alpha && __cplusplus) to the
+	list of	platform compilers that may look, smell and act
+	like __STDC__ but that may not define it.
+
+2002-10-11  David O'Brien  <obrien@FreeBSD.org>
+
+	* getopt.h: getopt is in unistd.h (based on SUSv2).
+
+2002-09-26  Andrew Cagney  <ac131313@redhat.com>
+
+	* regs/: Delete directory.
+
+2002-09-19  Alexandre Oliva  <aoliva@redhat.com>
+
+	* libiberty.h (asprintf, vasprintf): Don't declare them if the
+	corresponding HAVE_DECL_ macro is 1.
+
+2002-09-19  Nathan Tallent  <eraxxon@alumni.rice.edu>
+
+	* dis-asm.h: Remove (errant) trailing semicolon (;) from the
+	extern "C" { } declaration.
+
+2002-09-04  Nick Clifton  <nickc@redhat.com>
+
+	* dis-asm.h (print_ppc_disassembler_options): Prototype.
+
+2002-08-28  Michael Hayes <m.hayes@elec.canterbury.ac.nz>
+
+	* dis-asm.h: Add standard disassembler for tic4x.
+
+2002-08-07  H.J. Lu <hjl@gnu.org>
+
+	* bfdlink.h (bfd_link_info): Add allow_undefined_version.
+	(bfd_elf_version_expr): Add symver and script.
+
+2002-07-31  Ian Dall  <ian@sibyl.beware.dropbear.id.au>
+
+	* bfdlink.h (bfd_link_common_skip_ar_symbols): New enum.
+	(struct bfd_link_info): Add new field 'common_skip_ar_symbols'.
+
+2002-07-19  Denis Chertykov  <denisc@overta.ru>
+	    Matthew Green  <mrg@redhat.com>
+
+	* dis-asm.h (print_insn_ip2k): Declare.
+
+2002-07-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* bfdlink.h (struct bfd_sym_chain): Declare.
+	(struct bfd_link_info): Add gc_sym_list.  Formatting fixes.
+
+2002-06-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* demangle.h: #include "ansidecl.h" rather than #include <ansidecl.h>.
+	* fibheap.h: Likewise.
+	* hashtab.h: Likewise.
+	* partition.h: Likewise.
+	* sort.h: Likewise.
+	* splay-tree.h: Likewise.
+
+2002-06-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* libiberty.h (basename): Don't declare if HAVE_DECL_BASENAME.
+	* getopt.h (getopt): Don't declare if HAVE_DECL_GETOPT.
+
+2002-06-18  Dave Brolley  <brolley@redhat.com>
+
+	From Catherine Moore:
+	* dis-asm.h (print_insn_frv): New prototype.
+
+2002-06-09  Andrew Cagney  <cagney@redhat.com>
+
+	* remote-sim.h: Move to directory gdb/.
+	* callback.h: Move to directory gdb/.
+
+2002-06-07  Charles Wilson  <cwilson@ece.gatech.edu>
+
+	* bfdlink.h (struct bfd_link_info): Change type of
+	pei386_auto_import field to int so that -1 can mean enabled by
+	default and 1 can mean enabled by command line switch.
+
+2002-06-06  DJ Delorie  <dj@redhat.com>
+
+	* hashtab.h (htab): Rearrange new members for backward
+	compatibility.
+	(htab_create): Don't use a macro that requires other headers.
+
+2002-06-05  Geoffrey Keating  <geoffk@redhat.com>
+
+	* hashtab.h (htab_create): Restore prototype for backward
+	compatibility.
+	(htab_try_create): Likewise.
+
+2002-05-22  Geoffrey Keating  <geoffk@redhat.com>
+
+	* hashtab.h (struct htab): Update for change to length specifier.
+
+2002-05-10  Geoffrey Keating  <geoffk@redhat.com>
+
+	* hashtab.h (GTY): Define if undefined.
+	(htab_alloc): New typedef.
+	(htab_free): New typedef.
+	(struct htab): Support gengtype; allow user-specified memory
+	allocation.
+	(htab_create_alloc): New.
+	(htab_create): Replace with #define.
+	(htab_try_create): Delete.
+
+2002-05-28  Kuang Hwa Lin <kuang@sbcglobal.net>
+
+	* dis-asm.h: Prototype print_insn_dlx.
+
+2002-05-23  Andrew Cagney  <ac131313@redhat.com>
+
+	* sim-d10v.h: Delete file.  Moved to include/gdb/.
+
+2002-05-21  H.J. Lu  (hjl@gnu.org)
+
+	* bfdlink.h (bfd_link_info): Add allow_multiple_definition.
+
+2002-05-17  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* dis-asm.h (print_insn_shl, print_insn_sh64l): Remove prototype.
+
+2002-04-16  David S. Miller  <davem@redhat.com>
+
+	* xregex2.h (__restrict_arr): Define to __restrict on GCC
+	3.1 and later.  Do not redefine.
+
+2002-04-01  Phil Edwards  <pme@gcc.gnu.org>
+
+	* dyn-string.h:  Also allow IN_GLIBCPP_V3 to redefine names.
+
+2002-03-10  Daniel Jacobowitz <drow@mvista.com>
+
+	* gdb: New directory.
+
+2002-03-06  Andrew Cagney  <ac131313@redhat.com>
+
+	* floatformat.h (floatformat_arm_ext): Delete declaration.
+
+2002-02-21  Jim Blandy  <jimb@redhat.com>
+
+	Allow the user to specify functions for allocating memory for
+	splay tree roots and nodes.
+	* splay-tree.h (splay_tree_allocate_fn, splay_tree_deallocate_fn):
+	New types.
+	(splay_tree): New fields: `allocate', `deallocate', and
+	`allocate_data'.
+	(splay_tree_new_with_allocator): New function declaration.
+
+2002-02-15  Alan Modra  <amodra@bigpond.net.au>
+
+	Support arbitrary length fill patterns.
+	* bfdlink.h (enum bfd_link_order_type): Remove bfd_fill_link_order.
+	(struct bfd_link_order): Remove fill.  Add data.size.
+
+2002-02-08  Alexandre Oliva  <aoliva@redhat.com>
+
+	Contribute sh64-elf.
+	2000-11-25  Hans-Peter Nilsson  <hpn@cygnus.com>
+	* dis-asm.h (print_insn_sh64): New prototype.
+	(print_insn_sh64l): New prototype.
+	(print_insn_sh64x_media): New prototype.
+
+2002-02-05  Frank Ch. Eigler  <fche@redhat.com>
+
+	* dis-asm.h (disassemble_info): New field `insn_sets'.
+	(INIT_DISASSEMBLE_INFO): Clear it.
+
+2002-02-05  Jason Merrill  <jason@redhat.com>
+
+	* demangle.h (cplus_demangle_v3): Add "options" parm.
+	(cplus_demangle_v3_type): Remove prototype.
+	(DMGL_VERBOSE): New macro.
+	(DMGL_TYPES): New macro.
+
+2002-02-02  H.J. Lu  (hjl@gnu.org)
+
+	* demangle.h (cplus_demangle_v3_type): New prototype.
+
+2002-01-31  Ivan Guzvinec  <ivang@opencores.org>
+
+	* dis-asm.h : Add support for or32 targets
+
+2002-01-28  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (C_alloca): Add ATTRIBUTE_MALLOC.
+
+2002-01-27  David O'Brien  <obrien@FreeBSD.org>
+
+	* cgen.h (BFD_VERSION): Use BFD_VERSION_DATE instead.
+
+2001-12-14  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialise the
+	disassembler_options field (to NULL).
+
+2001-12-13  Jakub Jelinek  <jakub@redhat.com>
+
+	* bfdlink.h (struct bfd_link_info): Add eh_frame_hdr field.
+
+2001-12-07  Geoffrey Keating  <geoffk@redhat.com>
+
+	* dis-asm.h (print_insn_xstormy16): Declare.
+
+2001-12-06  Richard Henderson  <rth@redhat.com>
+
+	* demangle.h (no_demangling): New.
+	(NO_DEMANGLING_STYLE_STRING): New.
+
+2001-11-14  Alan Modra  <amodra@bigpond.net.au>
+
+	* dis-asm.h (print_insn_i386): Declare.
+
+2001-11-11  Timothy Wall  <twall@alum.mit.edu>
+
+	* dis-asm.h: Fix comment to refer to octets rather than bytes.
+
+2001-10-30  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* dis-asm.h (print_insn_mmix): Add prototype.
+
+2001-10-24  Neil Booth  <neil@daikokuya.demon.co.uk>
+
+	* safe-ctype.h (_sch_isbasic, IS_ISOBASIC): New.
+
+2001-10-22  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (hex_init): Revert delete.
+
+	* libiberty.h (_hex_value): Const-ify.
+	(hex_init): Delete.
+
+2001-10-16  Christopher Faylor  <cgf@redhat.com>
+
+	* filenames.h: Add cygwin to the list of dosish style path systems.
+
+2001-10-07  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* demangle.h (demangler_engine): Const-ify.
+	* libiberty.h (buildargv): Likewise.
+
+2001-10-03  Vassili Karpov  <malc@pulsesoft.com>
+
+	* bfdlink.h (struct bfd_link_info): Add nocopyreloc field.
+
+2001-09-24  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (reconcat): New function.
+
+2001-09-18  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (concat, concat_length, concat_copy, concat_copy2,
+	ACONCAT): Improve comments.
+
+2001-09-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* objalloc.h (OBJALLOC_ALIGN): Define using offsetof.
+
+2001-09-17  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (concat_length, concat_copy, concat_copy2,
+	libiberty_concat_ptr, ACONCAT): New.
+
+	* libiberty.h (ASTRDUP): New macro.
+	libiberty_optr, libiberty_nptr, libiberty_len): Declare.
+
+2001-08-29  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* ansidecl.h: Update comments reflecting previous change.
+
+2001-08-27  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* ansidecl.h (VA_OPEN, VA_CLOSE): Allow multiple uses.
+
+2001-08-25  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* bfdlink.h (struct bfd_link_info): Change 'spare_dynamic_tags' to
+	unsigned to remove a compile time warning message.
+
+2001-08-24  H.J. Lu  <hjl@gnu.org>
+
+	* bfdlink.h (bfd_link_hash_table_type): New. The linker hash
+	table type, bfd_link_generic_hash_table and
+	bfd_link_elf_hash_table.
+	(bfd_link_hash_table): Add a new field, type, for the linker
+	hash table type.
+
+2001-08-23  Jakub Jelinek  <jakub@redhat.com>
+
+	* bfdlink.h (struct bfd_link_info): Add combreloc and
+	spare_dynamic_tags fields.
+
+2001-08-23  Lars Brinkhoff  <lars@nocrew.org>
+
+	* dyn-string.h, fibheap.h, partition.h, sort.h, splay-tree.h:
+	replace "GNU CC" with "GCC".
+
+2001-08-21  Richard Henderson  <rth@redhat.com>
+
+	* fibheap.h: Tidy formatting.
+	(fibnode_t): Limit degree to 31 bits to avoid warning.
+
+2001-08-20  Daniel Berlin  <dan@cgsoftware.com>
+
+	* fibheap.h: New file. Fibonacci heap.
+
+2001-08-20  Andrew Cagney  <ac131313@redhat.com>
+
+	* floatformat.h (floatformat_arm_ext): Document as deprecated.
+	(floatformat_arm_ext_big, floatformat_arm_ext_littlebyte_bigword)
+	(floatformat_ia64_spill_little, floatformat_ia64_quad_little)
+	(floatformat_ia64_spill_big, floatformat_ia64_quad_big)
+	(floatformat_m88110_harris_ext): Declare.
+
+2001-08-18  Zack Weinberg  <zackw@panix.com>
+
+	* ansidecl.h: Reorganize for readability, remove documentation
+	of obsolete macros, document PARAMS and VPARAMS.  Add new
+	macros VA_OPEN, VA_CLOSE, and VA_FIXEDARG for nicer variadic
+	function implementation.
+
+2001-08-16  Richard Henderson  <rth@redhat.com>
+
+	* hashtab.h (htab_hash_string): Declare.
+
+2001-08-10  Andrew Cagney  <ac131313@redhat.com>
+
+	* libiberty.h (lbasename): Change function declaration to return a
+	const char pointer.
+
+2001-08-02  Mark Kettenis  <kettenis@gnu.org>
+
+	* xregex.h (_REGEX_RE_COMP): Define.
+	(re_comp): Define to xre_comp.
+	(re_exec): Define to xre_exec.
+
+2001-08-02  Charles Wilson  <cwilson@ece.gatech.edu>
+
+	* bfdlink.h (struct bfd_link_info): add new boolean
+	field pei386_auto_import.
+
+2001-07-18  Andreas Jaeger  <aj@suse.de>
+
+	* xregex2.h: Place under LGPL version 2.1.
+
+2001-07-10  Jeff Johnston  <jjohnstn@redhat.com>
+
+	* xregex.h: New file to support libiberty regex.
+	* xregex2.h: Ditto.
+
+2001-06-15  Hans-Peter Nilsson  <hp@axis.com>
+
+	* bfdlink.h (struct bfd_link_info): New member export_dynamic.
+
+2001-05-16  Matt Kraai  <kraai@alumni.carnegiemellon.edu>
+
+	* partition.h: Fix misspelling of `implementation'.
+
+2001-05-10  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* ansidecl.h (NULL_PTR): Delete.
+
+2001-05-07  Zack Weinberg  <zackw@stanford.edu>
+
+	* demangle.h: Use PARAMS for all prototypes.
+	* ternary.h: Use PARAMS for all prototypes.  Use PTR, not void *.
+	Make arguments constant where possible.
+
+2001-05-07  Mark Mitchell  <mark@codesourcery.com>
+
+	* splay-tree.h (splay_tree_max): New function.
+	(splay_tree_min): Likewise.
+
+2001-04-27  Johan Rydberg  <jrydberg@opencores.org>
+
+	* dis-asm.h (print_insn_openrisc): Add prototype.
+
+2001-04-15  Daniel Berlin  <dan@cgsoftware.com>
+
+	* ternary.h: New file - Ternary search tree header.
+
+2001-04-13  Jakub Jelinek  <jakub@redhat.com>
+
+	* bfdlink.h (bfd_link_discard): Add discard_sec_merge.
+
+2001-04-03  Zack Weinberg  <zackw@stanford.edu>
+
+	* ansidecl.h: All logic from gcc/gansidecl.h moved here.
+
+2001-03-31  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (alloca): Handle setting C_ALLOCA.
+
+2001-03-20  Jim Blandy  <jimb@redhat.com>
+
+	* demangle.h (enum gnu_v3_constructor_kinds,
+	is_gnu_v3_mangled_ctor, enum gnu_v3_destructor_kinds,
+	is_gnu_v3_mangled_dtor): New declarations.
+
+2001-03-14  Nick Clifton  <nickc@redhat.com>
+
+	* ansidecl.h: Fix copyright dates.
+	* demangle.h: Fix copyright dates.
+	* floatformat.h: Fix copyright dates.
+	* fnmatch.h: Fix copyright dates.
+	* getopt.h: Fix copyright dates.
+	* libiberty.h: Add FSF copyright notice.
+	* md5.h: Fix copyright dates.
+	* obstack.h: Fix copyright dates.
+	* splay-tree.h: Fix copyright dates.
+
+2001-03-10  Neil Booth  <neil@daikokuya.demon.co.uk>
+	    John David Anglin  <dave@hiauly1.hia.nrc.ca>
+
+	* libiberty.h: Add lbasename.
+
+2001-03-06  Zack Weinberg  <zackw@stanford.edu>
+
+	* libiberty.h: Prototype C_alloca; define alloca to either
+	__builtin_alloca or C_alloca as appropriate.
+
+2001-03-01  John David Anglin  <dave@hiauly1.hia.nrc.ca>
+
+	* safe-ctype.h (_sch_test): Cast enum bit to unsigned short int for pcc
+	compatibility.
+
+2001-02-18  lars brinkhoff  <lars@nocrew.org>
+
+	* dis-asm.h: Add PDP-11 target.
+
+2001-02-09  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* dis-asm.h: Add linux target for S/390.
+
+2001-01-11  Peter Targett  <peter.targett@arccores.com>
+
+	* dis-asm.h (arc_get_disassembler): Correct declaration.
+
+2001-01-09  Philip Blundell  <philb@gnu.org>
+
+	* bin-bugs.h (REPORT_BUGS_TO): Set to `bug-binutils@gnu.org'.
+
+2000-12-18  Joseph S. Myers  <jsm28@cam.ac.uk>
+
+	* COPYING: Update to current
+	ftp://ftp.gnu.org/pub/gnu/Licenses/COPYING-2.0 (fixes references
+	to 19yy as example year in copyright notice).
+
+2000-12-19  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* dis-asm.h (struct disassemble_info): New member "section".
+	(INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize private_data member.
+	Initialize section member.
+
+2000-12-16  Herman A.J. ten Brugge  <Haj.Ten.Brugge@net.HCC.nl>
+
+	* safe-ctype.h: Make code work on all targets and not just on
+	targets where a char is 8 bits.
+
+2000-12-10  Fred Fish  <fnf@be.com>
+
+	* bfdlink.h (struct bfd_link_info): Add new allow_shlib_undefined
+	member to struct for systems where it is normal to have undefined
+	symbols in shared libraries at runtime and the runtime linker
+	takes care of redirecting them.
+
+2000-12-07  Zack Weinberg  <zack@wolery.stanford.edu>
+
+	* safe-ctype.h: New file.
+
+2000-12-06  Rodney Brown  <RodneyBrown@mynd.com>
+
+	* getopt.h obstack.h: Standarize copyright statement.
+
+2000-12-04  Richard Henderson  <rth@redhat.com>
+
+	* demangle.h: Change "new_abi" to "v3" everywhere.
+
+2000-11-22  Zack Weinberg  <zack@wolery.stanford.edu>
+
+	* libiberty.h: Move #includes to top.  Prototype xmalloc_failed.
+
+2000-11-15  Kenneth Block  <kenneth.block@compaq.com>
+
+	* demangle.h: Add gnat and java demangle styles.
+
+2000-11-04  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* hashtab.h (struct htab): Add member return_allocation_failure.
+	(htab_try_create): New prototype.  Mention which functions may
+	return NULL when this is used.
+
+2000-11-03  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* hashtab.h: Change void * to PTR where necessary.
+
+2000-10-11  Mark Mitchell  <mark@codesourcery.com>
+
+	* splay-tree.h (splay_tree_predecessor): Declare.
+
+2000-09-29  Hans-Peter Nilsson  <hp@axis.com>
+
+	* dis-asm.h: Declare cris_get_disassembler, not print_insn_cris.
+	Fix typo in comment.
+
+2000-09-28  John David Anglin <dave@hiauly1.hia.nrc.ca>
+
+	* alloca-conf.h: New file (copied from libiberty).
+
+2000-09-05  John David Anglin <dave@hiauly1.hia.nrc.ca>
+
+	* md5.h (md5_uint32): Choose via INT_MAX instead of UINT_MAX.
+
+2000-09-04  Alex Samuel  <samuel@codesourcery.com>
+
+	* dyn-string.h: Adjust formatting.
+	(dyn_string_insert_char): New macro.  New declaration.
+
+2000-08-28  Jason Merrill  <jason@redhat.com>
+
+	* md5.h: New file.
+
+2000-08-24  Greg McGary  <greg@mcgary.org>
+
+	* libiberty.h (ARRAY_SIZE): New macro.
+
+2000-07-29  Nick Clifton  <nickc@cygnus.com>
+
+	* os9k.h: Add copyright notice.
+	Fix formatting.
+
+2000-07-22  Jason Eckhardt  <jle@cygnus.com>
+
+	* dis-asm.h (print_insn_i860): Add prototype.
+
+2000-07-20  H.J. Lu  <hjl@gnu.org>
+
+	* bfdlink.h (bfd_link_info): Add new_dtags.
+
+2000-07-20  Hans-Peter Nilsson  <hp@axis.com>
+
+	* dis-asm.h (print_insn_cris): Declare.
+
+2000-07-19  H.J. Lu  (hjl@gnu.org)
+
+	* bfdlink.h (bfd_link_info): Add flags and flags_1.
+
+2000-06-05  DJ Delorie  <dj@redhat.com>
+
+	* MAINTAINERS: new
+
+2000-06-21  Alex Samuel  <samuel@codesourcery.com>
+
+	* dyn-string.h (dyn_string_init, dyn_string_new,
+	dyn_string_delete, dyn_string_release, dyn_string_resize,
+	dyn_string_clear, dyn_string_copy, dyn_string_copy_cstr,
+	dyn_string_prepend, dyn_string_prepend_cstr, dyn_string_insert,
+	dyn_string_insert_cstr, dyn_string_append, dyn_string_append_cstr,
+	dyn_string_append_char, dyn_string_substring_dyn_string_eq):
+	Define as same name with __cxa_ prepended, if IN_LIBGCC2.
+	(dyn_string_init, dyn_string_copy, dyn_string_copy_cstr,
+	dyn_string_prepend, dyn_string_prepend_cstr, dyn_string_insert,
+	dyn_string_insert_cstr, dyn_string_append, dyn_string_append_cstr,
+	dyn_string_append_char, dyn_string_substring): Change return type
+	to int.
+
+2000-06-18  Stephane Carrez  <stcarrez@worldnet.fr>
+
+	* dis-asm.h (print_insn_m68hc12): Define.
+	(print_insn_m68hc11): Likewise.
+
+2000-06-18  Nick Clifton  <nickc@redhat.com>
+
+	* os9k.h: Change values of MODSYNC and CRCCON due to bug report
+	from Russ Magee <rmagee@home.com>.
+
+2000-06-07  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* demangle.h (demangling_styles): Remove trailing comma in enum.
+
+	* dyn-string.h (dyn_string_append_char): Change parameter from
+	char to int.
+
+2000-06-04  Alex Samuel  <samuel@codesourcery.com>
+
+	* dyn-string.h: Move here from gcc/dyn-string.h.  Add new functions.
+
+	* demangle.h (DMGL_GNU_NEW_ABI): New macro.
+	(DMGL_STYLE_MASK): Or in DMGL_GNU_NEW_ABI.
+	(current_demangling_style): Add gnu_new_abi_demangling.
+	(GNU_NEW_ABI_DEMANGLING_STYLE_STRING): New macro.
+	(GNU_NEW_ABI_DEMANGLING): Likewise.
+	(cplus_demangle_new_abi): New declaration.
+
+Tue May 30 16:53:34 2000  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* floatformat.h (struct floatformat): Add field name.
+
+2000-05-26  Eli Zaretskii  <eliz@is.elta.co.il>
+
+	* filenames.h: New file.
+	(HAVE_DOS_BASED_FILE_SYSTEM, IS_DIR_SEPARATOR)
+	(IS_ABSOLUTE_PATH, FILENAME_CMP): New macros.
+
+2000-05-23  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* getopt.h (getopt): Also check HAVE_DECL_* when prototyping.
+
+	* libiberty.h (basename): Likewise.
+
+2000-05-17  S. Bharadwaj Yadavalli  <sby@scrugs.lkg.dec.com>
+	    Rick Gorton             <gorton@scrugs.lkg.dec.com>
+
+	* bfdlink.h (struct bfd_link_info): Add emitrelocations flag.
+
+2000-05-08  Alan Modra  <alan@linuxcare.com.au>
+
+	* dis-asm.h (print_insn_tic54x): Declare.
+
+2000-05-06  Zack Weinberg  <zack@wolery.cumb.org>
+
+	* ansidecl.h: #define __extension__ to nothing if
+	GCC_VERSION < 2008.
+
+2000-05-04  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* demangle.h (demangler_engine): Constify.
+
+Thu May  4 17:15:26 2000  Philippe De Muyter  <phdm@macqel.be>
+
+	* sort.h (sys/types.h): File included unconditionnaly.
+	(stddef.h): File include only #ifdef __STDC__.
+
+2000-05-03  Zack Weinberg  <zack@wolery.cumb.org>
+
+	* symcat.h: Remove #endif label.
+
+2000-04-28  Kenneth Block  <block@zk3.dec.com>
+	    Jason Merrill  <jason@casey.cygnus.com>
+
+	* demangle.h (libiberty_demanglers): new table for different styles.
+	(cplus_demangle_set_style): New function for setting style.
+	(cplus_demangle_name_to_style): New function to translate name.
+
+2000-04-24  Mark Mitchell  <mark@codesourcery.com>
+
+	* hashtab.h (hash_pointer): Declare.
+	(eq_pointer): Likewise.
+
+2000-04-23  Mark Mitchell  <mark@codesourcery.com>
+
+	* sort.h: New file.
+
+Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
+			  David Mosberger  <davidm@hpl.hp.com>
+
+	* dis-asm.h (print_insn_ia64): Declare.
+
+Tue Apr 18 16:22:30 2000  Richard Kenner  <kenner@vlsi1.ultra.nyu.edu>
+
+	* hashtab.h (enum insert_option): New type.
+	(htab_find_slot, htab_find_slot_with_hash): Use it.
+
+2000-04-17  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* symcat.h: Honor autoconf macro HAVE_STRINGIZE.  Add
+	comments/caveats with regard to traditional C behavior.
+
+2000-04-05  Richard Henderson  <rth@cygnus.com>
+
+	* splay-tree.h (splay_tree_remove): Declare.
+
+2000-04-04  Alan Modra  <alan@linuxcare.com.au>
+
+	* bin-bugs.h (REPORT_BUGS_TO): Remove translated part.
+
+2000-04-03  Alan Modra  <alan@linuxcare.com.au>
+
+	* bin-bugs.h: New file.
+
+2000-03-30  Mark Mitchell  <mark@codesourcery.com>
+
+	* hashtab.h (hashval_t): New type.
+	(htab_find_with_hash): Use it as an argument.
+	(htab_find_slot_with_hash): Likewise.
+
+2000-03-27  Denis Chertykov  <denisc@overta.ru>
+
+	* dis-asm.h (print_insn_avr): Declare.
+
+2000-03-14  Bernd Schmidt  <bernds@cygnus.co.uk>
+
+	* hashtab.h (htab_trav): Modify type so that first arg is of type
+	void **.
+	(htab_find_with_hash, htab_find_slot_with_hash): Declare new
+	functions.
+
+2000-03-09  Alex Samuel  <samuel@codesourcery.com>
+
+	* partition.h: New file.
+
+2000-03-09  Zack Weinberg  <zack@wolery.cumb.org>
+
+	* hashtab.h (struct htab): Add del_f.
+	(htab_del): New type.
+	(htab_create): Add fourth argument.
+
+2000-03-08  Zack Weinberg  <zack@wolery.cumb.org>
+
+	* hashtab.h (hash_table_t): Rename to htab_t.
+	(struct hash_table): Rename to struct htab.  Shorten element
+	names.  Reorder elements by size.
+	(htab_hash, htab_eq, htab_trav): New typedefs for the callback
+	function pointers.
+	(hash_table_entry_t): Discard; just use void * for element
+	type.
+
+2000-03-01  H.J. Lu  <hjl@gnu.org>
+
+	* bfdlink.h (bfd_link_callbacks): Add a boolean arg to
+	the undefined_symbol callback.
+
+2000-02-23  Linas Vepstas <linas@linas.org>
+
+	* dis-asm.h (print_insn_i370): Declare.
+
+Tue Feb 22 15:19:54 2000  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_trace): Document return values.
+	(sim_set_trace): Declare.  Deprecate.
+
+2000-02-21  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* dis-asm.h (struct disassemble_info): Change `length' param of
+	read_memory_func to unsigned.  Change type of `buffer_length' and
+	`octets_per_byte' to unsigned.
+	(buffer_read_memory): Change `length' param to unsigned.
+
+2000-02-16  Nick Clifton  <nickc@cygnus.com>
+
+	* dis-asm.h: Add prototypes for ARM register name functions.
+
+Wed Feb  9 18:45:49 2000  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* wait.h: Delete. No longer used by GDB.
+
+Tue Feb  8 17:01:13 2000  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_resume): Clarify use of SIGGNAL.
+	(sim_stop_reason): Clarify meaning of sim_signalled.
+
+2000-02-03  Timothy Wall <twall@redhat.com>
+
+	* dis-asm.h (struct disassemble_info): Added octets_per_byte
+	field and initialize it to one (1).
+
+2000-01-27  Nick Clifton  <nickc@redhat.com>
+
+	* dis-asm.h: Add prototype for disassembler_usage().
+	Add prototype for arm_disassembler_options().
+	Remove prototype for arm_toggle_regnames().
+	Add prototype for parse_arm_disassembler_option().
+
+Sat Jan  1 19:06:52 2000  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* symcat.h (STRINGX) [!__STDC__ || ALMOST_STDC]: Change "?" to "s"
+	to stringify argument s.
+
+Wed Dec 15 11:22:56 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hp-symtab.h (HP_LANGUAGE_FORTRAN): New enumeration constant.
+	(HP_LANGUAGE_F77): Define using HP_LANGUAGE_FORTRAN.
+
+1999-12-15  Doug Evans  <dje@transmeta.com>
+
+	* dis-asm.h: Enclose in extern "C" ifdef __cplusplus.
+
+1999-12-05  Mark Mitchell  <mark@codesourcery.com>
+
+	* splay-tree.h (struct splay_tree_node): Rename to ...
+	(struct splay_tree_node_s): ... this.
+	(struct splay_tree): Rename to ...
+	(struct splay_tree_s): ... this.
+
+1999-11-30  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* ansidecl.h (ATTRIBUTE_MALLOC): New macro.
+
+	* libiberty.h (buildargv, dupargv, concat, choose_temp_base,
+	make_temp_file, xmalloc, xcalloc, xstrdup, xmemdup): Add
+	ATTRIBUTE_MALLOC.
+	(xatexit): Remove __GNUC__ check, add ATTRIBUTE_NORETURN.
+
+1999-11-28  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h: Include stdarg.h when ANSI_PROTOTYPES is defined.
+	(asprintf, vasprintf): Provide declarations.
+
+Wed Nov 10 12:43:21 1999  Philippe De Muyter  <phdm@macqel.be>
+			  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* ansidecl.h: Define and test `GCC_VERSION', not `HAVE_GCC_VERSION'.
+
+1999-11-04      Jimmy Guo       <guo@cup.hp.com>
+
+	* hp-symtab.h (dntt_type_fparam): Add doc_ranges, misc_kind
+	fields, change location type to CORE_ADDR from int.
+	(dntt_type_const): Name the 5th field location_type.
+
+Sun Oct 24 19:11:32 1999  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* sim-d10v.h (SIM_D10V_TS2_DMAP_REGNUM): Define.
+
+1999-10-23 08:51 -0700  Zack Weinberg  <zack@bitmover.com>
+
+	* hashtab.h: Give hash_table_t a struct tag.  Add prototypes
+	for clear_hash_table_slot and traverse_hash_table.  Correct
+	prototype of all_hash_table_collisions.
+
+Sat Oct 23 19:00:13 1999  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* sim-d10v.h: New file.
+
+Fri Oct 15 01:47:51 1999  Vladimir Makarov  <vmakarov@loony.cygnus.com>
+
+	* hashtab.h: New file.
+
+1999-10-10  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* ansidecl.h (HAVE_GCC_VERSION): New macro.  Use it instead of
+	explicitly testing __GNUC__ and __GNUC_MINOR__.
+
+	(ATTRIBUTE_PRINTF): Use `__format__', not `format'.
+
+1999-09-25  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (make_temp_file):  Add a prototype.
+
+Tue Sep 14 00:35:02 1999  Marc Espie <espie@cvs.openbsd.org>
+
+	* libiberty.h (basename):  OpenBSD has a correct prototype.
+	(xrealloc):  Remove outdated comment.
+
+1999-09-07  Jeff Garzik  <jgarzik@pobox.com>
+
+	* libiberty.h (xmemdup): Add prototype for new function.
+
+1999-09-04  Steve Chamberlain  <sac@pobox.com>
+
+	* dis-asm.h (print_insn_pj): Declare.
+
+1999-09-01  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* obstack.h (obstack_grow, obstack_grow0): Move (char*) casts
+	in calls to `_obstack_memcpy' from here ...
+
+	(_obstack_memcpy): ... to here, except in the __STDC__ case which
+	doesn't need it.
+
+1999-08-30  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h (getpwd): Prototype.
+
+1999-08-01  Mark Mitchell  <mark@codesourcery.com>
+
+	* splay-tree.h (splay_tree_insert): Return the new node.
+
+1999-07-11  Ian Lance Taylor  <ian@zembu.com>
+
+	* ansidecl.h: Copy attribute support macros from egcs.
+
+1999-06-22  Mark Mitchell  <mark@codesourcery.com>
+
+	* bfdlink.h (struct bfd_link_hash_entry): Add init_function and
+	fini_function.
+
+1999-06-20  Mark Mitchell  <mark@codesourcery.com>
+
+	* mips.h (Elf32_Internal_Msym): New structure.
+	(Elf32_External_Msym): Likewise.
+	(ELF32_MS_REL_INDEX): New macro.
+	(ELF32_MS_FLAGS): Likewise.
+	(ELF32_MS_INFO): Likewise.
+
+1999-06-14  Nick Clifton  <nickc@cygnus.com>
+
+	* dis-asm.h (arm_toggle_regnames): New prototype.
+	(struct diassemble_info): New field: disassembler_options.
+
+1999-04-11  Richard Henderson  <rth@cygnus.com>
+
+	* bfdlink.h (bfd_elf_version_expr): Rename `match' to `pattern'.
+	Add `match' callback function.
+
+1999-04-10  Richard Henderson  <rth@cygnus.com>
+
+	* bfdlink.h (bfd_link_info): Add no_undefined.
+
+1999-04-08  Nick Clifton  <nickc@cygnus.com>
+
+	* dis-asm.h: Add prototype for print_insn_mcore.
+
+1999-04-02  Mark Mitchell  <mark@codesourcery.com>
+
+	* splay-tree.h (splay_tree_compare_pointers): Declare.
+
+1999-03-30  Mark Mitchell  <mark@codesourcery.com>
+
+	* splay-tree.h (splay_tree_compare_ints): Declare.
+
+Wed Mar 24 12:46:29 1999  Andrew Cagney  <cagney@amy.cygnus.com>
+
+	* libiberty.h (basename): Cygwin{,32} should have the prototype.
+
+1999-02-22  Jim Lemke  <jlemke@cygnus.com>
+
+	* bfdlink.h (bfd_link_info): add field "mpc860c0".
+
+Mon Feb  1 21:05:46 1999  Catherine Moore  <clm@cygnus.com>
+
+	* dis-asm.h (print_insn_i386_att):  Declare.
+	(print_insn_i386_intel):  Declare.
+
+1998-12-30  Michael Meissner  <meissner@cygnus.com>
+
+	* dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Cast STREAM and
+	FPRINTF_FUNC to avoid compiler warnings.
+
+Wed Dec 30 16:07:14 1998  David Taylor  <taylor@texas.cygnus.com>
+
+	* dis-asm.h: change void * to PTR (two places).
+
+Mon Dec 14 09:53:31 1998  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* demangle.h: Don't check IN_GCC anymore.
+	* splay-tree.h: Likewise.
+
+Tue Dec  8 00:30:31 1998  Elena Zannoni  <ezannoni@kwikemart.cygnus.com>
+
+	The following changes were made by Elena Zannoni
+	<ezannoni@kwikemart.cygnus.com> and Edith Epstein
+	<eepstein@sophia.cygnus.com> as part of a project to merge in
+	changes made by HP; HP did not create ChangeLog entries.
+
+	* dis-asm.h (struct disassemble_info): change the type of stream
+	from FILE* to void*, for use with gdb's new type GDB_FILE.
+	(fprintf_ftype): change FILE* parameter type to void*.
+
+	* demangle.h: (DMGL_EDG): new macro for Kuck and Associates
+	(DMGL_STYLE_MASK): modify to include Kuck and Assoc style
+	(demangling_styles): add new edg_demangling style
+	(EDG_DEMANGLING_STYLE_STRING): new macro
+	(EDG_DEMANGLING): new macro
+	(DMGL_HP): new macro, for HP/aCC compiler.
+	(DMGL_STYLE_MASK): modify to include new HP's style.
+	(demangling_styles): add new hp_demangling value.
+	(HP_DEMANGLING_STYLE_STRING): new macro.
+	(ARM_DEMANGLING): coerce to int.
+	(HP_DEMANGLING): new macro.
+
+	* hp-symtab.h: rewritten, from HP.
+	(quick_procedure): change type of language field to unsigned int
+	(quick_module): change type of language field to unsigned int
+	(struct dntt_type_svar): add field thread_specific.
+	(hp_language): add languages modcal and dmpascal.
+
+Fri Nov 20 13:14:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* libiberty.h (basename): Add prototype for FreeBSD.
+
+Fri Nov 13 19:19:11 1998  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* libiberty.h: Prototype xcalloc.
+
+Sun Nov  8 17:42:25 1998  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* ansidecl.h: Wrap problematic macros with !IN_GCC.
+
+	* demangle.h: Never define PARAMS().
+	* splay-tree.h: Likewise.
+
+Sat Nov  7 18:30:20 1998  Peter Schauer  <peter.schauer@regent.e-technik.tu-muenchen.de>
+
+	* dis-asm.h (print_insn_vax): Declare.
+
+Sat Nov  7 16:04:03 1998  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* demangle.h: Don't include gansidecl.h.
+	* splay-tree.h: Likewise.
+
+1998-10-26 16:03  Ulrich Drepper  <drepper@cygnus.com>
+
+	* bfdlink.h (struct bfd_link_info): Add new field optimize.
+
+Thu Oct 22 19:58:00 1998  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* splay-tree.h: Wrap function pointer parameter declarations in
+	PARAMS() macro.
+
+1998-10-21  Mark Mitchell  <mark@markmitchell.com>
+
+	* splay-tree.h: New file.
+
+Fri Oct  9 00:02:03 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* Merge devo and egcs include directories.
+
+Sat Sep  5 12:16:33 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* getopt.h, obstack.h: Updated from gcc.
+
+1998-08-03  Jason Molenda  (jsm@bugshack.cygnus.com)
+
+	* libiberty.h (xexit): Change decl to use modern GCC attribute
+	to indicate exit does not return.
+
+Mon Jun  1 13:48:32 1998  Jason Molenda  (crash@bugshack.cygnus.com)
+
+	* obstack.h: Update to latest FSF version.
+
+Tue Feb 24 13:05:02 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* dis-asm.h (disassemble_info): Member `symbol' renamed to `symbols'
+	and made an "asymbol **".  New member num_symbols.
+	(INIT_DISASSEMBLE_INFO_NO_ARCH): Update.
+
+Tue Feb 17 12:32:18 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_fetch_register, sim_store_register): Add
+	register length parameter.  Functions return actual length of
+	register.
+
+Thu Feb 12 16:29:01 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* getopt.h: Update to latest FSF version.
+
+Wed Feb 11 16:56:06 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* symcat.h: New file.
+
+Mon Feb  2 17:13:31 1998  Steve Haworth  <steve@pm.cse.rmit.EDU.AU>
+
+	* dis-asm.h (print_insn_tic30): Declare.
+
+Thu Jan 22 16:23:59 1998  Fred Fish <fnf@cygnus.com>
+
+	* dis-asm.h: Add flag INSN_HAS_RELOC to tell disassembly
+	function there is a reloc on this line.
+
+Mon Dec  8 11:22:23 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* dis-asm.h: Remove prototype of disasm_symaddr() as this function
+	no longer exists.
+
+Tue Dec  2 10:20:53 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* dis-asm.h (disasm_symaddr): New prototype.
+
+Mon Dec  1 11:29:35 1997  Doug Evans  <devans@canuck.cygnus.com>
+
+	* callback.h (CB_SYSCALL): Comment out arg names in prototypes.
+
+Wed Nov 26 16:47:58 1997  Michael Meissner  <meissner@cygnus.com>
+
+	* callback.h (CB_SYSCALL): Consistantly use names for prototype
+	arguments.
+
+Wed Nov 26 11:39:30 1997  Doug Evans  <devans@canuck.cygnus.com>
+
+	* callback.h (CB_SYSCALL): Change byte count arguments to
+	{read,write}_mem to `int'.  New member `magic'.
+	(CB_SYSCALL_MAGIC,CB_SYSCALL_INIT): New macros.
+
+Tue Nov 25 01:35:52 1997  Doug Evans  <devans@seba.cygnus.com>
+
+	* callback.h (struct stat): Move forward decl up.
+	(host_callback): Pass stat struct pointer to stat,fstat.
+	(CB_SYS_nnn): Reorganize.
+	(CB_SYSCALL): New members p1,p2.
+	(cb_host_to_target_stat): Delete fourth arg.
+
+Sat Nov 22 23:34:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_stop_reason): Clarify sim_signalled SIGRC
+	argument.
+
+Mon Nov 17 14:00:51 1997  Doug Evans  <devans@seba.cygnus.com>
+
+	* callback.h (CB_TARGET_DEFS_MAP): Renamed from target_defs_map.
+	(host_callback): Add stat, fstat, syscall_map, errno_map, open_map,
+	signal_map, stat_map.
+	(errn_map,open_map): Renamed to cb_init_foo_map.
+	(cb_host_to_target_errno,cb_target_to_host_open): Renamed from
+	host_to_target_errno,target_to_host_open.
+	(cb_read_target_syscall_maps): Add prototype.
+	(cb_target_to_host_syscall): Likewise.
+	(cb_host_to_target_stat): Likewise.
+	(cb_syscall): Likewise.
+	(CB_SYS_{exit,open,close,read,write,lseek,unlink,getpid,kill,fstat,
+	argvlen,argv,chdir,stat,chmod,utime,time}): Define.
+	(CB_SYSCALL): New type.
+	(CB_RC): New enum.
+
+Fri Nov  7 10:34:09 1997  Rob Savoye  <rob@darkstar.cygnus.com>
+
+	* libiberty.h: Add extern "C" { so it can be used with C++
+	programs.
+	* remote-sim.h:  Add extern "C" { so it can be used with C++
+	programs.
+
+Tue Oct 14 16:07:51 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* dis-asm.h (struct disassemble_info): New field
+	'symbol_at_address_func'.
+	(INIT_DISASSEMBLE_INFO_NO_ARCH): Initialise new field with
+	generic_symbol_at_address.
+
+Mon Oct 13 10:17:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h: Clarify sim_read, sim_write MEM argument.
+
+Wed Sep 24 18:03:10 1997  Stu Grossman  <grossman@babylon-5.cygnus.com>
+
+	* remote-sim.h (SIM_RC):  Add a bunch of new return codes for
+	breakpoint stuff.
+	* Add functions to tell the simulator to set/clear/enable/disable
+	intrinsic breakpoints.
+
+Thu Aug 28 19:41:42 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* libiberty.h (dupargv): Add prototype.
+
+Tue Aug 26 12:25:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_create_inferior): Add ABFD arg. Document.
+
+Mon Aug 25 10:50:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_open): Add ABFD arg. Document.
+
+Fri Aug  8 16:43:56 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* dis-asm.h (arc_get_disassembler): Declare.
+
+Wed Jul 30 11:39:50 1997  Per Bothner  <bothner@deneb.cygnus.com>
+
+	* demangle.h (DMGL_JAVA):  New option to request Java demangling.
+
+Tue Jul 22 17:59:54 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* libiberty.h (PEXECUTE_*): Define.
+	(pexecute, pwait): Declare.
+
+Fri Jun  6 13:02:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_kill): Mark as depreciated.
+
+Fri May 23 13:43:41 1997  Fred Fish  <fnf@cygnus.com>
+
+	* bfdlink.h (struct bfd_link_info): Add task_link member.
+
+Thu May 22 11:32:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h: Review documentation.  Clarify restrictions on
+	when functions can be called.
+
+Wed May 21 16:47:53 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_set_profile_size): Add prototype, document as
+	depreciated.
+
+Tue May 20 09:32:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_open): Add callback struct.
+	(sim_set_callbacks): Drop SIM_DESC argument. Document.
+	(sim_size): Remove recently added SIM_DESC argument. Document.
+
+Mon May 19 19:14:44 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h: Pass SD into sim_size.
+
+Thu May 15 01:24:16 1997  Mark Alexander  <marka@cygnus.com>
+
+	* obstack.h (obstack_specify_allocation_with_arg, obstack_chunkfun,
+	obstack_freefun): Eliminate compile warnings in gdb.
+
+Tue Apr 22 10:24:34 1997  Fred Fish  <fnf@cygnus.com>
+
+	* floatformat.h (floatformat_byteorders): Add comments for previous
+	formats and add floatformat_littlebyte_bigword, primarily for ARM.
+	Add declaration for floatformat_ieee_double_littlebyte_bigword.
+
+Fri Apr 18 13:04:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_stop): New interface - asynchronous
+	notification of a request to stop / suspend the running
+	simulation.
+
+	* remote-sim.h (enum sim_stop): Add sim_running and sim_polling as
+	states for use internal to simulators.
+
+	* callback.h (struct host_callback_strut): Put a magic number at
+	the end of the struct to allow basic checking.
+	(struct host_callback_struct ): Add poll_quit - so
+	that the console etc can be polled at regular intervals.
+
+Thu Apr 17 02:17:12 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* remote-sim.h (struct _bfd): Declare.
+	(sim_load): Return SIM_RC.  New arg `abfd'.
+	(sim_create_inferior): Return SIM_RC.  Delete arg `start_address'.
+
+Wed Apr  2 17:09:12 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
+
+	* remote-sim.h (sim_trace, sim_size): Make these global.  They
+	will go away shortly.
+
+Wed Apr  2 15:23:49 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* remote-sim.h (SIM_OPEN_KIND, SIM_RC): New enums.
+	(sim_open): New argument `kind'.
+
+Wed Apr  2 14:45:51 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* COPYING: Update FSF address.
+
+Fri Mar 28 15:29:54 1997  Mike Meissner  <meissner@cygnus.com>
+
+	* callback.h (top level): Include stdarg.h or varargs.h if
+	va_start is not defined.
+	(host_callback_struct): Make {,e}vprintf_filtered take a va_list
+	instead of void *, since va_list might be an array or structure
+	type.
+
+Fri Mar 28 15:44:41 1997  H.J. Lu  <hjl@gnu.ai.mit.edu>
+
+	* libiberty.h (basename): Add prototype for glibc and linux.
+
+Mon Mar 17 19:22:12 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* objalloc.h: New file.
+
+Mon Mar 17 14:57:55 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
+
+	* remote-sim.h: New file, copied in from gdb/remote-sim.h.  One
+	day this will be placed in a directory of its own.
+
+Sat Mar 15 19:00:14 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* obstack.h: Update to current FSF version.
+
+Thu Mar  6 15:46:59 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
+
+	* callback.h (struct host_callback_struct): Add callbacks -
+	flush_stdout, write_stderr, flush_stderr, vprintf_filtered,
+	evprintf_filtered.  Delete redundant callbacks - printf_filtered.
+
+Thu Feb 27 23:18:27 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* bfdlink.h (struct bfd_link_info): Remove lprefix and lprefix_len
+	fields.
+
+Tue Feb 25 00:10:49 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize
+	bytes_per_chunk and display_endian.
+
+Mon Feb 24 17:47:02 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	From Eric Youngdale <eric@andante.jic.com>:
+	* bfdlink.h (struct bfd_elf_version_expr): Define.
+	(struct bfd_elf_version_deps): Define.
+	(struct bfd_elf_version_tree): Define.
+
+Thu Feb  6 14:20:01 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* dis-asm.h: (disassemble_info):  Add new fields
+	bytes_per_chunk and display_endian to control the
+	display of raw instructions.
+
+Fri Dec 27 22:17:37 1996  Fred Fish  <fnf@cygnus.com>
+
+	* dis-asm.h (print_insn_tic80): Declare.
+
+Sun Dec  8 17:11:12 1996  Doug Evans  <dje@canuck.cygnus.com>
+
+	* callback.h (host_callback): New member `error'.
+
+Wed Nov 20 00:40:23 1996  Doug Evans  <dje@canuck.cygnus.com>
+
+	* callback.h: New file, moved here from gdb.
+
+Mon Nov 18 16:34:00 1996  Dawn Perchik  <dawn@critters.cygnus.com>
+
+	* libiberty.h: Checkin again; last checkin failed due to sticky tag.
+
+Wed Nov 13 08:22:00 1996  Dawn Perchik  <dawn@critters.cygnus.com>
+
+	* libiberty.h: Revert last commit due to conflicts with hpux
+	system headers.
+
+Tue Nov 12 16:31:00 1996  Dawn Perchik  <dawn@critters.cygnus.com>
+
+	* libiberty.h: Move prototypes from argv.c here.
+
+Thu Oct 31 14:56:18 1996  Doug Evans  <dje@canuck.cygnus.com>
+
+	* ansidecl.h (VPARAMS,VA_START): Define.
+
+Fri Oct 25 12:08:04 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* dis-asm.h (disassemble_info): Add bytes_per_line field.
+	(INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize bytes_per_line field.
+
+Thu Oct 24 17:10:01 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* dis-asm.h (disassemble_info): Add symbol field.
+	(INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize symbol field.
+
+Thu Oct 17 11:17:40 1996  Doug Evans  <dje@canuck.cygnus.com>
+
+	* dis-asm.h (print_insn_m32r): Declare.
+
+Mon Oct 14 23:56:52 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* libiberty.h: Declare parameter types for xmalloc and xrealloc.
+
+Thu Oct  3 13:45:27 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* fnmatch.h: New file.
+
+Thu Oct  3 10:33:14 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* dis-asm.h (print_insn_mn10x00): Delete declaration.
+	(print_insn_mn10200, print_insn_mn10300): Declare.
+
+Wed Oct  2 21:24:43 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* dis-asm.h (print_insn_mn10x00): Declare.
+
+Mon Sep 30 13:56:11 1996  Fred Fish  <fnf@cygnus.com>
+
+	* libiberty.h: Remove #ifndef PRIVATE_XMALLOC.
+
+Sat Aug 31 13:27:06 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* dis-asm.h (print_insn_v850): Declare.
+
+Tue Aug 13 16:10:30 1996  Stu Grossman  (grossman@critters.cygnus.com)
+
+	* obstack.h:  Change bcopy to memcpy.  Works better on Posix
+	systems, which generally lack bcopy.
+
+Mon Aug 12 17:03:18 1996  Stu Grossman  (grossman@critters.cygnus.com)
+
+	* ansidecl.h:  Change WIN32 to _WIN32.
+
+Fri Jul 26 13:58:18 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* dis-asm.h: Add flavour field.
+	(print_insn_alpha): Declare.
+	(print_insn_alpha_osf, print_insn_alpha_vms): Don't declare.
+	(INIT_DISASSEMBLE_INFO): Initialize flavour field.
+
+Tue Jul 23 17:37:58 1996  Fred Fish  <fnf@cygnus.com>
+
+	* libiberty.h (PRIVATE_XMALLOC): Enclose xmalloc/xrealloc
+	definitions inside #ifndef so that programs that want to
+	can define PRIVATE_XMALLOC and then define xmalloc and
+	xrealloc anyway they want.
+	(basename): Document in source that we can't declare the
+	parameter type because it is declared inconsistently across
+	different systems.
+
+Mon Jul 22 13:16:13 1996  Richard Henderson  <rth@tamu.edu>
+
+	* dis-asm.h (print_insn_alpha): Don't declare.
+	(print_insn_alpha_osf, print_insn_alpha_vms): Declare.
+
+Wed Jul 17 14:45:12 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* dis-asm.h: (print_insn_d10v): Declare.
+
+Mon Jul 15 16:55:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
+
+	* dis-asm.h:  Get rid of decls for print_insn_i8086,
+	print_insn_sparc64 and print_insn_sparclite.
+	* (INIT_DISASSEMBLE_INFO):  Split into two pieces.  One,
+	INIT_DISASSEMBLE_INFO_NO_ARCH inits everything except for endian,
+	mach, and arch.
+
+Fri Jul 12 10:19:27 1996  Stu Grossman  (grossman@critters.cygnus.com)
+
+	* dis-asm.h (print_insn_i8086):  Declare.
+
+Wed Jul  3 16:02:39 1996  Stu Grossman  (grossman@critters.cygnus.com)
+
+	* dis-asm.h (print_insn_sparclite):  Declare.
+
+Tue Jun 18 16:02:46 1996  Jeffrey A. Law  <law@rtl.cygnus.com>
+
+	* dis-asm.h (print_insn_h8300s): Declare.
+
+Tue Jun 18 15:11:33 1996  Klaus Kaempf  <kkaempf@progis.de>
+
+	* fopen-vms.h: New file.
+
+Tue Jun  4 18:58:16 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* bfdlink.h (struct bfd_link_info): Add notice_all field.
+
+Fri Apr 26 10:33:12 1996  Doug Evans  <dje@canuck.cygnus.com>
+
+	* demangle.h (#ifdef IN_GCC): #include "gansidecl.h".
+	(PROTO,PTR,const): Delete.
+
+Mon Apr 22 17:27:42 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* bfdlink.h (struct bfd_link_info): Add traditional_format field.
+
+Mon Apr 15 15:16:56 1996  Doug Evans  <dje@canuck.cygnus.com>
+
+	* libiberty.h (choose_temp_base): Add prototype.
+
+Tue Mar 12 17:29:46 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* bfdlink.h (bfd_wrapped_link_hash_lookup): Declare.
+	(struct bfd_link_info): Add wrap_hash field.
+
+Wed Feb 14 16:49:17 1996  Martin Anantharaman  <martin@mail.imech.uni-duisburg.de>
+
+	* ieee.h (ieee_record_enum_type): Define
+	ieee_external_reference_info_enum.
+
+Fri Feb  2 17:09:25 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+	* dis-asm.h (DISASM_RAW_INSN): Delete.
+
+Tue Jan 23 09:21:47 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+	* dis-asm.h (INIT_DISASSEMBLE_INFO): Set endian to BFD_ENDIAN_UNKNOWN.
+	New argument FPRINTF_FUNC.
+
+Mon Jan 22 16:37:59 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+	* dis-asm.h (disassemble_info): New members arch, mach, endian.
+	(INIT_DISASSEMBLE_INFO): Initialize them.
+	(DISASM_RAW_INSN{,FLAG}): Define.
+
+Thu Jan 18 11:32:38 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* demangle.h (cplus_demangle_opname): Change opname parameter to
+	const char *.
+	(cplus_mangle_opname): Change return type and opname parameter to
+	const char *.
+
+Fri Jan  5 00:01:22 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ieee.h (enum ieee_record): Add ieee_asn_record_enum,
+	ieee_at_record_enum, ieee_ty_record_enum, ieee_atn_record_enum,
+	ieee_bb_record_enum, and ieee_be_record_enum.
+
+Wed Jan  3 13:12:09 1996  Fred Fish  <fnf@cygnus.com>
+
+	* obstack.h: Update copyright to 1996.
+	(_obstack_memory_used): Declare.
+	(obstack_memory_used): Define macro.
+
+Thu Dec 28 11:42:12 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* libiberty.h (xstrdup): Declare.
+
+Thu Dec 21 14:47:17 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* wait.h: Protect all macros with #ifndef.
+
+Tue Oct 24 21:45:40 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* bfdlink.h (struct bfd_link_info): Add static_link field.
+
+Tue Sep 12 16:28:04 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* bfdlink.h (struct bfd_link_callbacks): Add symbol parameter to
+	warning callback.
+
+Fri Sep  1 13:11:51 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* bfdlink.h (struct bfd_link_callbacks): Change warning callback
+	to take BFD, section, and address arguments.
+
+Thu Aug 31 16:45:12 1995  steve chamberlain  <sac@slash.cygnus.com>
+
+	* bfdlink.h (struct bfd_link_info): Remove PE stuff.
+
+Tue Aug 22 03:18:23 1995  Ken Raeburn  <raeburn@kr-laptop.cygnus.com>
+
+	* libiberty.h: Declare xstrerror.  From Pat Rankin.
+
+Mon Aug 21 18:11:36 1995  steve chamberlain  <sac@slash.cygnus.com>
+
+	* bfdlink.h (struct bfd_link_info): Remove PE stuff.
+
+Wed Aug  2 08:14:12 1995  Doug Evans  <dje@canuck.cygnus.com>
+
+	* dis-asm.h (print_insn_sparc64): Declare.
+
+Mon Jul 10 13:26:49 1995  Eric Youngdale  <eric@aib.com>
+
+	* bfdlink.h (struct bfd_link_info): Add new field symbolic.
+
+Sun Jul  2 17:48:40 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* bfdlink.h (struct bfd_link_info): Change type of base_file to
+	PTR.
+
+Thu Jun 29 00:02:45 1995  Steve Chamberlain  <sac@slash.cygnus.com>
+
+	* bfdlink.h (struct bfd_link_info): Added base_file member.
+
+Tue Jun 20 16:40:04 1995  Steve Chamberlain  <sac@slash.cygnus.com>
+
+	* ansidecl.h: win32s is ANSI enough.
+
+Thu May 18 04:25:50 1995  Ken Raeburn  <raeburn@kr-laptop.cygnus.com>
+
+	Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk)
+
+	* dis-asm.h (print_insn_arm): Delete declaration.
+	(print_insn_{little,big}_arm): New declarations.
+
+	* floatformat.h (floatformat_arm_ext): Declare.
+
+Sat May 13 10:14:08 1995  Steve Chamberlain  <sac@slash.cygnus.com>
+
+	* bfdlink.h (subsytem, stack_heap_parameters): New.
+
+Thu May  4 14:36:42 1995  Jason Merrill  <jason@phydeaux.cygnus.com>
+
+	* demangle.h: Don't include ansidecl.h if IN_GCC.
+
+Tue Feb 21 00:37:28 1995  Jeff Law  (law@snake.cs.utah.edu)
+
+	* hp-symtab.h: Don't use bitfield enumerations, the HP C compiler
+	does not handle them correctly.
+
+Thu Feb  9 14:20:27 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* libiberty.h (basename): Don't declare parameter type; some
+	systems have this in their header files.
+
+Wed Feb  8 17:35:38 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* bfdlink.h (struct bfd_link_hash_entry): Change format of common
+	symbol information, to remove restrictions on maximum size and
+	alignment power, by using a pointer to a structure instead.
+
+Mon Feb  6 14:55:32 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* bfdlink.h (enum bfd_link_hash_type): Rename bfd_link_hash_weak
+	to bfd_link_hash_undefweak.  Add bfd_link_hash_defweak.
+
+Mon Jan 16 21:00:23 1995  Stan Shebs  <shebs@andros.cygnus.com>
+
+	* dis-asm.h (GDB_INIT_DISASSEMBLE_INFO, etc): Remove all
+	GDB-specific definitions.
+
+Sun Jan 15 18:39:35 1995  Steve Chamberlain  <sac@splat>
+
+	* dis-asm.h (print_insn_w65): Declare.
+
+Thu Jan 12 17:51:17 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	* libiberty.h (hex_p): Fix sense of test.
+
+Wed Jan 11 22:36:40 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	* libiberty.h (_hex_array_size, _hex_bad, _hex_value, hex_init,
+	hex_p, hex_value): New macros and declarations, for hex.c.
+
+Fri Jan  6 17:44:14 1995  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+
+	* dis-asm.h: Make idempotent.
+
+Wed Dec 14 13:08:43 1994  Stan Shebs  <shebs@andros.cygnus.com>
+
+	* progress.h: New file, empty definitions for progress macros.
+
+Fri Nov 25 00:14:05 1994  Jeff Law  (law@snake.cs.utah.edu)
+
+	* hp-symtab.h: New file describing the debug symbols emitted
+	by the HP C compilers.
+
+Fri Nov 11 15:48:37 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+
+	* bfdlink.h (struct bfd_link_hash_entry): Change u.c.size from 24
+	to 26 bits, and change u.c.alignment_power from 8 to 6 bits.  6
+	bit in the alignment power is enough for a 64 bit address space.
+
+Mon Oct 31 13:02:51 1994  Stan Shebs  (shebs@andros.cygnus.com)
+
+	* demangle.h (cplus_mangle_opname): Declare.
+
+Tue Oct 25 11:38:02 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+
+	* bfdlink.h (struct bfd_link_callbacks): Fix comments for
+	multiple_common field.
+
+Sun Sep 04 17:58:10 1994  Richard Earnshaw (rwe@pegasus.esprit.ec.org)
+
+	* dis-asm.h: Add support for the ARM.
+
+Wed Aug 10 12:51:41 1994  Doug Evans  (dje@canuck.cygnus.com)
+
+	* libiberty.h (strsignal): Document its existence even if we
+	can't declare it.
+
+Tue Aug  2 14:40:03 1994  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* os9k.h: Remove u_int16, u_int32, and owner_id typedefs and
+	expand their uses.  Those names conflict with Mach headers.
+
+Fri Jul 22 14:17:12 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
+
+	* bfdlink.h (struct bfd_link_hash_entry): Change u.c.size into a
+	bitfield.  Add field u.c.alignment_power.
+
+Sun Jul 10 00:26:39 1994  Ian Dall  (dall@hfrd.dsto.gov.au)
+
+	* dis-asm.h: Add print_insn_ns32k declaration.
+
+Mon Jun 20 17:13:29 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
+
+	* bfdlink.h (bfd_link_hash_table): Make creator a const pointer.
+
+Sat Jun 18 16:09:32 1994  Stan Shebs  (shebs@andros.cygnus.com)
+
+	* demangle.h (cplus_demangle_opname): Declare.
+
+Thu Jun 16 15:19:03 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* bfdlink.h (struct bfd_link_info): Add new field shared.
+
+Mon Jun  6 14:39:44 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* bfdlink.h (struct bfd_link_hash_entry): Remove written field:
+	not needed for all backends.
+
+Thu Apr 28 19:06:50 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* dis-asm.h (disassembler): Declare.
+
+Fri Apr  1 00:38:17 1994  Jim Wilson  (wilson@mole.gnu.ai.mit.edu)
+
+	* obstack.h: Delete use of IN_GCC to control whether
+	stddef.h or gstddef.h is included.
+
+Tue Mar 22 13:06:02 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* bfdlink.h (enum bfd_link_order_type): Add bfd_data_link_order.
+	(struct bfd_link_order): Add data field to union.
+
+Mon Mar 21 18:45:26 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* bfdlink.h (struct bfd_link_callbacks): Change bitsize argument
+	to add_to_set to reloc.  Remove bitsize argument from constructor.
+	Comment that reloc_overflow, reloc_dangerous and unattached_reloc
+	must handle NULL pointers for reloc location.
+	(enum bfd_link_order_type): Add bfd_section_reloc_link_order and
+	bfd_symbol_reloc_link_order.
+	(struct bfd_link_order): Add reloc field to union.
+	(struct bfd_link_order_reloc): Define.
+
+Mon Mar 14 12:27:50 1994  Ian Lance Taylor  (ian@cygnus.com)
+
+	* ieee-float.h: Removed; no longer used.
+
+Tue Mar  1 18:10:49 1994  Kung Hsu  (kung@mexican.cygnus.com)
+
+	* os9k.h: os9000 target specific header file, the header of the
+	object file is used now.
+
+Sun Feb 27 21:52:26 1994  Jim Kingdon  (kingdon@deneb.cygnus.com)
+
+	* floatformat.h: New file, intended to replace ieee-float.h.
+
+Sun Feb 20 17:15:42 1994  Ian Lance Taylor  (ian@lisa.cygnus.com)
+
+	* ansidecl.h (ANSI_PROTOTYPES): Define if using ANSI prototypes.
+
+Wed Feb 16 01:07:12 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* libiberty.h: Don't declare strsignal, to avoid conflicts with
+	Solaris system header files.
+
+Sat Feb 12 22:11:32 1994  Jeffrey A. Law  (law@snake.cs.utah.edu)
+
+	* libiberty.h (xexit): Use __volatile__ to avoid losing if
+	compiling with gcc -traditional.
+
+Thu Feb 10 14:05:41 1994  Ian Lance Taylor  (ian@cygnus.com)
+
+	* libiberty.h: New file.  Declares functions provided by
+	libiberty.
+
+Tue Feb  8 05:19:52 1994  David J. Mackenzie  (djm@thepub.cygnus.com)
+
+	Handle obstack_chunk_alloc returning NULL.  This allows
+	obstacks to be used by libraries, without forcing them
+	to call exit or longjmp.
+	* obstack.h (struct obstack): Add alloc_failed flag.
+	_obstack_begin, _obstack_begin_1): Declare to return int, not void.
+	(obstack_finish): If alloc_failed, return NULL.
+	(obstack_base, obstack_next_free, objstack_object_size):
+	If alloc_failed, return 0.
+	(obstack_grow, obstack_grow0, obstack_1grow, obstack_ptr_grow,
+	obstack_int_grow, obstack_blank): If alloc_failed, do nothing that
+	could corrupt the obstack.
+
+Mon Jan 24 15:06:05 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* bfdlink.h (struct bfd_link_callbacks): Add name, reloc_name and
+	addend argments to reloc_overflow callback.
+
+Fri Jan 21 19:13:12 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* dis-asm.h (print_insn_big_powerpc, print_insn_little_powerpc,
+	print_insn_rs6000): Declare.
+
+Thu Jan  6 14:15:55 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* bfdlink.h (struct bfd_link_callbacks): Add bitsize argument to
+	add_to_set field.  Add new callback named constructor.
+
+Thu Dec 30 10:44:06 1993  Ian Lance Taylor  (ian@rtl.cygnus.com)
+
+	* bfdlink.h: New file for new BFD linker backend routines.
+
+Mon Nov 29 10:43:57 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* dis-asm.h (enum dis_insn_tyupe): Remove non-ANSI trailing comma.
+
+Sat Oct  2 20:42:26 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* dis-asm.h: Move comment to right place.
+
+Mon Aug  9 19:03:35 1993  David J. Mackenzie  (djm@thepub.cygnus.com)
+
+	* obstack.h (obstack_chunkfun, obstack_freefun): Add defns from
+	previous version.  Are these Cygnus local changes?
+
+Fri Aug  6 17:05:47 1993  David J. Mackenzie  (djm@thepub.cygnus.com)
+
+	* getopt.h, obstack.h: Update to latest FSF version.
+
+Mon Aug  2 14:45:29 1993  John Gilmore  (gnu@cygnus.com)
+
+	* dis-asm.h:  Move enum outside of struct defn to avoid warnings.
+
+Mon Aug  2 08:49:30 1993  Stu Grossman  (grossman at cygnus.com)
+
+	* wait.h (WEXITSTATUS, WSTOPSIG): Mask down to 8 bits.  This is
+	for systems that store stuff into the high 16 bits of a wait
+	status.
+
+Fri Jul 30 18:38:02 1993  John Gilmore  (gnu@cygnus.com)
+
+	* dis-asm.h:  Add new fields insn_info_valid, branch_delay_insns,
+	data_size, insn_type, target, target2.  These are used to return
+	information from the instruction decoders back to the calling
+	program.  Add comments, make more readable.
+
+Mon Jul 19 22:14:14 1993  Fred Fish  (fnf@deneb.cygnus.com)
+
+	* nlm:  New directory containing NLM/NetWare includes.
+
+Thu Jul 15 12:10:04 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+
+	* dis-asm.h (struct disassemble_info): New field application_data.
+
+Thu Jul 15 12:41:15 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* dis-asm.h: Added declaration of print_insn_m88k.
+
+Fri Jul  2 10:31:59 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* ansidecl.h: Use ANSI macros if __mips and _SYSTYPE_SVR4 are
+	defined, since RISC/OS cc handles ANSI declarations in SVR4 mode
+	but does not define __STDC__.
+
+Sun Jun 20 18:27:52 1993  Ken Raeburn  (raeburn@poseidon.cygnus.com)
+
+	* dis-asm.h: Don't need to include ansidecl.h any more.
+
+Fri Jun 18 03:22:10 1993  John Gilmore  (gnu@cygnus.com)
+
+	* oasys.h:  Eliminate "int8_type", "int16_type", "int32_type", and
+	their variants.  These changes are coordinated with corresponding
+	changes in ../bfd/oasys.c.
+
+Wed Jun 16 10:43:08 1993  Fred Fish  (fnf@cygnus.com)
+
+	* bfd.h:  Note that it has been removed.
+
+Tue Jun  8 12:16:03 1993  Steve Chamberlain  (sac@phydeaux.cygnus.com)
+
+	 Support for H8/300-H
+	* dis-asm.h (print_insn_h8300, print_insn_h8300h): Declare it.
+
+Tue Jun  1 07:35:03 1993  Ken Raeburn  (raeburn@kr-pc.cygnus.com)
+
+	* ansidecl.h (const): Don't define it if it's already defined.
+
+Thu May 27 18:19:51 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+
+	* dis-asm.h (print_insn_hppa): Declare it.
+
+	* bfd.h: Moved to bfd directory.  Small stub here includes it
+	without requiring "-I../bfd".
+
+Thu Apr 29 12:06:13 1993  Ken Raeburn  (raeburn@deneb.cygnus.com)
+
+	* bfd.h: Updated with BSF_FUNCTION.
+
+Mon Apr 26 18:15:50 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* bfd.h, dis-asm.h: Updated with Hitachi SH.
+
+Fri Apr 23 18:41:38 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* bfd.h: Updated with alpha changes.
+	* dis-asm.h: Added alpha.
+
+Fri Apr 16 17:35:30 1993  Jim Kingdon  (kingdon@cygnus.com)
+
+	* bfd.h: Update for signed bfd_*get_*.
+
+Thu Apr 15 09:24:21 1993  Jim Kingdon  (kingdon@cygnus.com)
+
+	* bfd.h: Updated for file_truncated error.
+
+Thu Apr  8 10:53:47 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* ansidecl.h: If no ANSI, define const to be empty.
+
+Thu Apr  1 09:00:10 1993  Jim Kingdon  (kingdon@cygnus.com)
+
+	* dis-asm.h: Declare a29k and i960 print_insn_*.
+
+	* dis-asm.h: Add print_address_func and related stuff.
+
+	* dis-asm.h (dis_asm_read_memory): Fix prototype.
+
+Wed Mar 31 17:40:16 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* dis-asm.h: Add print_insn_sparc.
+
+Wed Mar 31 17:51:42 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* bfd.h: Updated for BFD_RELOC_MIPS_GPREL and bfd_[gs]et_gp_size
+	prototypes.
+
+Wed Mar 31 16:35:12 1993  Stu Grossman  (grossman@cygnus.com)
+
+	* dis-asm.h: (disassemble_info):  Fix typo in prototype of
+	dis_asm_memory_error().
+
+Tue Mar 30 19:09:23 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* dis-asm.h (disassembler_info): Add read_memory_func,
+	memory_error_func, buffer, and length.
+	({GDB_,}INIT_DISASSEMBLE_INFO): Set them.
+	print_insn_*: Remove second argument.
+
+Tue Mar 30 14:48:55 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* bfd.h: Update for lma field of section.
+
+Tue Mar 30 12:22:55 1993  Jim Kingdon  (kingdon@cygnus.com)
+
+	* ansidecl.h: Use ANSI versions on AIX regardless of __STDC__.
+
+Fri Mar 19 14:49:49 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* dis-asm.h: Add h8500.
+
+Thu Mar 18 13:49:09 1993  Per Bothner  (bothner@rtl.cygnus.com)
+
+	* ieee-float.h:  Moved from ../gdb.
+	* dis-asm.h:  New file.  Interface to dis-assembler.
+
+Thu Mar 11 10:52:57 1993  Fred Fish  (fnf@cygnus.com)
+
+	* demangle.h (DMGL_NO_OPTS):  Add define (set to 0) to use
+	in place of bare 0, for readability reasons.
+
+Tue Mar  2 17:50:11 1993  Fred Fish  (fnf@cygnus.com)
+
+	* demangle.h:  Replace all references to cfront with ARM.
+
+Tue Feb 23 12:21:14 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* bfd.h: Update for new elements in JUMP_TABLE.
+
+Tue Feb 16 00:51:30 1993  John Gilmore  (gnu@cygnus.com)
+
+	* bfd.h:  Update for BFD_VERSION 2.1.
+
+Tue Jan 26 11:49:20 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* bfd.h: Update for SEC_IS_COMMON flag.
+
+Tue Jan 19 12:25:12 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* bfd.h: Update for bfd_asymbol_value bug fix.
+
+Fri Jan  8 16:37:18 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* bfd.h: Update to include ECOFF tdata and target_flavour.
+
+Sun Dec 27 17:52:30 1992  Fred Fish  (fnf@cygnus.com)
+
+	* bfd.h:  Add declaration for bfd_get_size().
+
+Tue Dec 22 22:42:46 1992  Fred Fish  (fnf@cygnus.com)
+
+	* demangle.h:  Protect file from multiple inclusions with
+	#if !defined(DEMANGLE_H)...#define DEMANGLE_H...#endif.
+
+Mon Dec 21 21:25:50 1992  Stu Grossman  (grossman at cygnus.com)
+
+	* bfd.h:  Update to get hppa_core_struct from bfd.c.
+
+Thu Dec 17 00:42:35 1992  John Gilmore  (gnu@cygnus.com)
+
+	* bfd.h:  Update to get tekhex tdata name change from bfd.
+
+Mon Nov  9 23:55:42 1992  John Gilmore  (gnu@cygnus.com)
+
+	* ansidecl.h:  Update comments to discourage use of EXFUN.
+
+Thu Nov  5 16:35:44 1992  Ian Lance Taylor  (ian@cygnus.com)
+
+	* bfd.h: Update to bring in SEC_SHARED_LIBRARY.
+
+Thu Nov  5 03:21:32 1992  John Gilmore  (gnu@cygnus.com)
+
+	* bfd.h:  Update to match EXFUN, bfd_seclet_struct, and SDEF
+	cleanups in bfd.
+
+Wed Nov  4 07:28:05 1992  Ken Raeburn  (raeburn@cygnus.com)
+
+	* bout.h (N_CALLNAME, N_BALNAME): Define as char-type values, so
+	widening works consistently.
+
+Fri Oct 16 03:17:08 1992  John Gilmore  (gnu@cygnus.com)
+
+	* getopt.h:  Update to Revised Standard FSF Version.
+
+Thu Oct 15 21:43:22 1992  K. Richard Pixley  (rich@sendai.cygnus.com)
+
+	* getopt.h (struct option): use the provided enum for has_arg.
+
+	* demangle.h (AUTO_DEMANGLING, GNU_DEMANGLING,
+	  LUCID_DEMANGLING): ultrix compilers require enums to be
+	  enums and ints to be ints and casts where they meet.  cast some
+	  enums into ints.
+
+Thu Oct 15 04:35:51 1992  John Gilmore  (gnu@cygnus.com)
+
+	* bfd.h:  Update after comment changes.
+
+Thu Oct  8 09:03:02 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* bfd.h (bfd_get_symbol_leading_char): new macro for getting in xvec
+
+Thu Sep  3 09:10:50 1992  Stu Grossman  (grossman at cygnus.com)
+
+	* bfd.h (struct reloc_howto_struct):  size needs to be signed if
+	it's going to hold negative values.
+
+Sun Aug 30 17:50:27 1992  Per Bothner  (bothner@rtl.cygnus.com)
+
+	* demangle.h:  New file, moved from ../gdb.  Made independent
+	of gdb.  Allow demangling style option to be passed as a
+	parameter to cplus_demangle(), but using the
+	current_demangling_style global as the default.
+
+Sat Aug 29 10:07:55 1992  Fred Fish  (fnf@cygnus.com)
+
+	* obstack.h:  Merge comment change from current FSF version.
+
+Thu Aug 27 12:59:29 1992  Brendan Kehoe  (brendan@cygnus.com)
+
+	* bfd.h: add we32k
+
+Tue Aug 25 15:07:47 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* bfd.h: new after Z8000 stuff
+
+Mon Aug 17 09:01:23 1992  Ken Raeburn  (raeburn@cygnus.com)
+
+	* bfd.h: Regenerated after page/segment size changes.
+
+Sat Aug  1 13:46:31 1992  Fred Fish  (fnf@cygnus.com)
+
+	* obstack.h: Merge changes from current FSF version.
+
+Mon Jul 20 21:06:23 1992  Fred Fish  (fnf@cygnus.com)
+
+	* obstack.h (area_id, flags):  Remove, replace with extra_arg,
+	use_extra_arg, and maybe_empty_object.
+	* obstack.h (OBSTACK_MAYBE_EMPTY_OBJECT, OBSTACK_MMALLOC_LIKE):
+	Remove, replaced by maybe_empty_object and use_extra_arg bitfields.
+	* obstack.h (obstack_full_begin, _obstack_begin):  Remove area_id
+	and flags arguments.
+	* obstack.h (obstack_alloc_arg):  New macro to set extra_arg.
+
+Thu Jul 16 08:12:44 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* bfd.h: new after adding BFD_IS_RELAXABLE
+
+Sat Jul  4 03:22:23 1992  John Gilmore  (gnu at cygnus.com)
+
+	* bfd.h:  Regen after adding BSF_FILE.
+
+Mon Jun 29 14:18:36 1992  Fred Fish  (fnf at sunfish)
+
+	* obstack.h:  Convert bcopy() use to memcpy(), which is more
+	portable, more standard, and can take advantage of gcc's builtin
+	functions for increased performance.
+
+Thu Jun 25 04:46:08 1992  John Gilmore  (gnu at cygnus.com)
+
+	* ansidecl.h (PARAMS):  Incorporate this macro from gdb's defs.h.
+	It's a cleaner way to forward-declare function prototypes.
+
+Fri Jun 19 15:46:32 1992  Stu Grossman  (grossman at cygnus.com)
+
+	* bfd.h:  HPPA merge.
+
+Tue Jun 16 21:30:56 1992  K. Richard Pixley  (rich@cygnus.com)
+
+	* getopt.h: gratuitous white space changes merged from other prep
+	  releases.
+
+Thu Jun 11 01:10:55 1992  John Gilmore  (gnu at cygnus.com)
+
+	* bfd.h:  Regen'd from bfd.c after removing elf_core_tdata_struct.
+
+Mon May 18 17:29:03 1992  K. Richard Pixley  (rich@cygnus.com)
+
+	* getopt.h: merged changes from make-3.62.11.
+
+	* getopt.h: merged changes from grep-1.6 (alpha).
+
+Fri May  8 14:53:32 1992  K. Richard Pixley  (rich@cygnus.com)
+
+	* getopt.h: merged changes from bison-1.18.
+
+Sat Mar 14 17:25:20 1992  Fred Fish  (fnf@cygnus.com)
+
+	* obstack.h:  Add "area_id" and "flags" members to obstack
+	structure.  Add obstack_chunkfun() and obstack_freefun() to
+	set functions explicitly.  Convert maybe_empty_object to
+	a bit in "flags".
+
+Thu Feb 27 22:01:02 1992  Per Bothner  (bothner@cygnus.com)
+
+	* wait.h (WIFSTOPPED):  Add IBM rs6000-specific version.
+
+Fri Feb 21 20:49:20 1992  John Gilmore  (gnu at cygnus.com)
+
+	* obstack.h:  Add obstack_full_begin.
+	* bfd.h, obstack.h:  Protolint.
+
+Thu Jan 30 01:18:42 1992  John Gilmore  (gnu at cygnus.com)
+
+	* bfd.h:  Remove comma from enum declaration.
+
+Mon Jan 27 22:01:13 1992  Steve Chamberlain  (sac at cygnus.com)
+
+	* bfd.h : new target entr, bfd_relax_section
+
+Wed Dec 18 17:19:44 1991  Stu Grossman  (grossman at cygnus.com)
+
+	* bfd.h, ieee.h:  ANSIfy enums.
+
+Thu Dec 12 20:59:56 1991  John Gilmore  (gnu at cygnus.com)
+
+	* fopen-same.h, fopen-bin.h:  New files for configuring
+	whether fopen distinguishes binary files or not.  For use
+	by host-dependent config files.
+
+Sat Nov 30 20:46:43 1991  Steve Chamberlain  (sac at rtl.cygnus.com)
+
+	* bfd.h: change the documentation format.
+
+	* created coff, elf and opcode and aout directories. Moved:
+
+	aout64.h	==> aout/aout64.h
+	ar.h		==> aout/ar.h
+	a.out.encap.h	==> aout/encap.h
+	a.out.host.h	==> aout/host.h
+	a.out.hp.h	==> aout/hp.h
+	a.out.sun4.h	==> aout/sun4.h
+	ranlib.h	==> aout/ranlib.h
+	reloc.h		==> aout/reloc.h
+	stab.def	==> aout/stab.def
+	stab.gnu.h	==> aout/stab_gnu.h
+
+	coff-a29k.h	==> coff/a29k.h
+	coff-h8300.h	==> coff/h8300.h
+	coff-i386.h	==> coff/i386.h
+	coff-i960.h	==> coff/i960.h
+	internalcoff.h	==> coff/internal.h
+	coff-m68k.h	==> coff/m68k.h
+	coff-m88k.h	==> coff/m88k.h
+	coff-mips.h	==> coff/mips.h
+	coff-rs6000.h	==> coff/rs6000.h
+
+	elf-common.h	==> elf/common.h
+	dwarf.h		==> elf/dwarf.h
+	elf-external.h	==> elf/external.h
+	elf-internal.h  ==> elf/internal.h
+
+	a29k-opcode.h	==> opcode/a29k.h
+	arm-opcode.h	==> opcode/arm.h
+	h8300-opcode.h	==> opcode/h8300.h
+	i386-opcode.h	==> opcode/i386.h
+	i860-opcode.h	==> opcode/i860.h
+	i960-opcode.h	==> opcode/i960.h
+	m68k-opcode.h	==> opcode/m68k.h
+	m88k-opcode.h	==> opcode/m88k.h
+	mips-opcode.h	==> opcode/mips.h
+	np1-opcode.h	==> opcode/np1.h
+	ns32k-opcode.h	==> opcode/ns32k.h
+	pn-opcode.h	==> opcode/pn.h
+	pyr-opcode.h	==> opcode/pyr.h
+	sparc-opcode.h	==> opcode/sparc.h
+	tahoe-opcode.h	==> opcode/tahoe.h
+	vax-opcode.h	==> opcode/vax.h
+
+
+
+Wed Nov 27 10:38:31 1991  Steve Chamberlain  (sac at rtl.cygnus.com)
+
+	* internalcoff.h: (internal_scnhdr) took out #def dependency, now
+	s_nreloc and s_nlnno are always long. 	(internal_reloc): allways
+	has an offset field now.
+
+Fri Nov 22 08:12:58 1991  John Gilmore  (gnu at cygnus.com)
+
+	* coff-rs6000.h:  Lint; use unsigned chars for external fields.
+	* internalcoff.h:  Lint; cast storage classes to signed char.
+
+Thu Nov 21 21:01:05 1991  Per Bothner  (bothner at cygnus.com)
+
+	* stab.def: Remove the GNU extended type codes (e.g. N_SETT).
+	* aout64.h:  The heuristic for distinguishing between
+	sunos-style and bsd-style ZMAGIC files (wrt. where the
+	text segment starts) is moved into (the default definition of)
+	the macro N_HEADER_IN_TEXT.  This definition is only used
+	if no other definition is used - e.g. bfd/newsos3.c defines
+	N_HEADER_IN_TEXT(x) to be always 0 (as before).
+
+Thu Nov 21 11:53:03 1991  John Gilmore  (gnu at cygnus.com)
+
+	* aout64.h (N_TXTADDR, N_TXTOFF, N_TXTSIZE):  New definitions
+	that should handle all uses.  LOGICAL_ versions deleted.
+	Eliminate N_HEADER_IN_TEXT, using a_entry to determine which
+	kind of zmagic a.out file we are looking at.
+	* coff-rs6000.h:  Typo.
+
+Tue Nov 19 18:43:37 1991  Per Bothner  (bothner at cygnus.com)
+
+	(Note:  This is a revised entry, as was aout64.h.)
+	* aout64.h:  Some cleanups of N_TXTADDR and N_TXTOFF:
+	Will now work for both old- and new-style ZMAGIC files,
+	depending on N_HEADER_IN_TEXT macro.
+	Add LOGICAL_TXTADDR, LOICAL_TXTOFF and LOGICAL_TXTSIZE
+	that don't count the exec header as part
+	of the text segment, to be consistent with bfd.
+	* a.out.sun4.h:  Simplified/fixed for previous change.
+
+Mon Nov 18 00:02:06 1991  Fred Fish  (fnf at cygnus.com)
+
+	* dwarf.h:  Update to DWARF draft 5 version from gcc2.
+
+Thu Nov 14 19:44:59 1991  Per Bothner  (bothner at cygnus.com)
+
+	* stab.def:  Added defs for extended GNU symbol types,
+	such as N_SETT.  These are normally ifdef'd out (because
+	of conflicts with a.out.gnu.h), but are used by bfb_stab_name().
+
+Thu Nov 14 19:17:03 1991  Fred Fish  (fnf at cygnus.com)
+
+	* elf-common.h:  Add defines to support ELF symbol table code.
+
+Mon Nov 11 19:01:06 1991  Fred Fish  (fnf at cygnus.com)
+
+	* elf-internal.h, elf-external.h, elf-common.h:  Add support for
+	note sections, which are used in ELF core files to hold copies
+	of various /proc structures.
+
+Thu Nov  7 08:58:26 1991  Steve Chamberlain  (sac at cygnus.com)
+
+	* internalcoff.h: took out the M88 dependency in the lineno
+	struct.
+	* coff-m88k.h: defines GET_LINENO_LNNO and PUT_LINENO_LNNO to use
+	32bit linno entries.
+	* a29k-opcode.h: fixed encoding of mtacc
+
+Sun Nov  3 11:54:22 1991  Per Bothner  (bothner at cygnus.com)
+
+	* bfd.h: Updated from ../bfd/bfd-in.h (q.v).
+
+Fri Nov  1 11:13:53 1991  John Gilmore  (gnu at cygnus.com)
+
+	* internalcoff.h:  Add x_csect defines.
+
+Fri Oct 25 03:18:20 1991  John Gilmore  (gnu at cygnus.com)
+
+	* Rename COFF-related files in `coff-ARCH.h' form.
+	coff-a29k.h, coff-i386.h, coff-i960.h, coff-m68k.h, coff-m88k.h,
+	coff-mips.h, coff-rs6000.h to be exact.
+
+Thu Oct 24 22:11:11 1991  John Gilmore  (gnu at cygnus.com)
+
+	RS/6000 support, by Metin G. Ozisik, Mimi Phûông-Thåo Võ, and
+	John Gilmore.
+
+	* a.out.gnu.h:  Update slightly.
+	* bfd.h:  Add new error code, fix doc, add bfd_arch_rs6000.
+	* internalcoff.h:  Add more F_ codes for filehdr.  Add
+	rs/6000-dependent fields to aouthdr.  Add storage classes
+	to syments.  Add 6000-specific auxent.  Add r_size in reloc.
+	* rs6000coff.c:  New file.
+
+Thu Oct 24 04:13:20 1991  Fred Fish  (fnf at cygnus.com)
+
+	* dwarf.h: New file for dwarf support.  Copied from gcc2
+	distribution.
+
+Wed Oct 16 13:31:45 1991  John Gilmore  (gnu at cygnus.com)
+
+	* aout64.h:  Remove PAGE_SIZE defines; they are target-dependent.
+	Add N_FN_SEQ for N_FN symbol type used on Sequent machines.
+	* stab.def:  Include N_FN_SEQ in table.
+	* bout.h:  External formats of structures use unsigned chars.
+
+Fri Oct 11 12:40:43 1991  Steve Chamberlain  (steve at cygnus.com)
+
+	* bfd.h:upgrade from bfd.c
+	* internalcoff.h: add n_name, n_zeroes and n_offset macros
+	* amdcoff.h: Define OMAGIC and AOUTHDRSZ.
+
+Fri Oct 11 10:58:06 1991  Per Bothner  (bothner at cygnus.com)
+
+	* a.out.host.h: Change SEGMENT_SIZE to 0x1000 for Sony.
+	* bfd.h (align_power): Add (actually move) comment.
+
+Tue Oct  8 15:29:32 1991  Per Bothner  (bothner at cygnus.com)
+
+	* sys/h-rtbsd.h: Define MISSING_VFPRINT (for binutils/bucomm.c).
+
+Sun Oct  6 19:24:39 1991  John Gilmore  (gnu at cygnus.com)
+
+	* aout64.h:  Move struct internal_exec to ../bfd/libaout.h so
+	it can be shared by all `a.out-family' code.  Rename
+	EXTERNAL_LIST_SIZE to EXTERNAL_NLIST_SIZE.  Use basic types
+	for nlist members, and make strx integral rather than pointer.
+	More commentary on n_type values.
+	* bout.h:  Provide a struct external_exec rather than an
+	internal_exec.
+	* m68kcoff.h:  Remove `tagentries' which snuck in from the i960
+	COFF port.
+
+Fri Oct  4 01:25:59 1991  John Gilmore  (gnu at cygnus.com)
+
+	* h8300-opcode.h:  Remove `_enum' from the typedef for an enum.
+	* bfd.h:  Update to match bfd changes.
+
+	* sys/h-i386mach.h, sysdep.h:  Add 386 Mach host support.
+
+Tue Oct  1 04:58:42 1991  John Gilmore  (gnu at cygnus.com)
+
+	* bfd.h, elf-common.h, elf-external.h, elf-internal.h:
+	Add preliminary ELF support, sufficient for GDB, from Fred Fish.
+	* sysdep.h, sys/h-amix.h:  Support Amiga SVR4.
+
+	* sys/h-vaxult.h:  Make it work.  (David Taylor <taylor@think.com>)
+	* a.out.vax.h:  Remove unused and confusing file.
+
+Mon Sep 30 12:52:35 1991  Per Bothner  (bothner at cygnus.com)
+
+	* sysdep.h: Define NEWSOS3_SYS, and use it.
+
+Fri Sep 20 13:38:21 1991  John Gilmore  (gnu at cygnus.com)
+
+	* a.out.gnu.h (N_FN):  Its value *really is* 0x1F.
+	Fix it, and add comments warning about or-ing N_EXT with it
+	and/or N_WARNING.
+	* aout64.h (N_FN):  Fix value, add comments about N_EXT.
+	* stab.def (table at end):  Update to show all the type
+	values <0x20, including low order bits.  Move N_FN to
+	its rightful place.
+
+Tue Sep 17 17:41:37 1991  Stu Grossman  (grossman at cygnus.com)
+
+	* sys/h-irix3.h:  sgi/irix support.
+
+Tue Sep 17 07:52:59 1991  John Gilmore  (gnu at cygint.cygnus.com)
+
+	* stab.def (N_DEFD):  Add GNU Modula-2 debug stab, from Andrew
+	Beers.
+
+Thu Sep 12 14:12:59 1991  John Gilmore  (gnu at cygint.cygnus.com)
+
+	* internalcoff.h (SYMNMLEN, FILNMLEN, DIMNUM):  Define these
+	for internalcoff, separately from the various external coff's.
+	* amdcoff.h, bcs88kcoff.h, i386coff.h, intel-coff.h, m68kcoff.h,
+	m88k-bcs.h: Prefix SYMNMLEN, FILNMLEN, and DIMNUM with E_'s for
+	the external struct definitions.
+	* ecoff.h: Remove these #define's, kludge no longer needed.
+
+	* sys/h-ultra3.h:  Add new Ultracomputer host.
+	* sysdep.h:  Add ULTRA3_SYM1_SYS and use it.
+
+Tue Sep 10 10:11:46 1991  John Gilmore  (gnu at cygint.cygnus.com)
+
+	* i386coff.h (LINESZ):  Always 6, not based on sizeof().
+	(Fix from Peter Schauer <pes@regent.e-technik.tu-muenchen.de>.)
+
+Wed Sep  4 08:58:37 1991  John Gilmore  (gnu at cygint.cygnus.com)
+
+	* a.out.gnu.h, aout64.h:  Add N_WARNING.  Change N_FN to 0x0E,
+	to match SunOS and BSD.  Add N_COMM as 0x12 for SunOS shared lib
+	support.
+	* stab.def:  Add N_COMM to table, fix overlap comment.
+
+Tue Sep  3 06:29:20 1991  John Gilmore  (gnu at cygint.cygnus.com)
+
+	Merge with latest FSF versions of these files.
+
+	* stab.gnu.h:  Add LAST_UNUSED_STAB_CODE.
+	* stab.def:  Update to GPL2.  Move N_WARNING out, since not a
+	debug symbol.  Change comments, and reorder table to numeric
+	order.  Update final table comment.
+	(N_DSLINE, N_BSLINE):  Renumber from 0x66 and 0x68, to 0x46 and 0x48.
+
+	* obstack.h:  GPL2.  Merge.
+
+Fri Aug 23 01:54:23 1991  John Gilmore  (gnu at cygint.cygnus.com)
+
+	* a.out.gnu.h, a.out.sun4.h:  Make SEGMENT_SIZE able to depend
+	on the particular a.out being examined.
+	* a.out.sun4.h:  Define segment sizes for Sun-3's and Sun-4's.
+	* FIXME:  a.out.gnu.h is almost obsolete.
+	* FIXME:  a.out.sun4.h should be renamed a.out.sun.h now.
+
+Wed Aug 21 20:32:13 1991  John Gilmore  (gnu at cygint.cygnus.com)
+
+	* Start a ChangeLog for the includes directory.
+
+	* a.out.gnu.h (N_FN):  Fix value -- was 15, should be 0x1E.
+	* stab.def:  Update allocation table in comments at end,
+	to reflect reality as I know it.
+
+
+Copyright (C) 1993-2003 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.25/include/MAINTAINERS b/binutils-2.25/include/MAINTAINERS
new file mode 100644
index 00000000..cd933df7
--- /dev/null
+++ b/binutils-2.25/include/MAINTAINERS
@@ -0,0 +1,7 @@
+See ../binutils/MAINTAINERS
+
+Copyright (C) 2012 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
diff --git a/binutils-2.25/include/alloca-conf.h b/binutils-2.25/include/alloca-conf.h
new file mode 100644
index 00000000..0e9e2c37
--- /dev/null
+++ b/binutils-2.25/include/alloca-conf.h
@@ -0,0 +1,60 @@
+/* Copyright 2012 Free Software Foundation, Inc.
+
+   This program is free software: you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+
+/* This is a merge of code recommended in the autoconf-2.61 documentation
+   with that recommended in the autoconf-2.13 documentation, with added
+   tweaks to heed C_ALLOCA.  */
+
+#if defined HAVE_ALLOCA_H && !defined C_ALLOCA
+# include <alloca.h>
+#else
+# if defined __GNUC__ && !defined C_ALLOCA
+#  if !defined alloca
+#   define alloca __builtin_alloca
+#  endif
+# else
+#  if defined _AIX
+/* Indented so that pre-ansi C compilers will ignore it, rather than
+   choke on it.  Some versions of AIX require this to be the first
+   thing seen by the compiler except for comments and preprocessor
+   directives.  */
+    #pragma alloca
+#  else
+#   if defined _MSC_VER && !defined C_ALLOCA
+#    include <malloc.h>
+#    define alloca _alloca
+#   else
+#    if !defined alloca
+#     if defined __STDC__ || defined __hpux
+#      if defined HAVE_STDDEF_H
+#       include <stddef.h>
+#       if defined  __cplusplus
+extern "C" void *alloca (size_t);
+#       else
+extern void *alloca (size_t);
+#       endif
+#      else
+extern void *alloca ();
+#      endif
+#     else
+extern char *alloca ();
+#     endif
+#    endif
+#   endif
+#  endif
+# endif
+#endif
diff --git a/binutils-2.25/include/ansidecl.h b/binutils-2.25/include/ansidecl.h
new file mode 100644
index 00000000..0fb23bba
--- /dev/null
+++ b/binutils-2.25/include/ansidecl.h
@@ -0,0 +1,313 @@
+/* ANSI and traditional C compatability macros
+   Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
+   2002, 2003, 2004, 2005, 2006, 2007, 2009, 2010, 2013
+   Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+/* ANSI and traditional C compatibility macros
+
+   ANSI C is assumed if __STDC__ is #defined.
+
+   Macro		ANSI C definition	Traditional C definition
+   -----		---- - ----------	----------- - ----------
+   PTR			`void *'		`char *'
+   const		not defined		`'
+   volatile		not defined		`'
+   signed		not defined		`'
+
+   For ease of writing code which uses GCC extensions but needs to be
+   portable to other compilers, we provide the GCC_VERSION macro that
+   simplifies testing __GNUC__ and __GNUC_MINOR__ together, and various
+   wrappers around __attribute__.  Also, __extension__ will be #defined
+   to nothing if it doesn't work.  See below.  */
+
+#ifndef	_ANSIDECL_H
+#define _ANSIDECL_H	1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Every source file includes this file,
+   so they will all get the switch for lint.  */
+/* LINTLIBRARY */
+
+/* Using MACRO(x,y) in cpp #if conditionals does not work with some
+   older preprocessors.  Thus we can't define something like this:
+
+#define HAVE_GCC_VERSION(MAJOR, MINOR) \
+  (__GNUC__ > (MAJOR) || (__GNUC__ == (MAJOR) && __GNUC_MINOR__ >= (MINOR)))
+
+and then test "#if HAVE_GCC_VERSION(2,7)".
+
+So instead we use the macro below and test it against specific values.  */
+
+/* This macro simplifies testing whether we are using gcc, and if it
+   is of a particular minimum version. (Both major & minor numbers are
+   significant.)  This macro will evaluate to 0 if we are not using
+   gcc at all.  */
+#ifndef GCC_VERSION
+#define GCC_VERSION (__GNUC__ * 1000 + __GNUC_MINOR__)
+#endif /* GCC_VERSION */
+
+#if defined (__STDC__) || defined(__cplusplus) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(_WIN32)
+/* All known AIX compilers implement these things (but don't always
+   define __STDC__).  The RISC/OS MIPS compiler defines these things
+   in SVR4 mode, but does not define __STDC__.  */
+/* eraxxon@alumni.rice.edu: The Compaq C++ compiler, unlike many other
+   C++ compilers, does not define __STDC__, though it acts as if this
+   was so. (Verified versions: 5.7, 6.2, 6.3, 6.5) */
+
+#define PTR		void *
+
+#undef const
+#undef volatile
+#undef signed
+
+/* inline requires special treatment; it's in C99, and GCC >=2.7 supports
+   it too, but it's not in C89.  */
+#undef inline
+#if __STDC_VERSION__ >= 199901L || defined(__cplusplus) || (defined(__SUNPRO_C) && defined(__C99FEATURES__))
+/* it's a keyword */
+#else
+# if GCC_VERSION >= 2007
+#  define inline __inline__   /* __inline__ prevents -pedantic warnings */
+# else
+#  define inline  /* nothing */
+# endif
+#endif
+
+#else	/* Not ANSI C.  */
+
+#define PTR		char *
+
+/* some systems define these in header files for non-ansi mode */
+#undef const
+#undef volatile
+#undef signed
+#undef inline
+#define const
+#define volatile
+#define signed
+#define inline
+
+#endif	/* ANSI C.  */
+
+/* Define macros for some gcc attributes.  This permits us to use the
+   macros freely, and know that they will come into play for the
+   version of gcc in which they are supported.  */
+
+#if (GCC_VERSION < 2007)
+# define __attribute__(x)
+#endif
+
+/* Attribute __malloc__ on functions was valid as of gcc 2.96. */
+#ifndef ATTRIBUTE_MALLOC
+# if (GCC_VERSION >= 2096)
+#  define ATTRIBUTE_MALLOC __attribute__ ((__malloc__))
+# else
+#  define ATTRIBUTE_MALLOC
+# endif /* GNUC >= 2.96 */
+#endif /* ATTRIBUTE_MALLOC */
+
+/* Attributes on labels were valid as of gcc 2.93 and g++ 4.5.  For
+   g++ an attribute on a label must be followed by a semicolon.  */
+#ifndef ATTRIBUTE_UNUSED_LABEL
+# ifndef __cplusplus
+#  if GCC_VERSION >= 2093
+#   define ATTRIBUTE_UNUSED_LABEL ATTRIBUTE_UNUSED
+#  else
+#   define ATTRIBUTE_UNUSED_LABEL
+#  endif
+# else
+#  if GCC_VERSION >= 4005
+#   define ATTRIBUTE_UNUSED_LABEL ATTRIBUTE_UNUSED ;
+#  else
+#   define ATTRIBUTE_UNUSED_LABEL
+#  endif
+# endif
+#endif
+
+/* Similarly to ARG_UNUSED below.  Prior to GCC 3.4, the C++ frontend
+   couldn't parse attributes placed after the identifier name, and now
+   the entire compiler is built with C++.  */
+#ifndef ATTRIBUTE_UNUSED
+#if GCC_VERSION >= 3004
+#  define ATTRIBUTE_UNUSED __attribute__ ((__unused__))
+#else
+#define ATTRIBUTE_UNUSED
+#endif
+#endif /* ATTRIBUTE_UNUSED */
+
+/* Before GCC 3.4, the C++ frontend couldn't parse attributes placed after the
+   identifier name.  */
+#if ! defined(__cplusplus) || (GCC_VERSION >= 3004)
+# define ARG_UNUSED(NAME) NAME ATTRIBUTE_UNUSED
+#else /* !__cplusplus || GNUC >= 3.4 */
+# define ARG_UNUSED(NAME) NAME
+#endif /* !__cplusplus || GNUC >= 3.4 */
+
+#ifndef ATTRIBUTE_NORETURN
+#define ATTRIBUTE_NORETURN __attribute__ ((__noreturn__))
+#endif /* ATTRIBUTE_NORETURN */
+
+/* Attribute `nonnull' was valid as of gcc 3.3.  */
+#ifndef ATTRIBUTE_NONNULL
+# if (GCC_VERSION >= 3003)
+#  define ATTRIBUTE_NONNULL(m) __attribute__ ((__nonnull__ (m)))
+# else
+#  define ATTRIBUTE_NONNULL(m)
+# endif /* GNUC >= 3.3 */
+#endif /* ATTRIBUTE_NONNULL */
+
+/* Attribute `returns_nonnull' was valid as of gcc 4.9.  */
+#ifndef ATTRIBUTE_RETURNS_NONNULL
+# if (GCC_VERSION >= 4009)
+#  define ATTRIBUTE_RETURNS_NONNULL __attribute__ ((__returns_nonnull__))
+# else
+#  define ATTRIBUTE_RETURNS_NONNULL
+# endif /* GNUC >= 4.9 */
+#endif /* ATTRIBUTE_RETURNS_NONNULL */
+
+/* Attribute `pure' was valid as of gcc 3.0.  */
+#ifndef ATTRIBUTE_PURE
+# if (GCC_VERSION >= 3000)
+#  define ATTRIBUTE_PURE __attribute__ ((__pure__))
+# else
+#  define ATTRIBUTE_PURE
+# endif /* GNUC >= 3.0 */
+#endif /* ATTRIBUTE_PURE */
+
+/* Use ATTRIBUTE_PRINTF when the format specifier must not be NULL.
+   This was the case for the `printf' format attribute by itself
+   before GCC 3.3, but as of 3.3 we need to add the `nonnull'
+   attribute to retain this behavior.  */
+#ifndef ATTRIBUTE_PRINTF
+#define ATTRIBUTE_PRINTF(m, n) __attribute__ ((__format__ (__printf__, m, n))) ATTRIBUTE_NONNULL(m)
+#define ATTRIBUTE_PRINTF_1 ATTRIBUTE_PRINTF(1, 2)
+#define ATTRIBUTE_PRINTF_2 ATTRIBUTE_PRINTF(2, 3)
+#define ATTRIBUTE_PRINTF_3 ATTRIBUTE_PRINTF(3, 4)
+#define ATTRIBUTE_PRINTF_4 ATTRIBUTE_PRINTF(4, 5)
+#define ATTRIBUTE_PRINTF_5 ATTRIBUTE_PRINTF(5, 6)
+#endif /* ATTRIBUTE_PRINTF */
+
+/* Use ATTRIBUTE_FPTR_PRINTF when the format attribute is to be set on
+   a function pointer.  Format attributes were allowed on function
+   pointers as of gcc 3.1.  */
+#ifndef ATTRIBUTE_FPTR_PRINTF
+# if (GCC_VERSION >= 3001)
+#  define ATTRIBUTE_FPTR_PRINTF(m, n) ATTRIBUTE_PRINTF(m, n)
+# else
+#  define ATTRIBUTE_FPTR_PRINTF(m, n)
+# endif /* GNUC >= 3.1 */
+# define ATTRIBUTE_FPTR_PRINTF_1 ATTRIBUTE_FPTR_PRINTF(1, 2)
+# define ATTRIBUTE_FPTR_PRINTF_2 ATTRIBUTE_FPTR_PRINTF(2, 3)
+# define ATTRIBUTE_FPTR_PRINTF_3 ATTRIBUTE_FPTR_PRINTF(3, 4)
+# define ATTRIBUTE_FPTR_PRINTF_4 ATTRIBUTE_FPTR_PRINTF(4, 5)
+# define ATTRIBUTE_FPTR_PRINTF_5 ATTRIBUTE_FPTR_PRINTF(5, 6)
+#endif /* ATTRIBUTE_FPTR_PRINTF */
+
+/* Use ATTRIBUTE_NULL_PRINTF when the format specifier may be NULL.  A
+   NULL format specifier was allowed as of gcc 3.3.  */
+#ifndef ATTRIBUTE_NULL_PRINTF
+# if (GCC_VERSION >= 3003)
+#  define ATTRIBUTE_NULL_PRINTF(m, n) __attribute__ ((__format__ (__printf__, m, n)))
+# else
+#  define ATTRIBUTE_NULL_PRINTF(m, n)
+# endif /* GNUC >= 3.3 */
+# define ATTRIBUTE_NULL_PRINTF_1 ATTRIBUTE_NULL_PRINTF(1, 2)
+# define ATTRIBUTE_NULL_PRINTF_2 ATTRIBUTE_NULL_PRINTF(2, 3)
+# define ATTRIBUTE_NULL_PRINTF_3 ATTRIBUTE_NULL_PRINTF(3, 4)
+# define ATTRIBUTE_NULL_PRINTF_4 ATTRIBUTE_NULL_PRINTF(4, 5)
+# define ATTRIBUTE_NULL_PRINTF_5 ATTRIBUTE_NULL_PRINTF(5, 6)
+#endif /* ATTRIBUTE_NULL_PRINTF */
+
+/* Attribute `sentinel' was valid as of gcc 3.5.  */
+#ifndef ATTRIBUTE_SENTINEL
+# if (GCC_VERSION >= 3005)
+#  define ATTRIBUTE_SENTINEL __attribute__ ((__sentinel__))
+# else
+#  define ATTRIBUTE_SENTINEL
+# endif /* GNUC >= 3.5 */
+#endif /* ATTRIBUTE_SENTINEL */
+
+
+#ifndef ATTRIBUTE_ALIGNED_ALIGNOF
+# if (GCC_VERSION >= 3000)
+#  define ATTRIBUTE_ALIGNED_ALIGNOF(m) __attribute__ ((__aligned__ (__alignof__ (m))))
+# else
+#  define ATTRIBUTE_ALIGNED_ALIGNOF(m)
+# endif /* GNUC >= 3.0 */
+#endif /* ATTRIBUTE_ALIGNED_ALIGNOF */
+
+/* Useful for structures whose layout must much some binary specification
+   regardless of the alignment and padding qualities of the compiler.  */
+#ifndef ATTRIBUTE_PACKED
+# define ATTRIBUTE_PACKED __attribute__ ((packed))
+#endif
+
+/* Attribute `hot' and `cold' was valid as of gcc 4.3.  */
+#ifndef ATTRIBUTE_COLD
+# if (GCC_VERSION >= 4003)
+#  define ATTRIBUTE_COLD __attribute__ ((__cold__))
+# else
+#  define ATTRIBUTE_COLD
+# endif /* GNUC >= 4.3 */
+#endif /* ATTRIBUTE_COLD */
+#ifndef ATTRIBUTE_HOT
+# if (GCC_VERSION >= 4003)
+#  define ATTRIBUTE_HOT __attribute__ ((__hot__))
+# else
+#  define ATTRIBUTE_HOT
+# endif /* GNUC >= 4.3 */
+#endif /* ATTRIBUTE_HOT */
+
+/* We use __extension__ in some places to suppress -pedantic warnings
+   about GCC extensions.  This feature didn't work properly before
+   gcc 2.8.  */
+#if GCC_VERSION < 2008
+#define __extension__
+#endif
+
+/* This is used to declare a const variable which should be visible
+   outside of the current compilation unit.  Use it as
+     EXPORTED_CONST int i = 1;
+   This is because the semantics of const are different in C and C++.
+   "extern const" is permitted in C but it looks strange, and gcc
+   warns about it when -Wc++-compat is not used.  */
+#ifdef __cplusplus
+#define EXPORTED_CONST extern const
+#else
+#define EXPORTED_CONST const
+#endif
+
+/* Be conservative and only use enum bitfields with C++ or GCC.
+   FIXME: provide a complete autoconf test for buggy enum bitfields.  */
+
+#ifdef __cplusplus
+#define ENUM_BITFIELD(TYPE) enum TYPE
+#elif (GCC_VERSION > 2000)
+#define ENUM_BITFIELD(TYPE) __extension__ enum TYPE
+#else
+#define ENUM_BITFIELD(TYPE) unsigned int
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* ansidecl.h	*/
diff --git a/binutils-2.25/include/aout/ChangeLog b/binutils-2.25/include/aout/ChangeLog
new file mode 100644
index 00000000..b4d4139d
--- /dev/null
+++ b/binutils-2.25/include/aout/ChangeLog
@@ -0,0 +1,262 @@
+2010-04-15  Nick Clifton  <nickc@redhat.com>
+
+	* adobe.h: Update copyright notice to use GPLv3.
+	* aout64.h: Likewise.
+	* ar.h: Likewise.
+	* dynix3.h: Likewise.
+	* encap.h: Likewise.
+	* host.h: Likewise.
+	* hp.h: Likewise.
+	* hp300hpux.h: Likewise.
+	* ranlib.h: Likewise.
+	* reloc.h: Likewise.
+	* stab.def: Likewise.
+	* stab_gnu.h: Likewise.
+	* sun4.h: Likewise.
+
+2009-10-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* aout64.h (N_SHARED_LIB): Define as zero if not already defined.
+	* sun4.h (N_SHARED_LIB): Define.
+	* hp300hpux.h (N_SHARED_LIB): Don't define.
+
+2008-08-28  Tristan Gingold  <gingold@adacore.com>
+
+	* stab.def: Add BNSYM, ENSYM, OSO for darwin.
+
+2008-03-27  Cary Coutant <ccoutant@google.com>
+
+	* ar.h (ARMAGT): New magic string for thin archives.
+
+2005-08-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* encap.h: Remove a29k support.
+
+2005-05-10  Nick Clifton  <nickc@redhat.com>
+
+	* Update the address and phone number of the FSF organization in
+	the GPL notices in the following files:
+	adobe.h, aout64.h, ar.h, dynix3.h, encap.h, host.h, hp.h,
+	ranlib.h, reloc.h, stab.def, stab_gnu.h, sun4.h
+
+2004-01-06  Mark Kettenis  <kettenis@gnu.org>
+
+	* stab.def: Add N_PATCH to DO definition.
+
+2003-03-06  Elias Athanasopoulos  <elathan@phys.uoa.gr>
+
+	* aout64.h (BYTES_IN_WORD): Define if necessary.
+
+2001-09-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* aout64.h: Formatting fixes.
+	(N_TXTADDR): Evaluate to a bfd_vma.
+	(N_DATADDR): Avoid negative unsigned warning.
+	* hp300hpux.h: Formatting fixes.
+	(N_DATADDR): Avoid negative unsigned warning.
+
+2000-04-03  Hans-Peter Nilsson  <hp@axis.com>
+
+	* aout64.h (RELOC_EXT_BITS_EXTERN_BIG): Wrap definition in #ifndef.
+	(RELOC_EXT_BITS_EXTERN_LITTLE): Ditto.
+	(RELOC_EXT_BITS_TYPE_BIG): Ditto.
+	(RELOC_EXT_BITS_TYPE_SH_BIG): Ditto.
+	(RELOC_EXT_BITS_TYPE_LITTLE): Ditto.
+	(RELOC_EXT_BITS_TYPE_SH_LITTLE): Ditto.
+
+1999-07-12  Ian Lance Taylor  <ian@zembu.com>
+
+	* aout64.h (N_SHARED_LIB): Define as 0 if TEXT_START_ADDR is
+	defined as 0.
+
+1998-06-28  Peter Schauer  <pes@regent.e-technik.tu-muenchen.de>
+
+	* stab.def:  Add N_ALIAS from SunPro F77.
+
+1996-03-11  Ian Lance Taylor  <ian@cygnus.com>
+
+	* stab.def: Use __define_stab_duplicate rather than __define_stab
+	for duplicate entries N_BROWS and N_MOD2.
+	* stab_gnu.h (__define_stab_duplicate): Define before including
+	stab.def.
+
+1995-10-27  Niklas Hallqvist  <niklas@appli.se>
+
+	* aout64.h, host.h, hp300hpux.h, sun4.h: Changed PAGE_SIZE to
+	TARGET_PAGE_SIZE.
+
+1995-09-12  Ian Lance Taylor  <ian@cygnus.com>
+
+	* sun4.h (struct internal_sun4_dynamic_link): Change all fields
+	from long to unsigned long.
+
+1995-07-12  Ken Raeburn  <raeburn@kr-pc.cygnus.com>
+
+	* sun4.h (PAGE_SIZE): Undefine before defining.
+
+1994-09-04  Richard Earnshaw (rwe@pegasus.esprit.ec.org)
+
+	* aout64.h: Only define QMAGIC if it isn't already defined.
+
+1994-06-16  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* aout64.h (BMAGIC): Define.
+
+1994-06-11  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	Add weak symbols as an extension to a.out.
+	* aout64.h (N_WEAKU, N_WEAKA, N_WEAKT, N_WEAKD, N_WEAKB): Define.
+	* stab.def: Update symbol value table.
+
+1994-06-02  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* sun4.h (EXTERNAL_SUN4_DYNAMIC_DEBUGGER_SIZE): Correct from 28 to
+	24.  Fix up ld_got comment.
+
+1994-03-30  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
+
+	* dynix3.h:  Cleanup, adapt to current bfd version.
+
+1994-02-26  Ian Lance Taylor  (ian@cygnus.com)
+
+	* aout64.h: Add casts to avoid warnings from SVR4 cc.
+
+1994-02-11  Stan Shebs  (shebs@andros.cygnus.com)
+
+	* ar.h (ARMAG, ARMAGB, ARFMAG): Change '\n' to '\012', for greater
+	portability.
+
+1994-01-21  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* sun4.h: Added information about SunOS shared libraries.
+
+1994-01-07  Jim Kingdon  (kingdon@deneb.cygnus.com)
+
+	* aout64.h (N_TXTADDR): Add comment regarding OMAGIC and NMAGIC.
+
+1993-12-25  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* aout64.h (N_DATOFF): Don't pad (revert change of 8 Jul 1993).
+
+1993-11-16  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* aout64.h: New macros ZMAGIC_DISK_BLOCK_SIZE and N_DISK_BLOCK_SIZE
+	for Linux ZMAGIC.
+	(N_TXTOFF, N_DATOFF): Use them.
+
+1993-11-04  Ken Raeburn  (raeburn@kr-pc.cygnus.com)
+
+	* aout64.h (RELOC_STD_BITS_RELATIVE_LITTLE): Fixed value to match
+	sun3 system; used to overlap other fields.
+	(RELOC_STD_BITS_JMPTABLE_LITTLE): Likewise.
+
+1993-11-03  David J. Mackenzie  (djm@thepub.cygnus.com)
+
+	* aout64.h (RELOC_STD_BITS_BASEREL_LITTLE): Make it 0x10 (Ken's
+	suggestion) to avoid conflict with RELOC_STD_BITS_EXTERN_LITTLE.
+
+1993-10-29  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* hp300hpux.h (N_SHARED_LIB): Define to be 0.
+
+1993-09-13  John Gilmore  (gnu@cygnus.com)
+
+	* ar.h (ARMAP_TIME_OFFSET):  Add and describe.
+
+Mon Aug 23  Sean Fagan  (sef@cygnus.com)
+
+	* aout64.h [ARCH_SIZE != 64]: Allow N_BADMAG to be overridden.
+
+1993-08-16  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* stab_gnu.h: Include aout/stab.def not just stab.def.
+
+1993-07-18  Jim Kingdon  (kingdon@rtl.cygnus.com)
+
+	* dynix3.h: New, for symmetry running dynix.
+
+1993-07-08  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* aout64.h (N_BADMAG): Recognize QMAGIC.
+	N_TXTOFF, N_TXTADDR, N_TXTSIZE: Special code for QMAGIC.
+	N_DATOFF: Pad text size if we need to.
+
+1993-06-18  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* stab.def (N_ECOML): Fix comment.
+
+1993-05-31  Jim Kingdon  (kingdon@cygnus.com)
+
+	* stab.def: Remove Solaris information on N_FUN stabstring grammar;
+	I've transferred it to gdb/doc/stabs.texinfo, where it belongs.
+
+1993-05-10  Ken Raeburn  (raeburn@kr-pc.cygnus.com)
+
+	* hp300hpux.h: Patch from Glenn Engel for linker problem and
+	compatibility fix:
+	(OMAGIC, NMAGIC): New definitions.
+	(SHAREMAGIC): Deleted.
+	(HPUX_DOT_O_MAGIC): New macro.
+	(_N_BADMAG): Adjusted.
+	(N_HEADER_IN_TEXT, N_DATADDR): New macros.
+
+1993-04-29  Ken Raeburn  (raeburn@deneb.cygnus.com)
+
+	* hp300hpux.h: New file from Glenn Engel, glenne@lsid.hp.com.
+
+1993-04-27  Ken Raeburn  (raeburn@kr-pc.cygnus.com)
+
+	* aout64.h (struct external_exec, *MAGIC, N_BADMAG): Don't define
+	if `external_exec' is already defined as a macro.
+	(N_DATOFF, N_TRELOFF, N_DRELOFF, N_SYMOFF, N_STROFF): Don't define
+	if already defined.
+	(struct external_nlist, EXTERNAL_NLIST_SIZE): Don't define if
+	`external_nlist' is already defined as a macro.
+
+1992-08-15  John Gilmore  (gnu@cygnus.com)
+
+	* adobe.h:  Add description of a.out.adobe format.
+
+1992-07-03  John Gilmore  (gnu at cygnus.com)
+
+	* stab.def:  Update more Solaris definitions.
+	* stab_gnu.h:  Add N_SO language types, and Solaris basic float types.
+
+1992-06-14  John Gilmore  (gnu at cygnus.com)
+
+	* stab.def:  Update descriptions of Solaris-2 stabs; add N_UNDF.
+
+1992-06-11  John Gilmore  (gnu at cygnus.com)
+
+	* stab.def:  Add N_OBJ and N_OPT from Solaris-2.
+
+1992-01-30  John Gilmore  (gnu at cygnus.com)
+
+	* aout64.h: N_TXTSIZE needs some more parentheses.
+	I don't trust C precedence.
+
+1991-12-18  Per Bothner  (bothner at cygnus.com)
+
+	* aout64.h:  Move common sunos-specific test
+	to recognize shared libraries into new macro N_SHARED_LIB.
+	Use it to simplify & reformat N_TXTADDR, N_TXTOFF, N_TXTSIZE.
+
+1991-11-30  Steve Chamberlain  (sac at rtl.cygnus.com)
+
+	* aout64.h, ar.h, encap.h, host.h, hp.h, ranlib.h, reloc.h,
+	stab.def, stab_gnu.h, sun4.h: All moved from the devo/include
+	directory.
+
+
+Copyright (C) 1991-2012 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.25/include/aout/adobe.h b/binutils-2.25/include/aout/adobe.h
new file mode 100644
index 00000000..ce225527
--- /dev/null
+++ b/binutils-2.25/include/aout/adobe.h
@@ -0,0 +1,314 @@
+/* `a.out.adobe' differences from standard a.out files
+
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef __A_OUT_ADOBE_H__
+#define __A_OUT_ADOBE_H__
+
+#define	BYTES_IN_WORD	4
+
+/* Struct external_exec is the same.  */
+
+/* This is the layout on disk of the 32-bit or 64-bit exec header. */
+
+struct external_exec 
+{
+  bfd_byte e_info[4];		/* magic number and stuff		*/
+  bfd_byte e_text[BYTES_IN_WORD]; /* length of text section in bytes	*/
+  bfd_byte e_data[BYTES_IN_WORD]; /* length of data section in bytes	*/
+  bfd_byte e_bss[BYTES_IN_WORD]; /* length of bss area in bytes 	*/
+  bfd_byte e_syms[BYTES_IN_WORD]; /* length of symbol table in bytes 	*/
+  bfd_byte e_entry[BYTES_IN_WORD]; /* start address 			*/
+  bfd_byte e_trsize[BYTES_IN_WORD]; /* length of text relocation info	*/
+  bfd_byte e_drsize[BYTES_IN_WORD]; /* length of data relocation info 	*/
+};
+
+#define	EXEC_BYTES_SIZE	(4 + BYTES_IN_WORD * 7)
+
+/* Magic numbers for a.out files */
+
+#undef	ZMAGIC
+#define	ZMAGIC	0xAD0BE		/* Cute, eh?  */
+#undef	OMAGIC
+#undef	NMAGIC
+
+#define N_BADMAG(x)	  ((x).a_info != ZMAGIC)
+
+/* By default, segment size is constant.  But some machines override this
+   to be a function of the a.out header (e.g. machine type).  */
+#ifndef	N_SEGSIZE
+#define	N_SEGSIZE(x)	SEGMENT_SIZE
+#endif
+#undef N_SEGSIZE   /* FIXMEXXXX */
+
+/* Segment information for the a.out.Adobe format is specified after the
+   file header.  It contains N segment descriptors, followed by one with
+   a type of zero.  
+
+   The actual text of the segments starts at N_TXTOFF in the file,
+   regardless of how many or how few segment headers there are.  */
+
+struct external_segdesc {
+	unsigned char e_type[1];
+	unsigned char e_size[3];
+	unsigned char e_virtbase[4];
+	unsigned char e_filebase[4];
+};
+
+struct internal_segdesc {
+	unsigned int	a_type:8;	/* Segment type N_TEXT, N_DATA, 0 */
+	unsigned int 	a_size:24;	/* Segment size */
+	bfd_vma		a_virtbase;	/* Virtual address */
+	unsigned int	a_filebase;	/* Base address in object file */
+};
+
+#define N_TXTADDR(x) \
+
+/* This is documented to be at 1024, but appears to really be at 2048.
+   FIXME?!  */
+#define N_TXTOFF(x)	2048
+
+#define	N_TXTSIZE(x) ((x).a_text)
+
+#define N_DATADDR(x)
+
+#define N_BSSADDR(x)
+
+/* Offsets of the various portions of the file after the text segment.  */
+
+#define N_DATOFF(x)	( N_TXTOFF(x) + N_TXTSIZE(x) )
+#define N_TRELOFF(x)	( N_DATOFF(x) + (x).a_data )
+#define N_DRELOFF(x)	( N_TRELOFF(x) + (x).a_trsize )
+#define N_SYMOFF(x)	( N_DRELOFF(x) + (x).a_drsize )
+#define N_STROFF(x)	( N_SYMOFF(x) + (x).a_syms )
+
+/* Symbols */
+struct external_nlist {
+  bfd_byte e_strx[BYTES_IN_WORD];	/* index into string table of name */
+  bfd_byte e_type[1];			/* type of symbol */
+  bfd_byte e_other[1];			/* misc info (usually empty) */
+  bfd_byte e_desc[2];			/* description field */
+  bfd_byte e_value[BYTES_IN_WORD];	/* value of symbol */
+};
+
+#define EXTERNAL_NLIST_SIZE (BYTES_IN_WORD+4+BYTES_IN_WORD)
+
+struct internal_nlist {
+  unsigned long n_strx;			/* index into string table of name */
+  unsigned char n_type;			/* type of symbol */
+  unsigned char n_other;		/* misc info (usually empty) */
+  unsigned short n_desc;		/* description field */
+  bfd_vma n_value;			/* value of symbol */
+};
+
+/* The n_type field is the symbol type, containing:  */
+
+#define N_UNDF	0	/* Undefined symbol */
+#define N_ABS 	2	/* Absolute symbol -- defined at particular addr */
+#define N_TEXT 	4	/* Text sym -- defined at offset in text seg */
+#define N_DATA 	6	/* Data sym -- defined at offset in data seg */
+#define N_BSS 	8	/* BSS  sym -- defined at offset in zero'd seg */
+#define	N_COMM	0x12	/* Common symbol (visible after shared lib dynlink) */
+#define N_FN	0x1f	/* File name of .o file */
+#define	N_FN_SEQ 0x0C	/* N_FN from Sequent compilers (sigh) */
+/* Note: N_EXT can only be usefully OR-ed with N_UNDF, N_ABS, N_TEXT,
+   N_DATA, or N_BSS.  When the low-order bit of other types is set,
+   (e.g. N_WARNING versus N_FN), they are two different types.  */
+#define N_EXT 	1	/* External symbol (as opposed to local-to-this-file) */
+#define N_TYPE  0x1e
+#define N_STAB 	0xe0	/* If any of these bits are on, it's a debug symbol */
+
+#define N_INDR 0x0a
+
+/* The following symbols refer to set elements.
+   All the N_SET[ATDB] symbols with the same name form one set.
+   Space is allocated for the set in the text section, and each set
+   elements value is stored into one word of the space.
+   The first word of the space is the length of the set (number of elements).
+
+   The address of the set is made into an N_SETV symbol
+   whose name is the same as the name of the set.
+   This symbol acts like a N_DATA global symbol
+   in that it can satisfy undefined external references.  */
+
+/* These appear as input to LD, in a .o file.  */
+#define	N_SETA	0x14		/* Absolute set element symbol */
+#define	N_SETT	0x16		/* Text set element symbol */
+#define	N_SETD	0x18		/* Data set element symbol */
+#define	N_SETB	0x1A		/* Bss set element symbol */
+
+/* This is output from LD.  */
+#define N_SETV	0x1C		/* Pointer to set vector in data area.  */
+
+/* Warning symbol. The text gives a warning message, the next symbol
+   in the table will be undefined. When the symbol is referenced, the
+   message is printed.  */
+
+#define	N_WARNING 0x1e
+
+/* Relocations 
+
+  There	are two types of relocation flavours for a.out systems,
+  standard and extended. The standard form is used on systems where the
+  instruction has room for all the bits of an offset to the operand, whilst
+  the extended form is used when an address operand has to be split over n
+  instructions. Eg, on the 68k, each move instruction can reference
+  the target with a displacement of 16 or 32 bits. On the sparc, move
+  instructions use an offset of 14 bits, so the offset is stored in
+  the reloc field, and the data in the section is ignored.
+*/
+
+/* This structure describes a single relocation to be performed.
+   The text-relocation section of the file is a vector of these structures,
+   all of which apply to the text section.
+   Likewise, the data-relocation section applies to the data section.  */
+
+struct reloc_std_external {
+  bfd_byte r_address[BYTES_IN_WORD];	/* offset of of data to relocate */
+  bfd_byte r_index[3];	/* symbol table index of symbol 	*/
+  bfd_byte r_type[1];	/* relocation type			*/
+};
+
+#define	RELOC_STD_BITS_PCREL_BIG	0x80
+#define	RELOC_STD_BITS_PCREL_LITTLE	0x01
+
+#define	RELOC_STD_BITS_LENGTH_BIG	0x60
+#define	RELOC_STD_BITS_LENGTH_SH_BIG	5	/* To shift to units place */
+#define	RELOC_STD_BITS_LENGTH_LITTLE	0x06
+#define	RELOC_STD_BITS_LENGTH_SH_LITTLE	1
+
+#define	RELOC_STD_BITS_EXTERN_BIG	0x10
+#define	RELOC_STD_BITS_EXTERN_LITTLE	0x08
+
+#define	RELOC_STD_BITS_BASEREL_BIG	0x08
+#define	RELOC_STD_BITS_BASEREL_LITTLE	0x08
+
+#define	RELOC_STD_BITS_JMPTABLE_BIG	0x04
+#define	RELOC_STD_BITS_JMPTABLE_LITTLE	0x04
+
+#define	RELOC_STD_BITS_RELATIVE_BIG	0x02
+#define	RELOC_STD_BITS_RELATIVE_LITTLE	0x02
+
+#define	RELOC_STD_SIZE	(BYTES_IN_WORD + 3 + 1)		/* Bytes per relocation entry */
+
+struct reloc_std_internal
+{
+  bfd_vma r_address;		/* Address (within segment) to be relocated.  */
+  /* The meaning of r_symbolnum depends on r_extern.  */
+  unsigned int r_symbolnum:24;
+  /* Nonzero means value is a pc-relative offset
+     and it should be relocated for changes in its own address
+     as well as for changes in the symbol or section specified.  */
+  unsigned int r_pcrel:1;
+  /* Length (as exponent of 2) of the field to be relocated.
+     Thus, a value of 2 indicates 1<<2 bytes.  */
+  unsigned int r_length:2;
+  /* 1 => relocate with value of symbol.
+     r_symbolnum is the index of the symbol
+     in files the symbol table.
+     0 => relocate with the address of a segment.
+     r_symbolnum is N_TEXT, N_DATA, N_BSS or N_ABS
+     (the N_EXT bit may be set also, but signifies nothing).  */
+  unsigned int r_extern:1;
+  /* The next three bits are for SunOS shared libraries, and seem to
+     be undocumented.  */
+  unsigned int r_baserel:1;	/* Linkage table relative */
+  unsigned int r_jmptable:1;	/* pc-relative to jump table */
+  unsigned int r_relative:1;	/* "relative relocation" */
+  /* unused */
+  unsigned int r_pad:1;		/* Padding -- set to zero */
+};
+
+
+/* EXTENDED RELOCS  */
+
+struct reloc_ext_external {
+  bfd_byte r_address[BYTES_IN_WORD];	/* offset of of data to relocate 	*/
+  bfd_byte r_index[3];	/* symbol table index of symbol 	*/
+  bfd_byte r_type[1];	/* relocation type			*/
+  bfd_byte r_addend[BYTES_IN_WORD];	/* datum addend				*/
+};
+
+#define	RELOC_EXT_BITS_EXTERN_BIG	0x80
+#define	RELOC_EXT_BITS_EXTERN_LITTLE	0x01
+
+#define	RELOC_EXT_BITS_TYPE_BIG		0x1F
+#define	RELOC_EXT_BITS_TYPE_SH_BIG	0
+#define	RELOC_EXT_BITS_TYPE_LITTLE	0xF8
+#define	RELOC_EXT_BITS_TYPE_SH_LITTLE	3
+
+/* Bytes per relocation entry */
+#define	RELOC_EXT_SIZE	(BYTES_IN_WORD + 3 + 1 + BYTES_IN_WORD)
+
+enum reloc_type
+{
+  /* simple relocations */
+  RELOC_8,			/* data[0:7] = addend + sv 		*/
+  RELOC_16,			/* data[0:15] = addend + sv 		*/
+  RELOC_32,			/* data[0:31] = addend + sv 		*/
+  /* pc-rel displacement */
+  RELOC_DISP8,			/* data[0:7] = addend - pc + sv 	*/
+  RELOC_DISP16,			/* data[0:15] = addend - pc + sv 	*/
+  RELOC_DISP32,			/* data[0:31] = addend - pc + sv 	*/
+  /* Special */
+  RELOC_WDISP30,		/* data[0:29] = (addend + sv - pc)>>2 	*/
+  RELOC_WDISP22,		/* data[0:21] = (addend + sv - pc)>>2 	*/
+  RELOC_HI22,			/* data[0:21] = (addend + sv)>>10 	*/
+  RELOC_22,			/* data[0:21] = (addend + sv) 		*/
+  RELOC_13,			/* data[0:12] = (addend + sv)		*/
+  RELOC_LO10,			/* data[0:9] = (addend + sv)		*/
+  RELOC_SFA_BASE,		
+  RELOC_SFA_OFF13,
+  /* P.I.C. (base-relative) */
+  RELOC_BASE10,  		/* Not sure - maybe we can do this the */
+  RELOC_BASE13,			/* right way now */
+  RELOC_BASE22,
+  /* for some sort of pc-rel P.I.C. (?) */
+  RELOC_PC10,
+  RELOC_PC22,
+  /* P.I.C. jump table */
+  RELOC_JMP_TBL,
+  /* reputedly for shared libraries somehow */
+  RELOC_SEGOFF16,
+  RELOC_GLOB_DAT,
+  RELOC_JMP_SLOT,
+  RELOC_RELATIVE,
+
+  RELOC_11,	
+  RELOC_WDISP2_14,
+  RELOC_WDISP19,
+  RELOC_HHI22,			/* data[0:21] = (addend + sv) >> 42     */
+  RELOC_HLO10,			/* data[0:9] = (addend + sv) >> 32      */
+  
+  /* 29K relocation types */
+  RELOC_JUMPTARG,
+  RELOC_CONST,
+  RELOC_CONSTH,
+  
+  NO_RELOC
+  };
+
+
+struct reloc_internal {
+  bfd_vma r_address;		/* offset of of data to relocate 	*/
+  long	r_index;		/* symbol table index of symbol 	*/
+  enum reloc_type r_type;	/* relocation type			*/
+  bfd_vma r_addend;		/* datum addend				*/
+};
+
+#endif				/* __A_OUT_ADOBE_H__ */
diff --git a/binutils-2.25/include/aout/aout64.h b/binutils-2.25/include/aout/aout64.h
new file mode 100644
index 00000000..384909e0
--- /dev/null
+++ b/binutils-2.25/include/aout/aout64.h
@@ -0,0 +1,516 @@
+/* `a.out' object-file definitions, including extensions to 64-bit fields
+
+   Copyright 1999, 2000, 2001, 2003, 2009, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef __A_OUT_64_H__
+#define __A_OUT_64_H__
+
+#ifndef BYTES_IN_WORD
+#define BYTES_IN_WORD 4
+#endif
+
+/* This is the layout on disk of the 32-bit or 64-bit exec header.  */
+
+#ifndef external_exec
+struct external_exec 
+{
+  bfd_byte e_info[4];		    /* Magic number and stuff.  */
+  bfd_byte e_text[BYTES_IN_WORD];   /* Length of text section in bytes.  */
+  bfd_byte e_data[BYTES_IN_WORD];   /* Length of data section in bytes.  */
+  bfd_byte e_bss[BYTES_IN_WORD];    /* Length of bss area in bytes.  */
+  bfd_byte e_syms[BYTES_IN_WORD];   /* Length of symbol table in bytes.  */
+  bfd_byte e_entry[BYTES_IN_WORD];  /* Start address.  */
+  bfd_byte e_trsize[BYTES_IN_WORD]; /* Length of text relocation info.  */
+  bfd_byte e_drsize[BYTES_IN_WORD]; /* Length of data relocation info.  */
+};
+
+#define	EXEC_BYTES_SIZE	(4 + BYTES_IN_WORD * 7)
+
+/* Magic numbers for a.out files.  */
+
+#if ARCH_SIZE==64
+#define OMAGIC 0x1001		/* Code indicating object file.  */
+#define ZMAGIC 0x1002		/* Code indicating demand-paged executable.  */
+#define NMAGIC 0x1003		/* Code indicating pure executable.  */
+
+/* There is no 64-bit QMAGIC as far as I know.  */
+
+#define N_BADMAG(x)	  (N_MAGIC(x) != OMAGIC		\
+			&& N_MAGIC(x) != NMAGIC		\
+  			&& N_MAGIC(x) != ZMAGIC)
+#else
+#define OMAGIC 0407		/* Object file or impure executable.  */
+#define NMAGIC 0410		/* Code indicating pure executable.  */
+#define ZMAGIC 0413		/* Code indicating demand-paged executable.  */
+#define BMAGIC 0415		/* Used by a b.out object.  */
+
+/* This indicates a demand-paged executable with the header in the text.
+   It is used by 386BSD (and variants) and Linux, at least.  */
+#ifndef QMAGIC
+#define QMAGIC 0314
+#endif
+# ifndef N_BADMAG
+#  define N_BADMAG(x)	  (N_MAGIC(x) != OMAGIC		\
+			&& N_MAGIC(x) != NMAGIC		\
+  			&& N_MAGIC(x) != ZMAGIC \
+		        && N_MAGIC(x) != QMAGIC)
+# endif /* N_BADMAG */
+#endif
+
+#endif
+
+#ifdef QMAGIC
+#define N_IS_QMAGIC(x) (N_MAGIC (x) == QMAGIC)
+#else
+#define N_IS_QMAGIC(x) (0)
+#endif
+
+/* The difference between TARGET_PAGE_SIZE and N_SEGSIZE is that TARGET_PAGE_SIZE is
+   the finest granularity at which you can page something, thus it
+   controls the padding (if any) before the text segment of a ZMAGIC
+   file.  N_SEGSIZE is the resolution at which things can be marked as
+   read-only versus read/write, so it controls the padding between the
+   text segment and the data segment (in memory; on disk the padding
+   between them is TARGET_PAGE_SIZE).  TARGET_PAGE_SIZE and N_SEGSIZE are the same
+   for most machines, but different for sun3.  */
+
+/* By default, segment size is constant.  But some machines override this
+   to be a function of the a.out header (e.g. machine type).  */
+
+#ifndef	N_SEGSIZE
+#define	N_SEGSIZE(x)	SEGMENT_SIZE
+#endif
+
+/* Virtual memory address of the text section.
+   This is getting very complicated.  A good reason to discard a.out format
+   for something that specifies these fields explicitly.  But til then...
+
+   * OMAGIC and NMAGIC files:
+       (object files: text for "relocatable addr 0" right after the header)
+       start at 0, offset is EXEC_BYTES_SIZE, size as stated.
+   * The text address, offset, and size of ZMAGIC files depend
+     on the entry point of the file:
+     * entry point below TEXT_START_ADDR:
+       (hack for SunOS shared libraries)
+       start at 0, offset is 0, size as stated.
+     * If N_HEADER_IN_TEXT(x) is true (which defaults to being the
+       case when the entry point is EXEC_BYTES_SIZE or further into a page):
+       no padding is needed; text can start after exec header.  Sun
+       considers the text segment of such files to include the exec header;
+       for BFD's purposes, we don't, which makes more work for us.
+       start at TEXT_START_ADDR + EXEC_BYTES_SIZE, offset is EXEC_BYTES_SIZE,
+       size as stated minus EXEC_BYTES_SIZE.
+     * If N_HEADER_IN_TEXT(x) is false (which defaults to being the case when
+       the entry point is less than EXEC_BYTES_SIZE into a page (e.g. page
+       aligned)): (padding is needed so that text can start at a page boundary)
+       start at TEXT_START_ADDR, offset TARGET_PAGE_SIZE, size as stated.
+
+    Specific configurations may want to hardwire N_HEADER_IN_TEXT,
+    for efficiency or to allow people to play games with the entry point.
+    In that case, you would #define N_HEADER_IN_TEXT(x) as 1 for sunos,
+    and as 0 for most other hosts (Sony News, Vax Ultrix, etc).
+    (Do this in the appropriate bfd target file.)
+    (The default is a heuristic that will break if people try changing
+    the entry point, perhaps with the ld -e flag.)
+
+    * QMAGIC is always like a ZMAGIC for which N_HEADER_IN_TEXT is true,
+    and for which the starting address is TARGET_PAGE_SIZE (or should this be
+    SEGMENT_SIZE?) (TEXT_START_ADDR only applies to ZMAGIC, not to QMAGIC).  */
+
+/* This macro is only relevant for ZMAGIC files; QMAGIC always has the header
+   in the text.  */
+#ifndef N_HEADER_IN_TEXT
+#define N_HEADER_IN_TEXT(x) \
+  (((x).a_entry & (TARGET_PAGE_SIZE-1)) >= EXEC_BYTES_SIZE)
+#endif
+
+/* Sun shared libraries, not linux.  This macro is only relevant for ZMAGIC
+   files.  */
+#ifndef N_SHARED_LIB
+#define N_SHARED_LIB(x) (0)
+#endif
+
+/* Returning 0 not TEXT_START_ADDR for OMAGIC and NMAGIC is based on
+   the assumption that we are dealing with a .o file, not an
+   executable.  This is necessary for OMAGIC (but means we don't work
+   right on the output from ld -N); more questionable for NMAGIC.  */
+
+#ifndef N_TXTADDR
+#define N_TXTADDR(x) \
+    (/* The address of a QMAGIC file is always one page in,		\
+        with the header in the text.  */				\
+     N_IS_QMAGIC (x)							\
+     ? (bfd_vma) TARGET_PAGE_SIZE + EXEC_BYTES_SIZE			\
+     : (N_MAGIC (x) != ZMAGIC						\
+	? (bfd_vma) 0	/* Object file or NMAGIC.  */			\
+	: (N_SHARED_LIB (x)						\
+	   ? (bfd_vma) 0						\
+	   : (N_HEADER_IN_TEXT (x)					\
+	      ? (bfd_vma) TEXT_START_ADDR + EXEC_BYTES_SIZE		\
+	      : (bfd_vma) TEXT_START_ADDR))))
+#endif
+
+/* If N_HEADER_IN_TEXT is not true for ZMAGIC, there is some padding
+   to make the text segment start at a certain boundary.  For most
+   systems, this boundary is TARGET_PAGE_SIZE.  But for Linux, in the
+   time-honored tradition of crazy ZMAGIC hacks, it is 1024 which is
+   not what TARGET_PAGE_SIZE needs to be for QMAGIC.  */
+
+#ifndef ZMAGIC_DISK_BLOCK_SIZE
+#define ZMAGIC_DISK_BLOCK_SIZE TARGET_PAGE_SIZE
+#endif
+
+#define N_DISK_BLOCK_SIZE(x) \
+  (N_MAGIC(x) == ZMAGIC ? ZMAGIC_DISK_BLOCK_SIZE : TARGET_PAGE_SIZE)
+
+/* Offset in an a.out of the start of the text section. */
+#ifndef N_TXTOFF
+#define N_TXTOFF(x)							\
+    (/* For {O,N,Q}MAGIC, no padding.  */				\
+     N_MAGIC (x) != ZMAGIC						\
+     ? EXEC_BYTES_SIZE							\
+     : (N_SHARED_LIB (x)						\
+	? 0								\
+	: (N_HEADER_IN_TEXT (x)						\
+	   ? EXEC_BYTES_SIZE		/* No padding.  */		\
+	   : ZMAGIC_DISK_BLOCK_SIZE	/* A page of padding.  */)))
+#endif
+/* Size of the text section.  It's always as stated, except that we
+   offset it to `undo' the adjustment to N_TXTADDR and N_TXTOFF
+   for ZMAGIC files that nominally include the exec header
+   as part of the first page of text.  (BFD doesn't consider the
+   exec header to be part of the text segment.)  */
+#ifndef N_TXTSIZE
+#define	N_TXTSIZE(x) \
+  (/* For QMAGIC, we don't consider the header part of the text section.  */\
+   N_IS_QMAGIC (x)							\
+   ? (x).a_text - EXEC_BYTES_SIZE					\
+   : ((N_MAGIC (x) != ZMAGIC || N_SHARED_LIB (x))			\
+      ? (x).a_text							\
+      : (N_HEADER_IN_TEXT (x)						\
+	 ? (x).a_text - EXEC_BYTES_SIZE	/* No padding.  */		\
+	 : (x).a_text			/* A page of padding.  */ )))
+#endif
+/* The address of the data segment in virtual memory.
+   It is the text segment address, plus text segment size, rounded
+   up to a N_SEGSIZE boundary for pure or pageable files.  */
+#ifndef N_DATADDR
+#define N_DATADDR(x) \
+  (N_MAGIC (x) == OMAGIC						\
+   ? (N_TXTADDR (x) + N_TXTSIZE (x))					\
+   : (N_SEGSIZE (x) + ((N_TXTADDR (x) + N_TXTSIZE (x) - 1)		\
+		       & ~ (bfd_vma) (N_SEGSIZE (x) - 1))))
+#endif
+/* The address of the BSS segment -- immediately after the data segment.  */
+
+#define N_BSSADDR(x)	(N_DATADDR (x) + (x).a_data)
+
+/* Offsets of the various portions of the file after the text segment.  */
+
+/* For {Q,Z}MAGIC, there is padding to make the data segment start on
+   a page boundary.  Most of the time the a_text field (and thus
+   N_TXTSIZE) already contains this padding.  It is possible that for
+   BSDI and/or 386BSD it sometimes doesn't contain the padding, and
+   perhaps we should be adding it here.  But this seems kind of
+   questionable and probably should be BSDI/386BSD-specific if we do
+   do it.
+
+   For NMAGIC (at least for hp300 BSD, probably others), there is
+   padding in memory only, not on disk, so we must *not* ever pad here
+   for NMAGIC.  */
+
+#ifndef N_DATOFF
+#define N_DATOFF(x)	(N_TXTOFF (x) + N_TXTSIZE (x))
+#endif
+#ifndef N_TRELOFF
+#define N_TRELOFF(x)	(N_DATOFF (x) + (x).a_data)
+#endif
+#ifndef N_DRELOFF
+#define N_DRELOFF(x)	(N_TRELOFF (x) + (x).a_trsize)
+#endif
+#ifndef N_SYMOFF
+#define N_SYMOFF(x)	(N_DRELOFF (x) + (x).a_drsize)
+#endif
+#ifndef N_STROFF
+#define N_STROFF(x)	(N_SYMOFF (x) + (x).a_syms)
+#endif
+
+/* Symbols */
+#ifndef external_nlist
+struct external_nlist
+{
+  bfd_byte e_strx[BYTES_IN_WORD];	/* Index into string table of name.  */
+  bfd_byte e_type[1];			/* Type of symbol.  */
+  bfd_byte e_other[1];			/* Misc info (usually empty).  */
+  bfd_byte e_desc[2];			/* Description field.  */
+  bfd_byte e_value[BYTES_IN_WORD];	/* Value of symbol.  */
+};
+#define EXTERNAL_NLIST_SIZE (BYTES_IN_WORD+4+BYTES_IN_WORD)
+#endif
+
+struct internal_nlist
+{
+  unsigned long n_strx;			/* Index into string table of name.  */
+  unsigned char n_type;			/* Type of symbol.  */
+  unsigned char n_other;		/* Misc info (usually empty).  */
+  unsigned short n_desc;		/* Description field.  */
+  bfd_vma n_value;			/* Value of symbol.  */
+};
+
+/* The n_type field is the symbol type, containing:  */
+
+#define N_UNDF	0	/* Undefined symbol.  */
+#define N_ABS 	2	/* Absolute symbol -- defined at particular addr.  */
+#define N_TEXT 	4	/* Text sym -- defined at offset in text seg.  */
+#define N_DATA 	6	/* Data sym -- defined at offset in data seg.  */
+#define N_BSS 	8	/* BSS  sym -- defined at offset in zero'd seg.  */
+#define	N_COMM	0x12	/* Common symbol (visible after shared lib dynlink).  */
+#define N_FN	0x1f	/* File name of .o file.  */
+#define	N_FN_SEQ 0x0C	/* N_FN from Sequent compilers (sigh).  */
+/* Note: N_EXT can only be usefully OR-ed with N_UNDF, N_ABS, N_TEXT,
+   N_DATA, or N_BSS.  When the low-order bit of other types is set,
+   (e.g. N_WARNING versus N_FN), they are two different types.  */
+#define N_EXT 	1	/* External symbol (as opposed to local-to-this-file).  */
+#define N_TYPE  0x1e
+#define N_STAB 	0xe0	/* If any of these bits are on, it's a debug symbol.  */
+
+#define N_INDR 0x0a
+
+/* The following symbols refer to set elements.
+   All the N_SET[ATDB] symbols with the same name form one set.
+   Space is allocated for the set in the text section, and each set
+   elements value is stored into one word of the space.
+   The first word of the space is the length of the set (number of elements).
+
+   The address of the set is made into an N_SETV symbol
+   whose name is the same as the name of the set.
+   This symbol acts like a N_DATA global symbol
+   in that it can satisfy undefined external references.  */
+
+/* These appear as input to LD, in a .o file.  */
+#define	N_SETA	0x14		/* Absolute set element symbol.  */
+#define	N_SETT	0x16		/* Text set element symbol.  */
+#define	N_SETD	0x18		/* Data set element symbol.  */
+#define	N_SETB	0x1A		/* Bss set element symbol.  */
+
+/* This is output from LD.  */
+#define N_SETV	0x1C		/* Pointer to set vector in data area.  */
+
+/* Warning symbol. The text gives a warning message, the next symbol
+   in the table will be undefined. When the symbol is referenced, the
+   message is printed.  */
+
+#define	N_WARNING 0x1e
+
+/* Weak symbols.  These are a GNU extension to the a.out format.  The
+   semantics are those of ELF weak symbols.  Weak symbols are always
+   externally visible.  The N_WEAK? values are squeezed into the
+   available slots.  The value of a N_WEAKU symbol is 0.  The values
+   of the other types are the definitions.  */
+#define N_WEAKU	0x0d		/* Weak undefined symbol.  */
+#define N_WEAKA 0x0e		/* Weak absolute symbol.  */
+#define N_WEAKT 0x0f		/* Weak text symbol.  */
+#define N_WEAKD 0x10		/* Weak data symbol.  */
+#define N_WEAKB 0x11		/* Weak bss symbol.  */
+
+/* Relocations 
+
+  There	are two types of relocation flavours for a.out systems,
+  standard and extended. The standard form is used on systems where the
+  instruction has room for all the bits of an offset to the operand, whilst
+  the extended form is used when an address operand has to be split over n
+  instructions. Eg, on the 68k, each move instruction can reference
+  the target with a displacement of 16 or 32 bits. On the sparc, move
+  instructions use an offset of 14 bits, so the offset is stored in
+  the reloc field, and the data in the section is ignored.  */
+
+/* This structure describes a single relocation to be performed.
+   The text-relocation section of the file is a vector of these structures,
+   all of which apply to the text section.
+   Likewise, the data-relocation section applies to the data section.  */
+
+struct reloc_std_external
+{
+  bfd_byte r_address[BYTES_IN_WORD];	/* Offset of of data to relocate.  */
+  bfd_byte r_index[3];			/* Symbol table index of symbol.  */
+  bfd_byte r_type[1];			/* Relocation type.  */
+};
+
+#define	RELOC_STD_BITS_PCREL_BIG	((unsigned int) 0x80)
+#define	RELOC_STD_BITS_PCREL_LITTLE	((unsigned int) 0x01)
+
+#define	RELOC_STD_BITS_LENGTH_BIG	((unsigned int) 0x60)
+#define	RELOC_STD_BITS_LENGTH_SH_BIG	5
+#define	RELOC_STD_BITS_LENGTH_LITTLE	((unsigned int) 0x06)
+#define	RELOC_STD_BITS_LENGTH_SH_LITTLE	1
+
+#define	RELOC_STD_BITS_EXTERN_BIG	((unsigned int) 0x10)
+#define	RELOC_STD_BITS_EXTERN_LITTLE	((unsigned int) 0x08)
+
+#define	RELOC_STD_BITS_BASEREL_BIG	((unsigned int) 0x08)
+#define	RELOC_STD_BITS_BASEREL_LITTLE	((unsigned int) 0x10)
+
+#define	RELOC_STD_BITS_JMPTABLE_BIG	((unsigned int) 0x04)
+#define	RELOC_STD_BITS_JMPTABLE_LITTLE	((unsigned int) 0x20)
+
+#define	RELOC_STD_BITS_RELATIVE_BIG	((unsigned int) 0x02)
+#define	RELOC_STD_BITS_RELATIVE_LITTLE	((unsigned int) 0x40)
+
+#define	RELOC_STD_SIZE	(BYTES_IN_WORD + 3 + 1)		/* Bytes per relocation entry.  */
+
+struct reloc_std_internal
+{
+  bfd_vma r_address;		/* Address (within segment) to be relocated.  */
+  /* The meaning of r_symbolnum depends on r_extern.  */
+  unsigned int r_symbolnum:24;
+  /* Nonzero means value is a pc-relative offset
+     and it should be relocated for changes in its own address
+     as well as for changes in the symbol or section specified.  */
+  unsigned int r_pcrel:1;
+  /* Length (as exponent of 2) of the field to be relocated.
+     Thus, a value of 2 indicates 1<<2 bytes.  */
+  unsigned int r_length:2;
+  /* 1 => relocate with value of symbol.
+     r_symbolnum is the index of the symbol
+     in files the symbol table.
+     0 => relocate with the address of a segment.
+     r_symbolnum is N_TEXT, N_DATA, N_BSS or N_ABS
+     (the N_EXT bit may be set also, but signifies nothing).  */
+  unsigned int r_extern:1;
+  /* The next three bits are for SunOS shared libraries, and seem to
+     be undocumented.  */
+  unsigned int r_baserel:1;	/* Linkage table relative.  */
+  unsigned int r_jmptable:1;	/* pc-relative to jump table.  */
+  unsigned int r_relative:1;	/* "relative relocation".  */
+  /* unused */
+  unsigned int r_pad:1;		/* Padding -- set to zero.  */
+};
+
+
+/* EXTENDED RELOCS.   */
+
+struct reloc_ext_external
+{
+  bfd_byte r_address[BYTES_IN_WORD];	/* Offset of of data to relocate.  */
+  bfd_byte r_index[3];			/* Symbol table index of symbol.  */
+  bfd_byte r_type[1];			/* Relocation type.  */
+  bfd_byte r_addend[BYTES_IN_WORD];	/* Datum addend.  */
+};
+
+#ifndef RELOC_EXT_BITS_EXTERN_BIG
+#define	RELOC_EXT_BITS_EXTERN_BIG	((unsigned int) 0x80)
+#endif
+
+#ifndef RELOC_EXT_BITS_EXTERN_LITTLE
+#define	RELOC_EXT_BITS_EXTERN_LITTLE	((unsigned int) 0x01)
+#endif
+
+#ifndef RELOC_EXT_BITS_TYPE_BIG
+#define	RELOC_EXT_BITS_TYPE_BIG		((unsigned int) 0x1F)
+#endif
+
+#ifndef RELOC_EXT_BITS_TYPE_SH_BIG
+#define	RELOC_EXT_BITS_TYPE_SH_BIG	0
+#endif
+
+#ifndef RELOC_EXT_BITS_TYPE_LITTLE
+#define	RELOC_EXT_BITS_TYPE_LITTLE	((unsigned int) 0xF8)
+#endif
+
+#ifndef RELOC_EXT_BITS_TYPE_SH_LITTLE
+#define	RELOC_EXT_BITS_TYPE_SH_LITTLE	3
+#endif
+
+/* Bytes per relocation entry.  */
+#define	RELOC_EXT_SIZE	(BYTES_IN_WORD + 3 + 1 + BYTES_IN_WORD)
+
+enum reloc_type
+{
+  /* Simple relocations.  */
+  RELOC_8,			/* data[0:7] = addend + sv 		*/
+  RELOC_16,			/* data[0:15] = addend + sv 		*/
+  RELOC_32,			/* data[0:31] = addend + sv 		*/
+  /* PC-rel displacement.  */
+  RELOC_DISP8,			/* data[0:7] = addend - pc + sv 	*/
+  RELOC_DISP16,			/* data[0:15] = addend - pc + sv 	*/
+  RELOC_DISP32,			/* data[0:31] = addend - pc + sv 	*/
+  /* Special.  */
+  RELOC_WDISP30,		/* data[0:29] = (addend + sv - pc)>>2 	*/
+  RELOC_WDISP22,		/* data[0:21] = (addend + sv - pc)>>2 	*/
+  RELOC_HI22,			/* data[0:21] = (addend + sv)>>10 	*/
+  RELOC_22,			/* data[0:21] = (addend + sv) 		*/
+  RELOC_13,			/* data[0:12] = (addend + sv)		*/
+  RELOC_LO10,			/* data[0:9] = (addend + sv)		*/
+  RELOC_SFA_BASE,		
+  RELOC_SFA_OFF13,
+  /* P.I.C. (base-relative).  */
+  RELOC_BASE10,  		/* Not sure - maybe we can do this the */
+  RELOC_BASE13,			/* right way now */
+  RELOC_BASE22,
+  /* For some sort of pc-rel P.I.C. (?)  */
+  RELOC_PC10,
+  RELOC_PC22,
+  /* P.I.C. jump table.  */
+  RELOC_JMP_TBL,
+  /* Reputedly for shared libraries somehow.  */
+  RELOC_SEGOFF16,
+  RELOC_GLOB_DAT,
+  RELOC_JMP_SLOT,
+  RELOC_RELATIVE,
+
+  RELOC_11,	
+  RELOC_WDISP2_14,
+  RELOC_WDISP19,
+  RELOC_HHI22,			/* data[0:21] = (addend + sv) >> 42     */
+  RELOC_HLO10,			/* data[0:9] = (addend + sv) >> 32      */
+  
+  /* 29K relocation types.  */
+  RELOC_JUMPTARG,
+  RELOC_CONST,
+  RELOC_CONSTH,
+  
+  /* All the new ones I can think of, for sparc v9.  */
+  RELOC_64,			/* data[0:63] = addend + sv 		*/
+  RELOC_DISP64,			/* data[0:63] = addend - pc + sv 	*/
+  RELOC_WDISP21,		/* data[0:20] = (addend + sv - pc)>>2 	*/
+  RELOC_DISP21,			/* data[0:20] = addend - pc + sv        */
+  RELOC_DISP14,			/* data[0:13] = addend - pc + sv 	*/
+  /* Q .
+     What are the other ones,
+     Since this is a clean slate, can we throw away the ones we dont
+     understand ? Should we sort the values ? What about using a
+     microcode format like the 68k ?  */
+  NO_RELOC
+  };
+
+
+struct reloc_internal
+{
+  bfd_vma r_address;		/* Offset of of data to relocate.  */
+  long	r_index;		/* Symbol table index of symbol.  */
+  enum reloc_type r_type;	/* Relocation type.  */
+  bfd_vma r_addend;		/* Datum addend.  */
+};
+
+/* Q.
+   Should the length of the string table be 4 bytes or 8 bytes ?
+
+   Q.
+   What about archive indexes ?  */
+
+#endif				/* __A_OUT_64_H__ */
diff --git a/binutils-2.25/include/aout/ar.h b/binutils-2.25/include/aout/ar.h
new file mode 100644
index 00000000..de043822
--- /dev/null
+++ b/binutils-2.25/include/aout/ar.h
@@ -0,0 +1,55 @@
+/* archive file definition for GNU software
+
+   Copyright 2001, 2008, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* So far this is correct for BSDish archives.  Don't forget that
+   files must begin on an even byte boundary. */
+
+#ifndef __GNU_AR_H__
+#define __GNU_AR_H__
+
+/* Note that the usual '\n' in magic strings may translate to different
+   characters, as allowed by ANSI.  '\012' has a fixed value, and remains
+   compatible with existing BSDish archives. */
+
+#define ARMAG  "!<arch>\012"	/* For COFF and a.out archives.  */
+#define ARMAGB "!<bout>\012"	/* For b.out archives.  */
+#define ARMAGT "!<thin>\012"	/* For thin archives.  */
+#define SARMAG 8
+#define ARFMAG "`\012"
+
+/* The ar_date field of the armap (__.SYMDEF) member of an archive
+   must be greater than the modified date of the entire file, or 
+   BSD-derived linkers complain.  We originally write the ar_date with
+   this offset from the real file's mod-time.  After finishing the
+   file, we rewrite ar_date if it's not still greater than the mod date.  */
+
+#define ARMAP_TIME_OFFSET       60
+
+struct ar_hdr
+{
+  char ar_name[16];		/* Name of this member.  */
+  char ar_date[12];		/* File mtime.  */
+  char ar_uid[6];		/* Owner uid; printed as decimal.  */
+  char ar_gid[6];		/* Owner gid; printed as decimal.  */
+  char ar_mode[8];		/* File mode, printed as octal.   */
+  char ar_size[10];		/* File size, printed as decimal.  */
+  char ar_fmag[2];		/* Should contain ARFMAG.  */
+};
+
+#endif /* __GNU_AR_H__ */
diff --git a/binutils-2.25/include/aout/dynix3.h b/binutils-2.25/include/aout/dynix3.h
new file mode 100644
index 00000000..808e53a7
--- /dev/null
+++ b/binutils-2.25/include/aout/dynix3.h
@@ -0,0 +1,87 @@
+/* a.out specifics for Sequent Symmetry running Dynix 3.x
+
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef A_OUT_DYNIX3_H
+#define A_OUT_DYNIX3_H
+
+#define external_exec dynix_external_exec
+
+/* struct exec for Dynix 3
+ 
+   a_gdtbl and a_bootstrap are only for standalone binaries.
+   Shared data fields are not supported by the kernel as of Dynix 3.1,
+   but are supported by Dynix compiler programs.  */
+struct dynix_external_exec
+  {
+    unsigned char e_info[4];
+    unsigned char e_text[4];
+    unsigned char e_data[4];
+    unsigned char e_bss[4];
+    unsigned char e_syms[4];
+    unsigned char e_entry[4];
+    unsigned char e_trsize[4];
+    unsigned char e_drsize[4];
+    unsigned char e_g_code[8];
+    unsigned char e_g_data[8];
+    unsigned char e_g_desc[8];
+    unsigned char e_shdata[4];
+    unsigned char e_shbss[4];
+    unsigned char e_shdrsize[4];
+    unsigned char e_bootstrap[44];
+    unsigned char e_reserved[12];
+    unsigned char e_version[4];
+  };
+
+#define	EXEC_BYTES_SIZE	(128)
+
+/* All executables under Dynix are demand paged with read-only text,
+   Thus no NMAGIC.
+  
+   ZMAGIC has a page of 0s at virtual 0,
+   XMAGIC has an invalid page at virtual 0.  */
+#define OMAGIC	0x12eb		/* .o */
+#define ZMAGIC	0x22eb		/* zero @ 0, demand load */
+#define XMAGIC	0x32eb		/* invalid @ 0, demand load */
+#define SMAGIC	0x42eb		/* standalone, not supported here */
+
+#define N_BADMAG(x) ((OMAGIC != N_MAGIC(x)) && \
+		     (ZMAGIC != N_MAGIC(x)) && \
+		     (XMAGIC != N_MAGIC(x)) && \
+		     (SMAGIC != N_MAGIC(x)))
+
+#define N_ADDRADJ(x) ((ZMAGIC == N_MAGIC(x) || XMAGIC == N_MAGIC(x)) ? 0x1000 : 0)
+
+#define N_TXTOFF(x) (EXEC_BYTES_SIZE)
+#define N_DATOFF(x) (N_TXTOFF(x) + N_TXTSIZE(x))
+#define N_SHDATOFF(x) (N_DATOFF(x) + (x).a_data)
+#define N_TRELOFF(x) (N_SHDATOFF(x) + (x).a_shdata)
+#define N_DRELOFF(x) (N_TRELOFF(x) + (x).a_trsize)
+#define N_SHDRELOFF(x) (N_DRELOFF(x) + (x).a_drsize)
+#define N_SYMOFF(x) (N_SHDRELOFF(x) + (x).a_shdrsize)
+#define N_STROFF(x) (N_SYMOFF(x) + (x).a_syms)
+
+#define N_TXTADDR(x) \
+	(((OMAGIC == N_MAGIC(x)) || (SMAGIC == N_MAGIC(x))) ? 0 \
+	 : TEXT_START_ADDR + EXEC_BYTES_SIZE)
+
+#define N_TXTSIZE(x) \
+	(((OMAGIC == N_MAGIC(x)) || (SMAGIC == N_MAGIC(x))) ? ((x).a_text) \
+	 : ((x).a_text - N_ADDRADJ(x) - EXEC_BYTES_SIZE))
+
+#endif /* A_OUT_DYNIX3_H */
diff --git a/binutils-2.25/include/aout/encap.h b/binutils-2.25/include/aout/encap.h
new file mode 100644
index 00000000..7ebec698
--- /dev/null
+++ b/binutils-2.25/include/aout/encap.h
@@ -0,0 +1,135 @@
+/* Yet Another Try at encapsulating bfd object files in coff.
+   Copyright 1988, 1989, 1991, 2010 Free Software Foundation, Inc.
+   Written by Pace Willisson 12/9/88
+
+   This file is obsolete.  It needs to be converted to just define a bunch
+   of stuff that BFD can use to do coff-encapsulated files.  --gnu@cygnus.com
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/*
+ * We only use the coff headers to tell the kernel
+ * how to exec the file.  Therefore, the only fields that need to 
+ * be filled in are the scnptr and vaddr for the text and data
+ * sections, and the vaddr for the bss.  As far as coff is concerned,
+ * there is no symbol table, relocation, or line numbers.
+ *
+ * A normal bsd header (struct exec) is placed after the coff headers,
+ * and before the real text.  I defined a the new fields 'a_machtype'
+ * and a_flags.  If a_machtype is M_386, and a_flags & A_ENCAP is
+ * true, then the bsd header is preceeded by a coff header.  Macros
+ * like N_TXTOFF and N_TXTADDR use this field to find the bsd header.
+ * 
+ * The only problem is to track down the bsd exec header.  The
+ * macros HEADER_OFFSET, etc do this.
+ */
+
+#define N_FLAGS_COFF_ENCAPSULATE 0x20 /* coff header precedes bsd header */
+
+/* Describe the COFF header used for encapsulation.  */
+
+struct coffheader
+{
+  /* filehdr */
+  unsigned short f_magic;
+  unsigned short f_nscns;
+  long f_timdat;
+  long f_symptr;
+  long f_nsyms;
+  unsigned short f_opthdr;
+  unsigned short f_flags;
+  /* aouthdr */
+  short magic;
+  short vstamp;
+  long tsize;
+  long dsize;
+  long bsize;
+  long entry;
+  long text_start;
+  long data_start;
+  struct coffscn
+    {
+      char s_name[8];
+      long s_paddr;
+      long s_vaddr;
+      long s_size;
+      long s_scnptr;
+      long s_relptr;
+      long s_lnnoptr;
+      unsigned short s_nreloc;
+      unsigned short s_nlnno;
+      long s_flags;
+    } scns[3];
+};
+
+/* Describe some of the parameters of the encapsulation,
+   including how to find the encapsulated BSD header.  */
+
+/* FIXME, this is dumb.  The same tools can't handle a.outs for different
+   architectures, just because COFF_MAGIC is different; so you need a
+   separate GNU nm for every architecture!!?  Unfortunately, it needs to
+   be this way, since the COFF_MAGIC value is determined by the kernel
+   we're trying to fool here.  */
+   
+#define COFF_MAGIC_I386 0514 /* I386MAGIC */
+#define COFF_MAGIC_M68K 0520 /* MC68MAGIC */
+
+#ifdef COFF_MAGIC
+short __header_offset_temp;
+#define HEADER_OFFSET(f) \
+	(__header_offset_temp = 0, \
+	 fread ((char *)&__header_offset_temp, sizeof (short), 1, (f)), \
+	 fseek ((f), -sizeof (short), 1), \
+	 __header_offset_temp==COFF_MAGIC ? sizeof(struct coffheader) : 0)
+#else
+#define HEADER_OFFSET(f) 0
+#endif
+
+#define HEADER_SEEK(f) (fseek ((f), HEADER_OFFSET((f)), 1))
+
+/* Describe the characteristics of the BSD header
+   that appears inside the encapsulation.  */
+
+/* Encapsulated coff files that are linked ZMAGIC have a text segment
+   offset just past the header (and a matching TXTADDR), excluding
+   the headers from the text segment proper but keeping the physical
+   layout and the virtual memory layout page-aligned.
+
+   Non-encapsulated a.out files that are linked ZMAGIC have a text
+   segment that starts at 0 and an N_TXTADR similarly offset to 0.
+   They too are page-aligned with each other, but they include the
+   a.out header as part of the text. 
+
+   The _N_HDROFF gets sizeof struct exec added to it, so we have
+   to compensate here.  See <a.out.gnu.h>.  */
+
+#undef _N_HDROFF
+#undef N_TXTADDR
+#undef N_DATADDR
+
+#define _N_HDROFF(x) ((N_FLAGS(x) & N_FLAGS_COFF_ENCAPSULATE) ? \
+		      sizeof (struct coffheader) : 0)
+
+/* Address of text segment in memory after it is loaded.  */
+#define N_TXTADDR(x) \
+	((N_FLAGS(x) & N_FLAGS_COFF_ENCAPSULATE) ? \
+	 sizeof (struct coffheader) + sizeof (struct exec) : 0)
+#define SEGMENT_SIZE 0x400000
+
+#define N_DATADDR(x) \
+	((N_FLAGS(x) & N_FLAGS_COFF_ENCAPSULATE) ? \
+	 (SEGMENT_SIZE + ((N_TXTADDR(x)+(x).a_text-1) & ~(SEGMENT_SIZE-1))) : \
+	 (N_TXTADDR(x)+(x).a_text))
diff --git a/binutils-2.25/include/aout/host.h b/binutils-2.25/include/aout/host.h
new file mode 100644
index 00000000..4260cc53
--- /dev/null
+++ b/binutils-2.25/include/aout/host.h
@@ -0,0 +1,43 @@
+/* host.h - Parameters about the a.out format, based on the host system
+   on which the program is compiled. 
+
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* Address of data segment in memory after it is loaded.
+   It is up to you to define SEGMENT_SIZE on machines not listed here.  */
+#ifndef SEGMENT_SIZE
+
+#if defined(hp300) || defined(pyr)
+#define SEGMENT_SIZE page_size
+#endif
+
+#ifdef	sony
+#define	SEGMENT_SIZE	0x1000
+#endif	/* Sony.  */
+
+#ifdef is68k
+#define SEGMENT_SIZE 0x20000
+#endif
+
+#if defined(m68k) && defined(PORTAR)
+#define TARGET_PAGE_SIZE 0x400
+#define SEGMENT_SIZE TARGET_PAGE_SIZE
+#endif
+
+#endif /*!defined(SEGMENT_SIZE)*/
+
diff --git a/binutils-2.25/include/aout/hp.h b/binutils-2.25/include/aout/hp.h
new file mode 100644
index 00000000..b60741a7
--- /dev/null
+++ b/binutils-2.25/include/aout/hp.h
@@ -0,0 +1,83 @@
+/* Special version of <a.out.h> for use under HP-UX.
+   Copyright 1988, 1991, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* THIS FILE IS OBSOLETE.  It needs to be revised as a variant "external"
+   a.out format for use with BFD.  */
+
+/* The `exec' structure and overall layout must be close to HP's when
+   we are running on an HP system, otherwise we will not be able to
+   execute the resulting file. */
+
+/* Allow this file to be included twice. */
+#ifndef __GNU_EXEC_MACROS__
+
+struct exec
+{
+  unsigned short a_machtype;	/* machine type */
+  unsigned short a_magic;	/* magic number */
+  unsigned long a_spare1;
+  unsigned long a_spare2;
+  unsigned long a_text;		/* length of text, in bytes */
+  unsigned long a_data;		/* length of data, in bytes */
+  unsigned long a_bss;		/* length of uninitialized data area for file, in bytes */
+  unsigned long a_trsize;	/* length of relocation info for text, in bytes */
+  unsigned long a_drsize;	/* length of relocation info for data, in bytes */
+  unsigned long a_spare3;	/* HP = pascal interface size */
+  unsigned long a_spare4;	/* HP = symbol table size */
+  unsigned long a_spare5;	/* HP = debug name table size */
+  unsigned long a_entry;	/* start address */
+  unsigned long a_spare6;	/* HP = source line table size */
+  unsigned long a_spare7;	/* HP = value table size */
+  unsigned long a_syms;		/* length of symbol table data in file, in bytes */
+  unsigned long a_spare8;
+};
+
+/* Tell a.out.gnu.h not to define `struct exec'.  */
+#define __STRUCT_EXEC_OVERRIDE__
+
+#include "../a.out.gnu.h"
+
+#undef N_MAGIC
+#undef N_MACHTYPE
+#undef N_FLAGS
+#undef N_SET_INFO
+#undef N_SET_MAGIC
+#undef N_SET_MACHTYPE
+#undef N_SET_FLAGS
+
+#define N_MAGIC(exec) ((exec) . a_magic)
+#define N_MACHTYPE(exec) ((exec) . a_machtype)
+#define N_SET_MAGIC(exec, magic) (((exec) . a_magic) = (magic))
+#define N_SET_MACHTYPE(exec, machtype) (((exec) . a_machtype) = (machtype))
+
+#undef N_BADMAG
+#define N_BADMAG(x) ((_N_BADMAG (x)) || (_N_BADMACH (x)))
+
+#define _N_BADMACH(x)							\
+(((N_MACHTYPE (x)) != HP9000S200_ID) &&					\
+ ((N_MACHTYPE (x)) != HP98x6_ID))
+
+#define HP98x6_ID 0x20A
+#define HP9000S200_ID 0x20C
+
+#undef _N_HDROFF
+#define _N_HDROFF(x) (SEGMENT_SIZE - (sizeof (struct exec)))
+
+#define SEGMENT_SIZE 0x1000
+
+#endif /* __GNU_EXEC_MACROS__ */
diff --git a/binutils-2.25/include/aout/hp300hpux.h b/binutils-2.25/include/aout/hp300hpux.h
new file mode 100644
index 00000000..97a3eb58
--- /dev/null
+++ b/binutils-2.25/include/aout/hp300hpux.h
@@ -0,0 +1,132 @@
+/* Special version of <a.out.h> for use under HP-UX.
+   Copyright 1988, 1993, 1995, 2001, 2009, 2010
+   Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+struct hp300hpux_exec_bytes
+{
+  unsigned char e_info[4];   /* a_machtype/a_magic */
+  unsigned char e_spare1[4];
+  unsigned char e_spare2[4];
+  unsigned char e_text[4];   /* length of text, in bytes */
+  unsigned char e_data[4];   /* length of data, in bytes */
+  unsigned char e_bss[4];    /* length of uninitialized data area , in bytes */
+  unsigned char e_trsize[4]; /* length of relocation info for text, in bytes*/
+  unsigned char e_drsize[4]; /* length of relocation info for data, in bytes*/
+  unsigned char e_passize[4];/* HP = pascal interface size */
+  unsigned char e_syms[4];   /* HP = symbol table size */
+  unsigned char e_spare5[4]; /* HP = debug name table size */
+  unsigned char e_entry[4];  /* start address */
+  unsigned char e_spare6[4]; /* HP = source line table size */
+  unsigned char e_supsize[4];/* HP = value table size */
+  unsigned char e_drelocs[4];
+  unsigned char e_extension[4]; /* file offset of extension */
+};
+#define	EXEC_BYTES_SIZE	64
+
+struct hp300hpux_nlist_bytes
+  {
+    unsigned char e_value[4];
+    unsigned char e_type[1];
+    unsigned char e_length[1];	/* length of ascii symbol name */
+    unsigned char e_almod[2];	/* alignment mod */
+    unsigned char e_shlib[2];   /* info about dynamic linking */
+  };
+#define EXTERNAL_NLIST_SIZE 10
+
+struct hp300hpux_reloc
+  {
+    unsigned char r_address[4];/* offset of of data to relocate */
+    unsigned char r_index[2];  /* symbol table index of symbol         */
+    unsigned char r_type[1];   /* relocation type                      */
+    unsigned char r_length[1]; /* length of item to reloc              */
+  };
+
+struct hp300hpux_header_extension
+{
+    unsigned char e_syms[4];
+    unsigned char unique_headers[12*4];
+    unsigned char e_header[2];   /* type of header */
+    unsigned char e_version[2];  /* version        */
+    unsigned char e_size[4];     /* bytes following*/
+    unsigned char e_extension[4];/* file offset of next extension */
+};
+#define EXTERNAL_EXTENSION_HEADER_SIZE (16*4)
+
+/* hpux separates object files (0x106) and impure executables (0x107)  */
+/* but the bfd code does not distinguish between them. Since we want to*/
+/* read hpux .o files, we add an special define and use it below in    */
+/* offset and address calculations.                                    */
+
+#define HPUX_DOT_O_MAGIC 0x106
+#define OMAGIC 0x107       /* object file or impure executable.  */
+#define NMAGIC 0x108       /* Code indicating pure executable.   */
+#define ZMAGIC 0x10B       /* demand-paged executable.           */
+
+#define N_HEADER_IN_TEXT(x) 0
+
+#if 0 /* libaout.h only uses the lower 8 bits */
+#define HP98x6_ID 0x20A
+#define HP9000S200_ID 0x20C
+#endif
+#define HP98x6_ID 0x0A
+#define HP9000S200_ID 0x0C
+
+#define N_BADMAG(x) ((_N_BADMAG (x)) || (_N_BADMACH (x)))
+
+#define N_DATADDR(x) \
+  ((N_MAGIC (x) == OMAGIC || N_MAGIC (x) == HPUX_DOT_O_MAGIC)		\
+   ? (N_TXTADDR (x) + N_TXTSIZE (x))					\
+   : (N_SEGSIZE (x) + ((N_TXTADDR (x) + N_TXTSIZE (x) - 1)		\
+		       & ~ (bfd_vma) (N_SEGSIZE (x) - 1))))
+
+#define _N_BADMACH(x) \
+  (((N_MACHTYPE (x)) != HP9000S200_ID) && ((N_MACHTYPE (x)) != HP98x6_ID))
+
+#define _N_BADMAG(x)	  (N_MAGIC(x) != HPUX_DOT_O_MAGIC \
+                        && N_MAGIC(x) != OMAGIC		\
+			&& N_MAGIC(x) != NMAGIC		\
+  			&& N_MAGIC(x) != ZMAGIC )
+
+#undef _N_HDROFF
+#define _N_HDROFF(x) (SEGMENT_SIZE - (sizeof (struct exec)))
+
+#undef N_DATOFF
+#undef N_PASOFF
+#undef N_SYMOFF
+#undef N_SUPOFF
+#undef N_TRELOFF
+#undef N_DRELOFF
+#undef N_STROFF
+
+#define N_DATOFF(x)	( N_TXTOFF(x) + N_TXTSIZE(x) )
+#define N_PASOFF(x)     ( N_DATOFF(x) + (x).a_data)
+#define N_SYMOFF(x)	( N_PASOFF(x)   /* + (x).a_passize*/ )
+#define N_SUPOFF(x)     ( N_SYMOFF(x) + (x).a_syms )
+#define N_TRELOFF(x)	( N_SUPOFF(x)    /* + 0 (x).a_supsize*/ )
+#define N_DRELOFF(x)	( N_TRELOFF(x) + (x).a_trsize )
+#define N_EXTHOFF(x)    ( N_DRELOFF(x)   /*  + 0 (x).a_drsize */)
+#define N_STROFF(x)	( 0 /* no string table */ )
+
+/* use these when the file has gnu symbol tables */
+#define N_GNU_TRELOFF(x) (N_DATOFF(x) + (x).a_data)
+#define N_GNU_DRELOFF(x) (N_GNU_TRELOFF(x) + (x).a_trsize)
+#define N_GNU_SYMOFF(x)  (N_GNU_DRELOFF(x) + (x).a_drsize)
+
+#define TARGET_PAGE_SIZE 0x1000
+#define SEGMENT_SIZE 0x1000
+#define TEXT_START_ADDR 0
diff --git a/binutils-2.25/include/aout/hppa.h b/binutils-2.25/include/aout/hppa.h
new file mode 100644
index 00000000..24698bb3
--- /dev/null
+++ b/binutils-2.25/include/aout/hppa.h
@@ -0,0 +1,22 @@
+/* Copyright 2012 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#include "filehdr.h"
+#include "aouthdr.h"
+#include "scnhdr.h"
+#include "spacehdr.h"
+#include "syms.h"
diff --git a/binutils-2.25/include/aout/ranlib.h b/binutils-2.25/include/aout/ranlib.h
new file mode 100644
index 00000000..92bec468
--- /dev/null
+++ b/binutils-2.25/include/aout/ranlib.h
@@ -0,0 +1,63 @@
+/* ranlib.h -- archive library index member definition for GNU.
+   Copyright 1990, 1991, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* The Symdef member of an archive contains two things:
+   a table that maps symbol-string offsets to file offsets,
+   and a symbol-string table.  All the symbol names are
+   run together (each with trailing null) in the symbol-string
+   table.  There is a single longword bytecount on the front
+   of each of these tables.  Thus if we have two symbols,
+   "foo" and "_bar", that are in archive members at offsets
+   200 and 900, it would look like this:
+        16		; byte count of index table
+  	0		; offset of "foo" in string table
+  	200		; offset of foo-module in file
+  	4		; offset of "bar" in string table
+  	900		; offset of bar-module in file
+  	9		; byte count of string table
+  	"foo\0_bar\0"	; string table  */
+
+#define	RANLIBMAG	"__.SYMDEF"	/* Archive file name containing index */
+#define	RANLIBSKEW	3		/* Creation time offset */
+
+/* Format of __.SYMDEF:
+   First, a longword containing the size of the 'symdef' data that follows.
+   Second, zero or more 'symdef' structures.
+   Third, a longword containing the length of symbol name strings.
+   Fourth, zero or more symbol name strings (each followed by a null).  */
+
+struct symdef
+  {
+    union
+      {
+	unsigned long string_offset;	/* In the file */
+	char *name;			/* In memory, sometimes */
+      } s;
+    /* this points to the front of the file header (AKA member header --
+       a struct ar_hdr), not to the front of the file or into the file).
+       in other words it only tells you which file to read */       
+    unsigned long file_offset;
+  };
+
+/* Compatability with BSD code */
+
+#define	ranlib	symdef
+#define	ran_un	s
+#define	ran_strx string_offset
+#define	ran_name name
+#define	ran_off	file_offset
diff --git a/binutils-2.25/include/aout/reloc.h b/binutils-2.25/include/aout/reloc.h
new file mode 100644
index 00000000..6f1bc52e
--- /dev/null
+++ b/binutils-2.25/include/aout/reloc.h
@@ -0,0 +1,67 @@
+/* reloc.h -- Header file for relocation information.
+   Copyright 1989, 1990, 1991, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* Relocation types for a.out files using reloc_info_extended
+   (SPARC and AMD 29000). */
+
+#ifndef _RELOC_H_READ_
+#define _RELOC_H_READ_ 1
+
+enum reloc_type
+  {
+    RELOC_8,        RELOC_16,        RELOC_32, /* simple relocations */
+    RELOC_DISP8,    RELOC_DISP16,    RELOC_DISP32, /* pc-rel displacement */
+    RELOC_WDISP30,  RELOC_WDISP22,
+    RELOC_HI22,     RELOC_22,
+    RELOC_13,       RELOC_LO10,
+    RELOC_SFA_BASE, RELOC_SFA_OFF13,
+    RELOC_BASE10,   RELOC_BASE13,    RELOC_BASE22, /* P.I.C. (base-relative) */
+    RELOC_PC10,     RELOC_PC22,	/* for some sort of pc-rel P.I.C. (?) */
+    RELOC_JMP_TBL,		/* P.I.C. jump table */
+    RELOC_SEGOFF16,		/* reputedly for shared libraries somehow */
+    RELOC_GLOB_DAT,  RELOC_JMP_SLOT, RELOC_RELATIVE,
+    RELOC_11,
+    RELOC_WDISP2_14,
+    RELOC_WDISP19,
+    RELOC_HHI22,
+    RELOC_HLO10,
+    
+    /* 29K relocation types */
+    RELOC_JUMPTARG, RELOC_CONST,     RELOC_CONSTH,
+    
+    RELOC_WDISP14, RELOC_WDISP21,
+    
+    NO_RELOC
+    };
+
+#define	RELOC_TYPE_NAMES \
+"8",		"16",		"32",		"DISP8",	\
+"DISP16",	"DISP32",	"WDISP30",	"WDISP22",	\
+"HI22",		"22",		"13",		"LO10",		\
+"SFA_BASE",	"SFAOFF13",	"BASE10",	"BASE13",	\
+"BASE22",	"PC10",		"PC22",		"JMP_TBL",	\
+"SEGOFF16",	"GLOB_DAT",	"JMP_SLOT",	"RELATIVE",	\
+"11",		"WDISP2_14",	"WDISP19", 	"HHI22",	\
+"HLO10",							\
+"JUMPTARG",	"CONST",	"CONSTH",	"WDISP14",	\
+"WDISP21",	\
+"NO_RELOC"
+
+#endif /* _RELOC_H_READ_ */
+
+/* end of reloc.h */
diff --git a/binutils-2.25/include/aout/stab.def b/binutils-2.25/include/aout/stab.def
new file mode 100644
index 00000000..ad1c62ed
--- /dev/null
+++ b/binutils-2.25/include/aout/stab.def
@@ -0,0 +1,283 @@
+/* Table of DBX symbol codes for the GNU system.
+   Copyright 1988, 1991, 1992, 1993, 1994, 1996, 1998, 2004, 2010
+   Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or
+   modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 3 of the
+   License, or (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* New stab from Solaris 2.  This uses an n_type of 0, which in a.out files
+   overlaps the N_UNDF used for ordinary symbols.  In ELF files, the
+   debug information is in a different file section, so there is no conflict.
+   This symbol's n_value gives the size of the string section associated
+   with this file.  The symbol's n_strx (relative to the just-updated
+   string section start address) gives the name of the source file,
+   e.g. "foo.c", without any path information.  The symbol's n_desc gives
+   the count of upcoming symbols associated with this file (not including
+   this one).  */
+/* __define_stab (N_UNDF, 0x00, "UNDF")  */
+
+/* Global variable.  Only the name is significant.
+   To find the address, look in the corresponding external symbol.  */
+__define_stab (N_GSYM, 0x20, "GSYM")
+
+/* Function name for BSD Fortran.  Only the name is significant.
+   To find the address, look in the corresponding external symbol.  */
+__define_stab (N_FNAME, 0x22, "FNAME")
+
+/* Function name or text-segment variable for C.  Value is its address.
+   Desc is supposedly starting line number, but GCC doesn't set it
+   and DBX seems not to miss it.  */
+__define_stab (N_FUN, 0x24, "FUN")
+
+/* Data-segment variable with internal linkage.  Value is its address.
+   "Static Sym".  */
+__define_stab (N_STSYM, 0x26, "STSYM")
+
+/* BSS-segment variable with internal linkage.  Value is its address.  */
+__define_stab (N_LCSYM, 0x28, "LCSYM")
+
+/* Name of main routine.  Only the name is significant.  */
+__define_stab (N_MAIN, 0x2a, "MAIN")
+
+/* Solaris2:  Read-only data symbols.  */
+__define_stab (N_ROSYM, 0x2c, "ROSYM")
+
+/* MacOS X:
+   The beginning of a relocatable function block - including stabs.  */
+__define_stab (N_BNSYM, 0x2e, "BNSYM")
+
+/* Global symbol in Pascal.
+   Supposedly the value is its line number; I'm skeptical.  */
+__define_stab (N_PC, 0x30, "PC")
+
+/* Number of symbols:  0, files,,funcs,lines according to Ultrix V4.0. */
+__define_stab (N_NSYMS, 0x32, "NSYMS")
+
+/* "No DST map for sym: name, ,0,type,ignored"  according to Ultrix V4.0. */
+__define_stab (N_NOMAP, 0x34, "NOMAP")
+
+/* New stab from Solaris 2.  Like N_SO, but for the object file.  Two in
+   a row provide the build directory and the relative path of the .o from it.
+   Solaris2 uses this to avoid putting the stabs info into the linked
+   executable; this stab goes into the ".stab.index" section, and the debugger
+   reads the real stabs directly from the .o files instead.  */
+__define_stab (N_OBJ, 0x38, "OBJ")
+
+/* New stab from Solaris 2.  Options for the debugger, related to the
+   source language for this module.  E.g. whether to use ANSI
+   integral promotions or traditional integral promotions.  */
+__define_stab (N_OPT, 0x3c, "OPT")
+
+/* Register variable.  Value is number of register.  */
+__define_stab (N_RSYM, 0x40, "RSYM")
+
+/* Modula-2 compilation unit.  Can someone say what info it contains?  */
+__define_stab (N_M2C, 0x42, "M2C")
+
+/* Line number in text segment.  Desc is the line number;
+   value is corresponding address.  On Solaris2, the line number is
+   relative to the start of the current function.  */
+__define_stab (N_SLINE, 0x44, "SLINE")
+
+/* Similar, for data segment.  */
+__define_stab (N_DSLINE, 0x46, "DSLINE")
+
+/* Similar, for bss segment.  */
+__define_stab (N_BSLINE, 0x48, "BSLINE")
+
+/* Sun's source-code browser stabs.  ?? Don't know what the fields are.
+   Supposedly the field is "path to associated .cb file".  THIS VALUE
+   OVERLAPS WITH N_BSLINE!  */
+__define_stab_duplicate (N_BROWS, 0x48, "BROWS")
+
+/* GNU Modula-2 definition module dependency.  Value is the modification time
+   of the definition file.  Other is non-zero if it is imported with the
+   GNU M2 keyword %INITIALIZE.  Perhaps N_M2C can be used if there
+   are enough empty fields? */
+__define_stab(N_DEFD, 0x4a, "DEFD")
+
+/* New in Solaris2.  Function start/body/end line numbers.  */
+__define_stab(N_FLINE, 0x4C, "FLINE")
+
+/* MacOS X: This tells the end of a relocatable function + debugging info.  */
+__define_stab(N_ENSYM, 0x4E, "ENSYM")
+
+/* THE FOLLOWING TWO STAB VALUES CONFLICT.  Happily, one is for Modula-2
+   and one is for C++.   Still,... */
+/* GNU C++ exception variable.  Name is variable name.  */
+__define_stab (N_EHDECL, 0x50, "EHDECL")
+/* Modula2 info "for imc":  name,,0,0,0  according to Ultrix V4.0.  */
+__define_stab_duplicate (N_MOD2, 0x50, "MOD2")
+
+/* GNU C++ `catch' clause.  Value is its address.  Desc is nonzero if
+   this entry is immediately followed by a CAUGHT stab saying what exception
+   was caught.  Multiple CAUGHT stabs means that multiple exceptions
+   can be caught here.  If Desc is 0, it means all exceptions are caught
+   here.  */
+__define_stab (N_CATCH, 0x54, "CATCH")
+
+/* Structure or union element.  Value is offset in the structure.  */
+__define_stab (N_SSYM, 0x60, "SSYM")
+
+/* Solaris2:  Last stab emitted for module.  */
+__define_stab (N_ENDM, 0x62, "ENDM")
+
+/* Name of main source file.
+   Value is starting text address of the compilation.
+   If multiple N_SO's appear, the first to contain a trailing / is the
+   compilation directory.  The first to not contain a trailing / is the
+   source file name, relative to the compilation directory.  Others (perhaps
+   resulting from cfront) are ignored.
+   On Solaris2, value is undefined, but desc is a source-language code.  */
+
+__define_stab (N_SO, 0x64, "SO")
+
+/* Apple:  This is the stab that associated the .o file with the
+   N_SO stab, in the case where debug info is mostly stored in the .o file.  */
+__define_stab (N_OSO, 0x66, "OSO")
+
+/* SunPro F77:  Name of alias.  */
+__define_stab (N_ALIAS, 0x6c, "ALIAS")
+
+/* Automatic variable in the stack.  Value is offset from frame pointer.
+   Also used for type descriptions.  */
+__define_stab (N_LSYM, 0x80, "LSYM")
+
+/* Beginning of an include file.  Only Sun uses this.
+   In an object file, only the name is significant.
+   The Sun linker puts data into some of the other fields.  */
+__define_stab (N_BINCL, 0x82, "BINCL")
+
+/* Name of sub-source file (#include file).
+   Value is starting text address of the compilation.  */
+__define_stab (N_SOL, 0x84, "SOL")
+
+/* Parameter variable.  Value is offset from argument pointer.
+   (On most machines the argument pointer is the same as the frame pointer.  */
+__define_stab (N_PSYM, 0xa0, "PSYM")
+
+/* End of an include file.  No name.
+   This and N_BINCL act as brackets around the file's output.
+   In an object file, there is no significant data in this entry.
+   The Sun linker puts data into some of the fields.  */
+__define_stab (N_EINCL, 0xa2, "EINCL")
+
+/* Alternate entry point.  Value is its address.  */
+__define_stab (N_ENTRY, 0xa4, "ENTRY")
+
+/* Beginning of lexical block.
+   The desc is the nesting level in lexical blocks.
+   The value is the address of the start of the text for the block.
+   The variables declared inside the block *precede* the N_LBRAC symbol.
+   On Solaris2, the value is relative to the start of the current function.  */
+__define_stab (N_LBRAC, 0xc0, "LBRAC")
+
+/* Place holder for deleted include file.  Replaces a N_BINCL and everything
+   up to the corresponding N_EINCL.  The Sun linker generates these when
+   it finds multiple identical copies of the symbols from an include file.
+   This appears only in output from the Sun linker.  */
+__define_stab (N_EXCL, 0xc2, "EXCL")
+
+/* Modula-2 scope information.  Can someone say what info it contains?  */
+__define_stab (N_SCOPE, 0xc4, "SCOPE")
+
+/* Solaris2: Patch Run Time Checker.  */
+__define_stab (N_PATCH, 0xd0, "PATCH")
+
+/* End of a lexical block.  Desc matches the N_LBRAC's desc.
+   The value is the address of the end of the text for the block.
+   On Solaris2, the value is relative to the start of the current function.  */
+__define_stab (N_RBRAC, 0xe0, "RBRAC")
+
+/* Begin named common block.  Only the name is significant.  */
+__define_stab (N_BCOMM, 0xe2, "BCOMM")
+
+/* End named common block.  Only the name is significant
+   (and it should match the N_BCOMM).  */
+__define_stab (N_ECOMM, 0xe4, "ECOMM")
+
+/* Member of a common block; value is offset within the common block.
+   This should occur within a BCOMM/ECOMM pair.  */
+__define_stab (N_ECOML, 0xe8, "ECOML")
+
+/* Solaris2: Pascal "with" statement: type,,0,0,offset */
+__define_stab (N_WITH, 0xea, "WITH")
+
+/* These STAB's are used on Gould systems for Non-Base register symbols
+   or something like that.  FIXME.  I have assigned the values at random
+   since I don't have a Gould here.  Fixups from Gould folk welcome... */
+__define_stab (N_NBTEXT, 0xF0, "NBTEXT")
+__define_stab (N_NBDATA, 0xF2, "NBDATA")
+__define_stab (N_NBBSS,  0xF4, "NBBSS")
+__define_stab (N_NBSTS,  0xF6, "NBSTS")
+__define_stab (N_NBLCS,  0xF8, "NBLCS")
+
+/* Second symbol entry containing a length-value for the preceding entry.
+   The value is the length.  */
+__define_stab (N_LENG, 0xfe, "LENG")
+
+/* The above information, in matrix format.
+
+			STAB MATRIX
+	_________________________________________________
+	| 00 - 1F are not dbx stab symbols		|
+	| In most cases, the low bit is the EXTernal bit|
+
+	| 00 UNDEF  | 02 ABS	| 04 TEXT   | 06 DATA	|
+	| 01  |EXT  | 03  |EXT	| 05  |EXT  | 07  |EXT	|
+
+	| 08 BSS    | 0A INDR	| 0C FN_SEQ | 0E WEAKA	|
+	| 09  |EXT  | 0B 	| 0D WEAKU  | 0F WEAKT	|
+
+	| 10 WEAKD  | 12 COMM	| 14 SETA   | 16 SETT	|
+	| 11 WEAKB  | 13	| 15 	    | 17	|
+
+	| 18 SETD   | 1A SETB	| 1C SETV   | 1E WARNING|
+	| 19	    | 1B	| 1D 	    | 1F FN	|
+
+	|_______________________________________________|
+	| Debug entries with bit 01 set are unused.	|
+	| 20 GSYM   | 22 FNAME	| 24 FUN    | 26 STSYM	|
+	| 28 LCSYM  | 2A MAIN	| 2C ROSYM  | 2E	|
+	| 30 PC	    | 32 NSYMS	| 34 NOMAP  | 36	|
+	| 38 OBJ    | 3A	| 3C OPT    | 3E	|
+	| 40 RSYM   | 42 M2C	| 44 SLINE  | 46 DSLINE |
+	| 48 BSLINE*| 4A DEFD	| 4C FLINE  | 4E	|
+	| 50 EHDECL*| 52	| 54 CATCH  | 56        |
+	| 58        | 5A        | 5C        | 5E	|
+	| 60 SSYM   | 62 ENDM	| 64 SO	    | 66 	|
+	| 68 	    | 6A	| 6C ALIAS  | 6E	|
+	| 70	    | 72	| 74	    | 76	|
+	| 78	    | 7A	| 7C	    | 7E	|
+	| 80 LSYM   | 82 BINCL	| 84 SOL    | 86	|
+	| 88	    | 8A	| 8C	    | 8E	|
+	| 90	    | 92	| 94	    | 96	|
+	| 98	    | 9A	| 9C	    | 9E	|
+	| A0 PSYM   | A2 EINCL	| A4 ENTRY  | A6	|
+	| A8	    | AA	| AC	    | AE	|
+	| B0	    | B2	| B4	    | B6	|
+	| B8	    | BA	| BC	    | BE	|
+	| C0 LBRAC  | C2 EXCL	| C4 SCOPE  | C6	|
+	| C8	    | CA	| CC	    | CE	|
+	| D0 PATCH  | D2	| D4	    | D6	|
+	| D8	    | DA	| DC	    | DE	|
+	| E0 RBRAC  | E2 BCOMM	| E4 ECOMM  | E6	|
+	| E8 ECOML  | EA WITH	| EC	    | EE	|
+	| F0	    | F2	| F4	    | F6	|
+	| F8	    | FA	| FC	    | FE LENG	|
+	+-----------------------------------------------+
+ * 50 EHDECL is also MOD2.
+ * 48 BSLINE is also BROWS.
+ */
diff --git a/binutils-2.25/include/aout/stab_gnu.h b/binutils-2.25/include/aout/stab_gnu.h
new file mode 100644
index 00000000..60b5272c
--- /dev/null
+++ b/binutils-2.25/include/aout/stab_gnu.h
@@ -0,0 +1,55 @@
+/* gnu_stab.h  Definitions for GNU extensions to STABS
+
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+#ifndef __GNU_STAB__
+
+/* Indicate the GNU stab.h is in use.  */
+
+#define __GNU_STAB__
+
+#define __define_stab(NAME, CODE, STRING) NAME=CODE,
+#define __define_stab_duplicate(NAME, CODE, STRING) NAME=CODE,
+
+enum __stab_debug_code
+{
+#include "aout/stab.def"
+LAST_UNUSED_STAB_CODE
+};
+
+#undef __define_stab
+
+/* Definitions of "desc" field for N_SO stabs in Solaris2.  */
+
+#define	N_SO_AS		1
+#define	N_SO_C		2
+#define	N_SO_ANSI_C	3
+#define	N_SO_CC		4	/* C++ */
+#define	N_SO_FORTRAN	5
+#define	N_SO_PASCAL	6
+
+/* Solaris2: Floating point type values in basic types.  */
+
+#define	NF_NONE		0
+#define	NF_SINGLE	1	/* IEEE 32-bit */
+#define	NF_DOUBLE	2	/* IEEE 64-bit */
+#define	NF_COMPLEX	3	/* Fortran complex */
+#define	NF_COMPLEX16	4	/* Fortran double complex */
+#define	NF_COMPLEX32	5	/* Fortran complex*16 */
+#define	NF_LDOUBLE	6	/* Long double (whatever that is) */
+
+#endif /* __GNU_STAB_ */
diff --git a/binutils-2.25/include/aout/sun4.h b/binutils-2.25/include/aout/sun4.h
new file mode 100644
index 00000000..06f7584c
--- /dev/null
+++ b/binutils-2.25/include/aout/sun4.h
@@ -0,0 +1,239 @@
+/* SPARC-specific values for a.out files 
+
+   Copyright 2001, 2009, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* Some systems, e.g., AIX, may have defined this in header files already
+   included.  */
+#undef  TARGET_PAGE_SIZE
+#define TARGET_PAGE_SIZE	0x2000		/* 8K.  aka NBPG in <sys/param.h> */
+/* Note that some SPARCs have 4K pages, some 8K, some others.  */
+
+#define SEG_SIZE_SPARC	TARGET_PAGE_SIZE
+#define	SEG_SIZE_SUN3	0x20000		/* Resolution of r/w protection hw */
+
+#define TEXT_START_ADDR	TARGET_PAGE_SIZE	/* Location 0 is not accessible */
+#define N_HEADER_IN_TEXT(x) 1
+
+/* Non-default definitions of the accessor macros... */
+
+/* Segment size varies on Sun-3 versus Sun-4.  */
+
+#define N_SEGSIZE(x)	(N_MACHTYPE(x) == M_SPARC?	SEG_SIZE_SPARC:	\
+			 N_MACHTYPE(x) == M_68020?	SEG_SIZE_SUN3:	\
+			/* Guess? */			TARGET_PAGE_SIZE)
+
+/* Virtual Address of text segment from the a.out file.  For OMAGIC,
+   (almost always "unlinked .o's" these days), should be zero.
+   Sun added a kludge so that shared libraries linked ZMAGIC get
+   an address of zero if a_entry (!!!) is lower than the otherwise
+   expected text address.  These kludges have gotta go!
+   For linked files, should reflect reality if we know it.  */
+
+#define N_SHARED_LIB(x) ((x).a_entry < TEXT_START_ADDR \
+			 && (x).a_text >= EXEC_BYTES_SIZE)
+
+/* This differs from the version in aout64.h (which we override by defining
+   it here) only for NMAGIC (we return TEXT_START_ADDR+EXEC_BYTES_SIZE;
+   they return 0).  */
+
+#define N_TXTADDR(x) \
+    (N_MAGIC(x)==OMAGIC? 0 \
+     : (N_MAGIC(x) == ZMAGIC && (x).a_entry < TEXT_START_ADDR)? 0 \
+     : TEXT_START_ADDR+EXEC_BYTES_SIZE)
+
+/* When a file is linked against a shared library on SunOS 4, the
+   dynamic bit in the exec header is set, and the first symbol in the
+   symbol table is __DYNAMIC.  Its value is the address of the
+   following structure.  */
+
+struct external_sun4_dynamic
+{
+  /* The version number of the structure.  SunOS 4.1.x creates files
+     with version number 3, which is what this structure is based on.
+     According to gdb, version 2 is similar.  I believe that version 2
+     used a different type of procedure linkage table, and there may
+     have been other differences.  */
+  bfd_byte ld_version[4];
+  /* The virtual address of a 28 byte structure used in debugging.
+     The contents are filled in at run time by ld.so.  */
+  bfd_byte ldd[4];
+  /* The virtual address of another structure with information about
+     how to relocate the executable at run time.  */
+  bfd_byte ld[4];
+};
+
+/* The size of the debugging structure pointed to by the debugger
+   field of __DYNAMIC.  */
+#define EXTERNAL_SUN4_DYNAMIC_DEBUGGER_SIZE (24)
+
+/* The structure pointed to by the linker field of __DYNAMIC.  As far
+   as I can tell, most of the addresses in this structure are offsets
+   within the file, but some are actually virtual addresses.  */
+
+struct internal_sun4_dynamic_link
+{
+  /* Linked list of loaded objects.  This is filled in at runtime by
+     ld.so and probably by dlopen.  */
+  unsigned long ld_loaded;
+
+  /* The address of the list of names of shared objects which must be
+     included at runtime.  Each entry in the list is 16 bytes: the 4
+     byte address of the string naming the object (e.g., for -lc this
+     is "c"); 4 bytes of flags--the high bit is whether to search for
+     the object using the library path; the 2 byte major version
+     number; the 2 byte minor version number; the 4 byte address of
+     the next entry in the list (zero if this is the last entry).  The
+     version numbers seem to only be non-zero when doing library
+     searching.  */
+  unsigned long ld_need;
+
+  /* The address of the path to search for the shared objects which
+     must be included.  This points to a string in PATH format which
+     is generated from the -L arguments to the linker.  According to
+     the man page, ld.so implicitly adds ${LD_LIBRARY_PATH} to the
+     beginning of this string and /lib:/usr/lib:/usr/local/lib to the
+     end.  The string is terminated by a null byte.  This field is
+     zero if there is no additional path.  */
+  unsigned long ld_rules;
+
+  /* The address of the global offset table.  This appears to be a
+     virtual address, not a file offset.  The first entry in the
+     global offset table seems to be the virtual address of the
+     sun4_dynamic structure (the same value as the __DYNAMIC symbol).
+     The global offset table is used for PIC code to hold the
+     addresses of variables.  A dynamically linked file which does not
+     itself contain PIC code has a four byte global offset table.  */
+  unsigned long ld_got;
+
+  /* The address of the procedure linkage table.  This appears to be a
+     virtual address, not a file offset.
+
+     On a SPARC, the table is composed of 12 byte entries, each of
+     which consists of three instructions.  The first entry is
+         sethi %hi(0),%g1
+	 jmp %g1
+	 nop
+     These instructions are changed by ld.so into a jump directly into
+     ld.so itself.  Each subsequent entry is
+         save %sp, -96, %sp
+	 call <address of first entry in procedure linkage table>
+	 <reloc_number | 0x01000000>
+     The reloc_number is the number of the reloc to use to resolve
+     this entry.  The reloc will be a JMP_SLOT reloc against some
+     symbol that is not defined in this object file but should be
+     defined in a shared object (if it is not, ld.so will report a
+     runtime error and exit).  The constant 0x010000000 turns the
+     reloc number into a sethi of %g0, which does nothing since %g0 is
+     hardwired to zero.
+
+     When one of these entries is executed, it winds up calling into
+     ld.so.  ld.so looks at the reloc number, available via the return
+     address, to determine which entry this is.  It then looks at the
+     reloc and patches up the entry in the table into a sethi and jmp
+     to the real address followed by a nop.  This means that the reloc
+     lookup only has to happen once, and it also means that the
+     relocation only needs to be done if the function is actually
+     called.  The relocation is expensive because ld.so must look up
+     the symbol by name.
+
+     The size of the procedure linkage table is given by the ld_plt_sz
+     field.  */
+  unsigned long ld_plt;
+
+  /* The address of the relocs.  These are in the same format as
+     ordinary relocs.  Symbol index numbers refer to the symbols
+     pointed to by ld_stab.  I think the only way to determine the
+     number of relocs is to assume that all the bytes from ld_rel to
+     ld_hash contain reloc entries.  */
+  unsigned long ld_rel;
+
+  /* The address of a hash table of symbols.  The hash table has
+     roughly the same number of entries as there are dynamic symbols;
+     I think the only way to get the exact size is to assume that
+     every byte from ld_hash to ld_stab is devoted to the hash table.
+
+     Each entry in the hash table is eight bytes.  The first four
+     bytes are a symbol index into the dynamic symbols.  The second
+     four bytes are the index of the next hash table entry in the
+     bucket.  The ld_buckets field gives the number of buckets, say B.
+     The first B entries in the hash table each start a bucket which
+     is chained through the second four bytes of each entry.  A value
+     of zero ends the chain.
+
+     The hash function is simply
+         h = 0;
+         while (*string != '\0')
+	   h = (h << 1) + *string++;
+	 h &= 0x7fffffff;
+
+     To look up a symbol, compute the hash value of the name.  Take
+     the modulos of hash value and the number of buckets.  Start at
+     that entry in the hash table.  See if the symbol (from the first
+     four bytes of the hash table entry) has the name you are looking
+     for.  If not, use the chain field (the second four bytes of the
+     hash table entry) to move on to the next entry in this bucket.
+     If the chain field is zero you have reached the end of the
+     bucket, and the symbol is not in the hash table.  */ 
+  unsigned long ld_hash;
+
+  /* The address of the symbol table.  This is a list of
+     external_nlist structures.  The string indices are relative to
+     the ld_symbols field.  I think the only way to determine the
+     number of symbols is to assume that all the bytes between ld_stab
+     and ld_symbols are external_nlist structures.  */
+  unsigned long ld_stab;
+
+  /* I don't know what this is for.  It seems to always be zero.  */
+  unsigned long ld_stab_hash;
+
+  /* The number of buckets in the hash table.  */
+  unsigned long ld_buckets;
+
+  /* The address of the symbol string table.  The first string in this
+     string table need not be the empty string.  */
+  unsigned long ld_symbols;
+
+  /* The size in bytes of the symbol string table.  */
+  unsigned long ld_symb_size;
+
+  /* The size in bytes of the text segment.  */
+  unsigned long ld_text;
+
+  /* The size in bytes of the procedure linkage table.  */
+  unsigned long ld_plt_sz;
+};
+
+/* The external form of the structure.  */
+
+struct external_sun4_dynamic_link
+{
+  bfd_byte ld_loaded[4];
+  bfd_byte ld_need[4];
+  bfd_byte ld_rules[4];
+  bfd_byte ld_got[4];
+  bfd_byte ld_plt[4];
+  bfd_byte ld_rel[4];
+  bfd_byte ld_hash[4];
+  bfd_byte ld_stab[4];
+  bfd_byte ld_stab_hash[4];
+  bfd_byte ld_buckets[4];
+  bfd_byte ld_symbols[4];
+  bfd_byte ld_symb_size[4];
+  bfd_byte ld_text[4];
+  bfd_byte ld_plt_sz[4];
+};
diff --git a/binutils-2.25/include/bfdlink.h b/binutils-2.25/include/bfdlink.h
new file mode 100644
index 00000000..1ac07382
--- /dev/null
+++ b/binutils-2.25/include/bfdlink.h
@@ -0,0 +1,842 @@
+/* bfdlink.h -- header file for BFD link routines
+   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+   2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
+   Free Software Foundation, Inc.
+   Written by Steve Chamberlain and Ian Lance Taylor, Cygnus Support.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef BFDLINK_H
+#define BFDLINK_H
+
+/* Which symbols to strip during a link.  */
+enum bfd_link_strip
+{
+  strip_none,		/* Don't strip any symbols.  */
+  strip_debugger,	/* Strip debugging symbols.  */
+  strip_some,		/* keep_hash is the list of symbols to keep.  */
+  strip_all		/* Strip all symbols.  */
+};
+
+/* Which local symbols to discard during a link.  This is irrelevant
+   if strip_all is used.  */
+enum bfd_link_discard
+{
+  discard_sec_merge,	/* Discard local temporary symbols in SEC_MERGE
+			   sections.  */
+  discard_none,		/* Don't discard any locals.  */
+  discard_l,		/* Discard local temporary symbols.  */
+  discard_all		/* Discard all locals.  */
+};
+
+/* Describes the type of hash table entry structure being used.
+   Different hash table structure have different fields and so
+   support different linking features.  */
+enum bfd_link_hash_table_type
+  {
+    bfd_link_generic_hash_table,
+    bfd_link_elf_hash_table
+  };
+
+/* These are the possible types of an entry in the BFD link hash
+   table.  */
+
+enum bfd_link_hash_type
+{
+  bfd_link_hash_new,		/* Symbol is new.  */
+  bfd_link_hash_undefined,	/* Symbol seen before, but undefined.  */
+  bfd_link_hash_undefweak,	/* Symbol is weak and undefined.  */
+  bfd_link_hash_defined,	/* Symbol is defined.  */
+  bfd_link_hash_defweak,	/* Symbol is weak and defined.  */
+  bfd_link_hash_common,		/* Symbol is common.  */
+  bfd_link_hash_indirect,	/* Symbol is an indirect link.  */
+  bfd_link_hash_warning		/* Like indirect, but warn if referenced.  */
+};
+
+enum bfd_link_common_skip_ar_symbols
+{
+  bfd_link_common_skip_none,
+  bfd_link_common_skip_text,
+  bfd_link_common_skip_data,
+  bfd_link_common_skip_all
+};
+
+struct bfd_link_hash_common_entry
+  {
+    unsigned int alignment_power;	/* Alignment.  */
+    asection *section;		/* Symbol section.  */
+  };
+
+/* The linking routines use a hash table which uses this structure for
+   its elements.  */
+
+struct bfd_link_hash_entry
+{
+  /* Base hash table entry structure.  */
+  struct bfd_hash_entry root;
+
+  /* Type of this entry.  */
+  ENUM_BITFIELD (bfd_link_hash_type) type : 8;
+
+  unsigned int non_ir_ref : 1;
+
+  /* A union of information depending upon the type.  */
+  union
+    {
+      /* Nothing is kept for bfd_hash_new.  */
+      /* bfd_link_hash_undefined, bfd_link_hash_undefweak.  */
+      struct
+	{
+	  /* Undefined and common symbols are kept in a linked list through
+	     this field.  This field is present in all of the union element
+	     so that we don't need to remove entries from the list when we
+	     change their type.  Removing entries would either require the
+	     list to be doubly linked, which would waste more memory, or
+	     require a traversal.  When an undefined or common symbol is
+	     created, it should be added to this list, the head of which is in
+	     the link hash table itself.  As symbols are defined, they need
+	     not be removed from the list; anything which reads the list must
+	     doublecheck the symbol type.
+
+	     Weak symbols are not kept on this list.
+
+	     Defined and defweak symbols use this field as a reference marker.
+	     If the field is not NULL, or this structure is the tail of the
+	     undefined symbol list, the symbol has been referenced.  If the
+	     symbol is undefined and becomes defined, this field will
+	     automatically be non-NULL since the symbol will have been on the
+	     undefined symbol list.  */
+	  struct bfd_link_hash_entry *next;
+	  bfd *abfd;		/* BFD symbol was found in.  */
+	} undef;
+      /* bfd_link_hash_defined, bfd_link_hash_defweak.  */
+      struct
+	{
+	  struct bfd_link_hash_entry *next;
+	  asection *section;	/* Symbol section.  */
+	  bfd_vma value;	/* Symbol value.  */
+	} def;
+      /* bfd_link_hash_indirect, bfd_link_hash_warning.  */
+      struct
+	{
+	  struct bfd_link_hash_entry *next;
+	  struct bfd_link_hash_entry *link;	/* Real symbol.  */
+	  const char *warning;	/* Warning (bfd_link_hash_warning only).  */
+	} i;
+      /* bfd_link_hash_common.  */
+      struct
+	{
+	  struct bfd_link_hash_entry *next;
+	  /* The linker needs to know three things about common
+	     symbols: the size, the alignment, and the section in
+	     which the symbol should be placed.  We store the size
+	     here, and we allocate a small structure to hold the
+	     section and the alignment.  The alignment is stored as a
+	     power of two.  We don't store all the information
+	     directly because we don't want to increase the size of
+	     the union; this structure is a major space user in the
+	     linker.  */
+	  struct bfd_link_hash_common_entry *p;
+	  bfd_size_type size;	/* Common symbol size.  */
+	} c;
+    } u;
+};
+
+/* This is the link hash table.  It is a derived class of
+   bfd_hash_table.  */
+
+struct bfd_link_hash_table
+{
+  /* The hash table itself.  */
+  struct bfd_hash_table table;
+  /* A linked list of undefined and common symbols, linked through the
+     next field in the bfd_link_hash_entry structure.  */
+  struct bfd_link_hash_entry *undefs;
+  /* Entries are added to the tail of the undefs list.  */
+  struct bfd_link_hash_entry *undefs_tail;
+  /* The type of the link hash table.  */
+  enum bfd_link_hash_table_type type;
+};
+
+/* Look up an entry in a link hash table.  If FOLLOW is TRUE, this
+   follows bfd_link_hash_indirect and bfd_link_hash_warning links to
+   the real symbol.  */
+extern struct bfd_link_hash_entry *bfd_link_hash_lookup
+  (struct bfd_link_hash_table *, const char *, bfd_boolean create,
+   bfd_boolean copy, bfd_boolean follow);
+
+/* Look up an entry in the main linker hash table if the symbol might
+   be wrapped.  This should only be used for references to an
+   undefined symbol, not for definitions of a symbol.  */
+
+extern struct bfd_link_hash_entry *bfd_wrapped_link_hash_lookup
+  (bfd *, struct bfd_link_info *, const char *, bfd_boolean,
+   bfd_boolean, bfd_boolean);
+
+/* Traverse a link hash table.  */
+extern void bfd_link_hash_traverse
+  (struct bfd_link_hash_table *,
+    bfd_boolean (*) (struct bfd_link_hash_entry *, void *),
+    void *);
+
+/* Add an entry to the undefs list.  */
+extern void bfd_link_add_undef
+  (struct bfd_link_hash_table *, struct bfd_link_hash_entry *);
+
+/* Remove symbols from the undefs list that don't belong there.  */
+extern void bfd_link_repair_undef_list
+  (struct bfd_link_hash_table *table);
+
+/* Read symbols and cache symbol pointer array in outsymbols.  */
+extern bfd_boolean bfd_generic_link_read_symbols (bfd *);
+
+struct bfd_sym_chain
+{
+  struct bfd_sym_chain *next;
+  const char *name;
+};
+
+/* How to handle unresolved symbols.
+   There are four possibilities which are enumerated below:  */
+enum report_method
+{
+  /* This is the initial value when then link_info structure is created.
+     It allows the various stages of the linker to determine whether they
+     allowed to set the value.  */
+  RM_NOT_YET_SET = 0,
+  RM_IGNORE,
+  RM_GENERATE_WARNING,
+  RM_GENERATE_ERROR
+};
+
+typedef enum {with_flags, without_flags} flag_type;
+
+/* A section flag list.  */
+struct flag_info_list
+{
+  flag_type with;
+  const char *name;
+  bfd_boolean valid;
+  struct flag_info_list *next;
+};
+
+/* Section flag info.  */
+struct flag_info
+{
+  flagword only_with_flags;
+  flagword not_with_flags;
+  struct flag_info_list *flag_list;
+  bfd_boolean flags_initialized;
+};
+
+struct bfd_elf_dynamic_list;
+struct bfd_elf_version_tree;
+
+/* This structure holds all the information needed to communicate
+   between BFD and the linker when doing a link.  */
+
+struct bfd_link_info
+{
+  /* TRUE if BFD should generate a shared object (or a pie).  */
+  unsigned int shared: 1;
+
+  /* TRUE if generating an executable, position independent or not.  */
+  unsigned int executable : 1;
+
+  /* TRUE if generating a position independent executable.  */
+  unsigned int pie: 1;
+
+  /* TRUE if BFD should generate a relocatable object file.  */
+  unsigned int relocatable: 1;
+
+  /* TRUE if BFD should pre-bind symbols in a shared object.  */
+  unsigned int symbolic: 1;
+
+  /* TRUE if executable should not contain copy relocs.
+     Setting this true may result in a non-sharable text segment.  */
+  unsigned int nocopyreloc: 1;
+
+  /* TRUE if BFD should export all symbols in the dynamic symbol table
+     of an executable, rather than only those used.  */
+  unsigned int export_dynamic: 1;
+
+  /* TRUE if a default symbol version should be created and used for
+     exported symbols.  */
+  unsigned int create_default_symver: 1;
+
+  /* TRUE if unreferenced sections should be removed.  */
+  unsigned int gc_sections: 1;
+
+  /* TRUE if every symbol should be reported back via the notice
+     callback.  */
+  unsigned int notice_all: 1;
+
+  /* TRUE if we are loading LTO outputs.  */
+  unsigned int loading_lto_outputs: 1;
+
+  /* TRUE if global symbols in discarded sections should be stripped.  */
+  unsigned int strip_discarded: 1;
+
+  /* TRUE if all data symbols should be dynamic.  */
+  unsigned int dynamic_data: 1;
+
+  /* Which symbols to strip.  */
+  ENUM_BITFIELD (bfd_link_strip) strip : 2;
+
+  /* Which local symbols to discard.  */
+  ENUM_BITFIELD (bfd_link_discard) discard : 2;
+
+  /* Criteria for skipping symbols when determining
+     whether to include an object from an archive. */
+  ENUM_BITFIELD (bfd_link_common_skip_ar_symbols) common_skip_ar_symbols : 2;
+
+  /* What to do with unresolved symbols in an object file.
+     When producing executables the default is GENERATE_ERROR.
+     When producing shared libraries the default is IGNORE.  The
+     assumption with shared libraries is that the reference will be
+     resolved at load/execution time.  */
+  ENUM_BITFIELD (report_method) unresolved_syms_in_objects : 2;
+
+  /* What to do with unresolved symbols in a shared library.
+     The same defaults apply.  */
+  ENUM_BITFIELD (report_method) unresolved_syms_in_shared_libs : 2;
+
+  /* TRUE if shared objects should be linked directly, not shared.  */
+  unsigned int static_link: 1;
+
+  /* TRUE if symbols should be retained in memory, FALSE if they
+     should be freed and reread.  */
+  unsigned int keep_memory: 1;
+
+  /* TRUE if BFD should generate relocation information in the final
+     executable.  */
+  unsigned int emitrelocations: 1;
+
+  /* TRUE if PT_GNU_RELRO segment should be created.  */
+  unsigned int relro: 1;
+
+  /* TRUE if .eh_frame_hdr section and PT_GNU_EH_FRAME ELF segment
+     should be created.  */
+  unsigned int eh_frame_hdr: 1;
+
+  /* TRUE if we should warn when adding a DT_TEXTREL to a shared object.  */
+  unsigned int warn_shared_textrel: 1;
+
+  /* TRUE if we should error when adding a DT_TEXTREL.  */
+  unsigned int error_textrel: 1;
+
+  /* TRUE if .hash section should be created.  */
+  unsigned int emit_hash: 1;
+
+  /* TRUE if .gnu.hash section should be created.  */
+  unsigned int emit_gnu_hash: 1;
+
+  /* If TRUE reduce memory overheads, at the expense of speed. This will
+     cause map file generation to use an O(N^2) algorithm and disable
+     caching ELF symbol buffer.  */
+  unsigned int reduce_memory_overheads: 1;
+
+  /* TRUE if the output file should be in a traditional format.  This
+     is equivalent to the setting of the BFD_TRADITIONAL_FORMAT flag
+     on the output file, but may be checked when reading the input
+     files.  */
+  unsigned int traditional_format: 1;
+
+  /* TRUE if non-PLT relocs should be merged into one reloc section
+     and sorted so that relocs against the same symbol come together.  */
+  unsigned int combreloc: 1;
+
+  /* TRUE if a default symbol version should be created and used for
+     imported symbols.  */
+  unsigned int default_imported_symver: 1;
+
+  /* TRUE if the new ELF dynamic tags are enabled. */
+  unsigned int new_dtags: 1;
+
+  /* FALSE if .eh_frame unwind info should be generated for PLT and other
+     linker created sections, TRUE if it should be omitted.  */
+  unsigned int no_ld_generated_unwind_info: 1;
+
+  /* TRUE if BFD should generate a "task linked" object file,
+     similar to relocatable but also with globals converted to
+     statics.  */
+  unsigned int task_link: 1;
+
+  /* TRUE if ok to have multiple definition.  */
+  unsigned int allow_multiple_definition: 1;
+
+  /* TRUE if ok to have version with no definition.  */
+  unsigned int allow_undefined_version: 1;
+
+  /* TRUE if some symbols have to be dynamic, controlled by
+     --dynamic-list command line options.  */
+  unsigned int dynamic: 1;
+
+  /* TRUE if PT_GNU_STACK segment should be created with PF_R|PF_W|PF_X
+     flags.  */
+  unsigned int execstack: 1;
+
+  /* TRUE if PT_GNU_STACK segment should be created with PF_R|PF_W
+     flags.  */
+  unsigned int noexecstack: 1;
+
+  /* TRUE if we want to produced optimized output files.  This might
+     need much more time and therefore must be explicitly selected.  */
+  unsigned int optimize: 1;
+
+  /* TRUE if user should be informed of removed unreferenced sections.  */
+  unsigned int print_gc_sections: 1;
+
+  /* TRUE if we should warn alternate ELF machine code.  */
+  unsigned int warn_alternate_em: 1;
+
+  /* TRUE if the linker script contained an explicit PHDRS command.  */
+  unsigned int user_phdrs: 1;
+
+  /* Char that may appear as the first char of a symbol, but should be
+     skipped (like symbol_leading_char) when looking up symbols in
+     wrap_hash.  Used by PowerPC Linux for 'dot' symbols.  */
+  char wrap_char;
+
+  /* Separator between archive and filename in linker script filespecs.  */
+  char path_separator;
+
+  /* Default stack size.  Zero means default (often zero itself), -1
+     means explicitly zero-sized.  */
+  bfd_signed_vma stacksize;
+
+  /* Enable or disable target specific optimizations.
+
+     Not all targets have optimizations to enable.
+
+     Normally these optimizations are disabled by default but some targets
+     prefer to enable them by default.  So this field is a tri-state variable.
+     The values are:
+     
+     zero: Enable the optimizations (either from --relax being specified on
+       the command line or the backend's before_allocation emulation function.
+       
+     positive: The user has requested that these optimizations be disabled.
+       (Via the --no-relax command line option).
+
+     negative: The optimizations are disabled.  (Set when initializing the
+       args_type structure in ldmain.c:main.  */
+  signed int disable_target_specific_optimizations;
+
+  /* Function callbacks.  */
+  const struct bfd_link_callbacks *callbacks;
+
+  /* Hash table handled by BFD.  */
+  struct bfd_link_hash_table *hash;
+
+  /* Hash table of symbols to keep.  This is NULL unless strip is
+     strip_some.  */
+  struct bfd_hash_table *keep_hash;
+
+  /* Hash table of symbols to report back via the notice callback.  If
+     this is NULL, and notice_all is FALSE, then no symbols are
+     reported back.  */
+  struct bfd_hash_table *notice_hash;
+
+  /* Hash table of symbols which are being wrapped (the --wrap linker
+     option).  If this is NULL, no symbols are being wrapped.  */
+  struct bfd_hash_table *wrap_hash;
+
+  /* Hash table of symbols which may be left unresolved during
+     a link.  If this is NULL, no symbols can be left unresolved.  */
+  struct bfd_hash_table *ignore_hash;
+
+  /* The output BFD.  */
+  bfd *output_bfd;
+
+  /* The list of input BFD's involved in the link.  These are chained
+     together via the link_next field.  */
+  bfd *input_bfds;
+  bfd **input_bfds_tail;
+
+  /* If a symbol should be created for each input BFD, this is section
+     where those symbols should be placed.  It must be a section in
+     the output BFD.  It may be NULL, in which case no such symbols
+     will be created.  This is to support CREATE_OBJECT_SYMBOLS in the
+     linker command language.  */
+  asection *create_object_symbols_section;
+
+  /* List of global symbol names that are starting points for marking
+     sections against garbage collection.  */
+  struct bfd_sym_chain *gc_sym_list;
+
+  /* If a base output file is wanted, then this points to it */
+  void *base_file;
+
+  /* The function to call when the executable or shared object is
+     loaded.  */
+  const char *init_function;
+
+  /* The function to call when the executable or shared object is
+     unloaded.  */
+  const char *fini_function;
+
+  /* Number of relaxation passes.  Usually only one relaxation pass
+     is needed.  But a backend can have as many relaxation passes as
+     necessary.  During bfd_relax_section call, it is set to the
+     current pass, starting from 0.  */
+  int relax_pass;
+
+  /* Number of relaxation trips.  This number is incremented every
+     time the relaxation pass is restarted due to a previous
+     relaxation returning true in *AGAIN.  */
+  int relax_trip;
+
+  /* Non-zero if auto-import thunks for DATA items in pei386 DLLs
+     should be generated/linked against.  Set to 1 if this feature
+     is explicitly requested by the user, -1 if enabled by default.  */
+  int pei386_auto_import;
+
+  /* Non-zero if runtime relocs for DATA items with non-zero addends
+     in pei386 DLLs should be generated.  Set to 1 if this feature
+     is explicitly requested by the user, -1 if enabled by default.  */
+  int pei386_runtime_pseudo_reloc;
+
+  /* How many spare .dynamic DT_NULL entries should be added?  */
+  unsigned int spare_dynamic_tags;
+
+  /* May be used to set DT_FLAGS for ELF. */
+  bfd_vma flags;
+
+  /* May be used to set DT_FLAGS_1 for ELF. */
+  bfd_vma flags_1;
+
+  /* Start and end of RELRO region.  */
+  bfd_vma relro_start, relro_end;
+
+  /* List of symbols should be dynamic.  */
+  struct bfd_elf_dynamic_list *dynamic_list;
+
+  /* The version information.  */
+  struct bfd_elf_version_tree *version_info;
+};
+
+/* This structures holds a set of callback functions.  These are called
+   by the BFD linker routines.  Except for the info functions, the first
+   argument to each callback function is the bfd_link_info structure
+   being used and each function returns a boolean value.  If the
+   function returns FALSE, then the BFD function which called it should
+   return with a failure indication.  */
+
+struct bfd_link_callbacks
+{
+  /* A function which is called when an object is added from an
+     archive.  ABFD is the archive element being added.  NAME is the
+     name of the symbol which caused the archive element to be pulled
+     in.  This function may set *SUBSBFD to point to an alternative
+     BFD from which symbols should in fact be added in place of the
+     original BFD's symbols.  */
+  bfd_boolean (*add_archive_element)
+    (struct bfd_link_info *, bfd *abfd, const char *name, bfd **subsbfd);
+  /* A function which is called when a symbol is found with multiple
+     definitions.  H is the symbol which is defined multiple times.
+     NBFD is the new BFD, NSEC is the new section, and NVAL is the new
+     value.  NSEC may be bfd_com_section or bfd_ind_section.  */
+  bfd_boolean (*multiple_definition)
+    (struct bfd_link_info *, struct bfd_link_hash_entry *h,
+     bfd *nbfd, asection *nsec, bfd_vma nval);
+  /* A function which is called when a common symbol is defined
+     multiple times.  H is the symbol appearing multiple times.
+     NBFD is the BFD of the new symbol.  NTYPE is the type of the new
+     symbol, one of bfd_link_hash_defined, bfd_link_hash_common, or
+     bfd_link_hash_indirect.  If NTYPE is bfd_link_hash_common, NSIZE
+     is the size of the new symbol.  */
+  bfd_boolean (*multiple_common)
+    (struct bfd_link_info *, struct bfd_link_hash_entry *h,
+     bfd *nbfd, enum bfd_link_hash_type ntype, bfd_vma nsize);
+  /* A function which is called to add a symbol to a set.  ENTRY is
+     the link hash table entry for the set itself (e.g.,
+     __CTOR_LIST__).  RELOC is the relocation to use for an entry in
+     the set when generating a relocatable file, and is also used to
+     get the size of the entry when generating an executable file.
+     ABFD, SEC and VALUE identify the value to add to the set.  */
+  bfd_boolean (*add_to_set)
+    (struct bfd_link_info *, struct bfd_link_hash_entry *entry,
+     bfd_reloc_code_real_type reloc, bfd *abfd, asection *sec, bfd_vma value);
+  /* A function which is called when the name of a g++ constructor or
+     destructor is found.  This is only called by some object file
+     formats.  CONSTRUCTOR is TRUE for a constructor, FALSE for a
+     destructor.  This will use BFD_RELOC_CTOR when generating a
+     relocatable file.  NAME is the name of the symbol found.  ABFD,
+     SECTION and VALUE are the value of the symbol.  */
+  bfd_boolean (*constructor)
+    (struct bfd_link_info *, bfd_boolean constructor, const char *name,
+     bfd *abfd, asection *sec, bfd_vma value);
+  /* A function which is called to issue a linker warning.  For
+     example, this is called when there is a reference to a warning
+     symbol.  WARNING is the warning to be issued.  SYMBOL is the name
+     of the symbol which triggered the warning; it may be NULL if
+     there is none.  ABFD, SECTION and ADDRESS identify the location
+     which trigerred the warning; either ABFD or SECTION or both may
+     be NULL if the location is not known.  */
+  bfd_boolean (*warning)
+    (struct bfd_link_info *, const char *warning, const char *symbol,
+     bfd *abfd, asection *section, bfd_vma address);
+  /* A function which is called when a relocation is attempted against
+     an undefined symbol.  NAME is the symbol which is undefined.
+     ABFD, SECTION and ADDRESS identify the location from which the
+     reference is made. IS_FATAL indicates whether an undefined symbol is
+     a fatal error or not. In some cases SECTION may be NULL.  */
+  bfd_boolean (*undefined_symbol)
+    (struct bfd_link_info *, const char *name, bfd *abfd,
+     asection *section, bfd_vma address, bfd_boolean is_fatal);
+  /* A function which is called when a reloc overflow occurs. ENTRY is
+     the link hash table entry for the symbol the reloc is against.
+     NAME is the name of the local symbol or section the reloc is
+     against, RELOC_NAME is the name of the relocation, and ADDEND is
+     any addend that is used.  ABFD, SECTION and ADDRESS identify the
+     location at which the overflow occurs; if this is the result of a
+     bfd_section_reloc_link_order or bfd_symbol_reloc_link_order, then
+     ABFD will be NULL.  */
+  bfd_boolean (*reloc_overflow)
+    (struct bfd_link_info *, struct bfd_link_hash_entry *entry,
+     const char *name, const char *reloc_name, bfd_vma addend,
+     bfd *abfd, asection *section, bfd_vma address);
+  /* A function which is called when a dangerous reloc is performed.
+     MESSAGE is an appropriate message.
+     ABFD, SECTION and ADDRESS identify the location at which the
+     problem occurred; if this is the result of a
+     bfd_section_reloc_link_order or bfd_symbol_reloc_link_order, then
+     ABFD will be NULL.  */
+  bfd_boolean (*reloc_dangerous)
+    (struct bfd_link_info *, const char *message,
+     bfd *abfd, asection *section, bfd_vma address);
+  /* A function which is called when a reloc is found to be attached
+     to a symbol which is not being written out.  NAME is the name of
+     the symbol.  ABFD, SECTION and ADDRESS identify the location of
+     the reloc; if this is the result of a
+     bfd_section_reloc_link_order or bfd_symbol_reloc_link_order, then
+     ABFD will be NULL.  */
+  bfd_boolean (*unattached_reloc)
+    (struct bfd_link_info *, const char *name,
+     bfd *abfd, asection *section, bfd_vma address);
+  /* A function which is called when a symbol in notice_hash is
+     defined or referenced.  H is the symbol.  ABFD, SECTION and
+     ADDRESS are the (new) value of the symbol.  If SECTION is
+     bfd_und_section, this is a reference.  FLAGS are the symbol
+     BSF_* flags.  STRING is the name of the symbol to indirect to if
+     the sym is indirect, or the warning string if a warning sym.  */
+  bfd_boolean (*notice)
+    (struct bfd_link_info *, struct bfd_link_hash_entry *h,
+     bfd *abfd, asection *section, bfd_vma address, flagword flags,
+     const char *string);
+  /* Error or warning link info message.  */
+  void (*einfo)
+    (const char *fmt, ...);
+  /* General link info message.  */
+  void (*info)
+    (const char *fmt, ...);
+  /* Message to be printed in linker map file.  */
+  void (*minfo)
+    (const char *fmt, ...);
+  /* This callback provides a chance for users of the BFD library to
+     override its decision about whether to place two adjacent sections
+     into the same segment.  */
+  bfd_boolean (*override_segment_assignment)
+    (struct bfd_link_info *, bfd * abfd,
+     asection * current_section, asection * previous_section,
+     bfd_boolean new_segment);
+};
+
+/* The linker builds link_order structures which tell the code how to
+   include input data in the output file.  */
+
+/* These are the types of link_order structures.  */
+
+enum bfd_link_order_type
+{
+  bfd_undefined_link_order,	/* Undefined.  */
+  bfd_indirect_link_order,	/* Built from a section.  */
+  bfd_data_link_order,		/* Set to explicit data.  */
+  bfd_section_reloc_link_order,	/* Relocate against a section.  */
+  bfd_symbol_reloc_link_order	/* Relocate against a symbol.  */
+};
+
+/* This is the link_order structure itself.  These form a chain
+   attached to the output section whose contents they are describing.  */
+
+struct bfd_link_order
+{
+  /* Next link_order in chain.  */
+  struct bfd_link_order *next;
+  /* Type of link_order.  */
+  enum bfd_link_order_type type;
+  /* Offset within output section.  */
+  bfd_vma offset;
+  /* Size within output section.  */
+  bfd_size_type size;
+  /* Type specific information.  */
+  union
+    {
+      struct
+	{
+	  /* Section to include.  If this is used, then
+	     section->output_section must be the section the
+	     link_order is attached to, section->output_offset must
+	     equal the link_order offset field, and section->size
+	     must equal the link_order size field.  Maybe these
+	     restrictions should be relaxed someday.  */
+	  asection *section;
+	} indirect;
+      struct
+	{
+	  /* Size of contents, or zero when contents should be filled by
+	     the architecture-dependent fill function.
+	     A non-zero value allows filling of the output section
+	     with an arbitrary repeated pattern.  */
+	  unsigned int size;
+	  /* Data to put into file.  */
+	  bfd_byte *contents;
+	} data;
+      struct
+	{
+	  /* Description of reloc to generate.  Used for
+	     bfd_section_reloc_link_order and
+	     bfd_symbol_reloc_link_order.  */
+	  struct bfd_link_order_reloc *p;
+	} reloc;
+    } u;
+};
+
+/* A linker order of type bfd_section_reloc_link_order or
+   bfd_symbol_reloc_link_order means to create a reloc against a
+   section or symbol, respectively.  This is used to implement -Ur to
+   generate relocs for the constructor tables.  The
+   bfd_link_order_reloc structure describes the reloc that BFD should
+   create.  It is similar to a arelent, but I didn't use arelent
+   because the linker does not know anything about most symbols, and
+   any asymbol structure it creates will be partially meaningless.
+   This information could logically be in the bfd_link_order struct,
+   but I didn't want to waste the space since these types of relocs
+   are relatively rare.  */
+
+struct bfd_link_order_reloc
+{
+  /* Reloc type.  */
+  bfd_reloc_code_real_type reloc;
+
+  union
+    {
+      /* For type bfd_section_reloc_link_order, this is the section
+	 the reloc should be against.  This must be a section in the
+	 output BFD, not any of the input BFDs.  */
+      asection *section;
+      /* For type bfd_symbol_reloc_link_order, this is the name of the
+	 symbol the reloc should be against.  */
+      const char *name;
+    } u;
+
+  /* Addend to use.  The object file should contain zero.  The BFD
+     backend is responsible for filling in the contents of the object
+     file correctly.  For some object file formats (e.g., COFF) the
+     addend must be stored into in the object file, and for some
+     (e.g., SPARC a.out) it is kept in the reloc.  */
+  bfd_vma addend;
+};
+
+/* Allocate a new link_order for a section.  */
+extern struct bfd_link_order *bfd_new_link_order (bfd *, asection *);
+
+/* These structures are used to describe version information for the
+   ELF linker.  These structures could be manipulated entirely inside
+   BFD, but it would be a pain.  Instead, the regular linker sets up
+   these structures, and then passes them into BFD.  */
+
+/* Glob pattern for a version.  */
+
+struct bfd_elf_version_expr
+{
+  /* Next glob pattern for this version.  */
+  struct bfd_elf_version_expr *next;
+  /* Glob pattern.  */
+  const char *pattern;
+  /* Set if pattern is not a glob.  */
+  unsigned int literal : 1;
+  /* Defined by ".symver".  */
+  unsigned int symver : 1;
+  /* Defined by version script.  */
+  unsigned int script : 1;
+  /* Pattern type.  */
+#define BFD_ELF_VERSION_C_TYPE		1
+#define BFD_ELF_VERSION_CXX_TYPE	2
+#define BFD_ELF_VERSION_JAVA_TYPE	4
+  unsigned int mask : 3;
+};
+
+struct bfd_elf_version_expr_head
+{
+  /* List of all patterns, both wildcards and non-wildcards.  */
+  struct bfd_elf_version_expr *list;
+  /* Hash table for non-wildcards.  */
+  void *htab;
+  /* Remaining patterns.  */
+  struct bfd_elf_version_expr *remaining;
+  /* What kind of pattern types are present in list (bitmask).  */
+  unsigned int mask;
+};
+
+/* Version dependencies.  */
+
+struct bfd_elf_version_deps
+{
+  /* Next dependency for this version.  */
+  struct bfd_elf_version_deps *next;
+  /* The version which this version depends upon.  */
+  struct bfd_elf_version_tree *version_needed;
+};
+
+/* A node in the version tree.  */
+
+struct bfd_elf_version_tree
+{
+  /* Next version.  */
+  struct bfd_elf_version_tree *next;
+  /* Name of this version.  */
+  const char *name;
+  /* Version number.  */
+  unsigned int vernum;
+  /* Regular expressions for global symbols in this version.  */
+  struct bfd_elf_version_expr_head globals;
+  /* Regular expressions for local symbols in this version.  */
+  struct bfd_elf_version_expr_head locals;
+  /* List of versions which this version depends upon.  */
+  struct bfd_elf_version_deps *deps;
+  /* Index of the version name.  This is used within BFD.  */
+  unsigned int name_indx;
+  /* Whether this version tree was used.  This is used within BFD.  */
+  int used;
+  /* Matching hook.  */
+  struct bfd_elf_version_expr *(*match)
+    (struct bfd_elf_version_expr_head *head,
+     struct bfd_elf_version_expr *prev, const char *sym);
+};
+
+struct bfd_elf_dynamic_list
+{
+  struct bfd_elf_version_expr_head head;
+  struct bfd_elf_version_expr *(*match)
+    (struct bfd_elf_version_expr_head *head,
+     struct bfd_elf_version_expr *prev, const char *sym);
+};
+
+#endif
diff --git a/binutils-2.25/include/binary-io.h b/binutils-2.25/include/binary-io.h
new file mode 100644
index 00000000..2984271f
--- /dev/null
+++ b/binutils-2.25/include/binary-io.h
@@ -0,0 +1,62 @@
+/* Binary mode I/O.
+   Copyright (C) 2001, 2003, 2005, 2008 Free Software Foundation, Inc.
+
+   This program is free software: you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#ifndef _BINARY_H
+#define _BINARY_H
+
+/* Include this header after <fcntl.h> and <stdio.h>, because
+   systems that distinguish between text and binary I/O usually
+   define O_BINARY in <fcntl.h>, and the MSVC7 <stdio.h> doesn't
+   like to be included after '#define fileno ...'
+
+   We don't include <fcntl.h> here because not all systems have
+   that header.  */
+
+#if !defined O_BINARY && defined _O_BINARY
+  /* For MSC-compatible compilers.  */
+# define O_BINARY _O_BINARY
+# define O_TEXT _O_TEXT
+#endif
+#ifdef __BEOS__
+  /* BeOS 5 has O_BINARY and O_TEXT, but they have no effect.  */
+# undef O_BINARY
+# undef O_TEXT
+#endif
+#if O_BINARY
+# if defined __EMX__ || defined __DJGPP__ || defined __CYGWIN__
+#  include <io.h> /* declares setmode() */
+# else
+#  define setmode _setmode
+#  undef fileno
+#  define fileno _fileno
+# endif
+# ifdef __DJGPP__
+#  include <unistd.h> /* declares isatty() */
+#  /* Avoid putting stdin/stdout in binary mode if it is connected to the
+#     console, because that would make it impossible for the user to
+#     interrupt the program through Ctrl-C or Ctrl-Break.  */
+#  define SET_BINARY(fd) (!isatty (fd) ? (setmode (fd, O_BINARY), 0) : 0)
+# else
+#  define SET_BINARY(fd) setmode (fd, O_BINARY)
+# endif
+#else
+  /* On reasonable systems, binary I/O is the default.  */
+# undef O_BINARY
+# define O_BINARY 0
+# define SET_BINARY(fd) /* nothing */
+#endif
+
+#endif /* _BINARY_H */
diff --git a/binutils-2.25/include/bout.h b/binutils-2.25/include/bout.h
new file mode 100644
index 00000000..4a302283
--- /dev/null
+++ b/binutils-2.25/include/bout.h
@@ -0,0 +1,192 @@
+/* This file is a modified version of 'a.out.h'.  It is to be used in all
+   GNU tools modified to support the i80960 (or tools that operate on
+   object files created by such tools).
+
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+ 
+/* All i80960 development is done in a CROSS-DEVELOPMENT environment.  I.e.,
+   object code is generated on, and executed under the direction of a symbolic
+   debugger running on, a host system.  We do not want to be subject to the
+   vagaries of which host it is or whether it supports COFF or a.out format,
+   or anything else.  We DO want to:
+  
+  	o always generate the same format object files, regardless of host.
+ 
+ 	o have an 'a.out' header that we can modify for our own purposes
+ 	  (the 80960 is typically an embedded processor and may require
+ 	  enhanced linker support that the normal a.out.h header can't
+ 	  accommodate).
+ 
+  As for byte-ordering, the following rules apply:
+ 
+ 	o Text and data that is actually downloaded to the target is always
+ 	  in i80960 (little-endian) order.
+ 
+ 	o All other numbers (in the header, symbols, relocation directives)
+ 	  are in host byte-order:  object files CANNOT be lifted from a
+ 	  little-end host and used on a big-endian (or vice versa) without
+ 	  modification.
+  ==> THIS IS NO LONGER TRUE USING BFD.  WE CAN GENERATE ANY BYTE ORDER
+      FOR THE HEADER, AND READ ANY BYTE ORDER.  PREFERENCE WOULD BE TO
+      USE LITTLE-ENDIAN BYTE ORDER THROUGHOUT, REGARDLESS OF HOST.  <==
+ 
+ 	o The downloader ('comm960') takes care to generate a pseudo-header
+ 	  with correct (i80960) byte-ordering before shipping text and data
+ 	  off to the NINDY monitor in the target systems.  Symbols and
+ 	  relocation info are never sent to the target.  */
+
+#define BMAGIC	0415
+/* We don't accept the following (see N_BADMAG macro).
+   They're just here so GNU code will compile.  */
+#define	OMAGIC	0407		/* old impure format */
+#define	NMAGIC	0410		/* read-only text */
+#define	ZMAGIC	0413		/* demand load format */
+
+/* FILE HEADER
+  	All 'lengths' are given as a number of bytes.
+  	All 'alignments' are for relinkable files only;  an alignment of
+  		'n' indicates the corresponding segment must begin at an
+  		address that is a multiple of (2**n).  */
+struct external_exec
+  {
+    /* Standard stuff */
+    unsigned char e_info[4];	/* Identifies this as a b.out file */
+    unsigned char e_text[4];	/* Length of text */
+    unsigned char e_data[4];	/* Length of data */
+    unsigned char e_bss[4];	/* Length of uninitialized data area */
+    unsigned char e_syms[4];	/* Length of symbol table */
+    unsigned char e_entry[4];	/* Runtime start address */
+    unsigned char e_trsize[4];	/* Length of text relocation info */
+    unsigned char e_drsize[4];	/* Length of data relocation info */
+
+    /* Added for i960 */
+    unsigned char e_tload[4];	/* Text runtime load address */
+    unsigned char e_dload[4];	/* Data runtime load address */
+    unsigned char e_talign[1];	/* Alignment of text segment */
+    unsigned char e_dalign[1];	/* Alignment of data segment */
+    unsigned char e_balign[1];	/* Alignment of bss segment */
+    unsigned char e_relaxable[1];/* Assembled with enough info to allow linker to relax */
+  };
+
+#define	EXEC_BYTES_SIZE	(sizeof (struct external_exec))
+
+/* These macros use the a_xxx field names, since they operate on the exec
+   structure after it's been byte-swapped and realigned on the host machine.  */
+#define N_BADMAG(x)	(((x).a_info)!=BMAGIC)
+#define N_TXTOFF(x)	EXEC_BYTES_SIZE
+#define N_DATOFF(x)	( N_TXTOFF(x) + (x).a_text )
+#define N_TROFF(x)	( N_DATOFF(x) + (x).a_data )
+#define N_TRELOFF	N_TROFF
+#define N_DROFF(x)	( N_TROFF(x) + (x).a_trsize )
+#define N_DRELOFF	N_DROFF
+#define N_SYMOFF(x)	( N_DROFF(x) + (x).a_drsize )
+#define N_STROFF(x)	( N_SYMOFF(x) + (x).a_syms )
+#define N_DATADDR(x)	( (x).a_dload )    
+
+/* Address of text segment in memory after it is loaded.  */
+#if !defined (N_TXTADDR)
+#define N_TXTADDR(x) 0
+#endif
+
+/* A single entry in the symbol table.  */
+struct nlist
+  {
+    union
+      {
+	char*          n_name;
+	struct nlist * n_next;
+	long	       n_strx;	/* Index into string table	*/
+      } n_un;
+
+    unsigned char n_type;	/* See below				*/
+    char	  n_other;	/* Used in i80960 support -- see below	*/
+    short	  n_desc;
+    unsigned long n_value;
+  };
+
+
+/* Legal values of n_type.  */
+#define N_UNDF	0	/* Undefined symbol	*/
+#define N_ABS	2	/* Absolute symbol	*/
+#define N_TEXT	4	/* Text symbol		*/
+#define N_DATA	6	/* Data symbol		*/
+#define N_BSS	8	/* BSS symbol		*/
+#define N_FN	31	/* Filename symbol	*/
+
+#define N_EXT	1	/* External symbol (OR'd in with one of above)	*/
+#define N_TYPE	036	/* Mask for all the type bits			*/
+#define N_STAB	0340	/* Mask for all bits used for SDB entries 	*/
+
+/* MEANING OF 'n_other'
+ 
+  If non-zero, the 'n_other' fields indicates either a leaf procedure or
+  a system procedure, as follows:
+ 
+ 	1 <= n_other <= 32 :
+ 		The symbol is the entry point to a system procedure.
+ 		'n_value' is the address of the entry, as for any other
+ 		procedure.  The system procedure number (which can be used in
+ 		a 'calls' instruction) is (n_other-1).  These entries come from
+ 		'.sysproc' directives.
+ 
+ 	n_other == N_CALLNAME
+ 		the symbol is the 'call' entry point to a leaf procedure.
+ 		The *next* symbol in the symbol table must be the corresponding
+ 		'bal' entry point to the procedure (see following).  These
+ 		entries come from '.leafproc' directives in which two different
+ 		symbols are specified (the first one is represented here).
+ 	
+ 
+ 	n_other == N_BALNAME
+ 		the symbol is the 'bal' entry point to a leaf procedure.
+ 		These entries result from '.leafproc' directives in which only
+ 		one symbol is specified, or in which the same symbol is
+ 		specified twice.
+ 
+  Note that an N_CALLNAME entry *must* have a corresponding N_BALNAME entry,
+  but not every N_BALNAME entry must have an N_CALLNAME entry.  */
+#define N_CALLNAME	((char)-1)
+#define N_BALNAME	((char)-2)
+#define IS_CALLNAME(x)	(N_CALLNAME == (x))
+#define IS_BALNAME(x)	(N_BALNAME == (x))
+#define IS_OTHER(x)	((x)>0 && (x) <=32)
+
+#define b_out_relocation_info relocation_info
+struct relocation_info
+  {
+    int	 r_address;	/* File address of item to be relocated.  */
+    unsigned
+#define r_index r_symbolnum
+    r_symbolnum:24,	/* Index of symbol on which relocation is based,
+			   if r_extern is set.  Otherwise set to
+			   either N_TEXT, N_DATA, or N_BSS to
+			   indicate section on which relocation is
+			   based.  */
+      r_pcrel:1,	/* 1 => relocate PC-relative; else absolute
+			   On i960, pc-relative implies 24-bit
+			   address, absolute implies 32-bit.  */
+      r_length:2,	/* Number of bytes to relocate:
+			   0 => 1 byte
+			   1 => 2 bytes -- used for 13 bit pcrel
+			   2 => 4 bytes.  */
+      r_extern:1,
+      r_bsr:1,		/* Something for the GNU NS32K assembler.  */
+      r_disp:1,		/* Something for the GNU NS32K assembler.  */
+      r_callj:1,	/* 1 if relocation target is an i960 'callj'.  */
+      r_relaxable:1;	/* 1 if enough info is left to relax the data.  */
+};
diff --git a/binutils-2.25/include/cgen/ChangeLog b/binutils-2.25/include/cgen/ChangeLog
new file mode 100644
index 00000000..7692d4e5
--- /dev/null
+++ b/binutils-2.25/include/cgen/ChangeLog
@@ -0,0 +1,32 @@
+2013-07-18  Andrew Neitsch  <andrew@neitsch.ca>
+
+	PR binutils/15728
+	* basic-ops.h: (SUBWORDSIQI) Make declaration static.
+	* (SUBWORDSIHI): Likewise.
+	* (SUBWORDDIQI): Likewise.
+	* (SUBWORDDIHI): Likewise.
+	* (SUBWORDDISI): Likewise.
+
+2010-01-05  Doug Evans  <dje@sebabeach.org>
+
+	* basic-modes.h (MAKEDI): New macro.
+
+2009-10-23  Doug Evans  <dje@sebabeach.org>
+
+	* basic-modes.h: New file.  Moved here from opcodes/cgen-types.h.
+	* basic-ops.h: New file.  Moved here from opcodes/cgen-ops.h.
+	* bitset.h: New file.  Moved here from ../opcode/cgen-bitset.h.
+	Update license to GPL v3.
+
+Copyright (C) 2009-2012 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.25/include/cgen/basic-modes.h b/binutils-2.25/include/cgen/basic-modes.h
new file mode 100644
index 00000000..bd87f3ac
--- /dev/null
+++ b/binutils-2.25/include/cgen/basic-modes.h
@@ -0,0 +1,52 @@
+/* Basic CGEN modes.
+   Copyright 2005, 2007, 2009 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+   This file is part of the GNU opcodes library.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this library; see the file COPYING3.  If not, write to the
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#ifndef CGEN_BASIC_MODES_H
+#define CGEN_BASIC_MODES_H
+
+/* This file doesn't contain all modes,
+   just the basic/portable ones.
+   It also provides access to stdint.h (*1) so the includer doesn't have
+   to deal with the portability issues.
+   (*1): To the extent that bfd_stdint.h does for now.  */
+
+/* IWBN to avoid unnecessary dependencies on bfd-anything.  */
+#include "bfd_stdint.h"
+
+typedef int8_t QI;
+typedef uint8_t UQI;
+
+typedef int16_t HI;
+typedef uint16_t UHI;
+
+typedef int32_t SI;
+typedef uint32_t USI;
+
+typedef int64_t DI;
+typedef uint64_t UDI;
+
+typedef int INT;
+typedef unsigned int UINT;
+
+/* Cover macro to create a 64-bit integer.  */
+#define MAKEDI(hi, lo) ((((DI) (SI) (hi)) << 32) | ((UDI) (USI) (lo)))
+
+#endif /* CGEN_BASIC_MODES_H */
diff --git a/binutils-2.25/include/cgen/basic-ops.h b/binutils-2.25/include/cgen/basic-ops.h
new file mode 100644
index 00000000..49883f49
--- /dev/null
+++ b/binutils-2.25/include/cgen/basic-ops.h
@@ -0,0 +1,347 @@
+/* Basic semantics ops support for CGEN.
+   Copyright 2005-2013 Free Software Foundation, Inc.
+   Contributed by Red Hat.
+
+   This file is part of the GNU opcodes library.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this library; see the file COPYING3.  If not, write to the
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#ifndef CGEN_BASIC_OPS_H
+#define CGEN_BASIC_OPS_H
+
+#include <assert.h>
+
+#if defined (__GNUC__) && ! defined (SEMOPS_DEFINE_INLINE)
+#define SEMOPS_DEFINE_INLINE
+#define SEMOPS_INLINE extern inline
+#else
+#define SEMOPS_INLINE
+#endif
+
+/* These don't really have a mode.  */
+#define ANDIF(x, y) ((x) && (y))
+#define ORIF(x, y) ((x) || (y))
+
+#define SUBBI(x, y) ((x) - (y))
+#define ANDBI(x, y) ((x) & (y))
+#define ORBI(x, y) ((x) | (y))
+#define XORBI(x, y) ((x) ^ (y))
+#define NEGBI(x) (- (x))
+#define NOTBI(x) (! (BI) (x))
+#define INVBI(x) (~ (x))
+#define EQBI(x, y) ((BI) (x) == (BI) (y))
+#define NEBI(x, y) ((BI) (x) != (BI) (y))
+#define LTBI(x, y) ((BI) (x) < (BI) (y))
+#define LEBI(x, y) ((BI) (x) <= (BI) (y))
+#define GTBI(x, y) ((BI) (x) > (BI) (y))
+#define GEBI(x, y) ((BI) (x) >= (BI) (y))
+#define LTUBI(x, y) ((BI) (x) < (BI) (y))
+#define LEUBI(x, y) ((BI) (x) <= (BI) (y))
+#define GTUBI(x, y) ((BI) (x) > (BI) (y))
+#define GEUBI(x, y) ((BI) (x) >= (BI) (y))
+
+#define ADDQI(x, y) ((x) + (y))
+#define SUBQI(x, y) ((x) - (y))
+#define MULQI(x, y) ((x) * (y))
+#define DIVQI(x, y) ((QI) (x) / (QI) (y))
+#define UDIVQI(x, y) ((UQI) (x) / (UQI) (y))
+#define MODQI(x, y) ((QI) (x) % (QI) (y))
+#define UMODQI(x, y) ((UQI) (x) % (UQI) (y))
+#define SRAQI(x, y) ((QI) (x) >> (y))
+#define SRLQI(x, y) ((UQI) (x) >> (y))
+#define SLLQI(x, y) ((UQI) (x) << (y))
+extern QI RORQI (QI, int);
+extern QI ROLQI (QI, int);
+#define ANDQI(x, y) ((x) & (y))
+#define ORQI(x, y) ((x) | (y))
+#define XORQI(x, y) ((x) ^ (y))
+#define NEGQI(x) (- (x))
+#define NOTQI(x) (! (QI) (x))
+#define INVQI(x) (~ (x))
+#define ABSQI(x) ((x) < 0 ? -(x) : (x))
+#define EQQI(x, y) ((QI) (x) == (QI) (y))
+#define NEQI(x, y) ((QI) (x) != (QI) (y))
+#define LTQI(x, y) ((QI) (x) < (QI) (y))
+#define LEQI(x, y) ((QI) (x) <= (QI) (y))
+#define GTQI(x, y) ((QI) (x) > (QI) (y))
+#define GEQI(x, y) ((QI) (x) >= (QI) (y))
+#define LTUQI(x, y) ((UQI) (x) < (UQI) (y))
+#define LEUQI(x, y) ((UQI) (x) <= (UQI) (y))
+#define GTUQI(x, y) ((UQI) (x) > (UQI) (y))
+#define GEUQI(x, y) ((UQI) (x) >= (UQI) (y))
+
+#define ADDHI(x, y) ((x) + (y))
+#define SUBHI(x, y) ((x) - (y))
+#define MULHI(x, y) ((x) * (y))
+#define DIVHI(x, y) ((HI) (x) / (HI) (y))
+#define UDIVHI(x, y) ((UHI) (x) / (UHI) (y))
+#define MODHI(x, y) ((HI) (x) % (HI) (y))
+#define UMODHI(x, y) ((UHI) (x) % (UHI) (y))
+#define SRAHI(x, y) ((HI) (x) >> (y))
+#define SRLHI(x, y) ((UHI) (x) >> (y))
+#define SLLHI(x, y) ((UHI) (x) << (y))
+extern HI RORHI (HI, int);
+extern HI ROLHI (HI, int);
+#define ANDHI(x, y) ((x) & (y))
+#define ORHI(x, y) ((x) | (y))
+#define XORHI(x, y) ((x) ^ (y))
+#define NEGHI(x) (- (x))
+#define NOTHI(x) (! (HI) (x))
+#define INVHI(x) (~ (x))
+#define ABSHI(x) ((x) < 0 ? -(x) : (x))
+#define EQHI(x, y) ((HI) (x) == (HI) (y))
+#define NEHI(x, y) ((HI) (x) != (HI) (y))
+#define LTHI(x, y) ((HI) (x) < (HI) (y))
+#define LEHI(x, y) ((HI) (x) <= (HI) (y))
+#define GTHI(x, y) ((HI) (x) > (HI) (y))
+#define GEHI(x, y) ((HI) (x) >= (HI) (y))
+#define LTUHI(x, y) ((UHI) (x) < (UHI) (y))
+#define LEUHI(x, y) ((UHI) (x) <= (UHI) (y))
+#define GTUHI(x, y) ((UHI) (x) > (UHI) (y))
+#define GEUHI(x, y) ((UHI) (x) >= (UHI) (y))
+
+#define ADDSI(x, y) ((x) + (y))
+#define SUBSI(x, y) ((x) - (y))
+#define MULSI(x, y) ((x) * (y))
+#define DIVSI(x, y) ((SI) (x) / (SI) (y))
+#define UDIVSI(x, y) ((USI) (x) / (USI) (y))
+#define MODSI(x, y) ((SI) (x) % (SI) (y))
+#define UMODSI(x, y) ((USI) (x) % (USI) (y))
+#define SRASI(x, y) ((SI) (x) >> (y))
+#define SRLSI(x, y) ((USI) (x) >> (y))
+#define SLLSI(x, y) ((USI) (x) << (y))
+extern SI RORSI (SI, int);
+extern SI ROLSI (SI, int);
+#define ANDSI(x, y) ((x) & (y))
+#define ORSI(x, y) ((x) | (y))
+#define XORSI(x, y) ((x) ^ (y))
+#define NEGSI(x) (- (x))
+#define NOTSI(x) (! (SI) (x))
+#define INVSI(x) (~ (x))
+#define ABSSI(x) ((x) < 0 ? -(x) : (x))
+#define EQSI(x, y) ((SI) (x) == (SI) (y))
+#define NESI(x, y) ((SI) (x) != (SI) (y))
+#define LTSI(x, y) ((SI) (x) < (SI) (y))
+#define LESI(x, y) ((SI) (x) <= (SI) (y))
+#define GTSI(x, y) ((SI) (x) > (SI) (y))
+#define GESI(x, y) ((SI) (x) >= (SI) (y))
+#define LTUSI(x, y) ((USI) (x) < (USI) (y))
+#define LEUSI(x, y) ((USI) (x) <= (USI) (y))
+#define GTUSI(x, y) ((USI) (x) > (USI) (y))
+#define GEUSI(x, y) ((USI) (x) >= (USI) (y))
+
+#ifdef DI_FN_SUPPORT
+extern DI ADDDI (DI, DI);
+extern DI SUBDI (DI, DI);
+extern DI MULDI (DI, DI);
+extern DI DIVDI (DI, DI);
+extern DI UDIVDI (DI, DI);
+extern DI MODDI (DI, DI);
+extern DI UMODDI (DI, DI);
+extern DI SRADI (DI, int);
+extern UDI SRLDI (UDI, int);
+extern UDI SLLDI (UDI, int);
+extern DI RORDI (DI, int);
+extern DI ROLDI (DI, int);
+extern DI ANDDI (DI, DI);
+extern DI ORDI (DI, DI);
+extern DI XORDI (DI, DI);
+extern DI NEGDI (DI);
+extern int NOTDI (DI);
+extern DI INVDI (DI);
+extern int EQDI (DI, DI);
+extern int NEDI (DI, DI);
+extern int LTDI (DI, DI);
+extern int LEDI (DI, DI);
+extern int GTDI (DI, DI);
+extern int GEDI (DI, DI);
+extern int LTUDI (UDI, UDI);
+extern int LEUDI (UDI, UDI);
+extern int GTUDI (UDI, UDI);
+extern int GEUDI (UDI, UDI);
+#else /* ! DI_FN_SUPPORT */
+#define ADDDI(x, y) ((x) + (y))
+#define SUBDI(x, y) ((x) - (y))
+#define MULDI(x, y) ((x) * (y))
+#define DIVDI(x, y) ((DI) (x) / (DI) (y))
+#define UDIVDI(x, y) ((UDI) (x) / (UDI) (y))
+#define MODDI(x, y) ((DI) (x) % (DI) (y))
+#define UMODDI(x, y) ((UDI) (x) % (UDI) (y))
+#define SRADI(x, y) ((DI) (x) >> (y))
+#define SRLDI(x, y) ((UDI) (x) >> (y))
+#define SLLDI(x, y) ((UDI) (x) << (y))
+extern DI RORDI (DI, int);
+extern DI ROLDI (DI, int);
+#define ANDDI(x, y) ((x) & (y))
+#define ORDI(x, y) ((x) | (y))
+#define XORDI(x, y) ((x) ^ (y))
+#define NEGDI(x) (- (x))
+#define NOTDI(x) (! (DI) (x))
+#define INVDI(x) (~ (x))
+#define ABSDI(x) ((x) < 0 ? -(x) : (x))
+#define EQDI(x, y) ((DI) (x) == (DI) (y))
+#define NEDI(x, y) ((DI) (x) != (DI) (y))
+#define LTDI(x, y) ((DI) (x) < (DI) (y))
+#define LEDI(x, y) ((DI) (x) <= (DI) (y))
+#define GTDI(x, y) ((DI) (x) > (DI) (y))
+#define GEDI(x, y) ((DI) (x) >= (DI) (y))
+#define LTUDI(x, y) ((UDI) (x) < (UDI) (y))
+#define LEUDI(x, y) ((UDI) (x) <= (UDI) (y))
+#define GTUDI(x, y) ((UDI) (x) > (UDI) (y))
+#define GEUDI(x, y) ((UDI) (x) >= (UDI) (y))
+#endif /* DI_FN_SUPPORT */
+
+#define EXTBIQI(x) ((QI) (BI) (x))
+#define EXTBIHI(x) ((HI) (BI) (x))
+#define EXTBISI(x) ((SI) (BI) (x))
+#if defined (DI_FN_SUPPORT)
+extern DI EXTBIDI (BI);
+#else
+#define EXTBIDI(x) ((DI) (BI) (x))
+#endif
+#define EXTQIHI(x) ((HI) (QI) (x))
+#define EXTQISI(x) ((SI) (QI) (x))
+#if defined (DI_FN_SUPPORT)
+extern DI EXTQIDI (QI);
+#else
+#define EXTQIDI(x) ((DI) (QI) (x))
+#endif
+#define EXTHIHI(x) ((HI) (HI) (x))
+#define EXTHISI(x) ((SI) (HI) (x))
+#define EXTSISI(x) ((SI) (SI) (x))
+#if defined (DI_FN_SUPPORT)
+extern DI EXTHIDI (HI);
+#else
+#define EXTHIDI(x) ((DI) (HI) (x))
+#endif
+#if defined (DI_FN_SUPPORT)
+extern DI EXTSIDI (SI);
+#else
+#define EXTSIDI(x) ((DI) (SI) (x))
+#endif
+
+#define ZEXTBIQI(x) ((QI) (BI) (x))
+#define ZEXTBIHI(x) ((HI) (BI) (x))
+#define ZEXTBISI(x) ((SI) (BI) (x))
+#if defined (DI_FN_SUPPORT)
+extern DI ZEXTBIDI (BI);
+#else
+#define ZEXTBIDI(x) ((DI) (BI) (x))
+#endif
+#define ZEXTQIHI(x) ((HI) (UQI) (x))
+#define ZEXTQISI(x) ((SI) (UQI) (x))
+#if defined (DI_FN_SUPPORT)
+extern DI ZEXTQIDI (QI);
+#else
+#define ZEXTQIDI(x) ((DI) (UQI) (x))
+#endif
+#define ZEXTHISI(x) ((SI) (UHI) (x))
+#define ZEXTHIHI(x) ((HI) (UHI) (x))
+#define ZEXTSISI(x) ((SI) (USI) (x))
+#if defined (DI_FN_SUPPORT)
+extern DI ZEXTHIDI (HI);
+#else
+#define ZEXTHIDI(x) ((DI) (UHI) (x))
+#endif
+#if defined (DI_FN_SUPPORT)
+extern DI ZEXTSIDI (SI);
+#else
+#define ZEXTSIDI(x) ((DI) (USI) (x))
+#endif
+
+#define TRUNCQIBI(x) ((BI) (QI) (x))
+#define TRUNCHIBI(x) ((BI) (HI) (x))
+#define TRUNCHIQI(x) ((QI) (HI) (x))
+#define TRUNCSIBI(x) ((BI) (SI) (x))
+#define TRUNCSIQI(x) ((QI) (SI) (x))
+#define TRUNCSIHI(x) ((HI) (SI) (x))
+#define TRUNCSISI(x) ((SI) (SI) (x))
+#if defined (DI_FN_SUPPORT)
+extern BI TRUNCDIBI (DI);
+#else
+#define TRUNCDIBI(x) ((BI) (DI) (x))
+#endif
+#if defined (DI_FN_SUPPORT)
+extern QI TRUNCDIQI (DI);
+#else
+#define TRUNCDIQI(x) ((QI) (DI) (x))
+#endif
+#if defined (DI_FN_SUPPORT)
+extern HI TRUNCDIHI (DI);
+#else
+#define TRUNCDIHI(x) ((HI) (DI) (x))
+#endif
+#if defined (DI_FN_SUPPORT)
+extern SI TRUNCDISI (DI);
+#else
+#define TRUNCDISI(x) ((SI) (DI) (x))
+#endif
+
+/* Composing/decomposing the various types.
+   Word ordering is endian-independent.  Words are specified most to least
+   significant and word number 0 is the most significant word.
+   ??? May also wish an endian-dependent version.  Later.  */
+
+static QI SUBWORDSIQI (SI, int);
+static HI SUBWORDSIHI (SI, int);
+static QI SUBWORDDIQI (DI, int);
+static HI SUBWORDDIHI (DI, int);
+static SI SUBWORDDISI (DI, int);
+
+#ifdef SEMOPS_DEFINE_INLINE
+
+SEMOPS_INLINE QI
+SUBWORDSIQI (SI in, int byte)
+{
+  assert (byte >= 0 && byte <= 3);
+  return (UQI) (in >> (8 * (3 - byte))) & 0xFF;
+}
+
+SEMOPS_INLINE HI
+SUBWORDSIHI (SI in, int word)
+{
+  if (word == 0)
+    return (USI) in >> 16;
+  else
+    return in;
+}
+
+SEMOPS_INLINE QI
+SUBWORDDIQI (DI in, int byte)
+{
+  assert (byte >= 0 && byte <= 7);
+  return (UQI) (in >> (8 * (7 - byte))) & 0xFF;
+}
+
+SEMOPS_INLINE HI
+SUBWORDDIHI (DI in, int word)
+{
+  assert (word >= 0 && word <= 3);
+  return (UHI) (in >> (16 * (3 - word))) & 0xFFFF;
+}
+
+SEMOPS_INLINE SI
+SUBWORDDISI (DI in, int word)
+{
+  if (word == 0)
+    return (UDI) in >> 32;
+  else
+    return in;
+}
+
+#endif /* SUBWORD,JOIN */
+
+#endif /* CGEN_BASIC_OPS_H */
diff --git a/binutils-2.25/include/cgen/bitset.h b/binutils-2.25/include/cgen/bitset.h
new file mode 100644
index 00000000..7a6a9930
--- /dev/null
+++ b/binutils-2.25/include/cgen/bitset.h
@@ -0,0 +1,56 @@
+/* Header file the type CGEN_BITSET.
+   Copyright 2002, 2005, 2009 Free Software Foundation, Inc.
+
+   This file is part of the GNU opcodes library.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this library; see the file COPYING3.  If not, write to the
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#ifndef CGEN_BITSET_H
+#define CGEN_BITSET_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* A bitmask represented as a string.
+   Each member of the set is represented as a bit
+   in the string. Bytes are indexed from left to right in the string and
+   bits from most significant to least within each byte.
+
+   For example, the bit representing member number 6 is (set->bits[0] & 0x02).
+*/
+typedef struct cgen_bitset
+{
+  unsigned length;
+  char *bits;
+} CGEN_BITSET;
+
+extern CGEN_BITSET *cgen_bitset_create PARAMS ((unsigned));
+extern void cgen_bitset_init PARAMS ((CGEN_BITSET *, unsigned));
+extern void cgen_bitset_clear PARAMS ((CGEN_BITSET *));
+extern void cgen_bitset_add PARAMS ((CGEN_BITSET *, unsigned));
+extern void cgen_bitset_set PARAMS ((CGEN_BITSET *, unsigned));
+extern int cgen_bitset_compare PARAMS ((CGEN_BITSET *, CGEN_BITSET *));
+extern void cgen_bitset_union PARAMS ((CGEN_BITSET *, CGEN_BITSET *, CGEN_BITSET *));
+extern int cgen_bitset_intersect_p PARAMS ((CGEN_BITSET *, CGEN_BITSET *));
+extern int cgen_bitset_contains PARAMS ((CGEN_BITSET *, unsigned));
+extern CGEN_BITSET *cgen_bitset_copy PARAMS ((CGEN_BITSET *));
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif
diff --git a/binutils-2.25/include/coff/ChangeLog b/binutils-2.25/include/coff/ChangeLog
new file mode 100644
index 00000000..2a9c0aba
--- /dev/null
+++ b/binutils-2.25/include/coff/ChangeLog
@@ -0,0 +1,373 @@
+2013-07-10  Tristan Gingold  <gingold@adacore.com>
+
+	* rs6000.h (external_core_dumpx): New structure.
+	(external_ld_info32): Ditto.
+
+2013-07-02  Tristan Gingold  <gingold@adacore.com>
+
+	* internal.h (C_STTLS, C_GTLS): Define.
+	* xcoff.h (XMC_TL, XMC_TU, XMC_TE): Define.
+
+2013-02-04  Alan Modra  <amodra@gmail.com>
+
+	* ti.h (SWAP_OUT_RELOC_EXTRA): Define.
+
+2013-01-02  Martin Storsjo <martin@martin.st>
+
+	* arm.h (ARMV7PEMAGIC): Define.
+	(ARMBADMAG): Update.
+
+2011-06-02  Nick Clifton  <nickc@redhat.com>
+
+	* i860.h: Fix spelling mistake in comment.
+
+2011-05-04  Tristan Gingold  <gingold@adacore.com>
+
+	* rs6000.h (union external_auxent): Add x_ftype field.
+	* rs6k64.h: (struct external_auxent): Remap x_file field.
+
+2011-05-04  Tristan Gingold  <gingold@adacore.com>
+
+	* rs6000.h (struct external_exceptab): New struct.
+	(EXCEPTSZ): New macro.
+	* rs6k64.h: (struct external_exceptab): New struct.
+	(EXCEPTSZ): New macro.
+
+2011-05-03  Tristan Gingold  <gingold@adacore.com>
+
+	* rs6000.h (struct external_ldsym): Use E_SYMNMLEN instead of
+	SYMNMLEN.
+
+2011-04-27  Tristan Gingold  <gingold@adacore.com>
+
+	* xcoff.h (F_FDPR_PROF, F_FDPR_OPTI, F_DSA, F_VARPG)
+	(STYP_DWARF, SSUBTYP_DWINFO)
+	(SSUBTYP_DWLINE, SSUBTYP_DWPBNMS, SSUBTYP_DWPBTYP)
+	(SSUBTYP_DWARNGE, SSUBTYP_DWABREV, SSUBTYP_DWSTR)
+	(SSUBTYP_DWRNGES, STYP_TDATA, STYP_TBSS, R_TLS, R_TLS_IE)
+	(R_TLS_LD, R_TLS_LE, R_TLSM, R_TLSML, R_TOCU, R_TOCL, C_DWARF):
+	New macros.
+
+2011-03-31  Tristan Gingold  <gingold@adacore.com>
+
+	* internal.h (C_NULL_VALUE): Define.
+
+2010-06-29  Alan Modra  <amodra@gmail.com>
+
+	* maxq.h: Delete file.
+
+2010-04-15  Nick Clifton  <nickc@redhat.com>
+
+	* alpha.h: Update copyright notice to use GPLv3.
+	* apollo.h: Likewise.
+	* arm.h: Likewise.
+	* aux-coff.h: Likewise.
+	* ecoff.h: Likewise.
+	* external.h: Likewise.
+	* go32exe.h: Likewise.
+	* h8300.h: Likewise.
+	* h8500.h: Likewise.
+	* i386.h: Likewise.
+	* i860.h: Likewise.
+	* i960.h: Likewise.
+	* ia64.h: Likewise.
+	* internal.h: Likewise.
+	* m68k.h: Likewise.
+	* m88k.h: Likewise.
+	* maxq.h: Likewise.
+	* mcore.h: Likewise.
+	* mips.h: Likewise.
+	* mipspe.h: Likewise.
+	* or32.h: Likewise.
+	* pe.h: Likewise.
+	* powerpc.h: Likewise.
+	* rs6000.h: Likewise.
+	* rs6k64.h: Likewise.
+	* sh.h: Likewise.
+	* sparc.h: Likewise.
+	* ti.h: Likewise.
+	* tic30.h: Likewise.
+	* tic4x.h: Likewise.
+	* tic54x.h: Likewise.
+	* tic80.h: Likewise.
+	* w65.h: Likewise.
+	* we32k.h: Likewise.
+	* x86_64.h: Likewise.
+	* xcoff.h: Likewise.
+	* z80.h: Likewise.
+	* z8k.h: Likewise.
+
+2009-12-02  Jerker Bäck  <jerker.back@gmail.com>
+
+	PR binutils/11017
+	* i386lh (COFF_PAGE_SIZE): Define.
+	* x86_64.h (COFF_PAGE_SIZE): Define.
+
+2009-10-17  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* z80.h: Store alignment requirement in section header, to allow
+	ld to preserve alignment. Some code was copied from ti.h.
+
+2009-09-05  Martin Thuresson  <martin@mtme.org>
+
+	* ti.h (GET_LNSZ_SIZE, PUT_LNSZ_SIZE): Updated name of class
+	variable to in_class to match changes in function that use this
+	macro.
+
+2009-08-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
+
+	Fix references past allocated memory for i386-*-go32.
+	* ti.h (COFF_ADJUST_FILEHDR_IN_POST, COFF_ADJUST_FILEHDR_OUT_POST):
+	Reference F_TARGET_ID only when !COFF0_P.
+
+2009-08-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
+
+	Stop using bfd_usrdata in libbfd.
+	* go32exe.h (struct external_filehdr_go32_exe <stub>, FILHSZ): Replace
+	STUBSIZE by GO32_STUBSIZE.
+	(STUBSIZE): Move the definition ...
+	* internal.h (GO32_STUBSIZE): ... here and rename it.
+	(struct internal_filehdr <go32stub>, F_GO32STUB): New.
+
+2009-06-03  Ulrich Weigand  <uweigand@de.ibm.com>
+
+	* symconst.h (btLong64, btULong64, btLongLong64, btULongLong64,
+	btAdr64, btInt64, btUInt64): New defines.
+
+2009-04-21  Kai Tietz  <kai.tietz@onevision.com>
+
+	* pe.h (pex64_runtime_function): New structure.
+	(external_pex64_runtime_function): Likewise.
+	(pex64_unwind_code): Likewise.
+	(external_pex64_unwind_code): Likewise.
+	(pex64_unwind_info): Likewise.
+	(external_pex64_unwind_info): Likewise.
+	(external_pex64_scope): Likewise.
+	(pex64_scope): Likewise.
+	(pex64_scope_entry):  Likewise.
+	(external_pex64_scope_entry): Likewise.
+	(PEX64_IS_RUNTIME_FUNCTION_CHAINED): New macro.
+	(PEX64_GET_UNWINDDATA_UNIFIED_RVA): Likewise.
+	(PEX64_UNWCODE_CODE): Likewise.
+	(PEX64_UNWCODE_INFO): Likewise.
+	(UWOP_...): Add defines for unwind code.
+	(UNW_FLAG_...): Add defined for unwind info flags.
+	(PEX64_SCOPE_ENTRY_SIZE): New macro.
+	(PEX64_UWI_VERSION): Likewise.
+	(PEX64_UWI_FLAGS): Likewise.
+	(PEX64_UWI_FRAMEREG): Likewise.
+	(PEX64_UWI_FRAMEOFF): Likewise.
+	(PEX64_UWI_SIZEOF_UWCODE_ARRAY): Likewise.
+	(PEX64_OFFSET_TO_UNWIND_CODE): Likewise.
+	(PEX64_OFFSET_TO_HANDLER_RVA): Likewise.
+	(PEX64_OFFSET_TO_SCOPE_COUNT): Likewise.
+	(PEX64_SCOPE_ENTRY): Likewise.
+
+2009-04-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* pe.h (IMAGE_SUBSYSTEM_EFI_ROM): Renamed to ...
+	(IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER): This.
+
+2009-04-01  Richard Sandiford  <r.sandiford@uk.ibm.com>
+
+	* xcoff.h (xcoff_link_hash_table): Move to bfd/xcofflink.c.
+
+2009-03-14  Richard Sandiford  <r.sandiford@uk.ibm.com>
+
+	* xcoff.h (XCOFF_EXPALL, XCOFF_EXPFULL): New flags.
+	(xcoff_loader_info): Add auto_export_flags.
+
+2009-03-14  Richard Sandiford  <r.sandiford@uk.ibm.com>
+
+	* internal.h (C_AIX_WEAKEXT): New macro.
+	(C_WEAKEXT): Use the GNU definition in the generic part of the file,
+	and conditionally reset it to C_AIX_WEAKEXT in the XCOFF part of
+	the file.
+	(CSECT_SYM_P): New macro.
+	* xcoff.h (L_WEAK): Define.
+	(EXTERN_SYM_P): New macro.
+
+2009-03-14  Richard Sandiford  <r.sandiford@uk.ibm.com>
+
+	* xcoff.h (XCOFF_ALLOCATED): New flag.
+
+2009-03-14  Richard Sandiford  <r.sandiford@uk.ibm.com>
+
+	* xcoff.h (XCOFF_CALLED, XCOFF_IMPORT): Update comments.
+	(XCOFF_WAS_UNDEFINED): New flag.
+	(xcoff_link_hash_table): Add an "rtld" field.
+
+2009-03-14  Dave Korn  <dave.korn.cygwin@gmail.com>
+
+	* internal.h (struct internal_extra_pe_aouthdr):  Correct type
+	of DllCharacteristics flags field to unsigned.
+	* pe.h (IMAGE_DLL_CHARACTERISTICS_DYNAMIC_BASE,
+	IMAGE_DLL_CHARACTERISTICS_DYNAMIC_BASE,
+	IMAGE_DLL_CHARACTERISTICS_NX_COMPAT,
+	IMAGE_DLLCHARACTERISTICS_NO_ISOLATION,
+	IMAGE_DLLCHARACTERISTICS_NO_SEH,
+	IMAGE_DLLCHARACTERISTICS_NO_BIND,
+	IMAGE_DLLCHARACTERISTICS_WDM_DRIVER,
+	IMAGE_DLLCHARACTERISTICS_TERMINAL_SERVER_AWARE):  New macros to
+	define flag bit values for DllCharacteristics field of PEAOUTHDR,
+	PEPAOUTHDR.
+
+2008-12-23  Johan Olmutz Nielsen  <jnielsen@ddci.com>
+
+	* ti.h (COFF_ADJUST_SCNHDR_OUT_PRE): Define.
+
+2008-06-17  Nick Clifton  <nickc@redhat.com>
+
+	* ti.h (GET_SCNHDR_NLNNO): Provide an alternative version of this
+	macro which does not trigger an array bounds warning in gcc.
+	(PUT_SCNHDR_NLNNO): Likewise.
+	(GET_SCNHDR_FLAGS): Likewise.
+	(PUT_SCNHDR_FLAGS): Likewise.
+	(GET_SCNHDR_PAGE): Likewise.
+	(PUT_SCNHDR_PAGE): Likewise.
+
+2007-11-05  Danny Smith  <dannysmith@users.sourceforge.net>
+
+	* pe.h (COFF_ENCODE_ALIGNMENT) Define.
+
+2007-08-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* pe.h (IMAGE_SCN_ALIGN_POWER_BIT_POS): New.
+	(IMAGE_SCN_ALIGN_POWER_BIT_MASK): Likewise.
+	(IMAGE_SCN_ALIGN_POWER_NUM): Likewise.
+	(IMAGE_SCN_ALIGN_POWER_CONST): Likewise.
+	(IMAGE_SCN_ALIGN_128BYTES): Likewise.
+	(IMAGE_SCN_ALIGN_256BYTES): Likewise.
+	(IMAGE_SCN_ALIGN_512BYTES): Likewise.
+	(IMAGE_SCN_ALIGN_1024BYTES): Likewise.
+	(IMAGE_SCN_ALIGN_2048BYTES): Likewise.
+	(IMAGE_SCN_ALIGN_4096BYTES): Likewise.
+	(IMAGE_SCN_ALIGN_8192BYTES): Likewise.
+	(IMAGE_SCN_ALIGN_1BYTES): Redefined with
+	IMAGE_SCN_ALIGN_POWER_CONST.
+	(IMAGE_SCN_ALIGN_2BYTES): Likewise.
+	(IMAGE_SCN_ALIGN_4BYTES): Likewise.
+	(IMAGE_SCN_ALIGN_8BYTES): Likewise.
+	(IMAGE_SCN_ALIGN_16BYTES): Likewise.
+	(IMAGE_SCN_ALIGN_32BYTES): Likewise.
+	(IMAGE_SCN_ALIGN_64BYTES): Likewise.
+
+2007-07-12  Kai Tietz   <kai.tietz@onevision.com>
+
+	* internal.h (struct internal_syment): Use bfd_hostptr_t for
+	_n_zeroes and _n_offset fields.
+
+2007-04-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* rs6000.h: Write Mimi's name in ASCII.
+
+2007-03-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* internal.h (internal_extra_pe_aouthdr): Add Magic,
+	MajorLinkerVersion, MinorLinkerVersion, SizeOfCode,
+	SizeOfInitializedData, SizeOfUninitializedData,
+	AddressOfEntryPoint, BaseOfCode and BaseOfData.
+
+2006-12-05  Michael Tautschnig  <tautschn@model.in.tum.de>
+	    Nick Clifton  <nickc@redhat.com>
+
+	* external.h (struct external_aouthdr): Add ATTRIBUTE_PACKED.
+	(struct external_syment): Likewise.
+	(union external_auxent): Likewise.
+
+2006-11-14  Phil Lello  <phil.lello@homecall.co.uk>
+
+	* pe.h: Added defines for IMAGE_SUBSYSTEM_EFI_ROM and
+	IMAGE_SUBSYSTEM_XBOX.
+	* internal.h: Added defines for PE directory entry types.
+	NB: in internal.h because IMAGE_NUMBEROF_DIRECTORY_ENTRYIES is in
+	pe.h
+
+2006-09-20  Kai Tietz  <Kai.Tietz@onevision.com>
+
+	* external.h: Add proper external_aouthdr64 structure (without
+	data_start member).
+	(AOUTHDRSZ64): Set according structure size.
+	(AOUTHDR64): As typedef of external_aouthdr64 structure.
+	* internal.h: Add relocation identifiers for coff.
+	* pe.h:	Add define IMAGE_FILE_MACHINE_AMD64 the coff signature.
+	(PEPAOUTHDR): Adjust structure to have proper size (using AOUTHDR64).
+	(PEPAOUTSZ): Calculated size of 240.
+	* x86_64.h: Coff information for x86_64 (AMD64).
+
+2006-02-05  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* internal.h: Add relocation number R_IMM24 for Z80.
+
+2005-10-25  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* internal.h: Add relocation number for Z80
+	* z80.h: New file.
+
+2005-08-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* a29k.h: Delete.
+
+2005-07-14  Daniel Marques  <marques@cs.cornell.edu>
+
+	* alpha.h (ALPHA_ECOFF_COMPRESSEDMAG): Define.
+	* ecoff.h (ALPHA_MAGIC_COMPRESSED): Define.
+
+2005-05-10  Nick Clifton  <nickc@redhat.com>
+
+	* Update the address and phone number of the FSF organization in
+	the GPL notices in the following files:
+	a29k.h,	alpha.h, apollo.h, arm.h, aux-coff.h, ecoff.h, external.h,
+	go32exe.h, h8300.h, h8500.h, i386.h, i860.h, i960.h, ia64.h,
+	internal.h, m68k.h, m88k.h, maxq.h, mcore.h, mips.h, mipspe.h,
+	or32.h, pe.h, powerpc.h, rs6k64.h, sh.h, sparc.h, ti.h, tic30.h,
+	tic4x.h, tic54x.h, tic80.h, w65.h, we32k.h, xcoff.h, z8k.h
+
+2005-02-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* xcoff.h (struct xcoff_loader_info): Warning fix.
+
+2005-01-10  Inderpreet Singh <inderpreetb@noida.hcltech.com>
+
+	* maxq.h (F_MAXQ10, F_MAXQ20): Define.
+
+2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
+	    Vineet Sharma      <vineets@noida.hcltech.com>
+
+	* maxq.h: New file: Defintions for the maxq port.
+
+2004-11-08  Aaron W. LaFramboise <aaron98wiridge9@aaronwl.com>
+
+	* pe.h (IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY): Define.
+	(IMAGE_WEAK_EXTERN_SEARCH_LIBRARY): Same.
+	(IMAGE_WEAK_EXTERN_SEARCH_ALIAS): Same.
+
+2004-08-13  Mark Kettenis  <kettenis@gnu.org>
+
+	* symconst.h (langMax): Fix typo in comment.
+
+2004-04-23  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h (MIPS_R_RELHI, MIPS_R_RELLO, MIPS_R_SWITCH): Remove
+	(MIPS_R_PCREL16): Update comment.
+	* ecoff.h (struct ecoff_value_adjust): Remove structure.
+	(struct ecoff_debug_info): Remove 'adjust' member.
+
+2004-04-20  DJ Delorie  <dj@redhat.com>
+
+	* internal.h (R_SECREL32): Add.
+
+For older changes see ChangeLog-9103
+
+Copyright (C) 2004-2012 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.25/include/coff/ChangeLog-9103 b/binutils-2.25/include/coff/ChangeLog-9103
new file mode 100644
index 00000000..c8a7b100
--- /dev/null
+++ b/binutils-2.25/include/coff/ChangeLog-9103
@@ -0,0 +1,1186 @@
+2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	Moved from ../ChangeLog
+
+	2003-04-04  Svein E. Seldal  <Svein.Seldal@solidas.com>
+	* tic4x.h: Namespace cleanup. Replace s/c4x/tic4x
+	and s/c3x/tic3x/
+
+	2003-01-20  Svein E. Seldal  <Svein.Seldal@solidas.com>
+	* tic4x.h (TICOFF_TARGET_MACHINE_GET): Fixed define bug
+	* ti.h (TICOFF_TARGET_MACHINE_GET): Added macros
+
+	2002-08-28  Michael Hayes <m.hayes@elec.canterbury.ac.nz>
+	* internal.h: Add new relocation types.
+	* ti.h: Add file-header flags for tic4x code.
+	* tic4x.h: New file
+
+2003-12-02  Graham Reed <grahamr@algorithmics.com>
+
+	* internal.h (C_WEAKEXT): Add alternative value for AIX 5.2
+	based targets.
+
+2003-08-23  Jason Eckhardt  <jle@rice.edu>
+
+	* coff/i860.h (COFF860_R_PAIR, COFF860_R_LOW0, COFF860_R_LOW1,
+	COFF860_R_LOW2, COFF860_R_LOW3, COFF860_R_LOW4, COFF860_R_SPLIT0,
+	COFF860_R_SPLIT1, COFF860_R_SPLIT2, COFF860_R_HIGHADJ,
+	COFF860_R_BRADDR): Define new relocation constants and document.
+	Minor formatting adjustments.
+
+2003-08-07  Alan Modra  <amodra@bigpond.net.au>
+
+	* ti.h (GET_SCNHDR_NRELOC): Rename PTR param to LOC.
+	(PUT_SCNHDR_NRELOC, GET_SCNHDR_NLNNO, PUT_SCNHDR_NLNNO): Likewise.
+	(GET_SCNHDR_FLAGS, PUT_SCNHDR_FLAGS): Likewise.
+	(GET_SCNHDR_PAGE, PUT_SCNHDR_PAGE): Likewise.
+
+2003-07-17  Jeff Muizelaar  <muizelaar@rogers.com>
+
+	* pe.h: (IMAGE_FILE_NET_RUN_FROM_SWAP): Define.
+	(IMAGE_FILE_MACHINE_WCEMIPSV2): Define.
+	(IMAGE_FILE_MACHINE_SH3DSP): Define.
+	(IMAGE_FILE_MACHINE_SH3E): Define.
+	(IMAGE_FILE_MACHINE_SH5): Define.
+	(IMAGE_FILE_MACHINE_AM33): Define.
+	(IMAGE_FILE_MACHINE_POWERPCFP): Define.
+	(IMAGE_FILE_MACHINE_AXP64): Define.
+	(IMAGE_FILE_MACHINE_TRICORE): Define.
+	(IMAGE_FILE_MACHINE_CEF): Define.
+	(IMAGE_FILE_MACHINE_EBC): Define.
+	(IMAGE_FILE_MACHINE_AMD64): Define.
+	(IMAGE_FILE_MACHINE_M32R): Define.
+	(IMAGE_FILE_MACHINE_CEE): Define.
+
+2003-07-14  Christian Groessler  <chris@groessler.org>
+
+        * i860.h (AOUTSZ): Define for i860 coff.
+
+2003-06-29  Andreas Jaeger  <aj@suse.de>
+
+	* xcoff.h (struct __rtinit ): Convert to ISO C90 prototypes.
+
+	* ecoff.h: Convert to ISO C90 prototypes.  Replace PTR by void *.
+
+2003-04-24 Dhananjay Deshpande <dhananjayd@kpitcummins.com>
+
+	* coff/h8300.h (H8300HNMAGIC, H8300SNMAGIC): New.
+	(H8300HNBADMAG, H8300SNBADMAG): New.
+
+2003-04-15  Rohit Kumar Srivastava <rohits@kpitcummins.com>
+
+	* sh.h: Replace occurrances of 'Hitachi' with 'Renesas'.
+	* h8300.h: Likewise.
+	* h8500.h: Likewise.
+
+2003-03-25  Stan Cox   <scox@redhat.com>
+	    Nick Clifton  <nickc@redhat.com>
+
+	Contribute support for Intel's iWMMXt chip - an	ARM variant:
+
+	* arm.h (ARM_NOTE_SECTION): Define.
+
+2002-11-30  Alan Modra  <amodra@bigpond.net.au>
+
+	* ecoff.h: Replace boolean with bfd_boolean.
+	* xcoff.h: Likewise.
+
+2002-03-18  Tom Rix  <trix@redhat.com>
+
+	* rs6k64.h: Add U64_TOCMAGIC, AIX 5 64 bit magic number.
+
+2002-02-01  Tom Rix  <trix@redhat.com>
+
+	* xcoff.h: Conditionally support <aiaff> for pre AIX 4.3.
+
+2002-01-31  Ivan Guzvinec  <ivang@opencores.org>
+
+	* or32.h: New file.
+
+2001-12-24  Tom Rix  <trix@redhat.com>
+
+	* xcoff.h (xcoff_big_format_p): Make <bigaf> the default archive
+	format.
+	(XCOFFARMAG_ELEMENT_SIZE, XCOFFARMAGBIG_ELEMENT_SIZE): Define for
+	archive header ascii elements.
+
+2001-12-17  Tom Rix  <trix@redhat.com>
+
+	* xcoff.h :  Add .except and .typchk section string and styp flags.
+	Fix xcoff_big_format_p macro.
+
+2001-12-16  Tom Rix  <trix@redhat.com>
+
+	* xcoff.h : Clean up formatting.
+
+2002-01-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.h (F_VFP_FLOAT): Define.
+
+2001-11-11  Timothy Wall  <twall@alum.mit.edu>
+
+	* ti.h: Move arch-specific stuff from here...
+	(COFF_ADJUST_SYM_IN/OUT): Optionally put page flag into symbol
+	value.
+	* tic54x.h: ...to here.
+
+2001-10-26  Christian Groessler  <cpg@aladdin.de>
+
+	* external.h (GET_LINENO_LNNO): Fix usage of H_GET_32/16.
+	(PUT_LINENO_LNNO): Likewise with H_PUT_32/16.
+
+2001-09-21  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* ti.h (GET_SCNHDR_PAGE): Fix compile time warning.
+
+2001-09-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* external.h (GET_LINENO_LNNO): Use H_GET_32/16.
+	(PUT_LINENO_LNNO): Use H_PUT_32/16.
+	* m88k.h (GET_LNSZ_SIZE, GET_LNSZ_LNNO, GET_SCN_NRELOC,
+	GET_SCN_NLINNO): Use H_GET_32.
+	(PUT_LNSZ_LNNO, PUT_LNSZ_SIZE, PUT_SCN_NRELOC, PUT_SCN_NLINNO):
+	Use H_PUT_32.
+	* ti.h: Formatting fixes.  Make use of H_GET_* and H_PUT_* throughout.
+	* xcoff.h: White space changes.
+
+2001-09-05  Tom Rix <trix@redhat.com>
+
+	* xcoff.h : Add XCOFF_SYSCALL32 and XCOFF_SYSCALL64 hash table flags.
+
+2001-08-27  Andreas Jaeger  <aj@suse.de>
+
+	* xcoff.h (struct __rtinit): Make proper prototype for rtl.
+
+Fri Aug 24 01:18:51 2001  J"orn Rennecke <amylaar@redhat.com>
+
+	* internal.h (R_JMP2, R_JMPL2, R_MOVL2): Comment spelling fix.
+
+2001-04-05  Tom Rix <trix@redhat.com>
+
+	* rs6000.h : move xcoff32 external structures from xcofflink.
+	* rs6k64.h : move xcoff64 external structures from xcofflink.
+	* internal.h : promote 32 bit structure elements to 64 bit
+	for xcoff64 support
+	* xcoff.h : New file.
+
+2001-03-23  Nick Clifton  <nickc@redhat.com>
+
+	* a29k.h: Fix compile time warning.
+	* external.h: Fix compile time warning.
+	* m88k.h: Fix compile time warning.
+
+2001-03-13  Nick Clifton  <nickc@redhat.com>
+
+	* external.h: New file. Common structure definitions found in
+	other COFF header files.
+
+	* a29k.h: Use external.h.
+	* apollo.h: Use external.h.
+	* arm.h: Use external.h.
+	* h8300.h: Use external.h.
+	* h8500.h: Use external.h.
+	* i386.h: Use external.h.
+	* i860.h: Use external.h.
+	* ia64.h: Use external.h.
+	* m68k.h: Use external.h.
+	* m88k.h: Use external.h.
+	* mcore.h: Use external.h.
+	* mips.h: Use external.h.
+	* mipspe.h: Use external.h.
+	* powerpc.h: Use external.h.
+	* rs6000.h: Use external.h.
+	* rs6k64.h: Use external.h.
+	* sh.h: Use external.h.
+	* sparc.h: Use external.h.
+	* tic30.h: Use external.h.
+	* tic80.h: Use external.h.
+	* w65.h: Use external.h.
+	* we32k.h: Use external.h.
+	* z8k.h: Use external.h.
+
+2001-02-09  David Mosberger  <davidm@hpl.hp.com>
+
+	* pe.h (PEPAOUTSZ): Rename from PEP64AOUTSZ.
+	Rename from PEPAOUTHDR.
+
+2001-01-23  H.J. Lu  <hjl@gnu.org>
+
+	* pe.h (struct external_PEI_DOS_hdr): New.
+	(struct external_PEI_IMAGE_hdr): New.
+
+2000-12-11  Alan Modra  <alan@linuxcare.com.au>
+
+	* ti.h (OCTETS_PER_BYTE_POWER): Change #warning to #error.
+
+2000-12-08  Alan Modra  <alan@linuxcare.com.au>
+
+	* ti.h (OCTETS_PER_BYTE_POWER): Change #warn to #warning.
+
+2000-06-30  DJ Delorie  <dj@cygnus.com>
+
+	* pe.h: Clarify a comment.
+
+2000-05-05  Clinton Popetz  <cpopetz@cygnus.com>
+
+	* rs6k64.h (U802TOC64MAGIC): Change to U803XTOCMAGIC.
+
+2000-04-24  Clinton Popetz  <cpopetz@cygnus.com>
+
+	* rs6k64.h: New file.
+
+2000-04-17  Timothy Wall  <twall@cygnus.com>
+
+	* ti.h: Load page cleanup.
+	* intental.h: Add load page field.
+
+Mon Apr 17 16:44:01 2000  David Mosberger  <davidm@hpl.hp.com>
+
+	* pe.h (PEP64AOUTHDR): New header for PE+.
+	(PEP64AOUTSZ): New macro.
+	(IMAGE_SUBSYSTEM_UNKNOWN): New macro.
+	(IMAGE_SUBSYSTEM_NATIVE): Ditto.
+	(IMAGE_SUBSYSTEM_WINDOWS_GUI): Ditto.
+	(IMAGE_SUBSYSTEM_WINDOWS_CUI): Ditto.
+	(IMAGE_SUBSYSTEM_POSIX_CUI): Ditto.
+	(IMAGE_SUBSYSTEM_WINDOWS_CE_GUI): Ditto.
+	(IMAGE_SUBSYSTEM_EFI_APPLICATION): Ditto.
+	(IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER): Ditto.
+	(IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER): Ditto.
+	* internal.h (PE_DEF_FILE_ALIGNMENT): Define only if not defined
+	already.
+	* ia64.h: New file.
+
+2000-04-13  Alan Modra  <alan@linuxcare.com.au>
+
+	* ti.h (ADDR_MASK): Don't use ul suffix on constants.
+	(PG_MASK): Ditto.
+
+2000-04-11  Timothy Wall  <twall@cygnus.com>
+
+	* ti.h: Remove load page references until load pages are
+	reimplemented.
+	* tic54x.h: Ditto.
+
+2000-04-07  Timothy Wall  <twall@cygnus.com>
+
+	* internal.h: Fix some comments related to TI COFF (instead of tic80).
+	* ti.h: New.
+	* tic54x.h: New.
+
+Wed Apr  5 22:08:41 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
+
+	* sh.h (R_SH_LOOP_START, R_SH_LOOP_END): Define.
+
+2000-03-15  Kazu Hirata  <kazu@hxi.com>
+
+	* internal.h: Fix a typo in the comment for R_MOVL2.
+
+2000-02-28  Nick Clifton  <nickc@cygnus.com>
+
+	* mipspe.h (MIPS_PE_MAGIC): Define.
+	* sh.h (SH_PE_MAGIC): Define.
+
+2000-02-22  Nick Clifton  <nickc@cygnus.com>  DJ Delorie <dj@cygnus.com>
+
+	* sh.h: Add Windows CE definitions.
+	* arm.h: Add Windows CE definitions.
+	* mipspe.h: New file: Windows CE definitions for MIPS.
+	* pe.h: Add constants for ILF support.
+
+2000-01-05  Nick Clifton  <nickc@cygnus.com>
+
+	* pe.h: Fix formatting of comments.
+	(IMAGE_FILE_AGGRESSIVE_WS_TRIM): Define.
+	(IMAGE_FILE_LARGE_ADDRESS_AWARE): Define.
+	(IMAGE_FILE_16BIT_MACHINE): Define.
+	(IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP): Define.
+	(IMAGE_FILE_UP_SYSTEM_ONLY): Define.
+	(IMAGE_FILE_MACHINE_UNKNOWN): Define.
+	(IMAGE_FILE_MACHINE_ALPHA): Define.
+	(IMAGE_FILE_MACHINE_ALPHA64): Define.
+	(IMAGE_FILE_MACHINE_I386): Define.
+	(IMAGE_FILE_MACHINE_IA64): Define.
+	(IMAGE_FILE_MACHINE_M68K): Define.
+	(IMAGE_FILE_MACHINE_MIPS16): Define.
+	(IMAGE_FILE_MACHINE_MIPSFPU): Define.
+	(IMAGE_FILE_MACHINE_MIPSFPU16): Define.
+	(IMAGE_FILE_MACHINE_POWERPC): Define.
+	(IMAGE_FILE_MACHINE_R3000): Define.
+	(IMAGE_FILE_MACHINE_R4000): Define.
+	(IMAGE_FILE_MACHINE_R10000): Define.
+	(IMAGE_FILE_MACHINE_SH3): Define.
+	(IMAGE_FILE_MACHINE_SH4): Define.
+	(IMAGE_FILE_MACHINE_THUMB): Define.
+
+1999-09-20  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* internal.h: Delete bogus R_PCLONG, duplicate R_RELBYTE and
+	R_RELWORD, and rewrite some R_* as decimal.
+
+1999-09-06  Donn Terry  <donn@interix.com>
+
+	* internal.h (DTYPE): Define.
+	* pe.h (struct external_PEI_filehdr): Rename from
+	external_PE_filehdr.  Define even if COFF_IMAGE_WITH_PE is not
+	defined.
+
+1999-07-17  Nick Clifton  <nickc@cygnus.com>
+
+	* arm.h (F_SOFT_FLOAT): Rename from F_SOFTFLOAT.
+
+1999-06-21  Philip Blundell  <pb@nexus.co.uk>
+
+	* arm.h (F_SOFTFLOAT): Define.
+
+1999-07-05  Nick Clifton  <nickc@cygnus.com>
+
+	* arm.h (F_ARM_5): Define.
+
+Wed Jun  2 18:08:18 1999  Richard Henderson  <rth@cygnus.com>
+
+	* internal.h (BEOS_EXE_IMAGE_BASE, BEOS_DLL_IMAGE_BASE): New.
+
+Mon May 17 13:35:35 1999  Stan Cox  <scox@cygnus.com>
+
+	* arm.h (F_PIC, F_ARM_2, F_ARM_2a, F_ARM_3, F_ARM_3M,
+	F_ARM_4, F_ARM_4T, F_APCS26): Changed values to distinguish
+	F_ARM_2a, F_ARM_3M, F_ARM_4T.
+
+1999-05-15  Nick Clifton  <nickc@cygnus.com>
+
+	* mcore.h (IMAGE_REL_MCORE_RVA): Define.
+
+1999-04-21  Nick Clifton  <nickc@cygnus.com>
+
+	* mcore.h (GET_LINENO_LNNO): New macro.
+	(PUT_LINENO_LNNO): New macro.
+
+1999-04-08  Nick Clifton  <nickc@cygnus.com>
+
+	* mcore.h: New header file.  Defines for Motorola's MCore
+	processor.
+
+Sun Dec  6 21:36:37 1998  Mark Elbrecht  <snowball3@usa.net>
+
+	* internal.h (C_WEAKEXT): Define.
+
+Wed Jan 27 13:35:35 1999  Stan Cox  <scox@cygnus.com>
+
+	* arm.h (F_PIC_INT, F_ARM_2, F_ARM_3, F_ARM_4, F_APCS26):
+	Changed values to avoid clashing with IMAGE_FILE_* coff header
+	flag values.
+
+Wed Apr  1 16:06:15 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* internal.h: Document numbers associated with Thumb symbol
+	types.
+
+Fri Mar 27 17:16:57 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* internal.h (ISPTR, ISFCN, ISARY): Add casts to unsigned long.
+
+Mon Feb  2 17:10:38 1998  Steve Haworth  <steve@pm.cse.rmit.EDU.AU>
+
+	* tic30.h: New file.
+
+Fri Dec 12 11:49:07 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (R_MPPCR15W): New relocation type, for 15 bit PC relative
+	offsets.
+
+Tue Dec  2 10:21:40 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* arm.h (COFFARM): New define.
+
+Mon Dec  1 20:24:18 1997  J"orn Rennecke <amylaar@cygnus.co.uk>
+
+	* sh.h (R_SH_SWITCH8): New.
+
+Sat Nov 22 15:10:14 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* internal.h (C_THUMBEXTFUNC, C_THUMBSTATFUNC): Constants to
+	define static and external functions.
+
+	* arm.h: Add bits to support PIC and APCS-FLOAT type binaries,
+	when implemented.
+
+Fri Oct  3 14:25:17 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (R_PPL16B): Make constant uppercase for consistency.
+
+Tue Jul 22 18:18:58 1997  Robert Hoehne <robert.hoehne@Mathematik.TU-Chemnitz.DE>
+
+	* go32exe.h: New file.
+
+Tue Jul  8 12:23:55 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_TARGET_ID): Add define.
+	* internal.h (struct internal_filehdr): Add f_target_id field.
+
+Tue Jun  3 16:44:18 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* internal.h: Add storage classes for Thumb symbols
+
+Mon May 26 14:07:55 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* tic80.h (R_PPL16B): Correct value.
+
+Tue May 13 10:21:14 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* arm.h (constants):   Added new flag bits F_APCS_26 and
+	F_APCS_SET for the f_flags field of the filehdr structure.  Added new
+	flags: F_APCS26, F_ARM_2, F_ARM_3, F_ARM_7, F_ARM_7T to store
+	information in the flags field of the internal_f structure used by BFD
+	routines.
+
+Sat May  3 08:24:59 1997  Fred Fish  <fnf@cygnus.com>
+
+	* internal.h (C_UEXT, C_STATLAB, C_EXTLAB, C_SYSTEM):
+	New storage classes for TIc80.
+
+Fri Apr 18 11:52:55 1997  Niklas Hallqvist  <niklas@appli.se>
+
+	* alpha.h (ALPHA_ECOFF_BADMAG): Recognize *BSD/alpha magic too.
+	(ALPHA_R_LITERALSLEAZY): Define.
+	* ecoff.h (ALPHA_MAGIC_BSD): Define.
+
+Wed Jan 29 11:31:51 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i960.h (R_IPR13, R_ALIGN): Define.
+
+Mon Jan 27 13:34:30 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* internal.h (R_IPRMED, R_OPTCALL, R_OPTCALLX): Move definitions
+	from here...
+	* i960.h (R_IPRMED, R_OPTCALL, R_OPTCALLX): ...to here.
+
+Wed Jan 22 20:10:47 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80MAGIC): Renamed to TIC80_AOUTHDR_MAGIC.
+
+Fri Dec 27 22:05:45 1996  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h: New file for TIc80 support.
+
+Thu Dec 19 16:18:11 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* arm.h (_LIT): Define.
+
+Fri Jun 28 12:54:38 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* pe.h (FILHSZ): Define.
+
+Wed Jun 26 16:24:26 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* All files: Define FILHSZ, AOUTSZ, AOUTHDRSZ, SCNHSZ, SYMESZ,
+	AUXESZ, LINESZ, RELSZ as numeric constants rather than uses of
+	sizeof.  Define AOUTHDRSZ in all files.
+	* pe.h (AOUTSZ): Define by adding to AOUTHDRSZ.
+
+Fri Jun 21 11:17:46 1996  Richard Henderson  <rth@tamu.edu>
+
+	* alpha.h: Add declarations for relocation types added for Alpha
+	OSF/1 3.0.
+
+Tue Jun 18 16:04:29 1996  Jeffrey A. Law  <law@rtl.cygnus.com>
+
+	* h8300.h (H8300SMAGIC): Define.
+	(H8300SBADMAG): Define.
+
+Mon Jun 10 11:53:28 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* internal.h (R_BCC_INV, R_JMP_DEL): New relocations for
+	relaxing in the H8/300 series.
+
+Thu May 16 15:49:22 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* sh.h (R_SH_CODE, R_SH_DATA, R_SH_LABEL): Define.
+
+Tue May  7 00:36:39 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* internal.h (R_JMPL2): Renamed from R_JMPL_B8 to be
+	consistent with other similar relocs.
+
+	* internal.h (H8/300 specific relocs): Add comments better
+	explaining what each reloc is used for.
+	(R_MOV16B1, R_MOV16B2): Renamed from R_MOVB1 and R_MOVB2.
+	(R_MOV24B1, R_MOV24B2): Renamed from R_MOVLB1 and R_MOVLB2.
+	(R_MOVL1, R_MOVL2): New relocs.
+
+Fri May  3 13:01:12 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* internal.h (R_PCRWORD_B): Define for the h8300 relaxing
+	linker.
+
+Wed May  1 19:21:03 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* internal.h (SCNNMLEN): Define.
+	(struct internal_scnhdr): Use SCNNMLEN for s_name field.
+
+Fri Mar 29 13:41:25 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* pe.h: Define IMAGE_COMDAT codes.
+
+Wed Mar 27 17:29:42 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* arm.h (union external_auxent): Add x_checksum, x_associated, and
+	x_comdat fields to x_scn struct.
+	* i386.h (union external_auxent): Likewise.
+	* powerpc.h (union external_auxent): Likewise.
+	* internal.h (union internal_auxent): Likewise.
+
+Thu Mar 21 16:25:57 1996  David Mosberger-Tang  <davidm@azstarnet.com>
+
+	* ecoff.h (struct ecoff_find_line): Add caching fields.
+
+Thu Mar 14 15:22:44 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* internal.h (R_MEM_INDIRECT): New reloc for the h8300.
+
+Fri Feb  9 10:44:11 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* aux-coff.h: Rename from aux.h, to avoid problems on hapless DOS
+	systems which think that aux is a com port.
+
+Mon Feb  5 18:35:00 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i960.h (F_I960HX): Define.
+
+Wed Jan 31 13:11:54 1996  Richard Henderson  <rth@tamu.edu>
+
+	* aux.h: New file.
+	* internal.h, m68k.h: Protect against multiple inclusion.
+
+Wed Nov 22 13:48:39 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ecoff.h (_RCONST, STYP_RCONST, RELOC_SECTION_RCONST): Define.
+	(NUM_RELOC_SECTIONS): Update.
+	* symconst.h (scRConst): Define.
+
+Tue Nov 14 18:54:29 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* internal.h (C_NT_WEAK): Define.
+
+Thu Nov  9 14:08:30 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* rs6000.h (STYP_OVRFLO): Define.
+
+Tue Nov  7 14:38:45 1995  Kim Knuttila  <krk@cygnus.com>
+
+	* powerpc.h (IMAGE_NT_OPTIONAL_HDR_MAGIC): Added define.
+	* pe.h: Added defines for file level flags
+
+Mon Nov  6 17:28:01 1995  Harry Dolan  <dolan@ssd.intel.com>
+
+	* i860.h: New file, based on i386.h.
+
+Wed Nov  1 15:25:18 1995  Manfred Hollstein KS/EF4A 60/1F/110 #40283  <manfred@lts.sel.alcatel.de>
+
+	* m68k.h (PAGEMAGICEXECSWAPPED): Define.
+	(PAGEMAGICPEXECSWAPPED): Define.
+	(PAGEMAGICPEXECTSHLIB): Define.
+	(PAGEMAGICPEXECPAGED): Define.
+	(_COMMENT): DEFINE.
+	* m88k.h (_COMMENT): Define.
+
+Wed Oct 18 18:36:19 1995  Geoffrey Noer  <noer@cygnus.com>
+
+	* sym.h: #if 0'd out runtime_pdr struct because it chokes
+	Visual C++ and there aren't any references to it elsewhere in gdb.
+
+Mon Oct 16 11:12:24 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* rs6000.h (SMALL_AOUTSZ): Define.
+
+	* internal.h (XMC_TD): Define.
+
+Tue Oct 10 18:41:03 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* internal.h (struct internal_aouthdr): Add o_cputype field.
+	* rs6000.h (AOUTHDR): Rename o_resv1 to o_cputype.
+
+Mon Oct  9 14:45:46 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* rs6000.h (AOUTHDR): Add o_maxdata field.  Add comments.
+	(_PAD, _LOADER): Define.
+	(STYP_LOADER): Define.
+	* internal.h (struct internal_aouthdr): Add o_maxdata field.
+
+Thu Oct  5 10:02:57 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ecoff.h: Define section name macros and STYP macros for various
+	Alpha sections: .got, .hash, .dynsym, .dynstr, .rel.dyn, .conflic,
+	.comment, .liblist, .dynamic.
+
+Wed Oct  4 10:56:35 1995  Kim Knuttila  <krk@cygnus.com>
+
+	* pe.h: Moved DOSMAGIC and NT_SIGNATURE defines here
+	* powerpc.h: removed DOSMAGIC, NT_SIGNATURE, and DEFAULT_* defines
+	Also removed other unused defines (various MAGIC ones)
+	* i386.h: removed DOSMAGIC, NT_SIGNATURE, and DEFAULT_* defines
+	* arm.h: removed DOSMAGIC, NT_SIGNATURE, and DEFAULT_* defines
+	* apollo.h: removed unused DEFAULT_* defines
+	* alpha.h: removed unused DEFAULT_* defines
+	* h8500.h: removed unused DEFAULT_* defines
+	* h8300.h: removed unused DEFAULT_* defines
+	* i960.h: removed unused DEFAULT_* defines
+	* m88k.h: removed unused DEFAULT_* defines
+	* we32k.h: removed unused DEFAULT_* defines
+	* rs6000.h: removed unused DEFAULT_* defines
+	* mips.h: removed unused DEFAULT_* defines
+	* m68k.h: removed unused DEFAULT_* defines
+	* z8k.h: removed unused DEFAULT_* defines
+	* w65.h: removed unused DEFAULT_* defines
+	* sparc.h: removed unused DEFAULT_* defines
+	* sh.h: removed unused DEFAULT_* defines
+
+Fri Sep 29 08:40:08 1995  Kim Knuttila  <krk@cygnus.com>
+
+	* powerpc.h: Reformatted to GNU coding conventions.
+
+Wed Sep 27 06:50:50 1995  Kim Knuttila  <krk@nellie>
+
+	* pe.h: added defines for more section characteristics
+	* powerpc.h (new file): base coff definitions for ppc PE
+
+Tue Sep 12 12:08:20 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* internal.h (struct internal_syment): Change n_numaux field from
+	char to unsigned char.
+
+Fri Sep  1 15:39:36 1995  Kazumoto Kojima  <kkojima@info.kanagawa-u.ac.jp>
+
+	* mips.h (struct rpdr_ext): Define.
+
+Thu Aug 31 16:51:50 1995  steve chamberlain  <sac@slash.cygnus.com>
+
+	* internal.h (internal_aouthdr, internal_filehdr):
+	don't indirect the pe stuff.
+
+Tue Aug 29 14:16:07 1995  steve chamberlain  <sac@slash.cygnus.com>
+
+	* i386.h (NT_DEF_RESERVE, NT_DEF_COMMIT): Make the same
+	as 'the other' compiler.
+	* internal.h (NT_IMAGE_BASE): Deleted.
+	(NT_EXE_IMAGE_BASE, NT_DLL_IMAGE_BASE): New.
+	(PE_DEF_SECTION_ALIGNMENT, PE_DEF_FILE_ALIGNMENT): New.
+	(R_IMAGEBASE): New.
+
+Mon Aug 21 18:12:19 1995  steve chamberlain  <sac@slash.cygnus.com>
+
+	* internal.h: (internal_filehdr): Moved PE stuff into
+	internal_extra_pe_filehdr.
+	(internal_aouthdr): Moved PE stuff into
+	interanl_extra_pe_aouthdr.
+
+Mon Jul 24 14:05:39 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* internal.h: Move R_SH_* relocs from here...
+	* sh.h: ...to here.
+	(R_SH_SWITCH16, R_SH_SWITCH32): Define.
+	(R_SH_USES, R_SH_COUNT, R_SH_ALIGN): Define.
+
+Thu Jun 29 00:04:25 1995  Steve Chamberlain  <sac@slash.cygnus.com>
+
+	* internal.h (NT_DEF_RESERVE, NT_DEF_COMMIT): Increase a lot.
+
+Tue May 16 15:08:20 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	* internal.h (NT_subsystem, NT_stack_heap): Delete
+
+Tue May 16 15:08:20 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	* internal.h (NT_subsystem, NT_stack_heap): Now extern.
+
+Sat May 13 10:14:08 1995  Steve Chamberlain  <sac@slash.cygnus.com>
+
+	* pe.h: New file.
+	* i386.h (NT_SECTION_ALIGNMENT, NT_FILE_ALIGNMENT,
+	NT_DEF_RESERVE, NT_DEF_COMMIT): New.
+	* internal.h (internal_filehdr):  New fields for PE.
+	(IMAGE_DATA_DIRECTORY): New.
+	(internal_aouthdr): New fields for PE.
+
+Tue Feb 14 17:59:37 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ecoff.h (struct ecoff_fdrtab_entry): Define.
+	(struct ecoff_find_line): Define.
+
+Sat Feb  4 14:38:03 1995  David Mosberger-Tang  <davidm@piston.cs.arizona.edu>
+
+	* sym.h (struct pdr): field "prof" added.
+
+	* alpha.h (PDR_BITS1_PROF_*): added, macros for PDR_BITS*_RESERVED_*
+	updated accordingly.
+
+Sun Jan 15 18:38:33 1995  Steve Chamberlain  <sac@splat>
+
+	* w65.h: New file.
+
+Wed Nov 23 22:43:38 1994  Steve Chamberlain  (sac@jonny.cygnus.com)
+
+	* sh.h (SH_ARCH_MAGIC_BIG, SH_ARCH_MAGIC_LITTLE): New.
+	(SHBADMAG): Changed to suit.
+
+Tue Jul 26 17:46:08 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* i960.h (F_I960JX): New macro.
+
+Wed Jul  6 00:48:57 1994  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
+
+	* alpha.h:  Add definitions for alpha file header flags, encoding
+	the object type of the file.
+
+Mon Jun 20 13:47:01 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
+
+	* ecoff.h (ecoff_swap_tir_in): Remove declaration.
+	(ecoff_swap_tir_out): Likewise.
+	(ecoff_swap_rndx_in, ecoff_swap_rndx_out): Likewise.
+	(struct ecoff_debug_swap): Add new fields: swap_tir_in,
+	swap_rndx_in, swap_tir_out, swap_rndx_out, read_debug_info.
+
+Sun Jun 12 03:51:52 1994  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
+
+	* symconst.h:  Pick up SGI define for stIndirect.
+
+Fri Apr 22 13:05:28 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ecoff.h (REGINFO): Don't define.
+	(struct ecoff_reginfo): Don't define.
+
+	* sh.h (SH_ARCH_MAGIC): Rename from SHMAGIC.  SHMAGIC is used by
+	several targets to mean a shared library.
+	(SHBADMAG): Corresponding change.
+
+Thu Apr 14 13:00:53 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h (RELOC_BITS3_TYPE_BIG): Changed from 0x1e to 0x3e.
+	(RELOC_BITS3_TYPEHI_LITTLE): Define.
+	(RELOC_BITS3_TYPEHI_SH_LITTLE): Define.
+	(MIPS_R_PCREL16): Change value from 8 to 12 to match Irix 4.
+	(MIPS_R_RELHI): Define.
+	(MIPS_R_RELLO): Define.
+	(MIPS_R_SWITCH): Change value from 9 to 22.
+
+Thu Apr  7 14:19:35 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h (MIPS_R_SWITCH): Define.
+
+Thu Mar 31 19:28:33 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* internal.h (internal_aouthdr): Added comments for Apollo fields.
+
+Thu Mar 31 16:28:02 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ecoff.h (STYP_ECOFF_LIB): Define as used on Irix 4.
+
+Fri Mar 25 17:16:55 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ecoff.h (struct ecoff_debug_info): Add adjust field.
+	(struct ecoff_value_adjust): Define.
+
+Tue Mar 22 13:22:47 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h (MIPS_R_PCREL16): Define.
+
+Sat Feb 26 10:26:38 1994  Ian Lance Taylor  (ian@cygnus.com)
+
+	* ecoff.h: Add casts to avoid warnings from SVR4 cc.
+
+Mon Feb 21 09:48:46 1994  Ian Lance Taylor  (ian@lisa.cygnus.com)
+
+	* sym.h (struct runtime_pdr): Make field adr bfd_vma, not unsigned
+	long.
+	(SYMR): Make field value bfd_vma, not long.
+
+Fri Feb  4 23:35:53 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* rs6000.h (STYP_DEBUG): Define.
+
+Wed Feb  2 14:31:37 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* internal.h (union internal_auxent): Change x_csect.x_scnlen into
+	a union of a long and a pointer to a symbol.  XCOFF sometimes uses
+	this field as a symbol index.
+
+Mon Jan 10 23:54:25 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ecoff.h (ecoff_debug_info): Remove fields line_end,
+	external_dnr_end, external_pdr_end, external_sym_end,
+	external_opt_end, external_aux_end, ss_end, external_fdr_end.
+	Replace ifdbase with ifdmap.
+
+Wed Jan  5 17:05:36 1994  Ken Raeburn  (raeburn@deneb.cygnus.com)
+
+	* ecoff.h (STYP_EXTENDESC, STYP_COMMENT, STYP_XDATA, STYP_PDATA):
+	Define.
+
+Wed Jan  5 16:58:24 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ecoff.h (NUM_RELOC_SECTIONS): Define.
+
+Tue Dec 21 09:24:56 1993  Ken Raeburn  (raeburn@rtl.cygnus.com)
+
+	* sparc.h (struct external_reloc): Rename field r_addend to
+	r_offset.
+
+Sat Dec 11 16:12:32 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* internal.h (R_DISP7, R_SH_IMM16): New reloc types.
+
+Tue Nov 23 14:23:19 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ecoff.h (struct ecoff_debug_swap): Added *_end fields for all
+	the symbolic information pointers.
+
+	* sym.h: Named the EXTR structure ecoff_extr.
+
+Fri Nov 19 08:21:18 1993  Ken Raeburn  (raeburn@rover.cygnus.com)
+
+	* sparc.h (RELSZ): Use correct size.
+
+Wed Nov 17 17:18:16 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h (struct ecoff_debug_info): Define.
+
+Tue Nov  2 17:56:57 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ecoff.h (struct ecoff_debug_swap): Define.
+
+Thu Oct 28 17:07:50 1993  Stan Shebs  (shebs@rtl.cygnus.com)
+
+	* i386.h (I386LYNXMAGIC): Rename to LYNXCOFFMAGIC.
+	* m68k.h (LYNXCOFFMAGIC): Define.
+	* sparc.h: New file.
+
+Tue Oct 19 15:34:50 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* alpha.h (external_aouthdr): Split four byte padding field into
+	two byte bldrev field and two byte padding field.
+
+	* ecoff.h (_LITA, _PDATA, _XDATA, STYP_LITA): Defined.
+
+Wed Oct 13 15:52:34 1993  Ken Raeburn  (raeburn@cygnus.com)
+
+	Sun Oct 10 17:27:10 1993  Troy Rollo (troy@cbme.unsw.edu.au)
+
+	* internal.h: Added o_sri, o_inlib and o_vid for Apollos as well
+	as R_DIR16.
+
+	* apollo.h: New file
+
+Mon Oct 11 17:16:48 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ecoff.h (REGINFO, struct ecoff_reginfo): Define.
+
+Tue Oct  5 10:52:53 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* rs6000.h: Change non-ASCII characters in comment to octal
+	escapes.
+
+Tue Sep 28 03:27:04 1993  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
+
+	* ecoff.h (_FINI, STYP_ECOFF_FINI):  Add to support .fini section.
+
+Fri Sep 24 11:53:53 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h (BADMAG): Recognize MIPS_MAGIC_LITTLE3 and MIPS_MAGIC_BIG3.
+	* ecoff.h: Define MIPS_MAGIC_LITTLE3 and MIPS_MAGIC_BIG3.
+
+Thu Sep 23 21:07:14 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* mips.h (BADMAG): Recognize MIPS_MAGIC_LITTLE2 and MIPS_MAGIC_BIG2.
+	* ecoff.h: Define MIPS_MAGIC_LITTLE2 and MIPS_MAGIC_BIG2.
+
+Thu Sep 16 20:27:21 1993  Jim Kingdon  (kingdon@cirdan.cygnus.com)
+
+	* sym.h, symconst.h: Add comment stating these files are not part
+	of GDB, GAS, etc.  In 1991, when we asked rms whether we could
+	include these files in GDB (although they are copyrighted by
+	someone besides the FSF), he said it was OK if they were not
+	considered part of GDB.
+
+Fri Sep 10 17:40:35 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ecoff.h (AUX_PUT_ANY): Cast val argument to bfd_vma.
+
+	* alpha.c (external_aouthdr): Need four bytes of padding between
+	vstamp and tsize.
+
+Tue Sep  7 14:20:43 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ecoff.h (AUX_GET_ANY, AUX_PUT_ANY): Changed to reflect further
+	change in bfd swapping routine names.
+
+Tue Sep  7 10:15:17 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* ecoff.h (AUX_GET_ANY): Change name of _do_getb32 to reflect bfd
+	changes.
+
+Fri Aug 13 14:30:32 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* ecoff.h (RELOC_SECTION_NONE): Define.
+
+Thu Aug 12 11:24:42 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* alpha.h (struct external_reloc): Add r_symndx field.
+	(RELSZ): Correct.
+	(RELOC_BITS*): Correct.
+	(ALPHA_R_*): Define.
+	* ecoff.h (RELOC_SECTION_{XDATA,PDATA,FINI,LITA,ABS}): Define.
+	(r_extern): Undefine.
+	* internal.h (struct internal_reloc): Make r_vaddr bfd_vma rather
+	than long.  Add r_extern field.
+
+	* alpha.h (PDR_BITS*): Define.
+	* sym.h (PDR): Give correct names to new fields.
+
+	* ecoff.h: Moved MIPS reloc definitions from here...
+	* mips.h: to here.
+
+Mon Aug  2 16:37:14 1993  Stu Grossman  (grossman at cygnus.com)
+
+	* i386.h:  Add Lynx magic number.
+
+Tue Aug  3 11:17:53 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* alpha.h: Corrected external symbolic debugging structures to
+	match actual usage.
+	* internal.h (internal_filehdr, internal_aouthdr,
+	internal_scnhdr): Changed type of some fields to bfd_vma so they
+	can hold 64 bits.
+	* sym.h (HDRR, FDR, PDR, EXTR): Likewise.
+	(PDR): Added new fields found on Alpha.
+	* symconst.h (magicSym2): Define; new value found on Alpha.
+
+	* ecoff.h: New file.
+	* alpha.h, mips.h: Moved common information into ecoff.h.  Moved
+	external structure definitions in from ecoff-ext.h.
+	* ecoff-ext.h: Removed; information now in alpha.h and mips.h.
+
+Sun Jul 18 21:43:59 1993  Jim Kingdon  (kingdon@rtl.cygnus.com)
+
+	* i386.h: Recognize I386PTXMAGIC.
+
+Fri Jul 16 09:54:35 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* mips.h (MIPS_AOUT_{OZ}MAGIC): Renamed from {OZ}MAGIC.
+
+Thu Jul 15 12:23:55 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* m88k.h (union external_auxent): Move x_fcn back inside x_fcnary.
+	({GET,PUT}_FCN_{LNNOPTR,ENDNDX}): Adjust accordingly.
+
+Sun Jul 11 18:00:18 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* m68k.h: Define MC68KBCSMAGIC.
+
+Thu Jun 10 11:46:28 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* mips.h (_INIT, STYP_MIPS_INIT): Define (used on Irix4).
+	(STYP_OTHER_LOAD): Define as STYP_MIPS_INIT.
+
+Wed Jun  9 15:09:09 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* mips.h (OMAGIC): Define.
+
+Tue Jun  8 12:16:03 1993  Steve Chamberlain  (sac@phydeaux.cygnus.com)
+
+	 Support for H8/300-H
+	* h8300.h: New magic number.
+	* internal.h: New relocations.
+
+Mon Apr 26 18:04:47 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* internal.h, sh.h: Support for SH.
+
+Sat Apr 24 21:34:59 1993  Jim Kingdon  (kingdon@cygnus.com)
+
+	* a29k.h: Define _LIT.
+
+Fri Apr 23 18:41:23 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* alpha.h: New file.
+
+Thu Apr  8 12:36:34 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* internal.h (C_SHADOW, C_VERSION): Copied in from m88k.h.
+	* m88k.h, i386.h, we32k.h: Don't define all the storage classes;
+	they're already in internal.h.
+
+Wed Apr  7 11:51:24 1993  Jim Kingdon  (kingdon@cygnus.com)
+
+	* internal.h: Change n_sclass to unsigned char.
+	Change C_EFCN to 0xff, change RS/6000 dbx symbols
+	to no longer be signed.
+
+Fri Mar 19 14:52:56 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* internal.h: Add H8/500 reloc types.
+
+Wed Mar 17 09:46:03 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* ecoff-ext.h (AUX_PUT_ANY): Don't use void values in branches of
+	conditional expression.
+
+Thu Mar  4 14:12:06 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* ecoff-ext.h (AUX_GET_*): Rewrote to use new macro AUX_GET_ANY.
+	(AUX_PUT_*): New macros corresponding to the AUX_GET macros.
+	(ecoff_swap_tir_out): Added prototype.
+
+	* mips.h (N_BTMASK, N_TMASK, N_BTSHFT, N_TSHIFT): Define; these
+	are needed to interpret gcc debugging output.
+
+Tue Feb  9 07:43:27 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* we32k.h (BTYPE, ISPTR, ISFCN, ISARY, DECREF): Removed
+	more definitions duplicated in internal.h.
+
+Wed Feb  3 09:18:24 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* mips.h (RELOC_BITS3_TYPE_*): Correct for big endian machines.
+
+Mon Jan 25 11:35:51 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* internal.h (internal_aouthdr): Added additional fields used only
+	by MIPS ECOFF.
+
+Thu Jan 21 10:28:38 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* mips.h (AOUTHDR): Added additional fields used by ECOFF.
+
+Tue Jan 19 12:21:19 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* i386.h, we32k.h (N_*, T_*, DT_*): Removed still more definitions
+	duplicated in internal.h.
+
+	* mips.h (RELOC_SECTION_*, ECOFF_R_*): Defined constants for ECOFF
+	relocs.
+
+Fri Jan 15 18:17:00 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ecoff-ext.h: Added prototypes for new ECOFF swapping functions.
+	(opt_ext): New structure.
+	* mips.h (ZMAGIC): Defined to be 0413.
+	(_LIB): Defined to be ".lib"
+	(external_reloc): MIPS ECOFF relocs are only 8 bytes.  Added
+	macros to aid in swapping.
+
+Fri Jan  8 16:19:26 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ecoff-ext.h: Added prototypes for ECOFF swapping functions.
+	* internal.h (internal_scnhdr): Always provide s_align field, not
+	just on i960.
+	(internal_reloc): Always provide r_size field, not just on
+	RS/6000.
+	* mips.h (_RDATA, _SDATA, _SBSS, _LIT4, _LIT8, STYP_RDATA,
+	STYP_SDATA, STYP_SBSS, STYP_LIT4, STYP_LIT8): Defined.
+	(CODE_MASK, MIPS_IS_STAB, MIPS_MARK_STAB, MIPS_UNMARK_STAB,
+	STABS_SYMBOL): Moved in from gdb/mipsread.c.
+
+Wed Jan  6 14:01:46 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* i386.h, we32k.h: removed STYP_* defines, since they duplicated
+	those in internal.h.
+
+Tue Dec 29 15:40:07 1992  Ian Lance Taylor  (ian@cygnus.com)
+
+	* i386.h: define I386AIXMAGIC for Danbury AIX PS/2 compiler.
+
+Sat Dec 12 16:07:57 1992  Ian Lance Taylor  (ian@cygnus.com)
+
+	* i386.h: don't define BTYPE, ISPTR, ISFCN, ISARY, DECREF: they
+	are defined in internal.h.
+
+Thu Nov 12 09:52:01 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* internal.h: (internal_reloc): r_offset is now a long.
+	* z8k.h: slight comment enhancement
+
+Wed Sep 30 07:46:08 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* internal.h: changed z8k reloc types
+
+Fri Aug 28 10:16:31 1992  Brendan Kehoe  (brendan@cygnus.com)
+
+	* we32k.h: new file
+
+Thu Aug 27 13:00:01 1992  Brendan Kehoe  (brendan@cygnus.com)
+
+	* symconst.h: comment out cruft at the end of #endif
+
+Tue Aug 25 15:06:49 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* internal.h: added #define for STYP_LIT, removed from a29k and
+	h8300.
+
+	* z8k.h: added z8000 support
+
+Thu Jul 16 16:32:00 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* internal.h: added R_RELLONG_NEG reloc type
+
+Fri Jun 12 20:11:04 1992  John Gilmore  (gnu at cygnus.com)
+
+	* symconst.h:  Fix unterminated comment.
+
+Wed Jun 10 07:57:49 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* i386.h: a.out magic numbers from
+	mohring@informatik.tu-muenchen.de
+
+Mon Jun  8 20:13:33 1992  John Gilmore  (gnu at cygnus.com)
+
+	* ecoff-ext.h, mips.h:  Use unsigned chars everywhere.
+	(Suggested by Antti Miettinen.)
+
+Tue Apr 14 15:18:44 1992  John Gilmore  (gnu at cygnus.com)
+
+	* sym.h:  Add comments.
+	* symconst.h:  Merge with Fred's changes.
+
+Tue Apr 14 14:30:05 1992  Fred Fish  (fnf@cygnus.com)
+
+	* symconst.h:  Pick up SGI defines for stStruct, stUnion, stEnum,
+	langCplusplus, and langCplusplusV2.
+
+Thu Apr  2 19:47:43 1992  John Gilmore  (gnu at cygnus.com)
+
+	* sym.h, symconst.h:  MIPS has provided redistributable versions
+	of these files.  Thanks!
+	* ecoff-ext.h:  Add weakext bit to match new sym.h.
+
+Fri Mar  6 00:10:46 1992  John Gilmore  (gnu at cygnus.com)
+
+	* ecoff-ext.h:  Add relative file descriptors.
+
+Thu Feb 27 11:53:04 1992  John Gilmore  (gnu at cygnus.com)
+
+	* ecoff-ext.h:  New file for external (in-file) form of ecoff
+	symbol structures.
+
+Thu Feb  6 11:33:32 1992  Steve Chamberlain  (sac at rtl.cygnus.com)
+
+	* h8300.h: made the external_lineno l_lnno field 4 bytes wide.
+	andded GET/PUT_LINENO_LNNO macros
+
+Sat Nov 30 20:38:35 1991  Steve Chamberlain  (sac at rtl.cygnus.com)
+
+	* a29k.h, h8300.h, i386.h, i960.h, internal.h, m68k.h, m88k.h,
+	mips.h, rs6000.h: Move from above coff-<foo>.h.
+
+
+Copyright (C) 1991-2003 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.25/include/coff/alpha.h b/binutils-2.25/include/coff/alpha.h
new file mode 100644
index 00000000..81516892
--- /dev/null
+++ b/binutils-2.25/include/coff/alpha.h
@@ -0,0 +1,386 @@
+/* ECOFF support on Alpha machines.
+   coff/ecoff.h must be included before this file.
+
+   Copyright 2001, 2005, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+   
+/********************** FILE HEADER **********************/
+
+struct external_filehdr
+{
+  unsigned char f_magic[2];	/* magic number			*/
+  unsigned char f_nscns[2];	/* number of sections		*/
+  unsigned char f_timdat[4];	/* time & date stamp		*/
+  unsigned char f_symptr[8];	/* file pointer to symtab	*/
+  unsigned char f_nsyms[4];	/* number of symtab entries	*/
+  unsigned char f_opthdr[2];	/* sizeof(optional hdr)		*/
+  unsigned char f_flags[2];	/* flags			*/
+};
+
+/* Magic numbers are defined in coff/ecoff.h.  */
+#define ALPHA_ECOFF_BADMAG(x) \
+  ((x).f_magic != ALPHA_MAGIC && (x).f_magic != ALPHA_MAGIC_BSD)
+
+#define ALPHA_ECOFF_COMPRESSEDMAG(x) \
+  ((x).f_magic == ALPHA_MAGIC_COMPRESSED)
+
+/* The object type is encoded in the f_flags.  */
+#define F_ALPHA_OBJECT_TYPE_MASK	0x3000
+#define F_ALPHA_NO_SHARED		0x1000
+#define F_ALPHA_SHARABLE		0x2000
+#define F_ALPHA_CALL_SHARED		0x3000
+
+#define	FILHDR	struct external_filehdr
+#define	FILHSZ	24
+
+/********************** AOUT "OPTIONAL HEADER" **********************/
+
+typedef struct external_aouthdr
+{
+  unsigned char magic[2];	/* type of file				*/
+  unsigned char	vstamp[2];	/* version stamp			*/
+  unsigned char bldrev[2];	/* ?? */
+  unsigned char padding[2];	/* pad to quadword boundary		*/
+  unsigned char	tsize[8];	/* text size in bytes			*/
+  unsigned char	dsize[8];	/* initialized data "  "		*/
+  unsigned char	bsize[8];	/* uninitialized data "   "		*/
+  unsigned char	entry[8];	/* entry pt.				*/
+  unsigned char text_start[8];	/* base of text used for this file */
+  unsigned char data_start[8];	/* base of data used for this file */
+  unsigned char bss_start[8];	/* base of bss used for this file */
+  unsigned char gprmask[4];	/* bitmask of general registers used */
+  unsigned char fprmask[4];	/* bitmask of floating point registers used */
+  unsigned char gp_value[8];	/* value for gp register */
+} AOUTHDR;
+
+/* compute size of a header */
+
+#define AOUTSZ 80
+#define AOUTHDRSZ 80
+
+/********************** SECTION HEADER **********************/
+
+struct external_scnhdr
+{
+  unsigned char	s_name[8];	/* section name			*/
+  unsigned char	s_paddr[8];	/* physical address, aliased s_nlib */
+  unsigned char	s_vaddr[8];	/* virtual address		*/
+  unsigned char	s_size[8];	/* section size			*/
+  unsigned char	s_scnptr[8];	/* file ptr to raw data for section */
+  unsigned char	s_relptr[8];	/* file ptr to relocation	*/
+  unsigned char	s_lnnoptr[8];	/* file ptr to line numbers	*/
+  unsigned char	s_nreloc[2];	/* number of relocation entries	*/
+  unsigned char	s_nlnno[2];	/* number of line number entries*/
+  unsigned char	s_flags[4];	/* flags			*/
+};
+
+#define	SCNHDR	struct external_scnhdr
+#define	SCNHSZ	64
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+struct external_reloc 
+{
+  unsigned char r_vaddr[8];
+  unsigned char r_symndx[4];
+  unsigned char r_bits[4];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 16
+
+/* Constants to unpack the r_bits field.  The Alpha seems to always be
+   little endian, so I haven't bothered to define big endian variants
+   of these.  */
+
+#define RELOC_BITS0_TYPE_LITTLE			0xff
+#define RELOC_BITS0_TYPE_SH_LITTLE		0
+
+#define RELOC_BITS1_EXTERN_LITTLE		0x01
+
+#define RELOC_BITS1_OFFSET_LITTLE		0x7e
+#define RELOC_BITS1_OFFSET_SH_LITTLE		1
+
+#define RELOC_BITS1_RESERVED_LITTLE		0x80
+#define RELOC_BITS1_RESERVED_SH_LITTLE		7
+#define RELOC_BITS2_RESERVED_LITTLE		0xff
+#define RELOC_BITS2_RESERVED_SH_LEFT_LITTLE	1
+#define RELOC_BITS3_RESERVED_LITTLE		0x03
+#define RELOC_BITS3_RESERVED_SH_LEFT_LITTLE	9
+
+#define RELOC_BITS3_SIZE_LITTLE			0xfc
+#define RELOC_BITS3_SIZE_SH_LITTLE		2
+
+/* The r_type field in a reloc is one of the following values.  */
+#define ALPHA_R_IGNORE		0
+#define ALPHA_R_REFLONG		1
+#define ALPHA_R_REFQUAD		2
+#define ALPHA_R_GPREL32		3
+#define ALPHA_R_LITERAL		4
+#define ALPHA_R_LITUSE		5
+#define ALPHA_R_GPDISP		6
+#define ALPHA_R_BRADDR		7
+#define ALPHA_R_HINT		8
+#define ALPHA_R_SREL16		9
+#define ALPHA_R_SREL32	       10
+#define ALPHA_R_SREL64	       11
+#define ALPHA_R_OP_PUSH	       12
+#define ALPHA_R_OP_STORE       13
+#define ALPHA_R_OP_PSUB	       14
+#define ALPHA_R_OP_PRSHIFT     15
+#define ALPHA_R_GPVALUE	       16
+#define ALPHA_R_GPRELHIGH      17
+#define ALPHA_R_GPRELLOW       18
+#define ALPHA_R_IMMED          19
+
+/* Overloaded reloc value used by Net- and OpenBSD.  */
+#define ALPHA_R_LITERALSLEAZY  17
+
+/* With ALPHA_R_LITUSE, the r_size field is one of the following values.  */
+#define ALPHA_R_LU_BASE         1
+#define ALPHA_R_LU_BYTOFF       2
+#define ALPHA_R_LU_JSR          3
+
+/* With ALPHA_R_IMMED, the r_size field is one of the following values.  */
+#define ALPHA_R_IMMED_GP_16     1
+#define ALPHA_R_IMMED_GP_HI32   2
+#define ALPHA_R_IMMED_SCN_HI32  3
+#define ALPHA_R_IMMED_BR_HI32   4
+#define ALPHA_R_IMMED_LO32      5
+
+/********************** SYMBOLIC INFORMATION **********************/
+
+/* Written by John Gilmore.  */
+
+/* ECOFF uses COFF-like section structures, but its own symbol format.
+   This file defines the symbol format in fields whose size and alignment
+   will not vary on different host systems.  */
+
+/* File header as a set of bytes */
+
+struct hdr_ext
+{
+	unsigned char 	h_magic[2];
+	unsigned char	h_vstamp[2];
+	unsigned char	h_ilineMax[4];
+	unsigned char	h_idnMax[4];
+	unsigned char	h_ipdMax[4];
+	unsigned char	h_isymMax[4];
+	unsigned char	h_ioptMax[4];
+	unsigned char	h_iauxMax[4];
+	unsigned char	h_issMax[4];
+	unsigned char	h_issExtMax[4];
+	unsigned char	h_ifdMax[4];
+	unsigned char	h_crfd[4];
+	unsigned char	h_iextMax[4];
+	unsigned char	h_cbLine[8];
+	unsigned char	h_cbLineOffset[8];
+	unsigned char	h_cbDnOffset[8];
+	unsigned char	h_cbPdOffset[8];
+	unsigned char	h_cbSymOffset[8];
+	unsigned char	h_cbOptOffset[8];
+	unsigned char	h_cbAuxOffset[8];
+	unsigned char	h_cbSsOffset[8];
+	unsigned char	h_cbSsExtOffset[8];
+	unsigned char	h_cbFdOffset[8];
+	unsigned char	h_cbRfdOffset[8];
+	unsigned char	h_cbExtOffset[8];
+};
+
+/* File descriptor external record */
+
+struct fdr_ext
+{
+	unsigned char	f_adr[8];
+	unsigned char	f_cbLineOffset[8];
+	unsigned char	f_cbLine[8];
+	unsigned char	f_cbSs[8];
+	unsigned char	f_rss[4];
+	unsigned char	f_issBase[4];
+	unsigned char	f_isymBase[4];
+	unsigned char	f_csym[4];
+	unsigned char	f_ilineBase[4];
+	unsigned char	f_cline[4];
+	unsigned char	f_ioptBase[4];
+	unsigned char	f_copt[4];
+	unsigned char	f_ipdFirst[4];
+	unsigned char	f_cpd[4];
+	unsigned char	f_iauxBase[4];
+	unsigned char	f_caux[4];
+	unsigned char	f_rfdBase[4];
+	unsigned char	f_crfd[4];
+	unsigned char	f_bits1[1];
+	unsigned char	f_bits2[3];
+	unsigned char	f_padding[4];
+};
+
+#define	FDR_BITS1_LANG_BIG		0xF8
+#define	FDR_BITS1_LANG_SH_BIG		3
+#define	FDR_BITS1_LANG_LITTLE		0x1F
+#define	FDR_BITS1_LANG_SH_LITTLE	0
+
+#define	FDR_BITS1_FMERGE_BIG		0x04
+#define	FDR_BITS1_FMERGE_LITTLE		0x20
+
+#define	FDR_BITS1_FREADIN_BIG		0x02
+#define	FDR_BITS1_FREADIN_LITTLE	0x40
+
+#define	FDR_BITS1_FBIGENDIAN_BIG	0x01
+#define	FDR_BITS1_FBIGENDIAN_LITTLE	0x80
+
+#define	FDR_BITS2_GLEVEL_BIG		0xC0
+#define	FDR_BITS2_GLEVEL_SH_BIG		6
+#define	FDR_BITS2_GLEVEL_LITTLE		0x03
+#define	FDR_BITS2_GLEVEL_SH_LITTLE	0
+
+/* We ignore the `reserved' field in bits2. */
+
+/* Procedure descriptor external record */
+
+struct pdr_ext {
+	unsigned char	p_adr[8];
+	unsigned char	p_cbLineOffset[8];
+	unsigned char	p_isym[4];
+	unsigned char	p_iline[4];
+	unsigned char	p_regmask[4];
+	unsigned char	p_regoffset[4];
+	unsigned char	p_iopt[4];
+	unsigned char	p_fregmask[4];
+	unsigned char	p_fregoffset[4];
+	unsigned char	p_frameoffset[4];
+	unsigned char	p_lnLow[4];
+	unsigned char	p_lnHigh[4];
+	unsigned char	p_gp_prologue[1];
+	unsigned char	p_bits1[1];
+	unsigned char	p_bits2[1];
+	unsigned char	p_localoff[1];
+	unsigned char	p_framereg[2];
+	unsigned char	p_pcreg[2];
+};
+
+#define PDR_BITS1_GP_USED_BIG		0x80
+#define PDR_BITS1_REG_FRAME_BIG		0x40
+#define PDR_BITS1_PROF_BIG		0x20
+#define PDR_BITS1_RESERVED_BIG		0x1f
+#define PDR_BITS1_RESERVED_SH_LEFT_BIG	8
+#define PDR_BITS2_RESERVED_BIG		0xff
+#define PDR_BITS2_RESERVED_SH_BIG	0
+
+#define PDR_BITS1_GP_USED_LITTLE	0x01
+#define PDR_BITS1_REG_FRAME_LITTLE	0x02
+#define PDR_BITS1_PROF_LITTLE		0x04
+#define PDR_BITS1_RESERVED_LITTLE	0xf8
+#define PDR_BITS1_RESERVED_SH_LITTLE	3
+#define PDR_BITS2_RESERVED_LITTLE	0xff
+#define PDR_BITS2_RESERVED_SH_LEFT_LITTLE 5
+
+/* Line numbers */
+
+struct line_ext {
+	unsigned char	l_line[4];
+};
+
+/* Symbol external record */
+
+struct sym_ext {
+	unsigned char	s_value[8];
+	unsigned char	s_iss[4];
+	unsigned char	s_bits1[1];
+	unsigned char	s_bits2[1];
+	unsigned char	s_bits3[1];
+	unsigned char	s_bits4[1];
+};
+
+#define	SYM_BITS1_ST_BIG		0xFC
+#define	SYM_BITS1_ST_SH_BIG		2
+#define	SYM_BITS1_ST_LITTLE		0x3F
+#define	SYM_BITS1_ST_SH_LITTLE		0
+
+#define	SYM_BITS1_SC_BIG		0x03
+#define	SYM_BITS1_SC_SH_LEFT_BIG	3
+#define	SYM_BITS1_SC_LITTLE		0xC0
+#define	SYM_BITS1_SC_SH_LITTLE		6
+
+#define	SYM_BITS2_SC_BIG		0xE0
+#define	SYM_BITS2_SC_SH_BIG		5
+#define	SYM_BITS2_SC_LITTLE		0x07
+#define	SYM_BITS2_SC_SH_LEFT_LITTLE	2
+
+#define	SYM_BITS2_RESERVED_BIG		0x10
+#define	SYM_BITS2_RESERVED_LITTLE	0x08
+
+#define	SYM_BITS2_INDEX_BIG		0x0F
+#define	SYM_BITS2_INDEX_SH_LEFT_BIG	16
+#define	SYM_BITS2_INDEX_LITTLE		0xF0
+#define	SYM_BITS2_INDEX_SH_LITTLE	4
+
+#define	SYM_BITS3_INDEX_SH_LEFT_BIG	8
+#define	SYM_BITS3_INDEX_SH_LEFT_LITTLE	4
+
+#define	SYM_BITS4_INDEX_SH_LEFT_BIG	0
+#define	SYM_BITS4_INDEX_SH_LEFT_LITTLE	12
+
+/* External symbol external record */
+
+struct ext_ext {
+	struct	sym_ext es_asym;
+	unsigned char	es_bits1[1];
+	unsigned char	es_bits2[3];
+	unsigned char	es_ifd[4];
+};
+
+#define	EXT_BITS1_JMPTBL_BIG		0x80
+#define	EXT_BITS1_JMPTBL_LITTLE		0x01
+
+#define	EXT_BITS1_COBOL_MAIN_BIG	0x40
+#define	EXT_BITS1_COBOL_MAIN_LITTLE	0x02
+
+#define	EXT_BITS1_WEAKEXT_BIG		0x20
+#define	EXT_BITS1_WEAKEXT_LITTLE	0x04
+
+/* Dense numbers external record */
+
+struct dnr_ext {
+	unsigned char	d_rfd[4];
+	unsigned char	d_index[4];
+};
+
+/* Relative file descriptor */
+
+struct rfd_ext {
+  unsigned char	rfd[4];
+};
+
+/* Optimizer symbol external record */
+
+struct opt_ext {
+  unsigned char o_bits1[1];
+  unsigned char o_bits2[1];
+  unsigned char o_bits3[1];
+  unsigned char o_bits4[1];
+  struct rndx_ext o_rndx;
+  unsigned char o_offset[4];
+};
+
+#define OPT_BITS2_VALUE_SH_LEFT_BIG	16
+#define OPT_BITS2_VALUE_SH_LEFT_LITTLE	0
+
+#define OPT_BITS3_VALUE_SH_LEFT_BIG	8
+#define OPT_BITS3_VALUE_SH_LEFT_LITTLE	8
+
+#define OPT_BITS4_VALUE_SH_LEFT_BIG	0
+#define OPT_BITS4_VALUE_SH_LEFT_LITTLE	16
diff --git a/binutils-2.25/include/coff/apollo.h b/binutils-2.25/include/coff/apollo.h
new file mode 100644
index 00000000..1d4802f1
--- /dev/null
+++ b/binutils-2.25/include/coff/apollo.h
@@ -0,0 +1,125 @@
+/* coff information for Apollo M68K
+
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define DO_NOT_DEFINE_AOUTHDR
+#define L_LNNO_SIZE 2
+#include "coff/external.h"
+
+/* Motorola 68000/68008/68010/68020 */
+#define	MC68MAGIC	0520
+#define MC68KWRMAGIC	0520	/* writeable text segments */
+#define	MC68TVMAGIC	0521
+#define MC68KROMAGIC	0521	/* readonly shareable text segments */
+#define MC68KPGMAGIC	0522	/* demand paged text segments */
+#define	M68MAGIC	0210
+#define	M68TVMAGIC	0211
+
+/* Apollo 68000-based machines have a different magic number. This comes
+ * from /usr/include/apollo/filehdr.h
+ */
+#define APOLLOM68KMAGIC 0627
+
+#define OMAGIC M68MAGIC
+#define M68KBADMAG(x) (((x).f_magic!=MC68MAGIC) && ((x).f_magic!=MC68KWRMAGIC) && ((x).f_magic!=MC68TVMAGIC) && \
+  ((x).f_magic!=MC68KROMAGIC) && ((x).f_magic!=MC68KPGMAGIC) && ((x).f_magic!=M68MAGIC) && ((x).f_magic!=M68TVMAGIC)  && \
+  ((x).f_magic!=APOLLOM68KMAGIC) )
+
+/********************** AOUT "OPTIONAL HEADER" **********************/
+
+typedef struct 
+{
+  char 	magic[2];		/* type of file				*/
+  char	vstamp[2];		/* version stamp			*/
+  char	tsize[4];		/* text size in bytes, padded to FW bdry*/
+  char	dsize[4];		/* initialized data "  "		*/
+  char	bsize[4];		/* uninitialized data "   "		*/
+  char	entry[4];		/* entry pt.				*/
+  char 	text_start[4];		/* base of text used for this file */
+  char 	data_start[4];		/* base of data used for this file */
+  char	o_sri[4];		/* Apollo specific - .sri data pointer */
+  char  o_inlib[4];		/* Apollo specific - .inlib data pointer */
+  char	vid[8];			/* Apollo specific - 64 bit version ID */
+}
+AOUTHDR;
+
+#define	APOLLO_COFF_VERSION_NUMBER 1 /* the value of the aouthdr magic */
+#define	AOUTHDRSZ 44
+#define AOUTSZ 44
+
+/* Apollo allowa for larger section names by allowing
+   them to be in the string table.  */
+
+/* If s_zeores is all zeroes, s_offset gives the real
+   location of the name in the string table.  */
+
+#define	s_zeroes section_name.s_name
+#define	s_offset (section_name.s_name+4)
+
+/* More names of "special" sections.  */
+#define _TV	".tv"
+#define _INIT	".init"
+#define _FINI	".fini"
+#define	_LINES	".lines"
+#define	_BLOCKS	".blocks"
+#define _SRI    ".sri"                  /* Static Resource Information (systype,
+ et al.) */
+#define _MIR    ".mir"                  /* Module Information Records  */
+#define _APTV   ".aptv"                 /* Apollo-style transfer vectors. */
+#define _INLIB  ".inlib"                /* Shared Library information */
+#define _RWDI   ".rwdi"         /* Read/write data initialization directives for
+ compressed sections */
+#define _UNWIND ".unwind"               /* Stack unwind information */
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+#ifdef M68K_COFF_OFFSET
+  char r_offset[4];
+#endif
+
+};
+
+#define RELOC struct external_reloc
+
+#ifdef M68K_COFF_OFFSET
+#define RELSZ 14
+#else
+#define RELSZ 10
+#endif
+
+/* Apollo specific STYP flags */
+
+#define STYP_RELOCATED_NOT_LOADED 0x00010000	/* Section is relocated normally during linking, but need
+                                            	   not be loaded during program execution */
+#define STYP_DEBUG              0x00020000	/* debug section */
+#define STYP_OVERLAY		0x00040000	/* Section is overlayed */
+#define STYP_INSTRUCTION    	0x00200000	/* Section contains executable code */
+
+#define STYP_ZERO		0x00800000	/* Section is initialized to zero */
+#define STYP_INSTALLED		0x02000000	/* Section should be installable in KGT */
+#define STYP_LOOK_INSTALLED	0x04000000	/* Look for section in KGT */
+#define STYP_SECALIGN1		0x08000000	/* Specially aligned section */
+#define STYP_SECALIGN2		0x10000000	/*      "       "       "    */
+#define STYP_COMPRESSED		0x20000000	/* No section data per se (s_scnptr = 0), but there are
+						   initialization directives for it in .rwdi section
+						   (used in conjunction with STYP_BSS) */
diff --git a/binutils-2.25/include/coff/arm.h b/binutils-2.25/include/coff/arm.h
new file mode 100644
index 00000000..4beb1212
--- /dev/null
+++ b/binutils-2.25/include/coff/arm.h
@@ -0,0 +1,130 @@
+/* ARM COFF support for BFD.
+   Copyright 1998, 1999, 2000, 2002, 2003, 2010, 2013
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#define COFFARM 1
+
+#define L_LNNO_SIZE 2
+#define INCLUDE_COMDAT_FIELDS_IN_AUXENT
+#include "coff/external.h"
+
+/* Bits for f_flags:
+ 	F_RELFLG	relocation info stripped from file
+ 	F_EXEC		file is executable (no unresolved external references)
+ 	F_LNNO		line numbers stripped from file
+ 	F_LSYMS		local symbols stripped from file
+        F_INTERWORK     file supports switching between ARM and Thumb instruction sets
+        F_INTERWORK_SET the F_INTERWORK bit is valid
+ 	F_APCS_FLOAT	code passes float arguments in float registers
+ 	F_PIC		code is reentrant/position-independent
+ 	F_AR32WR	file has byte ordering of an AR32WR machine (e.g. vax)
+ 	F_APCS_26	file uses 26 bit ARM Procedure Calling Standard
+ 	F_APCS_SET	the F_APCS_26, F_APCS_FLOAT and F_PIC bits have been initialised
+ 	F_SOFT_FLOAT	code does not use floating point instructions.  */
+
+#define F_RELFLG	(0x0001)
+#define F_EXEC		(0x0002)
+#define F_LNNO		(0x0004)
+#define F_LSYMS		(0x0008)
+#define F_INTERWORK	(0x0010)
+#define F_INTERWORK_SET	(0x0020)
+#define F_APCS_FLOAT	(0x0040)
+#undef  F_AR16WR
+#define F_PIC		(0x0080)
+#define	F_AR32WR	(0x0100)
+#define F_APCS_26	(0x0400)
+#define F_APCS_SET	(0x0800)
+#define F_SOFT_FLOAT	(0x2000)
+#define F_VFP_FLOAT	(0x4000)
+
+/* Bits stored in flags field of the internal_f structure */
+
+#define F_INTERWORK	(0x0010)
+#define F_APCS_FLOAT	(0x0040)
+#define F_PIC		(0x0080)
+#define F_APCS26	(0x1000)
+#define F_ARM_ARCHITECTURE_MASK (0x4000+0x0800+0x0400)
+#define F_ARM_2		(0x0400)
+#define F_ARM_2a	(0x0800)
+#define F_ARM_3		(0x0c00)
+#define F_ARM_3M	(0x4000)
+#define F_ARM_4		(0x4400)
+#define F_ARM_4T	(0x4800)
+#define F_ARM_5		(0x4c00)
+
+/*
+  ARMMAGIC ought to encoded the procesor type,
+  but it is too late to change it now, instead
+  the flags field of the internal_f structure
+  is used as shown above.
+ 
+  XXX - NC 5/6/97.  */
+
+#define	ARMMAGIC	0xa00  /* I just made this up */
+
+#define ARMBADMAG(x) (((x).f_magic != ARMMAGIC))
+
+#define	ARMPEMAGIC	0x1c0
+#define	THUMBPEMAGIC	0x1c2
+#define	ARMV7PEMAGIC	0x1c4
+
+#undef  ARMBADMAG
+#define ARMBADMAG(x) (((x).f_magic != ARMMAGIC) && ((x).f_magic != ARMPEMAGIC) && ((x).f_magic != THUMBPEMAGIC) && ((x).f_magic != ARMV7PEMAGIC))
+
+#define OMAGIC          0404    /* object files, eg as output */
+#define ZMAGIC          0413    /* demand load format, eg normal ld output */
+#define STMAGIC		0401	/* target shlib */
+#define SHMAGIC		0443	/* host   shlib */
+
+/* define some NT default values */
+/*  #define NT_IMAGE_BASE        0x400000 moved to internal.h */
+#define NT_SECTION_ALIGNMENT 0x1000
+#define NT_FILE_ALIGNMENT    0x200  
+#define NT_DEF_RESERVE       0x100000
+#define NT_DEF_COMMIT        0x1000
+
+/* We use the .rdata section to hold read only data.  */
+#define _LIT	".rdata"
+
+/********************** RELOCATION DIRECTIVES **********************/
+#ifdef ARM_WINCE
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 10
+
+#else
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+  char r_offset[4];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 14
+#endif
+
+#define ARM_NOTE_SECTION ".note"
diff --git a/binutils-2.25/include/coff/aux-coff.h b/binutils-2.25/include/coff/aux-coff.h
new file mode 100644
index 00000000..de7979a6
--- /dev/null
+++ b/binutils-2.25/include/coff/aux-coff.h
@@ -0,0 +1,49 @@
+/* Modifications of internal.h and m68k.h needed by A/UX
+
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.
+   
+   Suggested by Ian Lance Taylor <ian@cygnus.com> */
+
+#ifndef GNU_COFF_AUX_H
+#define GNU_COFF_AUX_H 1
+
+#include "coff/internal.h"
+#include "coff/m68k.h"
+
+/* Section contains 64-byte padded pathnames of shared libraries */
+#undef STYP_LIB
+#define STYP_LIB 0x200
+
+/* Section contains shared library initialization code */
+#undef STYP_INIT
+#define STYP_INIT 0x400
+
+/* Section contains .ident information */
+#undef STYP_IDENT
+#define STYP_IDENT 0x800
+
+/* Section types used by bfd and gas not defined (directly) by A/UX */
+#undef STYP_OVER
+#define STYP_OVER 0
+#undef STYP_INFO
+#define STYP_INFO STYP_IDENT
+
+/* Traditional name of the section tagged with STYP_LIB */
+#define _LIB ".lib"
+
+#endif /* GNU_COFF_AUX_H */
diff --git a/binutils-2.25/include/coff/ecoff.h b/binutils-2.25/include/coff/ecoff.h
new file mode 100644
index 00000000..a7991a99
--- /dev/null
+++ b/binutils-2.25/include/coff/ecoff.h
@@ -0,0 +1,411 @@
+/* Generic ECOFF support.
+   This does not include symbol information, found in sym.h and
+   symconst.h.
+
+   Copyright 2001, 2002, 2003, 2004, 2005, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef ECOFF_H
+#define ECOFF_H
+
+/* Mips magic numbers used in filehdr.  MIPS_MAGIC_LITTLE is used on
+   little endian machines.  MIPS_MAGIC_BIG is used on big endian
+   machines.  Where is MIPS_MAGIC_1 from?  */
+#define MIPS_MAGIC_1 0x0180
+#define MIPS_MAGIC_LITTLE 0x0162
+#define MIPS_MAGIC_BIG 0x0160
+
+/* These are the magic numbers used for MIPS code compiled at ISA
+   level 2.  */
+#define MIPS_MAGIC_LITTLE2 0x0166
+#define MIPS_MAGIC_BIG2 0x0163
+
+/* These are the magic numbers used for MIPS code compiled at ISA
+   level 3.  */
+#define MIPS_MAGIC_LITTLE3 0x142
+#define MIPS_MAGIC_BIG3 0x140
+
+/* Alpha magic numbers used in filehdr.  */
+#define ALPHA_MAGIC 0x183
+#define ALPHA_MAGIC_BSD 0x185
+/* A compressed version of an ALPHA_MAGIC file created by DEC's tools.  */
+#define ALPHA_MAGIC_COMPRESSED 0x188
+
+/* Magic numbers used in a.out header.  */
+#define ECOFF_AOUT_OMAGIC 0407	/* not demand paged (ld -N).  */
+#define ECOFF_AOUT_ZMAGIC 0413	/* demand load format, eg normal ld output */
+
+/* Names of special sections.  */
+#define _TEXT   ".text"
+#define _DATA   ".data"
+#define _BSS    ".bss"
+#define _RDATA	".rdata"
+#define _SDATA	".sdata"
+#define _SBSS	".sbss"
+#define _LITA	".lita"
+#define _LIT4	".lit4"
+#define _LIT8	".lit8"
+#define _LIB	".lib"
+#define _INIT	".init"
+#define _FINI	".fini"
+#define _PDATA	".pdata"
+#define _XDATA	".xdata"
+#define _GOT	".got"
+#define _HASH	".hash"
+#define _DYNSYM	".dynsym"
+#define _DYNSTR	".dynstr"
+#define _RELDYN	".rel.dyn"
+#define _CONFLIC ".conflic"
+#define _COMMENT ".comment"
+#define _LIBLIST ".liblist"
+#define _DYNAMIC ".dynamic"
+#define _RCONST	".rconst"
+
+/* ECOFF uses some additional section flags.  */
+#define STYP_RDATA	     0x100
+#define STYP_SDATA	     0x200
+#define STYP_SBSS	     0x400
+#define STYP_GOT	    0x1000
+#define STYP_DYNAMIC	    0x2000
+#define STYP_DYNSYM	    0x4000
+#define STYP_RELDYN	    0x8000
+#define STYP_DYNSTR	   0x10000
+#define STYP_HASH	   0x20000
+#define STYP_LIBLIST	   0x40000
+#define STYP_CONFLIC	  0x100000
+#define STYP_ECOFF_FINI	 0x1000000
+#define STYP_EXTENDESC	 0x2000000 /* 0x02FFF000 bits => scn type, rest clr */
+#define STYP_LITA	 0x4000000
+#define STYP_LIT8	 0x8000000
+#define STYP_LIT4	0x10000000
+#define STYP_ECOFF_LIB	0x40000000
+#define STYP_ECOFF_INIT 0x80000000
+#define STYP_OTHER_LOAD (STYP_ECOFF_INIT | STYP_ECOFF_FINI)
+
+/* extended section types */
+#define STYP_COMMENT	 0x2100000
+#define STYP_RCONST	 0x2200000
+#define STYP_XDATA	 0x2400000
+#define STYP_PDATA	 0x2800000
+
+/* The linker needs a section to hold small common variables while
+   linking.  There is no convenient way to create it when the linker
+   needs it, so we always create one for each BFD.  We then avoid
+   writing it out.  */
+#define SCOMMON ".scommon"
+
+/* If the extern bit in a reloc is 1, then r_symndx is an index into
+   the external symbol table.  If the extern bit is 0, then r_symndx
+   indicates a section, and is one of the following values.  */
+#define RELOC_SECTION_NONE	0
+#define RELOC_SECTION_TEXT	1
+#define RELOC_SECTION_RDATA	2
+#define RELOC_SECTION_DATA	3
+#define RELOC_SECTION_SDATA	4
+#define RELOC_SECTION_SBSS	5
+#define RELOC_SECTION_BSS	6
+#define RELOC_SECTION_INIT	7
+#define RELOC_SECTION_LIT8	8
+#define RELOC_SECTION_LIT4	9
+#define RELOC_SECTION_XDATA    10
+#define RELOC_SECTION_PDATA    11
+#define RELOC_SECTION_FINI     12
+#define RELOC_SECTION_LITA     13
+#define RELOC_SECTION_ABS      14
+#define RELOC_SECTION_RCONST   15
+
+#define NUM_RELOC_SECTIONS     16
+
+/********************** STABS **********************/
+
+/* gcc uses mips-tfile to output type information in special stabs
+   entries.  These must match the corresponding definition in
+   gcc/config/mips.h.  At some point, these should probably go into a
+   shared include file, but currently gcc and gdb do not share any
+   directories. */
+#define CODE_MASK 0x8F300
+#define ECOFF_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
+#define ECOFF_MARK_STAB(code) ((code)+CODE_MASK)
+#define ECOFF_UNMARK_STAB(code) ((code)-CODE_MASK)
+#define STABS_SYMBOL "@stabs"
+
+/********************** COFF **********************/
+
+/* gcc also uses mips-tfile to output COFF debugging information.
+   These are the values it uses when outputting the .type directive.
+   These should also be in a shared include file.  */
+#define N_BTMASK	(017)
+#define N_TMASK		(060)
+#define N_BTSHFT	(4)
+#define N_TSHIFT	(2)
+
+/********************** AUX **********************/
+
+/* The auxiliary type information is the same on all known ECOFF
+   targets.  I can't see any reason that it would ever change, so I am
+   going to gamble and define the external structures here, in the
+   target independent ECOFF header file.  The internal forms are
+   defined in coff/sym.h, which was originally donated by MIPS
+   Computer Systems.  */
+
+/* Type information external record */
+
+struct tir_ext {
+	unsigned char	t_bits1[1];
+	unsigned char	t_tq45[1];
+	unsigned char	t_tq01[1];
+	unsigned char	t_tq23[1];
+};
+
+#define	TIR_BITS1_FBITFIELD_BIG		((unsigned int) 0x80)
+#define	TIR_BITS1_FBITFIELD_LITTLE	((unsigned int) 0x01)
+
+#define	TIR_BITS1_CONTINUED_BIG		((unsigned int) 0x40)
+#define	TIR_BITS1_CONTINUED_LITTLE	((unsigned int) 0x02)
+
+#define	TIR_BITS1_BT_BIG		((unsigned int) 0x3F)
+#define	TIR_BITS1_BT_SH_BIG		0
+#define	TIR_BITS1_BT_LITTLE		((unsigned int) 0xFC)
+#define	TIR_BITS1_BT_SH_LITTLE		2
+
+#define	TIR_BITS_TQ4_BIG		((unsigned int) 0xF0)
+#define	TIR_BITS_TQ4_SH_BIG		4
+#define	TIR_BITS_TQ5_BIG		((unsigned int) 0x0F)
+#define	TIR_BITS_TQ5_SH_BIG		0
+#define	TIR_BITS_TQ4_LITTLE		((unsigned int) 0x0F)
+#define	TIR_BITS_TQ4_SH_LITTLE		0
+#define	TIR_BITS_TQ5_LITTLE		((unsigned int) 0xF0)
+#define	TIR_BITS_TQ5_SH_LITTLE		4
+
+#define	TIR_BITS_TQ0_BIG		((unsigned int) 0xF0)
+#define	TIR_BITS_TQ0_SH_BIG		4
+#define	TIR_BITS_TQ1_BIG		((unsigned int) 0x0F)
+#define	TIR_BITS_TQ1_SH_BIG		0
+#define	TIR_BITS_TQ0_LITTLE		((unsigned int) 0x0F)
+#define	TIR_BITS_TQ0_SH_LITTLE		0
+#define	TIR_BITS_TQ1_LITTLE		((unsigned int) 0xF0)
+#define	TIR_BITS_TQ1_SH_LITTLE		4
+
+#define	TIR_BITS_TQ2_BIG		((unsigned int) 0xF0)
+#define	TIR_BITS_TQ2_SH_BIG		4
+#define	TIR_BITS_TQ3_BIG		((unsigned int) 0x0F)
+#define	TIR_BITS_TQ3_SH_BIG		0
+#define	TIR_BITS_TQ2_LITTLE		((unsigned int) 0x0F)
+#define	TIR_BITS_TQ2_SH_LITTLE		0
+#define	TIR_BITS_TQ3_LITTLE		((unsigned int) 0xF0)
+#define	TIR_BITS_TQ3_SH_LITTLE		4
+
+/* Relative symbol external record */
+
+struct rndx_ext {
+	unsigned char	r_bits[4];
+};
+
+#define	RNDX_BITS0_RFD_SH_LEFT_BIG	4
+#define	RNDX_BITS1_RFD_BIG		((unsigned int) 0xF0)
+#define	RNDX_BITS1_RFD_SH_BIG		4
+
+#define	RNDX_BITS0_RFD_SH_LEFT_LITTLE	0
+#define	RNDX_BITS1_RFD_LITTLE		((unsigned int) 0x0F)
+#define	RNDX_BITS1_RFD_SH_LEFT_LITTLE	8
+
+#define	RNDX_BITS1_INDEX_BIG		((unsigned int) 0x0F)
+#define	RNDX_BITS1_INDEX_SH_LEFT_BIG	16
+#define	RNDX_BITS2_INDEX_SH_LEFT_BIG	8
+#define	RNDX_BITS3_INDEX_SH_LEFT_BIG	0
+
+#define	RNDX_BITS1_INDEX_LITTLE		((unsigned int) 0xF0)
+#define	RNDX_BITS1_INDEX_SH_LITTLE	4
+#define	RNDX_BITS2_INDEX_SH_LEFT_LITTLE	4
+#define	RNDX_BITS3_INDEX_SH_LEFT_LITTLE	12
+
+/* Auxiliary symbol information external record */
+
+union aux_ext {
+	struct tir_ext	a_ti;
+	struct rndx_ext	a_rndx;
+	unsigned char	a_dnLow[4];
+	unsigned char	a_dnHigh[4];
+	unsigned char	a_isym[4];
+	unsigned char	a_iss[4];
+	unsigned char	a_width[4];
+	unsigned char	a_count[4];
+};
+
+#define AUX_GET_ANY(bigend, ax, field) \
+  ((bigend) ? bfd_getb32 ((ax)->field) : bfd_getl32 ((ax)->field))
+
+#define	AUX_GET_DNLOW(bigend, ax)	AUX_GET_ANY ((bigend), (ax), a_dnLow)
+#define	AUX_GET_DNHIGH(bigend, ax)	AUX_GET_ANY ((bigend), (ax), a_dnHigh)
+#define	AUX_GET_ISYM(bigend, ax)	AUX_GET_ANY ((bigend), (ax), a_isym)
+#define AUX_GET_ISS(bigend, ax)		AUX_GET_ANY ((bigend), (ax), a_iss)
+#define AUX_GET_WIDTH(bigend, ax)	AUX_GET_ANY ((bigend), (ax), a_width)
+#define AUX_GET_COUNT(bigend, ax)	AUX_GET_ANY ((bigend), (ax), a_count)
+
+#define AUX_PUT_ANY(bigend, val, ax, field) \
+  ((bigend) \
+   ? (bfd_putb32 ((bfd_vma) (val), (ax)->field), 0) \
+   : (bfd_putl32 ((bfd_vma) (val), (ax)->field), 0))
+
+#define AUX_PUT_DNLOW(bigend, val, ax) \
+  AUX_PUT_ANY ((bigend), (val), (ax), a_dnLow)
+#define AUX_PUT_DNHIGH(bigend, val, ax) \
+  AUX_PUT_ANY ((bigend), (val), (ax), a_dnHigh)
+#define AUX_PUT_ISYM(bigend, val, ax) \
+  AUX_PUT_ANY ((bigend), (val), (ax), a_isym)
+#define AUX_PUT_ISS(bigend, val, ax) \
+  AUX_PUT_ANY ((bigend), (val), (ax), a_iss)
+#define AUX_PUT_WIDTH(bigend, val, ax) \
+  AUX_PUT_ANY ((bigend), (val), (ax), a_width)
+#define AUX_PUT_COUNT(bigend, val, ax) \
+  AUX_PUT_ANY ((bigend), (val), (ax), a_count)
+
+/********************** SYMBOLS **********************/
+
+/* For efficiency, gdb deals directly with the unswapped symbolic
+   information (that way it only takes the time to swap information
+   that it really needs to read).  gdb originally retrieved the
+   information directly from the BFD backend information, but that
+   strategy, besides being sort of ugly, does not work for MIPS ELF,
+   which also uses ECOFF debugging information.  This structure holds
+   pointers to the (mostly) unswapped symbolic information.  */
+
+struct ecoff_debug_info
+{
+  /* The swapped ECOFF symbolic header.  */
+  HDRR symbolic_header;
+
+  /* Pointers to the unswapped symbolic information.  Note that the
+     pointers to external structures point to different sorts of
+     information on different ECOFF targets.  The ecoff_debug_swap
+     structure provides the sizes of the structures and the functions
+     needed to swap the information in and out.  These pointers are
+     all pointers to arrays, not single structures.  They will be NULL
+     if there are no instances of the relevant structure.  These
+     fields are also used by the assembler to output ECOFF debugging
+     information.  */
+  unsigned char *line;
+  void *external_dnr;	/* struct dnr_ext */
+  void *external_pdr;	/* struct pdr_ext */
+  void *external_sym;	/* struct sym_ext */
+  void *external_opt;	/* struct opt_ext */
+  union aux_ext *external_aux;
+  char *ss;
+  char *ssext;
+  void *external_fdr;	/* struct fdr_ext */
+  void *external_rfd;	/* struct rfd_ext */
+  void *external_ext;	/* struct ext_ext */
+
+  /* These fields are used when linking.  They may disappear at some
+     point.  */
+  char *ssext_end;
+  void *external_ext_end;
+
+  /* When linking, this field holds a mapping from the input FDR
+     numbers to the output numbers, and is used when writing out the
+     external symbols.  It is NULL if no mapping is required.  */
+  RFDT *ifdmap;
+
+  /* The swapped FDR information.  Currently this is never NULL, but
+     code using this structure should probably double-check in case
+     this changes in the future.  This is a pointer to an array, not a
+     single structure.  */
+  FDR *fdr;
+};
+
+/* These structures are used by the ECOFF find_nearest_line function.  */
+
+struct ecoff_fdrtab_entry
+{
+  /* Base address in .text of this FDR.  */
+  bfd_vma base_addr;
+  FDR *fdr;
+};
+
+struct ecoff_find_line
+{
+  /* Allocated memory to hold function and file names.  */
+  char *find_buffer;
+
+  /* FDR table, sorted by address: */
+  long fdrtab_len;
+  struct ecoff_fdrtab_entry *fdrtab;
+
+  /* Cache entry for most recently found line information.  The sect
+     field is NULL if this cache does not contain valid information.  */
+  struct
+    {
+      asection *sect;
+      bfd_vma start;
+      bfd_vma stop;
+      const char *filename;
+      const char *functionname;
+      unsigned int line_num;
+    } cache;
+};
+
+/********************** SWAPPING **********************/
+
+/* The generic ECOFF code needs to be able to swap debugging
+   information in and out in the specific format used by a particular
+   ECOFF implementation.  This structure provides the information
+   needed to do this.  */
+
+struct ecoff_debug_swap
+{
+  /* Symbol table magic number.  */
+  int sym_magic;
+  /* Alignment of debugging information.  E.g., 4.  */
+  bfd_size_type debug_align;
+  /* Sizes of external symbolic information.  */
+  bfd_size_type external_hdr_size;
+  bfd_size_type external_dnr_size;
+  bfd_size_type external_pdr_size;
+  bfd_size_type external_sym_size;
+  bfd_size_type external_opt_size;
+  bfd_size_type external_fdr_size;
+  bfd_size_type external_rfd_size;
+  bfd_size_type external_ext_size;
+  /* Functions to swap in external symbolic data.  */
+  void (*swap_hdr_in) (bfd *, void *, HDRR *);
+  void (*swap_dnr_in) (bfd *, void *, DNR *);
+  void (*swap_pdr_in) (bfd *, void *, PDR *);
+  void (*swap_sym_in) (bfd *, void *, SYMR *);
+  void (*swap_opt_in) (bfd *, void *, OPTR *);
+  void (*swap_fdr_in) (bfd *, void *, FDR *);
+  void (*swap_rfd_in) (bfd *, void *, RFDT *);
+  void (*swap_ext_in) (bfd *, void *, EXTR *);
+  void (*swap_tir_in) (int, const struct tir_ext *, TIR *);
+  void (*swap_rndx_in) (int, const struct rndx_ext *, RNDXR *);
+  /* Functions to swap out external symbolic data.  */
+  void (*swap_hdr_out) (bfd *, const HDRR *, void *);
+  void (*swap_dnr_out) (bfd *, const DNR *, void *);
+  void (*swap_pdr_out) (bfd *, const PDR *, void *);
+  void (*swap_sym_out) (bfd *, const SYMR *, void *);
+  void (*swap_opt_out) (bfd *, const OPTR *, void *);
+  void (*swap_fdr_out) (bfd *, const FDR *, void *);
+  void (*swap_rfd_out) (bfd *, const RFDT *, void *);
+  void (*swap_ext_out) (bfd *, const EXTR *, void *);
+  void (*swap_tir_out) (int, const TIR *, struct tir_ext *);
+  void (*swap_rndx_out) (int, const RNDXR *, struct rndx_ext *);
+  /* Function to read symbol data and set up pointers in
+     ecoff_debug_info structure.  The section argument is used for
+     ELF, not straight ECOFF.  */
+  bfd_boolean (*read_debug_info) (bfd *, asection *, struct ecoff_debug_info *);
+};
+
+#endif /* ! defined (ECOFF_H) */
diff --git a/binutils-2.25/include/coff/external.h b/binutils-2.25/include/coff/external.h
new file mode 100644
index 00000000..4bf594d3
--- /dev/null
+++ b/binutils-2.25/include/coff/external.h
@@ -0,0 +1,269 @@
+/* external.h  -- External COFF structures
+   
+   Copyright 2001, 2006, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef COFF_EXTERNAL_H
+#define COFF_EXTERNAL_H
+
+#ifndef DO_NOT_DEFINE_FILHDR
+/********************** FILE HEADER **********************/
+
+struct external_filehdr
+  {
+    char f_magic[2];	/* magic number			*/
+    char f_nscns[2];	/* number of sections		*/
+    char f_timdat[4];	/* time & date stamp		*/
+    char f_symptr[4];	/* file pointer to symtab	*/
+    char f_nsyms[4];	/* number of symtab entries	*/
+    char f_opthdr[2];	/* sizeof(optional hdr)		*/
+    char f_flags[2];	/* flags			*/
+  };
+
+#define	FILHDR	struct external_filehdr
+#define	FILHSZ	20
+#endif
+
+#ifndef DO_NOT_DEFINE_AOUTHDR
+/********************** AOUT "OPTIONAL HEADER" **********************/
+
+typedef struct external_aouthdr
+  {
+    char magic[2];	/* type of file				*/
+    char vstamp[2];	/* version stamp			*/
+    char tsize[4];	/* text size in bytes, padded to FW bdry*/
+    char dsize[4];	/* initialized data "  "		*/
+    char bsize[4];	/* uninitialized data "   "		*/
+    char entry[4];	/* entry pt.				*/
+    char text_start[4];	/* base of text used for this file 	*/
+    char data_start[4];	/* base of data used for this file 	*/
+  } ATTRIBUTE_PACKED
+AOUTHDR;
+
+#define AOUTHDRSZ 28
+#define AOUTSZ 28
+
+typedef struct external_aouthdr64
+{
+  char magic[2];	/* Type of file.			*/
+  char vstamp[2];	/* Version stamp.			*/
+  char tsize[4];	/* Text size in bytes, padded to FW bdry*/
+  char dsize[4];	/* Initialized data "  ".		*/
+  char bsize[4];	/* Uninitialized data "   ".		*/
+  char entry[4];	/* Entry pt.				*/
+  char text_start[4];	/* Base of text used for this file. 	*/
+}
+AOUTHDR64;
+#define AOUTHDRSZ64	24
+
+#endif /* not DO_NOT_DEFINE_AOUTHDR */
+
+#ifndef DO_NOT_DEFINE_SCNHDR
+/********************** SECTION HEADER **********************/
+
+struct external_scnhdr
+  {
+    char s_name[8];	/* section name				*/
+    char s_paddr[4];	/* physical address, aliased s_nlib 	*/
+    char s_vaddr[4];	/* virtual address			*/
+    char s_size[4];	/* section size				*/
+    char s_scnptr[4];	/* file ptr to raw data for section 	*/
+    char s_relptr[4];	/* file ptr to relocation		*/
+    char s_lnnoptr[4];	/* file ptr to line numbers		*/
+    char s_nreloc[2];	/* number of relocation entries		*/
+    char s_nlnno[2];	/* number of line number entries	*/
+    char s_flags[4];	/* flags				*/
+  };
+
+#define	SCNHDR	struct external_scnhdr
+#define	SCNHSZ	40
+
+/* Names of "special" sections.  */
+
+#define _TEXT	 ".text"
+#define _DATA	 ".data"
+#define _BSS	 ".bss"
+#define _COMMENT ".comment"
+#define _LIB     ".lib"
+#endif /* not DO_NOT_DEFINE_SCNHDR */
+
+#ifndef DO_NOT_DEFINE_LINENO
+
+/********************** LINE NUMBERS **********************/
+
+#ifndef L_LNNO_SIZE
+#error  L_LNNO_SIZE needs to be defined
+#endif
+
+/* 1 line number entry for every "breakpointable" source line in a section.
+   Line numbers are grouped on a per function basis; first entry in a function
+   grouping will have l_lnno = 0 and in place of physical address will be the
+   symbol table index of the function name.  */
+struct external_lineno
+{
+  union
+  {
+    char l_symndx[4];	/* function name symbol index, iff l_lnno == 0*/
+    char l_paddr[4];	/* (physical) address of line number	*/
+  } l_addr;
+
+  char l_lnno[L_LNNO_SIZE];	/* line number		*/
+};
+
+#define	LINENO	struct external_lineno
+#define	LINESZ	(4 + L_LNNO_SIZE)
+
+#if L_LNNO_SIZE == 4
+#define GET_LINENO_LNNO(abfd, ext)      H_GET_32 (abfd,      (ext->l_lnno))
+#define PUT_LINENO_LNNO(abfd, val, ext) H_PUT_32 (abfd, val, (ext->l_lnno))
+#endif
+#if L_LNNO_SIZE == 2
+#define GET_LINENO_LNNO(abfd, ext)      H_GET_16 (abfd,      (ext->l_lnno))
+#define PUT_LINENO_LNNO(abfd, val, ext) H_PUT_16 (abfd, val, (ext->l_lnno))
+#endif
+
+#endif /* not DO_NOT_DEFINE_LINENO */
+
+#ifndef DO_NOT_DEFINE_SYMENT
+/********************** SYMBOLS **********************/
+
+#define E_SYMNMLEN	8	/* # characters in a symbol name	*/
+#ifndef E_FILNMLEN
+#define E_FILNMLEN	14
+#endif
+#define E_DIMNUM	4	/* # array dimensions in auxiliary entry */
+
+struct external_syment 
+{
+  union
+  {
+    char e_name[E_SYMNMLEN];
+
+    struct
+    {
+      char e_zeroes[4];
+      char e_offset[4];
+    } e;
+  } e;
+
+  char e_value[4];
+  char e_scnum[2];
+  char e_type[2];
+  char e_sclass[1];
+  char e_numaux[1];
+} ATTRIBUTE_PACKED ;
+
+#define	SYMENT	struct external_syment
+#define	SYMESZ	18	
+
+#ifndef N_BTMASK
+#define N_BTMASK	0xf
+#endif
+
+#ifndef N_TMASK
+#define N_TMASK		0x30
+#endif
+
+#ifndef N_BTSHFT
+#define N_BTSHFT	4
+#endif
+
+#ifndef N_TSHIFT
+#define N_TSHIFT	2
+#endif
+
+#endif /* not DO_NOT_DEFINE_SYMENT */
+
+#ifndef DO_NOT_DEFINE_AUXENT
+
+union external_auxent
+{
+  struct
+  {
+    char x_tagndx[4];		/* str, un, or enum tag indx */
+    
+    union
+    {
+      struct
+      {
+	char  x_lnno[2]; /* declaration line number */
+	char  x_size[2]; /* str/union/array size */
+      } x_lnsz;
+      
+      char x_fsize[4];	/* size of function */
+      
+    } x_misc;
+    
+    union
+    {
+      struct 		/* if ISFCN, tag, or .bb */
+      {
+	char x_lnnoptr[4];	/* ptr to fcn line # */
+	char x_endndx[4];	/* entry ndx past block end */
+      } x_fcn;
+      
+      struct 		/* if ISARY, up to 4 dimen. */
+      {
+	char x_dimen[E_DIMNUM][2];
+      } x_ary;
+      
+    } x_fcnary;
+    
+    char x_tvndx[2];	/* tv index */
+    
+  } x_sym;
+  
+  union
+  {
+    char x_fname[E_FILNMLEN];
+    
+    struct
+    {
+      char x_zeroes[4];
+      char x_offset[4];
+    } x_n;
+    
+  } x_file;
+  
+  struct
+  {
+    char x_scnlen[4];	/* section length */
+    char x_nreloc[2];	/* # relocation entries */
+    char x_nlinno[2];	/* # line numbers */
+#ifdef INCLUDE_COMDAT_FIELDS_IN_AUXENT
+    char x_checksum[4];		   /* section COMDAT checksum	      */
+    char x_associated[2];	   /* COMDAT associated section index */
+    char x_comdat[1];		   /* COMDAT selection number	      */
+#endif    
+  } x_scn;
+  
+  struct
+  {
+    char x_tvfill[4];	/* tv fill value */
+    char x_tvlen[2];	/* length of .tv */
+    char x_tvran[2][2];	/* tv range */
+  } x_tv;		/* info about .tv section (in auxent of symbol .tv)) */
+} ATTRIBUTE_PACKED ;
+
+#define	AUXENT	union external_auxent
+#define	AUXESZ	18
+
+#define _ETEXT	"etext"
+
+#endif /* not DO_NOT_DEFINE_AUXENT */
+
+#endif /* COFF_EXTERNAL_H */
diff --git a/binutils-2.25/include/coff/go32exe.h b/binutils-2.25/include/coff/go32exe.h
new file mode 100644
index 00000000..a2ca6cd7
--- /dev/null
+++ b/binutils-2.25/include/coff/go32exe.h
@@ -0,0 +1,36 @@
+/* COFF information for PC running go32.
+
+   Copyright 2001, 2005, 2009, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+struct external_filehdr_go32_exe
+  {
+    char stub[GO32_STUBSIZE]; /* the stub to load the image */
+			/* the standard COFF header     */
+    char f_magic[2];	/* magic number			*/
+    char f_nscns[2];	/* number of sections		*/
+    char f_timdat[4];	/* time & date stamp		*/
+    char f_symptr[4];	/* file pointer to symtab	*/
+    char f_nsyms[4];	/* number of symtab entries	*/
+    char f_opthdr[2];	/* sizeof(optional hdr)		*/
+    char f_flags[2];	/* flags			*/
+  };
+
+#undef FILHDR
+#define	FILHDR	struct external_filehdr_go32_exe
+#undef FILHSZ
+#define	FILHSZ	GO32_STUBSIZE+20
diff --git a/binutils-2.25/include/coff/h8300.h b/binutils-2.25/include/coff/h8300.h
new file mode 100644
index 00000000..4de6602e
--- /dev/null
+++ b/binutils-2.25/include/coff/h8300.h
@@ -0,0 +1,55 @@
+/* coff information for Renesas H8/300 and H8/300-H
+
+   Copyright 2001, 2003, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define L_LNNO_SIZE 4
+#include "coff/external.h"
+
+#define	H8300MAGIC	0x8300
+#define	H8300HMAGIC	0x8301
+#define	H8300SMAGIC	0x8302
+#define	H8300HNMAGIC	0x8303
+#define	H8300SNMAGIC	0x8304
+
+#define H8300BADMAG(x)   (((x).f_magic != H8300MAGIC))
+#define H8300HBADMAG(x)  (((x).f_magic != H8300HMAGIC))
+#define H8300SBADMAG(x)  (((x).f_magic != H8300SMAGIC))
+#define H8300HNBADMAG(x) (((x).f_magic != H8300HNMAGIC))
+#define H8300SNBADMAG(x) (((x).f_magic != H8300SNMAGIC))
+
+/* Relocation directives.  */
+
+/* The external reloc has an offset field, because some of the reloc
+   types on the h8 don't have room in the instruction for the entire
+   offset - eg the strange jump and high page addressing modes.  */
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_offset[4];
+  char r_type[2];
+  char r_stuff[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 16
+
+
+
+
diff --git a/binutils-2.25/include/coff/h8500.h b/binutils-2.25/include/coff/h8500.h
new file mode 100644
index 00000000..56097f86
--- /dev/null
+++ b/binutils-2.25/include/coff/h8500.h
@@ -0,0 +1,47 @@
+/* coff information for Renesas H8/500
+   
+   Copyright 2001, 2003, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define L_LNNO_SIZE 4
+#include "coff/external.h"
+
+#define	H8500MAGIC	0x8500
+
+#define H8500BADMAG(x) ((0xffff && ((x).f_magic) != H8500MAGIC))
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+/* The external reloc has an offset field, because some of the reloc
+   types on the h8 don't have room in the instruction for the entire
+   offset - eg the strange jump and high page addressing modes.  */
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_offset[4];
+  char r_type[2];
+  char r_stuff[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 16
+
+
+
+
diff --git a/binutils-2.25/include/coff/i386.h b/binutils-2.25/include/coff/i386.h
new file mode 100644
index 00000000..61e723ab
--- /dev/null
+++ b/binutils-2.25/include/coff/i386.h
@@ -0,0 +1,74 @@
+/* coff information for Intel 386/486.
+   
+   Copyright 2001, 2009, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define L_LNNO_SIZE 2
+#define INCLUDE_COMDAT_FIELDS_IN_AUXENT
+#include "coff/external.h"
+
+#define COFF_PAGE_SIZE	0x1000
+
+/* Bits for f_flags:
+ 	F_RELFLG	Relocation info stripped from file
+ 	F_EXEC		File is executable (no unresolved external references)
+ 	F_LNNO		Line numbers stripped from file
+ 	F_LSYMS		Local symbols stripped from file
+ 	F_AR32WR	File has byte ordering of an AR32WR machine (e.g. vax).  */
+
+#define F_RELFLG	(0x0001)
+#define F_EXEC		(0x0002)
+#define F_LNNO		(0x0004)
+#define F_LSYMS		(0x0008)
+
+#define	I386MAGIC	0x14c
+#define I386PTXMAGIC	0x154
+#define I386AIXMAGIC	0x175
+
+/* This is Lynx's all-platform magic number for executables.  */
+
+#define LYNXCOFFMAGIC	0415
+
+#define I386BADMAG(x) (  ((x).f_magic != I386MAGIC) \
+		       && (x).f_magic != I386AIXMAGIC \
+		       && (x).f_magic != I386PTXMAGIC \
+		       && (x).f_magic != LYNXCOFFMAGIC)
+
+#define OMAGIC          0404    /* Object files, eg as output.  */
+#define ZMAGIC          0413    /* Demand load format, eg normal ld output.  */
+#define STMAGIC		0401	/* Target shlib.  */
+#define SHMAGIC		0443	/* Host shlib.  */
+
+/* Define some NT default values.  */
+/*  #define NT_IMAGE_BASE        0x400000 moved to internal.h */
+#define NT_SECTION_ALIGNMENT 0x1000
+#define NT_FILE_ALIGNMENT    0x200
+#define NT_DEF_RESERVE       0x100000
+#define NT_DEF_COMMIT        0x1000
+
+/* Relocation directives.  */
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 10
+
diff --git a/binutils-2.25/include/coff/i860.h b/binutils-2.25/include/coff/i860.h
new file mode 100644
index 00000000..0767de4f
--- /dev/null
+++ b/binutils-2.25/include/coff/i860.h
@@ -0,0 +1,87 @@
+/* COFF information for the Intel i860.
+   
+   Copyright 2001, 2003, 2010, 2011 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file was hacked from i386.h   [dolan@ssd.intel.com] */
+
+#define L_LNNO_SIZE 2
+#include "coff/external.h"
+
+/* Bits for f_flags:
+ 	F_RELFLG	relocation info stripped from file
+ 	F_EXEC		file is executable (no unresolved external references)
+ 	F_LNNO		line numbers stripped from file
+ 	F_LSYMS		local symbols stripped from file
+ 	F_AR32WR	file has byte ordering of an AR32WR machine (e.g. vax).  */
+
+#define F_RELFLG	(0x0001)
+#define F_EXEC		(0x0002)
+#define F_LNNO		(0x0004)
+#define F_LSYMS		(0x0008)
+
+#define	I860MAGIC	0x14d
+
+#define I860BADMAG(x)   ((x).f_magic != I860MAGIC)
+
+#undef AOUTSZ
+#define AOUTSZ 36
+
+/* FIXME: What are the a.out magic numbers?  */
+
+#define _ETEXT	"etext"
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 10
+
+/* The relocation directory entry types.
+     PAIR   : The low half that follows relates to the preceding HIGH[ADJ].
+     HIGH   : The high half of a 32-bit constant.
+     LOWn   : The low half, insn bits 15..(n-1), 2^n-byte aligned. 
+     SPLITn : The low half, insn bits 20..16 and 10..(n-1), 2^n-byte aligned. 
+     HIGHADJ: Similar to HIGH, but with adjustment.
+     BRADDR : 26-bit branch displacement.
+
+   Note: The Intel assembler manual lists LOW4 as one of the
+   relocation types, but it appears to be useless for the i860.
+   We will recognize it anyway, just in case it actually appears in
+   any object files.  */
+
+enum {
+  COFF860_R_PAIR	= 0x1c,
+  COFF860_R_HIGH	= 0x1e,
+  COFF860_R_LOW0	= 0x1f,
+  COFF860_R_LOW1	= 0x20,
+  COFF860_R_LOW2	= 0x21,
+  COFF860_R_LOW3	= 0x22,
+  COFF860_R_LOW4	= 0x23,
+  COFF860_R_SPLIT0	= 0x24,
+  COFF860_R_SPLIT1	= 0x25,
+  COFF860_R_SPLIT2	= 0x26,
+  COFF860_R_HIGHADJ	= 0x27,
+  COFF860_R_BRADDR	= 0x28
+};
+
diff --git a/binutils-2.25/include/coff/i960.h b/binutils-2.25/include/coff/i960.h
new file mode 100644
index 00000000..2bf42adc
--- /dev/null
+++ b/binutils-2.25/include/coff/i960.h
@@ -0,0 +1,320 @@
+/* coff information for 80960.  Origins: Intel corp, natch.
+   
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* NOTE: Tagentries (cf TAGBITS) are no longer used by the 960 */
+
+/********************** FILE HEADER **********************/
+
+struct external_filehdr
+{
+  char f_magic[2];	/* magic number			*/
+  char f_nscns[2];	/* number of sections		*/
+  char f_timdat[4];	/* time & date stamp		*/
+  char f_symptr[4];	/* file pointer to symtab	*/
+  char f_nsyms[4];	/* number of symtab entries	*/
+  char f_opthdr[2];	/* sizeof(optional hdr)		*/
+  char f_flags[2];	/* flags			*/
+};
+
+#define OMAGIC      (0407)	/* old impure format. data immediately
+                                   follows text. both sections are rw. */
+#define NMAGIC      (0410)	/* split i&d, read-only text */
+
+/*
+*	Intel 80960 (I960) processor flags.
+*	F_I960TYPE == mask for processor type field. 
+*/
+
+#define	F_I960TYPE	(0xf000)
+#define	F_I960CORE	(0x1000)
+#define	F_I960KB	(0x2000)
+#define	F_I960SB	(0x2000)
+#define	F_I960MC	(0x3000)
+#define	F_I960XA	(0x4000)
+#define	F_I960CA	(0x5000)
+#define	F_I960KA	(0x6000)
+#define	F_I960SA	(0x6000)
+#define F_I960JX	(0x7000)
+#define F_I960HX	(0x8000)
+
+
+/** i80960 Magic Numbers
+*/
+
+#define I960ROMAGIC	(0x160)	/* read-only text segments */
+#define I960RWMAGIC	(0x161)	/* read-write text segments */
+
+#define I960BADMAG(x) (((x).f_magic!=I960ROMAGIC) && ((x).f_magic!=I960RWMAGIC))
+
+#define	FILHDR	struct external_filehdr
+#define	FILHSZ	20
+
+/********************** AOUT "OPTIONAL HEADER" **********************/
+
+typedef struct
+{
+  unsigned long	phys_addr;
+  unsigned long	bitarray;
+} TAGBITS;
+
+typedef struct 
+{
+  char 	magic[2];		/* type of file				*/
+  char	vstamp[2];		/* version stamp			*/
+  char	tsize[4];		/* text size in bytes, padded to FW bdry*/
+  char	dsize[4];		/* initialized data "  "		*/
+  char	bsize[4];		/* uninitialized data "   "		*/
+  char	entry[4];		/* entry pt.				*/
+  char 	text_start[4];		/* base of text used for this file */
+  char 	data_start[4];		/* base of data used for this file */
+  char	tagentries[4];		/* number of tag entries to follow */
+}
+AOUTHDR;
+
+/* return a pointer to the tag bits array */
+
+#define TAGPTR(aout) ((TAGBITS *) (&(aout.tagentries)+1))
+
+/* compute size of a header */
+
+/*#define AOUTSZ(aout) (sizeof(AOUTHDR)+(aout.tagentries*sizeof(TAGBITS)))*/
+#define AOUTSZ 32
+#define AOUTHDRSZ 32
+
+
+/********************** SECTION HEADER **********************/
+
+struct external_scnhdr
+{
+  char		s_name[8];	/* section name			*/
+  char		s_paddr[4];	/* physical address, aliased s_nlib */
+  char		s_vaddr[4];	/* virtual address		*/
+  char		s_size[4];	/* section size			*/
+  char		s_scnptr[4];	/* file ptr to raw data for section */
+  char		s_relptr[4];	/* file ptr to relocation	*/
+  char		s_lnnoptr[4];	/* file ptr to line numbers	*/
+  char		s_nreloc[2];	/* number of relocation entries	*/
+  char		s_nlnno[2];	/* number of line number entries*/
+  char		s_flags[4];	/* flags			*/
+  char 		s_align[4];	/* section alignment		*/
+};
+
+
+#define	SCNHDR	struct external_scnhdr
+#define	SCNHSZ	44
+
+/*
+ * names of "special" sections
+ */
+#define _TEXT   ".text"
+#define _DATA   ".data"
+#define _BSS    ".bss"
+
+/********************** LINE NUMBERS **********************/
+
+/* 1 line number entry for every "breakpointable" source line in a section.
+ * Line numbers are grouped on a per function basis; first entry in a function
+ * grouping will have l_lnno = 0 and in place of physical address will be the
+ * symbol table index of the function name.
+ */
+struct external_lineno
+{
+  union
+  {
+    char l_symndx[4];	/* function name symbol index, iff l_lnno == 0*/
+    char l_paddr[4];	/* (physical) address of line number	*/
+  } l_addr;
+
+  char l_lnno[2];		/* line number		*/
+  char padding[2];	/* force alignment	*/
+};
+
+
+#define	LINENO	struct external_lineno
+#define	LINESZ	8
+
+/********************** SYMBOLS **********************/
+
+#define E_SYMNMLEN	8	/* # characters in a symbol name	*/
+#define E_FILNMLEN	14	/* # characters in a file name		*/
+#define E_DIMNUM	4	/* # array dimensions in auxiliary entry */
+
+struct external_syment 
+{
+  union
+  {
+    char e_name[E_SYMNMLEN];
+
+    struct
+    {
+      char e_zeroes[4];
+      char e_offset[4];
+    } e;
+  } e;
+
+  char e_value[4];
+  char e_scnum[2];
+  char e_flags[2];
+  char e_type[4];
+  char e_sclass[1];
+  char e_numaux[1];
+  char pad2[2];
+};
+
+#define N_BTMASK	(0x1f)
+#define N_TMASK		(0x60)
+#define N_BTSHFT	(5)
+#define N_TSHIFT	(2)
+  
+union external_auxent
+{
+  struct
+  {
+    char x_tagndx[4];	/* str, un, or enum tag indx */
+
+    union
+    {
+      struct
+      {
+	char  x_lnno[2]; /* declaration line number */
+	char  x_size[2]; /* str/union/array size */
+      } x_lnsz;
+
+      char x_fsize[4];	/* size of function */
+
+    } x_misc;
+
+    union
+    {
+      struct 		/* if ISFCN, tag, or .bb */
+      {
+	char x_lnnoptr[4];	/* ptr to fcn line # */
+	char x_endndx[4];	/* entry ndx past block end */
+      } x_fcn;
+
+      struct 		/* if ISARY, up to 4 dimen. */
+      {
+	char x_dimen[E_DIMNUM][2];
+      } x_ary;
+
+    } x_fcnary;
+
+    char x_tvndx[2];		/* tv index */
+
+  } x_sym;
+
+  union
+  {
+    char x_fname[E_FILNMLEN];
+
+    struct
+    {
+      char x_zeroes[4];
+      char x_offset[4];
+    } x_n;
+
+  } x_file;
+
+  struct
+  {
+    char x_scnlen[4];			/* section length */
+    char x_nreloc[2];	/* # relocation entries */
+    char x_nlinno[2];	/* # line numbers */
+
+  } x_scn;
+
+  struct
+  {
+    char x_tvfill[4];	/* tv fill value */
+    char x_tvlen[2];	/* length of .tv */
+    char x_tvran[2][2];	/* tv range */
+
+  } x_tv;		/* info about .tv section (in auxent of symbol .tv)) */
+
+  /******************************************
+   *  I960-specific *2nd* aux. entry formats
+   ******************************************/
+  struct
+  {
+    /* This is a very old typo that keeps getting propagated. */
+#define x_stdindx x_stindx
+    char x_stindx[4];	/* sys. table entry */
+  } x_sc;	/* system call entry */
+
+  struct
+  {
+    char x_balntry[4]; /* BAL entry point */
+  } x_bal; /* BAL-callable function */
+
+  struct
+  {
+    char x_timestamp[4];	        /* time stamp */
+    char 	x_idstring[20];	        /* producer identity string */
+
+  } x_ident;	                        /* Producer ident info */
+};
+
+#define	SYMENT	struct external_syment
+#define	SYMESZ	24
+#define	AUXENT	union external_auxent
+#define	AUXESZ	24
+
+#	define _ETEXT	"_etext"
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+  char pad[2];
+};
+
+/* r_type values for the i960.  */
+
+/* The i960 uses R_RELLONG, which is defined in internal.h as 0x11.
+   It is an absolute 32 bit relocation.  */
+
+#define R_IPRMED 	(0x19)	/* 24-bit ip-relative relocation */
+#define R_OPTCALL	(0x1b)	/* 32-bit optimizable call (leafproc/sysproc) */
+#define R_OPTCALLX	(0x1c)	/* 64-bit optimizable call (leafproc/sysproc) */
+
+/* The following relocation types are defined use by relaxing linkers,
+   which convert 32 bit calls (which require a 64 bit instruction)
+   into 24 bit calls (which require a 32 bit instruction) when
+   possible.  It will be possible whenever the target of the call is
+   within a 24 bit range of the call instruction.
+
+   It is always safe to ignore these relocations.  They only serve to
+   mark points which the relaxing linker will have to consider.  The
+   assembler must ensure that the correct code is generated even if
+   the relocations are ignored.  In particular, this means that the
+   R_IPR13 relocation may not appear with an external symbol.  */
+
+#define R_IPR13		(0x1d)	/* 13 bit ip-relative branch */
+#define R_ALIGN		(0x1e)  /* alignment marker.  This has no
+				   associated symbol.  Instead, the
+				   r_symndx field indicates the
+				   require alignment at this point in
+				   the file.  It must be a power of 2.  */
+
+#define RELOC struct external_reloc
+#define RELSZ 12
+
diff --git a/binutils-2.25/include/coff/ia64.h b/binutils-2.25/include/coff/ia64.h
new file mode 100644
index 00000000..2ee62686
--- /dev/null
+++ b/binutils-2.25/include/coff/ia64.h
@@ -0,0 +1,89 @@
+/* coff information for HP/Intel IA-64.
+   
+   Copyright 2000, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define DO_NOT_DEFINE_AOUTHDR
+#define L_LNNO_SIZE 2
+#define INCLUDE_COMDAT_FIELDS_IN_AUXENT
+#include "coff/external.h"
+
+#define IA64MAGIC	0x200
+
+#define IA64BADMAG(x)	(((x).f_magic != IA64MAGIC))
+
+/* Bits for f_flags:
+ *	F_RELFLG	relocation info stripped from file
+ *	F_EXEC		file is executable (no unresolved external references)
+ *	F_LNNO		line numbers stripped from file
+ *	F_LSYMS		local symbols stripped from file
+ *	F_AR32WR	file has byte ordering of an AR32WR machine (e.g. vax)
+ */
+
+#define F_RELFLG	(0x0001)
+#define F_EXEC		(0x0002)
+#define F_LNNO		(0x0004)
+#define F_LSYMS		(0x0008)
+
+/********************** AOUT "OPTIONAL HEADER" **********************/
+typedef struct 
+{
+  char 	magic[2];		/* type of file				*/
+  char	vstamp[2];		/* version stamp			*/
+  char	tsize[4];		/* text size in bytes, padded to FW bdry*/
+  char	dsize[4];		/* initialized data "  "		*/
+  char	bsize[4];		/* uninitialized data "   "		*/
+  char	entry[4];		/* entry pt.				*/
+  char 	text_start[4];		/* base of text used for this file	*/
+#ifndef BFD64
+  char 	data_start[4];		/* base of data used for this file	*/
+#endif
+}
+AOUTHDR;
+
+#define PE32MAGIC	0x10b	/* 32-bit image */
+#define PE32PMAGIC	0x20b	/* 32-bit image inside 64-bit address space */
+
+#define PE32PBADMAG(x) (((x).f_magic != PE32PMAGIC))
+
+#define AOUTSZ		108
+#define AOUTHDRSZ	108
+
+#define OMAGIC          0404    /* object files, eg as output */
+#define ZMAGIC          0413    /* demand load format, eg normal ld output */
+#define STMAGIC		0401	/* target shlib */
+#define SHMAGIC		0443	/* host   shlib */
+
+/* define some NT default values */
+/*  #define NT_IMAGE_BASE        0x400000 moved to internal.h */
+#define NT_SECTION_ALIGNMENT 0x1000
+#define NT_FILE_ALIGNMENT    0x200
+#define NT_DEF_RESERVE       0x100000
+#define NT_DEF_COMMIT        0x1000
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 10
+
diff --git a/binutils-2.25/include/coff/internal.h b/binutils-2.25/include/coff/internal.h
new file mode 100644
index 00000000..8b843247
--- /dev/null
+++ b/binutils-2.25/include/coff/internal.h
@@ -0,0 +1,830 @@
+/* Internal format of COFF object file data structures, for GNU BFD.
+   This file is part of BFD, the Binary File Descriptor library.
+   
+   Copyright 1999, 2000, 2001, 2002, 2003, 2004. 2005, 2006, 2007, 2009,
+   2010  Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef GNU_COFF_INTERNAL_H
+#define GNU_COFF_INTERNAL_H 1
+
+/* First, make "signed char" work, even on old compilers. */
+#ifndef signed
+#ifndef __STDC__
+#define	signed			/**/
+#endif
+#endif
+
+/********************** FILE HEADER **********************/
+
+/* extra stuff in a PE header. */
+
+struct internal_extra_pe_filehdr
+{
+  /* DOS header data follows for PE stuff */
+  unsigned short e_magic;	/* Magic number, 0x5a4d */
+  unsigned short e_cblp;	/* Bytes on last page of file, 0x90 */
+  unsigned short e_cp;		/* Pages in file, 0x3 */
+  unsigned short e_crlc;	/* Relocations, 0x0 */
+  unsigned short e_cparhdr;	/* Size of header in paragraphs, 0x4 */
+  unsigned short e_minalloc;	/* Minimum extra paragraphs needed, 0x0 */
+  unsigned short e_maxalloc;	/* Maximum extra paragraphs needed, 0xFFFF */
+  unsigned short e_ss;		/* Initial (relative) SS value, 0x0 */
+  unsigned short e_sp;		/* Initial SP value, 0xb8 */
+  unsigned short e_csum;	/* Checksum, 0x0 */
+  unsigned short e_ip;		/* Initial IP value, 0x0 */
+  unsigned short e_cs;		/* Initial (relative) CS value, 0x0 */
+  unsigned short e_lfarlc;	/* File address of relocation table, 0x40 */
+  unsigned short e_ovno;	/* Overlay number, 0x0 */
+  unsigned short e_res[4];	/* Reserved words, all 0x0 */
+  unsigned short e_oemid;	/* OEM identifier (for e_oeminfo), 0x0 */
+  unsigned short e_oeminfo;	/* OEM information; e_oemid specific, 0x0 */
+  unsigned short e_res2[10];	/* Reserved words, all 0x0 */
+  bfd_vma  e_lfanew;		/* File address of new exe header, 0x80 */
+  unsigned long dos_message[16]; /* text which always follows dos header */
+  bfd_vma  nt_signature;   	/* required NT signature, 0x4550 */ 
+};
+
+#define GO32_STUBSIZE 2048
+
+struct internal_filehdr
+{
+  struct internal_extra_pe_filehdr pe;
+
+  /* coff-stgo32 EXE stub header before BFD tdata has been allocated.
+     Its data is kept in INTERNAL_FILEHDR.GO32STUB afterwards.
+     
+     F_GO32STUB is set iff go32stub contains a valid data.  Artifical headers
+     created in BFD have no pre-set go32stub.  */
+  char go32stub[GO32_STUBSIZE];
+
+  /* Standard coff internal info.  */
+  unsigned short f_magic;	/* magic number			*/
+  unsigned short f_nscns;	/* number of sections		*/
+  long f_timdat;		/* time & date stamp		*/
+  bfd_vma f_symptr;		/* file pointer to symtab	*/
+  long f_nsyms;			/* number of symtab entries	*/
+  unsigned short f_opthdr;	/* sizeof(optional hdr)		*/
+  unsigned short f_flags;	/* flags			*/
+  unsigned short f_target_id;	/* (TI COFF specific)		*/
+};
+
+
+/* Bits for f_flags:
+ 	F_RELFLG	relocation info stripped from file
+ 	F_EXEC		file is executable (no unresolved external references)
+ 	F_LNNO		line numbers stripped from file
+ 	F_LSYMS		local symbols stripped from file
+ 	F_AR16WR	file is 16-bit little-endian
+ 	F_AR32WR	file is 32-bit little-endian
+ 	F_AR32W		file is 32-bit big-endian
+ 	F_DYNLOAD	rs/6000 aix: dynamically loadable w/imports & exports
+ 	F_SHROBJ	rs/6000 aix: file is a shared object
+	F_DLL           PE format DLL
+	F_GO32STUB      Field go32stub contains valid data.  */
+
+#define	F_RELFLG	(0x0001)
+#define	F_EXEC		(0x0002)
+#define	F_LNNO		(0x0004)
+#define	F_LSYMS		(0x0008)
+#define	F_AR16WR	(0x0080)
+#define	F_AR32WR	(0x0100)
+#define	F_AR32W     	(0x0200)
+#define	F_DYNLOAD	(0x1000)
+#define	F_SHROBJ	(0x2000)
+#define F_DLL           (0x2000)
+#define F_GO32STUB      (0x4000)
+
+/* Extra structure which is used in the optional header.  */
+typedef struct _IMAGE_DATA_DIRECTORY 
+{
+  bfd_vma VirtualAddress;
+  long    Size;
+}  IMAGE_DATA_DIRECTORY;
+#define PE_EXPORT_TABLE			0
+#define PE_IMPORT_TABLE			1
+#define PE_RESOURCE_TABLE		2
+#define PE_EXCEPTION_TABLE		3
+#define PE_CERTIFICATE_TABLE		4
+#define PE_BASE_RELOCATION_TABLE	5
+#define PE_DEBUG_DATA			6
+#define PE_ARCHITECTURE			7
+#define PE_GLOBAL_PTR			8
+#define PE_TLS_TABLE			9
+#define PE_LOAD_CONFIG_TABLE		10
+#define PE_BOUND_IMPORT_TABLE		11
+#define PE_IMPORT_ADDRESS_TABLE		12
+#define PE_DELAY_IMPORT_DESCRIPTOR	13
+#define PE_CLR_RUNTIME_HEADER		14
+/* DataDirectory[15] is currently reserved, so no define. */
+#define IMAGE_NUMBEROF_DIRECTORY_ENTRIES  16
+
+/* Default image base for NT.  */
+#define NT_EXE_IMAGE_BASE 0x400000
+#define NT_DLL_IMAGE_BASE 0x10000000
+
+/* Default image base for BeOS. */
+#define BEOS_EXE_IMAGE_BASE 0x80000000
+#define BEOS_DLL_IMAGE_BASE 0x10000000
+
+/* Extra stuff in a PE aouthdr */
+
+#define PE_DEF_SECTION_ALIGNMENT 0x1000
+#ifndef PE_DEF_FILE_ALIGNMENT
+# define PE_DEF_FILE_ALIGNMENT 0x200
+#endif
+
+struct internal_extra_pe_aouthdr 
+{
+  /* FIXME: The following entries are in AOUTHDR.  But they aren't
+     available internally in bfd.  We add them here so that objdump
+     can dump them.  */
+  /* The state of the image file  */
+  short Magic;
+  /* Linker major version number */
+  char MajorLinkerVersion;
+  /* Linker minor version number  */
+  char MinorLinkerVersion;	
+  /* Total size of all code sections  */
+  long SizeOfCode;
+  /* Total size of all initialized data sections  */
+  long SizeOfInitializedData;
+  /* Total size of all uninitialized data sections  */
+  long SizeOfUninitializedData;
+  /* Address of entry point relative to image base.  */
+  bfd_vma AddressOfEntryPoint;
+  /* Address of the first code section relative to image base.  */
+  bfd_vma BaseOfCode;
+  /* Address of the first data section relative to image base.  */
+  bfd_vma BaseOfData;
+ 
+  /* PE stuff  */
+  bfd_vma ImageBase;		/* address of specific location in memory that
+				   file is located, NT default 0x10000 */
+
+  bfd_vma SectionAlignment;	/* section alignment default 0x1000 */
+  bfd_vma FileAlignment;	/* file alignment default 0x200 */
+  short   MajorOperatingSystemVersion; /* minimum version of the operating */
+  short   MinorOperatingSystemVersion; /* system req'd for exe, default to 1*/
+  short   MajorImageVersion;	/* user defineable field to store version of */
+  short   MinorImageVersion;	/* exe or dll being created, default to 0 */ 
+  short   MajorSubsystemVersion; /* minimum subsystem version required to */
+  short   MinorSubsystemVersion; /* run exe; default to 3.1 */
+  long    Reserved1;		/* seems to be 0 */
+  long    SizeOfImage;		/* size of memory to allocate for prog */
+  long    SizeOfHeaders;	/* size of PE header and section table */
+  long    CheckSum;		/* set to 0 */
+  short   Subsystem;	
+
+  /* type of subsystem exe uses for user interface,
+     possible values:
+     1 - NATIVE   Doesn't require a subsystem
+     2 - WINDOWS_GUI runs in Windows GUI subsystem
+     3 - WINDOWS_CUI runs in Windows char sub. (console app)
+     5 - OS2_CUI runs in OS/2 character subsystem
+     7 - POSIX_CUI runs in Posix character subsystem */
+  unsigned short DllCharacteristics; /* flags for DLL init  */
+  bfd_vma SizeOfStackReserve;	/* amount of memory to reserve  */
+  bfd_vma SizeOfStackCommit;	/* amount of memory initially committed for 
+				   initial thread's stack, default is 0x1000 */
+  bfd_vma SizeOfHeapReserve;	/* amount of virtual memory to reserve and */
+  bfd_vma SizeOfHeapCommit;	/* commit, don't know what to defaut it to */
+  long    LoaderFlags;		/* can probably set to 0 */
+  long    NumberOfRvaAndSizes;	/* number of entries in next entry, 16 */
+  IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES];
+};
+
+/********************** AOUT "OPTIONAL HEADER" **********************/
+struct internal_aouthdr
+{
+  short magic;			/* type of file				*/
+  short vstamp;			/* version stamp			*/
+  bfd_vma tsize;		/* text size in bytes, padded to FW bdry*/
+  bfd_vma dsize;		/* initialized data "  "		*/
+  bfd_vma bsize;		/* uninitialized data "   "		*/
+  bfd_vma entry;		/* entry pt.				*/
+  bfd_vma text_start;		/* base of text used for this file */
+  bfd_vma data_start;		/* base of data used for this file */
+
+  /* i960 stuff */
+  unsigned long tagentries;	/* number of tag entries to follow */
+
+  /* RS/6000 stuff */
+  bfd_vma o_toc;		/* address of TOC			*/
+  short o_snentry;		/* section number for entry point */
+  short o_sntext;		/* section number for text	*/
+  short o_sndata;		/* section number for data	*/
+  short o_sntoc;		/* section number for toc	*/
+  short o_snloader;		/* section number for loader section */
+  short o_snbss;		/* section number for bss	*/
+  short o_algntext;		/* max alignment for text	*/
+  short o_algndata;		/* max alignment for data	*/
+  short o_modtype;		/* Module type field, 1R,RE,RO	*/
+  short o_cputype;		/* Encoded CPU type		*/
+  bfd_vma o_maxstack;	/* max stack size allowed.	*/
+  bfd_vma o_maxdata;	/* max data size allowed.	*/
+
+  /* ECOFF stuff */
+  bfd_vma bss_start;		/* Base of bss section.		*/
+  bfd_vma gp_value;		/* GP register value.		*/
+  unsigned long gprmask;	/* General registers used.	*/
+  unsigned long cprmask[4];	/* Coprocessor registers used.	*/
+  unsigned long fprmask;	/* Floating pointer registers used.  */
+
+  /* Apollo stuff */
+  long o_inlib;			/* inlib data */
+  long o_sri;			/* Static Resource Information */
+  long vid[2];			/* Version id */
+
+  struct internal_extra_pe_aouthdr pe;
+};
+
+/********************** STORAGE CLASSES **********************/
+
+/* This used to be defined as -1, but now n_sclass is unsigned.  */
+#define C_EFCN		0xff	/* physical end of function	*/
+#define C_NULL		0
+#define C_AUTO		1	/* automatic variable		*/
+#define C_EXT		2	/* external symbol		*/
+#define C_STAT		3	/* static			*/
+#define C_REG		4	/* register variable		*/
+#define C_EXTDEF	5	/* external definition		*/
+#define C_LABEL		6	/* label			*/
+#define C_ULABEL	7	/* undefined label		*/
+#define C_MOS		8	/* member of structure		*/
+#define C_ARG		9	/* function argument		*/
+#define C_STRTAG	10	/* structure tag		*/
+#define C_MOU		11	/* member of union		*/
+#define C_UNTAG		12	/* union tag			*/
+#define C_TPDEF		13	/* type definition		*/
+#define C_USTATIC	14	/* undefined static		*/
+#define C_ENTAG		15	/* enumeration tag		*/
+#define C_MOE		16	/* member of enumeration	*/
+#define C_REGPARM	17	/* register parameter		*/
+#define C_FIELD		18	/* bit field			*/
+#define C_AUTOARG	19	/* auto argument		*/
+#define C_LASTENT	20	/* dummy entry (end of block)	*/
+#define C_BLOCK		100	/* ".bb" or ".eb"		*/
+#define C_FCN		101	/* ".bf" or ".ef"		*/
+#define C_EOS		102	/* end of structure		*/
+#define C_FILE		103	/* file name			*/
+#define C_LINE		104	/* line # reformatted as symbol table entry */
+#define C_ALIAS	 	105	/* duplicate tag		*/
+#define C_HIDDEN	106	/* ext symbol in dmert public lib */
+#define C_WEAKEXT	127	/* weak symbol -- GNU extension.  */
+
+/* New storage classes for TI COFF */
+#define C_UEXT		19	/* Tentative external definition */
+#define C_STATLAB	20	/* Static load time label */
+#define C_EXTLAB	21	/* External load time label */
+#define C_SYSTEM	23	/* System Wide variable */
+
+/* New storage classes for WINDOWS_NT   */
+#define C_SECTION       104     /* section name */
+#define C_NT_WEAK	105	/* weak external */
+
+ /* New storage classes for 80960 */
+
+/* C_LEAFPROC is obsolete.  Use C_LEAFEXT or C_LEAFSTAT */
+#define C_LEAFPROC	108	/* Leaf procedure, "call" via BAL */
+
+#define C_SCALL		107	/* Procedure reachable via system call */
+#define C_LEAFEXT       108	/* External leaf */
+#define C_LEAFSTAT      113	/* Static leaf */
+#define C_OPTVAR	109	/* Optimized variable		*/
+#define C_DEFINE	110	/* Preprocessor #define		*/
+#define C_PRAGMA	111	/* Advice to compiler or linker	*/
+#define C_SEGMENT	112	/* 80960 segment name		*/
+
+  /* Storage classes for m88k */
+#define C_SHADOW        107     /* shadow symbol                */
+#define C_VERSION       108     /* coff version symbol          */
+
+ /* New storage classes for RS/6000 */
+#define C_HIDEXT        107	/* Un-named external symbol */
+#define C_BINCL         108	/* Marks beginning of include file */
+#define C_EINCL         109	/* Marks ending of include file */
+#define C_AIX_WEAKEXT   111	/* AIX definition of C_WEAKEXT.  */
+
+#define C_NULL_VALUE	0x00de1e00    /* Value for a C_NULL deleted entry.  */
+
+#if defined _AIX52 || defined AIX_WEAK_SUPPORT
+#undef C_WEAKEXT
+#define C_WEAKEXT       C_AIX_WEAKEXT
+#endif
+
+ /* storage classes for stab symbols for RS/6000 */
+#define C_GSYM          (0x80)
+#define C_LSYM          (0x81)
+#define C_PSYM          (0x82)
+#define C_RSYM          (0x83)
+#define C_RPSYM         (0x84)
+#define C_STSYM         (0x85)
+#define C_TCSYM         (0x86)
+#define C_BCOMM         (0x87)
+#define C_ECOML         (0x88)
+#define C_ECOMM         (0x89)
+#define C_DECL          (0x8c)
+#define C_ENTRY         (0x8d)
+#define C_FUN           (0x8e)
+#define C_BSTAT         (0x8f)
+#define C_ESTAT         (0x90)
+#define C_GTLS          (0x97)
+#define C_STTLS         (0x98)
+
+/* Storage classes for Thumb symbols */
+#define C_THUMBEXT      (128 + C_EXT)		/* 130 */
+#define C_THUMBSTAT     (128 + C_STAT)		/* 131 */
+#define C_THUMBLABEL    (128 + C_LABEL)		/* 134 */
+#define C_THUMBEXTFUNC  (C_THUMBEXT  + 20)	/* 150 */
+#define C_THUMBSTATFUNC (C_THUMBSTAT + 20)	/* 151 */
+
+/* True if XCOFF symbols of class CLASS have auxillary csect information.  */
+#define CSECT_SYM_P(CLASS) \
+  ((CLASS) == C_EXT || (CLASS) == C_AIX_WEAKEXT || (CLASS) == C_HIDEXT)
+
+/********************** SECTION HEADER **********************/
+
+#define SCNNMLEN (8)
+
+struct internal_scnhdr
+{
+  char s_name[SCNNMLEN];	/* section name			*/
+
+  /* Physical address, aliased s_nlib.
+     In the pei format, this field is the virtual section size
+     (the size of the section after being loaded int memory),
+     NOT the physical address.  */
+  bfd_vma s_paddr;
+
+  bfd_vma s_vaddr;		/* virtual address		*/
+  bfd_vma s_size;		/* section size			*/
+  bfd_vma s_scnptr;		/* file ptr to raw data for section */
+  bfd_vma s_relptr;		/* file ptr to relocation	*/
+  bfd_vma s_lnnoptr;		/* file ptr to line numbers	*/
+  unsigned long s_nreloc;	/* number of relocation entries	*/
+  unsigned long s_nlnno;	/* number of line number entries*/
+  long s_flags;			/* flags			*/
+  long s_align;			/* used on I960			*/
+  unsigned char s_page;         /* TI COFF load page            */
+};
+
+/* s_flags "type".  */
+#define STYP_REG	 (0x0000)	/* "regular": allocated, relocated, loaded */
+#define STYP_DSECT	 (0x0001)	/* "dummy":  relocated only*/
+#define STYP_NOLOAD	 (0x0002)	/* "noload": allocated, relocated, not loaded */
+#define STYP_GROUP	 (0x0004)	/* "grouped": formed of input sections */
+#define STYP_PAD	 (0x0008)	/* "padding": not allocated, not relocated, loaded */
+#define STYP_COPY	 (0x0010)	/* "copy": for decision function used by field update;  not allocated, not relocated,
+									     loaded; reloc & lineno entries processed normally */
+#define STYP_TEXT	 (0x0020)	/* section contains text only */
+#define S_SHRSEG	 (0x0020)	/* In 3b Update files (output of ogen), sections which appear in SHARED segments of the Pfile
+									     will have the S_SHRSEG flag set by ogen, to inform dufr that updating 1 copy of the proc. will
+									     update all process invocations. */
+#define STYP_DATA	 (0x0040)	/* section contains data only */
+#define STYP_BSS	 (0x0080)	/* section contains bss only */
+#define S_NEWFCN	 (0x0100)	/* In a minimal file or an update file, a new function (as compared with a replaced function) */
+#define STYP_INFO	 (0x0200)	/* comment: not allocated not relocated, not loaded */
+#define STYP_OVER	 (0x0400)	/* overlay: relocated not allocated or loaded */
+#define STYP_LIB	 (0x0800)	/* for .lib: same as INFO */
+#define STYP_MERGE	 (0x2000)	/* merge section -- combines with text, data or bss sections only */
+#define STYP_REVERSE_PAD (0x4000)	/* section will be padded with no-op instructions
+					   wherever padding is necessary and there is a
+					   word of contiguous bytes beginning on a word
+					   boundary. */
+
+#define STYP_LIT	0x8020	/* Literal data (like STYP_TEXT) */
+
+
+/********************** LINE NUMBERS **********************/
+
+/* 1 line number entry for every "breakpointable" source line in a section.
+   Line numbers are grouped on a per function basis; first entry in a function
+   grouping will have l_lnno = 0 and in place of physical address will be the
+   symbol table index of the function name.  */
+
+struct internal_lineno
+{
+  union
+  {
+    bfd_signed_vma l_symndx;		/* function name symbol index, iff l_lnno == 0*/
+    bfd_signed_vma l_paddr;		/* (physical) address of line number	*/
+  }     l_addr;
+  unsigned long l_lnno;		/* line number		*/
+};
+
+/********************** SYMBOLS **********************/
+
+#define SYMNMLEN	8	/* # characters in a symbol name	*/
+#define FILNMLEN	14	/* # characters in a file name		*/
+#define DIMNUM		4	/* # array dimensions in auxiliary entry */
+
+struct internal_syment
+{
+  union
+  {
+    char _n_name[SYMNMLEN];	/* old COFF version		*/
+    struct
+    {
+      bfd_hostptr_t _n_zeroes;	/* new == 0			*/
+      bfd_hostptr_t _n_offset;	/* offset into string table	*/
+    }      _n_n;
+    char *_n_nptr[2];		/* allows for overlaying	*/
+  }     _n;
+  bfd_vma n_value;		/* value of symbol		*/
+  short n_scnum;		/* section number		*/
+  unsigned short n_flags;	/* copy of flags from filhdr	*/
+  unsigned short n_type;	/* type and derived type	*/
+  unsigned char n_sclass;	/* storage class		*/
+  unsigned char n_numaux;	/* number of aux. entries	*/
+};
+
+#define n_name		_n._n_name
+#define n_zeroes	_n._n_n._n_zeroes
+#define n_offset	_n._n_n._n_offset
+
+/* Relocatable symbols have number of the section in which they are defined,
+   or one of the following:  */
+
+#define N_UNDEF	((short)0)	/* undefined symbol */
+#define N_ABS	((short)-1)	/* value of symbol is absolute */
+#define N_DEBUG	((short)-2)	/* debugging symbol -- value is meaningless */
+#define N_TV	((short)-3)	/* indicates symbol needs preload transfer vector */
+#define P_TV	((short)-4)	/* indicates symbol needs postload transfer vector*/
+
+/* Type of a symbol, in low N bits of the word.  */
+
+#define T_NULL		0
+#define T_VOID		1	/* function argument (only used by compiler) */
+#define T_CHAR		2	/* character		*/
+#define T_SHORT		3	/* short integer	*/
+#define T_INT		4	/* integer		*/
+#define T_LONG		5	/* long integer		*/
+#define T_FLOAT		6	/* floating point	*/
+#define T_DOUBLE	7	/* double word		*/
+#define T_STRUCT	8	/* structure 		*/
+#define T_UNION		9	/* union 		*/
+#define T_ENUM		10	/* enumeration 		*/
+#define T_MOE		11	/* member of enumeration*/
+#define T_UCHAR		12	/* unsigned character	*/
+#define T_USHORT	13	/* unsigned short	*/
+#define T_UINT		14	/* unsigned integer	*/
+#define T_ULONG		15	/* unsigned long	*/
+#define T_LNGDBL	16	/* long double		*/
+
+/* Derived types, in n_type.  */
+
+#define DT_NON		(0)	/* no derived type */
+#define DT_PTR		(1)	/* pointer */
+#define DT_FCN		(2)	/* function */
+#define DT_ARY		(3)	/* array */
+
+#define BTYPE(x)	((x) & N_BTMASK)
+#define DTYPE(x)	(((x) & N_TMASK) >> N_BTSHFT)
+
+#define ISPTR(x) \
+  (((unsigned long) (x) & N_TMASK) == ((unsigned long) DT_PTR << N_BTSHFT))
+#define ISFCN(x) \
+  (((unsigned long) (x) & N_TMASK) == ((unsigned long) DT_FCN << N_BTSHFT))
+#define ISARY(x) \
+  (((unsigned long) (x) & N_TMASK) == ((unsigned long) DT_ARY << N_BTSHFT))
+#define ISTAG(x) \
+  ((x) == C_STRTAG || (x) == C_UNTAG || (x) == C_ENTAG)
+#define DECREF(x) \
+  ((((x) >> N_TSHIFT) & ~ N_BTMASK) | ((x) & N_BTMASK))
+
+union internal_auxent
+{
+  struct
+  {
+
+    union
+    {
+      long l;			/* str, un, or enum tag indx */
+      struct coff_ptr_struct *p;
+    }     x_tagndx;
+
+    union
+    {
+      struct
+      {
+	unsigned short x_lnno;	/* declaration line number */
+	unsigned short x_size;	/* str/union/array size */
+      }      x_lnsz;
+      long x_fsize;		/* size of function */
+    }     x_misc;
+
+    union
+    {
+      struct
+      {				/* if ISFCN, tag, or .bb */
+	bfd_signed_vma x_lnnoptr;		/* ptr to fcn line # */
+	union
+	{			/* entry ndx past block end */
+	  long l;
+	  struct coff_ptr_struct *p;
+	}     x_endndx;
+      }      x_fcn;
+
+      struct
+      {				/* if ISARY, up to 4 dimen. */
+	unsigned short x_dimen[DIMNUM];
+      }      x_ary;
+    }     x_fcnary;
+
+    unsigned short x_tvndx;	/* tv index */
+  }      x_sym;
+
+  union
+  {
+    char x_fname[FILNMLEN];
+    struct
+    {
+      long x_zeroes;
+      long x_offset;
+    }      x_n;
+  }     x_file;
+
+  struct
+  {
+    long x_scnlen;		/* section length */
+    unsigned short x_nreloc;	/* # relocation entries */
+    unsigned short x_nlinno;	/* # line numbers */
+    unsigned long x_checksum;	/* section COMDAT checksum for PE */
+    unsigned short x_associated; /* COMDAT associated section index for PE */
+    unsigned char x_comdat;	/* COMDAT selection number for PE */
+  }      x_scn;
+
+  struct
+  {
+    long x_tvfill;		/* tv fill value */
+    unsigned short x_tvlen;	/* length of .tv */
+    unsigned short x_tvran[2];	/* tv range */
+  }      x_tv;			/* info about .tv section (in auxent of symbol .tv)) */
+
+  /******************************************
+   * RS/6000-specific auxent - last auxent for every external symbol
+   ******************************************/
+  struct
+  {
+    union
+      {				/* csect length or enclosing csect */
+	bfd_signed_vma l;
+	struct coff_ptr_struct *p;
+      } x_scnlen;
+    long x_parmhash;		/* parm type hash index */
+    unsigned short x_snhash;	/* sect num with parm hash */
+    unsigned char x_smtyp;	/* symbol align and type */
+    /* 0-4 - Log 2 of alignment */
+    /* 5-7 - symbol type */
+    unsigned char x_smclas;	/* storage mapping class */
+    long x_stab;		/* dbx stab info index */
+    unsigned short x_snstab;	/* sect num with dbx stab */
+  }      x_csect;		/* csect definition information */
+
+/* x_smtyp values:  */
+
+#define	SMTYP_ALIGN(x)	((x) >> 3)	/* log2 of alignment */
+#define	SMTYP_SMTYP(x)	((x) & 0x7)	/* symbol type */
+/* Symbol type values:  */
+#define	XTY_ER	0		/* External reference */
+#define	XTY_SD	1		/* Csect definition */
+#define	XTY_LD	2		/* Label definition */
+#define XTY_CM	3		/* .BSS */
+#define	XTY_EM	4		/* Error message */
+#define	XTY_US	5		/* "Reserved for internal use" */
+
+/* x_smclas values:  */
+
+#define	XMC_PR	0		/* Read-only program code */
+#define	XMC_RO	1		/* Read-only constant */
+#define	XMC_DB	2		/* Read-only debug dictionary table */
+#define	XMC_TC	3		/* Read-write general TOC entry */
+#define	XMC_UA	4		/* Read-write unclassified */
+#define	XMC_RW	5		/* Read-write data */
+#define	XMC_GL	6		/* Read-only global linkage */
+#define	XMC_XO	7		/* Read-only extended operation */
+#define	XMC_SV	8		/* Read-only supervisor call */
+#define	XMC_BS	9		/* Read-write BSS */
+#define	XMC_DS	10		/* Read-write descriptor csect */
+#define	XMC_UC	11		/* Read-write unnamed Fortran common */
+#define	XMC_TI	12		/* Read-only traceback index csect */
+#define	XMC_TB	13		/* Read-only traceback table csect */
+/* 		14	??? */
+#define	XMC_TC0	15		/* Read-write TOC anchor */
+#define XMC_TD	16		/* Read-write data in TOC */
+
+  /******************************************
+   *  I960-specific *2nd* aux. entry formats
+   ******************************************/
+  struct
+  {
+    /* This is a very old typo that keeps getting propagated. */
+#define x_stdindx x_stindx
+    long x_stindx;		/* sys. table entry */
+  }      x_sc;			/* system call entry */
+
+  struct
+  {
+    unsigned long x_balntry;	/* BAL entry point */
+  }      x_bal;			/* BAL-callable function */
+
+  struct
+  {
+    unsigned long x_timestamp;	/* time stamp */
+    char x_idstring[20];	/* producer identity string */
+  }      x_ident;		/* Producer ident info */
+
+};
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+struct internal_reloc
+{
+  bfd_vma r_vaddr;		/* Virtual address of reference */
+  long r_symndx;		/* Index into symbol table	*/
+  unsigned short r_type;	/* Relocation type		*/
+  unsigned char r_size;		/* Used by RS/6000 and ECOFF	*/
+  unsigned char r_extern;	/* Used by ECOFF		*/
+  unsigned long r_offset;	/* Used by Alpha ECOFF, SPARC, others */
+};
+
+/* X86-64 relocations.  */
+#define R_AMD64_ABS 		 0 /* Reference is absolute, no relocation is necessary.  */
+#define R_AMD64_DIR64		 1 /* 64-bit address (VA).  */
+#define R_AMD64_DIR32		 2 /* 32-bit address (VA) R_DIR32.  */
+#define R_AMD64_IMAGEBASE	 3 /* 32-bit absolute ref w/o base R_IMAGEBASE.  */
+#define R_AMD64_PCRLONG		 4 /* 32-bit relative address from byte following reloc R_PCRLONG.  */
+#define R_AMD64_PCRLONG_1	 5 /* 32-bit relative address from byte distance 1 from reloc.  */
+#define R_AMD64_PCRLONG_2	 6 /* 32-bit relative address from byte distance 2 from reloc.  */
+#define R_AMD64_PCRLONG_3	 7 /* 32-bit relative address from byte distance 3 from reloc.  */
+#define R_AMD64_PCRLONG_4	 8 /* 32-bit relative address from byte distance 4 from reloc.  */
+#define R_AMD64_PCRLONG_5	 9 /* 32-bit relative address from byte distance 5 from reloc.  */
+#define R_AMD64_SECTION		10 /* Section index.  */
+#define R_AMD64_SECREL		11 /* 32 bit offset from base of section containing target R_SECREL.  */
+#define R_AMD64_SECREL7		12 /* 7 bit unsigned offset from base of section containing target.  */
+#define R_AMD64_TOKEN		13 /* 32 bit metadata token.  */
+#define R_AMD64_PCRQUAD		14 /* Pseude PC64 relocation - Note: not specified by MS/AMD but need for gas pc-relative 64bit wide relocation generated by ELF.  */
+
+/* i386 Relocations.  */
+
+#define R_DIR16 	 1
+#define R_REL24          5
+#define R_DIR32 	 6
+#define R_IMAGEBASE	 7
+#define R_SECREL32	11
+#define R_RELBYTE	15
+#define R_RELWORD	16
+#define R_RELLONG	17
+#define R_PCRBYTE	18
+#define R_PCRWORD	19
+#define R_PCRLONG	20
+#define R_PCR24         21
+#define R_IPRSHORT	24
+#define R_IPRLONG	26
+#define R_GETSEG	29
+#define R_GETPA 	30
+#define R_TAGWORD	31
+#define R_JUMPTARG	32	/* strange 29k 00xx00xx reloc */
+#define R_PARTLS16      32
+#define R_PARTMS8       33
+
+#define R_PCR16L       128
+#define R_PCR26L       129
+#define R_VRT16        130
+#define R_HVRT16       131
+#define R_LVRT16       132
+#define R_VRT32        133
+
+
+/* This reloc identifies mov.b instructions with a 16bit absolute
+   address.  The linker tries to turn insns with this reloc into
+   an absolute 8-bit address.  */
+#define R_MOV16B1    	0x41
+
+/* This reloc identifies mov.b instructions which had a 16bit
+   absolute address which have been shortened into a 8-bit
+   absolute address.  */
+#define R_MOV16B2 	0x42
+
+/* This reloc identifies jmp insns with a 16bit target address;
+   the linker tries to turn these insns into bra insns with
+   an 8bit pc-relative target.  */
+#define R_JMP1     	0x43
+
+/* This reloc identifies a bra with an 8-bit pc-relative
+   target that was formerly a jmp insn with a 16bit target.  */
+#define R_JMP2 		0x44
+
+/* ??? */
+#define R_RELLONG_NEG  	0x45
+
+/* This reloc identifies jmp insns with a 24bit target address;
+   the linker tries to turn these insns into bra insns with
+   an 8bit pc-relative target.  */
+#define R_JMPL1     	0x46
+
+/* This reloc identifies a bra with an 8-bit pc-relative
+   target that was formerly a jmp insn with a 24bit target.  */
+#define R_JMPL2		0x47
+
+/* This reloc identifies mov.b instructions with a 24bit absolute
+   address.  The linker tries to turn insns with this reloc into
+   an absolute 8-bit address.  */
+
+#define R_MOV24B1    	0x48
+
+/* This reloc identifies mov.b instructions which had a 24bit
+   absolute address which have been shortened into a 8-bit
+   absolute address.  */
+#define R_MOV24B2 	0x49
+
+/* An h8300 memory indirect jump/call.  Forces the address of the jump/call
+   target into the function vector (in page zero), and the address of the
+   vector entry to be placed in the jump/call instruction.  */
+#define R_MEM_INDIRECT	0x4a
+
+/* This reloc identifies a 16bit pc-relative branch target which was
+   shortened into an 8bit pc-relative branch target.  */
+#define R_PCRWORD_B	0x4b
+
+/* This reloc identifies mov.[wl] instructions with a 32/24 bit
+   absolute address; the linker may turn this into a mov.[wl]
+   insn with a 16bit absolute address.  */
+#define R_MOVL1    	0x4c
+
+/* This reloc identifies mov.[wl] insns which formerly had
+   a 32/24bit absolute address and now have a 16bit absolute address.  */
+#define R_MOVL2 	0x4d
+
+/* This reloc identifies a bCC:8 which will have it's condition
+   inverted and its target redirected to the target of the branch
+   in the following insn.  */
+#define R_BCC_INV	0x4e
+
+/* This reloc identifies a jmp instruction that has been deleted.  */
+#define R_JMP_DEL	0x4f
+
+/* Z8k modes */
+#define R_IMM16   0x01		/* 16 bit abs */
+#define R_JR	  0x02		/* jr  8 bit disp */
+#define R_IMM4L   0x23		/* low nibble */
+#define R_IMM8    0x22		/* 8 bit abs */
+#define R_IMM32   R_RELLONG	/* 32 bit abs */
+#define R_CALL    R_DA		/* Absolute address which could be a callr */
+#define R_JP	  R_DA		/* Absolute address which could be a jp */
+#define R_REL16   0x04		/* 16 bit PC rel */
+#define R_CALLR	  0x05		/* callr 12 bit disp */
+#define R_SEG     0x10		/* set if in segmented mode */
+#define R_IMM4H   0x24		/* high nibble */
+#define R_DISP7   0x25          /* djnz displacement */
+
+/* Z80 modes */
+#define R_OFF8    0x32		/* 8 bit signed abs, for (i[xy]+d) */
+#define R_IMM24   0x33          /* 24 bit abs */
+/* R_JR, R_IMM8, R_IMM16, R_IMM32 - as for Z8k */
+
+/* H8500 modes */
+
+#define R_H8500_IMM8  	1		/*  8 bit immediate 	*/
+#define R_H8500_IMM16 	2		/* 16 bit immediate	*/
+#define R_H8500_PCREL8 	3		/*  8 bit pcrel 	*/
+#define R_H8500_PCREL16 4		/* 16 bit pcrel 	*/
+#define R_H8500_HIGH8  	5		/* high 8 bits of 24 bit address */
+#define R_H8500_LOW16 	7		/* low 16 bits of 24 bit immediate */
+#define R_H8500_IMM24	6		/* 24 bit immediate */
+#define R_H8500_IMM32   8               /* 32 bit immediate */
+#define R_H8500_HIGH16  9		/* high 16 bits of 32 bit immediate */
+
+/* W65 modes */
+
+#define R_W65_ABS8	1  /* addr & 0xff 		*/
+#define R_W65_ABS16	2  /* addr & 0xffff 		*/
+#define R_W65_ABS24	3  /* addr & 0xffffff 		*/
+
+#define R_W65_ABS8S8    4  /* (addr >> 8) & 0xff 	*/
+#define R_W65_ABS8S16   5  /* (addr >> 16) & 0xff 	*/
+
+#define R_W65_ABS16S8   6  /* (addr >> 8) & 0ffff 	*/
+#define R_W65_ABS16S16  7  /* (addr >> 16) & 0ffff 	*/
+
+#define R_W65_PCR8	8
+#define R_W65_PCR16	9
+
+#define R_W65_DP       10  /* direct page 8 bits only   */
+
+#endif /* GNU_COFF_INTERNAL_H */
diff --git a/binutils-2.25/include/coff/m68k.h b/binutils-2.25/include/coff/m68k.h
new file mode 100644
index 00000000..c00c5a94
--- /dev/null
+++ b/binutils-2.25/include/coff/m68k.h
@@ -0,0 +1,82 @@
+/* coff information for M68K
+   
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef GNU_COFF_M68K_H
+#define GNU_COFF_M68K_H 1
+
+#define L_LNNO_SIZE 2
+#include "coff/external.h"
+
+/* Motorola 68000/68008/68010/68020 */
+#define	MC68MAGIC	0520
+#define MC68KWRMAGIC	0520	/* writeable text segments */
+#define	MC68TVMAGIC	0521
+#define MC68KROMAGIC	0521	/* readonly shareable text segments */
+#define MC68KPGMAGIC	0522	/* demand paged text segments */
+#define	M68MAGIC	0210
+#define	M68TVMAGIC	0211
+
+/* This is the magic of the Bull dpx/2 */
+#define MC68KBCSMAGIC	0526
+
+/* This is Lynx's all-platform magic number for executables. */
+
+#define LYNXCOFFMAGIC	0415
+
+#define OMAGIC M68MAGIC
+
+/* This intentionally does not include MC68KBCSMAGIC; it only includes
+   magic numbers which imply that names do not have underscores.  */
+#define M68KBADMAG(x) (((x).f_magic != MC68MAGIC) \
+                    && ((x).f_magic != MC68KWRMAGIC) \
+                    && ((x).f_magic != MC68TVMAGIC) \
+                    && ((x).f_magic != MC68KROMAGIC) \
+                    && ((x).f_magic != MC68KPGMAGIC) \
+                    && ((x).f_magic != M68MAGIC) \
+                    && ((x).f_magic != M68TVMAGIC) \
+                    && ((x).f_magic != LYNXCOFFMAGIC))
+
+/* Magic numbers for the a.out header.  */
+
+#define PAGEMAGICEXECSWAPPED  0407 /* executable (swapped) */
+#define PAGEMAGICPEXECSWAPPED 0410 /* pure executable (swapped) */
+#define PAGEMAGICPEXECTSHLIB  0443 /* pure executable (target shared library) */
+#define PAGEMAGICPEXECPAGED   0413 /* pure executable (paged) */
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+#ifdef M68K_COFF_OFFSET
+  char r_offset[4];
+#endif
+};
+
+#define RELOC struct external_reloc
+
+#ifdef M68K_COFF_OFFSET
+#define RELSZ 14
+#else
+#define RELSZ 10
+#endif
+
+#endif /* GNU_COFF_M68K_H */
diff --git a/binutils-2.25/include/coff/m88k.h b/binutils-2.25/include/coff/m88k.h
new file mode 100644
index 00000000..8e1b3c93
--- /dev/null
+++ b/binutils-2.25/include/coff/m88k.h
@@ -0,0 +1,197 @@
+/* coff information for 88k bcs
+   
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define DO_NOT_DEFINE_SCNHDR
+#define L_LNNO_SIZE 4
+#define DO_NOT_DEFINE_SYMENT
+#define DO_NOT_DEFINE_AUXENT
+#include "coff/external.h"
+
+#define MC88MAGIC  0540           /* 88k BCS executable */
+#define MC88DMAGIC 0541           /* DG/UX executable   */
+#define MC88OMAGIC 0555	          /* Object file        */
+
+#define MC88BADMAG(x) (((x).f_magic != MC88MAGIC) \
+                    && ((x).f_magic != MC88DMAGIC) \
+                    && ((x).f_magic != MC88OMAGIC))
+
+#define PAGEMAGIC3   0414 /* Split i&d, zero mapped */
+#define PAGEMAGICBCS 0413
+
+/********************** SECTION HEADER **********************/
+
+struct external_scnhdr 
+{
+  char		s_name[8];	/* section name			*/
+  char		s_paddr[4];	/* physical address, aliased s_nlib */
+  char		s_vaddr[4];	/* virtual address		*/
+  char		s_size[4];	/* section size			*/
+  char		s_scnptr[4];	/* file ptr to raw data for section */
+  char		s_relptr[4];	/* file ptr to relocation	*/
+  char		s_lnnoptr[4];	/* file ptr to line numbers	*/
+  char		s_nreloc[4];	/* number of relocation entries	*/
+  char		s_nlnno[4];	/* number of line number entries*/
+  char		s_flags[4];	/* flags			*/
+};
+
+#define	SCNHDR	struct external_scnhdr
+#define	SCNHSZ	44
+
+/* Names of "special" sections.  */
+#define _TEXT   ".text"
+#define _DATA   ".data"
+#define _BSS    ".bss"
+#define _COMMENT ".comment"
+
+
+/********************** SYMBOLS **********************/
+
+#define E_SYMNMLEN	8	/* # characters in a symbol name	*/
+#define E_FILNMLEN	14	/* # characters in a file name		*/
+#define E_DIMNUM	4	/* # array dimensions in auxiliary entry */
+
+struct external_syment 
+{
+  union
+  {
+    char e_name[E_SYMNMLEN];
+
+    struct
+    {
+      char e_zeroes[4];
+      char e_offset[4];
+    } e;
+
+  } e;
+
+  char e_value[4];
+  char e_scnum[2];
+  char e_type[2];
+  char e_sclass[1];
+  char e_numaux[1];
+  char pad2[2];
+};
+
+#define N_BTMASK	017
+#define N_TMASK		060
+#define N_BTSHFT	4
+#define N_TSHIFT	2
+
+/* Note that this isn't the same shape as other coffs */
+union external_auxent
+{
+  struct
+  {
+    char x_tagndx[4];		/* str, un, or enum tag indx */
+    /* 4 */
+    
+    union
+    {
+      char x_fsize[4];		/* size of function */
+
+      struct
+      {
+	char  x_lnno[4];	/* declaration line number */
+	char  x_size[4];	/* str/union/array size */
+      } x_lnsz;
+
+    } x_misc;
+    
+    /* 12 */
+    union
+    {
+      struct 			/* if ISFCN, tag, or .bb */
+      {
+	char x_lnnoptr[4];	/* ptr to fcn line # */
+	char x_endndx[4];		/* entry ndx past block end */
+      } x_fcn;
+
+      struct 			/* if ISARY, up to 4 dimen. */
+      {
+	char x_dimen[E_DIMNUM][2];
+      } x_ary;
+
+    } x_fcnary;
+    /* 20 */
+    
+  } x_sym;
+  
+  union
+  {
+    char x_fname[E_FILNMLEN];
+
+    struct
+    {
+      char x_zeroes[4];
+      char x_offset[4];
+    } x_n;
+
+  } x_file;
+  
+  struct
+  {
+    char x_scnlen[4];		/* section length */
+    char x_nreloc[4];		/* # relocation entries */
+    char x_nlinno[4];		/* # line numbers */
+  } x_scn;
+  
+  struct
+  {
+    char x_tvfill[4];		/* tv fill value */
+    char x_tvlen[2];		/* length of .tv */
+    char x_tvran[2][2];		/* tv range */
+  } x_tv;			/* info about .tv section (in auxent of symbol .tv)) */
+};
+
+#define GET_LNSZ_SIZE(abfd, ext) \
+  H_GET_32 (abfd, ext->x_sym.x_misc.x_lnsz.x_size)
+#define GET_LNSZ_LNNO(abfd, ext) \
+  H_GET_32 (abfd, ext->x_sym.x_misc.x_lnsz.x_lnno)
+#define PUT_LNSZ_LNNO(abfd, in, ext) \
+  H_PUT_32 (abfd, in, ext->x_sym.x_misc.x_lnsz.x_lnno)
+#define PUT_LNSZ_SIZE(abfd, in, ext) \
+  H_PUT_32 (abfd, in, ext->x_sym.x_misc.x_lnsz.x_size)
+#define GET_SCN_NRELOC(abfd, ext) \
+  H_GET_32 (abfd, ext->x_scn.x_nreloc)
+#define GET_SCN_NLINNO(abfd, ext) \
+  H_GET_32 (abfd, ext->x_scn.x_nlinno)
+#define PUT_SCN_NRELOC(abfd, in, ext) \
+  H_PUT_32 (abfd, in, ext->x_scn.x_nreloc)
+#define PUT_SCN_NLINNO(abfd, in, ext) \
+  H_PUT_32 (abfd,in, ext->x_scn.x_nlinno)
+
+#define	SYMENT	struct external_syment
+#define	SYMESZ	20
+#define	AUXENT	union external_auxent
+#define	AUXESZ	20
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+  char r_offset[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ  12
+
+#define NO_TVNDX
diff --git a/binutils-2.25/include/coff/mcore.h b/binutils-2.25/include/coff/mcore.h
new file mode 100644
index 00000000..60dbfb27
--- /dev/null
+++ b/binutils-2.25/include/coff/mcore.h
@@ -0,0 +1,72 @@
+/* Motorola MCore support for BFD.
+   Copyright 1999, 2000, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file holds definitions specific to the MCore COFF/PE ABI. */
+
+#ifndef _COFF_MORE_H
+#define _COFF_MORE_H
+
+#define INCLUDE_COMDAT_FIELDS_IN_AUXENT
+#define L_LNNO_SIZE 2
+#include "coff/external.h"
+
+#define	MCOREMAGIC	0xb00  /* I just made this up */ 
+
+#define MCOREBADMAG(x) (((x).f_magic != MCOREMAGIC))
+
+#define E_DIMNUM	4	/* # array dimensions in auxiliary entry */
+
+#define IMAGE_REL_MCORE_ABSOLUTE          	0x0000
+#define IMAGE_REL_MCORE_ADDR32            	0x0001
+#define IMAGE_REL_MCORE_PCREL_IMM8BY4		0x0002
+#define IMAGE_REL_MCORE_PCREL_IMM11BY2		0x0003
+#define IMAGE_REL_MCORE_PCREL_IMM4BY2		0x0004
+#define IMAGE_REL_MCORE_PCREL_32		0x0005
+#define IMAGE_REL_MCORE_PCREL_JSR_IMM11BY2	0x0006
+#define IMAGE_REL_MCORE_RVA			0x0007
+
+#define PEMCORE
+
+#define OMAGIC          0404    /* object files, eg as output */
+#define ZMAGIC          0413    /* demand load format, eg normal ld output */
+#define STMAGIC		0401	/* target shlib */
+#define SHMAGIC		0443	/* host   shlib */
+
+/* From winnt.h */
+#define IMAGE_NT_OPTIONAL_HDR_MAGIC        0x10b
+
+/* Define some NT default values. */
+#define NT_SECTION_ALIGNMENT 0x1000
+#define NT_FILE_ALIGNMENT    0x200  
+#define NT_DEF_RESERVE       0x100000
+#define NT_DEF_COMMIT        0x1000
+
+struct external_reloc
+{
+  char r_vaddr  [4];
+  char r_symndx [4];
+  char r_type   [2];
+  char r_offset [4];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 14
+
+#endif /* __COFF_MCORE_H */
diff --git a/binutils-2.25/include/coff/mips.h b/binutils-2.25/include/coff/mips.h
new file mode 100644
index 00000000..f1c243b6
--- /dev/null
+++ b/binutils-2.25/include/coff/mips.h
@@ -0,0 +1,344 @@
+/* ECOFF support on MIPS machines.
+   coff/ecoff.h must be included before this file.
+   
+   Copyright 1999, 2004, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define DO_NOT_DEFINE_AOUTHDR
+#define L_LNNO_SIZE 4
+#include "coff/external.h"
+
+/* Magic numbers are defined in coff/ecoff.h.  */
+#define MIPS_ECOFF_BADMAG(x) (((x).f_magic!=MIPS_MAGIC_1) && \
+			      ((x).f_magic!=MIPS_MAGIC_LITTLE) &&\
+			      ((x).f_magic!=MIPS_MAGIC_BIG) && \
+			      ((x).f_magic!=MIPS_MAGIC_LITTLE2) && \
+			      ((x).f_magic!=MIPS_MAGIC_BIG2) && \
+			      ((x).f_magic!=MIPS_MAGIC_LITTLE3) && \
+			      ((x).f_magic!=MIPS_MAGIC_BIG3))
+
+
+/********************** AOUT "OPTIONAL HEADER" **********************/
+
+typedef struct external_aouthdr
+{
+  unsigned char magic[2];	/* type of file				*/
+  unsigned char	vstamp[2];	/* version stamp			*/
+  unsigned char	tsize[4];	/* text size in bytes, padded to FW bdry*/
+  unsigned char	dsize[4];	/* initialized data "  "		*/
+  unsigned char	bsize[4];	/* uninitialized data "   "		*/
+  unsigned char	entry[4];	/* entry pt.				*/
+  unsigned char text_start[4];	/* base of text used for this file */
+  unsigned char data_start[4];	/* base of data used for this file */
+  unsigned char bss_start[4];	/* base of bss used for this file */
+  unsigned char gprmask[4];	/* ?? */
+  unsigned char cprmask[4][4];	/* ?? */
+  unsigned char gp_value[4];	/* value for gp register */
+} AOUTHDR;
+
+/* compute size of a header */
+
+#define AOUTSZ 56
+#define AOUTHDRSZ 56
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+struct external_reloc
+  {
+    unsigned char r_vaddr[4];
+    unsigned char r_bits[4];
+  };
+
+#define RELOC struct external_reloc
+#define RELSZ 8
+
+/* MIPS ECOFF uses a packed 8 byte format for relocs.  These constants
+   are used to unpack the r_bits field.  */
+
+#define RELOC_BITS0_SYMNDX_SH_LEFT_BIG		16
+#define RELOC_BITS0_SYMNDX_SH_LEFT_LITTLE	0
+
+#define RELOC_BITS1_SYMNDX_SH_LEFT_BIG		8
+#define RELOC_BITS1_SYMNDX_SH_LEFT_LITTLE	8
+
+#define RELOC_BITS2_SYMNDX_SH_LEFT_BIG		0
+#define RELOC_BITS2_SYMNDX_SH_LEFT_LITTLE	16
+
+/* Originally, ECOFF used four bits for the reloc type and had three
+   reserved bits.  Irix 4 added another bit for the reloc type, which
+   was easy because it was big endian and one of the spare bits became
+   the new most significant bit.  To make this also work for little
+   endian ECOFF, we need to wrap one of the reserved bits around to
+   become the most significant bit of the reloc type.  */
+#define RELOC_BITS3_TYPE_BIG			0x3E
+#define RELOC_BITS3_TYPE_SH_BIG			1
+#define RELOC_BITS3_TYPE_LITTLE			0x78
+#define RELOC_BITS3_TYPE_SH_LITTLE		3
+#define RELOC_BITS3_TYPEHI_LITTLE		0x04
+#define RELOC_BITS3_TYPEHI_SH_LITTLE		2
+
+#define RELOC_BITS3_EXTERN_BIG			0x01
+#define RELOC_BITS3_EXTERN_LITTLE		0x80
+
+/* The r_type field in a reloc is one of the following values.  I
+   don't know if any other values can appear.  These seem to be all
+   that occur in the Ultrix 4.2 libraries.  */
+#define MIPS_R_IGNORE	0
+#define MIPS_R_REFHALF	1
+#define MIPS_R_REFWORD	2
+#define MIPS_R_JMPADDR	3
+#define MIPS_R_REFHI	4
+#define MIPS_R_REFLO	5
+#define MIPS_R_GPREL	6
+#define MIPS_R_LITERAL	7
+
+/* FIXME: This relocation is used (internally only) to represent branches
+   when assembling.  It should never appear in output files, and  
+   be removed.  (It used to be used for embedded-PIC support.)  */
+#define MIPS_R_PCREL16	12
+
+/********************** STABS **********************/
+
+#define MIPS_IS_STAB ECOFF_IS_STAB
+#define MIPS_MARK_STAB ECOFF_MARK_STAB
+#define MIPS_UNMARK_STAB ECOFF_UNMARK_STAB
+
+/********************** SYMBOLIC INFORMATION **********************/
+
+/* Written by John Gilmore.  */
+
+/* ECOFF uses COFF-like section structures, but its own symbol format.
+   This file defines the symbol format in fields whose size and alignment
+   will not vary on different host systems.  */
+
+/* File header as a set of bytes */
+
+struct hdr_ext
+{
+	unsigned char 	h_magic[2];
+	unsigned char	h_vstamp[2];
+	unsigned char	h_ilineMax[4];
+	unsigned char	h_cbLine[4];
+	unsigned char	h_cbLineOffset[4];
+	unsigned char	h_idnMax[4];
+	unsigned char	h_cbDnOffset[4];
+	unsigned char	h_ipdMax[4];
+	unsigned char	h_cbPdOffset[4];
+	unsigned char	h_isymMax[4];
+	unsigned char	h_cbSymOffset[4];
+	unsigned char	h_ioptMax[4];
+	unsigned char	h_cbOptOffset[4];
+	unsigned char	h_iauxMax[4];
+	unsigned char	h_cbAuxOffset[4];
+	unsigned char	h_issMax[4];
+	unsigned char	h_cbSsOffset[4];
+	unsigned char	h_issExtMax[4];
+	unsigned char	h_cbSsExtOffset[4];
+	unsigned char	h_ifdMax[4];
+	unsigned char	h_cbFdOffset[4];
+	unsigned char	h_crfd[4];
+	unsigned char	h_cbRfdOffset[4];
+	unsigned char	h_iextMax[4];
+	unsigned char	h_cbExtOffset[4];
+};
+
+/* File descriptor external record */
+
+struct fdr_ext
+{
+	unsigned char	f_adr[4];
+	unsigned char	f_rss[4];
+	unsigned char	f_issBase[4];
+	unsigned char	f_cbSs[4];
+	unsigned char	f_isymBase[4];
+	unsigned char	f_csym[4];
+	unsigned char	f_ilineBase[4];
+	unsigned char	f_cline[4];
+	unsigned char	f_ioptBase[4];
+	unsigned char	f_copt[4];
+	unsigned char	f_ipdFirst[2];
+	unsigned char	f_cpd[2];
+	unsigned char	f_iauxBase[4];
+	unsigned char	f_caux[4];
+	unsigned char	f_rfdBase[4];
+	unsigned char	f_crfd[4];
+	unsigned char	f_bits1[1];
+	unsigned char	f_bits2[3];
+	unsigned char	f_cbLineOffset[4];
+	unsigned char	f_cbLine[4];
+};
+
+#define	FDR_BITS1_LANG_BIG		0xF8
+#define	FDR_BITS1_LANG_SH_BIG		3
+#define	FDR_BITS1_LANG_LITTLE		0x1F
+#define	FDR_BITS1_LANG_SH_LITTLE	0
+
+#define	FDR_BITS1_FMERGE_BIG		0x04
+#define	FDR_BITS1_FMERGE_LITTLE		0x20
+
+#define	FDR_BITS1_FREADIN_BIG		0x02
+#define	FDR_BITS1_FREADIN_LITTLE	0x40
+
+#define	FDR_BITS1_FBIGENDIAN_BIG	0x01
+#define	FDR_BITS1_FBIGENDIAN_LITTLE	0x80
+
+#define	FDR_BITS2_GLEVEL_BIG		0xC0
+#define	FDR_BITS2_GLEVEL_SH_BIG		6
+#define	FDR_BITS2_GLEVEL_LITTLE		0x03
+#define	FDR_BITS2_GLEVEL_SH_LITTLE	0
+
+/* We ignore the `reserved' field in bits2. */
+
+/* Procedure descriptor external record */
+
+struct pdr_ext
+{
+	unsigned char	p_adr[4];
+	unsigned char	p_isym[4];
+	unsigned char	p_iline[4];
+	unsigned char	p_regmask[4];
+	unsigned char	p_regoffset[4];
+	unsigned char	p_iopt[4];
+	unsigned char	p_fregmask[4];
+	unsigned char	p_fregoffset[4];
+	unsigned char	p_frameoffset[4];
+	unsigned char	p_framereg[2];
+	unsigned char	p_pcreg[2];
+	unsigned char	p_lnLow[4];
+	unsigned char	p_lnHigh[4];
+	unsigned char	p_cbLineOffset[4];
+};
+
+/* Runtime procedure table */
+
+struct rpdr_ext
+{
+	unsigned char	p_adr[4];
+	unsigned char	p_regmask[4];
+	unsigned char	p_regoffset[4];
+	unsigned char	p_fregmask[4];
+	unsigned char	p_fregoffset[4];
+	unsigned char	p_frameoffset[4];
+	unsigned char	p_framereg[2];
+	unsigned char	p_pcreg[2];
+	unsigned char	p_irpss[4];
+	unsigned char	p_reserved[4];
+	unsigned char	p_exception_info[4];
+};
+
+/* Line numbers */
+
+struct line_ext
+{
+	unsigned char	l_line[4];
+};
+
+/* Symbol external record */
+
+struct sym_ext
+{
+	unsigned char	s_iss[4];
+	unsigned char	s_value[4];
+	unsigned char	s_bits1[1];
+	unsigned char	s_bits2[1];
+	unsigned char	s_bits3[1];
+	unsigned char	s_bits4[1];
+};
+
+#define	SYM_BITS1_ST_BIG		0xFC
+#define	SYM_BITS1_ST_SH_BIG		2
+#define	SYM_BITS1_ST_LITTLE		0x3F
+#define	SYM_BITS1_ST_SH_LITTLE		0
+
+#define	SYM_BITS1_SC_BIG		0x03
+#define	SYM_BITS1_SC_SH_LEFT_BIG	3
+#define	SYM_BITS1_SC_LITTLE		0xC0
+#define	SYM_BITS1_SC_SH_LITTLE		6
+
+#define	SYM_BITS2_SC_BIG		0xE0
+#define	SYM_BITS2_SC_SH_BIG		5
+#define	SYM_BITS2_SC_LITTLE		0x07
+#define	SYM_BITS2_SC_SH_LEFT_LITTLE	2
+
+#define	SYM_BITS2_RESERVED_BIG		0x10
+#define	SYM_BITS2_RESERVED_LITTLE	0x08
+
+#define	SYM_BITS2_INDEX_BIG		0x0F
+#define	SYM_BITS2_INDEX_SH_LEFT_BIG	16
+#define	SYM_BITS2_INDEX_LITTLE		0xF0
+#define	SYM_BITS2_INDEX_SH_LITTLE	4
+
+#define	SYM_BITS3_INDEX_SH_LEFT_BIG	8
+#define	SYM_BITS3_INDEX_SH_LEFT_LITTLE	4
+
+#define	SYM_BITS4_INDEX_SH_LEFT_BIG	0
+#define	SYM_BITS4_INDEX_SH_LEFT_LITTLE	12
+
+/* External symbol external record */
+
+struct ext_ext
+{
+	unsigned char	es_bits1[1];
+	unsigned char	es_bits2[1];
+	unsigned char	es_ifd[2];
+	struct	sym_ext es_asym;
+};
+
+#define	EXT_BITS1_JMPTBL_BIG		0x80
+#define	EXT_BITS1_JMPTBL_LITTLE		0x01
+
+#define	EXT_BITS1_COBOL_MAIN_BIG	0x40
+#define	EXT_BITS1_COBOL_MAIN_LITTLE	0x02
+
+#define	EXT_BITS1_WEAKEXT_BIG		0x20
+#define	EXT_BITS1_WEAKEXT_LITTLE	0x04
+
+/* Dense numbers external record */
+
+struct dnr_ext
+{
+	unsigned char	d_rfd[4];
+	unsigned char	d_index[4];
+};
+
+/* Relative file descriptor */
+
+struct rfd_ext
+{
+  unsigned char	rfd[4];
+};
+
+/* Optimizer symbol external record */
+
+struct opt_ext
+{
+  unsigned char o_bits1[1];
+  unsigned char o_bits2[1];
+  unsigned char o_bits3[1];
+  unsigned char o_bits4[1];
+  struct rndx_ext o_rndx;
+  unsigned char o_offset[4];
+};
+
+#define OPT_BITS2_VALUE_SH_LEFT_BIG	16
+#define OPT_BITS2_VALUE_SH_LEFT_LITTLE	0
+
+#define OPT_BITS3_VALUE_SH_LEFT_BIG	8
+#define OPT_BITS3_VALUE_SH_LEFT_LITTLE	8
+
+#define OPT_BITS4_VALUE_SH_LEFT_BIG	0
+#define OPT_BITS4_VALUE_SH_LEFT_LITTLE	16
diff --git a/binutils-2.25/include/coff/mipspe.h b/binutils-2.25/include/coff/mipspe.h
new file mode 100644
index 00000000..f1a0d439
--- /dev/null
+++ b/binutils-2.25/include/coff/mipspe.h
@@ -0,0 +1,67 @@
+/* coff information for Windows CE with MIPS VR4111
+   
+   Copyright 2000, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define L_LNNO_SIZE 2
+#define INCLUDE_COMDAT_FIELDS_IN_AUXENT
+#include "coff/external.h"
+
+#define MIPS_ARCH_MAGIC_WINCE	0x0166  /* Windows CE - little endian */
+#define MIPS_PE_MAGIC		0x010b
+
+#define MIPSBADMAG(x) ((x).f_magic != MIPS_ARCH_MAGIC_WINCE)
+
+/* define some NT default values */
+/*  #define NT_IMAGE_BASE        0x400000 moved to internal.h */
+#define NT_SECTION_ALIGNMENT 0x1000
+#define NT_FILE_ALIGNMENT    0x200
+#define NT_DEF_RESERVE       0x100000
+#define NT_DEF_COMMIT        0x1000
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+/* The external reloc has an offset field, because some of the reloc
+   types on the h8 don't have room in the instruction for the entire
+   offset - eg the strange jump and high page addressing modes.  */
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 10
+
+/* MIPS PE relocation types. */
+
+#define	MIPS_R_ABSOLUTE	0 /* ignored */
+#define	MIPS_R_REFHALF	1
+#define	MIPS_R_REFWORD	2
+#define	MIPS_R_JMPADDR	3
+#define	MIPS_R_REFHI	4 /* PAIR follows */
+#define	MIPS_R_REFLO	5
+#define	MIPS_R_GPREL	6
+#define	MIPS_R_LITERAL	7 /* same as GPREL */
+#define	MIPS_R_SECTION	10
+#define	MIPS_R_SECREL	11
+#define	MIPS_R_SECRELLO	12
+#define	MIPS_R_SECRELHI	13 /* PAIR follows */
+#define	MIPS_R_RVA	34 /* 0x22 */
+#define	MIPS_R_PAIR	37 /* 0x25 - symndx is really a signed 16-bit addend */
diff --git a/binutils-2.25/include/coff/or32.h b/binutils-2.25/include/coff/or32.h
new file mode 100644
index 00000000..9be7887a
--- /dev/null
+++ b/binutils-2.25/include/coff/or32.h
@@ -0,0 +1,288 @@
+/* COFF specification for OpenRISC 1000.
+   Copyright (C) 1993-2000, 2002, 2010 Free Software Foundation, Inc.
+   Contributed by David Wood @ New York University.
+   Modified by Johan Rydberg, <johan.rydberg@netinsight.se>
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef OR32
+# define OR32
+#endif
+
+/* File Header and related definitions.  */
+struct external_filehdr
+{
+  char f_magic[2];	/* magic number		    */
+  char f_nscns[2];	/* number of sections	    */
+  char f_timdat[4];     /* time & date stamp	    */
+  char f_symptr[4];     /* file pointer to symtab   */
+  char f_nsyms[4];	/* number of symtab entries */
+  char f_opthdr[2];     /* sizeof(optional hdr)	    */
+  char f_flags[2];	/* flags		    */
+};
+
+#define FILHDR  struct external_filehdr
+#define FILHSZ	20
+
+/* Magic numbers for OpenRISC 1000. As it is know we use the
+   numbers for Am29000.
+
+   (AT&T will assign the "real" magic number).  */
+#define SIPFBOMAGIC     0572    /* Am29000 (Byte 0 is MSB).  */
+#define SIPRBOMAGIC     0573    /* Am29000 (Byte 0 is LSB).  */
+
+#define OR32_MAGIC_BIG 		SIPFBOMAGIC	
+#define OR32_MAGIC_LITTLE	SIPRBOMAGIC	
+#define OR32BADMAG(x)     (((x).f_magic!=OR32_MAGIC_BIG) && \
+			                      ((x).f_magic!=OR32_MAGIC_LITTLE))
+
+#define OMAGIC OR32_MAGIC_BIG
+
+/* Optional (a.out) header.  */
+typedef	struct external_aouthdr 
+{
+  char  magic[2];         /* type of file                     */
+  char  vstamp[2];	  /* version stamp                    */
+  char  tsize[4];	  /* text size in bytes, padded to FW bdry */
+  char  dsize[4];	  /* initialized data "  "            */
+  char  bsize[4];	  /* uninitialized data "   "         */
+  char  entry[4];	  /* entry pt.                        */
+  char  text_start[4];	  /* base of text used for this file  */
+  char  data_start[4];	  /* base of data used for this file  */
+} AOUTHDR;
+
+#define AOUTSZ      28
+#define AOUTHDRSZ   28
+
+/* aouthdr magic numbers.  */
+#define NMAGIC    0410	  /* separate i/d executable.  */
+#define SHMAGIC   0406	  /* NYU/Ultra3 shared data executable 
+                             (writable text).  */
+
+#define _ETEXT   	"_etext"
+
+/* Section header and related definitions.  */
+struct external_scnhdr 
+{
+  char	    s_name[8];      /* section name                   */
+  char	    s_paddr[4];     /* physical address, aliased s_nlib */
+  char	    s_vaddr[4];     /* virtual address                */
+  char	    s_size[4];      /* section size                   */
+  char	    s_scnptr[4];    /* file ptr to raw data for section */
+  char	    s_relptr[4];    /* file ptr to relocation         */
+  char	    s_lnnoptr[4];   /* file ptr to line numbers       */
+  char	    s_nreloc[2];    /* number of relocation entries   */
+  char	    s_nlnno[2];     /* number of line number entries  */
+  char	    s_flags[4];     /* flags                          */
+};
+
+#define	SCNHDR	struct external_scnhdr
+#define	SCNHSZ	40
+
+/* Names of "special" sections:  */
+#define _TEXT   ".text"
+#define _DATA   ".data"
+#define _BSS    ".bss"
+#define _LIT    ".lit"
+
+/* Section types - with additional section type for global 
+   registers which will be relocatable for the OpenRISC 1000.
+
+   In instances where it is necessary for a linker to produce an
+   output file which contains text or data not based at virtual
+   address 0, e.g. for a ROM, then the linker should accept
+   address base information as command input and use PAD sections
+   to skip over unused addresses.  */
+#define	STYP_BSSREG 0x1200	/* Global register area (like STYP_INFO) */
+#define STYP_ENVIR  0x2200	/* Environment (like STYP_INFO) */
+#define STYP_ABS    0x4000	/* Absolute (allocated, not reloc, loaded) */
+
+/* Relocation information declaration and related definitions:  */
+struct external_reloc
+{
+  char r_vaddr[4];    /* (virtual) address of reference */
+  char r_symndx[4];   /* index into symbol table */
+  char r_type[2];     /* relocation type */
+};
+
+#define	RELOC		struct external_reloc
+#define	RELSZ		10		/* sizeof (RELOC) */ 
+
+/* Relocation types for the OpenRISC 1000: */
+
+#define	R_ABS     0     /* reference is absolute */
+#define	R_IREL    030	/* instruction relative (jmp/call) */
+#define	R_IABS    031	/* instruction absolute (jmp/call) */
+#define	R_ILOHALF 032	/* instruction low half  (const)  */
+#define	R_IHIHALF 033	/* instruction high half (consth) part 1 */
+#define	R_IHCONST 034	/* instruction high half (consth) part 2 */
+                        /* constant offset of R_IHIHALF relocation */
+#define	R_BYTE    035	/* relocatable byte value */
+#define R_HWORD   036	/* relocatable halfword value */
+#define R_WORD    037	/* relocatable word value */
+
+#define	R_IGLBLRC 040	/* instruction global register RC */
+#define	R_IGLBLRA 041	/* instruction global register RA */
+#define	R_IGLBLRB 042	/* instruction global register RB */
+ 
+/*
+  NOTE:
+  All the "I" forms refer to 29000 instruction formats.  The linker is 
+  expected to know how the numeric information is split and/or aligned
+  within the instruction word(s).  R_BYTE works for instructions, too.
+
+  If the parameter to a CONSTH instruction is a relocatable type, two 
+  relocation records are written.  The first has an r_type of R_IHIHALF 
+  (33 octal) and a normal r_vaddr and r_symndx.  The second relocation 
+  record has an r_type of R_IHCONST (34 octal), a normal r_vaddr (which 
+  is redundant), and an r_symndx containing the 32-bit constant offset 
+  to the relocation instead of the actual symbol table index.  This 
+  second record is always written, even if the constant offset is zero.
+  The constant fields of the instruction are set to zero.  */
+
+/* Line number entry declaration and related definitions:  */
+struct external_lineno 
+{
+  union
+  {
+    char l_symndx[4];  /* function name symbol index, iff l_lnno == 0*/
+    char l_paddr[4];   /* (physical) address of line number    */
+  }
+  l_addr;
+
+  char l_lnno[2];      /* line number	  */
+};
+
+#define	LINENO		struct external_lineno
+#define	LINESZ		6		  /* sizeof (LINENO) */
+
+/* Symbol entry declaration and related definitions:  */
+#define	E_SYMNMLEN	8	  /* Number of characters in a symbol name */
+
+struct external_syment
+{
+  union
+  {
+    char e_name[E_SYMNMLEN];
+    struct
+    {
+      char e_zeroes[4];
+      char e_offset[4];
+    }
+    e;
+  }
+  e;
+
+  char e_value[4];
+  char e_scnum[2];
+  char e_type[2];
+  char e_sclass[1];
+  char e_numaux[1];
+};
+
+#define	SYMENT	struct external_syment
+#define	SYMESZ 	18
+
+/* Storage class definitions - new classes for global registers:  */
+#define C_GLBLREG	19		/* global register */
+#define C_EXTREG	20		/* external global register */
+#define	C_DEFREG	21		/* ext. def. of global register */
+
+/* Derived symbol mask/shifts:  */
+#define N_BTMASK	(0xf)
+#define N_BTSHFT	(4)
+#define N_TMASK		(0x30)
+#define N_TSHIFT	(2)
+
+/* Auxiliary symbol table entry declaration and related 
+   definitions.  */
+#define E_FILNMLEN  14  /* # characters in a file name	  */
+#define E_DIMNUM    4   /* # array dimensions in auxiliary entry */
+
+union external_auxent
+{
+  struct
+  {
+    char x_tagndx[4];       /* str, un, or enum tag indx */
+    union
+    {
+      struct
+      {
+	char  x_lnno[2];    /* declaration line number */
+        char  x_size[2];    /* str/union/array size */
+      }
+      x_lnsz;
+
+      char x_fsize[4];      /* size of function */
+    }
+    x_misc;
+
+    union
+    {
+      struct 		          /* if ISFCN, tag, or .bb */
+      {
+	char x_lnnoptr[4];  /* ptr to fcn line # */
+        char x_endndx[4];   /* entry ndx past block end */
+      }
+      x_fcn;
+
+      struct   	          /* if ISARY, up to 4 dimen. */
+      {
+	char x_dimen[E_DIMNUM][2];
+      }
+      x_ary;
+    }
+    x_fcnary;
+
+    char x_tvndx[2];        /* tv index */
+  }
+  x_sym;
+
+  union
+  {
+    char x_fname[E_FILNMLEN];
+
+    struct
+    {
+      char x_zeroes[4];
+      char x_offset[4];
+    }
+    x_n;
+  }
+  x_file;
+
+  struct
+  {
+    char x_scnlen[4];       /* section length */
+    char x_nreloc[2];       /* # relocation entries */
+    char x_nlinno[2];       /* # line numbers */
+  }
+  x_scn;
+
+  struct
+  {
+    char x_tvfill[4];       /* tv fill value */
+    char x_tvlen[2];        /* length of .tv */
+    char x_tvran[2][2];     /* tv range */
+  }
+  x_tv;                   /* info about .tv section 
+			     (in auxent of symbol .tv)) */
+};
+
+#define	AUXENT		union external_auxent
+#define	AUXESZ		18	
diff --git a/binutils-2.25/include/coff/pe.h b/binutils-2.25/include/coff/pe.h
new file mode 100644
index 00000000..601a68e8
--- /dev/null
+++ b/binutils-2.25/include/coff/pe.h
@@ -0,0 +1,512 @@
+/* pe.h  -  PE COFF header information 
+
+   Copyright 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007, 2009, 2010
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+#ifndef _PE_H
+#define _PE_H
+
+/* NT specific file attributes.  */
+#define IMAGE_FILE_RELOCS_STRIPPED           0x0001
+#define IMAGE_FILE_EXECUTABLE_IMAGE          0x0002
+#define IMAGE_FILE_LINE_NUMS_STRIPPED        0x0004
+#define IMAGE_FILE_LOCAL_SYMS_STRIPPED       0x0008
+#define IMAGE_FILE_AGGRESSIVE_WS_TRIM        0x0010
+#define IMAGE_FILE_LARGE_ADDRESS_AWARE       0x0020
+#define IMAGE_FILE_16BIT_MACHINE             0x0040
+#define IMAGE_FILE_BYTES_REVERSED_LO         0x0080
+#define IMAGE_FILE_32BIT_MACHINE             0x0100
+#define IMAGE_FILE_DEBUG_STRIPPED            0x0200
+#define IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP   0x0400
+#define IMAGE_FILE_NET_RUN_FROM_SWAP         0x0800
+#define IMAGE_FILE_SYSTEM                    0x1000
+#define IMAGE_FILE_DLL                       0x2000
+#define IMAGE_FILE_UP_SYSTEM_ONLY            0x4000
+#define IMAGE_FILE_BYTES_REVERSED_HI         0x8000
+
+/* DllCharacteristics flag bits.  The inconsistent naming may seem
+   odd, but that is how they are defined in the PE specification.  */
+#define IMAGE_DLL_CHARACTERISTICS_DYNAMIC_BASE          0x0040
+#define IMAGE_DLL_CHARACTERISTICS_FORCE_INTEGRITY       0x0080
+#define IMAGE_DLL_CHARACTERISTICS_NX_COMPAT             0x0100
+#define IMAGE_DLLCHARACTERISTICS_NO_ISOLATION           0x0200
+#define IMAGE_DLLCHARACTERISTICS_NO_SEH                 0x0400
+#define IMAGE_DLLCHARACTERISTICS_NO_BIND                0x0800
+#define IMAGE_DLLCHARACTERISTICS_WDM_DRIVER             0x2000
+#define IMAGE_DLLCHARACTERISTICS_TERMINAL_SERVER_AWARE  0x8000
+
+/* Additional flags to be set for section headers to allow the NT loader to
+   read and write to the section data (to replace the addresses of data in
+   dlls for one thing); also to execute the section in .text's case.  */
+#define IMAGE_SCN_MEM_DISCARDABLE 0x02000000
+#define IMAGE_SCN_MEM_EXECUTE     0x20000000
+#define IMAGE_SCN_MEM_READ        0x40000000
+#define IMAGE_SCN_MEM_WRITE       0x80000000
+
+/* Section characteristics added for ppc-nt.  */
+
+#define IMAGE_SCN_TYPE_NO_PAD                0x00000008  /* Reserved. */
+
+#define IMAGE_SCN_CNT_CODE                   0x00000020  /* Section contains code. */
+#define IMAGE_SCN_CNT_INITIALIZED_DATA       0x00000040  /* Section contains initialized data. */
+#define IMAGE_SCN_CNT_UNINITIALIZED_DATA     0x00000080  /* Section contains uninitialized data. */
+
+#define IMAGE_SCN_LNK_OTHER                  0x00000100  /* Reserved. */
+#define IMAGE_SCN_LNK_INFO                   0x00000200  /* Section contains comments or some other type of information. */
+#define IMAGE_SCN_LNK_REMOVE                 0x00000800  /* Section contents will not become part of image. */
+#define IMAGE_SCN_LNK_COMDAT                 0x00001000  /* Section contents comdat. */
+
+#define IMAGE_SCN_MEM_FARDATA                0x00008000
+
+#define IMAGE_SCN_MEM_PURGEABLE              0x00020000
+#define IMAGE_SCN_MEM_16BIT                  0x00020000
+#define IMAGE_SCN_MEM_LOCKED                 0x00040000
+#define IMAGE_SCN_MEM_PRELOAD                0x00080000
+
+/* Bit position in the s_flags field where the alignment values start. */
+#define IMAGE_SCN_ALIGN_POWER_BIT_POS	     20
+#define IMAGE_SCN_ALIGN_POWER_BIT_MASK	     0x00f00000
+#define IMAGE_SCN_ALIGN_POWER_NUM(val)	     \
+  (((val) >> IMAGE_SCN_ALIGN_POWER_BIT_POS) - 1)
+#define IMAGE_SCN_ALIGN_POWER_CONST(val)     \
+  (((val) + 1) << IMAGE_SCN_ALIGN_POWER_BIT_POS)
+
+#define IMAGE_SCN_ALIGN_1BYTES		     IMAGE_SCN_ALIGN_POWER_CONST (0)
+#define IMAGE_SCN_ALIGN_2BYTES		     IMAGE_SCN_ALIGN_POWER_CONST (1)
+#define IMAGE_SCN_ALIGN_4BYTES		     IMAGE_SCN_ALIGN_POWER_CONST (2)
+#define IMAGE_SCN_ALIGN_8BYTES		     IMAGE_SCN_ALIGN_POWER_CONST (3)
+/* Default alignment if no others are specified. */
+#define IMAGE_SCN_ALIGN_16BYTES		     IMAGE_SCN_ALIGN_POWER_CONST (4)
+#define IMAGE_SCN_ALIGN_32BYTES		     IMAGE_SCN_ALIGN_POWER_CONST (5)
+#define IMAGE_SCN_ALIGN_64BYTES		     IMAGE_SCN_ALIGN_POWER_CONST (6)
+#define IMAGE_SCN_ALIGN_128BYTES	     IMAGE_SCN_ALIGN_POWER_CONST (7)
+#define IMAGE_SCN_ALIGN_256BYTES	     IMAGE_SCN_ALIGN_POWER_CONST (8)
+#define IMAGE_SCN_ALIGN_512BYTES	     IMAGE_SCN_ALIGN_POWER_CONST (9)
+#define IMAGE_SCN_ALIGN_1024BYTES	     IMAGE_SCN_ALIGN_POWER_CONST (10)
+#define IMAGE_SCN_ALIGN_2048BYTES	     IMAGE_SCN_ALIGN_POWER_CONST (11)
+#define IMAGE_SCN_ALIGN_4096BYTES	     IMAGE_SCN_ALIGN_POWER_CONST (12)
+#define IMAGE_SCN_ALIGN_8192BYTES	     IMAGE_SCN_ALIGN_POWER_CONST (13)
+
+/* Encode alignment power into IMAGE_SCN_ALIGN bits of s_flags */
+#define COFF_ENCODE_ALIGNMENT(SECTION, ALIGNMENT_POWER) \
+  ((SECTION).s_flags |= IMAGE_SCN_ALIGN_POWER_CONST ((ALIGNMENT_POWER)))
+
+#define IMAGE_SCN_LNK_NRELOC_OVFL            0x01000000  /* Section contains extended relocations. */
+#define IMAGE_SCN_MEM_NOT_CACHED             0x04000000  /* Section is not cachable.               */
+#define IMAGE_SCN_MEM_NOT_PAGED              0x08000000  /* Section is not pageable.               */
+#define IMAGE_SCN_MEM_SHARED                 0x10000000  /* Section is shareable.                  */
+
+/* COMDAT selection codes.  */
+
+#define IMAGE_COMDAT_SELECT_NODUPLICATES     (1) /* Warn if duplicates.  */
+#define IMAGE_COMDAT_SELECT_ANY		     (2) /* No warning.  */
+#define IMAGE_COMDAT_SELECT_SAME_SIZE	     (3) /* Warn if different size.  */
+#define IMAGE_COMDAT_SELECT_EXACT_MATCH	     (4) /* Warn if different.  */
+#define IMAGE_COMDAT_SELECT_ASSOCIATIVE	     (5) /* Base on other section.  */
+
+/* Machine numbers.  */
+
+#define IMAGE_FILE_MACHINE_UNKNOWN           0x0000
+#define IMAGE_FILE_MACHINE_ALPHA             0x0184
+#define IMAGE_FILE_MACHINE_ALPHA64           0x0284
+#define IMAGE_FILE_MACHINE_AM33              0x01d3
+#define IMAGE_FILE_MACHINE_AMD64             0x8664
+#define IMAGE_FILE_MACHINE_ARM               0x01c0
+#define IMAGE_FILE_MACHINE_AXP64             IMAGE_FILE_MACHINE_ALPHA64
+#define IMAGE_FILE_MACHINE_CEE               0xc0ee
+#define IMAGE_FILE_MACHINE_CEF               0x0cef
+#define IMAGE_FILE_MACHINE_EBC               0x0ebc
+#define IMAGE_FILE_MACHINE_I386              0x014c
+#define IMAGE_FILE_MACHINE_IA64              0x0200
+#define IMAGE_FILE_MACHINE_M32R              0x9041
+#define IMAGE_FILE_MACHINE_M68K              0x0268
+#define IMAGE_FILE_MACHINE_MIPS16            0x0266
+#define IMAGE_FILE_MACHINE_MIPSFPU           0x0366
+#define IMAGE_FILE_MACHINE_MIPSFPU16         0x0466
+#define IMAGE_FILE_MACHINE_POWERPC           0x01f0
+#define IMAGE_FILE_MACHINE_POWERPCFP         0x01f1
+#define IMAGE_FILE_MACHINE_R10000            0x0168
+#define IMAGE_FILE_MACHINE_R3000             0x0162
+#define IMAGE_FILE_MACHINE_R4000             0x0166
+#define IMAGE_FILE_MACHINE_SH3               0x01a2
+#define IMAGE_FILE_MACHINE_SH3DSP            0x01a3
+#define IMAGE_FILE_MACHINE_SH3E              0x01a4
+#define IMAGE_FILE_MACHINE_SH4               0x01a6
+#define IMAGE_FILE_MACHINE_SH5               0x01a8
+#define IMAGE_FILE_MACHINE_THUMB             0x01c2
+#define IMAGE_FILE_MACHINE_TRICORE           0x0520
+#define IMAGE_FILE_MACHINE_WCEMIPSV2         0x0169
+#define IMAGE_FILE_MACHINE_AMD64             0x8664
+
+#define IMAGE_SUBSYSTEM_UNKNOWN			 0
+#define IMAGE_SUBSYSTEM_NATIVE			 1
+#define IMAGE_SUBSYSTEM_WINDOWS_GUI		 2
+#define IMAGE_SUBSYSTEM_WINDOWS_CUI		 3
+#define IMAGE_SUBSYSTEM_POSIX_CUI		 7
+#define IMAGE_SUBSYSTEM_WINDOWS_CE_GUI		 9
+#define IMAGE_SUBSYSTEM_EFI_APPLICATION		10
+#define IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER	11
+#define IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER	12
+#define IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER	13
+#define IMAGE_SUBSYSTEM_XBOX			14
+  
+/* Magic values that are true for all dos/nt implementations.  */
+#define DOSMAGIC       0x5a4d  
+#define NT_SIGNATURE   0x00004550
+
+/* NT allows long filenames, we want to accommodate this.
+   This may break some of the bfd functions.  */
+#undef  FILNMLEN
+#define FILNMLEN	18	/* # characters in a file name.  */
+
+struct external_PEI_DOS_hdr
+{
+  /* DOS header fields - always at offset zero in the EXE file.  */
+  char e_magic[2];		/* Magic number, 0x5a4d.  */
+  char e_cblp[2];		/* Bytes on last page of file, 0x90.  */
+  char e_cp[2];			/* Pages in file, 0x3.  */
+  char e_crlc[2];		/* Relocations, 0x0.  */
+  char e_cparhdr[2];		/* Size of header in paragraphs, 0x4.  */
+  char e_minalloc[2];		/* Minimum extra paragraphs needed, 0x0.  */
+  char e_maxalloc[2];		/* Maximum extra paragraphs needed, 0xFFFF.  */
+  char e_ss[2];			/* Initial (relative) SS value, 0x0.  */
+  char e_sp[2];			/* Initial SP value, 0xb8.  */
+  char e_csum[2];		/* Checksum, 0x0.  */
+  char e_ip[2];			/* Initial IP value, 0x0.  */
+  char e_cs[2];			/* Initial (relative) CS value, 0x0.  */
+  char e_lfarlc[2];		/* File address of relocation table, 0x40.  */
+  char e_ovno[2];		/* Overlay number, 0x0.  */
+  char e_res[4][2];		/* Reserved words, all 0x0.  */
+  char e_oemid[2];		/* OEM identifier (for e_oeminfo), 0x0.  */
+  char e_oeminfo[2];		/* OEM information; e_oemid specific, 0x0.  */
+  char e_res2[10][2];		/* Reserved words, all 0x0.  */
+  char e_lfanew[4];		/* File address of new exe header, usually 0x80.  */
+  char dos_message[16][4];	/* Other stuff, always follow DOS header.  */
+};
+
+struct external_PEI_IMAGE_hdr
+{
+  char nt_signature[4];		/* required NT signature, 0x4550.  */
+
+  /* From standard header.  */
+  char f_magic[2];		/* Magic number.		*/
+  char f_nscns[2];		/* Number of sections.		*/
+  char f_timdat[4];		/* Time & date stamp.		*/
+  char f_symptr[4];		/* File pointer to symtab.	*/
+  char f_nsyms[4];		/* Number of symtab entries.	*/
+  char f_opthdr[2];		/* Sizeof(optional hdr).	*/
+  char f_flags[2];		/* Flags.			*/
+};
+
+struct external_PEI_filehdr
+{
+  /* DOS header fields - always at offset zero in the EXE file.  */
+  char e_magic[2];		/* Magic number, 0x5a4d.  */
+  char e_cblp[2];		/* Bytes on last page of file, 0x90.  */
+  char e_cp[2];			/* Pages in file, 0x3.  */
+  char e_crlc[2];		/* Relocations, 0x0.  */
+  char e_cparhdr[2];		/* Size of header in paragraphs, 0x4.  */
+  char e_minalloc[2];		/* Minimum extra paragraphs needed, 0x0.  */
+  char e_maxalloc[2];		/* Maximum extra paragraphs needed, 0xFFFF.  */
+  char e_ss[2];			/* Initial (relative) SS value, 0x0.  */
+  char e_sp[2];			/* Initial SP value, 0xb8.  */
+  char e_csum[2];		/* Checksum, 0x0.  */
+  char e_ip[2];			/* Initial IP value, 0x0.  */
+  char e_cs[2];			/* Initial (relative) CS value, 0x0.  */
+  char e_lfarlc[2];		/* File address of relocation table, 0x40.  */
+  char e_ovno[2];		/* Overlay number, 0x0.  */
+  char e_res[4][2];		/* Reserved words, all 0x0.  */
+  char e_oemid[2];		/* OEM identifier (for e_oeminfo), 0x0.  */
+  char e_oeminfo[2];		/* OEM information; e_oemid specific, 0x0.  */
+  char e_res2[10][2];		/* Reserved words, all 0x0.  */
+  char e_lfanew[4];		/* File address of new exe header, usually 0x80.  */
+  char dos_message[16][4];	/* Other stuff, always follow DOS header.  */
+
+  /* Note: additional bytes may be inserted before the signature.  Use
+   the e_lfanew field to find the actual location of the NT signature.  */
+
+  char nt_signature[4];		/* required NT signature, 0x4550.  */
+
+  /* From standard header.  */
+  char f_magic[2];		/* Magic number.		*/
+  char f_nscns[2];		/* Number of sections.		*/
+  char f_timdat[4];		/* Time & date stamp.		*/
+  char f_symptr[4];		/* File pointer to symtab.	*/
+  char f_nsyms[4];		/* Number of symtab entries.	*/
+  char f_opthdr[2];		/* Sizeof(optional hdr).	*/
+  char f_flags[2];		/* Flags.			*/
+};
+
+#ifdef COFF_IMAGE_WITH_PE
+
+/* The filehdr is only weird in images.  */
+
+#undef  FILHDR
+#define FILHDR struct external_PEI_filehdr
+#undef  FILHSZ
+#define FILHSZ 152
+
+#endif /* COFF_IMAGE_WITH_PE */
+
+/* 32-bit PE a.out header: */
+
+typedef struct 
+{
+  AOUTHDR standard;
+
+  /* NT extra fields; see internal.h for descriptions.  */
+  char  ImageBase[4];
+  char  SectionAlignment[4];
+  char  FileAlignment[4];
+  char  MajorOperatingSystemVersion[2];
+  char  MinorOperatingSystemVersion[2];
+  char  MajorImageVersion[2];
+  char  MinorImageVersion[2];
+  char  MajorSubsystemVersion[2];
+  char  MinorSubsystemVersion[2];
+  char  Reserved1[4];
+  char  SizeOfImage[4];
+  char  SizeOfHeaders[4];
+  char  CheckSum[4];
+  char  Subsystem[2];
+  char  DllCharacteristics[2];
+  char  SizeOfStackReserve[4];
+  char  SizeOfStackCommit[4];
+  char  SizeOfHeapReserve[4];
+  char  SizeOfHeapCommit[4];
+  char  LoaderFlags[4];
+  char  NumberOfRvaAndSizes[4];
+  /* IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES];  */
+  char  DataDirectory[16][2][4]; /* 16 entries, 2 elements/entry, 4 chars.  */
+} PEAOUTHDR;
+
+#undef AOUTSZ
+#define AOUTSZ (AOUTHDRSZ + 196)
+
+/* Like PEAOUTHDR, except that the "standard" member has no BaseOfData
+   (aka data_start) member and that some of the members are 8 instead
+   of just 4 bytes long.  */
+typedef struct 
+{
+#ifdef AOUTHDRSZ64
+  AOUTHDR64 standard;
+#else
+  AOUTHDR standard;
+#endif
+  /* NT extra fields; see internal.h for descriptions.  */
+  char  ImageBase[8];
+  char  SectionAlignment[4];
+  char  FileAlignment[4];
+  char  MajorOperatingSystemVersion[2];
+  char  MinorOperatingSystemVersion[2];
+  char  MajorImageVersion[2];
+  char  MinorImageVersion[2];
+  char  MajorSubsystemVersion[2];
+  char  MinorSubsystemVersion[2];
+  char  Reserved1[4];
+  char  SizeOfImage[4];
+  char  SizeOfHeaders[4];
+  char  CheckSum[4];
+  char  Subsystem[2];
+  char  DllCharacteristics[2];
+  char  SizeOfStackReserve[8];
+  char  SizeOfStackCommit[8];
+  char  SizeOfHeapReserve[8];
+  char  SizeOfHeapCommit[8];
+  char  LoaderFlags[4];
+  char  NumberOfRvaAndSizes[4];
+  /* IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES];  */
+  char  DataDirectory[16][2][4]; /* 16 entries, 2 elements/entry, 4 chars.  */
+} PEPAOUTHDR;
+
+#ifdef AOUTHDRSZ64
+#define PEPAOUTSZ	(AOUTHDRSZ64 + 196 + 5 * 4) /* = 240 */
+#else
+#define PEPAOUTSZ	240
+#endif
+  
+#undef  E_FILNMLEN
+#define E_FILNMLEN	18	/* # characters in a file name.  */
+
+/* Import Tyoes fot ILF format object files..  */
+#define IMPORT_CODE	0
+#define IMPORT_DATA	1
+#define IMPORT_CONST	2
+
+/* Import Name Tyoes for ILF format object files.  */
+#define IMPORT_ORDINAL		0
+#define IMPORT_NAME		1
+#define IMPORT_NAME_NOPREFIX	2
+#define IMPORT_NAME_UNDECORATE	3
+
+/* Weak external characteristics.  */
+#define IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY	1
+#define IMAGE_WEAK_EXTERN_SEARCH_LIBRARY	2
+#define IMAGE_WEAK_EXTERN_SEARCH_ALIAS		3
+
+/* .pdata/.xdata defines and structures for x64 PE+ for exception handling.  */
+
+/* .pdata in exception directory.  */
+
+struct pex64_runtime_function
+{
+  bfd_vma rva_BeginAddress;
+  bfd_vma rva_EndAddress;
+  bfd_vma rva_UnwindData;
+  unsigned int isChained : 1;
+};
+
+struct external_pex64_runtime_function
+{
+  bfd_byte rva_BeginAddress[4];
+  bfd_byte rva_EndAddress[4];
+  bfd_byte rva_UnwindData[4];
+};
+
+/* If the lowest significant bit is set for rva_UnwindData RVA, it
+   means that the unified RVA points to another pex64_runtime_function
+   that this entry shares the unwind_info block with.  */
+#define PEX64_IS_RUNTIME_FUNCTION_CHAINED(PTR_RTF) \
+  (((PTR_RTF)->rva_UnwindData & 1) != 0)
+#define PEX64_GET_UNWINDDATA_UNIFIED_RVA(PTR_RTF) \
+  ((PTR_RTF)->rva_UnwindData & ~1)
+
+/* The unwind codes.  */
+#define UWOP_PUSH_NONVOL      0
+#define UWOP_ALLOC_LARGE      1
+#define UWOP_ALLOC_SMALL      2
+#define UWOP_SET_FPREG	      3
+#define UWOP_SAVE_NONVOL      4
+#define UWOP_SAVE_NONVOL_FAR  5
+#define UWOP_SAVE_XMM	      6
+#define UWOP_SAVE_XMM_FAR     7
+#define UWOP_SAVE_XMM128      8
+#define UWOP_SAVE_XMM128_FAR  9
+#define UWOP_PUSH_MACHFRAME   10
+
+struct pex64_unwind_code
+{
+  bfd_vma prologue_offset;
+  /* Contains Frame offset, or frame allocation size.  */
+  bfd_vma frame_addr;
+  unsigned int uwop_code : 4;
+  /* xmm, mm, or standard register from 0 - 15.  */
+  unsigned int reg : 4;
+  /* Used for UWOP_PUSH_MACHFRAME to indicate optional errorcode stack
+     argument.  */
+  unsigned int has_errorcode : 1;
+};
+
+struct external_pex64_unwind_code
+{
+  bfd_byte dta[2];
+};
+
+#define PEX64_UNWCODE_CODE(VAL)	((VAL) & 0xf)
+#define PEX64_UNWCODE_INFO(VAL) (((VAL) >> 4) & 0xf)
+
+/* The unwind info.  */
+#define UNW_FLAG_NHANDLER     0
+#define UNW_FLAG_EHANDLER     1
+#define UNW_FLAG_UHANDLER     2
+#define UNW_FLAG_FHANDLER     3
+#define UNW_FLAG_CHAININFO    4
+
+#define UNW_FLAG_MASK	      0x1f
+
+struct pex64_unwind_info
+{
+  bfd_vma SizeOfBlock;
+  bfd_byte Version; /* Values from 0 up to 7 are possible.  */
+  bfd_byte Flags; /* Values from 0 up to 31 are possible.  */
+  bfd_vma SizeOfPrologue;
+  bfd_vma CountOfCodes; /* Amount of pex64_unwind_code elements.  */
+  /* 0 = CFA, 1..15 are index of integer registers.  */
+  unsigned int FrameRegister : 4;
+  bfd_vma FrameOffset;
+  bfd_vma sizeofUnwindCodes;
+  bfd_byte *rawUnwindCodes;
+  /* Valid for UNW_FLAG_EHANDLER and UNW_FLAG_UHANDLER.  */
+  bfd_vma CountOfScopes;
+  bfd_byte *rawScopeEntries;
+  bfd_vma rva_ExceptionHandler; /* UNW_EHANDLER.  */
+  bfd_vma rva_TerminationHandler; /* UNW_FLAG_UHANDLER.  */
+  bfd_vma rva_FrameHandler; /* UNW_FLAG_FHANDLER.  */
+  bfd_vma FrameHandlerArgument; /* UNW_FLAG_FHANDLER.  */
+  bfd_vma rva_FunctionEntry; /* UNW_FLAG_CHAININFO.  */
+};
+
+struct external_pex64_unwind_info
+{
+  bfd_byte Version_Flags;
+  bfd_byte SizeOfPrologue;
+  bfd_byte CountOfCodes;
+  bfd_byte FrameRegisterOffset;
+  /* external_pex64_unwind_code array.  */
+  /* bfd_byte handler[4];  */
+  /* Optional language specific data.  */
+};
+
+struct external_pex64_scope
+{
+  bfd_vma Count;
+};
+
+struct pex64_scope
+{
+  bfd_byte Count[4];
+};
+
+struct pex64_scope_entry
+{
+  bfd_vma rva_BeginAddress;
+  bfd_vma rva_EndAddress;
+  bfd_vma rva_HandlerAddress;
+  bfd_vma rva_JumpAddress;
+};
+#define PEX64_SCOPE_ENTRY_SIZE	16
+
+struct external_pex64_scope_entry
+{
+  bfd_byte rva_BeginAddress[4];
+  bfd_byte rva_EndAddress[4];
+  bfd_byte rva_HandlerAddress[4];
+  bfd_byte rva_JumpAddress[4];
+};
+
+#define PEX64_UWI_VERSION(VAL)	((VAL) & 7)
+#define PEX64_UWI_FLAGS(VAL)	(((VAL) >> 3) & 0x1f)
+#define PEX64_UWI_FRAMEREG(VAL)	((VAL) & 0xf)
+#define PEX64_UWI_FRAMEOFF(VAL)	(((VAL) >> 4) & 0xf)
+#define PEX64_UWI_SIZEOF_UWCODE_ARRAY(VAL) \
+  ((((VAL) + 1) & ~1) * 2)
+
+#define PEX64_OFFSET_TO_UNWIND_CODE 0x4
+
+#define PEX64_OFFSET_TO_HANDLER_RVA (COUNTOFUNWINDCODES) \
+  (PEX64_OFFSET_TO_UNWIND_CODE + \
+   PEX64_UWI_SIZEOF_UWCODE_ARRAY(COUNTOFUNWINDCODES))
+
+#define PEX64_OFFSET_TO_SCOPE_COUNT(COUNTOFUNWINDCODES) \
+  (PEX64_OFFSET_TO_HANDLER_RVA(COUNTOFUNWINDCODES) + 4)
+
+#define PEX64_SCOPE_ENTRY(COUNTOFUNWINDCODES, IDX) \
+  (PEX64_OFFSET_TO_SCOPE_COUNT(COUNTOFUNWINDCODES) + \
+   PEX64_SCOPE_ENTRY_SIZE * (IDX))
+
+#endif /* _PE_H */
diff --git a/binutils-2.25/include/coff/powerpc.h b/binutils-2.25/include/coff/powerpc.h
new file mode 100644
index 00000000..eba47309
--- /dev/null
+++ b/binutils-2.25/include/coff/powerpc.h
@@ -0,0 +1,59 @@
+/* Basic coff information for the PowerPC
+   Based on coff/rs6000.h, coff/i386.h and others.
+   
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.
+ 
+   Initial release: Kim Knuttila (krk@cygnus.com)  */
+#define L_LNNO_SIZE 2
+#define INCLUDE_COMDAT_FIELDS_IN_AUXENT
+#include "coff/external.h"
+
+/* Bits for f_flags:
+ 	F_RELFLG	relocation info stripped from file
+ 	F_EXEC		file is executable (no unresolved external references)
+ 	F_LNNO		line numbers stripped from file
+ 	F_LSYMS		local symbols stripped from file
+ 	F_AR32WR	file has byte ordering of an AR32WR machine (e.g. vax).  */
+
+#define F_RELFLG	(0x0001)
+#define F_EXEC		(0x0002)
+#define F_LNNO		(0x0004)
+#define F_LSYMS		(0x0008)
+
+/* extra NT defines */
+#define PPCMAGIC       0760         /* peeked on aa PowerPC Windows NT box */
+#define DOSMAGIC       0x5a4d       /* from arm.h, i386.h */
+#define NT_SIGNATURE   0x00004550   /* from arm.h, i386.h */
+
+/* from winnt.h */
+#define IMAGE_NT_OPTIONAL_HDR_MAGIC        0x10b
+
+#define PPCBADMAG(x) ((x).f_magic != PPCMAGIC) 
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 10
+
diff --git a/binutils-2.25/include/coff/rs6000.h b/binutils-2.25/include/coff/rs6000.h
new file mode 100644
index 00000000..7972d338
--- /dev/null
+++ b/binutils-2.25/include/coff/rs6000.h
@@ -0,0 +1,353 @@
+/* IBM RS/6000 "XCOFF" file definitions for BFD.
+   Copyright (C) 1990, 1991, 2001, 2010 Free Software Foundation, Inc.
+   Written by Mimi Phuong-Thao Vo of IBM
+   and John Gilmore of Cygnus Support.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/********************** FILE HEADER **********************/
+
+struct external_filehdr {
+	char f_magic[2];	/* magic number			*/
+	char f_nscns[2];	/* number of sections		*/
+	char f_timdat[4];	/* time & date stamp		*/
+	char f_symptr[4];	/* file pointer to symtab	*/
+	char f_nsyms[4];	/* number of symtab entries	*/
+	char f_opthdr[2];	/* sizeof(optional hdr)		*/
+	char f_flags[2];	/* flags			*/
+};
+
+        /* IBM RS/6000 */
+#define U802WRMAGIC     0730    /* writeable text segments **chh**      */
+#define U802ROMAGIC     0735    /* readonly sharable text segments      */
+#define U802TOCMAGIC    0737    /* readonly text segments and TOC       */
+
+#define BADMAG(x)	\
+	((x).f_magic != U802ROMAGIC && (x).f_magic != U802WRMAGIC && \
+	 (x).f_magic != U802TOCMAGIC)
+
+#define	FILHDR	struct external_filehdr
+#define	FILHSZ	20
+
+
+/********************** AOUT "OPTIONAL HEADER" **********************/
+
+
+typedef struct
+{
+  unsigned char	magic[2];	/* type of file			*/
+  unsigned char	vstamp[2];	/* version stamp		*/
+  unsigned char	tsize[4];	/* text size in bytes, padded to FW bdry */
+  unsigned char	dsize[4];	/* initialized data "  "	*/
+  unsigned char	bsize[4];	/* uninitialized data "   "	*/
+  unsigned char	entry[4];	/* entry pt.			*/
+  unsigned char	text_start[4];	/* base of text used for this file */
+  unsigned char	data_start[4];	/* base of data used for this file */
+  unsigned char	o_toc[4];	/* address of TOC */
+  unsigned char	o_snentry[2];	/* section number of entry point */
+  unsigned char	o_sntext[2];	/* section number of .text section */
+  unsigned char	o_sndata[2];	/* section number of .data section */
+  unsigned char	o_sntoc[2];	/* section number of TOC */
+  unsigned char	o_snloader[2];	/* section number of .loader section */
+  unsigned char	o_snbss[2];	/* section number of .bss section */
+  unsigned char	o_algntext[2];	/* .text alignment */
+  unsigned char	o_algndata[2];	/* .data alignment */
+  unsigned char	o_modtype[2];	/* module type (??) */
+  unsigned char o_cputype[2];	/* cpu type */
+  unsigned char	o_maxstack[4];	/* max stack size (??) */
+  unsigned char o_maxdata[4];	/* max data size (??) */
+  unsigned char	o_resv2[12];	/* reserved */
+}
+AOUTHDR;
+
+#define AOUTSZ 72
+#define SMALL_AOUTSZ (28)
+#define AOUTHDRSZ 72
+
+/********************** SECTION HEADER **********************/
+
+
+struct external_scnhdr {
+	char		s_name[8];	/* section name			*/
+	char		s_paddr[4];	/* physical address, aliased s_nlib */
+	char		s_vaddr[4];	/* virtual address		*/
+	char		s_size[4];	/* section size			*/
+	char		s_scnptr[4];	/* file ptr to raw data for section */
+	char		s_relptr[4];	/* file ptr to relocation	*/
+	char		s_lnnoptr[4];	/* file ptr to line numbers	*/
+	char		s_nreloc[2];	/* number of relocation entries	*/
+	char		s_nlnno[2];	/* number of line number entries*/
+	char		s_flags[4];	/* flags			*/
+};
+
+#define	SCNHDR	struct external_scnhdr
+#define	SCNHSZ	40
+
+/********************** LINE NUMBERS **********************/
+
+/* 1 line number entry for every "breakpointable" source line in a section.
+ * Line numbers are grouped on a per function basis; first entry in a function
+ * grouping will have l_lnno = 0 and in place of physical address will be the
+ * symbol table index of the function name.
+ */
+struct external_lineno {
+	union {
+		char l_symndx[4];	/* function name symbol index, iff l_lnno == 0*/
+		char l_paddr[4];	/* (physical) address of line number	*/
+	} l_addr;
+	char l_lnno[2];	/* line number		*/
+};
+
+
+#define	LINENO	struct external_lineno
+#define	LINESZ	6
+
+
+/********************** SYMBOLS **********************/
+
+#define E_SYMNMLEN	8	/* # characters in a symbol name	*/
+#define E_FILNMLEN	14	/* # characters in a file name		*/
+#define E_DIMNUM	4	/* # array dimensions in auxiliary entry */
+
+struct external_syment 
+{
+  union {
+    char e_name[E_SYMNMLEN];
+    struct {
+      char e_zeroes[4];
+      char e_offset[4];
+    } e;
+  } e;
+  char e_value[4];
+  char e_scnum[2];
+  char e_type[2];
+  char e_sclass[1];
+  char e_numaux[1];
+};
+
+
+
+#define N_BTMASK	(017)
+#define N_TMASK		(060)
+#define N_BTSHFT	(4)
+#define N_TSHIFT	(2)
+  
+
+union external_auxent {
+	struct {
+		char x_tagndx[4];	/* str, un, or enum tag indx */
+		union {
+			struct {
+			    char  x_lnno[2]; /* declaration line number */
+			    char  x_size[2]; /* str/union/array size */
+			} x_lnsz;
+			char x_fsize[4];	/* size of function */
+		} x_misc;
+		union {
+			struct {		/* if ISFCN, tag, or .bb */
+			    char x_lnnoptr[4];	/* ptr to fcn line # */
+			    char x_endndx[4];	/* entry ndx past block end */
+			} x_fcn;
+			struct {		/* if ISARY, up to 4 dimen. */
+			    char x_dimen[E_DIMNUM][2];
+			} x_ary;
+		} x_fcnary;
+		char x_tvndx[2];		/* tv index */
+	} x_sym;
+
+        struct {
+                union {
+                        char x_fname[E_FILNMLEN];
+                        struct {
+                                char x_zeroes[4];
+                                char x_offset[4];
+                        } x_n;
+                } x_n;
+                char x_ftype[1];
+        } x_file;
+
+	struct {
+		char x_scnlen[4];			/* section length */
+		char x_nreloc[2];	/* # relocation entries */
+		char x_nlinno[2];	/* # line numbers */
+	} x_scn;
+
+        struct {
+		char x_tvfill[4];	/* tv fill value */
+		char x_tvlen[2];	/* length of .tv */
+		char x_tvran[2][2];	/* tv range */
+	} x_tv;		/* info about .tv section (in auxent of symbol .tv)) */
+
+	struct {
+		unsigned char x_scnlen[4];
+		unsigned char x_parmhash[4];
+		unsigned char x_snhash[2];
+		unsigned char x_smtyp[1];
+		unsigned char x_smclas[1];
+		unsigned char x_stab[4];
+		unsigned char x_snstab[2];
+	} x_csect;
+
+};
+
+#define	SYMENT	struct external_syment
+#define	SYMESZ	18
+#define	AUXENT	union external_auxent
+#define	AUXESZ	18
+#define DBXMASK 0x80		/* for dbx storage mask */
+#define SYMNAME_IN_DEBUG(symptr) ((symptr)->n_sclass & DBXMASK)
+
+
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+
+struct external_reloc {
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_size[1];
+  char r_type[1];
+};
+
+
+#define RELOC struct external_reloc
+#define RELSZ 10
+
+#define DEFAULT_DATA_SECTION_ALIGNMENT 4
+#define DEFAULT_BSS_SECTION_ALIGNMENT 4
+#define DEFAULT_TEXT_SECTION_ALIGNMENT 4
+/* For new sections we havn't heard of before */
+#define DEFAULT_SECTION_ALIGNMENT 4
+
+/* The ldhdr structure.  This appears at the start of the .loader
+   section.  */
+
+struct external_ldhdr
+{
+  bfd_byte l_version[4];
+  bfd_byte l_nsyms[4];
+  bfd_byte l_nreloc[4];
+  bfd_byte l_istlen[4];
+  bfd_byte l_nimpid[4];
+  bfd_byte l_impoff[4];
+  bfd_byte l_stlen[4];
+  bfd_byte l_stoff[4];
+};
+
+#define LDHDRSZ (8 * 4)
+
+struct external_ldsym
+{
+  union
+    {
+      bfd_byte _l_name[E_SYMNMLEN];
+      struct
+	{
+	  bfd_byte _l_zeroes[4];
+	  bfd_byte _l_offset[4];
+	} _l_l;
+    } _l;
+  bfd_byte l_value[4];
+  bfd_byte l_scnum[2];
+  bfd_byte l_smtype[1];
+  bfd_byte l_smclas[1];
+  bfd_byte l_ifile[4];
+  bfd_byte l_parm[4];
+};
+
+#define LDSYMSZ (8 + 3 * 4 + 2 + 2)
+
+struct external_ldrel
+{
+  bfd_byte l_vaddr[4];
+  bfd_byte l_symndx[4];
+  bfd_byte l_rtype[2];
+  bfd_byte l_rsecnm[2];
+};
+
+#define LDRELSZ (2 * 4 + 2 * 2)
+
+struct external_exceptab
+{
+  union {
+    bfd_byte e_symndx[4];
+    bfd_byte e_paddr[4];
+  } e_addr;
+  bfd_byte e_lang[1];
+  bfd_byte e_reason[1];
+};
+
+#define EXCEPTSZ (4 + 2)
+
+/******************** Core files *************************/
+
+struct external_core_dumpx
+{
+  unsigned char c_signo[1];
+  unsigned char c_flag[1];
+  unsigned char c_entries[2];
+
+  unsigned char c_version[4];
+
+  unsigned char c_fdsinfox[8];
+  unsigned char c_loader[8];
+  unsigned char c_lsize[8];
+
+  unsigned char c_n_thr[4];
+  unsigned char c_reserved0[4];
+  unsigned char c_thr[8];
+
+  unsigned char c_segs[8];
+  unsigned char c_segregion[8];
+
+  unsigned char c_stack[8];
+  unsigned char c_stackorg[8];
+  unsigned char c_size[8];
+
+  unsigned char c_data[8];
+  unsigned char c_dataorg[8];
+  unsigned char c_datasize[8];
+  unsigned char c_sdorg[8];
+  unsigned char c_sdsize[8];
+
+  unsigned char c_vmmregions[8];
+  unsigned char c_vmm[8];
+
+  unsigned char c_impl[4];
+  unsigned char c_pad[4];
+  unsigned char c_cprs[8];
+  unsigned char c_reserved[7 * 8];
+
+  /* Followed by:
+     - context of the faulting thread.
+     - user structure.  */
+};
+
+
+/* Core file verion.  */
+#define CORE_DUMPX_VERSION 0x0feeddb1
+#define CORE_DUMPXX_VERSION 0x0feeddb2
+
+struct external_ld_info32
+{
+  unsigned char ldinfo_next[4];
+  unsigned char core_offset[4];
+  unsigned char ldinfo_textorg[4];
+  unsigned char ldinfo_textsize[4];
+  unsigned char ldinfo_dataorg[4];
+  unsigned char ldinfo_datasize[4];
+  unsigned char ldinfo_filename[2];
+};
diff --git a/binutils-2.25/include/coff/rs6k64.h b/binutils-2.25/include/coff/rs6k64.h
new file mode 100644
index 00000000..453198a5
--- /dev/null
+++ b/binutils-2.25/include/coff/rs6k64.h
@@ -0,0 +1,275 @@
+/* IBM RS/6000 "XCOFF64" file definitions for BFD.
+   Copyright (C) 2000, 2001, 2002, 2010 Free Software Foundation, Inc.  
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/********************** FILE HEADER **********************/
+
+struct external_filehdr
+{
+  char f_magic[2];	/* magic number			*/
+  char f_nscns[2];	/* number of sections		*/
+  char f_timdat[4];	/* time & date stamp		*/
+  char f_symptr[8];	/* file pointer to symtab 	*/
+  char f_opthdr[2];	/* sizeof(optional hdr)		*/
+  char f_flags[2];	/* flags			*/
+  char f_nsyms[4];	/* number of symtab entries	*/
+};
+
+/* IBM RS/6000.  */
+#define U803XTOCMAGIC 0757	/* Aix 4.3 64-bit XCOFF */
+#define	U64_TOCMAGIC  0767	/* AIX 5+ 64-bit XCOFF */
+#define BADMAG(x) ((x).f_magic != U803XTOCMAGIC && (x).f_magic != U64_TOCMAGIC)
+
+#define	FILHDR	struct external_filehdr
+#define	FILHSZ	24
+
+/********************** AOUT "OPTIONAL HEADER" **********************/
+
+typedef struct 
+{
+  unsigned char	magic[2];		/* type of file			*/
+  unsigned char	vstamp[2];		/* version stamp		*/
+  unsigned char	o_debugger[4];		/* reserved 			*/
+  unsigned char	text_start[8];		/* base of text used for this file */
+  unsigned char	data_start[8];		/* base of data used for this file */
+  unsigned char	o_toc[8];		/* address of TOC */
+  unsigned char	o_snentry[2];		/* section number of entry point */
+  unsigned char	o_sntext[2];		/* section number of .text section */
+  unsigned char	o_sndata[2];		/* section number of .data section */
+  unsigned char	o_sntoc[2];		/* section number of TOC */
+  unsigned char	o_snloader[2];		/* section number of .loader section */
+  unsigned char	o_snbss[2];		/* section number of .bss section */
+  unsigned char	o_algntext[2];		/* .text alignment */
+  unsigned char	o_algndata[2];		/* .data alignment */
+  unsigned char	o_modtype[2];		/* module type (??) */
+  unsigned char o_cputype[2];		/* cpu type */
+  unsigned char	o_resv2[4];		/* reserved 			*/
+  unsigned char	tsize[8];		/* text size bytes, padded to FW bdry */
+  unsigned char	dsize[8];		/* initialized data "  "	*/
+  unsigned char	bsize[8];		/* uninitialized data "   "	*/
+  unsigned char	entry[8];		/* entry pt.			*/
+  unsigned char	o_maxstack[8];		/* max stack size (??) 		*/
+  unsigned char o_maxdata[8];		/* max data size (??) 		*/
+  unsigned char	o_resv3[16];		/* reserved 			*/
+}
+AOUTHDR;
+
+#define AOUTSZ 120
+#define SMALL_AOUTSZ (0)
+#define AOUTHDRSZ 72
+
+/********************** SECTION HEADER **********************/
+
+struct external_scnhdr
+{
+  char	s_name[8];	/* section name			*/
+  char	s_paddr[8];	/* physical address, aliased s_nlib */
+  char	s_vaddr[8];	/* virtual address		*/
+  char	s_size[8];	/* section size			*/
+  char	s_scnptr[8];	/* file ptr to raw data for section */
+  char	s_relptr[8];	/* file ptr to relocation	*/
+  char	s_lnnoptr[8];	/* file ptr to line numbers	*/
+  char	s_nreloc[4];	/* number of relocation entries	*/
+  char	s_nlnno[4];	/* number of line number entries*/
+  char	s_flags[4];	/* flags			*/
+  char  s_pad[4];	/* padding */  
+};
+
+#define	SCNHDR	struct external_scnhdr
+
+#define	SCNHSZ	72
+
+/********************** LINE NUMBERS **********************/
+
+/* 1 line number entry for every "breakpointable" source line in a section.
+   Line numbers are grouped on a per function basis; first entry in a function
+   grouping will have l_lnno = 0 and in place of physical address will be the
+   symbol table index of the function name.  */
+
+struct external_lineno
+{
+  union
+  {
+    char l_symndx[4];	/* function name symbol index, iff l_lnno == 0*/
+    char l_paddr[8];	/* (physical) address of line number	*/
+  } l_addr;
+
+  char l_lnno[4];	/* line number		*/
+};
+
+#define	LINENO	struct external_lineno
+
+#define	LINESZ	12
+
+/********************** SYMBOLS **********************/
+
+#define E_SYMNMLEN	8	/* # characters in a symbol name	*/
+#define E_FILNMLEN	14	/* # characters in a file name		*/
+#define E_DIMNUM	4	/* # array dimensions in auxiliary entry */
+
+struct external_syment 
+{
+  char e_value[8];
+  char e_offset[4];
+  char e_scnum[2];
+  char e_type[2];
+  char e_sclass[1];
+  char e_numaux[1];
+};
+
+#define N_BTMASK	(017)
+#define N_TMASK		(060)
+#define N_BTSHFT	(4)
+#define N_TSHIFT	(2)
+
+union external_auxent
+{
+    struct {
+    	union {
+	    struct {
+		char x_lnno[4]; 	/* declaration line number */
+		char x_size[2]; 	/* str/union/array size */
+	    } x_lnsz;
+	    struct {
+		char x_lnnoptr[8];/* ptr to fcn line */
+		char x_fsize[4];	 /* size of function */
+		char x_endndx[4];	 /* entry ndx past block end */
+	    } x_fcn;
+ 	} x_fcnary;
+    } x_sym;
+         
+    struct {
+        union {
+            char x_fname[E_FILNMLEN];
+            struct {
+	        char x_zeroes[4];
+                char x_offset[4];
+	        char x_pad[6];
+            } x_n;
+        } x_n;
+        unsigned char x_ftype[1];
+        unsigned char x_resv[2];
+    } x_file;
+
+    struct {
+	char x_exptr[8];
+	char x_fsize[4];
+	char x_endndx[4];
+	char x_pad[1];
+    } x_except;
+
+    struct {
+	    unsigned char x_scnlen_lo[4];
+	    unsigned char x_parmhash[4];
+	    unsigned char x_snhash[2];
+	    unsigned char x_smtyp[1];
+	    unsigned char x_smclas[1];
+	    unsigned char x_scnlen_hi[4];
+	    unsigned char x_pad[1];
+    } x_csect;	
+
+    struct {
+	char x_pad[17];
+	char x_auxtype[1];
+    } x_auxtype;
+};
+
+#define	SYMENT	struct external_syment
+#define	SYMESZ	18	
+#define	AUXENT	union external_auxent
+#define	AUXESZ	18
+#define DBXMASK 0x80		/* for dbx storage mask */
+#define SYMNAME_IN_DEBUG(symptr) ((symptr)->n_sclass & DBXMASK)
+
+/* Values for auxtype field in XCOFF64, taken from AIX 4.3 sym.h.  */
+#define _AUX_EXCEPT     255
+#define _AUX_FCN        254
+#define _AUX_SYM        253
+#define _AUX_FILE       252
+#define _AUX_CSECT      251
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+struct external_reloc
+{
+  char r_vaddr[8];
+  char r_symndx[4];
+  char r_size[1];
+  char r_type[1];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 14
+
+#define DEFAULT_DATA_SECTION_ALIGNMENT 4
+#define DEFAULT_BSS_SECTION_ALIGNMENT 4
+#define DEFAULT_TEXT_SECTION_ALIGNMENT 4
+/* For new sections we havn't heard of before */
+#define DEFAULT_SECTION_ALIGNMENT 4
+
+/* The ldhdr structure.  This appears at the start of the .loader
+   section.  */
+
+struct external_ldhdr
+{
+  bfd_byte l_version[4];
+  bfd_byte l_nsyms[4];
+  bfd_byte l_nreloc[4];
+  bfd_byte l_istlen[4];
+  bfd_byte l_nimpid[4];
+  bfd_byte l_stlen[4];
+  bfd_byte l_impoff[8];
+  bfd_byte l_stoff[8];
+  bfd_byte l_symoff[8];
+  bfd_byte l_rldoff[8];
+};
+#define LDHDRSZ (56)
+
+struct external_ldsym
+{
+  bfd_byte l_value[8];
+  bfd_byte l_offset[4];
+  bfd_byte l_scnum[2];
+  bfd_byte l_smtype[1];
+  bfd_byte l_smclas[1];
+  bfd_byte l_ifile[4];
+  bfd_byte l_parm[4];
+};
+
+#define LDSYMSZ (24)
+
+struct external_ldrel
+{
+  bfd_byte l_vaddr[8];
+  bfd_byte l_rtype[2];
+  bfd_byte l_rsecnm[2];
+  bfd_byte l_symndx[4];
+};
+
+#define LDRELSZ (16)
+
+struct external_exceptab
+{
+  union {
+    bfd_byte e_symndx[4];
+    bfd_byte e_paddr[8];
+  } e_addr;
+  bfd_byte e_lang[1];
+  bfd_byte e_reason[1];
+};
+
+#define EXCEPTSZ (10)
diff --git a/binutils-2.25/include/coff/sh.h b/binutils-2.25/include/coff/sh.h
new file mode 100644
index 00000000..bf131046
--- /dev/null
+++ b/binutils-2.25/include/coff/sh.h
@@ -0,0 +1,148 @@
+/* coff information for Renesas SH
+   
+   Copyright 2000, 2003, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifdef COFF_WITH_PE
+#define L_LNNO_SIZE 2
+#else
+#define L_LNNO_SIZE 4
+#endif
+#define INCLUDE_COMDAT_FIELDS_IN_AUXENT
+#include "coff/external.h"
+
+#define	SH_ARCH_MAGIC_BIG	0x0500
+#define	SH_ARCH_MAGIC_LITTLE	0x0550  /* Little endian SH */
+#define SH_ARCH_MAGIC_WINCE	0x01a2  /* Windows CE - little endian */
+#define SH_PE_MAGIC		0x010b
+
+#define SHBADMAG(x) \
+ (((x).f_magic != SH_ARCH_MAGIC_BIG) && \
+  ((x).f_magic != SH_ARCH_MAGIC_WINCE) && \
+  ((x).f_magic != SH_ARCH_MAGIC_LITTLE))
+
+/* Define some NT default values.  */
+/*  #define NT_IMAGE_BASE        0x400000 moved to internal.h */
+#define NT_SECTION_ALIGNMENT 0x1000
+#define NT_FILE_ALIGNMENT    0x200
+#define NT_DEF_RESERVE       0x100000
+#define NT_DEF_COMMIT        0x1000
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+/* The external reloc has an offset field, because some of the reloc
+   types on the h8 don't have room in the instruction for the entire
+   offset - eg the strange jump and high page addressing modes.  */
+
+#ifndef COFF_WITH_PE
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_offset[4];
+  char r_type[2];
+  char r_stuff[2];
+};
+#else
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+};
+#endif
+
+#define RELOC struct external_reloc
+#ifdef COFF_WITH_PE
+#define RELSZ 10
+#else
+#define RELSZ 16
+#endif
+
+/* SH relocation types.  Not all of these are actually used.  */
+
+#define R_SH_UNUSED	0		/* only used internally */
+#define R_SH_IMM32CE	2		/* 32 bit immediate for WinCE */
+#define R_SH_PCREL8 	3		/*  8 bit pcrel 	*/
+#define R_SH_PCREL16 	4		/* 16 bit pcrel 	*/
+#define R_SH_HIGH8  	5		/* high 8 bits of 24 bit address */
+#define R_SH_LOW16 	7		/* low 16 bits of 24 bit immediate */
+#define R_SH_IMM24	6		/* 24 bit immediate */
+#define R_SH_PCDISP8BY4	9  		/* PC rel 8 bits *4 +ve */
+#define R_SH_PCDISP8BY2	10  		/* PC rel 8 bits *2 +ve */
+#define R_SH_PCDISP8    11  		/* 8 bit branch */
+#define R_SH_PCDISP     12  		/* 12 bit branch */
+#define R_SH_IMM32      14    		/* 32 bit immediate */
+#define R_SH_IMM8   	16		/* 8 bit immediate */
+#define R_SH_IMAGEBASE	16		/* Windows CE */
+#define R_SH_IMM8BY2    17		/* 8 bit immediate *2 */
+#define R_SH_IMM8BY4    18		/* 8 bit immediate *4 */
+#define R_SH_IMM4   	19		/* 4 bit immediate */
+#define R_SH_IMM4BY2    20		/* 4 bit immediate *2 */
+#define R_SH_IMM4BY4    21		/* 4 bit immediate *4 */
+#define R_SH_PCRELIMM8BY2   22		/* PC rel 8 bits *2 unsigned */
+#define R_SH_PCRELIMM8BY4   23		/* PC rel 8 bits *4 unsigned */
+#define R_SH_IMM16      24    		/* 16 bit immediate */
+
+/* The switch table reloc types are used for relaxing.  They are
+   generated for expressions such as
+     .word L1 - L2
+   The r_offset field holds the difference between the reloc address
+   and L2.  */
+#define R_SH_SWITCH8	33		/* 8 bit switch table entry */
+#define R_SH_SWITCH16	25		/* 16 bit switch table entry */
+#define R_SH_SWITCH32	26		/* 32 bit switch table entry */
+
+/* The USES reloc type is used for relaxing.  The compiler will
+   generate .uses pseudo-ops when it finds a function call which it
+   can relax.  The r_offset field of the USES reloc holds the PC
+   relative offset to the instruction which loads the register used in
+   the function call.  */
+#define R_SH_USES	27		/* .uses pseudo-op */
+
+/* The COUNT reloc type is used for relaxing.  The assembler will
+   generate COUNT relocs for addresses referred to by the register
+   loads associated with USES relocs.  The r_offset field of the COUNT
+   reloc holds the number of times the address is referenced in the
+   object file.  */
+#define R_SH_COUNT	28		/* Count of constant pool uses */
+
+/* The ALIGN reloc type is used for relaxing.  The r_offset field is
+   the power of two to which subsequent portions of the object file
+   must be aligned.  */
+#define R_SH_ALIGN	29		/* .align pseudo-op */
+
+/* The CODE and DATA reloc types are used for aligning load and store
+   instructions.  The assembler will generate a CODE reloc before a
+   block of instructions.  It will generate a DATA reloc before data.
+   A section should be processed assuming it contains data, unless a
+   CODE reloc is seen.  The only relevant pieces of information in the
+   CODE and DATA relocs are the section and the address.  The symbol
+   and offset are meaningless.  */
+#define R_SH_CODE	30		/* start of code */
+#define R_SH_DATA	31		/* start of data */
+
+/* The LABEL reloc type is used for aligning load and store
+   instructions.  The assembler will generate a LABEL reloc for each
+   label within a block of instructions.  This permits the linker to
+   avoid swapping instructions which are the targets of branches.  */
+#define R_SH_LABEL	32		/* label */
+
+/* NB: R_SH_SWITCH8 is 33 */
+
+#define R_SH_LOOP_START	34
+#define R_SH_LOOP_END	35
diff --git a/binutils-2.25/include/coff/sparc.h b/binutils-2.25/include/coff/sparc.h
new file mode 100644
index 00000000..fa94c5f7
--- /dev/null
+++ b/binutils-2.25/include/coff/sparc.h
@@ -0,0 +1,156 @@
+/* coff information for Sparc.
+   
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file is an amalgamation of several standard include files that
+   define coff format, such as filehdr.h, aouthdr.h, and so forth.  In
+   addition, all datatypes have been translated into character arrays of
+   (presumed) equivalent size.  This is necessary so that this file can
+   be used with different systems while still yielding the same results.  */
+
+#define L_LNNO_SIZE 2
+#define DO_NOT_DEFINE_SYMENT
+#define DO_NOT_DEFINE_AUXENT
+#include "coff/external.h"
+
+#define F_RELFLG	(0x0001)	/* relocation info stripped */
+#define F_EXEC		(0x0002)	/* file is executable */
+#define F_LNNO		(0x0004)	/* line numbers stripped */
+#define F_LSYMS		(0x0008)	/* local symbols stripped */
+
+#define SPARCMAGIC	(0540)
+
+/* This is Lynx's all-platform magic number for executables. */
+
+#define LYNXCOFFMAGIC	(0415)
+
+#define OMAGIC          0404    /* object files, eg as output */
+#define ZMAGIC          0413    /* demand load format, eg normal ld output */
+#define STMAGIC		0401	/* target shlib */
+#define SHMAGIC		0443	/* host   shlib */
+
+/* More names of "special" sections. */
+
+#define _TV	".tv"
+#define _INIT	".init"
+#define _FINI	".fini"
+
+/********************** SYMBOLS **********************/
+
+#define E_SYMNMLEN	(8)	/* # characters in a symbol name	*/
+#define E_FILNMLEN	(14)	/* # characters in a file name		*/
+#define E_DIMNUM	(4)	/* # array dimensions in auxiliary entry */
+
+struct external_syment 
+{
+  union {
+    char e_name[E_SYMNMLEN];
+    struct {
+      char e_zeroes[4];
+      char e_offset[4];
+    } e;
+#if 0 /* of doubtful value */
+    char e_nptr[2][4];
+    struct {
+      char e_leading_zero[1];
+      char e_dbx_type[1];
+      char e_dbx_desc[2];
+    } e_dbx;
+#endif
+  } e;
+
+  char e_value[4];
+  char e_scnum[2];
+  char e_type[2];
+  char e_sclass[1];
+  char e_numaux[1];
+  char padding[2];
+};
+
+#define N_BTMASK	(0xf)
+#define N_TMASK		(0x30)
+#define N_BTSHFT	(4)
+#define N_TSHIFT	(2)
+  
+union external_auxent
+{
+  struct {
+    char x_tagndx[4];		/* str, un, or enum tag indx */
+    union {
+      struct {
+	char  x_lnno[2];	/* declaration line number */
+	char  x_size[2];	/* str/union/array size */
+      } x_lnsz;
+      char x_fsize[4];		/* size of function */
+    } x_misc;
+    union {
+      struct {			/* if ISFCN, tag, or .bb */
+	char x_lnnoptr[4];	/* ptr to fcn line # */
+	char x_endndx[4];	/* entry ndx past block end */
+      } x_fcn;
+      struct {		/* if ISARY, up to 4 dimen. */
+	char x_dimen[E_DIMNUM][2];
+      } x_ary;
+    } x_fcnary;
+    char x_tvndx[2];		/* tv index */
+  } x_sym;
+  
+  union {
+    char x_fname[E_FILNMLEN];
+    struct {
+      char x_zeroes[4];
+      char x_offset[4];
+    } x_n;
+  } x_file;
+  
+  struct {
+    char x_scnlen[4];		/* section length */
+    char x_nreloc[2];		/* # relocation entries */
+    char x_nlinno[2];		/* # line numbers */
+  } x_scn;
+  
+  struct {
+    char x_tvfill[4];		/* tv fill value */
+    char x_tvlen[2];		/* length of .tv */
+    char x_tvran[2][2];		/* tv range */
+  } x_tv;			/* .tv section info (in auxent of sym .tv)) */
+
+  char x_fill[20];		/* forces to 20-byte size */
+};
+
+#define	SYMENT	struct external_syment
+#define	SYMESZ	20	
+#define	AUXENT	union external_auxent
+#define	AUXESZ	20
+
+#define _ETEXT	"etext"
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+  char r_spare[2];
+  char r_offset[4];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 16
+
diff --git a/binutils-2.25/include/coff/sym.h b/binutils-2.25/include/coff/sym.h
new file mode 100644
index 00000000..76204af5
--- /dev/null
+++ b/binutils-2.25/include/coff/sym.h
@@ -0,0 +1,484 @@
+/* Declarations of internal format of MIPS ECOFF symbols.
+   Originally contributed by MIPS Computer Systems and Third Eye Software.
+   Changes contributed by Cygnus Support are in the public domain.  
+
+   This file is just aggregated with the files that make up the GNU
+   release; it is not considered part of GAS, GDB, or other GNU
+   programs.  */
+
+/*
+ * |-----------------------------------------------------------|
+ * | Copyright (c) 1992, 1991, 1990 MIPS Computer Systems, Inc.|
+ * | MIPS Computer Systems, Inc. grants reproduction and use   |
+ * | rights to all parties, PROVIDED that this comment is      |
+ * | maintained in the copy.                                   |
+ * |-----------------------------------------------------------|
+ */
+#ifndef _SYM_H
+#define _SYM_H
+
+/* (C) Copyright 1984 by Third Eye Software, Inc.
+ *
+ * Third Eye Software, Inc. grants reproduction and use rights to
+ * all parties, PROVIDED that this comment is maintained in the copy.
+ *
+ * Third Eye makes no claims about the applicability of this
+ * symbol table to a particular use.
+ */
+
+/* 
+ * This file contains the definition of the Third Eye Symbol Table.
+ *
+ * Symbols are assumed to be in 'encounter order' - i.e. the order that
+ * the things they represent were encountered by the compiler/assembler/loader.
+ * EXCEPT for globals!	These are assumed to be bunched together,
+ * probably right after the last 'normal' symbol.  Globals ARE sorted
+ * in ascending order.
+ *
+ * -----------------------------------------------------------------------
+ * A brief word about Third Eye naming/use conventions:
+ *
+ * All arrays and index's are 0 based.
+ * All "ifooMax" values are the highest legal value PLUS ONE. This makes
+ * them good for allocating arrays, etc. All checks are "ifoo < ifooMax".
+ *
+ * "isym"	Index into the SYMbol table.
+ * "ipd"	Index into the Procedure Descriptor array.
+ * "ifd"	Index into the File Descriptor array.
+ * "iss"	Index into String Space.
+ * "cb"		Count of Bytes.
+ * "rgPd"	array whose domain is "0..ipdMax-1" and RanGe is PDR.
+ * "rgFd"	array whose domain is "0..ifdMax-1" and RanGe is FDR.
+ */
+
+
+/* 
+ * Symbolic Header (HDR) structure.
+ * As long as all the pointers are set correctly,
+ * we don't care WHAT order the various sections come out in!
+ *
+ * A file produced solely for the use of CDB will probably NOT have
+ * any instructions or data areas in it, as these are available
+ * in the original.
+ */
+
+typedef struct {
+	short	magic;		/* to verify validity of the table */
+	short	vstamp;		/* version stamp */
+	long	ilineMax;	/* number of line number entries */
+	bfd_vma	cbLine;		/* number of bytes for line number entries */
+	bfd_vma	cbLineOffset;	/* offset to start of line number entries*/
+	long	idnMax;		/* max index into dense number table */
+	bfd_vma	cbDnOffset;	/* offset to start dense number table */
+	long	ipdMax;		/* number of procedures */
+	bfd_vma	cbPdOffset;	/* offset to procedure descriptor table */
+	long	isymMax;	/* number of local symbols */
+	bfd_vma	cbSymOffset;	/* offset to start of local symbols*/
+	long	ioptMax;	/* max index into optimization symbol entries */
+	bfd_vma	cbOptOffset;	/* offset to optimization symbol entries */
+	long	iauxMax;	/* number of auxillary symbol entries */
+	bfd_vma	cbAuxOffset;	/* offset to start of auxillary symbol entries*/
+	long	issMax;		/* max index into local strings */
+	bfd_vma	cbSsOffset;	/* offset to start of local strings */
+	long	issExtMax;	/* max index into external strings */
+	bfd_vma	cbSsExtOffset;	/* offset to start of external strings */
+	long	ifdMax;		/* number of file descriptor entries */
+	bfd_vma	cbFdOffset;	/* offset to file descriptor table */
+	long	crfd;		/* number of relative file descriptor entries */
+	bfd_vma	cbRfdOffset;	/* offset to relative file descriptor table */
+	long	iextMax;	/* max index into external symbols */
+	bfd_vma	cbExtOffset;	/* offset to start of external symbol entries*/
+	/* If you add machine dependent fields, add them here */
+	} HDRR, *pHDRR; 
+#define cbHDRR sizeof(HDRR)
+#define hdrNil ((pHDRR)0)
+
+/*
+ * The FDR and PDR structures speed mapping of address <-> name.
+ * They are sorted in ascending memory order and are kept in
+ * memory by CDB at runtime.
+ */
+
+/* 
+ * File Descriptor
+ *
+ * There is one of these for EVERY FILE, whether compiled with
+ * full debugging symbols or not.  The name of a file should be
+ * the path name given to the compiler.	 This allows the user
+ * to simply specify the names of the directories where the COMPILES
+ * were done, and we will be able to find their files.
+ * A field whose comment starts with "R - " indicates that it will be
+ * setup at runtime.
+ */
+typedef struct fdr {
+	bfd_vma	adr;		/* memory address of beginning of file */
+	long	rss;		/* file name (of source, if known) */
+	long	issBase;	/* file's string space */
+	bfd_vma	cbSs;		/* number of bytes in the ss */
+	long	isymBase;	/* beginning of symbols */
+	long	csym;		/* count file's of symbols */
+	long	ilineBase;	/* file's line symbols */
+	long	cline;		/* count of file's line symbols */
+	long	ioptBase;	/* file's optimization entries */
+	long	copt;		/* count of file's optimization entries */
+	unsigned short ipdFirst;/* start of procedures for this file */
+	short	cpd;		/* count of procedures for this file */
+	long	iauxBase;	/* file's auxiliary entries */
+	long	caux;		/* count of file's auxiliary entries */
+	long	rfdBase;	/* index into the file indirect table */
+	long	crfd;		/* count file indirect entries */
+	unsigned lang: 5;	/* language for this file */
+	unsigned fMerge : 1;	/* whether this file can be merged */
+	unsigned fReadin : 1;	/* true if it was read in (not just created) */
+	unsigned fBigendian : 1;/* if set, was compiled on big endian machine */
+				/*	aux's will be in compile host's sex */
+	unsigned glevel : 2;	/* level this file was compiled with */
+	unsigned reserved : 22;  /* reserved for future use */
+	bfd_vma	cbLineOffset;	/* byte offset from header for this file ln's */
+	bfd_vma	cbLine;		/* size of lines for this file */
+	} FDR, *pFDR;
+#define cbFDR sizeof(FDR)
+#define fdNil ((pFDR)0)
+#define ifdNil -1
+#define ifdTemp 0
+#define ilnNil -1
+
+
+/* 
+ * Procedure Descriptor
+ *
+ * There is one of these for EVERY TEXT LABEL.
+ * If a procedure is in a file with full symbols, then isym
+ * will point to the PROC symbols, else it will point to the
+ * global symbol for the label.
+ */
+
+typedef struct pdr {
+	bfd_vma	adr;		/* memory address of start of procedure */
+	long	isym;		/* start of local symbol entries */
+	long	iline;		/* start of line number entries*/
+	long	regmask;	/* save register mask */
+	long	regoffset;	/* save register offset */
+	long	iopt;		/* start of optimization symbol entries*/
+	long	fregmask;	/* save floating point register mask */
+	long	fregoffset;	/* save floating point register offset */
+	long	frameoffset;	/* frame size */
+	short	framereg;	/* frame pointer register */
+	short	pcreg;		/* offset or reg of return pc */
+	long	lnLow;		/* lowest line in the procedure */
+	long	lnHigh;		/* highest line in the procedure */
+	bfd_vma	cbLineOffset;	/* byte offset for this procedure from the fd base */
+	/* These fields are new for 64 bit ECOFF.  */
+	unsigned gp_prologue : 8; /* byte size of GP prologue */
+	unsigned gp_used : 1;	/* true if the procedure uses GP */
+	unsigned reg_frame : 1;	/* true if register frame procedure */
+	unsigned prof : 1;	/* true if compiled with -pg */
+	unsigned reserved : 13;	/* reserved: must be zero */
+	unsigned localoff : 8;	/* offset of local variables from vfp */
+	} PDR, *pPDR;
+#define cbPDR sizeof(PDR)
+#define pdNil ((pPDR) 0)
+#define ipdNil	-1
+
+/*
+ * The structure of the runtime procedure descriptor created by the loader
+ * for use by the static exception system.
+ */
+/*
+ * If 0'd out because exception_info chokes Visual C++ and because there
+ * don't seem to be any references to this structure elsewhere in gdb.
+ */
+#if 0
+typedef struct runtime_pdr {
+	bfd_vma	adr;		/* memory address of start of procedure */
+	long	regmask;	/* save register mask */
+	long	regoffset;	/* save register offset */
+	long	fregmask;	/* save floating point register mask */
+	long	fregoffset;	/* save floating point register offset */
+	long	frameoffset;	/* frame size */
+	short	framereg;	/* frame pointer register */
+	short	pcreg;		/* offset or reg of return pc */
+	long	irpss;		/* index into the runtime string table */
+	long	reserved;
+	struct exception_info *exception_info;/* pointer to exception array */
+} RPDR, *pRPDR;
+#define cbRPDR sizeof(RPDR)
+#define rpdNil ((pRPDR) 0)
+#endif
+
+/*
+ * Line Numbers
+ *
+ * Line Numbers are segregated from the normal symbols because they
+ * are [1] smaller , [2] are of no interest to your
+ * average loader, and [3] are never needed in the middle of normal
+ * scanning and therefore slow things down.
+ *
+ * By definition, the first LINER for any given procedure will have
+ * the first line of a procedure and represent the first address.
+ */
+
+typedef	long LINER, *pLINER;
+#define lineNil ((pLINER)0)
+#define cbLINER sizeof(LINER)
+#define ilineNil	-1
+
+
+
+/*
+ * The Symbol Structure		(GFW, to those who Know!)
+ */
+
+typedef struct {
+	long	iss;		/* index into String Space of name */
+	bfd_vma	value;		/* value of symbol */
+	unsigned st : 6;	/* symbol type */
+	unsigned sc  : 5;	/* storage class - text, data, etc */
+	unsigned reserved : 1;	/* reserved */
+	unsigned index : 20;	/* index into sym/aux table */
+	} SYMR, *pSYMR;
+#define symNil ((pSYMR)0)
+#define cbSYMR sizeof(SYMR)
+#define isymNil -1
+#define indexNil 0xfffff
+#define issNil -1
+#define issNull 0
+
+
+/* The following converts a memory resident string to an iss.
+ * This hack is recognized in SbFIss, in sym.c of the debugger.
+ */
+#define IssFSb(sb) (0x80000000 | ((unsigned long)(sb)))
+
+/* E X T E R N A L   S Y M B O L  R E C O R D
+ *
+ *	Same as the SYMR except it contains file context to determine where
+ *	the index is.
+ */
+typedef struct ecoff_extr {
+	unsigned jmptbl:1;	/* symbol is a jump table entry for shlibs */
+	unsigned cobol_main:1;	/* symbol is a cobol main procedure */
+	unsigned weakext:1;	/* symbol is weak external */
+	unsigned reserved:13;	/* reserved for future use */
+	int	ifd;		/* where the iss and index fields point into */
+	SYMR	asym;		/* symbol for the external */
+	} EXTR, *pEXTR;
+#define extNil ((pEXTR)0)
+#define cbEXTR sizeof(EXTR)
+
+
+/* A U X I L L A R Y   T Y P E	 I N F O R M A T I O N */
+
+/*
+ * Type Information Record
+ */
+typedef struct {
+	unsigned fBitfield : 1; /* set if bit width is specified */
+	unsigned continued : 1; /* indicates additional TQ info in next AUX */
+	unsigned bt  : 6;	/* basic type */
+	unsigned tq4 : 4;
+	unsigned tq5 : 4;
+	/* ---- 16 bit boundary ---- */
+	unsigned tq0 : 4;
+	unsigned tq1 : 4;	/* 6 type qualifiers - tqPtr, etc. */
+	unsigned tq2 : 4;
+	unsigned tq3 : 4;
+	} TIR, *pTIR;
+#define cbTIR sizeof(TIR)
+#define tiNil ((pTIR)0)
+#define itqMax 6
+
+/*
+ * Relative symbol record
+ *
+ * If the rfd field is 4095, the index field indexes into the global symbol
+ *	table.
+ */
+
+typedef struct {
+	unsigned	rfd : 12;    /* index into the file indirect table */
+	unsigned	index : 20; /* index int sym/aux/iss tables */
+	} RNDXR, *pRNDXR;
+#define cbRNDXR sizeof(RNDXR)
+#define rndxNil ((pRNDXR)0)
+
+/* dense numbers or sometimes called block numbers are stored in this type,
+ *	a rfd of 0xffffffff is an index into the global table.
+ */
+typedef struct {
+	unsigned long	rfd;    /* index into the file table */
+	unsigned long	index; 	/* index int sym/aux/iss tables */
+	} DNR, *pDNR;
+#define cbDNR sizeof(DNR)
+#define dnNil ((pDNR)0)
+
+
+
+/*
+ * Auxillary information occurs only if needed.
+ * It ALWAYS occurs in this order when present.
+
+	    isymMac		used by stProc only
+	    TIR			type info
+	    TIR			additional TQ info (if first TIR was not enough)
+	    rndx		if (bt == btStruct,btUnion,btEnum,btSet,btRange,
+				    btTypedef):
+				    rsym.index == iaux for btSet or btRange
+				    else rsym.index == isym
+	    dimLow		btRange, btSet
+	    dimMac		btRange, btSet
+	    rndx0		As many as there are tq arrays
+	    dimLow0
+	    dimHigh0
+	    ...
+	    rndxMax-1
+	    dimLowMax-1
+	    dimHighMax-1
+	    width in bits	if (bit field), width in bits.
+ */
+#define cAuxMax (6 + (idimMax*3))
+
+/* a union of all possible info in the AUX universe */
+typedef union {
+	TIR	ti;		/* type information record */
+	RNDXR	rndx;		/* relative index into symbol table */
+	long	dnLow;		/* low dimension */
+	long	dnHigh;		/* high dimension */
+	long	isym;		/* symbol table index (end of proc) */
+	long	iss;		/* index into string space (not used) */
+	long	width;		/* width for non-default sized struc fields */
+	long	count;		/* count of ranges for variant arm */
+	} AUXU, *pAUXU;
+#define cbAUXU sizeof(AUXU)
+#define auxNil ((pAUXU)0)
+#define iauxNil -1
+
+
+/*
+ * Optimization symbols
+ *
+ * Optimization symbols contain some overlap information with the normal
+ * symbol table. In particular, the proc information
+ * is somewhat redundant but necessary to easily find the other information
+ * present. 
+ *
+ * All of the offsets are relative to the beginning of the last otProc
+ */
+
+typedef struct {
+	unsigned ot: 8;		/* optimization type */
+	unsigned value: 24;	/* address where we are moving it to */
+	RNDXR	rndx;		/* points to a symbol or opt entry */
+	unsigned long	offset;	/* relative offset this occured */
+	} OPTR, *pOPTR;
+#define optNil	((pOPTR) 0)
+#define cbOPTR sizeof(OPTR)
+#define ioptNil -1
+
+/*
+ * File Indirect
+ *
+ * When a symbol is referenced across files the following procedure is used:
+ *	1) use the file index to get the File indirect entry.
+ *	2) use the file indirect entry to get the File descriptor.
+ *	3) add the sym index to the base of that file's sym table
+ *
+ */
+
+typedef long RFDT, *pRFDT;
+#define cbRFDT sizeof(RFDT)
+#define rfdNil	-1
+
+/*
+ * The file indirect table in the mips loader is known as an array of FITs.
+ * This is done to keep the code in the loader readable in the area where
+ * these tables are merged.  Note this is only a name change.
+ */
+typedef long FIT, *pFIT;
+#define cbFIT	sizeof(FIT)
+#define ifiNil	-1
+#define fiNil	((pFIT) 0)
+
+#ifdef _LANGUAGE_PASCAL
+#define ifdNil -1
+#define ilnNil -1
+#define ipdNil -1
+#define ilineNil -1
+#define isymNil -1
+#define indexNil 16#fffff
+#define issNil -1
+#define issNull 0
+#define itqMax 6
+#define iauxNil -1
+#define ioptNil -1
+#define rfdNil -1
+#define ifiNil -1
+#endif	/* _LANGUAGE_PASCAL */
+
+
+/* Dense numbers
+ *
+ * Rather than use file index, symbol index pairs to represent symbols
+ *	and globals, we use dense number so that they can be easily embeded
+ *	in intermediate code and the programs that process them can
+ *	use direct access tabls instead of hash table (which would be
+ *	necesary otherwise because of the sparse name space caused by
+ *	file index, symbol index pairs. Dense number are represented
+ *	by RNDXRs.
+ */
+
+/*
+ * The following table defines the meaning of each SYM field as
+ * a function of the "st". (scD/B == scData OR scBss)
+ *
+ * Note: the value "isymMac" is used by symbols that have the concept
+ * of enclosing a block of related information.	 This value is the
+ * isym of the first symbol AFTER the end associated with the primary
+ * symbol. For example if a procedure was at isym==90 and had an
+ * isymMac==155, the associated end would be at isym==154, and the
+ * symbol at 155 would probably (although not necessarily) be the
+ * symbol for the next procedure.  This allows rapid skipping over
+ * internal information of various sorts. "stEnd"s ALWAYS have the
+ * isym of the primary symbol that started the block.
+ * 
+
+ST		SC	VALUE		INDEX
+--------	------	--------	------
+stFile		scText	address		isymMac
+stLabel		scText	address		---
+stGlobal	scD/B	address		iaux
+stStatic	scD/B	address		iaux
+stParam		scAbs	offset		iaux
+stLocal		scAbs	offset		iaux
+stProc		scText	address		iaux	(isymMac is first AUX)
+stStaticProc	scText	address		iaux	(isymMac is first AUX)
+
+stMember	scNil	ordinal		---	(if member of enum)
+	(mipsread thinks the case below has a bit, not byte, offset.)
+stMember	scNil	byte offset	iaux	(if member of struct/union)
+stMember	scBits	bit offset	iaux	(bit field spec)
+
+stBlock		scText	address		isymMac (text block)
+	(the code seems to think that rather than scNil, we see scInfo for
+	 the two cases below.)
+stBlock		scNil	cb		isymMac (struct/union member define)
+stBlock		scNil	cMembers	isymMac (enum member define)
+
+	(New types added by SGI to simplify things:)
+stStruct	scInfo	cb		isymMac (struct type define)
+stUnion		scInfo	cb		isymMac (union  type define)
+stEnum		scInfo	cMembers	isymMac (enum   type define)
+
+stEnd		scText	address		isymStart
+stEnd		scNil	-------		isymStart (struct/union/enum)
+
+stTypedef	scNil	-------		iaux
+stRegReloc	sc???	value		old register number
+stForward	sc???	new address	isym to original symbol
+
+stConstant	scInfo	value		--- (scalar)
+stConstant	scInfo	iss		--- (complex, e.g. string)
+
+ *
+ */
+#endif
diff --git a/binutils-2.25/include/coff/symconst.h b/binutils-2.25/include/coff/symconst.h
new file mode 100644
index 00000000..ac62ba22
--- /dev/null
+++ b/binutils-2.25/include/coff/symconst.h
@@ -0,0 +1,184 @@
+/* Declarations of constants for internal format of MIPS ECOFF symbols.
+   Originally contributed by MIPS Computer Systems and Third Eye Software.
+   Changes contributed by Cygnus Support are in the public domain.
+
+   This file is just aggregated with the files that make up the GNU
+   release; it is not considered part of GAS, GDB, or other GNU
+   programs.  */
+
+/*
+ * |-----------------------------------------------------------|
+ * | Copyright (c) 1992, 1991, 1990 MIPS Computer Systems, Inc.|
+ * | MIPS Computer Systems, Inc. grants reproduction and use   |
+ * | rights to all parties, PROVIDED that this comment is      |
+ * | maintained in the copy.                                   |
+ * |-----------------------------------------------------------|
+ */
+
+/* (C) Copyright 1984 by Third Eye Software, Inc.
+ *
+ * Third Eye Software, Inc. grants reproduction and use rights to
+ * all parties, PROVIDED that this comment is maintained in the copy.
+ *
+ * Third Eye makes no claims about the applicability of this
+ * symbol table to a particular use.
+ */
+
+/* glevels for field in FDR */
+#define GLEVEL_0	2
+#define GLEVEL_1	1
+#define GLEVEL_2	0	/* for upward compat reasons. */
+#define GLEVEL_3	3
+
+/* magic number fo symheader */
+#define magicSym	0x7009
+/* The Alpha uses this value instead, for some reason.  */
+#define magicSym2	0x1992
+
+/* Language codes */
+#define langC		0	
+#define langPascal	1
+#define langFortran	2
+#define	langAssembler	3	/* one Assembley inst might map to many mach */
+#define langMachine	4
+#define langNil		5
+#define langAda		6
+#define langPl1		7
+#define langCobol	8
+#define langStdc	9	/* FIXME: Collides with SGI langCplusplus */
+#define langCplusplus	9	/* FIXME: Collides with langStdc */
+#define langCplusplusV2	10	/* SGI addition */
+#define langMax		11	/* maximum allowed 32 -- 5 bits */
+
+/* The following are value definitions for the fields in the SYMR */
+
+/*
+ * Storage Classes
+ */
+
+#define scNil		0
+#define scText		1	/* text symbol */
+#define scData		2	/* initialized data symbol */
+#define scBss		3	/* un-initialized data symbol */
+#define scRegister	4	/* value of symbol is register number */
+#define scAbs		5	/* value of symbol is absolute */
+#define scUndefined	6	/* who knows? */
+#define scCdbLocal	7	/* variable's value is IN se->va.?? */
+#define scBits		8	/* this is a bit field */
+#define scCdbSystem	9	/* variable's value is IN CDB's address space */
+#define scDbx		9	/* overlap dbx internal use */
+#define scRegImage	10	/* register value saved on stack */
+#define scInfo		11	/* symbol contains debugger information */
+#define scUserStruct	12	/* address in struct user for current process */
+#define scSData		13	/* load time only small data */
+#define scSBss		14	/* load time only small common */
+#define scRData		15	/* load time only read only data */
+#define scVar		16	/* Var parameter (fortran,pascal) */
+#define scCommon	17	/* common variable */
+#define scSCommon	18	/* small common */
+#define scVarRegister	19	/* Var parameter in a register */
+#define scVariant	20	/* Variant record */
+#define scSUndefined	21	/* small undefined(external) data */
+#define scInit		22	/* .init section symbol */
+#define scBasedVar	23	/* Fortran or PL/1 ptr based var */ 
+#define scXData         24      /* exception handling data */
+#define scPData         25      /* Procedure section */
+#define scFini          26      /* .fini section */
+#define scRConst	27	/* .rconst section */
+#define scMax		32
+
+
+/*
+ *   Symbol Types
+ */
+
+#define stNil		0	/* Nuthin' special */
+#define stGlobal	1	/* external symbol */
+#define stStatic	2	/* static */
+#define stParam		3	/* procedure argument */
+#define stLocal		4	/* local variable */
+#define stLabel		5	/* label */
+#define stProc		6	/*     "      "	 Procedure */
+#define stBlock		7	/* beginnning of block */
+#define stEnd		8	/* end (of anything) */
+#define stMember	9	/* member (of anything	- struct/union/enum */
+#define stTypedef	10	/* type definition */
+#define stFile		11	/* file name */
+#define stRegReloc	12	/* register relocation */
+#define stForward	13	/* forwarding address */
+#define stStaticProc	14	/* load time only static procs */
+#define stConstant	15	/* const */
+#define stStaParam	16	/* Fortran static parameters */
+    /* These new symbol types have been recently added to SGI machines. */
+#define stStruct	26	/* Beginning of block defining a struct type */
+#define stUnion		27	/* Beginning of block defining a union type */
+#define stEnum		28	/* Beginning of block defining an enum type */
+#define stIndirect	34	/* Indirect type specification */
+    /* Pseudo-symbols - internal to debugger */
+#define stStr		60	/* string */
+#define stNumber	61	/* pure number (ie. 4 NOR 2+2) */
+#define stExpr		62	/* 2+2 vs. 4 */
+#define stType		63	/* post-coersion SER */
+#define stMax		64
+
+/* definitions for fields in TIR */
+
+/* type qualifiers for ti.tq0 -> ti.(itqMax-1) */
+#define tqNil	0	/* bt is what you see */
+#define tqPtr	1	/* pointer */
+#define tqProc	2	/* procedure */
+#define tqArray 3	/* duh */
+#define tqFar	4	/* longer addressing - 8086/8 land */
+#define tqVol	5	/* volatile */
+#define tqConst 6	/* const */
+#define tqMax	8
+
+/* basic types as seen in ti.bt */
+#define btNil		0	/* undefined (also, enum members) */
+#define btAdr		1	/* address - integer same size as pointer */
+#define btChar		2	/* character */
+#define btUChar		3	/* unsigned character */
+#define btShort		4	/* short */
+#define btUShort	5	/* unsigned short */
+#define btInt		6	/* int */
+#define btUInt		7	/* unsigned int */
+#define btLong		8	/* long */
+#define btULong		9	/* unsigned long */
+#define btFloat		10	/* float (real) */
+#define btDouble	11	/* Double (real) */
+#define btStruct	12	/* Structure (Record) */
+#define btUnion		13	/* Union (variant) */
+#define btEnum		14	/* Enumerated */
+#define btTypedef	15	/* defined via a typedef, isymRef points */
+#define btRange		16	/* subrange of int */
+#define btSet		17	/* pascal sets */
+#define btComplex	18	/* fortran complex */
+#define btDComplex	19	/* fortran double complex */
+#define btIndirect	20	/* forward or unnamed typedef */
+#define btFixedDec	21	/* Fixed Decimal */
+#define btFloatDec	22	/* Float Decimal */
+#define btString	23	/* Varying Length Character String */
+#define btBit		24	/* Aligned Bit String */
+#define btPicture	25	/* Picture */
+#define btVoid		26	/* void */
+#define btLongLong	27	/* long long */
+#define btULongLong	28	/* unsigned long long */
+#define btLong64	30	/* long (64-bit) */
+#define btULong64	31	/* unsigned long (64-bit) */
+#define btLongLong64	32	/* long long (64-bit) */
+#define btULongLong64	33	/* unsigned long long (64-bit) */
+#define btAdr64		34	/* address (64-bit) */
+#define btInt64		35	/* int (64-bit) */
+#define btUInt64	36	/* unsigned int (64-bit) */
+#define btMax		64
+
+#if (_MFG == _MIPS)
+/* optimization type codes */
+#define otNil		0
+#define otReg		1	/* move var to reg */
+#define otBlock		2	/* begin basic block */
+#define	otProc		3	/* procedure */
+#define otInline	4	/* inline procedure */
+#define otEnd		5	/* whatever you started */
+#define otMax		6	/* KEEP UP TO DATE */
+#endif /* (_MFG == _MIPS) */
diff --git a/binutils-2.25/include/coff/ti.h b/binutils-2.25/include/coff/ti.h
new file mode 100644
index 00000000..d54b2ed1
--- /dev/null
+++ b/binutils-2.25/include/coff/ti.h
@@ -0,0 +1,561 @@
+/* COFF information for TI COFF support.  Definitions in this file should be
+   customized in a target-specific file, and then this file included (see
+   tic54x.h for an example).
+   
+   Copyright 2000, 2001, 2002, 2003, 2005, 2008, 2009, 2010
+   Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef COFF_TI_H
+#define COFF_TI_H
+
+/* Note "coff/external.h is not used because TI adds extra fields to the structures.  */
+
+/********************** FILE HEADER **********************/
+
+struct external_filehdr
+  {
+    char f_magic[2];	/* magic number			*/
+    char f_nscns[2];	/* number of sections		*/
+    char f_timdat[4];	/* time & date stamp		*/
+    char f_symptr[4];	/* file pointer to symtab	*/
+    char f_nsyms[4];	/* number of symtab entries	*/
+    char f_opthdr[2];	/* sizeof(optional hdr)		*/
+    char f_flags[2];	/* flags			*/
+    char f_target_id[2];    /* magic no. (TI COFF-specific) */
+  };
+
+/* COFF0 has magic number in f_magic, and omits f_target_id from the file
+   header; for later versions, f_magic is 0xC1 for COFF1 and 0xC2 for COFF2
+   and the target-specific magic number is found in f_target_id */ 
+
+#define TICOFF0MAGIC    TI_TARGET_ID
+#define TICOFF1MAGIC    0x00C1
+#define TICOFF2MAGIC    0x00C2
+#define TICOFF_AOUT_MAGIC    0x0108 /* magic number in optional header */
+#define TICOFF          1 /* customize coffcode.h */
+
+/* The target_id field changes depending on the particular CPU target */
+/* for COFF0, the target id appeared in f_magic, where COFFX magic is now */
+#ifndef TI_TARGET_ID
+#error "TI_TARGET_ID needs to be defined for your CPU"
+#endif
+
+/* Which bfd_arch to use... */
+#ifndef TICOFF_TARGET_ARCH
+#error "TICOFF_TARGET_ARCH needs to be defined for your CPU"
+#endif
+
+#ifndef TICOFF_TARGET_MACHINE_GET
+#define TICOFF_TARGET_MACHINE_GET(FLAGS) 0
+#endif
+
+#ifndef TICOFF_TARGET_MACHINE_SET
+#define TICOFF_TARGET_MACHINE_SET(FLAGSP, MACHINE)
+#endif
+
+/* Default to COFF2 for file output */
+#ifndef TICOFF_DEFAULT_MAGIC
+#define TICOFF_DEFAULT_MAGIC TICOFF2MAGIC
+#endif
+
+/* This value is made available in the rare case where a bfd is unavailable */
+#ifndef OCTETS_PER_BYTE_POWER
+#error "OCTETS_PER_BYTE_POWER not defined for this CPU"
+#else
+#define OCTETS_PER_BYTE (1<<OCTETS_PER_BYTE_POWER)
+#endif
+
+/* default alignment is on a byte (not octet!) boundary */
+#ifndef COFF_DEFAULT_SECTION_ALIGNMENT_POWER
+#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 0
+#endif
+
+/* TI COFF encodes the section alignment in the section header flags */
+#define COFF_ALIGN_IN_SECTION_HEADER 1
+#define COFF_ALIGN_IN_S_FLAGS 1
+/* requires a power-of-two argument */
+#define COFF_ENCODE_ALIGNMENT(S,X) ((S).s_flags |= (((unsigned)(X)&0xF)<<8))
+/* result is a power of two */
+#define COFF_DECODE_ALIGNMENT(X) (((X)>>8)&0xF)
+
+#define COFF0_P(ABFD) (bfd_coff_filhsz(ABFD) == FILHSZ_V0)
+#define COFF2_P(ABFD) (bfd_coff_scnhsz(ABFD) != SCNHSZ_V01)
+
+#define COFF0_BADMAG(x) ((x).f_magic != TICOFF0MAGIC)
+#define COFF1_BADMAG(x) ((x).f_magic != TICOFF1MAGIC || (x).f_target_id != TI_TARGET_ID)
+#define COFF2_BADMAG(x) ((x).f_magic != TICOFF2MAGIC || (x).f_target_id != TI_TARGET_ID)
+
+/* we need to read/write an extra field in the coff file header */
+#ifndef COFF_ADJUST_FILEHDR_IN_POST
+#define COFF_ADJUST_FILEHDR_IN_POST(abfd, src, dst) \
+  do									\
+    {									\
+      if (!COFF0_P (abfd))						\
+	((struct internal_filehdr *)(dst))->f_target_id =		\
+	  H_GET_16 (abfd, ((FILHDR *)(src))->f_target_id);		\
+    }									\
+  while (0)
+#endif
+
+#ifndef COFF_ADJUST_FILEHDR_OUT_POST
+#define COFF_ADJUST_FILEHDR_OUT_POST(abfd, src, dst) \
+  do									 \
+    {									 \
+      if (!COFF0_P (abfd))						 \
+	H_PUT_16 (abfd, ((struct internal_filehdr *)(src))->f_target_id, \
+		 ((FILHDR *)(dst))->f_target_id);			 \
+    }									 \
+  while (0)
+#endif
+
+#define	FILHDR	struct external_filehdr
+#define	FILHSZ	22
+#define FILHSZ_V0 20                /* COFF0 omits target_id field */
+
+/* File header flags */
+#define	F_RELFLG	(0x0001)
+#define	F_EXEC		(0x0002)
+#define	F_LNNO		(0x0004)
+#define F_VERS          (0x0010) /* TMS320C4x code */
+/* F_LSYMS needs to be redefined in your source file */
+#define	F_LSYMS_TICOFF	(0x0010) /* normal COFF is 0x8 */
+
+#define F_10            0x00    /* file built for TMS320C1x devices */
+#define F_20            0x10    /* file built for TMS320C2x devices */
+#define F_25            0x20    /* file built for TMS320C2x/C5x devices */
+#define F_LENDIAN       0x0100  /* 16 bits/word, LSB first */
+#define F_SYMMERGE      0x1000  /* duplicate symbols were removed */
+
+/********************** OPTIONAL HEADER **********************/
+
+
+typedef struct 
+{
+  char 	magic[2];		/* type of file (0x108) 		*/
+  char	vstamp[2];		/* version stamp			*/
+  char	tsize[4];		/* text size in bytes, padded to FW bdry*/
+  char	dsize[4];		/* initialized data "  "		*/
+  char	bsize[4];		/* uninitialized data "   "		*/
+  char	entry[4];		/* entry pt.				*/
+  char 	text_start[4];		/* base of text used for this file */
+  char 	data_start[4];		/* base of data used for this file */
+}
+AOUTHDR;
+
+
+#define AOUTHDRSZ 28
+#define AOUTSZ 28
+
+
+/********************** SECTION HEADER **********************/
+/* COFF0, COFF1 */
+struct external_scnhdr_v01 {
+	char		s_name[8];	/* section name			*/
+	char		s_paddr[4];	/* physical address, aliased s_nlib */
+	char		s_vaddr[4];	/* virtual address		*/
+	char		s_size[4];	/* section size (in WORDS)      */
+	char		s_scnptr[4];	/* file ptr to raw data for section */
+	char		s_relptr[4];	/* file ptr to relocation	*/
+	char		s_lnnoptr[4];	/* file ptr to line numbers	*/
+	char		s_nreloc[2];	/* number of relocation entries	*/
+	char		s_nlnno[2];	/* number of line number entries*/
+	char		s_flags[2];	/* flags			*/
+        char            s_reserved[1];  /* reserved                     */ 
+        char            s_page[1];      /* section page number (LOAD)   */
+};
+
+/* COFF2 */
+struct external_scnhdr {
+	char		s_name[8];	/* section name			*/
+	char		s_paddr[4];	/* physical address, aliased s_nlib */
+	char		s_vaddr[4];	/* virtual address		*/
+	char		s_size[4];	/* section size (in WORDS)      */
+	char		s_scnptr[4];	/* file ptr to raw data for section */
+	char		s_relptr[4];	/* file ptr to relocation	*/
+	char		s_lnnoptr[4];	/* file ptr to line numbers	*/
+	char		s_nreloc[4];	/* number of relocation entries	*/
+	char		s_nlnno[4];	/* number of line number entries*/
+	char		s_flags[4];	/* flags			*/
+        char            s_reserved[2];  /* reserved                     */ 
+        char            s_page[2];      /* section page number (LOAD)   */
+};
+
+/*
+ * Special section flags
+ */
+
+/* TI COFF defines these flags; 
+   STYP_CLINK: the section should be excluded from the final
+   linker output if there are no references found to any symbol in the section
+   STYP_BLOCK: the section should be blocked, i.e. if the section would cross
+   a page boundary, it is started at a page boundary instead.
+   TI COFF puts the section alignment power of two in the section flags
+   e.g. 2**N is alignment, flags |= (N & 0xF) << 8
+*/ 
+#define STYP_CLINK      (0x4000)
+#define STYP_BLOCK      (0x1000)
+#define STYP_ALIGN      (0x0F00) /* TI COFF stores section alignment here */
+
+#define	SCNHDR_V01 struct external_scnhdr_v01
+#define SCNHDR struct external_scnhdr
+#define	SCNHSZ_V01 40                  /* for v0 and v1 */
+#define SCNHSZ 48
+
+/* COFF2 changes the offsets and sizes of these fields 
+   Assume we're dealing with the COFF2 scnhdr structure, and adjust
+   accordingly.  Note: The GNU C versions of some of these macros
+   are necessary in order to avoid compile time warnings triggered
+   gcc's array bounds checking.  The PUT_SCNHDR_PAGE macro also has
+   the advantage on not evaluating LOC twice.  */
+
+#define GET_SCNHDR_NRELOC(ABFD, LOC) \
+  (COFF2_P (ABFD) ? H_GET_32 (ABFD, LOC) : H_GET_16 (ABFD, LOC))
+#define PUT_SCNHDR_NRELOC(ABFD, VAL, LOC) \
+  (COFF2_P (ABFD) ? H_PUT_32 (ABFD, VAL, LOC) : H_PUT_16 (ABFD, VAL, LOC))
+#ifdef __GNUC__
+#define GET_SCNHDR_NLNNO(ABFD, LOC) \
+  ({ \
+    int nlnno;		\
+    char * ptr = (LOC); \
+    if (COFF2_P (ABFD)) \
+      nlnno = H_GET_32 (ABFD, ptr); \
+    else \
+      nlnno = H_GET_16 (ABFD, ptr - 2); \
+    nlnno; \
+  })
+#define PUT_SCNHDR_NLNNO(ABFD, VAL, LOC) \
+  do \
+    { \
+      char * ptr = (LOC); \
+      if (COFF2_P (ABFD)) \
+	H_PUT_32 (ABFD, VAL, ptr); \
+      else \
+	H_PUT_16 (ABFD, VAL, ptr - 2); \
+    } \
+  while (0)
+#define GET_SCNHDR_FLAGS(ABFD, LOC) \
+  ({ \
+    int flags; \
+    char * ptr = (LOC); \
+    if (COFF2_P (ABFD)) \
+      flags = H_GET_32 (ABFD, ptr); \
+    else \
+      flags = H_GET_16 (ABFD, ptr - 4); \
+    flags; \
+  })
+#define PUT_SCNHDR_FLAGS(ABFD, VAL, LOC) \
+  do \
+    { \
+      char * ptr = (LOC); \
+      if (COFF2_P (ABFD)) \
+	H_PUT_32 (ABFD, VAL, ptr); \
+      else \
+	H_PUT_16 (ABFD, VAL, ptr - 4); \
+    } \
+  while (0)
+#define GET_SCNHDR_PAGE(ABFD, LOC) \
+  ({ \
+    unsigned page; \
+    char * ptr = (LOC); \
+    if (COFF2_P (ABFD)) \
+      page = H_GET_16 (ABFD, ptr); \
+    else \
+      page = (unsigned) H_GET_8 (ABFD, ptr - 7); \
+    page; \
+  })
+/* On output, make sure that the "reserved" field is zero.  */
+#define PUT_SCNHDR_PAGE(ABFD, VAL, LOC) \
+  do \
+    { \
+      char * ptr = (LOC); \
+      if (COFF2_P (ABFD)) \
+	H_PUT_16 (ABFD, VAL, ptr); \
+      else \
+	{ \
+	  H_PUT_8 (ABFD, VAL, ptr - 7); \
+	  H_PUT_8 (ABFD, 0, ptr - 8); \
+	} \
+    } \
+  while (0)
+#else
+#define GET_SCNHDR_NLNNO(ABFD, LOC) \
+  (COFF2_P (ABFD) ? H_GET_32 (ABFD, LOC) : H_GET_16 (ABFD, (LOC) - 2))
+#define PUT_SCNHDR_NLNNO(ABFD, VAL, LOC) \
+  (COFF2_P (ABFD) ? H_PUT_32 (ABFD, VAL, LOC) : H_PUT_16 (ABFD, VAL, (LOC) - 2))
+#define GET_SCNHDR_FLAGS(ABFD, LOC) \
+  (COFF2_P (ABFD) ? H_GET_32 (ABFD, LOC) : H_GET_16 (ABFD, (LOC) - 4))
+#define PUT_SCNHDR_FLAGS(ABFD, VAL, LOC) \
+  (COFF2_P (ABFD) ? H_PUT_32 (ABFD, VAL, LOC) : H_PUT_16 (ABFD, VAL, (LOC) - 4))
+#define GET_SCNHDR_PAGE(ABFD, LOC) \
+  (COFF2_P (ABFD) ? H_GET_16 (ABFD, LOC) : (unsigned) H_GET_8 (ABFD, (LOC) - 7))
+/* On output, make sure that the "reserved" field is zero.  */
+#define PUT_SCNHDR_PAGE(ABFD, VAL, LOC) \
+  (COFF2_P (ABFD) \
+   ? H_PUT_16 (ABFD, VAL, LOC) \
+   : H_PUT_8 (ABFD, VAL, (LOC) - 7), H_PUT_8 (ABFD, 0, (LOC) - 8))
+#endif
+
+
+/* TI COFF stores section size as number of bytes (address units, not octets),
+   so adjust to be number of octets, which is what BFD expects */ 
+#define GET_SCNHDR_SIZE(ABFD, SZP) \
+  (H_GET_32 (ABFD, SZP) * bfd_octets_per_byte (ABFD))
+#define PUT_SCNHDR_SIZE(ABFD, SZ, SZP) \
+  H_PUT_32 (ABFD, (SZ) / bfd_octets_per_byte (ABFD), SZP)
+
+#define COFF_ADJUST_SCNHDR_IN_POST(ABFD, EXT, INT) \
+  do									\
+    {									\
+      ((struct internal_scnhdr *)(INT))->s_page =			\
+	GET_SCNHDR_PAGE (ABFD, ((SCNHDR *)(EXT))->s_page);		\
+    }									\
+   while (0)
+
+/* The entire scnhdr may not be assigned.
+   Ensure that everything is initialized.  */
+#define COFF_ADJUST_SCNHDR_OUT_PRE(ABFD, INT, EXT)	\
+  do							\
+    {							\
+      memset((EXT), 0, sizeof (SCNHDR));		\
+    }							\
+  while (0)
+
+/* The line number and reloc overflow checking in coff_swap_scnhdr_out in
+   coffswap.h doesn't use PUT_X for s_nlnno and s_nreloc.
+   Due to different sized v0/v1/v2 section headers, we have to re-write these
+   fields.
+ */
+#define COFF_ADJUST_SCNHDR_OUT_POST(ABFD, INT, EXT) \
+  do									   \
+    {									   \
+      PUT_SCNHDR_NLNNO (ABFD, ((struct internal_scnhdr *)(INT))->s_nlnno,  \
+			((SCNHDR *)(EXT))->s_nlnno);			   \
+      PUT_SCNHDR_NRELOC (ABFD, ((struct internal_scnhdr *)(INT))->s_nreloc,\
+			 ((SCNHDR *)(EXT))->s_nreloc);			   \
+      PUT_SCNHDR_FLAGS (ABFD, ((struct internal_scnhdr *)(INT))->s_flags,  \
+			((SCNHDR *)(EXT))->s_flags);			   \
+      PUT_SCNHDR_PAGE (ABFD, ((struct internal_scnhdr *)(INT))->s_page,    \
+		       ((SCNHDR *)(EXT))->s_page);			   \
+    }									   \
+   while (0)
+
+/*
+ * names of "special" sections
+ */
+#define _TEXT	".text"
+#define _DATA	".data"
+#define _BSS	".bss"
+#define _CINIT  ".cinit"            /* initialized C data */
+#define _SCONST  ".const"           /* constants */
+#define _SWITCH ".switch"           /* switch tables */
+#define _STACK  ".stack"            /* C stack */
+#define _SYSMEM ".sysmem"           /* used for malloc et al. syscalls */
+
+/********************** LINE NUMBERS **********************/
+
+/* 1 line number entry for every "breakpointable" source line in a section.
+ * Line numbers are grouped on a per function basis; first entry in a function
+ * grouping will have l_lnno = 0 and in place of physical address will be the
+ * symbol table index of the function name.
+ */
+struct external_lineno {
+  union {
+    char l_symndx[4];	/* function name symbol index, iff l_lnno == 0*/
+    char l_paddr[4];	/* (physical) address of line number	*/
+  } l_addr;
+  char l_lnno[2];	/* line number		*/
+};
+
+#define	LINENO	struct external_lineno
+#define	LINESZ	6
+
+
+/********************** SYMBOLS **********************/
+
+/* NOTE: this is what a local label looks like in assembly source; what it
+   looks like in COFF output is undefined */
+#define TICOFF_LOCAL_LABEL_P(NAME) \
+((NAME[0] == '$' && NAME[1] >= '0' && NAME[1] <= '9' && NAME[2] == '\0') \
+ || NAME[strlen(NAME)-1] == '?')
+
+#define E_SYMNMLEN	8	/* # characters in a symbol name	*/
+#define E_FILNMLEN	14	/* # characters in a file name		*/
+#define E_DIMNUM	4	/* # array dimensions in auxiliary entry */
+
+struct external_syment 
+{
+  union {
+    char e_name[E_SYMNMLEN];
+    struct {
+      char e_zeroes[4];
+      char e_offset[4];
+    } e;
+  } e;
+  char e_value[4];
+  char e_scnum[2];
+  char e_type[2];
+  char e_sclass[1];
+  char e_numaux[1];
+};
+
+
+#define N_BTMASK	(017)
+#define N_TMASK		(060)
+#define N_BTSHFT	(4)
+#define N_TSHIFT	(2)
+  
+
+union external_auxent {
+  struct {
+	char x_tagndx[4];	/* str, un, or enum tag indx */
+	union {
+	  struct {
+		char  x_lnno[2]; /* declaration line number */
+		char  x_size[2]; /* str/union/array size */
+	  } x_lnsz;
+	  char x_fsize[4];	/* size of function */
+	} x_misc;
+	union {
+	  struct {		/* if ISFCN, tag, or .bb */
+		char x_lnnoptr[4];	/* ptr to fcn line # */
+		char x_endndx[4];	/* entry ndx past block end */
+	  } x_fcn;
+	  struct {		/* if ISARY, up to 4 dimen. */
+		char x_dimen[E_DIMNUM][2];
+	  } x_ary;
+	} x_fcnary;
+	char x_tvndx[2];		/* tv index */
+  } x_sym;
+  
+  union {
+	char x_fname[E_FILNMLEN];
+	struct {
+	  char x_zeroes[4];
+	  char x_offset[4];
+	} x_n;
+  } x_file;
+  
+  struct {
+	char x_scnlen[4];			/* section length */
+	char x_nreloc[2];	/* # relocation entries */
+	char x_nlinno[2];	/* # line numbers */
+  } x_scn;
+  
+  struct {
+	char x_tvfill[4];	/* tv fill value */
+	char x_tvlen[2];	/* length of .tv */
+	char x_tvran[2][2];	/* tv range */
+  } x_tv;		/* info about .tv section (in auxent of symbol .tv)) */
+  
+
+};
+
+#define	SYMENT	struct external_syment
+#define	SYMESZ	18	
+#define	AUXENT	union external_auxent
+#define	AUXESZ	18
+
+/* section lengths are in target bytes (not host bytes) */
+#define GET_SCN_SCNLEN(ABFD, EXT) \
+  (H_GET_32 (ABFD, (EXT)->x_scn.x_scnlen) * bfd_octets_per_byte (ABFD))
+#define PUT_SCN_SCNLEN(ABFD, INT, EXT) \
+  H_PUT_32 (ABFD, (INT) / bfd_octets_per_byte (ABFD), (EXT)->x_scn.x_scnlen)
+
+/* lnsz size is in bits in COFF file, in bytes in BFD */
+#define GET_LNSZ_SIZE(abfd, ext) \
+ (H_GET_16 (abfd, ext->x_sym.x_misc.x_lnsz.x_size) / (in_class != C_FIELD ? 8 : 1))
+
+#define PUT_LNSZ_SIZE(abfd, in, ext) \
+  H_PUT_16 (abfd, ((in_class != C_FIELD) ? (in) * 8 : (in)), \
+	   ext->x_sym.x_misc.x_lnsz.x_size)
+ 
+/* TI COFF stores offsets for MOS and MOU in bits; BFD expects bytes 
+   Also put the load page flag of the section into the symbol value if it's an
+   address.  */
+#ifndef NEEDS_PAGE
+#define NEEDS_PAGE(X) 0
+#define PAGE_MASK 0
+#endif
+#define COFF_ADJUST_SYM_IN_POST(ABFD, EXT, INT) \
+  do									\
+    {									\
+      struct internal_syment *dst = (struct internal_syment *)(INT);	\
+      if (dst->n_sclass == C_MOS || dst->n_sclass == C_MOU)		\
+	dst->n_value /= 8;						\
+      else if (NEEDS_PAGE (dst->n_sclass)) {                            \
+        asection *scn = coff_section_from_bfd_index (abfd, dst->n_scnum); \
+        dst->n_value |= (scn->lma & PAGE_MASK);                         \
+      }									\
+    }									\
+   while (0)
+
+#define COFF_ADJUST_SYM_OUT_POST(ABFD, INT, EXT) \
+  do									\
+    {									\
+       struct internal_syment *src = (struct internal_syment *)(INT);	\
+       SYMENT *dst = (SYMENT *)(EXT);					\
+       if (src->n_sclass == C_MOU || src->n_sclass == C_MOS)		\
+	 H_PUT_32 (abfd, src->n_value * 8, dst->e_value);		\
+       else if (NEEDS_PAGE (src->n_sclass)) {                           \
+         H_PUT_32 (abfd, src->n_value &= ~PAGE_MASK, dst->e_value);     \
+       }								\
+    }									\
+   while (0)
+
+/* Detect section-relative absolute symbols so they get flagged with a sym
+   index of -1.
+*/
+#define SECTION_RELATIVE_ABSOLUTE_SYMBOL_P(RELOC, SECT) \
+  ((*(RELOC)->sym_ptr_ptr)->section->output_section == (SECT) \
+   && (RELOC)->howto->name[0] == 'A')
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+struct external_reloc_v0
+{
+  char r_vaddr[4];
+  char r_symndx[2];
+  char r_reserved[2];
+  char r_type[2];
+};
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_reserved[2]; /* extended pmad byte for COFF2 */
+  char r_type[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ_V0 10                 /* FIXME -- coffcode.h needs fixing */
+#define RELSZ 12                    /* for COFF1/2 */
+
+#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
+  do memset (dst->r_reserved, 0, sizeof (dst->r_reserved)); while (0)
+
+/* various relocation types.  */
+#define R_ABS     0x0000            /* no relocation */
+#define R_REL13   0x002A            /* 13-bit direct reference (???) */
+#define R_PARTLS7 0x0028            /* 7 LSBs of an address */
+#define R_PARTMS9 0x0029            /* 9MSBs of an address */
+#define R_EXTWORD 0x002B            /* 23-bit direct reference */
+#define R_EXTWORD16 0x002C          /* 16-bit direct reference to 23-bit addr*/
+#define R_EXTWORDMS7 0x002D         /* upper 7 bits of 23-bit address */
+
+#endif /* COFF_TI_H */
diff --git a/binutils-2.25/include/coff/tic30.h b/binutils-2.25/include/coff/tic30.h
new file mode 100644
index 00000000..4f7776a4
--- /dev/null
+++ b/binutils-2.25/include/coff/tic30.h
@@ -0,0 +1,51 @@
+/* coff information for Texas Instruments TMS320C3X
+   
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define L_LNNO_SIZE 4
+#include "coff/external.h"
+
+#define	TIC30MAGIC	0xC000
+
+#define TIC30BADMAG(x) (((x).f_magic != TIC30MAGIC))
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+/* The external reloc has an offset field, because some of the reloc
+   types on the z8k don't have room in the instruction for the entire
+   offset - eg with segments */
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_offset[4];
+  char r_type[2];
+  char r_stuff[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 16
+
+/* TMS320C30 relocation types.  */
+
+#define R_TIC30_ABS16 0x100  /* 16 bit absolute. */
+#define R_TIC30_ABS24 0x101  /* 24 bit absolute. */
+#define R_TIC30_ABS32 0x102  /* 32 bit absolute. */
+#define R_TIC30_LDP   0x103  /* LDP bits 23-16 to 7-0. */
+#define R_TIC30_PC16  0x104  /* 16 bit pc relative. */
diff --git a/binutils-2.25/include/coff/tic4x.h b/binutils-2.25/include/coff/tic4x.h
new file mode 100644
index 00000000..1eb3e26b
--- /dev/null
+++ b/binutils-2.25/include/coff/tic4x.h
@@ -0,0 +1,47 @@
+/* TI COFF information for Texas Instruments TMS320C4X/C3X.
+   This file customizes the settings in coff/ti.h. 
+   
+   Copyright 2002, 2003, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef COFF_TIC4X_H
+#define COFF_TIC4X_H
+
+#define TIC4X_TARGET_ID 	0x0093
+/* Octets per byte, as a power of two.  */
+#define TI_TARGET_ID 		TIC4X_TARGET_ID
+#define OCTETS_PER_BYTE_POWER 	2 
+/* Add to howto to get absolute/sect-relative version.  */
+#define HOWTO_BANK 		6		
+#define TICOFF_TARGET_ARCH 	bfd_arch_tic4x
+/* We use COFF2.  */
+#define TICOFF_DEFAULT_MAGIC 	TICOFF2MAGIC 
+
+#define TICOFF_TARGET_MACHINE_GET(FLAGS) \
+  (((FLAGS) & F_VERS) ? bfd_mach_tic4x : bfd_mach_tic3x)
+
+#define TICOFF_TARGET_MACHINE_SET(FLAGSP, MACHINE)	\
+  do							\
+    {							\
+      if ((MACHINE) == bfd_mach_tic4x)			\
+        *(FLAGSP) |= F_VERS;				\
+    }							\
+  while (0)
+
+#include "coff/ti.h"
+
+#endif /* COFF_TIC4X_H */
diff --git a/binutils-2.25/include/coff/tic54x.h b/binutils-2.25/include/coff/tic54x.h
new file mode 100644
index 00000000..c61f1f20
--- /dev/null
+++ b/binutils-2.25/include/coff/tic54x.h
@@ -0,0 +1,60 @@
+/* TI COFF information for Texas Instruments TMS320C54X.
+   This file customizes the settings in coff/ti.h. 
+   
+   Copyright 2000, 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef COFF_TIC54X_H
+#define COFF_TIC54X_H
+
+#define TIC54X_TARGET_ID 0x98
+#define TIC54XALGMAGIC  0x009B  /* c54x algebraic assembler output */
+#define TIC5X_TARGET_ID  0x92
+#define TI_TARGET_ID TIC54X_TARGET_ID
+#define OCTETS_PER_BYTE_POWER 1 /* octets per byte, as a power of two */
+#define HOWTO_BANK 6 /* add to howto to get absolute/sect-relative version */
+#define TICOFF_TARGET_ARCH bfd_arch_tic54x
+#define TICOFF_DEFAULT_MAGIC TICOFF1MAGIC /* we use COFF1 for compatibility */
+
+/* Page macros
+
+   The first GDB port requires flags in its remote memory access commands to
+   distinguish between data/prog space.  Hopefully we can make this go away
+   eventually.  Stuff the page in the upper bits of a 32-bit address, since
+   the c5x family only uses 16 or 23 bits.
+
+   c2x, c5x and most c54x devices have 16-bit addresses, but the c548 has
+   23-bit program addresses.  Make sure the page flags don't interfere.
+   These flags are used by GDB to identify the destination page for
+   addresses. 
+*/
+
+/* Recognized load pages (by common convention).  */
+#define PG_PROG         0x0         /* PROG page */
+#define PG_DATA         0x1         /* DATA page */
+#define PG_IO           0x2         /* I/O page */
+
+/** Indicate whether the given storage class requires a page flag.  */
+#define NEEDS_PAGE(X) ((X)==C_EXT)
+#define PAGE_MASK       0xFF000000
+#define ADDR_MASK       0x00FFFFFF
+#define PG_TO_FLAG(p)   (((unsigned long)(p) & 0xFF) << 24)
+#define FLAG_TO_PG(f)   (((f) >> 24) & 0xFF)
+
+#include "coff/ti.h"
+
+#endif /* COFF_TIC54X_H */
diff --git a/binutils-2.25/include/coff/tic80.h b/binutils-2.25/include/coff/tic80.h
new file mode 100644
index 00000000..44f873ef
--- /dev/null
+++ b/binutils-2.25/include/coff/tic80.h
@@ -0,0 +1,123 @@
+/* coff information for TI TMS320C80 (MVP)
+   
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define DO_NOT_DEFINE_FILHDR
+#define DO_NOT_DEFINE_SCNHDR
+#define L_LNNO_SIZE 2
+#include "coff/external.h"
+
+/********************** FILE HEADER **********************/
+
+struct external_filehdr
+  {
+    char f_magic[2];	/* magic number			*/
+    char f_nscns[2];	/* number of sections		*/
+    char f_timdat[4];	/* time & date stamp		*/
+    char f_symptr[4];	/* file pointer to symtab	*/
+    char f_nsyms[4];	/* number of symtab entries	*/
+    char f_opthdr[2];	/* sizeof(optional hdr)		*/
+    char f_flags[2];	/* flags			*/
+    char f_target_id[2];/* target id (TIc80 specific)	*/
+};
+
+#define	TIC80_ARCH_MAGIC	0x0C1	/* Goes in the file header magic number field */
+#define TIC80_TARGET_ID		0x95	/* Goes in the target id field */
+
+#define TIC80BADMAG(x) ((x).f_magic != TIC80_ARCH_MAGIC)
+
+#define	FILHDR	struct external_filehdr
+#define	FILHSZ	22
+
+#define TIC80_AOUTHDR_MAGIC	0x108	/* Goes in the optional file header magic number field */
+
+/********************** SECTION HEADER **********************/
+
+struct external_scnhdr
+{
+	char		s_name[8];	/* section name			*/
+	char		s_paddr[4];	/* physical address, aliased s_nlib */
+	char		s_vaddr[4];	/* virtual address		*/
+	char		s_size[4];	/* section size			*/
+	char		s_scnptr[4];	/* file ptr to raw data for section */
+	char		s_relptr[4];	/* file ptr to relocation	*/
+	char		s_lnnoptr[4];	/* file ptr to line numbers	*/
+	char		s_nreloc[2];	/* number of relocation entries	*/
+	char		s_nlnno[2];	/* number of line number entries*/
+	char		s_flags[2];	/* flags			*/
+	char		s_reserved[1];	/* reserved (TIc80 specific)	*/
+	char		s_mempage[1];	/* memory page number (TIc80)	*/
+};
+
+/* Names of "special" sections.  */
+#define _TEXT	".text"
+#define _DATA	".data"
+#define _BSS	".bss"
+#define _CINIT	".cinit"
+#define _CONST	".const"
+#define _SWITCH	".switch"
+#define _STACK	".stack"
+#define _SYSMEM	".sysmem"
+
+#define	SCNHDR	struct external_scnhdr
+#define	SCNHSZ	40
+  
+/* FIXME - need to correlate external_auxent with
+   TIc80 Code Generation Tools User's Guide, CG:A-25 */
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+/* The external reloc has an offset field, because some of the reloc
+   types on the h8 don't have room in the instruction for the entire
+   offset - eg the strange jump and high page addressing modes.  */
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_reserved[2];
+  char r_type[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 12
+
+/* TIc80 relocation types. */
+
+#define R_ABS		0x00		/* Absolute address - no relocation */
+#define R_RELLONGX	0x11		/* PP: 32 bits, direct */
+#define R_PPBASE	0x34		/* PP: Global base address type */
+#define R_PPLBASE	0x35		/* PP: Local base address type */
+#define R_PP15		0x38		/* PP: Global 15 bit offset */
+#define R_PP15W		0x39		/* PP: Global 15 bit offset divided by 4 */
+#define R_PP15H		0x3A		/* PP: Global 15 bit offset divided by 2 */
+#define R_PP16B		0x3B		/* PP: Global 16 bit offset for bytes */
+#define R_PPL15		0x3C		/* PP: Local 15 bit offset */
+#define R_PPL15W	0x3D		/* PP: Local 15 bit offset divided by 4 */
+#define R_PPL15H	0x3E		/* PP: Local 15 bit offset divided by 2 */
+#define R_PPL16B	0x3F		/* PP: Local 16 bit offset for bytes */
+#define R_PPN15		0x40		/* PP: Global 15 bit negative offset */
+#define R_PPN15W	0x41		/* PP: Global 15 bit negative offset divided by 4 */
+#define R_PPN15H	0x42		/* PP: Global 15 bit negative offset divided by 2 */
+#define R_PPN16B	0x43		/* PP: Global 16 bit negative byte offset */
+#define R_PPLN15	0x44		/* PP: Local 15 bit negative offset */
+#define R_PPLN15W	0x45		/* PP: Local 15 bit negative offset divided by 4 */
+#define R_PPLN15H	0x46		/* PP: Local 15 bit negative offset divided by 2 */
+#define R_PPLN16B	0x47		/* PP: Local 16 bit negative byte offset */
+#define R_MPPCR15W	0x4E		/* MP: 15 bit PC-relative divided by 4 */
+#define R_MPPCR		0x4F		/* MP: 32 bit PC-relative divided by 4 */
diff --git a/binutils-2.25/include/coff/w65.h b/binutils-2.25/include/coff/w65.h
new file mode 100644
index 00000000..31d96093
--- /dev/null
+++ b/binutils-2.25/include/coff/w65.h
@@ -0,0 +1,47 @@
+/* coff information for WDC 65816
+   
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define L_LNNO_SIZE 4
+#include "coff/external.h"
+
+#define	W65MAGIC	0x6500
+
+#define W65BADMAG(x) (((x).f_magic != W65MAGIC))
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+/* The external reloc has an offset field, because some of the reloc
+   types on the w65 don't have room in the instruction for the entire
+   offset - eg the strange jump and high page addressing modes */
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_offset[4];
+  char r_type[2];
+  char r_stuff[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 16
+
+
+
+
diff --git a/binutils-2.25/include/coff/we32k.h b/binutils-2.25/include/coff/we32k.h
new file mode 100644
index 00000000..3787dd27
--- /dev/null
+++ b/binutils-2.25/include/coff/we32k.h
@@ -0,0 +1,62 @@
+/* coff information for we32k
+   
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define L_LNNO_SIZE 2
+#include "coff/external.h"
+
+/* Bits for f_flags:
+ 	F_RELFLG	relocation info stripped from file
+ 	F_EXEC		file is executable (no unresolved external references)
+ 	F_LNNO		line numbers stripped from file
+ 	F_LSYMS		local symbols stripped from file
+ 	F_AR32WR	file has byte ordering of an AR32WR machine (e.g. vax).  */
+
+#define F_RELFLG	(0x0001)
+#define F_EXEC		(0x0002)
+#define F_LNNO		(0x0004)
+#define F_LSYMS		(0x0008)
+#define	F_BM32B		(0020000)
+#define	F_BM32MAU	(0040000)
+
+#define	WE32KMAGIC	0x170	/* we32k sans transfer vector */
+#define FBOMAGIC	0x170	/* we32k sans transfer vector */
+#define MTVMAGIC	0x171	/* we32k with transfer vector */
+#define RBOMAGIC	0x172	/* reserved */
+#define WE32KBADMAG(x) (   ((x).f_magic != WE32KMAGIC) \
+			&& ((x).f_magic != FBOMAGIC) \
+			&& ((x).f_magic != RBOMAGIC) \
+			&& ((x).f_magic != MTVMAGIC))
+
+/* More names of "special" sections.  */
+#define _TV	".tv"
+#define _INIT	".init"
+#define _FINI	".fini"
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 10
+
diff --git a/binutils-2.25/include/coff/x86_64.h b/binutils-2.25/include/coff/x86_64.h
new file mode 100644
index 00000000..fcd44c8e
--- /dev/null
+++ b/binutils-2.25/include/coff/x86_64.h
@@ -0,0 +1,57 @@
+/* COFF information for AMD 64.
+   Copyright 2006, 2009, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.
+   
+   Written by Kai Tietz, OneVision Software GmbH&CoKg.  */
+
+#define L_LNNO_SIZE 2
+#define INCLUDE_COMDAT_FIELDS_IN_AUXENT
+
+#include "coff/external.h"
+
+#define COFF_PAGE_SIZE	0x1000
+
+#define AMD64MAGIC	0x8664
+
+#define AMD64BADMAG(x)	((x).f_magic != AMD64MAGIC)
+#define IMAGE_NT_OPTIONAL_HDR64_MAGIC      0x20b
+
+#define OMAGIC          0404    /* Object files, eg as output.  */
+#define ZMAGIC          IMAGE_NT_OPTIONAL_HDR64_MAGIC    /* Demand load format, eg normal ld output 0x10b.  */
+#define STMAGIC		0401	/* Target shlib.  */
+#define SHMAGIC		0443	/* Host   shlib.  */
+
+/* Define some NT default values.  */
+/*  #define NT_IMAGE_BASE        0x400000 moved to internal.h.  */
+#define NT_SECTION_ALIGNMENT 0x1000
+#define NT_FILE_ALIGNMENT    0x200
+#define NT_DEF_RESERVE       0x100000
+#define NT_DEF_COMMIT        0x1000
+
+/* Relocation directives.  */
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_type[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 10
diff --git a/binutils-2.25/include/coff/xcoff.h b/binutils-2.25/include/coff/xcoff.h
new file mode 100644
index 00000000..67502cda
--- /dev/null
+++ b/binutils-2.25/include/coff/xcoff.h
@@ -0,0 +1,647 @@
+/* Internal format of XCOFF object file data structures for BFD.
+
+   Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005,
+   2009, 2010  Free Software Foundation, Inc.
+   Written by Ian Lance Taylor <ian@cygnus.com>, Cygnus Support.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _INTERNAL_XCOFF_H
+#define _INTERNAL_XCOFF_H
+
+/* XCOFF specific f_flags.  */
+
+/* File was profiled with fdpr.  */
+#define F_FDPR_PROF 0x0010
+
+/* File was reordered with fdpr.  */
+#define F_FDPR_OPTI 0x0020
+
+/* File use very large program support.  */
+#define F_DSA       0x0040
+
+/* One aux header specifying medium page sizes is non-zero.  */
+#define F_VARPG     0x0100
+
+/* Read/write sections are non-executable.  */
+#define F_NONEXEC   0x8000
+
+/* Linker */
+
+/* Names of "special" sections.  */
+#define _TEXT	".text"
+#define _DATA	".data"
+#define _BSS	".bss"
+#define _PAD	".pad"
+#define _LOADER	".loader"
+#define _EXCEPT ".except"
+#define _TYPCHK ".typchk"
+
+/* XCOFF uses special .dwXXX sections with the type STYP_DWARF.  */
+#define STYP_DWARF  0x0010
+
+/* High-order 16-bits dwarf subtypes.  */
+#define SSUBTYP_DWINFO  0x10000
+#define SSUBTYP_DWLINE  0x20000
+#define SSUBTYP_DWPBNMS 0x30000
+#define SSUBTYP_DWPBTYP 0x40000
+#define SSUBTYP_DWARNGE 0x50000
+#define SSUBTYP_DWABREV 0x60000
+#define SSUBTYP_DWSTR   0x70000
+#define SSUBTYP_DWRNGES 0x80000
+
+/* XCOFF uses a special .loader section with type STYP_LOADER.  */
+#define STYP_LOADER 0x1000
+
+/* Specifies an exception section.  A section of this type provides 
+   information to identify the reason that a trap or ececptin occured within 
+   and executable object program */
+#define STYP_EXCEPT 0x0100
+
+/* Specifies an initialized thread-local data section.  */
+#define STYP_TDATA  0x0400
+
+/* Specifies an uninitialized thread-local data section.  */
+#define STYP_TBSS   0x0800
+
+/* XCOFF uses a special .debug section with type STYP_DEBUG.  */
+#define STYP_DEBUG  0x2000
+
+/* Specifies a type check section.  A section of this type contains parameter 
+   argument type check strings used by the AIX binder.  */
+#define STYP_TYPCHK 0x4000
+
+/* XCOFF handles line number or relocation overflow by creating
+   another section header with STYP_OVRFLO set.  */
+#define STYP_OVRFLO 0x8000
+
+#define	RS6K_AOUTHDR_OMAGIC 0x0107 /* old: text & data writeable */
+#define	RS6K_AOUTHDR_NMAGIC 0x0108 /* new: text r/o, data r/w */
+#define	RS6K_AOUTHDR_ZMAGIC 0x010B /* paged: text r/o, both page-aligned */
+
+/* XCOFF relocation types.  
+   The relocations are described in the function  
+   xcoff[64]_ppc_relocate_section in coff64-rs6000.c and coff-rs6000.c  */
+
+#define R_POS   (0x00)
+#define R_NEG   (0x01)
+#define R_REL   (0x02)
+#define R_TOC   (0x03)
+#define R_RTB   (0x04)
+#define R_GL    (0x05)
+#define R_TCL   (0x06)
+#define R_BA    (0x08)
+#define R_BR    (0x0a)
+#define R_RL    (0x0c)
+#define R_RLA   (0x0d)
+#define R_REF   (0x0f)
+#define R_TRL   (0x12)
+#define R_TRLA  (0x13)
+#define R_RRTBI (0x14)
+#define R_RRTBA (0x15)
+#define R_CAI   (0x16)
+#define R_CREL  (0x17)
+#define R_RBA   (0x18)
+#define R_RBAC  (0x19)
+#define R_RBR   (0x1a)
+#define R_RBRC  (0x1b)
+#define R_TLS   (0x20)
+#define R_TLS_IE (0x21)
+#define R_TLS_LD (0x22)
+#define R_TLS_LE (0x23)
+#define R_TLSM  (0x24)
+#define R_TLSML (0x25)
+#define R_TOCU  (0x30)
+#define R_TOCL  (0x31)
+
+/* Storage class #defines, from /usr/include/storclass.h that are not already 
+   defined in internal.h */
+
+/* Comment string in .info section */
+#define	C_INFO		110	
+
+/* Dwarf symbol.  */
+#define C_DWARF		112
+
+/* Auxillary Symbol Entries  */
+
+/* x_smtyp values:  */
+#define	SMTYP_ALIGN(x)	((x) >> 3)	/* log2 of alignment */
+#define	SMTYP_SMTYP(x)	((x) & 0x7)	/* symbol type */
+/* Symbol type values:  */
+#define	XTY_ER	0		/* External reference */
+#define	XTY_SD	1		/* Csect definition */
+#define	XTY_LD	2		/* Label definition */
+#define XTY_CM	3		/* .BSS */
+#define	XTY_EM	4		/* Error message */
+#define	XTY_US	5		/* "Reserved for internal use" */
+
+/* x_smclas values:  */
+#define	XMC_PR	0		/* Read-only program code */
+#define	XMC_RO	1		/* Read-only constant */
+#define	XMC_DB	2		/* Read-only debug dictionary table */
+#define	XMC_TC	3		/* Read-write general TOC entry */
+#define	XMC_UA	4		/* Read-write unclassified */
+#define	XMC_RW	5		/* Read-write data */
+#define	XMC_GL	6		/* Read-only global linkage */
+#define	XMC_XO	7		/* Read-only extended operation */
+#define	XMC_SV	8		/* Read-only supervisor call */
+#define	XMC_BS	9		/* Read-write BSS */
+#define	XMC_DS	10		/* Read-write descriptor csect */
+#define	XMC_UC	11		/* Read-write unnamed Fortran common */
+#define	XMC_TI	12		/* Read-only traceback index csect */
+#define	XMC_TB	13		/* Read-only traceback table csect */
+/* 		14	??? */
+#define	XMC_TC0	15		/* Read-write TOC anchor */
+#define XMC_TD	16		/* Read-write data in TOC */
+#define	XMC_SV64   17		/* Read-only 64 bit supervisor call */
+#define	XMC_SV3264 18		/* Read-only 32 or 64 bit supervisor call */
+/*                19   ??? */
+#define XMC_TL     20          /* Read-write initialized TLS data */
+#define XMC_TU     21          /* Read-write uninitialized TLS data */
+#define XMC_TE     22          /* Same as XMC_TC but mapped after it */
+
+/* The ldhdr structure.  This appears at the start of the .loader
+   section.  */
+
+struct internal_ldhdr
+{
+  /* The version number: 
+     1 : 32 bit
+     2 : 64 bit */
+  unsigned long l_version;
+
+  /* The number of symbol table entries.  */
+  bfd_size_type l_nsyms;
+
+  /* The number of relocation table entries.  */
+  bfd_size_type l_nreloc;
+
+  /* The length of the import file string table.  */
+  bfd_size_type l_istlen;
+
+  /* The number of import files.  */
+  bfd_size_type l_nimpid;
+
+  /* The offset from the start of the .loader section to the first
+     entry in the import file table.  */
+  bfd_size_type l_impoff;
+
+  /* The length of the string table.  */
+  bfd_size_type l_stlen;
+
+  /* The offset from the start of the .loader section to the first
+     entry in the string table.  */
+  bfd_size_type l_stoff;
+
+  /* The offset to start of the symbol table, only in XCOFF64 */
+  bfd_vma l_symoff;
+
+  /* The offset to the start of the relocation table, only in XCOFF64 */
+  bfd_vma l_rldoff;
+};
+
+/* The ldsym structure.  This is used to represent a symbol in the
+   .loader section.  */
+
+struct internal_ldsym
+{
+  union
+  {
+    /* The symbol name if <= SYMNMLEN characters.  */
+    char _l_name[SYMNMLEN];
+    struct
+    {
+      /* Zero if the symbol name is more than SYMNMLEN characters.  */
+	long _l_zeroes;
+      
+      /* The offset in the string table if the symbol name is more
+	 than SYMNMLEN characters.  */
+      long _l_offset;
+    } 
+    _l_l;
+  }
+  _l;
+
+  /* The symbol value.  */
+  bfd_vma l_value;
+
+  /* The symbol section number.  */
+  short l_scnum;
+
+  /* The symbol type and flags.  */
+  char l_smtype;
+
+  /* The symbol storage class.  */
+  char l_smclas;
+
+  /* The import file ID.  */
+  bfd_size_type l_ifile;
+
+  /* Offset to the parameter type check string.  */
+  bfd_size_type l_parm;
+};
+
+/* These flags are for the l_smtype field (the lower three bits are an
+   XTY_* value).  */
+
+/* Imported symbol.  */
+#define L_IMPORT (0x40)
+/* Entry point.  */
+#define L_ENTRY (0x20)
+/* Exported symbol.  */
+#define L_EXPORT (0x10)
+/* Weak symbol.  */
+#define L_WEAK (0x08)
+
+/* The ldrel structure.  This is used to represent a reloc in the
+   .loader section.  */
+
+struct internal_ldrel
+{
+  /* The reloc address.  */
+  bfd_vma l_vaddr;
+
+  /* The symbol table index in the .loader section symbol table.  */
+  bfd_size_type l_symndx;
+
+  /* The relocation type and size.  */
+  short l_rtype;
+
+  /* The section number this relocation applies to.  */
+  short l_rsecnm;
+};
+
+/* An entry in the XCOFF linker hash table.  */
+struct xcoff_link_hash_entry
+{
+  struct bfd_link_hash_entry root;
+
+  /* Symbol index in output file.  Set to -1 initially.  Set to -2 if
+     there is a reloc against this symbol.  */
+  long indx;
+
+  /* If we have created a TOC entry for this symbol, this is the .tc
+     section which holds it.  */
+  asection *toc_section;
+
+  union
+  {
+    /* If we have created a TOC entry (the XCOFF_SET_TOC flag is
+       set), this is the offset in toc_section.  */
+    bfd_vma toc_offset;
+    
+    /* If the TOC entry comes from an input file, this is set to the
+       symbol index of the C_HIDEXT XMC_TC or XMC_TD symbol.  */
+    long toc_indx;
+  } 
+  u;
+
+  /* If this symbol is a function entry point which is called, this
+     field holds a pointer to the function descriptor.  If this symbol
+     is a function descriptor, this field holds a pointer to the
+     function entry point.  */
+  struct xcoff_link_hash_entry *descriptor;
+
+  /* The .loader symbol table entry, if there is one.  */
+  struct internal_ldsym *ldsym;
+
+  /* If XCOFF_BUILT_LDSYM is set, this is the .loader symbol table
+     index.  If XCOFF_BUILD_LDSYM is clear, and XCOFF_IMPORT is set,
+     this is the l_ifile value.  */
+  long ldindx;
+
+  /* Some linker flags.  */
+  unsigned long flags;
+
+  /* The storage mapping class.  */
+  unsigned char smclas;
+};
+
+/*  Flags for xcoff_link_hash_entry.  */
+
+/* Symbol is referenced by a regular object. */
+#define XCOFF_REF_REGULAR      0x00000001
+/* Symbol is defined by a regular object. */
+#define XCOFF_DEF_REGULAR      0x00000002
+/* Symbol is defined by a dynamic object. */
+#define XCOFF_DEF_DYNAMIC      0x00000004
+/* Symbol is used in a reloc being copied into the .loader section.  */
+#define XCOFF_LDREL            0x00000008
+/* Symbol is the entry point.  */
+#define XCOFF_ENTRY            0x00000010
+/* Symbol is for a function and is the target of a relocation.
+   The relocation may or may not be a branch-type relocation.  */
+#define XCOFF_CALLED           0x00000020
+/* Symbol needs the TOC entry filled in.  */
+#define XCOFF_SET_TOC          0x00000040
+/* Symbol is implicitly or explicitly imported.  */
+#define XCOFF_IMPORT           0x00000080
+/* Symbol is explicitly exported.  */
+#define XCOFF_EXPORT           0x00000100
+/* Symbol has been processed by xcoff_build_ldsyms.  */
+#define XCOFF_BUILT_LDSYM      0x00000200
+/* Symbol is mentioned by a section which was not garbage collected. */
+#define XCOFF_MARK             0x00000400
+/* Symbol size is recorded in size_list list from hash table.  */
+#define XCOFF_HAS_SIZE         0x00000800
+/* Symbol is a function descriptor.  */
+#define XCOFF_DESCRIPTOR       0x00001000
+/* Multiple definitions have been for the symbol. */
+#define XCOFF_MULTIPLY_DEFINED 0x00002000
+/* Symbol is the __rtinit symbol.  */
+#define XCOFF_RTINIT           0x00004000
+/* Symbol is an imported 32 bit syscall.  */
+#define XCOFF_SYSCALL32        0x00008000
+/* Symbol is an imported 64 bit syscall.  */
+#define XCOFF_SYSCALL64        0x00010000 
+/* Symbol was not explicitly defined by the time it was marked.  */
+#define XCOFF_WAS_UNDEFINED    0x00020000
+/* We have assigned an output XCOFF entry to this symbol.  */
+#define XCOFF_ALLOCATED	       0x00040000
+
+/* The XCOFF linker hash table.  */
+
+#define XCOFF_NUMBER_OF_SPECIAL_SECTIONS 6
+#define XCOFF_SPECIAL_SECTION_TEXT       0
+#define XCOFF_SPECIAL_SECTION_ETEXT      1 
+#define XCOFF_SPECIAL_SECTION_DATA       2
+#define XCOFF_SPECIAL_SECTION_EDATA      3
+#define XCOFF_SPECIAL_SECTION_END        4
+#define XCOFF_SPECIAL_SECTION_END2       5
+
+/* These flags indicate which of -bexpall and -bexpfull are in effect.  */
+#define XCOFF_EXPALL 1
+#define XCOFF_EXPFULL 2
+
+/* This structure is used to pass information through
+   xcoff_link_hash_traverse.  */
+
+struct xcoff_loader_info
+{
+  /* Set if a problem occurred.  */
+  bfd_boolean failed;
+
+  /* Output BFD.  */
+  bfd *output_bfd;
+
+  /* Link information structure.  */
+  struct bfd_link_info *info;
+
+  /* A mask of XCOFF_EXPALL and XCOFF_EXPFULL flags.  */
+  unsigned int auto_export_flags;
+
+  /* Number of ldsym structures.  */
+  size_t ldsym_count;
+
+  /* Size of string table.  */
+  size_t string_size;
+
+  /* String table.  */
+  char *strings;
+
+  /* Allocated size of string table.  */
+  size_t string_alc;
+};
+
+/* In case we're on a 32-bit machine, construct a 64-bit "-1" value
+   from smaller values.  Start with zero, widen, *then* decrement.  */
+#define MINUS_ONE       (((bfd_vma) 0) - 1)
+
+/* __rtinit, from /usr/include/rtinit.h.  */
+struct __rtinit 
+{
+  /* Pointer to runtime linker.     
+     XXX: Is the parameter really void?  */
+  int	(*rtl) (void);	
+
+  /* Offset to array of init functions, 0 if none. */
+  int	init_offset;
+
+  /* Offset to array of fini functions, 0 if none. */		   
+  int	fini_offset;		
+
+  /* Size of __RTINIT_DESCRIPTOR. This value should be used instead of 
+     sizeof(__RTINIT_DESCRIPTOR). */
+  int	__rtinit_descriptor_size; 
+};
+
+#define RTINIT_DESCRIPTOR_SIZE (12)
+
+struct __rtinit_descriptor 
+{
+  /* Init/fini function. */
+  int	f;
+
+  /* Offset, relative to the start of the __rtinit symbol, to name of the 
+     function. */
+
+  int	name_offset;	
+
+  /* Flags */			   
+  unsigned char	flags;	
+};
+
+/* Archive */
+
+#define XCOFFARMAG    "<aiaff>\012"
+#define XCOFFARMAGBIG "<bigaf>\012"
+#define SXCOFFARMAG   8
+
+/* The size of the ascii archive elements */
+#define XCOFFARMAG_ELEMENT_SIZE 12
+#define XCOFFARMAGBIG_ELEMENT_SIZE 20
+
+/* This terminates an XCOFF archive member name.  */
+
+#define XCOFFARFMAG "`\012"
+#define SXCOFFARFMAG 2
+
+/* XCOFF archives start with this (printable) structure.  */
+
+struct xcoff_ar_file_hdr
+{
+  /* Magic string.  */
+  char magic[SXCOFFARMAG];
+
+  /* Offset of the member table (decimal ASCII string).  */
+  char memoff[XCOFFARMAG_ELEMENT_SIZE];
+
+  /* Offset of the global symbol table (decimal ASCII string).  */
+  char symoff[XCOFFARMAG_ELEMENT_SIZE];
+
+  /* Offset of the first member in the archive (decimal ASCII string).  */
+  char firstmemoff[XCOFFARMAG_ELEMENT_SIZE];
+
+  /* Offset of the last member in the archive (decimal ASCII string).  */
+  char lastmemoff[XCOFFARMAG_ELEMENT_SIZE];
+
+  /* Offset of the first member on the free list (decimal ASCII
+     string).  */
+  char freeoff[XCOFFARMAG_ELEMENT_SIZE];
+};
+
+#define SIZEOF_AR_FILE_HDR (SXCOFFARMAG + 5 * XCOFFARMAG_ELEMENT_SIZE)
+
+/* This is the equivalent data structure for the big archive format.  */
+
+struct xcoff_ar_file_hdr_big
+{
+  /* Magic string.  */
+  char magic[SXCOFFARMAG];
+
+  /* Offset of the member table (decimal ASCII string).  */
+  char memoff[XCOFFARMAGBIG_ELEMENT_SIZE];
+
+  /* Offset of the global symbol table for 32-bit objects (decimal ASCII
+     string).  */
+  char symoff[XCOFFARMAGBIG_ELEMENT_SIZE];
+
+  /* Offset of the global symbol table for 64-bit objects (decimal ASCII
+     string).  */
+  char symoff64[XCOFFARMAGBIG_ELEMENT_SIZE];
+
+  /* Offset of the first member in the archive (decimal ASCII string).  */
+  char firstmemoff[XCOFFARMAGBIG_ELEMENT_SIZE];
+
+  /* Offset of the last member in the archive (decimal ASCII string).  */
+  char lastmemoff[XCOFFARMAGBIG_ELEMENT_SIZE];
+
+  /* Offset of the first member on the free list (decimal ASCII
+     string).  */
+  char freeoff[XCOFFARMAGBIG_ELEMENT_SIZE];
+};
+
+#define SIZEOF_AR_FILE_HDR_BIG (SXCOFFARMAG + 6 * XCOFFARMAGBIG_ELEMENT_SIZE)
+
+/* Each XCOFF archive member starts with this (printable) structure.  */
+
+struct xcoff_ar_hdr
+{
+  /* File size not including the header (decimal ASCII string).  */
+  char size[XCOFFARMAG_ELEMENT_SIZE];
+
+  /* File offset of next archive member (decimal ASCII string).  */
+  char nextoff[XCOFFARMAG_ELEMENT_SIZE];
+
+  /* File offset of previous archive member (decimal ASCII string).  */
+  char prevoff[XCOFFARMAG_ELEMENT_SIZE];
+
+  /* File mtime (decimal ASCII string).  */
+  char date[12];
+
+  /* File UID (decimal ASCII string).  */
+  char uid[12];
+
+  /* File GID (decimal ASCII string).  */
+  char gid[12];
+
+  /* File mode (octal ASCII string).  */
+  char mode[12];
+
+  /* Length of file name (decimal ASCII string).  */
+  char namlen[4];
+
+  /* This structure is followed by the file name.  The length of the
+     name is given in the namlen field.  If the length of the name is
+     odd, the name is followed by a null byte.  The name and optional
+     null byte are followed by XCOFFARFMAG, which is not included in
+     namlen.  The contents of the archive member follow; the number of
+     bytes is given in the size field.  */
+};
+
+#define SIZEOF_AR_HDR (3 * XCOFFARMAG_ELEMENT_SIZE + 4 * 12 + 4)
+
+/* The equivalent for the big archive format.  */
+
+struct xcoff_ar_hdr_big
+{
+  /* File size not including the header (decimal ASCII string).  */
+  char size[XCOFFARMAGBIG_ELEMENT_SIZE];
+
+  /* File offset of next archive member (decimal ASCII string).  */
+  char nextoff[XCOFFARMAGBIG_ELEMENT_SIZE];
+
+  /* File offset of previous archive member (decimal ASCII string).  */
+  char prevoff[XCOFFARMAGBIG_ELEMENT_SIZE];
+
+  /* File mtime (decimal ASCII string).  */
+  char date[12];
+
+  /* File UID (decimal ASCII string).  */
+  char uid[12];
+
+  /* File GID (decimal ASCII string).  */
+  char gid[12];
+
+  /* File mode (octal ASCII string).  */
+  char mode[12];
+
+  /* Length of file name (decimal ASCII string).  */
+  char namlen[4];
+
+  /* This structure is followed by the file name.  The length of the
+     name is given in the namlen field.  If the length of the name is
+     odd, the name is followed by a null byte.  The name and optional
+     null byte are followed by XCOFFARFMAG, which is not included in
+     namlen.  The contents of the archive member follow; the number of
+     bytes is given in the size field.  */
+};
+
+#define SIZEOF_AR_HDR_BIG (3 * XCOFFARMAGBIG_ELEMENT_SIZE + 4 * 12 + 4)
+
+/* We often have to distinguish between the old and big file format.
+   Make it a bit cleaner.  We can use `xcoff_ardata' here because the
+   `hdr' member has the same size and position in both formats.  
+   <bigaf> is the default format, return TRUE even when xcoff_ardata is 
+   NULL. */
+#ifndef SMALL_ARCHIVE
+/* Creates big archives by default */
+#define xcoff_big_format_p(abfd) \
+  ((NULL != bfd_ardata (abfd) && NULL == xcoff_ardata (abfd)) || \
+   ((NULL != bfd_ardata (abfd)) && \
+    (NULL != xcoff_ardata (abfd)) && \
+    (xcoff_ardata (abfd)->magic[1] == 'b')))
+#else
+/* Creates small archives by default. */
+#define xcoff_big_format_p(abfd) \
+  (((NULL != bfd_ardata (abfd)) && \
+    (NULL != xcoff_ardata (abfd)) && \
+    (xcoff_ardata (abfd)->magic[1] == 'b')))
+#endif
+
+/* We store a copy of the xcoff_ar_file_hdr in the tdata field of the
+   artdata structure.  Similar for the big archive.  */
+#define xcoff_ardata(abfd) \
+  ((struct xcoff_ar_file_hdr *) bfd_ardata (abfd)->tdata)
+#define xcoff_ardata_big(abfd) \
+  ((struct xcoff_ar_file_hdr_big *) bfd_ardata (abfd)->tdata)
+
+/* We store a copy of the xcoff_ar_hdr in the arelt_data field of an
+   archive element.  Similar for the big archive.  */
+#define arch_eltdata(bfd) ((struct areltdata *) ((bfd)->arelt_data))
+#define arch_xhdr(bfd) \
+  ((struct xcoff_ar_hdr *) arch_eltdata (bfd)->arch_header)
+#define arch_xhdr_big(bfd) \
+  ((struct xcoff_ar_hdr_big *) arch_eltdata (bfd)->arch_header)
+
+/* True if symbols of class CLASS are external.  */
+#define EXTERN_SYM_P(CLASS) \
+  ((CLASS) == C_EXT || (CLASS) == C_AIX_WEAKEXT)
+
+#endif /* _INTERNAL_XCOFF_H */
diff --git a/binutils-2.25/include/coff/z80.h b/binutils-2.25/include/coff/z80.h
new file mode 100644
index 00000000..712af054
--- /dev/null
+++ b/binutils-2.25/include/coff/z80.h
@@ -0,0 +1,60 @@
+/* coff information for Zilog Z80
+   Copyright 2005, 2010 Free Software Foundation, Inc.
+   Contributed by Arnold Metselaar <arnold_m@operamail.com>
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#define L_LNNO_SIZE 4
+#include "coff/external.h"
+
+/* z80 backend does not use dots in section names.  */
+#undef  _TEXT
+#define _TEXT "text"
+#undef  _DATA
+#define _DATA "data"
+#undef  _BSS
+#define _BSS "bss"
+
+/* Type of cpu is stored in flags.  */
+#define F_MACHMASK 0xF000
+
+/* Z80 COFF encodes the section alignment in the section header flags */
+#define COFF_ALIGN_IN_SECTION_HEADER 1
+#define COFF_ALIGN_IN_S_FLAGS 1
+#define F_ALGNMASK 0x0F00
+/* requires a power-of-two argument */
+#define COFF_ENCODE_ALIGNMENT(S,X) ((S).s_flags |= (((unsigned)(X)&0xF)<<8))
+/* result is a power of two */
+#define COFF_DECODE_ALIGNMENT(X) (((X)>>8)&0xF)
+
+#define	Z80MAGIC   0x805A
+
+#define Z80BADMAG(x) (((x).f_magic != Z80MAGIC))
+
+/* Relocation directives.  */
+
+/* This format actually has more bits than we need.  */
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_offset[4];
+  char r_type[2];
+  char r_stuff[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 16
diff --git a/binutils-2.25/include/coff/z8k.h b/binutils-2.25/include/coff/z8k.h
new file mode 100644
index 00000000..5eef86d4
--- /dev/null
+++ b/binutils-2.25/include/coff/z8k.h
@@ -0,0 +1,49 @@
+/* coff information for Zilog Z800N
+   
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define L_LNNO_SIZE 4
+#include "coff/external.h"
+
+/* Type of cpu is stored in flags */
+#define F_Z8001    0x1000
+#define F_Z8002    0x2000
+#define F_MACHMASK 0xf000
+
+#define	Z8KMAGIC   0x8000
+
+#define Z8KBADMAG(x) (((x).f_magic != Z8KMAGIC))
+  
+/********************** RELOCATION DIRECTIVES **********************/
+
+/* The external reloc has an offset field, because some of the reloc
+   types on the z8k don't have room in the instruction for the entire
+   offset - eg with segments.  */
+
+struct external_reloc
+{
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_offset[4];
+  char r_type[2];
+  char r_stuff[2];
+};
+
+#define RELOC struct external_reloc
+#define RELSZ 16
+
diff --git a/binutils-2.25/include/demangle.h b/binutils-2.25/include/demangle.h
new file mode 100644
index 00000000..bbad71bd
--- /dev/null
+++ b/binutils-2.25/include/demangle.h
@@ -0,0 +1,679 @@
+/* Defs for interface to demanglers.
+   Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002,
+   2003, 2004, 2005, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+   
+   This program is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Library General Public License
+   as published by the Free Software Foundation; either version 2, or
+   (at your option) any later version.
+
+   In addition to the permissions in the GNU Library General Public
+   License, the Free Software Foundation gives you unlimited
+   permission to link the compiled version of this file into
+   combinations with other programs, and to distribute those
+   combinations without any restriction coming from the use of this
+   file.  (The Library Public License restrictions do apply in other
+   respects; for example, they cover modification of the file, and
+   distribution when not linked into a combined executable.)
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Library General Public License for more details.
+
+   You should have received a copy of the GNU Library General Public
+   License along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+
+#if !defined (DEMANGLE_H)
+#define DEMANGLE_H
+
+#include "libiberty.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Options passed to cplus_demangle (in 2nd parameter). */
+
+#define DMGL_NO_OPTS	 0		/* For readability... */
+#define DMGL_PARAMS	 (1 << 0)	/* Include function args */
+#define DMGL_ANSI	 (1 << 1)	/* Include const, volatile, etc */
+#define DMGL_JAVA	 (1 << 2)	/* Demangle as Java rather than C++. */
+#define DMGL_VERBOSE	 (1 << 3)	/* Include implementation details.  */
+#define DMGL_TYPES	 (1 << 4)	/* Also try to demangle type encodings.  */
+#define DMGL_RET_POSTFIX (1 << 5)       /* Print function return types (when
+					   present) after function signature.
+					   It applies only to the toplevel
+					   function type.  */
+#define DMGL_RET_DROP	 (1 << 6)       /* Suppress printing function return
+					   types, even if present.  It applies
+					   only to the toplevel function type.
+					   */
+
+#define DMGL_AUTO	 (1 << 8)
+#define DMGL_GNU	 (1 << 9)
+#define DMGL_LUCID	 (1 << 10)
+#define DMGL_ARM	 (1 << 11)
+#define DMGL_HP 	 (1 << 12)       /* For the HP aCC compiler;
+                                            same as ARM except for
+                                            template arguments, etc. */
+#define DMGL_EDG	 (1 << 13)
+#define DMGL_GNU_V3	 (1 << 14)
+#define DMGL_GNAT	 (1 << 15)
+
+/* If none of these are set, use 'current_demangling_style' as the default. */
+#define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU|DMGL_LUCID|DMGL_ARM|DMGL_HP|DMGL_EDG|DMGL_GNU_V3|DMGL_JAVA|DMGL_GNAT)
+
+/* Enumeration of possible demangling styles.
+
+   Lucid and ARM styles are still kept logically distinct, even though
+   they now both behave identically.  The resulting style is actual the
+   union of both.  I.E. either style recognizes both "__pt__" and "__rf__"
+   for operator "->", even though the first is lucid style and the second
+   is ARM style. (FIXME?) */
+
+extern enum demangling_styles
+{
+  no_demangling = -1,
+  unknown_demangling = 0,
+  auto_demangling = DMGL_AUTO,
+  gnu_demangling = DMGL_GNU,
+  lucid_demangling = DMGL_LUCID,
+  arm_demangling = DMGL_ARM,
+  hp_demangling = DMGL_HP,
+  edg_demangling = DMGL_EDG,
+  gnu_v3_demangling = DMGL_GNU_V3,
+  java_demangling = DMGL_JAVA,
+  gnat_demangling = DMGL_GNAT
+} current_demangling_style;
+
+/* Define string names for the various demangling styles. */
+
+#define NO_DEMANGLING_STYLE_STRING            "none"
+#define AUTO_DEMANGLING_STYLE_STRING	      "auto"
+#define GNU_DEMANGLING_STYLE_STRING    	      "gnu"
+#define LUCID_DEMANGLING_STYLE_STRING	      "lucid"
+#define ARM_DEMANGLING_STYLE_STRING	      "arm"
+#define HP_DEMANGLING_STYLE_STRING	      "hp"
+#define EDG_DEMANGLING_STYLE_STRING	      "edg"
+#define GNU_V3_DEMANGLING_STYLE_STRING        "gnu-v3"
+#define JAVA_DEMANGLING_STYLE_STRING          "java"
+#define GNAT_DEMANGLING_STYLE_STRING          "gnat"
+
+/* Some macros to test what demangling style is active. */
+
+#define CURRENT_DEMANGLING_STYLE current_demangling_style
+#define AUTO_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_AUTO)
+#define GNU_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNU)
+#define LUCID_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_LUCID)
+#define ARM_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_ARM)
+#define HP_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_HP)
+#define EDG_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_EDG)
+#define GNU_V3_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNU_V3)
+#define JAVA_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_JAVA)
+#define GNAT_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNAT)
+
+/* Provide information about the available demangle styles. This code is
+   pulled from gdb into libiberty because it is useful to binutils also.  */
+
+extern const struct demangler_engine
+{
+  const char *const demangling_style_name;
+  const enum demangling_styles demangling_style;
+  const char *const demangling_style_doc;
+} libiberty_demanglers[];
+
+extern char *
+cplus_demangle (const char *mangled, int options);
+
+extern int
+cplus_demangle_opname (const char *opname, char *result, int options);
+
+extern const char *
+cplus_mangle_opname (const char *opname, int options);
+
+/* Note: This sets global state.  FIXME if you care about multi-threading. */
+
+extern void
+set_cplus_marker_for_demangling (int ch);
+
+extern enum demangling_styles 
+cplus_demangle_set_style (enum demangling_styles style);
+
+extern enum demangling_styles 
+cplus_demangle_name_to_style (const char *name);
+
+/* Callback typedef for allocation-less demangler interfaces. */
+typedef void (*demangle_callbackref) (const char *, size_t, void *);
+
+/* V3 ABI demangling entry points, defined in cp-demangle.c.  Callback
+   variants return non-zero on success, zero on error.  char* variants
+   return a string allocated by malloc on success, NULL on error.  */
+extern int
+cplus_demangle_v3_callback (const char *mangled, int options,
+                            demangle_callbackref callback, void *opaque);
+
+extern char*
+cplus_demangle_v3 (const char *mangled, int options);
+
+extern int
+java_demangle_v3_callback (const char *mangled,
+                           demangle_callbackref callback, void *opaque);
+
+extern char*
+java_demangle_v3 (const char *mangled);
+
+char *
+ada_demangle (const char *mangled, int options);
+
+enum gnu_v3_ctor_kinds {
+  gnu_v3_complete_object_ctor = 1,
+  gnu_v3_base_object_ctor,
+  gnu_v3_complete_object_allocating_ctor,
+  /* These are not part of the V3 ABI.  Unified constructors are generated
+     as a speed-for-space optimization when the -fdeclone-ctor-dtor option
+     is used, and are always internal symbols.  */
+  gnu_v3_unified_ctor,
+  gnu_v3_object_ctor_group
+};
+
+/* Return non-zero iff NAME is the mangled form of a constructor name
+   in the G++ V3 ABI demangling style.  Specifically, return an `enum
+   gnu_v3_ctor_kinds' value indicating what kind of constructor
+   it is.  */
+extern enum gnu_v3_ctor_kinds
+	is_gnu_v3_mangled_ctor (const char *name);
+
+
+enum gnu_v3_dtor_kinds {
+  gnu_v3_deleting_dtor = 1,
+  gnu_v3_complete_object_dtor,
+  gnu_v3_base_object_dtor,
+  /* These are not part of the V3 ABI.  Unified destructors are generated
+     as a speed-for-space optimization when the -fdeclone-ctor-dtor option
+     is used, and are always internal symbols.  */
+  gnu_v3_unified_dtor,
+  gnu_v3_object_dtor_group
+};
+
+/* Return non-zero iff NAME is the mangled form of a destructor name
+   in the G++ V3 ABI demangling style.  Specifically, return an `enum
+   gnu_v3_dtor_kinds' value, indicating what kind of destructor
+   it is.  */
+extern enum gnu_v3_dtor_kinds
+	is_gnu_v3_mangled_dtor (const char *name);
+
+/* The V3 demangler works in two passes.  The first pass builds a tree
+   representation of the mangled name, and the second pass turns the
+   tree representation into a demangled string.  Here we define an
+   interface to permit a caller to build their own tree
+   representation, which they can pass to the demangler to get a
+   demangled string.  This can be used to canonicalize user input into
+   something which the demangler might output.  It could also be used
+   by other demanglers in the future.  */
+
+/* These are the component types which may be found in the tree.  Many
+   component types have one or two subtrees, referred to as left and
+   right (a component type with only one subtree puts it in the left
+   subtree).  */
+
+enum demangle_component_type
+{
+  /* A name, with a length and a pointer to a string.  */
+  DEMANGLE_COMPONENT_NAME,
+  /* A qualified name.  The left subtree is a class or namespace or
+     some such thing, and the right subtree is a name qualified by
+     that class.  */
+  DEMANGLE_COMPONENT_QUAL_NAME,
+  /* A local name.  The left subtree describes a function, and the
+     right subtree is a name which is local to that function.  */
+  DEMANGLE_COMPONENT_LOCAL_NAME,
+  /* A typed name.  The left subtree is a name, and the right subtree
+     describes that name as a function.  */
+  DEMANGLE_COMPONENT_TYPED_NAME,
+  /* A template.  The left subtree is a template name, and the right
+     subtree is a template argument list.  */
+  DEMANGLE_COMPONENT_TEMPLATE,
+  /* A template parameter.  This holds a number, which is the template
+     parameter index.  */
+  DEMANGLE_COMPONENT_TEMPLATE_PARAM,
+  /* A function parameter.  This holds a number, which is the index.  */
+  DEMANGLE_COMPONENT_FUNCTION_PARAM,
+  /* A constructor.  This holds a name and the kind of
+     constructor.  */
+  DEMANGLE_COMPONENT_CTOR,
+  /* A destructor.  This holds a name and the kind of destructor.  */
+  DEMANGLE_COMPONENT_DTOR,
+  /* A vtable.  This has one subtree, the type for which this is a
+     vtable.  */
+  DEMANGLE_COMPONENT_VTABLE,
+  /* A VTT structure.  This has one subtree, the type for which this
+     is a VTT.  */
+  DEMANGLE_COMPONENT_VTT,
+  /* A construction vtable.  The left subtree is the type for which
+     this is a vtable, and the right subtree is the derived type for
+     which this vtable is built.  */
+  DEMANGLE_COMPONENT_CONSTRUCTION_VTABLE,
+  /* A typeinfo structure.  This has one subtree, the type for which
+     this is the tpeinfo structure.  */
+  DEMANGLE_COMPONENT_TYPEINFO,
+  /* A typeinfo name.  This has one subtree, the type for which this
+     is the typeinfo name.  */
+  DEMANGLE_COMPONENT_TYPEINFO_NAME,
+  /* A typeinfo function.  This has one subtree, the type for which
+     this is the tpyeinfo function.  */
+  DEMANGLE_COMPONENT_TYPEINFO_FN,
+  /* A thunk.  This has one subtree, the name for which this is a
+     thunk.  */
+  DEMANGLE_COMPONENT_THUNK,
+  /* A virtual thunk.  This has one subtree, the name for which this
+     is a virtual thunk.  */
+  DEMANGLE_COMPONENT_VIRTUAL_THUNK,
+  /* A covariant thunk.  This has one subtree, the name for which this
+     is a covariant thunk.  */
+  DEMANGLE_COMPONENT_COVARIANT_THUNK,
+  /* A Java class.  This has one subtree, the type.  */
+  DEMANGLE_COMPONENT_JAVA_CLASS,
+  /* A guard variable.  This has one subtree, the name for which this
+     is a guard variable.  */
+  DEMANGLE_COMPONENT_GUARD,
+  /* The init and wrapper functions for C++11 thread_local variables.  */
+  DEMANGLE_COMPONENT_TLS_INIT,
+  DEMANGLE_COMPONENT_TLS_WRAPPER,
+  /* A reference temporary.  This has one subtree, the name for which
+     this is a temporary.  */
+  DEMANGLE_COMPONENT_REFTEMP,
+  /* A hidden alias.  This has one subtree, the encoding for which it
+     is providing alternative linkage.  */
+  DEMANGLE_COMPONENT_HIDDEN_ALIAS,
+  /* A standard substitution.  This holds the name of the
+     substitution.  */
+  DEMANGLE_COMPONENT_SUB_STD,
+  /* The restrict qualifier.  The one subtree is the type which is
+     being qualified.  */
+  DEMANGLE_COMPONENT_RESTRICT,
+  /* The volatile qualifier.  The one subtree is the type which is
+     being qualified.  */
+  DEMANGLE_COMPONENT_VOLATILE,
+  /* The const qualifier.  The one subtree is the type which is being
+     qualified.  */
+  DEMANGLE_COMPONENT_CONST,
+  /* The restrict qualifier modifying a member function.  The one
+     subtree is the type which is being qualified.  */
+  DEMANGLE_COMPONENT_RESTRICT_THIS,
+  /* The volatile qualifier modifying a member function.  The one
+     subtree is the type which is being qualified.  */
+  DEMANGLE_COMPONENT_VOLATILE_THIS,
+  /* The const qualifier modifying a member function.  The one subtree
+     is the type which is being qualified.  */
+  DEMANGLE_COMPONENT_CONST_THIS,
+  /* C++11 A reference modifying a member function.  The one subtree is the
+     type which is being referenced.  */
+  DEMANGLE_COMPONENT_REFERENCE_THIS,
+  /* C++11: An rvalue reference modifying a member function.  The one
+     subtree is the type which is being referenced.  */
+  DEMANGLE_COMPONENT_RVALUE_REFERENCE_THIS,
+  /* A vendor qualifier.  The left subtree is the type which is being
+     qualified, and the right subtree is the name of the
+     qualifier.  */
+  DEMANGLE_COMPONENT_VENDOR_TYPE_QUAL,
+  /* A pointer.  The one subtree is the type which is being pointed
+     to.  */
+  DEMANGLE_COMPONENT_POINTER,
+  /* A reference.  The one subtree is the type which is being
+     referenced.  */
+  DEMANGLE_COMPONENT_REFERENCE,
+  /* C++0x: An rvalue reference.  The one subtree is the type which is
+     being referenced.  */
+  DEMANGLE_COMPONENT_RVALUE_REFERENCE,
+  /* A complex type.  The one subtree is the base type.  */
+  DEMANGLE_COMPONENT_COMPLEX,
+  /* An imaginary type.  The one subtree is the base type.  */
+  DEMANGLE_COMPONENT_IMAGINARY,
+  /* A builtin type.  This holds the builtin type information.  */
+  DEMANGLE_COMPONENT_BUILTIN_TYPE,
+  /* A vendor's builtin type.  This holds the name of the type.  */
+  DEMANGLE_COMPONENT_VENDOR_TYPE,
+  /* A function type.  The left subtree is the return type.  The right
+     subtree is a list of ARGLIST nodes.  Either or both may be
+     NULL.  */
+  DEMANGLE_COMPONENT_FUNCTION_TYPE,
+  /* An array type.  The left subtree is the dimension, which may be
+     NULL, or a string (represented as DEMANGLE_COMPONENT_NAME), or an
+     expression.  The right subtree is the element type.  */
+  DEMANGLE_COMPONENT_ARRAY_TYPE,
+  /* A pointer to member type.  The left subtree is the class type,
+     and the right subtree is the member type.  CV-qualifiers appear
+     on the latter.  */
+  DEMANGLE_COMPONENT_PTRMEM_TYPE,
+  /* A fixed-point type.  */
+  DEMANGLE_COMPONENT_FIXED_TYPE,
+  /* A vector type.  The left subtree is the number of elements,
+     the right subtree is the element type.  */
+  DEMANGLE_COMPONENT_VECTOR_TYPE,
+  /* An argument list.  The left subtree is the current argument, and
+     the right subtree is either NULL or another ARGLIST node.  */
+  DEMANGLE_COMPONENT_ARGLIST,
+  /* A template argument list.  The left subtree is the current
+     template argument, and the right subtree is either NULL or
+     another TEMPLATE_ARGLIST node.  */
+  DEMANGLE_COMPONENT_TEMPLATE_ARGLIST,
+  /* An initializer list.  The left subtree is either an explicit type or
+     NULL, and the right subtree is a DEMANGLE_COMPONENT_ARGLIST.  */
+  DEMANGLE_COMPONENT_INITIALIZER_LIST,
+  /* An operator.  This holds information about a standard
+     operator.  */
+  DEMANGLE_COMPONENT_OPERATOR,
+  /* An extended operator.  This holds the number of arguments, and
+     the name of the extended operator.  */
+  DEMANGLE_COMPONENT_EXTENDED_OPERATOR,
+  /* A typecast, represented as a unary operator.  The one subtree is
+     the type to which the argument should be cast.  */
+  DEMANGLE_COMPONENT_CAST,
+  /* A nullary expression.  The left subtree is the operator.  */
+  DEMANGLE_COMPONENT_NULLARY,
+  /* A unary expression.  The left subtree is the operator, and the
+     right subtree is the single argument.  */
+  DEMANGLE_COMPONENT_UNARY,
+  /* A binary expression.  The left subtree is the operator, and the
+     right subtree is a BINARY_ARGS.  */
+  DEMANGLE_COMPONENT_BINARY,
+  /* Arguments to a binary expression.  The left subtree is the first
+     argument, and the right subtree is the second argument.  */
+  DEMANGLE_COMPONENT_BINARY_ARGS,
+  /* A trinary expression.  The left subtree is the operator, and the
+     right subtree is a TRINARY_ARG1.  */
+  DEMANGLE_COMPONENT_TRINARY,
+  /* Arguments to a trinary expression.  The left subtree is the first
+     argument, and the right subtree is a TRINARY_ARG2.  */
+  DEMANGLE_COMPONENT_TRINARY_ARG1,
+  /* More arguments to a trinary expression.  The left subtree is the
+     second argument, and the right subtree is the third argument.  */
+  DEMANGLE_COMPONENT_TRINARY_ARG2,
+  /* A literal.  The left subtree is the type, and the right subtree
+     is the value, represented as a DEMANGLE_COMPONENT_NAME.  */
+  DEMANGLE_COMPONENT_LITERAL,
+  /* A negative literal.  Like LITERAL, but the value is negated.
+     This is a minor hack: the NAME used for LITERAL points directly
+     to the mangled string, but since negative numbers are mangled
+     using 'n' instead of '-', we want a way to indicate a negative
+     number which involves neither modifying the mangled string nor
+     allocating a new copy of the literal in memory.  */
+  DEMANGLE_COMPONENT_LITERAL_NEG,
+  /* A libgcj compiled resource.  The left subtree is the name of the
+     resource.  */
+  DEMANGLE_COMPONENT_JAVA_RESOURCE,
+  /* A name formed by the concatenation of two parts.  The left
+     subtree is the first part and the right subtree the second.  */
+  DEMANGLE_COMPONENT_COMPOUND_NAME,
+  /* A name formed by a single character.  */
+  DEMANGLE_COMPONENT_CHARACTER,
+  /* A number.  */
+  DEMANGLE_COMPONENT_NUMBER,
+  /* A decltype type.  */
+  DEMANGLE_COMPONENT_DECLTYPE,
+  /* Global constructors keyed to name.  */
+  DEMANGLE_COMPONENT_GLOBAL_CONSTRUCTORS,
+  /* Global destructors keyed to name.  */
+  DEMANGLE_COMPONENT_GLOBAL_DESTRUCTORS,
+  /* A lambda closure type.  */
+  DEMANGLE_COMPONENT_LAMBDA,
+  /* A default argument scope.  */
+  DEMANGLE_COMPONENT_DEFAULT_ARG,
+  /* An unnamed type.  */
+  DEMANGLE_COMPONENT_UNNAMED_TYPE,
+  /* A transactional clone.  This has one subtree, the encoding for
+     which it is providing alternative linkage.  */
+  DEMANGLE_COMPONENT_TRANSACTION_CLONE,
+  /* A non-transactional clone entry point.  In the i386/x86_64 abi,
+     the unmangled symbol of a tm_callable becomes a thunk and the
+     non-transactional function version is mangled thus.  */
+  DEMANGLE_COMPONENT_NONTRANSACTION_CLONE,
+  /* A pack expansion.  */
+  DEMANGLE_COMPONENT_PACK_EXPANSION,
+  /* A name with an ABI tag.  */
+  DEMANGLE_COMPONENT_TAGGED_NAME,
+  /* A cloned function.  */
+  DEMANGLE_COMPONENT_CLONE
+};
+
+/* Types which are only used internally.  */
+
+struct demangle_operator_info;
+struct demangle_builtin_type_info;
+
+/* A node in the tree representation is an instance of a struct
+   demangle_component.  Note that the field names of the struct are
+   not well protected against macros defined by the file including
+   this one.  We can fix this if it ever becomes a problem.  */
+
+struct demangle_component
+{
+  /* The type of this component.  */
+  enum demangle_component_type type;
+
+  union
+  {
+    /* For DEMANGLE_COMPONENT_NAME.  */
+    struct
+    {
+      /* A pointer to the name (which need not NULL terminated) and
+	 its length.  */
+      const char *s;
+      int len;
+    } s_name;
+
+    /* For DEMANGLE_COMPONENT_OPERATOR.  */
+    struct
+    {
+      /* Operator.  */
+      const struct demangle_operator_info *op;
+    } s_operator;
+
+    /* For DEMANGLE_COMPONENT_EXTENDED_OPERATOR.  */
+    struct
+    {
+      /* Number of arguments.  */
+      int args;
+      /* Name.  */
+      struct demangle_component *name;
+    } s_extended_operator;
+
+    /* For DEMANGLE_COMPONENT_FIXED_TYPE.  */
+    struct
+    {
+      /* The length, indicated by a C integer type name.  */
+      struct demangle_component *length;
+      /* _Accum or _Fract?  */
+      short accum;
+      /* Saturating or not?  */
+      short sat;
+    } s_fixed;
+
+    /* For DEMANGLE_COMPONENT_CTOR.  */
+    struct
+    {
+      /* Kind of constructor.  */
+      enum gnu_v3_ctor_kinds kind;
+      /* Name.  */
+      struct demangle_component *name;
+    } s_ctor;
+
+    /* For DEMANGLE_COMPONENT_DTOR.  */
+    struct
+    {
+      /* Kind of destructor.  */
+      enum gnu_v3_dtor_kinds kind;
+      /* Name.  */
+      struct demangle_component *name;
+    } s_dtor;
+
+    /* For DEMANGLE_COMPONENT_BUILTIN_TYPE.  */
+    struct
+    {
+      /* Builtin type.  */
+      const struct demangle_builtin_type_info *type;
+    } s_builtin;
+
+    /* For DEMANGLE_COMPONENT_SUB_STD.  */
+    struct
+    {
+      /* Standard substitution string.  */
+      const char* string;
+      /* Length of string.  */
+      int len;
+    } s_string;
+
+    /* For DEMANGLE_COMPONENT_*_PARAM.  */
+    struct
+    {
+      /* Parameter index.  */
+      long number;
+    } s_number;
+
+    /* For DEMANGLE_COMPONENT_CHARACTER.  */
+    struct
+    {
+      int character;
+    } s_character;
+
+    /* For other types.  */
+    struct
+    {
+      /* Left (or only) subtree.  */
+      struct demangle_component *left;
+      /* Right subtree.  */
+      struct demangle_component *right;
+    } s_binary;
+
+    struct
+    {
+      /* subtree, same place as d_left.  */
+      struct demangle_component *sub;
+      /* integer.  */
+      int num;
+    } s_unary_num;
+
+  } u;
+};
+
+/* People building mangled trees are expected to allocate instances of
+   struct demangle_component themselves.  They can then call one of
+   the following functions to fill them in.  */
+
+/* Fill in most component types with a left subtree and a right
+   subtree.  Returns non-zero on success, zero on failure, such as an
+   unrecognized or inappropriate component type.  */
+
+extern int
+cplus_demangle_fill_component (struct demangle_component *fill,
+                               enum demangle_component_type,
+                               struct demangle_component *left,
+                               struct demangle_component *right);
+
+/* Fill in a DEMANGLE_COMPONENT_NAME.  Returns non-zero on success,
+   zero for bad arguments.  */
+
+extern int
+cplus_demangle_fill_name (struct demangle_component *fill,
+                          const char *, int);
+
+/* Fill in a DEMANGLE_COMPONENT_BUILTIN_TYPE, using the name of the
+   builtin type (e.g., "int", etc.).  Returns non-zero on success,
+   zero if the type is not recognized.  */
+
+extern int
+cplus_demangle_fill_builtin_type (struct demangle_component *fill,
+                                  const char *type_name);
+
+/* Fill in a DEMANGLE_COMPONENT_OPERATOR, using the name of the
+   operator and the number of arguments which it takes (the latter is
+   used to disambiguate operators which can be both binary and unary,
+   such as '-').  Returns non-zero on success, zero if the operator is
+   not recognized.  */
+
+extern int
+cplus_demangle_fill_operator (struct demangle_component *fill,
+                              const char *opname, int args);
+
+/* Fill in a DEMANGLE_COMPONENT_EXTENDED_OPERATOR, providing the
+   number of arguments and the name.  Returns non-zero on success,
+   zero for bad arguments.  */
+
+extern int
+cplus_demangle_fill_extended_operator (struct demangle_component *fill,
+                                       int numargs,
+                                       struct demangle_component *nm);
+
+/* Fill in a DEMANGLE_COMPONENT_CTOR.  Returns non-zero on success,
+   zero for bad arguments.  */
+
+extern int
+cplus_demangle_fill_ctor (struct demangle_component *fill,
+                          enum gnu_v3_ctor_kinds kind,
+                          struct demangle_component *name);
+
+/* Fill in a DEMANGLE_COMPONENT_DTOR.  Returns non-zero on success,
+   zero for bad arguments.  */
+
+extern int
+cplus_demangle_fill_dtor (struct demangle_component *fill,
+                          enum gnu_v3_dtor_kinds kind,
+                          struct demangle_component *name);
+
+/* This function translates a mangled name into a struct
+   demangle_component tree.  The first argument is the mangled name.
+   The second argument is DMGL_* options.  This returns a pointer to a
+   tree on success, or NULL on failure.  On success, the third
+   argument is set to a block of memory allocated by malloc.  This
+   block should be passed to free when the tree is no longer
+   needed.  */
+
+extern struct demangle_component *
+cplus_demangle_v3_components (const char *mangled, int options, void **mem);
+
+/* This function takes a struct demangle_component tree and returns
+   the corresponding demangled string.  The first argument is DMGL_*
+   options.  The second is the tree to demangle.  The third is a guess
+   at the length of the demangled string, used to initially allocate
+   the return buffer.  The fourth is a pointer to a size_t.  On
+   success, this function returns a buffer allocated by malloc(), and
+   sets the size_t pointed to by the fourth argument to the size of
+   the allocated buffer (not the length of the returned string).  On
+   failure, this function returns NULL, and sets the size_t pointed to
+   by the fourth argument to 0 for an invalid tree, or to 1 for a
+   memory allocation error.  */
+
+extern char *
+cplus_demangle_print (int options,
+                      const struct demangle_component *tree,
+                      int estimated_length,
+                      size_t *p_allocated_size);
+
+/* This function takes a struct demangle_component tree and passes back
+   a demangled string in one or more calls to a callback function.
+   The first argument is DMGL_* options.  The second is the tree to
+   demangle.  The third is a pointer to a callback function; on each call
+   this receives an element of the demangled string, its length, and an
+   opaque value.  The fourth is the opaque value passed to the callback.
+   The callback is called once or more to return the full demangled
+   string.  The demangled element string is always nul-terminated, though
+   its length is also provided for convenience.  In contrast to
+   cplus_demangle_print(), this function does not allocate heap memory
+   to grow output strings (except perhaps where alloca() is implemented
+   by malloc()), and so is normally safe for use where the heap has been
+   corrupted.  On success, this function returns 1; on failure, 0.  */
+
+extern int
+cplus_demangle_print_callback (int options,
+                               const struct demangle_component *tree,
+                               demangle_callbackref callback, void *opaque);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif	/* DEMANGLE_H */
diff --git a/binutils-2.25/include/dis-asm.h b/binutils-2.25/include/dis-asm.h
new file mode 100644
index 00000000..78e9fc01
--- /dev/null
+++ b/binutils-2.25/include/dis-asm.h
@@ -0,0 +1,382 @@
+/* Interface between the opcode library and its callers.
+
+   Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2009, 2010,
+   2011, 2012 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.
+
+   Written by Cygnus Support, 1993.
+
+   The opcode library (libopcodes.a) provides instruction decoders for
+   a large variety of instruction sets, callable with an identical
+   interface, for making instruction-processing programs more independent
+   of the instruction set being processed.  */
+
+#ifndef DIS_ASM_H
+#define DIS_ASM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdio.h>
+#include "bfd.h"
+
+  typedef int (*fprintf_ftype) (void *, const char*, ...) ATTRIBUTE_FPTR_PRINTF_2;
+
+enum dis_insn_type
+{
+  dis_noninsn,			/* Not a valid instruction.  */
+  dis_nonbranch,		/* Not a branch instruction.  */
+  dis_branch,			/* Unconditional branch.  */
+  dis_condbranch,		/* Conditional branch.  */
+  dis_jsr,			/* Jump to subroutine.  */
+  dis_condjsr,			/* Conditional jump to subroutine.  */
+  dis_dref,			/* Data reference instruction.  */
+  dis_dref2			/* Two data references in instruction.  */
+};
+
+/* This struct is passed into the instruction decoding routine,
+   and is passed back out into each callback.  The various fields are used
+   for conveying information from your main routine into your callbacks,
+   for passing information into the instruction decoders (such as the
+   addresses of the callback functions), or for passing information
+   back from the instruction decoders to their callers.
+
+   It must be initialized before it is first passed; this can be done
+   by hand, or using one of the initialization macros below.  */
+
+typedef struct disassemble_info
+{
+  fprintf_ftype fprintf_func;
+  void *stream;
+  void *application_data;
+
+  /* Target description.  We could replace this with a pointer to the bfd,
+     but that would require one.  There currently isn't any such requirement
+     so to avoid introducing one we record these explicitly.  */
+  /* The bfd_flavour.  This can be bfd_target_unknown_flavour.  */
+  enum bfd_flavour flavour;
+  /* The bfd_arch value.  */
+  enum bfd_architecture arch;
+  /* The bfd_mach value.  */
+  unsigned long mach;
+  /* Endianness (for bi-endian cpus).  Mono-endian cpus can ignore this.  */
+  enum bfd_endian endian;
+  /* Endianness of code, for mixed-endian situations such as ARM BE8.  */
+  enum bfd_endian endian_code;
+  /* An arch/mach-specific bitmask of selected instruction subsets, mainly
+     for processors with run-time-switchable instruction sets.  The default,
+     zero, means that there is no constraint.  CGEN-based opcodes ports
+     may use ISA_foo masks.  */
+  void *insn_sets;
+
+  /* Some targets need information about the current section to accurately
+     display insns.  If this is NULL, the target disassembler function
+     will have to make its best guess.  */
+  asection *section;
+
+  /* An array of pointers to symbols either at the location being disassembled
+     or at the start of the function being disassembled.  The array is sorted
+     so that the first symbol is intended to be the one used.  The others are
+     present for any misc. purposes.  This is not set reliably, but if it is
+     not NULL, it is correct.  */
+  asymbol **symbols;
+  /* Number of symbols in array.  */
+  int num_symbols;
+
+  /* Symbol table provided for targets that want to look at it.  This is
+     used on Arm to find mapping symbols and determine Arm/Thumb code.  */
+  asymbol **symtab;
+  int symtab_pos;
+  int symtab_size;
+
+  /* For use by the disassembler.
+     The top 16 bits are reserved for public use (and are documented here).
+     The bottom 16 bits are for the internal use of the disassembler.  */
+  unsigned long flags;
+  /* Set if the disassembler has determined that there are one or more
+     relocations associated with the instruction being disassembled.  */
+#define INSN_HAS_RELOC	 (1 << 31)
+  /* Set if the user has requested the disassembly of data as well as code.  */
+#define DISASSEMBLE_DATA (1 << 30)
+  /* Set if the user has specifically set the machine type encoded in the
+     mach field of this structure.  */
+#define USER_SPECIFIED_MACHINE_TYPE (1 << 29)
+
+  /* Use internally by the target specific disassembly code.  */
+  void *private_data;
+
+  /* Function used to get bytes to disassemble.  MEMADDR is the
+     address of the stuff to be disassembled, MYADDR is the address to
+     put the bytes in, and LENGTH is the number of bytes to read.
+     INFO is a pointer to this struct.
+     Returns an errno value or 0 for success.  */
+  int (*read_memory_func)
+    (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length,
+     struct disassemble_info *dinfo);
+
+  /* Function which should be called if we get an error that we can't
+     recover from.  STATUS is the errno value from read_memory_func and
+     MEMADDR is the address that we were trying to read.  INFO is a
+     pointer to this struct.  */
+  void (*memory_error_func)
+    (int status, bfd_vma memaddr, struct disassemble_info *dinfo);
+
+  /* Function called to print ADDR.  */
+  void (*print_address_func)
+    (bfd_vma addr, struct disassemble_info *dinfo);
+
+  /* Function called to determine if there is a symbol at the given ADDR.
+     If there is, the function returns 1, otherwise it returns 0.
+     This is used by ports which support an overlay manager where
+     the overlay number is held in the top part of an address.  In
+     some circumstances we want to include the overlay number in the
+     address, (normally because there is a symbol associated with
+     that address), but sometimes we want to mask out the overlay bits.  */
+  int (* symbol_at_address_func)
+    (bfd_vma addr, struct disassemble_info *dinfo);
+
+  /* Function called to check if a SYMBOL is can be displayed to the user.
+     This is used by some ports that want to hide special symbols when
+     displaying debugging outout.  */
+  bfd_boolean (* symbol_is_valid)
+    (asymbol *, struct disassemble_info *dinfo);
+
+  /* These are for buffer_read_memory.  */
+  bfd_byte *buffer;
+  bfd_vma buffer_vma;
+  unsigned int buffer_length;
+
+  /* This variable may be set by the instruction decoder.  It suggests
+      the number of bytes objdump should display on a single line.  If
+      the instruction decoder sets this, it should always set it to
+      the same value in order to get reasonable looking output.  */
+  int bytes_per_line;
+
+  /* The next two variables control the way objdump displays the raw data.  */
+  /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */
+  /* output will look like this:
+     00:   00000000 00000000
+     with the chunks displayed according to "display_endian". */
+  int bytes_per_chunk;
+  enum bfd_endian display_endian;
+
+  /* Number of octets per incremented target address
+     Normally one, but some DSPs have byte sizes of 16 or 32 bits.  */
+  unsigned int octets_per_byte;
+
+  /* The number of zeroes we want to see at the end of a section before we
+     start skipping them.  */
+  unsigned int skip_zeroes;
+
+  /* The number of zeroes to skip at the end of a section.  If the number
+     of zeroes at the end is between SKIP_ZEROES_AT_END and SKIP_ZEROES,
+     they will be disassembled.  If there are fewer than
+     SKIP_ZEROES_AT_END, they will be skipped.  This is a heuristic
+     attempt to avoid disassembling zeroes inserted by section
+     alignment.  */
+  unsigned int skip_zeroes_at_end;
+
+  /* Whether the disassembler always needs the relocations.  */
+  bfd_boolean disassembler_needs_relocs;
+
+  /* Results from instruction decoders.  Not all decoders yet support
+     this information.  This info is set each time an instruction is
+     decoded, and is only valid for the last such instruction.
+
+     To determine whether this decoder supports this information, set
+     insn_info_valid to 0, decode an instruction, then check it.  */
+
+  char insn_info_valid;		/* Branch info has been set. */
+  char branch_delay_insns;	/* How many sequential insn's will run before
+				   a branch takes effect.  (0 = normal) */
+  char data_size;		/* Size of data reference in insn, in bytes */
+  enum dis_insn_type insn_type;	/* Type of instruction */
+  bfd_vma target;		/* Target address of branch or dref, if known;
+				   zero if unknown.  */
+  bfd_vma target2;		/* Second target address for dref2 */
+
+  /* Command line options specific to the target disassembler.  */
+  char * disassembler_options;
+
+} disassemble_info;
+
+
+/* Standard disassemblers.  Disassemble one instruction at the given
+   target address.  Return number of octets processed.  */
+typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
+
+extern int print_insn_aarch64		(bfd_vma, disassemble_info *);
+extern int print_insn_alpha		(bfd_vma, disassemble_info *);
+extern int print_insn_avr		(bfd_vma, disassemble_info *);
+extern int print_insn_bfin		(bfd_vma, disassemble_info *);
+extern int print_insn_big_arm		(bfd_vma, disassemble_info *);
+extern int print_insn_big_mips		(bfd_vma, disassemble_info *);
+extern int print_insn_big_nios2		(bfd_vma, disassemble_info *);
+extern int print_insn_big_or32		(bfd_vma, disassemble_info *);
+extern int print_insn_big_powerpc	(bfd_vma, disassemble_info *);
+extern int print_insn_big_score         (bfd_vma, disassemble_info *);
+extern int print_insn_cr16              (bfd_vma, disassemble_info *);
+extern int print_insn_crx               (bfd_vma, disassemble_info *);
+extern int print_insn_d10v		(bfd_vma, disassemble_info *);
+extern int print_insn_d30v		(bfd_vma, disassemble_info *);
+extern int print_insn_dlx 		(bfd_vma, disassemble_info *);
+extern int print_insn_epiphany		(bfd_vma, disassemble_info *);
+extern int print_insn_fr30		(bfd_vma, disassemble_info *);
+extern int print_insn_frv		(bfd_vma, disassemble_info *);
+extern int print_insn_h8300		(bfd_vma, disassemble_info *);
+extern int print_insn_h8300h		(bfd_vma, disassemble_info *);
+extern int print_insn_h8300s		(bfd_vma, disassemble_info *);
+extern int print_insn_h8500		(bfd_vma, disassemble_info *);
+extern int print_insn_hppa		(bfd_vma, disassemble_info *);
+extern int print_insn_i370		(bfd_vma, disassemble_info *);
+extern int print_insn_i386		(bfd_vma, disassemble_info *);
+extern int print_insn_i386_att		(bfd_vma, disassemble_info *);
+extern int print_insn_i386_intel	(bfd_vma, disassemble_info *);
+extern int print_insn_i860		(bfd_vma, disassemble_info *);
+extern int print_insn_i960		(bfd_vma, disassemble_info *);
+extern int print_insn_ia64		(bfd_vma, disassemble_info *);
+extern int print_insn_ip2k		(bfd_vma, disassemble_info *);
+extern int print_insn_iq2000		(bfd_vma, disassemble_info *);
+extern int print_insn_little_arm	(bfd_vma, disassemble_info *);
+extern int print_insn_little_mips	(bfd_vma, disassemble_info *);
+extern int print_insn_little_nios2	(bfd_vma, disassemble_info *);
+extern int print_insn_little_or32	(bfd_vma, disassemble_info *);
+extern int print_insn_little_powerpc	(bfd_vma, disassemble_info *);
+extern int print_insn_little_score      (bfd_vma, disassemble_info *); 
+extern int print_insn_lm32		(bfd_vma, disassemble_info *);
+extern int print_insn_m32c	        (bfd_vma, disassemble_info *);
+extern int print_insn_m32r		(bfd_vma, disassemble_info *);
+extern int print_insn_m68hc11		(bfd_vma, disassemble_info *);
+extern int print_insn_m68hc12		(bfd_vma, disassemble_info *);
+extern int print_insn_m9s12x		(bfd_vma, disassemble_info *);
+extern int print_insn_m9s12xg		(bfd_vma, disassemble_info *);
+extern int print_insn_m68k		(bfd_vma, disassemble_info *);
+extern int print_insn_m88k		(bfd_vma, disassemble_info *);
+extern int print_insn_mcore		(bfd_vma, disassemble_info *);
+extern int print_insn_mep		(bfd_vma, disassemble_info *);
+extern int print_insn_metag		(bfd_vma, disassemble_info *);
+extern int print_insn_microblaze	(bfd_vma, disassemble_info *);
+extern int print_insn_mmix		(bfd_vma, disassemble_info *);
+extern int print_insn_mn10200		(bfd_vma, disassemble_info *);
+extern int print_insn_mn10300		(bfd_vma, disassemble_info *);
+extern int print_insn_moxie		(bfd_vma, disassemble_info *);
+extern int print_insn_msp430		(bfd_vma, disassemble_info *);
+extern int print_insn_mt                (bfd_vma, disassemble_info *);
+extern int print_insn_ns32k		(bfd_vma, disassemble_info *);
+extern int print_insn_openrisc		(bfd_vma, disassemble_info *);
+extern int print_insn_pdp11		(bfd_vma, disassemble_info *);
+extern int print_insn_pj		(bfd_vma, disassemble_info *);
+extern int print_insn_rs6000		(bfd_vma, disassemble_info *);
+extern int print_insn_s390		(bfd_vma, disassemble_info *);
+extern int print_insn_sh		(bfd_vma, disassemble_info *);
+extern int print_insn_sh64		(bfd_vma, disassemble_info *);
+extern int print_insn_sh64x_media	(bfd_vma, disassemble_info *);
+extern int print_insn_sparc		(bfd_vma, disassemble_info *);
+extern int print_insn_spu		(bfd_vma, disassemble_info *);
+extern int print_insn_tic30		(bfd_vma, disassemble_info *);
+extern int print_insn_tic4x		(bfd_vma, disassemble_info *);
+extern int print_insn_tic54x		(bfd_vma, disassemble_info *);
+extern int print_insn_tic6x		(bfd_vma, disassemble_info *);
+extern int print_insn_tic80		(bfd_vma, disassemble_info *);
+extern int print_insn_tilegx		(bfd_vma, disassemble_info *);
+extern int print_insn_tilepro		(bfd_vma, disassemble_info *);
+extern int print_insn_v850		(bfd_vma, disassemble_info *);
+extern int print_insn_vax		(bfd_vma, disassemble_info *);
+extern int print_insn_w65		(bfd_vma, disassemble_info *);
+extern int print_insn_xc16x		(bfd_vma, disassemble_info *);
+extern int print_insn_xgate             (bfd_vma, disassemble_info *);
+extern int print_insn_xstormy16		(bfd_vma, disassemble_info *);
+extern int print_insn_xtensa		(bfd_vma, disassemble_info *);
+extern int print_insn_z80		(bfd_vma, disassemble_info *);
+extern int print_insn_z8001		(bfd_vma, disassemble_info *);
+extern int print_insn_z8002		(bfd_vma, disassemble_info *);
+extern int print_insn_rx		(bfd_vma, disassemble_info *);
+extern int print_insn_rl78		(bfd_vma, disassemble_info *);
+
+extern disassembler_ftype arc_get_disassembler (void *);
+extern disassembler_ftype cris_get_disassembler (bfd *);
+
+extern void print_aarch64_disassembler_options (FILE *);
+extern void print_i386_disassembler_options (FILE *);
+extern void print_mips_disassembler_options (FILE *);
+extern void print_ppc_disassembler_options (FILE *);
+extern void print_arm_disassembler_options (FILE *);
+extern void parse_arm_disassembler_option (char *);
+extern void print_s390_disassembler_options (FILE *);
+extern int  get_arm_regname_num_options (void);
+extern int  set_arm_regname_option (int);
+extern int  get_arm_regnames (int, const char **, const char **, const char *const **);
+extern bfd_boolean aarch64_symbol_is_valid (asymbol *, struct disassemble_info *);
+extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *);
+extern void disassemble_init_powerpc (struct disassemble_info *);
+
+/* Fetch the disassembler for a given BFD, if that support is available.  */
+extern disassembler_ftype disassembler (bfd *);
+
+/* Amend the disassemble_info structure as necessary for the target architecture.
+   Should only be called after initialising the info->arch field.  */
+extern void disassemble_init_for_target (struct disassemble_info * dinfo);
+
+/* Document any target specific options available from the disassembler.  */
+extern void disassembler_usage (FILE *);
+
+
+/* This block of definitions is for particular callers who read instructions
+   into a buffer before calling the instruction decoder.  */
+
+/* Here is a function which callers may wish to use for read_memory_func.
+   It gets bytes from a buffer.  */
+extern int buffer_read_memory
+  (bfd_vma, bfd_byte *, unsigned int, struct disassemble_info *);
+
+/* This function goes with buffer_read_memory.
+   It prints a message using info->fprintf_func and info->stream.  */
+extern void perror_memory (int, bfd_vma, struct disassemble_info *);
+
+
+/* Just print the address in hex.  This is included for completeness even
+   though both GDB and objdump provide their own (to print symbolic
+   addresses).  */
+extern void generic_print_address
+  (bfd_vma, struct disassemble_info *);
+
+/* Always true.  */
+extern int generic_symbol_at_address
+  (bfd_vma, struct disassemble_info *);
+
+/* Also always true.  */
+extern bfd_boolean generic_symbol_is_valid
+  (asymbol *, struct disassemble_info *);
+
+/* Method to initialize a disassemble_info struct.  This should be
+   called by all applications creating such a struct.  */
+extern void init_disassemble_info (struct disassemble_info *dinfo, void *stream,
+				   fprintf_ftype fprintf_func);
+
+/* For compatibility with existing code.  */
+#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
+  init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC))
+#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
+  init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC))
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ! defined (DIS_ASM_H) */
diff --git a/binutils-2.25/include/dwarf2.def b/binutils-2.25/include/dwarf2.def
new file mode 100644
index 00000000..71a37b30
--- /dev/null
+++ b/binutils-2.25/include/dwarf2.def
@@ -0,0 +1,688 @@
+/* -*- c -*-
+   Declarations and definitions of codes relating to the DWARF2 and
+   DWARF3 symbolic debugging information formats.
+   Copyright (C) 1992, 1993, 1995, 1996, 1997, 1999, 2000, 2001, 2002,
+   2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
+   Free Software Foundation, Inc.
+
+   Written by Gary Funck (gary@intrepid.com) The Ada Joint Program
+   Office (AJPO), Florida State University and Silicon Graphics Inc.
+   provided support for this effort -- June 21, 1995.
+
+   Derived from the DWARF 1 implementation written by Ron Guilmette
+   (rfg@netcom.com), November 1990.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3, or (at your option) any later
+   version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+/* This file is derived from the DWARF specification (a public document)
+   Revision 2.0.0 (July 27, 1993) developed by the UNIX International
+   Programming Languages Special Interest Group (UI/PLSIG) and distributed
+   by UNIX International.  Copies of this specification are available from
+   UNIX International, 20 Waterview Boulevard, Parsippany, NJ, 07054.
+
+   This file also now contains definitions from the DWARF 3 specification
+   published Dec 20, 2005, available from: http://dwarf.freestandards.org.
+
+   This file also now contains definitions from the DWARF 4
+   specification, available from: http://dwarfstd.org/ */
+
+/* This file declares various DWARF-related constants using a set of
+   macros which can be redefined by the including file.
+   
+   The macros are in sections.  Each section corresponds to a single
+   set of DWARF constants and has a corresponding key.  The key is
+   used in all the macro names.
+   
+   The sections are TAG (for DW_TAG_ constants), FORM (DW_FORM_), AT
+   (DW_AT_), OP (DW_OP_), ATE (DW_ATE_), and CFA (DW_CFA_).
+   
+   Using TAG as an example, the following macros may be used for each
+   key:
+   
+   DW_FIRST_TAG(name, value) - Introduce the first DW_TAG constant.
+   
+   DW_TAG(name, value) - Define a subsequent constant.
+   
+   DW_TAG_DUP(name, value) - Define a subsequent constant whose value
+   is a duplicate of some other constant.  Not all keys use the _DUP
+   macro form.  If more than one name shares a value, then the base
+   (DW_TAG) form will be the preferred name and DW_TAG_DUP will hold
+   any alternate names.
+   
+   DW_END_TAG - Invoked at the end of the DW_TAG constants.  */
+
+DW_FIRST_TAG (DW_TAG_padding, 0x00)
+DW_TAG (DW_TAG_array_type, 0x01)
+DW_TAG (DW_TAG_class_type, 0x02)
+DW_TAG (DW_TAG_entry_point, 0x03)
+DW_TAG (DW_TAG_enumeration_type, 0x04)
+DW_TAG (DW_TAG_formal_parameter, 0x05)
+DW_TAG (DW_TAG_imported_declaration, 0x08)
+DW_TAG (DW_TAG_label, 0x0a)
+DW_TAG (DW_TAG_lexical_block, 0x0b)
+DW_TAG (DW_TAG_member, 0x0d)
+DW_TAG (DW_TAG_pointer_type, 0x0f)
+DW_TAG (DW_TAG_reference_type, 0x10)
+DW_TAG (DW_TAG_compile_unit, 0x11)
+DW_TAG (DW_TAG_string_type, 0x12)
+DW_TAG (DW_TAG_structure_type, 0x13)
+DW_TAG (DW_TAG_subroutine_type, 0x15)
+DW_TAG (DW_TAG_typedef, 0x16)
+DW_TAG (DW_TAG_union_type, 0x17)
+DW_TAG (DW_TAG_unspecified_parameters, 0x18)
+DW_TAG (DW_TAG_variant, 0x19)
+DW_TAG (DW_TAG_common_block, 0x1a)
+DW_TAG (DW_TAG_common_inclusion, 0x1b)
+DW_TAG (DW_TAG_inheritance, 0x1c)
+DW_TAG (DW_TAG_inlined_subroutine, 0x1d)
+DW_TAG (DW_TAG_module, 0x1e)
+DW_TAG (DW_TAG_ptr_to_member_type, 0x1f)
+DW_TAG (DW_TAG_set_type, 0x20)
+DW_TAG (DW_TAG_subrange_type, 0x21)
+DW_TAG (DW_TAG_with_stmt, 0x22)
+DW_TAG (DW_TAG_access_declaration, 0x23)
+DW_TAG (DW_TAG_base_type, 0x24)
+DW_TAG (DW_TAG_catch_block, 0x25)
+DW_TAG (DW_TAG_const_type, 0x26)
+DW_TAG (DW_TAG_constant, 0x27)
+DW_TAG (DW_TAG_enumerator, 0x28)
+DW_TAG (DW_TAG_file_type, 0x29)
+DW_TAG (DW_TAG_friend, 0x2a)
+DW_TAG (DW_TAG_namelist, 0x2b)
+DW_TAG (DW_TAG_namelist_item, 0x2c)
+DW_TAG (DW_TAG_packed_type, 0x2d)
+DW_TAG (DW_TAG_subprogram, 0x2e)
+DW_TAG (DW_TAG_template_type_param, 0x2f)
+DW_TAG (DW_TAG_template_value_param, 0x30)
+DW_TAG (DW_TAG_thrown_type, 0x31)
+DW_TAG (DW_TAG_try_block, 0x32)
+DW_TAG (DW_TAG_variant_part, 0x33)
+DW_TAG (DW_TAG_variable, 0x34)
+DW_TAG (DW_TAG_volatile_type, 0x35)
+/* DWARF 3.  */
+DW_TAG (DW_TAG_dwarf_procedure, 0x36)
+DW_TAG (DW_TAG_restrict_type, 0x37)
+DW_TAG (DW_TAG_interface_type, 0x38)
+DW_TAG (DW_TAG_namespace, 0x39)
+DW_TAG (DW_TAG_imported_module, 0x3a)
+DW_TAG (DW_TAG_unspecified_type, 0x3b)
+DW_TAG (DW_TAG_partial_unit, 0x3c)
+DW_TAG (DW_TAG_imported_unit, 0x3d)
+DW_TAG (DW_TAG_condition, 0x3f)
+DW_TAG (DW_TAG_shared_type, 0x40)
+/* DWARF 4.  */
+DW_TAG (DW_TAG_type_unit, 0x41)
+DW_TAG (DW_TAG_rvalue_reference_type, 0x42)
+DW_TAG (DW_TAG_template_alias, 0x43)
+
+DW_TAG_DUP (DW_TAG_lo_user, 0x4080)
+DW_TAG_DUP (DW_TAG_hi_user, 0xffff)
+
+/* SGI/MIPS Extensions.  */
+DW_TAG (DW_TAG_MIPS_loop, 0x4081)
+
+/* HP extensions.  See: ftp://ftp.hp.com/pub/lang/tools/WDB/wdb-4.0.tar.gz .  */
+DW_TAG (DW_TAG_HP_array_descriptor, 0x4090)
+DW_TAG (DW_TAG_HP_Bliss_field, 0x4091)
+DW_TAG (DW_TAG_HP_Bliss_field_set, 0x4092)
+
+/* GNU extensions.  */
+DW_TAG (DW_TAG_format_label, 0x4101)	/* For FORTRAN 77 and Fortran 90.  */
+DW_TAG (DW_TAG_function_template, 0x4102)	/* For C++.  */
+DW_TAG (DW_TAG_class_template, 0x4103)	/* For C++.  */
+DW_TAG (DW_TAG_GNU_BINCL, 0x4104)
+DW_TAG (DW_TAG_GNU_EINCL, 0x4105)
+/* Template template parameter.
+   See http://gcc.gnu.org/wiki/TemplateParmsDwarf .  */
+DW_TAG (DW_TAG_GNU_template_template_param, 0x4106)
+
+/* Template parameter pack extension, specified at
+   http://wiki.dwarfstd.org/index.php?title=C%2B%2B0x:_Variadic_templates
+   The values of these two TAGS are in the DW_TAG_GNU_* space until the tags
+   are properly part of DWARF 5.  */
+DW_TAG (DW_TAG_GNU_template_parameter_pack, 0x4107)
+DW_TAG (DW_TAG_GNU_formal_parameter_pack, 0x4108)
+/* The GNU call site extension, specified at
+   http://www.dwarfstd.org/ShowIssue.php?issue=100909.2&type=open .
+   The values of these two TAGS are in the DW_TAG_GNU_* space until the tags
+   are properly part of DWARF 5.  */
+DW_TAG (DW_TAG_GNU_call_site, 0x4109)
+DW_TAG (DW_TAG_GNU_call_site_parameter, 0x410a)
+/* Extensions for UPC.  See: http://dwarfstd.org/doc/DWARF4.pdf.  */
+DW_TAG (DW_TAG_upc_shared_type, 0x8765)
+DW_TAG (DW_TAG_upc_strict_type, 0x8766)
+DW_TAG (DW_TAG_upc_relaxed_type, 0x8767)
+/* PGI (STMicroelectronics) extensions.  No documentation available.  */
+DW_TAG (DW_TAG_PGI_kanji_type, 0xA000)
+DW_TAG (DW_TAG_PGI_interface_block, 0xA020)
+DW_END_TAG
+
+DW_FIRST_FORM (DW_FORM_addr, 0x01)
+DW_FORM (DW_FORM_block2, 0x03)
+DW_FORM (DW_FORM_block4, 0x04)
+DW_FORM (DW_FORM_data2, 0x05)
+DW_FORM (DW_FORM_data4, 0x06)
+DW_FORM (DW_FORM_data8, 0x07)
+DW_FORM (DW_FORM_string, 0x08)
+DW_FORM (DW_FORM_block, 0x09)
+DW_FORM (DW_FORM_block1, 0x0a)
+DW_FORM (DW_FORM_data1, 0x0b)
+DW_FORM (DW_FORM_flag, 0x0c)
+DW_FORM (DW_FORM_sdata, 0x0d)
+DW_FORM (DW_FORM_strp, 0x0e)
+DW_FORM (DW_FORM_udata, 0x0f)
+DW_FORM (DW_FORM_ref_addr, 0x10)
+DW_FORM (DW_FORM_ref1, 0x11)
+DW_FORM (DW_FORM_ref2, 0x12)
+DW_FORM (DW_FORM_ref4, 0x13)
+DW_FORM (DW_FORM_ref8, 0x14)
+DW_FORM (DW_FORM_ref_udata, 0x15)
+DW_FORM (DW_FORM_indirect, 0x16)
+/* DWARF 4.  */
+DW_FORM (DW_FORM_sec_offset, 0x17)
+DW_FORM (DW_FORM_exprloc, 0x18)
+DW_FORM (DW_FORM_flag_present, 0x19)
+DW_FORM (DW_FORM_ref_sig8, 0x20)
+/* Extensions for Fission.  See http://gcc.gnu.org/wiki/DebugFission.  */
+DW_FORM (DW_FORM_GNU_addr_index, 0x1f01)
+DW_FORM (DW_FORM_GNU_str_index, 0x1f02)
+/* Extensions for DWZ multifile.
+   See http://www.dwarfstd.org/ShowIssue.php?issue=120604.1&type=open .  */
+DW_FORM (DW_FORM_GNU_ref_alt, 0x1f20)
+DW_FORM (DW_FORM_GNU_strp_alt, 0x1f21)
+DW_END_FORM
+
+DW_FIRST_AT (DW_AT_sibling, 0x01)
+DW_AT (DW_AT_location, 0x02)
+DW_AT (DW_AT_name, 0x03)
+DW_AT (DW_AT_ordering, 0x09)
+DW_AT (DW_AT_subscr_data, 0x0a)
+DW_AT (DW_AT_byte_size, 0x0b)
+DW_AT (DW_AT_bit_offset, 0x0c)
+DW_AT (DW_AT_bit_size, 0x0d)
+DW_AT (DW_AT_element_list, 0x0f)
+DW_AT (DW_AT_stmt_list, 0x10)
+DW_AT (DW_AT_low_pc, 0x11)
+DW_AT (DW_AT_high_pc, 0x12)
+DW_AT (DW_AT_language, 0x13)
+DW_AT (DW_AT_member, 0x14)
+DW_AT (DW_AT_discr, 0x15)
+DW_AT (DW_AT_discr_value, 0x16)
+DW_AT (DW_AT_visibility, 0x17)
+DW_AT (DW_AT_import, 0x18)
+DW_AT (DW_AT_string_length, 0x19)
+DW_AT (DW_AT_common_reference, 0x1a)
+DW_AT (DW_AT_comp_dir, 0x1b)
+DW_AT (DW_AT_const_value, 0x1c)
+DW_AT (DW_AT_containing_type, 0x1d)
+DW_AT (DW_AT_default_value, 0x1e)
+DW_AT (DW_AT_inline, 0x20)
+DW_AT (DW_AT_is_optional, 0x21)
+DW_AT (DW_AT_lower_bound, 0x22)
+DW_AT (DW_AT_producer, 0x25)
+DW_AT (DW_AT_prototyped, 0x27)
+DW_AT (DW_AT_return_addr, 0x2a)
+DW_AT (DW_AT_start_scope, 0x2c)
+DW_AT (DW_AT_bit_stride, 0x2e)
+DW_AT (DW_AT_upper_bound, 0x2f)
+DW_AT (DW_AT_abstract_origin, 0x31)
+DW_AT (DW_AT_accessibility, 0x32)
+DW_AT (DW_AT_address_class, 0x33)
+DW_AT (DW_AT_artificial, 0x34)
+DW_AT (DW_AT_base_types, 0x35)
+DW_AT (DW_AT_calling_convention, 0x36)
+DW_AT (DW_AT_count, 0x37)
+DW_AT (DW_AT_data_member_location, 0x38)
+DW_AT (DW_AT_decl_column, 0x39)
+DW_AT (DW_AT_decl_file, 0x3a)
+DW_AT (DW_AT_decl_line, 0x3b)
+DW_AT (DW_AT_declaration, 0x3c)
+DW_AT (DW_AT_discr_list, 0x3d)
+DW_AT (DW_AT_encoding, 0x3e)
+DW_AT (DW_AT_external, 0x3f)
+DW_AT (DW_AT_frame_base, 0x40)
+DW_AT (DW_AT_friend, 0x41)
+DW_AT (DW_AT_identifier_case, 0x42)
+DW_AT (DW_AT_macro_info, 0x43)
+DW_AT (DW_AT_namelist_items, 0x44)
+DW_AT (DW_AT_priority, 0x45)
+DW_AT (DW_AT_segment, 0x46)
+DW_AT (DW_AT_specification, 0x47)
+DW_AT (DW_AT_static_link, 0x48)
+DW_AT (DW_AT_type, 0x49)
+DW_AT (DW_AT_use_location, 0x4a)
+DW_AT (DW_AT_variable_parameter, 0x4b)
+DW_AT (DW_AT_virtuality, 0x4c)
+DW_AT (DW_AT_vtable_elem_location, 0x4d)
+/* DWARF 3 values.  */
+DW_AT (DW_AT_allocated, 0x4e)
+DW_AT (DW_AT_associated, 0x4f)
+DW_AT (DW_AT_data_location, 0x50)
+DW_AT (DW_AT_byte_stride, 0x51)
+DW_AT (DW_AT_entry_pc, 0x52)
+DW_AT (DW_AT_use_UTF8, 0x53)
+DW_AT (DW_AT_extension, 0x54)
+DW_AT (DW_AT_ranges, 0x55)
+DW_AT (DW_AT_trampoline, 0x56)
+DW_AT (DW_AT_call_column, 0x57)
+DW_AT (DW_AT_call_file, 0x58)
+DW_AT (DW_AT_call_line, 0x59)
+DW_AT (DW_AT_description, 0x5a)
+DW_AT (DW_AT_binary_scale, 0x5b)
+DW_AT (DW_AT_decimal_scale, 0x5c)
+DW_AT (DW_AT_small, 0x5d)
+DW_AT (DW_AT_decimal_sign, 0x5e)
+DW_AT (DW_AT_digit_count, 0x5f)
+DW_AT (DW_AT_picture_string, 0x60)
+DW_AT (DW_AT_mutable, 0x61)
+DW_AT (DW_AT_threads_scaled, 0x62)
+DW_AT (DW_AT_explicit, 0x63)
+DW_AT (DW_AT_object_pointer, 0x64)
+DW_AT (DW_AT_endianity, 0x65)
+DW_AT (DW_AT_elemental, 0x66)
+DW_AT (DW_AT_pure, 0x67)
+DW_AT (DW_AT_recursive, 0x68)
+/* DWARF 4.  */
+DW_AT (DW_AT_signature, 0x69)
+DW_AT (DW_AT_main_subprogram, 0x6a)
+DW_AT (DW_AT_data_bit_offset, 0x6b)
+DW_AT (DW_AT_const_expr, 0x6c)
+DW_AT (DW_AT_enum_class, 0x6d)
+DW_AT (DW_AT_linkage_name, 0x6e)
+
+DW_AT_DUP (DW_AT_lo_user, 0x2000) /* Implementation-defined range start.  */
+DW_AT_DUP (DW_AT_hi_user, 0x3fff) /* Implementation-defined range end.  */
+
+/* SGI/MIPS extensions.  */
+DW_AT (DW_AT_MIPS_fde, 0x2001)
+DW_AT (DW_AT_MIPS_loop_begin, 0x2002)
+DW_AT (DW_AT_MIPS_tail_loop_begin, 0x2003)
+DW_AT (DW_AT_MIPS_epilog_begin, 0x2004)
+DW_AT (DW_AT_MIPS_loop_unroll_factor, 0x2005)
+DW_AT (DW_AT_MIPS_software_pipeline_depth, 0x2006)
+DW_AT (DW_AT_MIPS_linkage_name, 0x2007)
+DW_AT (DW_AT_MIPS_stride, 0x2008)
+DW_AT (DW_AT_MIPS_abstract_name, 0x2009)
+DW_AT (DW_AT_MIPS_clone_origin, 0x200a)
+DW_AT (DW_AT_MIPS_has_inlines, 0x200b)
+/* HP extensions.  */
+DW_AT (DW_AT_HP_block_index, 0x2000)
+DW_AT_DUP (DW_AT_HP_unmodifiable, 0x2001) /* Same as DW_AT_MIPS_fde.  */
+DW_AT_DUP (DW_AT_HP_prologue, 0x2005) /* Same as DW_AT_MIPS_loop_unroll.  */
+DW_AT_DUP (DW_AT_HP_epilogue, 0x2008) /* Same as DW_AT_MIPS_stride.  */
+DW_AT (DW_AT_HP_actuals_stmt_list, 0x2010)
+DW_AT (DW_AT_HP_proc_per_section, 0x2011)
+DW_AT (DW_AT_HP_raw_data_ptr, 0x2012)
+DW_AT (DW_AT_HP_pass_by_reference, 0x2013)
+DW_AT (DW_AT_HP_opt_level, 0x2014)
+DW_AT (DW_AT_HP_prof_version_id, 0x2015)
+DW_AT (DW_AT_HP_opt_flags, 0x2016)
+DW_AT (DW_AT_HP_cold_region_low_pc, 0x2017)
+DW_AT (DW_AT_HP_cold_region_high_pc, 0x2018)
+DW_AT (DW_AT_HP_all_variables_modifiable, 0x2019)
+DW_AT (DW_AT_HP_linkage_name, 0x201a)
+DW_AT (DW_AT_HP_prof_flags, 0x201b)  /* In comp unit of procs_info for -g.  */
+DW_AT (DW_AT_HP_unit_name, 0x201f)
+DW_AT (DW_AT_HP_unit_size, 0x2020)
+DW_AT (DW_AT_HP_widened_byte_size, 0x2021)
+DW_AT (DW_AT_HP_definition_points, 0x2022)
+DW_AT (DW_AT_HP_default_location, 0x2023)
+DW_AT (DW_AT_HP_is_result_param, 0x2029)
+
+/* GNU extensions.  */
+DW_AT (DW_AT_sf_names, 0x2101)
+DW_AT (DW_AT_src_info, 0x2102)
+DW_AT (DW_AT_mac_info, 0x2103)
+DW_AT (DW_AT_src_coords, 0x2104)
+DW_AT (DW_AT_body_begin, 0x2105)
+DW_AT (DW_AT_body_end, 0x2106)
+DW_AT (DW_AT_GNU_vector, 0x2107)
+/* Thread-safety annotations.
+   See http://gcc.gnu.org/wiki/ThreadSafetyAnnotation .  */
+DW_AT (DW_AT_GNU_guarded_by, 0x2108)
+DW_AT (DW_AT_GNU_pt_guarded_by, 0x2109)
+DW_AT (DW_AT_GNU_guarded, 0x210a)
+DW_AT (DW_AT_GNU_pt_guarded, 0x210b)
+DW_AT (DW_AT_GNU_locks_excluded, 0x210c)
+DW_AT (DW_AT_GNU_exclusive_locks_required, 0x210d)
+DW_AT (DW_AT_GNU_shared_locks_required, 0x210e)
+/* One-definition rule violation detection.
+   See http://gcc.gnu.org/wiki/DwarfSeparateTypeInfo .  */
+DW_AT (DW_AT_GNU_odr_signature, 0x210f)
+/* Template template argument name.
+   See http://gcc.gnu.org/wiki/TemplateParmsDwarf .  */
+DW_AT (DW_AT_GNU_template_name, 0x2110)
+/* The GNU call site extension.
+   See http://www.dwarfstd.org/ShowIssue.php?issue=100909.2&type=open .  */
+DW_AT (DW_AT_GNU_call_site_value, 0x2111)
+DW_AT (DW_AT_GNU_call_site_data_value, 0x2112)
+DW_AT (DW_AT_GNU_call_site_target, 0x2113)
+DW_AT (DW_AT_GNU_call_site_target_clobbered, 0x2114)
+DW_AT (DW_AT_GNU_tail_call, 0x2115)
+DW_AT (DW_AT_GNU_all_tail_call_sites, 0x2116)
+DW_AT (DW_AT_GNU_all_call_sites, 0x2117)
+DW_AT (DW_AT_GNU_all_source_call_sites, 0x2118)
+/* Section offset into .debug_macro section.  */
+DW_AT (DW_AT_GNU_macros, 0x2119)
+/* Extensions for Fission.  See http://gcc.gnu.org/wiki/DebugFission.  */
+DW_AT (DW_AT_GNU_dwo_name, 0x2130)
+DW_AT (DW_AT_GNU_dwo_id, 0x2131)
+DW_AT (DW_AT_GNU_ranges_base, 0x2132)
+DW_AT (DW_AT_GNU_addr_base, 0x2133)
+DW_AT (DW_AT_GNU_pubnames, 0x2134)
+DW_AT (DW_AT_GNU_pubtypes, 0x2135)
+/* Attribute for discriminator.
+   See http://gcc.gnu.org/wiki/Discriminator  */
+DW_AT (DW_AT_GNU_discriminator, 0x2136)
+/* VMS extensions.  */
+DW_AT (DW_AT_VMS_rtnbeg_pd_address, 0x2201)
+/* GNAT extensions.  */
+/* GNAT descriptive type.
+   See http://gcc.gnu.org/wiki/DW_AT_GNAT_descriptive_type .  */
+DW_AT (DW_AT_use_GNAT_descriptive_type, 0x2301)
+DW_AT (DW_AT_GNAT_descriptive_type, 0x2302)
+/* UPC extension.  */
+DW_AT (DW_AT_upc_threads_scaled, 0x3210)
+/* PGI (STMicroelectronics) extensions.  */
+DW_AT (DW_AT_PGI_lbase, 0x3a00)
+DW_AT (DW_AT_PGI_soffset, 0x3a01)
+DW_AT (DW_AT_PGI_lstride, 0x3a02)
+DW_END_AT
+
+DW_FIRST_OP (DW_OP_addr, 0x03)
+DW_OP (DW_OP_deref, 0x06)
+DW_OP (DW_OP_const1u, 0x08)
+DW_OP (DW_OP_const1s, 0x09)
+DW_OP (DW_OP_const2u, 0x0a)
+DW_OP (DW_OP_const2s, 0x0b)
+DW_OP (DW_OP_const4u, 0x0c)
+DW_OP (DW_OP_const4s, 0x0d)
+DW_OP (DW_OP_const8u, 0x0e)
+DW_OP (DW_OP_const8s, 0x0f)
+DW_OP (DW_OP_constu, 0x10)
+DW_OP (DW_OP_consts, 0x11)
+DW_OP (DW_OP_dup, 0x12)
+DW_OP (DW_OP_drop, 0x13)
+DW_OP (DW_OP_over, 0x14)
+DW_OP (DW_OP_pick, 0x15)
+DW_OP (DW_OP_swap, 0x16)
+DW_OP (DW_OP_rot, 0x17)
+DW_OP (DW_OP_xderef, 0x18)
+DW_OP (DW_OP_abs, 0x19)
+DW_OP (DW_OP_and, 0x1a)
+DW_OP (DW_OP_div, 0x1b)
+DW_OP (DW_OP_minus, 0x1c)
+DW_OP (DW_OP_mod, 0x1d)
+DW_OP (DW_OP_mul, 0x1e)
+DW_OP (DW_OP_neg, 0x1f)
+DW_OP (DW_OP_not, 0x20)
+DW_OP (DW_OP_or, 0x21)
+DW_OP (DW_OP_plus, 0x22)
+DW_OP (DW_OP_plus_uconst, 0x23)
+DW_OP (DW_OP_shl, 0x24)
+DW_OP (DW_OP_shr, 0x25)
+DW_OP (DW_OP_shra, 0x26)
+DW_OP (DW_OP_xor, 0x27)
+DW_OP (DW_OP_bra, 0x28)
+DW_OP (DW_OP_eq, 0x29)
+DW_OP (DW_OP_ge, 0x2a)
+DW_OP (DW_OP_gt, 0x2b)
+DW_OP (DW_OP_le, 0x2c)
+DW_OP (DW_OP_lt, 0x2d)
+DW_OP (DW_OP_ne, 0x2e)
+DW_OP (DW_OP_skip, 0x2f)
+DW_OP (DW_OP_lit0, 0x30)
+DW_OP (DW_OP_lit1, 0x31)
+DW_OP (DW_OP_lit2, 0x32)
+DW_OP (DW_OP_lit3, 0x33)
+DW_OP (DW_OP_lit4, 0x34)
+DW_OP (DW_OP_lit5, 0x35)
+DW_OP (DW_OP_lit6, 0x36)
+DW_OP (DW_OP_lit7, 0x37)
+DW_OP (DW_OP_lit8, 0x38)
+DW_OP (DW_OP_lit9, 0x39)
+DW_OP (DW_OP_lit10, 0x3a)
+DW_OP (DW_OP_lit11, 0x3b)
+DW_OP (DW_OP_lit12, 0x3c)
+DW_OP (DW_OP_lit13, 0x3d)
+DW_OP (DW_OP_lit14, 0x3e)
+DW_OP (DW_OP_lit15, 0x3f)
+DW_OP (DW_OP_lit16, 0x40)
+DW_OP (DW_OP_lit17, 0x41)
+DW_OP (DW_OP_lit18, 0x42)
+DW_OP (DW_OP_lit19, 0x43)
+DW_OP (DW_OP_lit20, 0x44)
+DW_OP (DW_OP_lit21, 0x45)
+DW_OP (DW_OP_lit22, 0x46)
+DW_OP (DW_OP_lit23, 0x47)
+DW_OP (DW_OP_lit24, 0x48)
+DW_OP (DW_OP_lit25, 0x49)
+DW_OP (DW_OP_lit26, 0x4a)
+DW_OP (DW_OP_lit27, 0x4b)
+DW_OP (DW_OP_lit28, 0x4c)
+DW_OP (DW_OP_lit29, 0x4d)
+DW_OP (DW_OP_lit30, 0x4e)
+DW_OP (DW_OP_lit31, 0x4f)
+DW_OP (DW_OP_reg0, 0x50)
+DW_OP (DW_OP_reg1, 0x51)
+DW_OP (DW_OP_reg2, 0x52)
+DW_OP (DW_OP_reg3, 0x53)
+DW_OP (DW_OP_reg4, 0x54)
+DW_OP (DW_OP_reg5, 0x55)
+DW_OP (DW_OP_reg6, 0x56)
+DW_OP (DW_OP_reg7, 0x57)
+DW_OP (DW_OP_reg8, 0x58)
+DW_OP (DW_OP_reg9, 0x59)
+DW_OP (DW_OP_reg10, 0x5a)
+DW_OP (DW_OP_reg11, 0x5b)
+DW_OP (DW_OP_reg12, 0x5c)
+DW_OP (DW_OP_reg13, 0x5d)
+DW_OP (DW_OP_reg14, 0x5e)
+DW_OP (DW_OP_reg15, 0x5f)
+DW_OP (DW_OP_reg16, 0x60)
+DW_OP (DW_OP_reg17, 0x61)
+DW_OP (DW_OP_reg18, 0x62)
+DW_OP (DW_OP_reg19, 0x63)
+DW_OP (DW_OP_reg20, 0x64)
+DW_OP (DW_OP_reg21, 0x65)
+DW_OP (DW_OP_reg22, 0x66)
+DW_OP (DW_OP_reg23, 0x67)
+DW_OP (DW_OP_reg24, 0x68)
+DW_OP (DW_OP_reg25, 0x69)
+DW_OP (DW_OP_reg26, 0x6a)
+DW_OP (DW_OP_reg27, 0x6b)
+DW_OP (DW_OP_reg28, 0x6c)
+DW_OP (DW_OP_reg29, 0x6d)
+DW_OP (DW_OP_reg30, 0x6e)
+DW_OP (DW_OP_reg31, 0x6f)
+DW_OP (DW_OP_breg0, 0x70)
+DW_OP (DW_OP_breg1, 0x71)
+DW_OP (DW_OP_breg2, 0x72)
+DW_OP (DW_OP_breg3, 0x73)
+DW_OP (DW_OP_breg4, 0x74)
+DW_OP (DW_OP_breg5, 0x75)
+DW_OP (DW_OP_breg6, 0x76)
+DW_OP (DW_OP_breg7, 0x77)
+DW_OP (DW_OP_breg8, 0x78)
+DW_OP (DW_OP_breg9, 0x79)
+DW_OP (DW_OP_breg10, 0x7a)
+DW_OP (DW_OP_breg11, 0x7b)
+DW_OP (DW_OP_breg12, 0x7c)
+DW_OP (DW_OP_breg13, 0x7d)
+DW_OP (DW_OP_breg14, 0x7e)
+DW_OP (DW_OP_breg15, 0x7f)
+DW_OP (DW_OP_breg16, 0x80)
+DW_OP (DW_OP_breg17, 0x81)
+DW_OP (DW_OP_breg18, 0x82)
+DW_OP (DW_OP_breg19, 0x83)
+DW_OP (DW_OP_breg20, 0x84)
+DW_OP (DW_OP_breg21, 0x85)
+DW_OP (DW_OP_breg22, 0x86)
+DW_OP (DW_OP_breg23, 0x87)
+DW_OP (DW_OP_breg24, 0x88)
+DW_OP (DW_OP_breg25, 0x89)
+DW_OP (DW_OP_breg26, 0x8a)
+DW_OP (DW_OP_breg27, 0x8b)
+DW_OP (DW_OP_breg28, 0x8c)
+DW_OP (DW_OP_breg29, 0x8d)
+DW_OP (DW_OP_breg30, 0x8e)
+DW_OP (DW_OP_breg31, 0x8f)
+DW_OP (DW_OP_regx, 0x90)
+DW_OP (DW_OP_fbreg, 0x91)
+DW_OP (DW_OP_bregx, 0x92)
+DW_OP (DW_OP_piece, 0x93)
+DW_OP (DW_OP_deref_size, 0x94)
+DW_OP (DW_OP_xderef_size, 0x95)
+DW_OP (DW_OP_nop, 0x96)
+/* DWARF 3 extensions.  */
+DW_OP (DW_OP_push_object_address, 0x97)
+DW_OP (DW_OP_call2, 0x98)
+DW_OP (DW_OP_call4, 0x99)
+DW_OP (DW_OP_call_ref, 0x9a)
+DW_OP (DW_OP_form_tls_address, 0x9b)
+DW_OP (DW_OP_call_frame_cfa, 0x9c)
+DW_OP (DW_OP_bit_piece, 0x9d)
+
+/* DWARF 4 extensions.  */
+DW_OP (DW_OP_implicit_value, 0x9e)
+DW_OP (DW_OP_stack_value, 0x9f)
+
+DW_OP_DUP (DW_OP_lo_user, 0xe0)	/* Implementation-defined range start.  */
+DW_OP_DUP (DW_OP_hi_user, 0xff)	/* Implementation-defined range end.  */
+
+/* GNU extensions.  */
+DW_OP (DW_OP_GNU_push_tls_address, 0xe0)
+/* The following is for marking variables that are uninitialized.  */
+DW_OP (DW_OP_GNU_uninit, 0xf0)
+DW_OP (DW_OP_GNU_encoded_addr, 0xf1)
+/* The GNU implicit pointer extension.
+   See http://www.dwarfstd.org/ShowIssue.php?issue=100831.1&type=open .  */
+DW_OP (DW_OP_GNU_implicit_pointer, 0xf2)
+/* The GNU entry value extension.
+   See http://www.dwarfstd.org/ShowIssue.php?issue=100909.1&type=open .  */
+DW_OP (DW_OP_GNU_entry_value, 0xf3)
+/* The GNU typed stack extension.
+   See http://www.dwarfstd.org/doc/040408.1.html .  */
+DW_OP (DW_OP_GNU_const_type, 0xf4)
+DW_OP (DW_OP_GNU_regval_type, 0xf5)
+DW_OP (DW_OP_GNU_deref_type, 0xf6)
+DW_OP (DW_OP_GNU_convert, 0xf7)
+DW_OP (DW_OP_GNU_reinterpret, 0xf9)
+/* The GNU parameter ref extension.  */
+DW_OP (DW_OP_GNU_parameter_ref, 0xfa)
+/* Extensions for Fission.  See http://gcc.gnu.org/wiki/DebugFission.  */
+DW_OP (DW_OP_GNU_addr_index, 0xfb)
+DW_OP (DW_OP_GNU_const_index, 0xfc)
+/* HP extensions.  */
+DW_OP_DUP (DW_OP_HP_unknown, 0xe0) /* Ouch, the same as GNU_push_tls_address.  */
+DW_OP (DW_OP_HP_is_value, 0xe1)
+DW_OP (DW_OP_HP_fltconst4, 0xe2)
+DW_OP (DW_OP_HP_fltconst8, 0xe3)
+DW_OP (DW_OP_HP_mod_range, 0xe4)
+DW_OP (DW_OP_HP_unmod_range, 0xe5)
+DW_OP (DW_OP_HP_tls, 0xe6)
+/* PGI (STMicroelectronics) extensions.  */
+DW_OP (DW_OP_PGI_omp_thread_num, 0xf8)
+DW_END_OP
+
+DW_FIRST_ATE (DW_ATE_void, 0x0)
+DW_ATE (DW_ATE_address, 0x1)
+DW_ATE (DW_ATE_boolean, 0x2)
+DW_ATE (DW_ATE_complex_float, 0x3)
+DW_ATE (DW_ATE_float, 0x4)
+DW_ATE (DW_ATE_signed, 0x5)
+DW_ATE (DW_ATE_signed_char, 0x6)
+DW_ATE (DW_ATE_unsigned, 0x7)
+DW_ATE (DW_ATE_unsigned_char, 0x8)
+/* DWARF 3.  */
+DW_ATE (DW_ATE_imaginary_float, 0x9)
+DW_ATE (DW_ATE_packed_decimal, 0xa)
+DW_ATE (DW_ATE_numeric_string, 0xb)
+DW_ATE (DW_ATE_edited, 0xc)
+DW_ATE (DW_ATE_signed_fixed, 0xd)
+DW_ATE (DW_ATE_unsigned_fixed, 0xe)
+DW_ATE (DW_ATE_decimal_float, 0xf)
+/* DWARF 4.  */
+DW_ATE (DW_ATE_UTF, 0x10)
+
+DW_ATE_DUP (DW_ATE_lo_user, 0x80)
+DW_ATE_DUP (DW_ATE_hi_user, 0xff)
+
+/* HP extensions.  */
+DW_ATE (DW_ATE_HP_float80, 0x80) /* Floating-point (80 bit).  */
+DW_ATE (DW_ATE_HP_complex_float80, 0x81) /* Complex floating-point (80 bit).  */
+DW_ATE (DW_ATE_HP_float128, 0x82) /* Floating-point (128 bit).  */
+DW_ATE (DW_ATE_HP_complex_float128, 0x83) /* Complex fp (128 bit).  */
+DW_ATE (DW_ATE_HP_floathpintel, 0x84) /* Floating-point (82 bit IA64).  */
+DW_ATE (DW_ATE_HP_imaginary_float80, 0x85)
+DW_ATE (DW_ATE_HP_imaginary_float128, 0x86)
+DW_ATE (DW_ATE_HP_VAX_float, 0x88) /* F or G floating.  */
+DW_ATE (DW_ATE_HP_VAX_float_d, 0x89) /* D floating.  */
+DW_ATE (DW_ATE_HP_packed_decimal, 0x8a) /* Cobol.  */
+DW_ATE (DW_ATE_HP_zoned_decimal, 0x8b) /* Cobol.  */
+DW_ATE (DW_ATE_HP_edited, 0x8c) /* Cobol.  */
+DW_ATE (DW_ATE_HP_signed_fixed, 0x8d) /* Cobol.  */
+DW_ATE (DW_ATE_HP_unsigned_fixed, 0x8e) /* Cobol.  */
+DW_ATE (DW_ATE_HP_VAX_complex_float, 0x8f) /* F or G floating complex.  */
+DW_ATE (DW_ATE_HP_VAX_complex_float_d, 0x90) /* D floating complex.  */
+
+DW_END_ATE
+
+DW_FIRST_CFA (DW_CFA_advance_loc, 0x40)
+DW_CFA (DW_CFA_offset, 0x80)
+DW_CFA (DW_CFA_restore, 0xc0)
+DW_CFA (DW_CFA_nop, 0x00)
+DW_CFA (DW_CFA_set_loc, 0x01)
+DW_CFA (DW_CFA_advance_loc1, 0x02)
+DW_CFA (DW_CFA_advance_loc2, 0x03)
+DW_CFA (DW_CFA_advance_loc4, 0x04)
+DW_CFA (DW_CFA_offset_extended, 0x05)
+DW_CFA (DW_CFA_restore_extended, 0x06)
+DW_CFA (DW_CFA_undefined, 0x07)
+DW_CFA (DW_CFA_same_value, 0x08)
+DW_CFA (DW_CFA_register, 0x09)
+DW_CFA (DW_CFA_remember_state, 0x0a)
+DW_CFA (DW_CFA_restore_state, 0x0b)
+DW_CFA (DW_CFA_def_cfa, 0x0c)
+DW_CFA (DW_CFA_def_cfa_register, 0x0d)
+DW_CFA (DW_CFA_def_cfa_offset, 0x0e)
+/* DWARF 3.  */
+DW_CFA (DW_CFA_def_cfa_expression, 0x0f)
+DW_CFA (DW_CFA_expression, 0x10)
+DW_CFA (DW_CFA_offset_extended_sf, 0x11)
+DW_CFA (DW_CFA_def_cfa_sf, 0x12)
+DW_CFA (DW_CFA_def_cfa_offset_sf, 0x13)
+DW_CFA (DW_CFA_val_offset, 0x14)
+DW_CFA (DW_CFA_val_offset_sf, 0x15)
+DW_CFA (DW_CFA_val_expression, 0x16)
+
+DW_CFA (DW_CFA_lo_user, 0x1c)
+DW_CFA (DW_CFA_hi_user, 0x3f)
+
+/* SGI/MIPS specific.  */
+DW_CFA (DW_CFA_MIPS_advance_loc8, 0x1d)
+/* GNU extensions.  */
+DW_CFA (DW_CFA_GNU_window_save, 0x2d)
+DW_CFA (DW_CFA_GNU_args_size, 0x2e)
+DW_CFA (DW_CFA_GNU_negative_offset_extended, 0x2f)
+
+DW_END_CFA
diff --git a/binutils-2.25/include/dwarf2.h b/binutils-2.25/include/dwarf2.h
new file mode 100644
index 00000000..120e2c16
--- /dev/null
+++ b/binutils-2.25/include/dwarf2.h
@@ -0,0 +1,426 @@
+/* Declarations and definitions of codes relating to the DWARF2 and
+   DWARF3 symbolic debugging information formats.
+   Copyright (C) 1992, 1993, 1995, 1996, 1997, 1999, 2000, 2001, 2002,
+   2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
+   Free Software Foundation, Inc.
+
+   Written by Gary Funck (gary@intrepid.com) The Ada Joint Program
+   Office (AJPO), Florida State University and Silicon Graphics Inc.
+   provided support for this effort -- June 21, 1995.
+
+   Derived from the DWARF 1 implementation written by Ron Guilmette
+   (rfg@netcom.com), November 1990.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3, or (at your option) any later
+   version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+/* This file is derived from the DWARF specification (a public document)
+   Revision 2.0.0 (July 27, 1993) developed by the UNIX International
+   Programming Languages Special Interest Group (UI/PLSIG) and distributed
+   by UNIX International.  Copies of this specification are available from
+   UNIX International, 20 Waterview Boulevard, Parsippany, NJ, 07054.
+
+   This file also now contains definitions from the DWARF 3 specification
+   published Dec 20, 2005, available from: http://dwarf.freestandards.org.  */
+
+#ifndef _DWARF2_H
+#define _DWARF2_H
+
+#define DW_TAG(name, value) , name = value
+#define DW_TAG_DUP(name, value) , name = value
+#define DW_FORM(name, value) , name = value
+#define DW_AT(name, value) , name = value
+#define DW_AT_DUP(name, value) , name = value
+#define DW_OP(name, value) , name = value
+#define DW_OP_DUP(name, value) , name = value
+#define DW_ATE(name, value) , name = value
+#define DW_ATE_DUP(name, value) , name = value
+#define DW_CFA(name, value) , name = value
+
+#define DW_FIRST_TAG(name, value) enum dwarf_tag { \
+  name = value
+#define DW_END_TAG };
+#define DW_FIRST_FORM(name, value) enum dwarf_form { \
+  name = value
+#define DW_END_FORM };
+#define DW_FIRST_AT(name, value) enum dwarf_attribute { \
+  name = value
+#define DW_END_AT };
+#define DW_FIRST_OP(name, value) enum dwarf_location_atom { \
+  name = value
+#define DW_END_OP };
+#define DW_FIRST_ATE(name, value) enum dwarf_type { \
+  name = value
+#define DW_END_ATE };
+#define DW_FIRST_CFA(name, value) enum dwarf_call_frame_info { \
+  name = value
+#define DW_END_CFA };
+
+#include "dwarf2.def"
+
+#undef DW_FIRST_TAG
+#undef DW_END_TAG
+#undef DW_FIRST_FORM
+#undef DW_END_FORM
+#undef DW_FIRST_AT
+#undef DW_END_AT
+#undef DW_FIRST_OP
+#undef DW_END_OP
+#undef DW_FIRST_ATE
+#undef DW_END_ATE
+#undef DW_FIRST_CFA
+#undef DW_END_CFA
+
+#undef DW_TAG
+#undef DW_TAG_DUP
+#undef DW_FORM
+#undef DW_AT
+#undef DW_AT_DUP
+#undef DW_OP
+#undef DW_OP_DUP
+#undef DW_ATE
+#undef DW_ATE_DUP
+#undef DW_CFA
+
+/* Flag that tells whether entry has a child or not.  */
+#define DW_children_no   0
+#define	DW_children_yes  1
+
+#define DW_AT_stride_size   DW_AT_bit_stride  /* Note: The use of DW_AT_stride_size is deprecated.  */
+#define DW_AT_stride   DW_AT_byte_stride  /* Note: The use of DW_AT_stride is deprecated.  */
+
+/* Decimal sign encodings.  */
+enum dwarf_decimal_sign_encoding
+  {
+    /* DWARF 3.  */
+    DW_DS_unsigned = 0x01,
+    DW_DS_leading_overpunch = 0x02,
+    DW_DS_trailing_overpunch = 0x03,
+    DW_DS_leading_separate = 0x04,
+    DW_DS_trailing_separate = 0x05
+  };
+
+/* Endianity encodings.  */
+enum dwarf_endianity_encoding
+  {
+    /* DWARF 3.  */
+    DW_END_default = 0x00,
+    DW_END_big = 0x01,
+    DW_END_little = 0x02,
+
+    DW_END_lo_user = 0x40,
+    DW_END_hi_user = 0xff
+  };
+
+/* Array ordering names and codes.  */
+enum dwarf_array_dim_ordering
+  {
+    DW_ORD_row_major = 0,
+    DW_ORD_col_major = 1
+  };
+
+/* Access attribute.  */
+enum dwarf_access_attribute
+  {
+    DW_ACCESS_public = 1,
+    DW_ACCESS_protected = 2,
+    DW_ACCESS_private = 3
+  };
+
+/* Visibility.  */
+enum dwarf_visibility_attribute
+  {
+    DW_VIS_local = 1,
+    DW_VIS_exported = 2,
+    DW_VIS_qualified = 3
+  };
+
+/* Virtuality.  */
+enum dwarf_virtuality_attribute
+  {
+    DW_VIRTUALITY_none = 0,
+    DW_VIRTUALITY_virtual = 1,
+    DW_VIRTUALITY_pure_virtual = 2
+  };
+
+/* Case sensitivity.  */
+enum dwarf_id_case
+  {
+    DW_ID_case_sensitive = 0,
+    DW_ID_up_case = 1,
+    DW_ID_down_case = 2,
+    DW_ID_case_insensitive = 3
+  };
+
+/* Calling convention.  */
+enum dwarf_calling_convention
+  {
+    DW_CC_normal = 0x1,
+    DW_CC_program = 0x2,
+    DW_CC_nocall = 0x3,
+
+    DW_CC_lo_user = 0x40,
+    DW_CC_hi_user = 0xff,
+
+    DW_CC_GNU_renesas_sh = 0x40,
+    DW_CC_GNU_borland_fastcall_i386 = 0x41,
+
+    /* This DW_CC_ value is not currently generated by any toolchain.  It is
+       used internally to GDB to indicate OpenCL C functions that have been
+       compiled with the IBM XL C for OpenCL compiler and use a non-platform
+       calling convention for passing OpenCL C vector types.  This value may
+       be changed freely as long as it does not conflict with any other DW_CC_
+       value defined here.  */
+    DW_CC_GDB_IBM_OpenCL = 0xff
+  };
+
+/* Inline attribute.  */
+enum dwarf_inline_attribute
+  {
+    DW_INL_not_inlined = 0,
+    DW_INL_inlined = 1,
+    DW_INL_declared_not_inlined = 2,
+    DW_INL_declared_inlined = 3
+  };
+
+/* Discriminant lists.  */
+enum dwarf_discrim_list
+  {
+    DW_DSC_label = 0,
+    DW_DSC_range = 1
+  };
+
+/* Line number opcodes.  */
+enum dwarf_line_number_ops
+  {
+    DW_LNS_extended_op = 0,
+    DW_LNS_copy = 1,
+    DW_LNS_advance_pc = 2,
+    DW_LNS_advance_line = 3,
+    DW_LNS_set_file = 4,
+    DW_LNS_set_column = 5,
+    DW_LNS_negate_stmt = 6,
+    DW_LNS_set_basic_block = 7,
+    DW_LNS_const_add_pc = 8,
+    DW_LNS_fixed_advance_pc = 9,
+    /* DWARF 3.  */
+    DW_LNS_set_prologue_end = 10,
+    DW_LNS_set_epilogue_begin = 11,
+    DW_LNS_set_isa = 12
+  };
+
+/* Line number extended opcodes.  */
+enum dwarf_line_number_x_ops
+  {
+    DW_LNE_end_sequence = 1,
+    DW_LNE_set_address = 2,
+    DW_LNE_define_file = 3,
+    DW_LNE_set_discriminator = 4,
+    /* HP extensions.  */
+    DW_LNE_HP_negate_is_UV_update      = 0x11,
+    DW_LNE_HP_push_context             = 0x12,
+    DW_LNE_HP_pop_context              = 0x13,
+    DW_LNE_HP_set_file_line_column     = 0x14,
+    DW_LNE_HP_set_routine_name         = 0x15,
+    DW_LNE_HP_set_sequence             = 0x16,
+    DW_LNE_HP_negate_post_semantics    = 0x17,
+    DW_LNE_HP_negate_function_exit     = 0x18,
+    DW_LNE_HP_negate_front_end_logical = 0x19,
+    DW_LNE_HP_define_proc              = 0x20,
+    DW_LNE_HP_source_file_correlation  = 0x80,
+
+    DW_LNE_lo_user = 0x80,
+    DW_LNE_hi_user = 0xff
+  };
+
+/* Sub-opcodes for DW_LNE_HP_source_file_correlation.  */
+enum dwarf_line_number_hp_sfc_ops
+  {
+    DW_LNE_HP_SFC_formfeed = 1,
+    DW_LNE_HP_SFC_set_listing_line = 2,
+    DW_LNE_HP_SFC_associate = 3
+  };
+
+/* Type codes for location list entries.
+   Extension for Fission.  See http://gcc.gnu.org/wiki/DebugFission.  */
+
+enum dwarf_location_list_entry_type
+  {
+    DW_LLE_GNU_end_of_list_entry = 0,
+    DW_LLE_GNU_base_address_selection_entry = 1,
+    DW_LLE_GNU_start_end_entry = 2,
+    DW_LLE_GNU_start_length_entry = 3
+  };
+
+#define DW_CIE_ID	  0xffffffff
+#define DW64_CIE_ID	  0xffffffffffffffffULL
+#define DW_CIE_VERSION	  1
+
+#define DW_CFA_extended   0
+
+#define DW_CHILDREN_no		     0x00
+#define DW_CHILDREN_yes		     0x01
+
+#define DW_ADDR_none		0
+
+/* Source language names and codes.  */
+enum dwarf_source_language
+  {
+    DW_LANG_C89 = 0x0001,
+    DW_LANG_C = 0x0002,
+    DW_LANG_Ada83 = 0x0003,
+    DW_LANG_C_plus_plus = 0x0004,
+    DW_LANG_Cobol74 = 0x0005,
+    DW_LANG_Cobol85 = 0x0006,
+    DW_LANG_Fortran77 = 0x0007,
+    DW_LANG_Fortran90 = 0x0008,
+    DW_LANG_Pascal83 = 0x0009,
+    DW_LANG_Modula2 = 0x000a,
+    /* DWARF 3.  */
+    DW_LANG_Java = 0x000b,
+    DW_LANG_C99 = 0x000c,
+    DW_LANG_Ada95 = 0x000d,
+    DW_LANG_Fortran95 = 0x000e,
+    DW_LANG_PLI = 0x000f,
+    DW_LANG_ObjC = 0x0010,
+    DW_LANG_ObjC_plus_plus = 0x0011,
+    DW_LANG_UPC = 0x0012,
+    DW_LANG_D = 0x0013,
+    /* DWARF 4.  */
+    DW_LANG_Python = 0x0014,
+    /* DWARF 5.  */
+    DW_LANG_Go = 0x0016,
+
+    DW_LANG_lo_user = 0x8000,	/* Implementation-defined range start.  */
+    DW_LANG_hi_user = 0xffff,	/* Implementation-defined range start.  */
+
+    /* MIPS.  */
+    DW_LANG_Mips_Assembler = 0x8001,
+    /* UPC.  */
+    DW_LANG_Upc = 0x8765,
+    /* HP extensions.  */
+    DW_LANG_HP_Bliss     = 0x8003,
+    DW_LANG_HP_Basic91   = 0x8004,
+    DW_LANG_HP_Pascal91  = 0x8005,
+    DW_LANG_HP_IMacro    = 0x8006,
+    DW_LANG_HP_Assembler = 0x8007
+  };
+
+/* Names and codes for macro information.  */
+enum dwarf_macinfo_record_type
+  {
+    DW_MACINFO_define = 1,
+    DW_MACINFO_undef = 2,
+    DW_MACINFO_start_file = 3,
+    DW_MACINFO_end_file = 4,
+    DW_MACINFO_vendor_ext = 255
+  };
+
+/* Names and codes for new style macro information.  */
+enum dwarf_macro_record_type
+  {
+    DW_MACRO_GNU_define = 1,
+    DW_MACRO_GNU_undef = 2,
+    DW_MACRO_GNU_start_file = 3,
+    DW_MACRO_GNU_end_file = 4,
+    DW_MACRO_GNU_define_indirect = 5,
+    DW_MACRO_GNU_undef_indirect = 6,
+    DW_MACRO_GNU_transparent_include = 7,
+    /* Extensions for DWZ multifile.
+       See http://www.dwarfstd.org/ShowIssue.php?issue=120604.1&type=open .  */
+    DW_MACRO_GNU_define_indirect_alt = 8,
+    DW_MACRO_GNU_undef_indirect_alt = 9,
+    DW_MACRO_GNU_transparent_include_alt = 10,
+    DW_MACRO_GNU_lo_user = 0xe0,
+    DW_MACRO_GNU_hi_user = 0xff
+  };
+
+/* @@@ For use with GNU frame unwind information.  */
+
+#define DW_EH_PE_absptr		0x00
+#define DW_EH_PE_omit		0xff
+
+#define DW_EH_PE_uleb128	0x01
+#define DW_EH_PE_udata2		0x02
+#define DW_EH_PE_udata4		0x03
+#define DW_EH_PE_udata8		0x04
+#define DW_EH_PE_sleb128	0x09
+#define DW_EH_PE_sdata2		0x0A
+#define DW_EH_PE_sdata4		0x0B
+#define DW_EH_PE_sdata8		0x0C
+#define DW_EH_PE_signed		0x08
+
+#define DW_EH_PE_pcrel		0x10
+#define DW_EH_PE_textrel	0x20
+#define DW_EH_PE_datarel	0x30
+#define DW_EH_PE_funcrel	0x40
+#define DW_EH_PE_aligned	0x50
+
+#define DW_EH_PE_indirect	0x80
+
+/* Codes for the debug sections in a dwarf package (.dwp) file.
+   Extensions for Fission.  See http://gcc.gnu.org/wiki/DebugFissionDWP.  */
+enum dwarf_sect
+  {
+    DW_SECT_INFO = 1,
+    DW_SECT_TYPES = 2,
+    DW_SECT_ABBREV = 3,
+    DW_SECT_LINE = 4,
+    DW_SECT_LOC = 5,
+    DW_SECT_STR_OFFSETS = 6,
+    DW_SECT_MACINFO = 7,
+    DW_SECT_MACRO = 8,
+    DW_SECT_MAX = 8
+  };
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Return the name of a DW_TAG_ constant, or NULL if the value is not
+   recognized.  */
+extern const char *get_DW_TAG_name (unsigned int tag);
+
+/* Return the name of a DW_AT_ constant, or NULL if the value is not
+   recognized.  */
+extern const char *get_DW_AT_name (unsigned int attr);
+
+/* Return the name of a DW_FORM_ constant, or NULL if the value is not
+   recognized.  */
+extern const char *get_DW_FORM_name (unsigned int form);
+
+/* Return the name of a DW_OP_ constant, or NULL if the value is not
+   recognized.  */
+extern const char *get_DW_OP_name (unsigned int op);
+
+/* Return the name of a DW_ATE_ constant, or NULL if the value is not
+   recognized.  */
+extern const char *get_DW_ATE_name (unsigned int enc);
+
+/* Return the name of a DW_CFA_ constant, or NULL if the value is not
+   recognized.  */
+extern const char *get_DW_CFA_name (unsigned int opc);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _DWARF2_H */
diff --git a/binutils-2.25/include/dyn-string.h b/binutils-2.25/include/dyn-string.h
new file mode 100644
index 00000000..2b147271
--- /dev/null
+++ b/binutils-2.25/include/dyn-string.h
@@ -0,0 +1,73 @@
+/* An abstract string datatype.
+   Copyright (C) 1998, 1999, 2000, 2002, 2004, 2005, 2009
+   Free Software Foundation, Inc.
+   Contributed by Mark Mitchell (mark@markmitchell.com).
+
+This file is part of GCC.
+   
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+#ifndef DYN_STRING_H
+#define DYN_STRING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct dyn_string
+{
+  int allocated;	/* The amount of space allocated for the string.  */
+  int length;		/* The actual length of the string.  */
+  char *s;		/* The string itself, NUL-terminated.  */
+}* dyn_string_t;
+
+/* The length STR, in bytes, not including the terminating NUL.  */
+#define dyn_string_length(STR)                                          \
+  ((STR)->length)
+
+/* The NTBS in which the contents of STR are stored.  */
+#define dyn_string_buf(STR)                                             \
+  ((STR)->s)
+
+/* Compare DS1 to DS2 with strcmp.  */
+#define dyn_string_compare(DS1, DS2)                                    \
+  (strcmp ((DS1)->s, (DS2)->s))
+
+
+extern int dyn_string_init (struct dyn_string *, int);
+extern dyn_string_t dyn_string_new (int);
+extern void dyn_string_delete (dyn_string_t);
+extern char *dyn_string_release (dyn_string_t);
+extern dyn_string_t dyn_string_resize (dyn_string_t, int);
+extern void dyn_string_clear (dyn_string_t);
+extern int dyn_string_copy (dyn_string_t, dyn_string_t);
+extern int dyn_string_copy_cstr (dyn_string_t, const char *);
+extern int dyn_string_prepend (dyn_string_t, dyn_string_t);
+extern int dyn_string_prepend_cstr (dyn_string_t, const char *);
+extern int dyn_string_insert (dyn_string_t, int, dyn_string_t);
+extern int dyn_string_insert_cstr (dyn_string_t, int, const char *);
+extern int dyn_string_insert_char (dyn_string_t, int, int);
+extern int dyn_string_append (dyn_string_t, dyn_string_t);
+extern int dyn_string_append_cstr (dyn_string_t, const char *);
+extern int dyn_string_append_char (dyn_string_t, int);
+extern int dyn_string_substring (dyn_string_t,  dyn_string_t, int, int);
+extern int dyn_string_eq (dyn_string_t, dyn_string_t);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined (DYN_STRING_H) */
diff --git a/binutils-2.25/include/elf/ChangeLog b/binutils-2.25/include/elf/ChangeLog
new file mode 100644
index 00000000..c2577e88
--- /dev/null
+++ b/binutils-2.25/include/elf/ChangeLog
@@ -0,0 +1,1892 @@
+2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
+
+	* mips.h (enum): Add Tag_GNU_MIPS_ABI_MSA.
+	(enum): Add Val_GNU_MIPS_ABI_MSA_ANY and Val_GNU_MIPS_ABI_MSA_128.
+
+2013-09-17  Doug Gilmore  <Doug.Gilmore@imgtec.com>
+
+	* mips.h (EF_MIPS_FP64): New e_flags bit.
+
+2013-08-09  Nick Clifton  <nickc@redhat.com>
+
+	* rl78.c (E_FLAG_RL78_G10): Define.
+
+2013-07-15  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h (Tag_GNU_MIPS_ABI_FP): Remove comment.
+	(Val_GNU_MIPS_ABI_FP_ANY, Val_GNU_MIPS_ABI_FP_DOUBLE,
+	Val_GNU_MIPS_ABI_FP_SINGLE, Val_GNU_MIPS_ABI_FP_SOFT,
+	Val_GNU_MIPS_ABI_FP_64): New enum.
+
+2013-07-12  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h (EF_MIPS_NAN2008): New macro.
+
+2013-07-08  Tristan Gingold  <gingold@adacore.com>
+
+	* ia64.h (STB_VMS_WEAK, STB_VMS_SYSTEM): Add.
+
+2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* s390.h: Add new relocs R_390_PC12DBL, R_390_PLT12DBL,
+	R_390_PC24DBL, and R_390_PLT24DBL.
+
+2013-06-26  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64.h: Add ELF32 reloc codes and remove fake ELF64 ones.
+
+2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h (ELF_ST_IS_MIPS_PLT): Respect STO_MIPS16 setting.
+	(ELF_ST_SET_MIPS_PLT): Likewise.
+
+2013-06-19  Will Newton  <will.newton@linaro.org>
+
+	* aarch64.h: Remove R_AARCH64_IRELATIVE.
+
+2013-06-07  Will Newton  <will.newton@linaro.org>
+
+	* aarch64.h: Add R_AARCH64_IRELATIVE reloc.
+
+2013-06-06  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h (ELF_ST_SET_MIPS_PIC): Clear any STO_MIPS16 setting.
+
+2013-05-30  Paul Brook  <paul@codesourcery.com>
+
+	* mips.h (R_MIPS_EH): New.
+
+2013-05-28  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64.h (R_AARCH64_TLSDESC_LD64_PREL19): Rename to ...
+	(R_AARCH64_TLSDESC_LD_PREL19): ... this.
+	(R_AARCH64_TLSDESC_ADR_PAGE): Rename to ...
+	(R_AARCH64_TLSDESC_ADR_PAGE21): ... this.
+
+2013-05-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* common.h (EM_INTEL205): New.
+	(EM_INTEL206): Likewise.
+	(EM_INTEL207): Likewise.
+	(EM_INTEL208): Likewise.
+	(EM_INTEL209): Likewise.
+
+2013-05-02  Nick Clifton  <nickc@redhat.com>
+
+	* msp430.h: Add MSP430X relocs.
+	Add some more MSP430 machine numbers.
+	Add values used by .MSP430.attributes section.
+
+2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
+
+	* h8.h: Add new reloc R_H8_DISP32A16 for relaxation of
+	mov @(disp:32,ERx) to mov @(disp:16,ERx).
+
+2013-03-08  Andreas Arnez  <arnez@linux.vnet.ibm.com>
+
+	* common.h (NT_S390_TDB): Define.
+
+2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
+            Andrew Jenner <andrew@codesourcery.com>
+
+	Based on patches from Altera Corporation.
+
+	* nios2.h: New file.
+
+2013-01-24  Nick Clifton  <nickc@redhat.com>
+
+	* v850.h: Add support for e3v5 architecture.
+	Reorganize processor selection macros.
+
+2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386.h (R_386_SIZE32): Fill it.
+	* x86-64.h (R_X86_64_SIZE32): Likewise.
+	(R_X86_64_SIZE64): Likewise.
+
+2013-01-10  Will Newton <will.newton@imgtec.com>
+
+	* common.h: Fix case of "Meta".
+	* metag.h: New file.
+
+2013-01-08  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* common.h (NT_ARM_TLS, NT_ARM_HW_BREAK, NT_ARM_HW_WATCH): New macro
+	definitions.
+
+2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
+
+	* mips.h: Add MIPS machine variant number for r5900 which is
+	compatible with old Playstation 2 software.
+
+2012-11-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* common.h (DF_1_CONLFAT): Renamed to ...
+	(DF_1_CONFALT): This.
+	(DF_1_ENDFILTEE): New.
+	(DF_1_DISPRELDNE): Likewise.
+	(DF_1_DISPRELPND): Likewise.
+	(DF_1_NODIRECT): Likewise.
+	(DF_1_IGNMULDEF): Likewise.
+	(DF_1_NOKSYMS): Likewise.
+	(DF_1_NOHDR): Likewise.
+	(DF_1_EDITED): Likewise.
+	(DF_1_NORELOC): Likewise.
+	(DF_1_SYMINTPOSE): Likewise.
+	(DF_1_GLOBAUDIT): Likewise.
+	(DF_1_SINGLETON): Likewise.
+
+2012-11-09  Nick Clifton  <nickc@redhat.com>
+
+	* rx.h (EF_RX_CPU_RX): Add comment.
+	(E_FLAG_RX_ABI): Define.
+
+	* v850.h: Add RH850 ABI values.
+
+2012-11-08  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h (EF_MIPS_32BITMODE): Move next to lower-order bits.
+
+2012-11-01  Tom Tromey  <tromey@redhat.com>
+
+	* common.h (NT_386_TLS, NT_386_IOPERM): New defines.
+
+2012-10-30  Steve McIntyre  <steve.mcintyre@linaro.org>
+
+	* elf/arm.h (EF_ARM_ABI_FLOAT_SOFT): New define.
+	(EF_ARM_ABI_FLOAT_HARD): Likewise.
+
+2012-10-23  Tom Tromey  <tromey@redhat.com>
+
+	* common.h (NT_SIGINFO, NT_FILE): New defines.
+
+2012-08-27  Walter Lee  <walt@tilera.com>
+
+	* tilegx.h (R_TILEGX_IMM16_X0_HW0_PLT_PCREL): New relocation.
+	(R_TILEGX_IMM16_X1_HW0_PLT_PCREL): Ditto.
+	(R_TILEGX_IMM16_X0_HW1_PLT_PCREL): Ditto.
+	(R_TILEGX_IMM16_X1_HW1_PLT_PCREL): Ditto.
+	(R_TILEGX_IMM16_X0_HW2_PLT_PCREL): Ditto.
+	(R_TILEGX_IMM16_X1_HW2_PLT_PCREL): Ditto.
+	(R_TILEGX_IMM16_X0_HW3_PLT_PCREL): Ditto.
+	(R_TILEGX_IMM16_X1_HW3_PLT_PCREL): Ditto.
+	(R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL): Ditto.
+	(R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL): Ditto.
+	(R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL): Ditto.
+	(R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL): Ditto.
+	(R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL	): Ditto.
+	(R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL): Ditto.
+
+2012-08-13  Ian Bolton  <ian.bolton@arm.com>
+            Laurent Desnogues  <laurent.desnogues@arm.com>
+            Jim MacArthur  <jim.macarthur@arm.com>
+            Marcus Shawcroft  <marcus.shawcroft@arm.com>
+            Nigel Stephens  <nigel.stephens@arm.com>
+            Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+            Richard Earnshaw  <rearnsha@arm.com>
+            Sofiane Naci  <sofiane.naci@arm.com>
+            Tejas Belagod  <tejas.belagod@arm.com>
+            Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64.h: New file.
+	* common.h (EM_res183): Rename to EM_AARCH64.
+	(EM_res184): Rename to EM_ARM184.
+
+2012-06-28  Iain Sandoe  <iain@codesourcery.com>
+
+	* common.h (AT_L1I_CACHESHAPE, AT_L1D_CACHESHAPE,
+	AT_L2_CACHESHAPE, AT_L3_CACHESHAPE): New defines.
+
+2012-05-16  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/13503
+	* avr.h (RELOC_NUMBERS): Rename R_AVR_8_HHI8 to R_AVR_8_HLO8.
+
+2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
+
+	* m68hc11.h (R_M68HC12_16B, R_M68HC12_PCREL_9, R_M68HC12_PCREL_10)
+	R_M68HC12_HI8XG, R_M68HC12_LO8XG): New relocations.
+	(E_M68HC11_XGATE_RAMOFFSET): Define.
+
+2012-05-14  James Lemke  <jwlemke@codesourcery.com>
+	* ppc.h (SEC_PPC_VLE): Remove.
+
+2012-05-14  Catherine Moore  <clm@codesourcery.com>
+	    James Lemke  <jwlemke@codesourcery.com>
+
+	* ppc.h (R_PPC_VLE_REL8): New reloction.
+	(R_PPC_VLE_REL15): Likewise.
+	(R_PPC_VLE_REL24): Likewise.
+	(R_PPC_VLE_LO16A): Likewise.
+	(R_PPC_VLE_LO16D): Likewise.
+	(R_PPC_VLE_HI16A): Likewise.
+	(R_PPC_VLE_HI16D): Likewise.
+	(R_PPC_VLE_HA16A): Likewise.
+	(R_PPC_VLE_HA16D): Likewise.
+	(R_PPC_VLE_SDA21): Likewise.
+	(R_PPC_VLE_SDA21_LO): Likewise.
+	(R_PPC_VLE_SDAREL_LO16A): Likewise.
+	(R_PPC_VLE_SDAREL_LO16D): Likewise.
+	(R_PPC_VLE_SDAREL_HI16A): Likewise.
+	(R_PPC_VLE_SDAREL_HI16D): Likewise.
+	(R_PPC_VLE_SDAREL_HA16A): Likewise.
+	(R_PPC_VLE_SDAREL_HA16D): Likewise.
+	(SEC_PPC_VLE): Remove.
+	(PF_PPC_VLE): New program header flag.
+	(SHF_PPC_VLE): New section header flag.
+	(vle_opcodes, vle_num_opcodes): New.
+	(VLE_OP): New macro.
+	(VLE_OP_TO_SEG): New macro.
+
+2012-05-11  Georg-Johann Lay  <avr@gjlay.de
+
+	PR target/13503
+	* elf/avr.h (RELOC_NUMBERS): Add values for R_AVR_8_LO8,
+	R_AVR_8_HI8, R_AVR_8_HHI8.
+
+2012-05-03  Sean Keys  <skeys@ipdatasys.com>
+
+	* xgate.h: Mininal file to support XGATE relocations.
+
+2012-04-27  David S. Miller  <davem@davemloft.net>
+
+	* sparc.h: Add new ELF_SPARC_HWCAP_* defines for crypto,
+	pause, and compare-and-branch instructions.
+
+2012-03-07  Nick Clifton  <nickc@redhat.com>
+
+	* mn10300.h (elf_mn10300_reloc_type): Add R_MN10300_TLS_GD,
+	R_MN10300_TLS_LD, R_MN10300_TLS_LDO, R_MN10300_TLS_GOTIE,
+	R_MN10300_TLS_IE, R_MN10300_TLS_LE, R_MN10300_TLS_DPTMOD,
+	R_MN10300_TLS_DTPOFF and R_MN10300_TLS_TPOFF.
+
+2012-02-25  Walter Lee  <walt@tilera.com>
+
+	* tilegx.h (R_TILEGX_IMM16_X0_HW1_GOT): Delete.
+	(R_TILEGX_IMM16_X1_HW1_GOT): Ditto.
+	(R_TILEGX_IMM16_X0_HW2_GOT): Ditto.
+	(R_TILEGX_IMM16_X1_HW2_GOT): Ditto.
+	(R_TILEGX_IMM16_X0_HW3_GOT): Ditto.
+	(R_TILEGX_IMM16_X1_HW3_GOT): Ditto.
+	(R_TILEGX_IMM16_X0_HW2_LAST_GOT): Ditto.
+	(R_TILEGX_IMM16_X1_HW2_LAST_GOT): Ditto.
+	(R_TILEGX_IMM16_X0_HW1_TLS_GD): Ditto.
+	(R_TILEGX_IMM16_X1_HW1_TLS_GD): Ditto.
+	(R_TILEGX_IMM16_X0_HW2_TLS_GD): Ditto.
+	(R_TILEGX_IMM16_X1_HW2_TLS_GD): Ditto.
+	(R_TILEGX_IMM16_X0_HW3_TLS_GD): Ditto.
+	(R_TILEGX_IMM16_X1_HW3_TLS_GD): Ditto.
+	(R_TILEGX_IMM16_X0_HW2_LAST_TLS_GD): Ditto.
+	(R_TILEGX_IMM16_X1_HW2_LAST_TLS_GD): Ditto.
+	(R_TILEGX_IMM16_X0_HW1_TLS_IE): Ditto.
+	(R_TILEGX_IMM16_X1_HW1_TLS_IE): Ditto.
+	(R_TILEGX_IMM16_X0_HW2_TLS_IE): Ditto.
+	(R_TILEGX_IMM16_X1_HW2_TLS_IE): Ditto.
+	(R_TILEGX_IMM16_X0_HW3_TLS_IE): Ditto.
+	(R_TILEGX_IMM16_X1_HW3_TLS_IE): Ditto.
+	(R_TILEGX_IMM16_X0_HW2_LAST_TLS_IE): Ditto.
+	(R_TILEGX_IMM16_X1_HW2_LAST_TLS_IE): Ditto.
+	(R_TILEGX_IMM16_X0_HW0_TLS_LE): New relocation.
+	(R_TILEGX_IMM16_X1_HW0_TLS_LE): Ditto.
+	(R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE): Ditto.
+	(R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE): Ditto.
+	(R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE): Ditto.
+	(R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE): Ditto.
+	(R_TILEGX_TLS_GD_CALL): Ditto.
+	(R_TILEGX_IMM8_X0_TLS_GD_ADD): Ditto.
+	(R_TILEGX_IMM8_X1_TLS_GD_ADD): Ditto.
+	(R_TILEGX_IMM8_Y0_TLS_GD_ADD): Ditto.
+	(R_TILEGX_IMM8_Y1_TLS_GD_ADD): Ditto.
+	(R_TILEGX_TLS_IE_LOAD): Ditto.
+	(R_TILEGX_IMM8_X0_TLS_ADD): Ditto.
+	(R_TILEGX_IMM8_X1_TLS_ADD): Ditto.
+	(R_TILEGX_IMM8_Y0_TLS_ADD): Ditto.
+	(R_TILEGX_IMM8_Y1_TLS_ADD): Ditto.
+	* tilepro.h (R_TILEPRO_TLS_GD_CALL): New relocation.
+	(R_TILEPRO_IMM8_X0_TLS_GD_ADD): Ditto.
+	(R_TILEPRO_IMM8_X1_TLS_GD_ADD): Ditto.
+	(R_TILEPRO_IMM8_Y0_TLS_GD_ADD): Ditto.
+	(R_TILEPRO_IMM8_Y1_TLS_GD_ADD): Ditto.
+	(R_TILEPRO_TLS_IE_LOAD): Ditto.
+	(R_TILEPRO_IMM16_X0_TLS_LE): Ditto.
+	(R_TILEPRO_IMM16_X1_TLS_LE): Ditto.
+	(R_TILEPRO_IMM16_X0_TLS_LE_LO): Ditto.
+	(R_TILEPRO_IMM16_X1_TLS_LE_LO): Ditto.
+	(R_TILEPRO_IMM16_X0_TLS_LE_HI): Ditto.
+	(R_TILEPRO_IMM16_X1_TLS_LE_HI): Ditto.
+	(R_TILEPRO_IMM16_X0_TLS_LE_HA): Ditto.
+	(R_TILEPRO_IMM16_X1_TLS_LE_HA): Ditto.
+
+2011-12-22  DJ Delorie  <dj@redhat.com>
+
+	* rl78.h (R_RL78_RH_RELAX, R_RL78_RH_SFR, R_RL78_RH_SADDR): New.
+	(RL78_RELAXA_BRA, RL78_RELAXA_ADDR16: New.
+
+2011-12-19  Chung-Lin Tang  <cltang@codesourcery.com>
+
+	* mips.h (elf_mips_reloc_type): Add R_MIPS16_TLS_* entries.
+
+2011-12-06  Ulrich Weigand  <uweigand@de.ibm.com>
+
+	* common.h (NT_S390_LAST_BREAK): Define.
+	(NT_S390_SYSTEM_CALL): Likewise.
+
+2011-11-01  DJ Delorie  <dj@redhat.com>
+
+	* common.h (EM_RL78, EM_78K0R): New.
+	* rl78.h: New.
+
+2011-10-25  Joern Rennecke  <joern.rennecke@embecosm.com>
+
+	* epiphany.h: New file.
+	* common.h (EM_ADAPTEVA_EPIPHANY): Define.
+
+2011-10-10  Alan Modra  <amodra@gmail.com>
+
+	* ppc64.h (R_PPC64_TOCSAVE): Add.
+
+2011-10-05  DJ Delorie  <dj@redhat.com>
+
+	* rx.h (E_FLAG_RX_PID): New.
+
+2011-09-21  David S. Miller  <davem@davemloft.net>
+
+	* sparc.h (Tag_GNU_Sparc_HWCAPS): New object attribute.
+	(ELF_SPARC_HWCAP_*): New HWCAPS bitmask values.
+
+2011-08-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/13082
+	* x86-64.h (R_X86_64_RELATIVE64): New.
+
+2011-07-24  Chao-ying Fu  <fu@mips.com>
+            Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h (R_MICROMIPS_min): New relocations.
+	(R_MICROMIPS_26_S1): Likewise.
+	(R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise.
+	(R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise.
+	(R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise.
+	(R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise.
+	(R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise.
+	(R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise.
+	(R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise.
+	(R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise.
+	(R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise.
+	(R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise.
+	(R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise.
+	(R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise.
+	(R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise.
+	(R_MICROMIPS_TLS_GOTTPREL): Likewise.
+	(R_MICROMIPS_TLS_TPREL_HI16): Likewise.
+	(R_MICROMIPS_TLS_TPREL_LO16): Likewise.
+	(R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise.
+	(R_MICROMIPS_max): Likewise.
+	(EF_MIPS_ARCH_ASE_MICROMIPS): New macro.
+	(STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise.
+	(ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise.
+	(STO_MICROMIPS): Likewise.
+	(ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise.
+	(ELF_ST_IS_COMPRESSED): Likewise.
+	(STO_MIPS_PLT, STO_MIPS_PIC): Rework.
+	(ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise.
+	(STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise.
+
+2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* common.h (EM_K1OM): New.
+
+2011-07-03  Samuel Thibault  <samuel.thibault@gnu.org>
+	    Thomas Schwinge  <thomas@schwinge.name>
+
+	PR binutils/12913
+	* common.h (ELFOSABI_GNU): Define, replaces...
+	(ELFOSABI_LINUX): ... this, kept as an alias.
+	(ELFOSABI_HURD): Remove.
+
+2011-06-15  Ulrich Weigand  <ulrich.weigand@linaro.org>
+
+	* common.h (NT_ARM_VFP): Define.
+
+2011-06-13  Walter Lee  <walt@tilera.com>
+
+	* common.h: Add EM_TILEGX.
+	* tilegx.h: New file.
+	* tilepro.h: New file.
+
+2011-06-09  Tristan Gingold  <gingold@adacore.com>
+
+	* ia64.h (Elf64_External_VMS_ORIG_DYN_Note): New struct.
+
+2011-06-02  Nick Clifton  <nickc@redhat.com>
+
+	* common.h: Fix spelling mistake in comment.
+	* reloc-macros.h: Likewise.
+
+2011-05-31  Paul Brook  <paul@codesourcery.com>
+
+	* arm.h (arm_st_branch_type): Add ST_BRANCH_UNKNOWN.
+
+2011-05-09  Paul Brook  <paul@codesourcery.com>
+
+	* tic6x.h (ELF_STRING_C6000_unwind,
+	ELF_STRING_C6000_unwind_info, ELF_STRING_C6000_unwind_once,
+	ELF_STRING_C6000_unwind_info_once): Define.
+
+2011-04-15  Sergio Durigan Junior  <sergiodj@redhat.com>
+
+	* common.h (NT_STAPSDT): New define.
+
+2011-03-31  Bernd Schmidt  <bernds@codesourcery.com>
+
+	* tic6x.h (R_C6000_JUMP_SPLOT, R_C6000_EHTYPE,
+	R_C6000_PCR_H16, R_C6000_PCR_L16): New relocs.
+	(SHN_TIC6X_SCOMMON): Define.
+
+2011-03-31  Tristan Gingold  <gingold@adacore.com>
+
+	* ia64.h (Elf64_External_VMS_Note): New struct.
+	(NT_VMS_MHD, NT_VMS_LNM, NT_VMS_SRC, NT_VMS_TITLE, NT_VMS_EIDC)
+	(NT_VMS_FPMODE, NT_VMS_LINKTIME, NT_VMS_IMGNAM, NT_VMS_IMGID)
+	(NT_VMS_LINKID, NT_VMS_IMGBID, NT_VMS_GSTNAM, NT_VMS_ORIG_DYN)
+	(NT_VMS_PATCHTIME) New macros.
+
+2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* arm.h (R_ARM_IRELATIVE): New relocation.
+
+2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
+
+	* internal.h (elf_internal_sym): Add st_target_internal.
+	* arm.h (arm_st_branch_type): New enum.
+	(ARM_SYM_BRANCH_TYPE): New macro.
+
+2011-03-10  Nick Clifton  <nickc@redhat.com>
+
+	* common.h (EM_V850): V850s now supplied by Renesas.
+
+2011-02-25  Alan Modra  <amodra@gmail.com>
+
+	PR 12516
+	* internal.h (ELF_SECTION_IN_SEGMENT_1): Don't match zero size
+	sections at start or end of PT_DYNAMIC.
+
+2011-01-10  Nathan Sidwell  <nathan@codesourcery.com>
+	    Glauber de Oliveira Costa  <glommer@gmail.com>
+
+	* arm.h (R_ARM_TLS_DESC, R_ARM_TLS_GOTDESC, R_ARM_TLS_CALL,
+	R_ARM_TLS_DESCSEQ, T_ARM_THM_TLS_CALL, R_ARM_THM_TLS_DESCSEQ): New
+	relocations.
+
+2010-11-16  Jie Zhang  <jie.zhang@analog.com>
+
+	* bfin.h (EF_BFIN_CODE_IN_L1): Define.
+	(EF_BFIN_DATA_IN_L1): Define.
+
+2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
+
+	* mips.h (E_MIPS_MACH_LS3A): Defined.
+
+2010-11-02  Joseph Myers  <joseph@codesourcery.com>
+
+	* tic6x-attrs.h (Tag_ABI_wchar_t, Tag_ABI_stack_align_needed,
+	Tag_ABI_stack_align_preserved, Tag_ABI_PID, Tag_ABI_PIC,
+	Tag_ABI_array_object_alignment,
+	Tag_ABI_array_object_align_expected, Tag_ABI_conformance): Define.
+
+2010-10-29  Joseph Myers  <joseph@codesourcery.com>
+
+	* tic6x-attrs.h (Tag_ABI_compatibility): Define.
+
+2010-10-29  Bernd Schmidt  <bernds@codesourcery.com>
+            Joseph Myers  <joseph@codesourcery.com>
+
+	* tic6x-attrs.h (Tag_ABI_DSBT): New.
+
+2010-10-21  Joseph Myers  <joseph@codesourcery.com>
+
+	* tic6x-attrs.h (Tag_C6XABI_Tag_CPU_arch): Change to Tag_ISA,
+	value 4.
+	* tic6x.h (Values for Tag_C6XABI_Tag_CPU_arch): Rename for
+	attribute renaming.
+
+2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
+	    Ina Pandit  <ina.pandit@kpitcummins.com>
+
+	* v850.h: Add support for V850E2 and V850E2V3.
+	(v850_reloc_type): Update the newly added relocations
+
+2010-07-20  Alan Modra  <amodra@gmail.com>
+
+	* internal.h (ELF_TBSS_SPECIAL): New macro, extracted from..
+	(ELF_SECTION_SIZE): ..here.
+	(ELF_SECTION_IN_SEGMENT_1): Add "strict" arg.
+	(ELF_SECTION_IN_SEGMENT_STRICT): New macro.
+
+2010-06-25  Alan Modra  <amodra@gmail.com>
+
+	* ppc64.h (R_PPC64_LO_DS_OPT): Define.
+
+2010-06-15  Joseph Myers  <joseph@codesourcery.com>
+
+	* tic6x-attrs.h: New.
+	* tic6x.h: Include elf/tic6x-attrs.h for attribute table.
+	(C6XABI_Tag_CPU_arch_none, C6XABI_Tag_CPU_arch_C62X,
+	C6XABI_Tag_CPU_arch_C67X, C6XABI_Tag_CPU_arch_C67XP,
+	C6XABI_Tag_CPU_arch_C64X, C6XABI_Tag_CPU_arch_C64XP,
+	C6XABI_Tag_CPU_arch_C674X): Define.
+
+2010-06-11  Tristan Gingold  <gingold@adacore.com>
+
+	* ia64.h (EF_IA_64_VMS_COMCOD, EF_IA_64_VMS_COMCOD_SUCCESS)
+	(EF_IA_64_VMS_COMCOD_WARNING, EF_IA_64_VMS_COMCOD_ERROR)
+	(EF_IA_64_VMS_COMCOD_ABORT, EF_IA_64_VMS_LINKAGES): Define.
+	(VMS_LF_CALL_DEBUG, VMS_LF_NOP0BUFS, VMS_LF_P0IMAGE)
+	(VMS_LF_MKTHREADS, VMS_LF_UPCALLS, VMS_LF_IMGSTA)
+	(VMS_LF_INITIALIZE, VMS_LF_MAIN, VMS_LF_EXE_INIT)
+	(VMS_LF_TBK_IN_IMG, VMS_LF_DBG_IN_IMG, VMS_LF_TBK_IN_DSF)
+	(VMS_LF_DBG_IN_DSF, VMS_LF_SIGNATURES, VMS_LF_REL_SEG_OFF): Define.
+	(VMS_STO_VISIBILITY, VMS_ST_VISIBILITY, VMS_STO_FUNC_TYPE)
+	(VMS_ST_FUNC_TYPE, VMS_SFT_CODE_ADDR, VMS_SFT_SYMV_IDX)
+	(VMS_SFT_FD, VMS_SFT_RESERVE, VMS_STO_LINKAGE, VMS_ST_LINKAGE)
+	(VMS_STL_IGNORE, VMS_STL_RESERVE, VMS_STL_STD, VMS_STL_LNK): Define.
+	(Elf64_External_VMS_IMAGE_FIXUP): New declaration.
+	(Elf64_External_VMS_IMAGE_RELA): Ditto.
+	(R_IA64_VMS_DIR8, R_IA64_VMS_DIR16LSB, R_IA64_VMS_CALL_SIGNATURE)
+	(R_IA64_VMS_EXECLET_FUNC, R_IA64_VMS_EXECLET_DATA, R_IA64_VMS_FIX8)
+	(R_IA64_VMS_FIX16, R_IA64_VMS_FIX32, R_IA64_VMS_FIX64)
+	(R_IA64_VMS_FIXFD, R_IA64_VMS_ACC_LOAD, R_IA64_VMS_ACC_ADD)
+	(R_IA64_VMS_ACC_SUB, R_IA64_VMS_ACC_MUL, R_IA64_VMS_ACC_DIV)
+	(R_IA64_VMS_ACC_AND, R_IA64_VMS_ACC_IOR, R_IA64_VMS_ACC_EOR)
+	(R_IA64_VMS_ACC_ASH, R_IA64_VMS_ACC_STO8, R_IA64_VMS_ACC_STO16LSH)
+	(R_IA64_VMS_ACC_STO32LSH, R_IA64_VMS_ACC_STO64LSH): New.
+
+2010-05-25  Daniel Jacobowitz  <dan@codesourcery.com>
+	    Joseph Myers  <joseph@codesourcery.com>
+	    Andrew Stubbs  <ams@codesourcery.com>
+
+	* sh.h (EF_SH_PIC, EF_SH_FDPIC): Define.
+	(R_SH_FIRST_INVALID_RELOC_6, R_SH_LAST_INVALID_RELOC_6): New.  Adjust
+	other invalid ranges.
+	(R_SH_GOT20, R_SH_GOTOFF20, R_SH_GOTFUNCDESC, R_SH_GOTFUNCDESC20)
+	(R_SH_GOTOFFFUNCDESC, R_SH_GOTOFFFUNCDESC20, R_SH_FUNCDESC)
+	(R_SH_FUNCDESC_VALUE): New.
+
+2010-05-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/11600
+	* common.h (SHF_EXCLUDE): New.
+
+	* i370.h (SHF_EXCLUDE): Removed.
+	* or32.h (SHF_EXCLUDE): Likewise.
+	* ppc.h (SHF_EXCLUDE): Likewise.
+	* sparc.h (SHF_EXCLUDE): Likewise.
+
+2010-04-23  Alan Modra  <amodra@gmail.com>
+
+	* internal.h (ELF_SECTION_SIZE): Protect macro args with parentheses.
+	Invert logic to clarify test for .tbss.
+	(ELF_IS_SECTION_IN_SEGMENT): Rename to..
+	(ELF_SECTION_IN_SEGMENT_1): ..this.  Add check_vma param.  Protect
+	macro args with parentheses.
+	(ELF_SECTION_IN_SEGMENT): Define.
+	(ELF_IS_SECTION_IN_SEGMENT_FILE): Delete.
+	(ELF_IS_SECTION_IN_SEGMENT_MEMORY): Delete.
+
+2010-04-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+	* arm.h (Tag_FP_arch, Tag_ABI_align_needed, Tag_ABI_align_preserved,
+	Tag_FP_HP_extension): Add new ABI attribute tags.
+
+2010-04-15  Nick Clifton  <nickc@redhat.com>
+
+	* alpha.h: Update copyright notice to use GPLv3.
+	* arc.h: Likewise.
+	* arm.h: Likewise.
+	* avr.h: Likewise.
+	* bfin.h: Likewise.
+	* common.h: Likewise.
+	* cr16.h: Likewise.
+	* cr16c.h: Likewise.
+	* cris.h: Likewise.
+	* crx.h: Likewise.
+	* d10v.h: Likewise.
+	* d30v.h: Likewise.
+	* dlx.h: Likewise.
+	* dwarf.h: Likewise.
+	* external.h: Likewise.
+	* fr30.h: Likewise.
+	* frv.h: Likewise.
+	* h8.h: Likewise.
+	* hppa.h: Likewise.
+	* i370.h: Likewise.
+	* i386.h: Likewise.
+	* i860.h: Likewise.
+	* i960.h: Likewise.
+	* ia64.h: Likewise.
+	* internal.h: Likewise.
+	* ip2k.h: Likewise.
+	* iq2000.h: Likewise.
+	* lm32.h: Likewise.
+	* m32c.h: Likewise.
+	* m32r.h: Likewise.
+	* m68hc11.h: Likewise.
+	* m68k.h: Likewise.
+	* mcore.h: Likewise.
+	* mep.h: Likewise.
+	* microblaze.h: Likewise.
+	* mips.h: Likewise.
+	* mmix.h: Likewise.
+	* mn10200.h: Likewise.
+	* moxie.h: Likewise.
+	* msp430.h: Likewise.
+	* mt.h: Likewise.
+	* openrisc.h: Likewise.
+	* or32.h: Likewise.
+	* pj.h: Likewise.
+	* ppc.h: Likewise.
+	* ppc64.h: Likewise.
+	* reloc-macros.h: Likewise.
+	* rx.h: Likewise.
+	* s390.h: Likewise.
+	* sh.h: Likewise.
+	* sparc.h: Likewise.
+	* spu.h: Likewise.
+	* v850.h: Likewise.
+	* vax.h: Likewise.
+	* vxworks.h: Likewise.
+	* x86-64.h: Likewise.
+	* xc16x.h: Likewise.
+	* xstormy16.h: Likewise.
+	* xtensa.h: Likewise.
+
+2010-04-08  David Stubbs  <stubbs@icerasemi.com>
+
+	* internal.h (ELF_IS_SECTION_IN_SEGMENT): PT_PHDR program headers
+	cannot contain any sections.
+
+2010-03-25  Joseph Myers  <joseph@codesourcery.com>
+
+	* common.h (ELFOSABI_C6000_ELFABI, ELFOSABI_C6000_LINUX): Define.
+	* tic6x.h: New.
+
+2010-03-05  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+	* common.h (VER_FLG_*): Document.
+	(VER_FLG_INFO): Define.
+
+2010-02-23  Andrew Zabolotny  <anpaza@mail.ru>
+
+	PR binutils/11297
+	* avr.h: (R_AVR_8): New relocation number.
+
+2010-02-18  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+	* arm.h (Tag_MPextension_use): Renumber.
+	(Tag_DIV_use): Add.
+	(Tag_MPextension_use_legacy): Likewise.
+
+2010-02-09  Michael Holzheu  <holzheu@de.ibm.com>
+
+	* common.h (NT_S390_TIMER, NT_S390_TODCMP, NT_S390_TODPREG,
+	NT_S390_CTRS and NT_S390_PREFIX): Define.
+
+2010-02-08  David S. Miller  <davem@davemloft.net>
+
+	* sparc.h (R_SPARC_JMP_IREL, R_SPARC_IRELATIVE): Define.
+
+2010-02-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* common.h (NT_386_XSTATE): New.
+
+2010-01-21  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* s390.h (EF_S390_HIGH_GPRS): Added macro definition.
+
+2010-01-19  Daisuke Hatayama  <d.hatayama@jp.fujitsu.com>
+
+	* common.h (PN_XNUM): Define.
+
+2009-12-18  Ulrich Weigand  <uweigand@de.ibm.com>
+
+	* common.h (NT_S390_HIGH_GPRS): Define.
+
+2009-12-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (R_PPC_RELAX32, R_PPC_RELAX32PC, R_PPC_RELAX32_PLT,
+	R_PPC_RELAX32PC_PLT): Delete.
+	(R_PPC_RELAX, R_PPC_RELAX_PLT, R_PPC_RELAX_PLTREL24): Define.
+
+2009-12-03  David Daney  <ddaney@caviumnetworks.com>
+	    Adam Nemet  <adambnemet@gmail.com>
+
+	* mips.h (E_MIPS_MACH_OCTEON2): New machine flag.
+
+2009-11-28  Joseph Myers  <joseph@codesourcery.com>
+
+	* common.h (ELFOSABI_FENIXOS, EM_TI_C6000, EM_TI_C2000,
+	EM_TI_C5500, EM_CUDA): Define.
+	(EM_res140, EM_res141, EM_res142): Remove.
+
+2009-11-17  Paul Brook  <paul@codesourcery.com>
+	Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* arm.h (TAG_CPU_ARCH_V7E_M): Define.
+
+2009-09-29  DJ Delorie  <dj@redhat.com>
+
+	* rx.h: New file.
+
+2009-09-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (DT_PPC_TLSOPT): Define.
+	* ppc64.h (DT_PPC64_TLSOPT): Define.
+
+2009-08-10  Daniel Gutson  <dgutson@codesourcery.com>
+
+	* arm.h: (SHT_ARM_DEBUGOVERLAY): New define.
+	(SHT_ARM_OVERLAYSECTION): New define.
+
+2006-08-09  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	From Mike Frysinger <michael.frysinger@analog.com>
+	* bfin.h (R_BFIN_UNUSED, R_BFIN_PCREL5M2, R_BFIN_UNUSED1,
+	R_BFIN_PCREL10, R_BFIN_PCREL12_JUMP, R_BFIN_RIMM16,
+	R_BFIN_LUIMM16, R_BFIN_HUIMM16, R_BFIN_PCREL12_JUMP_S,
+	R_BFIN_PCREL24_JUMP_X, R_BFIN_PCREL24, R_BFIN_UNUSEDB,
+	R_BFIN_UNUSEDC, R_BFIN_PCREL24_JUMP_L, R_BFIN_PCREL24_CALL_X,
+	R_BFIN_VAR_EQ_SYMB, R_BFIN_BYTE_DATA, R_BFIN_BYTE2_DATA,
+	R_BFIN_BYTE4_DATA, R_BFIN_PCREL11, R_BFIN_PUSH, R_BFIN_CONST,
+	R_BFIN_ADD, R_BFIN_SUB, R_BFIN_MULT, R_BFIN_DIV, R_BFIN_MOD,
+	R_BFIN_LSHIFT, R_BFIN_RSHIFT, R_BFIN_AND, R_BFIN_OR, R_BFIN_XOR,
+	R_BFIN_LAND, R_BFIN_LOR, R_BFIN_LEN, R_BFIN_NEG, R_BFIN_COMP,
+	R_BFIN_PAGE, R_BFIN_HWPAGE, R_BFIN_ADDR, R_BFIN_PLTPLC,
+	R_BFIN_GOT, R_BFIN_MAX): Renamed from R_unused0, R_pcrel5ms,
+	R_unused1, R_pcrel10, R_pcrel12_jump, R_rimm16, R_luimm16,
+	R_huimm16, R_pcrel12_jump_s, R_pcrel24_jump_x, R_pcrel24,
+	R_unusedb, R_unusedc, R_pcrel24_jump_l, R_pcrel24_call_x,
+	R_var_eq_symb, R_byte_data, R_byte2_data, R_byte4_data, R_pcrel11,
+	R_push, R_const, R_add, R_sub, R_mult, R_div, R_mod, R_lshift,
+	R_rshift, R_and, R_or, R_xor, R_land, R_lor, R_len, R_neg, R_comp,
+	R_page, R_hwpage, R_addr, R_pltpc, R_got.
+
+2009-08-09  Michael Eager <eager@eagercon.com>
+
+	* elf/common.h: Define EM_resnnn reserved values. Add EM_AVR32,
+	EM_STM8, EM_TILE64, EM_TILEPRO.  Change EM_MICROBLAZE.
+
+2009-08-06  Michael Eager <eager@eagercon.com>
+
+	* elf/common.h: Define EM_MICROBLAZE & EM_MICROBLAZE_OLD.
+	* elf/microblaze.h: New reloc definitions.
+
+2009-07-30  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc64.h: Add R_PPC64_JMP_IREL, R_PPC64_REL16, R_PPC64_REL16_LO,
+	R_PPC64_REL16_HI, R_PPC64_REL16_HA.
+
+2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* common.h (EM_L1OM): New.
+
+2009-07-24  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* spu.h (R_SPU_ADD_PIC): New.
+
+2009-07-23  Ulrich Drepper  <drepper@redhat.com>
+
+	* common.h (STB_GNU_UNIQUE): Define.
+
+2009-07-10  Tom Tromey  <tromey@redhat.com>
+
+	* dwarf2.h: Move to `..'.
+
+2009-07-10  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* dwarf2.h: Just include ../dwarf2.h.
+
+2009-07-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (R_PPC_IRELATIVE): Add.
+	(R_PPC_RELAX32, R_PPC_RELAX32PC,
+	R_PPC_RELAX32_PLT, R_PPC_RELAX32PC_PLT): Renumber.
+	* ppc64.h (R_PPC64_IRELATIVE): Add.
+
+2009-07-03  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2.h (enum dwarf_location_atom): Add DW_OP_implicit_value
+	and DW_OP_stack_value.
+
+2009-06-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (R_PPC_RELAX*): Define as enum.
+
+2009-06-11  Anthony Green  <green@moxielogic.org>
+
+	* moxie.h (R_MOXIE_PCREL10): New.
+
+2009-06-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/10205
+	* i386.h (R_386_IRELATIVE): New.
+	* x86-64.h (R_X86_64_IRELATIVE): Likewise.
+
+2009-05-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* common.h: Update comments for dynamic tag ranges.
+
+2009-04-30  DJ Delorie  <dj@redhat.com>
+
+	* mep.h (EF_MEP_COP_*): New.
+	(EF_MEP_ALL_FLAGS): Add them.
+
+2009-04-30  Nick Clifton  <nickc@redhat.com>
+
+	* common.h (STT_GNU_IFUNC): Define.
+
+2009-04-24  Cary Coutant  <ccoutant@google.com>
+
+	 * dwarf2.h (DW_LNE_set_discriminator): New enum value.
+
+2009-04-15  Anthony Green  <green@moxielogic.com>
+
+	* common.h (EM_MOXIE): Define.
+	* moxie.h: New file.
+
+2009-04-07  DJ Delorie  <dj@redhat.com>
+
+	* mep.h (EF_MEP_CPU_C5): New.
+
+2009-04-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* common.h (EM_INTEL178): Removed.
+	(EM_INTEL179): Likewise.
+	(EM_ETPU): New.
+	(EM_SLE9X): Likewise.
+	(EM_INTEL181): Likewise.
+	(EM_INTEL182): Likewise.
+
+2009-03-31  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* common.h (EM_INTEL178): New.
+	(EM_INTEL179): Likewise.
+	(EM_INTEL180): Likewise.
+
+2009-03-20  Mikolaj Zalewski  <mikolajz@google.com>
+
+	* common.h (SHT_GNU_INCREMENTAL_INPUTS): Define.
+
+2009-03-14  Mark Kettenis  <kettenis@gnu.org>
+
+	* common.h (NT_OPENBSD_PROCINFO, NT_OPENBSD_AUXV)
+	(NT_OPENBSD_REGS, NT_OPENBSD_FPREGS, NT_OPENBSD_XFPREGS)
+	(NT_OPENBSD_WCOOKIE): New defines.
+
+2009-03-16  Jan Kratochvil  <jan.kratochvil@redhat.com>
+
+	* common.h (AT_RANDOM): Define.
+
+2009-03-04  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (R_PPC_TLSGD, R_PPC_TLSLD): Add new relocs.
+	* ppc64.h (R_PPC64_TLSGD, R_PPC64_TLSLD): Add new relocs.
+
+2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
+
+	* score.h (RELOC_NUMBER): Add R_SCORE_IMM32.
+	* common.h (EM_SCORE_OLD): Define.
+
+2009-02-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* common.h (STB_LOPROC): Replace Application-specific with
+	Processor-specific in comments.
+	(STB_HIPROC): Likewise.
+	(STT_LOPROC): Likewise.
+	(STT_HIPROC): Likewise.
+
+2009-02-03  Sandip Matte  <sandip@rmicorp.com>
+
+	* mips.h (E_MIPS_MACH_XLR): Define.
+
+2009-02-03  Maxim Kuvyrkov  <maxim@codesourcery.com>
+
+	* m68k.h: Map TLS relocations to numbers.
+
+2009-01-15  Andrew Stubbs  <ams@codesourcery.com>
+	    Julian Brown   <julian@codesourcery.com>
+
+	* arm.h (TAG_CPU_ARCH_V6_M, TAG_CPU_ARCH_V6S_M): New defines.
+	(MAX_TAG_CPU_ARCH, TAG_CPU_ARCH_V4T_PLUS_V6_M): New defines.
+	(Tag_NEON_arch): Rename to Tag_Advanced_SIMD_arch to match ARM ABI
+	version 2.07.
+	(Tag_undefined39, Tag_nodefaults): New enum values.
+	(Tag_also_compatible_with, Tag_T2EE_use): Likewise.
+	(Tag_conformance, Tag_Virtualization_use): Likewise.
+	(Tag_undefined69, Tag_MPextension_use): Likewise.
+
+2009-01-15  Douglas B Rupp  <rupp@gnat.com>
+
+	* ia64.h (SHT_IA_64_VMS_DISPLAY_NAME_INFO, EF_IA_64_ARCHVER_1):
+	New macros. Minor reformatting.
+
+2008-12-23  Jon Beniston <jon@beniston.com>
+
+	* lm32.h: New file.
+
+2008-12-23  Nick Clifton  <nickc@redhat.com>
+
+	* commmon.h (STT_IFUNC): Delete.
+
+2008-12-20  Hans-Peter Nilsson  <hp@axis.com>
+
+	* cris.h (R_CRIS_32_IE): New relocation.
+
+2008-12-03  Nick Clifton  <nickc@redhat.com>
+
+	* common.h (STT_IFUNC): Define.
+
+2008-11-27  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+	* cr16.h (R_CR16_GOT_REGREL20, R_CR16_GOTC_REGREL20 and
+	R_CR16_GLOB_DAT): New relocations.
+
+2008-11-25  Hans-Peter Nilsson  <hp@axis.com>
+
+	* cris.h (R_CRIS_32_TPREL): Correct comment.
+	(R_CRIS_DTPMOD): Open up for use elsewhere than the fourth GOT entry.
+
+2008-11-18  Catherine Moore  <clm@codesourcery.com>
+
+	* arm.h (Tag_ABI_FP_16bit_format): Define.
+
+2008-11-14  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* internal.h (struct elf_segment_map): Add header_size field.
+
+2008-10-13  Ulrich Weigand  <uweigand@de.ibm.com>
+
+	* common.h (AT_BASE_PLATFORM, AT_EXECFN): Define.
+
+2008-10-10  Nathan Froyd  <froydnj@codesourcery.com>
+
+	* ppc.h: Add Tag_GNU_Power_ABI_Struct_Return.
+
+2008-10-04  Hans-Peter Nilsson  <hp@axis.com>
+
+	* cris.h (R_CRIS_32_GOT_GD, R_CRIS_16_GOT_GD, R_CRIS_32_GD)
+	(R_CRIS_DTP, R_CRIS_32_DTPREL, R_CRIS_16_DTPREL, R_CRIS_DTPMOD)
+	(R_CRIS_32_GOT_TPREL, R_CRIS_16_GOT_TPREL, R_CRIS_32_TPREL)
+	(R_CRIS_16_TPREL): New relocations.
+
+2008-08-20  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa.h (R_XTENSA_TLSDESC_FN, R_XTENSA_TLSDESC_ARG)
+	(R_XTENSA_TLS_DTPOFF, R_XTENSA_TLS_TPOFF, R_XTENSA_TLS_FUNC)
+	(R_XTENSA_TLS_ARG, R_XTENSA_TLS_CALL): New.
+
+2008-08-08  Richard Sandiford  <rdsandiford@googlemail.com>
+	    Daniel Jacobowitz  <dan@codesourcery.com>
+	    Catherine Moore  <clm@codesourcery.com>
+	    Mark Shinwell  <shinwell@codesourcery.com>
+
+	* mips.h (STO_MIPS_PLT, ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT)
+	(STO_MIPS_PIC, DT_MIPS_PLTGOT, DT_MIPS_RWPLT): New macros.
+
+2008-08-04  Markus Weiss  <weissms@aros.org>
+
+	* common.h (ELFOSABI_AROS): Update comment.
+
+2008-07-26  Michael Eager <eager@eagercon.com>
+
+	* ppc.h: Add description of single-precision.
+
+2008-07-21  Luis Machado  <luisgpm@br.ibm.com>
+
+	* common.h: Define NT_PPC_VSX.
+
+2008-07-10  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h (ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): New macros.
+
+2008-06-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+	* common.h (EM_CR16): Correct value.
+	(EM_CR16): Rename to EM_CR16_OLD.
+
+2008-06-12  DJ Delorie  <dj@redhat.com>
+
+	* common.h (EM_M32C_NEW): Rename to EM_M32C.
+	(EM_M32C): Rename to EM_M32C_OLD.
+
+2008-06-12  Joseph Myers  <joseph@codesourcery.com>
+
+	* common.h: Update e_machine table.
+
+2008-06-09  Takashi Yoshii  <yoshii.takashi@renesas.com>
+
+	* sh.h (EF_SH_BFD_TABLE): Set bfd_mach_sh for EF_SH_UNKNOWN.
+
+2008-06-09  Joseph Myers  <joseph@codesourcery.com>
+
+	* common.h: Change registry@caldera.com to registry@sco.com.
+
+2008-05-21  Nick Clifton  <nickc@redhat.com>
+
+	* reloc-macros.h: Add a comment about the use of the
+	END_RELOC_NUMBERS symbol as a sentinel value.
+
+2008-05-15  Christophe Lyon  <christophe.lyon@st.com>
+
+	* arm.h (END_RELOC_NUMBERS): Provide a maximum value.
+
+2008-04-16  David S. Miller  <davem@davemloft.net>
+
+	* elf/sparc.h (R_SPARC_GOTDATA_HIX22,
+	R_SPARC_GOTDATA_LOX10, R_SPARC_GOTDATA_OP_HIX22,
+	R_SPARC_GOTDATA_OP_LOX10, R_SPARC_GOTDATA_OP,
+	R_SPARC_H34, R_SPARC_SIZE32, R_SPARC_SIZE64): New relocs.
+
+2008-03-24  Ian Lance Taylor  <iant@google.com>
+
+	* common.h (NT_GNU_GOLD_VERSION): Define.
+
+2008-03-13  Alan Modra  <amodra@bigpond.net.au>
+
+	* internal.h (Elf_Internal_Shdr): Change sh_link and sh_info from
+	unsigned long to unsigned int.  Change sh_addralign to bfd_vma.
+	Order struct as for external version.
+
+2008-03-12  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 5900
+	* common.h (SHN_BAD): Delete.
+	(SHN_LORESERVE .. SHN_HIRESERVE): Move to..
+	* external.h: ..here.
+	* internal.h (SHN_LORESERVE, SHN_HIRESERVE): Define.
+	(SHN_LOPROC, SHN_HIPROC, SHN_LOOS, SHN_HIOS): Define.
+	(SHN_ABS, SHN_COMMON, SHN_XINDEX, SHN_BAD): Define.
+
+2008-03-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* cr16c.h (SHN_CR16C_FCOMMON): Define using SHN_LORESERVE.
+	(SHN_CR16C_NCOMMON): Likewise.
+	* hppa.h (SHN_PARISC_ANSI_COMMON): Likewise.
+	(SHN_PARISC_HUGE_COMMON): Likewise.
+	* ia64.h (SHN_IA_64_ANSI_COMMON): Likewise.
+	(SHN_IA_64_VMS_SYMVEC): Define using SHN_LOOS.
+	* m32r.h (SHN_M32R_SCOMMON): Define using SHN_LORESERVE.
+	* mips.h (SHN_MIPS_ACOMMON, SHN_MIPS_TEXT): Likewise.
+	(SHN_MIPS_DATA, SHN_MIPS_SCOMMON, SHN_MIPS_SUNDEFINED): Likewise.
+	* score.h (SHN_SCORE_TEXT, SHN_SCORE_DATA): Likewise.
+	(SHN_SCORE_SCOMMON): Likewise.
+	* sparc.h (SHN_BEFORE, SHN_AFTER): Likewise.
+	* v850.h (SHN_V850_SCOMMON, SHN_V850_TCOMMON): Likewise.
+	(SHN_V850_ZCOMMON): Likewise.
+	* x86-64.h (SHN_X86_64_LCOMMON): Likewise.
+
+2008-03-03  Pallavi Tambay  <pallavi.tambay@amd.com>
+
+	* dwarf2.h: (enum dwarf_location_atom): Add new DW_OP:
+	DW_OP_PGI_omp_thread_num.
+
+2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
+
+	* mips.h: Update copyright.
+	(E_MIPS_MACH_OCTEON): New macro.
+
+2008-01-30  Tristan Gingold  <gingold@adacore.com>
+
+	Add OpenVMS extensions.
+	* ia64.h (SHF_IA_64_VMS_GLOBAL, SHF_IA_64_VMS_OVERLAID)
+	(SHF_IA_64_VMS_SHARED, SHF_IA_64_VMS_VECTOR)
+	(SHF_IA_64_VMS_ALLOC_64BIT, SHF_IA_64_VMS_PROTECTED)
+	(SHT_IA_64_VMS_TRACE, SHT_IA_64_VMS_TIE_SIGNATURES)
+	(SHT_IA_64_VMS_DEBUG, SHT_IA_64_VMS_DEBUG_STR)
+	(SHT_IA_64_VMS_LINKAGES, SHT_IA_64_VMS_SYMBOL_VECTOR)
+	(SHT_IA_64_VMS_FIXUP, DT_IA_64_VMS_SUBTYPE)
+	(DT_IA_64_VMS_IMGIOCNT, DT_IA_64_VMS_LNKFLAGS)
+	(DT_IA_64_VMS_VIR_MEM_BLK_SIZ, DT_IA_64_VMS_IDENT)
+	(DT_IA_64_VMS_NEEDED_IDENT, DT_IA_64_VMS_IMG_RELA_CNT)
+	(DT_IA_64_VMS_SEG_RELA_CNT, DT_IA_64_VMS_FIXUP_RELA_CNT)
+	(DT_IA_64_VMS_FIXUP_NEEDED, DT_IA_64_VMS_SYMVEC_CNT)
+	(DT_IA_64_VMS_XLATED, DT_IA_64_VMS_STACKSIZE)
+	(DT_IA_64_VMS_UNWINDSZ, DT_IA_64_VMS_UNWIND_CODSEG)
+	(DT_IA_64_VMS_UNWIND_INFOSEG, DT_IA_64_VMS_LINKTIME)
+	(DT_IA_64_VMS_SEG_NO, DT_IA_64_VMS_SYMVEC_OFFSET)
+	(DT_IA_64_VMS_SYMVEC_SEG, DT_IA_64_VMS_UNWIND_OFFSET)
+	(DT_IA_64_VMS_UNWIND_SEG, DT_IA_64_VMS_STRTAB_OFFSET)
+	(DT_IA_64_VMS_SYSVER_OFFSET, DT_IA_64_VMS_IMG_RELA_OFF)
+	(DT_IA_64_VMS_SEG_RELA_OFF, DT_IA_64_VMS_FIXUP_RELA_OFF)
+	(DT_IA_64_VMS_PLTGOT_OFFSET, DT_IA_64_VMS_PLTGOT_SEG)
+	(DT_IA_64_VMS_FPMODE, SHN_IA_64_VMS_SYMVEC): Define
+
+2008-01-16  Mark Kettenis  <kettenis@gnu.org>
+
+	* common.h (AT_SUN_AUXFLAGS): Define.
+
+2007-12-11  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* dwarf2.h (DW_AT_hi_user): Correct value.
+
+2007-12-07  Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa.h (R_XTENSA_32_PCREL): New.
+
+2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* mips.h (E_MIPS_MACH_LS2E): New.
+	(E_MIPS_MACH_LS2F): New.
+
+2007-11-28  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* internal.h (ELF_IS_SECTION_IN_SEGMENT): Adjust to cope with
+	segments at the end of memory.
+
+2007-11-17  Thiemo Seufer  <ths@mips.com>
+
+	* mips.h (Tag_GNU_MIPS_ABI_FP): Mention -mips32r2 -mfp64 variant
+	in comment.
+
+2007-11-16  Nick Clifton  <nickc@redhat.com>
+
+	* dwarf2.h: Mention the location of the DWARF3 spec on the web.
+	(DW_AT_stride_size): Rename to DW_AT_bit_stride.
+	(DW_AT_stride): Rename to DW_AT_byte_stride.
+
+2007-11-08  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* vxworks.h: New.
+
+2007-10-30  Nick Clifton  <nickc@redhat.com>
+
+	* mn10300.h (R_MN10300_ALIGN): Define.
+
+2007-10-25  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ppc.h (Tag_GNU_Power_ABI_Vector): New.
+
+2007-10-19  Nick Clifton  <nickc@redhat.com>
+
+	* mn10300.h: Add R_MN10300_SYM_DIFF reloc.
+
+2007-10-18  Roland McGrath  <roland@redhat.com>
+
+	* common.h (NT_PPC_VMX): New macro.
+
+2007-10-01  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+	* cr16.h: Updated with new relocaction macros.
+
+2007-09-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/3281
+	PR binutils/5037
+	* internal.h (elf_segment_map): Add p_size and p_size_valid.
+	(ELF_IS_SECTION_IN_SEGMENT): Allow SHF_TLS sections in
+	PT_GNU_RELRO segments.
+
+2007-09-11  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* m68k.h (EF_M68K_CF_ISA_C_NODIV): New.
+
+2007-08-25  Ulrich Weigand  <uweigand@de.ibm.com>
+
+	* common.h (NT_SPU): Define.
+
+2007-08-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* common.h: Revert last change.
+
+2007-08-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* common.h (PT_GNU_STACK): Renamed to ...
+	(PT_GNU_ATTR): This.
+	(PT_GNU_STACK): New.  Make an alias of PT_GNU_ATTR.
+
+2007-07-09  Roland McGrath  <roland@redhat.com>
+
+	* common.h (NT_GNU_HWCAP, NT_GNU_BUILD_ID): New macros.
+
+2007-06-29  Joseph Myers  <joseph@codesourcery.com>
+
+	* ppc.h (Tag_GNU_Power_ABI_FP): Define.
+
+2007-06-29  Joseph Myers  <joseph@codesourcery.com>
+
+	* mips.h (Tag_GNU_MIPS_ABI_FP): Define.
+
+2007-06-29  Joseph Myers  <joseph@codesourcery.com>
+
+	* arm.h (elf32_arm_add_eabi_attr_int,
+	elf32_arm_add_eabi_attr_string, elf32_arm_add_eabi_attr_compat,
+	elf32_arm_get_eabi_attr_int, elf32_arm_set_eabi_attr_contents,
+	elf32_arm_eabi_attr_size, Tag_NULL, Tag_File, Tag_Section,
+	Tag_Symbol, Tag_compatibility): Remove.
+	* common.h (SHT_GNU_ATTRIBUTES): Define.
+
+2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
+
+	* common.h (EM_CR16): New entry for CR16 cpu.
+	* cr16.h: New file.
+
+2007-06-11  Sterling Augustine  <sterling@tensilica.com>
+	    Bob Wilson  <bob.wilson@acm.org>
+
+	* xtensa.h (XTENSA_PROP_INSN_NO_TRANSFORM): Renamed to...
+	(XTENSA_PROP_NO_TRANSFORM): ...this.
+
+2007-05-18  Caroline Tice  <ctice@apple.com>
+
+	* dwarf2.h: (enum dwarf_location_atom): Add new DW_OP,
+	DW_OP_GNU_uninit.
+
+2007-05-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* spu.h (R_SPU_ADDR16X): Define.
+	(R_SPU_PPU32, R_SPU_PPU64): Renumber.
+
+2007-05-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* spu.h (R_SPU_PPU32, R_SPU_PPU64): Define.
+
+2007-05-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* internal.h (ELF_IS_SECTION_IN_SEGMENT): Check both file offset
+	and vma for appropriate sections.
+
+2007-04-26  Jan Beulich  <jbeulich@novell.com>
+
+	* common.h (DT_ENCODING): Correct value (back to spec mandated
+	value).
+
+2007-03-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* v850.h (V850_OTHER_TDA_BYTE): Delete.
+	(V850_OTHER_SDA, V850_OTHER_ZDA, V850_OTHER_TDA): Assign bits
+	that don't clash with visibility bits.
+
+2007-03-07  Alan Modra  <amodra@bigpond.net.au>
+
+	* common.h (ELF_ST_VISIBILITY): Comment typo fix.
+
+2007-02-05  Dave Brolley  <brolley@redhat.com>
+	    Richard Sandiford  <rsandifo@redhat.com>
+	    Richard Henderson  <rth@redhat.com>
+	    DJ Delorie  <dj@redhat.com>
+	    Ben Elliston  <bje@redhat.com>
+
+	* mep.h: New file.
+	* common.h (EM_CYGNUS_MEP): Define.
+
+2007-02-15  Dave Brolley  <brolley@redhat.com>
+
+	From Graydon Hoare  <graydon@redhat.com>:
+	* common.h (STT_RELC, STT_SRELC, R_RELC): New macros.
+
+2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
+
+	* m68k.h (EF_M68K_FIDO): New.
+	(EF_M68K_ARCH_MASK): OR EF_M68K_FIDO.
+	(EF_M68K_CPU32_FIDO_A, EF_M68K_CPU32_MASK): Remove.
+
+2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
+
+	* m68k.h (EF_M68K_CPU32_FIDO_A, EF_M68K_CPU32_MASK): New.
+
+2006-12-19  Kazu Hirata  <kazu@codesourcery.com>
+
+	* m68k.h (EF_M68K_ARCH_MASK): New.
+
+2006-12-19  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* internal.h (struct elf_segment_map): Add p_vaddr_offset field.
+
+2006-12-07  Kazu Hirata  <kazu@codesourcery.com>
+
+	* m68k.h (EF_M68K_ISA_MASK, EF_M68K_ISA_A_NODIV,
+	EF_M68K_ISA_A, EF_M68K_ISA_A_PLUS, EF_M68K_ISA_B_NOUSP,
+	EF_M68K_ISA_B, EF_M68K_ISA_C, EF_M68K_MAC_MASK, EF_M68K_MAC,
+	EF_M68K_EMAC, EF_M68K_EMAC_B, EF_M68K_FLOAT): Rename to
+	EF_M68K_CF_ISA_MASK, EF_M68K_CF_ISA_A_NODIV, EF_M68K_CF_ISA_A,
+	EF_M68K_CF_ISA_A_PLUS, EF_M68K_CF_ISA_B_NOUSP,
+	EF_M68K_CF_ISA_B, EF_M68K_CF_ISA_C, EF_M68K_CF_MAC_MASK,
+	EF_M68K_CF_MAC, EF_M68K_CF_EMAC, EF_M68K_CF_EMAC_B,
+	EF_M68K_CF_FLOAT, respectively.
+
+2006-12-05  Michael Tautschnig  <tautschn@model.in.tum.de>
+	    Nick Clifton  <nickc@redhat.com>
+
+	* external.h (struct Elf_External_Versym): Use ATTRIBUTE_PACKED.
+
+2006-10-28  Richard Sandiford  <richard@codesourcery.com>
+
+	* mips.h (R_MIPS_GLOB_DAT): Define
+	(R_MIPS_max): Bump by 1.
+
+2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
+	    Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
+	    Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
+	    Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* common.h (EM_SPU): Define.
+	* spu.h: New file.
+
+2006-10-19  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* score.h (EF_SCORE_PIC): Redefine EF_SCORE_PIC as 0x80000000.
+	(EF_SCORE_FIXDEP): Redefine EF_SCORE_FIXDEP as 0x40000000.
+	(EF_SCORE_HASENTRY): Delete.
+
+2006-10-17  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* arm.h: Define TAG_CPU_ARCH_* constants.
+
+2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* score.h: New file.
+	* common.h: Add Score machine number.
+
+2006-07-10  Jakub Jelinek  <jakub@redhat.com>
+
+	* common.h (SHT_GNU_HASH, DT_GNU_HASH): Define.
+
+2006-05-31  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* internal.h (ELF_SECTION_SIZE): New.
+	(ELF_IS_SECTION_IN_SEGMENT): Likewise.
+	(ELF_IS_SECTION_IN_SEGMENT_FILE): Updated.
+	(ELF_IS_SECTION_IN_SEGMENT_MEMORY): Likewise.
+
+2006-05-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* internal.h (struct elf_segment_map): Add p_align and p_align_valid.
+
+2006-05-24  Carlos O'Donell  <carlos@systemhalted.org>
+	    Randolph Chung  <randolph@tausq.org>
+	* hppa.h (R_PARISC_TLS_GD21L, R_PARISC_TLS_GD14R, R_PARISC_TLS_GDCALL,
+	R_PARISC_TLS_LDM21L, R_PARISC_TLS_LDM14R, R_PARISC_TLS_LDMCALL,
+	R_PARISC_TLS_LDO21L, R_PARISC_TLS_LDO14R, R_PARISC_TLS_DTPMOD32,
+	R_PARISC_TLS_DTPMOD64, R_PARISC_TLS_DTPOFF32, R_PARISC_TLS_DTPOFF64):
+	New TLS relocs.
+	(R_PARISC_TLS_LE21L, R_PARISC_TLS_LE14R, R_PARISC_TLS_IE21L,
+	R_PARISC_TLS_IE14R, R_PARISC_TLS_TPREL32, R_PARISC_TLS_TPREL64):
+	Define TLS relocs using existing equivalents.
+
+2006-05-24  Bjoern Haase  <bjoern.m.haase@web.de>
+
+	* avr.h: Add E_AVR_MACH_AVR6, R_AVR_LO8_LDI_GS and R_AVR_HI8_LDI_GS.
+
+2006-03-25  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* bfin.h (R_BFIN_GOT17M4, R_BFIN_GOTHI, R_BFIN_GOTLO,
+	R_BFIN_FUNCDESC, R_BFIN_FUNCDESC_GOT17M4,  R_BFIN_FUNCDESC_GOTHI,
+	R_BFIN_FUNCDESC_GOTLO, R_BFIN_FUNCDESC_VALUE,
+	R_BFIN_FUNCDESC_GOTOFF17M4, R_BFIN_FUNCDESC_GOTOFFHI,
+	R_BFIN_FUNCDESC_GOTOFFLO, R_BFIN_GOTOFF17M4, R_BFIN_GOTOFFHI,
+	R_BFIN_GOTOFFLO): New relocs.
+	(EF_BFIN_PIC, EF_BFIN_FDPIC, EF_BFIN_PIC_FLAGS): New macros.
+
+2006-03-23  Michael Matz  <matz@suse.de>
+
+	* x86-64.h: Add the new relocations with their official
+	numbers.
+
+2006-03-22  Richard Sandiford  <richard@codesourcery.com>
+	    Daniel Jacobowitz  <dan@codesourcery.com>
+	    Phil Edwards  <phil@codesourcery.com>
+	    Zack Weinberg  <zack@codesourcery.com>
+	    Mark Mitchell  <mark@codesourcery.com>
+	    Nathan Sidwell  <nathan@codesourcery.com>
+
+	* mips.h (R_MIPS_COPY, R_MIPS_JUMP_SLOT): New relocs.
+
+2006-03-19  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* hppa.h (SHF_HP_TLS, SHF_HP_NEAR_SHARED, SHF_HP_FAR_SHARED,
+	SHF_HP_COMDAT, SHF_HP_CONST, SHN_TLS_COMMON, SHN_NS_COMMON,
+	SHN_NS_UNDEF, SHN_FS_UNDEF, SHN_HP_EXTERN, SHN_HP_EXTHINT,
+	SHN_HP_UNDEF_BIND_IMM, SHT_HP_OVLBITS, SHT_HP_DLKM, SHT_HP_COMDAT,
+	SHT_HP_OBJDICT, SHT_HP_ANNOT, STB_HP_ALIAS): Define.
+
+2006-03-10  Paul Brook  <paul@codesourcery.com>
+
+	* arm.h (EF_ARM_EABI_VER5): Define.
+
+2006-03-06  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* m68k.h (EF_M68K_ISA_MASK, EF_M68K_ISA_A,
+	EF_M68K_ISA_A_PLUS, EF_M68K_ISA_B, EF_M68K_ISA_C): Adjust.
+	(EF_M68K_ISA_A_NODIV, EF_M68K_ISA_B_NOUSP): New.
+	(EF_M68K_HW_DIV, EF_M68K_USP): Remove.
+	(EF_M68K_MAC, EF_M68K_EMAC, EF_M68K_FLOAT): Adjust.
+	(EF_M68K_EMAC_B): New.
+
+2006-03-03  Bjoern Haase  <bjoern.m.haase@web.de>
+
+	* avr.h (R_AVR_MS8_LDI,R_AVR_MS8_LDI_NEG): Add.
+	(EF_AVR_LINKRELAX_PREPARED): Add.
+
+2006-03-02  Ben Elliston  <bje@au.ibm.com>
+
+	Import from the GCC tree:
+	2006-03-01  Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2.h (DW_TAG_condition, DW_TAG_shared_type): New constants
+	from DWARF 3.
+	(DW_AT_description, DW_AT_binary_scale, DW_AT_decimal_scale,
+	DW_AT_small, DW_AT_decimal_sign, DW_AT_digit_count,
+	DW_AT_picture_string, DW_AT_mutable, DW_AT_threads_scaled,
+	DW_AT_explicit, DW_AT_object_pointer, DW_AT_endianity,
+	DW_AT_elemental, DW_AT_pure, DW_AT_recursive): New.
+	(DW_OP_form_tls_address, DW_OP_call_frame_cfa, DW_OP_bit_piece): New.
+	(DW_ATE_packed_decimal, DW_ATE_numeric_string, DW_ATE_edited,
+	DW_ATE_signed_fixed, DW_ATE_unsigned_fixed): New.
+	(DW_DS_unsigned, DW_DS_leading_overpunch, DW_DS_trailing_overpunch,
+	DW_DS_leading_separate, DW_DS_trailing_separate): New.
+	(DW_END_default, DW_END_big, DW_END_little): New.
+	(DW_END_lo_user, DW_END_hi_user): Define.
+	(DW_LNE_lo_user, DW_LNE_hi_user): Define.
+	(DW_CFA_val_offset, DW_CFA_val_offset_sf, DW_CFA_val_expression): New.
+	(DW_LANG_PLI, DW_LANG_ObjC, DW_LANG_ObjC_plus_plus, DW_LANG_UPC,
+	DW_LANG_D): New.
+
+2006-02-06  Steve Ellcey  <sje@cup.hp.com>
+
+	* ia64.h (SHF_IA_64_HP_TLS): New.
+
+2006-02-24  DJ Delorie  <dj@redhat.com>
+
+	* m32c.h: Add relax relocs.
+
+2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
+            Anil Paranjape   <anilp1@kpitcummins.com>
+            Shilin Shakti    <shilins@kpitcummins.com>
+
+	* common.h (EM_XC16X): New entry for xc16x cpu.
+	Sort other EM_* numbers into numerical order.
+	* xc16x.h: New file.
+
+2006-02-10  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/2258
+	* internal.h (ELF_IS_SECTION_IN_SEGMENT_FILE): New.
+	(ELF_IS_SECTION_IN_SEGMENT_MEMORY): Likewise.
+
+2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* m68k.h (EF_CPU32, EF_M68000, EF_CFV4E): Rename to ...
+	(EF_M68K_CPU32, EF_M68K_M68000, EF_M68K_CFV4E): ... here.
+	(EF_M68K_ISA_MASK, EF_M68K_ISA_A, EF_M68K_M68K_ISA_A_PLUS,
+	EF_M68K_ISA_B, EF_M68K_HW_DIV, EF_M68K_MAC_MASK, EF_M68K_MAC,
+	EF_M68K_EMAC, EF_M68K_USP, EF_M68K_FLOAT): New.
+
+2006-02-06  Steve Ellcey  <sje@cup.hp.com>
+
+	* ia64.h (SHF_IA_64_HP_TLS): New.
+
+2006-01-18  Alexandre Oliva  <aoliva@redhat.com>
+
+	Introduce TLS descriptors for i386 and x86_64.
+	* common.h (DT_TLSDESC_GOT, DT_TLSDESC_PLT): New.
+	* i386.h (R_386_TLS_GOTDESC, R_386_TLS_DESC_CALL, R_386_TLS_DESC):
+	New.
+	* x86-64.h (R_X86_64_GOTPC32_TLSDESC, R_X86_64_TLSDESC_CALL,
+	R_X86_64_TLSDESC): New.
+
+2006-01-09  Mike Frysinger  <vapier@gentoo.org>:
+
+	* common.h (EM_ALTERA_NIOS2, EM_NIOS32) Define.
+
+2005-12-16  Nathan Sidwell  <nathan@codesourcery.com>
+
+	Second part of ms1 to mt renaming.
+	* common.h (EM_MT): Renamed.
+	* mt.h: Rename relocs, cpu & other defines.
+
+2005-12-12  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* mt.h: Renamed from ms1.h
+
+2005-12-12  Paul Brook  <paul@codesourcery.com>
+
+	* arm.h (elf32_arm_get_eabi_attr_int): Add prototype.
+
+2005-11-11  Nick Clifton  <nickc@redhat.com>
+
+	PR 1150
+	* mips.h (STO_OPTIONAL): Define.
+	(ELF_MIPS_IS_OPTIONAL): Define.
+
+2005-11-07  Nathan Sidwell  <nathan@codesourcery.com>
+
+	Add ms2.
+	* ms1.h (EF_MS1_CPU_MS2): New.
+
+2005-11-06  John David Anglin  <dave.anglin@nrc-crnc.gc.ca>
+
+	* hppa.h (R_PARISC_DIR64WR, R_PARISC_DIR64DR): Remove relocs.
+
+2005-09-30  Catherine Moore  <clm@cm00re.com>
+
+	* bfin.h: New file.
+	* common.h (EM_BLACKFIN): Define.
+
+2005-10-08  Paul Brook  <paul@codesourcery.com>
+
+	* arm.h: Add prototypes for BFD object attribute routines.
+
+2005-09-09  Richard Earnshaw  <richard.earnshaw@arm.com>
+
+	* arm.h (SHT_ARM_PREEMPTMAP, SHT_ARM_ATTRIBUTES): New defines.
+
+2005-08-09  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* hppa.h (SHT_PARISC_DLKM, SHF_PARISC_WEAKORDER, PT_PARISC_WEAKORDER):
+	New defines.
+
+2005-08-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* hppa.h (PF_HP_CODE, PF_HP_MODIFY, PF_HP_LAZYSWAP): Revise defines.
+	(PF_HP_CODE_DEPR, PF_HP_MODIFY_DEPR, PF_HP_LAZYSWAP_DEPR): New
+	deprecated defines.
+	(DT_HP_EPLTREL, DT_HP_EPLTRELSZ, DT_HP_FILTERED, DT_HP_FILTER_TLS,
+	DT_HP_COMPAT_FILTERED, DT_HP_LAZYLOAD, DT_HP_BIND_NOW_COUNT, DT_PLT,
+	DT_PLT_SIZE, DT_DLT, DT_DLT_SIZE, DT_HP_BIND_DEPTH_FIRST, DT_HP_GST,
+	DT_HP_SHLIB_FIXED, DT_HP_MERGE_SHLIB_SEG, DT_HP_NODELETE, DT_HP_GROUP,
+	DT_HP_PROTECT_LINKAGE_TABLE, PT_HP_OPT_ANNOT, PT_HP_HSL_ANNOT,
+	PT_HP_STACK, PT_HP_CORE_UTSNAME, NT_HP_COMPILER, NT_HP_COPYRIGHT,
+	NT_HP_VERSION, NT_HP_SRCFILE_INFO, NT_HP_LINKER, NT_HP_INSTRUMENTED,
+	NT_HP_UX_OPTIONS): Define.
+
+2005-07-25  DJ Delorie  <dj@redhat.com>
+
+	* m32c.h: Add R_M32C_8, R_M32C_LO16, R_M32C_HI8, and R_M32C_HI16.
+
+2005-07-25  Jan Hubicka  <jh@suse.cz>
+
+	* x86-64.h (SHN_X86_64_LCOMMON): New.
+	(SHF_X86_64_LARGE): New.
+
+2005-07-20  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* m32r.h (R_M32R_REL32): Added.
+
+2005-07-18  Ben Elliston  <bje@au.ibm.com>
+
+	* dwarf2.h (enum dwarf_type): Remove DW_AT_GNU_decimal_float.
+	Replace with DW_ATE_decimal_float (now in DWARF 3).
+
+2005-07-14  Jim Blandy  <jimb@redhat.com>
+
+	Add support for Renesas M32C and M16C.
+	* common.h (EM_M32C): New machine number.
+	* m32c.h: New file.
+
+2005-06-17  Jakub Jelinek  <jakub@redhat.com>
+
+	* external.h (GRP_ENTRY_SIZE): Define.
+
+2005-06-17  Jan Beulich  <jbeulich@novell.com>
+
+	* x86-64.h (elf_x86_64_reloc_type): Adjust comment for
+	R_X86_64_GOTPCREL. Add R_X86_64_PC64, R_X86_64_GOTOFF64, and
+	R_X86_64_GOTPC32.
+
+2005-06-07  Aldy Hernandez  <aldyh@redhat.com>
+	    Michael Snyder  <msnyder@redhat.com>
+	    Stan Cox  <scox@redhat.com>
+
+	* common.h (EM_MS1): Define.
+
+	* ms1.h: New file.
+
+2005-05-31  Richard Henderson  <rth@redhat.com>
+
+	* alpha.h (LITUSE_ALPHA_JSRDIRECT): New.
+
+2005-05-29  Richard Henderson  <rth@redhat.com>
+
+	* alpha.h (DT_ALPHA_PLTRO): New.
+
+2005-05-19  Ben Elliston  <bje@au.ibm.com>
+
+	* dwarf2.h (enum dwarf_type): Assign DW_ATE_GNU_decimal_float from
+	the user-defined encoding space pending inclusion in the standard.
+
+2005-05-18  Zack Weinberg  <zack@codesourcery.com>
+
+	* arm.h: Make all #ifndef OLD_ARM_ABI blocks
+	unconditional, delete all #ifdef OLD_ARM_ABI blocks.
+
+2005-05-17  Zack Weinberg  <zack@codesourcery.com>
+
+	* arm.h: Import complete list of official relocation names
+	and numbers from AAELF.  Define FAKE_RELOCs for old names.
+	Remove a few old names no longer used anywhere.
+
+2005-05-14  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (DT_PPC_GOT): Rename from DT_PPC_GLINK.
+
+2005-05-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (R_PPC_RELAX32, R_PPC_RELAX32PC, R_PPC_RELAX32_PLT,
+	R_PPC_RELAX32PC_PLT) Adjust.
+	(R_PPC_REL16, R_PPC_REL16_LO, R_PPC_REL16_HI, R_PPC_REL16_HA): Define.
+	(DT_PPC_GLINK): Define.
+
+2005-05-10  Nick Clifton  <nickc@redhat.com>
+
+	* Update the address and phone number of the FSF organization in
+	the GPL notices in the following files:
+	alpha.h, arc.h, arm.h, avr.h, common.h, cr16c.h, cris.h, crx.h,
+	d10v.h, d30v.h, dlx.h, dwarf.h, dwarf2.h, external.h, fr30.h,
+	frv.h, h8.h, hppa.h, i370.h, i386.h, i860.h, i960.h, ia64.h,
+	internal.h, ip2k.h, iq2000.h, m32r.h, m68hc11.h, m68k.h, mcore.h,
+	mips.h, mmix.h, mn10200.h, mn10300.h, msp430.h, openrisc.h,
+	or32.h, pj.h, ppc.h, ppc64.h, reloc-macros.h, s390.h, sh.h,
+	sparc.h, v850.h,  vax.h, x86-64.h, xstormy16.h,	xtensa.h
+
+2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	Moved from ../ChangeLog
+
+	2004-10-27  Richard Earnshaw  <rearnsha@arm.com>
+	* arm.h: Add R_ARM_CALL and R_ARM_JUMP32.
+
+	2004-10-12  Paul Brook  <paul@codesourcery.com>
+	* arm.h (EF_ARM_EABI_VER4): Define.
+
+	2004-10-08  Daniel Jacobowitz  <dan@debian.org>
+
+	* common.h (PT_SUNW_EH_FRAME): Define.
+	* x86-64.h (SHT_X86_64_UNWIND): Define.
+
+	2004-10-07  Bob Wilson  <bob.wilson@acm.org>
+	* xtensa.h (R_XTENSA_DIFF8, R_XTENSA_DIFF16, R_XTENSA_DIFF32,
+	R_XTENSA_SLOT*_OP, R_XTENSA_SLOT*_ALT): New relocations.
+	(XTENSA_PROP_SEC_NAME): Define.
+	(property_table_entry): Add flags field.
+	(XTENSA_PROP_*, GET_XTENSA_PROP_*, SET_XTENSA_PROP_*): Define.
+
+	2004-09-17  Paul Brook  <paul@codesourcery.com>
+	* arm.h: Remove R_ARM_STKCHK and R_ARM_THM_STKCHK.
+	Add R_ARM_TARGET2, R_ARM_PREL31, R_ARM_GOT_ABS, R_ARM_GOT_PREL,
+	R_ARM_GOT_BREL12, R_ARM_GOTOFF12 and R_ARM_GOTRELAX.
+
+	2004-09-13  Paul Brook  <paul@codesourcery.com>
+	* arm.h: Rename RELABS to TARGET1.
+
+	2004-05-11  Jakub Jelinek  <jakub@redhat.com>
+	* common.h (PT_GNU_EH_FRAME, PT_GNU_STACK): Add comments.
+	(PT_GNU_RELRO): Define.
+
+2005-03-29  Daniel Jacobowitz  <dan@codesourcery.com>
+	    Phil Blundell  <philb@gnu.org>
+
+	* arm.h: Add TLS relocations.
+
+2005-03-23  Ben Elliston  <bje@au.ibm.com>
+
+	* dwarf.h: Merge with GCC's dwarf.h.
+
+2005-03-18  C Jaipraash  <cjaiprakash@noida.hcltech.com>
+
+	* m68k.h (EF_CFV4E): Define.
+
+2005-03-17  Paul Brook <paul@codesourcery.com>
+	    Dan Jacobowitz <dan@codesourcery.com>
+	    Mark Mitchell  <mark@codesourcery.com>
+
+	* arm.h (PT_ARM_EXIDX): Define.
+
+2005-03-02  Daniel Jacobowitz  <dan@codesourcery.com>
+	    Joseph Myers  <joseph@codesourcery.com>
+
+	* mips.h: Define MIPS TLS relocations.
+
+2005-02-15  Nigel Stephens  <nigel@mips.com>
+	    Maciej W. Rozycki  <macro@mips.com>
+
+	* mips.h (R_MIPS16_GOT16): New reloc code.
+	(R_MIPS16_CALL16): Likewise.
+	(R_MIPS16_HI16): Likewise.
+	(R_MIPS16_LO16): Likewise.
+	(R_MIPS16_min): New fake reloc code.
+	(R_MIPS16_max): Likewise.
+
+2005-02-11  Maciej W. Rozycki  <macro@mips.com>
+
+	* mips.h (R_MIPS_max): Use FAKE_RELOC to define.
+
+2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
+
+	2004-12-10  Alexandre Oliva  <aoliva@redhat.com>
+	* frv.h: Add R_FRV_TLSMOFF.
+	2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
+	* frv.h: Add TLS relocations.
+
+2005-01-17  Nick Clifton  <nickc@redhat.com>
+
+	* sh.h (EF_SH2A_SH4_NOFPU, EF_SH2A_SH3_NOFPU, EF_SH2A_SH4,
+	EF_SH2A_SH3E): New flags.
+	(EF_SH_BFD_TABLE): Add these new flags to the table.
+
+2005-01-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (R_PPC_RELAX32_PLT, R_PPC_RELAX32PC_PLT): Define.
+	(R_PPC_RELAX32, R_PPC_RELAX32PC): Adjust value.
+
+2004-12-22  Klaus Rudolph  <lts-rudolph@gmx.de>
+
+	* avr.h (R_AVR_LDI, R_AVR_6, R_AVR_6_ADIW): New relocs.
+
+2004-12-16  Richard Sandiford  <rsandifo@redhat.com>
+
+	* v850.h (R_V850_LO16_SPLIT_OFFSET): New reloc.
+
+2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
+
+	* mips.h (E_MIPS_MACH_9000): Define.
+
+2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
+
+	* cris.h (EF_CRIS_VARIANT_MASK, EF_CRIS_VARIANT_ANY_V0_V10)
+	(EF_CRIS_VARIANT_V32, EF_CRIS_VARIANT_COMMON_V10_V32): New
+	macros.
+
+2004-10-06  Eric Christopher  <echristo@redhat.com>
+
+	* dwarf2.h: Sync with gcc dwarf2.h. Fix typo.
+
+2004-10-01  Paul Brook  <paul@codesourcery.com>
+
+	* arm.h (SHT_ARM_EXIDX): Define.
+	(ELF_STRING_ARM_unwind, ELF_STRING_ARM_unwind,
+	ELF_STRING_ARM_unwind_once, ELF_STRING_ARM_unwind_info_once):
+	Define.
+
+2004-08-25  Dmitry Diky  <diwil@spec.ru>
+
+	* msp430.h: Add new relocs.
+
+2004-08-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386.h (R_386_USED_BY_INTEL_200): New.
+
+2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
+
+	Introduce SH2a support.
+	2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
+	* sh.h (EF_SH2A_NOFPU): New.
+	2003-12-01  Michael Snyder  <msnyder@redhat.com>
+	* sh.h (EF_SH2A): New.
+
+2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* crx.h: Add BFD_RELOC_CRX_SWITCH8, BFD_RELOC_CRX_SWITCH16,
+	BFD_RELOC_CRX_SWITCH32.
+
+2004-07-06  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* common.h (EM_CRX): Define.
+	* crx.h: New file.
+
+2004-06-25  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* m32r.h: Add defintions of R_M32R_GOTOFF_HI_ULO,
+	R_M32R_GOTOFF_HI_SLO and R_M32R_GOTOFF_LO.
+
+2004-06-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* common.h (ELF64_R_INFO): Warning fix.
+
+2004-06-14  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h (R_MIPS_PC32): Add back (undoing removal on 2004-04-24),
+	with an updated comment.
+
+2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
+
+	* sh.h (EF_SH_HAS_DSP): Remove.
+	(EF_SH_HAS_FP): Remove.
+	(EF_SH_MERGE_MACH): Remove.
+	(EF_SH4_NOFPU): Convert to decimal.
+	(EF_SH4A_NOFPU): Likewise.
+	(EF_SH4_NOMMU_NOFPU): Likewise.
+	(EF_SH3_NOMMU): Add new macro.
+	(EF_SH_BFD_TABLE): Likewise.
+	(sh_find_elf_flags): Add prototype.
+	(sh_elf_get_flags_from_mach): Likewise.
+
+2004-04-24  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h (R_MIPS_PC32, R_MIPS_PC64, R_MIPS_GNU_REL_LO16)
+	(R_MIPS_GNU_REL_HI16): Remove.
+	(R_MIPS_GNU_REL16_S2): Update comment.
+
+2004-30-30  Galit Heller  <Galit.Heller@nsc.com>
+	    Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* common.h (EM_CR): Define.
+	* cr16c.h: New file.
+
+2004-03-23  Paul Brook  <paul@codesourcery.com>
+
+	* arm.h (EF_ERM_BE8, EF_ARM_LE8, EF_ARM_EABI_VER3): Add.
+
+2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
+
+	* sh.h: Add EF_SH4_NOMMU_NOFPU.
+
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
+	* frv.h (EF_FRV_CPU_FR405, EF_FRV_CPU_FR450): Define.
+
+2004-01-28  Roland McGrath  <roland@redhat.com>
+
+	* common.h (AT_SECURE): New macro.
+
+2004-01-21  Roland McGrath  <roland@redhat.com>
+
+	* common.h (AT_SUN_UID, AT_SUN_RUID, AT_SUN_GID): New macros.
+	(AT_SUN_RGID, AT_SUN_LDELF, AT_SUN_LDSHDR, AT_SUN_LDNAME,
+	AT_SUN_LPAGESZ, AT_SUN_PLATFORM, AT_SUN_HWCAP, AT_SUN_IFLUSH,
+	AT_SUN_CPU, AT_SUN_EMUL_ENTRY, AT_SUN_EMUL_EXECFD,
+	AT_SUN_EXECNAME) AT_SUN_MMU, AT_SUN_LDDATA): Likewise.
+
+2004-01-17  Mark Kettenis  <kettenis@gnu.org>
+
+	* common.h (NT_OPENBSD_IDENT): Define.
+
+2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
+
+	2003-09-18  Alexandre Oliva  <aoliva@redhat.com>
+	* frv.h (EF_FRV_FDPIC): New macro.
+	(EF_FRV_PIC_FLAGS): Adjust.
+	2003-08-08  Alexandre Oliva  <aoliva@redhat.com>
+	* frv.h (R_FRV_FUNCDESC_VALUE, R_FRV_FUNCDESC_GOTOFF12,
+	R_FRV_FUNCDESC_GOTOFFLO, R_FRV_FUNCDESC_GOTOFFHI, R_FRV_GOTOFF12,
+	R_FRV_GOTOFFLO, R_FRV_GOTOFFHI): New.
+	2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
+	* frv.h (R_FRV_GOT12, R_FRV_GOTHI, R_FRV_GOTLO, R_FRV_FUNCDESC,
+	R_FRV_FUNCDESC_GOT12, R_FRV_FUNCDESC_GOTHI, R_FRV_FUNCDESC_GOTLO):
+	New.
+
+
+For older changes see ChangeLog-9103
+
+Copyright (C) 2004-2012 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.25/include/elf/ChangeLog-9103 b/binutils-2.25/include/elf/ChangeLog-9103
new file mode 100644
index 00000000..6746d0aa
--- /dev/null
+++ b/binutils-2.25/include/elf/ChangeLog-9103
@@ -0,0 +1,1957 @@
+2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	Moved from ../ChangeLog
+
+	2003-10-14  Bob Wilson  <bob.wilson@acm.org>
+	* xtensa.h: Formatting.  Fix comments about property section
+	names for linkonce sections.
+
+	2003-05-23  Jakub Jelinek  <jakub@redhat.com>
+	* common.h (PT_GNU_STACK): Define.
+
+	2003-01-25  Jakub Jelinek  <jakub@redhat.com>
+	* sparc.h: Add TLS relocs.  Move R_SPARC_REV32 to 252.
+
+	2002-09-26  Jakub Jelinek  <jakub@redhat.com>
+	* x86-64.h: Add TLS relocs.
+
+	2002-09-19  Jakub Jelinek  <jakub@redhat.com>
+	* i386.h (R_386_TLS_TPOFF, R_386_TLS_IE, R_386_TLS_GOTIE):
+	Define.
+
+	2002-07-10  Jakub Jelinek  <jakub@redhat.com>
+	* common.h (SHT_GNU_LIBLIST, DT_GNU_PRELINKED,
+	DT_GNU_CONFLICT*, DT_GNU_LIBLIST*): Define.
+
+	2002-05-31  Michal Ludvig  <mludvig@suse.cz>
+	* dwarf2.h (DW_CFA_low_user, DW_CFA_high_user): Renamed
+	to DW_CFA_lo_user, DW_CFA_hi_user respectively.
+
+	2002-05-23  Jakub Jelinek  <jakub@redhat.com>
+	* common.h (PT_TLS, SHF_TLS, STT_TLS, DF_STATIC_TLS): Define.
+	* ia64.h (R_IA64_LTOFF_TPREL22): Renamed from R_IA64_LTOFF_TP22.
+	* i386.h: Add TLS relocs.
+
+2003-12-19  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* m32r.h : Added m32r-linux and PIC support.  Add new ABI that
+	uses RELA.
+	(R_M32R_16_RELA, R_M32R_32_RELA, R_M32R_24_RELA,
+	R_M32R_10_PCREL_RELA, R_M32R_18_PCREL_RELA,
+	R_M32R_26_PCREL_RELA, R_M32R_HI16_ULO_RELA,
+	R_M32R_HI16_SLO_RELA, R_M32R_LO16_RELA,
+	R_M32R_SDA16_RELA, R_M32R_RELA_GNU_VTINHERIT,
+	R_M32R_RELA_GNU_VTENTRY, R_M32R_GOT24,
+	R_M32R_26_PLTREL, R_M32R_COPY, R_M32R_GLOB_DAT,
+	R_M32R_JMP_SLOT, R_M32R_RELATIVE, R_M32R_GOTOFF,
+	R_M32R_GOTPC24, R_M32R_GOT16_HI_ULO,
+	R_M32R_GOT16_HI_SLO, R_M32R_GOT16_LO,
+	R_M32R_GOTPC_HI_ULO, R_M32R_GOTPC_HI_SLO,
+	R_M32R_GOTPC_LO): New relocs.
+
+2003-12-06  Alan Modra  <amodra@bigpond.net.au>
+
+	From Jan Beulich <JBeulich@novell.com>
+	* common.h (DT_HIOS): Correct value.
+
+2003-12-03   Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* m32r.h: Add new machine type m32r2 and instruction modes.
+
+2003-11-06  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (R_PPC_RELAX32PC): Define.
+
+2003-10-22  Alexandre Oliva  <aoliva@redhat.com>,
+	    Michael Snyder  <msnyder@redhat.com>
+
+	* sh.h (EF_SH4A, EF_SH4AL_DSP, EF_SH4_NOFPU, EF_SH4A_NOFPU): New.
+	(EF_SH_MERGE_MACH): Combine them.
+
+2003-10-18  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* mmix.h (R_MMIX_PUSHJ_STUBBABLE): New reloc number.
+	(_bfd_mmix_before_linker_allocation): Rename from
+	_bfd_mmix_prepare_linker_allocated_gregs.
+	(_bfd_mmix_after_linker_allocation): Rename from
+	_bfd_mmix_finalize_linker_allocated_gregs.
+
+2003-10-06  Dave Brolley  <brolley@redhat.com>
+
+	* frv.h (EF_FRV_CPU_FR550): New macro.
+
+2003-09-30  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h (E_MIPS_ARCH_64R2): New define.
+
+2003-09-23  DJ Delorie  <dj@redhat.com>
+
+	* sh.h (R_SH_SWITCH8, R_SH_GNU_VTINHERIT, R_SH_GNU_VTENTRY,
+	R_SH_LOOP_START,R_SH_LOOP_END): Move to "reserved" spaces.
+	(R_SH_DIR16, R_SH_DIR8, R_SH_DIR8UL, R_SH_DIR8UW, R_SH_DIR8U,
+	R_SH_DIR8SW, R_SH_DIR8S, R_SH_DIR4UL, R_SH_DIR4UW, R_SH_DIR4U,
+	R_SH_PSHA, R_SH_PSHL): New.
+
+2003-09-11  James Cownie <jcownie@etnus.com>
+
+	* dwarf2.h: Add HP dwarf extensions from their hacked gdb
+	header files (ftp://ftp.hp.com/pub/lang/tools/WDB/wdb-4.0.tar.gz).
+
+2003-09-04  Nick Clifton  <nickc@redhat.com>
+
+	* v850.h (E_V850E1_ARCH): Define.
+
+2003-08-21  James Cownie <jcownie@etnus.com>
+
+	* dwarf2.h: Add PGI dwarf extensions.
+
+2003-08-08 Dmitry Diky <diwil@mail.ru>
+
+	* msp430.h: Add xW42 and xE42 parts. Sort MPU list according to
+	gcc order.
+
+2003-08-07  Alan Modra  <amodra@bigpond.net.au>
+
+	* reloc-macros.h (START_RELOC_NUMBERS) : Remove PARAMS macro.  Use
+	C90 function definition.  Formatting.
+	(RELOC_NUMBER): Remove !__STDC__ code.
+
+2003-07-28  Eric Christopher  <echristo@redhat.com>
+
+	* ppc.h (R_PPC_RELAX32): New. Fake relocation.
+
+2003-07-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* v850.h (SHF_V850_GPREL): New.
+	(SHF_V850_EPREL): Likewise.
+	(SHF_V850_R0REL): Likewise.
+
+2003-07-09  Alexandre Oliva  <aoliva@redhat.com>
+
+	2001-05-16  Alexandre Oliva  <aoliva@redhat.com>
+	* mn10300.h: Introduce GOTPC16, GOTOFF24, GOTOFF16 and
+	PLT16, and rename GOTPC to GOTPC32 and GOTOFF to GOTOFF32.
+	Renumbered all relocs.
+	2001-04-12  Alexandre Oliva  <aoliva@redhat.com>
+	* mn10300.h (R_MN10300_GOTPC, R_MN10300_GOTOFF,
+	R_MN10300_PLT32, R_MN10300_GOT32, R_MN10300_GOT24,
+	R_MN10300_GOT16, R_MN10300_COPY, R_MN10300_GLOB_DAT,
+	R_MN10300_JMP_SLOT, R_MN10300_RELATIVE): New relocs.
+
+2003-07-09  Alexandre Oliva  <aoliva@redhat.com>
+
+	2000-04-01  Alexandre Oliva  <aoliva@cygnus.com>
+	* mn10300.h (E_MN10300_MACH_AM33_2): Renamed from
+	E_MN10300_MACH_AM332.
+	2000-03-31  Alexandre Oliva  <aoliva@cygnus.com>
+	* mn10300.h (E_MN10300_MACH_AM332): Defined.
+
+2003-07-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* s390.h (elf_s390_reloc_type): Add long displacement relocations
+	R_390_20, R_390_GOT20, R_390_GOTPLT20 and R_390_TLS_GOTIE20.
+
+2003-06-29  Andreas Jaeger  <aj@suse.de>
+
+	* mmix.h: Convert to ISO C90 prototypes.
+	* mips.h: Likewise.
+
+2003-06-13  Robert Millan <zeratul2@wanadoo.es>
+
+	* common.h (GNU_ABI_TAG_NETBSD): New tag.
+	(GNU_ABI_TAG_FREEBSD): New tag.
+
+2003-06-10  Richard Sandiford  <rsandifo@redhat.com>
+
+	* h8.h (E_H8_MACH_H8300SXN): New flag.
+
+2003-06-03  Nick Clifton  <nickc@redhat.com>
+
+	* v850.h (R_V850_32): Rename to R_V850_ABS32.
+	Add R_V850_REL32.
+
+2003-05-15  Roland McGrath  <roland@redhat.com>
+
+	* common.h (NT_AUXV, AT_*): New macros.
+	* external.h (Elf32_External_Auxv, Elf64_External_Auxv): New types.
+	* internal.h (Elf_Internal_Auxv): New type.
+
+2003-05-14  Michael Snyder  <msnyder@redhat.com>
+	From  Bernd Schmidt  <bernds@redhat.com>
+	* h8.h (E_H8_MACH_H8300SX): New.
+
+2003-04-24 Dhananjay Deshpande <dhananjayd@kpitcummins.com>
+
+	* h8.h (E_H8_MACH_H8300HN, E_H8_MACH_H8300SN): New
+
+2003-04-23  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* common.h (EM_SH): Amend comment to refer to SuperH.
+
+2003-04-22  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* common.h: Replace references to Mitsubishi M32R with
+	references to Renesas M32R.
+
+2003-04-15  Rohit Kumar Srivastava <rohits@kpitcummins.com>
+
+	* common.h: Replace occurrances of 'Hitachi' with 'Renesas'.
+
+2003-04-01  Bob Wilson  <bob.wilson@acm.org>
+
+	* common.h (EM_XTENSA_OLD): Define.
+	* xtensa.h: New file.
+
+2003-04-01  Nick Clifton  <nickc@redhat.com>
+
+	* arm.h (ARM_NOTE_SECTION): Include .gnu in the string.
+
+2003-03-25  Stan Cox   <scox@redhat.com>
+	    Nick Clifton  <nickc@redhat.com>
+
+	Contribute support for Intel's iWMMXt chip - an	ARM variant:
+
+	* arm.h (ARM_NOTE_SECTION): Define.
+
+2003-03-03  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* sh.h (EF_SH_MERGE_MACH): Make sure SH2E & SH3/SH3E merge to SH3E,
+	and SH2E & SH4 merge to SH4, not SH2E.
+
+2003-02-21  Ian Wienand  <ianw@gelato.unsw.edu.au>
+
+	* ia64.h (SHT_IA_64_LOPSREG, SHT_IA_64_HIPSREG,
+	SHT_IA_64_PRIORITY_INIT): Define.
+
+2003-02-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc64.h (IS_PPC64_TLS_RELOC): Rename from IS_TLS_RELOC.
+
+	* ppc.h: Replace DTPMOD64, TPREL64, DTPREL64 with DTPMOD32 etc.
+	(IS_PPC_TLS_RELOC): Define.
+
+2003-02-10  Nick Clifton  <nickc@redhat.com>
+
+	* arm.h (EF_ARM_MAVERICK_FLOAT): Define.
+
+2003-02-05  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h: Add TLS relocs.  Format.
+	* ppc64.h: Likewise.
+
+2003-01-27  Alexandre Oliva  <aoliva@redhat.com>
+
+	* mips.h (EF_MIPS_XGOT): Define.
+
+2003-01-24  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* s390.h: Add s390 TLS relocations.
+
+2003-01-23  Nick Clifton  <nickc@redhat.com>
+
+	* Add sh2e support:
+
+	2002-04-02  Alexandre Oliva  <aoliva@redhat.com>
+
+		* sh.h (EF_SH_MERGE_MACH): Handle SH2E.
+
+	2002-04-02  Elena Zannoni  <ezannoni@redhat.com>
+
+		* sh.h (EF_SH2E): New.
+
+2003-01-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* sh.h: Split out various bits to bfd/elf32-sh64.h.
+
+2003-01-20  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* s390.h: Rename R_390_GOTOFF to R_390_GOTOFF32. Add new gotoff,
+	gotplt and pltoff relocations.
+
+2003-01-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* common.h: Formatting, typo fixes.
+	(DT_ENCODING): Correct value.
+
+2003-01-17  Fabio Alemagna  <falemagn@aros.org>
+
+	* common.h (ELFOSABI_AROS): Define.
+	(ELFOSABI_OPENVMS): Likewise.
+	(ELFOSABI_NSK): Likewise.
+
+2003-01-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h: Split out ppc64 definitions to..
+	* pcc64.h: ..here.  New file.
+	(R_PPC64_REL30): Rename from R_PPC64_ADDR30.
+
+2003-01-13 Dmitry Diky <diwil@mail.ru>
+
+	* elf/common.h (EM_MSP430): Change e_machine value to officially
+	assigned.
+
+2003-01-02  Ben Elliston  <bje@redhat.com>
+
+	* common.h (EM_IQ2000): Define.
+	* iq2000.h: New file.
+
+2002-12-30  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h (E_MIPS_ARCH_32R2): New define.
+
+2002-12-24    Dmitry Diky <diwil@mail.ru>
+
+	* common.h: Define msp430 machine numbers.
+	* msp430.h: New file.  Define msp430 relocs.
+
+2002-12-20  DJ Delorie  <dj@redhat.com>
+
+	* xstormy16.h: Add XSTORMY16_12.
+
+2002-12-16  Andrew MacLeod  <amacleod@redhat.com>
+
+	* xstormy16.h (START_RELOC_NUMBERS) Add relocation numbers
+	for R_XSTORMY16_LO16 and R_XSTORMY16_HI16.
+
+2002-12-10  James Cownie <jcownie@etnus.com>
+
+	* dwarf2.h (DW_TAG_upc_shared_type, DW_TAG_upc_strict_type,
+	DW_TAG_upc_relaxed_type, DW_AT_upc_threads_scaled, DW_LANG_Upc):
+	Define.
+
+2002-12-01  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* m68hc11.h (EF_M68HC12_MACH, EF_M68HCS12_MACH): Define.
+	(EF_M68HC11_MACH_MASK, EF_M68HC11_MACH): Define.
+	(EF_M68HC11_MERGE_MACH, EF_M68HC11_CAN_MERGE_MACH): Define.
+
+2002-11-30  Alan Modra  <amodra@bigpond.net.au>
+
+	* mmix.h: Replace boolean with bfd_boolean.
+	* sh.h: Likewise.
+
+2002-11-28  Alan Modra  <amodra@bigpond.net.au>
+
+	* internal.h (elf32_internal_ehdr, Elf32_Internal_Ehdr,
+	elf64_internal_ehdr, Elf64_Internal_Ehdr, elf32_internal_phdr,
+	Elf32_Internal_Phdr, elf64_internal_phdr, Elf64_Internal_Phdr,
+	elf32_internal_shdr, Elf32_Internal_Shdr, elf64_internal_shdr,
+	Elf64_Internal_Shdr, elf32_internal_sym, elf64_internal_sym,
+	Elf32_Internal_Sym, Elf64_Internal_Sym, Elf32_Internal_Note,
+	elf32_internal_note, elf32_internal_rel, Elf32_Internal_Rel,
+	elf64_internal_rel, Elf64_Internal_Rel, elf32_internal_rela,
+	elf64_internal_rela, Elf32_Internal_Rela, Elf64_Internal_Rela,
+	elf32_internal_dyn, elf64_internal_dyn, Elf32_Internal_Dyn,
+	Elf64_Internal_Dyn, elf32_internal_verdef, elf64_internal_verdef,
+	elf32_internal_verdaux, elf64_internal_verdaux, elf32_internal_verneed,
+	elf64_internal_verneed, elf32_internal_vernaux, elf64_internal_vernaux,
+	elf32_internal_versym, elf64_internal_versym, Elf32_Internal_Verdef,
+	Elf64_Internal_Verdef, Elf32_Internal_Verdaux, Elf64_Internal_Verdaux,
+	Elf32_Internal_Verneed, Elf64_Internal_Verneed, Elf32_Internal_Vernaux,
+	Elf64_Internal_Vernaux, Elf32_Internal_Versym, Elf64_Internal_Versym,
+	Elf32_Internal_Syminfo, Elf64_Internal_Syminfo): Delete.
+	(Elf_Internal_Rel): Delete.
+
+2002-10-11  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* sh.h: Add SH TLS relocs.
+
+2002-09-30  Gavin Romig-Koch  <gavin@redhat.com>
+	    Ken Raeburn  <raeburn@cygnus.com>
+	    Aldy Hernandez  <aldyh@redhat.com>
+	    Eric Christopher  <echristo@redhat.com>
+	    Richard Sandiford  <rsandifo@redhat.com>
+
+	* mips.h (E_MIPS_MACH_4120, E_MIPS_MACH_5400, E_MIPS_MACH_5500): New.
+
+2002-09-12  Roland McGrath  <roland@redhat.com>
+
+	* dwarf2.h: Updates from GCC version of thie file:
+	(enum dwarf_location_atom): DW_OP_calli -> DW_OP_call_ref.
+	Add DW_OP_GNU_push_tls_address.
+	(DW_OP_lo_user): Change to 0xe0.
+
+2002-08-28  Catherine Moore  <clm@redhat.com>
+
+	* v850.h (R_V850_LONGCALL, R_V850_ALIGN,
+	R_V850_LONGJUMP): New relocations.
+
+2002-08-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* i370.h: Define relocs using reloc-macros.h.
+
+2002-08-13  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* m68hc11.h (E_M68HC12_BANKS, E_M68HC11_I32, E_M68HC11_F64,
+	EF_M68HC11_ABI): Define for ABI specification.
+	(STO_M68HC12_FAR, STO_M68HC12_INTERRUPT): Symbol flags for
+	linker and debugger.
+	(R_M68HC11_24, R_M68HC11_LO16, R_M68HC11_PAGE): New relocs.
+	(R_M68HC11_RL_JUMP, R_M68HC11_RL_GROUP): New reloc for linker
+	relaxation.
+
+2002-07-15  Denis Chertykov  <denisc@overta.ru>
+	    Frank Ch. Eigler  <fche@redhat.com>
+	    Ben Elliston  <bje@redhat.com>
+	    Alan Lehotsky  <alehotsky@cygnus.com>
+	    John Healy  <jhealy@redhat.com>
+	    Graham Stott  <grahams@redhat.com>
+	    Jeff Johnston  <jjohnstn@redhat.com>
+
+	* common.h (EM_IP2K): New macro.
+	(EM_IP2K_OLD): New macro.
+	* ip2k.h: New file.
+
+2002-07-01  Matt Thomas  <matt@3am-software.com>
+
+	* vax.h: Rename EF_* to EF_VAX_*.
+
+2002-06-18  Dave Brolley  <brolley@redhat.com>
+
+	From Catherine Moore, Michael Meissner, Dave Brolley:
+	* common.h (EM_CYGNUS_FRV): New macro.
+	* frv.h: New file.
+
+2002-06-06  Lars Brinkhoff  <lars@nocrew.org>
+
+	* common.h: Change registry@sco.com to registry@caldera.com.
+	(EM_PDP10, EM_PDP11): Define.
+
+2002-06-04  Jason Thorpe  <thorpej@wasabisystems.com>
+
+	* sh.h (_bfd_sh64_crange_qsort_cmpb, _bfd_sh64_crange_qsort_cmpl)
+	(_bfd_sh64_crange_bsearch_cmpb, _bfd_sh64_crange_bsearch_cmpl): New
+	prototypes.
+
+2002-06-01  Richard Henderson  <rth@redhat.com>
+
+	* alpha.h (LITUSE_ALPHA_ADDR, LITUSE_ALPHA_BASE, LITUSE_ALPHA_BYTOFF,
+	LITUSE_ALPHA_JSR, LITUSE_ALPHA_TLSGD, LITUSE_ALPHA_TLSLDM): New.
+
+2002-05-30  Richard Henderson  <rth@redhat.com>
+
+	* alpha.h (R_ALPHA_TLSGD, R_ALPHA_TLSLDM, R_ALPHA_DTPMOD64,
+	R_ALPHA_GOTDTPREL, R_ALPHA_DTPREL64, R_ALPHA_DTPRELHI,
+	R_ALPHA_DTPRELLO, R_ALPHA_DTPREL16, R_ALPHA_GOTTPREL, R_ALPHA_TPREL64,
+	R_ALPHA_TPRELHI, R_ALPHA_TPRELLO, R_ALPHA_TPREL16): New.
+
+2002-05-29  Matt Thomas  <matt@3am-software.com>
+
+	* vax.h: New file
+
+2002-05-28  Kuang Hwa Lin <kuang@sbcglobal.net>
+
+	* common.h (EM_DLX): Define.
+	* dlx.h: New file.
+
+2002-05-08  Jason Thorpe  <thorpej@wasabisystems.com>
+
+	* common.h (NT_GNU_ABI_TAG): Define.
+	(GNU_ABI_TAG_LINUX): Define.
+	(GNU_ABI_TAG_HURD): Define.
+	(GNU_ABI_TAG_SOLARIS): Define.
+	(NT_NETBSD_IDENT): Define.
+	(NT_FREEBSD_ABI_TAG): Define.
+
+2002-04-24  Elena Zannoni  <ezannoni@redhat.com>
+
+	* dwarf2.h: Add DW_AT_GNU_vector.
+
+2002-02-13  Matt Fredette  <fredette@netbsd.org>
+
+	* m68k.h (EF_M68000): Define.
+
+2002-02-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (DT_PPC64_OPD, DT_PPC64_OPDSZ): Define.
+
+2002-02-09  Richard Henderson  <rth@redhat.com>
+
+	* alpha.h (R_ALPHA_BRSGP): New.
+
+2002-02-08  Alexandre Oliva  <aoliva@redhat.com>
+
+	Contribute sh64-elf.
+	2002-01-23  Alexandre Oliva  <aoliva@redhat.com>
+	* sh.h (R_SH_GOTPLT32, R_SH_GOT_LOW16, R_SH_GOT_MEDLOW16,
+	R_SH_GOT_MEDHI16, R_SH_GOT_HI16, R_SH_GOTPLT_LOW16,
+	R_SH_GOTPLT_MEDLOW16, R_SH_GOTPLT_MEDHI16, R_SH_GOTPLT_HI16,
+	R_SH_PLT_LOW16, R_SH_PLT_MEDLOW16, R_SH_PLT_MEDHI16,
+	R_SH_PLT_HI16, R_SH_GOTOFF_LOW16, R_SH_GOTOFF_MEDLOW16,
+	R_SH_GOTOFF_MEDHI16, R_SH_GOTOFF_HI16, R_SH_GOTPC_LOW16,
+	R_SH_GOTPC_MEDLOW16, R_SH_GOTPC_MEDHI16, R_SH_GOTPC_HI16,
+	R_SH_GOT10BY4, R_SH_GOTPLT10BY4, R_SH_GOT10BY8,
+	R_SH_GOTPLT10BY8, R_SH_COPY64, R_SH_GLOB_DAT64, R_SH_JMP_SLOT64,
+	R_SH_RELATIVE64): New relocs.
+	(R_SH_FIRST_INVALID_RELOC_4): Adjust.
+	2001-05-16  Alexandre Oliva  <aoliva@redhat.com>
+	* sh.h: Renumbered and renamed some SH5 relocations to match
+	official numbers and names; moved unmaching ones to the range
+	0xf2-0xff.
+	2001-01-06  Hans-Peter Nilsson  <hpn@cygnus.com>
+	* sh.h (sh64_get_contents_type): Declare.
+	(sh64_address_is_shmedia): Likewise.
+	2000-12-30  Hans-Peter Nilsson  <hpn@cygnus.com>
+	* sh.h (sh64_elf_crange): New type.
+	(struct sh64_section_data): New.
+	(sh64_elf_section_data): New macro.
+	(EF_SH5): Rename back from EF_SH64.
+	2000-12-18  Hans-Peter Nilsson  <hpn@cygnus.com>
+	* sh.h (SHF_SH5_ISA32_MIXED, SHT_SH5_CR_SORTED,
+	SH64_CRANGES_SECTION_NAME, SH64_CRANGE_SIZE,
+	SH64_CRANGE_CR_ADDR_OFFSET, SH64_CRANGE_CR_SIZE_OFFSET,
+	SH64_CRANGE_CR_TYPE_OFFSET): New macros.
+	2000-12-12  Hans-Peter Nilsson  <hpn@cygnus.com>
+	* sh.h (EF_SH64): Don't define EF_SH64_ABI64.
+	2000-11-27  Hans-Peter Nilsson  <hpn@cygnus.com>
+	* sh.h (EF_SH64_32BIT_ABI, EF_SH64_64BIT_ABI): Delete.
+	(EF_SH64_ABI64): New.
+	2000-11-23  Hans-Peter Nilsson  <hpn@cygnus.com>
+	* sh.h (EF_SH64): Rename from EF_SH5.
+	(EF_SH64_32BIT_ABI): New.
+	(EF_SH64_64BIT_ABI): New.
+	(R_SH_PT_16, R_SH_SHMEDIA_CODE
+	R_SH_IMMU5, R_SH_IMMS6, R_SH_IMMU6, R_SH_IMMS10, R_SH_IMMS10BY2,
+	R_SH_IMMS10BY4, R_SH_IMMS10BY8, R_SH_IMMS16, R_SH_IMMU16,
+	R_SH_IMM_LOW16, R_SH_IMM_LOW16_PCREL, R_SH_IMM_MEDLOW16,
+	R_SH_IMM_MEDLOW16_PCREL, R_SH_IMM_MEDHI16, R_SH_IMM_MEDHI16_PCREL,
+	R_SH_IMM_HI16, R_SH_IMM_HI16_PCREL, R_SH_64, R_SH_64_PCREL): New
+	relocs.
+	2000-09-01  Ben Elliston  <bje@redhat.com>
+	* sh.h (EF_SH5): Define.
+
+2002-02-01  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* mmix.h: Tweak comments.
+	(MMIX_LD_ALLOCATED_REG_CONTENTS_SECTION_NAME): New.
+	[BFD_ARCH_SIZE] (_bfd_mmix_prepare_linker_allocated_gregs,
+	_bfd_mmix_finalize_linker_allocated_gregs,
+	_bfd_mmix_check_all_relocs): Provide prototypes.
+
+2002-01-31  Ivan Guzvinec  <ivang@opencores.org>
+
+	* or32.h: New file.
+	* common.h: Add support for or32 targets.
+
+2002-01-28  Jason Merrill  <jason@redhat.com>
+
+	* dwarf2.h: Sync with gcc version.
+
+2002-01-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (DT_PPC64_GLINK): Define.
+
+2002-01-15  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.h (F_VFP_FLOAT, EF_ARM_VFP_FLOAT): Define.
+
+2002-01-09  Jason Thorpe  <thorpej@wasabisystems.com>
+
+	* common.h: Update copyright years.
+	(NT_NETBSDCORE_PROCINFO): Define.
+	(NT_NETBSDCORE_FIRSTMACH): Define.
+
+2002-01-06  Steve Ellcey  <sje@cup.hp.com>
+
+	* ia64.h (ELF_STRING_ia64_unwind_hdr): New Macro for HP-UX.
+	(SHT_IA_64_HP_OPT_ANOT): Ditto
+	(PT_IA_64_HP_OPT_ANOT): Ditto
+	(PT_IA_64_HP_HSL_ANOT): Ditto
+	(PT_IA_64_HP_STACK): Ditto
+	(SHN_IA_64_ANSI_COMMON): Ditto
+
+2001-12-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* external.h (Elf_External_Sym_Shndx): Declare.
+	* internal.h (struct elf_internal_sym <st_shndx>): Make it an
+	unsigned int.
+	* common.h (SHN_BAD): Define.
+
+2001-12-13  Jakub Jelinek  <jakub@redhat.com>
+
+	* common.h (PT_GNU_EH_FRAME): Define.
+
+2001-12-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* common.h (SHN_XINDEX): Comment typo fix.
+	* internal.h (Elf_Internal_Ehdr): Change existing "unsigned short"
+	size, count and index fields to "unsigned int".
+
+2001-12-07  Geoffrey Keating  <geoffk@redhat.com>
+	    Richard Henderson  <rth@redhat.com>
+
+	* common.h (EM_XSTORMY16): Define.
+	* xstormy16.h: New file.
+
+2001-11-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* common.h (NT_ARCH): Define.  Remove incorrect comment.
+
+2001-11-11  Geoffrey Keating  <geoffk@redhat.com>
+
+	* dwarf2.h (dwarf_line_number_ops): Add DWARF 3 opcodes.
+
+2001-10-30  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* mmix.h: New file.
+
+2001-10-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* internal.h: White space changes to keep lines under 80 chars.
+
+2001-10-16  Jeff Holcomb  <jeffh@redhat.com>
+
+	* internal.h (elf_internal_shdr): Make contents a unsigned char *.
+
+2001-09-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* internal.h (elf_internal_rela): Make r_addend a bfd_vma.
+
+2001-09-13  Alexandre Oliva  <aoliva@redhat.com>
+
+	* common.h (EM_OPENRISC_OLD): Renamed the old EM_OPENRISC entry.
+
+2001-09-12  Alexandre Oliva  <aoliva@redhat.com>
+
+	* common.h (EM_AVR_OLD): Renamed from...
+	(EM_AVR): this, redefined as in the current ELF standard.
+	(EM_PJ_OLD): Renamed from...
+	(EM_PJ): this, redefined as in the current ELF standard.
+	(EM_R30, EM_D10V, EM_D30V, EM_V850, EM_M32R, EM_MN10300,
+	EM_MN10200, EM_OPENRISC, EM_ARC_A5, EM_XTENSA): Defined as in
+	the current ELF standard.
+	(EM_CYGNUS_ARC): Removed, unused for a long time.
+
+2001-09-04  Richard Henderson  <rth@redhat.com>
+
+	* alpha.h (R_ALPHA_OP*, R_ALPHA_IMMED*, R_ALPHA_GPVALUE): Remove.
+	(R_ALPHA_GPREL16): Rename from R_ALPHA_IMMED_GP_16.
+
+2001-08-30  Eric Christopher  <echristo@redhat.com>
+
+	* mips.h: Remove E_MIPS_MACH_MIPS32_4K.
+
+2001-08-29  Jeff Law <law@redhat.com>
+
+	* h8.h (EF_H8_MACH): New mask for encoded machine type.
+	(E_H8_MACH_H8300, E_H8_MACH_H8300H, E_H8_MACH_H8300S): New
+	machine types.
+
+2001-08-26  J"orn Rennecke <amylaar@redhat.com>
+
+	* h8.h: New file.
+
+2001-08-27  Staffan Ulfberg  <staffanu@swox.se>
+
+	* ppc.h: Add relocs from the 64-bit PowerPC ELF ABI revision 1.2.
+
+2001-06-30  Daniel Berlin  <dan@cgsoftware.com>
+
+	* dwarf2.h: Remerge with gcc version,
+	including all new DWARF 2.1 extensions.
+
+2001-06-29  James Cownie <jcownie@etnus.com>
+
+	* dwarf2.h: Add DWARF 2.1 attribues.
+
+2001-06-15  Per Bothner  <per@bothner.com>
+
+	* dwarf2.h:  Partial merge with gcc version.
+	(enum dwarf_descrim_list):  Fix typo -> dwarf_discrim_list.
+	(DW_LANG_Java):  Use value from dwarf 2.1 draft (also used in gcc).
+
+2001-05-15  Ralf Baechle  <ralf@gnu.org>
+
+	* common.h: Remove definition of EM_MIPS_RS4_BE.  The constant was
+	never in active use and is used otherwise by the ABI.
+
+2001-05-11  Jakub Jelinek  <jakub@redhat.com>
+
+	* ia64.h (ELF_STRING_ia64_unwind_once): Define.
+	(ELF_STRING_ia64_unwind_info_once): Define.
+
+2001-05-07  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* external.h: Fix typo.
+	* mips.h: Add/Extend many comments with reference to the MIPS ELF64
+	spec v. 2.4, available at e.g.
+	ftp://oss.sgi.com/pub/linux/mips/doc/ABI/ELF64.ps.
+	(EF_MIPS_UCODE): Define.
+	(EF_MIPS_OPTIONS_FIRST): Define.
+	(EF_MIPS_ARCH_ASE): Define.
+	(EF_MIPS_ARCH_ASE_MDMX): Define.
+	(EF_MIPS_ARCH_ASE_M16): Define.
+	(SHF_MIPS_ADDR): Renamed SHF_MIPS_ADDR32.
+	(SHF_MIPS_STRING): Renamed SHF_MIPS_ADDR64.
+	(SHF_MIPS_NODUPES): Define.
+	(ELF64_MIPS_R_SSYM): New MIPS ELF 64 relocation info access macro.
+	(ELF64_MIPS_R_TYPE3): Likewise.
+	(ELF64_MIPS_R_TYPE2): Likewise.
+	(ELF64_MIPS_R_TYPE): Likewise.
+	(OHW_R10KLDL): Define.
+
+2001-04-24  Todd Fries  <todd@fries.net>
+
+	* sparc.h: Fix typo.
+
+2001-04-20  Johan Rydberg  <jrydberg@opencores.org>
+
+	* openrisc.h: New file.
+	* common.h (EM_OPENRISC): New constant.
+
+2001-04-23  Bo Thorsen  <bo@suse.de>
+
+	* x86-64.h: Add vtable support.
+
+2001-03-23  Nick Clifton  <nickc@redhat.com>
+
+	* mips.h: Remove extraneous whitespace.
+
+2001-03-22  Hans-Peter Nilsson  <hp@axis.com>
+
+	* cris.h: Add leading comment about PC-relative location.
+	(R_CRIS_COPY, R_CRIS_GLOB_DAT, R_CRIS_JUMP_SLOT, R_CRIS_RELATIVE,
+	R_CRIS_16_GOT, R_CRIS_32_GOT, R_CRIS_16_GOTPLT, R_CRIS_32_GOTPLT,
+	R_CRIS_32_GOTREL, R_CRIS_32_PLT_GOTREL, R_CRIS_32_PLT_PCREL):
+	New relocs.
+
+2001-02-27  Philip Blundell  <pb@futuretv.com>
+
+	* arm.h: Add new definitions from ARM document SWS ESPC 0003 B-01.
+	(EF_PIC, et al.): Rename to EF_ARM_xx.
+
+2001-02-09  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* common.h: Add linux target for S/390.
+	* s390.h: New file.
+
+2001-01-11  Peter Targett  <peter.targett@arccores.com>
+
+	* arc.h (E_ARC_MACH_ARC5, E_ARC_MACH_ARC6, E_ARC_MACH_ARC7,
+	E_ARC_MACH_ARC8): New definitions for cpu types.
+
+	* common.h (EM_ARC): Change comment.
+
+2000-12-12  Nick Clifton  <nickc@redhat.com>
+
+	* mips.h: Fix formatting.
+
+2000-12-11  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (DT_HP_*): Define relative to OLD_DT_LOOS for hpux
+	compatibility.
+
+2000-10-16  Chris Demetriou  <cgd@sibyte.com>
+
+	* mips.h (E_MIPS_ARCH_32): New constant.
+	(E_MIPS_MACH_MIPS32, E_MIPS_MACH_MIPS32_4K): Replace the
+	former with the latter.
+
+	* mips.h (E_MIPS_ARCH_5, E_MIPS_ARCH_64): New definitions.
+
+	* mips.h (E_MIPS_MACH_SB1): New constant.
+
+2000-11-30  Jan Hubicka  <jh@suse.cz>
+
+	* common.h (EM_X86_64): New macro.
+	* x86-64.h: New file.
+
+2000-11-27  Hans-Peter Nilsson  <hp@axis.com>
+
+	* common.h (e_machine numbers): Clarify comments to describe how
+	EM_* constants are assigned.  Move EM_PJ from official section to
+	ad-hoc section.
+	(EM_CRIS): Correct comment to match official description.
+	(EM_MMIX): Ditto.
+
+2000-11-22  Nick Clifton  <nickc@redhat.com>
+
+	* common.h (EM_JAVELIN): New machine number.
+	(EM_FIREPATH): New machine number.
+	(EM_ZSP): New machine number.
+	(EM_MMIX): New machine number.
+	(EM_HUANY): New machine number.
+	(EM_PRISM): New machine number.
+	(SHT_GROUP): New section type.
+	(SHT_SYMTAB_SHNDX): New section type.
+	(SHF_GROUP): New section flag.
+	(SHN_XINDEX): New section index.
+	(GRP_COMDAT): New section group flag.
+
+2000-11-20  H.J. Lu  <hjl@gnu.org>
+
+	* common.h (ELFOSABI_MONTEREY): Renamed to ...
+	(ELFOSABI_AIX): This.
+
+2000-11-16  Richard Henderson  <rth@redhat.com>
+
+	Update relocations per August psABI docs.
+	* ia64.h (R_IA64_SEGBASE): Remove.
+	(R_IA64_LTV*): Renumber to 0x74 to 0x77.
+	(R_IA64_EPLTMSB, R_IA64_EPLTLSB): Remove.
+	(R_IA64_TPREL14, R_IA64_TPREL64I): New.
+	(R_IA64_DTPMOD*): New.
+	(R_IA64_DTPREL*): New.
+
+2000-09-29  Hans-Peter Nilsson  <hp@axis.com>
+
+	* cris.h (EF_CRIS_UNDERSCORE): New.
+
+2000-09-27  Alan Modra  <alan@linuxcare.com.au>
+
+	* hppa.h (R_PARISC_DIR14F): Add.
+
+2000-09-14  Alexandre Oliva  <aoliva@redhat.com>
+
+	* sh.h (R_SH_GOT32, R_SH_PLT32, R_SH_COPY, R_SH_GLOB_DAT,
+	R_SH_JMP_SLOT, R_SH_RELATIVE, R_SH_GOTOFF, R_SH_GOTPC): Change
+	numbers to the range from 160 to 167.
+	(R_SH_FIRST_INVALID_RELOC): Adjust.
+	(R_SH_FIRST_INVALID_RELOC_2, R_SH_LAST_INVALID_RELOC_2):
+	New relocs to fill in the gap.
+
+2000-09-13  Anders Norlander  <anorland@acc.umu.se>
+
+	* mips.h (E_MIPS_MACH_4K): New define.
+
+2000-09-05  Alan Modra  <alan@linuxcare.com.au>
+
+	* hppa.h: Fix a comment.
+	(R_PARISC_PCREL12F): Define.
+	(R_PARISC_GNU_VTENTRY): Define.
+	(R_PARISC_GNU_VTINHERIT): Define.
+
+2000-09-01  Alexandre Oliva  <aoliva@redhat.com>
+
+	* sh.h (R_SH_GOT32, R_SH_PLT32, R_SH_COPY, R_SH_GLOB_DAT,
+	R_SH_JMP_SLOT, R_SH_RELATIVE, R_SH_GOTOFF, R_SH_GOTPC): New relocs.
+	(R_SH_FIRST_INVALID_RELOC): Adjust.
+
+2000-08-14  Jim Wilson  <wilson@cygnus.com>
+
+	* ia64.h (EF_IA_64_REDUCEDFP, EF_IA_64_CONS_GP,
+	EF_IA_64_NOFUNCDESC_CONS_GP, EF_IA_64_ABSOLUTE): Define.
+
+2000-08-07  Nick Clifton  <nickc@cygnus.com>
+
+	* ppc.h: Remove spurious CYGNUS LOCAL comments.
+	* v850.h: Likewise.
+
+2000-07-22  Jason Eckhardt  <jle@cygnus.com>
+
+	* i860.h: New file.
+	(elf_i860_reloc_type): Defined ELF32 i860 relocations.
+
+2000-07-20  Hans-Peter Nilsson  <hp@axis.com>
+
+	common.h (EM_CRIS): New machine number.
+	cris.h: New file.
+
+2000-07-19  H.J. Lu  <hjl@gnu.org>
+
+	* common.h (DF_1_NODEFLIB): Renamed from DF_1_NODEPLIB.
+
+2000-07-19  H.J. Lu  <hjl@gnu.org>
+
+	* common.h (DT_CHECKSUM): Set to 0x6ffffdf8.
+	(DTF_1_CONFEXP): It is 0x00000002 as suspected.
+
+2000-07-19  H.J. Lu  <hjl@gnu.org>
+
+	* common.h (DT_FEATURE): Renamed from DT_FEATURE_1.
+	(DT_CONFIG): New. From Solaris 8.
+	(DT_DEPAUDIT): Likewise.
+	(DT_AUDIT): Likewise.
+	(DT_PLTPAD): Likewise.
+	(DT_MOVETAB): Likewise.
+	(DF_1_NODEPLIB): Likewise.
+	(DF_1_NODUMP): Likewise.
+	(DF_1_CONLFAT): Likewise.
+	(DT_CHECKSUM): Likewise. FIXME. Check the value on Solaris 8.
+	(DTF_1_CONFEXP): Likewise.
+
+2000-07-18  H.J. Lu  <hjl@gnu.org>
+
+	* common.h (DT_FLAGS_1): Renamed from DT_1_FLAGS.
+
+2000-07-12  Alan Modra  <alan@linuxcare.com.au>
+
+	* internal.h (struct elf_internal_sym): Update comment for st_other.
+
+2000-07-10  Alan Modra  <alan@linuxcare.com.au>
+
+	* hppa.h: Add comments to all the relocs.
+
+2000-06-26  Marek Michalkiewicz  <marekm@linux.org.pl>
+
+	* avr.h (E_AVR_MACH_AVR5): Define.
+
+2000-06-18  Stephane Carrez  <stcarrez@worldnet.fr>
+
+	* m68hc11.h: New file, definitions for the Motorola 68hc11.
+
+2000-06-06  Alan Modra  <alan@linuxcare.com.au>
+
+	* reloc-macros.h (START_RELOC_NUMBERS): Don't define initial dummy
+	-1 valued enum.
+	(RELOC_NUMBER, FAKE_RELOC, EMPTY_RELOC): Append rather than
+	prepend comma.
+	(END_RELOC_NUMBERS): Give macro an arg to define as last enum.
+
+	* alpha.h (R_ALPHA_max): Define via END_RELOC_NUMBERS rather than
+	with EMPTY_RELOC.
+	* arc.h (R_ARC_max): Likewise.
+	* avr.h (R_AVR_max): Likewise.
+	* fr30.h (R_FR30_max): Likewise.
+	* hppa.h (R_PARISC_UNIMPLEMENTED): Likewise.
+	* i960.h (R_960_max): Likewise.
+	* m32r.h (R_M32R_max): Likewise.
+	* m68k.h (R_68K_max): Likewise.
+	* mcore.h (R_MCORE_max): Likewise.
+	* mn10300.h (R_MN10300_MAX): Likewise.
+	* pj.h (R_PJ_max): Likewise.
+	* ppc.h (R_PPC_max): Likewise.
+	* sh.h (R_SH_max): Likewise.
+	* sparc.h (R_SPARC_max): Likewise.
+	* v850.h (R_V850_max): Likewise.
+
+	* arm.h (R_ARM_max): Define via END_RELOC_NUMBERS.
+	* d10v.h (R_D10V_max): Likewise.
+	* d30v.h (R_D30V_max): Likewise.
+	* ia64.h (R_IA64_max): Likewise.
+	* mips.h (R_MIPS_maxext): Likewise.
+	* mn10200.h (R_MN10200_max): Likewise.
+
+	* i386.h (R_386_max): Remove old RELOC_NUMBER definition, and
+	define via END_RELOC_NUMBERS.
+
+2000-06-03  Alan Modra  <alan@linuxcare.com.au>
+
+	* reloc-macros.h (START_RELOC_NUMBERS): Fix name clash for
+	!__STDC__ case.
+	(RELOC_NUMBER): Use ansi stringify if ALMOST_STDC defined.
+
+2000-05-22  Richard Henderson  <rth@cygnus.com>
+
+	* ia64.h (R_IA64_PCREL60B, R_IA64_PCREL21BI): New.
+	(R_IA64_PCREL22, R_IA64_PCREL64I): New.
+
+2000-05-02  H.J. Lu  <hjl@gnu.org>
+
+	* common.h (ELFOSABI_NONE): Renamed from ELFOSABI_SYSV.
+	(ELFOSABI_MODESTO): Defined.
+	(ELFOSABI_OPENBSD): Likewise.
+
+2000-04-21  Richard Henderson  <rth@cygnus.com>
+	    David Mosberger  <davidm@hpl.hp.com>
+
+	* ia64.h: New file.
+
+2000-04-14  H.J. Lu  <hjl@gnu.org>
+
+	* common.h (ELFOSABI_TRUE64): Renamed to ELFOSABI_TRU64.
+
+2000-04-14  H.J. Lu  <hjl@gnu.org>
+
+	* common.h (ELFOSABI_NETBSD): Defined.
+	(ELFOSABI_HURD): Likewise.
+	(ELFOSABI_SOLARIS): Likewise.
+	(ELFOSABI_MONTEREY): Likewise.
+	(ELFOSABI_IRIX): Likewise.
+	(ELFOSABI_FREEBSD): Likewise.
+	(ELFOSABI_TRUE64): Likewise.
+
+2000-04-07  Nick Clifton  <nickc@cygnus.com>
+
+	* arm-oabi.h: Delete.
+	* arm.h: Merge in definitions of old reloc numbers from
+	arm-oabi.h.
+
+2000-04-06  Nick Clifton  <nickc@cygnus.com>
+
+	* arm.h (EF_ARM_SYMSARESORTED): Define.
+	(EF_ARM_EABIMASK): Define.
+	(EF_ARM_EABI_VERSION): Define.
+	(EF_ARM_EABI_UNKNOWN): Define.
+	(EF_ARM_EABI_VER1): Define.
+	(PF_ARM_PI): Define.
+	(PF_ARM_ABS): Define.
+
+2000-04-05  J"orn Rennecke <amylaar@cygnus.co.uk>
+
+	* sh.h (R_SH_LOOP_START, R_SH_LOOP_END): New RELOC_NUMBERs.
+
+2000-03-27  Denis Chertykov  <denisc@overta.ru>
+
+	* avr.h: New file.  AVR ELF support for BFD.
+	* common.h: Add AVR magic number.
+
+2000-03-10  Geoffrey Keating  <geoffk@cygnus.com>
+
+	* mips.h: Add R_MIPS_GNU_REL_HI16, R_MIPS_GNU_REL_LO16,
+	R_MIPS_GNU_REL16_S2, R_MIPS_PC64 and R_MIPS_PC32 relocation
+	numbers.
+
+2000-02-23  Linas Vepstas <linas@linas.org>
+
+	* i370.h: New file.
+
+2000-02-22  Nick Clifton  <nickc@cygnus.com>
+
+	* common.h (ELF_ST_OTHER): Remove definition.
+	(ELF32_ST_OTHER): Remove definition.
+	(ELF64_ST_OTHER): Remove definition.
+
+2000-02-22  H.J. Lu  <hjl@gnu.org>
+
+	* common.h (ELFOSABI_LINUX): Define.
+
+2000-02-17  J"orn Rennecke <amylaar@cygnus.co.uk>
+
+	* sh.h: (EF_SH_MACH_MASK, EF_SH_UNKNOWN, EF_SH1, EF_SH2): New macros.
+	(EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise.
+	(EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise.
+
+2000-02-03  H.J. Lu  <hjl@gnu.org>
+
+	* arm-oabi.h: Duplicate changes made to arm.h on Jan. 27,
+	2000 by Thomas de Lellis  <tdel@windriver.com>.
+
+2000-01-27  Thomas de Lellis  <tdel@windriver.com>
+
+	* arm.h (STT_ARM_TFUNC): Define in terms of STT_LOPROC.
+	(STT_ARM_16BIT): New flag.  Denotes a label that was defined in
+	Thumb block but was does not identify a function.
+
+2000-01-20  Nick Clifton  <nickc@cygnus.com>
+
+	* common.h (EM_MCORE): Fix spelling of Motorola.
+	* mcore.h (EM_MCORE): Fix spelling of Motorola.
+
+2000-01-13  Nick Clifton  <nickc@cygnus.com>
+
+	* common.h (EM_S370): Change comment - this is now the IBM
+	System/370.
+	(EM_IA_64): Change comment - this is now the IA-64.
+
+2000-01-11  Nick Clifton  <nickc@cygnus.com>
+
+	* common.h (DT_ENCODING): Fix definition of this value.
+	(DT_LOOS): Fix definition of this value.
+	(DT_HIOS): Fix definition of this value.
+	(OLD_DT_LOOS): Value of DT_LOOS before Oct 4, 1999 draft
+	of ELF spec changed it.
+	(OLD_DT_HIOS): Value of DT_HIOS before Oct 4, 1999 draft
+	of ELF spec changed it.
+
+2000-01-10  Egor Duda  <deo@logos-m.ru>
+
+	* common.h (NT_WIN32PSTATUS): Define.  (cygwin elf core dumps).
+
+1999-12-28  Nick Clifton  <nickc@cygnus.com>
+
+	* mips.h (STO_*): Redefine in terms of STV_* values now in
+	common.h.
+
+1999-12-27  Nick Clifton  <nickc@cygnus.com>
+
+	* common.h: Upgrade to match Oct4, 1999 Draft ELF ABI Spec.
+	(EM_MIPS_RS3_LE): New machine number.
+	(EM_RCE): New machine number.
+	(EM_MMA): New machine number.
+	(EM_PCP): New machine number.
+	(EM_NCPU): New machine number.
+	(EM_NDR1): New machine number.
+	(EM_STARCORE): New machine number.
+	(EM_ME16): New machine number.
+	(EM_ST100): New machine number.
+	(EM_TINYJ): New machine number.
+	(EM_FX66): New machine number.
+	(EM_ST9PLUS): New machine number.
+	(EM_ST7): New machine number.
+	(EM_68HC16): New machine number.
+	(EM_68HC11): New machine number.
+	(EM_68HC08): New machine number.
+	(EM_68HC05): New machine number.
+	(EM_SVX): New machine number.
+	(EM_VAX): New machine number.
+	(PF_MASKOS): Change value.
+	(SHT_INIT_ARRAY): New value for sh_type field.
+	(SHT_FINI_ARRAY): New value for sh_type field.
+	(SHT_PREINIT_ARRAY): New value for sh_type field.
+	(SHT_HIUSER): Change value.
+	(SHF_MERGE): New valye for sh_flags field.
+	(SHF_STRINGS): New valye for sh_flags field.
+	(SHF_INFO_LINK): New valye for sh_flags field.
+	(SHF_OS_NONCONFORMING): New valye for sh_flags field.
+	(SHF_MASKOS): Change value.
+	(ELF_ST_VISIBILITY): New macro.
+	(ELF_ST_OTHER): New macro.
+	(STT_COMMON): New symbol type.
+	(STV_DEFAULT): Value for symbol visibility.
+	(STV_INTERNAL): Value for symbol visibility.
+	(STV_HIDDEN): Value for symbol visibility.
+	(STV_PROTECTED): Value for symbol visibility.
+	(DT_RUNPATH): New dynamic section tag.
+	(DT_FLAGS): New dynamic section tag.
+	(DT_ENCODING): New dynamic section tag.
+	(DT_PREINIT_ARRAY): New dynamic section tag.
+	(DT_PREINIT_ARRAYSZ): New dynamic section tag.
+	(DT_LOPROC): New dynamic section tag index.
+	(DT_HIPROC): New dynamic section tag index.
+	(DF_ORIGIN): Value for dynamic section flag.
+	(DF_SYMBOLIC): Value for dynamic section flag.
+	(DF_TEXTREL): Value for dynamic section flag.
+	(DF_BIND_NOW): Value for dynamic section flag.
+
+1999-12-09  Fred Fish  <fnf@cygnus.com>
+
+	* i960.h (reloc-macros.h):  Include using relative dir elf/.
+	* i386.h (reloc-macros.h):  Include using relative dir elf/.
+	* hppa.h (reloc-macros.h):  Include using relative dir elf/.
+
+1999-12-07  Jim Blandy  <jimb@cygnus.com>
+
+	* common.h (NT_PRXFPREG): New definition.
+
+Wed Dec  1 03:02:15 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (E_MN10300_MACH_AM33): Define.
+
+Mon Oct 11 22:42:37 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (PF_HP_PAGE_SIZE): Define.
+	(PF_HP_FAR_SHARED, PF_HP_NEAR_SHARED, PF_HP_CODE): Likewise.
+	(PF_HP_MODIFY, PF_HP_LAZYSWAP, PF_HP_SBP): Likewise.
+
+Mon Oct  4 17:42:38 1999  Doug Evans  <devans@canuck.cygnus.com>
+
+	* m32r.h (E_M32RX_ARCH): Define.
+
+1999-09-15  Ulrich Drepper  <drepper@cygnus.com>
+
+	* hppa.h: Add DT_HP_GST_SIZE, DT_HP_GST_VERSION, and DT_HP_GST_HASHVAL.
+
+1999-09-04  Steve Chamberlain  <sac@pobox.com>
+
+	* pj.h: New file.
+	* common.h (EM_PJ): Define.
+
+1999-09-02  Ulrich Drepper  <drepper@cygnus.com>
+
+	* hppa.h: Add HPUX specific symbol type definitions.
+
+	* hppa.h: Add HPUX specific dynamic and program header table
+	specific definitions.
+
+1999-08-31  Scott Bambrough <scottb@netwinder.org>
+
+	* common.h (NT_TASKSTRUCT): Define.
+
+1999-07-16  Jakub Jelinek  <jj@ultra.linux.cz>
+
+	* sparc.h (EF_SPARC_SUN_US3): Define in Cheetah extensions
+	flag (as per SCD2.4.1).
+
+1999-07-16  Jakub Jelinek  <jj@ultra.linux.cz>
+
+	* sparc.h (ELF64_R_TYPE_DATA): Only use ELF64_R_TYPE bits, not
+	ELF64_R_SYM bits.
+
+1999-06-21  Philip Blundell  <pb@nexus.co.uk>
+
+	* arm.h (EF_SOFT_FLOAT, F_SOFT_FLOAT): Define.
+
+1999-07-13  Andreas Schwab  <schwab@suse.de>
+
+	* m68k.h (EF_CPU32): Move definition inside multiple inclusion
+	guard.
+
+1999-07-08  Richard Henderson  <rth@cygnus.com>
+
+	* sparc.h (ELF64_R_TYPE_DATA): Sign extend the value.
+	(ELF64_R_TYPE_INFO): Mask out all but low 24 bits of data.
+	(DT_SPARC_PLTFMT): Delete.
+	Based on a patch from Jakub Jelinek.
+
+Mon Jun 21 16:36:02 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (elf_hppa_reloc_type): Renamed from elf32_hppa_reloc_type.
+
+1999-06-10  Jakub Jelinek  <jj@ultra.linux.cz>
+
+	* sparc.h (R_SPARC_max_std): Define.
+
+Wed Jun  9 15:16:34 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h: Update with various changes from newest PA ELF
+	specifications.
+
+1999-06-03  Ian Lance Taylor  <ian@zembu.com>
+
+	* common.h (EM_PPC64): Define.
+
+1999-06-02  Stu Grossman  <grossman@babylon-5.cygnus.com>
+
+	* dwarf.h: Add LANG_JAVA.
+	* dwarf2.h: Add DW_LANG_Java.
+
+1999-05-29  Nick Clifton  <nickc@cygnus.com>
+
+	* common.h (ELFOSABI_ARM): Define.
+
+1999-05-28  Nick Clifton  <nickc@cygnus.com>
+
+	* reloc-macros.h: Update comment.
+
+1999-05-28  Ian Lance Taylor  <ian@zembu.com>
+
+	* i960.h: New file.
+
+1999-05-16  Nick Clifton  <nickc@cygnus.com>
+
+	* mcore.h (R_MCORE_COPY): Define.
+	(R_MCORE_GLOB_DAT): Define.
+	(R_MCORE_JUMP_SLOT): Define.
+
+1999-05-15  Nick Clifton  <nickc@cygnus.com>
+
+	* mcore.h (R_MCORE_RELATIVE): Define.
+
+1999-05-05  Catherine Moore  <clm@cygnus.com>
+
+	* m68k.h (EF_CPU32): Define.
+
+1999-04-21  Nick Clifton  <nickc@cygnus.com>
+
+	* reloc-macros.h (START_RELOC_NUMBERS): Prepend an underscore to
+	fake reloc entry name (if possible), in order to avoid conflicts
+	with typedefs of the same name.
+
+1999-04-16  Gavin Romig-Koch  <gavin@cygnus.com>
+
+	* mips.h (EF_MIPS_32BITMODE): New.
+
+1999-04-08  Nick Clifton  <nickc@cygnus.com>
+
+	* mcore.h: New header file.  Defines for Motorola's MCore
+	processor.
+
+1999-04-08  Nick Clifton  <nickc@cygnus.com>
+
+	* common.h: Add new constants defined in: "System V Application
+	Binary Interface - DRAFT - April 29, 1998" found at the web site:
+	http://www.sco.com/developer/gabi/contents.html
+
+	(EM_MMA): Removed.  Replaced with EM_MCORE as Motorolla own this
+	value.
+
+1999-03-31  Nick Clifton  <nickc@cygnus.com>
+
+	* reloc-macros.h: Fixed to not generate an enum with a trailing
+	comma.
+
+1999-03-16  Gavin Romig-Koch  <gavin@cygnus.com>
+
+	* mips.h (E_MIPS_MACH_5000): New.
+
+1999-03-10  Ulrich Drepper  <drepper@cygnus.com>
+
+	* common.h: Add definitions for a few more Solaris ELF extensions.
+
+Thu Feb 18 18:58:26 1999  Ian Lance Taylor  <ian@cygnus.com>
+
+	* external.h: Only use attribute if __GNUC__ is defined.
+
+1999-02-17  Nick Clifton  <nickc@cygnus.com>
+
+	Patch submitted by: Scott Bambrough <scottb@corelcomputer.com>
+
+	* external.h: struct Elf_External_Versym must be packed on
+	ARM.  Code uses sizeof(Elf_External_Versym) and assumes it is
+	equal to sizeof(char[2]).  Reported by Jim Pick <jim@jimpick.com>
+
+1999-02-02  Nick Clifton  <nickc@cygnus.com>
+
+	* dwarf2.h (DWARF2_External_ARange): New structure.
+	(DWARF2_Internal_ARange): New structure.
+
+Mon Feb  1 11:33:56 1999  Catherine Moore  <clm@cygnus.com>
+
+	* arm.h:  Renumber relocs to conform to standard.
+	(EF_NEW_ABI):  Define.
+	(EF_OLD_ABI):  Define.
+	* arm-oabi.h:  New file.
+
+1999-01-28  Nick Clifton  <nickc@cygnus.com>
+
+	* fr30.h: Add R_FR30_GNU_VT{INHERIT,ENTRY} relocs.
+
+1999-01-27  Nick Clifton  <nickc@cygnus.com>
+
+	* dwarf2.h: Add typedefs for structures found in dwarf2 sections.
+
+1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
+
+	* mips.h (E_MIPS_MACH_4111): New.
+
+1998-12-15  Gavin Romig-Koch  <gavin@cygnus.com>
+
+	* mips.h (EF_MIPS_ABI,E_MIPS_ABI_O32,E_MIPS_ABI_O64,
+	E_MIPS_ABI_EABI32,E_MIPS_ABI_EABI64):
+
+1998-12-03  Nick Clifton  <nickc@cygnus.com>
+
+	* fr30.h: Add R_FR30_48 reloc.
+
+1998-12-02  Ulrich Drepper  <drepper@cygnus.com>
+
+	* mips.h: Add external data type for conflict section.
+
+	* mips.h: Add more LL_* options from Irix 6.5.
+
+	* mips.h: Add R_MIPS_JALR and adjust R_MIPS_max appropriately.
+
+Mon Nov 30 15:25:58 1998  J"orn Rennecke <amylaar@cygnus.co.uk>
+
+	* sh.h (elf_sh_reloc_type): Add R_SH_FIRST_INVALID_RELOC,
+	R_SH_LAST_INVALID_RELOC, R_SH_SWITCH8 and R_SH_max.
+
+Tue Nov 10 15:12:28 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* common.h (EM_CYGNUS_FR30): Reduce to a 16 bit value.
+
+Tue Nov 10 15:17:28 1998  Catherine Moore  <clm@cygnus.com>
+
+	* d10v.h:  Add vtable relocs.
+
+Wed Nov  4 15:56:50 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* common.h (EM_CYGNUS_FR30): New machine number.
+
+	* fr30.h: New file: Definitions for the FR30.
+
+Fri Oct 30 11:54:15 1998  Catherine Moore  <clm@cygnus.com>
+
+	From Philip Blundell <pb@nexus.co.uk>:
+	* arm.h (R_ARM_COPY, et al.): New relocs, used by Linux for PIC.
+	(EF_ALIGN8): New flag.
+
+Tue Oct 20 11:19:50 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* common.h (NT_LWPSTATUS): Close comment accidentally left open.
+
+Mon Oct 19 20:24:11 1998  Catherine Moore  <clm@cygnus.com>
+
+	* sh.h:  Add vtable relocs.
+
+Mon Oct 19 01:44:42 1998  Felix Lee  <flee@cygnus.com>
+
+	* common.h (NT_PSTATUS, NT_FPREGS, NT_PSINFO,
+	NT_LWPSTATUS,NT_LWPSINFO): added.
+	* internal.h (Elf_Internal_Note): new structure members.
+
+Fri Oct 16 14:11:25 1998  Catherine Moore  <clm@cygnus.com>
+
+	* m32r.h:  Add vtable relocs.
+
+Tue Oct  6 09:22:22 1998  Catherine Moore  <clm@cygnus.com>
+
+	* sparc.h:  Add vtable relocs.
+
+Mon Oct  5 09:39:22 1998  Catherine Moore  <clm@cygnus.com>
+
+	* v850.h:  Add vtable relocs.
+
+Sun Oct  4 21:17:51 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h (R_386_max): Change from 252 to 24.
+
+Mon Sep 21 12:24:44 1998  Catherine Moore  <clm@cygnus.com>
+
+	* i386.h:  Change vtable reloc numbers.
+
+Sun Sep 20 00:54:22 1998  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
+
+	* m68k.h: Add vtable relocs and R_68K_max.
+
+Tue Sep 15 09:56:49 CDT 1998  Catherine Moore  <clm@cygnus.com>
+
+	* arm.h:  Add vtable relocs.
+
+Mon Aug 31 11:25:27 1998  Catherine Moore  <clm@cygnus.com>
+
+	* arm.h:  Define STT_ARM_TFUNC.  Remove ST_THUMB_xxxx
+	definitions.
+
+Sat Aug 29 22:25:51 1998  Richard Henderson  <rth@cygnus.com>
+
+	* i386.h: Add vtable relocs.
+
+1998-08-25 16:42  Ulrich Drepper  <drepper@cygnus.com>
+
+	* common.h: Add SYMINFO_* macros to access Elf*_Syminfo information.
+
+	* external.h: Add Elf_External_Syminfo definition.
+
+	* internal.h: Add Elf_Internal_Syminfo, Elf32_Internal_Syminfo,
+	and Elf64_Syminfo definitions.
+
+Sun Aug  9 20:26:49 CDT 1998  Catherine Moore  <clm@cygnus.com>
+
+	* arm.h:  Add ST_THUMB definitions.
+
+Wed Aug  5 15:52:35 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* arm.h: Add ELF header flags to specify compile time optins:
+	EF_INTERWORK: New flag.
+	EF_APCS_26: New flag.
+	EF_APCS_FLOAT: New flag.
+	EF_PIC: New flag.
+
+1998-07-31 21:28  Ulrich Drepper  <drepper@cygnus.com>
+
+	* mips.h: Add missing RHF_* constants.
+
+Fri Jul 31 10:01:40 1998 Catherine Moore  <clm@cygnus.com>
+
+	* arm.h: Add R_ARM_THM_PC9 relocation.
+
+1998-07-30 16:25  Ulrich Drepper  <drepper@cygnus.com>
+
+	* common.h: Add new DT_* entries and there flag macros from Solaris.
+
+Tue Jul 28 18:14:07 1998  Stan Cox  <scox@equinox.cygnus.com>
+
+	* sparc.h: (R_SPARC_REV32): Added for little endian data e.g. sparc 86x.
+
+Fri Jul 24 11:22:06 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h: Add R_MN10300_24 relocation.
+
+1998-07-24  Ulrich Drepper  <drepper@cygnus.com>
+
+	* mips.h: Add MIPS64 relocation names and values.
+
+Wed Jul 22 19:29:00 Catherine Moore  <clm@cygnus.com>
+
+	* arm.h: Rename relocations.
+
+1998-07-22  Ulrich Drepper  <drepper@cygnus.com>
+
+	* ppc.h: Define enum as elf_ppc_reloc_type.
+
+Wed Jul 22 16:22:11 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* reloc-macros.h: New file.  Provides relocation macros:
+	START_RELOC_NUMBERS, RELOC_NUMBER, FAKE_RELOC, EMPTY_RELOC and
+	END_RELOC_NUMBERS used by other elf header files.
+
+	* alpha.h: Use reloc-macros.h.
+	* arc.h: Use reloc-macros.h.
+	* arm.h: Use reloc-macros.h.
+	* d10v.h: Use reloc-macros.h.
+	* d30v.h: Use reloc-macros.h.
+	* hppa.h: Use reloc-macros.h.
+	* i386.h: Use reloc-macros.h.
+	* m32r.h: Use reloc-macros.h.
+	* m68k.h: Use reloc-macros.h.
+	* mips.h: Use reloc-macros.h.
+	* mn10200.h: Use reloc-macros.h.
+	* mn10300.h: Use reloc-macros.h.
+	* ppc.h: Use reloc-macros.h.
+	* sh.h: Use reloc-macros.h.
+	* sparc.h: Use reloc-macros.h.
+	* v850.h: Use reloc-macros.h.
+
+1998-07-22 13:07  Ulrich Drepper  <drepper@cygnus.com>
+
+	* mn10300.h: Rewrite relocation definition using macros.
+	* mips.h: Likewise.
+	* ppc.h: Likewise.
+	* alpha.h: Likewise.
+	* arm.h: Likewise.
+	* d10v.h: Likewise.
+	* d30v.h: Likewise.
+	* m32r.h: Likewise.
+	* m68k.h: Likewise.
+	* mn10200.h: Likewise.
+	* sh.h: Likewise.
+	* sparc.h: Likewise.
+
+1998-07-21 13:07  Ulrich Drepper  <drepper@cygnus.com>
+
+	* arm.h: New file.
+	* d10v.h: New file.
+	* d30v.h: New file.
+	* i386.h: New file.
+	* m68k.h: New file.
+	* mn10200.h: New file.
+	* sh.h: New file.
+
+	* mips.h: Add R_MIPS_* and SHT_MIPS_* entries.
+
+	* mn10300.h: Add R_MN10300_* entries.
+
+	* ppc.h: Add R_PPC_* entries.
+
+1998-07-20 07:11  Ulrich Drepper  <drepper@cygnus.com>
+
+	* mips.h: Add ODK_*, OEX_*, OPAD_*, OHW_*, and OGP_* constants.
+	Define Elf32_External_Lib.
+
+1998-07-19 15:24  Ulrich Drepper  <drepper@cygnus.com>
+
+	* mips.h (PT_MIPS_OPTIONS): New symbol.
+	Add lots of DT_MIPS_* symbols.
+
+Fri Jun 26 10:46:35 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h: New file.
+
+Thu Jun 18 19:27:56 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* common.h (EM_960, EM_V800, EM_FR20, EM_RH32, EM_MMA,
+	EM_OLD_ALPHA): Add these constants.
+
+Thu Jun 11 17:59:01 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* common.h (EM_486, EM_S370): Add these constants.
+
+Tue Jun  9 09:35:29 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* common.h (EM_ARM): Add this constant.
+
+Wed May  6 09:45:30 1998  Gavin Koch  <gavin@cygnus.com>
+
+	* mips.h (EF_MIPS_MACH,E_MIPS_MACH_*): Added.
+
+Sat Apr 25 18:35:06 1998  Richard Henderson  <rth@cygnus.com>
+
+	* alpha.h (STO_ALPHA_NOPV, STO_ALPHA_STD_GPLOAD): New.
+
+Wed Apr 15 15:42:45 1998  Richard Henderson  <rth@cygnus.com>
+
+	* common.h (EM_SPARC64): Move and rename to EM_OLD_SPARCV9.
+	(EM_SPARCV9): New.  This is the official ABI name and number.
+
+Sat Feb 28 17:04:41 1998  Richard Henderson  <rth@cygnus.com>
+
+	* alpha.h (EF_ALPHA_32BIT, EF_ALPHA_CANRELAX): New.
+
+Mon Dec 15 15:07:49 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* m32r.h (EF_M32R_ARCH, E_M32R_ARCH): New flags to
+	specify machine architecture.
+
+Fri Dec  5 11:20:08 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h: New constants: SHN_V850_SCOMMON, SHN_V850_TCOMMON,
+	SHN_V850_ZCOMMON, SHT_V850_SCOMMON, SHT_V850_TCOMMON,
+	SHT_V850_ZCOMMON to handle v850 common sections.
+	enum reloc_type renamed to v850_reloc_type to avoid name
+	conflict.
+
+Thu Oct 23 13:55:24 1997  Richard Henderson  <rth@cygnus.com>
+
+	* sparc.h (enum elf_sparc_reloc_type): Add UA64 & UA16.
+
+Thu Oct 23 00:42:04 1997  Richard Henderson  <rth@dot.cygnus.com>
+
+	* sparc.h (DT_SPARC_REGISTER): New macro.
+	(DT_SPARC_PLTFMT): In support of old sparc64-linux .plts; will
+	go away soon.
+
+Tue Sep 30 13:26:58 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* sparc.h (EF_SPARC_HAL_R1, EF_SPARC_EXT_MASK): New macros.
+	(EF_SPARCV9_{MM,TSO,PSO,RMO}): New macros.
+	(SHN_BEFORE,SHN_AFTER): New macros.
+	(SHF_EXCLUDE,SHF_ORDERED): New macros.
+	(STT_REGISTER): New macro.
+	(R_SPARC_GLOB_JMP): Deleted, but slot reserved.
+	(R_SPARC_{DISP64,PLT64,HIX22,LOX10}): New relocations.
+	(R_SPARC_{H44,M44,L44,REGISTER}): New relocations.
+	(ELF64_R_TYPE_{DATA,ID,INFO}): New macros.
+
+Wed Sep 17 16:41:42 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h: Add R_V850_CALLT_6_7_OFFSET and R_V850_CALLT_16_16_OFFSET.
+
+Tue Sep 16 14:16:17 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (reloc_type): Add R_V850_TDA_16_16_OFFSET.
+
+Wed Sep  3 15:11:14 1997  Richard Henderson  <rth@cygnus.com>
+
+	* mips.h: Correct typo in comment.
+
+Wed Sep  3 11:25:57 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (reloc_type): Remove R_V850_16_PCREL.
+
+Tue Sep  2 17:41:05 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* common.h: Remove magic number for V850E.
+	* common.h: Remove magic number for V850EA.
+	* v850.h: Add new flags for e_flags field in elf header.
+
+Mon Aug 25 16:06:47 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* common.h (EM_CYGNUS_V850E): backend magic number for v850e.
+	* common.h (EM_CYGNUS_V850EA): backend magic number for v850ea.
+
+Mon Aug 18 11:05:23 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (reloc_type): Add 16 bit PC relative relocation.
+
+Fri Aug 15 05:10:09 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* arc.h (enum reloc): Move here from elf32-arc.c.
+
+Fri Aug  8 17:05:29 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* arc.h: New file.
+	* common.h (EM_CYGNUS_ARC): Define.
+
+Mon Jun 16 14:46:12 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* internal.h (Elf_Internal_Ehdr): Change e_phoff and e_shoff from
+	bfd_signed_vma to bfd_size_type, as they are not signed.
+
+Wed Mar  5 15:35:26 1997  Doug Evans  <dje@seba.cygnus.com>
+
+	* m32r.h (SHF_M32R_CAN_RELAX): Define.
+
+Mon Feb 24 17:49:01 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* external.h: Dump the 32/64 bit specific forms of the version
+	structures, and just define them as size independent.
+
+	* common.h (VERSYM_HIDDEN, VERSYM_VERSION): Define.
+
+Fri Feb 21 13:00:34 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* m32r.h (enum reloc_type): Add R_M32R_SDA16.
+	(SHN_M32R_SCOMMON): Define.
+
+Wed Feb 19 15:35:31 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	From Eric Youngdale <eric@andante.jic.com>:
+	* external.h, internal.h, common.h: Added new structures and
+	definitions for ELF versions.
+
+Tue Feb 18 17:40:36 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* common.h (EM_CYGNUS_D30V): Define.
+
+Mon Jan 27 11:54:44 1997  Doug Evans  <dje@seba.cygnus.com>
+
+	* m32r.h (enum reloc_type): Add R_M32R_HI16_[SU]LO,R_M32R_LO16.
+
+Fri Jan  3 11:32:51 1997  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* v850.h (V850_OTHER_{TDA_BYTE,ERROR}): New bits for the st_other
+	field.
+	(SHN_V850_*): Remove v850 specific section indexes, which are not
+	needed.
+	(enum reloc_type): Move the v850 relocations here from
+	elf32-v850.c
+
+Thu Jan  2 19:30:23 1997  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* v850.h: New file, provide V850 specific definitions.
+
+Tue Dec 31 14:44:32 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* common.h (DT_AUXILIARY): Define.
+	(DT_FILTER): Define.
+
+Wed Dec  4 05:03:37 1996  Jason Merrill  <jason@yorick.cygnus.com>
+
+	* dwarf2.h: Update.
+
+Tue Nov 26 10:44:47 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (STO_MIPS16): Define.
+
+Tue Nov 12 15:45:42 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h: Remove empty file.
+
+Tue Oct  8 11:31:24 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (EF_MIPS_ABI2): Define.
+
+Thu Oct  3 10:01:40 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* common.h: Break mn10x00 support into mn10200 and mn10300.
+
+Wed Oct  2 21:26:43 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* common.h (EM_CYGNUS_MN10x00): Define.
+
+Mon Sep 23 09:18:04 1996  Doug Evans  <dje@seba.cygnus.com>
+
+	* m32r.h: New file.
+
+Fri Aug 30 17:06:21 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* common.h (EM_SH): Define.
+
+Tue Aug 20 14:47:54 1996  J.T. Conklin  <jtc@hippo.cygnus.com>
+
+	* common.h (EM_CYGNUS_V850): Define.
+
+Mon Aug 19 10:59:10 1996  Doug Evans  <dje@canuck.cygnus.com>
+
+	* common.h (EM_CYGNUS_M32R): Define.
+
+Mon Jul 22 18:59:55 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (SHT_MIPS_IFACE, SHT_MIPS_CONTENT): Define.
+	(SHT_MIPS_SYMBOL_LIB): Define.
+	(SHF_MIPS_MERGE, SHF_MIPS_ADDR32, SHF_MIPS_ADDR64): Define.
+	(SHF_MIPS_NOSTRIP, SHF_MIPS_LOCAL, SHF_MIPS_NAMES): Define.
+
+Thu Jul 18 19:12:15 1996  Stan Shebs  <shebs@andros.cygnus.com>
+
+	* dwarf2.h: New file.
+
+Jul 18 13:20:39 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* common.h (EM_CYGNUS_D10V): Define.
+	* d10v.h: New file.
+
+Fri Jun 21 12:33:24 1996  Richard Henderson  <rth@tamu.edu>
+
+	* alpha.h: New file.
+	* common.h (EM_ALPHA): Define.
+
+Fri May 31 17:28:05 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (Elf_External_Options, Elf_Internal_Options): Define.
+	(bfd_mips_elf_swap_options_in): Declare.
+	(bfd_mips_elf_swap_options_out): Declare.
+	(ODK_*): Define.
+	(Elf64_External_RegInfo, Elf64_Internal_RegInfo): Define.
+	(bfd_mips_elf64_swap_reginfo_in): Declare.
+	(bfd_mips_elf64_swap_reginfo_out): Declare.
+
+Thu May 30 12:35:57 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (E_MIPS_ARCH_4): Define.
+
+Wed May 29 15:35:33 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (Elf64_Mips_External_Rel): Define.
+	(Elf64_Mips_Internal_Rel): Define.
+	(Elf64_Mips_External_Rela, Elf64_Mips_Internal_Rela): Define.
+	(RSS_*): Define.
+
+Mon Apr 22 18:26:30 1996  Doug Evans  <dje@canuck.cygnus.com>
+
+	* sparc.h (R_SPARC_[56]): Always define.
+
+Mon Feb 19 01:55:56 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+	* sparc.h (R_SPARC_{PLT32,HIPLT22,LOPLT10,PCPLT32,PCPLT22,
+	PCPLT10,5,6}): Don't define ifdef SPARC64_OLD_RELOCS.
+
+Tue Feb  6 11:33:58 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+	* sparc.h (enum sparc_elf_reloc_type): Define.
+
+Wed Jan 17 09:09:16 1996  Doug Evans  <dje@canuck.cygnus.com>
+
+	* common.h: Define EM_SPARC32PLUS.
+	* sparc.h: New file.
+
+Thu Jan 11 16:27:34 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* ppc.h (SHF_EXCLUDE, SHT_ORDERED): New fields from the abi.
+
+Thu Nov 30 16:47:18 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* internal.h (struct elf_segment_map): Add includes_filehdr and
+	includes_phdrs fields.
+
+Tue Nov 28 16:58:10 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* internal.h (struct elf_segment_map): Define.
+
+Tue Oct 31 15:19:36 1995  Fred Fish  <fnf@cygnus.com>
+
+	* common.h, dwarf.h, external.h, hppa.h, internal.h,
+	mips.h, ppc.h:  Protect against multiple inclusions.
+
+Thu Sep 21 13:51:58 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* ppc.h (EF_PPC_RELOCATABLE_LIB): Add new flag bit.
+
+Fri Sep  1 15:32:17 1995  Kazumoto Kojima  <kkojima@info.kanagawa-u.ac.jp>
+
+	* mips.h: Add some definitions used on Irix 5.
+
+Tue Jun 20 10:18:28 1995  Jeff Law  (law@snake.cs.utah.edu)
+
+	* hppa.h (CPU_PA_RISC1_0): Protect from redefinitions.
+	(CPU_PA_RISC1_1): Likewise.
+
+Wed Mar  8 18:14:37 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* ppc.h: New file for PowerPC support.
+
+Tue Feb 14 13:59:13 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* common.h (EM_PPC): Use offical value of 20, not 17.
+	(EM_PPC_OLD): Define this to be the old value of EM_PPC.
+
+Tue Jan 24 09:40:59 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* common.h (EM_PPC): New macro, PowerPC machine id.
+
+Tue Jan 17 10:51:38 1995  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+
+	* mips.h (SHT_MIPS_MSYM, SHT_MIPS_DWARF, SHT_MIPS_EVENTS): Define.
+
+Mon Oct 17 13:43:59 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+
+	* internal.h (Elf_Internal_Shdr): Remove rawdata and size fields.
+	Add bfd_section field.
+
+Tue May 24 16:11:50 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h (Elf32_External_gptab): Define.
+
+Mon May 16 13:22:04 1994  Jeff Law  (law@snake.cs.utah.edu)
+
+	* common.h (EM_HPPA): Delete.
+	(EM_PARISC): Add.
+	* hppa.h: New file.
+
+Mon May  9 13:27:03 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* common.h (SHN_LORESERVE): Rename from SHN_LORESERV.
+	(ELF32_R_TYPE, ELF32_R_INFO): Don't rely on size of unsigned char.
+	(ELF64_R_TYPE): Don't rely on size of unsigned long.
+
+Mon Apr 25 15:53:09 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* internal.h (Elf_Internal_Shdr): Use PTR, not void *.
+
+Fri Mar 11 00:34:59 1994  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
+
+	* mips.h (SHN_MIPS_TEXT, SHN_MIPS_DATA):  Define.
+
+Sat Mar  5 14:08:54 1994  Peter Schauer  (pes@regent.e-technik.tu-muenchen.de)
+
+	* internal.h:  Remove Elf32_*, Elf64_* typedefs.  These names
+	cause conflicts with system headers, e.g. link.h in gdb/solib.c.
+	Combine 32- and 64-bit versions of *_Internal_Dyn.
+	* common.h:  Replace uses of Elf64_Word, Elf64_Xword typedefs
+	by their expansion.
+	* mips.h:  Replace uses of Elf32_Word, Elf32_Sword, Elf32_Addr
+	typedefs by their expansion. Add DT_MIPS_RLD_MAP definition.
+
+Fri Feb 18 10:39:54 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* common.h (EM_CYGNUS_POWERPC): Define.  This may be temporary,
+	depending upon how quickly I can find a real PowerPC ABI.
+
+Mon Feb  7 08:27:13 1994  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* internal.h: Change HOST_64_BIT to BFD_HOST_64_BIT.
+
+Wed Feb  2 14:12:18 1994  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* common.h: Add comments regarding value of EM_HPPA and how to
+	pick an unofficial value.
+
+Wed Nov 17 17:14:26 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h (SHT_MIPS_OPTIONS): Define.
+
+Mon Nov  8 17:57:00 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h: Added some more MIPS ABI macro definitions.
+
+Wed Nov  3 22:07:17 1993  Ken Raeburn  (raeburn@rtl.cygnus.com)
+
+	* common.h (EM_MIPS_RS4_BE): New macro.
+
+Tue Oct 12 07:28:18 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* mips.h: New file.  MIPS ABI specific information.
+
+Mon Jun 21 13:13:43 1993  Ken Raeburn  (raeburn@poseidon.cygnus.com)
+
+	* internal.h: Combined 32- and 64-bit versions of all structures
+	except *_Internal_Dyn.  This will simply the assembler interface,
+	and some bfd code.
+
+Tue May 25 02:00:16 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+
+	* external.h, internal.h, common.h: Added 64-bit versions of some
+	structures and macros.  Renamed old versions to put "32" in the
+	name.  Some are unchanged.
+
+Thu Apr 29 12:12:20 1993  Ken Raeburn  (raeburn@deneb.cygnus.com)
+
+	* common.h (EM_HPPA, NT_VERSION, STN_UNDEF, DT_*): New macros.
+	* external.h (Elf_External_Dyn): New type.
+
+	* internal.h (Elf_Intenral_Shdr): New field `size'.
+	(Elf_Internal_Dyn): New type.
+
+Tue Apr 20 16:03:45 1993  Fred Fish  (fnf@cygnus.com)
+
+	* dwarf.h (LANG_CHILL):  Change value to one randomly picked in
+	the user defined range, to reduce probability of collisions.
+
+Sun Nov 15 09:34:02 1992  Fred Fish  (fnf@cygnus.com)
+
+	* dwarf.h (AT_src_coords):  Whitespace change only.
+	* dwarf.h (AT_body_begin, AT_body_end, LANG_MODULA2):
+	Add from latest gcc.
+	* dwarf.h (LANG_CHILL):  Add as GNU extension.
+
+Sat Aug  1 13:46:53 1992  Fred Fish  (fnf@cygnus.com)
+
+	* dwarf.h:  Replace with current version from gcc distribution.
+
+Fri Jun 19 19:05:09 1992  John Gilmore  (gnu at cygnus.com)
+
+	* internal.h:  Add real struct tags to all the Type_Defs, so they
+	can be used in prototypes where the Type_Defs are not known.
+
+Fri Apr  3 20:58:58 1992  Mark Eichin  (eichin at cygnus.com)
+
+	* common.h: added ELF_R_{SYM,TYPE,INFO} for handling relocation
+	info
+	added EM_MIPS, and corrected value of EM_860 based on System V ABI
+	manual.
+
+	* external.h: added Elf_External_{Rel,Rela}.
+
+	* internal.h: added Elf_Internal_{Rel,Rela}.
+	added rawdata to Elf_Internal_Shdr.
+
+Sat Nov 30 20:43:59 1991  Steve Chamberlain  (sac at rtl.cygnus.com)
+
+	* common.h, dwarf.h, external.h, internal.h, ChangeLog; moved from
+	../elf-<foo>
+
+
+Copyright (C) 1991-2003 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.25/include/elf/aarch64.h b/binutils-2.25/include/elf/aarch64.h
new file mode 100644
index 00000000..41016038
--- /dev/null
+++ b/binutils-2.25/include/elf/aarch64.h
@@ -0,0 +1,327 @@
+/* AArch64 ELF support for BFD.
+
+   Copyright 2009, 2010, 2011, 2012  Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is part of GNU Binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the license, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; see the file COPYING3. If not,
+   see <http://www.gnu.org/licenses/>.  */
+
+#ifndef _ELF_AARCH64_H
+#define _ELF_AARCH64_H
+
+#include "elf/reloc-macros.h"
+
+/* Processor specific program header types.  */
+#define PT_AARCH64_ARCHEXT	(PT_LOPROC + 0)
+
+/* Additional section types.  */
+#define SHT_AARCH64_ATTRIBUTES	0x70000003  /* Section holds attributes.  */
+
+/* AArch64-specific values for sh_flags.  */
+#define SHF_ENTRYSECT		0x10000000   /* Section contains an
+						entry point.  */
+#define SHF_COMDEF		0x80000000   /* Section may be multiply defined
+						in the input to a link step.  */
+
+/* Relocation types.  */
+
+START_RELOC_NUMBERS (elf_aarch64_reloc_type)
+
+/* Null relocations.  */
+RELOC_NUMBER (R_AARCH64_NONE, 0) /* No reloc */
+
+/* Basic data relocations.  */
+
+/* .word:  (S+A) */
+RELOC_NUMBER (R_AARCH64_P32_ABS32, 1)
+
+/* .half: (S+A) */
+RELOC_NUMBER (R_AARCH64_P32_ABS16, 2)
+
+/* .word: (S+A-P) */
+RELOC_NUMBER (R_AARCH64_P32_PREL32, 3)
+
+/* .half:  (S+A-P) */
+RELOC_NUMBER (R_AARCH64_P32_PREL16, 4)
+
+/* Group relocations to create a 16, 32, 48 or 64 bit
+   unsigned data or abs address inline.  */
+
+/* MOV[ZK]:   ((S+A) >>  0) & 0xffff */
+RELOC_NUMBER (R_AARCH64_P32_MOVW_UABS_G0, 5)
+
+/* MOV[ZK]:   ((S+A) >>  0) & 0xffff */
+RELOC_NUMBER (R_AARCH64_P32_MOVW_UABS_G0_NC, 6)
+
+/* MOV[ZK]:   ((S+A) >> 16) & 0xffff */
+RELOC_NUMBER (R_AARCH64_P32_MOVW_UABS_G1, 7)
+
+/* Group relocations to create high part of a 16, 32, 48 or 64 bit
+   signed data or abs address inline. Will change instruction
+   to MOVN or MOVZ depending on sign of calculated value.  */
+
+/* MOV[ZN]:   ((S+A) >>  0) & 0xffff */
+RELOC_NUMBER (R_AARCH64_P32_MOVW_SABS_G0, 8)
+
+/* Relocations to generate 19, 21 and 33 bit PC-relative load/store
+   addresses: PG(x) is (x & ~0xfff).  */
+
+/* LD-lit: ((S+A-P) >> 2) & 0x7ffff */
+RELOC_NUMBER (R_AARCH64_P32_LD_PREL_LO19, 9)
+
+/* ADR:    (S+A-P) & 0x1fffff */
+RELOC_NUMBER (R_AARCH64_P32_ADR_PREL_LO21, 10)
+
+/* ADRH:   ((PG(S+A)-PG(P)) >> 12) & 0x1fffff */
+RELOC_NUMBER (R_AARCH64_P32_ADR_PREL_PG_HI21, 11)
+
+/* ADD:    (S+A) & 0xfff */
+RELOC_NUMBER (R_AARCH64_P32_ADD_ABS_LO12_NC, 12)
+
+/* LD/ST8: (S+A) & 0xfff */
+RELOC_NUMBER (R_AARCH64_P32_LDST8_ABS_LO12_NC, 13)
+
+/* LD/ST16: (S+A) & 0xffe */
+RELOC_NUMBER (R_AARCH64_P32_LDST16_ABS_LO12_NC, 14)
+
+/* LD/ST32: (S+A) & 0xffc */
+RELOC_NUMBER (R_AARCH64_P32_LDST32_ABS_LO12_NC, 15)
+
+/* LD/ST64: (S+A) & 0xff8 */
+RELOC_NUMBER (R_AARCH64_P32_LDST64_ABS_LO12_NC, 16)
+
+/* LD/ST128: (S+A) & 0xff0 */
+RELOC_NUMBER (R_AARCH64_P32_LDST128_ABS_LO12_NC, 17)
+
+/* Relocations for control-flow instructions.  */
+
+/* TBZ/NZ: ((S+A-P) >> 2) & 0x3fff.  */
+RELOC_NUMBER (R_AARCH64_P32_TSTBR14, 18)
+
+/* B.cond: ((S+A-P) >> 2) & 0x7ffff.  */
+RELOC_NUMBER (R_AARCH64_P32_CONDBR19, 19)
+
+/* B:      ((S+A-P) >> 2) & 0x3ffffff.  */
+RELOC_NUMBER (R_AARCH64_P32_JUMP26, 20)
+
+/* BL:     ((S+A-P) >> 2) & 0x3ffffff.  */
+RELOC_NUMBER (R_AARCH64_P32_CALL26, 21)
+
+
+RELOC_NUMBER (R_AARCH64_P32_GOT_LD_PREL19, 25)
+RELOC_NUMBER (R_AARCH64_P32_ADR_GOT_PAGE, 26)
+RELOC_NUMBER (R_AARCH64_P32_LD32_GOT_LO12_NC, 27)
+
+
+RELOC_NUMBER (R_AARCH64_P32_TLSGD_ADR_PAGE21, 81)
+RELOC_NUMBER (R_AARCH64_P32_TLSGD_ADD_LO12_NC, 82)
+RELOC_NUMBER (R_AARCH64_P32_TLSIE_ADR_GOTTPREL_PAGE21, 103)
+RELOC_NUMBER (R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC, 104)
+RELOC_NUMBER (R_AARCH64_P32_TLSIE_LD_GOTTPREL_PREL19, 105)
+RELOC_NUMBER (R_AARCH64_P32_TLSLE_MOVW_TPREL_G1, 106)
+RELOC_NUMBER (R_AARCH64_P32_TLSLE_MOVW_TPREL_G0, 107)
+RELOC_NUMBER (R_AARCH64_P32_TLSLE_MOVW_TPREL_G0_NC, 108)
+RELOC_NUMBER (R_AARCH64_P32_TLSLE_ADD_TPREL_HI12, 109)
+RELOC_NUMBER (R_AARCH64_P32_TLSLE_ADD_TPREL_LO12, 110)
+RELOC_NUMBER (R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC, 111)
+
+RELOC_NUMBER (R_AARCH64_P32_TLSDESC_LD_PREL19, 122)
+RELOC_NUMBER (R_AARCH64_P32_TLSDESC_ADR_PREL21, 123)
+RELOC_NUMBER (R_AARCH64_P32_TLSDESC_ADR_PAGE21, 124)
+RELOC_NUMBER (R_AARCH64_P32_TLSDESC_LD32_LO12_NC, 125)
+RELOC_NUMBER (R_AARCH64_P32_TLSDESC_ADD_LO12_NC, 126)
+RELOC_NUMBER (R_AARCH64_P32_TLSDESC_CALL, 127)
+
+/* Dynamic relocations */
+
+/* Copy symbol at runtime.  */
+RELOC_NUMBER (R_AARCH64_P32_COPY, 180)
+
+/* Create GOT entry.  */
+RELOC_NUMBER (R_AARCH64_P32_GLOB_DAT, 181)
+
+ /* Create PLT entry.  */
+RELOC_NUMBER (R_AARCH64_P32_JUMP_SLOT, 182)
+
+/* Adjust by program base.  */
+RELOC_NUMBER (R_AARCH64_P32_RELATIVE, 183)
+RELOC_NUMBER (R_AARCH64_P32_TLS_DTPMOD, 184)
+RELOC_NUMBER (R_AARCH64_P32_TLS_DTPREL, 185)
+RELOC_NUMBER (R_AARCH64_P32_TLS_TPREL, 186)
+RELOC_NUMBER (R_AARCH64_P32_TLSDESC, 187)
+RELOC_NUMBER (R_AARCH64_P32_IRELATIVE, 188)
+
+RELOC_NUMBER (R_AARCH64_NULL, 256) /* No reloc */
+
+/* Basic data relocations.  */
+
+/* .xword: (S+A) */
+RELOC_NUMBER (R_AARCH64_ABS64, 257)
+
+/* .word:  (S+A) */
+RELOC_NUMBER (R_AARCH64_ABS32, 258)
+
+/* .half: (S+A) */
+RELOC_NUMBER (R_AARCH64_ABS16, 259)
+
+/* .xword: (S+A-P) */
+RELOC_NUMBER (R_AARCH64_PREL64, 260)
+
+/* .word: (S+A-P) */
+RELOC_NUMBER (R_AARCH64_PREL32, 261)
+
+/* .half:  (S+A-P) */
+RELOC_NUMBER (R_AARCH64_PREL16, 262)
+
+/* Group relocations to create a 16, 32, 48 or 64 bit
+   unsigned data or abs address inline.  */
+
+/* MOV[ZK]:   ((S+A) >>  0) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_UABS_G0,		263)
+
+/* MOV[ZK]:   ((S+A) >>  0) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_UABS_G0_NC, 264)
+
+/* MOV[ZK]:   ((S+A) >> 16) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_UABS_G1, 265)
+
+/* MOV[ZK]:   ((S+A) >> 16) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_UABS_G1_NC, 266)
+
+/* MOV[ZK]:   ((S+A) >> 32) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_UABS_G2, 267)
+
+/* MOV[ZK]:   ((S+A) >> 32) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_UABS_G2_NC, 268)
+
+/* MOV[ZK]:   ((S+A) >> 48) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_UABS_G3, 269)
+
+/* Group relocations to create high part of a 16, 32, 48 or 64 bit
+   signed data or abs address inline. Will change instruction
+   to MOVN or MOVZ depending on sign of calculated value.  */
+
+/* MOV[ZN]:   ((S+A) >>  0) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_SABS_G0, 270)
+
+/* MOV[ZN]:   ((S+A) >> 16) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_SABS_G1, 271)
+
+/* MOV[ZN]:   ((S+A) >> 32) & 0xffff */
+RELOC_NUMBER (R_AARCH64_MOVW_SABS_G2, 272)
+
+/* Relocations to generate 19, 21 and 33 bit PC-relative load/store
+   addresses: PG(x) is (x & ~0xfff).  */
+
+/* LD-lit: ((S+A-P) >> 2) & 0x7ffff */
+RELOC_NUMBER (R_AARCH64_LD_PREL_LO19, 273)
+
+/* ADR:    (S+A-P) & 0x1fffff */
+RELOC_NUMBER (R_AARCH64_ADR_PREL_LO21, 274)
+
+/* ADRH:   ((PG(S+A)-PG(P)) >> 12) & 0x1fffff */
+RELOC_NUMBER (R_AARCH64_ADR_PREL_PG_HI21, 275)
+
+/* ADRH:   ((PG(S+A)-PG(P)) >> 12) & 0x1fffff */
+RELOC_NUMBER (R_AARCH64_ADR_PREL_PG_HI21_NC, 276)
+
+/* ADD:    (S+A) & 0xfff */
+RELOC_NUMBER (R_AARCH64_ADD_ABS_LO12_NC, 277)
+
+/* LD/ST8: (S+A) & 0xfff */
+RELOC_NUMBER (R_AARCH64_LDST8_ABS_LO12_NC, 278)
+
+/* Relocations for control-flow instructions.  */
+
+/* TBZ/NZ: ((S+A-P) >> 2) & 0x3fff.  */
+RELOC_NUMBER (R_AARCH64_TSTBR14, 279)
+
+/* B.cond: ((S+A-P) >> 2) & 0x7ffff.  */
+RELOC_NUMBER (R_AARCH64_CONDBR19, 280)
+
+/* 281 unused */
+
+/* B:      ((S+A-P) >> 2) & 0x3ffffff.  */
+RELOC_NUMBER (R_AARCH64_JUMP26, 282)
+
+/* BL:     ((S+A-P) >> 2) & 0x3ffffff.  */
+RELOC_NUMBER (R_AARCH64_CALL26, 283)
+
+/* LD/ST16: (S+A) & 0xffe */
+RELOC_NUMBER (R_AARCH64_LDST16_ABS_LO12_NC, 284)
+
+/* LD/ST32: (S+A) & 0xffc */
+RELOC_NUMBER (R_AARCH64_LDST32_ABS_LO12_NC, 285)
+
+/* LD/ST64: (S+A) & 0xff8 */
+RELOC_NUMBER (R_AARCH64_LDST64_ABS_LO12_NC, 286)
+
+/* LD/ST128: (S+A) & 0xff0 */
+RELOC_NUMBER (R_AARCH64_LDST128_ABS_LO12_NC, 299)
+
+RELOC_NUMBER (R_AARCH64_GOT_LD_PREL19, 309)
+RELOC_NUMBER (R_AARCH64_ADR_GOT_PAGE, 311)
+RELOC_NUMBER (R_AARCH64_LD64_GOT_LO12_NC, 312)
+
+RELOC_NUMBER (R_AARCH64_TLSGD_ADR_PAGE21, 513)
+RELOC_NUMBER (R_AARCH64_TLSGD_ADD_LO12_NC, 514)
+RELOC_NUMBER (R_AARCH64_TLSIE_MOVW_GOTTPREL_G1, 539)
+RELOC_NUMBER (R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC, 540)
+RELOC_NUMBER (R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, 541)
+RELOC_NUMBER (R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, 542)
+RELOC_NUMBER (R_AARCH64_TLSIE_LD_GOTTPREL_PREL19, 543)
+RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G2, 544)
+RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G1, 545)
+RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G1_NC, 546)
+RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G0, 547)
+RELOC_NUMBER (R_AARCH64_TLSLE_MOVW_TPREL_G0_NC, 548)
+RELOC_NUMBER (R_AARCH64_TLSLE_ADD_TPREL_HI12, 549)
+RELOC_NUMBER (R_AARCH64_TLSLE_ADD_TPREL_LO12, 550)
+RELOC_NUMBER (R_AARCH64_TLSLE_ADD_TPREL_LO12_NC, 551)
+
+RELOC_NUMBER (R_AARCH64_TLSDESC_LD_PREL19, 560)
+RELOC_NUMBER (R_AARCH64_TLSDESC_ADR_PREL21, 561)
+RELOC_NUMBER (R_AARCH64_TLSDESC_ADR_PAGE21, 562)
+RELOC_NUMBER (R_AARCH64_TLSDESC_LD64_LO12_NC, 563)
+RELOC_NUMBER (R_AARCH64_TLSDESC_ADD_LO12_NC, 564)
+RELOC_NUMBER (R_AARCH64_TLSDESC_OFF_G1, 565)
+RELOC_NUMBER (R_AARCH64_TLSDESC_OFF_G0_NC, 566)
+RELOC_NUMBER (R_AARCH64_TLSDESC_LDR, 567)
+RELOC_NUMBER (R_AARCH64_TLSDESC_ADD, 568)
+RELOC_NUMBER (R_AARCH64_TLSDESC_CALL, 569)
+
+/* Dynamic relocations */
+
+/* Copy symbol at runtime.  */
+RELOC_NUMBER (R_AARCH64_COPY, 1024)
+
+/* Create GOT entry.  */
+RELOC_NUMBER (R_AARCH64_GLOB_DAT, 1025)
+
+ /* Create PLT entry.  */
+RELOC_NUMBER (R_AARCH64_JUMP_SLOT, 1026)
+
+/* Adjust by program base.  */
+RELOC_NUMBER (R_AARCH64_RELATIVE, 1027)
+RELOC_NUMBER (R_AARCH64_TLS_DTPMOD, 1028)
+RELOC_NUMBER (R_AARCH64_TLS_DTPREL, 1029)
+RELOC_NUMBER (R_AARCH64_TLS_TPREL, 1030)
+RELOC_NUMBER (R_AARCH64_TLSDESC, 1031)
+RELOC_NUMBER (R_AARCH64_IRELATIVE, 1032)
+
+END_RELOC_NUMBERS (R_AARCH64_end)
+
+#endif /* _ELF_AARCH64_H */
diff --git a/binutils-2.25/include/elf/alpha.h b/binutils-2.25/include/elf/alpha.h
new file mode 100644
index 00000000..f4fe566b
--- /dev/null
+++ b/binutils-2.25/include/elf/alpha.h
@@ -0,0 +1,131 @@
+/* ALPHA ELF support for BFD.
+   Copyright 1996, 1998, 2000, 2001, 2002, 2010 Free Software Foundation, Inc.
+
+   By Eric Youngdale, <eric@aib.com>.  No processor supplement available
+   for this platform.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file holds definitions specific to the ALPHA ELF ABI.  Note
+   that most of this is not actually implemented by BFD.  */
+
+#ifndef _ELF_ALPHA_H
+#define _ELF_ALPHA_H
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+/* All addresses must be below 2GB.  */
+#define EF_ALPHA_32BIT		0x00000001
+
+/* All relocations needed for relaxation with code movement are present.  */
+#define EF_ALPHA_CANRELAX	0x00000002
+
+/* Processor specific section flags.  */
+
+/* This section must be in the global data area.  */
+#define SHF_ALPHA_GPREL		0x10000000
+
+/* Section contains some sort of debugging information.  The exact
+   format is unspecified.  It's probably ECOFF symbols.  */
+#define SHT_ALPHA_DEBUG		0x70000001
+
+/* Section contains register usage information.  */
+#define SHT_ALPHA_REGINFO	0x70000002
+
+/* A section of type SHT_MIPS_REGINFO contains the following
+   structure.  */
+typedef struct
+{
+  /* Mask of general purpose registers used.  */
+  unsigned long ri_gprmask;
+  /* Mask of co-processor registers used.  */
+  unsigned long ri_cprmask[4];
+  /* GP register value for this object file.  */
+  long ri_gp_value;
+} Elf64_RegInfo;
+
+/* Special values for the st_other field in the symbol table.  */
+
+#define STO_ALPHA_NOPV		0x80
+#define STO_ALPHA_STD_GPLOAD	0x88
+
+/* Special values for Elf64_Dyn tag.  */
+#define DT_ALPHA_PLTRO		DT_LOPROC
+
+#include "elf/reloc-macros.h"
+
+/* Alpha relocs.  */
+START_RELOC_NUMBERS (elf_alpha_reloc_type)
+  RELOC_NUMBER (R_ALPHA_NONE, 0)	/* No reloc */
+  RELOC_NUMBER (R_ALPHA_REFLONG, 1)	/* Direct 32 bit */
+  RELOC_NUMBER (R_ALPHA_REFQUAD, 2)	/* Direct 64 bit */
+  RELOC_NUMBER (R_ALPHA_GPREL32, 3)	/* GP relative 32 bit */
+  RELOC_NUMBER (R_ALPHA_LITERAL, 4)	/* GP relative 16 bit w/optimization */
+  RELOC_NUMBER (R_ALPHA_LITUSE, 5)	/* Optimization hint for LITERAL */
+  RELOC_NUMBER (R_ALPHA_GPDISP, 6)	/* Add displacement to GP */
+  RELOC_NUMBER (R_ALPHA_BRADDR, 7)	/* PC+4 relative 23 bit shifted */
+  RELOC_NUMBER (R_ALPHA_HINT, 8)	/* PC+4 relative 16 bit shifted */
+  RELOC_NUMBER (R_ALPHA_SREL16, 9)	/* PC relative 16 bit */
+  RELOC_NUMBER (R_ALPHA_SREL32, 10)	/* PC relative 32 bit */
+  RELOC_NUMBER (R_ALPHA_SREL64, 11)	/* PC relative 64 bit */
+
+  /* Skip 12 - 16; deprecated ECOFF relocs.  */
+
+  RELOC_NUMBER (R_ALPHA_GPRELHIGH, 17)	/* GP relative 32 bit, high 16 bits */
+  RELOC_NUMBER (R_ALPHA_GPRELLOW, 18)	/* GP relative 32 bit, low 16 bits */
+  RELOC_NUMBER (R_ALPHA_GPREL16, 19)	/* GP relative 16 bit */
+
+  /* Skip 20 - 23; deprecated ECOFF relocs.  */
+
+  /* These relocations are specific to shared libraries.  */
+  RELOC_NUMBER (R_ALPHA_COPY, 24)	/* Copy symbol at runtime */
+  RELOC_NUMBER (R_ALPHA_GLOB_DAT, 25)	/* Create GOT entry */
+  RELOC_NUMBER (R_ALPHA_JMP_SLOT, 26)	/* Create PLT entry */
+  RELOC_NUMBER (R_ALPHA_RELATIVE, 27)	/* Adjust by program base */
+
+  /* Like BRADDR, but assert that the source and target object file
+     share the same GP value, and adjust the target address for 
+     STO_ALPHA_STD_GPLOAD.  */
+  RELOC_NUMBER (R_ALPHA_BRSGP, 28)
+
+  /* Thread-Local Storage.  */
+  RELOC_NUMBER (R_ALPHA_TLSGD, 29)
+  RELOC_NUMBER (R_ALPHA_TLSLDM, 30)
+  RELOC_NUMBER (R_ALPHA_DTPMOD64, 31)
+  RELOC_NUMBER (R_ALPHA_GOTDTPREL, 32)
+  RELOC_NUMBER (R_ALPHA_DTPREL64, 33)
+  RELOC_NUMBER (R_ALPHA_DTPRELHI, 34)
+  RELOC_NUMBER (R_ALPHA_DTPRELLO, 35)
+  RELOC_NUMBER (R_ALPHA_DTPREL16, 36)
+  RELOC_NUMBER (R_ALPHA_GOTTPREL, 37)
+  RELOC_NUMBER (R_ALPHA_TPREL64, 38)
+  RELOC_NUMBER (R_ALPHA_TPRELHI, 39)
+  RELOC_NUMBER (R_ALPHA_TPRELLO, 40)
+  RELOC_NUMBER (R_ALPHA_TPREL16, 41)
+
+END_RELOC_NUMBERS (R_ALPHA_max)
+
+#define LITUSE_ALPHA_ADDR	0
+#define LITUSE_ALPHA_BASE	1
+#define LITUSE_ALPHA_BYTOFF	2
+#define LITUSE_ALPHA_JSR	3
+#define LITUSE_ALPHA_TLSGD	4
+#define LITUSE_ALPHA_TLSLDM	5
+#define LITUSE_ALPHA_JSRDIRECT	6
+
+#endif /* _ELF_ALPHA_H */
diff --git a/binutils-2.25/include/elf/arc.h b/binutils-2.25/include/elf/arc.h
new file mode 100644
index 00000000..a07ed2e3
--- /dev/null
+++ b/binutils-2.25/include/elf/arc.h
@@ -0,0 +1,57 @@
+/* ARC ELF support for BFD.
+   Copyright 1995, 1997, 1998, 2000, 2001, 2010 Free Software Foundation, Inc.
+   Contributed by Doug Evans, (dje@cygnus.com)
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file holds definitions specific to the ARC ELF ABI.  */
+
+#ifndef _ELF_ARC_H
+#define _ELF_ARC_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+
+START_RELOC_NUMBERS (elf_arc_reloc_type)
+  RELOC_NUMBER (R_ARC_NONE, 0)
+  RELOC_NUMBER (R_ARC_32, 1)
+  RELOC_NUMBER (R_ARC_B26, 2)
+  RELOC_NUMBER (R_ARC_B22_PCREL, 3)
+END_RELOC_NUMBERS (R_ARC_max)
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+/* Four bit ARC machine type field.  */
+
+#define EF_ARC_MACH 0x0000000f
+
+/* Various CPU types.  */
+
+#define E_ARC_MACH_ARC5 0
+#define E_ARC_MACH_ARC6 1	
+#define E_ARC_MACH_ARC7 2
+#define E_ARC_MACH_ARC8 3
+
+/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types.  */
+
+/* File contains position independent code.  */
+
+#define EF_ARC_PIC 0x00000100
+
+#endif /* _ELF_ARC_H */
diff --git a/binutils-2.25/include/elf/arm.h b/binutils-2.25/include/elf/arm.h
new file mode 100644
index 00000000..d7993038
--- /dev/null
+++ b/binutils-2.25/include/elf/arm.h
@@ -0,0 +1,344 @@
+/* ARM ELF support for BFD.
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2009, 2010
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_ARM_H
+#define _ELF_ARM_H
+
+#include "elf/reloc-macros.h"
+
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_ARM_RELEXEC     0x01
+#define EF_ARM_HASENTRY    0x02
+#define EF_ARM_INTERWORK   0x04
+#define EF_ARM_APCS_26     0x08
+#define EF_ARM_APCS_FLOAT  0x10
+#define EF_ARM_PIC         0x20
+#define EF_ARM_ALIGN8	   0x40		/* 8-bit structure alignment is in use.  */
+#define EF_ARM_NEW_ABI     0x80
+#define EF_ARM_OLD_ABI     0x100
+#define EF_ARM_SOFT_FLOAT  0x200
+#define EF_ARM_VFP_FLOAT   0x400
+#define EF_ARM_MAVERICK_FLOAT 0x800
+
+/* Frame unwind information */
+#define PT_ARM_EXIDX (PT_LOPROC + 1)
+
+/* Other constants defined in the ARM ELF spec. version B-01.  */
+#define EF_ARM_SYMSARESORTED 0x04	/* NB conflicts with EF_INTERWORK.  */
+#define EF_ARM_DYNSYMSUSESEGIDX 0x08	/* NB conflicts with EF_APCS26.  */
+#define EF_ARM_MAPSYMSFIRST 0x10	/* NB conflicts with EF_APCS_FLOAT.  */
+#define EF_ARM_EABIMASK      0xFF000000
+
+/* New constants defined in the ARM ELF spec. version XXX.
+   Only valid in conjunction with EF_ARM_EABI_VER5. */
+#define EF_ARM_ABI_FLOAT_SOFT 0x200	/* NB conflicts with EF_ARM_SOFT_FLOAT.  */
+#define EF_ARM_ABI_FLOAT_HARD 0x400	/* NB conflicts with EF_ARM_VFP_FLOAT.  */
+
+/* Constants defined in AAELF.  */
+#define EF_ARM_BE8	    0x00800000
+#define EF_ARM_LE8	    0x00400000
+
+#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK)
+#define EF_ARM_EABI_UNKNOWN  0x00000000
+#define EF_ARM_EABI_VER1     0x01000000
+#define EF_ARM_EABI_VER2     0x02000000
+#define EF_ARM_EABI_VER3     0x03000000
+#define EF_ARM_EABI_VER4     0x04000000
+#define EF_ARM_EABI_VER5     0x05000000
+
+/* Local aliases for some flags to match names used by COFF port.  */
+#define F_INTERWORK	   EF_ARM_INTERWORK
+#define F_APCS26	   EF_ARM_APCS_26
+#define F_APCS_FLOAT	   EF_ARM_APCS_FLOAT
+#define F_PIC              EF_ARM_PIC
+#define F_SOFT_FLOAT	   EF_ARM_SOFT_FLOAT
+#define F_VFP_FLOAT	   EF_ARM_VFP_FLOAT
+
+/* Additional symbol types for Thumb.  */
+#define STT_ARM_TFUNC      STT_LOPROC   /* A Thumb function.  */
+#define STT_ARM_16BIT      STT_HIPROC   /* A Thumb label.  */
+
+/* Additional section types.  */
+#define SHT_ARM_EXIDX	       0x70000001	/* Section holds ARM unwind info.  */
+#define SHT_ARM_PREEMPTMAP     0x70000002	/* Section pre-emption details.  */
+#define SHT_ARM_ATTRIBUTES     0x70000003	/* Section holds attributes.  */
+#define SHT_ARM_DEBUGOVERLAY   0x70000004	/* Section holds overlay debug info.  */
+#define SHT_ARM_OVERLAYSECTION 0x70000005	/* Section holds GDB and overlay integration info.  */
+
+/* ARM-specific values for sh_flags.  */
+#define SHF_ENTRYSECT      0x10000000   /* Section contains an entry point.  */
+#define SHF_COMDEF         0x80000000   /* Section may be multiply defined in the input to a link step.  */
+
+/* ARM-specific program header flags.  */
+#define PF_ARM_SB          0x10000000   /* Segment contains the location addressed by the static base.  */
+#define PF_ARM_PI          0x20000000   /* Segment is position-independent.  */
+#define PF_ARM_ABS         0x40000000   /* Segment must be loaded at its base address.  */
+
+/* Values for the Tag_CPU_arch EABI attribute.  */
+#define TAG_CPU_ARCH_PRE_V4	0
+#define TAG_CPU_ARCH_V4		1
+#define TAG_CPU_ARCH_V4T	2
+#define TAG_CPU_ARCH_V5T	3
+#define TAG_CPU_ARCH_V5TE	4
+#define TAG_CPU_ARCH_V5TEJ	5
+#define TAG_CPU_ARCH_V6		6
+#define TAG_CPU_ARCH_V6KZ	7
+#define TAG_CPU_ARCH_V6T2	8
+#define TAG_CPU_ARCH_V6K	9
+#define TAG_CPU_ARCH_V7		10
+#define TAG_CPU_ARCH_V6_M	11
+#define TAG_CPU_ARCH_V6S_M	12
+#define TAG_CPU_ARCH_V7E_M	13
+#define TAG_CPU_ARCH_V8		14
+#define MAX_TAG_CPU_ARCH	14
+/* Pseudo-architecture to allow objects to be compatible with the subset of
+   armv4t and armv6-m.  This value should never be stored in object files.  */
+#define TAG_CPU_ARCH_V4T_PLUS_V6_M (MAX_TAG_CPU_ARCH + 1)
+
+/* Relocation types.  */
+
+START_RELOC_NUMBERS (elf_arm_reloc_type)
+/* AAELF official names and numbers.  */
+  RELOC_NUMBER (R_ARM_NONE,            	  0)
+  RELOC_NUMBER (R_ARM_PC24,            	  1)   /* deprecated */
+  RELOC_NUMBER (R_ARM_ABS32,           	  2)
+  RELOC_NUMBER (R_ARM_REL32,           	  3)
+  RELOC_NUMBER (R_ARM_LDR_PC_G0,       	  4)
+  RELOC_NUMBER (R_ARM_ABS16,           	  5)
+  RELOC_NUMBER (R_ARM_ABS12,           	  6)
+  RELOC_NUMBER (R_ARM_THM_ABS5,        	  7)
+  RELOC_NUMBER (R_ARM_ABS8,            	  8)
+  RELOC_NUMBER (R_ARM_SBREL32,         	  9)
+  RELOC_NUMBER (R_ARM_THM_CALL,        	 10)
+  RELOC_NUMBER (R_ARM_THM_PC8,         	 11)
+  RELOC_NUMBER (R_ARM_BREL_ADJ,	       	 12)
+  RELOC_NUMBER (R_ARM_TLS_DESC,          13)
+  RELOC_NUMBER (R_ARM_THM_SWI8,        	 14)   /* obsolete */
+  RELOC_NUMBER (R_ARM_XPC25,           	 15)   /* obsolete */
+  RELOC_NUMBER (R_ARM_THM_XPC22,       	 16)   /* obsolete */
+  RELOC_NUMBER (R_ARM_TLS_DTPMOD32,    	 17)
+  RELOC_NUMBER (R_ARM_TLS_DTPOFF32,    	 18)
+  RELOC_NUMBER (R_ARM_TLS_TPOFF32,     	 19)
+  RELOC_NUMBER (R_ARM_COPY,            	 20)   /* Copy symbol at runtime.  */
+  RELOC_NUMBER (R_ARM_GLOB_DAT,        	 21)   /* Create GOT entry.  */
+  RELOC_NUMBER (R_ARM_JUMP_SLOT,       	 22)   /* Create PLT entry.  */
+  RELOC_NUMBER (R_ARM_RELATIVE,        	 23)   /* Adjust by program base.  */
+  RELOC_NUMBER (R_ARM_GOTOFF32,        	 24)   /* 32 bit offset to GOT.  */
+  RELOC_NUMBER (R_ARM_BASE_PREL,       	 25)   /* 32 bit PC relative offset to GOT.  */
+  RELOC_NUMBER (R_ARM_GOT_BREL,        	 26)   /* 32 bit GOT entry.  */
+  RELOC_NUMBER (R_ARM_PLT32,           	 27)   /* deprecated - 32 bit PLT address.  */
+  RELOC_NUMBER (R_ARM_CALL,            	 28)
+  RELOC_NUMBER (R_ARM_JUMP24,          	 29)
+  RELOC_NUMBER (R_ARM_THM_JUMP24,      	 30)
+  RELOC_NUMBER (R_ARM_BASE_ABS,        	 31)
+  RELOC_NUMBER (R_ARM_ALU_PCREL7_0,    	 32)   /* obsolete */
+  RELOC_NUMBER (R_ARM_ALU_PCREL15_8,   	 33)   /* obsolete */
+  RELOC_NUMBER (R_ARM_ALU_PCREL23_15,  	 34)   /* obsolete */
+  RELOC_NUMBER (R_ARM_LDR_SBREL_11_0,  	 35)   /* deprecated, should have _NC suffix */
+  RELOC_NUMBER (R_ARM_ALU_SBREL_19_12, 	 36)   /* deprecated, should have _NC suffix */
+  RELOC_NUMBER (R_ARM_ALU_SBREL_27_20, 	 37)   /* deprecated, should have _CK suffix */
+  RELOC_NUMBER (R_ARM_TARGET1,         	 38)
+  RELOC_NUMBER (R_ARM_SBREL31,         	 39)   /* deprecated */
+  RELOC_NUMBER (R_ARM_V4BX,            	 40)
+  RELOC_NUMBER (R_ARM_TARGET2,	       	 41)
+  RELOC_NUMBER (R_ARM_PREL31,	       	 42)
+  RELOC_NUMBER (R_ARM_MOVW_ABS_NC,     	 43)
+  RELOC_NUMBER (R_ARM_MOVT_ABS,        	 44)
+  RELOC_NUMBER (R_ARM_MOVW_PREL_NC,    	 45)
+  RELOC_NUMBER (R_ARM_MOVT_PREL,       	 46)
+  RELOC_NUMBER (R_ARM_THM_MOVW_ABS_NC, 	 47)
+  RELOC_NUMBER (R_ARM_THM_MOVT_ABS,    	 48)
+  RELOC_NUMBER (R_ARM_THM_MOVW_PREL_NC,	 49)
+  RELOC_NUMBER (R_ARM_THM_MOVT_PREL,   	 50)
+  RELOC_NUMBER (R_ARM_THM_JUMP19,      	 51)
+  RELOC_NUMBER (R_ARM_THM_JUMP6,       	 52)
+  RELOC_NUMBER (R_ARM_THM_ALU_PREL_11_0, 53)
+  RELOC_NUMBER (R_ARM_THM_PC12,        	 54)
+  RELOC_NUMBER (R_ARM_ABS32_NOI,       	 55)
+  RELOC_NUMBER (R_ARM_REL32_NOI,       	 56)
+  RELOC_NUMBER (R_ARM_ALU_PC_G0_NC,      57)
+  RELOC_NUMBER (R_ARM_ALU_PC_G0,         58)
+  RELOC_NUMBER (R_ARM_ALU_PC_G1_NC,      59)
+  RELOC_NUMBER (R_ARM_ALU_PC_G1,         60)
+  RELOC_NUMBER (R_ARM_ALU_PC_G2,         61)
+  RELOC_NUMBER (R_ARM_LDR_PC_G1,         62)
+  RELOC_NUMBER (R_ARM_LDR_PC_G2,         63)
+  RELOC_NUMBER (R_ARM_LDRS_PC_G0,        64)
+  RELOC_NUMBER (R_ARM_LDRS_PC_G1,        65)
+  RELOC_NUMBER (R_ARM_LDRS_PC_G2,        66)
+  RELOC_NUMBER (R_ARM_LDC_PC_G0,         67)
+  RELOC_NUMBER (R_ARM_LDC_PC_G1,         68)
+  RELOC_NUMBER (R_ARM_LDC_PC_G2,         69)
+  RELOC_NUMBER (R_ARM_ALU_SB_G0_NC,      70)
+  RELOC_NUMBER (R_ARM_ALU_SB_G0,         71)
+  RELOC_NUMBER (R_ARM_ALU_SB_G1_NC,      72)
+  RELOC_NUMBER (R_ARM_ALU_SB_G1,         73)
+  RELOC_NUMBER (R_ARM_ALU_SB_G2,         74)
+  RELOC_NUMBER (R_ARM_LDR_SB_G0,         75)
+  RELOC_NUMBER (R_ARM_LDR_SB_G1,         76)
+  RELOC_NUMBER (R_ARM_LDR_SB_G2,         77)
+  RELOC_NUMBER (R_ARM_LDRS_SB_G0,        78)
+  RELOC_NUMBER (R_ARM_LDRS_SB_G1,        79)
+  RELOC_NUMBER (R_ARM_LDRS_SB_G2,        80)
+  RELOC_NUMBER (R_ARM_LDC_SB_G0,         81)
+  RELOC_NUMBER (R_ARM_LDC_SB_G1,         82)
+  RELOC_NUMBER (R_ARM_LDC_SB_G2,         83)
+  RELOC_NUMBER (R_ARM_MOVW_BREL_NC,    	 84)
+  RELOC_NUMBER (R_ARM_MOVT_BREL,       	 85)
+  RELOC_NUMBER (R_ARM_MOVW_BREL,       	 86)
+  RELOC_NUMBER (R_ARM_THM_MOVW_BREL_NC,	 87)
+  RELOC_NUMBER (R_ARM_THM_MOVT_BREL,   	 88)
+  RELOC_NUMBER (R_ARM_THM_MOVW_BREL,   	 89)
+  RELOC_NUMBER (R_ARM_TLS_GOTDESC,       90)
+  RELOC_NUMBER (R_ARM_TLS_CALL,          91)
+  RELOC_NUMBER (R_ARM_TLS_DESCSEQ,       92)
+  RELOC_NUMBER (R_ARM_THM_TLS_CALL,      93)
+  RELOC_NUMBER (R_ARM_PLT32_ABS,       	 94)
+  RELOC_NUMBER (R_ARM_GOT_ABS,	       	 95)
+  RELOC_NUMBER (R_ARM_GOT_PREL,	       	 96)
+  RELOC_NUMBER (R_ARM_GOT_BREL12,      	 97)
+  RELOC_NUMBER (R_ARM_GOTOFF12,	       	 98)
+  RELOC_NUMBER (R_ARM_GOTRELAX,	       	 99)
+  RELOC_NUMBER (R_ARM_GNU_VTENTRY,    	100)   /* deprecated - old C++ abi */
+  RELOC_NUMBER (R_ARM_GNU_VTINHERIT,  	101)   /* deprecated - old C++ abi */
+  RELOC_NUMBER (R_ARM_THM_JUMP11,     	102)
+  RELOC_NUMBER (R_ARM_THM_JUMP8,      	103)
+  RELOC_NUMBER (R_ARM_TLS_GD32,	      	104)
+  RELOC_NUMBER (R_ARM_TLS_LDM32,      	105)
+  RELOC_NUMBER (R_ARM_TLS_LDO32,      	106)
+  RELOC_NUMBER (R_ARM_TLS_IE32,       	107)
+  RELOC_NUMBER (R_ARM_TLS_LE32,	      	108)
+  RELOC_NUMBER (R_ARM_TLS_LDO12,      	109)
+  RELOC_NUMBER (R_ARM_TLS_LE12,	      	110)
+  RELOC_NUMBER (R_ARM_TLS_IE12GP,     	111)
+  /* 112 - 127 private range */
+  RELOC_NUMBER (R_ARM_ME_TOO,	        128)   /* obsolete */
+  RELOC_NUMBER (R_ARM_THM_TLS_DESCSEQ  ,129)
+
+  RELOC_NUMBER (R_ARM_IRELATIVE,      	160)
+
+  /* Extensions?  R=read-only?  */
+  RELOC_NUMBER (R_ARM_RXPC25,         	249)
+  RELOC_NUMBER (R_ARM_RSBREL32,       	250)
+  RELOC_NUMBER (R_ARM_THM_RPC22,      	251)
+  RELOC_NUMBER (R_ARM_RREL32,         	252)
+  RELOC_NUMBER (R_ARM_RABS32,         	253)
+  RELOC_NUMBER (R_ARM_RPC24,          	254)
+  RELOC_NUMBER (R_ARM_RBASE,          	255)
+
+  /* Unofficial names for some of the relocs.  */
+  FAKE_RELOC (R_ARM_GOTOFF,             R_ARM_GOTOFF32)   /* 32 bit offset to GOT.  */
+  FAKE_RELOC (R_ARM_THM_PC22,           R_ARM_THM_CALL)
+  FAKE_RELOC (R_ARM_THM_PC11,           R_ARM_THM_JUMP11)
+  FAKE_RELOC (R_ARM_THM_PC9,            R_ARM_THM_JUMP8)
+
+  /* Relocs with both a different name, and (apparently) different meaning in
+     GNU usage.  */
+  FAKE_RELOC (R_ARM_GOTPC,              R_ARM_BASE_PREL)  /* 32 bit PC relative offset to GOT.  */
+  FAKE_RELOC (R_ARM_GOT32,              R_ARM_GOT_BREL)   /* 32 bit GOT entry.  */
+  FAKE_RELOC (R_ARM_ROSEGREL32,         R_ARM_SBREL31)    /* ??? */
+  FAKE_RELOC (R_ARM_AMP_VCALL9,         R_ARM_BREL_ADJ)   /* Thumb-something.  Not used.  */
+
+END_RELOC_NUMBERS (R_ARM_max = 256)
+
+#ifdef BFD_ARCH_SIZE
+/* EABI object attributes.  */
+
+enum
+{
+  /* 0-3 are generic.  */
+  Tag_CPU_raw_name = 4,
+  Tag_CPU_name,
+  Tag_CPU_arch,
+  Tag_CPU_arch_profile,
+  Tag_ARM_ISA_use,
+  Tag_THUMB_ISA_use,
+  Tag_FP_arch,
+  Tag_WMMX_arch,
+  Tag_Advanced_SIMD_arch,
+  Tag_PCS_config,
+  Tag_ABI_PCS_R9_use,
+  Tag_ABI_PCS_RW_data,
+  Tag_ABI_PCS_RO_data,
+  Tag_ABI_PCS_GOT_use,
+  Tag_ABI_PCS_wchar_t,
+  Tag_ABI_FP_rounding,
+  Tag_ABI_FP_denormal,
+  Tag_ABI_FP_exceptions,
+  Tag_ABI_FP_user_exceptions,
+  Tag_ABI_FP_number_model,
+  Tag_ABI_align_needed,
+  Tag_ABI_align_preserved,
+  Tag_ABI_enum_size,
+  Tag_ABI_HardFP_use,
+  Tag_ABI_VFP_args,
+  Tag_ABI_WMMX_args,
+  Tag_ABI_optimization_goals,
+  Tag_ABI_FP_optimization_goals,
+  /* 32 is generic (Tag_compatibility).  */
+  Tag_undefined33 = 33,
+  Tag_CPU_unaligned_access,
+  Tag_undefined35,
+  Tag_FP_HP_extension,
+  Tag_undefined37,
+  Tag_ABI_FP_16bit_format,
+  Tag_undefined39,
+  Tag_undefined40,
+  Tag_undefined41,
+  Tag_MPextension_use,
+  Tag_undefined_43,
+  Tag_DIV_use,
+  Tag_nodefaults = 64,
+  Tag_also_compatible_with,
+  Tag_T2EE_use,
+  Tag_conformance,
+  Tag_Virtualization_use,
+  Tag_undefined69,
+  Tag_MPextension_use_legacy,
+
+  /* The following tags are legacy names for other tags.  */
+  Tag_VFP_arch = Tag_FP_arch,
+  Tag_ABI_align8_needed = Tag_ABI_align_needed,
+  Tag_ABI_align8_preserved = Tag_ABI_align_preserved,
+  Tag_VFP_HP_extension = Tag_FP_HP_extension
+};
+
+#endif
+
+/* The name of the note section used to identify arm variants.  */
+#define ARM_NOTE_SECTION ".note.gnu.arm.ident"
+
+/* Special section names.  */
+#define ELF_STRING_ARM_unwind           ".ARM.exidx"
+#define ELF_STRING_ARM_unwind_info      ".ARM.extab"
+#define ELF_STRING_ARM_unwind_once      ".gnu.linkonce.armexidx."
+#define ELF_STRING_ARM_unwind_info_once ".gnu.linkonce.armextab."
+
+enum arm_st_branch_type {
+  ST_BRANCH_TO_ARM,
+  ST_BRANCH_TO_THUMB,
+  ST_BRANCH_LONG,
+  ST_BRANCH_UNKNOWN
+};
+
+#define ARM_SYM_BRANCH_TYPE(SYM) \
+  ((enum arm_st_branch_type) (SYM)->st_target_internal)
+
+#endif /* _ELF_ARM_H */
diff --git a/binutils-2.25/include/elf/avr.h b/binutils-2.25/include/elf/avr.h
new file mode 100644
index 00000000..b45d902d
--- /dev/null
+++ b/binutils-2.25/include/elf/avr.h
@@ -0,0 +1,86 @@
+/* AVR ELF support for BFD.
+   Copyright 1999, 2000, 2004, 2006, 2010, 2012
+   Free Software Foundation, Inc.
+   Contributed by Denis Chertykov <denisc@overta.ru>
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_AVR_H
+#define _ELF_AVR_H
+
+#include "elf/reloc-macros.h"
+
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_AVR_MACH 0x7F
+
+/* If bit #7 is set, it is assumed that the elf file uses local symbols
+   as reference for the relocations so that linker relaxation is possible.  */
+#define EF_AVR_LINKRELAX_PREPARED 0x80
+
+#define E_AVR_MACH_AVR1     1
+#define E_AVR_MACH_AVR2     2
+#define E_AVR_MACH_AVR25   25
+#define E_AVR_MACH_AVR3     3
+#define E_AVR_MACH_AVR31   31
+#define E_AVR_MACH_AVR35   35
+#define E_AVR_MACH_AVR4     4
+#define E_AVR_MACH_AVR5     5
+#define E_AVR_MACH_AVR51   51
+#define E_AVR_MACH_AVR6     6 
+#define E_AVR_MACH_XMEGA1 101
+#define E_AVR_MACH_XMEGA2 102
+#define E_AVR_MACH_XMEGA3 103
+#define E_AVR_MACH_XMEGA4 104
+#define E_AVR_MACH_XMEGA5 105
+#define E_AVR_MACH_XMEGA6 106
+#define E_AVR_MACH_XMEGA7 107
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_avr_reloc_type)
+     RELOC_NUMBER (R_AVR_NONE,			0)
+     RELOC_NUMBER (R_AVR_32,			1)
+     RELOC_NUMBER (R_AVR_7_PCREL,		2)
+     RELOC_NUMBER (R_AVR_13_PCREL,		3)
+     RELOC_NUMBER (R_AVR_16, 			4)
+     RELOC_NUMBER (R_AVR_16_PM, 		5)
+     RELOC_NUMBER (R_AVR_LO8_LDI,		6)
+     RELOC_NUMBER (R_AVR_HI8_LDI,		7)
+     RELOC_NUMBER (R_AVR_HH8_LDI,		8)
+     RELOC_NUMBER (R_AVR_LO8_LDI_NEG,		9)
+     RELOC_NUMBER (R_AVR_HI8_LDI_NEG,	       10)
+     RELOC_NUMBER (R_AVR_HH8_LDI_NEG,	       11)
+     RELOC_NUMBER (R_AVR_LO8_LDI_PM,	       12)
+     RELOC_NUMBER (R_AVR_HI8_LDI_PM,	       13)
+     RELOC_NUMBER (R_AVR_HH8_LDI_PM,	       14)
+     RELOC_NUMBER (R_AVR_LO8_LDI_PM_NEG,       15)
+     RELOC_NUMBER (R_AVR_HI8_LDI_PM_NEG,       16)
+     RELOC_NUMBER (R_AVR_HH8_LDI_PM_NEG,       17)
+     RELOC_NUMBER (R_AVR_CALL,		       18)
+     RELOC_NUMBER (R_AVR_LDI,                  19)
+     RELOC_NUMBER (R_AVR_6,                    20)
+     RELOC_NUMBER (R_AVR_6_ADIW,               21)
+     RELOC_NUMBER (R_AVR_MS8_LDI,              22)
+     RELOC_NUMBER (R_AVR_MS8_LDI_NEG,          23)
+     RELOC_NUMBER (R_AVR_LO8_LDI_GS,	       24)
+     RELOC_NUMBER (R_AVR_HI8_LDI_GS,	       25)
+     RELOC_NUMBER (R_AVR_8, 		       26)
+     RELOC_NUMBER (R_AVR_8_LO8,                27)
+     RELOC_NUMBER (R_AVR_8_HI8,                28)
+     RELOC_NUMBER (R_AVR_8_HLO8,               29)
+END_RELOC_NUMBERS (R_AVR_max)
+
+#endif /* _ELF_AVR_H */
diff --git a/binutils-2.25/include/elf/bfin.h b/binutils-2.25/include/elf/bfin.h
new file mode 100644
index 00000000..8d92906a
--- /dev/null
+++ b/binutils-2.25/include/elf/bfin.h
@@ -0,0 +1,95 @@
+/* Blackfin ELF support for BFD.
+   Copyright (C) 2005, 2006, 2009, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_BFIN_H
+#define _ELF_BFIN_H
+
+#include "elf/reloc-macros.h"
+
+START_RELOC_NUMBERS (elf_bfin_reloc_type)
+  RELOC_NUMBER (R_BFIN_UNUSED0, 0x00)          /* relocation type 0 is not defined */
+  RELOC_NUMBER (R_BFIN_PCREL5M2, 0x01)         /* LSETUP part a */
+  RELOC_NUMBER (R_BFIN_UNUSED1, 0x02)          /* relocation type 2 is not defined */
+  RELOC_NUMBER (R_BFIN_PCREL10, 0x03)          /* type 3, 0x00) if cc jump <target> */
+  RELOC_NUMBER (R_BFIN_PCREL12_JUMP, 0x04)     /* type 4, 0x00) jump <target> */
+  RELOC_NUMBER (R_BFIN_RIMM16, 0x05)           /* type 0x5, 0x00) rN = <target> */
+  RELOC_NUMBER (R_BFIN_LUIMM16, 0x06)          /* # 0x6, 0x00) preg.l=<target> Load imm 16 to lower half */
+  RELOC_NUMBER (R_BFIN_HUIMM16, 0x07)          /* # 0x7, 0x00) preg.h=<target> Load imm 16 to upper half */
+  RELOC_NUMBER (R_BFIN_PCREL12_JUMP_S, 0x08)   /* # 0x8 jump.s <target> */
+  RELOC_NUMBER (R_BFIN_PCREL24_JUMP_X, 0x09)   /* # 0x9 jump.x <target> */
+  RELOC_NUMBER (R_BFIN_PCREL24, 0x0a)          /* # 0xa call <target> , 0x00) not expandable */
+  RELOC_NUMBER (R_BFIN_UNUSEDB, 0x0b)          /* # 0xb not generated */
+  RELOC_NUMBER (R_BFIN_UNUSEDC, 0x0c)          /* # 0xc  not used */
+  RELOC_NUMBER (R_BFIN_PCREL24_JUMP_L, 0x0d)   /* 0xd jump.l <target> */
+  RELOC_NUMBER (R_BFIN_PCREL24_CALL_X, 0x0e)   /* 0xE, 0x00) call.x <target> if <target> is above 24 bit limit call through P1 */
+  RELOC_NUMBER (R_BFIN_VAR_EQ_SYMB, 0x0f)      /* 0xf, 0x00) linker should treat it same as 0x12 */
+  RELOC_NUMBER (R_BFIN_BYTE_DATA, 0x10)        /* 0x10, 0x00) .byte var = symbol */
+  RELOC_NUMBER (R_BFIN_BYTE2_DATA, 0x11)       /* 0x11, 0x00) .byte2 var = symbol */
+  RELOC_NUMBER (R_BFIN_BYTE4_DATA, 0x12)       /* 0x12, 0x00) .byte4 var = symbol and .var var=symbol */
+  RELOC_NUMBER (R_BFIN_PCREL11, 0x13)          /* 0x13, 0x00) lsetup part b */
+  RELOC_NUMBER (R_BFIN_GOT17M4, 0x14)
+  RELOC_NUMBER (R_BFIN_GOTHI, 0x15)
+  RELOC_NUMBER (R_BFIN_GOTLO, 0x16)
+  RELOC_NUMBER (R_BFIN_FUNCDESC, 0x17)
+  RELOC_NUMBER (R_BFIN_FUNCDESC_GOT17M4, 0x18)
+  RELOC_NUMBER (R_BFIN_FUNCDESC_GOTHI, 0x19)
+  RELOC_NUMBER (R_BFIN_FUNCDESC_GOTLO, 0x1a)
+  RELOC_NUMBER (R_BFIN_FUNCDESC_VALUE, 0x1b)
+  RELOC_NUMBER (R_BFIN_FUNCDESC_GOTOFF17M4, 0x1c)
+  RELOC_NUMBER (R_BFIN_FUNCDESC_GOTOFFHI, 0x1d)
+  RELOC_NUMBER (R_BFIN_FUNCDESC_GOTOFFLO, 0x1e)
+  RELOC_NUMBER (R_BFIN_GOTOFF17M4, 0x1f)
+  RELOC_NUMBER (R_BFIN_GOTOFFHI, 0x20)
+  RELOC_NUMBER (R_BFIN_GOTOFFLO, 0x21)
+
+  RELOC_NUMBER (R_BFIN_PUSH, 0xE0)
+  RELOC_NUMBER (R_BFIN_CONST, 0xE1)
+  RELOC_NUMBER (R_BFIN_ADD, 0xE2)
+  RELOC_NUMBER (R_BFIN_SUB, 0xE3)
+  RELOC_NUMBER (R_BFIN_MULT, 0xE4)
+  RELOC_NUMBER (R_BFIN_DIV, 0xE5)
+  RELOC_NUMBER (R_BFIN_MOD, 0xE6)
+  RELOC_NUMBER (R_BFIN_LSHIFT, 0xE7)
+  RELOC_NUMBER (R_BFIN_RSHIFT, 0xE8)
+  RELOC_NUMBER (R_BFIN_AND, 0xE9)
+  RELOC_NUMBER (R_BFIN_OR, 0xEA)
+  RELOC_NUMBER (R_BFIN_XOR, 0xEB)
+  RELOC_NUMBER (R_BFIN_LAND, 0xEC)
+  RELOC_NUMBER (R_BFIN_LOR, 0xED)
+  RELOC_NUMBER (R_BFIN_LEN, 0xEE)
+  RELOC_NUMBER (R_BFIN_NEG, 0xEF)
+  RELOC_NUMBER (R_BFIN_COMP, 0xF0)
+  RELOC_NUMBER (R_BFIN_PAGE, 0xF1)
+  RELOC_NUMBER (R_BFIN_HWPAGE, 0xF2)
+  RELOC_NUMBER (R_BFIN_ADDR, 0xF3)
+  RELOC_NUMBER (R_BFIN_PLTPC, 0x40)         /* PLT gnu only relocation */
+  RELOC_NUMBER (R_BFIN_GOT, 0x41)           /* GOT gnu only relocation */
+  RELOC_NUMBER (R_BFIN_GNU_VTINHERIT, 0x42) /* C++, gnu only */
+  RELOC_NUMBER (R_BFIN_GNU_VTENTRY, 0x43) /* C++, gnu only */
+END_RELOC_NUMBERS (R_BFIN_max)
+
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_BFIN_PIC		0x00000001	/* -fpic */
+#define EF_BFIN_FDPIC		0x00000002      /* -mfdpic */
+
+#define EF_BFIN_CODE_IN_L1	0x00000010	/* --code-in-l1 */
+#define EF_BFIN_DATA_IN_L1	0x00000020	/* --data-in-l1 */
+
+#define	EF_BFIN_PIC_FLAGS	(EF_BFIN_PIC | EF_BFIN_FDPIC)
+#endif /* _ELF_BFIN_H */
diff --git a/binutils-2.25/include/elf/common.h b/binutils-2.25/include/elf/common.h
new file mode 100644
index 00000000..cd3bcdd2
--- /dev/null
+++ b/binutils-2.25/include/elf/common.h
@@ -0,0 +1,1001 @@
+/* ELF support for BFD.
+   Copyright 1991-2013 Free Software Foundation, Inc.
+
+   Written by Fred Fish @ Cygnus Support, from information published
+   in "UNIX System V Release 4, Programmers Guide: ANSI C and
+   Programming Support Tools".
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file is part of ELF support for BFD, and contains the portions
+   that are common to both the internal and external representations.
+   For example, ELFMAG0 is the byte 0x7F in both the internal (in-memory)
+   and external (in-file) representations.  */
+
+#ifndef _ELF_COMMON_H
+#define _ELF_COMMON_H
+
+/* Fields in e_ident[].  */
+
+#define EI_MAG0		0	/* File identification byte 0 index */
+#define ELFMAG0		   0x7F	/* Magic number byte 0 */
+
+#define EI_MAG1		1	/* File identification byte 1 index */
+#define ELFMAG1		    'E'	/* Magic number byte 1 */
+
+#define EI_MAG2		2	/* File identification byte 2 index */
+#define ELFMAG2		    'L'	/* Magic number byte 2 */
+
+#define EI_MAG3		3	/* File identification byte 3 index */
+#define ELFMAG3		    'F'	/* Magic number byte 3 */
+
+#define EI_CLASS	4	/* File class */
+#define ELFCLASSNONE	      0	/* Invalid class */
+#define ELFCLASS32	      1	/* 32-bit objects */
+#define ELFCLASS64	      2	/* 64-bit objects */
+
+#define EI_DATA		5	/* Data encoding */
+#define ELFDATANONE	      0	/* Invalid data encoding */
+#define ELFDATA2LSB	      1	/* 2's complement, little endian */
+#define ELFDATA2MSB	      2	/* 2's complement, big endian */
+
+#define EI_VERSION	6	/* File version */
+
+#define EI_OSABI	7	/* Operating System/ABI indication */
+#define ELFOSABI_NONE	      0	/* UNIX System V ABI */
+#define ELFOSABI_HPUX	      1	/* HP-UX operating system */
+#define ELFOSABI_NETBSD	      2	/* NetBSD */
+#define ELFOSABI_GNU	      3	/* GNU */
+#define ELFOSABI_LINUX	      3	/* Alias for ELFOSABI_GNU */
+#define ELFOSABI_SOLARIS      6	/* Solaris */
+#define ELFOSABI_AIX	      7	/* AIX */
+#define ELFOSABI_IRIX	      8	/* IRIX */
+#define ELFOSABI_FREEBSD      9	/* FreeBSD */
+#define ELFOSABI_TRU64	     10	/* TRU64 UNIX */
+#define ELFOSABI_MODESTO     11	/* Novell Modesto */
+#define ELFOSABI_OPENBSD     12	/* OpenBSD */
+#define ELFOSABI_OPENVMS     13	/* OpenVMS */
+#define ELFOSABI_NSK	     14	/* Hewlett-Packard Non-Stop Kernel */
+#define ELFOSABI_AROS	     15	/* AROS */
+#define ELFOSABI_FENIXOS     16 /* FenixOS */
+#define ELFOSABI_C6000_ELFABI 64 /* Bare-metal TMS320C6000 */
+#define ELFOSABI_C6000_LINUX 65 /* Linux TMS320C6000 */
+#define ELFOSABI_ARM	     97	/* ARM */
+#define ELFOSABI_STANDALONE 255	/* Standalone (embedded) application */
+
+#define EI_ABIVERSION	8	/* ABI version */
+
+#define EI_PAD		9	/* Start of padding bytes */
+
+
+/* Values for e_type, which identifies the object file type.  */
+
+#define ET_NONE		0	/* No file type */
+#define ET_REL		1	/* Relocatable file */
+#define ET_EXEC		2	/* Executable file */
+#define ET_DYN		3	/* Shared object file */
+#define ET_CORE		4	/* Core file */
+#define ET_LOOS		0xFE00	/* Operating system-specific */
+#define ET_HIOS		0xFEFF	/* Operating system-specific */
+#define ET_LOPROC	0xFF00	/* Processor-specific */
+#define ET_HIPROC	0xFFFF	/* Processor-specific */
+
+/* Values for e_machine, which identifies the architecture.  These numbers
+   are officially assigned by registry@sco.com.  See below for a list of
+   ad-hoc numbers used during initial development.  */
+
+#define EM_NONE		  0	/* No machine */
+#define EM_M32		  1	/* AT&T WE 32100 */
+#define EM_SPARC	  2	/* SUN SPARC */
+#define EM_386		  3	/* Intel 80386 */
+#define EM_68K		  4	/* Motorola m68k family */
+#define EM_88K		  5	/* Motorola m88k family */
+#define EM_486		  6	/* Intel 80486 *//* Reserved for future use */
+#define EM_860		  7	/* Intel 80860 */
+#define EM_MIPS		  8	/* MIPS R3000 (officially, big-endian only) */
+#define EM_S370		  9	/* IBM System/370 */
+#define EM_MIPS_RS3_LE	 10	/* MIPS R3000 little-endian (Oct 4 1999 Draft) Deprecated */
+#define EM_res011	 11	/* Reserved */
+#define EM_res012	 12	/* Reserved */
+#define EM_res013	 13	/* Reserved */
+#define EM_res014	 14	/* Reserved */
+#define EM_PARISC	 15	/* HPPA */
+#define EM_res016	 16	/* Reserved */
+#define EM_VPP550	 17	/* Fujitsu VPP500 */
+#define EM_SPARC32PLUS	 18	/* Sun's "v8plus" */
+#define EM_960		 19	/* Intel 80960 */
+#define EM_PPC		 20	/* PowerPC */
+#define EM_PPC64	 21	/* 64-bit PowerPC */
+#define EM_S390		 22	/* IBM S/390 */
+#define EM_SPU		 23	/* Sony/Toshiba/IBM SPU */
+#define EM_res024	 24	/* Reserved */
+#define EM_res025	 25	/* Reserved */
+#define EM_res026	 26	/* Reserved */
+#define EM_res027	 27	/* Reserved */
+#define EM_res028	 28	/* Reserved */
+#define EM_res029	 29	/* Reserved */
+#define EM_res030	 30	/* Reserved */
+#define EM_res031	 31	/* Reserved */
+#define EM_res032	 32	/* Reserved */
+#define EM_res033	 33	/* Reserved */
+#define EM_res034	 34	/* Reserved */
+#define EM_res035	 35	/* Reserved */
+#define EM_V800		 36	/* NEC V800 series */
+#define EM_FR20		 37	/* Fujitsu FR20 */
+#define EM_RH32		 38	/* TRW RH32 */
+#define EM_MCORE	 39	/* Motorola M*Core */ /* May also be taken by Fujitsu MMA */
+#define EM_RCE		 39	/* Old name for MCore */
+#define EM_ARM		 40	/* ARM */
+#define EM_OLD_ALPHA	 41	/* Digital Alpha */
+#define EM_SH		 42	/* Renesas (formerly Hitachi) / SuperH SH */
+#define EM_SPARCV9	 43	/* SPARC v9 64-bit */
+#define EM_TRICORE	 44	/* Siemens Tricore embedded processor */
+#define EM_ARC		 45	/* ARC Cores */
+#define EM_H8_300	 46	/* Renesas (formerly Hitachi) H8/300 */
+#define EM_H8_300H	 47	/* Renesas (formerly Hitachi) H8/300H */
+#define EM_H8S		 48	/* Renesas (formerly Hitachi) H8S */
+#define EM_H8_500	 49	/* Renesas (formerly Hitachi) H8/500 */
+#define EM_IA_64	 50	/* Intel IA-64 Processor */
+#define EM_MIPS_X	 51	/* Stanford MIPS-X */
+#define EM_COLDFIRE	 52	/* Motorola Coldfire */
+#define EM_68HC12	 53	/* Motorola M68HC12 */
+#define EM_MMA		 54	/* Fujitsu Multimedia Accelerator */
+#define EM_PCP		 55	/* Siemens PCP */
+#define EM_NCPU		 56	/* Sony nCPU embedded RISC processor */
+#define EM_NDR1		 57	/* Denso NDR1 microprocessor */
+#define EM_STARCORE	 58	/* Motorola Star*Core processor */
+#define EM_ME16		 59	/* Toyota ME16 processor */
+#define EM_ST100	 60	/* STMicroelectronics ST100 processor */
+#define EM_TINYJ	 61	/* Advanced Logic Corp. TinyJ embedded processor */
+#define EM_X86_64	 62	/* Advanced Micro Devices X86-64 processor */
+#define EM_PDSP		 63	/* Sony DSP Processor */
+#define EM_PDP10	 64	/* Digital Equipment Corp. PDP-10 */
+#define EM_PDP11	 65	/* Digital Equipment Corp. PDP-11 */
+#define EM_FX66		 66	/* Siemens FX66 microcontroller */
+#define EM_ST9PLUS	 67	/* STMicroelectronics ST9+ 8/16 bit microcontroller */
+#define EM_ST7		 68	/* STMicroelectronics ST7 8-bit microcontroller */
+#define EM_68HC16	 69	/* Motorola MC68HC16 Microcontroller */
+#define EM_68HC11	 70	/* Motorola MC68HC11 Microcontroller */
+#define EM_68HC08	 71	/* Motorola MC68HC08 Microcontroller */
+#define EM_68HC05	 72	/* Motorola MC68HC05 Microcontroller */
+#define EM_SVX		 73	/* Silicon Graphics SVx */
+#define EM_ST19		 74	/* STMicroelectronics ST19 8-bit cpu */
+#define EM_VAX		 75	/* Digital VAX */
+#define EM_CRIS		 76	/* Axis Communications 32-bit embedded processor */
+#define EM_JAVELIN	 77	/* Infineon Technologies 32-bit embedded cpu */
+#define EM_FIREPATH	 78	/* Element 14 64-bit DSP processor */
+#define EM_ZSP		 79	/* LSI Logic's 16-bit DSP processor */
+#define EM_MMIX		 80	/* Donald Knuth's educational 64-bit processor */
+#define EM_HUANY	 81	/* Harvard's machine-independent format */
+#define EM_PRISM	 82	/* SiTera Prism */
+#define EM_AVR		 83	/* Atmel AVR 8-bit microcontroller */
+#define EM_FR30		 84	/* Fujitsu FR30 */
+#define EM_D10V		 85	/* Mitsubishi D10V */
+#define EM_D30V		 86	/* Mitsubishi D30V */
+#define EM_V850		 87	/* Renesas V850 (formerly NEC V850) */
+#define EM_M32R		 88	/* Renesas M32R (formerly Mitsubishi M32R) */
+#define EM_MN10300	 89	/* Matsushita MN10300 */
+#define EM_MN10200	 90	/* Matsushita MN10200 */
+#define EM_PJ		 91	/* picoJava */
+#define EM_OPENRISC	 92	/* OpenRISC 32-bit embedded processor */
+#define EM_ARC_A5	 93	/* ARC Cores Tangent-A5 */
+#define EM_XTENSA	 94	/* Tensilica Xtensa Architecture */
+#define EM_VIDEOCORE	 95	/* Alphamosaic VideoCore processor */
+#define EM_TMM_GPP	 96	/* Thompson Multimedia General Purpose Processor */
+#define EM_NS32K	 97	/* National Semiconductor 32000 series */
+#define EM_TPC		 98	/* Tenor Network TPC processor */
+#define EM_SNP1K	 99	/* Trebia SNP 1000 processor */
+#define EM_ST200	100	/* STMicroelectronics ST200 microcontroller */
+#define EM_IP2K		101	/* Ubicom IP2022 micro controller */
+#define EM_MAX		102	/* MAX Processor */
+#define EM_CR		103	/* National Semiconductor CompactRISC */
+#define EM_F2MC16	104	/* Fujitsu F2MC16 */
+#define EM_MSP430	105	/* TI msp430 micro controller */
+#define EM_BLACKFIN	106	/* ADI Blackfin */
+#define EM_SE_C33	107	/* S1C33 Family of Seiko Epson processors */
+#define EM_SEP		108	/* Sharp embedded microprocessor */
+#define EM_ARCA		109	/* Arca RISC Microprocessor */
+#define EM_UNICORE	110	/* Microprocessor series from PKU-Unity Ltd. and MPRC of Peking University */
+#define EM_EXCESS	111	/* eXcess: 16/32/64-bit configurable embedded CPU */
+#define EM_DXP		112	/* Icera Semiconductor Inc. Deep Execution Processor */
+#define EM_ALTERA_NIOS2	113	/* Altera Nios II soft-core processor */
+#define EM_CRX		114	/* National Semiconductor CRX */
+#define EM_XGATE	115	/* Motorola XGATE embedded processor */
+#define EM_C166		116	/* Infineon C16x/XC16x processor */
+#define EM_M16C		117	/* Renesas M16C series microprocessors */
+#define EM_DSPIC30F	118	/* Microchip Technology dsPIC30F Digital Signal Controller */
+#define EM_CE		119	/* Freescale Communication Engine RISC core */
+#define EM_M32C		120	/* Renesas M32C series microprocessors */
+#define EM_res121	121	/* Reserved */
+#define EM_res122	122	/* Reserved */
+#define EM_res123	123	/* Reserved */
+#define EM_res124	124	/* Reserved */
+#define EM_res125	125	/* Reserved */
+#define EM_res126	126	/* Reserved */
+#define EM_res127	127	/* Reserved */
+#define EM_res128	128	/* Reserved */
+#define EM_res129	129	/* Reserved */
+#define EM_res130	130	/* Reserved */
+#define EM_TSK3000	131	/* Altium TSK3000 core */
+#define EM_RS08		132	/* Freescale RS08 embedded processor */
+#define EM_res133	133	/* Reserved */
+#define EM_ECOG2	134	/* Cyan Technology eCOG2 microprocessor */
+#define EM_SCORE	135	/* Sunplus Score */
+#define EM_SCORE7	135	/* Sunplus S+core7 RISC processor */
+#define EM_DSP24	136	/* New Japan Radio (NJR) 24-bit DSP Processor */
+#define EM_VIDEOCORE3	137	/* Broadcom VideoCore III processor */
+#define EM_LATTICEMICO32 138	/* RISC processor for Lattice FPGA architecture */
+#define EM_SE_C17	139	/* Seiko Epson C17 family */
+#define EM_TI_C6000	140	/* Texas Instruments TMS320C6000 DSP family */
+#define EM_TI_C2000	141	/* Texas Instruments TMS320C2000 DSP family */
+#define EM_TI_C5500	142	/* Texas Instruments TMS320C55x DSP family */
+#define EM_res143	143	/* Reserved */
+#define EM_res144	144	/* Reserved */
+#define EM_res145	145	/* Reserved */
+#define EM_res146	146	/* Reserved */
+#define EM_res147	147	/* Reserved */
+#define EM_res148	148	/* Reserved */
+#define EM_res149	149	/* Reserved */
+#define EM_res150	150	/* Reserved */
+#define EM_res151	151	/* Reserved */
+#define EM_res152	152	/* Reserved */
+#define EM_res153	153	/* Reserved */
+#define EM_res154	154	/* Reserved */
+#define EM_res155	155	/* Reserved */
+#define EM_res156	156	/* Reserved */
+#define EM_res157	157	/* Reserved */
+#define EM_res158	158	/* Reserved */
+#define EM_res159	159	/* Reserved */
+#define EM_MMDSP_PLUS	160	/* STMicroelectronics 64bit VLIW Data Signal Processor */
+#define EM_CYPRESS_M8C	161	/* Cypress M8C microprocessor */
+#define EM_R32C		162	/* Renesas R32C series microprocessors */
+#define EM_TRIMEDIA	163	/* NXP Semiconductors TriMedia architecture family */
+#define EM_QDSP6	164	/* QUALCOMM DSP6 Processor */
+#define EM_8051		165	/* Intel 8051 and variants */
+#define EM_STXP7X	166	/* STMicroelectronics STxP7x family */
+#define EM_NDS32	167	/* Andes Technology compact code size embedded RISC processor family */
+#define EM_ECOG1	168	/* Cyan Technology eCOG1X family */
+#define EM_ECOG1X	168	/* Cyan Technology eCOG1X family */
+#define EM_MAXQ30	169	/* Dallas Semiconductor MAXQ30 Core Micro-controllers */
+#define EM_XIMO16	170	/* New Japan Radio (NJR) 16-bit DSP Processor */
+#define EM_MANIK	171	/* M2000 Reconfigurable RISC Microprocessor */
+#define EM_CRAYNV2	172	/* Cray Inc. NV2 vector architecture */
+#define EM_RX		173	/* Renesas RX family */
+#define EM_METAG	174	/* Imagination Technologies Meta processor architecture */
+#define EM_MCST_ELBRUS	175	/* MCST Elbrus general purpose hardware architecture */
+#define EM_ECOG16	176	/* Cyan Technology eCOG16 family */
+#define EM_CR16		177	/* National Semiconductor CompactRISC 16-bit processor */
+#define EM_ETPU		178	/* Freescale Extended Time Processing Unit */
+#define EM_SLE9X	179	/* Infineon Technologies SLE9X core */
+#define EM_L1OM		180	/* Intel L1OM */
+#define EM_K1OM		181	/* Intel K1OM */
+#define EM_INTEL182	182	/* Reserved by Intel */
+#define EM_AARCH64	183	/* ARM 64-bit architecture */
+#define EM_ARM184	184	/* Reserved by ARM */
+#define EM_AVR32	185	/* Atmel Corporation 32-bit microprocessor family */
+#define EM_STM8	186	/* STMicroeletronics STM8 8-bit microcontroller */
+#define EM_TILE64	187	/* Tilera TILE64 multicore architecture family */
+#define EM_TILEPRO	188	/* Tilera TILEPro multicore architecture family */
+#define EM_MICROBLAZE	189	/* Xilinx MicroBlaze 32-bit RISC soft processor core */
+#define EM_CUDA		190	/* NVIDIA CUDA architecture */
+#define EM_TILEGX	191	/* Tilera TILE-Gx multicore architecture family */
+#define EM_RL78		197	/* Renesas RL78 family.  */
+#define EM_78K0R	199	/* Renesas 78K0R.  */
+#define EM_INTEL205	205	/* Reserved by Intel */
+#define EM_INTEL206	206	/* Reserved by Intel */
+#define EM_INTEL207	207	/* Reserved by Intel */
+#define EM_INTEL208	208	/* Reserved by Intel */
+#define EM_INTEL209	209	/* Reserved by Intel */
+
+/* If it is necessary to assign new unofficial EM_* values, please pick large
+   random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision
+   with official or non-GNU unofficial values.
+
+   NOTE: Do not just increment the most recent number by one.
+   Somebody else somewhere will do exactly the same thing, and you
+   will have a collision.  Instead, pick a random number.
+
+   Normally, each entity or maintainer responsible for a machine with an
+   unofficial e_machine number should eventually ask registry@sco.com for
+   an officially blessed number to be added to the list above.	*/
+
+/* Old version of Sparc v9, from before the ABI;
+   This should be removed shortly.  */
+#define EM_OLD_SPARCV9		11
+
+/* Old version of PowerPC, this should be removed shortly. */
+#define EM_PPC_OLD		17
+
+/* picoJava */
+#define EM_PJ_OLD		99
+
+/* Old, unofficial value for National Semiconductor CompactRISC - CR16 */
+#define EM_CR16_OLD		115
+
+/* AVR magic number.  Written in the absense of an ABI.  */
+#define EM_AVR_OLD		0x1057
+
+/* MSP430 magic number.  Written in the absense of everything.  */
+#define EM_MSP430_OLD		0x1059
+
+/* Morpho MT.   Written in the absense of an ABI.  */
+#define EM_MT			0x2530
+
+/* FR30 magic number - no EABI available.  */
+#define EM_CYGNUS_FR30		0x3330
+
+/* OpenRISC magic number.  Written in the absense of an ABI.  */
+#define EM_OPENRISC_OLD		0x3426
+
+/* DLX magic number.  Written in the absense of an ABI.  */
+#define EM_DLX			0x5aa5
+
+/* FRV magic number - no EABI available??.  */
+#define EM_CYGNUS_FRV		0x5441
+
+/* Infineon Technologies 16-bit microcontroller with C166-V2 core.  */
+#define EM_XC16X		0x4688
+
+/* D10V backend magic number.  Written in the absence of an ABI.  */
+#define EM_CYGNUS_D10V		0x7650
+
+/* D30V backend magic number.  Written in the absence of an ABI.  */
+#define EM_CYGNUS_D30V		0x7676
+
+/* Ubicom IP2xxx;   Written in the absense of an ABI.  */
+#define EM_IP2K_OLD		0x8217
+
+/* (Deprecated) Temporary number for the OpenRISC processor.  */
+#define EM_OR32			0x8472
+
+/* Cygnus PowerPC ELF backend.  Written in the absence of an ABI.  */
+#define EM_CYGNUS_POWERPC	0x9025
+
+/* Alpha backend magic number.  Written in the absence of an ABI.  */
+#define EM_ALPHA		0x9026
+
+/* Cygnus M32R ELF backend.  Written in the absence of an ABI.  */
+#define EM_CYGNUS_M32R		0x9041
+
+/* V850 backend magic number.  Written in the absense of an ABI.  */
+#define EM_CYGNUS_V850		0x9080
+
+/* old S/390 backend magic number. Written in the absence of an ABI.  */
+#define EM_S390_OLD		0xa390
+
+/* Old, unofficial value for Xtensa.  */
+#define EM_XTENSA_OLD		0xabc7
+
+#define EM_XSTORMY16		0xad45
+
+/* mn10200 and mn10300 backend magic numbers.
+   Written in the absense of an ABI.  */
+#define EM_CYGNUS_MN10300	0xbeef
+#define EM_CYGNUS_MN10200	0xdead
+
+/* Renesas M32C and M16C.  */
+#define EM_M32C_OLD		0xFEB0
+
+/* Vitesse IQ2000.  */
+#define EM_IQ2000		0xFEBA
+
+/* NIOS magic number - no EABI available.  */
+#define EM_NIOS32		0xFEBB
+
+#define EM_CYGNUS_MEP		0xF00D  /* Toshiba MeP */
+
+#define EM_MOXIE                0xFEED  /* Moxie */
+
+/* Old Sunplus S+core7 backend magic number. Written in the absence of an ABI.  */
+#define EM_SCORE_OLD            95
+
+#define EM_MICROBLAZE_OLD	0xbaab	/* Old MicroBlaze */
+
+#define EM_ADAPTEVA_EPIPHANY   0x1223  /* Adapteva's Epiphany architecture.  */
+
+/* See the above comment before you add a new EM_* value here.  */
+
+/* Values for e_version.  */
+
+#define EV_NONE		0		/* Invalid ELF version */
+#define EV_CURRENT	1		/* Current version */
+
+/* Value for e_phnum. */
+#define PN_XNUM		0xffff		/* Extended numbering */
+
+/* Values for program header, p_type field.  */
+
+#define PT_NULL		0		/* Program header table entry unused */
+#define PT_LOAD		1		/* Loadable program segment */
+#define PT_DYNAMIC	2		/* Dynamic linking information */
+#define PT_INTERP	3		/* Program interpreter */
+#define PT_NOTE		4		/* Auxiliary information */
+#define PT_SHLIB	5		/* Reserved, unspecified semantics */
+#define PT_PHDR		6		/* Entry for header table itself */
+#define PT_TLS		7		/* Thread local storage segment */
+#define PT_LOOS		0x60000000	/* OS-specific */
+#define PT_HIOS		0x6fffffff	/* OS-specific */
+#define PT_LOPROC	0x70000000	/* Processor-specific */
+#define PT_HIPROC	0x7FFFFFFF	/* Processor-specific */
+
+#define PT_GNU_EH_FRAME	(PT_LOOS + 0x474e550) /* Frame unwind information */
+#define PT_SUNW_EH_FRAME PT_GNU_EH_FRAME      /* Solaris uses the same value */
+#define PT_GNU_STACK	(PT_LOOS + 0x474e551) /* Stack flags */
+#define PT_GNU_RELRO	(PT_LOOS + 0x474e552) /* Read-only after relocation */
+
+/* Program segment permissions, in program header p_flags field.  */
+
+#define PF_X		(1 << 0)	/* Segment is executable */
+#define PF_W		(1 << 1)	/* Segment is writable */
+#define PF_R		(1 << 2)	/* Segment is readable */
+/* #define PF_MASKOS	0x0F000000    *//* OS-specific reserved bits */
+#define PF_MASKOS	0x0FF00000	/* New value, Oct 4, 1999 Draft */
+#define PF_MASKPROC	0xF0000000	/* Processor-specific reserved bits */
+
+/* Values for section header, sh_type field.  */
+
+#define SHT_NULL	0		/* Section header table entry unused */
+#define SHT_PROGBITS	1		/* Program specific (private) data */
+#define SHT_SYMTAB	2		/* Link editing symbol table */
+#define SHT_STRTAB	3		/* A string table */
+#define SHT_RELA	4		/* Relocation entries with addends */
+#define SHT_HASH	5		/* A symbol hash table */
+#define SHT_DYNAMIC	6		/* Information for dynamic linking */
+#define SHT_NOTE	7		/* Information that marks file */
+#define SHT_NOBITS	8		/* Section occupies no space in file */
+#define SHT_REL		9		/* Relocation entries, no addends */
+#define SHT_SHLIB	10		/* Reserved, unspecified semantics */
+#define SHT_DYNSYM	11		/* Dynamic linking symbol table */
+
+#define SHT_INIT_ARRAY	  14		/* Array of ptrs to init functions */
+#define SHT_FINI_ARRAY	  15		/* Array of ptrs to finish functions */
+#define SHT_PREINIT_ARRAY 16		/* Array of ptrs to pre-init funcs */
+#define SHT_GROUP	  17		/* Section contains a section group */
+#define SHT_SYMTAB_SHNDX  18		/* Indicies for SHN_XINDEX entries */
+
+#define SHT_LOOS	0x60000000	/* First of OS specific semantics */
+#define SHT_HIOS	0x6fffffff	/* Last of OS specific semantics */
+
+#define SHT_GNU_INCREMENTAL_INPUTS 0x6fff4700   /* incremental build data */
+#define SHT_GNU_ATTRIBUTES 0x6ffffff5	/* Object attributes */
+#define SHT_GNU_HASH	0x6ffffff6	/* GNU style symbol hash table */
+#define SHT_GNU_LIBLIST	0x6ffffff7	/* List of prelink dependencies */
+
+/* The next three section types are defined by Solaris, and are named
+   SHT_SUNW*.  We use them in GNU code, so we also define SHT_GNU*
+   versions.  */
+#define SHT_SUNW_verdef	0x6ffffffd	/* Versions defined by file */
+#define SHT_SUNW_verneed 0x6ffffffe	/* Versions needed by file */
+#define SHT_SUNW_versym	0x6fffffff	/* Symbol versions */
+
+#define SHT_GNU_verdef	SHT_SUNW_verdef
+#define SHT_GNU_verneed	SHT_SUNW_verneed
+#define SHT_GNU_versym	SHT_SUNW_versym
+
+#define SHT_LOPROC	0x70000000	/* Processor-specific semantics, lo */
+#define SHT_HIPROC	0x7FFFFFFF	/* Processor-specific semantics, hi */
+#define SHT_LOUSER	0x80000000	/* Application-specific semantics */
+/* #define SHT_HIUSER	0x8FFFFFFF    *//* Application-specific semantics */
+#define SHT_HIUSER	0xFFFFFFFF	/* New value, defined in Oct 4, 1999 Draft */
+
+/* Values for section header, sh_flags field.  */
+
+#define SHF_WRITE	(1 << 0)	/* Writable data during execution */
+#define SHF_ALLOC	(1 << 1)	/* Occupies memory during execution */
+#define SHF_EXECINSTR	(1 << 2)	/* Executable machine instructions */
+#define SHF_MERGE	(1 << 4)	/* Data in this section can be merged */
+#define SHF_STRINGS	(1 << 5)	/* Contains null terminated character strings */
+#define SHF_INFO_LINK	(1 << 6)	/* sh_info holds section header table index */
+#define SHF_LINK_ORDER	(1 << 7)	/* Preserve section ordering when linking */
+#define SHF_OS_NONCONFORMING (1 << 8)	/* OS specific processing required */
+#define SHF_GROUP	(1 << 9)	/* Member of a section group */
+#define SHF_TLS		(1 << 10)	/* Thread local storage section */
+
+/* #define SHF_MASKOS	0x0F000000    *//* OS-specific semantics */
+#define SHF_MASKOS	0x0FF00000	/* New value, Oct 4, 1999 Draft */
+#define SHF_MASKPROC	0xF0000000	/* Processor-specific semantics */
+
+/* This used to be implemented as a processor specific section flag.
+   We just make it generic.  */
+#define SHF_EXCLUDE	0x80000000	/* Link editor is to exclude
+					   this section from executable
+					   and shared library that it
+					   builds when those objects
+					   are not to be further
+					   relocated.  */
+
+/* Values of note segment descriptor types for core files.  */
+
+#define NT_PRSTATUS	1		/* Contains copy of prstatus struct */
+#define NT_FPREGSET	2		/* Contains copy of fpregset struct */
+#define NT_PRPSINFO	3		/* Contains copy of prpsinfo struct */
+#define NT_TASKSTRUCT	4		/* Contains copy of task struct */
+#define NT_AUXV		6		/* Contains copy of Elfxx_auxv_t */
+#define NT_PRXFPREG	0x46e62b7f	/* Contains a user_xfpregs_struct; */
+					/*   note name must be "LINUX".  */
+#define NT_PPC_VMX	0x100		/* PowerPC Altivec/VMX registers */
+					/*   note name must be "LINUX".  */
+#define NT_PPC_VSX	0x102		/* PowerPC VSX registers */
+					/*   note name must be "LINUX".  */
+#define NT_386_TLS	0x200		/* x86 TLS information */
+					/*   note name must be "LINUX".  */
+#define NT_386_IOPERM	0x201		/* x86 io permissions */
+					/*   note name must be "LINUX".  */
+#define NT_X86_XSTATE	0x202		/* x86 XSAVE extended state */
+					/*   note name must be "LINUX".  */
+#define NT_S390_HIGH_GPRS 0x300		/* S/390 upper halves of GPRs  */
+					/*   note name must be "LINUX".  */
+#define NT_S390_TIMER	0x301		/* S390 timer */
+					/*   note name must be "LINUX".  */
+#define NT_S390_TODCMP	0x302		/* S390 TOD clock comparator */
+					/*   note name must be "LINUX".  */
+#define NT_S390_TODPREG	0x303		/* S390 TOD programmable register */
+					/*   note name must be "LINUX".  */
+#define NT_S390_CTRS	0x304		/* S390 control registers */
+					/*   note name must be "LINUX".  */
+#define NT_S390_PREFIX	0x305		/* S390 prefix register */
+					/*   note name must be "LINUX".  */
+#define NT_S390_LAST_BREAK      0x306   /* S390 breaking event address */
+					/*   note name must be "LINUX".  */
+#define NT_S390_SYSTEM_CALL     0x307   /* S390 system call restart data */
+					/*   note name must be "LINUX".  */
+#define NT_S390_TDB	0x308		/* S390 transaction diagnostic block */
+					/*   note name must be "LINUX".  */
+#define NT_ARM_VFP	0x400		/* ARM VFP registers */
+/* The following definitions should really use NT_AARCH_..., but defined
+   this way for compatibility with Linux.  */
+#define NT_ARM_TLS	0x401		/* AArch TLS registers */
+					/*   note name must be "LINUX".  */
+#define NT_ARM_HW_BREAK	0x402		/* AArch hardware breakpoint registers */
+					/*   note name must be "LINUX".  */
+#define NT_ARM_HW_WATCH	0x403		/* AArch hardware watchpoint registers */
+					/*   note name must be "LINUX".  */
+#define NT_SIGINFO	0x53494749	/* Fields of siginfo_t.  */
+#define NT_FILE		0x46494c45	/* Description of mapped files.  */
+
+/* Note segments for core files on dir-style procfs systems.  */
+
+#define NT_PSTATUS	10		/* Has a struct pstatus */
+#define NT_FPREGS	12		/* Has a struct fpregset */
+#define NT_PSINFO	13		/* Has a struct psinfo */
+#define NT_LWPSTATUS	16		/* Has a struct lwpstatus_t */
+#define NT_LWPSINFO	17		/* Has a struct lwpsinfo_t */
+#define NT_WIN32PSTATUS	18		/* Has a struct win32_pstatus */
+
+/* Note segment for SystemTap probes.  */
+#define NT_STAPSDT	3
+
+/* Note segments for core files on NetBSD systems.  Note name
+   must start with "NetBSD-CORE".  */
+
+#define NT_NETBSDCORE_PROCINFO	1	/* Has a struct procinfo */
+#define NT_NETBSDCORE_FIRSTMACH	32	/* start of machdep note types */
+
+
+/* Note segments for core files on OpenBSD systems.  Note name is
+   "OpenBSD".  */
+
+#define NT_OPENBSD_PROCINFO	10
+#define NT_OPENBSD_AUXV		11
+#define NT_OPENBSD_REGS		20
+#define NT_OPENBSD_FPREGS	21
+#define NT_OPENBSD_XFPREGS	22
+#define NT_OPENBSD_WCOOKIE	23
+
+
+/* Note segments for core files on SPU systems.  Note name
+   must start with "SPU/".  */
+
+#define NT_SPU		1
+
+/* Values of note segment descriptor types for object files.  */
+
+#define NT_VERSION	1		/* Contains a version string.  */
+#define NT_ARCH		2		/* Contains an architecture string.  */
+
+/* Values for notes in non-core files using name "GNU".  */
+
+#define NT_GNU_ABI_TAG		1
+#define NT_GNU_HWCAP		2	/* Used by ld.so and kernel vDSO.  */
+#define NT_GNU_BUILD_ID		3	/* Generated by ld --build-id.  */
+#define NT_GNU_GOLD_VERSION	4	/* Generated by gold.  */
+
+/* Values used in GNU .note.ABI-tag notes (NT_GNU_ABI_TAG).  */
+#define GNU_ABI_TAG_LINUX	0
+#define GNU_ABI_TAG_HURD	1
+#define GNU_ABI_TAG_SOLARIS	2
+#define GNU_ABI_TAG_FREEBSD	3
+#define GNU_ABI_TAG_NETBSD	4
+
+/* Values for NetBSD .note.netbsd.ident notes.  Note name is "NetBSD".  */
+
+#define NT_NETBSD_IDENT		1
+
+/* Values for OpenBSD .note.openbsd.ident notes.  Note name is "OpenBSD".  */
+
+#define NT_OPENBSD_IDENT	1
+
+/* Values for FreeBSD .note.ABI-tag notes.  Note name is "FreeBSD".  */
+
+#define NT_FREEBSD_ABI_TAG	1
+
+/* These three macros disassemble and assemble a symbol table st_info field,
+   which contains the symbol binding and symbol type.  The STB_ and STT_
+   defines identify the binding and type.  */
+
+#define ELF_ST_BIND(val)		(((unsigned int)(val)) >> 4)
+#define ELF_ST_TYPE(val)		((val) & 0xF)
+#define ELF_ST_INFO(bind,type)		(((bind) << 4) + ((type) & 0xF))
+
+/* The 64bit and 32bit versions of these macros are identical, but
+   the ELF spec defines them, so here they are.  */
+#define ELF32_ST_BIND  ELF_ST_BIND
+#define ELF32_ST_TYPE  ELF_ST_TYPE
+#define ELF32_ST_INFO  ELF_ST_INFO
+#define ELF64_ST_BIND  ELF_ST_BIND
+#define ELF64_ST_TYPE  ELF_ST_TYPE
+#define ELF64_ST_INFO  ELF_ST_INFO
+
+/* This macro disassembles and assembles a symbol's visibility into
+   the st_other field.  The STV_ defines specify the actual visibility.  */
+
+#define ELF_ST_VISIBILITY(v)		((v) & 0x3)
+/* The remaining bits in the st_other field are not currently used.
+   They should be set to zero.  */
+
+#define ELF32_ST_VISIBILITY  ELF_ST_VISIBILITY
+#define ELF64_ST_VISIBILITY  ELF_ST_VISIBILITY
+
+
+#define STN_UNDEF	0		/* Undefined symbol index */
+
+#define STB_LOCAL	0		/* Symbol not visible outside obj */
+#define STB_GLOBAL	1		/* Symbol visible outside obj */
+#define STB_WEAK	2		/* Like globals, lower precedence */
+#define STB_LOOS	10		/* OS-specific semantics */
+#define STB_GNU_UNIQUE	10		/* Symbol is unique in namespace */
+#define STB_HIOS	12		/* OS-specific semantics */
+#define STB_LOPROC	13		/* Processor-specific semantics */
+#define STB_HIPROC	15		/* Processor-specific semantics */
+
+#define STT_NOTYPE	0		/* Symbol type is unspecified */
+#define STT_OBJECT	1		/* Symbol is a data object */
+#define STT_FUNC	2		/* Symbol is a code object */
+#define STT_SECTION	3		/* Symbol associated with a section */
+#define STT_FILE	4		/* Symbol gives a file name */
+#define STT_COMMON	5		/* An uninitialised common block */
+#define STT_TLS		6		/* Thread local data object */
+#define STT_RELC	8		/* Complex relocation expression */
+#define STT_SRELC	9		/* Signed Complex relocation expression */
+#define STT_LOOS	10		/* OS-specific semantics */
+#define STT_GNU_IFUNC	10		/* Symbol is an indirect code object */
+#define STT_HIOS	12		/* OS-specific semantics */
+#define STT_LOPROC	13		/* Processor-specific semantics */
+#define STT_HIPROC	15		/* Processor-specific semantics */
+
+/* The following constants control how a symbol may be accessed once it has
+   become part of an executable or shared library.  */
+
+#define STV_DEFAULT	0		/* Visibility is specified by binding type */
+#define STV_INTERNAL	1		/* OS specific version of STV_HIDDEN */
+#define STV_HIDDEN	2		/* Can only be seen inside currect component */
+#define STV_PROTECTED	3		/* Treat as STB_LOCAL inside current component */
+
+/* Relocation info handling macros.  */
+
+#define ELF32_R_SYM(i)		((i) >> 8)
+#define ELF32_R_TYPE(i)		((i) & 0xff)
+#define ELF32_R_INFO(s,t)	(((s) << 8) + ((t) & 0xff))
+
+#define ELF64_R_SYM(i)		((i) >> 32)
+#define ELF64_R_TYPE(i)		((i) & 0xffffffff)
+#define ELF64_R_INFO(s,t)	(((bfd_vma) (s) << 31 << 1) + (bfd_vma) (t))
+
+/* Dynamic section tags.  */
+
+#define DT_NULL		0
+#define DT_NEEDED	1
+#define DT_PLTRELSZ	2
+#define DT_PLTGOT	3
+#define DT_HASH		4
+#define DT_STRTAB	5
+#define DT_SYMTAB	6
+#define DT_RELA		7
+#define DT_RELASZ	8
+#define DT_RELAENT	9
+#define DT_STRSZ	10
+#define DT_SYMENT	11
+#define DT_INIT		12
+#define DT_FINI		13
+#define DT_SONAME	14
+#define DT_RPATH	15
+#define DT_SYMBOLIC	16
+#define DT_REL		17
+#define DT_RELSZ	18
+#define DT_RELENT	19
+#define DT_PLTREL	20
+#define DT_DEBUG	21
+#define DT_TEXTREL	22
+#define DT_JMPREL	23
+#define DT_BIND_NOW	24
+#define DT_INIT_ARRAY	25
+#define DT_FINI_ARRAY	26
+#define DT_INIT_ARRAYSZ 27
+#define DT_FINI_ARRAYSZ 28
+#define DT_RUNPATH	29
+#define DT_FLAGS	30
+#define DT_ENCODING	32
+#define DT_PREINIT_ARRAY   32
+#define DT_PREINIT_ARRAYSZ 33
+
+/* Note, the Oct 4, 1999 draft of the ELF ABI changed the values
+   for DT_LOOS and DT_HIOS.  Some implementations however, use
+   values outside of the new range (see below).	 */
+#define OLD_DT_LOOS	0x60000000
+#define DT_LOOS		0x6000000d
+#define DT_HIOS		0x6ffff000
+#define OLD_DT_HIOS	0x6fffffff
+
+#define DT_LOPROC	0x70000000
+#define DT_HIPROC	0x7fffffff
+
+/* The next 2 dynamic tag ranges, integer value range (DT_VALRNGLO to
+   DT_VALRNGHI) and virtual address range (DT_ADDRRNGLO to DT_ADDRRNGHI),
+   are used on Solaris.  We support them everywhere.  Note these values
+   lie outside of the (new) range for OS specific values.  This is a
+   deliberate special case and we maintain it for backwards compatability.
+ */
+#define DT_VALRNGLO	0x6ffffd00
+#define DT_GNU_PRELINKED 0x6ffffdf5
+#define DT_GNU_CONFLICTSZ 0x6ffffdf6
+#define DT_GNU_LIBLISTSZ 0x6ffffdf7
+#define DT_CHECKSUM	0x6ffffdf8
+#define DT_PLTPADSZ	0x6ffffdf9
+#define DT_MOVEENT	0x6ffffdfa
+#define DT_MOVESZ	0x6ffffdfb
+#define DT_FEATURE	0x6ffffdfc
+#define DT_POSFLAG_1	0x6ffffdfd
+#define DT_SYMINSZ	0x6ffffdfe
+#define DT_SYMINENT	0x6ffffdff
+#define DT_VALRNGHI	0x6ffffdff
+
+#define DT_ADDRRNGLO	0x6ffffe00
+#define DT_GNU_HASH	0x6ffffef5
+#define DT_TLSDESC_PLT	0x6ffffef6
+#define DT_TLSDESC_GOT	0x6ffffef7
+#define DT_GNU_CONFLICT	0x6ffffef8
+#define DT_GNU_LIBLIST	0x6ffffef9
+#define DT_CONFIG	0x6ffffefa
+#define DT_DEPAUDIT	0x6ffffefb
+#define DT_AUDIT	0x6ffffefc
+#define DT_PLTPAD	0x6ffffefd
+#define DT_MOVETAB	0x6ffffefe
+#define DT_SYMINFO	0x6ffffeff
+#define DT_ADDRRNGHI	0x6ffffeff
+
+#define DT_RELACOUNT	0x6ffffff9
+#define DT_RELCOUNT	0x6ffffffa
+#define DT_FLAGS_1	0x6ffffffb
+#define DT_VERDEF	0x6ffffffc
+#define DT_VERDEFNUM	0x6ffffffd
+#define DT_VERNEED	0x6ffffffe
+#define DT_VERNEEDNUM	0x6fffffff
+
+/* This tag is a GNU extension to the Solaris version scheme.  */
+#define DT_VERSYM	0x6ffffff0
+
+#define DT_LOPROC	0x70000000
+#define DT_HIPROC	0x7fffffff
+
+/* These section tags are used on Solaris.  We support them
+   everywhere, and hope they do not conflict.  */
+
+#define DT_AUXILIARY	0x7ffffffd
+#define DT_USED		0x7ffffffe
+#define DT_FILTER	0x7fffffff
+
+
+/* Values used in DT_FEATURE .dynamic entry.  */
+#define DTF_1_PARINIT	0x00000001
+/* From
+
+   http://docs.sun.com:80/ab2/coll.45.13/LLM/@Ab2PageView/21165?Ab2Lang=C&Ab2Enc=iso-8859-1
+
+   DTF_1_CONFEXP is the same as DTF_1_PARINIT. It is a typo. The value
+   defined here is the same as the one in <sys/link.h> on Solaris 8.  */
+#define DTF_1_CONFEXP	0x00000002
+
+/* Flag values used in the DT_POSFLAG_1 .dynamic entry.	 */
+#define DF_P1_LAZYLOAD	0x00000001
+#define DF_P1_GROUPPERM	0x00000002
+
+/* Flag value in in the DT_FLAGS_1 .dynamic entry.  */
+#define DF_1_NOW	0x00000001
+#define DF_1_GLOBAL	0x00000002
+#define DF_1_GROUP	0x00000004
+#define DF_1_NODELETE	0x00000008
+#define DF_1_LOADFLTR	0x00000010
+#define DF_1_INITFIRST	0x00000020
+#define DF_1_NOOPEN	0x00000040
+#define DF_1_ORIGIN	0x00000080
+#define DF_1_DIRECT	0x00000100
+#define DF_1_TRANS	0x00000200
+#define DF_1_INTERPOSE	0x00000400
+#define DF_1_NODEFLIB	0x00000800
+#define DF_1_NODUMP	0x00001000
+#define DF_1_CONFALT	0x00002000
+#define DF_1_ENDFILTEE	0x00004000
+#define	DF_1_DISPRELDNE	0x00008000
+#define	DF_1_DISPRELPND	0x00010000
+#define	DF_1_NODIRECT	0x00020000
+#define	DF_1_IGNMULDEF	0x00040000
+#define	DF_1_NOKSYMS	0x00080000
+#define	DF_1_NOHDR	0x00100000
+#define	DF_1_EDITED	0x00200000
+#define	DF_1_NORELOC	0x00400000
+#define	DF_1_SYMINTPOSE	0x00800000
+#define	DF_1_GLOBAUDIT	0x01000000
+#define	DF_1_SINGLETON	0x02000000
+
+/* Flag values for the DT_FLAGS entry.	*/
+#define DF_ORIGIN	(1 << 0)
+#define DF_SYMBOLIC	(1 << 1)
+#define DF_TEXTREL	(1 << 2)
+#define DF_BIND_NOW	(1 << 3)
+#define DF_STATIC_TLS	(1 << 4)
+
+/* These constants are used for the version number of a Elf32_Verdef
+   structure.  */
+
+#define VER_DEF_NONE		0
+#define VER_DEF_CURRENT		1
+
+/* These constants appear in the vd_flags field of a Elf32_Verdef
+   structure.
+
+   Cf. the Solaris Linker and Libraries Guide, Ch. 7, Object File Format,
+   Versioning Sections, for a description:
+
+   http://docs.sun.com/app/docs/doc/819-0690/chapter6-93046?l=en&a=view  */
+
+#define VER_FLG_BASE		0x1
+#define VER_FLG_WEAK		0x2
+#define VER_FLG_INFO		0x4
+
+/* These special constants can be found in an Elf32_Versym field.  */
+
+#define VER_NDX_LOCAL		0
+#define VER_NDX_GLOBAL		1
+
+/* These constants are used for the version number of a Elf32_Verneed
+   structure.  */
+
+#define VER_NEED_NONE		0
+#define VER_NEED_CURRENT	1
+
+/* This flag appears in a Versym structure.  It means that the symbol
+   is hidden, and is only visible with an explicit version number.
+   This is a GNU extension.  */
+
+#define VERSYM_HIDDEN		0x8000
+
+/* This is the mask for the rest of the Versym information.  */
+
+#define VERSYM_VERSION		0x7fff
+
+/* This is a special token which appears as part of a symbol name.  It
+   indictes that the rest of the name is actually the name of a
+   version node, and is not part of the actual name.  This is a GNU
+   extension.  For example, the symbol name `stat@ver2' is taken to
+   mean the symbol `stat' in version `ver2'.  */
+
+#define ELF_VER_CHR	'@'
+
+/* Possible values for si_boundto.  */
+
+#define SYMINFO_BT_SELF		0xffff	/* Symbol bound to self */
+#define SYMINFO_BT_PARENT	0xfffe	/* Symbol bound to parent */
+#define SYMINFO_BT_LOWRESERVE	0xff00	/* Beginning of reserved entries */
+
+/* Possible bitmasks for si_flags.  */
+
+#define SYMINFO_FLG_DIRECT	0x0001	/* Direct bound symbol */
+#define SYMINFO_FLG_PASSTHRU	0x0002	/* Pass-thru symbol for translator */
+#define SYMINFO_FLG_COPY	0x0004	/* Symbol is a copy-reloc */
+#define SYMINFO_FLG_LAZYLOAD	0x0008	/* Symbol bound to object to be lazy loaded */
+
+/* Syminfo version values.  */
+
+#define SYMINFO_NONE		0
+#define SYMINFO_CURRENT		1
+#define SYMINFO_NUM		2
+
+/* Section Group Flags.	 */
+
+#define GRP_COMDAT		0x1	/* A COMDAT group */
+
+/* Auxv a_type values.  */
+
+#define AT_NULL		0		/* End of vector */
+#define AT_IGNORE	1		/* Entry should be ignored */
+#define AT_EXECFD	2		/* File descriptor of program */
+#define AT_PHDR		3		/* Program headers for program */
+#define AT_PHENT	4		/* Size of program header entry */
+#define AT_PHNUM	5		/* Number of program headers */
+#define AT_PAGESZ	6		/* System page size */
+#define AT_BASE		7		/* Base address of interpreter */
+#define AT_FLAGS	8		/* Flags */
+#define AT_ENTRY	9		/* Entry point of program */
+#define AT_NOTELF	10		/* Program is not ELF */
+#define AT_UID		11		/* Real uid */
+#define AT_EUID		12		/* Effective uid */
+#define AT_GID		13		/* Real gid */
+#define AT_EGID		14		/* Effective gid */
+#define AT_CLKTCK	17		/* Frequency of times() */
+#define AT_PLATFORM	15		/* String identifying platform.  */
+#define AT_HWCAP	16		/* Machine dependent hints about
+					   processor capabilities.  */
+#define AT_FPUCW	18		/* Used FPU control word.  */
+#define AT_DCACHEBSIZE	19		/* Data cache block size.  */
+#define AT_ICACHEBSIZE	20		/* Instruction cache block size.  */
+#define AT_UCACHEBSIZE	21		/* Unified cache block size.  */
+#define AT_IGNOREPPC	22		/* Entry should be ignored */
+#define	AT_SECURE	23		/* Boolean, was exec setuid-like?  */
+#define AT_BASE_PLATFORM 24		/* String identifying real platform,
+					   may differ from AT_PLATFORM.  */
+#define AT_RANDOM	25		/* Address of 16 random bytes.  */
+#define AT_EXECFN	31		/* Filename of executable.  */
+/* Pointer to the global system page used for system calls and other
+   nice things.  */
+#define AT_SYSINFO	32
+#define AT_SYSINFO_EHDR	33 /* Pointer to ELF header of system-supplied DSO.  */
+
+/* More complete cache descriptions than AT_[DIU]CACHEBSIZE.  If the
+   value is -1, then the cache doesn't exist.  Otherwise:
+
+   bit 0-3:  Cache set-associativity; 0 means fully associative.
+   bit 4-7:  Log2 of cacheline size.
+   bit 8-31:  Size of the entire cache >> 8.  */
+
+#define AT_L1I_CACHESHAPE 34
+#define AT_L1D_CACHESHAPE 35
+#define AT_L2_CACHESHAPE  36
+#define AT_L3_CACHESHAPE  37
+
+#define AT_SUN_UID      2000    /* Effective user ID.  */
+#define AT_SUN_RUID     2001    /* Real user ID.  */
+#define AT_SUN_GID      2002    /* Effective group ID.  */
+#define AT_SUN_RGID     2003    /* Real group ID.  */
+#define AT_SUN_LDELF    2004    /* Dynamic linker's ELF header.  */
+#define AT_SUN_LDSHDR   2005    /* Dynamic linker's section headers.  */
+#define AT_SUN_LDNAME   2006    /* String giving name of dynamic linker.  */
+#define AT_SUN_LPAGESZ  2007    /* Large pagesize.   */
+#define AT_SUN_PLATFORM 2008    /* Platform name string.  */
+#define AT_SUN_HWCAP    2009	/* Machine dependent hints about
+				   processor capabilities.  */
+#define AT_SUN_IFLUSH   2010    /* Should flush icache? */
+#define AT_SUN_CPU      2011    /* CPU name string.  */
+#define AT_SUN_EMUL_ENTRY 2012	/* COFF entry point address.  */
+#define AT_SUN_EMUL_EXECFD 2013	/* COFF executable file descriptor.  */
+#define AT_SUN_EXECNAME 2014    /* Canonicalized file name given to execve.  */
+#define AT_SUN_MMU      2015    /* String for name of MMU module.   */
+#define AT_SUN_LDDATA   2016    /* Dynamic linker's data segment address.  */
+#define AT_SUN_AUXFLAGS	2017	/* AF_SUN_ flags passed from the kernel.  */
+
+
+#endif /* _ELF_COMMON_H */
diff --git a/binutils-2.25/include/elf/cr16.h b/binutils-2.25/include/elf/cr16.h
new file mode 100644
index 00000000..32784748
--- /dev/null
+++ b/binutils-2.25/include/elf/cr16.h
@@ -0,0 +1,62 @@
+/* CR16 ELF support for BFD.
+   Copyright 2007, 2010 Free Software Foundation, Inc.
+   Contributed by M R Swami Reddy.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_CR16_H
+#define _ELF_CR16_H
+
+#include "elf/reloc-macros.h"
+
+/* Creating indices for reloc_map_index array.  */
+START_RELOC_NUMBERS(elf_cr16_reloc_type)
+  RELOC_NUMBER (R_CR16_NONE,           0)
+  RELOC_NUMBER (R_CR16_NUM8,           1)
+  RELOC_NUMBER (R_CR16_NUM16,          2)
+  RELOC_NUMBER (R_CR16_NUM32,          3)
+  RELOC_NUMBER (R_CR16_NUM32a,         4)
+  RELOC_NUMBER (R_CR16_REGREL4,        5)
+  RELOC_NUMBER (R_CR16_REGREL4a,       6)
+  RELOC_NUMBER (R_CR16_REGREL14,       7)
+  RELOC_NUMBER (R_CR16_REGREL14a,      8)
+  RELOC_NUMBER (R_CR16_REGREL16,       9)
+  RELOC_NUMBER (R_CR16_REGREL20,       10)
+  RELOC_NUMBER (R_CR16_REGREL20a,      11)
+  RELOC_NUMBER (R_CR16_ABS20,          12)
+  RELOC_NUMBER (R_CR16_ABS24,          13)
+  RELOC_NUMBER (R_CR16_IMM4,           14)
+  RELOC_NUMBER (R_CR16_IMM8,           15)
+  RELOC_NUMBER (R_CR16_IMM16,          16)
+  RELOC_NUMBER (R_CR16_IMM20,          17)
+  RELOC_NUMBER (R_CR16_IMM24,          18)
+  RELOC_NUMBER (R_CR16_IMM32,          19)
+  RELOC_NUMBER (R_CR16_IMM32a,         20)
+  RELOC_NUMBER (R_CR16_DISP4,          21)
+  RELOC_NUMBER (R_CR16_DISP8,          22)
+  RELOC_NUMBER (R_CR16_DISP16,         23)
+  RELOC_NUMBER (R_CR16_DISP24,         24)
+  RELOC_NUMBER (R_CR16_DISP24a,        25)
+  RELOC_NUMBER (R_CR16_SWITCH8,        26)
+  RELOC_NUMBER (R_CR16_SWITCH16,       27)
+  RELOC_NUMBER (R_CR16_SWITCH32,       28)
+  RELOC_NUMBER (R_CR16_GOT_REGREL20,   29)
+  RELOC_NUMBER (R_CR16_GOTC_REGREL20,  30)
+  RELOC_NUMBER (R_CR16_GLOB_DAT,       31)
+END_RELOC_NUMBERS(R_CR16_MAX)
+        
+#endif /* _ELF_CR16_H */
diff --git a/binutils-2.25/include/elf/cr16c.h b/binutils-2.25/include/elf/cr16c.h
new file mode 100644
index 00000000..dbefb0ab
--- /dev/null
+++ b/binutils-2.25/include/elf/cr16c.h
@@ -0,0 +1,258 @@
+/* CR16C ELF support for BFD.
+   Copyright 2004, 2008, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_CR16C_H
+#define _ELF_CR16C_H
+
+#include "bfd.h"
+#include "elf/reloc-macros.h"
+
+/* Creating indices for reloc_map_index array.  */
+START_RELOC_NUMBERS (elf_cr16c_reloc_type)
+     RELOC_NUMBER (RINDEX_16C_NUM08,		0)
+     RELOC_NUMBER (RINDEX_16C_NUM08_C,		1)
+     RELOC_NUMBER (RINDEX_16C_NUM16,		2)
+     RELOC_NUMBER (RINDEX_16C_NUM16_C,		3)
+     RELOC_NUMBER (RINDEX_16C_NUM32,		4)
+     RELOC_NUMBER (RINDEX_16C_NUM32_C,		5)
+     RELOC_NUMBER (RINDEX_16C_DISP04,		6)
+     RELOC_NUMBER (RINDEX_16C_DISP04_C,		7)
+     RELOC_NUMBER (RINDEX_16C_DISP08,		8)
+     RELOC_NUMBER (RINDEX_16C_DISP08_C,		9)
+     RELOC_NUMBER (RINDEX_16C_DISP16,		10)
+     RELOC_NUMBER (RINDEX_16C_DISP16_C,		11)
+     RELOC_NUMBER (RINDEX_16C_DISP24,		12)
+     RELOC_NUMBER (RINDEX_16C_DISP24_C,		13)
+     RELOC_NUMBER (RINDEX_16C_DISP24a,		14)
+     RELOC_NUMBER (RINDEX_16C_DISP24a_C,	15)
+     RELOC_NUMBER (RINDEX_16C_REG04,		16)
+     RELOC_NUMBER (RINDEX_16C_REG04_C,		17)
+     RELOC_NUMBER (RINDEX_16C_REG04a,		18)
+     RELOC_NUMBER (RINDEX_16C_REG04a_C,		19)
+     RELOC_NUMBER (RINDEX_16C_REG14,		20)
+     RELOC_NUMBER (RINDEX_16C_REG14_C,		21)
+     RELOC_NUMBER (RINDEX_16C_REG16,		22)
+     RELOC_NUMBER (RINDEX_16C_REG16_C,		23)
+     RELOC_NUMBER (RINDEX_16C_REG20,		24)
+     RELOC_NUMBER (RINDEX_16C_REG20_C,		25)
+     RELOC_NUMBER (RINDEX_16C_ABS20,		26)
+     RELOC_NUMBER (RINDEX_16C_ABS20_C,		27)
+     RELOC_NUMBER (RINDEX_16C_ABS24,		28)
+     RELOC_NUMBER (RINDEX_16C_ABS24_C,		29)
+     RELOC_NUMBER (RINDEX_16C_IMM04,		30)
+     RELOC_NUMBER (RINDEX_16C_IMM04_C,		31)
+     RELOC_NUMBER (RINDEX_16C_IMM16,		32)
+     RELOC_NUMBER (RINDEX_16C_IMM16_C,		33)
+     RELOC_NUMBER (RINDEX_16C_IMM20,		34)
+     RELOC_NUMBER (RINDEX_16C_IMM20_C,		35)
+     RELOC_NUMBER (RINDEX_16C_IMM24,		36)
+     RELOC_NUMBER (RINDEX_16C_IMM24_C,		37)
+     RELOC_NUMBER (RINDEX_16C_IMM32,		38)
+     RELOC_NUMBER (RINDEX_16C_IMM32_C,		39)
+END_RELOC_NUMBERS (RINDEX_16C_MAX)
+
+/* CR16C Relocation Types ('cr_reloc_type' entry in the reloc_map structure).
+   The relocation constant name is determined as follows :
+
+   R_16C_<format><size>[_C]
+
+   Where :
+
+     <format> is one of the following:
+	NUM  - R_NUMBER mnemonic,
+	DISP - R_16C_DISPL mnemonic,
+	REG  - R_16C_REGREL mnemonic,
+	ABS  - R_16C_ABS mnemonic,
+	IMM  - R_16C_IMMED mnemonic,
+     <size> stands for R_S_16C_<size> 
+     _C means 'code label' and is only added when R_ADDRTYPE subfield 
+     is of type R_CODE_ADDR.  */
+   
+/* The table below shows what the hex digits in the definition of the
+   relocation type constants correspond to.
+   ------------------------------------------------------------------
+	R_SIZESP	R_FORMAT	R_RELTO	      R_ADDRTYPE
+   ------------------------------------------------------------------  */
+/*	R_S_16C_08	R_NUMBER 	R_ABS 	      R_ADDRESS */
+#define R_16C_NUM08	0X0001
+
+/*	R_S_16C_08	R_NUMBER 	R_ABS 	      R_CODE_ADDR */
+#define R_16C_NUM08_C	0X0006
+
+/*	R_S_16C_16	R_NUMBER 	R_ABS 	      R_ADDRESS */
+#define R_16C_NUM16	0X1001
+
+/*	R_S_16C_16	R_NUMBER 	R_ABS 	      R_CODE_ADDR */
+#define R_16C_NUM16_C 	0X1006
+
+/*      R_S_16C_32      R_NUMBER	R_ABS	      R_ADDRESS */
+#define R_16C_NUM32     0X2001
+
+/*      R_S_16C_32      R_NUMBER	R_ABS	      R_CODE_ADDR */
+#define R_16C_NUM32_C   0X2006
+
+/*	R_S_16C_04	R_16C_DISPL 	R_PCREL	      R_ADDRESS */
+#define R_16C_DISP04	0X5411
+
+/*	R_S_16C_04	R_16C_DISPL 	R_PCREL	      R_CODE_ADDR */
+#define R_16C_DISP04_C	0X5416
+
+/*	R_S_16C_08	R_16C_DISPL 	R_PCREL	      R_ADDRESS */
+#define R_16C_DISP08	0X0411
+
+/*	R_S_16C_08	R_16C_DISPL 	R_PCREL	      R_CODE_ADDR */
+#define R_16C_DISP08_C	0X0416
+
+/*	R_S_16C_16	R_16C_DISPL 	R_PCREL	      R_ADDRESS */
+#define R_16C_DISP16	0X1411
+
+/*	R_S_16C_16	R_16C_DISPL 	R_PCREL	      R_CODE_ADDR */
+#define R_16C_DISP16_C	0X1416
+
+/*	R_S_16C_24	R_16C_DISPL 	R_PCREL	      R_ADDRESS */
+#define R_16C_DISP24	0X7411
+
+/*	R_S_16C_24	R_16C_DISPL 	R_PCREL	      R_CODE_ADDR */
+#define R_16C_DISP24_C	0X7416
+
+/*	R_S_16C_24a	R_16C_DISPL 	R_PCREL	      R_ADDRESS */
+#define R_16C_DISP24a	0X6411
+
+/*	R_S_16C_24a	R_16C_DISPL 	R_PCREL	      R_CODE_ADDR */
+#define R_16C_DISP24a_C	0X6416
+
+/*	R_S_16C_04	R_16C_REGREL 	R_ABS 	      R_ADDRESS */
+#define R_16C_REG04	0X5201
+
+/*	R_S_16C_04	R_16C_REGREL 	R_ABS 	      R_CODE_ADDR */
+#define R_16C_REG04_C	0X5206
+
+/*	R_S_16C_04_a	R_16C_REGREL 	R_ABS 	      R_ADDRESS */
+#define R_16C_REG04a	0X4201
+
+/*	R_S_16C_04_a	R_16C_REGREL 	R_ABS 	      R_CODE_ADDR */
+#define R_16C_REG04a_C	0X4206
+
+/*	R_S_16C_14	R_16C_REGREL 	R_ABS 	      R_ADDRESS */
+#define R_16C_REG14	0X3201
+
+/*	R_S_16C_14	R_16C_REGREL 	R_ABS 	      R_CODE_ADDR */
+#define R_16C_REG14_C	0X3206
+
+/*	R_S_16C_16	R_16C_REGREL 	R_ABS 	      R_ADDRESS */
+#define R_16C_REG16	0X1201
+
+/*	R_S_16C_16	R_16C_REGREL 	R_ABS 	      R_CODE_ADDR */
+#define R_16C_REG16_C	0X1206
+
+/*	R_S_16C_20	R_16C_REGREL 	R_ABS 	      R_ADDRESS */
+#define R_16C_REG20	0X8201
+
+/*	R_S_16C_20	R_16C_REGREL 	R_ABS 	      R_CODE_ADDR */
+#define R_16C_REG20_C	0X8206
+
+/*      R_S_16C_20      R_16C_ABS	R_ABS	      R_ADDRESS */
+#define R_16C_ABS20     0X8101
+
+/*      R_S_16C_20      R_16C_ABS	R_ABS	      R_CODE_ADDR */
+#define R_16C_ABS20_C   0X8106
+
+/*      R_S_16C_24      R_16C_ABS	R_ABS	      R_ADDRESS */
+#define R_16C_ABS24     0X7101
+
+/*      R_S_16C_24      R_16C_ABS	R_ABS	      R_CODE_ADDR */
+#define R_16C_ABS24_C   0X7106
+
+/*      R_S_16C_04      R_16C_IMMED	R_ABS	      R_ADDRESS */
+#define R_16C_IMM04     0X5301
+
+/*      R_S_16C_04      R_16C_IMMED	R_ABS	      R_CODE_ADDR */
+#define R_16C_IMM04_C   0X5306
+
+/*      R_S_16C_16      R_16C_IMMED	R_ABS	      R_ADDRESS */
+#define R_16C_IMM16     0X1301
+
+/*      R_S_16C_16      R_16C_IMMED	R_ABS	      R_CODE_ADDR */
+#define R_16C_IMM16_C   0X1306
+
+/*      R_S_16C_20      R_16C_IMMED	R_ABS	      R_ADDRESS */
+#define R_16C_IMM20     0X8301
+
+/*      R_S_16C_20      R_16C_IMMED	R_ABS	      R_CODE_ADDR */
+#define R_16C_IMM20_C   0X8306
+
+/*      R_S_16C_24      R_16C_IMMED	R_ABS	      R_ADDRESS */
+#define R_16C_IMM24     0X7301
+
+/*      R_S_16C_24      R_16C_IMMED	R_ABS	      R_CODE_ADDR */
+#define R_16C_IMM24_C   0X7306
+
+/*      R_S_16C_32      R_16C_IMMED	R_ABS	      R_ADDRESS */
+#define R_16C_IMM32     0X2301
+
+/*      R_S_16C_32      R_16C_IMMED	R_ABS	      R_CODE_ADDR */
+#define R_16C_IMM32_C   0X2306
+
+
+/* Relocation item type.  */
+#define   R_ADDRTYPE	 0x000f
+#define   R_ADDRESS      0x0001    /* Take address of symbol.  */
+#define   R_CODE_ADDR    0x0006    /* Take address of symbol divided by 2.  */
+
+/* Relocation action.  */
+#define   R_RELTO        0x00f0
+#define   R_ABS          0x0000    /* Keep symbol's address as such.  */
+#define   R_PCREL        0x0010    /* Subtract the pc address of hole.  */
+
+/* Relocation item data format.  */
+#define   R_FORMAT       0x0f00
+#define   R_NUMBER       0x0000    /* Retain as two's complement value.  */
+#define   R_16C_DISPL    0x0400    /* CR16C displacement type.  */
+#define   R_16C_ABS      0x0100    /* CR16C absolute type.  */
+#define   R_16C_REGREL   0x0200    /* CR16C register-relative type.  */
+#define   R_16C_IMMED    0x0300    /* CR16C immediate type.  */
+
+/* Relocation item size. */
+#define   R_SIZESP       0xf000
+#define   R_S_16C_04     0x5000
+#define   R_S_16C_04_a   0x4000
+#define   R_S_16C_08	 0x0000
+#define   R_S_16C_14     0x3000
+#define   R_S_16C_16	 0x1000
+#define   R_S_16C_20     0x8000
+#define   R_S_16C_24_a   0x6000
+#define   R_S_16C_24	 0x7000
+#define   R_S_16C_32     0x2000
+
+
+/* Processor specific section indices.  These sections do not actually
+   exist.  Symbols with a st_shndx field corresponding to one of these
+   values have a special meaning.  */
+
+/* Far common symbol.  */
+#define SHN_CR16C_FCOMMON	SHN_LORESERVE
+#define SHN_CR16C_NCOMMON	(SHN_LORESERVE + 1)
+
+typedef struct reloc_map
+{
+  unsigned short            cr_reloc_type;  /* CR relocation type.  */
+  bfd_reloc_code_real_type  bfd_reloc_enum; /* BFD relocation enum.  */
+} RELOC_MAP;
+
+#endif /* _ELF_CR16C_H */
diff --git a/binutils-2.25/include/elf/cris.h b/binutils-2.25/include/elf/cris.h
new file mode 100644
index 00000000..5889a90d
--- /dev/null
+++ b/binutils-2.25/include/elf/cris.h
@@ -0,0 +1,193 @@
+/* CRIS ELF support for BFD.
+   Copyright 2000, 2001, 2004, 2010  Free Software Foundation, Inc.
+   Contributed by Axis Communications AB, Lund, Sweden.
+   Written by Hans-Peter Nilsson.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_CRIS_H
+#define _ELF_CRIS_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_cris_reloc_type)
+  RELOC_NUMBER (R_CRIS_NONE,		0)
+  RELOC_NUMBER (R_CRIS_8,		1)
+  RELOC_NUMBER (R_CRIS_16,		2)
+  RELOC_NUMBER (R_CRIS_32,		3)
+
+  /* The "PC" position is the location right after the relocation.  */
+  RELOC_NUMBER (R_CRIS_8_PCREL,		4)
+  RELOC_NUMBER (R_CRIS_16_PCREL,	5)
+  RELOC_NUMBER (R_CRIS_32_PCREL,	6)
+
+  RELOC_NUMBER (R_CRIS_GNU_VTINHERIT,	7)
+  RELOC_NUMBER (R_CRIS_GNU_VTENTRY,	8)
+
+  /* Copy contents at dynlinking.  Generated by the linker.
+     The BFD equivalent is BFD_RELOC_CRIS_COPY.  */
+  RELOC_NUMBER (R_CRIS_COPY, 9)
+
+  /* Create GOT entry.  Generated by the linker.
+     The BFD equivalent is BFD_RELOC_CRIS_GLOB_DAT.  */
+  RELOC_NUMBER (R_CRIS_GLOB_DAT, 10)
+
+  /* Create PLT entry.  Generated by the linker.
+     The BFD equivalent is BFD_RELOC_CRIS_JUMP_SLOT.  */
+  RELOC_NUMBER (R_CRIS_JUMP_SLOT, 11)
+
+  /* Adjust by program base.  Generated by the linker.
+     The BFD equivalent is BFD_RELOC_CRIS_RELATIVE.  */
+  RELOC_NUMBER (R_CRIS_RELATIVE, 12)
+
+  /* A 16-bit offset to entry in GOT and request to create GOT entry for
+     that symbol.
+     The BFD equivalent is BFD_RELOC_CRIS_16_GOT.  */
+  RELOC_NUMBER (R_CRIS_16_GOT, 13)
+
+  /* A 32-bit offset to entry in GOT and request to create GOT entry for
+     that symbol.
+     The BFD equivalent is BFD_RELOC_CRIS_32_GOT.  */
+  RELOC_NUMBER (R_CRIS_32_GOT, 14)
+
+  /* A 16-bit offset to entry in PLT part of GOT and request to create PLT
+     entry for that symbol.
+     The BFD equivalent is BFD_RELOC_CRIS_16_GOTPLT.  */
+  RELOC_NUMBER (R_CRIS_16_GOTPLT, 15)
+
+  /* A 32-bit offset to entry in PLT part of GOT and request to create PLT
+     entry for that symbol.
+     The BFD equivalent is BFD_RELOC_CRIS_32_GOTPLT.  */
+  RELOC_NUMBER (R_CRIS_32_GOTPLT, 16)
+
+  /* A 32-bit offset from GOT to (local) symbol: no GOT entry should be
+     necessary.
+     The BFD equivalent is BFD_RELOC_CRIS_32_GOTREL.  */
+  RELOC_NUMBER (R_CRIS_32_GOTREL, 17)
+
+  /* A 32-bit offset from GOT to entry for this symbol in PLT and request
+     to create PLT entry for symbol.
+     The BFD equivalent is BFD_RELOC_CRIS_32_GOTREL.  */
+  RELOC_NUMBER (R_CRIS_32_PLT_GOTREL, 18)
+
+  /* A 32-bit offset from location after this relocation (addend specifies
+     offset) to entry for this symbol in PLT and request to create PLT
+     entry for symbol.
+     The BFD equivalent is BFD_RELOC_CRIS_32_PLT_PCREL.  */
+  RELOC_NUMBER (R_CRIS_32_PLT_PCREL, 19)
+
+  /* An assembler-generated-only relocation, instructing the linker to
+     reserve two GOT slots, carrying the R_CRIS_DTP relocation for the
+     symbol (pointing to the first slot, the relocation fills in
+     both).  The value is a 32-bit-value, relative to the start of the
+     GOT.  Assembly syntax: "sym:GDGOTREL".  */
+  RELOC_NUMBER (R_CRIS_32_GOT_GD, 20)
+
+  /* Similar to R_CRIS_32_GOT_GD, but the value is a 16-bit unsigned
+     number, limiting access to 65536/4 global symbols per module (or
+     65536/8 thread variables; loosely speaking G*4+T*8 < 65536, where
+     T is the number of thread variables and G is the number of other
+     external global variables and functions).  Assembly syntax:
+     "sym:GDGOTREL16".  */
+  RELOC_NUMBER (R_CRIS_16_GOT_GD, 21)
+
+  /* Similar to R_CRIS_32_GOT_GD, but the value is the absolute
+     address of the GOT entry.  Disallowed in DSOs created with
+     -shared.  Assembly syntax: "sym:GD".  */
+  RELOC_NUMBER (R_CRIS_32_GD, 22)
+
+  /* A linker-generated-only relocation, instructing the dynamic
+     linker to fill in the module ID and module-relative-TLS-block
+     offset of the symbol in question, used for GOT entries.  Note
+     that this relocation instructs to fill in two 32-bit values.  */
+  RELOC_NUMBER (R_CRIS_DTP, 23)
+
+  /* An assembler-generated-only relocation, instructing the linker to
+     reserve the first two GOT slots, and attach the R_CRIS_DTPMOD
+     relocation(*) for the module to the first slot, the second
+     containing zero.  The value is 32 bits, the offset from the start
+     of the TLS block of the module to the thread-local symbol
+     mentioned in the relocation.  This relocation must only be applied
+     to module-local symbols.  Assembly syntax: "expr:DTPREL".  */
+  RELOC_NUMBER (R_CRIS_32_DTPREL, 24)
+
+  /* Similar to R_CRIS_32_DTPREL, but the value is a 16-bit signed
+     number, limiting the size of thread-variables of the DSO to 32768
+     bytes.  (Note: matches both model 1 and 2 and allows use of addo.w
+     as the instruction where this relocation is used.)  Assembly
+     syntax: "expr:DTPREL16".  */
+  RELOC_NUMBER (R_CRIS_16_DTPREL, 25)
+
+  /* An assembler-generated-only relocation, instructing the linker to
+     reserve a GOT slot and attach the R_CRIS_32_TPREL relocation for
+     the symbol in question.  The value is 32 bits, which is the
+     GOT-relative offset of the slot.  Assembly syntax:
+     "sym:TPOFFGOT".  */
+  RELOC_NUMBER (R_CRIS_32_GOT_TPREL, 26)
+
+  /* Similar to R_CRIS_32_TPREL, but the value is a 16-bit positive
+     number, limiting the number of thread- and global variables of
+     the DSO to 32768/4.  Assembly syntax: "sym:TPOFFGOT16".  */
+  RELOC_NUMBER (R_CRIS_16_GOT_TPREL, 27)
+
+  /* An assembler- and linker-generated relocation, instructing to
+     resolve the symbol in question yielding the TLS offset of the
+     thread variable, relative to the global TLS block.  Not allowed
+     as input when generating a DSO.  Assembly syntax:
+     "expr:TPOFF".  */
+  RELOC_NUMBER (R_CRIS_32_TPREL, 28)
+
+  /* Similar to R_CRIS_32_TPREL, but only applicable to executables
+     compiled with -msmall-tls. Not allowed in a DSO. The value is a
+     16-bit signed number, limiting the size of thread-variables of
+     the executable to 32768 bytes. (Note: being signed makes it match
+     both model 1 and 2 and allows use of addo.w as the instruction
+     where this relocation is applied.)  Assembly syntax:
+     "expr:TPOFF16".  */
+  RELOC_NUMBER (R_CRIS_16_TPREL, 29)
+
+  /* A linker-generated-only relocation, instructing the dynamic
+     linker to fill in the current module ID, used for GOT entries
+     (usually the fourth one).  */
+  RELOC_NUMBER (R_CRIS_DTPMOD, 30)
+
+  /* Similar to R_CRIS_32_GOT_TPREL, but the value is the absolute
+     address of the GOT entry.  Disallowed in DSOs created with
+     -shared.  Assembly syntax: "sym:IE".  */
+  RELOC_NUMBER (R_CRIS_32_IE, 31)
+
+  /* No other relocs must be visible outside the assembler.  */
+
+END_RELOC_NUMBERS (R_CRIS_max)
+
+/* User symbols in this file have a leading underscore.  */
+#define EF_CRIS_UNDERSCORE		0x00000001
+
+/* This is a mask for different incompatible machine variants.  */
+#define EF_CRIS_VARIANT_MASK		0x0000000e
+
+/* Variant 0; may contain v0..10 object.  */
+#define EF_CRIS_VARIANT_ANY_V0_V10	0x00000000
+
+/* Variant 1; contains v32 object.  */
+#define EF_CRIS_VARIANT_V32		0x00000002
+
+/* Variant 2; contains object compatible with v32 and v10.  */
+#define EF_CRIS_VARIANT_COMMON_V10_V32	0x00000004
+
+#endif /* _ELF_CRIS_H */
diff --git a/binutils-2.25/include/elf/crx.h b/binutils-2.25/include/elf/crx.h
new file mode 100644
index 00000000..38428f29
--- /dev/null
+++ b/binutils-2.25/include/elf/crx.h
@@ -0,0 +1,53 @@
+/* CRX ELF support for BFD.
+   Copyright 2004, 2010 Free Software Foundation, Inc.
+   Contributed by Tomer Levi, NSC, Israel.
+   Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
+   Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_CRX_H
+#define _ELF_CRX_H
+
+#include "elf/reloc-macros.h"
+
+/* Creating indices for reloc_map_index array.  */
+START_RELOC_NUMBERS(elf_crx_reloc_type)
+  RELOC_NUMBER (R_CRX_NONE,           0)
+  RELOC_NUMBER (R_CRX_REL4,           1)
+  RELOC_NUMBER (R_CRX_REL8,           2)
+  RELOC_NUMBER (R_CRX_REL8_CMP,       3)
+  RELOC_NUMBER (R_CRX_REL16,          4)
+  RELOC_NUMBER (R_CRX_REL24,          5)
+  RELOC_NUMBER (R_CRX_REL32,          6)
+  RELOC_NUMBER (R_CRX_REGREL12,       7)
+  RELOC_NUMBER (R_CRX_REGREL22,       8)
+  RELOC_NUMBER (R_CRX_REGREL28,       9)
+  RELOC_NUMBER (R_CRX_REGREL32,       10)
+  RELOC_NUMBER (R_CRX_ABS16,          11)
+  RELOC_NUMBER (R_CRX_ABS32,          12)
+  RELOC_NUMBER (R_CRX_NUM8,	      13)
+  RELOC_NUMBER (R_CRX_NUM16,          14)
+  RELOC_NUMBER (R_CRX_NUM32,          15)
+  RELOC_NUMBER (R_CRX_IMM16,	      16)
+  RELOC_NUMBER (R_CRX_IMM32,	      17)
+  RELOC_NUMBER (R_CRX_SWITCH8,	      18)
+  RELOC_NUMBER (R_CRX_SWITCH16,	      19)
+  RELOC_NUMBER (R_CRX_SWITCH32,	      20)
+END_RELOC_NUMBERS(R_CRX_MAX)
+	
+#endif /* _ELF_CRX_H */
diff --git a/binutils-2.25/include/elf/d10v.h b/binutils-2.25/include/elf/d10v.h
new file mode 100644
index 00000000..5850b374
--- /dev/null
+++ b/binutils-2.25/include/elf/d10v.h
@@ -0,0 +1,38 @@
+/* d10v ELF support for BFD.
+   Copyright 1998, 2000, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_D10V_H
+#define _ELF_D10V_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocation types.  */
+START_RELOC_NUMBERS (elf_d10v_reloc_type)
+  RELOC_NUMBER (R_D10V_NONE, 0)
+  RELOC_NUMBER (R_D10V_10_PCREL_R, 1)
+  RELOC_NUMBER (R_D10V_10_PCREL_L, 2)
+  RELOC_NUMBER (R_D10V_16, 3)
+  RELOC_NUMBER (R_D10V_18, 4)
+  RELOC_NUMBER (R_D10V_18_PCREL, 5)
+  RELOC_NUMBER (R_D10V_32, 6)
+  RELOC_NUMBER (R_D10V_GNU_VTINHERIT, 7)
+  RELOC_NUMBER (R_D10V_GNU_VTENTRY, 8)
+END_RELOC_NUMBERS (R_D10V_max)
+
+#endif
diff --git a/binutils-2.25/include/elf/d30v.h b/binutils-2.25/include/elf/d30v.h
new file mode 100644
index 00000000..8174a40e
--- /dev/null
+++ b/binutils-2.25/include/elf/d30v.h
@@ -0,0 +1,42 @@
+/* d30v ELF support for BFD.
+   Copyright 1998, 2000, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_D30V_H
+#define _ELF_D30V_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_d30v_reloc_type)
+  RELOC_NUMBER (R_D30V_NONE, 0)
+  RELOC_NUMBER (R_D30V_6, 1)
+  RELOC_NUMBER (R_D30V_9_PCREL, 2)
+  RELOC_NUMBER (R_D30V_9_PCREL_R, 3)
+  RELOC_NUMBER (R_D30V_15, 4)
+  RELOC_NUMBER (R_D30V_15_PCREL, 5)
+  RELOC_NUMBER (R_D30V_15_PCREL_R, 6)
+  RELOC_NUMBER (R_D30V_21, 7)
+  RELOC_NUMBER (R_D30V_21_PCREL, 8)
+  RELOC_NUMBER (R_D30V_21_PCREL_R, 9)
+  RELOC_NUMBER (R_D30V_32, 10)
+  RELOC_NUMBER (R_D30V_32_PCREL, 11)
+  RELOC_NUMBER (R_D30V_32_NORMAL, 12)
+END_RELOC_NUMBERS (R_D30V_max)
+
+#endif
diff --git a/binutils-2.25/include/elf/dlx.h b/binutils-2.25/include/elf/dlx.h
new file mode 100644
index 00000000..7d61633c
--- /dev/null
+++ b/binutils-2.25/include/elf/dlx.h
@@ -0,0 +1,53 @@
+/* DLX support for BFD.
+   Copyright 2002, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_DLX_H
+#define _ELF_DLX_H
+
+#include "elf/reloc-macros.h"
+
+#if 0
+START_RELOC_NUMBERS (elf_dlx_reloc_type)
+     RELOC_NUMBER (R_DLX_NONE,            0)
+     RELOC_NUMBER (R_DLX_RELOC_16,        1)
+     RELOC_NUMBER (R_DLX_RELOC_26,        2)
+     RELOC_NUMBER (R_DLX_RELOC_32,        3)
+     RELOC_NUMBER (R_DLX_GNU_VTINHERIT,   4)
+     RELOC_NUMBER (R_DLX_GNU_VTENTRY,     5)
+     RELOC_NUMBER (R_DLX_RELOC_16_HI,     6)
+     RELOC_NUMBER (R_DLX_RELOC_16_LO,     7)
+     RELOC_NUMBER (R_DLX_RELOC_16_PCREL,  8)
+     RELOC_NUMBER (R_DLX_RELOC_26_PCREL,  9)
+END_RELOC_NUMBERS (R_DLX_max)
+#else
+START_RELOC_NUMBERS (elf_dlx_reloc_type)
+     RELOC_NUMBER (R_DLX_NONE,            0)
+     RELOC_NUMBER (R_DLX_RELOC_8,         1)
+     RELOC_NUMBER (R_DLX_RELOC_16,        2)
+     RELOC_NUMBER (R_DLX_RELOC_32,        3)
+     RELOC_NUMBER (R_DLX_GNU_VTINHERIT,   4)
+     RELOC_NUMBER (R_DLX_GNU_VTENTRY,     5)
+     RELOC_NUMBER (R_DLX_RELOC_16_HI,     6)
+     RELOC_NUMBER (R_DLX_RELOC_16_LO,     7)
+     RELOC_NUMBER (R_DLX_RELOC_16_PCREL,  8)
+     RELOC_NUMBER (R_DLX_RELOC_26_PCREL,  9)
+END_RELOC_NUMBERS (R_DLX_max)
+#endif /* 0 */
+
+#endif /* _ELF_DLX_H */
diff --git a/binutils-2.25/include/elf/dwarf.h b/binutils-2.25/include/elf/dwarf.h
new file mode 100644
index 00000000..c2e6a67e
--- /dev/null
+++ b/binutils-2.25/include/elf/dwarf.h
@@ -0,0 +1,323 @@
+/* Declarations and definitions of codes relating to the DWARF symbolic
+   debugging information format.
+
+   Written by Ron Guilmette (rfg@netcom.com)
+
+   Copyright 1992, 1993, 1995, 1999, 2005, 2010 Free Software Foundation, Inc.
+
+   This file is part of both GCC and the BFD library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+/* This file is derived from the DWARF specification (a public document)
+   Revision 1.0.1 (April 8, 1992) developed by the UNIX International
+   Programming Languages Special Interest Group (UI/PLSIG) and distributed
+   by UNIX International.  Copies of this specification are available from
+   UNIX International, 20 Waterview Boulevard, Parsippany, NJ, 07054.  */
+
+#ifndef _ELF_DWARF_H
+#define _ELF_DWARF_H
+
+/* Tag names and codes.  */
+
+enum dwarf_tag {
+    TAG_padding			= 0x0000,
+    TAG_array_type		= 0x0001,
+    TAG_class_type		= 0x0002,
+    TAG_entry_point		= 0x0003,
+    TAG_enumeration_type	= 0x0004,
+    TAG_formal_parameter	= 0x0005,
+    TAG_global_subroutine	= 0x0006,
+    TAG_global_variable		= 0x0007,
+    				/* 0x0008 -- reserved */
+				/* 0x0009 -- reserved */
+    TAG_label			= 0x000a,
+    TAG_lexical_block		= 0x000b,
+    TAG_local_variable		= 0x000c,
+    TAG_member			= 0x000d,
+				/* 0x000e -- reserved */
+    TAG_pointer_type		= 0x000f,
+    TAG_reference_type		= 0x0010,
+    TAG_compile_unit		= 0x0011,
+    TAG_string_type		= 0x0012,
+    TAG_structure_type		= 0x0013,
+    TAG_subroutine		= 0x0014,
+    TAG_subroutine_type		= 0x0015,
+    TAG_typedef			= 0x0016,
+    TAG_union_type		= 0x0017,
+    TAG_unspecified_parameters	= 0x0018,
+    TAG_variant			= 0x0019,
+    TAG_common_block		= 0x001a,
+    TAG_common_inclusion	= 0x001b,
+    TAG_inheritance		= 0x001c,
+    TAG_inlined_subroutine	= 0x001d,
+    TAG_module			= 0x001e,
+    TAG_ptr_to_member_type	= 0x001f,
+    TAG_set_type		= 0x0020,
+    TAG_subrange_type		= 0x0021,
+    TAG_with_stmt		= 0x0022,
+
+    /* GNU extensions */
+
+    TAG_format_label		= 0x8000,  /* for FORTRAN 77 and Fortran 90 */
+    TAG_namelist		= 0x8001,  /* For Fortran 90 */
+    TAG_function_template	= 0x8002,  /* for C++ */
+    TAG_class_template		= 0x8003   /* for C++ */
+};
+
+#define TAG_lo_user	0x8000  /* implementation-defined range start */
+#define TAG_hi_user	0xffff  /* implementation-defined range end */
+#define TAG_source_file TAG_compile_unit  /* for backward compatibility */
+
+/* Form names and codes.  */
+
+enum dwarf_form {
+    FORM_ADDR	= 0x1,
+    FORM_REF	= 0x2,
+    FORM_BLOCK2	= 0x3,
+    FORM_BLOCK4	= 0x4,
+    FORM_DATA2	= 0x5,
+    FORM_DATA4	= 0x6,
+    FORM_DATA8	= 0x7,
+    FORM_STRING	= 0x8
+};
+
+/* Attribute names and codes.  */
+
+enum dwarf_attribute {
+    AT_sibling			= (0x0010|FORM_REF),
+    AT_location			= (0x0020|FORM_BLOCK2),
+    AT_name			= (0x0030|FORM_STRING),
+    AT_fund_type		= (0x0050|FORM_DATA2),
+    AT_mod_fund_type		= (0x0060|FORM_BLOCK2),
+    AT_user_def_type		= (0x0070|FORM_REF),
+    AT_mod_u_d_type		= (0x0080|FORM_BLOCK2),
+    AT_ordering			= (0x0090|FORM_DATA2),
+    AT_subscr_data		= (0x00a0|FORM_BLOCK2),
+    AT_byte_size		= (0x00b0|FORM_DATA4),
+    AT_bit_offset		= (0x00c0|FORM_DATA2),
+    AT_bit_size			= (0x00d0|FORM_DATA4),
+				/* (0x00e0|FORM_xxxx) -- reserved */
+    AT_element_list		= (0x00f0|FORM_BLOCK4),
+    AT_stmt_list		= (0x0100|FORM_DATA4),
+    AT_low_pc			= (0x0110|FORM_ADDR),
+    AT_high_pc			= (0x0120|FORM_ADDR),
+    AT_language			= (0x0130|FORM_DATA4),
+    AT_member			= (0x0140|FORM_REF),
+    AT_discr			= (0x0150|FORM_REF),
+    AT_discr_value		= (0x0160|FORM_BLOCK2),
+				/* (0x0170|FORM_xxxx) -- reserved */
+				/* (0x0180|FORM_xxxx) -- reserved */
+    AT_string_length		= (0x0190|FORM_BLOCK2),
+    AT_common_reference		= (0x01a0|FORM_REF),
+    AT_comp_dir			= (0x01b0|FORM_STRING),
+        AT_const_value_string	= (0x01c0|FORM_STRING),
+        AT_const_value_data2	= (0x01c0|FORM_DATA2),
+        AT_const_value_data4	= (0x01c0|FORM_DATA4),
+        AT_const_value_data8	= (0x01c0|FORM_DATA8),
+        AT_const_value_block2	= (0x01c0|FORM_BLOCK2),
+        AT_const_value_block4	= (0x01c0|FORM_BLOCK4),
+    AT_containing_type		= (0x01d0|FORM_REF),
+        AT_default_value_addr	= (0x01e0|FORM_ADDR),
+        AT_default_value_data2	= (0x01e0|FORM_DATA2),
+        AT_default_value_data4	= (0x01e0|FORM_DATA4),
+        AT_default_value_data8	= (0x01e0|FORM_DATA8),
+        AT_default_value_string	= (0x01e0|FORM_STRING),
+    AT_friends			= (0x01f0|FORM_BLOCK2),
+    AT_inline			= (0x0200|FORM_STRING),
+    AT_is_optional		= (0x0210|FORM_STRING),
+        AT_lower_bound_ref	= (0x0220|FORM_REF),
+        AT_lower_bound_data2	= (0x0220|FORM_DATA2),
+        AT_lower_bound_data4	= (0x0220|FORM_DATA4),
+        AT_lower_bound_data8	= (0x0220|FORM_DATA8),
+    AT_private			= (0x0240|FORM_STRING),
+    AT_producer			= (0x0250|FORM_STRING),
+    AT_program			= (0x0230|FORM_STRING),
+    AT_protected		= (0x0260|FORM_STRING),
+    AT_prototyped		= (0x0270|FORM_STRING),
+    AT_public			= (0x0280|FORM_STRING),
+    AT_pure_virtual		= (0x0290|FORM_STRING),
+    AT_return_addr		= (0x02a0|FORM_BLOCK2),
+    AT_abstract_origin		= (0x02b0|FORM_REF),
+    AT_start_scope		= (0x02c0|FORM_DATA4),
+    AT_stride_size		= (0x02e0|FORM_DATA4),
+        AT_upper_bound_ref	= (0x02f0|FORM_REF),
+        AT_upper_bound_data2	= (0x02f0|FORM_DATA2),
+        AT_upper_bound_data4	= (0x02f0|FORM_DATA4),
+        AT_upper_bound_data8	= (0x02f0|FORM_DATA8),
+    AT_virtual			= (0x0300|FORM_STRING),
+
+    /* GNU extensions.  */
+
+    AT_sf_names			= (0x8000|FORM_DATA4),
+    AT_src_info			= (0x8010|FORM_DATA4),
+    AT_mac_info			= (0x8020|FORM_DATA4),
+    AT_src_coords		= (0x8030|FORM_DATA4),
+    AT_body_begin		= (0x8040|FORM_ADDR),
+    AT_body_end			= (0x8050|FORM_ADDR)
+};
+
+#define AT_lo_user	0x2000	/* implementation-defined range start */
+#define AT_hi_user	0x3ff0	/* implementation-defined range end */
+
+/* Location atom names and codes.  */
+
+enum dwarf_location_atom {
+    OP_REG	= 0x01,
+    OP_BASEREG	= 0x02,
+    OP_ADDR	= 0x03,
+    OP_CONST	= 0x04,
+    OP_DEREF2	= 0x05,
+    OP_DEREF4	= 0x06,
+    OP_ADD	= 0x07,
+
+    /* GNU extensions.  */
+
+    OP_MULT	= 0x80
+};
+
+#define OP_LO_USER	0x80  /* implementation-defined range start */
+#define OP_HI_USER	0xff  /* implementation-defined range end */
+
+/* Fundamental type names and codes.  */
+
+enum dwarf_fundamental_type {
+    FT_char		= 0x0001,
+    FT_signed_char	= 0x0002,
+    FT_unsigned_char	= 0x0003,
+    FT_short		= 0x0004,
+    FT_signed_short	= 0x0005,
+    FT_unsigned_short	= 0x0006,
+    FT_integer		= 0x0007,
+    FT_signed_integer	= 0x0008,
+    FT_unsigned_integer	= 0x0009,
+    FT_long		= 0x000a,
+    FT_signed_long	= 0x000b,
+    FT_unsigned_long	= 0x000c,
+    FT_pointer		= 0x000d,  /* an alias for (void *) */
+    FT_float		= 0x000e,
+    FT_dbl_prec_float	= 0x000f,
+    FT_ext_prec_float	= 0x0010,  /* breaks "classic" svr4 SDB */
+    FT_complex		= 0x0011,  /* breaks "classic" svr4 SDB */
+    FT_dbl_prec_complex	= 0x0012,  /* breaks "classic" svr4 SDB */
+			/* 0x0013 -- reserved */
+    FT_void		= 0x0014,
+    FT_boolean		= 0x0015,  /* breaks "classic" svr4 SDB */
+    FT_ext_prec_complex	= 0x0016,  /* breaks "classic" svr4 SDB */
+    FT_label		= 0x0017,
+  
+    /* GNU extensions
+       The low order byte must indicate the size (in bytes) for the type.
+       All of these types will probably break "classic" svr4 SDB.  */
+
+    FT_long_long	= 0x8008,
+    FT_signed_long_long	= 0x8108,
+    FT_unsigned_long_long = 0x8208,
+
+    FT_int8		= 0x9001,
+    FT_signed_int8	= 0x9101,
+    FT_unsigned_int8	= 0x9201,
+    FT_int16		= 0x9302,
+    FT_signed_int16	= 0x9402,
+    FT_unsigned_int16	= 0x9502,
+    FT_int32		= 0x9604,
+    FT_signed_int32	= 0x9704,
+    FT_unsigned_int32	= 0x9804,
+    FT_int64		= 0x9908,
+    FT_signed_int64	= 0x9a08,
+    FT_unsigned_int64	= 0x9b08,
+    FT_int128		= 0x9c10,
+    FT_signed_int128	= 0x9d10,
+    FT_unsigned_int128	= 0x9e10,
+
+    FT_real32		= 0xa004,
+    FT_real64		= 0xa108,
+    FT_real96		= 0xa20c,
+    FT_real128		= 0xa310
+};
+
+#define FT_lo_user	0x8000  /* implementation-defined range start */
+#define FT_hi_user	0xffff  /* implementation defined range end */
+
+/* Type modifier names and codes.  */
+
+enum dwarf_type_modifier {
+    MOD_pointer_to	= 0x01,
+    MOD_reference_to	= 0x02,
+    MOD_const		= 0x03,
+    MOD_volatile	= 0x04
+};
+
+#define MOD_lo_user	0x80  /* implementation-defined range start */
+#define MOD_hi_user	0xff  /* implementation-defined range end */
+
+/* Array ordering names and codes.  */
+
+enum dwarf_array_dim_ordering {
+    ORD_row_major	= 0,
+    ORD_col_major	= 1
+};
+
+/* Array subscript format names and codes.  */
+
+enum dwarf_subscr_data_formats {
+    FMT_FT_C_C	= 0x0,
+    FMT_FT_C_X	= 0x1,
+    FMT_FT_X_C	= 0x2,
+    FMT_FT_X_X	= 0x3,
+    FMT_UT_C_C	= 0x4,
+    FMT_UT_C_X	= 0x5,
+    FMT_UT_X_C	= 0x6,
+    FMT_UT_X_X	= 0x7,
+    FMT_ET	= 0x8
+};
+
+/* Derived from above for ease of use.  */
+
+#define FMT_CODE(_FUNDAMENTAL_TYPE_P, _LB_CONST_P, _UB_CONST_P) \
+ (((_FUNDAMENTAL_TYPE_P) ? 0 : 4)	\
+  | ((_LB_CONST_P) ? 0 : 2)		\
+  | ((_UB_CONST_P) ? 0 : 1))
+
+/* Source language names and codes.  */
+
+enum dwarf_source_language {
+    LANG_C89		= 0x00000001,
+    LANG_C		= 0x00000002,
+    LANG_ADA83		= 0x00000003,
+    LANG_C_PLUS_PLUS	= 0x00000004,
+    LANG_COBOL74	= 0x00000005,
+    LANG_COBOL85	= 0x00000006,
+    LANG_FORTRAN77	= 0x00000007,
+    LANG_FORTRAN90	= 0x00000008,
+    LANG_PASCAL83	= 0x00000009,
+    LANG_MODULA2	= 0x0000000a,
+    LANG_JAVA		= 0x0000000b
+};
+
+#define LANG_lo_user	0x00008000  /* implementation-defined range start */
+#define LANG_hi_user	0x0000ffff  /* implementation-defined range end */
+
+/* Names and codes for GNU "macinfo" extension.  */
+
+enum dwarf_macinfo_record_type {
+    MACINFO_start	= 's',
+    MACINFO_resume	= 'r',
+    MACINFO_define	= 'd',
+    MACINFO_undef	= 'u'
+};
+
+#endif /* _ELF_DWARF_H */
diff --git a/binutils-2.25/include/elf/epiphany.h b/binutils-2.25/include/elf/epiphany.h
new file mode 100755
index 00000000..bb2dcffe
--- /dev/null
+++ b/binutils-2.25/include/elf/epiphany.h
@@ -0,0 +1,59 @@
+/* Adapteva EPIPHANY ELF support for BFD.
+   Copyright (C) 2009, 2011 Free Software Foundation, Inc.
+   Contributed by Embecosm on behalf of Adapteva, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_EPIPHANY_H
+#define _ELF_EPIPHANY_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_epiphany_reloc_type)
+  RELOC_NUMBER (R_EPIPHANY_NONE,    0)
+
+  /* Absolute address relocations.  */
+  RELOC_NUMBER (R_EPIPHANY_8,       1)
+  RELOC_NUMBER (R_EPIPHANY_16,      2)
+  RELOC_NUMBER (R_EPIPHANY_32,      3)
+
+  /* PC-relative relocations.  */
+  RELOC_NUMBER (R_EPIPHANY_8_PCREL, 4)
+  RELOC_NUMBER (R_EPIPHANY_16_PCREL,5)
+  RELOC_NUMBER (R_EPIPHANY_32_PCREL,6)
+
+  /* special forms for 8/24 bit branch displacements.  */
+  RELOC_NUMBER (R_EPIPHANY_SIMM8,   7)
+  RELOC_NUMBER (R_EPIPHANY_SIMM24,  8)
+
+  /* HIGH and LOW relocations taking part of a 32 bit address and
+     depositing it into the IMM16 field of a destination.  */
+  RELOC_NUMBER (R_EPIPHANY_HIGH, 9)
+  RELOC_NUMBER (R_EPIPHANY_LOW,10)
+
+  /* 11 bit signed immediate value.  */
+  RELOC_NUMBER (R_EPIPHANY_SIMM11, 11)
+  /* 11 bit magnitude addressing displacement.  */
+  RELOC_NUMBER (R_EPIPHANY_IMM11, 12)
+
+  /* 8 bit immediate for MOV.S R,IMM8.  */
+  RELOC_NUMBER (R_EPIPHANY_IMM8, 13)
+
+END_RELOC_NUMBERS(R_EPIPHANY_max)
+
+#endif /* _ELF_EPIPHANY_H */
diff --git a/binutils-2.25/include/elf/external.h b/binutils-2.25/include/elf/external.h
new file mode 100644
index 00000000..ef7724e9
--- /dev/null
+++ b/binutils-2.25/include/elf/external.h
@@ -0,0 +1,288 @@
+/* ELF support for BFD.
+   Copyright 1991, 1992, 1993, 1995, 1997, 1998, 1999, 2001, 2003, 2005,
+   2008, 2010 Free Software Foundation, Inc.
+
+   Written by Fred Fish @ Cygnus Support, from information published
+   in "UNIX System V Release 4, Programmers Guide: ANSI C and
+   Programming Support Tools".
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file is part of ELF support for BFD, and contains the portions
+   that describe how ELF is represented externally by the BFD library.
+   I.E. it describes the in-file representation of ELF.  It requires
+   the elf/common.h file which contains the portions that are common to
+   both the internal and external representations.  */
+
+/* The 64-bit stuff is kind of random.  Perhaps someone will publish a
+   spec someday.  */
+
+#ifndef _ELF_EXTERNAL_H
+#define _ELF_EXTERNAL_H
+
+/* Special section indices, which may show up in st_shndx fields, among
+   other places.  */
+
+#define SHN_LORESERVE	0xFF00		/* Begin range of reserved indices */
+#define SHN_LOPROC	0xFF00		/* Begin range of appl-specific */
+#define SHN_HIPROC	0xFF1F		/* End range of appl-specific */
+#define SHN_LOOS	0xFF20		/* OS specific semantics, lo */
+#define SHN_HIOS	0xFF3F		/* OS specific semantics, hi */
+#define SHN_ABS		0xFFF1		/* Associated symbol is absolute */
+#define SHN_COMMON	0xFFF2		/* Associated symbol is in common */
+#define SHN_XINDEX	0xFFFF		/* Section index is held elsewhere */
+#define SHN_HIRESERVE	0xFFFF		/* End range of reserved indices */
+
+/* ELF Header (32-bit implementations) */
+
+typedef struct {
+  unsigned char	e_ident[16];		/* ELF "magic number" */
+  unsigned char	e_type[2];		/* Identifies object file type */
+  unsigned char	e_machine[2];		/* Specifies required architecture */
+  unsigned char	e_version[4];		/* Identifies object file version */
+  unsigned char	e_entry[4];		/* Entry point virtual address */
+  unsigned char	e_phoff[4];		/* Program header table file offset */
+  unsigned char	e_shoff[4];		/* Section header table file offset */
+  unsigned char	e_flags[4];		/* Processor-specific flags */
+  unsigned char	e_ehsize[2];		/* ELF header size in bytes */
+  unsigned char	e_phentsize[2];		/* Program header table entry size */
+  unsigned char	e_phnum[2];		/* Program header table entry count */
+  unsigned char	e_shentsize[2];		/* Section header table entry size */
+  unsigned char	e_shnum[2];		/* Section header table entry count */
+  unsigned char	e_shstrndx[2];		/* Section header string table index */
+} Elf32_External_Ehdr;
+
+typedef struct {
+  unsigned char	e_ident[16];		/* ELF "magic number" */
+  unsigned char	e_type[2];		/* Identifies object file type */
+  unsigned char	e_machine[2];		/* Specifies required architecture */
+  unsigned char	e_version[4];		/* Identifies object file version */
+  unsigned char	e_entry[8];		/* Entry point virtual address */
+  unsigned char	e_phoff[8];		/* Program header table file offset */
+  unsigned char	e_shoff[8];		/* Section header table file offset */
+  unsigned char	e_flags[4];		/* Processor-specific flags */
+  unsigned char	e_ehsize[2];		/* ELF header size in bytes */
+  unsigned char	e_phentsize[2];		/* Program header table entry size */
+  unsigned char	e_phnum[2];		/* Program header table entry count */
+  unsigned char	e_shentsize[2];		/* Section header table entry size */
+  unsigned char	e_shnum[2];		/* Section header table entry count */
+  unsigned char	e_shstrndx[2];		/* Section header string table index */
+} Elf64_External_Ehdr;
+
+/* Program header */
+
+typedef struct {
+  unsigned char	p_type[4];		/* Identifies program segment type */
+  unsigned char	p_offset[4];		/* Segment file offset */
+  unsigned char	p_vaddr[4];		/* Segment virtual address */
+  unsigned char	p_paddr[4];		/* Segment physical address */
+  unsigned char	p_filesz[4];		/* Segment size in file */
+  unsigned char	p_memsz[4];		/* Segment size in memory */
+  unsigned char	p_flags[4];		/* Segment flags */
+  unsigned char	p_align[4];		/* Segment alignment, file & memory */
+} Elf32_External_Phdr;
+
+typedef struct {
+  unsigned char	p_type[4];		/* Identifies program segment type */
+  unsigned char	p_flags[4];		/* Segment flags */
+  unsigned char	p_offset[8];		/* Segment file offset */
+  unsigned char	p_vaddr[8];		/* Segment virtual address */
+  unsigned char	p_paddr[8];		/* Segment physical address */
+  unsigned char	p_filesz[8];		/* Segment size in file */
+  unsigned char	p_memsz[8];		/* Segment size in memory */
+  unsigned char	p_align[8];		/* Segment alignment, file & memory */
+} Elf64_External_Phdr;
+
+/* Section header */
+
+typedef struct {
+  unsigned char	sh_name[4];		/* Section name, index in string tbl */
+  unsigned char	sh_type[4];		/* Type of section */
+  unsigned char	sh_flags[4];		/* Miscellaneous section attributes */
+  unsigned char	sh_addr[4];		/* Section virtual addr at execution */
+  unsigned char	sh_offset[4];		/* Section file offset */
+  unsigned char	sh_size[4];		/* Size of section in bytes */
+  unsigned char	sh_link[4];		/* Index of another section */
+  unsigned char	sh_info[4];		/* Additional section information */
+  unsigned char	sh_addralign[4];	/* Section alignment */
+  unsigned char	sh_entsize[4];		/* Entry size if section holds table */
+} Elf32_External_Shdr;
+
+typedef struct {
+  unsigned char	sh_name[4];		/* Section name, index in string tbl */
+  unsigned char	sh_type[4];		/* Type of section */
+  unsigned char	sh_flags[8];		/* Miscellaneous section attributes */
+  unsigned char	sh_addr[8];		/* Section virtual addr at execution */
+  unsigned char	sh_offset[8];		/* Section file offset */
+  unsigned char	sh_size[8];		/* Size of section in bytes */
+  unsigned char	sh_link[4];		/* Index of another section */
+  unsigned char	sh_info[4];		/* Additional section information */
+  unsigned char	sh_addralign[8];	/* Section alignment */
+  unsigned char	sh_entsize[8];		/* Entry size if section holds table */
+} Elf64_External_Shdr;
+
+/* Symbol table entry */
+
+typedef struct {
+  unsigned char	st_name[4];		/* Symbol name, index in string tbl */
+  unsigned char	st_value[4];		/* Value of the symbol */
+  unsigned char	st_size[4];		/* Associated symbol size */
+  unsigned char	st_info[1];		/* Type and binding attributes */
+  unsigned char	st_other[1];		/* No defined meaning, 0 */
+  unsigned char	st_shndx[2];		/* Associated section index */
+} Elf32_External_Sym;
+
+typedef struct {
+  unsigned char	st_name[4];		/* Symbol name, index in string tbl */
+  unsigned char	st_info[1];		/* Type and binding attributes */
+  unsigned char	st_other[1];		/* No defined meaning, 0 */
+  unsigned char	st_shndx[2];		/* Associated section index */
+  unsigned char	st_value[8];		/* Value of the symbol */
+  unsigned char	st_size[8];		/* Associated symbol size */
+} Elf64_External_Sym;
+
+typedef struct {
+  unsigned char est_shndx[4];		/* Section index */
+} Elf_External_Sym_Shndx;
+
+/* Note segments */
+
+typedef struct {
+  unsigned char	namesz[4];		/* Size of entry's owner string */
+  unsigned char	descsz[4];		/* Size of the note descriptor */
+  unsigned char	type[4];		/* Interpretation of the descriptor */
+  char		name[1];		/* Start of the name+desc data */
+} Elf_External_Note;
+
+/* Relocation Entries */
+typedef struct {
+  unsigned char r_offset[4];	/* Location at which to apply the action */
+  unsigned char	r_info[4];	/* index and type of relocation */
+} Elf32_External_Rel;
+
+typedef struct {
+  unsigned char r_offset[4];	/* Location at which to apply the action */
+  unsigned char	r_info[4];	/* index and type of relocation */
+  unsigned char	r_addend[4];	/* Constant addend used to compute value */
+} Elf32_External_Rela;
+
+typedef struct {
+  unsigned char r_offset[8];	/* Location at which to apply the action */
+  unsigned char	r_info[8];	/* index and type of relocation */
+} Elf64_External_Rel;
+
+typedef struct {
+  unsigned char r_offset[8];	/* Location at which to apply the action */
+  unsigned char	r_info[8];	/* index and type of relocation */
+  unsigned char	r_addend[8];	/* Constant addend used to compute value */
+} Elf64_External_Rela;
+
+/* dynamic section structure */
+
+typedef struct {
+  unsigned char	d_tag[4];		/* entry tag value */
+  union {
+    unsigned char	d_val[4];
+    unsigned char	d_ptr[4];
+  } d_un;
+} Elf32_External_Dyn;
+
+typedef struct {
+  unsigned char	d_tag[8];		/* entry tag value */
+  union {
+    unsigned char	d_val[8];
+    unsigned char	d_ptr[8];
+  } d_un;
+} Elf64_External_Dyn;
+
+/* The version structures are currently size independent.  They are
+   named without a 32 or 64.  If that ever changes, these structures
+   will need to be renamed.  */
+
+/* This structure appears in a SHT_GNU_verdef section.  */
+
+typedef struct {
+  unsigned char		vd_version[2];
+  unsigned char		vd_flags[2];
+  unsigned char		vd_ndx[2];
+  unsigned char		vd_cnt[2];
+  unsigned char		vd_hash[4];
+  unsigned char		vd_aux[4];
+  unsigned char		vd_next[4];
+} Elf_External_Verdef;
+
+/* This structure appears in a SHT_GNU_verdef section.  */
+
+typedef struct {
+  unsigned char		vda_name[4];
+  unsigned char		vda_next[4];
+} Elf_External_Verdaux;
+
+/* This structure appears in a SHT_GNU_verneed section.  */
+
+typedef struct {
+  unsigned char		vn_version[2];
+  unsigned char		vn_cnt[2];
+  unsigned char		vn_file[4];
+  unsigned char		vn_aux[4];
+  unsigned char		vn_next[4];
+} Elf_External_Verneed;
+
+/* This structure appears in a SHT_GNU_verneed section.  */
+
+typedef struct {
+  unsigned char		vna_hash[4];
+  unsigned char		vna_flags[2];
+  unsigned char		vna_other[2];
+  unsigned char		vna_name[4];
+  unsigned char		vna_next[4];
+} Elf_External_Vernaux;
+
+/* This structure appears in a SHT_GNU_versym section.  This is not a
+   standard ELF structure; ELF just uses Elf32_Half.  */
+
+typedef struct {
+  unsigned char		vs_vers[2];
+} ATTRIBUTE_PACKED  Elf_External_Versym;
+
+/* Structure for syminfo section.  */
+typedef struct
+{
+  unsigned char		si_boundto[2];
+  unsigned char		si_flags[2];
+} Elf_External_Syminfo;
+
+
+/* This structure appears on the stack and in NT_AUXV core file notes.  */
+typedef struct
+{
+  unsigned char		a_type[4];
+  unsigned char		a_val[4];
+} Elf32_External_Auxv;
+
+typedef struct
+{
+  unsigned char		a_type[8];
+  unsigned char		a_val[8];
+} Elf64_External_Auxv;
+
+/* Size of SHT_GROUP section entry.  */
+
+#define GRP_ENTRY_SIZE		4
+
+#endif /* _ELF_EXTERNAL_H */
diff --git a/binutils-2.25/include/elf/fr30.h b/binutils-2.25/include/elf/fr30.h
new file mode 100644
index 00000000..918ac977
--- /dev/null
+++ b/binutils-2.25/include/elf/fr30.h
@@ -0,0 +1,42 @@
+/* FR30 ELF support for BFD.
+   Copyright 1998, 1999, 2000, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_FR30_H
+#define _ELF_FR30_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_fr30_reloc_type)
+  RELOC_NUMBER (R_FR30_NONE, 0)
+  RELOC_NUMBER (R_FR30_8, 1)
+  RELOC_NUMBER (R_FR30_20, 2)
+  RELOC_NUMBER (R_FR30_32, 3)
+  RELOC_NUMBER (R_FR30_48, 4)
+  RELOC_NUMBER (R_FR30_6_IN_4, 5)
+  RELOC_NUMBER (R_FR30_8_IN_8, 6)
+  RELOC_NUMBER (R_FR30_9_IN_8, 7)
+  RELOC_NUMBER (R_FR30_10_IN_8, 8)
+  RELOC_NUMBER (R_FR30_9_PCREL, 9)
+  RELOC_NUMBER (R_FR30_12_PCREL, 10)
+  RELOC_NUMBER (R_FR30_GNU_VTINHERIT, 11)
+  RELOC_NUMBER (R_FR30_GNU_VTENTRY, 12)
+END_RELOC_NUMBERS (R_FR30_max)
+
+#endif /* _ELF_FR30_H */
diff --git a/binutils-2.25/include/elf/frv.h b/binutils-2.25/include/elf/frv.h
new file mode 100644
index 00000000..b79e51d0
--- /dev/null
+++ b/binutils-2.25/include/elf/frv.h
@@ -0,0 +1,130 @@
+/* FRV ELF support for BFD.
+   Copyright (C) 2002, 2003, 2004, 2005, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_FRV_H
+#define _ELF_FRV_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_frv_reloc_type)
+  RELOC_NUMBER (R_FRV_NONE, 0)
+  RELOC_NUMBER (R_FRV_32, 1)
+  RELOC_NUMBER (R_FRV_LABEL16, 2)
+  RELOC_NUMBER (R_FRV_LABEL24, 3)
+  RELOC_NUMBER (R_FRV_LO16, 4)
+  RELOC_NUMBER (R_FRV_HI16, 5)
+  RELOC_NUMBER (R_FRV_GPREL12, 6)
+  RELOC_NUMBER (R_FRV_GPRELU12, 7)
+  RELOC_NUMBER (R_FRV_GPREL32, 8)
+  RELOC_NUMBER (R_FRV_GPRELHI, 9)
+  RELOC_NUMBER (R_FRV_GPRELLO, 10)
+  RELOC_NUMBER (R_FRV_GOT12, 11)
+  RELOC_NUMBER (R_FRV_GOTHI, 12)
+  RELOC_NUMBER (R_FRV_GOTLO, 13)
+  RELOC_NUMBER (R_FRV_FUNCDESC, 14)
+  RELOC_NUMBER (R_FRV_FUNCDESC_GOT12, 15)
+  RELOC_NUMBER (R_FRV_FUNCDESC_GOTHI, 16)
+  RELOC_NUMBER (R_FRV_FUNCDESC_GOTLO, 17)
+  RELOC_NUMBER (R_FRV_FUNCDESC_VALUE, 18)
+  RELOC_NUMBER (R_FRV_FUNCDESC_GOTOFF12, 19)
+  RELOC_NUMBER (R_FRV_FUNCDESC_GOTOFFHI, 20)
+  RELOC_NUMBER (R_FRV_FUNCDESC_GOTOFFLO, 21)
+  RELOC_NUMBER (R_FRV_GOTOFF12, 22)
+  RELOC_NUMBER (R_FRV_GOTOFFHI, 23)
+  RELOC_NUMBER (R_FRV_GOTOFFLO, 24)
+  RELOC_NUMBER (R_FRV_GETTLSOFF, 25)
+  RELOC_NUMBER (R_FRV_TLSDESC_VALUE, 26)
+  RELOC_NUMBER (R_FRV_GOTTLSDESC12, 27)
+  RELOC_NUMBER (R_FRV_GOTTLSDESCHI, 28)
+  RELOC_NUMBER (R_FRV_GOTTLSDESCLO, 29)
+  RELOC_NUMBER (R_FRV_TLSMOFF12, 30)
+  RELOC_NUMBER (R_FRV_TLSMOFFHI, 31)
+  RELOC_NUMBER (R_FRV_TLSMOFFLO, 32)
+  RELOC_NUMBER (R_FRV_GOTTLSOFF12, 33)
+  RELOC_NUMBER (R_FRV_GOTTLSOFFHI, 34)
+  RELOC_NUMBER (R_FRV_GOTTLSOFFLO, 35)
+  RELOC_NUMBER (R_FRV_TLSOFF, 36)
+  RELOC_NUMBER (R_FRV_TLSDESC_RELAX, 37)
+  RELOC_NUMBER (R_FRV_GETTLSOFF_RELAX, 38)
+  RELOC_NUMBER (R_FRV_TLSOFF_RELAX, 39)
+  RELOC_NUMBER (R_FRV_TLSMOFF, 40)
+  RELOC_NUMBER (R_FRV_GNU_VTINHERIT, 200)
+  RELOC_NUMBER (R_FRV_GNU_VTENTRY, 201)
+END_RELOC_NUMBERS(R_FRV_max)
+
+/* Processor specific flags for the ELF header e_flags field.  */
+						/* gpr support */
+#define EF_FRV_GPR_MASK		0x00000003	/* mask for # of gprs */
+#define EF_FRV_GPR_32		0x00000001	/* -mgpr-32 */
+#define EF_FRV_GPR_64		0x00000002	/* -mgpr-64 */
+
+						/* fpr support */
+#define EF_FRV_FPR_MASK		0x0000000c	/* mask for # of fprs */
+#define EF_FRV_FPR_32		0x00000004	/* -mfpr-32 */
+#define EF_FRV_FPR_64		0x00000008	/* -mfpr-64 */
+#define EF_FRV_FPR_NONE		0x0000000c	/* -msoft-float */
+
+						/* double word support */
+#define EF_FRV_DWORD_MASK	0x00000030	/* mask for dword support */
+#define EF_FRV_DWORD_YES	0x00000010	/* use double word insns */
+#define EF_FRV_DWORD_NO		0x00000020	/* don't use double word insn*/
+
+#define EF_FRV_DOUBLE		0x00000040	/* -mdouble */
+#define EF_FRV_MEDIA		0x00000080	/* -mmedia */
+
+#define EF_FRV_PIC		0x00000100	/* -fpic */
+#define EF_FRV_NON_PIC_RELOCS	0x00000200	/* used non pic safe relocs */
+
+#define EF_FRV_MULADD		0x00000400	/* -mmuladd */
+#define EF_FRV_BIGPIC		0x00000800	/* -fPIC */
+#define	EF_FRV_LIBPIC		0x00001000	/* -mlibrary-pic */
+#define EF_FRV_G0		0x00002000	/* -G 0, no small data ptr */
+#define EF_FRV_NOPACK		0x00004000	/* -mnopack */
+#define EF_FRV_FDPIC		0x00008000      /* -mfdpic */
+
+#define	EF_FRV_CPU_MASK		0xff000000	/* specific cpu bits */
+#define EF_FRV_CPU_GENERIC	0x00000000	/* generic FRV */
+#define EF_FRV_CPU_FR500	0x01000000	/* FRV500 */
+#define EF_FRV_CPU_FR300	0x02000000	/* FRV300 */
+#define EF_FRV_CPU_SIMPLE	0x03000000	/* SIMPLE */
+#define EF_FRV_CPU_TOMCAT	0x04000000	/* Tomcat, FR500 prototype */
+#define EF_FRV_CPU_FR400	0x05000000	/* FRV400 */
+#define EF_FRV_CPU_FR550	0x06000000	/* FRV550 */
+#define EF_FRV_CPU_FR405	0x07000000
+#define EF_FRV_CPU_FR450	0x08000000
+
+						/* Mask of PIC related bits */
+#define	EF_FRV_PIC_FLAGS	(EF_FRV_PIC | EF_FRV_LIBPIC | EF_FRV_BIGPIC \
+				 | EF_FRV_FDPIC)
+
+						/* Mask of all flags */
+#define EF_FRV_ALL_FLAGS	(EF_FRV_GPR_MASK | \
+				 EF_FRV_FPR_MASK | \
+				 EF_FRV_DWORD_MASK | \
+				 EF_FRV_DOUBLE | \
+				 EF_FRV_MEDIA | \
+				 EF_FRV_PIC_FLAGS | \
+				 EF_FRV_NON_PIC_RELOCS | \
+				 EF_FRV_MULADD | \
+				 EF_FRV_G0 | \
+				 EF_FRV_NOPACK | \
+				 EF_FRV_CPU_MASK)
+
+#endif /* _ELF_FRV_H */
diff --git a/binutils-2.25/include/elf/h8.h b/binutils-2.25/include/elf/h8.h
new file mode 100644
index 00000000..2a3d905e
--- /dev/null
+++ b/binutils-2.25/include/elf/h8.h
@@ -0,0 +1,101 @@
+/* H8300/h8500 ELF support for BFD.
+   Copyright 2001-2013 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_H8_H
+#define _ELF_H8_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+/* Relocations 59..64 are GNU extensions.  */
+START_RELOC_NUMBERS (elf_h8_reloc_type)
+  RELOC_NUMBER (R_H8_NONE, 0)
+  RELOC_NUMBER (R_H8_DIR32, 1)
+  RELOC_NUMBER (R_H8_DIR32_28, 2)
+  RELOC_NUMBER (R_H8_DIR32_24, 3)
+  RELOC_NUMBER (R_H8_DIR32_16, 4)
+  RELOC_NUMBER (R_H8_DIR32U, 6)
+  RELOC_NUMBER (R_H8_DIR32U_28, 7)
+  RELOC_NUMBER (R_H8_DIR32U_24, 8)
+  RELOC_NUMBER (R_H8_DIR32U_20, 9)
+  RELOC_NUMBER (R_H8_DIR32U_16, 10)
+  RELOC_NUMBER (R_H8_DIR24, 11)
+  RELOC_NUMBER (R_H8_DIR24_20, 12)
+  RELOC_NUMBER (R_H8_DIR24_16, 13)
+  RELOC_NUMBER (R_H8_DIR24U, 14)
+  RELOC_NUMBER (R_H8_DIR24U_20, 15)
+  RELOC_NUMBER (R_H8_DIR24U_16, 16)
+  RELOC_NUMBER (R_H8_DIR16, 17)
+  RELOC_NUMBER (R_H8_DIR16U, 18)
+  RELOC_NUMBER (R_H8_DIR16S_32, 19)
+  RELOC_NUMBER (R_H8_DIR16S_28, 20)
+  RELOC_NUMBER (R_H8_DIR16S_24, 21)
+  RELOC_NUMBER (R_H8_DIR16S_20, 22)
+  RELOC_NUMBER (R_H8_DIR16S, 23)
+  RELOC_NUMBER (R_H8_DIR8, 24)
+  RELOC_NUMBER (R_H8_DIR8U, 25)
+  RELOC_NUMBER (R_H8_DIR8Z_32, 26)
+  RELOC_NUMBER (R_H8_DIR8Z_28, 27)
+  RELOC_NUMBER (R_H8_DIR8Z_24, 28)
+  RELOC_NUMBER (R_H8_DIR8Z_20, 29)
+  RELOC_NUMBER (R_H8_DIR8Z_16, 30)
+  RELOC_NUMBER (R_H8_PCREL16, 31)
+  RELOC_NUMBER (R_H8_PCREL8, 32)
+  RELOC_NUMBER (R_H8_BPOS, 33)
+  FAKE_RELOC (R_H8_FIRST_INVALID_DIR_RELOC, 34)
+  FAKE_RELOC (R_H8_LAST_INVALID_DIR_RELOC, 58)
+  RELOC_NUMBER (R_H8_DIR16A8, 59)
+  RELOC_NUMBER (R_H8_DIR16R8, 60)
+  RELOC_NUMBER (R_H8_DIR24A8, 61)
+  RELOC_NUMBER (R_H8_DIR24R8, 62)
+  RELOC_NUMBER (R_H8_DIR32A16, 63)
+  RELOC_NUMBER (R_H8_DISP32A16, 64)
+  RELOC_NUMBER (R_H8_ABS32, 65)
+  RELOC_NUMBER (R_H8_ABS32A16, 127)
+  RELOC_NUMBER (R_H8_SYM, 128)
+  RELOC_NUMBER (R_H8_OPneg, 129)
+  RELOC_NUMBER (R_H8_OPadd, 130)
+  RELOC_NUMBER (R_H8_OPsub, 131)
+  RELOC_NUMBER (R_H8_OPmul, 132)
+  RELOC_NUMBER (R_H8_OPdiv, 133)
+  RELOC_NUMBER (R_H8_OPshla, 134)
+  RELOC_NUMBER (R_H8_OPshra, 135)
+  RELOC_NUMBER (R_H8_OPsctsize, 136)
+  RELOC_NUMBER (R_H8_OPhword, 137)
+  RELOC_NUMBER (R_H8_OPlword, 138)
+  RELOC_NUMBER (R_H8_OPhigh, 139)
+  RELOC_NUMBER (R_H8_OPlow, 140)
+  RELOC_NUMBER (R_H8_OPscttop, 141)
+END_RELOC_NUMBERS (R_H8_max)
+
+/* Machine variant if we know it.  This field was invented at Cygnus,
+   but it is hoped that other vendors will adopt it.  If some standard
+   is developed, this code should be changed to follow it. */
+
+#define EF_H8_MACH		0x00FF0000
+
+#define E_H8_MACH_H8300		0x00800000
+#define E_H8_MACH_H8300H	0x00810000
+#define E_H8_MACH_H8300S	0x00820000
+#define E_H8_MACH_H8300HN	0x00830000
+#define E_H8_MACH_H8300SN	0x00840000
+#define E_H8_MACH_H8300SX	0x00850000
+#define E_H8_MACH_H8300SXN	0x00860000
+
+#endif
diff --git a/binutils-2.25/include/elf/hppa.h b/binutils-2.25/include/elf/hppa.h
new file mode 100644
index 00000000..8d3ea45f
--- /dev/null
+++ b/binutils-2.25/include/elf/hppa.h
@@ -0,0 +1,635 @@
+/* HPPA ELF support for BFD.
+   Copyright 1993, 1994, 1995, 1998, 1999, 2000, 2005, 2006, 2008, 2010
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file holds definitions specific to the HPPA ELF ABI.  Note
+   that most of this is not actually implemented by BFD.  */
+
+#ifndef _ELF_HPPA_H
+#define _ELF_HPPA_H
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+/* Trap null address dereferences.  */
+#define EF_PARISC_TRAPNIL	0x00010000
+
+/* .PARISC.archext section is present.  */
+#define EF_PARISC_EXT		0x00020000
+
+/* Program expects little-endian mode.  */
+#define EF_PARISC_LSB		0x00040000
+
+/* Program expects wide mode.  */
+#define EF_PARISC_WIDE		0x00080000
+
+/* Do not allow kernel-assisted branch prediction.  */
+#define EF_PARISC_NO_KABP	0x00100000
+
+/* Allow lazy swap for dynamically allocated program segments.  */
+#define EF_PARISC_LAZYSWAP	0x00400000
+
+/* Architecture version */
+#define EF_PARISC_ARCH		0x0000ffff
+
+#define EFA_PARISC_1_0			0x020b
+#define EFA_PARISC_1_1			0x0210
+#define EFA_PARISC_2_0			0x0214
+
+/* Special section indices.  */
+/* A symbol that has been declared as a tentative definition in an ANSI C
+   compilation.  */
+#define SHN_PARISC_ANSI_COMMON 	SHN_LORESERVE
+
+/* A symbol that has been declared as a common block using the
+   huge memory model.  */
+#define SHN_PARISC_HUGE_COMMON	(SHN_LORESERVE + 1)
+
+/* Processor specific section types.  */
+
+/* Section contains product specific extension bits.  */
+#define SHT_PARISC_EXT		0x70000000
+
+/* Section contains unwind table entries.  */
+#define SHT_PARISC_UNWIND	0x70000001
+
+/* Section contains debug information for optimized code.  */
+#define SHT_PARISC_DOC		0x70000002
+
+/* Section contains code annotations.  */
+#define SHT_PARISC_ANNOT	0x70000003
+
+/* DLKM special section.  */
+#define SHT_PARISC_DLKM		0x70000004
+
+/* These are strictly for compatibility with the older elf32-hppa
+   implementation.  Hopefully we can eliminate them in the future.  */
+/* Optional section holding argument location/relocation info.  */
+#define SHT_PARISC_SYMEXTN    SHT_LOPROC + 8
+
+/* Option section for linker stubs.  */
+#define SHT_PARISC_STUBS      SHT_LOPROC + 9
+
+/* Processor specific section flags.  */
+
+/* Section contains code compiled for static branch prediction.  */
+#define SHF_PARISC_SBP		0x80000000
+
+/* Section should be allocated from from GP.  */
+#define SHF_PARISC_HUGE		0x40000000
+
+/* Section should go near GP.  */
+#define SHF_PARISC_SHORT	0x20000000
+
+/* Section is weak ordered.  */
+#define SHF_PARISC_WEAKORDER	0x10000000
+
+/* Identifies the entry point of a millicode routine.  */
+#define STT_PARISC_MILLI	13
+
+/* ELF/HPPA relocation types */
+
+/* Note: PA-ELF is defined to use only RELA relocations.  */
+#include "elf/reloc-macros.h"
+
+START_RELOC_NUMBERS (elf_hppa_reloc_type)
+RELOC_NUMBER (R_PARISC_NONE,	         0) /* No reloc */
+
+/*		Data / Inst. Format	   Relocation Expression	  */
+
+RELOC_NUMBER (R_PARISC_DIR32,	   	 1)
+/*		32-bit word            	   symbol + addend    		  */
+
+RELOC_NUMBER (R_PARISC_DIR21L,	   	 2)
+/*		long immediate (7)	   LR(symbol, addend) 		  */
+
+RELOC_NUMBER (R_PARISC_DIR17R,	   	 3)
+/*		branch external (19)	   RR(symbol, addend) 		  */
+
+RELOC_NUMBER (R_PARISC_DIR17F,	   	 4)
+/*		branch external (19)	   symbol + addend    		  */
+
+RELOC_NUMBER (R_PARISC_DIR14R,	   	 6)
+/*		load/store (1)		   RR(symbol, addend) 		  */
+
+RELOC_NUMBER (R_PARISC_DIR14F,	   	 7)
+/*		load/store (1)		   symbol, addend 		  */
+
+/* PC-relative relocation types
+   Typically used for calls.
+   Note PCREL17C and PCREL17F differ only in overflow handling.
+   PCREL17C never reports a relocation error.
+
+   When supporting argument relocations, function calls must be
+   accompanied by parameter relocation information.  This information is
+   carried in the ten high-order bits of the addend field.  The remaining
+   22 bits of of the addend field are sign-extended to form the Addend.
+
+   Note the code to build argument relocations depends on the
+   addend being zero.  A consequence of this limitation is GAS
+   can not perform relocation reductions for function symbols.  */
+
+RELOC_NUMBER (R_PARISC_PCREL12F,  	 8)
+/*		op & branch (17)	   symbol - PC - 8 + addend    	  */
+
+RELOC_NUMBER (R_PARISC_PCREL32,   	 9)
+/*		32-bit word		   symbol - PC - 8 + addend    	  */
+
+RELOC_NUMBER (R_PARISC_PCREL21L,  	10)
+/*		long immediate (7)	   L(symbol - PC - 8 + addend) 	  */
+
+RELOC_NUMBER (R_PARISC_PCREL17R,  	11)
+/*		branch external (19)	   R(symbol - PC - 8 + addend) 	  */
+
+RELOC_NUMBER (R_PARISC_PCREL17F,  	12)
+/*		branch (20)		   symbol - PC - 8 + addend    	  */
+
+RELOC_NUMBER (R_PARISC_PCREL17C,  	13)
+/*		branch (20)		   symbol - PC - 8 + addend    	  */
+
+RELOC_NUMBER (R_PARISC_PCREL14R,  	14)
+/*		load/store (1)		   R(symbol - PC - 8 + addend) 	  */
+
+RELOC_NUMBER (R_PARISC_PCREL14F,  	15)
+/*		load/store (1)             symbol - PC - 8 + addend    	  */
+
+
+/* DP-relative relocation types.  */
+RELOC_NUMBER (R_PARISC_DPREL21L,  	18)
+/*		long immediate (7)         LR(symbol - GP, addend)  	  */
+
+RELOC_NUMBER (R_PARISC_DPREL14WR, 	19)
+/*		load/store mod. comp. (2)  RR(symbol - GP, addend)  	  */
+
+RELOC_NUMBER (R_PARISC_DPREL14DR, 	20)
+/*		load/store doubleword (3)  RR(symbol - GP, addend)  	  */
+
+RELOC_NUMBER (R_PARISC_DPREL14R,  	22)
+/*		load/store (1)             RR(symbol - GP, addend)  	  */
+
+RELOC_NUMBER (R_PARISC_DPREL14F,  	23)
+/*		load/store (1)             symbol - GP + addend     	  */
+
+
+/* Data linkage table (DLT) relocation types
+
+   SOM DLT_REL fixup requests are used to for static data references
+   from position-independent code within shared libraries.  They are
+   similar to the GOT relocation types in some SVR4 implementations.  */
+
+RELOC_NUMBER (R_PARISC_DLTREL21L,     	26)
+/*		long immediate (7)         LR(symbol - GP, addend) 	  */
+
+RELOC_NUMBER (R_PARISC_DLTREL14R,     	30)
+/*		load/store (1)             RR(symbol - GP, addend) 	  */
+
+RELOC_NUMBER (R_PARISC_DLTREL14F,     	31)
+/*		load/store (1)             symbol - GP + addend    	  */
+
+
+/* DLT indirect relocation types  */
+RELOC_NUMBER (R_PARISC_DLTIND21L,     	34)
+/*		long immediate (7)         L(ltoff(symbol + addend)) 	  */
+
+RELOC_NUMBER (R_PARISC_DLTIND14R,     	38)
+/*		load/store (1)             R(ltoff(symbol + addend)) 	  */
+
+RELOC_NUMBER (R_PARISC_DLTIND14F,     	39)
+/*		load/store (1)             ltoff(symbol + addend)    	  */
+
+
+/* Base relative relocation types.  Ugh.  These imply lots of state */
+RELOC_NUMBER (R_PARISC_SETBASE,       	40)
+/*		none                       no reloc; base := sym     	  */
+
+RELOC_NUMBER (R_PARISC_SECREL32,      	41)
+/*		32-bit word                symbol - SECT + addend    	  */
+
+RELOC_NUMBER (R_PARISC_BASEREL21L,    	42)
+/*		long immediate (7)         LR(symbol - base, addend) 	  */
+
+RELOC_NUMBER (R_PARISC_BASEREL17R,    	43)
+/*		branch external (19)       RR(symbol - base, addend) 	  */
+
+RELOC_NUMBER (R_PARISC_BASEREL17F,    	44)
+/*		branch external (19)       symbol - base + addend    	  */
+
+RELOC_NUMBER (R_PARISC_BASEREL14R,    	46)
+/*		load/store (1)             RR(symbol - base, addend) 	  */
+
+RELOC_NUMBER (R_PARISC_BASEREL14F,    	47)
+/*		load/store (1)             symbol - base, addend     	  */
+
+
+/* Segment relative relocation types.  */
+RELOC_NUMBER (R_PARISC_SEGBASE,       	48)
+/*		none                       no relocation; SB := sym  	  */
+
+RELOC_NUMBER (R_PARISC_SEGREL32,      	49)
+/*		32-bit word                symbol - SB + addend 	  */
+  
+
+/* Offsets from the PLT.  */  
+RELOC_NUMBER (R_PARISC_PLTOFF21L,     	50)
+/*		long immediate (7)         LR(pltoff(symbol), addend) 	  */
+
+RELOC_NUMBER (R_PARISC_PLTOFF14R,     	54)
+/*		load/store (1)             RR(pltoff(symbol), addend) 	  */
+
+RELOC_NUMBER (R_PARISC_PLTOFF14F,     	55)
+/*		load/store (1)             pltoff(symbol) + addend    	  */
+
+
+RELOC_NUMBER (R_PARISC_LTOFF_FPTR32,  	57)
+/*		32-bit word                ltoff(fptr(symbol+addend))     */
+
+RELOC_NUMBER (R_PARISC_LTOFF_FPTR21L, 	58)
+/*		long immediate (7)         L(ltoff(fptr(symbol+addend)))  */
+
+RELOC_NUMBER (R_PARISC_LTOFF_FPTR14R, 	62)
+/*		load/store (1)             R(ltoff(fptr(symbol+addend)))  */
+
+
+RELOC_NUMBER (R_PARISC_FPTR64,        	64)
+/*		64-bit doubleword          fptr(symbol+addend) 		  */
+
+
+/* Plabel relocation types.  */	 
+RELOC_NUMBER (R_PARISC_PLABEL32,      	65)
+/*		32-bit word	  	   fptr(symbol) 		  */
+
+RELOC_NUMBER (R_PARISC_PLABEL21L,     	66)
+/*		long immediate (7)         L(fptr(symbol))		  */
+
+RELOC_NUMBER (R_PARISC_PLABEL14R,     	70)
+/*		load/store (1)             R(fptr(symbol))		  */
+
+  
+/* PCREL relocations.  */  
+RELOC_NUMBER (R_PARISC_PCREL64,       	72)
+/*		64-bit doubleword          symbol - PC - 8 + addend       */
+
+RELOC_NUMBER (R_PARISC_PCREL22C,      	73)
+/*		branch & link (21)         symbol - PC - 8 + addend       */
+
+RELOC_NUMBER (R_PARISC_PCREL22F,      	74)
+/*		branch & link (21)         symbol - PC - 8 + addend       */
+
+RELOC_NUMBER (R_PARISC_PCREL14WR,     	75)
+/*		load/store mod. comp. (2)  R(symbol - PC - 8 + addend)    */
+
+RELOC_NUMBER (R_PARISC_PCREL14DR,     	76)
+/*		load/store doubleword (3)  R(symbol - PC - 8 + addend)    */
+
+RELOC_NUMBER (R_PARISC_PCREL16F,      	77)
+/*		load/store (1)             symbol - PC - 8 + addend       */
+
+RELOC_NUMBER (R_PARISC_PCREL16WF,     	78)
+/*		load/store mod. comp. (2)  symbol - PC - 8 + addend       */
+
+RELOC_NUMBER (R_PARISC_PCREL16DF,     	79)
+/*		load/store doubleword (3)  symbol - PC - 8 + addend       */
+
+
+RELOC_NUMBER (R_PARISC_DIR64,         	80)
+/*		64-bit doubleword          symbol + addend    		  */
+
+RELOC_NUMBER (R_PARISC_DIR14WR,       	83)
+/*		load/store mod. comp. (2)  RR(symbol, addend) 		  */
+
+RELOC_NUMBER (R_PARISC_DIR14DR,       	84)
+/*		load/store doubleword (3)  RR(symbol, addend) 		  */
+
+RELOC_NUMBER (R_PARISC_DIR16F,        	85)
+/*		load/store (1)             symbol + addend    		  */
+
+RELOC_NUMBER (R_PARISC_DIR16WF,       	86)
+/*		load/store mod. comp. (2)  symbol + addend    		  */
+
+RELOC_NUMBER (R_PARISC_DIR16DF,       	87)
+/*		load/store doubleword (3)  symbol + addend    		  */
+  
+RELOC_NUMBER (R_PARISC_GPREL64,       	88)
+/*		64-bit doubleword          symbol - GP + addend 	  */
+  
+RELOC_NUMBER (R_PARISC_DLTREL14WR,    	91)
+/*		load/store mod. comp. (2)  RR(symbol - GP, addend) 	  */
+
+RELOC_NUMBER (R_PARISC_DLTREL14DR,    	92)
+/*		load/store doubleword (3)  RR(symbol - GP, addend) 	  */
+
+RELOC_NUMBER (R_PARISC_GPREL16F,      	93)
+/*		load/store (1)             symbol - GP + addend    	  */
+
+RELOC_NUMBER (R_PARISC_GPREL16WF,     	94)
+/*		load/store mod. comp. (2)  symbol - GP + addend    	  */
+
+RELOC_NUMBER (R_PARISC_GPREL16DF,     	95)
+/*		load/store doubleword (3)  symbol - GP + addend    	  */
+
+
+RELOC_NUMBER (R_PARISC_LTOFF64,      	96)
+/*		64-bit doubleword          ltoff(symbol + addend)    	  */
+
+RELOC_NUMBER (R_PARISC_DLTIND14WR,   	99)
+/*		load/store mod. comp. (2)  R(ltoff(symbol + addend)) 	  */
+
+RELOC_NUMBER (R_PARISC_DLTIND14DR,     100)
+/*		load/store doubleword (3)  R(ltoff(symbol + addend)) 	  */
+
+RELOC_NUMBER (R_PARISC_LTOFF16F,       101)
+/*		load/store (1)             ltoff(symbol + addend)    	  */
+
+RELOC_NUMBER (R_PARISC_LTOFF16WF,      102)
+/*		load/store mod. comp. (2)  ltoff(symbol + addend)    	  */
+
+RELOC_NUMBER (R_PARISC_LTOFF16DF,      103)
+/*		load/store doubleword (3)  ltoff(symbol + addend)    	  */
+
+
+RELOC_NUMBER (R_PARISC_SECREL64,       104)
+/*		64-bit doubleword          symbol - SECT + addend 	  */
+
+RELOC_NUMBER (R_PARISC_BASEREL14WR,    107)
+/*		load/store mod. comp. (2)  RR(symbol - base, addend) 	  */
+
+RELOC_NUMBER (R_PARISC_BASEREL14DR,    108)
+/*		load/store doubleword (3)  RR(symbol - base, addend) 	  */
+
+
+RELOC_NUMBER (R_PARISC_SEGREL64,       112)
+/*		64-bit doubleword          symbol - SB + addend 	  */
+  
+RELOC_NUMBER (R_PARISC_PLTOFF14WR,     115)
+/*		load/store mod. comp. (2)  RR(pltoff(symbol), addend) 	  */
+
+RELOC_NUMBER (R_PARISC_PLTOFF14DR,     116)    
+/*		load/store doubleword (3)  RR(pltoff(symbol), addend) 	  */
+
+RELOC_NUMBER (R_PARISC_PLTOFF16F,      117)    
+/*		load/store (1)             pltoff(symbol) + addend    	  */
+
+RELOC_NUMBER (R_PARISC_PLTOFF16WF,     118)    
+/*		load/store mod. comp. (2)  pltoff(symbol) + addend    	  */
+
+RELOC_NUMBER (R_PARISC_PLTOFF16DF,     119)    
+/*		load/store doubleword (3)  pltoff(symbol) + addend    	  */
+
+
+RELOC_NUMBER (R_PARISC_LTOFF_FPTR64,   120)
+/*		64-bit doubleword          ltoff(fptr(symbol+addend))     */
+
+RELOC_NUMBER (R_PARISC_LTOFF_FPTR14WR, 123)
+/*		load/store mod. comp. (2)  R(ltoff(fptr(symbol+addend)))  */
+
+RELOC_NUMBER (R_PARISC_LTOFF_FPTR14DR, 124)
+/*		load/store doubleword (3)  R(ltoff(fptr(symbol+addend)))  */
+
+RELOC_NUMBER (R_PARISC_LTOFF_FPTR16F,  125)
+/*		load/store (1)             ltoff(fptr(symbol+addend))     */
+
+RELOC_NUMBER (R_PARISC_LTOFF_FPTR16WF, 126)
+/*		load/store mod. comp. (2)  ltoff(fptr(symbol+addend))     */
+
+RELOC_NUMBER (R_PARISC_LTOFF_FPTR16DF, 127)
+/*		load/store doubleword (3)  ltoff(fptr(symbol+addend))     */
+
+
+RELOC_NUMBER (R_PARISC_COPY, 	       128)
+/*		data                       Dynamic relocations only 	  */
+
+RELOC_NUMBER (R_PARISC_IPLT, 	       129)
+/*		plt                                                 	  */
+
+RELOC_NUMBER (R_PARISC_EPLT, 	       130)
+/*		plt                                                 	  */
+
+
+RELOC_NUMBER (R_PARISC_TPREL32,        153)
+/*		32-bit word                symbol - TP + addend    	  */
+
+RELOC_NUMBER (R_PARISC_TPREL21L,       154)
+/*		long immediate (7)         LR(symbol - TP, addend) 	  */
+
+RELOC_NUMBER (R_PARISC_TPREL14R,       158)
+/*		load/store (1)             RR(symbol - TP, addend) 	  */
+
+
+RELOC_NUMBER (R_PARISC_LTOFF_TP21L,    162)
+/*		long immediate (7)         L(ltoff(symbol - TP + addend)) */
+
+RELOC_NUMBER (R_PARISC_LTOFF_TP14R,    166)
+/*		load/store (1)             R(ltoff(symbol - TP + addend)) */
+
+RELOC_NUMBER (R_PARISC_LTOFF_TP14F,    167)
+/*		load/store (1)             ltoff(symbol - TP + addend)    */
+
+
+RELOC_NUMBER (R_PARISC_TPREL64,        216)
+/*		64-bit word                symbol - TP + addend        	  */
+
+RELOC_NUMBER (R_PARISC_TPREL14WR,      219)    	  
+/*		load/store mod. comp. (2)  RR(symbol - TP, addend)     	  */
+
+RELOC_NUMBER (R_PARISC_TPREL14DR,      220)    	  
+/*		load/store doubleword (3)  RR(symbol - TP, addend)     	  */
+
+RELOC_NUMBER (R_PARISC_TPREL16F,       221)    	  
+/*		load/store (1)             symbol - TP + addend        	  */
+
+RELOC_NUMBER (R_PARISC_TPREL16WF,      222)    	  
+/*		load/store mod. comp. (2)  symbol - TP + addend        	  */
+
+RELOC_NUMBER (R_PARISC_TPREL16DF,      223)    	  
+/*		load/store doubleword (3)  symbol - TP + addend        	  */
+
+
+RELOC_NUMBER (R_PARISC_LTOFF_TP64,     224)
+/*		64-bit doubleword          ltoff(symbol - TP + addend)    */
+
+RELOC_NUMBER (R_PARISC_LTOFF_TP14WR,   227)
+/*		load/store mod. comp. (2)  R(ltoff(symbol - TP + addend)) */
+
+RELOC_NUMBER (R_PARISC_LTOFF_TP14DR,   228)
+/*		load/store doubleword (3)  R(ltoff(symbol - TP + addend)) */
+
+RELOC_NUMBER (R_PARISC_LTOFF_TP16F,    229)
+/*		load/store (1)             ltoff(symbol - TP + addend)    */
+
+RELOC_NUMBER (R_PARISC_LTOFF_TP16WF,   230)
+/*		load/store mod. comp. (2)  ltoff(symbol - TP + addend)    */
+
+RELOC_NUMBER (R_PARISC_LTOFF_TP16DF,   231)
+/*		load/store doubleword (3)  ltoff(symbol - TP + addend)    */
+
+RELOC_NUMBER (R_PARISC_GNU_VTENTRY,    232)
+RELOC_NUMBER (R_PARISC_GNU_VTINHERIT,  233)
+
+RELOC_NUMBER (R_PARISC_TLS_GD21L,      234)
+RELOC_NUMBER (R_PARISC_TLS_GD14R,      235)
+RELOC_NUMBER (R_PARISC_TLS_GDCALL,     236)
+RELOC_NUMBER (R_PARISC_TLS_LDM21L,     237)
+RELOC_NUMBER (R_PARISC_TLS_LDM14R,     238)
+RELOC_NUMBER (R_PARISC_TLS_LDMCALL,    239)
+RELOC_NUMBER (R_PARISC_TLS_LDO21L,     240)
+RELOC_NUMBER (R_PARISC_TLS_LDO14R,     241)
+RELOC_NUMBER (R_PARISC_TLS_DTPMOD32,   242)
+RELOC_NUMBER (R_PARISC_TLS_DTPMOD64,   243)
+RELOC_NUMBER (R_PARISC_TLS_DTPOFF32,   244)
+RELOC_NUMBER (R_PARISC_TLS_DTPOFF64,   245)
+
+END_RELOC_NUMBERS (R_PARISC_UNIMPLEMENTED)
+
+#define R_PARISC_TLS_LE21L     R_PARISC_TPREL21L
+#define R_PARISC_TLS_LE14R     R_PARISC_TPREL14R
+#define R_PARISC_TLS_IE21L     R_PARISC_LTOFF_TP21L
+#define R_PARISC_TLS_IE14R     R_PARISC_LTOFF_TP14R
+#define R_PARISC_TLS_TPREL32   R_PARISC_TPREL32
+#define R_PARISC_TLS_TPREL64   R_PARISC_TPREL64
+
+#ifndef RELOC_MACROS_GEN_FUNC
+typedef enum elf_hppa_reloc_type elf_hppa_reloc_type;
+#endif
+
+#define PT_PARISC_ARCHEXT	0x70000000
+#define PT_PARISC_UNWIND	0x70000001
+#define PT_PARISC_WEAKORDER	0x70000002
+
+/* Flag bits in sh_flags of ElfXX_Shdr.  */
+#define SHF_HP_TLS              0x01000000
+#define SHF_HP_NEAR_SHARED      0x02000000
+#define SHF_HP_FAR_SHARED       0x04000000
+#define SHF_HP_COMDAT           0x08000000
+#define SHF_HP_CONST            0x00800000
+
+/* Reserved section header indices.  */
+#define SHN_TLS_COMMON          (SHN_LOOS + 0x0)
+#define SHN_NS_COMMON           (SHN_LOOS + 0x1)
+#define SHN_FS_COMMON           (SHN_LOOS + 0x2)
+#define SHN_NS_UNDEF            (SHN_LOOS + 0x3)
+#define SHN_FS_UNDEF            (SHN_LOOS + 0x4)
+#define SHN_HP_EXTERN           (SHN_LOOS + 0x5)
+#define SHN_HP_EXTHINT          (SHN_LOOS + 0x6)
+#define SHN_HP_UNDEF_BIND_IMM   (SHN_LOOS + 0x7)
+
+/* Values of sh_type in ElfXX_Shdr.  */
+#define SHT_HP_OVLBITS  (SHT_LOOS + 0x0)
+#define SHT_HP_DLKM     (SHT_LOOS + 0x1)
+#define SHT_HP_COMDAT   (SHT_LOOS + 0x2)
+#define SHT_HP_OBJDICT  (SHT_LOOS + 0x3)
+#define SHT_HP_ANNOT    (SHT_LOOS + 0x4)
+
+/* Flag bits in p_flags of ElfXX_Phdr.  */
+#define PF_HP_CODE		0x00040000
+#define PF_HP_MODIFY		0x00080000
+#define PF_HP_PAGE_SIZE		0x00100000
+#define PF_HP_FAR_SHARED	0x00200000
+#define PF_HP_NEAR_SHARED	0x00400000
+#define PF_HP_LAZYSWAP		0x00800000
+#define PF_HP_CODE_DEPR		0x01000000
+#define PF_HP_MODIFY_DEPR	0x02000000
+#define PF_HP_LAZYSWAP_DEPR	0x04000000
+#define PF_PARISC_SBP		0x08000000
+#define PF_HP_SBP		0x08000000
+
+
+/* Processor specific dynamic array tags.  */
+
+/* Arggh.  HP's tools define these symbols based on the
+   old value of DT_LOOS.  So we must do the same to be
+   compatible.  */
+#define DT_HP_LOAD_MAP		(OLD_DT_LOOS + 0x0)
+#define DT_HP_DLD_FLAGS		(OLD_DT_LOOS + 0x1)
+#define DT_HP_DLD_HOOK		(OLD_DT_LOOS + 0x2)
+#define DT_HP_UX10_INIT		(OLD_DT_LOOS + 0x3)
+#define DT_HP_UX10_INITSZ	(OLD_DT_LOOS + 0x4)
+#define DT_HP_PREINIT		(OLD_DT_LOOS + 0x5)
+#define DT_HP_PREINITSZ		(OLD_DT_LOOS + 0x6)
+#define DT_HP_NEEDED		(OLD_DT_LOOS + 0x7)
+#define DT_HP_TIME_STAMP	(OLD_DT_LOOS + 0x8)
+#define DT_HP_CHECKSUM		(OLD_DT_LOOS + 0x9)
+#define DT_HP_GST_SIZE		(OLD_DT_LOOS + 0xa)
+#define DT_HP_GST_VERSION	(OLD_DT_LOOS + 0xb)
+#define DT_HP_GST_HASHVAL	(OLD_DT_LOOS + 0xc)
+#define DT_HP_EPLTREL		(OLD_DT_LOOS + 0xd)
+#define DT_HP_EPLTRELSZ		(OLD_DT_LOOS + 0xe)
+#define DT_HP_FILTERED		(OLD_DT_LOOS + 0xf)
+#define DT_HP_FILTER_TLS	(OLD_DT_LOOS + 0x10)
+#define DT_HP_COMPAT_FILTERED	(OLD_DT_LOOS + 0x11)
+#define DT_HP_LAZYLOAD		(OLD_DT_LOOS + 0x12)
+#define DT_HP_BIND_NOW_COUNT	(OLD_DT_LOOS + 0x13)
+#define DT_PLT			(OLD_DT_LOOS + 0x14)
+#define DT_PLT_SIZE		(OLD_DT_LOOS + 0x15)
+#define DT_DLT			(OLD_DT_LOOS + 0x16)
+#define DT_DLT_SIZE		(OLD_DT_LOOS + 0x17)
+
+/* Values for DT_HP_DLD_FLAGS.  */
+#define DT_HP_DEBUG_PRIVATE		0x00001 /* Map text private */
+#define DT_HP_DEBUG_CALLBACK		0x00002 /* Callback */
+#define DT_HP_DEBUG_CALLBACK_BOR	0x00004 /* BOR callback */
+#define DT_HP_NO_ENVVAR			0x00008 /* No env var */
+#define DT_HP_BIND_NOW			0x00010 /* Bind now */
+#define DT_HP_BIND_NONFATAL		0x00020 /* Bind non-fatal */
+#define DT_HP_BIND_VERBOSE		0x00040 /* Bind verbose */
+#define DT_HP_BIND_RESTRICTED		0x00080 /* Bind restricted */
+#define DT_HP_BIND_SYMBOLIC		0x00100 /* Bind symbolic */
+#define DT_HP_RPATH_FIRST		0x00200 /* RPATH first */
+#define DT_HP_BIND_DEPTH_FIRST		0x00400 /* Bind depth-first */
+#define DT_HP_GST			0x00800 /* Dld global sym table */
+#define DT_HP_SHLIB_FIXED		0x01000 /* shared vtable support */
+#define DT_HP_MERGE_SHLIB_SEG		0x02000 /* merge shlib data segs */
+#define DT_HP_NODELETE			0x04000 /* never unload */
+#define DT_HP_GROUP			0x08000 /* bind only within group */
+#define DT_HP_PROTECT_LINKAGE_TABLE	0x10000 /* protected linkage table */
+
+/* Program header extensions.  */
+#define PT_HP_TLS		(PT_LOOS + 0x0)
+#define PT_HP_CORE_NONE		(PT_LOOS + 0x1)
+#define PT_HP_CORE_VERSION	(PT_LOOS + 0x2)
+#define PT_HP_CORE_KERNEL	(PT_LOOS + 0x3)
+#define PT_HP_CORE_COMM		(PT_LOOS + 0x4)
+#define PT_HP_CORE_PROC		(PT_LOOS + 0x5)
+#define PT_HP_CORE_LOADABLE	(PT_LOOS + 0x6)
+#define PT_HP_CORE_STACK	(PT_LOOS + 0x7)
+#define PT_HP_CORE_SHM		(PT_LOOS + 0x8)
+#define PT_HP_CORE_MMF		(PT_LOOS + 0x9)
+#define PT_HP_PARALLEL		(PT_LOOS + 0x10)
+#define PT_HP_FASTBIND		(PT_LOOS + 0x11)
+#define PT_HP_OPT_ANNOT		(PT_LOOS + 0x12)
+#define PT_HP_HSL_ANNOT		(PT_LOOS + 0x13)
+#define PT_HP_STACK		(PT_LOOS + 0x14)
+#define PT_HP_CORE_UTSNAME	(PT_LOOS + 0x15)
+
+/* Binding information.  */
+#define STB_HP_ALIAS		(STB_LOOS + 0x0)
+
+/* Additional symbol types.  */
+#define STT_HP_OPAQUE		(STT_LOOS + 0x1)
+#define STT_HP_STUB		(STT_LOOS + 0x2)
+
+/* Note types.  */
+#define NT_HP_COMPILER		1
+#define NT_HP_COPYRIGHT		2
+#define NT_HP_VERSION		3
+#define NT_HP_SRCFILE_INFO	4
+#define NT_HP_LINKER		5
+#define NT_HP_INSTRUMENTED	6
+#define NT_HP_UX_OPTIONS	7
+
+#endif /* _ELF_HPPA_H */
diff --git a/binutils-2.25/include/elf/i370.h b/binutils-2.25/include/elf/i370.h
new file mode 100644
index 00000000..7b451ff9
--- /dev/null
+++ b/binutils-2.25/include/elf/i370.h
@@ -0,0 +1,61 @@
+/* i370 ELF support for BFD.
+   Copyright 2000, 2002, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file holds definitions specific to the i370 ELF ABI.  Note
+   that most of this is not actually implemented by BFD.  */
+
+#ifndef _ELF_I370_H
+#define _ELF_I370_H
+
+#include "elf/reloc-macros.h"
+
+/* Processor specific section headers, sh_type field */
+
+#define SHT_ORDERED		SHT_HIPROC	/* Link editor is to sort the \
+						   entries in this section \
+						   based on the address \
+						   specified in the associated \
+						   symbol table entry.  */
+
+#define	EF_I370_RELOCATABLE	0x00010000	/* i370 -mrelocatable flag */
+#define	EF_I370_RELOCATABLE_LIB	0x00008000	/* i370 -mrelocatable-lib flag */
+
+/* i370 relocations
+   Note that there is really just one relocation that we currently
+   support (and only one that we seem to need, at the moment), and
+   that is the 31-bit address relocation.  Note that the 370/390
+   only supports a 31-bit (2GB) address space.  */
+
+START_RELOC_NUMBERS (i370_reloc_type)
+  RELOC_NUMBER (R_I370_NONE,      0)
+  RELOC_NUMBER (R_I370_ADDR31,    1)
+  RELOC_NUMBER (R_I370_ADDR32,    2)
+  RELOC_NUMBER (R_I370_ADDR16,    3) 
+  RELOC_NUMBER (R_I370_REL31,     4)
+  RELOC_NUMBER (R_I370_REL32,     5)  
+  RELOC_NUMBER (R_I370_ADDR12,    6)
+  RELOC_NUMBER (R_I370_REL12,     7)
+  RELOC_NUMBER (R_I370_ADDR8,     8)
+  RELOC_NUMBER (R_I370_REL8,      9)
+  RELOC_NUMBER (R_I370_COPY,     10)
+  RELOC_NUMBER (R_I370_RELATIVE, 11)
+END_RELOC_NUMBERS (R_I370_max)
+
+#endif /* _ELF_I370_H */
diff --git a/binutils-2.25/include/elf/i386.h b/binutils-2.25/include/elf/i386.h
new file mode 100644
index 00000000..c4750925
--- /dev/null
+++ b/binutils-2.25/include/elf/i386.h
@@ -0,0 +1,79 @@
+/* ix86 ELF support for BFD.
+   Copyright 1998, 1999, 2000, 2002, 2004, 2005, 2006, 2009, 2010
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_I386_H
+#define _ELF_I386_H
+
+#include "elf/reloc-macros.h"
+
+START_RELOC_NUMBERS (elf_i386_reloc_type)
+     RELOC_NUMBER (R_386_NONE,      0)	/* No reloc */
+     RELOC_NUMBER (R_386_32,        1)	/* Direct 32 bit  */
+     RELOC_NUMBER (R_386_PC32,      2)	/* PC relative 32 bit */
+     RELOC_NUMBER (R_386_GOT32,     3)	/* 32 bit GOT entry */
+     RELOC_NUMBER (R_386_PLT32,	    4)	/* 32 bit PLT address */
+     RELOC_NUMBER (R_386_COPY,	    5)	/* Copy symbol at runtime */
+     RELOC_NUMBER (R_386_GLOB_DAT,  6)	/* Create GOT entry */
+     RELOC_NUMBER (R_386_JUMP_SLOT, 7)	/* Create PLT entry */
+     RELOC_NUMBER (R_386_RELATIVE,  8)	/* Adjust by program base */
+     RELOC_NUMBER (R_386_GOTOFF,    9)	/* 32 bit offset to GOT */
+     RELOC_NUMBER (R_386_GOTPC,    10)	/* 32 bit PC relative offset to GOT */
+     RELOC_NUMBER (R_386_32PLT,    11)	/* Used by Sun */
+     FAKE_RELOC   (FIRST_INVALID_RELOC, 12)
+     FAKE_RELOC   (LAST_INVALID_RELOC,  13)
+     RELOC_NUMBER (R_386_TLS_TPOFF,14)
+     RELOC_NUMBER (R_386_TLS_IE,   15)
+     RELOC_NUMBER (R_386_TLS_GOTIE,16)
+     RELOC_NUMBER (R_386_TLS_LE,   17)
+     RELOC_NUMBER (R_386_TLS_GD,   18)
+     RELOC_NUMBER (R_386_TLS_LDM,  19)
+     RELOC_NUMBER (R_386_16,       20)
+     RELOC_NUMBER (R_386_PC16,     21)
+     RELOC_NUMBER (R_386_8,	   22)
+     RELOC_NUMBER (R_386_PC8,      23)
+     RELOC_NUMBER (R_386_TLS_GD_32,    24)
+     RELOC_NUMBER (R_386_TLS_GD_PUSH,  25)
+     RELOC_NUMBER (R_386_TLS_GD_CALL,  26)
+     RELOC_NUMBER (R_386_TLS_GD_POP,   27)
+     RELOC_NUMBER (R_386_TLS_LDM_32,   28)
+     RELOC_NUMBER (R_386_TLS_LDM_PUSH, 29)
+     RELOC_NUMBER (R_386_TLS_LDM_CALL, 30)
+     RELOC_NUMBER (R_386_TLS_LDM_POP,  31)
+     RELOC_NUMBER (R_386_TLS_LDO_32,   32)
+     RELOC_NUMBER (R_386_TLS_IE_32,    33)
+     RELOC_NUMBER (R_386_TLS_LE_32,    34)
+     RELOC_NUMBER (R_386_TLS_DTPMOD32, 35)
+     RELOC_NUMBER (R_386_TLS_DTPOFF32, 36)
+     RELOC_NUMBER (R_386_TLS_TPOFF32,  37)
+     RELOC_NUMBER (R_386_SIZE32,       38) /* 32-bit symbol size */
+     RELOC_NUMBER (R_386_TLS_GOTDESC,  39)
+     RELOC_NUMBER (R_386_TLS_DESC_CALL,40)
+     RELOC_NUMBER (R_386_TLS_DESC,     41)
+     RELOC_NUMBER (R_386_IRELATIVE,    42) /* Adjust indirectly by program base */
+
+     /* Used by Intel.  */
+     RELOC_NUMBER (R_386_USED_BY_INTEL_200, 200)
+
+     /* These are GNU extensions to enable C++ vtable garbage collection.  */
+     RELOC_NUMBER (R_386_GNU_VTINHERIT, 250)
+     RELOC_NUMBER (R_386_GNU_VTENTRY, 251)
+END_RELOC_NUMBERS (R_386_max)
+
+#endif
diff --git a/binutils-2.25/include/elf/i860.h b/binutils-2.25/include/elf/i860.h
new file mode 100644
index 00000000..834c7766
--- /dev/null
+++ b/binutils-2.25/include/elf/i860.h
@@ -0,0 +1,66 @@
+/* i860 ELF support for BFD.
+   Copyright 2000, 2010 Free Software Foundation, Inc.
+
+   Contributed by Jason Eckhardt <jle@cygnus.com>.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_I860_H
+#define _ELF_I860_H
+
+/* Note: i860 ELF is defined to use only RELA relocations.  */
+
+#include "elf/reloc-macros.h"
+
+START_RELOC_NUMBERS (elf_i860_reloc_type)
+     RELOC_NUMBER (R_860_NONE,      0x00)	/* No reloc */
+     RELOC_NUMBER (R_860_32,        0x01)	/* S+A  */
+     RELOC_NUMBER (R_860_COPY,	    0x02)	/* No calculation */
+     RELOC_NUMBER (R_860_GLOB_DAT,  0x03)	/* S, Create GOT entry */
+     RELOC_NUMBER (R_860_JUMP_SLOT, 0x04)	/* S+A, Create PLT entry */
+     RELOC_NUMBER (R_860_RELATIVE,  0x05)	/* B+A, Adj by program base */
+     RELOC_NUMBER (R_860_PC26,      0x30)	/* (S+A-P) >> 2 */ 
+     RELOC_NUMBER (R_860_PLT26,	    0x31)	/* (L+A-P) >> 2 */
+     RELOC_NUMBER (R_860_PC16,      0x32)	/* (S+A-P) >> 2 */
+     RELOC_NUMBER (R_860_LOW0,      0x40)	/* S+A */
+     RELOC_NUMBER (R_860_SPLIT0,    0x42)	/* S+A */       
+     RELOC_NUMBER (R_860_LOW1,      0x44)	/* S+A */
+     RELOC_NUMBER (R_860_SPLIT1,    0x46)	/* S+A */
+     RELOC_NUMBER (R_860_LOW2,      0x48)	/* S+A */
+     RELOC_NUMBER (R_860_SPLIT2,    0x4A)	/* S+A */
+     RELOC_NUMBER (R_860_LOW3,      0x4C)	/* S+A */
+     RELOC_NUMBER (R_860_LOGOT0,    0x50)	/* G */
+     RELOC_NUMBER (R_860_SPGOT0,    0x52)	/* G */
+     RELOC_NUMBER (R_860_LOGOT1,    0x54)	/* G */
+     RELOC_NUMBER (R_860_SPGOT1,    0x56)	/* G */
+     RELOC_NUMBER (R_860_LOGOTOFF0, 0x60)	/* O */
+     RELOC_NUMBER (R_860_SPGOTOFF0, 0x62)	/* O */
+     RELOC_NUMBER (R_860_LOGOTOFF1, 0x64)	/* O */
+     RELOC_NUMBER (R_860_SPGOTOFF1, 0x66)	/* O */
+     RELOC_NUMBER (R_860_LOGOTOFF2, 0x68)	/* O */
+     RELOC_NUMBER (R_860_LOGOTOFF3, 0x6C)	/* O */
+     RELOC_NUMBER (R_860_LOPC,      0x70)	/* (S+A-P) >> 2 */
+     RELOC_NUMBER (R_860_HIGHADJ,   0x80)	/* hiadj(S+A) */
+     RELOC_NUMBER (R_860_HAGOT,     0x90)	/* hiadj(G) */
+     RELOC_NUMBER (R_860_HAGOTOFF,  0xA0)	/* hiadj(O) */
+     RELOC_NUMBER (R_860_HAPC,      0xB0)	/* hiadj((S+A-P) >> 2) */
+     RELOC_NUMBER (R_860_HIGH,      0xC0)	/* (S+A) >> 16 */
+     RELOC_NUMBER (R_860_HIGOT,     0xD0)	/* G >> 16 */
+     RELOC_NUMBER (R_860_HIGOTOFF,  0xE0)	/* O */
+END_RELOC_NUMBERS (R_860_max)
+
+#endif
diff --git a/binutils-2.25/include/elf/i960.h b/binutils-2.25/include/elf/i960.h
new file mode 100644
index 00000000..c319b322
--- /dev/null
+++ b/binutils-2.25/include/elf/i960.h
@@ -0,0 +1,37 @@
+/* Intel 960 ELF support for BFD.
+   Copyright 1999, 2000, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_I960_H
+#define _ELF_I960_H
+
+#include "elf/reloc-macros.h"
+
+
+START_RELOC_NUMBERS (elf_i960_reloc_type)
+     RELOC_NUMBER (R_960_NONE,	    0)
+     RELOC_NUMBER (R_960_12,	    1)
+     RELOC_NUMBER (R_960_32,	    2)
+     RELOC_NUMBER (R_960_IP24,	    3)
+     RELOC_NUMBER (R_960_SUB,	    4)
+     RELOC_NUMBER (R_960_OPTCALL,   5)
+     RELOC_NUMBER (R_960_OPTCALLX,  6)
+     RELOC_NUMBER (R_960_OPTCALLXA, 7)
+END_RELOC_NUMBERS (R_960_max)
+
+#endif /* _ELF_I960_H */
diff --git a/binutils-2.25/include/elf/ia64.h b/binutils-2.25/include/elf/ia64.h
new file mode 100644
index 00000000..7f2453d0
--- /dev/null
+++ b/binutils-2.25/include/elf/ia64.h
@@ -0,0 +1,416 @@
+/* IA-64 ELF support for BFD.
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2008, 2009, 2010
+   Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _ELF_IA64_H
+#define _ELF_IA64_H
+
+/* Bits in the e_flags field of the Elf64_Ehdr:  */
+
+#define EF_IA_64_MASKOS	   0x0000000f	/* OS-specific flags.  */
+#define EF_IA_64_ARCH	   0xff000000	/* Arch. version mask.  */
+#define EF_IA_64_ARCHVER_1 (1 << 24)    /* Arch. version level 1 compat.  */
+
+/* ??? These four definitions are not part of the SVR4 ABI.
+   They were present in David's initial code drop, so it is probable
+   that they are used by HP/UX.  */
+#define EF_IA_64_TRAPNIL (1 << 0)	/* Trap NIL pointer dereferences.  */
+#define EF_IA_64_EXT	 (1 << 2)	/* Program uses arch. extensions.  */
+#define EF_IA_64_BE	 (1 << 3)	/* PSR BE bit set (big-endian).  */
+#define EFA_IA_64_EAS2_3 0x23000000	/* IA64 EAS 2.3.  */
+
+#define EF_IA_64_ABI64		    (1 << 4) /* 64-bit ABI.  */
+/* Not used yet.  */
+#define EF_IA_64_REDUCEDFP	    (1 << 5) /* Only FP6-FP11 used.  */
+#define EF_IA_64_CONS_GP	    (1 << 6) /* gp as program wide constant.  */
+#define EF_IA_64_NOFUNCDESC_CONS_GP (1 << 7) /* And no function descriptors.  */
+/* Not used yet.  */
+#define EF_IA_64_ABSOLUTE	    (1 << 8) /* Load at absolute addresses.  */
+
+/* OpenVMS speficic.  */
+#define EF_IA_64_VMS_COMCOD	    0x03   /* Completion code.  */
+#define EF_IA_64_VMS_COMCOD_SUCCESS 0
+#define EF_IA_64_VMS_COMCOD_WARNING 1
+#define EF_IA_64_VMS_COMCOD_ERROR   2
+#define EF_IA_64_VMS_COMCOD_ABORT   3
+#define EF_IA_64_VMS_LINKAGES	    0x04   /* Contains VMS linkages info.  */
+
+#define ELF_STRING_ia64_archext		".IA_64.archext"
+#define ELF_STRING_ia64_pltoff		".IA_64.pltoff"
+#define ELF_STRING_ia64_unwind		".IA_64.unwind"
+#define ELF_STRING_ia64_unwind_info	".IA_64.unwind_info"
+#define ELF_STRING_ia64_unwind_once	".gnu.linkonce.ia64unw."
+#define ELF_STRING_ia64_unwind_info_once ".gnu.linkonce.ia64unwi."
+/* .IA_64.unwind_hdr is only used by HP-UX.  */
+#define ELF_STRING_ia64_unwind_hdr	".IA_64.unwind_hdr"
+
+/* Bits in the sh_flags field of Elf64_Shdr:  */
+
+#define SHF_IA_64_SHORT		  0x10000000	/* Section near gp.  */
+#define SHF_IA_64_NORECOV	  0x20000000	/* Spec insns w/o recovery.  */
+
+#define SHF_IA_64_HP_TLS	  0x01000000	/* HP specific TLS flag.  */
+
+#define SHF_IA_64_VMS_GLOBAL      0x0100000000ULL /* Global for clustering.  */
+#define SHF_IA_64_VMS_OVERLAID    0x0200000000ULL /* To be overlaid.  */
+#define SHF_IA_64_VMS_SHARED      0x0400000000ULL /* Shared btw processes.  */
+#define SHF_IA_64_VMS_VECTOR      0x0800000000ULL /* Priv change mode vect.  */
+#define SHF_IA_64_VMS_ALLOC_64BIT 0x1000000000ULL /* Allocate beyond 2GB.  */
+#define SHF_IA_64_VMS_PROTECTED   0x2000000000ULL /* Export from sharable.  */
+
+/* Possible values for sh_type in Elf64_Shdr: */
+
+#define SHT_IA_64_EXT		(SHT_LOPROC + 0)	/* Extension bits.  */
+#define SHT_IA_64_UNWIND	(SHT_LOPROC + 1)	/* Unwind bits.  */
+#define SHT_IA_64_LOPSREG	(SHT_LOPROC + 0x8000000)
+/* ABI says (SHT_LOPROC + 0xfffffff) but I think it's a typo -- this makes sense.  */
+#define SHT_IA_64_HIPSREG	(SHT_LOPROC + 0x8ffffff)
+#define SHT_IA_64_PRIORITY_INIT (SHT_LOPROC + 0x9000000)
+
+/* SHT_IA_64_HP_OPT_ANOT is only generated by HPUX compilers for its
+   optimization annotation section.  GCC does not generate it but we
+   want readelf to know what they are.  Do not use two capital Ns in
+   annotate or sed will turn it into 32 or 64 during the build.  */
+#define SHT_IA_64_HP_OPT_ANOT	0x60000004
+
+/* OpenVMS section types.  */
+/* The section contains PC-to-source correlation information for use by the
+   VMS RTL's traceback facility.  */
+#define SHT_IA_64_VMS_TRACE             0x60000000
+/* The section contains routine signature information for use by the
+   translated image executive.  */
+#define SHT_IA_64_VMS_TIE_SIGNATURES    0x60000001
+/* The section contains dwarf-3 information.  */
+#define SHT_IA_64_VMS_DEBUG             0x60000002
+/* The section contains the dwarf-3 string table.  */
+#define SHT_IA_64_VMS_DEBUG_STR         0x60000003
+/* The section contains linkage information to perform consistency checking
+   accross object modules.  */
+#define SHT_IA_64_VMS_LINKAGES          0x60000004
+/* The section allows the symbol vector in an image to be location through
+   the section table.  */
+#define SHT_IA_64_VMS_SYMBOL_VECTOR     0x60000005
+/* The section contains inter-image fixups.  */
+#define SHT_IA_64_VMS_FIXUP             0x60000006
+/* The section contains unmangled name info.  */
+#define SHT_IA_64_VMS_DISPLAY_NAME_INFO 0x60000007
+
+/* Bits in the p_flags field of Elf64_Phdr:  */
+
+#define PF_IA_64_NORECOV	0x80000000
+
+/* Possible values for p_type in Elf64_Phdr:  */
+
+#define PT_IA_64_ARCHEXT	(PT_LOPROC + 0)	/* Arch extension bits,  */
+#define PT_IA_64_UNWIND 	(PT_LOPROC + 1)	/* IA64 unwind bits.  */
+
+/* HP-UX specific values for p_type in Elf64_Phdr.
+   These values are currently just used to make
+   readelf more usable on HP-UX.  */
+
+#define PT_IA_64_HP_OPT_ANOT	(PT_LOOS + 0x12)
+#define PT_IA_64_HP_HSL_ANOT	(PT_LOOS + 0x13)
+#define PT_IA_64_HP_STACK	(PT_LOOS + 0x14)
+
+/* Possible values for d_tag in Elf64_Dyn:  */
+
+#define DT_IA_64_PLT_RESERVE	(DT_LOPROC + 0)
+
+/* VMS specific values for d_tag in Elf64_Dyn:  */
+
+#define DT_IA_64_VMS_SUBTYPE         (DT_LOOS + 0)
+#define DT_IA_64_VMS_IMGIOCNT        (DT_LOOS + 2)
+#define DT_IA_64_VMS_LNKFLAGS        (DT_LOOS + 8)
+#define DT_IA_64_VMS_VIR_MEM_BLK_SIZ (DT_LOOS + 10)
+#define DT_IA_64_VMS_IDENT           (DT_LOOS + 12)
+#define DT_IA_64_VMS_NEEDED_IDENT    (DT_LOOS + 16)
+#define DT_IA_64_VMS_IMG_RELA_CNT    (DT_LOOS + 18)
+#define DT_IA_64_VMS_SEG_RELA_CNT    (DT_LOOS + 20)
+#define DT_IA_64_VMS_FIXUP_RELA_CNT  (DT_LOOS + 22)
+#define DT_IA_64_VMS_FIXUP_NEEDED    (DT_LOOS + 24)
+#define DT_IA_64_VMS_SYMVEC_CNT      (DT_LOOS + 26)
+#define DT_IA_64_VMS_XLATED          (DT_LOOS + 30)
+#define DT_IA_64_VMS_STACKSIZE       (DT_LOOS + 32)
+#define DT_IA_64_VMS_UNWINDSZ        (DT_LOOS + 34)
+#define DT_IA_64_VMS_UNWIND_CODSEG   (DT_LOOS + 36)
+#define DT_IA_64_VMS_UNWIND_INFOSEG  (DT_LOOS + 38)
+#define DT_IA_64_VMS_LINKTIME        (DT_LOOS + 40)
+#define DT_IA_64_VMS_SEG_NO          (DT_LOOS + 42)
+#define DT_IA_64_VMS_SYMVEC_OFFSET   (DT_LOOS + 44)
+#define DT_IA_64_VMS_SYMVEC_SEG      (DT_LOOS + 46)
+#define DT_IA_64_VMS_UNWIND_OFFSET   (DT_LOOS + 48)
+#define DT_IA_64_VMS_UNWIND_SEG      (DT_LOOS + 50)
+#define DT_IA_64_VMS_STRTAB_OFFSET   (DT_LOOS + 52)
+#define DT_IA_64_VMS_SYSVER_OFFSET   (DT_LOOS + 54)
+#define DT_IA_64_VMS_IMG_RELA_OFF    (DT_LOOS + 56)
+#define DT_IA_64_VMS_SEG_RELA_OFF    (DT_LOOS + 58)
+#define DT_IA_64_VMS_FIXUP_RELA_OFF  (DT_LOOS + 60)
+#define DT_IA_64_VMS_PLTGOT_OFFSET   (DT_LOOS + 62)
+#define DT_IA_64_VMS_PLTGOT_SEG      (DT_LOOS + 64)
+#define DT_IA_64_VMS_FPMODE          (DT_LOOS + 66)
+
+/* Values for DT_IA_64_LNKFLAGS.  */
+#define VMS_LF_CALL_DEBUG	0x0001	/* Activate and call the debugger.  */
+#define VMS_LF_NOP0BUFS		0x0002	/* RMS use of P0 for i/o disabled.  */
+#define VMS_LF_P0IMAGE		0x0004	/* Image in P0 space only.  */
+#define VMS_LF_MKTHREADS	0x0008	/* Multiple kernel threads enabled.  */
+#define VMS_LF_UPCALLS		0x0010	/* Upcalls enabled.  */
+#define VMS_LF_IMGSTA		0x0020	/* Use SYS$IMGSTA.  */
+#define VMS_LF_INITIALIZE	0x0040	/* Image uses tfradr2.  */
+#define VMS_LF_MAIN		0x0080	/* Image uses tfradr3.  */
+#define VMS_LF_EXE_INIT		0x0200	/* Image uses tfradr4.  */
+#define VMS_LF_TBK_IN_IMG	0x0400	/* Traceback records in image.  */
+#define VMS_LF_DBG_IN_IMG	0x0800	/* Debug records in image.  */
+#define VMS_LF_TBK_IN_DSF	0x1000	/* Traceback records in DSF.  */
+#define VMS_LF_DBG_IN_DSF	0x2000	/* Debug records in DSF.  */
+#define VMS_LF_SIGNATURES	0x4000	/* Signatures present.  */
+#define VMS_LF_REL_SEG_OFF	0x8000	/* Maintain relative pos of seg.  */
+
+/* This section only used by HP-UX, The HP linker gives weak symbols
+   precedence over regular common symbols.  We want common to override
+   weak.  Using this common instead of SHN_COMMON does that.  */
+#define SHN_IA_64_ANSI_COMMON SHN_LORESERVE
+
+/* This section is only used by OpenVMS.  Symbol is defined in the symbol
+   vector (only possible for image files).  */
+#define SHN_IA_64_VMS_SYMVEC SHN_LOOS
+
+/* OpenVMS IA64-specific symbol attributes.  */
+#define VMS_STO_VISIBILITY 3	  /* Alias of the standard field.  */
+#define VMS_ST_VISIBILITY(o) ((o) & VMS_STO_VISIBILITY)
+#define VMS_STO_FUNC_TYPE  0x30	  /* Function type.  */
+#define VMS_ST_FUNC_TYPE(o)  (((o) & VMS_STO_FUNC_TYPE) >> 4)
+# define VMS_SFT_CODE_ADDR 0	  /* Symbol value is a code address.  */
+# define VMS_SFT_SYMV_IDX  1	  /* Symbol value is a symbol vector index.  */
+# define VMS_SFT_FD	   2	  /* Symbol value is a function descriptor.  */
+# define VMS_SFT_RESERVE   3	  /* Reserved.  */
+#define VMS_STO_LINKAGE    0xc0
+#define VMS_ST_LINKAGE(o)  (((o) & VMS_STO_LINKAGE) >> 6)
+# define VMS_STL_IGNORE	   0	  /* No associated linkage.  */
+# define VMS_STL_RESERVE   1
+# define VMS_STL_STD	   2	  /* Standard linkage with return value.  */
+# define VMS_STL_LNK	   3	  /* Explicit represented in .vms_linkages.  */
+
+/* OpenVMS specific symbol binding values.  */
+#define STB_VMS_WEAK	11	/* VMS weak symbol.  */
+#define STB_VMS_SYSTEM	12	/* System symbol.  */
+
+/* OpenVMS specific fixup and relocation structures.  */
+
+typedef struct
+{
+  unsigned char fixup_offset[8];
+  unsigned char type[4];
+  unsigned char fixup_seg[4];
+  unsigned char addend[8];
+  unsigned char symvec_index[4];
+  unsigned char data_type[4];
+} Elf64_External_VMS_IMAGE_FIXUP;
+
+typedef struct
+{
+  unsigned char rela_offset[8];
+  unsigned char type[4];
+  unsigned char rela_seg[4];
+  unsigned char addend[8];
+  unsigned char sym_offset[8];
+  unsigned char sym_seg[4];
+  unsigned char fill_1[4];
+} Elf64_External_VMS_IMAGE_RELA;
+
+/* Note segments.  VMS is special as it uses 64-bit entries.  */
+
+typedef struct {
+  unsigned char	namesz[8];		/* Size of entry's owner string */
+  unsigned char	descsz[8];		/* Size of the note descriptor */
+  unsigned char	type[8];		/* Interpretation of the descriptor */
+  char		name[1];		/* Start of the name+desc data */
+} Elf64_External_VMS_Note;
+
+#define NT_VMS_MHD         1 /* Object module name, version, and date/time.  */
+#define NT_VMS_LNM         2 /* Language processor name.  */
+#define NT_VMS_SRC         3 /* Source files.  */
+#define NT_VMS_TITLE       4 /* Title text.  */
+#define NT_VMS_EIDC        5 /* Entity ident consistency check.  */
+#define NT_VMS_FPMODE      6 /* Whole program floating-point mode.  */
+#define NT_VMS_LINKTIME  101 /* Date/time image was linked.  */
+#define NT_VMS_IMGNAM    102 /* Image name string.  */
+#define NT_VMS_IMGID     103 /* Image ident string.  */
+#define NT_VMS_LINKID    104 /* Linker ident string.  */
+#define NT_VMS_IMGBID    105 /* Image build ident string.  */
+#define NT_VMS_GSTNAM    106 /* Global Symbol Table Name.  */
+#define NT_VMS_ORIG_DYN  107 /* Original setting of dynamic data.  */
+#define NT_VMS_PATCHTIME 108 /* Date/time of last patch.  */
+
+/* Corresponding data for NT_VMS_ORIG_DYM.  */
+
+typedef struct  {
+  unsigned char major_id[4];		/* Should be 1.  */
+  unsigned char minor_id[4];		/* Should be 3.  */
+  unsigned char manipulation_date[8];	/* Original NT_VMS_LNKTIME.  */
+  unsigned char link_flags[8];		/* Original NT_VMS_LNKFLAGS.  */
+  unsigned char elf_flags[4];		/* Original ehdr flags.  */
+  unsigned char _pad[4];
+  unsigned char imgid[1];		/* Original NT_VMS_IMGID.  */
+} Elf64_External_VMS_ORIG_DYN_Note;
+
+/* IA64-specific relocation types: */
+
+/* Relocs apply to specific instructions within a bundle.  The least
+   significant 2 bits of the address indicate which instruction in the
+   bundle the reloc refers to (0=first slot, 1=second slow, 2=third
+   slot, 3=undefined) and the remaining bits give the address of the
+   bundle (16 byte aligned).
+
+   The top 5 bits of the reloc code specifies the expression type, the
+   low 3 bits the format of the data word being relocated.  */
+
+#include "elf/reloc-macros.h"
+
+START_RELOC_NUMBERS (elf_ia64_reloc_type)
+  RELOC_NUMBER (R_IA64_NONE, 0x00)	/* none */
+
+  RELOC_NUMBER (R_IA64_IMM14, 0x21)	/* symbol + addend, add imm14 */
+  RELOC_NUMBER (R_IA64_IMM22, 0x22)	/* symbol + addend, add imm22 */
+  RELOC_NUMBER (R_IA64_IMM64, 0x23)	/* symbol + addend, mov imm64 */
+  RELOC_NUMBER (R_IA64_DIR32MSB, 0x24)	/* symbol + addend, data4 MSB */
+  RELOC_NUMBER (R_IA64_DIR32LSB, 0x25)	/* symbol + addend, data4 LSB */
+  RELOC_NUMBER (R_IA64_DIR64MSB, 0x26)	/* symbol + addend, data8 MSB */
+  RELOC_NUMBER (R_IA64_DIR64LSB, 0x27)	/* symbol + addend, data8 LSB */
+
+  RELOC_NUMBER (R_IA64_GPREL22, 0x2a)	/* @gprel(sym+add), add imm22 */
+  RELOC_NUMBER (R_IA64_GPREL64I, 0x2b)	/* @gprel(sym+add), mov imm64 */
+  RELOC_NUMBER (R_IA64_GPREL32MSB, 0x2c) /* @gprel(sym+add), data4 MSB */
+  RELOC_NUMBER (R_IA64_GPREL32LSB, 0x2d) /* @gprel(sym+add), data4 LSB */
+  RELOC_NUMBER (R_IA64_GPREL64MSB, 0x2e) /* @gprel(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_GPREL64LSB, 0x2f) /* @gprel(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_LTOFF22, 0x32)	/* @ltoff(sym+add), add imm22 */
+  RELOC_NUMBER (R_IA64_LTOFF64I, 0x33)	/* @ltoff(sym+add), mov imm64 */
+
+  RELOC_NUMBER (R_IA64_PLTOFF22, 0x3a)	/* @pltoff(sym+add), add imm22 */
+  RELOC_NUMBER (R_IA64_PLTOFF64I, 0x3b)	/* @pltoff(sym+add), mov imm64 */
+  RELOC_NUMBER (R_IA64_PLTOFF64MSB, 0x3e) /* @pltoff(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_PLTOFF64LSB, 0x3f) /* @pltoff(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_FPTR64I, 0x43)	/* @fptr(sym+add), mov imm64 */
+  RELOC_NUMBER (R_IA64_FPTR32MSB, 0x44)	/* @fptr(sym+add), data4 MSB */
+  RELOC_NUMBER (R_IA64_FPTR32LSB, 0x45)	/* @fptr(sym+add), data4 LSB */
+  RELOC_NUMBER (R_IA64_FPTR64MSB, 0x46)	/* @fptr(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_FPTR64LSB, 0x47)	/* @fptr(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_PCREL60B, 0x48)	/* @pcrel(sym+add), brl */
+  RELOC_NUMBER (R_IA64_PCREL21B, 0x49)	/* @pcrel(sym+add), ptb, call */
+  RELOC_NUMBER (R_IA64_PCREL21M, 0x4a)	/* @pcrel(sym+add), chk.s */
+  RELOC_NUMBER (R_IA64_PCREL21F, 0x4b)	/* @pcrel(sym+add), fchkf */
+  RELOC_NUMBER (R_IA64_PCREL32MSB, 0x4c) /* @pcrel(sym+add), data4 MSB */
+  RELOC_NUMBER (R_IA64_PCREL32LSB, 0x4d) /* @pcrel(sym+add), data4 LSB */
+  RELOC_NUMBER (R_IA64_PCREL64MSB, 0x4e) /* @pcrel(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_PCREL64LSB, 0x4f) /* @pcrel(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR22, 0x52) /* @ltoff(@fptr(s+a)), imm22 */
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR64I, 0x53) /* @ltoff(@fptr(s+a)), imm64 */
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR32MSB, 0x54) /* @ltoff(@fptr(s+a)), 4 MSB */
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR32LSB, 0x55) /* @ltoff(@fptr(s+a)), 4 LSB */
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR64MSB, 0x56) /* @ltoff(@fptr(s+a)), 8 MSB */
+  RELOC_NUMBER (R_IA64_LTOFF_FPTR64LSB, 0x57) /* @ltoff(@fptr(s+a)), 8 LSB */
+
+  RELOC_NUMBER (R_IA64_SEGREL32MSB, 0x5c) /* @segrel(sym+add), data4 MSB */
+  RELOC_NUMBER (R_IA64_SEGREL32LSB, 0x5d) /* @segrel(sym+add), data4 LSB */
+  RELOC_NUMBER (R_IA64_SEGREL64MSB, 0x5e) /* @segrel(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_SEGREL64LSB, 0x5f) /* @segrel(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_SECREL32MSB, 0x64) /* @secrel(sym+add), data4 MSB */
+  RELOC_NUMBER (R_IA64_SECREL32LSB, 0x65) /* @secrel(sym+add), data4 LSB */
+  RELOC_NUMBER (R_IA64_SECREL64MSB, 0x66) /* @secrel(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_SECREL64LSB, 0x67) /* @secrel(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_REL32MSB, 0x6c)	/* data 4 + REL */
+  RELOC_NUMBER (R_IA64_REL32LSB, 0x6d)	/* data 4 + REL */
+  RELOC_NUMBER (R_IA64_REL64MSB, 0x6e)	/* data 8 + REL */
+  RELOC_NUMBER (R_IA64_REL64LSB, 0x6f)	/* data 8 + REL */
+
+  RELOC_NUMBER (R_IA64_LTV32MSB, 0x74)	/* symbol + addend, data4 MSB */
+  RELOC_NUMBER (R_IA64_LTV32LSB, 0x75)	/* symbol + addend, data4 LSB */
+  RELOC_NUMBER (R_IA64_LTV64MSB, 0x76)	/* symbol + addend, data8 MSB */
+  RELOC_NUMBER (R_IA64_LTV64LSB, 0x77)	/* symbol + addend, data8 LSB */
+
+  RELOC_NUMBER (R_IA64_PCREL21BI, 0x79)	/* @pcrel(sym+add), ptb, call */
+  RELOC_NUMBER (R_IA64_PCREL22, 0x7a)	/* @pcrel(sym+add), imm22 */
+  RELOC_NUMBER (R_IA64_PCREL64I, 0x7b)	/* @pcrel(sym+add), imm64 */
+
+  RELOC_NUMBER (R_IA64_IPLTMSB, 0x80)	/* dynamic reloc, imported PLT, MSB */
+  RELOC_NUMBER (R_IA64_IPLTLSB, 0x81)	/* dynamic reloc, imported PLT, LSB */
+  RELOC_NUMBER (R_IA64_COPY, 0x84)	/* dynamic reloc, data copy */
+  RELOC_NUMBER (R_IA64_LTOFF22X, 0x86)  /* LTOFF22, relaxable.  */
+  RELOC_NUMBER (R_IA64_LDXMOV, 0x87)	/* Use of LTOFF22X.  */
+
+  RELOC_NUMBER (R_IA64_TPREL14, 0x91)	 /* @tprel(sym+add), add imm14 */
+  RELOC_NUMBER (R_IA64_TPREL22, 0x92)	 /* @tprel(sym+add), add imm22 */
+  RELOC_NUMBER (R_IA64_TPREL64I, 0x93)	 /* @tprel(sym+add), add imm64 */
+  RELOC_NUMBER (R_IA64_TPREL64MSB, 0x96) /* @tprel(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_TPREL64LSB, 0x97) /* @tprel(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_LTOFF_TPREL22, 0x9a) /* @ltoff(@tprel(s+a)), add imm22 */
+
+  RELOC_NUMBER (R_IA64_DTPMOD64MSB, 0xa6) /* @dtpmod(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_DTPMOD64LSB, 0xa7) /* @dtpmod(sym+add), data8 LSB */
+  RELOC_NUMBER (R_IA64_LTOFF_DTPMOD22, 0xaa) /* @ltoff(@dtpmod(s+a)), imm22 */
+
+  RELOC_NUMBER (R_IA64_DTPREL14, 0xb1)    /* @dtprel(sym+add), imm14 */
+  RELOC_NUMBER (R_IA64_DTPREL22, 0xb2)    /* @dtprel(sym+add), imm22 */
+  RELOC_NUMBER (R_IA64_DTPREL64I, 0xb3)   /* @dtprel(sym+add), imm64 */
+  RELOC_NUMBER (R_IA64_DTPREL32MSB, 0xb4) /* @dtprel(sym+add), data4 MSB */
+  RELOC_NUMBER (R_IA64_DTPREL32LSB, 0xb5) /* @dtprel(sym+add), data4 LSB */
+  RELOC_NUMBER (R_IA64_DTPREL64MSB, 0xb6) /* @dtprel(sym+add), data8 MSB */
+  RELOC_NUMBER (R_IA64_DTPREL64LSB, 0xb7) /* @dtprel(sym+add), data8 LSB */
+
+  RELOC_NUMBER (R_IA64_LTOFF_DTPREL22, 0xba) /* @ltoff(@dtprel(s+a)), imm22 */
+
+  FAKE_RELOC (R_IA64_MAX_RELOC_CODE, 0xba)
+
+  /* OpenVMS specific relocs.  */
+  RELOC_NUMBER (R_IA64_VMS_DIR8, 0x70000000)		/* S + A */
+  RELOC_NUMBER (R_IA64_VMS_DIR16LSB, 0x70000001)	/* S + A */
+  RELOC_NUMBER (R_IA64_VMS_CALL_SIGNATURE, 0x70000002)
+  RELOC_NUMBER (R_IA64_VMS_EXECLET_FUNC, 0x70000003)
+  RELOC_NUMBER (R_IA64_VMS_EXECLET_DATA, 0x70000004)
+  RELOC_NUMBER (R_IA64_VMS_FIX8, 0x70000005)		/* S + A */
+  RELOC_NUMBER (R_IA64_VMS_FIX16, 0x70000006)		/* S + A */
+  RELOC_NUMBER (R_IA64_VMS_FIX32, 0x70000007)		/* S + A */
+  RELOC_NUMBER (R_IA64_VMS_FIX64, 0x70000008)		/* S + A */
+  RELOC_NUMBER (R_IA64_VMS_FIXFD, 0x70000009)
+  RELOC_NUMBER (R_IA64_VMS_ACC_LOAD, 0x7000000a)	/* ACC = S + A */
+  RELOC_NUMBER (R_IA64_VMS_ACC_ADD, 0x7000000b)		/* ACC += S + A */
+  RELOC_NUMBER (R_IA64_VMS_ACC_SUB, 0x7000000c)		/* ACC -= S + A */
+  RELOC_NUMBER (R_IA64_VMS_ACC_MUL, 0x7000000d)		/* ACC *= S + A */
+  RELOC_NUMBER (R_IA64_VMS_ACC_DIV, 0x7000000e)		/* ACC /= S + A */
+  RELOC_NUMBER (R_IA64_VMS_ACC_AND, 0x7000000f)		/* ACC &= S + A */
+  RELOC_NUMBER (R_IA64_VMS_ACC_IOR, 0x70000010)		/* ACC |= S + A */
+  RELOC_NUMBER (R_IA64_VMS_ACC_EOR, 0x70000011)		/* ACC ^= S + A */
+  RELOC_NUMBER (R_IA64_VMS_ACC_ASH, 0x70000012)		/* ACC >>= S + A */
+  RELOC_NUMBER (R_IA64_VMS_ACC_STO8, 0x70000014)	/* ACC */
+  RELOC_NUMBER (R_IA64_VMS_ACC_STO16LSH, 0x70000015)	/* ACC */
+  RELOC_NUMBER (R_IA64_VMS_ACC_STO32LSH, 0x70000016)	/* ACC */
+  RELOC_NUMBER (R_IA64_VMS_ACC_STO64LSH, 0x70000017)	/* ACC */
+END_RELOC_NUMBERS (R_IA64_max)
+
+#endif /* _ELF_IA64_H */
diff --git a/binutils-2.25/include/elf/internal.h b/binutils-2.25/include/elf/internal.h
new file mode 100644
index 00000000..46150378
--- /dev/null
+++ b/binutils-2.25/include/elf/internal.h
@@ -0,0 +1,360 @@
+/* ELF support for BFD.
+   Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002,
+   2003, 2006, 2007, 2008, 2010, 2011 Free Software Foundation, Inc.
+
+   Written by Fred Fish @ Cygnus Support, from information published
+   in "UNIX System V Release 4, Programmers Guide: ANSI C and
+   Programming Support Tools".
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file is part of ELF support for BFD, and contains the portions
+   that describe how ELF is represented internally in the BFD library.
+   I.E. it describes the in-memory representation of ELF.  It requires
+   the elf-common.h file which contains the portions that are common to
+   both the internal and external representations.  */
+
+/* NOTE that these structures are not kept in the same order as they appear
+   in the object file.  In some cases they've been reordered for more optimal
+   packing under various circumstances.  */
+
+#ifndef _ELF_INTERNAL_H
+#define _ELF_INTERNAL_H
+
+/* Special section indices, which may show up in st_shndx fields, among
+   other places.  */
+
+#undef SHN_UNDEF
+#undef SHN_LORESERVE
+#undef SHN_LOPROC
+#undef SHN_HIPROC
+#undef SHN_LOOS
+#undef SHN_HIOS
+#undef SHN_ABS
+#undef SHN_COMMON
+#undef SHN_XINDEX
+#undef SHN_HIRESERVE
+#define SHN_UNDEF	0		/* Undefined section reference */
+#define SHN_LORESERVE	(-0x100u)	/* Begin range of reserved indices */
+#define SHN_LOPROC	(-0x100u)	/* Begin range of appl-specific */
+#define SHN_HIPROC	(-0xE1u)	/* End range of appl-specific */
+#define SHN_LOOS	(-0xE0u)	/* OS specific semantics, lo */
+#define SHN_HIOS	(-0xC1u)	/* OS specific semantics, hi */
+#define SHN_ABS		(-0xFu)		/* Associated symbol is absolute */
+#define SHN_COMMON	(-0xEu)		/* Associated symbol is in common */
+#define SHN_XINDEX	(-0x1u)		/* Section index is held elsewhere */
+#define SHN_HIRESERVE	(-0x1u)		/* End range of reserved indices */
+#define SHN_BAD		(-0x101u)	/* Used internally by bfd */
+
+/* ELF Header */
+
+#define EI_NIDENT	16		/* Size of e_ident[] */
+
+typedef struct elf_internal_ehdr {
+  unsigned char		e_ident[EI_NIDENT]; /* ELF "magic number" */
+  bfd_vma		e_entry;	/* Entry point virtual address */
+  bfd_size_type		e_phoff;	/* Program header table file offset */
+  bfd_size_type		e_shoff;	/* Section header table file offset */
+  unsigned long		e_version;	/* Identifies object file version */
+  unsigned long		e_flags;	/* Processor-specific flags */
+  unsigned short	e_type;		/* Identifies object file type */
+  unsigned short	e_machine;	/* Specifies required architecture */
+  unsigned int		e_ehsize;	/* ELF header size in bytes */
+  unsigned int		e_phentsize;	/* Program header table entry size */
+  unsigned int		e_phnum;	/* Program header table entry count */
+  unsigned int		e_shentsize;	/* Section header table entry size */
+  unsigned int		e_shnum;	/* Section header table entry count */
+  unsigned int		e_shstrndx;	/* Section header string table index */
+} Elf_Internal_Ehdr;
+
+/* Program header */
+
+struct elf_internal_phdr {
+  unsigned long	p_type;			/* Identifies program segment type */
+  unsigned long	p_flags;		/* Segment flags */
+  bfd_vma	p_offset;		/* Segment file offset */
+  bfd_vma	p_vaddr;		/* Segment virtual address */
+  bfd_vma	p_paddr;		/* Segment physical address */
+  bfd_vma	p_filesz;		/* Segment size in file */
+  bfd_vma	p_memsz;		/* Segment size in memory */
+  bfd_vma	p_align;		/* Segment alignment, file & memory */
+};
+
+typedef struct elf_internal_phdr Elf_Internal_Phdr;
+
+/* Section header */
+
+typedef struct elf_internal_shdr {
+  unsigned int	sh_name;		/* Section name, index in string tbl */
+  unsigned int	sh_type;		/* Type of section */
+  bfd_vma	sh_flags;		/* Miscellaneous section attributes */
+  bfd_vma	sh_addr;		/* Section virtual addr at execution */
+  file_ptr	sh_offset;		/* Section file offset */
+  bfd_size_type	sh_size;		/* Size of section in bytes */
+  unsigned int	sh_link;		/* Index of another section */
+  unsigned int	sh_info;		/* Additional section information */
+  bfd_vma	sh_addralign;		/* Section alignment */
+  bfd_size_type	sh_entsize;		/* Entry size if section holds table */
+
+  /* The internal rep also has some cached info associated with it. */
+  asection *	bfd_section;		/* Associated BFD section.  */
+  unsigned char *contents;		/* Section contents.  */
+} Elf_Internal_Shdr;
+
+/* Symbol table entry */
+
+struct elf_internal_sym {
+  bfd_vma	st_value;		/* Value of the symbol */
+  bfd_vma	st_size;		/* Associated symbol size */
+  unsigned long	st_name;		/* Symbol name, index in string tbl */
+  unsigned char	st_info;		/* Type and binding attributes */
+  unsigned char	st_other;		/* Visibilty, and target specific */
+  unsigned char st_target_internal;	/* Internal-only information */
+  unsigned int  st_shndx;		/* Associated section index */
+};
+
+typedef struct elf_internal_sym Elf_Internal_Sym;
+
+/* Note segments */
+
+typedef struct elf_internal_note {
+  unsigned long	namesz;			/* Size of entry's owner string */
+  unsigned long	descsz;			/* Size of the note descriptor */
+  unsigned long	type;			/* Interpretation of the descriptor */
+  char *	namedata;		/* Start of the name+desc data */
+  char *	descdata;		/* Start of the desc data */
+  bfd_vma	descpos;		/* File offset of the descdata */
+} Elf_Internal_Note;
+
+/* Relocation Entries */
+
+typedef struct elf_internal_rela {
+  bfd_vma	r_offset;	/* Location at which to apply the action */
+  bfd_vma	r_info;		/* Index and Type of relocation */
+  bfd_vma	r_addend;	/* Constant addend used to compute value */
+} Elf_Internal_Rela;
+
+/* dynamic section structure */
+
+typedef struct elf_internal_dyn {
+  /* This needs to support 64-bit values in elf64.  */
+  bfd_vma d_tag;		/* entry tag value */
+  union {
+    /* This needs to support 64-bit values in elf64.  */
+    bfd_vma	d_val;
+    bfd_vma	d_ptr;
+  } d_un;
+} Elf_Internal_Dyn;
+
+/* This structure appears in a SHT_GNU_verdef section.  */
+
+typedef struct elf_internal_verdef {
+  unsigned short vd_version;	/* Version number of structure.  */
+  unsigned short vd_flags;	/* Flags (VER_FLG_*).  */
+  unsigned short vd_ndx;	/* Version index.  */
+  unsigned short vd_cnt;	/* Number of verdaux entries.  */
+  unsigned long	 vd_hash;	/* Hash of name.  */
+  unsigned long	 vd_aux;	/* Offset to verdaux entries.  */
+  unsigned long	 vd_next;	/* Offset to next verdef.  */
+
+  /* These fields are set up when BFD reads in the structure.  FIXME:
+     It would be cleaner to store these in a different structure.  */
+  bfd			      *vd_bfd;		/* BFD.  */
+  const char		      *vd_nodename;	/* Version name.  */
+  struct elf_internal_verdef  *vd_nextdef;	/* vd_next as pointer.  */
+  struct elf_internal_verdaux *vd_auxptr;	/* vd_aux as pointer.  */
+  unsigned int		       vd_exp_refno;	/* Used by the linker.  */
+} Elf_Internal_Verdef;
+
+/* This structure appears in a SHT_GNU_verdef section.  */
+
+typedef struct elf_internal_verdaux {
+  unsigned long vda_name;	/* String table offset of name.  */
+  unsigned long vda_next;	/* Offset to next verdaux.  */
+
+  /* These fields are set up when BFD reads in the structure.  FIXME:
+     It would be cleaner to store these in a different structure.  */
+  const char *vda_nodename;			/* vda_name as pointer.  */
+  struct elf_internal_verdaux *vda_nextptr;	/* vda_next as pointer.  */
+} Elf_Internal_Verdaux;
+
+/* This structure appears in a SHT_GNU_verneed section.  */
+
+typedef struct elf_internal_verneed {
+  unsigned short vn_version;	/* Version number of structure.  */
+  unsigned short vn_cnt;	/* Number of vernaux entries.  */
+  unsigned long	 vn_file;	/* String table offset of library name.  */
+  unsigned long	 vn_aux;	/* Offset to vernaux entries.  */
+  unsigned long	 vn_next;	/* Offset to next verneed.  */
+
+  /* These fields are set up when BFD reads in the structure.  FIXME:
+     It would be cleaner to store these in a different structure.  */
+  bfd			      *vn_bfd;		/* BFD.  */
+  const char                  *vn_filename;	/* vn_file as pointer.  */
+  struct elf_internal_vernaux *vn_auxptr;	/* vn_aux as pointer.  */
+  struct elf_internal_verneed *vn_nextref;	/* vn_nextref as pointer.  */
+} Elf_Internal_Verneed;
+
+/* This structure appears in a SHT_GNU_verneed section.  */
+
+typedef struct elf_internal_vernaux {
+  unsigned long	 vna_hash;	/* Hash of dependency name.  */
+  unsigned short vna_flags;	/* Flags (VER_FLG_*).  */
+  unsigned short vna_other;	/* Unused.  */
+  unsigned long	 vna_name;	/* String table offset to version name.  */
+  unsigned long	 vna_next;	/* Offset to next vernaux.  */
+
+  /* These fields are set up when BFD reads in the structure.  FIXME:
+     It would be cleaner to store these in a different structure.  */
+  const char                  *vna_nodename;	/* vna_name as pointer.  */
+  struct elf_internal_vernaux *vna_nextptr;	/* vna_next as pointer.  */
+} Elf_Internal_Vernaux;
+
+/* This structure appears in a SHT_GNU_versym section.  This is not a
+   standard ELF structure; ELF just uses Elf32_Half.  */
+
+typedef struct elf_internal_versym {
+  unsigned short vs_vers;
+} Elf_Internal_Versym;
+
+/* Structure for syminfo section.  */
+typedef struct
+{
+  unsigned short int 	si_boundto;
+  unsigned short int	si_flags;
+} Elf_Internal_Syminfo;
+
+/* This structure appears on the stack and in NT_AUXV core file notes.  */
+typedef struct
+{
+  bfd_vma a_type;
+  bfd_vma a_val;
+} Elf_Internal_Auxv;
+
+
+/* This structure is used to describe how sections should be assigned
+   to program segments.  */
+
+struct elf_segment_map
+{
+  /* Next program segment.  */
+  struct elf_segment_map *next;
+  /* Program segment type.  */
+  unsigned long p_type;
+  /* Program segment flags.  */
+  unsigned long p_flags;
+  /* Program segment physical address.  */
+  bfd_vma p_paddr;
+  /* Program segment virtual address offset from section vma.  */
+  bfd_vma p_vaddr_offset;
+  /* Program segment alignment.  */
+  bfd_vma p_align;
+  /* Segment size in file and memory */
+  bfd_vma p_size;
+  /* Required size of filehdr + phdrs, if non-zero */
+  bfd_vma header_size;
+  /* Whether the p_flags field is valid; if not, the flags are based
+     on the section flags.  */
+  unsigned int p_flags_valid : 1;
+  /* Whether the p_paddr field is valid; if not, the physical address
+     is based on the section lma values.  */
+  unsigned int p_paddr_valid : 1;
+  /* Whether the p_align field is valid; if not, PT_LOAD segment
+     alignment is based on the default maximum page size.  */
+  unsigned int p_align_valid : 1;
+  /* Whether the p_size field is valid; if not, the size are based
+     on the section sizes.  */
+  unsigned int p_size_valid : 1;
+  /* Whether this segment includes the file header.  */
+  unsigned int includes_filehdr : 1;
+  /* Whether this segment includes the program headers.  */
+  unsigned int includes_phdrs : 1;
+  /* Number of sections (may be 0).  */
+  unsigned int count;
+  /* Sections.  Actual number of elements is in count field.  */
+  asection *sections[1];
+};
+
+/* .tbss is special.  It doesn't contribute memory space to normal
+   segments and it doesn't take file space in normal segments.  */
+#define ELF_TBSS_SPECIAL(sec_hdr, segment)			\
+  (((sec_hdr)->sh_flags & SHF_TLS) != 0				\
+   && (sec_hdr)->sh_type == SHT_NOBITS				\
+   && (segment)->p_type != PT_TLS)
+
+#define ELF_SECTION_SIZE(sec_hdr, segment)			\
+  (ELF_TBSS_SPECIAL(sec_hdr, segment) ? 0 : (sec_hdr)->sh_size)
+
+/* Decide if the section SEC_HDR is in SEGMENT.  If CHECK_VMA, then
+   VMAs are checked for alloc sections.  If STRICT, then a zero size
+   section won't match at the end of a segment, unless the segment
+   is also zero size.  Regardless of STRICT and CHECK_VMA, zero size
+   sections won't match at the start or end of PT_DYNAMIC, unless
+   PT_DYNAMIC is itself zero sized.  */
+#define ELF_SECTION_IN_SEGMENT_1(sec_hdr, segment, check_vma, strict)	\
+  ((/* Only PT_LOAD, PT_GNU_RELRO and PT_TLS segments can contain	\
+       SHF_TLS sections.  */						\
+    ((((sec_hdr)->sh_flags & SHF_TLS) != 0)				\
+     && ((segment)->p_type == PT_TLS					\
+	 || (segment)->p_type == PT_GNU_RELRO				\
+	 || (segment)->p_type == PT_LOAD))				\
+    /* PT_TLS segment contains only SHF_TLS sections, PT_PHDR no	\
+       sections at all.  */						\
+    || (((sec_hdr)->sh_flags & SHF_TLS) == 0				\
+	&& (segment)->p_type != PT_TLS					\
+	&& (segment)->p_type != PT_PHDR))				\
+   /* Any section besides one of type SHT_NOBITS must have file		\
+      offsets within the segment.  */					\
+   && ((sec_hdr)->sh_type == SHT_NOBITS					\
+       || ((bfd_vma) (sec_hdr)->sh_offset >= (segment)->p_offset	\
+	   && (!(strict)						\
+	       || ((sec_hdr)->sh_offset - (segment)->p_offset		\
+		   <= (segment)->p_filesz - 1))				\
+	   && (((sec_hdr)->sh_offset - (segment)->p_offset		\
+		+ ELF_SECTION_SIZE(sec_hdr, segment))			\
+	       <= (segment)->p_filesz)))				\
+   /* SHF_ALLOC sections must have VMAs within the segment.  */		\
+   && (!(check_vma)							\
+       || ((sec_hdr)->sh_flags & SHF_ALLOC) == 0			\
+       || ((sec_hdr)->sh_addr >= (segment)->p_vaddr			\
+	   && (!(strict)						\
+	       || ((sec_hdr)->sh_addr - (segment)->p_vaddr		\
+		   <= (segment)->p_memsz - 1))				\
+	   && (((sec_hdr)->sh_addr - (segment)->p_vaddr			\
+		+ ELF_SECTION_SIZE(sec_hdr, segment))			\
+	       <= (segment)->p_memsz)))					\
+   /* No zero size sections at start or end of PT_DYNAMIC.  */		\
+   && ((segment)->p_type != PT_DYNAMIC					\
+       || (sec_hdr)->sh_size != 0					\
+       || (segment)->p_memsz == 0					\
+       || (((sec_hdr)->sh_type == SHT_NOBITS				\
+	    || ((bfd_vma) (sec_hdr)->sh_offset > (segment)->p_offset	\
+	        && ((sec_hdr)->sh_offset - (segment)->p_offset		\
+		    < (segment)->p_filesz)))				\
+	   && (((sec_hdr)->sh_flags & SHF_ALLOC) == 0			\
+	       || ((sec_hdr)->sh_addr > (segment)->p_vaddr		\
+		   && ((sec_hdr)->sh_addr - (segment)->p_vaddr		\
+		       < (segment)->p_memsz))))))
+
+#define ELF_SECTION_IN_SEGMENT(sec_hdr, segment)			\
+  (ELF_SECTION_IN_SEGMENT_1 (sec_hdr, segment, 1, 0))
+
+#define ELF_SECTION_IN_SEGMENT_STRICT(sec_hdr, segment)			\
+  (ELF_SECTION_IN_SEGMENT_1 (sec_hdr, segment, 1, 1))
+
+#endif /* _ELF_INTERNAL_H */
diff --git a/binutils-2.25/include/elf/ip2k.h b/binutils-2.25/include/elf/ip2k.h
new file mode 100644
index 00000000..8b4f36ef
--- /dev/null
+++ b/binutils-2.25/include/elf/ip2k.h
@@ -0,0 +1,62 @@
+/* IP2xxx ELF support for BFD.
+   Copyright (C) 2000, 2002, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_IP2K_H
+#define _ELF_IP2K_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_ip2k_reloc_type)
+  RELOC_NUMBER (R_IP2K_NONE, 0)
+  RELOC_NUMBER (R_IP2K_16, 1)
+  RELOC_NUMBER (R_IP2K_32, 2)
+  RELOC_NUMBER (R_IP2K_FR9, 3)
+  RELOC_NUMBER (R_IP2K_BANK, 4)
+  RELOC_NUMBER (R_IP2K_ADDR16CJP, 5)
+  RELOC_NUMBER (R_IP2K_PAGE3, 6)
+  RELOC_NUMBER (R_IP2K_LO8DATA, 7)
+  RELOC_NUMBER (R_IP2K_HI8DATA, 8)
+  RELOC_NUMBER (R_IP2K_LO8INSN, 9)
+  RELOC_NUMBER (R_IP2K_HI8INSN, 10)
+  RELOC_NUMBER (R_IP2K_PC_SKIP, 11)
+  RELOC_NUMBER (R_IP2K_TEXT, 12)
+  RELOC_NUMBER (R_IP2K_FR_OFFSET, 13)
+  RELOC_NUMBER (R_IP2K_EX8DATA, 14)
+END_RELOC_NUMBERS(R_IP2K_max)
+
+
+/* Define the data & instruction memory discriminator.  In a linked
+   executable, an symbol should be deemed to point to an instruction
+   if ((address & IP2K_INSN_MASK) == IP2K_INSN_VALUE), and similarly
+   for the data space.  See also `ld/emulparams/elf32ip2k.sh'.  */
+/* ??? Consider extending the _MASK values to include all the
+   intermediate bits that must be zero due to the limited physical
+   memory size on the IP2K.  */
+
+#define IP2K_DATA_MASK   0xff000000
+#define IP2K_DATA_VALUE  0x01000000
+#define IP2K_INSN_MASK   0xff000000
+#define IP2K_INSN_VALUE  0x02000000
+
+/* The location of the memory mapped hardware stack.  */
+#define IP2K_STACK_VALUE 0x0f000000
+#define IP2K_STACK_SIZE  0x20
+
+#endif /* _ELF_IP2K_H */
diff --git a/binutils-2.25/include/elf/iq2000.h b/binutils-2.25/include/elf/iq2000.h
new file mode 100644
index 00000000..0f8e6971
--- /dev/null
+++ b/binutils-2.25/include/elf/iq2000.h
@@ -0,0 +1,58 @@
+/* IQ2000 ELF support for BFD.
+   Copyright (C) 2002, 2003, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_IQ2000_H
+#define _ELF_IQ2000_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_iq2000_reloc_type)
+  RELOC_NUMBER (R_IQ2000_NONE, 0)
+  RELOC_NUMBER (R_IQ2000_16, 1)
+  RELOC_NUMBER (R_IQ2000_32, 2)
+  RELOC_NUMBER (R_IQ2000_26, 3)
+  RELOC_NUMBER (R_IQ2000_PC16, 4)
+  RELOC_NUMBER (R_IQ2000_HI16, 5)
+  RELOC_NUMBER (R_IQ2000_LO16, 6)
+  RELOC_NUMBER (R_IQ2000_OFFSET_16, 7)
+  RELOC_NUMBER (R_IQ2000_OFFSET_21, 8)
+  RELOC_NUMBER (R_IQ2000_UHI16, 9)
+  RELOC_NUMBER (R_IQ2000_32_DEBUG, 10)
+  RELOC_NUMBER (R_IQ2000_GNU_VTINHERIT, 200)
+  RELOC_NUMBER (R_IQ2000_GNU_VTENTRY, 201)
+END_RELOC_NUMBERS(R_IQ2000_max)
+
+#define EF_IQ2000_CPU_IQ2000	0x00000001      /* default */
+#define EF_IQ2000_CPU_IQ10      0x00000002      /* IQ10 */
+#define EF_IQ2000_CPU_MASK	0x00000003	/* specific cpu bits */
+#define EF_IQ2000_ALL_FLAGS	(EF_IQ2000_CPU_MASK)
+
+/* Define the data & instruction memory discriminator.  In a linked
+   executable, an symbol should be deemed to point to an instruction
+   if ((address & IQ2000_INSN_MASK) == IQ2000_INSN_VALUE), and similarly
+   for the data space.  */
+
+#define IQ2000_DATA_MASK   0x80000000
+#define IQ2000_DATA_VALUE  0x00000000
+#define IQ2000_INSN_MASK   0x80000000
+#define IQ2000_INSN_VALUE  0x80000000
+
+
+#endif /* _ELF_IQ2000_H */
diff --git a/binutils-2.25/include/elf/lm32.h b/binutils-2.25/include/elf/lm32.h
new file mode 100644
index 00000000..6ed34ec4
--- /dev/null
+++ b/binutils-2.25/include/elf/lm32.h
@@ -0,0 +1,56 @@
+/* Lattice Mico32 ELF support for BFD.
+   Copyright 2008, 2010   Free Software Foundation, Inc.
+   Contributed by Jon Beniston <jon@beniston.com>
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_LM32_H
+#define _ELF_LM32_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_lm32_reloc_type)
+     RELOC_NUMBER (R_LM32_NONE,                      0)
+     RELOC_NUMBER (R_LM32_8,                         1)
+     RELOC_NUMBER (R_LM32_16,                        2)
+     RELOC_NUMBER (R_LM32_32,                        3)
+     RELOC_NUMBER (R_LM32_HI16,                      4)
+     RELOC_NUMBER (R_LM32_LO16,                      5)
+     RELOC_NUMBER (R_LM32_GPREL16,                   6)
+     RELOC_NUMBER (R_LM32_CALL,                      7)
+     RELOC_NUMBER (R_LM32_BRANCH,                    8)
+     RELOC_NUMBER (R_LM32_GNU_VTINHERIT,             9)
+     RELOC_NUMBER (R_LM32_GNU_VTENTRY,               10)
+     RELOC_NUMBER (R_LM32_16_GOT,                    11)
+     RELOC_NUMBER (R_LM32_GOTOFF_HI16,               12)
+     RELOC_NUMBER (R_LM32_GOTOFF_LO16,               13)
+     RELOC_NUMBER (R_LM32_COPY,                      14)
+     RELOC_NUMBER (R_LM32_GLOB_DAT,                  15)
+     RELOC_NUMBER (R_LM32_JMP_SLOT,                  16)
+     RELOC_NUMBER (R_LM32_RELATIVE,                  17)
+END_RELOC_NUMBERS (R_LM32_max)
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+#define EF_LM32_MACH                 0x00000001
+
+/* Various CPU types.  */
+
+#define E_LM32_MACH                  0x1
+
+#endif /* _ELF_LM32_H */
diff --git a/binutils-2.25/include/elf/m32c.h b/binutils-2.25/include/elf/m32c.h
new file mode 100644
index 00000000..29b80a67
--- /dev/null
+++ b/binutils-2.25/include/elf/m32c.h
@@ -0,0 +1,67 @@
+/* M32C ELF support for BFD.
+   Copyright (C) 2004, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_M32C_H
+#define _ELF_M32C_H
+
+#include "elf/reloc-macros.h"
+
+  /* Relocations.  */
+  START_RELOC_NUMBERS (elf_m32c_reloc_type)
+     RELOC_NUMBER (R_M32C_NONE, 0)
+     RELOC_NUMBER (R_M32C_16, 1)
+     RELOC_NUMBER (R_M32C_24, 2)
+     RELOC_NUMBER (R_M32C_32, 3)
+     RELOC_NUMBER (R_M32C_8_PCREL, 4)
+     RELOC_NUMBER (R_M32C_16_PCREL, 5)
+
+    /* 8 bit unsigned address, used for dsp8[a0] etc */
+     RELOC_NUMBER (R_M32C_8, 6)
+    /* Bits 0..15 of an address, for SMOVF's A0, A1A0, etc. */
+     RELOC_NUMBER (R_M32C_LO16, 7)
+    /* Bits 16..23 of an address, for SMOVF's R1H etc. */
+     RELOC_NUMBER (R_M32C_HI8, 8)
+    /* Bits 16..31 of an address, for LDE's A1A0 etc. */
+     RELOC_NUMBER (R_M32C_HI16, 9)
+
+    /* These are relocs we need when relaxing.  */
+    /* Marks various jump opcodes.  */
+     RELOC_NUMBER (R_M32C_RL_JUMP, 10)
+    /* Marks standard one-address form.  */
+     RELOC_NUMBER (R_M32C_RL_1ADDR, 11)
+    /* Marks standard two-address form.  */
+     RELOC_NUMBER (R_M32C_RL_2ADDR, 12)
+
+     END_RELOC_NUMBERS (R_M32C_max)
+
+#define EF_M32C_CPU_M16C	0x00000075      /* default */
+#define EF_M32C_CPU_M32C        0x00000078      /* m32c */
+#define EF_M32C_CPU_MASK	0x0000007F	/* specific cpu bits */
+#define EF_M32C_ALL_FLAGS	(EF_M32C_CPU_MASK)
+
+/* Define the data & instruction memory discriminator.  In a linked
+   executable, an symbol should be deemed to point to an instruction
+   if ((address & M16C_INSN_MASK) == M16C_INSN_VALUE), and similarly
+   for the data space.  See also `ld/emulparams/elf32m32c.sh'.  */
+#define M32C_DATA_MASK   0xffc00000
+#define M32C_DATA_VALUE  0x00000000
+#define M32C_INSN_MASK   0xffc00000
+#define M32C_INSN_VALUE  0x00400000
+
+#endif /* _ELF_M32C_H */
diff --git a/binutils-2.25/include/elf/m32r.h b/binutils-2.25/include/elf/m32r.h
new file mode 100644
index 00000000..7e06e3f3
--- /dev/null
+++ b/binutils-2.25/include/elf/m32r.h
@@ -0,0 +1,123 @@
+/* M32R ELF support for BFD.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2003, 2004, 2008, 2010
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_M32R_H
+#define _ELF_M32R_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_m32r_reloc_type)
+  RELOC_NUMBER (R_M32R_NONE, 0)
+  /* REL relocations */
+  RELOC_NUMBER (R_M32R_16, 1)		 /* For backwards compatibility. */
+  RELOC_NUMBER (R_M32R_32, 2)		 /* For backwards compatibility. */
+  RELOC_NUMBER (R_M32R_24, 3)		 /* For backwards compatibility. */
+  RELOC_NUMBER (R_M32R_10_PCREL, 4)	 /* For backwards compatibility. */
+  RELOC_NUMBER (R_M32R_18_PCREL, 5)	 /* For backwards compatibility. */
+  RELOC_NUMBER (R_M32R_26_PCREL, 6)	 /* For backwards compatibility. */
+  RELOC_NUMBER (R_M32R_HI16_ULO, 7)	 /* For backwards compatibility. */
+  RELOC_NUMBER (R_M32R_HI16_SLO, 8)	 /* For backwards compatibility. */
+  RELOC_NUMBER (R_M32R_LO16, 9)		 /* For backwards compatibility. */
+  RELOC_NUMBER (R_M32R_SDA16, 10)	 /* For backwards compatibility. */
+  RELOC_NUMBER (R_M32R_GNU_VTINHERIT, 11)/* For backwards compatibility. */
+  RELOC_NUMBER (R_M32R_GNU_VTENTRY, 12)	 /* For backwards compatibility. */
+
+  /* RELA relocations */
+  RELOC_NUMBER (R_M32R_16_RELA, 33)
+  RELOC_NUMBER (R_M32R_32_RELA, 34)
+  RELOC_NUMBER (R_M32R_24_RELA, 35)
+  RELOC_NUMBER (R_M32R_10_PCREL_RELA, 36)
+  RELOC_NUMBER (R_M32R_18_PCREL_RELA, 37)
+  RELOC_NUMBER (R_M32R_26_PCREL_RELA, 38)
+  RELOC_NUMBER (R_M32R_HI16_ULO_RELA, 39)
+  RELOC_NUMBER (R_M32R_HI16_SLO_RELA, 40)
+  RELOC_NUMBER (R_M32R_LO16_RELA, 41)
+  RELOC_NUMBER (R_M32R_SDA16_RELA, 42)
+  RELOC_NUMBER (R_M32R_RELA_GNU_VTINHERIT, 43)
+  RELOC_NUMBER (R_M32R_RELA_GNU_VTENTRY, 44)
+
+  RELOC_NUMBER (R_M32R_REL32, 45)
+                                                                                
+  RELOC_NUMBER (R_M32R_GOT24, 48)
+  RELOC_NUMBER (R_M32R_26_PLTREL, 49)
+  RELOC_NUMBER (R_M32R_COPY, 50)
+  RELOC_NUMBER (R_M32R_GLOB_DAT, 51)
+  RELOC_NUMBER (R_M32R_JMP_SLOT, 52)
+  RELOC_NUMBER (R_M32R_RELATIVE, 53)
+  RELOC_NUMBER (R_M32R_GOTOFF, 54)
+  RELOC_NUMBER (R_M32R_GOTPC24, 55)
+  RELOC_NUMBER (R_M32R_GOT16_HI_ULO, 56)
+  RELOC_NUMBER (R_M32R_GOT16_HI_SLO, 57)
+  RELOC_NUMBER (R_M32R_GOT16_LO, 58)
+  RELOC_NUMBER (R_M32R_GOTPC_HI_ULO, 59)
+  RELOC_NUMBER (R_M32R_GOTPC_HI_SLO, 60)
+  RELOC_NUMBER (R_M32R_GOTPC_LO, 61)
+  RELOC_NUMBER (R_M32R_GOTOFF_HI_ULO, 62)
+  RELOC_NUMBER (R_M32R_GOTOFF_HI_SLO, 63)
+  RELOC_NUMBER (R_M32R_GOTOFF_LO, 64)
+
+END_RELOC_NUMBERS (R_M32R_max)
+
+/* Processor specific section indices.  These sections do not actually
+   exist.  Symbols with a st_shndx field corresponding to one of these
+   values have a special meaning.  */
+
+/* Small common symbol.  */
+#define SHN_M32R_SCOMMON	SHN_LORESERVE
+
+/* Processor specific section flags.  */
+
+/* This section contains sufficient relocs to be relaxed.
+   When relaxing, even relocs of branch instructions the assembler could
+   complete must be present because relaxing may cause the branch target to
+   move.  */
+#define SHF_M32R_CAN_RELAX	0x10000000
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+/* Two bit m32r architecture field.  */
+#define EF_M32R_ARCH		0x30000000
+
+/* m32r code.  */
+#define E_M32R_ARCH		0x00000000
+/* m32rx code.  */
+#define E_M32RX_ARCH            0x10000000
+/* m32r2 code.  */
+#define E_M32R2_ARCH            0x20000000
+
+/* 12 bit m32r new instructions field.  */
+#define EF_M32R_INST            0x0FFF0000
+/* Parallel instructions.  */
+#define E_M32R_HAS_PARALLEL     0x00010000
+/* Hidden instructions for m32rx:
+   jc, jnc, macwhi-a, macwlo-a, mulwhi-a, mulwlo-a, sth+, shb+, sat, pcmpbz,
+   sc, snc.  */
+#define E_M32R_HAS_HIDDEN_INST  0x00020000
+/* New bit instructions:
+   clrpsw, setpsw, bset, bclr, btst.  */
+#define E_M32R_HAS_BIT_INST     0x00040000
+/* Floating point instructions.  */
+#define E_M32R_HAS_FLOAT_INST   0x00080000
+
+/* 4 bit m32r ignore to check field.  */
+#define EF_M32R_IGNORE          0x0000000F
+
+#endif
diff --git a/binutils-2.25/include/elf/m68hc11.h b/binutils-2.25/include/elf/m68hc11.h
new file mode 100644
index 00000000..58d88208
--- /dev/null
+++ b/binutils-2.25/include/elf/m68hc11.h
@@ -0,0 +1,107 @@
+/* m68hc11 & m68hc12 ELF support for BFD.
+   Copyright 1999, 2000, 2001, 2002, 2010, 2012 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_M68HC11_H
+#define _ELF_M68HC11_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocation types.  */
+START_RELOC_NUMBERS (elf_m68hc11_reloc_type)
+  RELOC_NUMBER (R_M68HC11_NONE, 0)
+  RELOC_NUMBER (R_M68HC11_8, 1)
+  RELOC_NUMBER (R_M68HC11_HI8, 2)
+  RELOC_NUMBER (R_M68HC11_LO8, 3)
+  RELOC_NUMBER (R_M68HC11_PCREL_8, 4)
+  RELOC_NUMBER (R_M68HC11_16, 5)
+  RELOC_NUMBER (R_M68HC11_32, 6)
+  RELOC_NUMBER (R_M68HC11_3B, 7)
+  RELOC_NUMBER (R_M68HC11_PCREL_16, 8)
+
+     /* These are GNU extensions to enable C++ vtable garbage collection.  */
+  RELOC_NUMBER (R_M68HC11_GNU_VTINHERIT, 9)
+  RELOC_NUMBER (R_M68HC11_GNU_VTENTRY, 10)
+
+  RELOC_NUMBER (R_M68HC11_24, 11)
+  RELOC_NUMBER (R_M68HC11_LO16, 12)
+  RELOC_NUMBER (R_M68HC11_PAGE, 13)
+
+  RELOC_NUMBER (R_M68HC12_16B, 15)
+  RELOC_NUMBER (R_M68HC12_PCREL_9, 16)
+  RELOC_NUMBER (R_M68HC12_PCREL_10, 17)
+  RELOC_NUMBER (R_M68HC12_HI8XG, 18)
+  RELOC_NUMBER (R_M68HC12_LO8XG, 19)
+
+     /* GNU extension for linker relaxation.
+        Mark beginning of a jump instruction (any form).  */
+  RELOC_NUMBER (R_M68HC11_RL_JUMP, 20)
+
+     /* Mark beginning of Gcc relaxation group instruction.  */
+  RELOC_NUMBER (R_M68HC11_RL_GROUP, 21)
+END_RELOC_NUMBERS (R_M68HC11_max)
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+/* ABI identification.  */
+#define EF_M68HC11_ABI  0x00000000F
+
+/* Integers are 32-bit long.  */
+#define E_M68HC11_I32   0x000000001
+
+/* Doubles are 64-bit long.  */
+#define E_M68HC11_F64   0x000000002
+
+/* Uses 68HC12 memory banks.  */
+#define E_M68HC12_BANKS 0x000000004
+
+/* XGATE ram offsetting.  */
+#define E_M68HC11_XGATE_RAMOFFSET     0x000000100
+
+/* Suppress warnings */
+#define E_M68HC11_NO_BANK_WARNING     0x000000200
+
+#define EF_M68HC11_MACH_MASK 0xF0
+#define EF_M68HC11_GENERIC   0x00 /* Generic 68HC12/backward compatibility.  */
+#define EF_M68HC12_MACH      0x10 /* 68HC12 microcontroller.  */
+#define EF_M68HCS12_MACH     0x20 /* 68HCS12 microcontroller.  */
+#define EF_M68HC11_MACH(mach) ((mach) & EF_M68HC11_MACH_MASK)
+
+/* True if we can merge machines.  A generic HC12 can work on any proc
+   but once we have specific code, merge is not possible.  */
+#define EF_M68HC11_CAN_MERGE_MACH(mach1, mach2) \
+  ((EF_M68HC11_MACH (mach1) == EF_M68HC11_MACH (mach2)) \
+   || (EF_M68HC11_MACH (mach1) == EF_M68HC11_GENERIC) \
+   || (EF_M68HC11_MACH (mach2) == EF_M68HC11_GENERIC))
+
+#define EF_M68HC11_MERGE_MACH(mach1, mach2) \
+  (((EF_M68HC11_MACH (mach1) == EF_M68HC11_MACH (mach2)) \
+    || (EF_M68HC11_MACH (mach1) == EF_M68HC11_GENERIC)) ? \
+      EF_M68HC11_MACH (mach2) : EF_M68HC11_MACH (mach1))
+
+
+/* Special values for the st_other field in the symbol table.  These
+   are used for 68HC12 to identify far functions (must be called with
+   'call' and returns with 'rtc').  */
+#define STO_M68HC12_FAR          0x80
+
+/* Identify interrupt handlers.  This is used by the debugger to
+   correctly compute the stack frame.  */
+#define STO_M68HC12_INTERRUPT    0x40
+     
+#endif
diff --git a/binutils-2.25/include/elf/m68k.h b/binutils-2.25/include/elf/m68k.h
new file mode 100644
index 00000000..f6f37ccf
--- /dev/null
+++ b/binutils-2.25/include/elf/m68k.h
@@ -0,0 +1,102 @@
+/* MC68k ELF support for BFD.
+   Copyright 1998, 1999, 2000, 2002, 2005, 2006, 2007, 2009, 2010
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_M68K_H
+#define _ELF_M68K_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocation types.  */
+START_RELOC_NUMBERS (elf_m68k_reloc_type)
+  RELOC_NUMBER (R_68K_NONE, 0)		/* No reloc */
+  RELOC_NUMBER (R_68K_32, 1)		/* Direct 32 bit  */
+  RELOC_NUMBER (R_68K_16, 2)		/* Direct 16 bit  */
+  RELOC_NUMBER (R_68K_8, 3)		/* Direct 8 bit  */
+  RELOC_NUMBER (R_68K_PC32, 4)		/* PC relative 32 bit */
+  RELOC_NUMBER (R_68K_PC16, 5)		/* PC relative 16 bit */
+  RELOC_NUMBER (R_68K_PC8, 6)		/* PC relative 8 bit */
+  RELOC_NUMBER (R_68K_GOT32, 7)		/* 32 bit PC relative GOT entry */
+  RELOC_NUMBER (R_68K_GOT16, 8)		/* 16 bit PC relative GOT entry */
+  RELOC_NUMBER (R_68K_GOT8, 9)		/* 8 bit PC relative GOT entry */
+  RELOC_NUMBER (R_68K_GOT32O, 10)	/* 32 bit GOT offset */
+  RELOC_NUMBER (R_68K_GOT16O, 11)	/* 16 bit GOT offset */
+  RELOC_NUMBER (R_68K_GOT8O, 12)	/* 8 bit GOT offset */
+  RELOC_NUMBER (R_68K_PLT32, 13)	/* 32 bit PC relative PLT address */
+  RELOC_NUMBER (R_68K_PLT16, 14)	/* 16 bit PC relative PLT address */
+  RELOC_NUMBER (R_68K_PLT8, 15)		/* 8 bit PC relative PLT address */
+  RELOC_NUMBER (R_68K_PLT32O, 16)	/* 32 bit PLT offset */
+  RELOC_NUMBER (R_68K_PLT16O, 17)	/* 16 bit PLT offset */
+  RELOC_NUMBER (R_68K_PLT8O, 18)	/* 8 bit PLT offset */
+  RELOC_NUMBER (R_68K_COPY, 19)		/* Copy symbol at runtime */
+  RELOC_NUMBER (R_68K_GLOB_DAT, 20)	/* Create GOT entry */
+  RELOC_NUMBER (R_68K_JMP_SLOT, 21)	/* Create PLT entry */
+  RELOC_NUMBER (R_68K_RELATIVE, 22)	/* Adjust by program base */
+  /* These are GNU extensions to enable C++ vtable garbage collection.  */
+  RELOC_NUMBER (R_68K_GNU_VTINHERIT, 23)
+  RELOC_NUMBER (R_68K_GNU_VTENTRY, 24)
+  /* TLS static relocations.  */
+  RELOC_NUMBER (R_68K_TLS_GD32, 25)
+  RELOC_NUMBER (R_68K_TLS_GD16, 26)
+  RELOC_NUMBER (R_68K_TLS_GD8, 27)
+  RELOC_NUMBER (R_68K_TLS_LDM32, 28)
+  RELOC_NUMBER (R_68K_TLS_LDM16, 29)
+  RELOC_NUMBER (R_68K_TLS_LDM8, 30)
+  RELOC_NUMBER (R_68K_TLS_LDO32, 31)
+  RELOC_NUMBER (R_68K_TLS_LDO16, 32)
+  RELOC_NUMBER (R_68K_TLS_LDO8, 33)
+  RELOC_NUMBER (R_68K_TLS_IE32, 34)
+  RELOC_NUMBER (R_68K_TLS_IE16, 35)
+  RELOC_NUMBER (R_68K_TLS_IE8, 36)
+  RELOC_NUMBER (R_68K_TLS_LE32, 37)
+  RELOC_NUMBER (R_68K_TLS_LE16, 38)
+  RELOC_NUMBER (R_68K_TLS_LE8, 39)
+  RELOC_NUMBER (R_68K_TLS_DTPMOD32, 40)
+  RELOC_NUMBER (R_68K_TLS_DTPREL32, 41)
+  RELOC_NUMBER (R_68K_TLS_TPREL32, 42)
+END_RELOC_NUMBERS (R_68K_max)
+
+/* We use the top 24 bits to encode information about the
+   architecture variant.  */
+#define EF_M68K_CPU32    0x00810000
+#define EF_M68K_M68000   0x01000000
+#define EF_M68K_CFV4E    0x00008000
+#define EF_M68K_FIDO     0x02000000
+#define EF_M68K_ARCH_MASK						\
+  (EF_M68K_M68000 | EF_M68K_CPU32 | EF_M68K_CFV4E | EF_M68K_FIDO)
+
+/* We use the bottom 8 bits to encode information about the
+   coldfire variant.  If we use any of these bits, the top 24 bits are
+   either 0 or EF_M68K_CFV4E.  */
+#define EF_M68K_CF_ISA_MASK	0x0F  /* Which ISA */
+#define EF_M68K_CF_ISA_A_NODIV	0x01  /* ISA A except for div */
+#define EF_M68K_CF_ISA_A	0x02
+#define EF_M68K_CF_ISA_A_PLUS	0x03
+#define EF_M68K_CF_ISA_B_NOUSP	0x04  /* ISA_B except for USP */
+#define EF_M68K_CF_ISA_B	0x05
+#define EF_M68K_CF_ISA_C	0x06
+#define EF_M68K_CF_ISA_C_NODIV	0x07  /* ISA C except for div */
+#define EF_M68K_CF_MAC_MASK	0x30 
+#define EF_M68K_CF_MAC		0x10  /* MAC */
+#define EF_M68K_CF_EMAC		0x20  /* EMAC */
+#define EF_M68K_CF_EMAC_B	0x30  /* EMAC_B */
+#define EF_M68K_CF_FLOAT	0x40  /* Has float insns */
+#define EF_M68K_CF_MASK		0xFF
+     
+#endif
diff --git a/binutils-2.25/include/elf/mcore.h b/binutils-2.25/include/elf/mcore.h
new file mode 100644
index 00000000..2745feeb
--- /dev/null
+++ b/binutils-2.25/include/elf/mcore.h
@@ -0,0 +1,47 @@
+/* Motorola MCore support for BFD.
+   Copyright 1995, 1999, 2000, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file holds definitions specific to the MCore ELF ABI.  */
+#ifndef _ELF_MORE_H
+#define _ELF_MORE_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_mcore_reloc_type)
+  RELOC_NUMBER (R_MCORE_NONE, 0)
+  RELOC_NUMBER (R_MCORE_ADDR32, 1)
+  RELOC_NUMBER (R_MCORE_PCRELIMM8BY4, 2)
+  RELOC_NUMBER (R_MCORE_PCRELIMM11BY2, 3)
+  RELOC_NUMBER (R_MCORE_PCRELIMM4BY2, 4)
+  RELOC_NUMBER (R_MCORE_PCREL32, 5)
+  RELOC_NUMBER (R_MCORE_PCRELJSR_IMM11BY2, 6)
+  RELOC_NUMBER (R_MCORE_GNU_VTINHERIT, 7)
+  RELOC_NUMBER (R_MCORE_GNU_VTENTRY, 8)
+  RELOC_NUMBER (R_MCORE_RELATIVE, 9)
+  RELOC_NUMBER (R_MCORE_COPY, 10)
+  RELOC_NUMBER (R_MCORE_GLOB_DAT, 11)
+  RELOC_NUMBER (R_MCORE_JUMP_SLOT, 12)
+END_RELOC_NUMBERS (R_MCORE_max)
+
+/* Section Attributes.  */
+#define SHF_MCORE_NOREAD	0x80000000
+
+#endif /* _ELF_MCORE_H */
diff --git a/binutils-2.25/include/elf/mep.h b/binutils-2.25/include/elf/mep.h
new file mode 100644
index 00000000..b0e42adc
--- /dev/null
+++ b/binutils-2.25/include/elf/mep.h
@@ -0,0 +1,95 @@
+/* Toshiba MeP ELF support for BFD.
+   Copyright (C) 2001, 2004, 2005, 2007, 2009, 2010
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_MEP_H
+#define _ELF_MEP_H
+
+/* Bits in the sh_flags field of Elf32_Shdr:  */
+
+#define SHF_MEP_VLIW		0x10000000	/* contains vliw code */
+
+/* This bit is reserved by BFD for processor specific stuff.  Name
+   it properly so that we can easily stay consistent elsewhere.  */
+#define SEC_MEP_VLIW		SEC_TIC54X_BLOCK
+
+#include "elf/reloc-macros.h"
+
+/* Note: The comments in this file are used by bfd/mep-relocs.pl to
+   build parts of bfd/elf32-mep.c.  */
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_mep_reloc_type)
+
+  /* These two must appear first so that they are not processed by bfd/mep-relocs.pl.  */
+  RELOC_NUMBER (R_MEP_NONE, 0)
+  RELOC_NUMBER (R_RELC, 1)
+
+  RELOC_NUMBER (R_MEP_8, 2)		/* 7654 3210                               U */
+  RELOC_NUMBER (R_MEP_16, 3)		/* fedc ba98 7654 3210                     U */
+  RELOC_NUMBER (R_MEP_32, 4)		/* vuts rqpo nmlk jihg fedc ba98 7654 3210 U */
+
+  RELOC_NUMBER (R_MEP_PCREL8A2, 5)	/* ---- ---- 7654 321-                     S PC-REL */
+  RELOC_NUMBER (R_MEP_PCREL12A2, 6)	/* ---- ba98 7654 321-                     S PC-REL */
+  RELOC_NUMBER (R_MEP_PCREL17A2, 7)	/* ---- ---- ---- ---- gfed cba9 8765 4321 S PC-REL */
+  RELOC_NUMBER (R_MEP_PCREL24A2, 8)	/* ---- -765 4321 ---- nmlk jihg fedc ba98 S PC-REL */
+  RELOC_NUMBER (R_MEP_PCABS24A2, 9)	/* ---- -765 4321 ---- nmlk jihg fedc ba98 U */
+
+  RELOC_NUMBER (R_MEP_LOW16, 10)	/* ---- ---- ---- ---- fedc ba98 7654 3210 U no-overflow */
+  RELOC_NUMBER (R_MEP_HI16U, 11)	/* ---- ---- ---- ---- vuts rqpo nmlk jihg U no-overflow */
+  RELOC_NUMBER (R_MEP_HI16S, 12)	/* ---- ---- ---- ---- vuts rqpo nmlk jihg S no-overflow */
+  RELOC_NUMBER (R_MEP_GPREL, 13)	/* ---- ---- ---- ---- fedc ba98 7654 3210 S GP-REL*/
+  RELOC_NUMBER (R_MEP_TPREL, 14)	/* ---- ---- ---- ---- fedc ba98 7654 3210 S TP-REL*/
+
+  RELOC_NUMBER (R_MEP_TPREL7, 15)	/* ---- ---- -654 3210                     U TP-REL */
+  RELOC_NUMBER (R_MEP_TPREL7A2, 16)	/* ---- ---- -654 321-                     U TP-REL */
+  RELOC_NUMBER (R_MEP_TPREL7A4, 17)	/* ---- ---- -654 32--                     U TP-REL */
+
+  RELOC_NUMBER (R_MEP_UIMM24, 18)	/* ---- ---- 7654 3210 nmlk jihg fedc ba98 U */
+  RELOC_NUMBER (R_MEP_ADDR24A4, 19)	/* ---- ---- 7654 32-- nmlk jihg fedc ba98 U */
+
+  RELOC_NUMBER (R_MEP_GNU_VTINHERIT, 20) /* ---- ---- ---- ----                     U no-overflow */
+  RELOC_NUMBER (R_MEP_GNU_VTENTRY, 21)   /* ---- ---- ---- ----                     U no-overflow */
+
+END_RELOC_NUMBERS(R_MEP_max)
+
+#define	EF_MEP_CPU_MASK		0xff000000	/* specific cpu bits */
+#define EF_MEP_CPU_MEP          0x00000000	/* generic MEP */
+#define EF_MEP_CPU_C2   	0x01000000	/* MEP c2 */
+#define EF_MEP_CPU_C3   	0x02000000	/* MEP c3 */
+#define EF_MEP_CPU_C4   	0x04000000	/* MEP c4 */
+/* 5..7 are reseved */
+#define EF_MEP_CPU_C5   	0x08000000	/* MEP c5 */
+#define EF_MEP_CPU_H1   	0x10000000	/* MEP h1 */
+
+#define EF_MEP_COP_MASK		0x00ff0000
+#define EF_MEP_COP_NONE		0x00000000
+#define EF_MEP_COP_AVC		0x00010000
+#define EF_MEP_COP_AVC2		0x00020000
+#define EF_MEP_COP_FMAX		0x00030000
+/* 4..5 are reserved.  */
+#define EF_MEP_COP_IVC2		0x00060000
+
+#define EF_MEP_LIBRARY		0x00000100	/* Built as a library */
+
+#define EF_MEP_INDEX_MASK       0x000000ff      /* Configuration index */
+
+#define EF_MEP_ALL_FLAGS	0xffff01ff
+
+#endif /* _ELF_MEP_H */
diff --git a/binutils-2.25/include/elf/metag.h b/binutils-2.25/include/elf/metag.h
new file mode 100644
index 00000000..7ea699df
--- /dev/null
+++ b/binutils-2.25/include/elf/metag.h
@@ -0,0 +1,91 @@
+/* Meta ELF support for BFD.
+   Copyright (C) 2013 Free Software Foundation, Inc.
+   Contributed by Imagination Technologies Ltd.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_METAG_H
+#define _ELF_METAG_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocation types.  */
+
+START_RELOC_NUMBERS (elf_metag_reloc_type)
+     RELOC_NUMBER (R_METAG_HIADDR16,      0)
+     RELOC_NUMBER (R_METAG_LOADDR16,      1)
+     RELOC_NUMBER (R_METAG_ADDR32,        2)
+     RELOC_NUMBER (R_METAG_NONE,          3)
+     RELOC_NUMBER (R_METAG_RELBRANCH,     4)
+     RELOC_NUMBER (R_METAG_GETSETOFF,     5)
+
+     /* Backward compatability */
+     RELOC_NUMBER (R_METAG_REG32OP1,      6)
+     RELOC_NUMBER (R_METAG_REG32OP2,      7)
+     RELOC_NUMBER (R_METAG_REG32OP3,      8)
+     RELOC_NUMBER (R_METAG_REG16OP1,      9)
+     RELOC_NUMBER (R_METAG_REG16OP2,     10)
+     RELOC_NUMBER (R_METAG_REG16OP3,     11)
+     RELOC_NUMBER (R_METAG_REG32OP4,     12)
+
+     RELOC_NUMBER (R_METAG_HIOG,         13)
+     RELOC_NUMBER (R_METAG_LOOG,         14)
+
+     RELOC_NUMBER (R_METAG_REL8,         15)
+     RELOC_NUMBER (R_METAG_REL16,        16)
+
+     /* GNU */
+     RELOC_NUMBER (R_METAG_GNU_VTINHERIT,30)
+     RELOC_NUMBER (R_METAG_GNU_VTENTRY,  31)
+
+     /* PIC relocations */
+     RELOC_NUMBER (R_METAG_HI16_GOTOFF,  32)
+     RELOC_NUMBER (R_METAG_LO16_GOTOFF,  33)
+     RELOC_NUMBER (R_METAG_GETSET_GOTOFF,34)
+     RELOC_NUMBER (R_METAG_GETSET_GOT,   35)
+     RELOC_NUMBER (R_METAG_HI16_GOTPC,   36)
+     RELOC_NUMBER (R_METAG_LO16_GOTPC,   37)
+     RELOC_NUMBER (R_METAG_HI16_PLT,     38)
+     RELOC_NUMBER (R_METAG_LO16_PLT,     39)
+     RELOC_NUMBER (R_METAG_RELBRANCH_PLT,40)
+     RELOC_NUMBER (R_METAG_GOTOFF,       41)
+     RELOC_NUMBER (R_METAG_PLT,          42)
+     RELOC_NUMBER (R_METAG_COPY,         43)
+     RELOC_NUMBER (R_METAG_JMP_SLOT,     44)
+     RELOC_NUMBER (R_METAG_RELATIVE,     45)
+     RELOC_NUMBER (R_METAG_GLOB_DAT,     46)
+
+     /* TLS relocations */
+     RELOC_NUMBER (R_METAG_TLS_GD,       47)
+     RELOC_NUMBER (R_METAG_TLS_LDM,      48)
+     RELOC_NUMBER (R_METAG_TLS_LDO_HI16, 49)
+     RELOC_NUMBER (R_METAG_TLS_LDO_LO16, 50)
+     RELOC_NUMBER (R_METAG_TLS_LDO,      51)
+     RELOC_NUMBER (R_METAG_TLS_IE,       52)
+     RELOC_NUMBER (R_METAG_TLS_IENONPIC, 53)
+     RELOC_NUMBER (R_METAG_TLS_IENONPIC_HI16,54)
+     RELOC_NUMBER (R_METAG_TLS_IENONPIC_LO16,55)
+     RELOC_NUMBER (R_METAG_TLS_TPOFF,    56)
+     RELOC_NUMBER (R_METAG_TLS_DTPMOD,   57)
+     RELOC_NUMBER (R_METAG_TLS_DTPOFF,   58)
+     RELOC_NUMBER (R_METAG_TLS_LE,       59)
+     RELOC_NUMBER (R_METAG_TLS_LE_HI16,  60)
+     RELOC_NUMBER (R_METAG_TLS_LE_LO16,  61)
+
+END_RELOC_NUMBERS (R_METAG_MAX)
+
+#endif /* _ELF_METAG_H */
diff --git a/binutils-2.25/include/elf/microblaze.h b/binutils-2.25/include/elf/microblaze.h
new file mode 100644
index 00000000..c4d98213
--- /dev/null
+++ b/binutils-2.25/include/elf/microblaze.h
@@ -0,0 +1,71 @@
+/* Xilinx MicroBlaze support for BFD.
+ 
+   Copyright 2009, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 
+   02110-1301, USA.  */
+
+/* This file holds definitions specific to the MICROBLAZE ELF ABI.  */
+
+#ifndef _ELF_MICROBLAZE_H
+#define _ELF_MICROBLAZE_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+  RELOC_NUMBER (R_MICROBLAZE_NONE, 0)
+  RELOC_NUMBER (R_MICROBLAZE_32, 1)
+  RELOC_NUMBER (R_MICROBLAZE_32_PCREL, 2)
+  RELOC_NUMBER (R_MICROBLAZE_64_PCREL, 3)
+  RELOC_NUMBER (R_MICROBLAZE_32_PCREL_LO, 4)
+  RELOC_NUMBER (R_MICROBLAZE_64, 5)
+  RELOC_NUMBER (R_MICROBLAZE_32_LO, 6)
+  RELOC_NUMBER (R_MICROBLAZE_SRO32, 7)
+  RELOC_NUMBER (R_MICROBLAZE_SRW32, 8)
+  RELOC_NUMBER (R_MICROBLAZE_64_NONE, 9)
+  RELOC_NUMBER (R_MICROBLAZE_32_SYM_OP_SYM, 10)
+  RELOC_NUMBER (R_MICROBLAZE_GNU_VTINHERIT, 11)
+  RELOC_NUMBER (R_MICROBLAZE_GNU_VTENTRY, 12)
+  RELOC_NUMBER (R_MICROBLAZE_GOTPC_64, 13)  /* PC-relative GOT offset.  */
+  RELOC_NUMBER (R_MICROBLAZE_GOT_64, 14)    /* GOT entry offset.  */
+  RELOC_NUMBER (R_MICROBLAZE_PLT_64, 15)    /* PLT offset (PC-relative).  */
+  RELOC_NUMBER (R_MICROBLAZE_REL, 16)       /* Adjust by program base.  */
+  RELOC_NUMBER (R_MICROBLAZE_JUMP_SLOT, 17) /* Create PLT entry.  */
+  RELOC_NUMBER (R_MICROBLAZE_GLOB_DAT, 18)  /* Create GOT entry.  */
+  RELOC_NUMBER (R_MICROBLAZE_GOTOFF_64, 19) /* Offset relative to GOT.  */
+  RELOC_NUMBER (R_MICROBLAZE_GOTOFF_32, 20) /* Offset relative to GOT.  */
+  RELOC_NUMBER (R_MICROBLAZE_COPY, 21)      /* Runtime copy.  */
+  RELOC_NUMBER (R_MICROBLAZE_TLS, 22)           /* TLS Reloc */
+  RELOC_NUMBER (R_MICROBLAZE_TLSGD, 23)         /* TLS General Dynamic */
+  RELOC_NUMBER (R_MICROBLAZE_TLSLD, 24)         /* TLS Local Dynamic */
+  RELOC_NUMBER (R_MICROBLAZE_TLSDTPMOD32, 25)   /* TLS Module ID */
+  RELOC_NUMBER (R_MICROBLAZE_TLSDTPREL32, 26)   /* TLS Offset Within TLS Block */
+  RELOC_NUMBER (R_MICROBLAZE_TLSDTPREL64, 27)   /* TLS Offset Within TLS Block */
+  RELOC_NUMBER (R_MICROBLAZE_TLSGOTTPREL32, 28) /* TLS Offset From Thread Pointer */
+  RELOC_NUMBER (R_MICROBLAZE_TLSTPREL32, 29)    /* TLS Offset From Thread Pointer */
+   
+END_RELOC_NUMBERS (R_MICROBLAZE_max)
+
+/* Global base address names.  */
+#define RO_SDA_ANCHOR_NAME "_SDA2_BASE_"
+#define RW_SDA_ANCHOR_NAME "_SDA_BASE_"
+
+/* Section Attributes.  */
+#define SHF_MICROBLAZE_NOREAD	0x80000000
+
+#endif /* _ELF_MICROBLAZE_H */
diff --git a/binutils-2.25/include/elf/mips.h b/binutils-2.25/include/elf/mips.h
new file mode 100644
index 00000000..2c5a9a62
--- /dev/null
+++ b/binutils-2.25/include/elf/mips.h
@@ -0,0 +1,1172 @@
+/* MIPS ELF support for BFD.
+   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+   2003, 2004, 2005, 2008, 2009, 2010, 2013
+   Free Software Foundation, Inc.
+
+   By Ian Lance Taylor, Cygnus Support, <ian@cygnus.com>, from
+   information in the System V Application Binary Interface, MIPS
+   Processor Supplement.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file holds definitions specific to the MIPS ELF ABI.  Note
+   that most of this is not actually implemented by BFD.  */
+
+#ifndef _ELF_MIPS_H
+#define _ELF_MIPS_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocation types.  */
+START_RELOC_NUMBERS (elf_mips_reloc_type)
+  RELOC_NUMBER (R_MIPS_NONE, 0)
+  RELOC_NUMBER (R_MIPS_16, 1)
+  RELOC_NUMBER (R_MIPS_32, 2)		/* In Elf 64: alias R_MIPS_ADD */
+  RELOC_NUMBER (R_MIPS_REL32, 3)	/* In Elf 64: alias R_MIPS_REL */
+  RELOC_NUMBER (R_MIPS_26, 4)
+  RELOC_NUMBER (R_MIPS_HI16, 5)
+  RELOC_NUMBER (R_MIPS_LO16, 6)
+  RELOC_NUMBER (R_MIPS_GPREL16, 7)	/* In Elf 64: alias R_MIPS_GPREL */
+  RELOC_NUMBER (R_MIPS_LITERAL, 8)
+  RELOC_NUMBER (R_MIPS_GOT16, 9)	/* In Elf 64: alias R_MIPS_GOT */
+  RELOC_NUMBER (R_MIPS_PC16, 10)
+  RELOC_NUMBER (R_MIPS_CALL16, 11)	/* In Elf 64: alias R_MIPS_CALL */
+  RELOC_NUMBER (R_MIPS_GPREL32, 12)
+  /* The remaining relocs are defined on Irix, although they are not
+     in the MIPS ELF ABI.  */
+  RELOC_NUMBER (R_MIPS_UNUSED1, 13)
+  RELOC_NUMBER (R_MIPS_UNUSED2, 14)
+  RELOC_NUMBER (R_MIPS_UNUSED3, 15)
+  RELOC_NUMBER (R_MIPS_SHIFT5, 16)
+  RELOC_NUMBER (R_MIPS_SHIFT6, 17)
+  RELOC_NUMBER (R_MIPS_64, 18)
+  RELOC_NUMBER (R_MIPS_GOT_DISP, 19)
+  RELOC_NUMBER (R_MIPS_GOT_PAGE, 20)
+  RELOC_NUMBER (R_MIPS_GOT_OFST, 21)
+  RELOC_NUMBER (R_MIPS_GOT_HI16, 22)
+  RELOC_NUMBER (R_MIPS_GOT_LO16, 23)
+  RELOC_NUMBER (R_MIPS_SUB, 24)
+  RELOC_NUMBER (R_MIPS_INSERT_A, 25)
+  RELOC_NUMBER (R_MIPS_INSERT_B, 26)
+  RELOC_NUMBER (R_MIPS_DELETE, 27)
+  RELOC_NUMBER (R_MIPS_HIGHER, 28)
+  RELOC_NUMBER (R_MIPS_HIGHEST, 29)
+  RELOC_NUMBER (R_MIPS_CALL_HI16, 30)
+  RELOC_NUMBER (R_MIPS_CALL_LO16, 31)
+  RELOC_NUMBER (R_MIPS_SCN_DISP, 32)
+  RELOC_NUMBER (R_MIPS_REL16, 33)
+  RELOC_NUMBER (R_MIPS_ADD_IMMEDIATE, 34)
+  RELOC_NUMBER (R_MIPS_PJUMP, 35)
+  RELOC_NUMBER (R_MIPS_RELGOT, 36)
+  RELOC_NUMBER (R_MIPS_JALR, 37)
+  /* TLS relocations.  */
+  RELOC_NUMBER (R_MIPS_TLS_DTPMOD32, 38)
+  RELOC_NUMBER (R_MIPS_TLS_DTPREL32, 39)
+  RELOC_NUMBER (R_MIPS_TLS_DTPMOD64, 40)
+  RELOC_NUMBER (R_MIPS_TLS_DTPREL64, 41)
+  RELOC_NUMBER (R_MIPS_TLS_GD, 42)
+  RELOC_NUMBER (R_MIPS_TLS_LDM, 43)
+  RELOC_NUMBER (R_MIPS_TLS_DTPREL_HI16, 44)
+  RELOC_NUMBER (R_MIPS_TLS_DTPREL_LO16, 45)
+  RELOC_NUMBER (R_MIPS_TLS_GOTTPREL, 46)
+  RELOC_NUMBER (R_MIPS_TLS_TPREL32, 47)
+  RELOC_NUMBER (R_MIPS_TLS_TPREL64, 48)
+  RELOC_NUMBER (R_MIPS_TLS_TPREL_HI16, 49)
+  RELOC_NUMBER (R_MIPS_TLS_TPREL_LO16, 50)
+  RELOC_NUMBER (R_MIPS_GLOB_DAT, 51)
+  FAKE_RELOC (R_MIPS_max, 52)
+  /* These relocs are used for the mips16.  */
+  FAKE_RELOC (R_MIPS16_min, 100)
+  RELOC_NUMBER (R_MIPS16_26, 100)
+  RELOC_NUMBER (R_MIPS16_GPREL, 101)
+  RELOC_NUMBER (R_MIPS16_GOT16, 102)
+  RELOC_NUMBER (R_MIPS16_CALL16, 103)
+  RELOC_NUMBER (R_MIPS16_HI16, 104)
+  RELOC_NUMBER (R_MIPS16_LO16, 105)
+  RELOC_NUMBER (R_MIPS16_TLS_GD, 106)
+  RELOC_NUMBER (R_MIPS16_TLS_LDM, 107)
+  RELOC_NUMBER (R_MIPS16_TLS_DTPREL_HI16, 108)
+  RELOC_NUMBER (R_MIPS16_TLS_DTPREL_LO16, 109)
+  RELOC_NUMBER (R_MIPS16_TLS_GOTTPREL, 110)
+  RELOC_NUMBER (R_MIPS16_TLS_TPREL_HI16, 111)
+  RELOC_NUMBER (R_MIPS16_TLS_TPREL_LO16, 112)
+  FAKE_RELOC (R_MIPS16_max, 113)
+  /* These relocations are specific to VxWorks.  */
+  RELOC_NUMBER (R_MIPS_COPY, 126)
+  RELOC_NUMBER (R_MIPS_JUMP_SLOT, 127)
+
+  /* These relocations are specific to microMIPS.  */
+  FAKE_RELOC (R_MICROMIPS_min, 130)
+  RELOC_NUMBER (R_MICROMIPS_26_S1, 133)
+  RELOC_NUMBER (R_MICROMIPS_HI16, 134)
+  RELOC_NUMBER (R_MICROMIPS_LO16, 135)
+  RELOC_NUMBER (R_MICROMIPS_GPREL16, 136)	/* In Elf 64:
+						   alias R_MICROMIPS_GPREL */
+  RELOC_NUMBER (R_MICROMIPS_LITERAL, 137)
+  RELOC_NUMBER (R_MICROMIPS_GOT16, 138)		/* In Elf 64:
+						   alias R_MICROMIPS_GOT */
+  RELOC_NUMBER (R_MICROMIPS_PC7_S1, 139)
+  RELOC_NUMBER (R_MICROMIPS_PC10_S1, 140)
+  RELOC_NUMBER (R_MICROMIPS_PC16_S1, 141)
+  RELOC_NUMBER (R_MICROMIPS_CALL16, 142)	/* In Elf 64:
+						   alias R_MICROMIPS_CALL */
+  RELOC_NUMBER (R_MICROMIPS_GOT_DISP, 145)
+  RELOC_NUMBER (R_MICROMIPS_GOT_PAGE, 146)
+  RELOC_NUMBER (R_MICROMIPS_GOT_OFST, 147)
+  RELOC_NUMBER (R_MICROMIPS_GOT_HI16, 148)
+  RELOC_NUMBER (R_MICROMIPS_GOT_LO16, 149)
+  RELOC_NUMBER (R_MICROMIPS_SUB, 150)
+  RELOC_NUMBER (R_MICROMIPS_HIGHER, 151)
+  RELOC_NUMBER (R_MICROMIPS_HIGHEST, 152)
+  RELOC_NUMBER (R_MICROMIPS_CALL_HI16, 153)
+  RELOC_NUMBER (R_MICROMIPS_CALL_LO16, 154)
+  RELOC_NUMBER (R_MICROMIPS_SCN_DISP, 155)
+  RELOC_NUMBER (R_MICROMIPS_JALR, 156)
+  RELOC_NUMBER (R_MICROMIPS_HI0_LO16, 157)
+  /* TLS relocations.  */
+  RELOC_NUMBER (R_MICROMIPS_TLS_GD, 162)
+  RELOC_NUMBER (R_MICROMIPS_TLS_LDM, 163)
+  RELOC_NUMBER (R_MICROMIPS_TLS_DTPREL_HI16, 164)
+  RELOC_NUMBER (R_MICROMIPS_TLS_DTPREL_LO16, 165)
+  RELOC_NUMBER (R_MICROMIPS_TLS_GOTTPREL, 166)
+  RELOC_NUMBER (R_MICROMIPS_TLS_TPREL_HI16, 169)
+  RELOC_NUMBER (R_MICROMIPS_TLS_TPREL_LO16, 170)
+  /* microMIPS GP- and PC-relative relocations. */
+  RELOC_NUMBER (R_MICROMIPS_GPREL7_S2, 172)
+  RELOC_NUMBER (R_MICROMIPS_PC23_S2, 173)
+  FAKE_RELOC (R_MICROMIPS_max, 174)
+
+  /* This was a GNU extension used by embedded-PIC.  It was co-opted by
+     mips-linux for exception-handling data.  GCC stopped using it in
+     May, 2004, then started using it again for compact unwind tables.  */
+  RELOC_NUMBER (R_MIPS_PC32, 248)
+  RELOC_NUMBER (R_MIPS_EH, 249)
+  /* FIXME: this relocation is used internally by gas.  */
+  RELOC_NUMBER (R_MIPS_GNU_REL16_S2, 250)
+  /* These are GNU extensions to enable C++ vtable garbage collection.  */
+  RELOC_NUMBER (R_MIPS_GNU_VTINHERIT, 253)
+  RELOC_NUMBER (R_MIPS_GNU_VTENTRY, 254)
+END_RELOC_NUMBERS (R_MIPS_maxext)
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+/* At least one .noreorder directive appears in the source.  */
+#define EF_MIPS_NOREORDER	0x00000001
+
+/* File contains position independent code.  */
+#define EF_MIPS_PIC		0x00000002
+
+/* Code in file uses the standard calling sequence for calling
+   position independent code.  */
+#define EF_MIPS_CPIC		0x00000004
+
+/* ???  Unknown flag, set in IRIX 6's BSDdup2.o in libbsd.a.  */
+#define EF_MIPS_XGOT		0x00000008
+
+/* Code in file uses UCODE (obsolete) */
+#define EF_MIPS_UCODE		0x00000010
+
+/* Code in file uses new ABI (-n32 on Irix 6).  */
+#define EF_MIPS_ABI2		0x00000020
+
+/* Process the .MIPS.options section first by ld */
+#define EF_MIPS_OPTIONS_FIRST	0x00000080
+
+/* Indicates code compiled for a 64-bit machine in 32-bit mode
+   (regs are 32-bits wide).  */
+#define EF_MIPS_32BITMODE	0x00000100
+
+/* 32-bit machine but FP registers are 64 bit (-mfp64).  */
+#define EF_MIPS_FP64		0x00000200
+
+/* Code in file uses the IEEE 754-2008 NaN encoding convention.  */
+#define EF_MIPS_NAN2008		0x00000400
+
+/* Architectural Extensions used by this file */
+#define EF_MIPS_ARCH_ASE	0x0f000000
+
+/* Use MDMX multimedia extensions */
+#define EF_MIPS_ARCH_ASE_MDMX	0x08000000
+
+/* Use MIPS-16 ISA extensions */
+#define EF_MIPS_ARCH_ASE_M16	0x04000000
+
+/* Use MICROMIPS ISA extensions.  */
+#define EF_MIPS_ARCH_ASE_MICROMIPS	0x02000000
+
+/* Four bit MIPS architecture field.  */
+#define EF_MIPS_ARCH		0xf0000000
+
+/* -mips1 code.  */
+#define E_MIPS_ARCH_1		0x00000000
+
+/* -mips2 code.  */
+#define E_MIPS_ARCH_2		0x10000000
+
+/* -mips3 code.  */
+#define E_MIPS_ARCH_3		0x20000000
+
+/* -mips4 code.  */
+#define E_MIPS_ARCH_4		0x30000000
+
+/* -mips5 code.  */
+#define E_MIPS_ARCH_5           0x40000000
+
+/* -mips32 code.  */
+#define E_MIPS_ARCH_32          0x50000000
+
+/* -mips64 code.  */
+#define E_MIPS_ARCH_64          0x60000000
+
+/* -mips32r2 code.  */
+#define E_MIPS_ARCH_32R2        0x70000000
+
+/* -mips64r2 code.  */
+#define E_MIPS_ARCH_64R2        0x80000000
+
+/* The ABI of the file.  Also see EF_MIPS_ABI2 above. */
+#define EF_MIPS_ABI		0x0000F000
+
+/* The original o32 abi. */
+#define E_MIPS_ABI_O32          0x00001000
+
+/* O32 extended to work on 64 bit architectures */
+#define E_MIPS_ABI_O64          0x00002000
+
+/* EABI in 32 bit mode */
+#define E_MIPS_ABI_EABI32       0x00003000
+
+/* EABI in 64 bit mode */
+#define E_MIPS_ABI_EABI64       0x00004000
+
+
+/* Machine variant if we know it.  This field was invented at Cygnus,
+   but it is hoped that other vendors will adopt it.  If some standard
+   is developed, this code should be changed to follow it. */
+
+#define EF_MIPS_MACH		0x00FF0000
+
+/* Cygnus is choosing values between 80 and 9F;
+   00 - 7F should be left for a future standard;
+   the rest are open. */
+
+#define E_MIPS_MACH_3900	0x00810000
+#define E_MIPS_MACH_4010	0x00820000
+#define E_MIPS_MACH_4100	0x00830000
+#define E_MIPS_MACH_4650	0x00850000
+#define E_MIPS_MACH_4120	0x00870000
+#define E_MIPS_MACH_4111	0x00880000
+#define E_MIPS_MACH_SB1         0x008a0000
+#define E_MIPS_MACH_OCTEON	0x008b0000
+#define E_MIPS_MACH_XLR     	0x008c0000
+#define E_MIPS_MACH_OCTEON2	0x008d0000
+#define E_MIPS_MACH_5400	0x00910000
+#define E_MIPS_MACH_5900	0x00920000
+#define E_MIPS_MACH_5500	0x00980000
+#define E_MIPS_MACH_9000	0x00990000
+#define E_MIPS_MACH_LS2E        0x00A00000
+#define E_MIPS_MACH_LS2F        0x00A10000
+#define E_MIPS_MACH_LS3A        0x00A20000
+
+/* Processor specific section indices.  These sections do not actually
+   exist.  Symbols with a st_shndx field corresponding to one of these
+   values have a special meaning.  */
+
+/* Defined and allocated common symbol.  Value is virtual address.  If
+   relocated, alignment must be preserved.  */
+#define SHN_MIPS_ACOMMON	SHN_LORESERVE
+
+/* Defined and allocated text symbol.  Value is virtual address.
+   Occur in the dynamic symbol table of Alpha OSF/1 and Irix 5 executables.  */
+#define SHN_MIPS_TEXT		(SHN_LORESERVE + 1)
+
+/* Defined and allocated data symbol.  Value is virtual address.
+   Occur in the dynamic symbol table of Alpha OSF/1 and Irix 5 executables.  */
+#define SHN_MIPS_DATA		(SHN_LORESERVE + 2)
+
+/* Small common symbol.  */
+#define SHN_MIPS_SCOMMON	(SHN_LORESERVE + 3)
+
+/* Small undefined symbol.  */
+#define SHN_MIPS_SUNDEFINED	(SHN_LORESERVE + 4)
+
+/* Processor specific section types.  */
+
+/* Section contains the set of dynamic shared objects used when
+   statically linking.  */
+#define SHT_MIPS_LIBLIST	0x70000000
+
+/* I'm not sure what this is, but it's used on Irix 5.  */
+#define SHT_MIPS_MSYM		0x70000001
+
+/* Section contains list of symbols whose definitions conflict with
+   symbols defined in shared objects.  */
+#define SHT_MIPS_CONFLICT	0x70000002
+
+/* Section contains the global pointer table.  */
+#define SHT_MIPS_GPTAB		0x70000003
+
+/* Section contains microcode information.  The exact format is
+   unspecified.  */
+#define SHT_MIPS_UCODE		0x70000004
+
+/* Section contains some sort of debugging information.  The exact
+   format is unspecified.  It's probably ECOFF symbols.  */
+#define SHT_MIPS_DEBUG		0x70000005
+
+/* Section contains register usage information.  */
+#define SHT_MIPS_REGINFO	0x70000006
+
+/* ??? */
+#define SHT_MIPS_PACKAGE	0x70000007
+
+/* ??? */
+#define SHT_MIPS_PACKSYM	0x70000008
+
+/* ??? */
+#define SHT_MIPS_RELD		0x70000009
+
+/* Section contains interface information.  */
+#define SHT_MIPS_IFACE		0x7000000b
+
+/* Section contains description of contents of another section.  */
+#define SHT_MIPS_CONTENT	0x7000000c
+
+/* Section contains miscellaneous options.  */
+#define SHT_MIPS_OPTIONS	0x7000000d
+
+/* ??? */
+#define SHT_MIPS_SHDR		0x70000010
+
+/* ??? */
+#define SHT_MIPS_FDESC		0x70000011
+
+/* ??? */
+#define SHT_MIPS_EXTSYM		0x70000012
+
+/* ??? */
+#define SHT_MIPS_DENSE		0x70000013
+
+/* ??? */
+#define SHT_MIPS_PDESC		0x70000014
+
+/* ??? */
+#define SHT_MIPS_LOCSYM		0x70000015
+
+/* ??? */
+#define SHT_MIPS_AUXSYM		0x70000016
+
+/* ??? */
+#define SHT_MIPS_OPTSYM		0x70000017
+
+/* ??? */
+#define SHT_MIPS_LOCSTR		0x70000018
+
+/* ??? */
+#define SHT_MIPS_LINE		0x70000019
+
+/* ??? */
+#define SHT_MIPS_RFDESC		0x7000001a
+
+/* Delta C++: symbol table */
+#define SHT_MIPS_DELTASYM	0x7000001b
+
+/* Delta C++: instance table */
+#define SHT_MIPS_DELTAINST	0x7000001c
+
+/* Delta C++: class table */
+#define SHT_MIPS_DELTACLASS	0x7000001d
+
+/* DWARF debugging section.  */
+#define SHT_MIPS_DWARF		0x7000001e
+
+/* Delta C++: declarations */
+#define SHT_MIPS_DELTADECL	0x7000001f
+
+/* List of libraries the binary depends on.  Includes a time stamp, version
+   number.  */
+#define SHT_MIPS_SYMBOL_LIB	0x70000020
+
+/* Events section.  */
+#define SHT_MIPS_EVENTS		0x70000021
+
+/* ??? */
+#define SHT_MIPS_TRANSLATE	0x70000022
+
+/* Special pixie sections */
+#define SHT_MIPS_PIXIE		0x70000023
+
+/* Address translation table (for debug info) */
+#define SHT_MIPS_XLATE		0x70000024
+
+/* SGI internal address translation table (for debug info) */
+#define SHT_MIPS_XLATE_DEBUG	0x70000025
+
+/* Intermediate code */
+#define SHT_MIPS_WHIRL		0x70000026
+
+/* C++ exception handling region info */
+#define SHT_MIPS_EH_REGION	0x70000027
+
+/* Obsolete address translation table (for debug info) */
+#define SHT_MIPS_XLATE_OLD	0x70000028
+
+/* Runtime procedure descriptor table exception information (ucode) ??? */
+#define SHT_MIPS_PDR_EXCEPTION	0x70000029
+
+
+/* A section of type SHT_MIPS_LIBLIST contains an array of the
+   following structure.  The sh_link field is the section index of the
+   string table.  The sh_info field is the number of entries in the
+   section.  */
+typedef struct
+{
+  /* String table index for name of shared object.  */
+  unsigned long l_name;
+  /* Time stamp.  */
+  unsigned long l_time_stamp;
+  /* Checksum of symbol names and common sizes.  */
+  unsigned long l_checksum;
+  /* String table index for version.  */
+  unsigned long l_version;
+  /* Flags.  */
+  unsigned long l_flags;
+} Elf32_Lib;
+
+/* The external version of Elf32_Lib.  */
+typedef struct
+{
+  unsigned char l_name[4];
+  unsigned char l_time_stamp[4];
+  unsigned char l_checksum[4];
+  unsigned char l_version[4];
+  unsigned char l_flags[4];
+} Elf32_External_Lib;
+
+/* The l_flags field of an Elf32_Lib structure may contain the
+   following flags.  */
+
+/* Require an exact match at runtime.  */
+#define LL_EXACT_MATCH		0x00000001
+
+/* Ignore version incompatibilities at runtime.  */
+#define LL_IGNORE_INT_VER	0x00000002
+
+/* Require matching minor version number.  */
+#define LL_REQUIRE_MINOR	0x00000004
+
+/* ??? */
+#define LL_EXPORTS		0x00000008
+
+/* Delay loading of this library until really needed.  */
+#define LL_DELAY_LOAD		0x00000010
+
+/* ??? Delta C++ stuff ??? */
+#define LL_DELTA		0x00000020
+
+
+/* A section of type SHT_MIPS_CONFLICT is an array of indices into the
+   .dynsym section.  Each element has the following type.  */
+typedef unsigned long Elf32_Conflict;
+typedef unsigned char Elf32_External_Conflict[4];
+
+typedef unsigned long Elf64_Conflict;
+typedef unsigned char Elf64_External_Conflict[8];
+
+/* A section of type SHT_MIPS_GPTAB contains information about how
+   much GP space would be required for different -G arguments.  This
+   information is only used so that the linker can provide informative
+   suggestions as to the best -G value to use.  The sh_info field is
+   the index of the section for which this information applies.  The
+   contents of the section are an array of the following union.  The
+   first element uses the gt_header field.  The remaining elements use
+   the gt_entry field.  */
+typedef union
+{
+  struct
+    {
+      /* -G value actually used for this object file.  */
+      unsigned long gt_current_g_value;
+      /* Unused.  */
+      unsigned long gt_unused;
+    } gt_header;
+  struct
+    {
+      /* If this -G argument has been used...  */
+      unsigned long gt_g_value;
+      /* ...this many GP section bytes would be required.  */
+      unsigned long gt_bytes;
+    } gt_entry;
+} Elf32_gptab;
+
+/* The external version of Elf32_gptab.  */
+
+typedef union
+{
+  struct
+    {
+      unsigned char gt_current_g_value[4];
+      unsigned char gt_unused[4];
+    } gt_header;
+  struct
+    {
+      unsigned char gt_g_value[4];
+      unsigned char gt_bytes[4];
+    } gt_entry;
+} Elf32_External_gptab;
+
+/* A section of type SHT_MIPS_REGINFO contains the following
+   structure.  */
+typedef struct
+{
+  /* Mask of general purpose registers used.  */
+  unsigned long ri_gprmask;
+  /* Mask of co-processor registers used.  */
+  unsigned long ri_cprmask[4];
+  /* GP register value for this object file.  */
+  long ri_gp_value;
+} Elf32_RegInfo;
+
+/* The external version of the Elf_RegInfo structure.  */
+typedef struct
+{
+  unsigned char ri_gprmask[4];
+  unsigned char ri_cprmask[4][4];
+  unsigned char ri_gp_value[4];
+} Elf32_External_RegInfo;
+
+/* MIPS ELF .reginfo swapping routines.  */
+extern void bfd_mips_elf32_swap_reginfo_in
+  (bfd *, const Elf32_External_RegInfo *, Elf32_RegInfo *);
+extern void bfd_mips_elf32_swap_reginfo_out
+  (bfd *, const Elf32_RegInfo *, Elf32_External_RegInfo *);
+
+/* Processor specific section flags.  */
+
+/* This section must be in the global data area.  */
+#define SHF_MIPS_GPREL		0x10000000
+
+/* This section should be merged.  */
+#define SHF_MIPS_MERGE		0x20000000
+
+/* This section contains address data of size implied by section
+   element size.  */
+#define SHF_MIPS_ADDR		0x40000000
+
+/* This section contains string data.  */
+#define SHF_MIPS_STRING		0x80000000
+
+/* This section may not be stripped.  */
+#define SHF_MIPS_NOSTRIP	0x08000000
+
+/* This section is local to threads.  */
+#define SHF_MIPS_LOCAL		0x04000000
+
+/* Linker should generate implicit weak names for this section.  */
+#define SHF_MIPS_NAMES		0x02000000
+
+/* Section contais text/data which may be replicated in other sections.
+   Linker should retain only one copy.  */
+#define SHF_MIPS_NODUPES	0x01000000
+
+/* Processor specific program header types.  */
+
+/* Register usage information.  Identifies one .reginfo section.  */
+#define PT_MIPS_REGINFO		0x70000000
+
+/* Runtime procedure table.  */
+#define PT_MIPS_RTPROC		0x70000001
+
+/* .MIPS.options section.  */
+#define PT_MIPS_OPTIONS		0x70000002
+
+/* Processor specific dynamic array tags.  */
+
+/* 32 bit version number for runtime linker interface.  */
+#define DT_MIPS_RLD_VERSION	0x70000001
+
+/* Time stamp.  */
+#define DT_MIPS_TIME_STAMP	0x70000002
+
+/* Checksum of external strings and common sizes.  */
+#define DT_MIPS_ICHECKSUM	0x70000003
+
+/* Index of version string in string table.  */
+#define DT_MIPS_IVERSION	0x70000004
+
+/* 32 bits of flags.  */
+#define DT_MIPS_FLAGS		0x70000005
+
+/* Base address of the segment.  */
+#define DT_MIPS_BASE_ADDRESS	0x70000006
+
+/* ??? */
+#define DT_MIPS_MSYM		0x70000007
+
+/* Address of .conflict section.  */
+#define DT_MIPS_CONFLICT	0x70000008
+
+/* Address of .liblist section.  */
+#define DT_MIPS_LIBLIST		0x70000009
+
+/* Number of local global offset table entries.  */
+#define DT_MIPS_LOCAL_GOTNO	0x7000000a
+
+/* Number of entries in the .conflict section.  */
+#define DT_MIPS_CONFLICTNO	0x7000000b
+
+/* Number of entries in the .liblist section.  */
+#define DT_MIPS_LIBLISTNO	0x70000010
+
+/* Number of entries in the .dynsym section.  */
+#define DT_MIPS_SYMTABNO	0x70000011
+
+/* Index of first external dynamic symbol not referenced locally.  */
+#define DT_MIPS_UNREFEXTNO	0x70000012
+
+/* Index of first dynamic symbol in global offset table.  */
+#define DT_MIPS_GOTSYM		0x70000013
+
+/* Number of page table entries in global offset table.  */
+#define DT_MIPS_HIPAGENO	0x70000014
+
+/* Address of run time loader map, used for debugging.  */
+#define DT_MIPS_RLD_MAP		0x70000016
+
+/* Delta C++ class definition.  */
+#define DT_MIPS_DELTA_CLASS	0x70000017
+
+/* Number of entries in DT_MIPS_DELTA_CLASS.  */
+#define DT_MIPS_DELTA_CLASS_NO	0x70000018
+
+/* Delta C++ class instances.  */
+#define DT_MIPS_DELTA_INSTANCE	0x70000019
+
+/* Number of entries in DT_MIPS_DELTA_INSTANCE.  */
+#define DT_MIPS_DELTA_INSTANCE_NO	0x7000001a
+
+/* Delta relocations.  */
+#define DT_MIPS_DELTA_RELOC	0x7000001b
+
+/* Number of entries in DT_MIPS_DELTA_RELOC.  */
+#define DT_MIPS_DELTA_RELOC_NO	0x7000001c
+
+/* Delta symbols that Delta relocations refer to.  */
+#define DT_MIPS_DELTA_SYM	0x7000001d
+
+/* Number of entries in DT_MIPS_DELTA_SYM.  */
+#define DT_MIPS_DELTA_SYM_NO	0x7000001e
+
+/* Delta symbols that hold class declarations.  */
+#define DT_MIPS_DELTA_CLASSSYM	0x70000020
+
+/* Number of entries in DT_MIPS_DELTA_CLASSSYM.  */
+#define DT_MIPS_DELTA_CLASSSYM_NO	0x70000021
+
+/* Flags indicating information about C++ flavor.  */
+#define DT_MIPS_CXX_FLAGS	0x70000022
+
+/* Pixie information (???).  */
+#define DT_MIPS_PIXIE_INIT	0x70000023
+
+/* Address of .MIPS.symlib */
+#define DT_MIPS_SYMBOL_LIB	0x70000024
+
+/* The GOT index of the first PTE for a segment */
+#define DT_MIPS_LOCALPAGE_GOTIDX	0x70000025
+
+/* The GOT index of the first PTE for a local symbol */
+#define DT_MIPS_LOCAL_GOTIDX	0x70000026
+
+/* The GOT index of the first PTE for a hidden symbol */
+#define DT_MIPS_HIDDEN_GOTIDX	0x70000027
+
+/* The GOT index of the first PTE for a protected symbol */
+#define DT_MIPS_PROTECTED_GOTIDX	0x70000028
+
+/* Address of `.MIPS.options'.  */
+#define DT_MIPS_OPTIONS		0x70000029
+
+/* Address of `.interface'.  */
+#define DT_MIPS_INTERFACE	0x7000002a
+
+/* ??? */
+#define DT_MIPS_DYNSTR_ALIGN	0x7000002b
+
+/* Size of the .interface section.  */
+#define DT_MIPS_INTERFACE_SIZE	0x7000002c
+
+/* Size of rld_text_resolve function stored in the GOT.  */
+#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR	0x7000002d
+
+/* Default suffix of DSO to be added by rld on dlopen() calls.  */
+#define DT_MIPS_PERF_SUFFIX	0x7000002e
+
+/* Size of compact relocation section (O32).  */
+#define DT_MIPS_COMPACT_SIZE	0x7000002f
+
+/* GP value for auxiliary GOTs.  */
+#define DT_MIPS_GP_VALUE	0x70000030
+
+/* Address of auxiliary .dynamic.  */
+#define DT_MIPS_AUX_DYNAMIC	0x70000031
+
+/* Address of the base of the PLTGOT.  */
+#define DT_MIPS_PLTGOT         0x70000032
+
+/* Points to the base of a writable PLT.  */
+#define DT_MIPS_RWPLT          0x70000034
+
+/* Flags which may appear in a DT_MIPS_FLAGS entry.  */
+
+/* No flags.  */
+#define RHF_NONE		0x00000000
+
+/* Uses shortcut pointers.  */
+#define RHF_QUICKSTART		0x00000001
+
+/* Hash size is not a power of two.  */
+#define RHF_NOTPOT		0x00000002
+
+/* Ignore LD_LIBRARY_PATH.  */
+#define RHS_NO_LIBRARY_REPLACEMENT 0x00000004
+
+/* DSO address may not be relocated. */
+#define RHF_NO_MOVE		0x00000008
+
+/* SGI specific features. */
+#define RHF_SGI_ONLY		0x00000010
+
+/* Guarantee that .init will finish executing before any non-init
+   code in DSO is called. */
+#define RHF_GUARANTEE_INIT	   0x00000020
+
+/* Contains Delta C++ code. */
+#define RHF_DELTA_C_PLUS_PLUS	   0x00000040
+
+/* Guarantee that .init will start executing before any non-init
+   code in DSO is called. */
+#define RHF_GUARANTEE_START_INIT   0x00000080
+
+/* Generated by pixie. */
+#define RHF_PIXIE		   0x00000100
+
+/* Delay-load DSO by default. */
+#define RHF_DEFAULT_DELAY_LOAD	   0x00000200
+
+/* Object may be requickstarted */
+#define RHF_REQUICKSTART	   0x00000400
+
+/* Object has been requickstarted */
+#define RHF_REQUICKSTARTED	   0x00000800
+
+/* Generated by cord. */
+#define RHF_CORD		   0x00001000
+
+/* Object contains no unresolved undef symbols. */
+#define RHF_NO_UNRES_UNDEF	   0x00002000
+
+/* Symbol table is in a safe order. */
+#define RHF_RLD_ORDER_SAFE	   0x00004000
+
+/* Special values for the st_other field in the symbol table.  These
+   are used in an Irix 5 dynamic symbol table.  */
+
+#define STO_DEFAULT		STV_DEFAULT
+#define STO_INTERNAL		STV_INTERNAL
+#define STO_HIDDEN		STV_HIDDEN
+#define STO_PROTECTED		STV_PROTECTED
+
+/* Two topmost bits denote the MIPS ISA for .text symbols:
+   + 00 -- standard MIPS code,
+   + 10 -- microMIPS code,
+   + 11 -- MIPS16 code; requires the following two bits to be set too.
+   Note that one of the MIPS16 bits overlaps with STO_MIPS_PIC.  See below
+   for details.  */
+#define STO_MIPS_ISA		(3 << 6)
+
+/* The mask spanning the rest of MIPS psABI flags.  At most one is expected
+   to be set except for STO_MIPS16.  */
+#define STO_MIPS_FLAGS		(~(STO_MIPS_ISA | ELF_ST_VISIBILITY (-1)))
+
+/* The MIPS psABI was updated in 2008 with support for PLTs and copy
+   relocs.  There are therefore two types of nonzero SHN_UNDEF functions:
+   PLT entries and traditional MIPS lazy binding stubs.  We mark the former
+   with STO_MIPS_PLT to distinguish them from the latter.  */
+#define STO_MIPS_PLT		0x8
+#define ELF_ST_IS_MIPS_PLT(other)					\
+  ((ELF_ST_IS_MIPS16 (other)						\
+    ? ((other) & (~STO_MIPS16 & STO_MIPS_FLAGS))			\
+    : ((other) & STO_MIPS_FLAGS)) == STO_MIPS_PLT)
+#define ELF_ST_SET_MIPS_PLT(other)					\
+  ((ELF_ST_IS_MIPS16 (other)						\
+    ? ((other) & (STO_MIPS16 | ~STO_MIPS_FLAGS))			\
+    : ((other) & ~STO_MIPS_FLAGS)) | STO_MIPS_PLT)
+
+/* This value is used to mark PIC functions in an object that mixes
+   PIC and non-PIC.  Note that this bit overlaps with STO_MIPS16,
+   although MIPS16 symbols are never considered to be MIPS_PIC.  */
+#define STO_MIPS_PIC		0x20
+#define ELF_ST_IS_MIPS_PIC(other) (((other) & STO_MIPS_FLAGS) == STO_MIPS_PIC)
+#define ELF_ST_SET_MIPS_PIC(other)					\
+  ((ELF_ST_IS_MIPS16 (other)						\
+    ? ((other) & ~(STO_MIPS16 | STO_MIPS_FLAGS))			\
+    : ((other) & ~STO_MIPS_FLAGS)) | STO_MIPS_PIC)
+
+/* This value is used for a mips16 .text symbol.  */
+#define STO_MIPS16		0xf0
+#define ELF_ST_IS_MIPS16(other) (((other) & STO_MIPS16) == STO_MIPS16)
+#define ELF_ST_SET_MIPS16(other) ((other) | STO_MIPS16)
+
+/* This value is used for a microMIPS .text symbol.  To distinguish from
+   STO_MIPS16, we set top two bits to be 10 to denote STO_MICROMIPS.  The
+   mask is STO_MIPS_ISA.  */
+#define STO_MICROMIPS		(2 << 6)
+#define ELF_ST_IS_MICROMIPS(other) (((other) & STO_MIPS_ISA) == STO_MICROMIPS)
+#define ELF_ST_SET_MICROMIPS(other) (((other) & ~STO_MIPS_ISA) | STO_MICROMIPS)
+
+/* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
+   has been indicated for a .text symbol.  */
+#define ELF_ST_IS_COMPRESSED(other) \
+  (ELF_ST_IS_MIPS16 (other) || ELF_ST_IS_MICROMIPS (other))
+
+/* This bit is used on Irix to indicate a symbol whose definition
+   is optional - if, at final link time, it cannot be found, no
+   error message should be produced.  */
+#define STO_OPTIONAL		(1 << 2)
+/* A macro to examine the STO_OPTIONAL bit.  */
+#define ELF_MIPS_IS_OPTIONAL(other)	((other) & STO_OPTIONAL)
+
+/* The 64-bit MIPS ELF ABI uses an unusual reloc format.  Each
+   relocation entry specifies up to three actual relocations, all at
+   the same address.  The first relocation which required a symbol
+   uses the symbol in the r_sym field.  The second relocation which
+   requires a symbol uses the symbol in the r_ssym field.  If all
+   three relocations require a symbol, the third one uses a zero
+   value.  */
+
+/* An entry in a 64 bit SHT_REL section.  */
+
+typedef struct
+{
+  /* Address of relocation.  */
+  unsigned char r_offset[8];
+  /* Symbol index.  */
+  unsigned char r_sym[4];
+  /* Special symbol.  */
+  unsigned char r_ssym[1];
+  /* Third relocation.  */
+  unsigned char r_type3[1];
+  /* Second relocation.  */
+  unsigned char r_type2[1];
+  /* First relocation.  */
+  unsigned char r_type[1];
+} Elf64_Mips_External_Rel;
+
+typedef struct
+{
+  /* Address of relocation.  */
+  bfd_vma r_offset;
+  /* Symbol index.  */
+  unsigned long r_sym;
+  /* Special symbol.  */
+  unsigned char r_ssym;
+  /* Third relocation.  */
+  unsigned char r_type3;
+  /* Second relocation.  */
+  unsigned char r_type2;
+  /* First relocation.  */
+  unsigned char r_type;
+} Elf64_Mips_Internal_Rel;
+
+/* An entry in a 64 bit SHT_RELA section.  */
+
+typedef struct
+{
+  /* Address of relocation.  */
+  unsigned char r_offset[8];
+  /* Symbol index.  */
+  unsigned char r_sym[4];
+  /* Special symbol.  */
+  unsigned char r_ssym[1];
+  /* Third relocation.  */
+  unsigned char r_type3[1];
+  /* Second relocation.  */
+  unsigned char r_type2[1];
+  /* First relocation.  */
+  unsigned char r_type[1];
+  /* Addend.  */
+  unsigned char r_addend[8];
+} Elf64_Mips_External_Rela;
+
+typedef struct
+{
+  /* Address of relocation.  */
+  bfd_vma r_offset;
+  /* Symbol index.  */
+  unsigned long r_sym;
+  /* Special symbol.  */
+  unsigned char r_ssym;
+  /* Third relocation.  */
+  unsigned char r_type3;
+  /* Second relocation.  */
+  unsigned char r_type2;
+  /* First relocation.  */
+  unsigned char r_type;
+  /* Addend.  */
+  bfd_signed_vma r_addend;
+} Elf64_Mips_Internal_Rela;
+
+/* MIPS ELF 64 relocation info access macros.  */
+#define ELF64_MIPS_R_SSYM(i) (((i) >> 24) & 0xff)
+#define ELF64_MIPS_R_TYPE3(i) (((i) >> 16) & 0xff)
+#define ELF64_MIPS_R_TYPE2(i) (((i) >> 8) & 0xff)
+#define ELF64_MIPS_R_TYPE(i) ((i) & 0xff)
+
+/* Values found in the r_ssym field of a relocation entry.  */
+
+/* No relocation.  */
+#define RSS_UNDEF	0
+
+/* Value of GP.  */
+#define RSS_GP		1
+
+/* Value of GP in object being relocated.  */
+#define RSS_GP0		2
+
+/* Address of location being relocated.  */
+#define RSS_LOC		3
+
+/* A SHT_MIPS_OPTIONS section contains a series of options, each of
+   which starts with this header.  */
+
+typedef struct
+{
+  /* Type of option.  */
+  unsigned char kind[1];
+  /* Size of option descriptor, including header.  */
+  unsigned char size[1];
+  /* Section index of affected section, or 0 for global option.  */
+  unsigned char section[2];
+  /* Information specific to this kind of option.  */
+  unsigned char info[4];
+} Elf_External_Options;
+
+typedef struct
+{
+  /* Type of option.  */
+  unsigned char kind;
+  /* Size of option descriptor, including header.  */
+  unsigned char size;
+  /* Section index of affected section, or 0 for global option.  */
+  unsigned short section;
+  /* Information specific to this kind of option.  */
+  unsigned long info;
+} Elf_Internal_Options;
+
+/* MIPS ELF option header swapping routines.  */
+extern void bfd_mips_elf_swap_options_in
+  (bfd *, const Elf_External_Options *, Elf_Internal_Options *);
+extern void bfd_mips_elf_swap_options_out
+  (bfd *, const Elf_Internal_Options *, Elf_External_Options *);
+
+/* Values which may appear in the kind field of an Elf_Options
+   structure.  */
+
+/* Undefined.  */
+#define ODK_NULL	0
+
+/* Register usage and GP value.  */
+#define ODK_REGINFO	1
+
+/* Exception processing information.  */
+#define ODK_EXCEPTIONS	2
+
+/* Section padding information.  */
+#define ODK_PAD		3
+
+/* Hardware workarounds performed.  */
+#define ODK_HWPATCH	4
+
+/* Fill value used by the linker.  */
+#define ODK_FILL	5
+
+/* Reserved space for desktop tools.  */
+#define ODK_TAGS	6
+
+/* Hardware workarounds, AND bits when merging.  */
+#define ODK_HWAND	7
+
+/* Hardware workarounds, OR bits when merging.  */
+#define ODK_HWOR	8
+
+/* GP group to use for text/data sections.  */
+#define ODK_GP_GROUP	9
+
+/* ID information.  */
+#define ODK_IDENT	10
+
+/* In the 32 bit ABI, an ODK_REGINFO option is just a Elf32_RegInfo
+   structure.  In the 64 bit ABI, it is the following structure.  The
+   info field of the options header is not used.  */
+
+typedef struct
+{
+  /* Mask of general purpose registers used.  */
+  unsigned char ri_gprmask[4];
+  /* Padding.  */
+  unsigned char ri_pad[4];
+  /* Mask of co-processor registers used.  */
+  unsigned char ri_cprmask[4][4];
+  /* GP register value for this object file.  */
+  unsigned char ri_gp_value[8];
+} Elf64_External_RegInfo;
+
+typedef struct
+{
+  /* Mask of general purpose registers used.  */
+  unsigned long ri_gprmask;
+  /* Padding.  */
+  unsigned long ri_pad;
+  /* Mask of co-processor registers used.  */
+  unsigned long ri_cprmask[4];
+  /* GP register value for this object file.  */
+  bfd_vma ri_gp_value;
+} Elf64_Internal_RegInfo;
+
+typedef struct
+{
+  /* The hash value computed from the name of the corresponding
+     dynamic symbol.  */
+  unsigned char ms_hash_value[4];
+  /* Contains both the dynamic relocation index and the symbol flags
+     field.  The macros ELF32_MS_REL_INDEX and ELF32_MS_FLAGS are used
+     to access the individual values.  The dynamic relocation index
+     identifies the first entry in the .rel.dyn section that
+     references the dynamic symbol corresponding to this msym entry.
+     If the index is 0, no dynamic relocations are associated with the
+     symbol.  The symbol flags field is reserved for future use.  */
+  unsigned char ms_info[4];
+} Elf32_External_Msym;
+
+typedef struct
+{
+  /* The hash value computed from the name of the corresponding
+     dynamic symbol.  */
+  unsigned long ms_hash_value;
+  /* Contains both the dynamic relocation index and the symbol flags
+     field.  The macros ELF32_MS_REL_INDEX and ELF32_MS_FLAGS are used
+     to access the individual values.  The dynamic relocation index
+     identifies the first entry in the .rel.dyn section that
+     references the dynamic symbol corresponding to this msym entry.
+     If the index is 0, no dynamic relocations are associated with the
+     symbol.  The symbol flags field is reserved for future use.  */
+  unsigned long ms_info;
+} Elf32_Internal_Msym;
+
+#define ELF32_MS_REL_INDEX(i) ((i) >> 8)
+#define ELF32_MS_FLAGS(i)     (i) & 0xff)
+#define ELF32_MS_INFO(r, f)   (((r) << 8) + ((f) & 0xff))
+
+/* MIPS ELF reginfo swapping routines.  */
+extern void bfd_mips_elf64_swap_reginfo_in
+  (bfd *, const Elf64_External_RegInfo *, Elf64_Internal_RegInfo *);
+extern void bfd_mips_elf64_swap_reginfo_out
+  (bfd *, const Elf64_Internal_RegInfo *, Elf64_External_RegInfo *);
+
+/* Masks for the info work of an ODK_EXCEPTIONS descriptor.  */
+#define OEX_FPU_MIN	0x1f	/* FPEs which must be enabled.  */
+#define OEX_FPU_MAX	0x1f00	/* FPEs which may be enabled.  */
+#define OEX_PAGE0	0x10000	/* Page zero must be mapped.  */
+#define OEX_SMM		0x20000	/* Force sequential memory mode.  */
+#define OEX_FPDBUG	0x40000	/* Force precise floating-point
+				   exceptions (debug mode).  */
+#define OEX_DISMISS	0x80000	/* Dismiss invalid address faults.  */
+
+/* Masks of the FP exceptions for OEX_FPU_MIN and OEX_FPU_MAX.  */
+#define OEX_FPU_INVAL	0x10	/* Invalid operation exception.  */
+#define OEX_FPU_DIV0	0x08	/* Division by zero exception.  */
+#define OEX_FPU_OFLO	0x04	/* Overflow exception.  */
+#define OEX_FPU_UFLO	0x02	/* Underflow exception.  */
+#define OEX_FPU_INEX	0x01	/* Inexact exception.  */
+
+/* Masks for the info word of an ODK_PAD descriptor.  */
+#define OPAD_PREFIX	0x01
+#define OPAD_POSTFIX	0x02
+#define OPAD_SYMBOL	0x04
+
+/* Masks for the info word of an ODK_HWPATCH descriptor.  */
+#define OHW_R4KEOP	0x00000001	/* R4000 end-of-page patch.  */
+#define OHW_R8KPFETCH	0x00000002	/* May need R8000 prefetch patch.  */
+#define OHW_R5KEOP	0x00000004	/* R5000 end-of-page patch.  */
+#define OHW_R5KCVTL	0x00000008	/* R5000 cvt.[ds].l bug
+					   (clean == 1).  */
+#define OHW_R10KLDL	0x00000010	/* Needs R10K misaligned
+					   load patch. */
+
+/* Masks for the info word of an ODK_IDENT/ODK_GP_GROUP descriptor.  */
+#define OGP_GROUP	0x0000ffff	/* GP group number.  */
+#define OGP_SELF	0xffff0000	/* Self-contained GP groups.  */
+
+/* Masks for the info word of an ODK_HWAND/ODK_HWOR descriptor.  */
+#define OHWA0_R4KEOP_CHECKED	0x00000001
+#define OHWA0_R4KEOP_CLEAN	0x00000002
+
+
+/* Object attribute tags.  */
+enum
+{
+  /* 0-3 are generic.  */
+
+  /* Floating-point ABI used by this object file.  */
+  Tag_GNU_MIPS_ABI_FP = 4,
+
+  /* MSA ABI used by this object file.  */
+  Tag_GNU_MIPS_ABI_MSA = 8,
+};
+
+/* Object attribute values.  */
+enum
+{
+  /* Values defined for Tag_GNU_MIPS_ABI_FP.  */
+
+  /* Not tagged or not using any ABIs affected by the differences.  */
+  Val_GNU_MIPS_ABI_FP_ANY = 0,
+
+  /* Using hard-float -mdouble-float.  */
+  Val_GNU_MIPS_ABI_FP_DOUBLE = 1,
+
+  /* Using hard-float -msingle-float.  */
+  Val_GNU_MIPS_ABI_FP_SINGLE = 2,
+
+  /* Using soft-float.  */
+  Val_GNU_MIPS_ABI_FP_SOFT = 3,
+
+  /* Using -mips32r2 -mfp64.  */
+  Val_GNU_MIPS_ABI_FP_64 = 4,
+
+  /* Values defined for Tag_GNU_MIPS_ABI_MSA.  */
+
+  /* Not tagged or not using any ABIs affected by the differences.  */
+  Val_GNU_MIPS_ABI_MSA_ANY = 0,
+
+  /* Using 128-bit MSA.  */
+  Val_GNU_MIPS_ABI_MSA_128 = 1,
+};
+
+#endif /* _ELF_MIPS_H */
diff --git a/binutils-2.25/include/elf/mmix.h b/binutils-2.25/include/elf/mmix.h
new file mode 100644
index 00000000..6d15f7ae
--- /dev/null
+++ b/binutils-2.25/include/elf/mmix.h
@@ -0,0 +1,173 @@
+/* MMIX support for BFD.
+   Copyright 2001, 2002, 2003, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file holds definitions specific to the MMIX ELF ABI.  */
+
+#ifndef ELF_MMIX_H
+#define ELF_MMIX_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  See the reloc table in bfd/elf64-mmix.c for details.  */
+START_RELOC_NUMBERS (elf_mmix_reloc_type)
+  RELOC_NUMBER (R_MMIX_NONE, 0)
+
+  /* Standard absolute relocations.  */
+  RELOC_NUMBER (R_MMIX_8, 1)
+  RELOC_NUMBER (R_MMIX_16, 2)
+  RELOC_NUMBER (R_MMIX_24, 3)
+  RELOC_NUMBER (R_MMIX_32, 4)
+  RELOC_NUMBER (R_MMIX_64, 5)
+
+  /* Standard relative relocations.  */
+  RELOC_NUMBER (R_MMIX_PC_8, 6)
+  RELOC_NUMBER (R_MMIX_PC_16, 7)
+  RELOC_NUMBER (R_MMIX_PC_24, 8)
+  RELOC_NUMBER (R_MMIX_PC_32, 9)
+  RELOC_NUMBER (R_MMIX_PC_64, 10)
+
+  /* GNU extensions for C++ vtables.  */
+  RELOC_NUMBER (R_MMIX_GNU_VTINHERIT, 11)
+  RELOC_NUMBER (R_MMIX_GNU_VTENTRY, 12)
+
+  /* A GETA instruction.  */
+  RELOC_NUMBER (R_MMIX_GETA, 13)
+  RELOC_NUMBER (R_MMIX_GETA_1, 14)
+  RELOC_NUMBER (R_MMIX_GETA_2, 15)
+  RELOC_NUMBER (R_MMIX_GETA_3, 16)
+
+  /* A conditional branch instruction.  */
+  RELOC_NUMBER (R_MMIX_CBRANCH, 17)
+  RELOC_NUMBER (R_MMIX_CBRANCH_J, 18)
+  RELOC_NUMBER (R_MMIX_CBRANCH_1, 19)
+  RELOC_NUMBER (R_MMIX_CBRANCH_2, 20)
+  RELOC_NUMBER (R_MMIX_CBRANCH_3, 21)
+
+  /* A PUSHJ instruction.  */
+  RELOC_NUMBER (R_MMIX_PUSHJ, 22)
+  RELOC_NUMBER (R_MMIX_PUSHJ_1, 23)
+  RELOC_NUMBER (R_MMIX_PUSHJ_2, 24)
+  RELOC_NUMBER (R_MMIX_PUSHJ_3, 25)
+
+  /* A JMP instruction.  */
+  RELOC_NUMBER (R_MMIX_JMP, 26)
+  RELOC_NUMBER (R_MMIX_JMP_1, 27)
+  RELOC_NUMBER (R_MMIX_JMP_2, 28)
+  RELOC_NUMBER (R_MMIX_JMP_3, 29)
+
+  /* A relative address such as in a GETA or a branch.  */
+  RELOC_NUMBER (R_MMIX_ADDR19, 30)
+
+  /* A relative address such as in a JMP (only).  */
+  RELOC_NUMBER (R_MMIX_ADDR27, 31)
+
+  /* A general register or a number 0..255.  */
+  RELOC_NUMBER (R_MMIX_REG_OR_BYTE, 32)
+
+  /* A general register. */
+  RELOC_NUMBER (R_MMIX_REG, 33)
+
+  /* A global register and an offset, the global register (allocated at
+     link time) contents plus the offset made equivalent to the relocation
+     expression at link time.  The relocation must point at the Y field of
+     an instruction.  */
+  RELOC_NUMBER (R_MMIX_BASE_PLUS_OFFSET, 34)
+
+  /* A LOCAL assertion.  */
+  RELOC_NUMBER (R_MMIX_LOCAL, 35)
+
+  /* A PUSHJ instruction, generating a stub if it does not reach.  */
+  RELOC_NUMBER (R_MMIX_PUSHJ_STUBBABLE, 36)
+END_RELOC_NUMBERS (R_MMIX_max)
+
+
+/* Section Attributes.  */
+/* A section containing necessary information for relaxation.  */
+#define SHF_MMIX_CANRELAX	0x80000000
+
+/* Symbol attributes.  */
+/* A symbol with this section-index is a register.  */
+#define SHN_REGISTER	SHN_LOPROC
+
+/* This section holds contents for each initialized register, at VMA
+   regno*8.  A symbol relative to this section will be transformed to an
+   absolute symbol with the value corresponding to the register number at
+   final link time.  A symbol with a value outside the inclusive range
+   32*8 .. 254*8 is an error.  It is highly recommended to only use an
+   upper bound of 253*8 or lower as specified in the (currently
+   unspecified) ABI.  */
+#define MMIX_REG_CONTENTS_SECTION_NAME ".MMIX.reg_contents"
+
+/* At link time, a section by this name is created, expected to be
+   included in MMIX_REG_CONTENTS_SECTION_NAME in the output.  */
+#define MMIX_LD_ALLOCATED_REG_CONTENTS_SECTION_NAME \
+ ".MMIX.reg_contents.linker_allocated"
+
+/* This is a faked section holding symbols with SHN_REGISTER.  Don't
+   confuse it with MMIX_REG_CONTENTS_SECTION_NAME; this one has no
+   contents, just values.  It is an error for a value in this section to
+   be outside the range 32..255 and it must never become an actual section
+   in an object file.  */
+#define MMIX_REG_SECTION_NAME "*REG*"
+
+/* Appended with a number N=0..65535, this is a representation of the
+   mmixal "BSPEC N" ... "ESPEC" directive pair; the contents go into an
+   ELF section by name ".MMIX.spec_data.N".  */
+#define MMIX_OTHER_SPEC_SECTION_PREFIX ".MMIX.spec_data."
+
+/* A section SECNAME is noted to start at "__.MMIX.start.SECNAME" by the
+   presence of this symbol.  Currently only implemented for ".text"
+   through the symbol "__.MMIX.start..text".  */
+#define MMIX_LOC_SECTION_START_SYMBOL_PREFIX "__.MMIX.start."
+
+/* This symbol is always a function.  */
+#define MMIX_START_SYMBOL_NAME "Main"
+
+
+/* We smuggle in a few MMO specifics here.  We don't make a specific MMO
+   file, since we can't reasonably support MMO without ELF; we have to
+   include this file anyway.  */
+
+#define MMO_TEXT_SECTION_NAME ".text"
+#define MMO_DATA_SECTION_NAME ".data"
+
+/* A definition for the flags we put in spec data in files.  A copy of our
+   own of some flags to keep immune to BFD flag changes.  See section.c of
+   2001-07-18 for flag documentation.  */
+#define MMO_SEC_ALLOC      0x001
+#define MMO_SEC_LOAD       0x002
+#define MMO_SEC_RELOC      0x004
+#define MMO_SEC_READONLY   0x010
+#define MMO_SEC_CODE       0x020
+#define MMO_SEC_DATA       0x040
+#define MMO_SEC_NEVER_LOAD 0x400
+#define MMO_SEC_IS_COMMON 0x8000
+#define MMO_SEC_DEBUGGING 0x10000
+
+#ifdef BFD_ARCH_SIZE
+extern bfd_boolean _bfd_mmix_before_linker_allocation
+  (bfd *, struct bfd_link_info *);
+extern bfd_boolean _bfd_mmix_after_linker_allocation
+  (bfd *, struct bfd_link_info *);
+extern bfd_boolean _bfd_mmix_check_all_relocs
+  (bfd *, struct bfd_link_info *);
+#endif
+
+#endif /* ELF_MMIX_H */
diff --git a/binutils-2.25/include/elf/mn10200.h b/binutils-2.25/include/elf/mn10200.h
new file mode 100644
index 00000000..24972b68
--- /dev/null
+++ b/binutils-2.25/include/elf/mn10200.h
@@ -0,0 +1,40 @@
+/* MN10200 ELF support for BFD.
+   Copyright 1998, 2000, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file holds definitions specific to the MN10200 ELF ABI.  */
+
+#ifndef _ELF_MN10200_H
+#define _ELF_MN10200_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_mn10200_reloc_type)
+  RELOC_NUMBER (R_MN10200_NONE, 0)
+  RELOC_NUMBER (R_MN10200_32, 1)
+  RELOC_NUMBER (R_MN10200_16, 2)
+  RELOC_NUMBER (R_MN10200_8, 3)
+  RELOC_NUMBER (R_MN10200_24, 4)
+  RELOC_NUMBER (R_MN10200_PCREL8, 5)
+  RELOC_NUMBER (R_MN10200_PCREL16, 6)
+  RELOC_NUMBER (R_MN10200_PCREL24, 7)
+END_RELOC_NUMBERS (R_MN10200_max)
+
+#endif /* _ELF_MN10200_H */
diff --git a/binutils-2.25/include/elf/mn10300.h b/binutils-2.25/include/elf/mn10300.h
new file mode 100644
index 00000000..529b3897
--- /dev/null
+++ b/binutils-2.25/include/elf/mn10300.h
@@ -0,0 +1,80 @@
+/* MN10300 ELF support for BFD.
+   Copyright 1998, 1999, 2000, 2003, 2007 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file holds definitions specific to the MN10300 ELF ABI.  */
+
+#ifndef _ELF_MN10300_H
+#define _ELF_MN10300_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_mn10300_reloc_type)
+  RELOC_NUMBER (R_MN10300_NONE, 0)
+  RELOC_NUMBER (R_MN10300_32, 1)
+  RELOC_NUMBER (R_MN10300_16, 2)
+  RELOC_NUMBER (R_MN10300_8, 3)
+  RELOC_NUMBER (R_MN10300_PCREL32, 4)
+  RELOC_NUMBER (R_MN10300_PCREL16, 5)
+  RELOC_NUMBER (R_MN10300_PCREL8, 6)
+  RELOC_NUMBER (R_MN10300_GNU_VTINHERIT, 7)
+  RELOC_NUMBER (R_MN10300_GNU_VTENTRY, 8)
+  RELOC_NUMBER (R_MN10300_24, 9)
+  RELOC_NUMBER (R_MN10300_GOTPC32, 10)
+  RELOC_NUMBER (R_MN10300_GOTPC16, 11)
+  RELOC_NUMBER (R_MN10300_GOTOFF32, 12)
+  RELOC_NUMBER (R_MN10300_GOTOFF24, 13)
+  RELOC_NUMBER (R_MN10300_GOTOFF16, 14)
+  RELOC_NUMBER (R_MN10300_PLT32, 15)
+  RELOC_NUMBER (R_MN10300_PLT16, 16)
+  RELOC_NUMBER (R_MN10300_GOT32, 17)
+  RELOC_NUMBER (R_MN10300_GOT24, 18)
+  RELOC_NUMBER (R_MN10300_GOT16, 19)
+  RELOC_NUMBER (R_MN10300_COPY, 20)
+  RELOC_NUMBER (R_MN10300_GLOB_DAT, 21)
+  RELOC_NUMBER (R_MN10300_JMP_SLOT, 22)
+  RELOC_NUMBER (R_MN10300_RELATIVE, 23)
+  RELOC_NUMBER (R_MN10300_TLS_GD, 24)
+  RELOC_NUMBER (R_MN10300_TLS_LD, 25)
+  RELOC_NUMBER (R_MN10300_TLS_LDO, 26)
+  RELOC_NUMBER (R_MN10300_TLS_GOTIE, 27)
+  RELOC_NUMBER (R_MN10300_TLS_IE, 28)
+  RELOC_NUMBER (R_MN10300_TLS_LE, 29)
+  RELOC_NUMBER (R_MN10300_TLS_DTPMOD, 30)
+  RELOC_NUMBER (R_MN10300_TLS_DTPOFF, 31)
+  RELOC_NUMBER (R_MN10300_TLS_TPOFF, 32)
+  RELOC_NUMBER (R_MN10300_SYM_DIFF, 33)
+  RELOC_NUMBER (R_MN10300_ALIGN, 34)
+END_RELOC_NUMBERS (R_MN10300_MAX)
+
+/* Machine variant if we know it.  This field was invented at Cygnus,
+   but it is hoped that other vendors will adopt it.  If some standard
+   is developed, this code should be changed to follow it.  */
+
+#define EF_MN10300_MACH		0x00FF0000
+
+/* Cygnus is choosing values between 80 and 9F;
+   00 - 7F should be left for a future standard;
+   the rest are open.  */
+
+#define E_MN10300_MACH_MN10300	0x00810000
+#define E_MN10300_MACH_AM33	0x00820000
+#define E_MN10300_MACH_AM33_2   0x00830000
+#endif /* _ELF_MN10300_H */
diff --git a/binutils-2.25/include/elf/moxie.h b/binutils-2.25/include/elf/moxie.h
new file mode 100644
index 00000000..0b3eb381
--- /dev/null
+++ b/binutils-2.25/include/elf/moxie.h
@@ -0,0 +1,32 @@
+/* moxie ELF support for BFD.
+   Copyright 2009, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_MOXIE_H
+#define _ELF_MOXIE_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocation types.  */
+START_RELOC_NUMBERS (elf_moxie_reloc_type)
+  RELOC_NUMBER (R_MOXIE_NONE, 0)
+  RELOC_NUMBER (R_MOXIE_32, 1)
+  RELOC_NUMBER (R_MOXIE_PCREL10, 2)
+END_RELOC_NUMBERS (R_MOXIE_max)
+
+#endif /* _ELF_MOXIE_H */
diff --git a/binutils-2.25/include/elf/msp430.h b/binutils-2.25/include/elf/msp430.h
new file mode 100644
index 00000000..ac8e28c3
--- /dev/null
+++ b/binutils-2.25/include/elf/msp430.h
@@ -0,0 +1,101 @@
+/* MSP430 ELF support for BFD.
+   Copyright (C) 2002-2013 Free Software Foundation, Inc.
+   Contributed by Dmitry Diky <diwil@mail.ru>
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_MSP430_H
+#define _ELF_MSP430_H
+
+#include "elf/reloc-macros.h"
+
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_MSP430_MACH 		0xff
+
+#define E_MSP430_MACH_MSP430x11  11
+#define E_MSP430_MACH_MSP430x11x1  110
+#define E_MSP430_MACH_MSP430x12  12
+#define E_MSP430_MACH_MSP430x13  13
+#define E_MSP430_MACH_MSP430x14  14
+#define E_MSP430_MACH_MSP430x15  15
+#define E_MSP430_MACH_MSP430x16  16
+#define E_MSP430_MACH_MSP430x20  20
+#define E_MSP430_MACH_MSP430x22  22
+#define E_MSP430_MACH_MSP430x23  23
+#define E_MSP430_MACH_MSP430x24  24
+#define E_MSP430_MACH_MSP430x26  26
+#define E_MSP430_MACH_MSP430x31  31
+#define E_MSP430_MACH_MSP430x32  32
+#define E_MSP430_MACH_MSP430x33  33
+#define E_MSP430_MACH_MSP430x41  41
+#define E_MSP430_MACH_MSP430x42  42
+#define E_MSP430_MACH_MSP430x43  43
+#define E_MSP430_MACH_MSP430x44  44
+#define E_MSP430_MACH_MSP430X    45
+#define E_MSP430_MACH_MSP430x46  46
+#define E_MSP430_MACH_MSP430x47  47
+#define E_MSP430_MACH_MSP430x54  54
+
+#define SHT_MSP430_ATTRIBUTES	0x70000003	/* Section holds ABI attributes.  */
+#define SHT_MSP430_SEC_FLAGS	0x7f000005	/* Holds TI compiler's section flags.  */
+#define SHT_MSP430_SYM_ALIASES	0x7f000006	/* Holds TI compiler's symbol aliases.  */
+
+/* Tag values for an attribute section.  */
+#define OFBA_MSPABI_Tag_ISA		4
+#define OFBA_MSPABI_Tag_Code_Model	6
+#define OFBA_MSPABI_Tag_Data_Model	8
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_msp430_reloc_type)
+     RELOC_NUMBER (R_MSP430_NONE,		0)
+     RELOC_NUMBER (R_MSP430_32,			1)
+     RELOC_NUMBER (R_MSP430_10_PCREL,		2)
+     RELOC_NUMBER (R_MSP430_16, 		3)
+     RELOC_NUMBER (R_MSP430_16_PCREL, 		4)
+     RELOC_NUMBER (R_MSP430_16_BYTE, 		5)
+     RELOC_NUMBER (R_MSP430_16_PCREL_BYTE, 	6)
+     RELOC_NUMBER (R_MSP430_2X_PCREL,		7)
+     RELOC_NUMBER (R_MSP430_RL_PCREL,		8)
+     RELOC_NUMBER (R_MSP430_8,			9)
+     RELOC_NUMBER (R_MSP430_SYM_DIFF,		10)
+END_RELOC_NUMBERS (R_MSP430_max)
+
+START_RELOC_NUMBERS (elf_msp430x_reloc_type)
+     RELOC_NUMBER (R_MSP430_ABS32, 1)		/* aka R_MSP430_32 */
+     RELOC_NUMBER (R_MSP430_ABS16, 2)		/* aka R_MSP430_16 */
+     RELOC_NUMBER (R_MSP430_ABS8, 3)
+     RELOC_NUMBER (R_MSP430_PCR16, 4)		/* aka R_MSP430_16_PCREL */
+     RELOC_NUMBER (R_MSP430X_PCR20_EXT_SRC, 5)
+     RELOC_NUMBER (R_MSP430X_PCR20_EXT_DST, 6)
+     RELOC_NUMBER (R_MSP430X_PCR20_EXT_ODST, 7)
+     RELOC_NUMBER (R_MSP430X_ABS20_EXT_SRC, 8)
+     RELOC_NUMBER (R_MSP430X_ABS20_EXT_DST, 9)
+     RELOC_NUMBER (R_MSP430X_ABS20_EXT_ODST, 10)
+     RELOC_NUMBER (R_MSP430X_ABS20_ADR_SRC, 11)
+     RELOC_NUMBER (R_MSP430X_ABS20_ADR_DST, 12)
+     RELOC_NUMBER (R_MSP430X_PCR16, 13)		/* Like R_MSP430_PCR16 but with overflow checking.  */
+     RELOC_NUMBER (R_MSP430X_PCR20_CALL, 14)
+     RELOC_NUMBER (R_MSP430X_ABS16, 15)		/* Like R_MSP430_ABS16 but with overflow checking.  */
+     RELOC_NUMBER (R_MSP430_ABS_HI16, 16)
+     RELOC_NUMBER (R_MSP430_PREL31, 17)
+     RELOC_NUMBER (R_MSP430_EHTYPE, 18)		/* Mentioned in ABI.  */
+     RELOC_NUMBER (R_MSP430X_10_PCREL, 19)	/* Red Hat invention.  Used for Jump instructions.  */
+     RELOC_NUMBER (R_MSP430X_2X_PCREL, 20)	/* Red Hat invention.  Used for relaxing jumps.  */
+     RELOC_NUMBER (R_MSP430X_SYM_DIFF, 21)	/* Red Hat invention.  Used for relaxing debug info.  */
+END_RELOC_NUMBERS (R_MSP430x_max)
+
+#endif /* _ELF_MSP430_H */
diff --git a/binutils-2.25/include/elf/mt.h b/binutils-2.25/include/elf/mt.h
new file mode 100644
index 00000000..2bc09f42
--- /dev/null
+++ b/binutils-2.25/include/elf/mt.h
@@ -0,0 +1,46 @@
+/* MS1  ELF support for BFD.
+   Copyright (C) 2000, 2005, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_MT_H
+#define _ELF_MT_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_mt_reloc_type)
+  RELOC_NUMBER (R_MT_NONE, 0)
+  RELOC_NUMBER (R_MT_16, 1)
+  RELOC_NUMBER (R_MT_32, 2)
+  RELOC_NUMBER (R_MT_32_PCREL, 3)
+  RELOC_NUMBER (R_MT_PC16, 4)
+  RELOC_NUMBER (R_MT_HI16, 5)
+  RELOC_NUMBER (R_MT_LO16, 6)
+END_RELOC_NUMBERS(R_MT_max)
+
+#define EF_MT_CPU_MRISC		0x00000001	/* default */
+#define EF_MT_CPU_MRISC2	0x00000002	/* MRISC2 */
+#define EF_MT_CPU_MS2		0x00000003      /* MS2 */
+#define EF_MT_CPU_MASK		0x00000003	/* specific cpu bits */
+#define EF_MT_ALL_FLAGS		(EF_MT_CPU_MASK)
+
+/* The location of the memory mapped hardware stack.  */
+#define MT_STACK_VALUE 0x0f000000
+#define MT_STACK_SIZE  0x20
+
+#endif /* _ELF_MT_H */
diff --git a/binutils-2.25/include/elf/nios2.h b/binutils-2.25/include/elf/nios2.h
new file mode 100644
index 00000000..ff5947bf
--- /dev/null
+++ b/binutils-2.25/include/elf/nios2.h
@@ -0,0 +1,91 @@
+/* Altera Nios II ELF support for BFD.
+   Copyright (C) 2012, 2013 Free Software Foundation, Inc.
+   Contributed by Nigel Gray (ngray@altera.com).
+   Contributed by Mentor Graphics, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+
+/* This file holds definitions specific to the Altera Nios II ELF ABI.  Note
+   that most of this is not actually implemented by BFD.  */
+
+#ifndef _ELF_NIOS2_H
+#define _ELF_NIOS2_H
+
+#include "elf/reloc-macros.h"
+
+/* The order of these numbers must match the order in
+   the elf_nios2_howto_table_rel table for the lookup
+   function to work properly.  */
+
+START_RELOC_NUMBERS (elf_nios2_reloc_type)
+  RELOC_NUMBER (R_NIOS2_NONE,	  0)
+  RELOC_NUMBER (R_NIOS2_S16,	  1)
+  RELOC_NUMBER (R_NIOS2_U16,	  2)
+  RELOC_NUMBER (R_NIOS2_PCREL16, 3)
+  RELOC_NUMBER (R_NIOS2_CALL26,  4)
+  RELOC_NUMBER (R_NIOS2_IMM5,	  5)
+  RELOC_NUMBER (R_NIOS2_CACHE_OPX, 6)
+  RELOC_NUMBER (R_NIOS2_IMM6,	  7)
+  RELOC_NUMBER (R_NIOS2_IMM8,	  8)
+  RELOC_NUMBER (R_NIOS2_HI16,	  9)
+  RELOC_NUMBER (R_NIOS2_LO16,	  10)
+  RELOC_NUMBER (R_NIOS2_HIADJ16, 11)
+  RELOC_NUMBER (R_NIOS2_BFD_RELOC_32, 12)
+  RELOC_NUMBER (R_NIOS2_BFD_RELOC_16, 13)
+  RELOC_NUMBER (R_NIOS2_BFD_RELOC_8, 14)
+  RELOC_NUMBER (R_NIOS2_GPREL, 15)
+  RELOC_NUMBER (R_NIOS2_GNU_VTINHERIT, 16)
+  RELOC_NUMBER (R_NIOS2_GNU_VTENTRY, 17)
+  RELOC_NUMBER (R_NIOS2_UJMP, 18)
+  RELOC_NUMBER (R_NIOS2_CJMP, 19)
+  RELOC_NUMBER (R_NIOS2_CALLR, 20)
+  RELOC_NUMBER (R_NIOS2_ALIGN, 21)
+  RELOC_NUMBER (R_NIOS2_GOT16, 22)
+  RELOC_NUMBER (R_NIOS2_CALL16, 23)
+  RELOC_NUMBER (R_NIOS2_GOTOFF_LO, 24)
+  RELOC_NUMBER (R_NIOS2_GOTOFF_HA, 25)
+  RELOC_NUMBER (R_NIOS2_PCREL_LO, 26)
+  RELOC_NUMBER (R_NIOS2_PCREL_HA, 27)
+  RELOC_NUMBER (R_NIOS2_TLS_GD16, 28)
+  RELOC_NUMBER (R_NIOS2_TLS_LDM16, 29)
+  RELOC_NUMBER (R_NIOS2_TLS_LDO16, 30)
+  RELOC_NUMBER (R_NIOS2_TLS_IE16, 31)
+  RELOC_NUMBER (R_NIOS2_TLS_LE16, 32)
+  RELOC_NUMBER (R_NIOS2_TLS_DTPMOD, 33)
+  RELOC_NUMBER (R_NIOS2_TLS_DTPREL, 34)
+  RELOC_NUMBER (R_NIOS2_TLS_TPREL, 35)
+  RELOC_NUMBER (R_NIOS2_COPY, 36)
+  RELOC_NUMBER (R_NIOS2_GLOB_DAT, 37)
+  RELOC_NUMBER (R_NIOS2_JUMP_SLOT, 38)
+  RELOC_NUMBER (R_NIOS2_RELATIVE, 39)
+  RELOC_NUMBER (R_NIOS2_GOTOFF, 40)
+  RELOC_NUMBER (R_NIOS2_ILLEGAL, 41)
+END_RELOC_NUMBERS (R_NIOS2_maxext)
+
+/* Processor-specific section flags.  */
+
+/* This is used to mark gp-relative sections.  */
+#define SHF_NIOS2_GPREL	0x10000000
+
+/* Processor-specific dynamic array tags.  */
+
+/* Address of _gp.  */
+#define DT_NIOS2_GP 0x70000002
+
+#endif /* _ELF_NIOS2_H */
diff --git a/binutils-2.25/include/elf/openrisc.h b/binutils-2.25/include/elf/openrisc.h
new file mode 100644
index 00000000..87969e8b
--- /dev/null
+++ b/binutils-2.25/include/elf/openrisc.h
@@ -0,0 +1,39 @@
+/* OpenRISC ELF support for BFD.
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_OPENRISC_H
+#define _ELF_OPENRISC_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_openrisc_reloc_type)
+  RELOC_NUMBER (R_OPENRISC_NONE, 0)
+  RELOC_NUMBER (R_OPENRISC_INSN_REL_26, 1)
+  RELOC_NUMBER (R_OPENRISC_INSN_ABS_26, 2)
+  RELOC_NUMBER (R_OPENRISC_LO_16_IN_INSN, 3)
+  RELOC_NUMBER (R_OPENRISC_HI_16_IN_INSN, 4)
+  RELOC_NUMBER (R_OPENRISC_8, 5)
+  RELOC_NUMBER (R_OPENRISC_16, 6)
+  RELOC_NUMBER (R_OPENRISC_32, 7)
+  RELOC_NUMBER (R_OPENRISC_GNU_VTINHERIT, 8)
+  RELOC_NUMBER (R_OPENRISC_GNU_VTENTRY, 9)
+END_RELOC_NUMBERS (R_OPENRISC_max)
+
+#endif /* _ELF_OPENRISC_H */
diff --git a/binutils-2.25/include/elf/or32.h b/binutils-2.25/include/elf/or32.h
new file mode 100644
index 00000000..9f1c2f3f
--- /dev/null
+++ b/binutils-2.25/include/elf/or32.h
@@ -0,0 +1,56 @@
+/* OR1K ELF support for BFD. Derived from ppc.h.
+   Copyright (C) 2002, 2010 Free Software Foundation, Inc.
+   Contributed by Ivan Guzvinec  <ivang@opencores.org>
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _ELF_OR1K_H
+#define _ELF_OR1K_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_or32_reloc_type)
+  RELOC_NUMBER (R_OR32_NONE, 0)
+  RELOC_NUMBER (R_OR32_32, 1)
+  RELOC_NUMBER (R_OR32_16, 2)
+  RELOC_NUMBER (R_OR32_8, 3)
+  RELOC_NUMBER (R_OR32_CONST, 4)
+  RELOC_NUMBER (R_OR32_CONSTH, 5)
+  RELOC_NUMBER (R_OR32_JUMPTARG, 6)
+  RELOC_NUMBER (R_OR32_GNU_VTENTRY, 7)
+  RELOC_NUMBER (R_OR32_GNU_VTINHERIT, 8)
+END_RELOC_NUMBERS (R_OR32_max)
+
+/* Four bit OR32 machine type field.  */
+#define EF_OR32_MACH             0x0000000f
+
+/* Various CPU types.  */
+#define E_OR32_MACH_BASE         0x00000000
+#define E_OR32_MACH_UNUSED1      0x00000001
+#define E_OR32_MACH_UNUSED2      0x00000002
+#define E_OR32_MACH_UNUSED4      0x00000003
+
+/* Processor specific section headers, sh_type field */
+#define SHT_ORDERED		SHT_HIPROC	/* Link editor is to sort the \
+						   entries in this section \
+						   based on the address \
+						   specified in the associated \
+						   symbol table entry.  */
+
+#endif /* _ELF_OR1K_H */
diff --git a/binutils-2.25/include/elf/pj.h b/binutils-2.25/include/elf/pj.h
new file mode 100644
index 00000000..afd19e8d
--- /dev/null
+++ b/binutils-2.25/include/elf/pj.h
@@ -0,0 +1,44 @@
+/* picoJava ELF support for BFD.
+   Copyright 1999, 2000, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_PJ_H
+#define _ELF_PJ_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+
+START_RELOC_NUMBERS (elf_pj_reloc_type)
+  RELOC_NUMBER (R_PJ_NONE, 0)
+  RELOC_NUMBER (R_PJ_DATA_DIR32, 1)
+  RELOC_NUMBER (R_PJ_CODE_REL32, 2)
+  RELOC_NUMBER (R_PJ_CODE_REL16, 3) 
+  RELOC_NUMBER (R_PJ_CODE_DIR32, 6)
+  RELOC_NUMBER (R_PJ_CODE_DIR16, 7)  
+  RELOC_NUMBER (R_PJ_CODE_LO16, 13)
+  RELOC_NUMBER (R_PJ_CODE_HI16, 14)
+  RELOC_NUMBER (R_PJ_GNU_VTINHERIT, 15)
+  RELOC_NUMBER (R_PJ_GNU_VTENTRY, 16)
+END_RELOC_NUMBERS (R_PJ_max)
+
+#define EF_PICOJAVA_ARCH     0x0000000f
+#define EF_PICOJAVA_NEWCALLS 0x00000010
+#define EF_PICOJAVA_GNUCALLS 0x00000020  /* The (currently) non standard GNU calling convention */
+
+#endif
diff --git a/binutils-2.25/include/elf/ppc.h b/binutils-2.25/include/elf/ppc.h
new file mode 100644
index 00000000..f80a1e8a
--- /dev/null
+++ b/binutils-2.25/include/elf/ppc.h
@@ -0,0 +1,223 @@
+/* PPC ELF support for BFD.
+   Copyright 1995, 1996, 1998, 2000, 2001, 2002, 2003, 2005, 2007, 2008,
+   2009, 2010 Free Software Foundation, Inc.
+
+   By Michael Meissner, Cygnus Support, <meissner@cygnus.com>,
+   from information in the System V Application Binary Interface,
+   PowerPC Processor Supplement and the PowerPC Embedded Application
+   Binary Interface (eabi).
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file holds definitions specific to the PPC ELF ABI.  Note
+   that most of this is not actually implemented by BFD.  */
+
+#ifndef _ELF_PPC_H
+#define _ELF_PPC_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_ppc_reloc_type)
+  RELOC_NUMBER (R_PPC_NONE,		  0)
+  RELOC_NUMBER (R_PPC_ADDR32,		  1)
+  RELOC_NUMBER (R_PPC_ADDR24,		  2)
+  RELOC_NUMBER (R_PPC_ADDR16,		  3)
+  RELOC_NUMBER (R_PPC_ADDR16_LO,	  4)
+  RELOC_NUMBER (R_PPC_ADDR16_HI,	  5)
+  RELOC_NUMBER (R_PPC_ADDR16_HA,	  6)
+  RELOC_NUMBER (R_PPC_ADDR14,		  7)
+  RELOC_NUMBER (R_PPC_ADDR14_BRTAKEN,	  8)
+  RELOC_NUMBER (R_PPC_ADDR14_BRNTAKEN,	  9)
+  RELOC_NUMBER (R_PPC_REL24,		 10)
+  RELOC_NUMBER (R_PPC_REL14,		 11)
+  RELOC_NUMBER (R_PPC_REL14_BRTAKEN,	 12)
+  RELOC_NUMBER (R_PPC_REL14_BRNTAKEN,	 13)
+  RELOC_NUMBER (R_PPC_GOT16,		 14)
+  RELOC_NUMBER (R_PPC_GOT16_LO,		 15)
+  RELOC_NUMBER (R_PPC_GOT16_HI,		 16)
+  RELOC_NUMBER (R_PPC_GOT16_HA,		 17)
+  RELOC_NUMBER (R_PPC_PLTREL24,		 18)
+  RELOC_NUMBER (R_PPC_COPY,		 19)
+  RELOC_NUMBER (R_PPC_GLOB_DAT,		 20)
+  RELOC_NUMBER (R_PPC_JMP_SLOT,		 21)
+  RELOC_NUMBER (R_PPC_RELATIVE,		 22)
+  RELOC_NUMBER (R_PPC_LOCAL24PC,	 23)
+  RELOC_NUMBER (R_PPC_UADDR32,		 24)
+  RELOC_NUMBER (R_PPC_UADDR16,		 25)
+  RELOC_NUMBER (R_PPC_REL32,		 26)
+  RELOC_NUMBER (R_PPC_PLT32,		 27)
+  RELOC_NUMBER (R_PPC_PLTREL32,		 28)
+  RELOC_NUMBER (R_PPC_PLT16_LO,		 29)
+  RELOC_NUMBER (R_PPC_PLT16_HI,		 30)
+  RELOC_NUMBER (R_PPC_PLT16_HA,		 31)
+  RELOC_NUMBER (R_PPC_SDAREL16,		 32)
+  RELOC_NUMBER (R_PPC_SECTOFF,		 33)
+  RELOC_NUMBER (R_PPC_SECTOFF_LO,	 34)
+  RELOC_NUMBER (R_PPC_SECTOFF_HI,	 35)
+  RELOC_NUMBER (R_PPC_SECTOFF_HA,	 36)
+  RELOC_NUMBER (R_PPC_ADDR30,		 37)
+
+#ifndef RELOC_MACROS_GEN_FUNC
+/* Fake relocations for branch stubs, only used internally by ld.  */
+  RELOC_NUMBER (R_PPC_RELAX,		 48)
+  RELOC_NUMBER (R_PPC_RELAX_PLT,	 49)
+  RELOC_NUMBER (R_PPC_RELAX_PLTREL24,	 50)
+#endif
+
+  /* Relocs added to support TLS.  */
+  RELOC_NUMBER (R_PPC_TLS,		 67)
+  RELOC_NUMBER (R_PPC_DTPMOD32,		 68)
+  RELOC_NUMBER (R_PPC_TPREL16,		 69)
+  RELOC_NUMBER (R_PPC_TPREL16_LO,	 70)
+  RELOC_NUMBER (R_PPC_TPREL16_HI,	 71)
+  RELOC_NUMBER (R_PPC_TPREL16_HA,	 72)
+  RELOC_NUMBER (R_PPC_TPREL32,		 73)
+  RELOC_NUMBER (R_PPC_DTPREL16,		 74)
+  RELOC_NUMBER (R_PPC_DTPREL16_LO,	 75)
+  RELOC_NUMBER (R_PPC_DTPREL16_HI,	 76)
+  RELOC_NUMBER (R_PPC_DTPREL16_HA,	 77)
+  RELOC_NUMBER (R_PPC_DTPREL32,		 78)
+  RELOC_NUMBER (R_PPC_GOT_TLSGD16,	 79)
+  RELOC_NUMBER (R_PPC_GOT_TLSGD16_LO,	 80)
+  RELOC_NUMBER (R_PPC_GOT_TLSGD16_HI,	 81)
+  RELOC_NUMBER (R_PPC_GOT_TLSGD16_HA,	 82)
+  RELOC_NUMBER (R_PPC_GOT_TLSLD16,	 83)
+  RELOC_NUMBER (R_PPC_GOT_TLSLD16_LO,	 84)
+  RELOC_NUMBER (R_PPC_GOT_TLSLD16_HI,	 85)
+  RELOC_NUMBER (R_PPC_GOT_TLSLD16_HA,	 86)
+  RELOC_NUMBER (R_PPC_GOT_TPREL16,	 87)
+  RELOC_NUMBER (R_PPC_GOT_TPREL16_LO,	 88)
+  RELOC_NUMBER (R_PPC_GOT_TPREL16_HI,	 89)
+  RELOC_NUMBER (R_PPC_GOT_TPREL16_HA,	 90)
+  RELOC_NUMBER (R_PPC_GOT_DTPREL16,	 91)
+  RELOC_NUMBER (R_PPC_GOT_DTPREL16_LO,	 92)
+  RELOC_NUMBER (R_PPC_GOT_DTPREL16_HI,	 93)
+  RELOC_NUMBER (R_PPC_GOT_DTPREL16_HA,	 94)
+  RELOC_NUMBER (R_PPC_TLSGD,		 95)
+  RELOC_NUMBER (R_PPC_TLSLD,		 96)
+
+/* The remaining relocs are from the Embedded ELF ABI, and are not
+   in the SVR4 ELF ABI.  */
+  RELOC_NUMBER (R_PPC_EMB_NADDR32,	101)
+  RELOC_NUMBER (R_PPC_EMB_NADDR16,	102)
+  RELOC_NUMBER (R_PPC_EMB_NADDR16_LO,	103)
+  RELOC_NUMBER (R_PPC_EMB_NADDR16_HI,	104)
+  RELOC_NUMBER (R_PPC_EMB_NADDR16_HA,	105)
+  RELOC_NUMBER (R_PPC_EMB_SDAI16,	106)
+  RELOC_NUMBER (R_PPC_EMB_SDA2I16,	107)
+  RELOC_NUMBER (R_PPC_EMB_SDA2REL,	108)
+  RELOC_NUMBER (R_PPC_EMB_SDA21,	109)
+  RELOC_NUMBER (R_PPC_EMB_MRKREF,	110)
+  RELOC_NUMBER (R_PPC_EMB_RELSEC16,	111)
+  RELOC_NUMBER (R_PPC_EMB_RELST_LO,	112)
+  RELOC_NUMBER (R_PPC_EMB_RELST_HI,	113)
+  RELOC_NUMBER (R_PPC_EMB_RELST_HA,	114)
+  RELOC_NUMBER (R_PPC_EMB_BIT_FLD,	115)
+  RELOC_NUMBER (R_PPC_EMB_RELSDA,	116)
+
+/* PowerPC VLE relocations.  */
+  RELOC_NUMBER (R_PPC_VLE_REL8,		216)
+  RELOC_NUMBER (R_PPC_VLE_REL15,	217)
+  RELOC_NUMBER (R_PPC_VLE_REL24,	218)
+  RELOC_NUMBER (R_PPC_VLE_LO16A,	219)
+  RELOC_NUMBER (R_PPC_VLE_LO16D,	220)
+  RELOC_NUMBER (R_PPC_VLE_HI16A,	221)
+  RELOC_NUMBER (R_PPC_VLE_HI16D,	222)
+  RELOC_NUMBER (R_PPC_VLE_HA16A,	223)
+  RELOC_NUMBER (R_PPC_VLE_HA16D,	224)
+  RELOC_NUMBER (R_PPC_VLE_SDA21,	225)
+  RELOC_NUMBER (R_PPC_VLE_SDA21_LO,	226)
+  RELOC_NUMBER (R_PPC_VLE_SDAREL_LO16A,	227)
+  RELOC_NUMBER (R_PPC_VLE_SDAREL_LO16D,	228)
+  RELOC_NUMBER (R_PPC_VLE_SDAREL_HI16A,	229)
+  RELOC_NUMBER (R_PPC_VLE_SDAREL_HI16D,	230)
+  RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16A,	231)
+  RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16D,	232)
+
+/* Support STT_GNU_IFUNC plt calls.  */
+  RELOC_NUMBER (R_PPC_IRELATIVE,	248)
+
+/* These are GNU extensions used in PIC code sequences.  */
+  RELOC_NUMBER (R_PPC_REL16,		249)
+  RELOC_NUMBER (R_PPC_REL16_LO,		250)
+  RELOC_NUMBER (R_PPC_REL16_HI,		251)
+  RELOC_NUMBER (R_PPC_REL16_HA,		252)
+
+/* These are GNU extensions to enable C++ vtable garbage collection.  */
+  RELOC_NUMBER (R_PPC_GNU_VTINHERIT,	253)
+  RELOC_NUMBER (R_PPC_GNU_VTENTRY,	254)
+
+/* This is a phony reloc to handle any old fashioned TOC16 references
+   that may still be in object files.  */
+  RELOC_NUMBER (R_PPC_TOC16,		255)
+
+END_RELOC_NUMBERS (R_PPC_max)
+
+#define IS_PPC_TLS_RELOC(R) \
+  ((R) >= R_PPC_TLS && (R) <= R_PPC_GOT_DTPREL16_HA)
+
+/* Specify the value of _GLOBAL_OFFSET_TABLE_.  */
+#define DT_PPC_GOT		(DT_LOPROC)
+
+/* Specify that tls descriptors should be optimized.  */
+#define DT_PPC_TLSOPT		(DT_LOPROC + 1)
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+#define	EF_PPC_EMB		0x80000000	/* PowerPC embedded flag.  */
+
+#define	EF_PPC_RELOCATABLE	0x00010000	/* PowerPC -mrelocatable flag.  */
+#define	EF_PPC_RELOCATABLE_LIB	0x00008000	/* PowerPC -mrelocatable-lib flag.  */
+
+/* Processor specific program headers, p_flags field.  */
+#define PF_PPC_VLE		0x10000000	/* PowerPC VLE.  */
+
+/* Processor specific section headers, sh_flags field.  */
+#define SHF_PPC_VLE		0x10000000	/* PowerPC VLE text section.  */
+
+/* Processor specific section headers, sh_type field.  */
+
+#define SHT_ORDERED		SHT_HIPROC	/* Link editor is to sort the \
+						   entries in this section \
+						   based on the address \
+						   specified in the associated \
+						   symbol table entry.  */
+
+/* Object attribute tags.  */
+enum
+{
+  /* 0-3 are generic.  */
+  Tag_GNU_Power_ABI_FP = 4, /* Value 1 for hard-float, 2 for
+			       soft-float, 3 for single=precision 
+			       hard-float; 0 for not tagged or not
+			       using any ABIs affected by the
+			       differences.  */
+
+  /* Value 1 for general purpose registers only, 2 for AltiVec
+     registers, 3 for SPE registers; 0 for not tagged or not using any
+     ABIs affected by the differences.  */
+  Tag_GNU_Power_ABI_Vector = 8,
+
+  /* Value 1 for ABIs using r3/r4 for returning structures <= 8 bytes,
+     2 for ABIs using memory; 0 for not tagged or not using any ABIs
+     affected by the differences.  */
+  Tag_GNU_Power_ABI_Struct_Return = 12
+};
+
+#endif /* _ELF_PPC_H */
diff --git a/binutils-2.25/include/elf/ppc64.h b/binutils-2.25/include/elf/ppc64.h
new file mode 100644
index 00000000..f1c80f18
--- /dev/null
+++ b/binutils-2.25/include/elf/ppc64.h
@@ -0,0 +1,177 @@
+/* PPC64 ELF support for BFD.
+   Copyright 2003, 2005, 2009, 2010, 2011 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _ELF_PPC64_H
+#define _ELF_PPC64_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_ppc64_reloc_type)
+  RELOC_NUMBER (R_PPC64_NONE,		     0)
+  RELOC_NUMBER (R_PPC64_ADDR32,		     1)
+  RELOC_NUMBER (R_PPC64_ADDR24,		     2)
+  RELOC_NUMBER (R_PPC64_ADDR16,		     3)
+  RELOC_NUMBER (R_PPC64_ADDR16_LO,	     4)
+  RELOC_NUMBER (R_PPC64_ADDR16_HI,	     5)
+  RELOC_NUMBER (R_PPC64_ADDR16_HA,	     6)
+  RELOC_NUMBER (R_PPC64_ADDR14,		     7)
+  RELOC_NUMBER (R_PPC64_ADDR14_BRTAKEN,	     8)
+  RELOC_NUMBER (R_PPC64_ADDR14_BRNTAKEN,     9)
+  RELOC_NUMBER (R_PPC64_REL24,		    10)
+  RELOC_NUMBER (R_PPC64_REL14,		    11)
+  RELOC_NUMBER (R_PPC64_REL14_BRTAKEN,	    12)
+  RELOC_NUMBER (R_PPC64_REL14_BRNTAKEN,	    13)
+  RELOC_NUMBER (R_PPC64_GOT16,		    14)
+  RELOC_NUMBER (R_PPC64_GOT16_LO,	    15)
+  RELOC_NUMBER (R_PPC64_GOT16_HI,	    16)
+  RELOC_NUMBER (R_PPC64_GOT16_HA,	    17)
+  /* 18 unused.  32-bit reloc is R_PPC_PLTREL24.  */
+  RELOC_NUMBER (R_PPC64_COPY,		    19)
+  RELOC_NUMBER (R_PPC64_GLOB_DAT,	    20)
+  RELOC_NUMBER (R_PPC64_JMP_SLOT,	    21)
+  RELOC_NUMBER (R_PPC64_RELATIVE,	    22)
+  /* 23 unused.  32-bit reloc is R_PPC_LOCAL24PC.  */
+  RELOC_NUMBER (R_PPC64_UADDR32,	    24)
+  RELOC_NUMBER (R_PPC64_UADDR16,	    25)
+  RELOC_NUMBER (R_PPC64_REL32,		    26)
+  RELOC_NUMBER (R_PPC64_PLT32,		    27)
+  RELOC_NUMBER (R_PPC64_PLTREL32,	    28)
+  RELOC_NUMBER (R_PPC64_PLT16_LO,	    29)
+  RELOC_NUMBER (R_PPC64_PLT16_HI,	    30)
+  RELOC_NUMBER (R_PPC64_PLT16_HA,	    31)
+  /* 32 unused.  32-bit reloc is R_PPC_SDAREL16.  */
+  RELOC_NUMBER (R_PPC64_SECTOFF,	    33)
+  RELOC_NUMBER (R_PPC64_SECTOFF_LO,	    34)
+  RELOC_NUMBER (R_PPC64_SECTOFF_HI,	    35)
+  RELOC_NUMBER (R_PPC64_SECTOFF_HA,	    36)
+  RELOC_NUMBER (R_PPC64_REL30,		    37)
+  RELOC_NUMBER (R_PPC64_ADDR64,		    38)
+  RELOC_NUMBER (R_PPC64_ADDR16_HIGHER,	    39)
+  RELOC_NUMBER (R_PPC64_ADDR16_HIGHERA,	    40)
+  RELOC_NUMBER (R_PPC64_ADDR16_HIGHEST,	    41)
+  RELOC_NUMBER (R_PPC64_ADDR16_HIGHESTA,    42)
+  RELOC_NUMBER (R_PPC64_UADDR64,	    43)
+  RELOC_NUMBER (R_PPC64_REL64,		    44)
+  RELOC_NUMBER (R_PPC64_PLT64,		    45)
+  RELOC_NUMBER (R_PPC64_PLTREL64,	    46)
+  RELOC_NUMBER (R_PPC64_TOC16,		    47)
+  RELOC_NUMBER (R_PPC64_TOC16_LO,	    48)
+  RELOC_NUMBER (R_PPC64_TOC16_HI,	    49)
+  RELOC_NUMBER (R_PPC64_TOC16_HA,	    50)
+  RELOC_NUMBER (R_PPC64_TOC,		    51)
+  RELOC_NUMBER (R_PPC64_PLTGOT16,	    52)
+  RELOC_NUMBER (R_PPC64_PLTGOT16_LO,	    53)
+  RELOC_NUMBER (R_PPC64_PLTGOT16_HI,	    54)
+  RELOC_NUMBER (R_PPC64_PLTGOT16_HA,	    55)
+
+  /* The following relocs were added in the 64-bit PowerPC ELF ABI
+     revision 1.2. */
+  RELOC_NUMBER (R_PPC64_ADDR16_DS,	    56)
+  RELOC_NUMBER (R_PPC64_ADDR16_LO_DS,	    57)
+  RELOC_NUMBER (R_PPC64_GOT16_DS,	    58)
+  RELOC_NUMBER (R_PPC64_GOT16_LO_DS,	    59)
+  RELOC_NUMBER (R_PPC64_PLT16_LO_DS,	    60)
+  RELOC_NUMBER (R_PPC64_SECTOFF_DS,	    61)
+  RELOC_NUMBER (R_PPC64_SECTOFF_LO_DS,	    62)
+  RELOC_NUMBER (R_PPC64_TOC16_DS,	    63)
+  RELOC_NUMBER (R_PPC64_TOC16_LO_DS,	    64)
+  RELOC_NUMBER (R_PPC64_PLTGOT16_DS,	    65)
+  RELOC_NUMBER (R_PPC64_PLTGOT16_LO_DS,	    66)
+
+  /* Relocs added to support TLS.  PowerPC64 ELF ABI revision 1.5.  */
+  RELOC_NUMBER (R_PPC64_TLS,		    67)
+  RELOC_NUMBER (R_PPC64_DTPMOD64,	    68)
+  RELOC_NUMBER (R_PPC64_TPREL16,	    69)
+  RELOC_NUMBER (R_PPC64_TPREL16_LO,	    70)
+  RELOC_NUMBER (R_PPC64_TPREL16_HI,	    71)
+  RELOC_NUMBER (R_PPC64_TPREL16_HA,	    72)
+  RELOC_NUMBER (R_PPC64_TPREL64,	    73)
+  RELOC_NUMBER (R_PPC64_DTPREL16,	    74)
+  RELOC_NUMBER (R_PPC64_DTPREL16_LO,	    75)
+  RELOC_NUMBER (R_PPC64_DTPREL16_HI,	    76)
+  RELOC_NUMBER (R_PPC64_DTPREL16_HA,	    77)
+  RELOC_NUMBER (R_PPC64_DTPREL64,	    78)
+  RELOC_NUMBER (R_PPC64_GOT_TLSGD16,	    79)
+  RELOC_NUMBER (R_PPC64_GOT_TLSGD16_LO,	    80)
+  RELOC_NUMBER (R_PPC64_GOT_TLSGD16_HI,	    81)
+  RELOC_NUMBER (R_PPC64_GOT_TLSGD16_HA,	    82)
+  RELOC_NUMBER (R_PPC64_GOT_TLSLD16,	    83)
+  RELOC_NUMBER (R_PPC64_GOT_TLSLD16_LO,	    84)
+  RELOC_NUMBER (R_PPC64_GOT_TLSLD16_HI,	    85)
+  RELOC_NUMBER (R_PPC64_GOT_TLSLD16_HA,	    86)
+  RELOC_NUMBER (R_PPC64_GOT_TPREL16_DS,	    87)
+  RELOC_NUMBER (R_PPC64_GOT_TPREL16_LO_DS,  88)
+  RELOC_NUMBER (R_PPC64_GOT_TPREL16_HI,	    89)
+  RELOC_NUMBER (R_PPC64_GOT_TPREL16_HA,	    90)
+  RELOC_NUMBER (R_PPC64_GOT_DTPREL16_DS,    91)
+  RELOC_NUMBER (R_PPC64_GOT_DTPREL16_LO_DS, 92)
+  RELOC_NUMBER (R_PPC64_GOT_DTPREL16_HI,    93)
+  RELOC_NUMBER (R_PPC64_GOT_DTPREL16_HA,    94)
+  RELOC_NUMBER (R_PPC64_TPREL16_DS,	    95)
+  RELOC_NUMBER (R_PPC64_TPREL16_LO_DS,	    96)
+  RELOC_NUMBER (R_PPC64_TPREL16_HIGHER,	    97)
+  RELOC_NUMBER (R_PPC64_TPREL16_HIGHERA,    98)
+  RELOC_NUMBER (R_PPC64_TPREL16_HIGHEST,    99)
+  RELOC_NUMBER (R_PPC64_TPREL16_HIGHESTA,  100)
+  RELOC_NUMBER (R_PPC64_DTPREL16_DS,	   101)
+  RELOC_NUMBER (R_PPC64_DTPREL16_LO_DS,	   102)
+  RELOC_NUMBER (R_PPC64_DTPREL16_HIGHER,   103)
+  RELOC_NUMBER (R_PPC64_DTPREL16_HIGHERA,  104)
+  RELOC_NUMBER (R_PPC64_DTPREL16_HIGHEST,  105)
+  RELOC_NUMBER (R_PPC64_DTPREL16_HIGHESTA, 106)
+  RELOC_NUMBER (R_PPC64_TLSGD,		   107)
+  RELOC_NUMBER (R_PPC64_TLSLD,		   108)
+  RELOC_NUMBER (R_PPC64_TOCSAVE,	   109)
+
+#ifndef RELOC_MACROS_GEN_FUNC
+/* Fake relocation only used internally by ld.  */
+  RELOC_NUMBER (R_PPC64_LO_DS_OPT,	   128)
+#endif
+/* Support STT_GNU_IFUNC plt calls.  */
+  RELOC_NUMBER (R_PPC64_JMP_IREL,	   247)
+  RELOC_NUMBER (R_PPC64_IRELATIVE,	   248)
+
+/* These are GNU extensions used in PIC code sequences.  */
+  RELOC_NUMBER (R_PPC64_REL16,		   249)
+  RELOC_NUMBER (R_PPC64_REL16_LO,	   250)
+  RELOC_NUMBER (R_PPC64_REL16_HI,	   251)
+  RELOC_NUMBER (R_PPC64_REL16_HA,	   252)
+
+  /* These are GNU extensions to enable C++ vtable garbage collection.  */
+  RELOC_NUMBER (R_PPC64_GNU_VTINHERIT,	   253)
+  RELOC_NUMBER (R_PPC64_GNU_VTENTRY,	   254)
+
+END_RELOC_NUMBERS (R_PPC64_max)
+
+#define IS_PPC64_TLS_RELOC(R) \
+  ((R) >= R_PPC64_TLS && (R) <= R_PPC64_DTPREL16_HIGHESTA)
+
+/* Specify the start of the .glink section.  */
+#define DT_PPC64_GLINK		DT_LOPROC
+
+/* Specify the start and size of the .opd section.  */
+#define DT_PPC64_OPD		(DT_LOPROC + 1)
+#define DT_PPC64_OPDSZ		(DT_LOPROC + 2)
+
+/* Specify that tls descriptors should be optimized.  */
+#define DT_PPC64_TLSOPT		(DT_LOPROC + 3)
+
+#endif /* _ELF_PPC64_H */
diff --git a/binutils-2.25/include/elf/reloc-macros.h b/binutils-2.25/include/elf/reloc-macros.h
new file mode 100644
index 00000000..92fc9c14
--- /dev/null
+++ b/binutils-2.25/include/elf/reloc-macros.h
@@ -0,0 +1,129 @@
+/* Generic relocation support for BFD.
+   Copyright 1998, 1999, 2000, 2003, 2010, 2011  Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+/* These macros are used by the various *.h target specific header
+   files to either generate an enum containing all the known relocations
+   for that target, or if RELOC_MACROS_GEN_FUNC is defined, a recognition
+   function is generated instead.  (This is used by binutils/readelf.c)
+
+   Given a header file like this:
+
+   	START_RELOC_NUMBERS (foo)
+   	    RELOC_NUMBER (R_foo_NONE,    0)
+   	    RELOC_NUMBER (R_foo_32,      1)
+   	    EMPTY_RELOC  (R_foo_good)
+   	    FAKE_RELOC   (R_foo_illegal, 9)
+   	END_RELOC_NUMBERS (R_foo_count)
+
+   Then the following will be produced by default (ie if
+   RELOC_MACROS_GEN_FUNC is *not* defined).
+
+   	enum foo
+	{
+   	  R_foo_NONE = 0,
+   	  R_foo_32 = 1,
+	  R_foo_good,
+   	  R_foo_illegal = 9,
+   	  R_foo_count
+   	};
+
+   Note: The value of the symbol defined in the END_RELOC_NUMBERS
+   macro (R_foo_count in the case of the example above) will be
+   set to the value of the whichever *_RELOC macro precedes it plus
+   one.  Therefore if you intend to use the symbol as a sentinel for
+   the highest valid macro value you should make sure that the
+   preceding *_RELOC macro is the highest valid number.  ie a
+   declaration like this:
+
+   	START_RELOC_NUMBERS (foo)
+   	    RELOC_NUMBER (R_foo_NONE,    0)
+   	    RELOC_NUMBER (R_foo_32,      1)
+   	    FAKE_RELOC   (R_foo_illegal, 9)
+   	    FAKE_RELOC   (R_foo_synonym, 0)
+   	END_RELOC_NUMBERS (R_foo_count)
+
+   will result in R_foo_count having a value of 1 (R_foo_synonym + 1)
+   rather than 10 or 2 as might be expected.
+
+   Alternatively you can assign a value to END_RELOC_NUMBERS symbol
+   explicitly, like this:
+
+   	START_RELOC_NUMBERS (foo)
+   	    RELOC_NUMBER (R_foo_NONE,    0)
+   	    RELOC_NUMBER (R_foo_32,      1)
+   	    FAKE_RELOC   (R_foo_illegal, 9)
+   	    FAKE_RELOC   (R_foo_synonym, 0)
+   	END_RELOC_NUMBERS (R_foo_count = 2)
+
+   If RELOC_MACROS_GEN_FUNC *is* defined, then instead the
+   following function will be generated:
+
+   	static const char *foo (unsigned long rtype);
+   	static const char *
+   	foo (unsigned long rtype)
+   	{
+   	   switch (rtype)
+   	   {
+   	   case 0: return "R_foo_NONE";
+   	   case 1: return "R_foo_32";
+   	   default: return NULL;
+   	   }
+   	}
+   */
+
+#ifndef _RELOC_MACROS_H
+#define _RELOC_MACROS_H
+
+#ifdef RELOC_MACROS_GEN_FUNC
+
+/* This function takes the relocation number and returns the
+   string version name of the name of that relocation.  If
+   the relocation is not recognised, NULL is returned.  */
+
+#define START_RELOC_NUMBERS(name)   				\
+static const char *name (unsigned long rtype);			\
+static const char *						\
+name (unsigned long rtype)					\
+{								\
+  switch (rtype)						\
+    {
+
+#define RELOC_NUMBER(name, number) \
+    case number: return #name;
+
+#define FAKE_RELOC(name, number)
+#define EMPTY_RELOC(name)
+
+#define END_RELOC_NUMBERS(name)	\
+    default: return NULL;	\
+    }				\
+}
+
+
+#else /* Default to generating enum.  */
+
+#define START_RELOC_NUMBERS(name)   enum name {
+#define RELOC_NUMBER(name, number)  name = number,
+#define FAKE_RELOC(name, number)    name = number,
+#define EMPTY_RELOC(name)           name,
+#define END_RELOC_NUMBERS(name)     name };
+
+#endif
+
+#endif /* _RELOC_MACROS_H */
diff --git a/binutils-2.25/include/elf/rl78.h b/binutils-2.25/include/elf/rl78.h
new file mode 100644
index 00000000..b281d3af
--- /dev/null
+++ b/binutils-2.25/include/elf/rl78.h
@@ -0,0 +1,120 @@
+/* RL78 ELF support for BFD.
+   Copyright (C) 2008-2013 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_RL78_H
+#define _ELF_RL78_H
+
+#include "elf/reloc-macros.h"
+
+/* Note that there are a few internal relocation types used by the
+   linker to do link-time relaxation.  If you update this file, please
+   check elf32-rl78.c to see if any of the internal relocations need to
+   be, er, relocated.  */
+
+/* Preliminary relocations.  */
+START_RELOC_NUMBERS (elf_rl78_reloc_type)
+
+  RELOC_NUMBER (R_RL78_NONE,         0x00)
+  /* These are for data, and are bi-endian.  */
+  RELOC_NUMBER (R_RL78_DIR32,        0x01) /* Was: R_RL78_32.  */
+  RELOC_NUMBER (R_RL78_DIR24S,       0x02) /* Was: R_RL78_24.  */
+  RELOC_NUMBER (R_RL78_DIR16,        0x03)
+  RELOC_NUMBER (R_RL78_DIR16U,       0x04) /* Was: R_RL78_16_UNS.  */
+  RELOC_NUMBER (R_RL78_DIR16S,       0x05) /* Was: R_RL78_16.  */
+  RELOC_NUMBER (R_RL78_DIR8,         0x06)
+  RELOC_NUMBER (R_RL78_DIR8U,        0x07) /* Was: R_RL78_8_UNS.  */
+  RELOC_NUMBER (R_RL78_DIR8S,        0x08) /* Was: R_RL78_8.  */
+
+  /* Signed pc-relative values.  */
+  RELOC_NUMBER (R_RL78_DIR24S_PCREL, 0x09) /* Was: R_RL78_24_PCREL.  */
+  RELOC_NUMBER (R_RL78_DIR16S_PCREL, 0x0a) /* Was: R_RL78_16_PCREL.  */
+  RELOC_NUMBER (R_RL78_DIR8S_PCREL,  0x0b) /* Was: R_RL78_8_PCREL.  */
+
+  /* These are for fields in the instructions.  */
+  RELOC_NUMBER (R_RL78_DIR16UL,      0x0c)
+  RELOC_NUMBER (R_RL78_DIR16UW,      0x0d)
+  RELOC_NUMBER (R_RL78_DIR8UL,       0x0e)
+  RELOC_NUMBER (R_RL78_DIR8UW,       0x0f)
+  RELOC_NUMBER (R_RL78_DIR32_REV,    0x10)
+  RELOC_NUMBER (R_RL78_DIR16_REV,    0x11)
+  RELOC_NUMBER (R_RL78_DIR3U_PCREL,  0x12)
+
+  /* These are extensions added by Red Hat.  */
+  RELOC_NUMBER (R_RL78_RH_RELAX,     0x2d) /* Marks opcodes suitable for linker relaxation.  */
+  RELOC_NUMBER (R_RL78_RH_SFR,       0x2e) /* SFR addresses - internal use only.  */
+  RELOC_NUMBER (R_RL78_RH_SADDR,     0x2f) /* SADDR addresses - internal use only..  */
+
+  /* These are for complex relocs.  */
+  RELOC_NUMBER (R_RL78_ABS32,        0x41)
+  RELOC_NUMBER (R_RL78_ABS24S,       0x42)
+  RELOC_NUMBER (R_RL78_ABS16,        0x43)
+  RELOC_NUMBER (R_RL78_ABS16U,       0x44)
+  RELOC_NUMBER (R_RL78_ABS16S,       0x45)
+  RELOC_NUMBER (R_RL78_ABS8,         0x46)
+  RELOC_NUMBER (R_RL78_ABS8U,        0x47)
+  RELOC_NUMBER (R_RL78_ABS8S,        0x48)
+  RELOC_NUMBER (R_RL78_ABS24S_PCREL, 0x49)
+  RELOC_NUMBER (R_RL78_ABS16S_PCREL, 0x4a)
+  RELOC_NUMBER (R_RL78_ABS8S_PCREL,  0x4b)
+  RELOC_NUMBER (R_RL78_ABS16UL,      0x4c)
+  RELOC_NUMBER (R_RL78_ABS16UW,      0x4d)
+  RELOC_NUMBER (R_RL78_ABS8UL,       0x4e)
+  RELOC_NUMBER (R_RL78_ABS8UW,       0x4f)
+  RELOC_NUMBER (R_RL78_ABS32_REV,    0x50)
+  RELOC_NUMBER (R_RL78_ABS16_REV,    0x51)
+
+  RELOC_NUMBER (R_RL78_SYM,          0x80)
+  RELOC_NUMBER (R_RL78_OPneg,        0x81)
+  RELOC_NUMBER (R_RL78_OPadd,        0x82)
+  RELOC_NUMBER (R_RL78_OPsub,        0x83)
+  RELOC_NUMBER (R_RL78_OPmul,        0x84)
+  RELOC_NUMBER (R_RL78_OPdiv,        0x85)
+  RELOC_NUMBER (R_RL78_OPshla,       0x86)
+  RELOC_NUMBER (R_RL78_OPshra,       0x87)
+  RELOC_NUMBER (R_RL78_OPsctsize,    0x88)
+  RELOC_NUMBER (R_RL78_OPscttop,     0x8d)
+  RELOC_NUMBER (R_RL78_OPand,        0x90)
+  RELOC_NUMBER (R_RL78_OPor,         0x91)
+  RELOC_NUMBER (R_RL78_OPxor,        0x92)
+  RELOC_NUMBER (R_RL78_OPnot,        0x93)
+  RELOC_NUMBER (R_RL78_OPmod,        0x94)
+  RELOC_NUMBER (R_RL78_OPromtop,     0x95)
+  RELOC_NUMBER (R_RL78_OPramtop,     0x96)
+
+END_RELOC_NUMBERS (R_RL78_max)
+
+#define EF_RL78_CPU_RL78	0x00000079      /* FIXME: correct value?  */
+#define EF_RL78_CPU_MASK	0x0000007F	/* specific cpu bits.  */
+#define EF_RL78_ALL_FLAGS	(EF_RL78_CPU_MASK)
+
+/* Values for the e_flags field in the ELF header.  */
+#define E_FLAG_RL78_64BIT_DOUBLES	(1 << 0)
+#define E_FLAG_RL78_DSP			(1 << 1) /* Defined in the RL78 CPU Object file specification, but not explained.  */
+#define E_FLAG_RL78_G10			(1 << 2) /* CPU is missing register banks 1-3, so uses different ABI.  */
+
+/* These define the addend field of R_RL78_RH_RELAX relocations.  */
+#define	RL78_RELAXA_BRA		0x00000010	/* Any type of branch (must be decoded).  */
+#define	RL78_RELAXA_ADDR16	0x00000020	/* addr16->sfr/saddr opportunity  */
+#define RL78_RELAXA_RNUM	0x0000000f	/* Number of associated relocations.  */
+/* These mark the place where alignment is requested, and the place where the filler bytes end.  */
+#define	RL78_RELAXA_ALIGN	0x10000000	/* Start alignment; the remaining bits are the alignment value.  */
+#define	RL78_RELAXA_ELIGN	0x20000000	/* End alignment; the remaining bits are the alignment value.  */
+#define	RL78_RELAXA_ANUM	0x00ffffff	/* Alignment amount, in bytes (i.e. .balign).  */
+
+#endif /* _ELF_RL78_H */
diff --git a/binutils-2.25/include/elf/rx.h b/binutils-2.25/include/elf/rx.h
new file mode 100644
index 00000000..83980853
--- /dev/null
+++ b/binutils-2.25/include/elf/rx.h
@@ -0,0 +1,136 @@
+/* RX ELF support for BFD.
+   Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_RX_H
+#define _ELF_RX_H
+
+#include "elf/reloc-macros.h"
+
+/* Note that there are a few internal relocation types used by the
+   linker to do link-time relaxation.  If you update this file, please
+   check elf32-rx.c to see if any of the internal relocations need to
+   be, er, relocated.  */
+
+/* Preliminary relocations.  */
+START_RELOC_NUMBERS (elf_rx_reloc_type)
+
+  RELOC_NUMBER (R_RX_NONE,         0x00)
+  /* These are for data, and are bi-endian.  */
+  RELOC_NUMBER (R_RX_DIR32,        0x01) /* Was: R_RX_32.  */
+  RELOC_NUMBER (R_RX_DIR24S,       0x02) /* Was: R_RX_24.  */
+  RELOC_NUMBER (R_RX_DIR16,        0x03)
+  RELOC_NUMBER (R_RX_DIR16U,       0x04) /* Was: R_RX_16_UNS.  */
+  RELOC_NUMBER (R_RX_DIR16S,       0x05) /* Was: R_RX_16.  */
+  RELOC_NUMBER (R_RX_DIR8,         0x06)
+  RELOC_NUMBER (R_RX_DIR8U,        0x07) /* Was: R_RX_8_UNS.  */
+  RELOC_NUMBER (R_RX_DIR8S,        0x08) /* Was: R_RX_8.  */
+
+  /* Signed pc-relative values.  */
+  RELOC_NUMBER (R_RX_DIR24S_PCREL, 0x09) /* Was: R_RX_24_PCREL.  */
+  RELOC_NUMBER (R_RX_DIR16S_PCREL, 0x0a) /* Was: R_RX_16_PCREL.  */
+  RELOC_NUMBER (R_RX_DIR8S_PCREL,  0x0b) /* Was: R_RX_8_PCREL.  */
+
+  /* These are for fields in the instructions.  */
+  RELOC_NUMBER (R_RX_DIR16UL,      0x0c)
+  RELOC_NUMBER (R_RX_DIR16UW,      0x0d)
+  RELOC_NUMBER (R_RX_DIR8UL,       0x0e)
+  RELOC_NUMBER (R_RX_DIR8UW,       0x0f)
+  RELOC_NUMBER (R_RX_DIR32_REV,    0x10)
+  RELOC_NUMBER (R_RX_DIR16_REV,    0x11)
+  RELOC_NUMBER (R_RX_DIR3U_PCREL,  0x12)
+
+  /* These are extensions added by Red Hat.  */
+  RELOC_NUMBER (R_RX_RH_3_PCREL,   0x20) /* Like R_RX_DIR8S_PCREL but only 3-bits.  */
+  RELOC_NUMBER (R_RX_RH_16_OP,     0x21) /* Like R_RX_DIR16 but for opcodes - always big endian.  */
+  RELOC_NUMBER (R_RX_RH_24_OP,     0x22) /* Like R_RX_DIR24S but for opcodes - always big endian.  */
+  RELOC_NUMBER (R_RX_RH_32_OP,     0x23) /* Like R_RX_DIR32 but for opcodes - always big endian.  */
+  RELOC_NUMBER (R_RX_RH_24_UNS,    0x24) /* Like R_RX_DIR24S but for unsigned values.  */
+  RELOC_NUMBER (R_RX_RH_8_NEG,     0x25) /* Like R_RX_DIR8 but -x is stored.  */
+  RELOC_NUMBER (R_RX_RH_16_NEG,    0x26) /* Like R_RX_DIR16 but -x is stored.  */
+  RELOC_NUMBER (R_RX_RH_24_NEG,    0x27) /* Like R_RX_DIR24S but -x is stored.  */
+  RELOC_NUMBER (R_RX_RH_32_NEG,    0x28) /* Like R_RX_DIR32 but -x is stored.  */
+  RELOC_NUMBER (R_RX_RH_DIFF,      0x29) /* Subtract from a previous relocation.  */
+  RELOC_NUMBER (R_RX_RH_GPRELB,    0x2a) /* Byte value, relative to __gp.  */
+  RELOC_NUMBER (R_RX_RH_GPRELW,    0x2b) /* Word value, relative to __gp.  */
+  RELOC_NUMBER (R_RX_RH_GPRELL,    0x2c) /* Long value, relative to __gp.  */
+  RELOC_NUMBER (R_RX_RH_RELAX,     0x2d) /* Marks opcodes suitable for linker relaxation.  */
+
+  /* These are for complex relocs.  */
+  RELOC_NUMBER (R_RX_ABS32,        0x41)
+  RELOC_NUMBER (R_RX_ABS24S,       0x42)
+  RELOC_NUMBER (R_RX_ABS16,        0x43)
+  RELOC_NUMBER (R_RX_ABS16U,       0x44)
+  RELOC_NUMBER (R_RX_ABS16S,       0x45)
+  RELOC_NUMBER (R_RX_ABS8,         0x46)
+  RELOC_NUMBER (R_RX_ABS8U,        0x47)
+  RELOC_NUMBER (R_RX_ABS8S,        0x48)
+  RELOC_NUMBER (R_RX_ABS24S_PCREL, 0x49)
+  RELOC_NUMBER (R_RX_ABS16S_PCREL, 0x4a)
+  RELOC_NUMBER (R_RX_ABS8S_PCREL,  0x4b)
+  RELOC_NUMBER (R_RX_ABS16UL,      0x4c)
+  RELOC_NUMBER (R_RX_ABS16UW,      0x4d)
+  RELOC_NUMBER (R_RX_ABS8UL,       0x4e)
+  RELOC_NUMBER (R_RX_ABS8UW,       0x4f)
+  RELOC_NUMBER (R_RX_ABS32_REV,    0x50)
+  RELOC_NUMBER (R_RX_ABS16_REV,    0x51)
+
+  RELOC_NUMBER (R_RX_SYM,          0x80)
+  RELOC_NUMBER (R_RX_OPneg,        0x81)
+  RELOC_NUMBER (R_RX_OPadd,        0x82)
+  RELOC_NUMBER (R_RX_OPsub,        0x83)
+  RELOC_NUMBER (R_RX_OPmul,        0x84)
+  RELOC_NUMBER (R_RX_OPdiv,        0x85)
+  RELOC_NUMBER (R_RX_OPshla,       0x86)
+  RELOC_NUMBER (R_RX_OPshra,       0x87)
+  RELOC_NUMBER (R_RX_OPsctsize,    0x88)
+  RELOC_NUMBER (R_RX_OPscttop,     0x8d)
+  RELOC_NUMBER (R_RX_OPand,        0x90)
+  RELOC_NUMBER (R_RX_OPor,         0x91)
+  RELOC_NUMBER (R_RX_OPxor,        0x92)
+  RELOC_NUMBER (R_RX_OPnot,        0x93)
+  RELOC_NUMBER (R_RX_OPmod,        0x94)
+  RELOC_NUMBER (R_RX_OPromtop,     0x95)
+  RELOC_NUMBER (R_RX_OPramtop,     0x96)
+
+END_RELOC_NUMBERS (R_RX_max)
+
+#define EF_RX_CPU_RX	0x00000079      /* FIXME: this collides with the E_FLAG_RX_... values below.  */
+#define EF_RX_CPU_MASK	0x0000007F	/* specific cpu bits.  */
+#define EF_RX_ALL_FLAGS	(EF_RX_CPU_MASK)
+
+/* Values for the e_flags field in the ELF header.  */
+#define E_FLAG_RX_64BIT_DOUBLES		(1 << 0)
+#define E_FLAG_RX_DSP			(1 << 1) /* Defined in the RX CPU Object file specification, but not explained. */
+#define E_FLAG_RX_PID			(1 << 2) /* Unofficial - DJ */
+#define E_FLAG_RX_ABI			(1 << 3) /* Binary passes stacked arguments using natural alignment.  Unofficial - NC.  */
+
+/* These define the addend field of R_RX_RH_RELAX relocations.  */
+#define	RX_RELAXA_IMM6	0x00000010	/* Imm8/16/24/32 at bit offset 6.  */
+#define	RX_RELAXA_IMM12	0x00000020	/* Imm8/16/24/32 at bit offset 12.  */
+#define	RX_RELAXA_DSP4	0x00000040	/* Dsp0/8/16 at bit offset 4.  */
+#define	RX_RELAXA_DSP6	0x00000080	/* Dsp0/8/16 at bit offset 6.  */
+#define	RX_RELAXA_DSP14	0x00000100	/* Dsp0/8/16 at bit offset 14.  */
+#define	RX_RELAXA_BRA	0x00000200	/* Any type of branch (must be decoded).  */
+#define RX_RELAXA_RNUM	0x0000000f	/* Number of associated relocations.  */
+/* These mark the place where alignment is requested, and the place where the filler bytes end.  */
+#define	RX_RELAXA_ALIGN	0x10000000	/* Start alignment; the remaining bits are the alignment value.  */
+#define	RX_RELAXA_ELIGN	0x20000000	/* End alignment; the remaining bits are the alignment value.  */
+#define	RX_RELAXA_ANUM	0x00ffffff	/* Alignment amount, in bytes (i.e. .balign).  */
+
+#endif /* _ELF_RX_H */
diff --git a/binutils-2.25/include/elf/s390.h b/binutils-2.25/include/elf/s390.h
new file mode 100644
index 00000000..9128f868
--- /dev/null
+++ b/binutils-2.25/include/elf/s390.h
@@ -0,0 +1,134 @@
+/* 390 ELF support for BFD.
+   Copyright 2000, 2001, 2003, 2010 Free Software Foundation, Inc.
+   Contributed by Carl B. Pedersen and Martin Schwidefsky.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#ifndef _ELF_390_H
+#define _ELF_390_H
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+/* Symbol types.  */
+
+#define STACK_REG		15		/* Global Stack reg */
+#define BACKL_REG		14		/* Global Backlink reg */
+#define BASE_REG		13		/* Global Base reg */
+#define GOT_REG 		12		/* Holds addr of GOT */
+
+#include "elf/reloc-macros.h"
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+#define EF_S390_HIGH_GPRS        0x00000001
+
+/* Relocation types.  */
+
+START_RELOC_NUMBERS (elf_s390_reloc_type)
+    RELOC_NUMBER (R_390_NONE, 0)	/* No reloc.  */
+    RELOC_NUMBER (R_390_8, 1)		/* Direct 8 bit.  */
+    RELOC_NUMBER (R_390_12, 2)		/* Direct 12 bit.  */
+    RELOC_NUMBER (R_390_16, 3)		/* Direct 16 bit.  */
+    RELOC_NUMBER (R_390_32, 4)		/* Direct 32 bit.  */
+    RELOC_NUMBER (R_390_PC32, 5)	/* PC relative 32 bit.  */
+    RELOC_NUMBER (R_390_GOT12, 6)	/* 12 bit GOT offset.  */
+    RELOC_NUMBER (R_390_GOT32, 7)	/* 32 bit GOT offset.  */
+    RELOC_NUMBER (R_390_PLT32, 8)	/* 32 bit PC relative PLT address.  */
+    RELOC_NUMBER (R_390_COPY, 9)	/* Copy symbol at runtime.  */
+    RELOC_NUMBER (R_390_GLOB_DAT, 10)	/* Create GOT entry.  */
+    RELOC_NUMBER (R_390_JMP_SLOT, 11)	/* Create PLT entry.  */
+    RELOC_NUMBER (R_390_RELATIVE, 12)	/* Adjust by program base.  */
+    RELOC_NUMBER (R_390_GOTOFF32, 13)	/* 32 bit offset to GOT.  */
+    RELOC_NUMBER (R_390_GOTPC, 14)	/* 32 bit PC relative offset to GOT.  */
+    RELOC_NUMBER (R_390_GOT16, 15)	/* 16 bit GOT offset.  */
+    RELOC_NUMBER (R_390_PC16, 16)	/* PC relative 16 bit.  */
+    RELOC_NUMBER (R_390_PC12DBL, 62)	/* PC relative 12 bit shifted by 1.  */
+    RELOC_NUMBER (R_390_PLT12DBL, 63)	/* 12 bit PC rel. PLT shifted by 1.  */
+    RELOC_NUMBER (R_390_PC16DBL, 17)	/* PC relative 16 bit shifted by 1.  */
+    RELOC_NUMBER (R_390_PLT16DBL, 18)	/* 16 bit PC rel. PLT shifted by 1.  */
+    RELOC_NUMBER (R_390_PC24DBL, 64)	/* PC relative 24 bit shifted by 1.  */
+    RELOC_NUMBER (R_390_PLT24DBL, 65)	/* 24 bit PC rel. PLT shifted by 1.  */
+    RELOC_NUMBER (R_390_PC32DBL, 19)	/* PC relative 32 bit shifted by 1.  */
+    RELOC_NUMBER (R_390_PLT32DBL, 20)	/* 32 bit PC rel. PLT shifted by 1.  */
+    RELOC_NUMBER (R_390_GOTPCDBL, 21)	/* 32 bit PC rel. GOT shifted by 1.  */
+    RELOC_NUMBER (R_390_64, 22)		/* Direct 64 bit.  */
+    RELOC_NUMBER (R_390_PC64, 23)	/* PC relative 64 bit.  */
+    RELOC_NUMBER (R_390_GOT64, 24)	/* 64 bit GOT offset.  */
+    RELOC_NUMBER (R_390_PLT64, 25)	/* 64 bit PC relative PLT address.  */
+    RELOC_NUMBER (R_390_GOTENT, 26)	/* 32 bit PC rel. to GOT entry >> 1. */
+    RELOC_NUMBER (R_390_GOTOFF16, 27)   /* 16 bit offset to GOT. */
+    RELOC_NUMBER (R_390_GOTOFF64, 28)   /* 64 bit offset to GOT. */
+    RELOC_NUMBER (R_390_GOTPLT12, 29)   /* 12 bit offset to jump slot.  */
+    RELOC_NUMBER (R_390_GOTPLT16, 30)   /* 16 bit offset to jump slot.  */
+    RELOC_NUMBER (R_390_GOTPLT32, 31)   /* 32 bit offset to jump slot.  */
+    RELOC_NUMBER (R_390_GOTPLT64, 32)   /* 64 bit offset to jump slot.  */
+    RELOC_NUMBER (R_390_GOTPLTENT, 33)  /* 32 bit rel. offset to jump slot.  */
+    RELOC_NUMBER (R_390_PLTOFF16, 34)   /* 16 bit offset from GOT to PLT. */
+    RELOC_NUMBER (R_390_PLTOFF32, 35)   /* 32 bit offset from GOT to PLT. */
+    RELOC_NUMBER (R_390_PLTOFF64, 36)   /* 16 bit offset from GOT to PLT. */
+    RELOC_NUMBER (R_390_TLS_LOAD, 37)	/* Tag for load insn in TLS code. */
+    RELOC_NUMBER (R_390_TLS_GDCALL, 38)	/* Tag for function call in general
+					   dynamic TLS code.  */
+    RELOC_NUMBER (R_390_TLS_LDCALL, 39)	/* Tag for function call in local
+					   dynamic TLS code.  */
+    RELOC_NUMBER (R_390_TLS_GD32, 40)	/* Direct 32 bit for general dynamic
+					   thread local data.  */
+    RELOC_NUMBER (R_390_TLS_GD64, 41)	/* Direct 64 bit for general dynamic
+					   thread local data.  */
+    RELOC_NUMBER (R_390_TLS_GOTIE12, 42)/* 12 bit GOT offset for static TLS
+					   block offset.  */
+    RELOC_NUMBER (R_390_TLS_GOTIE32, 43)/* 32 bit GOT offset for static TLS
+					   block offset.  */
+    RELOC_NUMBER (R_390_TLS_GOTIE64, 44)/* 64 bit GOT offset for static TLS
+					   block offset.  */
+    RELOC_NUMBER (R_390_TLS_LDM32, 45)	/* Direct 32 bit for local dynamic
+					   thread local data in LD code.  */
+    RELOC_NUMBER (R_390_TLS_LDM64, 46)	/* Direct 64 bit for local dynamic
+					   thread local data in LD code.  */
+    RELOC_NUMBER (R_390_TLS_IE32, 47)	/* 32 bit address of GOT entry for
+					   negated static TLS block offset.  */
+    RELOC_NUMBER (R_390_TLS_IE64, 48)	/* 64 bit address of GOT entry for
+					   negated static TLS block offset.  */
+    RELOC_NUMBER (R_390_TLS_IEENT, 49)	/* 32 bit rel. offset to GOT entry for
+					   negated static TLS block offset.  */
+    RELOC_NUMBER (R_390_TLS_LE32, 50)	/* 32 bit negated offset relative to
+					   static TLS block.  */
+    RELOC_NUMBER (R_390_TLS_LE64, 51)	/* 64 bit negated offset relative to
+					   static TLS block.  */
+    RELOC_NUMBER (R_390_TLS_LDO32, 52)	/* 32 bit offset relative to TLS
+					   block.  */
+    RELOC_NUMBER (R_390_TLS_LDO64, 53)	/* 64 bit offset relative to TLS
+					   block.  */
+    RELOC_NUMBER (R_390_TLS_DTPMOD, 54)	/* ID of module containing symbol.  */
+    RELOC_NUMBER (R_390_TLS_DTPOFF, 55)	/* Offset in TLS block.  */
+    RELOC_NUMBER (R_390_TLS_TPOFF, 56)	/* Negate offset in static TLS
+					   block.  */
+    RELOC_NUMBER (R_390_20, 57)		/* Direct 20 bit.  */
+    RELOC_NUMBER (R_390_GOT20, 58)	/* 20 bit GOT offset.  */
+    RELOC_NUMBER (R_390_GOTPLT20, 59)	/* 20 bit offset to jump slot.  */
+    RELOC_NUMBER (R_390_TLS_GOTIE20, 60)/* 20 bit GOT offset for statis TLS
+					   block offset.  */
+    RELOC_NUMBER (R_390_IRELATIVE, 61)  /* IFUNC relocation.  */
+    /* These are GNU extensions to enable C++ vtable garbage collection.  */
+    RELOC_NUMBER (R_390_GNU_VTINHERIT, 250)
+    RELOC_NUMBER (R_390_GNU_VTENTRY, 251)
+END_RELOC_NUMBERS (R_390_max)
+
+#endif /* _ELF_390_H */
+
+
diff --git a/binutils-2.25/include/elf/score.h b/binutils-2.25/include/elf/score.h
new file mode 100644
index 00000000..8d9c026b
--- /dev/null
+++ b/binutils-2.25/include/elf/score.h
@@ -0,0 +1,130 @@
+/* Score ELF support for BFD.
+   Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
+   Contributed by 
+   Brain.lin (brain.lin@sunplusct.com)
+   Mei Ligang (ligang@sunnorth.com.cn)
+   Pei-Lin Tsai (pltsai@sunplus.com)
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_SCORE_H
+#define _ELF_SCORE_H
+
+#include "elf/reloc-macros.h"
+
+#define SCORE_SIMULATOR_ACTIVE  1
+#define OPC_PTMASK              0xc0000000      /* Parity-bit Mask.  */
+#define OPC16_PTMASK		0x00008000
+/* The parity-bit denotes.  */
+#define OPC_32                  0xc0000000      /* Denotes 32b instruction, (default).  */
+#define OPC_16                  0x00000000      /* Denotes 16b instruction.  */
+#define OPC_PE                  0x8000          /* Denotes parallel-execution instructions.  */
+#define GP_DISP_LABEL           "_gp_disp"
+
+/* Processor specific flags for the ELF header e_flags field:  */
+#define EF_SCORE_MACH           0xffff0000      
+#define EF_OMIT_PIC_FIXDD       0x0fff0000      
+#define E_SCORE_MACH_SCORE3     0x00030000
+#define E_SCORE_MACH_SCORE7     0x00070000
+
+/* File contains position independent code.  */
+#define EF_SCORE_PIC            0x80000000
+
+/* Fix data dependency.  */
+#define EF_SCORE_FIXDEP         0x40000000 
+
+/* Defined and allocated common symbol.  Value is virtual address.  If
+   relocated, alignment must be preserved.  */
+#define SHN_SCORE_TEXT		(SHN_LORESERVE + 1)
+#define SHN_SCORE_DATA		(SHN_LORESERVE + 2)
+/* Small common symbol.  */
+#define SHN_SCORE_SCOMMON	(SHN_LORESERVE + 3)
+
+/* Processor specific section flags.  */
+
+/* This section must be in the global data area.  */
+#define SHF_SCORE_GPREL		0x10000000
+
+/* This section should be merged.  */
+#define SHF_SCORE_MERGE		0x20000000
+
+/* This section contains address data of size implied by section
+   element size.  */
+#define SHF_SCORE_ADDR		0x40000000
+
+/* This section contains string data.  */
+#define SHF_SCORE_STRING		0x80000000
+
+/* This section may not be stripped.  */
+#define SHF_SCORE_NOSTRIP	0x08000000
+
+/* This section is local to threads.  */
+#define SHF_SCORE_LOCAL		0x04000000
+
+/* Linker should generate implicit weak names for this section.  */
+#define SHF_SCORE_NAMES		0x02000000
+
+/* Section contais text/data which may be replicated in other sections.
+   Linker should retain only one copy.  */
+#define SHF_SCORE_NODUPES	0x01000000
+
+/* Processor specific dynamic array tags.  */
+
+/* Base address of the segment.  */
+#define DT_SCORE_BASE_ADDRESS	0x70000001
+/* Number of local global offset table entries.  */
+#define DT_SCORE_LOCAL_GOTNO	0x70000002
+/* Number of entries in the .dynsym section.  */
+#define DT_SCORE_SYMTABNO	0x70000003
+/* Index of first dynamic symbol in global offset table.  */
+#define DT_SCORE_GOTSYM		0x70000004
+/* Index of first external dynamic symbol not referenced locally.  */
+#define DT_SCORE_UNREFEXTNO	0x70000005
+/* Number of page table entries in global offset table.  */
+#define DT_SCORE_HIPAGENO	0x70000006
+
+
+/* Processor specific section types.  */
+
+
+/* Relocation types.  */
+START_RELOC_NUMBERS (elf_score_reloc_type)
+  RELOC_NUMBER (R_SCORE_NONE,           0)
+  RELOC_NUMBER (R_SCORE_HI16,           1)   
+  RELOC_NUMBER (R_SCORE_LO16,           2)   
+  RELOC_NUMBER (R_SCORE_BCMP,           3)
+  RELOC_NUMBER (R_SCORE_24,             4)   
+  RELOC_NUMBER (R_SCORE_PC19,           5)  
+  RELOC_NUMBER (R_SCORE16_11,           6)   
+  RELOC_NUMBER (R_SCORE16_PC8,          7)  
+  RELOC_NUMBER (R_SCORE_ABS32,          8)
+  RELOC_NUMBER (R_SCORE_ABS16,          9)
+  RELOC_NUMBER (R_SCORE_DUMMY2,         10)
+  RELOC_NUMBER (R_SCORE_GP15,           11)
+  RELOC_NUMBER (R_SCORE_GNU_VTINHERIT,  12)
+  RELOC_NUMBER (R_SCORE_GNU_VTENTRY,    13)
+  RELOC_NUMBER (R_SCORE_GOT15,          14)
+  RELOC_NUMBER (R_SCORE_GOT_LO16,       15)
+  RELOC_NUMBER (R_SCORE_CALL15,         16)
+  RELOC_NUMBER (R_SCORE_GPREL32,        17)
+  RELOC_NUMBER (R_SCORE_REL32,          18)
+  RELOC_NUMBER (R_SCORE_DUMMY_HI16,     19)
+  RELOC_NUMBER (R_SCORE_IMM30,          20)
+  RELOC_NUMBER (R_SCORE_IMM32,          21)
+END_RELOC_NUMBERS (R_SCORE_max)
+
+#endif /* _ELF_SCORE_H */
diff --git a/binutils-2.25/include/elf/sh.h b/binutils-2.25/include/elf/sh.h
new file mode 100644
index 00000000..c2bd50d2
--- /dev/null
+++ b/binutils-2.25/include/elf/sh.h
@@ -0,0 +1,250 @@
+/* SH ELF support for BFD.
+   Copyright 1998, 2000, 2001, 2002, 2003, 2004, 2005, 2010
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_SH_H
+#define _ELF_SH_H
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+#define EF_SH_MACH_MASK	0x1f
+#define EF_SH_UNKNOWN	   0 /* For backwards compatibility.  */
+#define EF_SH1		   1
+#define EF_SH2		   2
+#define EF_SH3		   3
+#define EF_SH_DSP	   4
+#define EF_SH3_DSP	   5
+#define EF_SH4AL_DSP	   6
+#define EF_SH3E		   8
+#define EF_SH4		   9
+#define EF_SH2E            11
+#define EF_SH4A		   12
+#define EF_SH2A            13
+
+#define EF_SH4_NOFPU	   16
+#define EF_SH4A_NOFPU	   17
+#define EF_SH4_NOMMU_NOFPU 18
+#define EF_SH2A_NOFPU      19
+#define EF_SH3_NOMMU       20
+
+#define EF_SH2A_SH4_NOFPU  21
+#define EF_SH2A_SH3_NOFPU  22
+#define EF_SH2A_SH4        23
+#define EF_SH2A_SH3E       24
+
+/* This one can only mix in objects from other EF_SH5 objects.  */
+#define EF_SH5		  10
+
+/* Define the mapping from ELF to bfd mach numbers.
+   bfd_mach_* are defined in bfd_in2.h (generated from
+   archures.c).  */
+#define EF_SH_BFD_TABLE \
+/* EF_SH_UNKNOWN	*/ bfd_mach_sh		, \
+/* EF_SH1		*/ bfd_mach_sh		, \
+/* EF_SH2		*/ bfd_mach_sh2		, \
+/* EF_SH3		*/ bfd_mach_sh3		, \
+/* EF_SH_DSP		*/ bfd_mach_sh_dsp	, \
+/* EF_SH3_DSP		*/ bfd_mach_sh3_dsp	, \
+/* EF_SHAL_DSP		*/ bfd_mach_sh4al_dsp	, \
+/* 7			*/ 0, \
+/* EF_SH3E		*/ bfd_mach_sh3e	, \
+/* EF_SH4		*/ bfd_mach_sh4		, \
+/* EF_SH5		*/ 0, \
+/* EF_SH2E		*/ bfd_mach_sh2e	, \
+/* EF_SH4A		*/ bfd_mach_sh4a	, \
+/* EF_SH2A		*/ bfd_mach_sh2a        , \
+/* 14, 15		*/ 0, 0, \
+/* EF_SH4_NOFPU		*/ bfd_mach_sh4_nofpu	, \
+/* EF_SH4A_NOFPU	*/ bfd_mach_sh4a_nofpu	, \
+/* EF_SH4_NOMMU_NOFPU	*/ bfd_mach_sh4_nommu_nofpu, \
+/* EF_SH2A_NOFPU	*/ bfd_mach_sh2a_nofpu  , \
+/* EF_SH3_NOMMU		*/ bfd_mach_sh3_nommu   , \
+/* EF_SH2A_SH4_NOFPU    */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
+/* EF_SH2A_SH3_NOFPU    */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
+/* EF_SH2A_SH4          */ bfd_mach_sh2a_or_sh4 , \
+/* EF_SH2A_SH3E         */ bfd_mach_sh2a_or_sh3e
+
+/* Convert arch_sh* into EF_SH*.  */
+int sh_find_elf_flags (unsigned int arch_set);
+
+/* Convert bfd_mach_* into EF_SH*.  */
+int sh_elf_get_flags_from_mach (unsigned long mach);
+
+/* Other e_flags bits.  */
+
+#define EF_SH_PIC		0x100	/* Segments of an FDPIC binary may
+					   be relocated independently.  */
+#define EF_SH_FDPIC		0x8000	/* Uses the FDPIC ABI.  */
+
+/* Flags for the st_other symbol field.
+   Keep away from the STV_ visibility flags (bit 0..1).  */
+
+/* A reference to this symbol should by default add 1.  */
+#define STO_SH5_ISA32 (1 << 2)
+
+/* Section contains only SHmedia code (no SHcompact code).  */
+#define SHF_SH5_ISA32		0x40000000
+
+/* Section contains both SHmedia and SHcompact code, and possibly also
+   constants.  */
+#define SHF_SH5_ISA32_MIXED	0x20000000
+
+/* If applied to a .cranges section, marks that the section is sorted by
+   increasing cr_addr values.  */
+#define SHT_SH5_CR_SORTED 0x80000001
+
+/* Symbol should be handled as DataLabel (attached to global SHN_UNDEF
+   symbols).  */
+#define STT_DATALABEL STT_LOPROC
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+/* Relocations 10-32 and 128-255 are GNU extensions.
+   25..32 and 10 are used for relaxation.  */
+START_RELOC_NUMBERS (elf_sh_reloc_type)
+  RELOC_NUMBER (R_SH_NONE, 0)
+  RELOC_NUMBER (R_SH_DIR32, 1)
+  RELOC_NUMBER (R_SH_REL32, 2)
+  RELOC_NUMBER (R_SH_DIR8WPN, 3)
+  RELOC_NUMBER (R_SH_IND12W, 4)
+  RELOC_NUMBER (R_SH_DIR8WPL, 5)
+  RELOC_NUMBER (R_SH_DIR8WPZ, 6)
+  RELOC_NUMBER (R_SH_DIR8BP, 7)
+  RELOC_NUMBER (R_SH_DIR8W, 8)
+  RELOC_NUMBER (R_SH_DIR8L, 9)
+
+  RELOC_NUMBER (R_SH_LOOP_START, 10)
+  RELOC_NUMBER (R_SH_LOOP_END, 11)
+
+  FAKE_RELOC (R_SH_FIRST_INVALID_RELOC, 12)
+  FAKE_RELOC (R_SH_LAST_INVALID_RELOC, 21)
+
+  RELOC_NUMBER (R_SH_GNU_VTINHERIT, 22)
+  RELOC_NUMBER (R_SH_GNU_VTENTRY, 23)
+  RELOC_NUMBER (R_SH_SWITCH8, 24)
+  RELOC_NUMBER (R_SH_SWITCH16, 25)
+  RELOC_NUMBER (R_SH_SWITCH32, 26)
+  RELOC_NUMBER (R_SH_USES, 27)
+  RELOC_NUMBER (R_SH_COUNT, 28)
+  RELOC_NUMBER (R_SH_ALIGN, 29)
+  RELOC_NUMBER (R_SH_CODE, 30)
+  RELOC_NUMBER (R_SH_DATA, 31)
+  RELOC_NUMBER (R_SH_LABEL, 32)
+
+  RELOC_NUMBER (R_SH_DIR16, 33)
+  RELOC_NUMBER (R_SH_DIR8, 34)
+  RELOC_NUMBER (R_SH_DIR8UL, 35)
+  RELOC_NUMBER (R_SH_DIR8UW, 36)
+  RELOC_NUMBER (R_SH_DIR8U, 37)
+  RELOC_NUMBER (R_SH_DIR8SW, 38)
+  RELOC_NUMBER (R_SH_DIR8S, 39)
+  RELOC_NUMBER (R_SH_DIR4UL, 40)
+  RELOC_NUMBER (R_SH_DIR4UW, 41)
+  RELOC_NUMBER (R_SH_DIR4U, 42)
+  RELOC_NUMBER (R_SH_PSHA, 43)
+  RELOC_NUMBER (R_SH_PSHL, 44)
+  RELOC_NUMBER (R_SH_DIR5U, 45)
+  RELOC_NUMBER (R_SH_DIR6U, 46)
+  RELOC_NUMBER (R_SH_DIR6S, 47)
+  RELOC_NUMBER (R_SH_DIR10S, 48)
+  RELOC_NUMBER (R_SH_DIR10SW, 49)
+  RELOC_NUMBER (R_SH_DIR10SL, 50)
+  RELOC_NUMBER (R_SH_DIR10SQ, 51)
+  FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_2, 52)
+  FAKE_RELOC (R_SH_LAST_INVALID_RELOC_2, 52)
+  RELOC_NUMBER (R_SH_DIR16S, 53)
+  FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_3, 54)
+  FAKE_RELOC (R_SH_LAST_INVALID_RELOC_3, 143)
+  RELOC_NUMBER (R_SH_TLS_GD_32, 144)
+  RELOC_NUMBER (R_SH_TLS_LD_32, 145)
+  RELOC_NUMBER (R_SH_TLS_LDO_32, 146)
+  RELOC_NUMBER (R_SH_TLS_IE_32, 147)
+  RELOC_NUMBER (R_SH_TLS_LE_32, 148)
+  RELOC_NUMBER (R_SH_TLS_DTPMOD32, 149)
+  RELOC_NUMBER (R_SH_TLS_DTPOFF32, 150)
+  RELOC_NUMBER (R_SH_TLS_TPOFF32, 151)
+  FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_4, 152)
+  FAKE_RELOC (R_SH_LAST_INVALID_RELOC_4, 159)
+  RELOC_NUMBER (R_SH_GOT32, 160)
+  RELOC_NUMBER (R_SH_PLT32, 161)
+  RELOC_NUMBER (R_SH_COPY, 162)
+  RELOC_NUMBER (R_SH_GLOB_DAT, 163)
+  RELOC_NUMBER (R_SH_JMP_SLOT, 164)
+  RELOC_NUMBER (R_SH_RELATIVE, 165)
+  RELOC_NUMBER (R_SH_GOTOFF, 166)
+  RELOC_NUMBER (R_SH_GOTPC, 167)
+  RELOC_NUMBER (R_SH_GOTPLT32, 168)
+  RELOC_NUMBER (R_SH_GOT_LOW16, 169)
+  RELOC_NUMBER (R_SH_GOT_MEDLOW16, 170)
+  RELOC_NUMBER (R_SH_GOT_MEDHI16, 171)
+  RELOC_NUMBER (R_SH_GOT_HI16, 172)
+  RELOC_NUMBER (R_SH_GOTPLT_LOW16, 173)
+  RELOC_NUMBER (R_SH_GOTPLT_MEDLOW16, 174)
+  RELOC_NUMBER (R_SH_GOTPLT_MEDHI16, 175)
+  RELOC_NUMBER (R_SH_GOTPLT_HI16, 176)
+  RELOC_NUMBER (R_SH_PLT_LOW16, 177)
+  RELOC_NUMBER (R_SH_PLT_MEDLOW16, 178)
+  RELOC_NUMBER (R_SH_PLT_MEDHI16, 179)
+  RELOC_NUMBER (R_SH_PLT_HI16, 180)
+  RELOC_NUMBER (R_SH_GOTOFF_LOW16, 181)
+  RELOC_NUMBER (R_SH_GOTOFF_MEDLOW16, 182)
+  RELOC_NUMBER (R_SH_GOTOFF_MEDHI16, 183)
+  RELOC_NUMBER (R_SH_GOTOFF_HI16, 184)
+  RELOC_NUMBER (R_SH_GOTPC_LOW16, 185)
+  RELOC_NUMBER (R_SH_GOTPC_MEDLOW16, 186)
+  RELOC_NUMBER (R_SH_GOTPC_MEDHI16, 187)
+  RELOC_NUMBER (R_SH_GOTPC_HI16, 188)
+  RELOC_NUMBER (R_SH_GOT10BY4, 189)
+  RELOC_NUMBER (R_SH_GOTPLT10BY4, 190)
+  RELOC_NUMBER (R_SH_GOT10BY8, 191)
+  RELOC_NUMBER (R_SH_GOTPLT10BY8, 192)
+  RELOC_NUMBER (R_SH_COPY64, 193)
+  RELOC_NUMBER (R_SH_GLOB_DAT64, 194)
+  RELOC_NUMBER (R_SH_JMP_SLOT64, 195)
+  RELOC_NUMBER (R_SH_RELATIVE64, 196)
+  FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_5, 197)
+  FAKE_RELOC (R_SH_LAST_INVALID_RELOC_5, 200)
+  RELOC_NUMBER (R_SH_GOT20, 201)
+  RELOC_NUMBER (R_SH_GOTOFF20, 202)
+  RELOC_NUMBER (R_SH_GOTFUNCDESC, 203)
+  RELOC_NUMBER (R_SH_GOTFUNCDESC20, 204)
+  RELOC_NUMBER (R_SH_GOTOFFFUNCDESC, 205)
+  RELOC_NUMBER (R_SH_GOTOFFFUNCDESC20, 206)
+  RELOC_NUMBER (R_SH_FUNCDESC, 207)
+  RELOC_NUMBER (R_SH_FUNCDESC_VALUE, 208)
+  FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_6, 209)
+  FAKE_RELOC (R_SH_LAST_INVALID_RELOC_6, 241)
+  RELOC_NUMBER (R_SH_SHMEDIA_CODE, 242)
+  RELOC_NUMBER (R_SH_PT_16, 243)
+  RELOC_NUMBER (R_SH_IMMS16, 244)
+  RELOC_NUMBER (R_SH_IMMU16, 245)
+  RELOC_NUMBER (R_SH_IMM_LOW16, 246)
+  RELOC_NUMBER (R_SH_IMM_LOW16_PCREL, 247)
+  RELOC_NUMBER (R_SH_IMM_MEDLOW16, 248)
+  RELOC_NUMBER (R_SH_IMM_MEDLOW16_PCREL, 249)
+  RELOC_NUMBER (R_SH_IMM_MEDHI16, 250)
+  RELOC_NUMBER (R_SH_IMM_MEDHI16_PCREL, 251)
+  RELOC_NUMBER (R_SH_IMM_HI16, 252)
+  RELOC_NUMBER (R_SH_IMM_HI16_PCREL, 253)
+  RELOC_NUMBER (R_SH_64, 254)
+  RELOC_NUMBER (R_SH_64_PCREL, 255)
+END_RELOC_NUMBERS (R_SH_max)
+
+#endif
diff --git a/binutils-2.25/include/elf/sparc.h b/binutils-2.25/include/elf/sparc.h
new file mode 100644
index 00000000..d182f4d7
--- /dev/null
+++ b/binutils-2.25/include/elf/sparc.h
@@ -0,0 +1,231 @@
+/* SPARC ELF support for BFD.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2008, 2010,
+   2011
+   Free Software Foundation, Inc.
+   By Doug Evans, Cygnus Support, <dje@cygnus.com>.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _ELF_SPARC_H
+#define _ELF_SPARC_H
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+/* These are defined by Sun.  */
+
+#define EF_SPARC_32PLUS_MASK	0xffff00	/* bits indicating V8+ type */
+#define EF_SPARC_32PLUS		0x000100	/* generic V8+ features */
+#define EF_SPARC_SUN_US1	0x000200	/* Sun UltraSPARC1 extensions */
+#define EF_SPARC_HAL_R1		0x000400	/* HAL R1 extensions */
+#define EF_SPARC_SUN_US3	0x000800	/* Sun UltraSPARCIII extensions */
+
+#define EF_SPARC_LEDATA         0x800000	/* little endian data */
+
+/* This name is used in the V9 ABI.  */
+#define EF_SPARC_EXT_MASK	0xffff00	/* reserved for vendor extensions */
+
+/* V9 memory models */
+#define EF_SPARCV9_MM		0x3		/* memory model mask */
+#define EF_SPARCV9_TSO		0x0		/* total store ordering */
+#define EF_SPARCV9_PSO		0x1		/* partial store ordering */
+#define EF_SPARCV9_RMO		0x2		/* relaxed store ordering */
+
+/* Section indices.  */
+
+#define SHN_BEFORE	SHN_LORESERVE		/* Used with SHF_ORDERED and...  */
+#define SHN_AFTER	(SHN_LORESERVE + 1)	/* SHF_LINK_ORDER section flags. */
+
+/* Section flags.  */
+
+#define SHF_ORDERED		0x40000000	/* treat sh_link,sh_info specially */
+
+/* Symbol types.  */
+
+#define STT_REGISTER		13		/* global reg reserved to app. */
+
+#include "elf/reloc-macros.h"
+
+/* Relocation types.  */
+START_RELOC_NUMBERS (elf_sparc_reloc_type)
+  RELOC_NUMBER (R_SPARC_NONE, 0)
+  RELOC_NUMBER (R_SPARC_8, 1)
+  RELOC_NUMBER (R_SPARC_16, 2)
+  RELOC_NUMBER (R_SPARC_32, 3)
+  RELOC_NUMBER (R_SPARC_DISP8, 4)
+  RELOC_NUMBER (R_SPARC_DISP16, 5)
+  RELOC_NUMBER (R_SPARC_DISP32, 6)
+  RELOC_NUMBER (R_SPARC_WDISP30, 7)
+  RELOC_NUMBER (R_SPARC_WDISP22, 8)
+  RELOC_NUMBER (R_SPARC_HI22, 9)
+  RELOC_NUMBER (R_SPARC_22, 10)
+  RELOC_NUMBER (R_SPARC_13, 11)
+  RELOC_NUMBER (R_SPARC_LO10, 12)
+  RELOC_NUMBER (R_SPARC_GOT10, 13)
+  RELOC_NUMBER (R_SPARC_GOT13, 14)
+  RELOC_NUMBER (R_SPARC_GOT22, 15)
+  RELOC_NUMBER (R_SPARC_PC10, 16)
+  RELOC_NUMBER (R_SPARC_PC22, 17)
+  RELOC_NUMBER (R_SPARC_WPLT30, 18)
+  RELOC_NUMBER (R_SPARC_COPY, 19)
+  RELOC_NUMBER (R_SPARC_GLOB_DAT, 20)
+  RELOC_NUMBER (R_SPARC_JMP_SLOT, 21)
+  RELOC_NUMBER (R_SPARC_RELATIVE, 22)
+  RELOC_NUMBER (R_SPARC_UA32, 23)
+
+  /* ??? These 6 relocs are new but not currently used.  For binary
+     compatibility in the sparc64-elf toolchain, we leave them out.
+     A non-binary upward compatible change is expected for sparc64-elf.  */
+#ifndef SPARC64_OLD_RELOCS
+  /* ??? New relocs on the UltraSPARC.  Not sure what they're for yet.  */
+  RELOC_NUMBER (R_SPARC_PLT32, 24)
+  RELOC_NUMBER (R_SPARC_HIPLT22, 25)
+  RELOC_NUMBER (R_SPARC_LOPLT10, 26)
+  RELOC_NUMBER (R_SPARC_PCPLT32, 27)
+  RELOC_NUMBER (R_SPARC_PCPLT22, 28)
+  RELOC_NUMBER (R_SPARC_PCPLT10, 29)
+#endif
+
+  /* v9 relocs */
+  RELOC_NUMBER (R_SPARC_10, 30)
+  RELOC_NUMBER (R_SPARC_11, 31)
+  RELOC_NUMBER (R_SPARC_64, 32)
+  RELOC_NUMBER (R_SPARC_OLO10, 33)
+  RELOC_NUMBER (R_SPARC_HH22, 34)
+  RELOC_NUMBER (R_SPARC_HM10, 35)
+  RELOC_NUMBER (R_SPARC_LM22, 36)
+  RELOC_NUMBER (R_SPARC_PC_HH22, 37)
+  RELOC_NUMBER (R_SPARC_PC_HM10, 38)
+  RELOC_NUMBER (R_SPARC_PC_LM22, 39)
+  RELOC_NUMBER (R_SPARC_WDISP16, 40)
+  RELOC_NUMBER (R_SPARC_WDISP19, 41)
+  RELOC_NUMBER (R_SPARC_UNUSED_42, 42)
+  RELOC_NUMBER (R_SPARC_7, 43)
+  RELOC_NUMBER (R_SPARC_5, 44)
+  RELOC_NUMBER (R_SPARC_6, 45)
+  RELOC_NUMBER (R_SPARC_DISP64, 46)
+  RELOC_NUMBER (R_SPARC_PLT64, 47)
+  RELOC_NUMBER (R_SPARC_HIX22, 48)
+  RELOC_NUMBER (R_SPARC_LOX10, 49)
+  RELOC_NUMBER (R_SPARC_H44, 50)
+  RELOC_NUMBER (R_SPARC_M44, 51)
+  RELOC_NUMBER (R_SPARC_L44, 52)
+  RELOC_NUMBER (R_SPARC_REGISTER, 53)
+  RELOC_NUMBER (R_SPARC_UA64, 54)
+  RELOC_NUMBER (R_SPARC_UA16, 55)
+
+  RELOC_NUMBER (R_SPARC_TLS_GD_HI22, 56)
+  RELOC_NUMBER (R_SPARC_TLS_GD_LO10, 57)
+  RELOC_NUMBER (R_SPARC_TLS_GD_ADD, 58)
+  RELOC_NUMBER (R_SPARC_TLS_GD_CALL, 59)
+  RELOC_NUMBER (R_SPARC_TLS_LDM_HI22, 60)
+  RELOC_NUMBER (R_SPARC_TLS_LDM_LO10, 61)
+  RELOC_NUMBER (R_SPARC_TLS_LDM_ADD, 62)
+  RELOC_NUMBER (R_SPARC_TLS_LDM_CALL, 63)
+  RELOC_NUMBER (R_SPARC_TLS_LDO_HIX22, 64)
+  RELOC_NUMBER (R_SPARC_TLS_LDO_LOX10, 65)
+  RELOC_NUMBER (R_SPARC_TLS_LDO_ADD, 66)
+  RELOC_NUMBER (R_SPARC_TLS_IE_HI22, 67)
+  RELOC_NUMBER (R_SPARC_TLS_IE_LO10, 68)
+  RELOC_NUMBER (R_SPARC_TLS_IE_LD, 69)
+  RELOC_NUMBER (R_SPARC_TLS_IE_LDX, 70)
+  RELOC_NUMBER (R_SPARC_TLS_IE_ADD, 71)
+  RELOC_NUMBER (R_SPARC_TLS_LE_HIX22, 72)
+  RELOC_NUMBER (R_SPARC_TLS_LE_LOX10, 73)
+  RELOC_NUMBER (R_SPARC_TLS_DTPMOD32, 74)
+  RELOC_NUMBER (R_SPARC_TLS_DTPMOD64, 75)
+  RELOC_NUMBER (R_SPARC_TLS_DTPOFF32, 76)
+  RELOC_NUMBER (R_SPARC_TLS_DTPOFF64, 77)
+  RELOC_NUMBER (R_SPARC_TLS_TPOFF32, 78)
+  RELOC_NUMBER (R_SPARC_TLS_TPOFF64, 79)
+
+  RELOC_NUMBER (R_SPARC_GOTDATA_HIX22, 80)
+  RELOC_NUMBER (R_SPARC_GOTDATA_LOX10, 81)
+  RELOC_NUMBER (R_SPARC_GOTDATA_OP_HIX22, 82)
+  RELOC_NUMBER (R_SPARC_GOTDATA_OP_LOX10, 83)
+  RELOC_NUMBER (R_SPARC_GOTDATA_OP, 84)
+
+  RELOC_NUMBER (R_SPARC_H34, 85)
+  RELOC_NUMBER (R_SPARC_SIZE32, 86)
+  RELOC_NUMBER (R_SPARC_SIZE64, 87)
+  RELOC_NUMBER (R_SPARC_WDISP10, 88)
+  
+  EMPTY_RELOC  (R_SPARC_max_std)
+
+  RELOC_NUMBER (R_SPARC_JMP_IREL, 248)
+  RELOC_NUMBER (R_SPARC_IRELATIVE, 249)
+  RELOC_NUMBER (R_SPARC_GNU_VTINHERIT, 250)
+  RELOC_NUMBER (R_SPARC_GNU_VTENTRY, 251)
+  RELOC_NUMBER (R_SPARC_REV32, 252)
+
+END_RELOC_NUMBERS (R_SPARC_max)
+
+/* Relocation macros.  */
+
+#define ELF64_R_TYPE_DATA(info) \
+  (((bfd_signed_vma)(ELF64_R_TYPE(info) >> 8) ^ 0x800000) - 0x800000)
+#define ELF64_R_TYPE_ID(info) \
+  ((info) & 0xff)
+#define ELF64_R_TYPE_INFO(data, type) \
+  (((bfd_vma) ((data) & 0xffffff) << 8) | (bfd_vma) (type))
+
+/* Values for Elf64_Dyn.d_tag.  */
+
+#define DT_SPARC_REGISTER	0x70000001
+
+/* Object attribute tags.  */
+enum
+{
+  /* 0-3 are generic.  */
+  Tag_GNU_Sparc_HWCAPS = 4,
+};
+
+/* These values match the AV_SPARC_* hwcap bits defined under Solaris.  */
+#define ELF_SPARC_HWCAP_MUL32	0x00000001 /* umul/umulcc/smul/smulcc insns */
+#define ELF_SPARC_HWCAP_DIV32	0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
+#define ELF_SPARC_HWCAP_FSMULD	0x00000004 /* 'fsmuld' insn */
+#define ELF_SPARC_HWCAP_V8PLUS	0x00000008 /* v9 insns available to 32bit */
+#define ELF_SPARC_HWCAP_POPC	0x00000010 /* 'popc' insn */
+#define ELF_SPARC_HWCAP_VIS	0x00000020 /* VIS insns */
+#define ELF_SPARC_HWCAP_VIS2	0x00000040 /* VIS2 insns */
+#define ELF_SPARC_HWCAP_ASI_BLK_INIT	\
+				0x00000080 /* block init ASIs */
+#define ELF_SPARC_HWCAP_FMAF	0x00000100 /* fused multiply-add */
+#define ELF_SPARC_HWCAP_VIS3	0x00000400 /* VIS3 insns */
+#define ELF_SPARC_HWCAP_HPC	0x00000800 /* HPC insns */
+#define ELF_SPARC_HWCAP_RANDOM	0x00001000 /* 'random' insn */
+#define ELF_SPARC_HWCAP_TRANS	0x00002000 /* transaction insns */
+#define ELF_SPARC_HWCAP_FJFMAU	0x00004000 /* unfused multiply-add */
+#define ELF_SPARC_HWCAP_IMA	0x00008000 /* integer multiply-add */
+#define ELF_SPARC_HWCAP_ASI_CACHE_SPARING \
+				0x00010000 /* cache sparing ASIs */
+#define ELF_SPARC_HWCAP_AES	0x00020000 /* AES crypto insns */
+#define ELF_SPARC_HWCAP_DES	0x00040000 /* DES crypto insns */
+#define ELF_SPARC_HWCAP_KASUMI	0x00080000 /* KASUMI crypto insns */
+#define ELF_SPARC_HWCAP_CAMELLIA \
+				0x00100000 /* CAMELLIA crypto insns */
+#define ELF_SPARC_HWCAP_MD5	0x00200000 /* MD5 hashing insns */
+#define ELF_SPARC_HWCAP_SHA1	0x00400000 /* SHA1 hashing insns */
+#define ELF_SPARC_HWCAP_SHA256	0x00800000 /* SHA256 hashing insns */
+#define ELF_SPARC_HWCAP_SHA512	0x01000000 /* SHA512 hashing insns */
+#define ELF_SPARC_HWCAP_MPMUL	0x02000000 /* Multiple Precision Multiply */
+#define ELF_SPARC_HWCAP_MONT	0x04000000 /* Montgomery Mult/Sqrt */
+#define ELF_SPARC_HWCAP_PAUSE	0x08000000 /* Pause insn */
+#define ELF_SPARC_HWCAP_CBCOND	0x10000000 /* Compare and Branch insns */
+#define ELF_SPARC_HWCAP_CRC32C	0x20000000 /* CRC32C insn */
+
+#endif /* _ELF_SPARC_H */
diff --git a/binutils-2.25/include/elf/spu.h b/binutils-2.25/include/elf/spu.h
new file mode 100644
index 00000000..0618ec8f
--- /dev/null
+++ b/binutils-2.25/include/elf/spu.h
@@ -0,0 +1,61 @@
+/* SPU ELF support for BFD.
+
+   Copyright 2006, 2007, 2009, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_SPU_H
+#define _ELF_SPU_H
+
+#include "elf/reloc-macros.h"
+
+/* elf32-spu.c depends on these being consecutive. */
+START_RELOC_NUMBERS (elf_spu_reloc_type)
+     RELOC_NUMBER (R_SPU_NONE,		 0)
+     RELOC_NUMBER (R_SPU_ADDR10,	 1)
+     RELOC_NUMBER (R_SPU_ADDR16,	 2)
+     RELOC_NUMBER (R_SPU_ADDR16_HI,	 3)
+     RELOC_NUMBER (R_SPU_ADDR16_LO,	 4)
+     RELOC_NUMBER (R_SPU_ADDR18,	 5)
+     RELOC_NUMBER (R_SPU_ADDR32,	 6)
+     RELOC_NUMBER (R_SPU_REL16,		 7)
+     RELOC_NUMBER (R_SPU_ADDR7,		 8)
+     RELOC_NUMBER (R_SPU_REL9,		 9)
+     RELOC_NUMBER (R_SPU_REL9I,		10)
+     RELOC_NUMBER (R_SPU_ADDR10I,	11)
+     RELOC_NUMBER (R_SPU_ADDR16I,	12)
+     RELOC_NUMBER (R_SPU_REL32,		13)
+     RELOC_NUMBER (R_SPU_ADDR16X,	14)
+     RELOC_NUMBER (R_SPU_PPU32,		15)
+     RELOC_NUMBER (R_SPU_PPU64,		16)
+     RELOC_NUMBER (R_SPU_ADD_PIC,	17)
+END_RELOC_NUMBERS (R_SPU_max)
+
+/* Program header extensions */
+
+/* Mark a PT_LOAD segment as containing an overlay which should not
+   initially be loaded.  */
+#define PF_OVERLAY		(1 << 27)
+
+/* SPU Dynamic Object Information.  */
+#define PT_SPU_INFO             0x70000000
+
+/* SPU plugin information */
+#define SPU_PLUGIN_NAME         "SPUNAME"
+#define SPU_PTNOTE_SPUNAME	".note.spu_name"
+
+#endif /* _ELF_SPU_H */
diff --git a/binutils-2.25/include/elf/tic6x-attrs.h b/binutils-2.25/include/elf/tic6x-attrs.h
new file mode 100644
index 00000000..21ce1e4f
--- /dev/null
+++ b/binutils-2.25/include/elf/tic6x-attrs.h
@@ -0,0 +1,35 @@
+/* TI C6X ELF attributes.
+   Copyright 2010
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* Define the TAG macro before including this file; it takes a tag
+   name and value.  */
+
+TAG(Tag_ISA, 4)
+TAG(Tag_ABI_wchar_t, 6)
+TAG(Tag_ABI_stack_align_needed, 8)
+TAG(Tag_ABI_stack_align_preserved, 10)
+TAG(Tag_ABI_DSBT, 12)
+TAG(Tag_ABI_PID, 14)
+TAG(Tag_ABI_PIC, 16)
+TAG(Tag_ABI_array_object_alignment, 18)
+TAG(Tag_ABI_array_object_align_expected, 20)
+TAG(Tag_ABI_compatibility, 32)
+TAG(Tag_ABI_conformance, 67)
diff --git a/binutils-2.25/include/elf/tic6x.h b/binutils-2.25/include/elf/tic6x.h
new file mode 100644
index 00000000..e686cc3a
--- /dev/null
+++ b/binutils-2.25/include/elf/tic6x.h
@@ -0,0 +1,167 @@
+/* TI C6X ELF support for BFD.
+   Copyright 2010, 2011
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _ELF_TIC6X_H
+#define _ELF_TIC6X_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocation types.  */
+START_RELOC_NUMBERS (elf_tic6x_reloc_type)
+  RELOC_NUMBER (R_C6000_NONE, 0)
+  RELOC_NUMBER (R_C6000_ABS32, 1)
+  RELOC_NUMBER (R_C6000_ABS16, 2)
+  RELOC_NUMBER (R_C6000_ABS8, 3)
+  RELOC_NUMBER (R_C6000_PCR_S21, 4)
+  RELOC_NUMBER (R_C6000_PCR_S12, 5)
+  RELOC_NUMBER (R_C6000_PCR_S10, 6)
+  RELOC_NUMBER (R_C6000_PCR_S7, 7)
+  RELOC_NUMBER (R_C6000_ABS_S16, 8)
+  RELOC_NUMBER (R_C6000_ABS_L16, 9)
+  RELOC_NUMBER (R_C6000_ABS_H16, 10)
+  RELOC_NUMBER (R_C6000_SBR_U15_B, 11)
+  RELOC_NUMBER (R_C6000_SBR_U15_H, 12)
+  RELOC_NUMBER (R_C6000_SBR_U15_W, 13)
+  RELOC_NUMBER (R_C6000_SBR_S16, 14)
+  RELOC_NUMBER (R_C6000_SBR_L16_B, 15)
+  RELOC_NUMBER (R_C6000_SBR_L16_H, 16)
+  RELOC_NUMBER (R_C6000_SBR_L16_W, 17)
+  RELOC_NUMBER (R_C6000_SBR_H16_B, 18)
+  RELOC_NUMBER (R_C6000_SBR_H16_H, 19)
+  RELOC_NUMBER (R_C6000_SBR_H16_W, 20)
+  RELOC_NUMBER (R_C6000_SBR_GOT_U15_W, 21)
+  RELOC_NUMBER (R_C6000_SBR_GOT_L16_W, 22)
+  RELOC_NUMBER (R_C6000_SBR_GOT_H16_W, 23)
+  RELOC_NUMBER (R_C6000_DSBT_INDEX, 24)
+  RELOC_NUMBER (R_C6000_PREL31, 25)
+  RELOC_NUMBER (R_C6000_COPY, 26)
+  RELOC_NUMBER (R_C6000_JUMP_SLOT, 27)
+  RELOC_NUMBER (R_C6000_EHTYPE, 28)
+  RELOC_NUMBER (R_C6000_PCR_H16, 29)
+  RELOC_NUMBER (R_C6000_PCR_L16, 30)
+  RELOC_NUMBER (R_C6000_ALIGN, 253)
+  RELOC_NUMBER (R_C6000_FPHEAD, 254)
+  RELOC_NUMBER (R_C6000_NOCMP, 255)
+END_RELOC_NUMBERS (R_TIC6X_max)
+
+/* Processor-specific flags.  */
+
+/* File contains static relocation information.  */
+#define EF_C6000_REL		0x1
+
+/* Processor-specific section types.  */
+
+/* Unwind function table for stack unwinding.  */
+#define SHT_C6000_UNWIND	0x70000001
+
+/* DLL dynamic linking pre-emption map.  */
+#define SHT_C6000_PREEMPTMAP	0x70000002
+
+/* Object file compatibility attributes.  */
+#define SHT_C6000_ATTRIBUTES	0x70000003
+
+/* Intermediate code for link-time optimization.  */
+#define SHT_TI_ICODE		0x7F000000
+
+/* Symbolic cross reference information.  */
+#define SHT_TI_XREF		0x7F000001
+
+/* Reserved.  */
+#define SHT_TI_HANDLER		0x7F000002
+
+/* Compressed data for initializing C variables.  */
+#define SHT_TI_INITINFO		0x7F000003
+
+/* Extended program header attributes.  */
+#define SHT_TI_PHATTRS		0x7F000004
+
+/* Processor specific section indices.  These sections do not actually
+   exist.  Symbols with a st_shndx field corresponding to one of these
+   values have a special meaning.  */
+
+/* Small data area common symbol.  */
+#define SHN_TIC6X_SCOMMON	SHN_LORESERVE
+
+/* Processor-specific segment types.  */
+
+/* Extended Segment Attributes.  */
+#define PT_C6000_PHATTR		0x70000000
+
+/* Processor-specific dynamic tags.  */
+
+/* Undocumented.  */
+#define DT_C6000_GSYM_OFFSET	0x6000000D
+
+/* Undocumented.  */
+#define DT_C6000_GSTR_OFFSET	0x6000000F
+
+/* Statically linked base address of data segment.  */
+#define DT_C6000_DSBT_BASE	0x70000000
+
+/* Number of entries in this module's DSBT.  */
+#define DT_C6000_DSBT_SIZE	0x70000001
+
+/* Undocumented.  */
+#define DT_C6000_PREEMPTMAP	0x70000002
+
+/* The hard-coded DSBT index for this module, if any.  */
+#define DT_C6000_DSBT_INDEX	0x70000003
+
+/* Extended program header attributes.  */
+
+/* Terminate a segment.  */
+#define PHA_NULL		0x0
+
+/* Segment's address bound to the final address.  */
+#define PHA_BOUND		0x1
+
+/* Segment cannot be further relocated.  */
+#define PHA_READONLY		0x2
+
+/* Build attributes.  */
+enum
+  {
+#define TAG(tag, value) tag = value,
+#include "elf/tic6x-attrs.h"
+#undef TAG
+    Tag_C6XABI_last
+  };
+
+/* Values for Tag_ISA.  GNU-specific names; the ABI does not specify
+   names for these values.  */
+enum
+  {
+    C6XABI_Tag_ISA_none = 0,
+    C6XABI_Tag_ISA_C62X = 1,
+    C6XABI_Tag_ISA_C67X = 3,
+    C6XABI_Tag_ISA_C67XP = 4,
+    C6XABI_Tag_ISA_C64X = 6,
+    C6XABI_Tag_ISA_C64XP = 7,
+    C6XABI_Tag_ISA_C674X = 8
+  };
+
+/* Special section names.  */
+#define ELF_STRING_C6000_unwind           ".c6xabi.exidx"
+#define ELF_STRING_C6000_unwind_info      ".c6xabi.extab"
+#define ELF_STRING_C6000_unwind_once      ".gnu.linkonce.c6xabi.exidx."
+#define ELF_STRING_C6000_unwind_info_once ".gnu.linkonce.c6xabi.extab."
+
+#endif /* _ELF_TIC6X_H */
diff --git a/binutils-2.25/include/elf/tilegx.h b/binutils-2.25/include/elf/tilegx.h
new file mode 100644
index 00000000..e838b809
--- /dev/null
+++ b/binutils-2.25/include/elf/tilegx.h
@@ -0,0 +1,176 @@
+/* TILE-Gx ELF support for BFD.
+   Copyright 2011 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _ELF_TILEGX_H
+#define _ELF_TILEGX_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_tilegx_reloc_type)
+  RELOC_NUMBER (R_TILEGX_NONE,              0)
+
+  /* Standard relocations */
+  RELOC_NUMBER (R_TILEGX_64,                1)
+  RELOC_NUMBER (R_TILEGX_32,                2)
+  RELOC_NUMBER (R_TILEGX_16,                3)
+  RELOC_NUMBER (R_TILEGX_8,                 4)
+  RELOC_NUMBER (R_TILEGX_64_PCREL,          5)
+  RELOC_NUMBER (R_TILEGX_32_PCREL,          6)
+  RELOC_NUMBER (R_TILEGX_16_PCREL,          7)
+  RELOC_NUMBER (R_TILEGX_8_PCREL,           8)
+
+  /* Custom relocations */
+
+  RELOC_NUMBER (R_TILEGX_HW0,               9)
+  RELOC_NUMBER (R_TILEGX_HW1,               10)
+  RELOC_NUMBER (R_TILEGX_HW2,               11)
+  RELOC_NUMBER (R_TILEGX_HW3,               12)
+  RELOC_NUMBER (R_TILEGX_HW0_LAST,          13)
+  RELOC_NUMBER (R_TILEGX_HW1_LAST,          14)
+  RELOC_NUMBER (R_TILEGX_HW2_LAST,          15)
+
+  RELOC_NUMBER (R_TILEGX_COPY,              16)
+  RELOC_NUMBER (R_TILEGX_GLOB_DAT,          17)
+  RELOC_NUMBER (R_TILEGX_JMP_SLOT,          18)
+  RELOC_NUMBER (R_TILEGX_RELATIVE,          19)
+
+  /* Branch/jump offsets */
+  RELOC_NUMBER (R_TILEGX_BROFF_X1,          20)
+  RELOC_NUMBER (R_TILEGX_JUMPOFF_X1,        21)
+  RELOC_NUMBER (R_TILEGX_JUMPOFF_X1_PLT,    22)
+
+  /* Immediate operands. */
+  RELOC_NUMBER (R_TILEGX_IMM8_X0,           23)
+  RELOC_NUMBER (R_TILEGX_IMM8_Y0,           24)
+  RELOC_NUMBER (R_TILEGX_IMM8_X1,           25)
+  RELOC_NUMBER (R_TILEGX_IMM8_Y1,           26)
+  RELOC_NUMBER (R_TILEGX_DEST_IMM8_X1,      27)
+  RELOC_NUMBER (R_TILEGX_MT_IMM14_X1,       28)
+  RELOC_NUMBER (R_TILEGX_MF_IMM14_X1,       29)
+  RELOC_NUMBER (R_TILEGX_MMSTART_X0,        30)
+  RELOC_NUMBER (R_TILEGX_MMEND_X0,          31)
+  RELOC_NUMBER (R_TILEGX_SHAMT_X0,          32)
+  RELOC_NUMBER (R_TILEGX_SHAMT_X1,          33)
+  RELOC_NUMBER (R_TILEGX_SHAMT_Y0,          34)
+  RELOC_NUMBER (R_TILEGX_SHAMT_Y1,          35)
+
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0,       36)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0,       37)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW1,       38)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW1,       39)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW2,       40)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW2,       41)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW3,       42)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW3,       43)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_LAST,  44)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_LAST,  45)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW1_LAST,  46)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW1_LAST,  47)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW2_LAST,  48)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW2_LAST,  49)
+
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_PCREL,        50)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_PCREL,        51)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW1_PCREL,        52)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW1_PCREL,        53)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW2_PCREL,        54)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW2_PCREL,        55)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW3_PCREL,        56)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW3_PCREL,        57)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_LAST_PCREL,   58)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_LAST_PCREL,   59)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW1_LAST_PCREL,   60)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW1_LAST_PCREL,   61)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW2_LAST_PCREL,   62)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW2_LAST_PCREL,   63)
+
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_GOT,          64)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_GOT,          65)
+
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_PLT_PCREL,    66)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_PLT_PCREL,    67)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW1_PLT_PCREL,    68)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW1_PLT_PCREL,    69)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW2_PLT_PCREL,    70)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW2_PLT_PCREL,    71)
+
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_LAST_GOT,     72)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_LAST_GOT,     73)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW1_LAST_GOT,     74)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW1_LAST_GOT,     75)
+
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW3_PLT_PCREL,    76)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW3_PLT_PCREL,    77)
+
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_TLS_GD,       78)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_TLS_GD,       79)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_TLS_LE,       80)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_TLS_LE,       81)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE,  82)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE,  83)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE,  84)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE,  85)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD,  86)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD,  87)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD,  88)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD,  89)
+  /* Relocs 90-91 are currently not defined.  */
+
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_TLS_IE,       92)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_TLS_IE,       93)
+
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL, 94)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL, 95)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL, 96)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL, 97)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL, 98)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL, 99)
+
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE, 100)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE, 101)
+  RELOC_NUMBER (R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE, 102)
+  RELOC_NUMBER (R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE, 103)
+  /* Relocs 104-105 are currently not defined.  */
+
+  RELOC_NUMBER (R_TILEGX_TLS_DTPMOD64,             106)
+  RELOC_NUMBER (R_TILEGX_TLS_DTPOFF64,             107)
+  RELOC_NUMBER (R_TILEGX_TLS_TPOFF64,              108)
+  RELOC_NUMBER (R_TILEGX_TLS_DTPMOD32,             109)
+  RELOC_NUMBER (R_TILEGX_TLS_DTPOFF32,             110)
+  RELOC_NUMBER (R_TILEGX_TLS_TPOFF32,              111)
+
+  RELOC_NUMBER (R_TILEGX_TLS_GD_CALL,              112)
+  RELOC_NUMBER (R_TILEGX_IMM8_X0_TLS_GD_ADD,       113)
+  RELOC_NUMBER (R_TILEGX_IMM8_X1_TLS_GD_ADD,       114)
+  RELOC_NUMBER (R_TILEGX_IMM8_Y0_TLS_GD_ADD,       115)
+  RELOC_NUMBER (R_TILEGX_IMM8_Y1_TLS_GD_ADD,       116)
+  RELOC_NUMBER (R_TILEGX_TLS_IE_LOAD,              117)
+  RELOC_NUMBER (R_TILEGX_IMM8_X0_TLS_ADD,          118)
+  RELOC_NUMBER (R_TILEGX_IMM8_X1_TLS_ADD,          119)
+  RELOC_NUMBER (R_TILEGX_IMM8_Y0_TLS_ADD,          120)
+  RELOC_NUMBER (R_TILEGX_IMM8_Y1_TLS_ADD,          121)
+
+/* These are GNU extensions to enable C++ vtable garbage collection.  */
+  RELOC_NUMBER (R_TILEGX_GNU_VTINHERIT, 128)
+  RELOC_NUMBER (R_TILEGX_GNU_VTENTRY, 129)
+END_RELOC_NUMBERS (R_TILEGX_max)
+
+#endif /* _ELF_TILEGX_H */
diff --git a/binutils-2.25/include/elf/tilepro.h b/binutils-2.25/include/elf/tilepro.h
new file mode 100644
index 00000000..0079a2fe
--- /dev/null
+++ b/binutils-2.25/include/elf/tilepro.h
@@ -0,0 +1,144 @@
+/* TILEPro ELF support for BFD.
+   Copyright 2011 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _ELF_TILEPRO_H
+#define _ELF_TILEPRO_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_tilepro_reloc_type)
+  RELOC_NUMBER (R_TILEPRO_NONE,        0)
+
+  /* Standard relocations */
+  RELOC_NUMBER (R_TILEPRO_32,                  1)
+  RELOC_NUMBER (R_TILEPRO_16,                  2)
+  RELOC_NUMBER (R_TILEPRO_8,                   3)
+  RELOC_NUMBER (R_TILEPRO_32_PCREL,            4)
+  RELOC_NUMBER (R_TILEPRO_16_PCREL,            5)
+  RELOC_NUMBER (R_TILEPRO_8_PCREL,             6)
+
+  RELOC_NUMBER (R_TILEPRO_LO16,                7)
+  RELOC_NUMBER (R_TILEPRO_HI16,                8)
+  RELOC_NUMBER (R_TILEPRO_HA16,                9)
+
+  RELOC_NUMBER (R_TILEPRO_COPY,               10)
+  RELOC_NUMBER (R_TILEPRO_GLOB_DAT,           11)
+  RELOC_NUMBER (R_TILEPRO_JMP_SLOT,           12)
+  RELOC_NUMBER (R_TILEPRO_RELATIVE,           13)
+
+  /* Branch/jump offsets */
+  RELOC_NUMBER (R_TILEPRO_BROFF_X1,           14)
+  RELOC_NUMBER (R_TILEPRO_JOFFLONG_X1,        15)
+  RELOC_NUMBER (R_TILEPRO_JOFFLONG_X1_PLT,    16)
+
+  /* Immediate operands. */
+  RELOC_NUMBER (R_TILEPRO_IMM8_X0,            17)
+  RELOC_NUMBER (R_TILEPRO_IMM8_Y0,            18)
+  RELOC_NUMBER (R_TILEPRO_IMM8_X1,            19)
+  RELOC_NUMBER (R_TILEPRO_IMM8_Y1,            20)
+  RELOC_NUMBER (R_TILEPRO_MT_IMM15_X1,        21)
+  RELOC_NUMBER (R_TILEPRO_MF_IMM15_X1,        22)
+
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0,           23)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1,           24)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_LO,        25)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_LO,        26)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_HI,        27)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_HI,        28)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_HA,        29)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_HA,        30)
+
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_PCREL,     31)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_PCREL,     32)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_LO_PCREL,  33)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_LO_PCREL,  34)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_HI_PCREL,  35)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_HI_PCREL,  36)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_HA_PCREL,  37)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_HA_PCREL,  38)
+
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_GOT,       39)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_GOT,       40)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_GOT_LO,    41)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_GOT_LO,    42)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_GOT_HI,    43)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_GOT_HI,    44)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_GOT_HA,    45)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_GOT_HA,    46)
+
+  RELOC_NUMBER (R_TILEPRO_MMSTART_X0,         47)
+  RELOC_NUMBER (R_TILEPRO_MMEND_X0,           48)
+  RELOC_NUMBER (R_TILEPRO_MMSTART_X1,         49)
+  RELOC_NUMBER (R_TILEPRO_MMEND_X1,           50)
+
+  RELOC_NUMBER (R_TILEPRO_SHAMT_X0,           51)
+  RELOC_NUMBER (R_TILEPRO_SHAMT_X1,           52)
+  RELOC_NUMBER (R_TILEPRO_SHAMT_Y0,           53)
+  RELOC_NUMBER (R_TILEPRO_SHAMT_Y1,           54)
+
+  RELOC_NUMBER (R_TILEPRO_DEST_IMM8_X1,       55)
+
+  /* Relocs 56-59 are currently not defined.  */
+
+  RELOC_NUMBER (R_TILEPRO_TLS_GD_CALL,        60)
+  RELOC_NUMBER (R_TILEPRO_IMM8_X0_TLS_GD_ADD, 61)
+  RELOC_NUMBER (R_TILEPRO_IMM8_X1_TLS_GD_ADD, 62)
+  RELOC_NUMBER (R_TILEPRO_IMM8_Y0_TLS_GD_ADD, 63)
+  RELOC_NUMBER (R_TILEPRO_IMM8_Y1_TLS_GD_ADD, 64)
+  RELOC_NUMBER (R_TILEPRO_TLS_IE_LOAD,        65)
+
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_TLS_GD,    66)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_TLS_GD,    67)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_TLS_GD_LO, 68)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_TLS_GD_LO, 69)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_TLS_GD_HI, 70)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_TLS_GD_HI, 71)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_TLS_GD_HA, 72)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_TLS_GD_HA, 73)
+
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_TLS_IE,    74)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_TLS_IE,    75)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_TLS_IE_LO, 76)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_TLS_IE_LO, 77)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_TLS_IE_HI, 78)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_TLS_IE_HI, 79)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_TLS_IE_HA, 80)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_TLS_IE_HA, 81)
+
+  RELOC_NUMBER (R_TILEPRO_TLS_DTPMOD32,       82)
+  RELOC_NUMBER (R_TILEPRO_TLS_DTPOFF32,       83)
+  RELOC_NUMBER (R_TILEPRO_TLS_TPOFF32,        84)
+
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_TLS_LE,    85)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_TLS_LE,    86)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_TLS_LE_LO, 87)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_TLS_LE_LO, 88)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_TLS_LE_HI, 89)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_TLS_LE_HI, 90)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X0_TLS_LE_HA, 91)
+  RELOC_NUMBER (R_TILEPRO_IMM16_X1_TLS_LE_HA, 92)
+
+/* These are GNU extensions to enable C++ vtable garbage collection.  */
+  RELOC_NUMBER (R_TILEPRO_GNU_VTINHERIT, 128)
+  RELOC_NUMBER (R_TILEPRO_GNU_VTENTRY, 129)
+END_RELOC_NUMBERS (R_TILEPRO_max)
+
+#endif /* _ELF_TILEPRO_H */
diff --git a/binutils-2.25/include/elf/v850.h b/binutils-2.25/include/elf/v850.h
new file mode 100644
index 00000000..5a088202
--- /dev/null
+++ b/binutils-2.25/include/elf/v850.h
@@ -0,0 +1,283 @@
+/* V850 ELF support for BFD.
+   Copyright 1997-2013 Free Software Foundation, Inc.
+   Created by Michael Meissner, Cygnus Support <meissner@cygnus.com>
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file holds definitions specific to the MIPS ELF ABI.  Note
+   that most of this is not actually implemented by BFD.  */
+
+#ifndef _ELF_V850_H
+#define _ELF_V850_H
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+/* Four bit V850 architecture field.  */
+#define EF_V850_ARCH		0xf0000000
+
+/* v850 code.  */
+#define E_V850_ARCH		0x00000000
+
+/* v850e code.  */
+#define E_V850E_ARCH		0x10000000
+
+/* v850e1 code.  */
+#define E_V850E1_ARCH		0x20000000
+
+/* v850e2 code.  */
+#define E_V850E2_ARCH		0x30000000
+
+/* v850e2v3 code.  */
+#define E_V850E2V3_ARCH		0x40000000
+
+/* v850e3v5 code.  */
+#define E_V850E3V5_ARCH		0x60000000
+
+/* Flags for the st_other field.  */
+#define V850_OTHER_SDA		0x10	/* Symbol had SDA relocations.  */
+#define V850_OTHER_ZDA		0x20	/* Symbol had ZDA relocations.  */
+#define V850_OTHER_TDA		0x40	/* Symbol had TDA relocations.  */
+#define V850_OTHER_ERROR	0x80	/* Symbol had an error reported.  */
+
+/* V850 relocations.  */
+#include "elf/reloc-macros.h"
+
+START_RELOC_NUMBERS (v850_reloc_type)
+     RELOC_NUMBER (R_V850_NONE, 0)
+     RELOC_NUMBER (R_V850_9_PCREL, 1)
+     RELOC_NUMBER (R_V850_22_PCREL, 2)
+     RELOC_NUMBER (R_V850_HI16_S, 3)
+     RELOC_NUMBER (R_V850_HI16, 4)
+     RELOC_NUMBER (R_V850_LO16, 5)
+     RELOC_NUMBER (R_V850_ABS32, 6)
+     RELOC_NUMBER (R_V850_16, 7)
+     RELOC_NUMBER (R_V850_8, 8)
+     RELOC_NUMBER( R_V850_SDA_16_16_OFFSET, 9)		/* For ld.b, st.b, set1, clr1, not1, tst1, movea, movhi */
+     RELOC_NUMBER( R_V850_SDA_15_16_OFFSET, 10)		/* For ld.w, ld.h, ld.hu, st.w, st.h */
+     RELOC_NUMBER( R_V850_ZDA_16_16_OFFSET, 11)		/* For ld.b, st.b, set1, clr1, not1, tst1, movea, movhi */
+     RELOC_NUMBER( R_V850_ZDA_15_16_OFFSET, 12)		/* For ld.w, ld.h, ld.hu, st.w, st.h */
+     RELOC_NUMBER( R_V850_TDA_6_8_OFFSET, 13)		/* For sst.w, sld.w */
+     RELOC_NUMBER( R_V850_TDA_7_8_OFFSET, 14)		/* For sst.h, sld.h */
+     RELOC_NUMBER( R_V850_TDA_7_7_OFFSET, 15)		/* For sst.b, sld.b */
+     RELOC_NUMBER( R_V850_TDA_16_16_OFFSET, 16)		/* For set1, clr1, not1, tst1, movea, movhi */
+     RELOC_NUMBER( R_V850_TDA_4_5_OFFSET, 17)		/* For sld.hu */
+     RELOC_NUMBER( R_V850_TDA_4_4_OFFSET, 18)		/* For sld.bu */
+     RELOC_NUMBER( R_V850_SDA_16_16_SPLIT_OFFSET, 19)	/* For ld.bu */
+     RELOC_NUMBER( R_V850_ZDA_16_16_SPLIT_OFFSET, 20)	/* For ld.bu */
+     RELOC_NUMBER( R_V850_CALLT_6_7_OFFSET, 21)		/* For callt */
+     RELOC_NUMBER( R_V850_CALLT_16_16_OFFSET, 22)	/* For callt */
+     RELOC_NUMBER (R_V850_GNU_VTINHERIT, 23)
+     RELOC_NUMBER (R_V850_GNU_VTENTRY, 24)
+     RELOC_NUMBER (R_V850_LONGCALL, 25)
+     RELOC_NUMBER (R_V850_LONGJUMP, 26)
+     RELOC_NUMBER (R_V850_ALIGN, 27)
+     RELOC_NUMBER (R_V850_REL32, 28)
+     RELOC_NUMBER (R_V850_LO16_SPLIT_OFFSET, 29)	/* For ld.bu */
+     RELOC_NUMBER (R_V850_16_PCREL, 30)      		/* For loop */
+     RELOC_NUMBER (R_V850_17_PCREL, 31)      		/* For br */
+     RELOC_NUMBER (R_V850_23, 32)			/* For 23bit ld.[w,h,hu,b,bu],st.[w,h,b] */
+     RELOC_NUMBER (R_V850_32_PCREL, 33)      		/* For jr32, jarl32 */
+     RELOC_NUMBER (R_V850_32_ABS, 34)      		/* For jmp32 */
+     RELOC_NUMBER (R_V850_16_SPLIT_OFFSET, 35)      	/* For ld.bu */
+     RELOC_NUMBER (R_V850_16_S1, 36)      		/* For ld.w, ld.h st.w st.h */
+     RELOC_NUMBER (R_V850_LO16_S1, 37)      		/* For ld.w, ld.h st.w st.h */
+     RELOC_NUMBER (R_V850_CALLT_15_16_OFFSET, 38)	/* For ld.w, ld.h, ld.hu, st.w, st.h */
+     RELOC_NUMBER (R_V850_32_GOTPCREL, 39)		/* GLOBAL_OFFSET_TABLE from pc */
+     RELOC_NUMBER (R_V850_16_GOT, 40)      		/* GOT ENTRY from gp */
+     RELOC_NUMBER (R_V850_32_GOT, 41)      		
+     RELOC_NUMBER (R_V850_22_PLT, 42)			/* For jr */
+     RELOC_NUMBER (R_V850_32_PLT, 43)			/* For jr32 */
+     RELOC_NUMBER (R_V850_COPY, 44)      		
+     RELOC_NUMBER (R_V850_GLOB_DAT, 45)      		
+     RELOC_NUMBER (R_V850_JMP_SLOT, 46)      		
+     RELOC_NUMBER (R_V850_RELATIVE, 47)      		
+     RELOC_NUMBER (R_V850_16_GOTOFF, 48)      		/* From gp */
+     RELOC_NUMBER (R_V850_32_GOTOFF, 49)      		
+     RELOC_NUMBER (R_V850_CODE, 50)      		
+     RELOC_NUMBER (R_V850_DATA, 51)      		/* For loop */
+
+END_RELOC_NUMBERS (R_V850_max)
+
+
+/* Processor specific section indices.  These sections do not actually
+   exist.  Symbols with a st_shndx field corresponding to one of these
+   values have a special meaning.  */
+
+/* Small data area common symbol.  */
+#define SHN_V850_SCOMMON	SHN_LORESERVE
+
+/* Tiny data area common symbol.  */
+#define SHN_V850_TCOMMON	(SHN_LORESERVE + 1)
+
+/* Zero data area common symbol.  */
+#define SHN_V850_ZCOMMON	(SHN_LORESERVE + 2)
+
+
+/* Processor specific section types.  */
+
+/* Section contains the .scommon data.  */
+#define SHT_V850_SCOMMON	0x70000000
+
+/* Section contains the .scommon data.  */
+#define SHT_V850_TCOMMON	0x70000001
+
+/* Section contains the .scommon data.  */
+#define SHT_V850_ZCOMMON	0x70000002
+
+/* Processor specific section flags.  */
+
+/* This section must be in the small data area (pointed to by GP).  */
+#define SHF_V850_GPREL		0x10000000
+
+/* This section must be in the tiny data area (pointed to by EP).  */
+#define SHF_V850_EPREL		0x20000000
+
+/* This section must be in the zero data area (pointed to by R0).  */
+#define SHF_V850_R0REL		0x40000000
+
+/* Alternative versions of the above definitions, as specified by the RH850 ABI.  */
+
+#define EF_RH850_ABI		0xF0000000
+
+#define EF_V800_850E3		0x00100000
+
+#define EF_RH850_FPU_DOUBLE	0x00000001	/* sizeof(double) == 8.  */
+#define EF_RH850_FPU_SINGLE	0x00000002	/* sizeof(double) == 4.  */
+#define EF_RH850_SIMD		0x00000004
+#define EF_RH850_CACHE		0x00000008
+#define EF_RH850_MMU		0x00000010
+#define EF_RH850_REGMODE22	0x00000020	/* Registers r15-r24 (inclusive) are not used.  */
+#define EF_RH850_REGMODE32	0x00000040
+#define EF_RH850_DATA_ALIGN8	0x00000080	/* 8-byte alignment supported.  */
+#define EF_RH850_GP_FIX		0x00000100	/* r4 is fixed.  */
+#define EF_RH850_GP_NOFIX	0x00000200	/* r4 is callee save.  */
+#define EF_RH850_EP_FIX		0x00000400	/* r30 is fixed.  */
+#define EF_RH850_EP_NOFIX	0x00000800	/* r30 is callee save.  */
+#define EF_RH850_TP_FIX		0x00001000	/* r5 is fixed.  */
+#define EF_RH850_TP_NOFIX	0x00002000	/* r5 is callee save.  */
+#define EF_RH850_REG2_RESERVE	0x00004000	/* r2 is fixed.  */
+#define EF_RH850_REG2_NORESERVE 0x00008000	/* r2 is callee saved.  */
+
+#define SHT_RNESAS_IOP		SHT_LOUSER	/* Used by Renesas linker.  */
+
+#define SHF_RENESAS_ABS		0x80000000	/* Absolute section.  */
+#define SHF_GHS_ABS		0x00000400	/* Use unknown.  */
+
+#define STT_RENESAS_ENTRY	14		/* Set for functions called at reset time.  */
+
+START_RELOC_NUMBERS (v800_reloc_type)
+
+     RELOC_NUMBER (R_V800_NONE,      0x00)
+     RELOC_NUMBER (R_V810_NONE,      0x30)
+     RELOC_NUMBER (R_V810_BYTE,      0x31)
+     RELOC_NUMBER (R_V810_HWORD,     0x32)
+     RELOC_NUMBER (R_V810_WORD,      0x33)
+     RELOC_NUMBER (R_V810_WLO,       0x34)
+     RELOC_NUMBER (R_V810_WHI,       0x35)
+     RELOC_NUMBER (R_V810_WHI1,      0x36)
+     RELOC_NUMBER (R_V810_GPBYTE,    0x37)
+     RELOC_NUMBER (R_V810_GPHWORD,   0x38)
+     RELOC_NUMBER (R_V810_GPWORD,    0x39)
+     RELOC_NUMBER (R_V810_GPWLO,     0x3a)
+     RELOC_NUMBER (R_V810_GPWHI,     0x3b)
+     RELOC_NUMBER (R_V810_GPWHI1,    0x3c)
+     RELOC_NUMBER (R_V850_HWLO,      0x3d)
+     FAKE_RELOC   (R_V810_reserved1, 0x3e)
+     RELOC_NUMBER (R_V850_EP7BIT,    0x3f)
+     RELOC_NUMBER (R_V850_EPHBYTE,   0x40)
+     RELOC_NUMBER (R_V850_EPWBYTE,   0x41)
+     RELOC_NUMBER (R_V850_REGHWLO,   0x42)
+     FAKE_RELOC   (R_V810_reserved2, 0x43)
+     RELOC_NUMBER (R_V850_GPHWLO,    0x44)
+     FAKE_RELOC   (R_V810_reserved3, 0x45)
+     RELOC_NUMBER (R_V850_PCR22,     0x46)
+     RELOC_NUMBER (R_V850_BLO,       0x47)
+     RELOC_NUMBER (R_V850_EP4BIT,    0x48)
+     RELOC_NUMBER (R_V850_EP5BIT,    0x49)
+     RELOC_NUMBER (R_V850_REGBLO,    0x4a)
+     RELOC_NUMBER (R_V850_GPBLO,     0x4b)
+     RELOC_NUMBER (R_V810_WLO_1,     0x4c)
+     RELOC_NUMBER (R_V810_GPWLO_1,   0x4d)
+     RELOC_NUMBER (R_V850_BLO_1,     0x4e)
+     RELOC_NUMBER (R_V850_HWLO_1,    0x4f)
+     FAKE_RELOC   (R_V810_reserved4, 0x50)
+     RELOC_NUMBER (R_V850_GPBLO_1,   0x51)
+     RELOC_NUMBER (R_V850_GPHWLO_1,  0x52)
+     FAKE_RELOC   (R_V810_reserved5, 0x53)
+     RELOC_NUMBER (R_V850_EPBLO,     0x54)
+     RELOC_NUMBER (R_V850_EPHWLO,    0x55)
+     FAKE_RELOC   (R_V810_reserved6, 0x56)
+     RELOC_NUMBER (R_V850_EPWLO_N,   0x57)
+     RELOC_NUMBER (R_V850_PC32,      0x58)
+     RELOC_NUMBER (R_V850_W23BIT,    0x59)
+     RELOC_NUMBER (R_V850_GPW23BIT,  0x5a)
+     RELOC_NUMBER (R_V850_EPW23BIT,  0x5b)
+     RELOC_NUMBER (R_V850_B23BIT,    0x5c)
+     RELOC_NUMBER (R_V850_GPB23BIT,  0x5d)
+     RELOC_NUMBER (R_V850_EPB23BIT,  0x5e)
+     RELOC_NUMBER (R_V850_PC16U,     0x5f)
+     RELOC_NUMBER (R_V850_PC17,      0x60)
+     RELOC_NUMBER (R_V850_DW8,       0x61)
+     RELOC_NUMBER (R_V850_GPDW8,     0x62)
+     RELOC_NUMBER (R_V850_EPDW8,     0x63)
+     RELOC_NUMBER (R_V850_PC9,       0x64)
+     RELOC_NUMBER (R_V810_REGBYTE,   0x65)
+     RELOC_NUMBER (R_V810_REGHWORD,  0x66)
+     RELOC_NUMBER (R_V810_REGWORD,   0x67)
+     RELOC_NUMBER (R_V810_REGWLO,    0x68)
+     RELOC_NUMBER (R_V810_REGWHI,    0x69)
+     RELOC_NUMBER (R_V810_REGWHI1,   0x6a)
+     RELOC_NUMBER (R_V850_REGW23BIT, 0x6b)
+     RELOC_NUMBER (R_V850_REGB23BIT, 0x6c)
+     RELOC_NUMBER (R_V850_REGDW8,    0x6d)
+     RELOC_NUMBER (R_V810_EPBYTE,    0x6e)
+     RELOC_NUMBER (R_V810_EPHWORD,   0x6f)
+     RELOC_NUMBER (R_V810_EPWORD,    0x70)
+     RELOC_NUMBER (R_V850_WLO23,     0x71)
+     RELOC_NUMBER (R_V850_WORD_E,    0x72)
+     RELOC_NUMBER (R_V850_REGWORD_E, 0x73)
+     RELOC_NUMBER (R_V850_WORD,      0x74)
+     RELOC_NUMBER (R_V850_GPWORD,    0x75)
+     RELOC_NUMBER (R_V850_REGWORD,   0x76)
+     RELOC_NUMBER (R_V850_EPWORD,    0x77)
+     RELOC_NUMBER (R_V810_TPBYTE,    0x78)
+     RELOC_NUMBER (R_V810_TPHWORD,   0x79)
+     RELOC_NUMBER (R_V810_TPWORD,    0x7a)
+     RELOC_NUMBER (R_V810_TPWLO,     0x7b)
+     RELOC_NUMBER (R_V810_TPWHI,     0x7c)
+     RELOC_NUMBER (R_V810_TPWHI1,    0x7d)
+     RELOC_NUMBER (R_V850_TPHWLO,    0x7e)
+     RELOC_NUMBER (R_V850_TPBLO,     0x7f)
+     RELOC_NUMBER (R_V810_TPWLO_1,   0x80)
+     RELOC_NUMBER (R_V850_TPBLO_1,   0x81)
+     RELOC_NUMBER (R_V850_TPHWLO_1,  0x82)
+     RELOC_NUMBER (R_V850_TP23BIT,   0x83)
+     RELOC_NUMBER (R_V850_TPW23BIT,  0x84)
+     RELOC_NUMBER (R_V850_TPDW8,     0x85)
+
+/* These are defined by the RH850 ABI, but not used.  */
+     RELOC_NUMBER (R_V810_ABS32,     0xa0)
+     RELOC_NUMBER (R_V850_SYM,       0xe0)
+     RELOC_NUMBER (R_V850_OPadd,     0xe1)
+     RELOC_NUMBER (R_V850_OPsub,     0xe2)
+     RELOC_NUMBER (R_V850_OPsctsize, 0xe3)
+     RELOC_NUMBER (R_V850_OPscttop,  0xe4)
+
+END_RELOC_NUMBERS (R_V800_max)
+
+#endif /* _ELF_V850_H */
diff --git a/binutils-2.25/include/elf/vax.h b/binutils-2.25/include/elf/vax.h
new file mode 100644
index 00000000..e44c48e7
--- /dev/null
+++ b/binutils-2.25/include/elf/vax.h
@@ -0,0 +1,51 @@
+/* VAX ELF support for BFD.
+   Copyright (C) 2002, 2010 Free Software Foundation, Inc.
+   Contributed by Matt Thomas <matt@3am-software.com>.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_VAX_H
+#define _ELF_VAX_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocation types.  */
+START_RELOC_NUMBERS (elf_vax_reloc_type)
+  RELOC_NUMBER (R_VAX_NONE, 0)		/* No reloc */
+  RELOC_NUMBER (R_VAX_32, 1)		/* Direct 32 bit  */
+  RELOC_NUMBER (R_VAX_16, 2)		/* Direct 16 bit  */
+  RELOC_NUMBER (R_VAX_8, 3)		/* Direct 8 bit  */
+  RELOC_NUMBER (R_VAX_PC32, 4)		/* PC relative 32 bit */
+  RELOC_NUMBER (R_VAX_PC16, 5)		/* PC relative 16 bit */
+  RELOC_NUMBER (R_VAX_PC8, 6)		/* PC relative 8 bit */
+  RELOC_NUMBER (R_VAX_GOT32, 7)		/* 32 bit PC relative GOT entry */
+  RELOC_NUMBER (R_VAX_PLT32, 13)	/* 32 bit PC relative PLT address */
+  RELOC_NUMBER (R_VAX_COPY, 19)		/* Copy symbol at runtime */
+  RELOC_NUMBER (R_VAX_GLOB_DAT, 20)	/* Create GOT entry */
+  RELOC_NUMBER (R_VAX_JMP_SLOT, 21)	/* Create PLT entry */
+  RELOC_NUMBER (R_VAX_RELATIVE, 22)	/* Adjust by program base */
+  /* These are GNU extensions to enable C++ vtable garbage collection.  */
+  RELOC_NUMBER (R_VAX_GNU_VTINHERIT, 23)
+  RELOC_NUMBER (R_VAX_GNU_VTENTRY, 24)
+END_RELOC_NUMBERS (R_VAX_max)   
+
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_VAX_NONPIC		0x0001	/* Object contains non-PIC code */
+#define EF_VAX_DFLOAT		0x0100	/* Object contains D-Float insn.  */
+#define EF_VAX_GFLOAT		0x0200	/* Object contains G-Float insn.  */
+
+#endif
diff --git a/binutils-2.25/include/elf/vxworks.h b/binutils-2.25/include/elf/vxworks.h
new file mode 100644
index 00000000..f25f0129
--- /dev/null
+++ b/binutils-2.25/include/elf/vxworks.h
@@ -0,0 +1,33 @@
+/* VxWorks ELF support for BFD.
+   Copyright 2007, 2010
+   Free Software Foundation, Inc.
+
+   Contributed by Nathan Sidwell <nathan@codesourcery.com>
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _ELF_VXWORKS_H
+#define _ELF_VXWORKS_H
+
+#define DT_VX_WRS_TLS_DATA_START 0x60000010
+#define DT_VX_WRS_TLS_DATA_SIZE  0x60000011
+#define DT_VX_WRS_TLS_DATA_ALIGN 0x60000015
+#define DT_VX_WRS_TLS_VARS_START 0x60000012
+#define DT_VX_WRS_TLS_VARS_SIZE  0x60000013
+  
+#endif /* _ELF_VXWORKS_H */
diff --git a/binutils-2.25/include/elf/x86-64.h b/binutils-2.25/include/elf/x86-64.h
new file mode 100644
index 00000000..0ce92cd5
--- /dev/null
+++ b/binutils-2.25/include/elf/x86-64.h
@@ -0,0 +1,90 @@
+/* x86_64 ELF support for BFD.
+   Copyright (C) 2000, 2001, 2002, 2004, 2005, 2006, 2008, 2009, 2010
+   Free Software Foundation, Inc.
+   Contributed by Jan Hubicka <jh@suse.cz>
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_X86_64_H
+#define _ELF_X86_64_H
+
+#include "elf/reloc-macros.h"
+
+START_RELOC_NUMBERS (elf_x86_64_reloc_type)
+     RELOC_NUMBER (R_X86_64_NONE,     0)      /* No reloc */
+     RELOC_NUMBER (R_X86_64_64,       1)      /* Direct 64 bit  */
+     RELOC_NUMBER (R_X86_64_PC32,     2)      /* PC relative 32 bit signed */
+     RELOC_NUMBER (R_X86_64_GOT32,    3)      /* 32 bit GOT entry */
+     RELOC_NUMBER (R_X86_64_PLT32,    4)      /* 32 bit PLT address */
+     RELOC_NUMBER (R_X86_64_COPY,     5)      /* Copy symbol at runtime */
+     RELOC_NUMBER (R_X86_64_GLOB_DAT, 6)      /* Create GOT entry */
+     RELOC_NUMBER (R_X86_64_JUMP_SLOT,7)      /* Create PLT entry */
+     RELOC_NUMBER (R_X86_64_RELATIVE, 8)      /* Adjust by program base */
+     RELOC_NUMBER (R_X86_64_GOTPCREL, 9)      /* 32 bit signed pc relative
+                                                 offset to GOT entry */
+     RELOC_NUMBER (R_X86_64_32,       10)     /* Direct 32 bit zero extended */
+     RELOC_NUMBER (R_X86_64_32S,      11)     /* Direct 32 bit sign extended */
+     RELOC_NUMBER (R_X86_64_16,       12)     /* Direct 16 bit zero extended */
+     RELOC_NUMBER (R_X86_64_PC16,     13)     /* 16 bit sign extended pc relative*/
+     RELOC_NUMBER (R_X86_64_8,        14)     /* Direct 8 bit sign extended */
+     RELOC_NUMBER (R_X86_64_PC8,      15)     /* 8 bit sign extended pc relative*/
+     RELOC_NUMBER (R_X86_64_DTPMOD64, 16)     /* ID of module containing symbol */
+     RELOC_NUMBER (R_X86_64_DTPOFF64, 17)     /* Offset in TLS block */
+     RELOC_NUMBER (R_X86_64_TPOFF64,  18)     /* Offset in initial TLS block */
+     RELOC_NUMBER (R_X86_64_TLSGD,    19)     /* PC relative offset to GD GOT block */
+     RELOC_NUMBER (R_X86_64_TLSLD,    20)     /* PC relative offset to LD GOT block */
+     RELOC_NUMBER (R_X86_64_DTPOFF32, 21)     /* Offset in TLS block */
+     RELOC_NUMBER (R_X86_64_GOTTPOFF, 22)     /* PC relative offset to IE GOT entry */
+     RELOC_NUMBER (R_X86_64_TPOFF32,  23)     /* Offset in initial TLS block */
+     RELOC_NUMBER (R_X86_64_PC64,     24)     /* PC relative 64 bit */
+     RELOC_NUMBER (R_X86_64_GOTOFF64, 25)     /* 64 bit offset to GOT */
+     RELOC_NUMBER (R_X86_64_GOTPC32,  26)     /* 32 bit signed pc relative
+                                                 offset to GOT */
+     RELOC_NUMBER (R_X86_64_GOT64,    27)     /* 64 bit GOT entry offset */
+     RELOC_NUMBER (R_X86_64_GOTPCREL64, 28)   /* 64 bit signed pc relative
+     						 offset to GOT entry */
+     RELOC_NUMBER (R_X86_64_GOTPC64,  29)     /* 64 bit signed pc relative
+     						 offset to GOT */
+     RELOC_NUMBER (R_X86_64_GOTPLT64, 30)     /* like GOT64, but indicates
+     						 that PLT entry is needed */
+     RELOC_NUMBER (R_X86_64_PLTOFF64, 31)     /* 64 bit GOT relative offset
+     						 to PLT entry */
+     RELOC_NUMBER (R_X86_64_SIZE32,   32)     /* 32-bit symbol size */
+     RELOC_NUMBER (R_X86_64_SIZE64,   33)     /* 64-bit symbol size */
+     RELOC_NUMBER (R_X86_64_GOTPC32_TLSDESC, 34)
+					      /* 32 bit signed pc relative
+						 offset to TLS descriptor
+						 in the GOT.  */
+     RELOC_NUMBER (R_X86_64_TLSDESC_CALL, 35) /* Relaxable call through TLS
+						 descriptor.  */
+     RELOC_NUMBER (R_X86_64_TLSDESC, 36)      /* 2x64-bit TLS descriptor.  */
+     RELOC_NUMBER (R_X86_64_IRELATIVE, 37)    /* Adjust indirectly by program base */
+     RELOC_NUMBER (R_X86_64_RELATIVE64, 38)   /* 64bit adjust by program base */
+     RELOC_NUMBER (R_X86_64_GNU_VTINHERIT, 250)       /* GNU C++ hack  */
+     RELOC_NUMBER (R_X86_64_GNU_VTENTRY, 251)         /* GNU C++ hack  */
+END_RELOC_NUMBERS (R_X86_64_max)
+
+/* Processor specific section types.  */
+
+#define SHT_X86_64_UNWIND	0x70000001	/* unwind information */
+
+/* Like SHN_COMMON but the symbol will be allocated in the .lbss
+   section.  */
+#define SHN_X86_64_LCOMMON 	(SHN_LORESERVE + 2)
+
+#define SHF_X86_64_LARGE	0x10000000
+#endif
diff --git a/binutils-2.25/include/elf/xc16x.h b/binutils-2.25/include/elf/xc16x.h
new file mode 100644
index 00000000..b46d9035
--- /dev/null
+++ b/binutils-2.25/include/elf/xc16x.h
@@ -0,0 +1,40 @@
+/* Infineon XC16X ELF support for BFD.
+   Copyright 2006, 2010 Free Software Foundation, Inc.
+   Contributed by KPIT Cummins Infosystems 
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_XC16X_H
+#define _ELF_XC16X_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_xc16x_reloc_type)
+  RELOC_NUMBER (R_XC16X_NONE, 0)
+  RELOC_NUMBER (R_XC16X_ABS_8, 1)
+  RELOC_NUMBER (R_XC16X_ABS_16, 2)
+  RELOC_NUMBER (R_XC16X_ABS_32, 3)
+  RELOC_NUMBER (R_XC16X_8_PCREL, 4)
+  RELOC_NUMBER (R_XC16X_PAG, 5)
+  RELOC_NUMBER (R_XC16X_POF, 6)
+  RELOC_NUMBER (R_XC16X_SEG, 7)
+  RELOC_NUMBER (R_XC16X_SOF, 8)
+
+END_RELOC_NUMBERS (R_XC16X_max)
+
+#endif /* _ELF_XC16X_H */
diff --git a/binutils-2.25/include/elf/xgate.h b/binutils-2.25/include/elf/xgate.h
new file mode 100644
index 00000000..33286a8d
--- /dev/null
+++ b/binutils-2.25/include/elf/xgate.h
@@ -0,0 +1,77 @@
+/* XGATE ELF support for BFD.
+   Copyright 2010, 2011, 2012 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_XGATE_H
+#define _ELF_XGATE_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocation types.  */
+START_RELOC_NUMBERS (elf_xgate_reloc_type)
+  RELOC_NUMBER (R_XGATE_NONE, 0)
+  RELOC_NUMBER (R_XGATE_8, 1)
+  RELOC_NUMBER (R_XGATE_PCREL_8, 2)
+  RELOC_NUMBER (R_XGATE_16, 3)
+  RELOC_NUMBER (R_XGATE_32, 4)
+  RELOC_NUMBER (R_XGATE_PCREL_16, 5)
+  /* These are GNU extensions to enable C++ vtable garbage collection.  */
+  RELOC_NUMBER (R_XGATE_GNU_VTINHERIT, 6)
+  RELOC_NUMBER (R_XGATE_GNU_VTENTRY, 7)
+
+  RELOC_NUMBER (R_XGATE_24, 8)
+  RELOC_NUMBER (R_XGATE_LO16, 9)
+  RELOC_NUMBER (R_XGATE_GPAGE, 10)
+  RELOC_NUMBER (R_XGATE_PCREL_9, 11)
+  RELOC_NUMBER (R_XGATE_PCREL_10, 12)
+  RELOC_NUMBER (R_XGATE_IMM8_LO, 13)
+  RELOC_NUMBER (R_XGATE_IMM8_HI, 14)
+  RELOC_NUMBER (R_XGATE_IMM3, 15)
+  RELOC_NUMBER (R_XGATE_IMM4, 16)
+  RELOC_NUMBER (R_XGATE_IMM5, 17)
+
+  /* GNU extension for linker relaxation.
+     Mark beginning of a jump instruction (any form).  */
+  RELOC_NUMBER (R_XGATE_RL_JUMP, 18)
+
+  /* Mark beginning of Gcc relaxation group instruction.  */
+  RELOC_NUMBER (R_XGATE_RL_GROUP, 19)
+END_RELOC_NUMBERS (R_XGATE_max)
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+/* ABI identification.  */
+#define EF_XGATE_ABI  0x00000000F
+
+/* Integers are 32-bit long.  */
+#define E_XGATE_I32   0x000000001
+
+/* Doubles are 64-bit long.  */
+#define E_XGATE_F64   0x000000002
+
+#define EF_XGATE_MACH_MASK  0xF0
+
+#define EF_XGATE_MACH       0x80 /* XGATE microcontroller.  */
+
+#define E_M68HCS12X_GLOBAL  0x100
+
+/* Identify interrupt handlers.  This is used by the debugger to
+   correctly compute the stack frame.  */
+#define STO_XGATE_INTERRUPT 0x40
+     
+#endif
diff --git a/binutils-2.25/include/elf/xstormy16.h b/binutils-2.25/include/elf/xstormy16.h
new file mode 100644
index 00000000..0ae0def8
--- /dev/null
+++ b/binutils-2.25/include/elf/xstormy16.h
@@ -0,0 +1,57 @@
+/* XSTORMY16 ELF support for BFD.
+   Copyright (C) 2001, 2002, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _ELF_XSTORMY16_H
+#define _ELF_XSTORMY16_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_xstormy16_reloc_type)
+  RELOC_NUMBER (R_XSTORMY16_NONE, 0)
+
+  RELOC_NUMBER (R_XSTORMY16_32, 1)
+  RELOC_NUMBER (R_XSTORMY16_16, 2)
+  RELOC_NUMBER (R_XSTORMY16_8, 3)
+  RELOC_NUMBER (R_XSTORMY16_PC32, 4)
+  RELOC_NUMBER (R_XSTORMY16_PC16, 5)
+  RELOC_NUMBER (R_XSTORMY16_PC8, 6)
+
+  RELOC_NUMBER (R_XSTORMY16_REL_12, 7)
+  RELOC_NUMBER (R_XSTORMY16_24, 8)
+  RELOC_NUMBER (R_XSTORMY16_FPTR16, 9)
+
+  RELOC_NUMBER (R_XSTORMY16_LO16, 10)
+  RELOC_NUMBER (R_XSTORMY16_HI16, 11)
+  RELOC_NUMBER (R_XSTORMY16_12, 12)
+
+  RELOC_NUMBER (R_XSTORMY16_GNU_VTINHERIT, 128)
+  RELOC_NUMBER (R_XSTORMY16_GNU_VTENTRY, 129)
+END_RELOC_NUMBERS (R_XSTORMY16_max)
+
+/* Define the data & instruction memory discriminator.  In a linked
+   executable, an symbol should be deemed to point to an instruction
+   if ((address & XSTORMY16_INSN_MASK) == XSTORMY16_INSN_VALUE), and similarly
+   for the data space.  See also `ld/emulparams/elf32xstormy16.sh'.  */
+#define XSTORMY16_DATA_MASK   0xffc00000
+#define XSTORMY16_DATA_VALUE  0x00000000
+#define XSTORMY16_INSN_MASK   0xffc00000
+#define XSTORMY16_INSN_VALUE  0x00400000
+
+#endif /* _ELF_XSTORMY16_H */
diff --git a/binutils-2.25/include/elf/xtensa.h b/binutils-2.25/include/elf/xtensa.h
new file mode 100644
index 00000000..0d35f7ab
--- /dev/null
+++ b/binutils-2.25/include/elf/xtensa.h
@@ -0,0 +1,208 @@
+/* Xtensa ELF support for BFD.
+   Copyright 2003, 2004, 2007, 2008, 2010 Free Software Foundation, Inc.
+   Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
+   USA.  */
+
+/* This file holds definitions specific to the Xtensa ELF ABI.  */
+
+#ifndef _ELF_XTENSA_H
+#define _ELF_XTENSA_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_xtensa_reloc_type)
+     RELOC_NUMBER (R_XTENSA_NONE, 0)
+     RELOC_NUMBER (R_XTENSA_32, 1)
+     RELOC_NUMBER (R_XTENSA_RTLD, 2)
+     RELOC_NUMBER (R_XTENSA_GLOB_DAT, 3)
+     RELOC_NUMBER (R_XTENSA_JMP_SLOT, 4)
+     RELOC_NUMBER (R_XTENSA_RELATIVE, 5)
+     RELOC_NUMBER (R_XTENSA_PLT, 6)
+     RELOC_NUMBER (R_XTENSA_OP0, 8)
+     RELOC_NUMBER (R_XTENSA_OP1, 9)
+     RELOC_NUMBER (R_XTENSA_OP2, 10) 
+     RELOC_NUMBER (R_XTENSA_ASM_EXPAND, 11)
+     RELOC_NUMBER (R_XTENSA_ASM_SIMPLIFY, 12)
+     RELOC_NUMBER (R_XTENSA_32_PCREL, 14)
+     RELOC_NUMBER (R_XTENSA_GNU_VTINHERIT, 15)
+     RELOC_NUMBER (R_XTENSA_GNU_VTENTRY, 16)
+     RELOC_NUMBER (R_XTENSA_DIFF8, 17)
+     RELOC_NUMBER (R_XTENSA_DIFF16, 18)
+     RELOC_NUMBER (R_XTENSA_DIFF32, 19)
+     RELOC_NUMBER (R_XTENSA_SLOT0_OP, 20)
+     RELOC_NUMBER (R_XTENSA_SLOT1_OP, 21)
+     RELOC_NUMBER (R_XTENSA_SLOT2_OP, 22)
+     RELOC_NUMBER (R_XTENSA_SLOT3_OP, 23)
+     RELOC_NUMBER (R_XTENSA_SLOT4_OP, 24)
+     RELOC_NUMBER (R_XTENSA_SLOT5_OP, 25)
+     RELOC_NUMBER (R_XTENSA_SLOT6_OP, 26)
+     RELOC_NUMBER (R_XTENSA_SLOT7_OP, 27)
+     RELOC_NUMBER (R_XTENSA_SLOT8_OP, 28)
+     RELOC_NUMBER (R_XTENSA_SLOT9_OP, 29)
+     RELOC_NUMBER (R_XTENSA_SLOT10_OP, 30)
+     RELOC_NUMBER (R_XTENSA_SLOT11_OP, 31)
+     RELOC_NUMBER (R_XTENSA_SLOT12_OP, 32)
+     RELOC_NUMBER (R_XTENSA_SLOT13_OP, 33)
+     RELOC_NUMBER (R_XTENSA_SLOT14_OP, 34)
+     RELOC_NUMBER (R_XTENSA_SLOT0_ALT, 35)
+     RELOC_NUMBER (R_XTENSA_SLOT1_ALT, 36)
+     RELOC_NUMBER (R_XTENSA_SLOT2_ALT, 37)
+     RELOC_NUMBER (R_XTENSA_SLOT3_ALT, 38)
+     RELOC_NUMBER (R_XTENSA_SLOT4_ALT, 39)
+     RELOC_NUMBER (R_XTENSA_SLOT5_ALT, 40)
+     RELOC_NUMBER (R_XTENSA_SLOT6_ALT, 41)
+     RELOC_NUMBER (R_XTENSA_SLOT7_ALT, 42)
+     RELOC_NUMBER (R_XTENSA_SLOT8_ALT, 43)
+     RELOC_NUMBER (R_XTENSA_SLOT9_ALT, 44)
+     RELOC_NUMBER (R_XTENSA_SLOT10_ALT, 45)
+     RELOC_NUMBER (R_XTENSA_SLOT11_ALT, 46)
+     RELOC_NUMBER (R_XTENSA_SLOT12_ALT, 47)
+     RELOC_NUMBER (R_XTENSA_SLOT13_ALT, 48)
+     RELOC_NUMBER (R_XTENSA_SLOT14_ALT, 49)
+     RELOC_NUMBER (R_XTENSA_TLSDESC_FN, 50)
+     RELOC_NUMBER (R_XTENSA_TLSDESC_ARG, 51)
+     RELOC_NUMBER (R_XTENSA_TLS_DTPOFF, 52)
+     RELOC_NUMBER (R_XTENSA_TLS_TPOFF, 53)
+     RELOC_NUMBER (R_XTENSA_TLS_FUNC, 54)
+     RELOC_NUMBER (R_XTENSA_TLS_ARG, 55)
+     RELOC_NUMBER (R_XTENSA_TLS_CALL, 56)
+END_RELOC_NUMBERS (R_XTENSA_max)
+
+/* Processor-specific flags for the ELF header e_flags field.  */
+
+/* Four-bit Xtensa machine type field.  */
+#define EF_XTENSA_MACH			0x0000000f
+
+/* Various CPU types.  */
+#define E_XTENSA_MACH			0x00000000
+
+/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types.
+   Highly unlikely, but what the heck.  */
+
+#define EF_XTENSA_XT_INSN		0x00000100
+#define EF_XTENSA_XT_LIT		0x00000200
+
+
+/* Processor-specific dynamic array tags.  */
+
+/* Offset of the table that records the GOT location(s).  */
+#define DT_XTENSA_GOT_LOC_OFF		0x70000000
+
+/* Number of entries in the GOT location table.  */
+#define DT_XTENSA_GOT_LOC_SZ		0x70000001
+
+
+/* Definitions for instruction and literal property tables.  The
+   tables for ".gnu.linkonce.*" sections are placed in the following
+   sections:
+
+   instruction tables:	.gnu.linkonce.x.*
+   literal tables:	.gnu.linkonce.p.*
+*/
+
+#define XTENSA_INSN_SEC_NAME ".xt.insn"
+#define XTENSA_LIT_SEC_NAME  ".xt.lit"
+#define XTENSA_PROP_SEC_NAME ".xt.prop"
+
+typedef struct property_table_entry_t
+{
+  bfd_vma address;
+  bfd_vma size;
+  flagword flags;
+} property_table_entry;
+
+/* Flags in the property tables to specify whether blocks of memory are
+   literals, instructions, data, or unreachable.  For instructions,
+   blocks that begin loop targets and branch targets are designated.
+   Blocks that do not allow density instructions, instruction reordering
+   or transformation are also specified.  Finally, for branch targets,
+   branch target alignment priority is included.  Alignment of the next
+   block is specified in the current block and the size of the current
+   block does not include any fill required to align to the next
+   block.  */
+   
+#define XTENSA_PROP_LITERAL		0x00000001
+#define XTENSA_PROP_INSN		0x00000002
+#define XTENSA_PROP_DATA		0x00000004
+#define XTENSA_PROP_UNREACHABLE		0x00000008
+/* Instruction-only properties at beginning of code. */
+#define XTENSA_PROP_INSN_LOOP_TARGET	0x00000010
+#define XTENSA_PROP_INSN_BRANCH_TARGET	0x00000020
+/* Instruction-only properties about code. */
+#define XTENSA_PROP_INSN_NO_DENSITY	0x00000040
+#define XTENSA_PROP_INSN_NO_REORDER	0x00000080
+/* Historically, NO_TRANSFORM was a property of instructions, 
+   but it should apply to literals under certain circumstances.  */
+#define XTENSA_PROP_NO_TRANSFORM	0x00000100
+
+/*  Branch target alignment information.  This transmits information
+    to the linker optimization about the priority of aligning a
+    particular block for branch target alignment: None, low priority,
+    high priority, or required.  These only need to be checked in
+    instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
+    Common usage is:
+
+    switch (GET_XTENSA_PROP_BT_ALIGN(flags))
+    case XTENSA_PROP_BT_ALIGN_NONE:
+    case XTENSA_PROP_BT_ALIGN_LOW:
+    case XTENSA_PROP_BT_ALIGN_HIGH:
+    case XTENSA_PROP_BT_ALIGN_REQUIRE:
+*/
+#define XTENSA_PROP_BT_ALIGN_MASK       0x00000600
+
+/* No branch target alignment.  */
+#define XTENSA_PROP_BT_ALIGN_NONE       0x0
+/* Low priority branch target alignment.  */
+#define XTENSA_PROP_BT_ALIGN_LOW        0x1
+/* High priority branch target alignment. */
+#define XTENSA_PROP_BT_ALIGN_HIGH       0x2
+/* Required branch target alignment.  */
+#define XTENSA_PROP_BT_ALIGN_REQUIRE    0x3
+
+#define GET_XTENSA_PROP_BT_ALIGN(flag) \
+  (((unsigned)((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
+#define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
+  (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
+    (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
+
+/* Alignment is specified in the block BEFORE the one that needs
+   alignment.  Up to 5 bits.  Use GET_XTENSA_PROP_ALIGNMENT(flags) to
+   get the required alignment specified as a power of 2.  Use
+   SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
+   alignment.  Be careful of side effects since the SET will evaluate
+   flags twice.  Also, note that the SIZE of a block in the property
+   table does not include the alignment size, so the alignment fill
+   must be calculated to determine if two blocks are contiguous.
+   TEXT_ALIGN is not currently implemented but is a placeholder for a
+   possible future implementation.  */
+
+#define XTENSA_PROP_ALIGN		0x00000800
+
+#define XTENSA_PROP_ALIGNMENT_MASK      0x0001f000
+
+#define GET_XTENSA_PROP_ALIGNMENT(flag) \
+  (((unsigned)((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
+#define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
+  (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
+    (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
+
+#define XTENSA_PROP_INSN_ABSLIT        0x00020000
+
+#endif /* _ELF_XTENSA_H */
diff --git a/binutils-2.25/include/fibheap.h b/binutils-2.25/include/fibheap.h
new file mode 100644
index 00000000..a3d09dd9
--- /dev/null
+++ b/binutils-2.25/include/fibheap.h
@@ -0,0 +1,95 @@
+/* A Fibonacci heap datatype.
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2009
+   Free Software Foundation, Inc.
+   Contributed by Daniel Berlin (dan@cgsoftware.com).
+
+This file is part of GCC.
+   
+GCC is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+/* Fibonacci heaps are somewhat complex, but, there's an article in
+   DDJ that explains them pretty well:
+
+   http://www.ddj.com/articles/1997/9701/9701o/9701o.htm?topic=algoritms
+
+   Introduction to algorithms by Corman and Rivest also goes over them.
+
+   The original paper that introduced them is "Fibonacci heaps and their
+   uses in improved network optimization algorithms" by Tarjan and
+   Fredman (JACM 34(3), July 1987).
+
+   Amortized and real worst case time for operations:
+
+   ExtractMin: O(lg n) amortized. O(n) worst case.
+   DecreaseKey: O(1) amortized.  O(lg n) worst case. 
+   Insert: O(2) amortized. O(1) actual.  
+   Union: O(1) amortized. O(1) actual.  */
+
+#ifndef _FIBHEAP_H_
+#define _FIBHEAP_H_
+
+#include "ansidecl.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef long fibheapkey_t;
+
+typedef struct fibheap
+{
+  size_t nodes;
+  struct fibnode *min;
+  struct fibnode *root;
+} *fibheap_t;
+
+typedef struct fibnode
+{
+  struct fibnode *parent;
+  struct fibnode *child;
+  struct fibnode *left;
+  struct fibnode *right;
+  fibheapkey_t key;
+  void *data;
+#if defined (__GNUC__) && (!defined (SIZEOF_INT) || SIZEOF_INT < 4)
+  __extension__ unsigned long int degree : 31;
+  __extension__ unsigned long int mark : 1;
+#else
+  unsigned int degree : 31;
+  unsigned int mark : 1;
+#endif
+} *fibnode_t;
+
+extern fibheap_t fibheap_new (void);
+extern fibnode_t fibheap_insert (fibheap_t, fibheapkey_t, void *);
+extern int fibheap_empty (fibheap_t);
+extern fibheapkey_t fibheap_min_key (fibheap_t);
+extern fibheapkey_t fibheap_replace_key (fibheap_t, fibnode_t,
+                                         fibheapkey_t);
+extern void *fibheap_replace_key_data (fibheap_t, fibnode_t,
+                                       fibheapkey_t, void *);
+extern void *fibheap_extract_min (fibheap_t);
+extern void *fibheap_min (fibheap_t);
+extern void *fibheap_replace_data (fibheap_t, fibnode_t, void *);
+extern void *fibheap_delete_node (fibheap_t, fibnode_t);
+extern void fibheap_delete (fibheap_t);
+extern fibheap_t fibheap_union (fibheap_t, fibheap_t);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FIBHEAP_H_ */
diff --git a/binutils-2.25/include/filenames.h b/binutils-2.25/include/filenames.h
new file mode 100644
index 00000000..e799a51b
--- /dev/null
+++ b/binutils-2.25/include/filenames.h
@@ -0,0 +1,97 @@
+/* Macros for taking apart, interpreting and processing file names.
+
+   These are here because some non-Posix (a.k.a. DOSish) systems have
+   drive letter brain-damage at the beginning of an absolute file name,
+   use forward- and back-slash in path names interchangeably, and
+   some of them have case-insensitive file names.
+
+   Copyright 2000, 2001, 2007, 2010 Free Software Foundation, Inc.
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef FILENAMES_H
+#define FILENAMES_H
+
+#include "hashtab.h" /* for hashval_t */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__MSDOS__) || defined(_WIN32) || defined(__OS2__) || defined (__CYGWIN__)
+#  ifndef HAVE_DOS_BASED_FILE_SYSTEM
+#    define HAVE_DOS_BASED_FILE_SYSTEM 1
+#  endif
+#  ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM
+#    define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1
+#  endif
+#  define HAS_DRIVE_SPEC(f) HAS_DOS_DRIVE_SPEC (f)
+#  define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c)
+#  define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f)
+#else /* not DOSish */
+#  if defined(__APPLE__)
+#    ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM
+#      define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1
+#    endif
+#  endif /* __APPLE__ */
+#  define HAS_DRIVE_SPEC(f) (0)
+#  define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c)
+#  define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f)
+#endif
+
+#define IS_DIR_SEPARATOR_1(dos_based, c)				\
+  (((c) == '/')								\
+   || (((c) == '\\') && (dos_based)))
+
+#define HAS_DRIVE_SPEC_1(dos_based, f)			\
+  ((f)[0] && ((f)[1] == ':') && (dos_based))
+
+/* Remove the drive spec from F, assuming HAS_DRIVE_SPEC (f).
+   The result is a pointer to the remainder of F.  */
+#define STRIP_DRIVE_SPEC(f)	((f) + 2)
+
+#define IS_DOS_DIR_SEPARATOR(c) IS_DIR_SEPARATOR_1 (1, c)
+#define IS_DOS_ABSOLUTE_PATH(f) IS_ABSOLUTE_PATH_1 (1, f)
+#define HAS_DOS_DRIVE_SPEC(f) HAS_DRIVE_SPEC_1 (1, f)
+
+#define IS_UNIX_DIR_SEPARATOR(c) IS_DIR_SEPARATOR_1 (0, c)
+#define IS_UNIX_ABSOLUTE_PATH(f) IS_ABSOLUTE_PATH_1 (0, f)
+
+/* Note that when DOS_BASED is true, IS_ABSOLUTE_PATH accepts d:foo as
+   well, although it is only semi-absolute.  This is because the users
+   of IS_ABSOLUTE_PATH want to know whether to prepend the current
+   working directory to a file name, which should not be done with a
+   name like d:foo.  */
+#define IS_ABSOLUTE_PATH_1(dos_based, f)		 \
+  (IS_DIR_SEPARATOR_1 (dos_based, (f)[0])		 \
+   || HAS_DRIVE_SPEC_1 (dos_based, f))
+
+extern int filename_cmp (const char *s1, const char *s2);
+#define FILENAME_CMP(s1, s2)	filename_cmp(s1, s2)
+
+extern int filename_ncmp (const char *s1, const char *s2,
+			  size_t n);
+
+extern hashval_t filename_hash (const void *s);
+
+extern int filename_eq (const void *s1, const void *s2);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* FILENAMES_H */
diff --git a/binutils-2.25/include/floatformat.h b/binutils-2.25/include/floatformat.h
new file mode 100644
index 00000000..04db61a2
--- /dev/null
+++ b/binutils-2.25/include/floatformat.h
@@ -0,0 +1,152 @@
+/* IEEE floating point support declarations, for GDB, the GNU Debugger.
+   Copyright 1991, 1994, 1995, 1997, 2000, 2003, 2005, 2010
+   Free Software Foundation, Inc.
+
+This file is part of GDB.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#if !defined (FLOATFORMAT_H)
+#define FLOATFORMAT_H 1
+
+#include "ansidecl.h"
+
+/* A floatformat consists of a sign bit, an exponent and a mantissa.  Once the
+   bytes are concatenated according to the byteorder flag, then each of those
+   fields is contiguous.  We number the bits with 0 being the most significant
+   (i.e. BITS_BIG_ENDIAN type numbering), and specify which bits each field
+   contains with the *_start and *_len fields.  */
+
+/* What is the order of the bytes?  */
+
+enum floatformat_byteorders {
+  /* Standard little endian byte order.
+     EX: 1.2345678e10 => 00 00 80 c5 e0 fe 06 42 */
+  floatformat_little,
+
+  /* Standard big endian byte order.
+     EX: 1.2345678e10 => 42 06 fe e0 c5 80 00 00 */
+  floatformat_big,
+
+  /* Little endian byte order but big endian word order.
+     EX: 1.2345678e10 => e0 fe 06 42 00 00 80 c5 */
+  floatformat_littlebyte_bigword,
+
+  /* VAX byte order.  Little endian byte order with 16-bit words.  The
+     following example is an illustration of the byte order only; VAX
+     doesn't have a fully IEEE compliant floating-point format.
+     EX: 1.2345678e10 => 80 c5 00 00 06 42 e0 fe */
+  floatformat_vax
+};
+
+enum floatformat_intbit { floatformat_intbit_yes, floatformat_intbit_no };
+
+struct floatformat
+{
+  enum floatformat_byteorders byteorder;
+  unsigned int totalsize;	/* Total size of number in bits */
+
+  /* Sign bit is always one bit long.  1 means negative, 0 means positive.  */
+  unsigned int sign_start;
+
+  unsigned int exp_start;
+  unsigned int exp_len;
+  /* Bias added to a "true" exponent to form the biased exponent.  It
+     is intentionally signed as, otherwize, -exp_bias can turn into a
+     very large number (e.g., given the exp_bias of 0x3fff and a 64
+     bit long, the equation (long)(1 - exp_bias) evaluates to
+     4294950914) instead of -16382).  */
+  int exp_bias;
+  /* Exponent value which indicates NaN.  This is the actual value stored in
+     the float, not adjusted by the exp_bias.  This usually consists of all
+     one bits.  */
+  unsigned int exp_nan;
+
+  unsigned int man_start;
+  unsigned int man_len;
+
+  /* Is the integer bit explicit or implicit?  */
+  enum floatformat_intbit intbit;
+
+  /* Internal name for debugging. */
+  const char *name;
+
+  /* Validator method.  */
+  int (*is_valid) (const struct floatformat *fmt, const void *from);
+
+  /* Is the format actually the sum of two smaller floating point
+     formats (IBM long double, as described in
+     gcc/config/rs6000/darwin-ldouble-format)?  If so, this is the
+     smaller format in question, and the fields sign_start through
+     intbit describe the first half.  If not, this is NULL.  */
+  const struct floatformat *split_half;
+};
+
+/* floatformats for IEEE single and double, big and little endian.  */
+
+extern const struct floatformat floatformat_ieee_half_big;
+extern const struct floatformat floatformat_ieee_half_little;
+extern const struct floatformat floatformat_ieee_single_big;
+extern const struct floatformat floatformat_ieee_single_little;
+extern const struct floatformat floatformat_ieee_double_big;
+extern const struct floatformat floatformat_ieee_double_little;
+
+/* floatformat for ARM IEEE double, little endian bytes and big endian words */
+
+extern const struct floatformat floatformat_ieee_double_littlebyte_bigword;
+
+/* floatformats for VAX.  */
+
+extern const struct floatformat floatformat_vax_f;
+extern const struct floatformat floatformat_vax_d;
+extern const struct floatformat floatformat_vax_g;
+
+/* floatformats for various extendeds.  */
+
+extern const struct floatformat floatformat_i387_ext;
+extern const struct floatformat floatformat_m68881_ext;
+extern const struct floatformat floatformat_i960_ext;
+extern const struct floatformat floatformat_m88110_ext;
+extern const struct floatformat floatformat_m88110_harris_ext;
+extern const struct floatformat floatformat_arm_ext_big;
+extern const struct floatformat floatformat_arm_ext_littlebyte_bigword;
+/* IA-64 Floating Point register spilt into memory.  */
+extern const struct floatformat floatformat_ia64_spill_big;
+extern const struct floatformat floatformat_ia64_spill_little;
+extern const struct floatformat floatformat_ia64_quad_big;
+extern const struct floatformat floatformat_ia64_quad_little;
+/* IBM long double (double+double).  */
+extern const struct floatformat floatformat_ibm_long_double_big;
+extern const struct floatformat floatformat_ibm_long_double_little;
+
+/* Convert from FMT to a double.
+   FROM is the address of the extended float.
+   Store the double in *TO.  */
+
+extern void
+floatformat_to_double (const struct floatformat *, const void *, double *);
+
+/* The converse: convert the double *FROM to FMT
+   and store where TO points.  */
+
+extern void
+floatformat_from_double (const struct floatformat *, const double *, void *);
+
+/* Return non-zero iff the data at FROM is a valid number in format FMT.  */
+
+extern int
+floatformat_is_valid (const struct floatformat *fmt, const void *from);
+
+#endif	/* defined (FLOATFORMAT_H) */
diff --git a/binutils-2.25/include/fnmatch.h b/binutils-2.25/include/fnmatch.h
new file mode 100644
index 00000000..5b9953ca
--- /dev/null
+++ b/binutils-2.25/include/fnmatch.h
@@ -0,0 +1,70 @@
+/* Copyright 1991, 1992, 1993, 1996 Free Software Foundation, Inc.
+
+NOTE: The canonical source of this file is maintained with the GNU C Library.
+Bugs can be reported to bug-glibc@prep.ai.mit.edu.
+
+This program is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, 51 Franklin Street - Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+#ifndef	_FNMATCH_H
+
+#define	_FNMATCH_H	1
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+#if defined (__cplusplus) || (defined (__STDC__) && __STDC__)
+#undef	__P
+#define	__P(args)	args
+#else /* Not C++ or ANSI C.  */
+#undef	__P
+#define	__P(args)	()
+/* We can get away without defining `const' here only because in this file
+   it is used only inside the prototype for `fnmatch', which is elided in
+   non-ANSI C where `const' is problematical.  */
+#endif /* C++ or ANSI C.  */
+
+
+/* We #undef these before defining them because some losing systems
+   (HP-UX A.08.07 for example) define these in <unistd.h>.  */
+#undef	FNM_PATHNAME
+#undef	FNM_NOESCAPE
+#undef	FNM_PERIOD
+
+/* Bits set in the FLAGS argument to `fnmatch'.  */
+#define	FNM_PATHNAME	(1 << 0) /* No wildcard can ever match `/'.  */
+#define	FNM_NOESCAPE	(1 << 1) /* Backslashes don't quote special chars.  */
+#define	FNM_PERIOD	(1 << 2) /* Leading `.' is matched only explicitly.  */
+
+#if !defined (_POSIX_C_SOURCE) || _POSIX_C_SOURCE < 2 || defined (_GNU_SOURCE)
+#define	FNM_FILE_NAME	FNM_PATHNAME /* Preferred GNU name.  */
+#define	FNM_LEADING_DIR	(1 << 3) /* Ignore `/...' after a match.  */
+#define	FNM_CASEFOLD	(1 << 4) /* Compare without regard to case.  */
+#endif
+
+/* Value returned by `fnmatch' if STRING does not match PATTERN.  */
+#define	FNM_NOMATCH	1
+
+/* Match STRING against the filename pattern PATTERN,
+   returning zero if it matches, FNM_NOMATCH if not.  */
+extern int fnmatch __P ((const char *__pattern, const char *__string,
+			 int __flags));
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* fnmatch.h */
diff --git a/binutils-2.25/include/fopen-bin.h b/binutils-2.25/include/fopen-bin.h
new file mode 100644
index 00000000..8f5f7710
--- /dev/null
+++ b/binutils-2.25/include/fopen-bin.h
@@ -0,0 +1,44 @@
+/* Macros for the 'type' part of an fopen, freopen or fdopen. 
+
+	<Read|Write>[Update]<Binary file|text file>
+
+   This version is for "binary" systems, where text and binary files are
+   different.  An example is Mess-Dose.  Many Unix systems could also
+   cope with a "b" in the string, indicating binary files, but some reject this
+   (and thereby don't conform to ANSI C, but what else is new?).
+
+   Copyright 1996-2012 Free Software Foundation, Inc.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+/* This file is designed for inclusion by host-dependent .h files.  No
+   user application should include it directly, since that would make
+   the application unable to be configured for both "same" and "binary"
+   variant systems.  */
+
+#define FOPEN_RB	"rb"
+#define FOPEN_WB 	"wb"
+#define FOPEN_AB 	"ab"
+#define FOPEN_RUB 	"r+b"
+#define FOPEN_WUB 	"w+b"
+#define FOPEN_AUB 	"a+b"
+
+#define FOPEN_RT	"r"
+#define FOPEN_WT 	"w"
+#define FOPEN_AT 	"a"
+#define FOPEN_RUT 	"r+"
+#define FOPEN_WUT 	"w+"
+#define FOPEN_AUT 	"a+"
diff --git a/binutils-2.25/include/fopen-same.h b/binutils-2.25/include/fopen-same.h
new file mode 100644
index 00000000..d139e02e
--- /dev/null
+++ b/binutils-2.25/include/fopen-same.h
@@ -0,0 +1,44 @@
+/* Macros for the 'type' part of an fopen, freopen or fdopen. 
+
+	<Read|Write>[Update]<Binary file|text file>
+
+   This version is for "same" systems, where text and binary files are
+   the same.  An example is Unix.  Many Unix systems could also add a
+   "b" to the string, indicating binary files, but some reject this
+   (and thereby don't conform to ANSI C, but what else is new?).
+
+   Copyright 1996-2012 Free Software Foundation, Inc.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+/* This file is designed for inclusion by host-dependent .h files.  No
+   user application should include it directly, since that would make
+   the application unable to be configured for both "same" and "binary"
+   variant systems.  */
+
+#define FOPEN_RB	"r"
+#define FOPEN_WB 	"w"
+#define FOPEN_AB 	"a"
+#define FOPEN_RUB 	"r+"
+#define FOPEN_WUB 	"w+"
+#define FOPEN_AUB 	"a+"
+
+#define FOPEN_RT	"r"
+#define FOPEN_WT 	"w"
+#define FOPEN_AT 	"a"
+#define FOPEN_RUT 	"r+"
+#define FOPEN_WUT 	"w+"
+#define FOPEN_AUT 	"a+"
diff --git a/binutils-2.25/include/fopen-vms.h b/binutils-2.25/include/fopen-vms.h
new file mode 100644
index 00000000..e2b2dc7a
--- /dev/null
+++ b/binutils-2.25/include/fopen-vms.h
@@ -0,0 +1,42 @@
+/* Macros for the 'type' part of an fopen, freopen or fdopen. 
+
+	<Read|Write>[Update]<Binary file|text file>
+
+   This version is for VMS systems, where text and binary files are
+   different.
+   
+   Copyright 1996-2012 Free Software Foundation, Inc.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+/* This file is designed for inclusion by host-dependent .h files.  No
+   user application should include it directly, since that would make
+   the application unable to be configured for both "same" and "binary"
+   variant systems.  */
+
+#define FOPEN_RB	"rb,rfm=udf,rat=none"
+#define FOPEN_WB 	"wb,rfm=udf,rat=none"
+#define FOPEN_AB 	"ab,rfm=udf,rat=none"
+#define FOPEN_RUB 	"r+b,rfm=udf,rat=none"
+#define FOPEN_WUB 	"w+b,rfm=udf,rat=none"
+#define FOPEN_AUB 	"a+b,rfm=udf,rat=none"
+
+#define FOPEN_RT	"r"
+#define FOPEN_WT 	"w"
+#define FOPEN_AT 	"a"
+#define FOPEN_RUT 	"r+"
+#define FOPEN_WUT 	"w+"
+#define FOPEN_AUT 	"a+"
diff --git a/binutils-2.25/include/gdb/ChangeLog b/binutils-2.25/include/gdb/ChangeLog
new file mode 100644
index 00000000..142f87ae
--- /dev/null
+++ b/binutils-2.25/include/gdb/ChangeLog
@@ -0,0 +1,272 @@
+2013-03-15  Steve Ellcey  <sellcey@mips.com>
+
+	* gdb/remote-sim.h (sim_command_completer): Make char arguments const.
+
+2013-01-01  Joel Brobecker  <brobecker@adacore.com>
+
+	Update year range in copyright notice of all files.
+
+2012-06-23  Doug Evans  <dje@google.com>
+
+	* gdb-index.h: New file.
+
+2012-05-24  Pedro Alves  <palves@redhat.com>
+
+	PR gdb/7205
+
+        Replace TARGET_SIGNAL_ with GDB_SIGNAL_ throughout.
+
+2012-05-24  Pedro Alves  <palves@redhat.com>
+
+	PR gdb/7205
+
+	Replace target_signal with gdb_signal throughout.
+
+2012-04-12  Mike Frysinger  <vapier@gentoo.org>
+
+	* callback.h (CB_SYS_argc, CB_SYS_argnlen, CB_SYS_argn): Define.
+
+2012-02-03  Kevin Buettner  <kevinb@redhat.com>
+
+	* sim-rl78.h: New file.
+
+2011-12-03  Mike Frysinger  <vapier@gentoo.org>
+
+	* callback.h (cb_get_string): New prototype.
+
+2011-04-14  Mike Frysinger  <vapier@gentoo.org>
+
+	* remote-sim.h (sim_complete_command): New prototype.
+
+2011-03-05  Mike Frysinger  <vapier@gentoo.org>
+
+	* sim-bfin.h: New file.
+
+2011-01-11  Andrew Burgess  <aburgess@broadcom.com>
+
+	* remote-sim.h (sim_store_register): Update the API
+	documentation for this function.
+
+2010-09-06  Pedro Alves  <pedro@codesourcery.com>
+
+	* signals.def: Replace all ANY uses by SET with specific numbers.
+	* signals.h (ANY): Remove.
+
+2010-07-31  Jan Kratochvil  <jan.kratochvil@redhat.com>
+
+	* signals.h (enum target_signal): Move the content to signals.def.
+	Include it.
+	* signals.def: New file.
+
+2010-06-24  Kevin Buettner  <kevinb@redhat.com>
+
+	* sim-rx.h (sim_rx_regnum): Add sim_rx_acc_regnum.  Adjust
+	register order.
+
+2010-04-13  Mike Frysinger  <vapier@gentoo.org>
+
+	* callback.h: Strip PARAMS from prototypes.
+	* remote-sim.h: Likewise.
+
+2010-04-13  Mike Frysinger  <vapier@gentoo.org>
+
+	* remote-sim.h (sim_write): Add const to buf arg.
+
+2009-11-24  DJ Delorie  <dj@redhat.com>
+
+	* sim-rx.h: New.
+
+2009-05-18  Jon Beniston <jon@beniston.com>
+
+        * sim-lm32.h: New file.
+
+2009-01-07  Hans-Peter Nilsson  <hp@axis.com>
+
+	* callback.h (struct host_callback_struct): Mark member error as
+	pointing to a noreturn function.
+
+2008-02-12  M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+	* sim-cr16.h: New file.
+
+2008-01-01  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	Updated copyright notices for most files.
+
+2007-10-15  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* sim-ppc.h (sim_spr_register_name): New prototype.
+
+2007-10-11  Jesper Nilsson  <jesper.nilsson@axis.com>
+
+	* callback.h (cb_is_stdin, cb_is_stdout, cb_is_stderr): Add prototypes.
+
+2007-08-23  Joel Brobecker  <brobecker@adacore.com>
+
+	Switch the license of all .h files to GPLv3.
+
+2007-01-09  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	Updated copyright notices for most files.
+
+2005-07-08  Ben Elliston  <bje@au.ibm.com>
+
+	* callback.h: Remove ANSI_PROTOTYPES conditional code.
+
+2005-01-28  Hans-Peter Nilsson  <hp@axis.com>
+
+	* callback.h (struct host_callback_struct): New members pipe,
+	pipe_empty, pipe_nonempty, ispipe, pipe_buffer and
+	target_sizeof_int.
+	(CB_SYS_pipe): New macro.
+
+	* callback.h: Include "bfd.h".
+	(struct host_callback_struct): New member target_endian.
+	(cb_store_target_endian): Declare.
+
+2004-12-15  Hans-Peter Nilsson  <hp@axis.com>
+
+	* callback.h (CB_SYS_truncate, CB_SYS_ftruncate): New macros.
+
+2004-12-13  Hans-Peter Nilsson  <hp@axis.com>
+
+	* callback.h (struct host_callback_struct): New member lstat.
+	(CB_SYS_lstat): New macro.
+	(CB_SYS_rename): New macro.
+
+2004-09-08  Michael Snyder  <msnyder@redhat.com>
+
+	Commited by Corinna Vinschen <vinschen@redhat.com>
+	* sim-sh.h: Add new sh2a banked registers.
+
+2004-08-04  Andrew Cagney  <cagney@gnu.org>
+
+	* sim-ppc.h: Add extern "C" wrapper.
+	(enum sim_ppc_regnum): Add full list of SPRs.
+
+2004-08-04  Jim Blandy  <jimb@redhat.com>
+
+	* sim-ppc.h: New file.
+
+2004-06-25  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* callback.h (host_callback_struct): Replace members fdopen and
+	alwaysopen with fd_buddy.
+	[sim/common: * callback.c: Changed all users.  ]
+
+2003-10-31  Kevin Buettner  <kevin@redhat.com>
+
+	* sim-frv.h: New file.
+
+2003-10-15  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* callback.h (struct host_callback_struct): New members ftruncate
+	and truncate.
+
+2003-06-10  Corinna Vinschen  <vinschen@redhat.com>
+
+	* gdb/fileio.h: New file.
+
+2003-05-07  Andrew Cagney  <cagney@redhat.com>
+
+	* sim-d10v.h (sim_d10v_translate_addr): Add regcache parameter.
+	(sim_d10v_translate_imap_addr): Add regcache parameter.
+	(sim_d10v_translate_dmap_addr): Ditto.
+
+2003-03-27  Nick Clifton  <nickc@redhat.com>
+
+	* sim-arm.h (sim_arm_regs): Add iWMMXt registers.
+
+2003-03-20  Nick Clifton  <nickc@redhat.com>
+
+	* sim-arm.h (sim_arm_regs): Add Maverick co-processor
+	registers.
+
+2003-02-27  Andrew Cagney  <cagney@redhat.com>
+
+	* remote-sim.h (sim_open, sim_load, sim_create_inferior): Rename
+	_bfd to bfd.
+
+2003-02-20  Andrew Cagney  <ac131313@redhat.com>
+
+	* remote-sim.h (SIM_RC): Delete unused SIM_RC_UNKNOWN_BREAKPOINT,
+	SIM_RC_INSUFFICIENT_RESOURCES and SIM_RC_DUPLICATE_BREAKPOINT.
+	(sim_set_breakpoint, sim_clear_breakpoint): Delete declarations.
+	(sim_clear_all_breakpoints, sim_enable_breakpoint): Ditto.
+	(sim_enable_all_breakpoints, sim_disable_breakpoint): Ditto.
+	(sim_disable_all_breakpoints): Ditto.
+
+2002-12-26  Kazu Hirata  <kazu@cs.umass.edu>
+
+	* sim-h8300.h: Remove ^M.
+
+2002-07-29  Andrey Volkov  <avolkov@transas.com>
+
+	* sim-h8300.h: Rename all enums from H8300_ to SIM_H8300_
+	 prefix.
+
+2002-07-23  Andrey Volkov  <avolkov@transas.com>
+
+	* sim-h8300.h: New file.
+
+2002-07-17  Andrew Cagney  <cagney@redhat.com>
+
+	* remote-sim.h: Update copyright.
+	(sim_set_callbacks, sim_size, sim_trace)
+	(sim_set_trace, sim_set_profile_size, sim_kill): Delete.  Moved to
+	"sim/common/run-sim.h".
+
+Wed Jul 17 19:36:38 2002  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* sim-sh.h: Add enum constants for sh[1-4], sh3e, sh3?-dsp,
+	renumbering the sh-dsp registers to use distinct numbers.
+
+2002-06-15  Andrew Cagney  <ac131313@redhat.com>
+
+	* sim-arm.h (enum sim_arm_regs): Rename sim_arm_regnum.
+
+2002-06-12  Andrew Cagney  <ac131313@redhat.com>
+
+	* sim-arm.h: New file.
+
+2002-06-08  Andrew Cagney  <cagney@redhat.com>
+
+	* callback.h: Copy to here from directory above.
+	* remote-sim.h: Copy to here from directory above.
+
+2002-06-01  Andrew Cagney  <ac131313@redhat.com>
+
+	* sim-d10v.h (sim_d10v_regs): Expand to include all registers.
+	Update copyright.
+
+2002-05-23  Andrew Cagney  <ac131313@redhat.com>
+
+	* sim-d10v.h: New file.  Moved from include/sim-d10v.h.
+
+2002-05-10  Elena Zannoni  <ezannoni@redhat.com>
+
+        * sim-sh.h: New file, for sh gdb<->sim interface.
+
+2002-05-09  Daniel Jacobowitz  <drow@mvista.com>
+
+	* signals.h: Update comments.
+	(enum target_signal): Remove conditional compilation around
+	Mach-specific signals.  Move them to after TARGET_SIGNAL_DEFAULT.
+
+2002-03-10  Daniel Jacobowitz  <drow@mvista.com>
+
+	* signals.h: New file, from gdb/defs.h.
+
+
+Copyright (C) 2002-2013 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.25/include/gdb/callback.h b/binutils-2.25/include/gdb/callback.h
new file mode 100644
index 00000000..f830398a
--- /dev/null
+++ b/binutils-2.25/include/gdb/callback.h
@@ -0,0 +1,338 @@
+/* Remote target system call callback support.
+   Copyright 1997-2013 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+/* This interface isn't intended to be specific to any particular kind
+   of remote (hardware, simulator, whatever).  As such, support for it
+   (e.g. sim/common/callback.c) should *not* live in the simulator source
+   tree, nor should it live in the gdb source tree.  */
+
+/* There are various ways to handle system calls:
+
+   1) Have a simulator intercept the appropriate trap instruction and
+   directly perform the system call on behalf of the target program.
+   This is the typical way of handling system calls for embedded targets.
+   [Handling system calls for embedded targets isn't that much of an
+   oxymoron as running compiler testsuites make use of the capability.]
+
+   This method of system call handling is done when STATE_ENVIRONMENT
+   is ENVIRONMENT_USER.
+
+   2) Have a simulator emulate the hardware as much as possible.
+   If the program running on the real hardware communicates with some sort
+   of target manager, one would want to be able to run this program on the
+   simulator as well.
+
+   This method of system call handling is done when STATE_ENVIRONMENT
+   is ENVIRONMENT_OPERATING.
+*/
+
+#ifndef CALLBACK_H
+#define CALLBACK_H
+
+/* ??? The reason why we check for va_start here should be documented.  */
+
+#ifndef va_start
+#include <ansidecl.h>
+#include <stdarg.h>
+#endif
+/* Needed for enum bfd_endian.  */
+#include "bfd.h"
+
+/* Mapping of host/target values.  */
+/* ??? For debugging purposes, one might want to add a string of the
+   name of the symbol.  */
+
+typedef struct {
+  int host_val;
+  int target_val;
+} CB_TARGET_DEFS_MAP;
+
+#define MAX_CALLBACK_FDS 10
+
+/* Forward decl for stat/fstat.  */
+struct stat;
+
+typedef struct host_callback_struct host_callback;
+
+struct host_callback_struct 
+{
+  int (*close) (host_callback *,int);
+  int (*get_errno) (host_callback *);
+  int (*isatty) (host_callback *, int);
+  int (*lseek) (host_callback *, int, long , int);
+  int (*open) (host_callback *, const char*, int mode);
+  int (*read) (host_callback *,int,  char *, int);
+  int (*read_stdin) ( host_callback *, char *, int);
+  int (*rename) (host_callback *, const char *, const char *);
+  int (*system) (host_callback *, const char *);
+  long (*time) (host_callback *, long *);
+  int (*unlink) (host_callback *, const char *);
+  int (*write) (host_callback *,int, const char *, int);
+  int (*write_stdout) (host_callback *, const char *, int);
+  void (*flush_stdout) (host_callback *);
+  int (*write_stderr) (host_callback *, const char *, int);
+  void (*flush_stderr) (host_callback *);
+  int (*stat) (host_callback *, const char *, struct stat *);
+  int (*fstat) (host_callback *, int, struct stat *);
+  int (*lstat) (host_callback *, const char *, struct stat *);
+  int (*ftruncate) (host_callback *, int, long);
+  int (*truncate) (host_callback *, const char *, long);
+  int (*pipe) (host_callback *, int *);
+
+  /* Called by the framework when a read call has emptied a pipe buffer.  */
+  void (*pipe_empty) (host_callback *, int read_fd, int write_fd);
+
+  /* Called by the framework when a write call makes a pipe buffer
+     non-empty.  */
+  void (*pipe_nonempty) (host_callback *, int read_fd, int write_fd);
+
+  /* When present, call to the client to give it the oportunity to
+     poll any io devices for a request to quit (indicated by a nonzero
+     return value). */
+  int (*poll_quit) (host_callback *);
+
+  /* Used when the target has gone away, so we can close open
+     handles and free memory etc etc.  */
+  int (*shutdown) (host_callback *);
+  int (*init)     (host_callback *);
+
+  /* depreciated, use vprintf_filtered - Talk to the user on a console.  */
+  void (*printf_filtered) (host_callback *, const char *, ...);
+
+  /* Talk to the user on a console.  */
+  void (*vprintf_filtered) (host_callback *, const char *, va_list);
+
+  /* Same as vprintf_filtered but to stderr.  */
+  void (*evprintf_filtered) (host_callback *, const char *, va_list);
+
+  /* Print an error message and "exit".
+     In the case of gdb "exiting" means doing a longjmp back to the main
+     command loop.  */
+  void (*error) (host_callback *, const char *, ...)
+#ifdef __GNUC__
+    __attribute__ ((__noreturn__))
+#endif
+    ;
+
+  int last_errno;		/* host format */
+
+  int fdmap[MAX_CALLBACK_FDS];
+  /* fd_buddy is used to contruct circular lists of target fds that point to
+     the same host fd.  A uniquely mapped fd points to itself; for a closed
+     one, fd_buddy has the value -1.  The host file descriptors for stdin /
+     stdout / stderr are never closed by the simulators, so they are put
+     in a special fd_buddy circular list which also has MAX_CALLBACK_FDS
+     as a member.  */
+  /* ??? We don't have a callback entry for dup, although it is trival to
+     implement now.  */
+  short fd_buddy[MAX_CALLBACK_FDS+1];
+
+  /* 0 = none, >0 = reader (index of writer),
+     <0 = writer (negative index of reader).
+     If abs (ispipe[N]) == N, then N is an end of a pipe whose other
+     end is closed.  */
+  short ispipe[MAX_CALLBACK_FDS];
+
+  /* A writer stores the buffer at its index.  Consecutive writes
+     realloc the buffer and add to the size.  The reader indicates the
+     read part in its .size, until it has consumed it all, at which
+     point it deallocates the buffer and zeroes out both sizes.  */
+  struct pipe_write_buffer
+  {
+    int size;
+    char *buffer;
+  } pipe_buffer[MAX_CALLBACK_FDS];
+
+  /* System call numbers.  */
+  CB_TARGET_DEFS_MAP *syscall_map;
+  /* Errno values.  */
+  CB_TARGET_DEFS_MAP *errno_map;
+  /* Flags to the open system call.  */
+  CB_TARGET_DEFS_MAP *open_map;
+  /* Signal numbers.  */
+  CB_TARGET_DEFS_MAP *signal_map;
+  /* Layout of `stat' struct.
+     The format is a series of "name,length" pairs separated by colons.
+     Empty space is indicated with a `name' of "space".
+     All padding must be explicitly mentioned.
+     Lengths are in bytes.  If this needs to be extended to bits,
+     use "name.bits".
+     Example: "st_dev,4:st_ino,4:st_mode,4:..."  */
+  const char *stat_map;
+
+  enum bfd_endian target_endian;
+
+  /* Size of an "int" on the target (for syscalls whose ABI uses "int").
+     This must include padding, and only padding-at-higher-address is
+     supported.  For example, a 64-bit target with 32-bit int:s which
+     are padded to 64 bits when in an array, should supposedly set this
+     to 8.  The default is 4 which matches ILP32 targets and 64-bit
+     targets with 32-bit ints and no padding.  */
+  int target_sizeof_int;
+
+  /* Marker for those wanting to do sanity checks.
+     This should remain the last member of this struct to help catch
+     miscompilation errors. */
+#define HOST_CALLBACK_MAGIC 4705 /* teds constant */
+  int magic;
+};
+
+extern host_callback default_callback;
+
+/* Canonical versions of system call numbers.
+   It's not intended to willy-nilly throw every system call ever heard
+   of in here.  Only include those that have an important use.
+   ??? One can certainly start a discussion over the ones that are currently
+   here, but that will always be true.  */
+
+/* These are used by the ANSI C support of libc.  */
+#define	CB_SYS_exit	1
+#define	CB_SYS_open	2
+#define	CB_SYS_close	3
+#define	CB_SYS_read	4
+#define	CB_SYS_write	5
+#define	CB_SYS_lseek	6
+#define	CB_SYS_unlink	7
+#define	CB_SYS_getpid	8
+#define	CB_SYS_kill	9
+#define CB_SYS_fstat    10
+/*#define CB_SYS_sbrk	11 - not currently a system call, but reserved.  */
+
+/* ARGV support.  */
+#define CB_SYS_argvlen	12
+#define CB_SYS_argv	13
+
+/* These are extras added for one reason or another.  */
+#define CB_SYS_chdir	14
+#define CB_SYS_stat	15
+#define CB_SYS_chmod 	16
+#define CB_SYS_utime 	17
+#define CB_SYS_time 	18
+
+/* More standard syscalls.  */
+#define CB_SYS_lstat    19
+#define CB_SYS_rename	20
+#define CB_SYS_truncate	21
+#define CB_SYS_ftruncate 22
+#define CB_SYS_pipe 	23
+
+/* New ARGV support.  */
+#define CB_SYS_argc	24
+#define CB_SYS_argnlen	25
+#define CB_SYS_argn	26
+
+/* Struct use to pass and return information necessary to perform a
+   system call.  */
+/* FIXME: Need to consider target word size.  */
+
+typedef struct cb_syscall {
+  /* The target's value of what system call to perform.  */
+  int func;
+  /* The arguments to the syscall.  */
+  long arg1, arg2, arg3, arg4;
+
+  /* The result.  */
+  long result;
+  /* Some system calls have two results.  */
+  long result2;
+  /* The target's errno value, or 0 if success.
+     This is converted to the target's value with host_to_target_errno.  */
+  int errcode;
+
+  /* Working space to be used by memory read/write callbacks.  */
+  PTR p1;
+  PTR p2;
+  long x1,x2;
+
+  /* Callbacks for reading/writing memory (e.g. for read/write syscalls).
+     ??? long or unsigned long might be better to use for the `count'
+     argument here.  We mimic sim_{read,write} for now.  Be careful to
+     test any changes with -Wall -Werror, mixed signed comparisons
+     will get you.  */
+  int (*read_mem) (host_callback * /*cb*/, struct cb_syscall * /*sc*/,
+		   unsigned long /*taddr*/, char * /*buf*/,
+		   int /*bytes*/);
+  int (*write_mem) (host_callback * /*cb*/, struct cb_syscall * /*sc*/,
+		    unsigned long /*taddr*/, const char * /*buf*/,
+		    int /*bytes*/);
+
+  /* For sanity checking, should be last entry.  */
+  int magic;
+} CB_SYSCALL;
+
+/* Magic number sanity checker.  */
+#define CB_SYSCALL_MAGIC 0x12344321
+
+/* Macro to initialize CB_SYSCALL.  Called first, before filling in
+   any fields.  */
+#define CB_SYSCALL_INIT(sc) \
+do { \
+  memset ((sc), 0, sizeof (*(sc))); \
+  (sc)->magic = CB_SYSCALL_MAGIC; \
+} while (0)
+
+/* Return codes for various interface routines.  */
+
+typedef enum {
+  CB_RC_OK = 0,
+  /* generic error */
+  CB_RC_ERR,
+  /* either file not found or no read access */
+  CB_RC_ACCESS,
+  CB_RC_NO_MEM
+} CB_RC;
+
+/* Read in target values for system call numbers, errno values, signals.  */
+CB_RC cb_read_target_syscall_maps (host_callback *, const char *);
+
+/* Translate target to host syscall function numbers.  */
+int cb_target_to_host_syscall (host_callback *, int);
+
+/* Translate host to target errno value.  */
+int cb_host_to_target_errno (host_callback *, int);
+
+/* Translate target to host open flags.  */
+int cb_target_to_host_open (host_callback *, int);
+
+/* Translate target signal number to host.  */
+int cb_target_to_host_signal (host_callback *, int);
+
+/* Translate host signal number to target.  */
+int cb_host_to_gdb_signal (host_callback *, int);
+
+/* Translate host stat struct to target.
+   If stat struct ptr is NULL, just compute target stat struct size.
+   Result is size of target stat struct or 0 if error.  */
+int cb_host_to_target_stat (host_callback *, const struct stat *, PTR);
+
+/* Translate a value to target endian.  */
+void cb_store_target_endian (host_callback *, char *, int, long);
+
+/* Tests for special fds.  */
+int cb_is_stdin (host_callback *, int);
+int cb_is_stdout (host_callback *, int);
+int cb_is_stderr (host_callback *, int);
+
+/* Read a string out of the target.  */
+int cb_get_string (host_callback *, CB_SYSCALL *, char *, int, unsigned long);
+
+/* Perform a system call.  */
+CB_RC cb_syscall (host_callback *, CB_SYSCALL *);
+
+#endif
diff --git a/binutils-2.25/include/gdb/fileio.h b/binutils-2.25/include/gdb/fileio.h
new file mode 100644
index 00000000..73275d43
--- /dev/null
+++ b/binutils-2.25/include/gdb/fileio.h
@@ -0,0 +1,144 @@
+/* Hosted File I/O interface definitions, for GDB, the GNU Debugger.
+
+   Copyright 2003-2013 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#ifndef GDB_FILEIO_H_
+#define GDB_FILEIO_H_
+
+/* The following flags are defined to be independent of the host
+   as well as the target side implementation of these constants.
+   All constants are defined with a leading FILEIO_ in the name
+   to allow the usage of these constants together with the
+   corresponding implementation dependent constants in one module. */
+
+/* open(2) flags */
+#define FILEIO_O_RDONLY           0x0
+#define FILEIO_O_WRONLY           0x1
+#define FILEIO_O_RDWR             0x2
+#define FILEIO_O_APPEND           0x8
+#define FILEIO_O_CREAT          0x200
+#define FILEIO_O_TRUNC          0x400
+#define FILEIO_O_EXCL           0x800
+#define FILEIO_O_SUPPORTED	(FILEIO_O_RDONLY | FILEIO_O_WRONLY| \
+				 FILEIO_O_RDWR   | FILEIO_O_APPEND| \
+				 FILEIO_O_CREAT  | FILEIO_O_TRUNC| \
+				 FILEIO_O_EXCL)
+
+/* mode_t bits */
+#define FILEIO_S_IFREG        0100000
+#define FILEIO_S_IFDIR         040000
+#define FILEIO_S_IFCHR         020000
+#define FILEIO_S_IRUSR           0400
+#define FILEIO_S_IWUSR           0200
+#define FILEIO_S_IXUSR           0100
+#define FILEIO_S_IRWXU           0700
+#define FILEIO_S_IRGRP            040
+#define FILEIO_S_IWGRP            020
+#define FILEIO_S_IXGRP            010
+#define FILEIO_S_IRWXG            070
+#define FILEIO_S_IROTH             04
+#define FILEIO_S_IWOTH             02
+#define FILEIO_S_IXOTH             01
+#define FILEIO_S_IRWXO             07
+#define FILEIO_S_SUPPORTED         (FILEIO_S_IFREG|FILEIO_S_IFDIR|  \
+				    FILEIO_S_IRWXU|FILEIO_S_IRWXG|  \
+                                    FILEIO_S_IRWXO)
+
+/* lseek(2) flags */
+#define FILEIO_SEEK_SET             0
+#define FILEIO_SEEK_CUR             1
+#define FILEIO_SEEK_END             2
+
+/* errno values */
+#define FILEIO_EPERM                1
+#define FILEIO_ENOENT               2
+#define FILEIO_EINTR                4
+#define FILEIO_EIO                  5
+#define FILEIO_EBADF                9
+#define FILEIO_EACCES              13
+#define FILEIO_EFAULT              14
+#define FILEIO_EBUSY               16
+#define FILEIO_EEXIST              17
+#define FILEIO_ENODEV              19
+#define FILEIO_ENOTDIR             20
+#define FILEIO_EISDIR              21
+#define FILEIO_EINVAL              22
+#define FILEIO_ENFILE              23
+#define FILEIO_EMFILE              24
+#define FILEIO_EFBIG               27
+#define FILEIO_ENOSPC              28
+#define FILEIO_ESPIPE              29
+#define FILEIO_EROFS               30
+#define FILEIO_ENOSYS		   88
+#define FILEIO_ENAMETOOLONG        91
+#define FILEIO_EUNKNOWN          9999
+
+/* limits */
+#define FILEIO_INT_MIN    -2147483648L
+#define FILEIO_INT_MAX     2147483647L
+#define FILEIO_UINT_MAX    4294967295UL
+#define FILEIO_LONG_MIN   -9223372036854775808LL
+#define FILEIO_LONG_MAX    9223372036854775807LL
+#define FILEIO_ULONG_MAX   18446744073709551615ULL
+
+/* Integral types as used in protocol. */
+#if 0
+typedef __int32_t fio_int_t;
+typedef __uint32_t fio_uint_t, fio_mode_t, fio_time_t;
+typedef __int64_t fio_long_t;
+typedef __uint64_t fio_ulong_t;
+#endif
+
+#define FIO_INT_LEN   4
+#define FIO_UINT_LEN  4
+#define FIO_MODE_LEN  4
+#define FIO_TIME_LEN  4
+#define FIO_LONG_LEN  8
+#define FIO_ULONG_LEN 8
+
+typedef char fio_int_t[FIO_INT_LEN];   
+typedef char fio_uint_t[FIO_UINT_LEN];
+typedef char fio_mode_t[FIO_MODE_LEN];
+typedef char fio_time_t[FIO_TIME_LEN];
+typedef char fio_long_t[FIO_LONG_LEN];
+typedef char fio_ulong_t[FIO_ULONG_LEN];
+
+/* Struct stat as used in protocol.  For complete independence
+   of host/target systems, it's defined as an array with offsets
+   to the members. */
+
+struct fio_stat {
+  fio_uint_t  fst_dev;
+  fio_uint_t  fst_ino;
+  fio_mode_t  fst_mode;
+  fio_uint_t  fst_nlink;
+  fio_uint_t  fst_uid;
+  fio_uint_t  fst_gid;
+  fio_uint_t  fst_rdev;
+  fio_ulong_t fst_size;
+  fio_ulong_t fst_blksize;
+  fio_ulong_t fst_blocks;
+  fio_time_t  fst_atime;
+  fio_time_t  fst_mtime;
+  fio_time_t  fst_ctime;
+};
+
+struct fio_timeval {
+  fio_time_t  ftv_sec;
+  fio_long_t  ftv_usec;
+};
+
+#endif /* GDB_FILEIO_H_ */
diff --git a/binutils-2.25/include/gdb/gdb-index.h b/binutils-2.25/include/gdb/gdb-index.h
new file mode 100644
index 00000000..b43c68f9
--- /dev/null
+++ b/binutils-2.25/include/gdb/gdb-index.h
@@ -0,0 +1,99 @@
+/* Public attributes of the .gdb_index section.
+   Copyright 2012 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+/* This file contains values for understanding the .gdb_index section
+   needed by more than just GDB, e.g. readelf.  */
+
+#ifndef GDB_INDEX_H
+#define GDB_INDEX_H
+
+/* Each symbol in .gdb_index refers to a set of CUs that defines the symbol.
+   Each CU is represented by a 32 bit number that is the index of the CU in
+   the CU table, plus some attributes of the use of the symbol in that CU.
+
+   The values are defined such that if all the bits are zero, then no
+   special meaning is assigned to any of them.  This is done to preserve
+   compatibility with older indices.  The way this is done is to specify
+   that if the GDB_INDEX_SYMBOL_KIND value is zero then all other attribute
+   bits must be zero.
+
+    0-23  CU index
+   24-27  reserved
+   28-30  symbol kind
+   31     0 == global, 1 == static
+
+   Bits 24-27 are reserved because it's easier to relax restrictions than
+   it is to impose them after the fact.  At present 24 bits to represent
+   the CU index is plenty.  If we need more bits for the CU index or for
+   attributes then we have them.  */
+
+/* Whether the symbol is in GLOBAL_BLOCK (== 0) or STATIC_BLOCK (== 1).  */
+#define GDB_INDEX_SYMBOL_STATIC_SHIFT 31
+#define GDB_INDEX_SYMBOL_STATIC_MASK 1
+#define GDB_INDEX_SYMBOL_STATIC_VALUE(cu_index) \
+  (((cu_index) >> GDB_INDEX_SYMBOL_STATIC_SHIFT) & GDB_INDEX_SYMBOL_STATIC_MASK)
+#define GDB_INDEX_SYMBOL_STATIC_SET_VALUE(cu_index, value) \
+  do { \
+    (cu_index) |= (((value) & GDB_INDEX_SYMBOL_STATIC_MASK) \
+		   << GDB_INDEX_SYMBOL_STATIC_SHIFT); \
+  } while (0)
+
+/* The kind of the symbol.
+   We don't use GDB's internal values as these numbers are published
+   so that other tools can build and read .gdb_index.  */
+
+typedef enum {
+  /* Special value to indicate no attributes are present.  */
+  GDB_INDEX_SYMBOL_KIND_NONE = 0,
+  GDB_INDEX_SYMBOL_KIND_TYPE = 1,
+  GDB_INDEX_SYMBOL_KIND_VARIABLE = 2,
+  GDB_INDEX_SYMBOL_KIND_FUNCTION = 3,
+  GDB_INDEX_SYMBOL_KIND_OTHER = 4,
+  /* We currently allocate 3 bits to record the symbol kind.
+     Give the unused bits a value so gdb will print them sensibly.  */
+  GDB_INDEX_SYMBOL_KIND_UNUSED5 = 5,
+  GDB_INDEX_SYMBOL_KIND_UNUSED6 = 6,
+  GDB_INDEX_SYMBOL_KIND_UNUSED7 = 7
+} gdb_index_symbol_kind;
+
+#define GDB_INDEX_SYMBOL_KIND_SHIFT 28
+#define GDB_INDEX_SYMBOL_KIND_MASK 7
+#define GDB_INDEX_SYMBOL_KIND_VALUE(cu_index) \
+  ((gdb_index_symbol_kind) (((cu_index) >> GDB_INDEX_SYMBOL_KIND_SHIFT) \
+			    & GDB_INDEX_SYMBOL_KIND_MASK))
+#define GDB_INDEX_SYMBOL_KIND_SET_VALUE(cu_index, value) \
+  do { \
+    (cu_index) |= (((value) & GDB_INDEX_SYMBOL_KIND_MASK) \
+		   << GDB_INDEX_SYMBOL_KIND_SHIFT); \
+  } while (0)
+
+#define GDB_INDEX_RESERVED_SHIFT 24
+#define GDB_INDEX_RESERVED_MASK 15
+#define GDB_INDEX_RESERVED_VALUE(cu_index) \
+  (((cu_index) >> GDB_INDEX_RESERVED_SHIFT) & GDB_INDEX_RESERVED_MASK)
+
+/* CU index.  */
+#define GDB_INDEX_CU_BITSIZE 24
+#define GDB_INDEX_CU_MASK ((1 << GDB_INDEX_CU_BITSIZE) - 1)
+#define GDB_INDEX_CU_VALUE(cu_index) ((cu_index) & GDB_INDEX_CU_MASK)
+#define GDB_INDEX_CU_SET_VALUE(cu_index, value) \
+  do { \
+    (cu_index) |= (value) & GDB_INDEX_CU_MASK; \
+  } while (0)
+
+#endif /* GDB_INDEX_H */
diff --git a/binutils-2.25/include/gdb/remote-sim.h b/binutils-2.25/include/gdb/remote-sim.h
new file mode 100644
index 00000000..113030c8
--- /dev/null
+++ b/binutils-2.25/include/gdb/remote-sim.h
@@ -0,0 +1,287 @@
+/* This file defines the interface between the simulator and gdb.
+
+   Copyright 1993-2013 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#if !defined (REMOTE_SIM_H)
+#define REMOTE_SIM_H 1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* This file is used when building stand-alone simulators, so isolate this
+   file from gdb.  */
+
+/* Pick up CORE_ADDR_TYPE if defined (from gdb), otherwise use same value as
+   gdb does (unsigned int - from defs.h).  */
+
+#ifndef CORE_ADDR_TYPE
+typedef unsigned int SIM_ADDR;
+#else
+typedef CORE_ADDR_TYPE SIM_ADDR;
+#endif
+
+
+/* Semi-opaque type used as result of sim_open and passed back to all
+   other routines.  "desc" is short for "descriptor".
+   It is up to each simulator to define `sim_state'.  */
+
+typedef struct sim_state *SIM_DESC;
+
+
+/* Values for `kind' arg to sim_open.  */
+
+typedef enum {
+  SIM_OPEN_STANDALONE, /* simulator used standalone (run.c) */
+  SIM_OPEN_DEBUG       /* simulator used by debugger (gdb) */
+} SIM_OPEN_KIND;
+
+
+/* Return codes from various functions.  */
+
+typedef enum {
+  SIM_RC_FAIL = 0,
+  SIM_RC_OK = 1
+} SIM_RC;
+
+
+/* The bfd struct, as an opaque type.  */
+
+struct bfd;
+
+
+/* Main simulator entry points.  */
+
+
+/* Create a fully initialized simulator instance.
+
+   (This function is called when the simulator is selected from the
+   gdb command line.)
+
+   KIND specifies how the simulator shall be used.  Currently there
+   are only two kinds: stand-alone and debug.
+
+   CALLBACK specifies a standard host callback (defined in callback.h).
+
+   ABFD, when non NULL, designates a target program.  The program is
+   not loaded.
+
+   ARGV is a standard ARGV pointer such as that passed from the
+   command line.  The syntax of the argument list is is assumed to be
+   ``SIM-PROG { SIM-OPTION } [ TARGET-PROGRAM { TARGET-OPTION } ]''.
+   The trailing TARGET-PROGRAM and args are only valid for a
+   stand-alone simulator.
+
+   On success, the result is a non NULL descriptor that shall be
+   passed to the other sim_foo functions.  While the simulator
+   configuration can be parameterized by (in decreasing precedence)
+   ARGV's SIM-OPTION, ARGV's TARGET-PROGRAM and the ABFD argument, the
+   successful creation of the simulator shall not dependent on the
+   presence of any of these arguments/options.
+
+   Hardware simulator: The created simulator shall be sufficiently
+   initialized to handle, with out restrictions any client requests
+   (including memory reads/writes, register fetch/stores and a
+   resume).
+
+   Process simulator: that process is not created until a call to
+   sim_create_inferior.  FIXME: What should the state of the simulator
+   be? */
+
+SIM_DESC sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *callback, struct bfd *abfd, char **argv);
+
+
+/* Destory a simulator instance.
+
+   QUITTING is non-zero if we cannot hang on errors.
+
+   This may involve freeing target memory and closing any open files
+   and mmap'd areas.  You cannot assume sim_kill has already been
+   called. */
+
+void sim_close (SIM_DESC sd, int quitting);
+
+
+/* Load program PROG into the simulators memory.
+
+   If ABFD is non-NULL, the bfd for the file has already been opened.
+   The result is a return code indicating success.
+
+   Hardware simulator: Normally, each program section is written into
+   memory according to that sections LMA using physical (direct)
+   addressing.  The exception being systems, such as PPC/CHRP, which
+   support more complicated program loaders.  A call to this function
+   should not effect the state of the processor registers.  Multiple
+   calls to this function are permitted and have an accumulative
+   effect.
+
+   Process simulator: Calls to this function may be ignored.
+
+   FIXME: Most hardware simulators load the image at the VMA using
+   virtual addressing.
+
+   FIXME: For some hardware targets, before a loaded program can be
+   executed, it requires the manipulation of VM registers and tables.
+   Such manipulation should probably (?) occure in
+   sim_create_inferior. */
+
+SIM_RC sim_load (SIM_DESC sd, char *prog, struct bfd *abfd, int from_tty);
+
+
+/* Prepare to run the simulated program.
+
+   ABFD, if not NULL, provides initial processor state information.
+   ARGV and ENV, if non NULL, are NULL terminated lists of pointers.
+
+   Hardware simulator: This function shall initialize the processor
+   registers to a known value.  The program counter and possibly stack
+   pointer shall be set using information obtained from ABFD (or
+   hardware reset defaults).  ARGV and ENV, dependant on the target
+   ABI, may be written to memory.
+
+   Process simulator: After a call to this function, a new process
+   instance shall exist. The TEXT, DATA, BSS and stack regions shall
+   all be initialized, ARGV and ENV shall be written to process
+   address space (according to the applicable ABI) and the program
+   counter and stack pointer set accordingly. */
+
+SIM_RC sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env);
+
+
+/* Fetch LENGTH bytes of the simulated program's memory.  Start fetch
+   at virtual address MEM and store in BUF.  Result is number of bytes
+   read, or zero if error.  */
+
+int sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length);
+
+
+/* Store LENGTH bytes from BUF into the simulated program's
+   memory. Store bytes starting at virtual address MEM. Result is
+   number of bytes write, or zero if error.  */
+
+int sim_write (SIM_DESC sd, SIM_ADDR mem, const unsigned char *buf, int length);
+
+
+/* Fetch register REGNO storing its raw (target endian) value in the
+   LENGTH byte buffer BUF.  Return the actual size of the register or
+   zero if REGNO is not applicable.
+
+   Legacy implementations ignore LENGTH and always return -1.
+
+   If LENGTH does not match the size of REGNO no data is transfered
+   (the actual register size is still returned). */
+
+int sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length);
+
+
+/* Store register REGNO from the raw (target endian) value in BUF.
+
+   Return the actual size of the register, any size not equal to
+   LENGTH indicates the register was not updated correctly.
+
+   Return a LENGTH of -1 to indicate the register was not updated
+   and an error has occurred.
+
+   Return a LENGTH of 0 to indicate the register was not updated
+   but no error has occurred. */
+
+int sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length);
+
+
+/* Print whatever statistics the simulator has collected.
+
+   VERBOSE is currently unused and must always be zero.  */
+
+void sim_info (SIM_DESC sd, int verbose);
+
+
+/* Run (or resume) the simulated program.
+
+   STEP, when non-zero indicates that only a single simulator cycle
+   should be emulated.
+
+   SIGGNAL, if non-zero is a (HOST) SIGRC value indicating the type of
+   event (hardware interrupt, signal) to be delivered to the simulated
+   program.
+
+   Hardware simulator: If the SIGRC value returned by
+   sim_stop_reason() is passed back to the simulator via SIGGNAL then
+   the hardware simulator shall correctly deliver the hardware event
+   indicated by that signal.  If a value of zero is passed in then the
+   simulation will continue as if there were no outstanding signal.
+   The effect of any other SIGGNAL value is is implementation
+   dependant.
+
+   Process simulator: If SIGRC is non-zero then the corresponding
+   signal is delivered to the simulated program and execution is then
+   continued.  A zero SIGRC value indicates that the program should
+   continue as normal. */
+
+void sim_resume (SIM_DESC sd, int step, int siggnal);
+
+
+/* Asynchronous request to stop the simulation.
+   A nonzero return indicates that the simulator is able to handle
+   the request */
+
+int sim_stop (SIM_DESC sd);
+
+
+/* Fetch the REASON why the program stopped.
+
+   SIM_EXITED: The program has terminated. SIGRC indicates the target
+   dependant exit status.
+
+   SIM_STOPPED: The program has stopped.  SIGRC uses the host's signal
+   numbering as a way of identifying the reaon: program interrupted by
+   user via a sim_stop request (SIGINT); a breakpoint instruction
+   (SIGTRAP); a completed single step (SIGTRAP); an internal error
+   condition (SIGABRT); an illegal instruction (SIGILL); Access to an
+   undefined memory region (SIGSEGV); Mis-aligned memory access
+   (SIGBUS).  For some signals information in addition to the signal
+   number may be retained by the simulator (e.g. offending address),
+   that information is not directly accessable via this interface.
+
+   SIM_SIGNALLED: The program has been terminated by a signal. The
+   simulator has encountered target code that causes the the program
+   to exit with signal SIGRC.
+
+   SIM_RUNNING, SIM_POLLING: The return of one of these values
+   indicates a problem internal to the simulator. */
+
+enum sim_stop { sim_running, sim_polling, sim_exited, sim_stopped, sim_signalled };
+
+void sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc);
+
+
+/* Passthru for other commands that the simulator might support.
+   Simulators should be prepared to deal with any combination of NULL
+   or empty CMD. */
+
+void sim_do_command (SIM_DESC sd, char *cmd);
+
+/* Complete a command based on the available sim commands.  Returns an
+   array of possible matches.  */
+
+char **sim_complete_command (SIM_DESC sd, const char *text, const char *word);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined (REMOTE_SIM_H) */
diff --git a/binutils-2.25/include/gdb/signals.def b/binutils-2.25/include/gdb/signals.def
new file mode 100644
index 00000000..637d00de
--- /dev/null
+++ b/binutils-2.25/include/gdb/signals.def
@@ -0,0 +1,200 @@
+/* Target signal numbers for GDB and the GDB remote protocol.
+   Copyright 2010-2013 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+/* Used some places (e.g. stop_signal) to record the concept that
+   there is no signal.  */
+SET (GDB_SIGNAL_0, 0, "0", "Signal 0")
+#define GDB_SIGNAL_FIRST GDB_SIGNAL_0
+SET (GDB_SIGNAL_HUP, 1, "SIGHUP", "Hangup")
+SET (GDB_SIGNAL_INT, 2, "SIGINT", "Interrupt")
+SET (GDB_SIGNAL_QUIT, 3, "SIGQUIT", "Quit")
+SET (GDB_SIGNAL_ILL, 4, "SIGILL", "Illegal instruction")
+SET (GDB_SIGNAL_TRAP, 5, "SIGTRAP", "Trace/breakpoint trap")
+SET (GDB_SIGNAL_ABRT, 6, "SIGABRT", "Aborted")
+SET (GDB_SIGNAL_EMT, 7, "SIGEMT", "Emulation trap")
+SET (GDB_SIGNAL_FPE, 8, "SIGFPE", "Arithmetic exception")
+SET (GDB_SIGNAL_KILL, 9, "SIGKILL", "Killed")
+SET (GDB_SIGNAL_BUS, 10, "SIGBUS", "Bus error")
+SET (GDB_SIGNAL_SEGV, 11, "SIGSEGV", "Segmentation fault")
+SET (GDB_SIGNAL_SYS, 12, "SIGSYS", "Bad system call")
+SET (GDB_SIGNAL_PIPE, 13, "SIGPIPE", "Broken pipe")
+SET (GDB_SIGNAL_ALRM, 14, "SIGALRM", "Alarm clock")
+SET (GDB_SIGNAL_TERM, 15, "SIGTERM", "Terminated")
+SET (GDB_SIGNAL_URG, 16, "SIGURG", "Urgent I/O condition")
+SET (GDB_SIGNAL_STOP, 17, "SIGSTOP", "Stopped (signal)")
+SET (GDB_SIGNAL_TSTP, 18, "SIGTSTP", "Stopped (user)")
+SET (GDB_SIGNAL_CONT, 19, "SIGCONT", "Continued")
+SET (GDB_SIGNAL_CHLD, 20, "SIGCHLD", "Child status changed")
+SET (GDB_SIGNAL_TTIN, 21, "SIGTTIN", "Stopped (tty input)")
+SET (GDB_SIGNAL_TTOU, 22, "SIGTTOU", "Stopped (tty output)")
+SET (GDB_SIGNAL_IO, 23, "SIGIO", "I/O possible")
+SET (GDB_SIGNAL_XCPU, 24, "SIGXCPU", "CPU time limit exceeded")
+SET (GDB_SIGNAL_XFSZ, 25, "SIGXFSZ", "File size limit exceeded")
+SET (GDB_SIGNAL_VTALRM, 26, "SIGVTALRM", "Virtual timer expired")
+SET (GDB_SIGNAL_PROF, 27, "SIGPROF", "Profiling timer expired")
+SET (GDB_SIGNAL_WINCH, 28, "SIGWINCH", "Window size changed")
+SET (GDB_SIGNAL_LOST, 29, "SIGLOST", "Resource lost")
+SET (GDB_SIGNAL_USR1, 30, "SIGUSR1", "User defined signal 1")
+SET (GDB_SIGNAL_USR2, 31, "SIGUSR2", "User defined signal 2")
+SET (GDB_SIGNAL_PWR, 32, "SIGPWR", "Power fail/restart")
+/* Similar to SIGIO.  Perhaps they should have the same number.  */
+SET (GDB_SIGNAL_POLL, 33, "SIGPOLL", "Pollable event occurred")
+SET (GDB_SIGNAL_WIND, 34, "SIGWIND", "SIGWIND")
+SET (GDB_SIGNAL_PHONE, 35, "SIGPHONE", "SIGPHONE")
+SET (GDB_SIGNAL_WAITING, 36, "SIGWAITING", "Process's LWPs are blocked")
+SET (GDB_SIGNAL_LWP, 37, "SIGLWP", "Signal LWP")
+SET (GDB_SIGNAL_DANGER, 38, "SIGDANGER", "Swap space dangerously low")
+SET (GDB_SIGNAL_GRANT, 39, "SIGGRANT", "Monitor mode granted")
+SET (GDB_SIGNAL_RETRACT, 40, "SIGRETRACT",
+     "Need to relinquish monitor mode")
+SET (GDB_SIGNAL_MSG, 41, "SIGMSG", "Monitor mode data available")
+SET (GDB_SIGNAL_SOUND, 42, "SIGSOUND", "Sound completed")
+SET (GDB_SIGNAL_SAK, 43, "SIGSAK", "Secure attention")
+SET (GDB_SIGNAL_PRIO, 44, "SIGPRIO", "SIGPRIO")
+SET (GDB_SIGNAL_REALTIME_33, 45, "SIG33", "Real-time event 33")
+SET (GDB_SIGNAL_REALTIME_34, 46, "SIG34", "Real-time event 34")
+SET (GDB_SIGNAL_REALTIME_35, 47, "SIG35", "Real-time event 35")
+SET (GDB_SIGNAL_REALTIME_36, 48, "SIG36", "Real-time event 36")
+SET (GDB_SIGNAL_REALTIME_37, 49, "SIG37", "Real-time event 37")
+SET (GDB_SIGNAL_REALTIME_38, 50, "SIG38", "Real-time event 38")
+SET (GDB_SIGNAL_REALTIME_39, 51, "SIG39", "Real-time event 39")
+SET (GDB_SIGNAL_REALTIME_40, 52, "SIG40", "Real-time event 40")
+SET (GDB_SIGNAL_REALTIME_41, 53, "SIG41", "Real-time event 41")
+SET (GDB_SIGNAL_REALTIME_42, 54, "SIG42", "Real-time event 42")
+SET (GDB_SIGNAL_REALTIME_43, 55, "SIG43", "Real-time event 43")
+SET (GDB_SIGNAL_REALTIME_44, 56, "SIG44", "Real-time event 44")
+SET (GDB_SIGNAL_REALTIME_45, 57, "SIG45", "Real-time event 45")
+SET (GDB_SIGNAL_REALTIME_46, 58, "SIG46", "Real-time event 46")
+SET (GDB_SIGNAL_REALTIME_47, 59, "SIG47", "Real-time event 47")
+SET (GDB_SIGNAL_REALTIME_48, 60, "SIG48", "Real-time event 48")
+SET (GDB_SIGNAL_REALTIME_49, 61, "SIG49", "Real-time event 49")
+SET (GDB_SIGNAL_REALTIME_50, 62, "SIG50", "Real-time event 50")
+SET (GDB_SIGNAL_REALTIME_51, 63, "SIG51", "Real-time event 51")
+SET (GDB_SIGNAL_REALTIME_52, 64, "SIG52", "Real-time event 52")
+SET (GDB_SIGNAL_REALTIME_53, 65, "SIG53", "Real-time event 53")
+SET (GDB_SIGNAL_REALTIME_54, 66, "SIG54", "Real-time event 54")
+SET (GDB_SIGNAL_REALTIME_55, 67, "SIG55", "Real-time event 55")
+SET (GDB_SIGNAL_REALTIME_56, 68, "SIG56", "Real-time event 56")
+SET (GDB_SIGNAL_REALTIME_57, 69, "SIG57", "Real-time event 57")
+SET (GDB_SIGNAL_REALTIME_58, 70, "SIG58", "Real-time event 58")
+SET (GDB_SIGNAL_REALTIME_59, 71, "SIG59", "Real-time event 59")
+SET (GDB_SIGNAL_REALTIME_60, 72, "SIG60", "Real-time event 60")
+SET (GDB_SIGNAL_REALTIME_61, 73, "SIG61", "Real-time event 61")
+SET (GDB_SIGNAL_REALTIME_62, 74, "SIG62", "Real-time event 62")
+SET (GDB_SIGNAL_REALTIME_63, 75, "SIG63", "Real-time event 63")
+
+/* Used internally by Solaris threads.  See signal(5) on Solaris.  */
+SET (GDB_SIGNAL_CANCEL, 76, "SIGCANCEL", "LWP internal signal")
+
+/* Yes, this pains me, too.  But LynxOS didn't have SIG32, and now
+   GNU/Linux does, and we can't disturb the numbering, since it's
+   part of the remote protocol.  Note that in some GDB's
+   GDB_SIGNAL_REALTIME_32 is number 76.  */
+SET (GDB_SIGNAL_REALTIME_32, 77, "SIG32", "Real-time event 32")
+/* Yet another pain, IRIX 6 has SIG64. */
+SET (GDB_SIGNAL_REALTIME_64, 78, "SIG64", "Real-time event 64")
+/* Yet another pain, GNU/Linux MIPS might go up to 128. */
+SET (GDB_SIGNAL_REALTIME_65, 79, "SIG65", "Real-time event 65")
+SET (GDB_SIGNAL_REALTIME_66, 80, "SIG66", "Real-time event 66")
+SET (GDB_SIGNAL_REALTIME_67, 81, "SIG67", "Real-time event 67")
+SET (GDB_SIGNAL_REALTIME_68, 82, "SIG68", "Real-time event 68")
+SET (GDB_SIGNAL_REALTIME_69, 83, "SIG69", "Real-time event 69")
+SET (GDB_SIGNAL_REALTIME_70, 84, "SIG70", "Real-time event 70")
+SET (GDB_SIGNAL_REALTIME_71, 85, "SIG71", "Real-time event 71")
+SET (GDB_SIGNAL_REALTIME_72, 86, "SIG72", "Real-time event 72")
+SET (GDB_SIGNAL_REALTIME_73, 87, "SIG73", "Real-time event 73")
+SET (GDB_SIGNAL_REALTIME_74, 88, "SIG74", "Real-time event 74")
+SET (GDB_SIGNAL_REALTIME_75, 89, "SIG75", "Real-time event 75")
+SET (GDB_SIGNAL_REALTIME_76, 90, "SIG76", "Real-time event 76")
+SET (GDB_SIGNAL_REALTIME_77, 91, "SIG77", "Real-time event 77")
+SET (GDB_SIGNAL_REALTIME_78, 92, "SIG78", "Real-time event 78")
+SET (GDB_SIGNAL_REALTIME_79, 93, "SIG79", "Real-time event 79")
+SET (GDB_SIGNAL_REALTIME_80, 94, "SIG80", "Real-time event 80")
+SET (GDB_SIGNAL_REALTIME_81, 95, "SIG81", "Real-time event 81")
+SET (GDB_SIGNAL_REALTIME_82, 96, "SIG82", "Real-time event 82")
+SET (GDB_SIGNAL_REALTIME_83, 97, "SIG83", "Real-time event 83")
+SET (GDB_SIGNAL_REALTIME_84, 98, "SIG84", "Real-time event 84")
+SET (GDB_SIGNAL_REALTIME_85, 99, "SIG85", "Real-time event 85")
+SET (GDB_SIGNAL_REALTIME_86, 100, "SIG86", "Real-time event 86")
+SET (GDB_SIGNAL_REALTIME_87, 101, "SIG87", "Real-time event 87")
+SET (GDB_SIGNAL_REALTIME_88, 102, "SIG88", "Real-time event 88")
+SET (GDB_SIGNAL_REALTIME_89, 103, "SIG89", "Real-time event 89")
+SET (GDB_SIGNAL_REALTIME_90, 104, "SIG90", "Real-time event 90")
+SET (GDB_SIGNAL_REALTIME_91, 105, "SIG91", "Real-time event 91")
+SET (GDB_SIGNAL_REALTIME_92, 106, "SIG92", "Real-time event 92")
+SET (GDB_SIGNAL_REALTIME_93, 107, "SIG93", "Real-time event 93")
+SET (GDB_SIGNAL_REALTIME_94, 108, "SIG94", "Real-time event 94")
+SET (GDB_SIGNAL_REALTIME_95, 109, "SIG95", "Real-time event 95")
+SET (GDB_SIGNAL_REALTIME_96, 110, "SIG96", "Real-time event 96")
+SET (GDB_SIGNAL_REALTIME_97, 111, "SIG97", "Real-time event 97")
+SET (GDB_SIGNAL_REALTIME_98, 112, "SIG98", "Real-time event 98")
+SET (GDB_SIGNAL_REALTIME_99, 113, "SIG99", "Real-time event 99")
+SET (GDB_SIGNAL_REALTIME_100, 114, "SIG100", "Real-time event 100")
+SET (GDB_SIGNAL_REALTIME_101, 115, "SIG101", "Real-time event 101")
+SET (GDB_SIGNAL_REALTIME_102, 116, "SIG102", "Real-time event 102")
+SET (GDB_SIGNAL_REALTIME_103, 117, "SIG103", "Real-time event 103")
+SET (GDB_SIGNAL_REALTIME_104, 118, "SIG104", "Real-time event 104")
+SET (GDB_SIGNAL_REALTIME_105, 119, "SIG105", "Real-time event 105")
+SET (GDB_SIGNAL_REALTIME_106, 120, "SIG106", "Real-time event 106")
+SET (GDB_SIGNAL_REALTIME_107, 121, "SIG107", "Real-time event 107")
+SET (GDB_SIGNAL_REALTIME_108, 122, "SIG108", "Real-time event 108")
+SET (GDB_SIGNAL_REALTIME_109, 123, "SIG109", "Real-time event 109")
+SET (GDB_SIGNAL_REALTIME_110, 124, "SIG110", "Real-time event 110")
+SET (GDB_SIGNAL_REALTIME_111, 125, "SIG111", "Real-time event 111")
+SET (GDB_SIGNAL_REALTIME_112, 126, "SIG112", "Real-time event 112")
+SET (GDB_SIGNAL_REALTIME_113, 127, "SIG113", "Real-time event 113")
+SET (GDB_SIGNAL_REALTIME_114, 128, "SIG114", "Real-time event 114")
+SET (GDB_SIGNAL_REALTIME_115, 129, "SIG115", "Real-time event 115")
+SET (GDB_SIGNAL_REALTIME_116, 130, "SIG116", "Real-time event 116")
+SET (GDB_SIGNAL_REALTIME_117, 131, "SIG117", "Real-time event 117")
+SET (GDB_SIGNAL_REALTIME_118, 132, "SIG118", "Real-time event 118")
+SET (GDB_SIGNAL_REALTIME_119, 133, "SIG119", "Real-time event 119")
+SET (GDB_SIGNAL_REALTIME_120, 134, "SIG120", "Real-time event 120")
+SET (GDB_SIGNAL_REALTIME_121, 135, "SIG121", "Real-time event 121")
+SET (GDB_SIGNAL_REALTIME_122, 136, "SIG122", "Real-time event 122")
+SET (GDB_SIGNAL_REALTIME_123, 137, "SIG123", "Real-time event 123")
+SET (GDB_SIGNAL_REALTIME_124, 138, "SIG124", "Real-time event 124")
+SET (GDB_SIGNAL_REALTIME_125, 139, "SIG125", "Real-time event 125")
+SET (GDB_SIGNAL_REALTIME_126, 140, "SIG126", "Real-time event 126")
+SET (GDB_SIGNAL_REALTIME_127, 141, "SIG127", "Real-time event 127")
+
+SET (GDB_SIGNAL_INFO, 142, "SIGINFO", "Information request")
+
+/* Some signal we don't know about.  */
+SET (GDB_SIGNAL_UNKNOWN, 143, NULL, "Unknown signal")
+
+/* Use whatever signal we use when one is not specifically specified
+   (for passing to proceed and so on).  */
+SET (GDB_SIGNAL_DEFAULT, 144, NULL,
+     "Internal error: printing GDB_SIGNAL_DEFAULT")
+
+/* Mach exceptions.  In versions of GDB before 5.2, these were just before
+   GDB_SIGNAL_INFO if you were compiling on a Mach host (and missing
+   otherwise).  */
+SET (TARGET_EXC_BAD_ACCESS, 145, "EXC_BAD_ACCESS", "Could not access memory")
+SET (TARGET_EXC_BAD_INSTRUCTION, 146, "EXC_BAD_INSTRUCTION",
+     "Illegal instruction/operand")
+SET (TARGET_EXC_ARITHMETIC, 147, "EXC_ARITHMETIC", "Arithmetic exception")
+SET (TARGET_EXC_EMULATION, 148, "EXC_EMULATION", "Emulation instruction")
+SET (TARGET_EXC_SOFTWARE, 149, "EXC_SOFTWARE", "Software generated exception")
+SET (TARGET_EXC_BREAKPOINT, 150, "EXC_BREAKPOINT", "Breakpoint")
+
+/* If you are adding a new signal, add it just above this comment.  */
+
+/* Last and unused enum value, for sizing arrays, etc.  */
+SET (GDB_SIGNAL_LAST, 151, NULL, "GDB_SIGNAL_MAGIC")
diff --git a/binutils-2.25/include/gdb/signals.h b/binutils-2.25/include/gdb/signals.h
new file mode 100644
index 00000000..1ee2c161
--- /dev/null
+++ b/binutils-2.25/include/gdb/signals.h
@@ -0,0 +1,58 @@
+/* Target signal numbers for GDB and the GDB remote protocol.
+   Copyright 1986-2013 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#ifndef GDB_SIGNALS_H
+#define GDB_SIGNALS_H
+
+/* The numbering of these signals is chosen to match traditional unix
+   signals (insofar as various unices use the same numbers, anyway).
+   It is also the numbering of the GDB remote protocol.  Other remote
+   protocols, if they use a different numbering, should make sure to
+   translate appropriately.
+
+   Since these numbers have actually made it out into other software
+   (stubs, etc.), you mustn't disturb the assigned numbering.  If you
+   need to add new signals here, add them to the end of the explicitly
+   numbered signals, at the comment marker.  Add them unconditionally,
+   not within any #if or #ifdef.
+
+   This is based strongly on Unix/POSIX signals for several reasons:
+   (1) This set of signals represents a widely-accepted attempt to
+   represent events of this sort in a portable fashion, (2) we want a
+   signal to make it from wait to child_wait to the user intact, (3) many
+   remote protocols use a similar encoding.  However, it is
+   recognized that this set of signals has limitations (such as not
+   distinguishing between various kinds of SIGSEGV, or not
+   distinguishing hitting a breakpoint from finishing a single step).
+   So in the future we may get around this either by adding additional
+   signals for breakpoint, single-step, etc., or by adding signal
+   codes; the latter seems more in the spirit of what BSD, System V,
+   etc. are doing to address these issues.  */
+
+/* For an explanation of what each signal means, see
+   gdb_signal_to_string.  */
+
+enum gdb_signal
+  {
+#define SET(symbol, constant, name, string) \
+    symbol = constant,
+#include "gdb/signals.def"
+#undef SET
+  };
+
+#endif /* #ifndef GDB_SIGNALS_H */
diff --git a/binutils-2.25/include/gdb/sim-arm.h b/binutils-2.25/include/gdb/sim-arm.h
new file mode 100644
index 00000000..cae062f1
--- /dev/null
+++ b/binutils-2.25/include/gdb/sim-arm.h
@@ -0,0 +1,112 @@
+/* This file defines the interface between the Arm simulator and GDB.
+
+   Copyright 2002-2013 Free Software Foundation, Inc.
+
+   Contributed by Red Hat.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#if !defined (SIM_ARM_H)
+#define SIM_ARM_H
+
+#ifdef __cplusplus
+extern "C" { // }
+#endif
+
+enum sim_arm_regs
+{
+  SIM_ARM_R0_REGNUM,
+  SIM_ARM_R1_REGNUM,
+  SIM_ARM_R2_REGNUM,
+  SIM_ARM_R3_REGNUM,
+  SIM_ARM_R4_REGNUM,
+  SIM_ARM_R5_REGNUM,
+  SIM_ARM_R6_REGNUM,
+  SIM_ARM_R7_REGNUM,
+  SIM_ARM_R8_REGNUM,
+  SIM_ARM_R9_REGNUM,
+  SIM_ARM_R10_REGNUM,
+  SIM_ARM_R11_REGNUM,
+  SIM_ARM_R12_REGNUM,
+  SIM_ARM_R13_REGNUM,
+  SIM_ARM_R14_REGNUM,
+  SIM_ARM_R15_REGNUM, /* PC */
+  SIM_ARM_FP0_REGNUM,
+  SIM_ARM_FP1_REGNUM,
+  SIM_ARM_FP2_REGNUM,
+  SIM_ARM_FP3_REGNUM,
+  SIM_ARM_FP4_REGNUM,
+  SIM_ARM_FP5_REGNUM,
+  SIM_ARM_FP6_REGNUM,
+  SIM_ARM_FP7_REGNUM,
+  SIM_ARM_FPS_REGNUM,
+  SIM_ARM_PS_REGNUM,
+  SIM_ARM_MAVERIC_COP0R0_REGNUM,
+  SIM_ARM_MAVERIC_COP0R1_REGNUM,
+  SIM_ARM_MAVERIC_COP0R2_REGNUM,
+  SIM_ARM_MAVERIC_COP0R3_REGNUM,
+  SIM_ARM_MAVERIC_COP0R4_REGNUM,
+  SIM_ARM_MAVERIC_COP0R5_REGNUM,
+  SIM_ARM_MAVERIC_COP0R6_REGNUM,
+  SIM_ARM_MAVERIC_COP0R7_REGNUM,
+  SIM_ARM_MAVERIC_COP0R8_REGNUM,
+  SIM_ARM_MAVERIC_COP0R9_REGNUM,
+  SIM_ARM_MAVERIC_COP0R10_REGNUM,
+  SIM_ARM_MAVERIC_COP0R11_REGNUM,
+  SIM_ARM_MAVERIC_COP0R12_REGNUM,
+  SIM_ARM_MAVERIC_COP0R13_REGNUM,
+  SIM_ARM_MAVERIC_COP0R14_REGNUM,
+  SIM_ARM_MAVERIC_COP0R15_REGNUM,
+  SIM_ARM_MAVERIC_DSPSC_REGNUM,
+  SIM_ARM_IWMMXT_COP0R0_REGNUM,
+  SIM_ARM_IWMMXT_COP0R1_REGNUM,
+  SIM_ARM_IWMMXT_COP0R2_REGNUM,
+  SIM_ARM_IWMMXT_COP0R3_REGNUM,
+  SIM_ARM_IWMMXT_COP0R4_REGNUM,
+  SIM_ARM_IWMMXT_COP0R5_REGNUM,
+  SIM_ARM_IWMMXT_COP0R6_REGNUM,
+  SIM_ARM_IWMMXT_COP0R7_REGNUM,
+  SIM_ARM_IWMMXT_COP0R8_REGNUM,
+  SIM_ARM_IWMMXT_COP0R9_REGNUM,
+  SIM_ARM_IWMMXT_COP0R10_REGNUM,
+  SIM_ARM_IWMMXT_COP0R11_REGNUM,
+  SIM_ARM_IWMMXT_COP0R12_REGNUM,
+  SIM_ARM_IWMMXT_COP0R13_REGNUM,
+  SIM_ARM_IWMMXT_COP0R14_REGNUM,
+  SIM_ARM_IWMMXT_COP0R15_REGNUM,
+  SIM_ARM_IWMMXT_COP1R0_REGNUM,
+  SIM_ARM_IWMMXT_COP1R1_REGNUM,
+  SIM_ARM_IWMMXT_COP1R2_REGNUM,
+  SIM_ARM_IWMMXT_COP1R3_REGNUM,
+  SIM_ARM_IWMMXT_COP1R4_REGNUM,
+  SIM_ARM_IWMMXT_COP1R5_REGNUM,
+  SIM_ARM_IWMMXT_COP1R6_REGNUM,
+  SIM_ARM_IWMMXT_COP1R7_REGNUM,
+  SIM_ARM_IWMMXT_COP1R8_REGNUM,
+  SIM_ARM_IWMMXT_COP1R9_REGNUM,
+  SIM_ARM_IWMMXT_COP1R10_REGNUM,
+  SIM_ARM_IWMMXT_COP1R11_REGNUM,
+  SIM_ARM_IWMMXT_COP1R12_REGNUM,
+  SIM_ARM_IWMMXT_COP1R13_REGNUM,
+  SIM_ARM_IWMMXT_COP1R14_REGNUM,
+  SIM_ARM_IWMMXT_COP1R15_REGNUM
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/binutils-2.25/include/gdb/sim-bfin.h b/binutils-2.25/include/gdb/sim-bfin.h
new file mode 100644
index 00000000..ef2a1154
--- /dev/null
+++ b/binutils-2.25/include/gdb/sim-bfin.h
@@ -0,0 +1,82 @@
+/* This file defines the interface between the Blackfin simulator and GDB.
+
+   Copyright (C) 2005-2013 Free Software Foundation, Inc.
+   Contributed by Analog Devices.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+enum sim_bfin_regnum {
+  SIM_BFIN_R0_REGNUM = 0,
+  SIM_BFIN_R1_REGNUM,
+  SIM_BFIN_R2_REGNUM,
+  SIM_BFIN_R3_REGNUM,
+  SIM_BFIN_R4_REGNUM,
+  SIM_BFIN_R5_REGNUM,
+  SIM_BFIN_R6_REGNUM,
+  SIM_BFIN_R7_REGNUM,
+  SIM_BFIN_P0_REGNUM,
+  SIM_BFIN_P1_REGNUM,
+  SIM_BFIN_P2_REGNUM,
+  SIM_BFIN_P3_REGNUM,
+  SIM_BFIN_P4_REGNUM,
+  SIM_BFIN_P5_REGNUM,
+  SIM_BFIN_SP_REGNUM,
+  SIM_BFIN_FP_REGNUM,
+  SIM_BFIN_I0_REGNUM,
+  SIM_BFIN_I1_REGNUM,
+  SIM_BFIN_I2_REGNUM,
+  SIM_BFIN_I3_REGNUM,
+  SIM_BFIN_M0_REGNUM,
+  SIM_BFIN_M1_REGNUM,
+  SIM_BFIN_M2_REGNUM,
+  SIM_BFIN_M3_REGNUM,
+  SIM_BFIN_B0_REGNUM,
+  SIM_BFIN_B1_REGNUM,
+  SIM_BFIN_B2_REGNUM,
+  SIM_BFIN_B3_REGNUM,
+  SIM_BFIN_L0_REGNUM,
+  SIM_BFIN_L1_REGNUM,
+  SIM_BFIN_L2_REGNUM,
+  SIM_BFIN_L3_REGNUM,
+  SIM_BFIN_A0_DOT_X_REGNUM,
+  SIM_BFIN_A0_DOT_W_REGNUM,
+  SIM_BFIN_A1_DOT_X_REGNUM,
+  SIM_BFIN_A1_DOT_W_REGNUM,
+  SIM_BFIN_ASTAT_REGNUM,
+  SIM_BFIN_RETS_REGNUM,
+  SIM_BFIN_LC0_REGNUM,
+  SIM_BFIN_LT0_REGNUM,
+  SIM_BFIN_LB0_REGNUM,
+  SIM_BFIN_LC1_REGNUM,
+  SIM_BFIN_LT1_REGNUM,
+  SIM_BFIN_LB1_REGNUM,
+  SIM_BFIN_CYCLES_REGNUM,
+  SIM_BFIN_CYCLES2_REGNUM,
+  SIM_BFIN_USP_REGNUM,
+  SIM_BFIN_SEQSTAT_REGNUM,
+  SIM_BFIN_SYSCFG_REGNUM,
+  SIM_BFIN_RETI_REGNUM,
+  SIM_BFIN_RETX_REGNUM,
+  SIM_BFIN_RETN_REGNUM,
+  SIM_BFIN_RETE_REGNUM,
+  SIM_BFIN_PC_REGNUM,
+  SIM_BFIN_CC_REGNUM,
+  SIM_BFIN_TEXT_ADDR,
+  SIM_BFIN_TEXT_END_ADDR,
+  SIM_BFIN_DATA_ADDR,
+  SIM_BFIN_IPEND_REGNUM
+};
+
diff --git a/binutils-2.25/include/gdb/sim-cr16.h b/binutils-2.25/include/gdb/sim-cr16.h
new file mode 100644
index 00000000..1503657a
--- /dev/null
+++ b/binutils-2.25/include/gdb/sim-cr16.h
@@ -0,0 +1,106 @@
+/* This file defines the interface between the cr16 simulator and gdb.
+
+   Copyright 2008-2013 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License 
+   along with this program; if not, see <http://www.gnu.org/licenses/>.  */
+
+#if !defined (SIM_CR16_H)
+#define SIM_CR16_H
+
+#ifdef __cplusplus
+extern "C" { // }
+#endif
+
+enum
+  {
+    SIM_CR16_MEMORY_UNIFIED = 0x00000000,
+    SIM_CR16_MEMORY_INSN    = 0x10000000,
+    SIM_CR16_MEMORY_DATA    = 0x10000000,
+    SIM_CR16_MEMORY_DMAP    = 0x10000000,
+    SIM_CR16_MEMORY_IMAP    = 0x10000000
+  };
+
+extern unsigned long sim_cr16_translate_dmap_addr
+  (unsigned long offset,
+   int nr_bytes,
+   unsigned long *phys,
+   void *regcache,
+   unsigned long (*dmap_register) (void *regcache, int reg_nr));
+
+extern unsigned long sim_cr16_translate_imap_addr
+  (unsigned long offset,
+   int nr_bytes,
+   unsigned long *phys,
+   void *regcache,
+   unsigned long (*imap_register) (void *regcache, int reg_nr));
+
+extern unsigned long sim_cr16_translate_addr
+  (unsigned long vaddr,
+   int nr_bytes,
+   unsigned long *phys,
+   void *regcache,
+   unsigned long (*dmap_register) (void *regcache, int reg_nr),
+   unsigned long (*imap_register) (void *regcache, int reg_nr));
+
+
+/* The simulator makes use of the following register information. */
+
+enum sim_cr16_regs
+{
+  SIM_CR16_R0_REGNUM,
+  SIM_CR16_R1_REGNUM,
+  SIM_CR16_R2_REGNUM,
+  SIM_CR16_R3_REGNUM,
+  SIM_CR16_R4_REGNUM,
+  SIM_CR16_R5_REGNUM,
+  SIM_CR16_R6_REGNUM,
+  SIM_CR16_R7_REGNUM,
+  SIM_CR16_R8_REGNUM,
+  SIM_CR16_R9_REGNUM,
+  SIM_CR16_R10_REGNUM,
+  SIM_CR16_R11_REGNUM,
+  SIM_CR16_R12_REGNUM,
+  SIM_CR16_R13_REGNUM,
+  SIM_CR16_R14_REGNUM,
+  SIM_CR16_R15_REGNUM,
+
+  SIM_CR16_PC_REGNUM,
+  SIM_CR16_ISP_REGNUM,
+  SIM_CR16_USP_REGNUM,
+  SIM_CR16_INTBASE_REGNUM,
+  SIM_CR16_PSR_REGNUM,
+  SIM_CR16_CFG_REGNUM,
+  SIM_CR16_DBS_REGNUM,
+  SIM_CR16_DCR_REGNUM,
+  SIM_CR16_DSR_REGNUM,
+  SIM_CR16_CAR0_REGNUM,
+  SIM_CR16_CAR1_REGNUM
+};
+  
+enum
+{
+  SIM_CR16_NR_R_REGS = 16,
+  SIM_CR16_NR_A_REGS = 2,
+  SIM_CR16_NR_IMAP_REGS = 2,
+  SIM_CR16_NR_DMAP_REGS = 4,
+  SIM_CR16_NR_CR_REGS = 11
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/binutils-2.25/include/gdb/sim-d10v.h b/binutils-2.25/include/gdb/sim-d10v.h
new file mode 100644
index 00000000..12eaa63e
--- /dev/null
+++ b/binutils-2.25/include/gdb/sim-d10v.h
@@ -0,0 +1,141 @@
+/* This file defines the interface between the d10v simulator and gdb.
+
+   Copyright 1999-2013 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#if !defined (SIM_D10V_H)
+#define SIM_D10V_H
+
+#ifdef __cplusplus
+extern "C" { // }
+#endif
+
+/* GDB interprets addresses as:
+
+   0x00xxxxxx: Physical unified memory segment     (Unified memory)
+   0x01xxxxxx: Physical instruction memory segment (On-chip insn memory)
+   0x02xxxxxx: Physical data memory segment        (On-chip data memory)
+   0x10xxxxxx: Logical data address segment        (DMAP translated memory)
+   0x11xxxxxx: Logical instruction address segment (IMAP translated memory)
+
+   The remote d10v board interprets addresses as:
+
+   0x00xxxxxx: Physical unified memory segment     (Unified memory)
+   0x01xxxxxx: Physical instruction memory segment (On-chip insn memory)
+   0x02xxxxxx: Physical data memory segment        (On-chip data memory)
+
+   The following translate a virtual DMAP/IMAP offset into a physical
+   memory segment assigning the translated address to PHYS.  Since a
+   memory access may cross a page boundrary the number of bytes for
+   which the translation is applicable (or 0 for an invalid virtual
+   offset) is returned. */
+
+enum
+  {
+    SIM_D10V_MEMORY_UNIFIED = 0x00000000,
+    SIM_D10V_MEMORY_INSN = 0x01000000,
+    SIM_D10V_MEMORY_DATA = 0x02000000,
+    SIM_D10V_MEMORY_DMAP = 0x10000000,
+    SIM_D10V_MEMORY_IMAP = 0x11000000
+  };
+
+extern unsigned long sim_d10v_translate_dmap_addr
+  (unsigned long offset,
+   int nr_bytes,
+   unsigned long *phys,
+   void *regcache,
+   unsigned long (*dmap_register) (void *regcache, int reg_nr));
+
+extern unsigned long sim_d10v_translate_imap_addr
+  (unsigned long offset,
+   int nr_bytes,
+   unsigned long *phys,
+   void *regcache,
+   unsigned long (*imap_register) (void *regcache, int reg_nr));
+
+extern unsigned long sim_d10v_translate_addr
+  (unsigned long vaddr,
+   int nr_bytes,
+   unsigned long *phys,
+   void *regcache,
+   unsigned long (*dmap_register) (void *regcache, int reg_nr),
+   unsigned long (*imap_register) (void *regcache, int reg_nr));
+
+
+/* The simulator makes use of the following register information. */
+
+enum sim_d10v_regs
+{
+  SIM_D10V_R0_REGNUM,
+  SIM_D10V_R1_REGNUM,
+  SIM_D10V_R2_REGNUM,
+  SIM_D10V_R3_REGNUM,
+  SIM_D10V_R4_REGNUM,
+  SIM_D10V_R5_REGNUM,
+  SIM_D10V_R6_REGNUM,
+  SIM_D10V_R7_REGNUM,
+  SIM_D10V_R8_REGNUM,
+  SIM_D10V_R9_REGNUM,
+  SIM_D10V_R10_REGNUM,
+  SIM_D10V_R11_REGNUM,
+  SIM_D10V_R12_REGNUM,
+  SIM_D10V_R13_REGNUM,
+  SIM_D10V_R14_REGNUM,
+  SIM_D10V_R15_REGNUM,
+  SIM_D10V_CR0_REGNUM,
+  SIM_D10V_CR1_REGNUM,
+  SIM_D10V_CR2_REGNUM,
+  SIM_D10V_CR3_REGNUM,
+  SIM_D10V_CR4_REGNUM,
+  SIM_D10V_CR5_REGNUM,
+  SIM_D10V_CR6_REGNUM,
+  SIM_D10V_CR7_REGNUM,
+  SIM_D10V_CR8_REGNUM,
+  SIM_D10V_CR9_REGNUM,
+  SIM_D10V_CR10_REGNUM,
+  SIM_D10V_CR11_REGNUM,
+  SIM_D10V_CR12_REGNUM,
+  SIM_D10V_CR13_REGNUM,
+  SIM_D10V_CR14_REGNUM,
+  SIM_D10V_CR15_REGNUM,
+  SIM_D10V_A0_REGNUM,
+  SIM_D10V_A1_REGNUM,
+  SIM_D10V_SPI_REGNUM,
+  SIM_D10V_SPU_REGNUM,
+  SIM_D10V_IMAP0_REGNUM,
+  SIM_D10V_IMAP1_REGNUM,
+  SIM_D10V_DMAP0_REGNUM,
+  SIM_D10V_DMAP1_REGNUM,
+  SIM_D10V_DMAP2_REGNUM,
+  SIM_D10V_DMAP3_REGNUM,
+  SIM_D10V_TS2_DMAP_REGNUM
+};
+  
+enum
+{
+  SIM_D10V_NR_R_REGS = 16,
+  SIM_D10V_NR_A_REGS = 2,
+  SIM_D10V_NR_IMAP_REGS = 2,
+  SIM_D10V_NR_DMAP_REGS = 4,
+  SIM_D10V_NR_CR_REGS = 16
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/binutils-2.25/include/gdb/sim-frv.h b/binutils-2.25/include/gdb/sim-frv.h
new file mode 100644
index 00000000..bdb17f8e
--- /dev/null
+++ b/binutils-2.25/include/gdb/sim-frv.h
@@ -0,0 +1,51 @@
+/* This file defines the interface between the FR-V simulator and GDB.
+
+   Copyright 2003-2013 Free Software Foundation, Inc.
+
+   Contributed by Red Hat.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#if !defined (SIM_FRV_H)
+#define SIM_FRV_H
+
+#ifdef __cplusplus
+extern "C" { // }
+#endif
+
+enum sim_frv_regs
+{
+  SIM_FRV_GR0_REGNUM  = 0,
+  SIM_FRV_GR63_REGNUM = 63,
+  SIM_FRV_FR0_REGNUM  = 64,
+  SIM_FRV_FR63_REGNUM = 127,
+  SIM_FRV_PC_REGNUM   = 128,
+
+  /* An FR-V architecture may have up to 4096 special purpose registers
+     (SPRs).  In order to determine a specific constant used to access
+     a particular SPR, one of the H_SPR_ prefixed offsets defined in
+     opcodes/frv-desc.h should be added to SIM_FRV_SPR0_REGNUM.  So,
+     for example, the number that GDB uses to fetch the link register
+     from the simulator is (SIM_FRV_SPR0_REGNUM + H_SPR_LR).  */
+  SIM_FRV_SPR0_REGNUM = 129,
+  SIM_FRV_SPR4095_REGNUM = SIM_FRV_SPR0_REGNUM + 4095
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/binutils-2.25/include/gdb/sim-h8300.h b/binutils-2.25/include/gdb/sim-h8300.h
new file mode 100644
index 00000000..1649b52e
--- /dev/null
+++ b/binutils-2.25/include/gdb/sim-h8300.h
@@ -0,0 +1,77 @@
+/* This file defines the interface between the h8300 simulator and gdb.
+   Copyright (C) 2002-2013 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#if !defined (SIM_H8300_H)
+#define SIM_H8300_H
+
+#ifdef __cplusplus
+extern "C" { //}
+#endif
+
+/* The simulator makes use of the following register information. */
+
+  enum sim_h8300_regs
+  {
+    /* Registers common to all the H8 variants. */
+    /* Start here: */
+    SIM_H8300_R0_REGNUM,
+    SIM_H8300_R1_REGNUM,
+    SIM_H8300_R2_REGNUM,
+    SIM_H8300_R3_REGNUM,
+    SIM_H8300_R4_REGNUM,
+    SIM_H8300_R5_REGNUM,
+    SIM_H8300_R6_REGNUM,
+    SIM_H8300_R7_REGNUM,
+
+    SIM_H8300_CCR_REGNUM,  /* Contains processor status */
+    SIM_H8300_PC_REGNUM,   /* Contains program counter */
+    /* End here */
+
+    SIM_H8300_EXR_REGNUM,  /* Contains extended processor status
+                              H8S and higher */
+    SIM_H8300_MACL_REGNUM, /* Lower part of MAC register (26xx only)*/
+    SIM_H8300_MACH_REGNUM, /* High part of MAC register (26xx only) */
+
+    SIM_H8300_CYCLE_REGNUM,
+    SIM_H8300_INST_REGNUM,
+    SIM_H8300_TICK_REGNUM
+  };
+
+  enum
+  {
+    SIM_H8300_ARG_FIRST_REGNUM = SIM_H8300_R0_REGNUM, /* first reg in which an arg
+                                                         may be passed */
+    SIM_H8300_ARG_LAST_REGNUM = SIM_H8300_R3_REGNUM,  /* last  reg in which an arg
+                                                         may be passed */
+    SIM_H8300_FP_REGNUM = SIM_H8300_R6_REGNUM, /* Contain address of executing
+                                                  stack frame */
+    SIM_H8300_SP_REGNUM = SIM_H8300_R7_REGNUM  /* Contains address of top of stack */
+  };
+
+  enum
+  {
+    SIM_H8300_NUM_COMMON_REGS = 10,
+    SIM_H8300_S_NUM_REGS = 13,
+    SIM_H8300_NUM_REGS = 16
+  };
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif				/* SIM_H8300_H */
diff --git a/binutils-2.25/include/gdb/sim-lm32.h b/binutils-2.25/include/gdb/sim-lm32.h
new file mode 100644
index 00000000..b04d8d61
--- /dev/null
+++ b/binutils-2.25/include/gdb/sim-lm32.h
@@ -0,0 +1,76 @@
+/* This file defines the interface between the LM32 simulator and GDB.
+   Contributed by Jon Beniston <jon@beniston.com>
+
+   Copyright (C) 2009-2013 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#ifndef SIM_LM32_H
+#define SIM_LM32_H
+
+#ifdef __cplusplus
+extern "C" { // }
+#endif
+
+enum sim_lm32_regs
+{
+  SIM_LM32_R0_REGNUM,
+  SIM_LM32_R1_REGNUM,     
+  SIM_LM32_R2_REGNUM,     
+  SIM_LM32_R3_REGNUM,     
+  SIM_LM32_R4_REGNUM,     
+  SIM_LM32_R5_REGNUM,     
+  SIM_LM32_R6_REGNUM,     
+  SIM_LM32_R7_REGNUM,     
+  SIM_LM32_R8_REGNUM,     
+  SIM_LM32_R9_REGNUM,     
+  SIM_LM32_R10_REGNUM,    
+  SIM_LM32_R11_REGNUM,    
+  SIM_LM32_R12_REGNUM,    
+  SIM_LM32_R13_REGNUM,    
+  SIM_LM32_R14_REGNUM,    
+  SIM_LM32_R15_REGNUM,    
+  SIM_LM32_R16_REGNUM,    
+  SIM_LM32_R17_REGNUM,    
+  SIM_LM32_R18_REGNUM,    
+  SIM_LM32_R19_REGNUM,    
+  SIM_LM32_R20_REGNUM,    
+  SIM_LM32_R21_REGNUM,    
+  SIM_LM32_R22_REGNUM,    
+  SIM_LM32_R23_REGNUM,    
+  SIM_LM32_R24_REGNUM,    
+  SIM_LM32_R25_REGNUM,    
+  SIM_LM32_GP_REGNUM,     
+  SIM_LM32_FP_REGNUM,     
+  SIM_LM32_SP_REGNUM,     
+  SIM_LM32_RA_REGNUM,     
+  SIM_LM32_BA_REGNUM,     
+  SIM_LM32_EA_REGNUM,     
+  SIM_LM32_PC_REGNUM,
+  SIM_LM32_EID_REGNUM,
+  SIM_LM32_EBA_REGNUM,  
+  SIM_LM32_DEBA_REGNUM, 
+  SIM_LM32_IE_REGNUM,  
+  SIM_LM32_IM_REGNUM,  
+  SIM_LM32_IP_REGNUM,  
+  SIM_LM32_NUM_REGS      
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/binutils-2.25/include/gdb/sim-m32c.h b/binutils-2.25/include/gdb/sim-m32c.h
new file mode 100644
index 00000000..963ae047
--- /dev/null
+++ b/binutils-2.25/include/gdb/sim-m32c.h
@@ -0,0 +1,62 @@
+/* This file defines the interface between the m32c simulator and gdb.
+   Copyright (C) 2005-2013 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#ifndef SIM_M32C_H
+#define SIM_M32C_H
+
+enum m32c_sim_reg {
+  m32c_sim_reg_r0_bank0,
+  m32c_sim_reg_r1_bank0,
+  m32c_sim_reg_r2_bank0,
+  m32c_sim_reg_r3_bank0,
+  m32c_sim_reg_a0_bank0,
+  m32c_sim_reg_a1_bank0,
+  m32c_sim_reg_fb_bank0,
+  m32c_sim_reg_sb_bank0,
+  m32c_sim_reg_r0_bank1,
+  m32c_sim_reg_r1_bank1,
+  m32c_sim_reg_r2_bank1,
+  m32c_sim_reg_r3_bank1,
+  m32c_sim_reg_a0_bank1,
+  m32c_sim_reg_a1_bank1,
+  m32c_sim_reg_fb_bank1,
+  m32c_sim_reg_sb_bank1,
+  m32c_sim_reg_usp,
+  m32c_sim_reg_isp,
+  m32c_sim_reg_pc,
+  m32c_sim_reg_intb,
+  m32c_sim_reg_flg,
+  m32c_sim_reg_svf,
+  m32c_sim_reg_svp,
+  m32c_sim_reg_vct,
+  m32c_sim_reg_dmd0,
+  m32c_sim_reg_dmd1,
+  m32c_sim_reg_dct0,
+  m32c_sim_reg_dct1,
+  m32c_sim_reg_drc0,
+  m32c_sim_reg_drc1,
+  m32c_sim_reg_dma0,
+  m32c_sim_reg_dma1,
+  m32c_sim_reg_dsa0,
+  m32c_sim_reg_dsa1,
+  m32c_sim_reg_dra0,
+  m32c_sim_reg_dra1,
+  m32c_sim_reg_num_regs
+};
+
+#endif /* SIM_M32C_H */
diff --git a/binutils-2.25/include/gdb/sim-ppc.h b/binutils-2.25/include/gdb/sim-ppc.h
new file mode 100644
index 00000000..188eb49d
--- /dev/null
+++ b/binutils-2.25/include/gdb/sim-ppc.h
@@ -0,0 +1,773 @@
+/* sim-ppc.h --- interface between PowerPC simulator and GDB.
+
+   Copyright 2004-2013 Free Software Foundation, Inc.
+
+   Contributed by Red Hat.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#if !defined (SIM_PPC_H)
+#define SIM_PPC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* The register access functions, sim_fetch_register and
+   sim_store_register, use the following numbering for PowerPC
+   registers.  */
+
+enum sim_ppc_regnum
+  {
+    /* General-purpose registers, r0 -- r31.  */
+    sim_ppc_r0_regnum,
+    sim_ppc_r1_regnum,
+    sim_ppc_r2_regnum,
+    sim_ppc_r3_regnum,
+    sim_ppc_r4_regnum,
+    sim_ppc_r5_regnum,
+    sim_ppc_r6_regnum,
+    sim_ppc_r7_regnum,
+    sim_ppc_r8_regnum,
+    sim_ppc_r9_regnum,
+    sim_ppc_r10_regnum,
+    sim_ppc_r11_regnum,
+    sim_ppc_r12_regnum,
+    sim_ppc_r13_regnum,
+    sim_ppc_r14_regnum,
+    sim_ppc_r15_regnum,
+    sim_ppc_r16_regnum,
+    sim_ppc_r17_regnum,
+    sim_ppc_r18_regnum,
+    sim_ppc_r19_regnum,
+    sim_ppc_r20_regnum,
+    sim_ppc_r21_regnum,
+    sim_ppc_r22_regnum,
+    sim_ppc_r23_regnum,
+    sim_ppc_r24_regnum,
+    sim_ppc_r25_regnum,
+    sim_ppc_r26_regnum,
+    sim_ppc_r27_regnum,
+    sim_ppc_r28_regnum,
+    sim_ppc_r29_regnum,
+    sim_ppc_r30_regnum,
+    sim_ppc_r31_regnum,
+
+    /* Floating-point registers, f0 -- f31.  */
+    sim_ppc_f0_regnum,
+    sim_ppc_f1_regnum,
+    sim_ppc_f2_regnum,
+    sim_ppc_f3_regnum,
+    sim_ppc_f4_regnum,
+    sim_ppc_f5_regnum,
+    sim_ppc_f6_regnum,
+    sim_ppc_f7_regnum,
+    sim_ppc_f8_regnum,
+    sim_ppc_f9_regnum,
+    sim_ppc_f10_regnum,
+    sim_ppc_f11_regnum,
+    sim_ppc_f12_regnum,
+    sim_ppc_f13_regnum,
+    sim_ppc_f14_regnum,
+    sim_ppc_f15_regnum,
+    sim_ppc_f16_regnum,
+    sim_ppc_f17_regnum,
+    sim_ppc_f18_regnum,
+    sim_ppc_f19_regnum,
+    sim_ppc_f20_regnum,
+    sim_ppc_f21_regnum,
+    sim_ppc_f22_regnum,
+    sim_ppc_f23_regnum,
+    sim_ppc_f24_regnum,
+    sim_ppc_f25_regnum,
+    sim_ppc_f26_regnum,
+    sim_ppc_f27_regnum,
+    sim_ppc_f28_regnum,
+    sim_ppc_f29_regnum,
+    sim_ppc_f30_regnum,
+    sim_ppc_f31_regnum,
+
+    /* Altivec vector registers, vr0 -- vr31.  */
+    sim_ppc_vr0_regnum,
+    sim_ppc_vr1_regnum,
+    sim_ppc_vr2_regnum,
+    sim_ppc_vr3_regnum,
+    sim_ppc_vr4_regnum,
+    sim_ppc_vr5_regnum,
+    sim_ppc_vr6_regnum,
+    sim_ppc_vr7_regnum,
+    sim_ppc_vr8_regnum,
+    sim_ppc_vr9_regnum,
+    sim_ppc_vr10_regnum,
+    sim_ppc_vr11_regnum,
+    sim_ppc_vr12_regnum,
+    sim_ppc_vr13_regnum,
+    sim_ppc_vr14_regnum,
+    sim_ppc_vr15_regnum,
+    sim_ppc_vr16_regnum,
+    sim_ppc_vr17_regnum,
+    sim_ppc_vr18_regnum,
+    sim_ppc_vr19_regnum,
+    sim_ppc_vr20_regnum,
+    sim_ppc_vr21_regnum,
+    sim_ppc_vr22_regnum,
+    sim_ppc_vr23_regnum,
+    sim_ppc_vr24_regnum,
+    sim_ppc_vr25_regnum,
+    sim_ppc_vr26_regnum,
+    sim_ppc_vr27_regnum,
+    sim_ppc_vr28_regnum,
+    sim_ppc_vr29_regnum,
+    sim_ppc_vr30_regnum,
+    sim_ppc_vr31_regnum,
+
+    /* SPE APU GPR upper halves.  These are the upper 32 bits of the
+       gprs; there is one upper-half register for each gpr, so it is
+       appropriate to use sim_ppc_num_gprs for iterating through
+       these.  */
+    sim_ppc_rh0_regnum,
+    sim_ppc_rh1_regnum,
+    sim_ppc_rh2_regnum,
+    sim_ppc_rh3_regnum,
+    sim_ppc_rh4_regnum,
+    sim_ppc_rh5_regnum,
+    sim_ppc_rh6_regnum,
+    sim_ppc_rh7_regnum,
+    sim_ppc_rh8_regnum,
+    sim_ppc_rh9_regnum,
+    sim_ppc_rh10_regnum,
+    sim_ppc_rh11_regnum,
+    sim_ppc_rh12_regnum,
+    sim_ppc_rh13_regnum,
+    sim_ppc_rh14_regnum,
+    sim_ppc_rh15_regnum,
+    sim_ppc_rh16_regnum,
+    sim_ppc_rh17_regnum,
+    sim_ppc_rh18_regnum,
+    sim_ppc_rh19_regnum,
+    sim_ppc_rh20_regnum,
+    sim_ppc_rh21_regnum,
+    sim_ppc_rh22_regnum,
+    sim_ppc_rh23_regnum,
+    sim_ppc_rh24_regnum,
+    sim_ppc_rh25_regnum,
+    sim_ppc_rh26_regnum,
+    sim_ppc_rh27_regnum,
+    sim_ppc_rh28_regnum,
+    sim_ppc_rh29_regnum,
+    sim_ppc_rh30_regnum,
+    sim_ppc_rh31_regnum,
+
+    /* SPE APU GPR full registers.  Each of these registers is the
+       64-bit concatenation of a 32-bit GPR (providing the lower bits)
+       and a 32-bit upper-half register (providing the higher bits).
+       As for the upper-half registers, it is appropriate to use
+       sim_ppc_num_gprs with these.  */
+    sim_ppc_ev0_regnum,
+    sim_ppc_ev1_regnum,
+    sim_ppc_ev2_regnum,
+    sim_ppc_ev3_regnum,
+    sim_ppc_ev4_regnum,
+    sim_ppc_ev5_regnum,
+    sim_ppc_ev6_regnum,
+    sim_ppc_ev7_regnum,
+    sim_ppc_ev8_regnum,
+    sim_ppc_ev9_regnum,
+    sim_ppc_ev10_regnum,
+    sim_ppc_ev11_regnum,
+    sim_ppc_ev12_regnum,
+    sim_ppc_ev13_regnum,
+    sim_ppc_ev14_regnum,
+    sim_ppc_ev15_regnum,
+    sim_ppc_ev16_regnum,
+    sim_ppc_ev17_regnum,
+    sim_ppc_ev18_regnum,
+    sim_ppc_ev19_regnum,
+    sim_ppc_ev20_regnum,
+    sim_ppc_ev21_regnum,
+    sim_ppc_ev22_regnum,
+    sim_ppc_ev23_regnum,
+    sim_ppc_ev24_regnum,
+    sim_ppc_ev25_regnum,
+    sim_ppc_ev26_regnum,
+    sim_ppc_ev27_regnum,
+    sim_ppc_ev28_regnum,
+    sim_ppc_ev29_regnum,
+    sim_ppc_ev30_regnum,
+    sim_ppc_ev31_regnum,
+
+    /* Segment registers, sr0 -- sr15.  */
+    sim_ppc_sr0_regnum,
+    sim_ppc_sr1_regnum,
+    sim_ppc_sr2_regnum,
+    sim_ppc_sr3_regnum,
+    sim_ppc_sr4_regnum,
+    sim_ppc_sr5_regnum,
+    sim_ppc_sr6_regnum,
+    sim_ppc_sr7_regnum,
+    sim_ppc_sr8_regnum,
+    sim_ppc_sr9_regnum,
+    sim_ppc_sr10_regnum,
+    sim_ppc_sr11_regnum,
+    sim_ppc_sr12_regnum,
+    sim_ppc_sr13_regnum,
+    sim_ppc_sr14_regnum,
+    sim_ppc_sr15_regnum,
+
+    /* Miscellaneous --- but non-SPR --- registers.  */
+    sim_ppc_pc_regnum,
+    sim_ppc_ps_regnum,
+    sim_ppc_cr_regnum,
+    sim_ppc_fpscr_regnum,
+    sim_ppc_acc_regnum,
+    sim_ppc_vscr_regnum,
+
+    /* Special-purpose registers.  */
+    sim_ppc_spr0_regnum, sim_ppc_spr1_regnum,
+    sim_ppc_spr2_regnum, sim_ppc_spr3_regnum,
+    sim_ppc_spr4_regnum, sim_ppc_spr5_regnum,
+    sim_ppc_spr6_regnum, sim_ppc_spr7_regnum,
+    sim_ppc_spr8_regnum, sim_ppc_spr9_regnum,
+    sim_ppc_spr10_regnum, sim_ppc_spr11_regnum,
+    sim_ppc_spr12_regnum, sim_ppc_spr13_regnum,
+    sim_ppc_spr14_regnum, sim_ppc_spr15_regnum,
+    sim_ppc_spr16_regnum, sim_ppc_spr17_regnum,
+    sim_ppc_spr18_regnum, sim_ppc_spr19_regnum,
+    sim_ppc_spr20_regnum, sim_ppc_spr21_regnum,
+    sim_ppc_spr22_regnum, sim_ppc_spr23_regnum,
+    sim_ppc_spr24_regnum, sim_ppc_spr25_regnum,
+    sim_ppc_spr26_regnum, sim_ppc_spr27_regnum,
+    sim_ppc_spr28_regnum, sim_ppc_spr29_regnum,
+    sim_ppc_spr30_regnum, sim_ppc_spr31_regnum,
+    sim_ppc_spr32_regnum, sim_ppc_spr33_regnum,
+    sim_ppc_spr34_regnum, sim_ppc_spr35_regnum,
+    sim_ppc_spr36_regnum, sim_ppc_spr37_regnum,
+    sim_ppc_spr38_regnum, sim_ppc_spr39_regnum,
+    sim_ppc_spr40_regnum, sim_ppc_spr41_regnum,
+    sim_ppc_spr42_regnum, sim_ppc_spr43_regnum,
+    sim_ppc_spr44_regnum, sim_ppc_spr45_regnum,
+    sim_ppc_spr46_regnum, sim_ppc_spr47_regnum,
+    sim_ppc_spr48_regnum, sim_ppc_spr49_regnum,
+    sim_ppc_spr50_regnum, sim_ppc_spr51_regnum,
+    sim_ppc_spr52_regnum, sim_ppc_spr53_regnum,
+    sim_ppc_spr54_regnum, sim_ppc_spr55_regnum,
+    sim_ppc_spr56_regnum, sim_ppc_spr57_regnum,
+    sim_ppc_spr58_regnum, sim_ppc_spr59_regnum,
+    sim_ppc_spr60_regnum, sim_ppc_spr61_regnum,
+    sim_ppc_spr62_regnum, sim_ppc_spr63_regnum,
+    sim_ppc_spr64_regnum, sim_ppc_spr65_regnum,
+    sim_ppc_spr66_regnum, sim_ppc_spr67_regnum,
+    sim_ppc_spr68_regnum, sim_ppc_spr69_regnum,
+    sim_ppc_spr70_regnum, sim_ppc_spr71_regnum,
+    sim_ppc_spr72_regnum, sim_ppc_spr73_regnum,
+    sim_ppc_spr74_regnum, sim_ppc_spr75_regnum,
+    sim_ppc_spr76_regnum, sim_ppc_spr77_regnum,
+    sim_ppc_spr78_regnum, sim_ppc_spr79_regnum,
+    sim_ppc_spr80_regnum, sim_ppc_spr81_regnum,
+    sim_ppc_spr82_regnum, sim_ppc_spr83_regnum,
+    sim_ppc_spr84_regnum, sim_ppc_spr85_regnum,
+    sim_ppc_spr86_regnum, sim_ppc_spr87_regnum,
+    sim_ppc_spr88_regnum, sim_ppc_spr89_regnum,
+    sim_ppc_spr90_regnum, sim_ppc_spr91_regnum,
+    sim_ppc_spr92_regnum, sim_ppc_spr93_regnum,
+    sim_ppc_spr94_regnum, sim_ppc_spr95_regnum,
+    sim_ppc_spr96_regnum, sim_ppc_spr97_regnum,
+    sim_ppc_spr98_regnum, sim_ppc_spr99_regnum,
+    sim_ppc_spr100_regnum, sim_ppc_spr101_regnum,
+    sim_ppc_spr102_regnum, sim_ppc_spr103_regnum,
+    sim_ppc_spr104_regnum, sim_ppc_spr105_regnum,
+    sim_ppc_spr106_regnum, sim_ppc_spr107_regnum,
+    sim_ppc_spr108_regnum, sim_ppc_spr109_regnum,
+    sim_ppc_spr110_regnum, sim_ppc_spr111_regnum,
+    sim_ppc_spr112_regnum, sim_ppc_spr113_regnum,
+    sim_ppc_spr114_regnum, sim_ppc_spr115_regnum,
+    sim_ppc_spr116_regnum, sim_ppc_spr117_regnum,
+    sim_ppc_spr118_regnum, sim_ppc_spr119_regnum,
+    sim_ppc_spr120_regnum, sim_ppc_spr121_regnum,
+    sim_ppc_spr122_regnum, sim_ppc_spr123_regnum,
+    sim_ppc_spr124_regnum, sim_ppc_spr125_regnum,
+    sim_ppc_spr126_regnum, sim_ppc_spr127_regnum,
+    sim_ppc_spr128_regnum, sim_ppc_spr129_regnum,
+    sim_ppc_spr130_regnum, sim_ppc_spr131_regnum,
+    sim_ppc_spr132_regnum, sim_ppc_spr133_regnum,
+    sim_ppc_spr134_regnum, sim_ppc_spr135_regnum,
+    sim_ppc_spr136_regnum, sim_ppc_spr137_regnum,
+    sim_ppc_spr138_regnum, sim_ppc_spr139_regnum,
+    sim_ppc_spr140_regnum, sim_ppc_spr141_regnum,
+    sim_ppc_spr142_regnum, sim_ppc_spr143_regnum,
+    sim_ppc_spr144_regnum, sim_ppc_spr145_regnum,
+    sim_ppc_spr146_regnum, sim_ppc_spr147_regnum,
+    sim_ppc_spr148_regnum, sim_ppc_spr149_regnum,
+    sim_ppc_spr150_regnum, sim_ppc_spr151_regnum,
+    sim_ppc_spr152_regnum, sim_ppc_spr153_regnum,
+    sim_ppc_spr154_regnum, sim_ppc_spr155_regnum,
+    sim_ppc_spr156_regnum, sim_ppc_spr157_regnum,
+    sim_ppc_spr158_regnum, sim_ppc_spr159_regnum,
+    sim_ppc_spr160_regnum, sim_ppc_spr161_regnum,
+    sim_ppc_spr162_regnum, sim_ppc_spr163_regnum,
+    sim_ppc_spr164_regnum, sim_ppc_spr165_regnum,
+    sim_ppc_spr166_regnum, sim_ppc_spr167_regnum,
+    sim_ppc_spr168_regnum, sim_ppc_spr169_regnum,
+    sim_ppc_spr170_regnum, sim_ppc_spr171_regnum,
+    sim_ppc_spr172_regnum, sim_ppc_spr173_regnum,
+    sim_ppc_spr174_regnum, sim_ppc_spr175_regnum,
+    sim_ppc_spr176_regnum, sim_ppc_spr177_regnum,
+    sim_ppc_spr178_regnum, sim_ppc_spr179_regnum,
+    sim_ppc_spr180_regnum, sim_ppc_spr181_regnum,
+    sim_ppc_spr182_regnum, sim_ppc_spr183_regnum,
+    sim_ppc_spr184_regnum, sim_ppc_spr185_regnum,
+    sim_ppc_spr186_regnum, sim_ppc_spr187_regnum,
+    sim_ppc_spr188_regnum, sim_ppc_spr189_regnum,
+    sim_ppc_spr190_regnum, sim_ppc_spr191_regnum,
+    sim_ppc_spr192_regnum, sim_ppc_spr193_regnum,
+    sim_ppc_spr194_regnum, sim_ppc_spr195_regnum,
+    sim_ppc_spr196_regnum, sim_ppc_spr197_regnum,
+    sim_ppc_spr198_regnum, sim_ppc_spr199_regnum,
+    sim_ppc_spr200_regnum, sim_ppc_spr201_regnum,
+    sim_ppc_spr202_regnum, sim_ppc_spr203_regnum,
+    sim_ppc_spr204_regnum, sim_ppc_spr205_regnum,
+    sim_ppc_spr206_regnum, sim_ppc_spr207_regnum,
+    sim_ppc_spr208_regnum, sim_ppc_spr209_regnum,
+    sim_ppc_spr210_regnum, sim_ppc_spr211_regnum,
+    sim_ppc_spr212_regnum, sim_ppc_spr213_regnum,
+    sim_ppc_spr214_regnum, sim_ppc_spr215_regnum,
+    sim_ppc_spr216_regnum, sim_ppc_spr217_regnum,
+    sim_ppc_spr218_regnum, sim_ppc_spr219_regnum,
+    sim_ppc_spr220_regnum, sim_ppc_spr221_regnum,
+    sim_ppc_spr222_regnum, sim_ppc_spr223_regnum,
+    sim_ppc_spr224_regnum, sim_ppc_spr225_regnum,
+    sim_ppc_spr226_regnum, sim_ppc_spr227_regnum,
+    sim_ppc_spr228_regnum, sim_ppc_spr229_regnum,
+    sim_ppc_spr230_regnum, sim_ppc_spr231_regnum,
+    sim_ppc_spr232_regnum, sim_ppc_spr233_regnum,
+    sim_ppc_spr234_regnum, sim_ppc_spr235_regnum,
+    sim_ppc_spr236_regnum, sim_ppc_spr237_regnum,
+    sim_ppc_spr238_regnum, sim_ppc_spr239_regnum,
+    sim_ppc_spr240_regnum, sim_ppc_spr241_regnum,
+    sim_ppc_spr242_regnum, sim_ppc_spr243_regnum,
+    sim_ppc_spr244_regnum, sim_ppc_spr245_regnum,
+    sim_ppc_spr246_regnum, sim_ppc_spr247_regnum,
+    sim_ppc_spr248_regnum, sim_ppc_spr249_regnum,
+    sim_ppc_spr250_regnum, sim_ppc_spr251_regnum,
+    sim_ppc_spr252_regnum, sim_ppc_spr253_regnum,
+    sim_ppc_spr254_regnum, sim_ppc_spr255_regnum,
+    sim_ppc_spr256_regnum, sim_ppc_spr257_regnum,
+    sim_ppc_spr258_regnum, sim_ppc_spr259_regnum,
+    sim_ppc_spr260_regnum, sim_ppc_spr261_regnum,
+    sim_ppc_spr262_regnum, sim_ppc_spr263_regnum,
+    sim_ppc_spr264_regnum, sim_ppc_spr265_regnum,
+    sim_ppc_spr266_regnum, sim_ppc_spr267_regnum,
+    sim_ppc_spr268_regnum, sim_ppc_spr269_regnum,
+    sim_ppc_spr270_regnum, sim_ppc_spr271_regnum,
+    sim_ppc_spr272_regnum, sim_ppc_spr273_regnum,
+    sim_ppc_spr274_regnum, sim_ppc_spr275_regnum,
+    sim_ppc_spr276_regnum, sim_ppc_spr277_regnum,
+    sim_ppc_spr278_regnum, sim_ppc_spr279_regnum,
+    sim_ppc_spr280_regnum, sim_ppc_spr281_regnum,
+    sim_ppc_spr282_regnum, sim_ppc_spr283_regnum,
+    sim_ppc_spr284_regnum, sim_ppc_spr285_regnum,
+    sim_ppc_spr286_regnum, sim_ppc_spr287_regnum,
+    sim_ppc_spr288_regnum, sim_ppc_spr289_regnum,
+    sim_ppc_spr290_regnum, sim_ppc_spr291_regnum,
+    sim_ppc_spr292_regnum, sim_ppc_spr293_regnum,
+    sim_ppc_spr294_regnum, sim_ppc_spr295_regnum,
+    sim_ppc_spr296_regnum, sim_ppc_spr297_regnum,
+    sim_ppc_spr298_regnum, sim_ppc_spr299_regnum,
+    sim_ppc_spr300_regnum, sim_ppc_spr301_regnum,
+    sim_ppc_spr302_regnum, sim_ppc_spr303_regnum,
+    sim_ppc_spr304_regnum, sim_ppc_spr305_regnum,
+    sim_ppc_spr306_regnum, sim_ppc_spr307_regnum,
+    sim_ppc_spr308_regnum, sim_ppc_spr309_regnum,
+    sim_ppc_spr310_regnum, sim_ppc_spr311_regnum,
+    sim_ppc_spr312_regnum, sim_ppc_spr313_regnum,
+    sim_ppc_spr314_regnum, sim_ppc_spr315_regnum,
+    sim_ppc_spr316_regnum, sim_ppc_spr317_regnum,
+    sim_ppc_spr318_regnum, sim_ppc_spr319_regnum,
+    sim_ppc_spr320_regnum, sim_ppc_spr321_regnum,
+    sim_ppc_spr322_regnum, sim_ppc_spr323_regnum,
+    sim_ppc_spr324_regnum, sim_ppc_spr325_regnum,
+    sim_ppc_spr326_regnum, sim_ppc_spr327_regnum,
+    sim_ppc_spr328_regnum, sim_ppc_spr329_regnum,
+    sim_ppc_spr330_regnum, sim_ppc_spr331_regnum,
+    sim_ppc_spr332_regnum, sim_ppc_spr333_regnum,
+    sim_ppc_spr334_regnum, sim_ppc_spr335_regnum,
+    sim_ppc_spr336_regnum, sim_ppc_spr337_regnum,
+    sim_ppc_spr338_regnum, sim_ppc_spr339_regnum,
+    sim_ppc_spr340_regnum, sim_ppc_spr341_regnum,
+    sim_ppc_spr342_regnum, sim_ppc_spr343_regnum,
+    sim_ppc_spr344_regnum, sim_ppc_spr345_regnum,
+    sim_ppc_spr346_regnum, sim_ppc_spr347_regnum,
+    sim_ppc_spr348_regnum, sim_ppc_spr349_regnum,
+    sim_ppc_spr350_regnum, sim_ppc_spr351_regnum,
+    sim_ppc_spr352_regnum, sim_ppc_spr353_regnum,
+    sim_ppc_spr354_regnum, sim_ppc_spr355_regnum,
+    sim_ppc_spr356_regnum, sim_ppc_spr357_regnum,
+    sim_ppc_spr358_regnum, sim_ppc_spr359_regnum,
+    sim_ppc_spr360_regnum, sim_ppc_spr361_regnum,
+    sim_ppc_spr362_regnum, sim_ppc_spr363_regnum,
+    sim_ppc_spr364_regnum, sim_ppc_spr365_regnum,
+    sim_ppc_spr366_regnum, sim_ppc_spr367_regnum,
+    sim_ppc_spr368_regnum, sim_ppc_spr369_regnum,
+    sim_ppc_spr370_regnum, sim_ppc_spr371_regnum,
+    sim_ppc_spr372_regnum, sim_ppc_spr373_regnum,
+    sim_ppc_spr374_regnum, sim_ppc_spr375_regnum,
+    sim_ppc_spr376_regnum, sim_ppc_spr377_regnum,
+    sim_ppc_spr378_regnum, sim_ppc_spr379_regnum,
+    sim_ppc_spr380_regnum, sim_ppc_spr381_regnum,
+    sim_ppc_spr382_regnum, sim_ppc_spr383_regnum,
+    sim_ppc_spr384_regnum, sim_ppc_spr385_regnum,
+    sim_ppc_spr386_regnum, sim_ppc_spr387_regnum,
+    sim_ppc_spr388_regnum, sim_ppc_spr389_regnum,
+    sim_ppc_spr390_regnum, sim_ppc_spr391_regnum,
+    sim_ppc_spr392_regnum, sim_ppc_spr393_regnum,
+    sim_ppc_spr394_regnum, sim_ppc_spr395_regnum,
+    sim_ppc_spr396_regnum, sim_ppc_spr397_regnum,
+    sim_ppc_spr398_regnum, sim_ppc_spr399_regnum,
+    sim_ppc_spr400_regnum, sim_ppc_spr401_regnum,
+    sim_ppc_spr402_regnum, sim_ppc_spr403_regnum,
+    sim_ppc_spr404_regnum, sim_ppc_spr405_regnum,
+    sim_ppc_spr406_regnum, sim_ppc_spr407_regnum,
+    sim_ppc_spr408_regnum, sim_ppc_spr409_regnum,
+    sim_ppc_spr410_regnum, sim_ppc_spr411_regnum,
+    sim_ppc_spr412_regnum, sim_ppc_spr413_regnum,
+    sim_ppc_spr414_regnum, sim_ppc_spr415_regnum,
+    sim_ppc_spr416_regnum, sim_ppc_spr417_regnum,
+    sim_ppc_spr418_regnum, sim_ppc_spr419_regnum,
+    sim_ppc_spr420_regnum, sim_ppc_spr421_regnum,
+    sim_ppc_spr422_regnum, sim_ppc_spr423_regnum,
+    sim_ppc_spr424_regnum, sim_ppc_spr425_regnum,
+    sim_ppc_spr426_regnum, sim_ppc_spr427_regnum,
+    sim_ppc_spr428_regnum, sim_ppc_spr429_regnum,
+    sim_ppc_spr430_regnum, sim_ppc_spr431_regnum,
+    sim_ppc_spr432_regnum, sim_ppc_spr433_regnum,
+    sim_ppc_spr434_regnum, sim_ppc_spr435_regnum,
+    sim_ppc_spr436_regnum, sim_ppc_spr437_regnum,
+    sim_ppc_spr438_regnum, sim_ppc_spr439_regnum,
+    sim_ppc_spr440_regnum, sim_ppc_spr441_regnum,
+    sim_ppc_spr442_regnum, sim_ppc_spr443_regnum,
+    sim_ppc_spr444_regnum, sim_ppc_spr445_regnum,
+    sim_ppc_spr446_regnum, sim_ppc_spr447_regnum,
+    sim_ppc_spr448_regnum, sim_ppc_spr449_regnum,
+    sim_ppc_spr450_regnum, sim_ppc_spr451_regnum,
+    sim_ppc_spr452_regnum, sim_ppc_spr453_regnum,
+    sim_ppc_spr454_regnum, sim_ppc_spr455_regnum,
+    sim_ppc_spr456_regnum, sim_ppc_spr457_regnum,
+    sim_ppc_spr458_regnum, sim_ppc_spr459_regnum,
+    sim_ppc_spr460_regnum, sim_ppc_spr461_regnum,
+    sim_ppc_spr462_regnum, sim_ppc_spr463_regnum,
+    sim_ppc_spr464_regnum, sim_ppc_spr465_regnum,
+    sim_ppc_spr466_regnum, sim_ppc_spr467_regnum,
+    sim_ppc_spr468_regnum, sim_ppc_spr469_regnum,
+    sim_ppc_spr470_regnum, sim_ppc_spr471_regnum,
+    sim_ppc_spr472_regnum, sim_ppc_spr473_regnum,
+    sim_ppc_spr474_regnum, sim_ppc_spr475_regnum,
+    sim_ppc_spr476_regnum, sim_ppc_spr477_regnum,
+    sim_ppc_spr478_regnum, sim_ppc_spr479_regnum,
+    sim_ppc_spr480_regnum, sim_ppc_spr481_regnum,
+    sim_ppc_spr482_regnum, sim_ppc_spr483_regnum,
+    sim_ppc_spr484_regnum, sim_ppc_spr485_regnum,
+    sim_ppc_spr486_regnum, sim_ppc_spr487_regnum,
+    sim_ppc_spr488_regnum, sim_ppc_spr489_regnum,
+    sim_ppc_spr490_regnum, sim_ppc_spr491_regnum,
+    sim_ppc_spr492_regnum, sim_ppc_spr493_regnum,
+    sim_ppc_spr494_regnum, sim_ppc_spr495_regnum,
+    sim_ppc_spr496_regnum, sim_ppc_spr497_regnum,
+    sim_ppc_spr498_regnum, sim_ppc_spr499_regnum,
+    sim_ppc_spr500_regnum, sim_ppc_spr501_regnum,
+    sim_ppc_spr502_regnum, sim_ppc_spr503_regnum,
+    sim_ppc_spr504_regnum, sim_ppc_spr505_regnum,
+    sim_ppc_spr506_regnum, sim_ppc_spr507_regnum,
+    sim_ppc_spr508_regnum, sim_ppc_spr509_regnum,
+    sim_ppc_spr510_regnum, sim_ppc_spr511_regnum,
+    sim_ppc_spr512_regnum, sim_ppc_spr513_regnum,
+    sim_ppc_spr514_regnum, sim_ppc_spr515_regnum,
+    sim_ppc_spr516_regnum, sim_ppc_spr517_regnum,
+    sim_ppc_spr518_regnum, sim_ppc_spr519_regnum,
+    sim_ppc_spr520_regnum, sim_ppc_spr521_regnum,
+    sim_ppc_spr522_regnum, sim_ppc_spr523_regnum,
+    sim_ppc_spr524_regnum, sim_ppc_spr525_regnum,
+    sim_ppc_spr526_regnum, sim_ppc_spr527_regnum,
+    sim_ppc_spr528_regnum, sim_ppc_spr529_regnum,
+    sim_ppc_spr530_regnum, sim_ppc_spr531_regnum,
+    sim_ppc_spr532_regnum, sim_ppc_spr533_regnum,
+    sim_ppc_spr534_regnum, sim_ppc_spr535_regnum,
+    sim_ppc_spr536_regnum, sim_ppc_spr537_regnum,
+    sim_ppc_spr538_regnum, sim_ppc_spr539_regnum,
+    sim_ppc_spr540_regnum, sim_ppc_spr541_regnum,
+    sim_ppc_spr542_regnum, sim_ppc_spr543_regnum,
+    sim_ppc_spr544_regnum, sim_ppc_spr545_regnum,
+    sim_ppc_spr546_regnum, sim_ppc_spr547_regnum,
+    sim_ppc_spr548_regnum, sim_ppc_spr549_regnum,
+    sim_ppc_spr550_regnum, sim_ppc_spr551_regnum,
+    sim_ppc_spr552_regnum, sim_ppc_spr553_regnum,
+    sim_ppc_spr554_regnum, sim_ppc_spr555_regnum,
+    sim_ppc_spr556_regnum, sim_ppc_spr557_regnum,
+    sim_ppc_spr558_regnum, sim_ppc_spr559_regnum,
+    sim_ppc_spr560_regnum, sim_ppc_spr561_regnum,
+    sim_ppc_spr562_regnum, sim_ppc_spr563_regnum,
+    sim_ppc_spr564_regnum, sim_ppc_spr565_regnum,
+    sim_ppc_spr566_regnum, sim_ppc_spr567_regnum,
+    sim_ppc_spr568_regnum, sim_ppc_spr569_regnum,
+    sim_ppc_spr570_regnum, sim_ppc_spr571_regnum,
+    sim_ppc_spr572_regnum, sim_ppc_spr573_regnum,
+    sim_ppc_spr574_regnum, sim_ppc_spr575_regnum,
+    sim_ppc_spr576_regnum, sim_ppc_spr577_regnum,
+    sim_ppc_spr578_regnum, sim_ppc_spr579_regnum,
+    sim_ppc_spr580_regnum, sim_ppc_spr581_regnum,
+    sim_ppc_spr582_regnum, sim_ppc_spr583_regnum,
+    sim_ppc_spr584_regnum, sim_ppc_spr585_regnum,
+    sim_ppc_spr586_regnum, sim_ppc_spr587_regnum,
+    sim_ppc_spr588_regnum, sim_ppc_spr589_regnum,
+    sim_ppc_spr590_regnum, sim_ppc_spr591_regnum,
+    sim_ppc_spr592_regnum, sim_ppc_spr593_regnum,
+    sim_ppc_spr594_regnum, sim_ppc_spr595_regnum,
+    sim_ppc_spr596_regnum, sim_ppc_spr597_regnum,
+    sim_ppc_spr598_regnum, sim_ppc_spr599_regnum,
+    sim_ppc_spr600_regnum, sim_ppc_spr601_regnum,
+    sim_ppc_spr602_regnum, sim_ppc_spr603_regnum,
+    sim_ppc_spr604_regnum, sim_ppc_spr605_regnum,
+    sim_ppc_spr606_regnum, sim_ppc_spr607_regnum,
+    sim_ppc_spr608_regnum, sim_ppc_spr609_regnum,
+    sim_ppc_spr610_regnum, sim_ppc_spr611_regnum,
+    sim_ppc_spr612_regnum, sim_ppc_spr613_regnum,
+    sim_ppc_spr614_regnum, sim_ppc_spr615_regnum,
+    sim_ppc_spr616_regnum, sim_ppc_spr617_regnum,
+    sim_ppc_spr618_regnum, sim_ppc_spr619_regnum,
+    sim_ppc_spr620_regnum, sim_ppc_spr621_regnum,
+    sim_ppc_spr622_regnum, sim_ppc_spr623_regnum,
+    sim_ppc_spr624_regnum, sim_ppc_spr625_regnum,
+    sim_ppc_spr626_regnum, sim_ppc_spr627_regnum,
+    sim_ppc_spr628_regnum, sim_ppc_spr629_regnum,
+    sim_ppc_spr630_regnum, sim_ppc_spr631_regnum,
+    sim_ppc_spr632_regnum, sim_ppc_spr633_regnum,
+    sim_ppc_spr634_regnum, sim_ppc_spr635_regnum,
+    sim_ppc_spr636_regnum, sim_ppc_spr637_regnum,
+    sim_ppc_spr638_regnum, sim_ppc_spr639_regnum,
+    sim_ppc_spr640_regnum, sim_ppc_spr641_regnum,
+    sim_ppc_spr642_regnum, sim_ppc_spr643_regnum,
+    sim_ppc_spr644_regnum, sim_ppc_spr645_regnum,
+    sim_ppc_spr646_regnum, sim_ppc_spr647_regnum,
+    sim_ppc_spr648_regnum, sim_ppc_spr649_regnum,
+    sim_ppc_spr650_regnum, sim_ppc_spr651_regnum,
+    sim_ppc_spr652_regnum, sim_ppc_spr653_regnum,
+    sim_ppc_spr654_regnum, sim_ppc_spr655_regnum,
+    sim_ppc_spr656_regnum, sim_ppc_spr657_regnum,
+    sim_ppc_spr658_regnum, sim_ppc_spr659_regnum,
+    sim_ppc_spr660_regnum, sim_ppc_spr661_regnum,
+    sim_ppc_spr662_regnum, sim_ppc_spr663_regnum,
+    sim_ppc_spr664_regnum, sim_ppc_spr665_regnum,
+    sim_ppc_spr666_regnum, sim_ppc_spr667_regnum,
+    sim_ppc_spr668_regnum, sim_ppc_spr669_regnum,
+    sim_ppc_spr670_regnum, sim_ppc_spr671_regnum,
+    sim_ppc_spr672_regnum, sim_ppc_spr673_regnum,
+    sim_ppc_spr674_regnum, sim_ppc_spr675_regnum,
+    sim_ppc_spr676_regnum, sim_ppc_spr677_regnum,
+    sim_ppc_spr678_regnum, sim_ppc_spr679_regnum,
+    sim_ppc_spr680_regnum, sim_ppc_spr681_regnum,
+    sim_ppc_spr682_regnum, sim_ppc_spr683_regnum,
+    sim_ppc_spr684_regnum, sim_ppc_spr685_regnum,
+    sim_ppc_spr686_regnum, sim_ppc_spr687_regnum,
+    sim_ppc_spr688_regnum, sim_ppc_spr689_regnum,
+    sim_ppc_spr690_regnum, sim_ppc_spr691_regnum,
+    sim_ppc_spr692_regnum, sim_ppc_spr693_regnum,
+    sim_ppc_spr694_regnum, sim_ppc_spr695_regnum,
+    sim_ppc_spr696_regnum, sim_ppc_spr697_regnum,
+    sim_ppc_spr698_regnum, sim_ppc_spr699_regnum,
+    sim_ppc_spr700_regnum, sim_ppc_spr701_regnum,
+    sim_ppc_spr702_regnum, sim_ppc_spr703_regnum,
+    sim_ppc_spr704_regnum, sim_ppc_spr705_regnum,
+    sim_ppc_spr706_regnum, sim_ppc_spr707_regnum,
+    sim_ppc_spr708_regnum, sim_ppc_spr709_regnum,
+    sim_ppc_spr710_regnum, sim_ppc_spr711_regnum,
+    sim_ppc_spr712_regnum, sim_ppc_spr713_regnum,
+    sim_ppc_spr714_regnum, sim_ppc_spr715_regnum,
+    sim_ppc_spr716_regnum, sim_ppc_spr717_regnum,
+    sim_ppc_spr718_regnum, sim_ppc_spr719_regnum,
+    sim_ppc_spr720_regnum, sim_ppc_spr721_regnum,
+    sim_ppc_spr722_regnum, sim_ppc_spr723_regnum,
+    sim_ppc_spr724_regnum, sim_ppc_spr725_regnum,
+    sim_ppc_spr726_regnum, sim_ppc_spr727_regnum,
+    sim_ppc_spr728_regnum, sim_ppc_spr729_regnum,
+    sim_ppc_spr730_regnum, sim_ppc_spr731_regnum,
+    sim_ppc_spr732_regnum, sim_ppc_spr733_regnum,
+    sim_ppc_spr734_regnum, sim_ppc_spr735_regnum,
+    sim_ppc_spr736_regnum, sim_ppc_spr737_regnum,
+    sim_ppc_spr738_regnum, sim_ppc_spr739_regnum,
+    sim_ppc_spr740_regnum, sim_ppc_spr741_regnum,
+    sim_ppc_spr742_regnum, sim_ppc_spr743_regnum,
+    sim_ppc_spr744_regnum, sim_ppc_spr745_regnum,
+    sim_ppc_spr746_regnum, sim_ppc_spr747_regnum,
+    sim_ppc_spr748_regnum, sim_ppc_spr749_regnum,
+    sim_ppc_spr750_regnum, sim_ppc_spr751_regnum,
+    sim_ppc_spr752_regnum, sim_ppc_spr753_regnum,
+    sim_ppc_spr754_regnum, sim_ppc_spr755_regnum,
+    sim_ppc_spr756_regnum, sim_ppc_spr757_regnum,
+    sim_ppc_spr758_regnum, sim_ppc_spr759_regnum,
+    sim_ppc_spr760_regnum, sim_ppc_spr761_regnum,
+    sim_ppc_spr762_regnum, sim_ppc_spr763_regnum,
+    sim_ppc_spr764_regnum, sim_ppc_spr765_regnum,
+    sim_ppc_spr766_regnum, sim_ppc_spr767_regnum,
+    sim_ppc_spr768_regnum, sim_ppc_spr769_regnum,
+    sim_ppc_spr770_regnum, sim_ppc_spr771_regnum,
+    sim_ppc_spr772_regnum, sim_ppc_spr773_regnum,
+    sim_ppc_spr774_regnum, sim_ppc_spr775_regnum,
+    sim_ppc_spr776_regnum, sim_ppc_spr777_regnum,
+    sim_ppc_spr778_regnum, sim_ppc_spr779_regnum,
+    sim_ppc_spr780_regnum, sim_ppc_spr781_regnum,
+    sim_ppc_spr782_regnum, sim_ppc_spr783_regnum,
+    sim_ppc_spr784_regnum, sim_ppc_spr785_regnum,
+    sim_ppc_spr786_regnum, sim_ppc_spr787_regnum,
+    sim_ppc_spr788_regnum, sim_ppc_spr789_regnum,
+    sim_ppc_spr790_regnum, sim_ppc_spr791_regnum,
+    sim_ppc_spr792_regnum, sim_ppc_spr793_regnum,
+    sim_ppc_spr794_regnum, sim_ppc_spr795_regnum,
+    sim_ppc_spr796_regnum, sim_ppc_spr797_regnum,
+    sim_ppc_spr798_regnum, sim_ppc_spr799_regnum,
+    sim_ppc_spr800_regnum, sim_ppc_spr801_regnum,
+    sim_ppc_spr802_regnum, sim_ppc_spr803_regnum,
+    sim_ppc_spr804_regnum, sim_ppc_spr805_regnum,
+    sim_ppc_spr806_regnum, sim_ppc_spr807_regnum,
+    sim_ppc_spr808_regnum, sim_ppc_spr809_regnum,
+    sim_ppc_spr810_regnum, sim_ppc_spr811_regnum,
+    sim_ppc_spr812_regnum, sim_ppc_spr813_regnum,
+    sim_ppc_spr814_regnum, sim_ppc_spr815_regnum,
+    sim_ppc_spr816_regnum, sim_ppc_spr817_regnum,
+    sim_ppc_spr818_regnum, sim_ppc_spr819_regnum,
+    sim_ppc_spr820_regnum, sim_ppc_spr821_regnum,
+    sim_ppc_spr822_regnum, sim_ppc_spr823_regnum,
+    sim_ppc_spr824_regnum, sim_ppc_spr825_regnum,
+    sim_ppc_spr826_regnum, sim_ppc_spr827_regnum,
+    sim_ppc_spr828_regnum, sim_ppc_spr829_regnum,
+    sim_ppc_spr830_regnum, sim_ppc_spr831_regnum,
+    sim_ppc_spr832_regnum, sim_ppc_spr833_regnum,
+    sim_ppc_spr834_regnum, sim_ppc_spr835_regnum,
+    sim_ppc_spr836_regnum, sim_ppc_spr837_regnum,
+    sim_ppc_spr838_regnum, sim_ppc_spr839_regnum,
+    sim_ppc_spr840_regnum, sim_ppc_spr841_regnum,
+    sim_ppc_spr842_regnum, sim_ppc_spr843_regnum,
+    sim_ppc_spr844_regnum, sim_ppc_spr845_regnum,
+    sim_ppc_spr846_regnum, sim_ppc_spr847_regnum,
+    sim_ppc_spr848_regnum, sim_ppc_spr849_regnum,
+    sim_ppc_spr850_regnum, sim_ppc_spr851_regnum,
+    sim_ppc_spr852_regnum, sim_ppc_spr853_regnum,
+    sim_ppc_spr854_regnum, sim_ppc_spr855_regnum,
+    sim_ppc_spr856_regnum, sim_ppc_spr857_regnum,
+    sim_ppc_spr858_regnum, sim_ppc_spr859_regnum,
+    sim_ppc_spr860_regnum, sim_ppc_spr861_regnum,
+    sim_ppc_spr862_regnum, sim_ppc_spr863_regnum,
+    sim_ppc_spr864_regnum, sim_ppc_spr865_regnum,
+    sim_ppc_spr866_regnum, sim_ppc_spr867_regnum,
+    sim_ppc_spr868_regnum, sim_ppc_spr869_regnum,
+    sim_ppc_spr870_regnum, sim_ppc_spr871_regnum,
+    sim_ppc_spr872_regnum, sim_ppc_spr873_regnum,
+    sim_ppc_spr874_regnum, sim_ppc_spr875_regnum,
+    sim_ppc_spr876_regnum, sim_ppc_spr877_regnum,
+    sim_ppc_spr878_regnum, sim_ppc_spr879_regnum,
+    sim_ppc_spr880_regnum, sim_ppc_spr881_regnum,
+    sim_ppc_spr882_regnum, sim_ppc_spr883_regnum,
+    sim_ppc_spr884_regnum, sim_ppc_spr885_regnum,
+    sim_ppc_spr886_regnum, sim_ppc_spr887_regnum,
+    sim_ppc_spr888_regnum, sim_ppc_spr889_regnum,
+    sim_ppc_spr890_regnum, sim_ppc_spr891_regnum,
+    sim_ppc_spr892_regnum, sim_ppc_spr893_regnum,
+    sim_ppc_spr894_regnum, sim_ppc_spr895_regnum,
+    sim_ppc_spr896_regnum, sim_ppc_spr897_regnum,
+    sim_ppc_spr898_regnum, sim_ppc_spr899_regnum,
+    sim_ppc_spr900_regnum, sim_ppc_spr901_regnum,
+    sim_ppc_spr902_regnum, sim_ppc_spr903_regnum,
+    sim_ppc_spr904_regnum, sim_ppc_spr905_regnum,
+    sim_ppc_spr906_regnum, sim_ppc_spr907_regnum,
+    sim_ppc_spr908_regnum, sim_ppc_spr909_regnum,
+    sim_ppc_spr910_regnum, sim_ppc_spr911_regnum,
+    sim_ppc_spr912_regnum, sim_ppc_spr913_regnum,
+    sim_ppc_spr914_regnum, sim_ppc_spr915_regnum,
+    sim_ppc_spr916_regnum, sim_ppc_spr917_regnum,
+    sim_ppc_spr918_regnum, sim_ppc_spr919_regnum,
+    sim_ppc_spr920_regnum, sim_ppc_spr921_regnum,
+    sim_ppc_spr922_regnum, sim_ppc_spr923_regnum,
+    sim_ppc_spr924_regnum, sim_ppc_spr925_regnum,
+    sim_ppc_spr926_regnum, sim_ppc_spr927_regnum,
+    sim_ppc_spr928_regnum, sim_ppc_spr929_regnum,
+    sim_ppc_spr930_regnum, sim_ppc_spr931_regnum,
+    sim_ppc_spr932_regnum, sim_ppc_spr933_regnum,
+    sim_ppc_spr934_regnum, sim_ppc_spr935_regnum,
+    sim_ppc_spr936_regnum, sim_ppc_spr937_regnum,
+    sim_ppc_spr938_regnum, sim_ppc_spr939_regnum,
+    sim_ppc_spr940_regnum, sim_ppc_spr941_regnum,
+    sim_ppc_spr942_regnum, sim_ppc_spr943_regnum,
+    sim_ppc_spr944_regnum, sim_ppc_spr945_regnum,
+    sim_ppc_spr946_regnum, sim_ppc_spr947_regnum,
+    sim_ppc_spr948_regnum, sim_ppc_spr949_regnum,
+    sim_ppc_spr950_regnum, sim_ppc_spr951_regnum,
+    sim_ppc_spr952_regnum, sim_ppc_spr953_regnum,
+    sim_ppc_spr954_regnum, sim_ppc_spr955_regnum,
+    sim_ppc_spr956_regnum, sim_ppc_spr957_regnum,
+    sim_ppc_spr958_regnum, sim_ppc_spr959_regnum,
+    sim_ppc_spr960_regnum, sim_ppc_spr961_regnum,
+    sim_ppc_spr962_regnum, sim_ppc_spr963_regnum,
+    sim_ppc_spr964_regnum, sim_ppc_spr965_regnum,
+    sim_ppc_spr966_regnum, sim_ppc_spr967_regnum,
+    sim_ppc_spr968_regnum, sim_ppc_spr969_regnum,
+    sim_ppc_spr970_regnum, sim_ppc_spr971_regnum,
+    sim_ppc_spr972_regnum, sim_ppc_spr973_regnum,
+    sim_ppc_spr974_regnum, sim_ppc_spr975_regnum,
+    sim_ppc_spr976_regnum, sim_ppc_spr977_regnum,
+    sim_ppc_spr978_regnum, sim_ppc_spr979_regnum,
+    sim_ppc_spr980_regnum, sim_ppc_spr981_regnum,
+    sim_ppc_spr982_regnum, sim_ppc_spr983_regnum,
+    sim_ppc_spr984_regnum, sim_ppc_spr985_regnum,
+    sim_ppc_spr986_regnum, sim_ppc_spr987_regnum,
+    sim_ppc_spr988_regnum, sim_ppc_spr989_regnum,
+    sim_ppc_spr990_regnum, sim_ppc_spr991_regnum,
+    sim_ppc_spr992_regnum, sim_ppc_spr993_regnum,
+    sim_ppc_spr994_regnum, sim_ppc_spr995_regnum,
+    sim_ppc_spr996_regnum, sim_ppc_spr997_regnum,
+    sim_ppc_spr998_regnum, sim_ppc_spr999_regnum,
+    sim_ppc_spr1000_regnum, sim_ppc_spr1001_regnum,
+    sim_ppc_spr1002_regnum, sim_ppc_spr1003_regnum,
+    sim_ppc_spr1004_regnum, sim_ppc_spr1005_regnum,
+    sim_ppc_spr1006_regnum, sim_ppc_spr1007_regnum,
+    sim_ppc_spr1008_regnum, sim_ppc_spr1009_regnum,
+    sim_ppc_spr1010_regnum, sim_ppc_spr1011_regnum,
+    sim_ppc_spr1012_regnum, sim_ppc_spr1013_regnum,
+    sim_ppc_spr1014_regnum, sim_ppc_spr1015_regnum,
+    sim_ppc_spr1016_regnum, sim_ppc_spr1017_regnum,
+    sim_ppc_spr1018_regnum, sim_ppc_spr1019_regnum,
+    sim_ppc_spr1020_regnum, sim_ppc_spr1021_regnum,
+    sim_ppc_spr1022_regnum, sim_ppc_spr1023_regnum
+  };
+
+
+/* Sizes of various register sets.  */
+enum
+  {
+    sim_ppc_num_gprs = 32,
+    sim_ppc_num_fprs = 32,
+    sim_ppc_num_vrs = 32,
+    sim_ppc_num_srs = 16,
+    sim_ppc_num_sprs = 1024,
+  };
+
+
+/* Return the register name for the supplied SPR number if any, or
+   NULL if none.  */
+extern const char *sim_spr_register_name (int);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SIM_PPC_H */
diff --git a/binutils-2.25/include/gdb/sim-rl78.h b/binutils-2.25/include/gdb/sim-rl78.h
new file mode 100644
index 00000000..c52a2a7f
--- /dev/null
+++ b/binutils-2.25/include/gdb/sim-rl78.h
@@ -0,0 +1,76 @@
+/* sim-rx.h --- interface between rl78 simulator and GDB.
+
+   Copyright 2011-2013 Free Software Foundation, Inc.
+
+   Contributed by Red Hat.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#if !defined (SIM_RL78_H)
+#define SIM_RL78_H
+
+enum sim_rl78_regnum
+{
+  sim_rl78_bank0_r0_regnum,
+  sim_rl78_bank0_r1_regnum,
+  sim_rl78_bank0_r2_regnum,
+  sim_rl78_bank0_r3_regnum,
+  sim_rl78_bank0_r4_regnum,
+  sim_rl78_bank0_r5_regnum,
+  sim_rl78_bank0_r6_regnum,
+  sim_rl78_bank0_r7_regnum,
+
+  sim_rl78_bank1_r0_regnum,
+  sim_rl78_bank1_r1_regnum,
+  sim_rl78_bank1_r2_regnum,
+  sim_rl78_bank1_r3_regnum,
+  sim_rl78_bank1_r4_regnum,
+  sim_rl78_bank1_r5_regnum,
+  sim_rl78_bank1_r6_regnum,
+  sim_rl78_bank1_r7_regnum,
+
+  sim_rl78_bank2_r0_regnum,
+  sim_rl78_bank2_r1_regnum,
+  sim_rl78_bank2_r2_regnum,
+  sim_rl78_bank2_r3_regnum,
+  sim_rl78_bank2_r4_regnum,
+  sim_rl78_bank2_r5_regnum,
+  sim_rl78_bank2_r6_regnum,
+  sim_rl78_bank2_r7_regnum,
+
+  sim_rl78_bank3_r0_regnum,
+  sim_rl78_bank3_r1_regnum,
+  sim_rl78_bank3_r2_regnum,
+  sim_rl78_bank3_r3_regnum,
+  sim_rl78_bank3_r4_regnum,
+  sim_rl78_bank3_r5_regnum,
+  sim_rl78_bank3_r6_regnum,
+  sim_rl78_bank3_r7_regnum,
+
+  sim_rl78_psw_regnum,
+  sim_rl78_es_regnum,
+  sim_rl78_cs_regnum,
+  sim_rl78_pc_regnum,
+
+  sim_rl78_spl_regnum,
+  sim_rl78_sph_regnum,
+  sim_rl78_pmc_regnum,
+  sim_rl78_mem_regnum,
+
+  sim_rl78_num_regs
+};
+
+#endif /* SIM_RL78_H */
diff --git a/binutils-2.25/include/gdb/sim-rx.h b/binutils-2.25/include/gdb/sim-rx.h
new file mode 100644
index 00000000..c4d855f7
--- /dev/null
+++ b/binutils-2.25/include/gdb/sim-rx.h
@@ -0,0 +1,56 @@
+/* sim-rx.h --- interface between RX simulator and GDB.
+
+   Copyright 2008-2013 Free Software Foundation, Inc.
+
+   Contributed by Red Hat.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#if !defined (SIM_RX_H)
+#define SIM_RX_H
+
+enum sim_rx_regnum
+  {
+    sim_rx_r0_regnum,
+    sim_rx_r1_regnum,
+    sim_rx_r2_regnum,
+    sim_rx_r3_regnum,
+    sim_rx_r4_regnum,
+    sim_rx_r5_regnum,
+    sim_rx_r6_regnum,
+    sim_rx_r7_regnum,
+    sim_rx_r8_regnum,
+    sim_rx_r9_regnum,
+    sim_rx_r10_regnum,
+    sim_rx_r11_regnum,
+    sim_rx_r12_regnum,
+    sim_rx_r13_regnum,
+    sim_rx_r14_regnum,
+    sim_rx_r15_regnum,
+    sim_rx_usp_regnum,
+    sim_rx_isp_regnum,
+    sim_rx_ps_regnum,
+    sim_rx_pc_regnum,
+    sim_rx_intb_regnum,
+    sim_rx_bpsw_regnum,
+    sim_rx_bpc_regnum,
+    sim_rx_fintv_regnum,
+    sim_rx_fpsw_regnum,
+    sim_rx_acc_regnum,
+    sim_rx_num_regs
+  };
+
+#endif /* SIM_RX_H */
diff --git a/binutils-2.25/include/gdb/sim-sh.h b/binutils-2.25/include/gdb/sim-sh.h
new file mode 100644
index 00000000..4e37992e
--- /dev/null
+++ b/binutils-2.25/include/gdb/sim-sh.h
@@ -0,0 +1,169 @@
+/* This file defines the interface between the sh simulator and gdb.
+   Copyright (C) 2000-2013 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#if !defined (SIM_SH_H)
+#define SIM_SH_H
+
+#ifdef __cplusplus
+extern "C" { // }
+#endif
+
+/* The simulator makes use of the following register information. */
+
+enum
+{
+  SIM_SH_R0_REGNUM = 0,
+  SIM_SH_R1_REGNUM,
+  SIM_SH_R2_REGNUM,
+  SIM_SH_R3_REGNUM,
+  SIM_SH_R4_REGNUM,
+  SIM_SH_R5_REGNUM,
+  SIM_SH_R6_REGNUM,
+  SIM_SH_R7_REGNUM,
+  SIM_SH_R8_REGNUM,
+  SIM_SH_R9_REGNUM,
+  SIM_SH_R10_REGNUM,
+  SIM_SH_R11_REGNUM,
+  SIM_SH_R12_REGNUM,
+  SIM_SH_R13_REGNUM,
+  SIM_SH_R14_REGNUM,
+  SIM_SH_R15_REGNUM,
+  SIM_SH_PC_REGNUM,
+  SIM_SH_PR_REGNUM,
+  SIM_SH_GBR_REGNUM,
+  SIM_SH_VBR_REGNUM,
+  SIM_SH_MACH_REGNUM,
+  SIM_SH_MACL_REGNUM,
+  SIM_SH_SR_REGNUM,
+  SIM_SH_FPUL_REGNUM,
+  SIM_SH_FPSCR_REGNUM,
+  SIM_SH_FR0_REGNUM, /* FRn registers: sh3e / sh4 */
+  SIM_SH_FR1_REGNUM,
+  SIM_SH_FR2_REGNUM,
+  SIM_SH_FR3_REGNUM,
+  SIM_SH_FR4_REGNUM,
+  SIM_SH_FR5_REGNUM,
+  SIM_SH_FR6_REGNUM,
+  SIM_SH_FR7_REGNUM,
+  SIM_SH_FR8_REGNUM,
+  SIM_SH_FR9_REGNUM,
+  SIM_SH_FR10_REGNUM,
+  SIM_SH_FR11_REGNUM,
+  SIM_SH_FR12_REGNUM,
+  SIM_SH_FR13_REGNUM,
+  SIM_SH_FR14_REGNUM,
+  SIM_SH_FR15_REGNUM,
+  SIM_SH_SSR_REGNUM, /* sh3{,e,-dsp}, sh4 */
+  SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */
+  SIM_SH_R0_BANK0_REGNUM, /* SIM_SH_Rn_BANKm_REGNUM: sh3[e] / sh4 */
+  SIM_SH_R1_BANK0_REGNUM,
+  SIM_SH_R2_BANK0_REGNUM,
+  SIM_SH_R3_BANK0_REGNUM,
+  SIM_SH_R4_BANK0_REGNUM,
+  SIM_SH_R5_BANK0_REGNUM,
+  SIM_SH_R6_BANK0_REGNUM,
+  SIM_SH_R7_BANK0_REGNUM,
+  SIM_SH_R0_BANK1_REGNUM,
+  SIM_SH_R1_BANK1_REGNUM,
+  SIM_SH_R2_BANK1_REGNUM,
+  SIM_SH_R3_BANK1_REGNUM,
+  SIM_SH_R4_BANK1_REGNUM,
+  SIM_SH_R5_BANK1_REGNUM,
+  SIM_SH_R6_BANK1_REGNUM,
+  SIM_SH_R7_BANK1_REGNUM,
+  SIM_SH_XF0_REGNUM,
+  SIM_SH_XF1_REGNUM,
+  SIM_SH_XF2_REGNUM,
+  SIM_SH_XF3_REGNUM,
+  SIM_SH_XF4_REGNUM,
+  SIM_SH_XF5_REGNUM,
+  SIM_SH_XF6_REGNUM,
+  SIM_SH_XF7_REGNUM,
+  SIM_SH_XF8_REGNUM,
+  SIM_SH_XF9_REGNUM,
+  SIM_SH_XF10_REGNUM,
+  SIM_SH_XF11_REGNUM,
+  SIM_SH_XF12_REGNUM,
+  SIM_SH_XF13_REGNUM,
+  SIM_SH_XF14_REGNUM,
+  SIM_SH_XF15_REGNUM,
+  SIM_SH_SGR_REGNUM,
+  SIM_SH_DBR_REGNUM,
+  SIM_SH4_NUM_REGS, /* 77 */
+
+  /* sh[3]-dsp */
+  SIM_SH_DSR_REGNUM,
+  SIM_SH_A0G_REGNUM,
+  SIM_SH_A0_REGNUM,
+  SIM_SH_A1G_REGNUM,
+  SIM_SH_A1_REGNUM,
+  SIM_SH_M0_REGNUM,
+  SIM_SH_M1_REGNUM,
+  SIM_SH_X0_REGNUM,
+  SIM_SH_X1_REGNUM,
+  SIM_SH_Y0_REGNUM,
+  SIM_SH_Y1_REGNUM,
+  SIM_SH_MOD_REGNUM,
+  SIM_SH_RS_REGNUM,
+  SIM_SH_RE_REGNUM,
+  SIM_SH_R0_BANK_REGNUM,
+  SIM_SH_R1_BANK_REGNUM,
+  SIM_SH_R2_BANK_REGNUM,
+  SIM_SH_R3_BANK_REGNUM,
+  SIM_SH_R4_BANK_REGNUM,
+  SIM_SH_R5_BANK_REGNUM,
+  SIM_SH_R6_BANK_REGNUM,
+  SIM_SH_R7_BANK_REGNUM,
+  /* 109..127: room for expansion.  */
+  SIM_SH_TBR_REGNUM,
+  SIM_SH_IBNR_REGNUM,
+  SIM_SH_IBCR_REGNUM,
+  SIM_SH_BANK_REGNUM,
+  SIM_SH_BANK_MACL_REGNUM,
+  SIM_SH_BANK_GBR_REGNUM,
+  SIM_SH_BANK_PR_REGNUM,
+  SIM_SH_BANK_IVN_REGNUM,
+  SIM_SH_BANK_MACH_REGNUM
+};
+
+enum
+{
+  SIM_SH64_R0_REGNUM = 0,
+  SIM_SH64_SP_REGNUM = 15,
+  SIM_SH64_PC_REGNUM = 64,
+  SIM_SH64_SR_REGNUM = 65,
+  SIM_SH64_SSR_REGNUM = 66,
+  SIM_SH64_SPC_REGNUM = 67,
+  SIM_SH64_TR0_REGNUM = 68,
+  SIM_SH64_FPCSR_REGNUM = 76,
+  SIM_SH64_FR0_REGNUM = 77
+};
+
+enum
+{
+  SIM_SH64_NR_REGS = 141,  /* total number of architectural registers */
+  SIM_SH64_NR_R_REGS = 64, /* number of general registers */
+  SIM_SH64_NR_TR_REGS = 8, /* number of target registers */
+  SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/binutils-2.25/include/gdbm.h b/binutils-2.25/include/gdbm.h
new file mode 100644
index 00000000..d2a60063
--- /dev/null
+++ b/binutils-2.25/include/gdbm.h
@@ -0,0 +1,91 @@
+/* GNU DBM - DataBase Manager include file
+   Copyright 1989, 1991  Free Software Foundation, Inc.
+   Written by Philip A. Nelson.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+/* You may contact the author by:
+       e-mail:  phil@wwu.edu
+      us-mail:  Philip A. Nelson
+                Computer Science Department
+                Western Washington University
+                Bellingham, WA 98226
+        phone:  (206) 676-3035
+       
+*************************************************************************/
+
+/* Parameters to gdbm_open for READERS, WRITERS, and WRITERS who
+   can create the database. */
+#define  GDBM_READER  0
+#define  GDBM_WRITER  1
+#define  GDBM_WRCREAT 2
+#define  GDBM_NEWDB   3
+
+/* Parameters to gdbm_store for simple insertion or replacement. */
+#define  GDBM_INSERT  0
+#define  GDBM_REPLACE 1
+
+
+/* The data and key structure.  This structure is defined for compatibility. */
+typedef struct {
+	char *dptr;
+	int   dsize;
+      } datum;
+
+
+/* The file information header. This is good enough for most applications. */
+typedef struct {int dummy[10];} *GDBM_FILE;
+
+
+/* These are the routines! */
+
+extern GDBM_FILE gdbm_open ();
+
+extern void	 gdbm_close ();
+
+extern datum	 gdbm_fetch ();
+
+extern int	 gdbm_store ();
+
+extern int	 gdbm_delete ();
+
+extern datum	 gdbm_firstkey ();
+
+extern datum	 gdbm_nextkey ();
+
+extern int	 gdbm_reorganize ();
+
+
+/* gdbm sends back the following error codes in the variable gdbm_errno. */
+typedef enum {	NO_ERROR,
+		MALLOC_ERROR,
+		BLOCK_SIZE_ERROR,
+		FILE_OPEN_ERROR,
+		FILE_WRITE_ERROR,
+		FILE_SEEK_ERROR,
+		FILE_READ_ERROR,
+		BAD_MAGIC_NUMBER,
+		EMPTY_DATABASE,
+		CANT_BE_READER,
+	        CANT_BE_WRITER,
+		READER_CANT_RECOVER,
+		READER_CANT_DELETE,
+		READER_CANT_STORE,
+		READER_CANT_REORGANIZE,
+		UNKNOWN_UPDATE,
+		ITEM_NOT_FOUND,
+		REORGANIZE_FAILED,
+		CANNOT_REPLACE}
+	gdbm_error;
diff --git a/binutils-2.25/include/getopt.h b/binutils-2.25/include/getopt.h
new file mode 100644
index 00000000..5421cabe
--- /dev/null
+++ b/binutils-2.25/include/getopt.h
@@ -0,0 +1,144 @@
+/* Declarations for getopt.
+   Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000,
+   2002 Free Software Foundation, Inc.
+
+   NOTE: The canonical source of this file is maintained with the GNU C Library.
+   Bugs can be reported to bug-glibc@gnu.org.
+
+   This program is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 2, or (at your option) any
+   later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
+   USA.  */
+
+#ifndef _GETOPT_H
+#define _GETOPT_H 1
+
+#ifdef	__cplusplus
+extern "C" {
+#endif
+
+/* For communication from `getopt' to the caller.
+   When `getopt' finds an option that takes an argument,
+   the argument value is returned here.
+   Also, when `ordering' is RETURN_IN_ORDER,
+   each non-option ARGV-element is returned here.  */
+
+extern char *optarg;
+
+/* Index in ARGV of the next element to be scanned.
+   This is used for communication to and from the caller
+   and for communication between successive calls to `getopt'.
+
+   On entry to `getopt', zero means this is the first call; initialize.
+
+   When `getopt' returns -1, this is the index of the first of the
+   non-option elements that the caller should itself scan.
+
+   Otherwise, `optind' communicates from one call to the next
+   how much of ARGV has been scanned so far.  */
+
+extern int optind;
+
+/* Callers store zero here to inhibit the error message `getopt' prints
+   for unrecognized options.  */
+
+extern int opterr;
+
+/* Set to an option character which was unrecognized.  */
+
+extern int optopt;
+
+/* Describe the long-named options requested by the application.
+   The LONG_OPTIONS argument to getopt_long or getopt_long_only is a vector
+   of `struct option' terminated by an element containing a name which is
+   zero.
+
+   The field `has_arg' is:
+   no_argument		(or 0) if the option does not take an argument,
+   required_argument	(or 1) if the option requires an argument,
+   optional_argument 	(or 2) if the option takes an optional argument.
+
+   If the field `flag' is not NULL, it points to a variable that is set
+   to the value given in the field `val' when the option is found, but
+   left unchanged if the option is not found.
+
+   To have a long-named option do something other than set an `int' to
+   a compiled-in constant, such as set a value from `optarg', set the
+   option's `flag' field to zero and its `val' field to a nonzero
+   value (the equivalent single-letter option character, if there is
+   one).  For long options that have a zero `flag' field, `getopt'
+   returns the contents of the `val' field.  */
+
+struct option
+{
+#if defined (__STDC__) && __STDC__
+  const char *name;
+#else
+  char *name;
+#endif
+  /* has_arg can't be an enum because some compilers complain about
+     type mismatches in all the code that assumes it is an int.  */
+  int has_arg;
+  int *flag;
+  int val;
+};
+
+/* Names for the values of the `has_arg' field of `struct option'.  */
+
+#define	no_argument		0
+#define required_argument	1
+#define optional_argument	2
+
+#if defined (__STDC__) && __STDC__
+/* HAVE_DECL_* is a three-state macro: undefined, 0 or 1.  If it is
+   undefined, we haven't run the autoconf check so provide the
+   declaration without arguments.  If it is 0, we checked and failed
+   to find the declaration so provide a fully prototyped one.  If it
+   is 1, we found it so don't provide any declaration at all.  */
+#if !HAVE_DECL_GETOPT
+#if defined (__GNU_LIBRARY__) || defined (HAVE_DECL_GETOPT)
+/* Many other libraries have conflicting prototypes for getopt, with
+   differences in the consts, in unistd.h.  To avoid compilation
+   errors, only prototype getopt for the GNU C library.  */
+extern int getopt (int argc, char *const *argv, const char *shortopts);
+#else
+#ifndef __cplusplus
+extern int getopt ();
+#endif /* __cplusplus */
+#endif
+#endif /* !HAVE_DECL_GETOPT */
+
+extern int getopt_long (int argc, char *const *argv, const char *shortopts,
+		        const struct option *longopts, int *longind);
+extern int getopt_long_only (int argc, char *const *argv,
+			     const char *shortopts,
+		             const struct option *longopts, int *longind);
+
+/* Internal only.  Users should not call this directly.  */
+extern int _getopt_internal (int argc, char *const *argv,
+			     const char *shortopts,
+		             const struct option *longopts, int *longind,
+			     int long_only);
+#else /* not __STDC__ */
+extern int getopt ();
+extern int getopt_long ();
+extern int getopt_long_only ();
+
+extern int _getopt_internal ();
+#endif /* __STDC__ */
+
+#ifdef	__cplusplus
+}
+#endif
+
+#endif /* getopt.h */
diff --git a/binutils-2.25/include/hashtab.h b/binutils-2.25/include/hashtab.h
new file mode 100644
index 00000000..4bb65d6c
--- /dev/null
+++ b/binutils-2.25/include/hashtab.h
@@ -0,0 +1,209 @@
+/* An expandable hash tables datatype.  
+   Copyright (C) 1999, 2000, 2002, 2003, 2004, 2005, 2009, 2010
+   Free Software Foundation, Inc.
+   Contributed by Vladimir Makarov (vmakarov@cygnus.com).
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+/* This package implements basic hash table functionality.  It is possible
+   to search for an entry, create an entry and destroy an entry.
+
+   Elements in the table are generic pointers.
+
+   The size of the table is not fixed; if the occupancy of the table
+   grows too high the hash table will be expanded.
+
+   The abstract data implementation is based on generalized Algorithm D
+   from Knuth's book "The art of computer programming".  Hash table is
+   expanded by creation of new hash table and transferring elements from
+   the old table to the new table.  */
+
+#ifndef __HASHTAB_H__
+#define __HASHTAB_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "ansidecl.h"
+
+#ifndef GTY
+#define GTY(X)
+#endif
+
+/* The type for a hash code.  */
+typedef unsigned int hashval_t;
+
+/* Callback function pointer types.  */
+
+/* Calculate hash of a table entry.  */
+typedef hashval_t (*htab_hash) (const void *);
+
+/* Compare a table entry with a possible entry.  The entry already in
+   the table always comes first, so the second element can be of a
+   different type (but in this case htab_find and htab_find_slot
+   cannot be used; instead the variants that accept a hash value
+   must be used).  */
+typedef int (*htab_eq) (const void *, const void *);
+
+/* Cleanup function called whenever a live element is removed from
+   the hash table.  */
+typedef void (*htab_del) (void *);
+  
+/* Function called by htab_traverse for each live element.  The first
+   arg is the slot of the element (which can be passed to htab_clear_slot
+   if desired), the second arg is the auxiliary pointer handed to
+   htab_traverse.  Return 1 to continue scan, 0 to stop.  */
+typedef int (*htab_trav) (void **, void *);
+
+/* Memory-allocation function, with the same functionality as calloc().
+   Iff it returns NULL, the hash table implementation will pass an error
+   code back to the user, so if your code doesn't handle errors,
+   best if you use xcalloc instead.  */
+typedef void *(*htab_alloc) (size_t, size_t);
+
+/* We also need a free() routine.  */
+typedef void (*htab_free) (void *);
+
+/* Memory allocation and deallocation; variants which take an extra
+   argument.  */
+typedef void *(*htab_alloc_with_arg) (void *, size_t, size_t);
+typedef void (*htab_free_with_arg) (void *, void *);
+
+/* This macro defines reserved value for empty table entry.  */
+
+#define HTAB_EMPTY_ENTRY    ((PTR) 0)
+
+/* This macro defines reserved value for table entry which contained
+   a deleted element. */
+
+#define HTAB_DELETED_ENTRY  ((PTR) 1)
+
+/* Hash tables are of the following type.  The structure
+   (implementation) of this type is not needed for using the hash
+   tables.  All work with hash table should be executed only through
+   functions mentioned below.  The size of this structure is subject to
+   change.  */
+
+struct GTY(()) htab {
+  /* Pointer to hash function.  */
+  htab_hash hash_f;
+
+  /* Pointer to comparison function.  */
+  htab_eq eq_f;
+
+  /* Pointer to cleanup function.  */
+  htab_del del_f;
+
+  /* Table itself.  */
+  void ** GTY ((use_param, length ("%h.size"))) entries;
+
+  /* Current size (in entries) of the hash table.  */
+  size_t size;
+
+  /* Current number of elements including also deleted elements.  */
+  size_t n_elements;
+
+  /* Current number of deleted elements in the table.  */
+  size_t n_deleted;
+
+  /* The following member is used for debugging. Its value is number
+     of all calls of `htab_find_slot' for the hash table. */
+  unsigned int searches;
+
+  /* The following member is used for debugging.  Its value is number
+     of collisions fixed for time of work with the hash table. */
+  unsigned int collisions;
+
+  /* Pointers to allocate/free functions.  */
+  htab_alloc alloc_f;
+  htab_free free_f;
+
+  /* Alternate allocate/free functions, which take an extra argument.  */
+  void * GTY((skip)) alloc_arg;
+  htab_alloc_with_arg alloc_with_arg_f;
+  htab_free_with_arg free_with_arg_f;
+
+  /* Current size (in entries) of the hash table, as an index into the
+     table of primes.  */
+  unsigned int size_prime_index;
+};
+
+typedef struct htab *htab_t;
+
+/* An enum saying whether we insert into the hash table or not.  */
+enum insert_option {NO_INSERT, INSERT};
+
+/* The prototypes of the package functions. */
+
+extern htab_t	htab_create_alloc  (size_t, htab_hash,
+                                    htab_eq, htab_del,
+                                    htab_alloc, htab_free);
+
+extern htab_t	htab_create_alloc_ex (size_t, htab_hash,
+                                      htab_eq, htab_del,
+                                      void *, htab_alloc_with_arg,
+                                      htab_free_with_arg);
+
+extern htab_t  htab_create_typed_alloc (size_t, htab_hash, htab_eq, htab_del,
+					htab_alloc, htab_alloc, htab_free);
+
+/* Backward-compatibility functions.  */
+extern htab_t htab_create (size_t, htab_hash, htab_eq, htab_del);
+extern htab_t htab_try_create (size_t, htab_hash, htab_eq, htab_del);
+
+extern void	htab_set_functions_ex (htab_t, htab_hash,
+                                       htab_eq, htab_del,
+                                       void *, htab_alloc_with_arg,
+                                       htab_free_with_arg);
+
+extern void	htab_delete (htab_t);
+extern void	htab_empty (htab_t);
+
+extern void *	htab_find (htab_t, const void *);
+extern void **	htab_find_slot (htab_t, const void *, enum insert_option);
+extern void *	htab_find_with_hash (htab_t, const void *, hashval_t);
+extern void **	htab_find_slot_with_hash (htab_t, const void *,
+					  hashval_t, enum insert_option);
+extern void	htab_clear_slot	(htab_t, void **);
+extern void	htab_remove_elt	(htab_t, void *);
+extern void	htab_remove_elt_with_hash (htab_t, void *, hashval_t);
+
+extern void	htab_traverse (htab_t, htab_trav, void *);
+extern void	htab_traverse_noresize (htab_t, htab_trav, void *);
+
+extern size_t	htab_size (htab_t);
+extern size_t	htab_elements (htab_t);
+extern double	htab_collisions	(htab_t);
+
+/* A hash function for pointers.  */
+extern htab_hash htab_hash_pointer;
+
+/* An equality function for pointers.  */
+extern htab_eq htab_eq_pointer;
+
+/* A hash function for null-terminated strings.  */
+extern hashval_t htab_hash_string (const void *);
+
+/* An iterative hash function for arbitrary data.  */
+extern hashval_t iterative_hash (const void *, size_t, hashval_t);
+/* Shorthand for hashing something with an intrinsic size.  */
+#define iterative_hash_object(OB,INIT) iterative_hash (&OB, sizeof (OB), INIT)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __HASHTAB_H */
diff --git a/binutils-2.25/include/hp-symtab.h b/binutils-2.25/include/hp-symtab.h
new file mode 100644
index 00000000..e944e909
--- /dev/null
+++ b/binutils-2.25/include/hp-symtab.h
@@ -0,0 +1,1867 @@
+/* Definitions and structures for reading debug symbols from the
+   native HP C compiler.
+
+   Written by the Center for Software Science at the University of Utah
+   and by Cygnus Support.
+
+   Copyright 1994, 1995, 1998, 1999, 2003 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef HP_SYMTAB_INCLUDED
+#define HP_SYMTAB_INCLUDED
+
+/* General information:
+
+   This header file defines and describes only the data structures
+   necessary to read debug symbols produced by the HP C compiler,
+   HP ANSI C++ compiler, and HP FORTRAN 90 compiler using the
+   SOM object file format.  
+   (For a full description of the debug format, ftp hpux-symtab.h from
+   jaguar.cs.utah.edu:/dist).
+   
+   Additional notes (Rich Title)
+   This file is a reverse-engineered version of a file called
+   "symtab.h" which exists internal to HP's Computer Languages Organization
+   in /CLO/Components/DDE/obj/som/symtab.h. Because HP's version of
+   the file is copyrighted and not distributed, it is necessary for
+   GDB to use the reverse-engineered version that follows.
+   Work was done by Cygnus to reverse-engineer the C subset of symtab.h.
+   The WDB project has extended this to also contain the C++ 
+   symbol definitions, the F90 symbol definitions, 
+   and the DOC (debugging-optimized-code) symbol definitions.
+   In some cases (the C++ symbol definitions)
+   I have added internal documentation here that
+   goes beyond what is supplied in HP's symtab.h. If we someday
+   unify these files again, the extra comments should be merged back
+   into HP's symtab.h.
+  
+   -------------------------------------------------------------------
+
+   Debug symbols are contained entirely within an unloadable space called
+   $DEBUG$.  $DEBUG$ contains several subspaces which group related
+   debug symbols.
+
+   $GNTT$ contains information for global variables, types and contants.
+
+   $LNTT$ contains information for procedures (including nesting), scoping
+   information, local variables, types, and constants.
+
+   $SLT$ contains source line information so that code addresses may be
+   mapped to source lines.
+
+   $VT$ contains various strings and constants for named objects (variables,
+   typedefs, functions, etc).  Strings are stored as null-terminated character
+   lists.  Constants always begin on word boundaries.  The first byte of
+   the VT must be zero (a null string).
+
+   $XT$ is not currently used by GDB.
+
+   Many structures within the subspaces point to other structures within
+   the same subspace, or to structures within a different subspace.  These
+   pointers are represented as a structure index from the beginning of
+   the appropriate subspace.  */
+
+/* Used to describe where a constant is stored.  */
+enum location_type
+{
+  LOCATION_IMMEDIATE,
+  LOCATION_PTR,
+  LOCATION_VT,
+};
+
+/* Languages supported by this debug format.  Within the data structures
+   this type is limited to 4 bits for a maximum of 16 languages.  */
+enum hp_language
+{
+  HP_LANGUAGE_UNKNOWN,
+  HP_LANGUAGE_C,
+  HP_LANGUAGE_FORTRAN,
+  HP_LANGUAGE_F77 = HP_LANGUAGE_FORTRAN,
+  HP_LANGUAGE_PASCAL,
+  HP_LANGUAGE_MODCAL,
+  HP_LANGUAGE_COBOL,
+  HP_LANGUAGE_BASIC,
+  HP_LANGUAGE_ADA,
+  HP_LANGUAGE_CPLUSPLUS,
+  HP_LANGUAGE_DMPASCAL
+};
+
+
+/* Basic data types available in this debug format.  Within the data
+   structures this type is limited to 5 bits for a maximum of 32 basic
+   data types.  */
+enum hp_type
+{
+  HP_TYPE_UNDEFINED, /* 0 */
+  HP_TYPE_BOOLEAN, /* 1 */
+  HP_TYPE_CHAR, /* 2 */
+  HP_TYPE_INT, /* 3 */
+  HP_TYPE_UNSIGNED_INT, /* 4 */
+  HP_TYPE_REAL, /* 5 */
+  HP_TYPE_COMPLEX, /* 6 */
+  HP_TYPE_STRING200, /* 7 */
+  HP_TYPE_LONGSTRING200, /* 8 */
+  HP_TYPE_TEXT, /* 9 */
+  HP_TYPE_FLABEL, /* 10 */
+  HP_TYPE_FTN_STRING_SPEC, /* 11 */
+  HP_TYPE_MOD_STRING_SPEC, /* 12 */
+  HP_TYPE_PACKED_DECIMAL, /* 13 */
+  HP_TYPE_REAL_3000, /* 14 */
+  HP_TYPE_MOD_STRING_3000, /* 15 */
+  HP_TYPE_ANYPOINTER, /* 16 */
+  HP_TYPE_GLOBAL_ANYPOINTER, /* 17 */
+  HP_TYPE_LOCAL_ANYPOINTER, /* 18 */
+  HP_TYPE_COMPLEXS3000, /* 19 */
+  HP_TYPE_FTN_STRING_S300_COMPAT, /* 20 */ 
+  HP_TYPE_FTN_STRING_VAX_COMPAT, /* 21 */
+  HP_TYPE_BOOLEAN_S300_COMPAT, /* 22 */
+  HP_TYPE_BOOLEAN_VAX_COMPAT, /* 23 */
+  HP_TYPE_WIDE_CHAR, /* 24 */
+  HP_TYPE_LONG, /* 25 */
+  HP_TYPE_UNSIGNED_LONG, /* 26 */
+  HP_TYPE_DOUBLE, /* 27 */
+  HP_TYPE_TEMPLATE_ARG, /* 28 */
+  HP_TYPE_VOID /* 29 */
+};
+
+/* An immediate name and type table entry.
+
+   extension and immediate will always be one.
+   global will always be zero.
+   hp_type is the basic type this entry describes.
+   bitlength is the length in bits for the basic type.  */
+struct dnttp_immediate
+{
+  unsigned int extension:	1;
+  unsigned int immediate:	1;
+  unsigned int global:		1;
+  unsigned int type: 		5;
+  unsigned int bitlength:	24;
+};
+
+/* A nonimmediate name and type table entry.
+
+   extension will always be one.
+   immediate will always be zero.
+   if global is zero, this entry points into the LNTT
+   if global is one, this entry points into the GNTT
+   index is the index within the GNTT or LNTT for this entry.  */
+struct dnttp_nonimmediate
+{
+  unsigned int extension:	1;
+  unsigned int immediate:	1;
+  unsigned int global:		1;
+  unsigned int index:		29;
+};
+
+/* A pointer to an entry in the GNTT and LNTT tables.  It has two
+   forms depending on the type being described.
+
+   The immediate form is used for simple entries and is one
+   word.
+
+   The nonimmediate form is used for complex entries and contains
+   an index into the LNTT or GNTT which describes the entire type.
+
+   If a dnttpointer is -1, then it is a NIL entry.  */
+
+#define DNTTNIL (-1)
+typedef union dnttpointer
+{
+  struct dnttp_immediate    dntti;
+  struct dnttp_nonimmediate dnttp;
+  int word;
+} dnttpointer;
+
+/* An index into the source line table.  As with dnttpointers, a sltpointer
+   of -1 indicates a NIL entry.  */
+#define SLTNIL (-1)
+typedef int sltpointer;
+
+/* Index into DOC (= "Debugging Optimized Code") line table.  */
+#define LTNIL (-1)
+typedef int ltpointer;
+
+/* Index into context table.  */
+#define CTXTNIL (-1)
+typedef int ctxtpointer;
+
+/* Unsigned byte offset into the VT.  */
+typedef unsigned int vtpointer;
+
+/* A DNTT entry (used within the GNTT and LNTT).
+
+   DNTT entries are variable sized objects, but are always a multiple
+   of 3 words (we call each group of 3 words a "block").
+
+   The first bit in each block is an extension bit.  This bit is zero
+   for the first block of a DNTT entry.  If the entry requires more
+   than one block, then this bit is set to one in all blocks after
+   the first one.  */
+
+/* Each DNTT entry describes a particular debug symbol (beginning of
+   a source file, a function, variables, structures, etc.
+
+   The type of the DNTT entry is stored in the "kind" field within the
+   DNTT entry itself.  */
+
+enum dntt_entry_type
+{
+  DNTT_TYPE_NIL = -1,
+  DNTT_TYPE_SRCFILE,
+  DNTT_TYPE_MODULE,
+  DNTT_TYPE_FUNCTION,
+  DNTT_TYPE_ENTRY,
+  DNTT_TYPE_BEGIN,
+  DNTT_TYPE_END,
+  DNTT_TYPE_IMPORT,
+  DNTT_TYPE_LABEL,
+  DNTT_TYPE_FPARAM,
+  DNTT_TYPE_SVAR,
+  DNTT_TYPE_DVAR,
+  DNTT_TYPE_HOLE1,
+  DNTT_TYPE_CONST,
+  DNTT_TYPE_TYPEDEF,
+  DNTT_TYPE_TAGDEF,
+  DNTT_TYPE_POINTER,
+  DNTT_TYPE_ENUM,
+  DNTT_TYPE_MEMENUM,
+  DNTT_TYPE_SET,
+  DNTT_TYPE_SUBRANGE,
+  DNTT_TYPE_ARRAY,
+  DNTT_TYPE_STRUCT,
+  DNTT_TYPE_UNION,
+  DNTT_TYPE_FIELD,
+  DNTT_TYPE_VARIANT,
+  DNTT_TYPE_FILE,
+  DNTT_TYPE_FUNCTYPE,
+  DNTT_TYPE_WITH,
+  DNTT_TYPE_COMMON,
+  DNTT_TYPE_COBSTRUCT,
+  DNTT_TYPE_XREF,
+  DNTT_TYPE_SA,
+  DNTT_TYPE_MACRO,
+  DNTT_TYPE_BLOCKDATA,
+  DNTT_TYPE_CLASS_SCOPE,
+  DNTT_TYPE_REFERENCE,
+  DNTT_TYPE_PTRMEM,
+  DNTT_TYPE_PTRMEMFUNC,
+  DNTT_TYPE_CLASS,
+  DNTT_TYPE_GENFIELD,
+  DNTT_TYPE_VFUNC,
+  DNTT_TYPE_MEMACCESS,
+  DNTT_TYPE_INHERITANCE,
+  DNTT_TYPE_FRIEND_CLASS,
+  DNTT_TYPE_FRIEND_FUNC,
+  DNTT_TYPE_MODIFIER,
+  DNTT_TYPE_OBJECT_ID,
+  DNTT_TYPE_MEMFUNC,
+  DNTT_TYPE_TEMPLATE,
+  DNTT_TYPE_TEMPLATE_ARG,
+  DNTT_TYPE_FUNC_TEMPLATE,
+  DNTT_TYPE_LINK,
+  DNTT_TYPE_DYN_ARRAY_DESC,
+  DNTT_TYPE_DESC_SUBRANGE,
+  DNTT_TYPE_BEGIN_EXT,
+  DNTT_TYPE_INLN,
+  DNTT_TYPE_INLN_LIST,
+  DNTT_TYPE_ALIAS,
+  DNTT_TYPE_DOC_FUNCTION,
+  DNTT_TYPE_DOC_MEMFUNC,
+  DNTT_TYPE_MAX
+};
+
+/* DNTT_TYPE_SRCFILE:
+
+   One DNTT_TYPE_SRCFILE symbol is output for the start of each source
+   file and at the begin and end of an included file.  A DNTT_TYPE_SRCFILE
+   entry is also output before each DNTT_TYPE_FUNC symbol so that debuggers
+   can determine what file a function was defined in.
+
+   LANGUAGE describes the source file's language.
+
+   NAME points to an VT entry providing the source file's name.
+
+   Note the name used for DNTT_TYPE_SRCFILE entries are exactly as seen
+   by the compiler (ie they may be relative or absolute).  C include files
+   via <> inclusion must use absolute paths.
+
+   ADDRESS points to an SLT entry from which line number and code locations
+   may be determined.  */
+
+struct dntt_type_srcfile
+{
+  unsigned int extension:	1;
+  unsigned int kind:		10;    /* DNTT_TYPE_SRCFILE */
+  unsigned int language:	4;
+  unsigned int unused:		17;
+  vtpointer name;
+  sltpointer address;
+};
+
+/* DNTT_TYPE_MODULE:
+
+   A DNTT_TYPE_MODULE symbol is emitted for the start of a pascal
+   module or C source file. A module indicates a compilation unit
+   for name-scoping purposes; in that regard there should be 
+   a 1-1 correspondence between GDB "symtab"'s and MODULE symbol records.
+
+   Each DNTT_TYPE_MODULE must have an associated DNTT_TYPE_END symbol.
+
+   NAME points to a VT entry providing the module's name.  Note C
+   source files are considered nameless modules.
+
+   ALIAS point to a VT entry providing a secondary name.
+
+   ADDRESS points to an SLT entry from which line number and code locations
+   may be determined.  */
+
+struct dntt_type_module
+{
+  unsigned int extension:	1;
+  unsigned int kind:		10; 	/* DNTT_TYPE_MODULE */
+  unsigned int unused:		21;
+  vtpointer name;
+  vtpointer alias;
+  dnttpointer unused2;
+  sltpointer address;
+};
+
+/* DNTT_TYPE_FUNCTION,
+   DNTT_TYPE_ENTRY,
+   DNTT_TYPE_BLOCKDATA,
+   DNTT_TYPE_MEMFUNC:
+
+   A DNTT_TYPE_FUNCTION symbol is emitted for each function definition;
+   a DNTT_TYPE_ENTRY symbols is used for secondary entry points.  Both
+   symbols used the dntt_type_function structure.
+   A DNTT_TYPE_BLOCKDATA symbol is emitted ...?
+   A DNTT_TYPE_MEMFUNC symbol is emitted for inlined member functions (C++). 
+
+   Each of DNTT_TYPE_FUNCTION must have a matching DNTT_TYPE_END.
+
+   GLOBAL is nonzero if the function has global scope.
+
+   LANGUAGE describes the function's source language.
+
+   OPT_LEVEL describes the optimization level the function was compiled
+   with.
+
+   VARARGS is nonzero if the function uses varargs.
+
+   NAME points to a VT entry providing the function's name.
+
+   ALIAS points to a VT entry providing a secondary name for the function.
+
+   FIRSTPARAM points to a LNTT entry which describes the parameter list.
+
+   ADDRESS points to an SLT entry from which line number and code locations
+   may be determined.
+
+   ENTRYADDR is the memory address corresponding the function's entry point
+
+   RETVAL points to a LNTT entry describing the function's return value.
+
+   LOWADDR is the lowest memory address associated with this function.
+
+   HIADDR is the highest memory address associated with this function.  */
+
+struct dntt_type_function
+{
+  unsigned int extension:	1;
+  unsigned int kind:		10;	/* DNTT_TYPE_FUNCTION,
+				           DNTT_TYPE_ENTRY,
+					   DNTT_TYPE_BLOCKDATA
+					   or DNTT_TYPE_MEMFUNC */
+  unsigned int global:		1;
+  unsigned int language:	4;
+  unsigned int nest_level:	5;
+  unsigned int opt_level:	2;
+  unsigned int varargs:		1;
+  unsigned int lang_info:	4;
+  unsigned int inlined:		1;
+  unsigned int localalloc:	1;
+  unsigned int expansion:	1;
+  unsigned int unused:		1;
+  vtpointer name;
+  vtpointer alias;
+  dnttpointer firstparam;
+  sltpointer address;
+  CORE_ADDR entryaddr;
+  dnttpointer retval;
+  CORE_ADDR lowaddr;
+  CORE_ADDR hiaddr;
+};
+
+/* DNTT_TYPE_BEGIN:
+
+   A DNTT_TYPE_BEGIN symbol is emitted to begin a new nested scope.
+   Every DNTT_TYPE_BEGIN symbol must have a matching DNTT_TYPE_END symbol.
+
+   CLASSFLAG is nonzero if this is the beginning of a c++ class definition.
+
+   ADDRESS points to an SLT entry from which line number and code locations
+   may be determined.  */
+
+struct dntt_type_begin
+{
+  unsigned int extension:	1;
+  unsigned int kind:		10;
+  unsigned int classflag:	1;
+  unsigned int unused:		20;
+  sltpointer address;
+};
+
+/* DNTT_TYPE_END:
+
+   A DNTT_TYPE_END symbol is emitted when closing a scope started by
+   a DNTT_TYPE_MODULE, DNTT_TYPE_FUNCTION, DNTT_TYPE_WITH,
+   DNTT_TYPE_COMMON, DNTT_TYPE_BEGIN, and DNTT_TYPE_CLASS_SCOPE symbols.
+
+   ENDKIND describes what type of scope the DNTT_TYPE_END is closing
+   (one of the above 6 kinds).
+
+   CLASSFLAG is nonzero if this is the end of a c++ class definition.
+
+   ADDRESS points to an SLT entry from which line number and code locations
+   may be determined.
+
+   BEGINSCOPE points to the LNTT entry which opened the scope.  */
+
+struct dntt_type_end
+{
+  unsigned int extension:	1;
+  unsigned int kind:		10;
+  unsigned int endkind:		10;
+  unsigned int classflag:	1;
+  unsigned int unused:		10;
+  sltpointer address;
+  dnttpointer beginscope;
+};
+
+/* DNTT_TYPE_IMPORT is unused by GDB.  */
+/* DNTT_TYPE_LABEL is unused by GDB.  */
+
+/* DNTT_TYPE_FPARAM:
+
+   A DNTT_TYPE_FPARAM symbol is emitted for a function argument.  When
+   chained together the symbols represent an argument list for a function.
+
+   REGPARAM is nonzero if this parameter was passed in a register.
+
+   INDIRECT is nonzero if this parameter is a pointer to the parameter
+   (pass by reference or pass by value for large items).
+
+   LONGADDR is nonzero if the parameter is a 64bit pointer.
+
+   NAME is a pointer into the VT for the parameter's name.
+
+   LOCATION describes where the parameter is stored.  Depending on the
+   parameter type LOCATION could be a register number, or an offset
+   from the stack pointer.
+
+   TYPE points to a NTT entry describing the type of this parameter.
+
+   NEXTPARAM points to the LNTT entry describing the next parameter.  */
+
+struct dntt_type_fparam
+{
+  unsigned int extension:	1;
+  unsigned int kind:		10;
+  unsigned int regparam:	1;
+  unsigned int indirect:	1;
+  unsigned int longaddr:	1;
+  unsigned int copyparam:	1;
+  unsigned int dflt:		1;
+  unsigned int doc_ranges:	1;
+  unsigned int misc_kind:       1;
+  unsigned int unused:		14;
+  vtpointer name;
+  CORE_ADDR location;
+  dnttpointer type;
+  dnttpointer nextparam;
+  int misc;
+};
+
+/* DNTT_TYPE_SVAR:
+
+   A DNTT_TYPE_SVAR is emitted to describe a variable in static storage.
+
+   GLOBAL is nonzero if the variable has global scope.
+
+   INDIRECT is nonzero if the variable is a pointer to an object.
+
+   LONGADDR is nonzero if the variable is in long pointer space.
+
+   STATICMEM is nonzero if the variable is a member of a class.
+
+   A_UNION is nonzero if the variable is an anonymous union member.
+
+   NAME is a pointer into the VT for the variable's name.
+
+   LOCATION provides the memory address for the variable.
+
+   TYPE is a pointer into either the GNTT or LNTT which describes
+   the type of this variable.  */
+
+struct dntt_type_svar
+{
+  unsigned int extension:	1;
+  unsigned int kind:		10;
+  unsigned int global:		1;
+  unsigned int indirect:	1;
+  unsigned int longaddr:	1;
+  unsigned int staticmem:	1;
+  unsigned int a_union:		1;
+  unsigned int unused1:         1;
+  unsigned int thread_specific: 1;
+  unsigned int unused2:         14;
+  vtpointer name;
+  CORE_ADDR location;
+  dnttpointer type;
+  unsigned int offset;
+  unsigned int displacement;
+};
+
+/* DNTT_TYPE_DVAR:
+
+   A DNTT_TYPE_DVAR is emitted to describe automatic variables and variables
+   held in registers.
+
+   GLOBAL is nonzero if the variable has global scope.
+
+   INDIRECT is nonzero if the variable is a pointer to an object.
+
+   REGVAR is nonzero if the variable is in a register.
+
+   A_UNION is nonzero if the variable is an anonymous union member.
+
+   NAME is a pointer into the VT for the variable's name.
+
+   LOCATION provides the memory address or register number for the variable.
+
+   TYPE is a pointer into either the GNTT or LNTT which describes
+   the type of this variable.  */
+
+struct dntt_type_dvar
+{
+  unsigned int extension:	1;
+  unsigned int kind:		10;
+  unsigned int global:		1;
+  unsigned int indirect:	1;
+  unsigned int regvar:		1;
+  unsigned int a_union:		1;
+  unsigned int unused:		17;
+  vtpointer name;
+  int location;
+  dnttpointer type;
+  unsigned int offset;
+};
+
+/* DNTT_TYPE_CONST:
+
+   A DNTT_TYPE_CONST symbol is emitted for program constants.
+
+   GLOBAL is nonzero if the constant has global scope.
+
+   INDIRECT is nonzero if the constant is a pointer to an object.
+
+   LOCATION_TYPE describes where to find the constant's value
+   (in the VT, memory, or embedded in an instruction).
+
+   CLASSMEM is nonzero if the constant is a member of a class.
+
+   NAME is a pointer into the VT for the constant's name.
+
+   LOCATION provides the memory address, register number or pointer
+   into the VT for the constant's value.
+
+   TYPE is a pointer into either the GNTT or LNTT which describes
+   the type of this variable.  */
+
+struct dntt_type_const
+{
+  unsigned int extension:	1;
+  unsigned int kind:		10;
+  unsigned int global:		1;
+  unsigned int indirect:	1;
+  unsigned int location_type:	3;
+  unsigned int classmem:	1;
+  unsigned int unused:		15;
+  vtpointer name;
+  CORE_ADDR location;
+  dnttpointer type;
+  unsigned int offset;
+  unsigned int displacement;
+};
+
+/* DNTT_TYPE_TYPEDEF and DNTT_TYPE_TAGDEF:
+
+   The same structure is used to describe typedefs and tagdefs.
+
+   DNTT_TYPE_TYPEDEFS are associated with C "typedefs".
+
+   DNTT_TYPE_TAGDEFs are associated with C "struct", "union", and "enum"
+   tags, which may have the same name as a typedef in the same scope.
+   Also they are associated with C++ "class" tags, which implicitly have 
+   the same name as the class type.
+
+   GLOBAL is nonzero if the typedef/tagdef has global scope.
+
+   TYPEINFO is used to determine if full type information is available
+   for a tag.  (usually 1, but can be zero for opaque types in C).
+
+   NAME is a pointer into the VT for the constant's name.
+
+   TYPE points to the underlying type for the typedef/tagdef in the
+   GNTT or LNTT.  */
+
+struct dntt_type_type
+{
+  unsigned int extension:	1;
+  unsigned int kind:		10;    /* DNTT_TYPE_TYPEDEF or 
+                                          DNTT_TYPE_TAGDEF.  */
+  unsigned int global:		1;
+  unsigned int typeinfo:	1;
+  unsigned int unused:		19;
+  vtpointer name;
+  dnttpointer type;                    /* Underlying type, which for TAGDEF's may be
+                                          DNTT_TYPE_STRUCT, DNTT_TYPE_UNION,
+                                          DNTT_TYPE_ENUM, or DNTT_TYPE_CLASS. 
+                                          For TYPEDEF's other underlying types
+                                          are also possible.  */
+};
+
+/* DNTT_TYPE_POINTER:
+
+   Used to describe a pointer to an underlying type.
+
+   POINTSTO is a pointer into the GNTT or LNTT for the type which this
+   pointer points to.
+
+   BITLENGTH is the length of the pointer (not the underlying type). */
+
+struct dntt_type_pointer
+{
+  unsigned int extension:	1;
+  unsigned int kind:		10;
+  unsigned int unused:		21;
+  dnttpointer pointsto;
+  unsigned int bitlength;
+};
+
+
+/* DNTT_TYPE_ENUM:
+
+   Used to describe enumerated types.
+
+   FIRSTMEM is a pointer to a DNTT_TYPE_MEMENUM in the GNTT/LNTT which
+   describes the first member (and contains a pointer to the chain of
+   members).
+
+   BITLENGTH is the number of bits used to hold the values of the enum's
+   members.  */
+
+struct dntt_type_enum
+{
+  unsigned int extension:	1;
+  unsigned int kind:	10;
+  unsigned int unused:		21;
+  dnttpointer firstmem;
+  unsigned int bitlength;
+};
+
+/* DNTT_TYPE_MEMENUM
+
+   Used to describe members of an enumerated type.
+
+   CLASSMEM is nonzero if this member is part of a class.
+
+   NAME points into the VT for the name of this member.
+
+   VALUE is the value of this enumeration member.
+
+   NEXTMEM points to the next DNTT_TYPE_MEMENUM in the chain.  */
+
+struct dntt_type_memenum
+{
+  unsigned int extension:	1;
+  unsigned int kind:	10;
+  unsigned int classmem:	1;
+  unsigned int unused:		20;
+  vtpointer name;
+  unsigned int value;
+  dnttpointer nextmem;
+};
+
+/* DNTT_TYPE_SET
+
+   Used to describe PASCAL "set" type.
+
+   DECLARATION describes the bitpacking of the set.
+
+   SUBTYPE points to a DNTT entry describing the type of the members.
+
+   BITLENGTH is the size of the set.  */ 
+
+struct dntt_type_set
+{
+  unsigned int extension:	1;
+  unsigned int kind:	10;
+  unsigned int declaration:	2;
+  unsigned int unused:		19;
+  dnttpointer subtype;
+  unsigned int bitlength;
+};
+
+/* DNTT_TYPE_SUBRANGE
+
+   Used to describe subrange type.
+
+   DYN_LOW describes the lower bound of the subrange:
+
+     00 for a constant lower bound (found in LOWBOUND).
+
+     01 for a dynamic lower bound with the lower bound found in the
+     memory address pointed to by LOWBOUND.
+
+     10 for a dynamic lower bound described by an variable found in the
+     DNTT/LNTT (LOWBOUND would be a pointer into the DNTT/LNTT).
+
+   DYN_HIGH is similar to DYN_LOW, except it describes the upper bound.
+
+   SUBTYPE points to the type of the subrange.
+
+   BITLENGTH is the length in bits needed to describe the subrange's
+   values.  */
+
+struct dntt_type_subrange
+{
+  unsigned int extension:	1;
+  unsigned int kind:	10;
+  unsigned int dyn_low:		2;
+  unsigned int dyn_high:	2;
+  unsigned int unused:		17;
+  int lowbound;
+  int highbound;
+  dnttpointer subtype;
+  unsigned int bitlength;
+};
+
+/* DNTT_TYPE_ARRAY
+
+   Used to describe an array type.
+
+   DECLARATION describes the bit packing used in the array.
+
+   ARRAYISBYTES is nonzero if the field in arraylength describes the
+   length in bytes rather than in bits.  A value of zero is used to
+   describe an array with size 2**32.
+
+   ELEMISBYTES is nonzero if the length if each element in the array
+   is describes in bytes rather than bits.  A value of zero is used
+   to an element with size 2**32.
+
+   ELEMORDER is nonzero if the elements are indexed in increasing order.
+
+   JUSTIFIED if the elements are left justified to index zero.
+
+   ARRAYLENGTH is the length of the array.
+
+   INDEXTYPE is a DNTT pointer to the type used to index the array.
+
+   ELEMTYPE is a DNTT pointer to the type for the array elements.
+
+   ELEMLENGTH is the length of each element in the array (including
+   any padding).
+
+   Multi-dimensional arrays are represented by ELEMTYPE pointing to
+   another DNTT_TYPE_ARRAY.  */
+
+struct dntt_type_array
+{
+  unsigned int extension:	1;
+  unsigned int kind:	10;
+  unsigned int declaration:	2;
+  unsigned int dyn_low:		2;
+  unsigned int dyn_high:	2;
+  unsigned int arrayisbytes:	1;
+  unsigned int elemisbytes:	1;
+  unsigned int elemorder:	1;
+  unsigned int justified:	1;
+  unsigned int unused:		11;
+  unsigned int arraylength;
+  dnttpointer indextype;
+  dnttpointer elemtype;
+  unsigned int elemlength;
+};
+
+/* DNTT_TYPE_STRUCT
+
+   DNTT_TYPE_STRUCT is used to describe a C structure.
+
+   DECLARATION describes the bitpacking used.
+
+   FIRSTFIELD is a DNTT pointer to the first field of the structure
+   (each field contains a pointer to the next field, walk the list
+   to access all fields of the structure).
+
+   VARTAGFIELD and VARLIST are used for Pascal variant records.
+
+   BITLENGTH is the size of the structure in bits.  */
+
+struct dntt_type_struct
+{
+  unsigned int extension:	1;
+  unsigned int kind:	10;
+  unsigned int declaration:	2;
+  unsigned int unused:		19;
+  dnttpointer firstfield;
+  dnttpointer vartagfield;
+  dnttpointer varlist;
+  unsigned int bitlength;
+};
+
+/* DNTT_TYPE_UNION
+
+   DNTT_TYPE_UNION is used to describe a C union.
+
+   FIRSTFIELD is a DNTT pointer to the beginning of the field chain.
+
+   BITLENGTH is the size of the union in bits.  */
+
+struct dntt_type_union
+{
+  unsigned int extension:	1;
+  unsigned int kind:	10;
+  unsigned int unused:		21;
+  dnttpointer firstfield;
+  unsigned int bitlength;
+};
+
+/* DNTT_TYPE_FIELD
+
+   DNTT_TYPE_FIELD describes one field in a structure or union
+   or C++ class.
+
+   VISIBILITY is used to describe the visibility of the field
+   (for c++.  public = 0, protected = 1, private = 2).
+
+   A_UNION is nonzero if this field is a member of an anonymous union.
+
+   STATICMEM is nonzero if this field is a static member of a template.
+
+   NAME is a pointer into the VT for the name of the field.
+
+   BITOFFSET gives the offset of this field in bits from the beginning
+   of the structure or union this field is a member of.
+
+   TYPE is a DNTT pointer to the type describing this field.
+
+   BITLENGTH is the size of the entry in bits.
+
+   NEXTFIELD is a DNTT pointer to the next field in the chain.  */
+
+struct dntt_type_field
+{
+  unsigned int extension:	1;
+  unsigned int kind:	10;
+  unsigned int visibility:	2;
+  unsigned int a_union:		1;
+  unsigned int staticmem:	1;
+  unsigned int unused:		17;
+  vtpointer name;
+  unsigned int bitoffset;
+  dnttpointer type;
+  unsigned int bitlength;
+  dnttpointer nextfield;
+};
+
+/* DNTT_TYPE_VARIANT is unused by GDB.  */
+/* DNTT_TYPE_FILE is unused by GDB.  */
+
+/* DNTT_TYPE_FUNCTYPE
+
+   I think this is used to describe a function type (e.g., would
+   be emitted as part of a function-pointer description).
+
+   VARARGS is nonzero if this function uses varargs.
+
+   FIRSTPARAM is a DNTT pointer to the first entry in the parameter
+   chain.
+
+   RETVAL is a DNTT pointer to the type of the return value.  */
+
+struct dntt_type_functype
+{
+  unsigned int extension:	1;
+  unsigned int kind:		10;
+  unsigned int varargs:		1;
+  unsigned int info:		4;
+  unsigned int unused:		16;
+  unsigned int bitlength;
+  dnttpointer firstparam;
+  dnttpointer retval;
+};
+
+/* DNTT_TYPE_WITH is emitted by C++ to indicate "with" scoping semantics.
+   (Probably also emitted by PASCAL to support "with"...).
+   
+   C++ example: Say "memfunc" is a method of class "c", and say
+   "m" is a data member of class "c". Then from within "memfunc",
+   it is legal to reference "m" directly (e.g. you don't have to
+   say "this->m". The symbol table indicates
+   this by emitting a DNTT_TYPE_WITH symbol within the function "memfunc",
+   pointing to the type symbol for class "c".
+ 
+   In GDB, this symbol record is unnecessary, 
+   because GDB's symbol lookup algorithm
+   infers the "with" semantics when it sees a "this" argument to the member
+   function. So GDB can safely ignore the DNTT_TYPE_WITH record.
+
+   A DNTT_TYPE_WITH has a matching DNTT_TYPE_END symbol.  */
+
+struct dntt_type_with
+{
+  unsigned int extension:	1;    /* always zero */
+  unsigned int kind:		10;   /* always DNTT_TYPE_WITH */
+  unsigned int addrtype:  	2;    /* 0 => STATTYPE                */
+                                      /* 1 => DYNTYPE                 */
+                                      /* 2 => REGTYPE                 */
+  unsigned int indirect: 	1;    /* 1 => pointer to object       */
+  unsigned int longaddr:  	1;    /* 1 => in long pointer space   */
+  unsigned int nestlevel: 	6;    /* # of nesting levels back     */
+  unsigned int doc_ranges: 	1;    /* 1 => location is range list  */
+  unsigned int unused:   	10;
+  long location;       		      /* where stored (allocated)     */
+  sltpointer address;
+  dnttpointer type;                   /* type of with expression      */
+  vtpointer name;                     /* name of with expression      */
+  unsigned long  offset;              /* byte offset from location    */
+};                                   
+
+/* DNTT_TYPE_COMMON is unsupported by GDB.  */
+/* A DNTT_TYPE_COMMON symbol must have a matching DNTT_TYPE_END symbol */
+
+/* DNTT_TYPE_COBSTRUCT is unsupported by GDB.  */
+/* DNTT_TYPE_XREF is unsupported by GDB.  */
+/* DNTT_TYPE_SA is unsupported by GDB.  */
+/* DNTT_TYPE_MACRO is unsupported by GDB */
+
+/* DNTT_TYPE_BLOCKDATA has the same structure as DNTT_TYPE_FUNCTION */
+
+/* The following are the C++ specific SOM records */
+
+/*  The purpose of the DNTT_TYPE_CLASS_SCOPE is to bracket C++ methods
+    and indicate the method name belongs in the "class scope" rather
+    than in the module they are being defined in. For example:
+
+    class c {
+    ...
+    void memfunc(); // member function
+    };
+
+    void c::memfunc()   // definition of class c's "memfunc"
+    {
+    ...
+    }
+
+    main()
+    {
+    ...
+    }
+
+    In the above, the name "memfunc" is not directly visible from "main".
+    I.e., you have to say "break c::memfunc".
+    If it were a normal function (not a method), it would be visible
+    via the simple "break memfunc". Since "memfunc" otherwise looks
+    like a normal FUNCTION in the symbol table, the bracketing
+    CLASS_SCOPE is what is used to indicate it is really a method.
+    
+
+   A DNTT_TYPE_CLASS_SCOPE symbol must have a matching DNTT_TYPE_END symbol.  */
+
+struct dntt_type_class_scope
+{
+  unsigned int extension:   1;	   /* Always zero.  */
+  unsigned int kind:       10;     /* Always DNTT_TYPE_CLASS_SCOPE.  */
+  unsigned int unused:     21; 
+  sltpointer address         ;     /* Pointer to SLT entry.  */
+  dnttpointer type           ;     /* Pointer to class type DNTT.  */
+};
+
+/* C++ reference parameter.
+   The structure of this record is the same as DNTT_TYPE_POINTER - 
+   refer to struct dntt_type_pointer.  */
+
+/* The next two describe C++ pointer-to-data-member type, and 
+   pointer-to-member-function type, respectively.
+   DNTT_TYPE_PTRMEM and DNTT_TYPE_PTRMEMFUNC have the same structure.  */
+
+struct dntt_type_ptrmem
+{
+  unsigned int extension:   1;	   /* Always zero.  */
+  unsigned int kind:       10;     /* Always DNTT_TYPE_PTRMEM.  */
+  unsigned int unused:	   21;
+  dnttpointer pointsto	     ;     /* Pointer to class DNTT.  */
+  dnttpointer memtype 	     ;     /* Type of member.  */
+};
+
+struct dntt_type_ptrmemfunc
+{
+  unsigned int extension:   1;	   /* Always zero.  */
+  unsigned int kind:       10;     /* Always DNTT_TYPE_PTRMEMFUNC.  */
+  unsigned int unused:	   21;
+  dnttpointer pointsto	     ;     /* Pointer to class DNTT.  */
+  dnttpointer memtype 	     ;     /* Type of member.  */
+};
+
+/* The DNTT_TYPE_CLASS symbol is emitted to describe a class type.
+   "memberlist" points to a chained list of FIELD or GENFIELD records
+   indicating the class members. "parentlist" points to a chained list
+   of INHERITANCE records indicating classes from which we inherit
+   fields.  */
+
+struct dntt_type_class 
+{
+  unsigned int extension:   1;     /* Always zero.  */
+  unsigned int kind:       10;     /* Always DNTT_TYPE_CLASS.  */
+  unsigned int abstract:    1;     /* Is this an abstract class?  */
+  unsigned int class_decl:  2;     /* 0=class,1=union,2=struct.  */
+  unsigned int expansion:   1;     /* 1=template expansion.  */
+  unsigned int unused:     17;     
+  dnttpointer memberlist     ;     /* Ptr to chain of [GEN]FIELDs.  */
+  unsigned long vtbl_loc     ;     /* Offset in obj of ptr to vtbl.  */
+  dnttpointer parentlist     ;     /* Ptr to K_INHERITANCE list.  */
+  unsigned long bitlength    ;     /* Total at this level.  */
+  dnttpointer identlist      ;     /* Ptr to chain of class ident's.  */
+  dnttpointer friendlist     ;     /* Ptr to K_FRIEND list.  */
+  dnttpointer templateptr    ;     /* Ptr to template.  */
+  dnttpointer nextexp        ;     /* Ptr to next expansion.  */
+};
+
+/* Class members are indicated via either the FIELD record (for
+   data members, same as for C struct fields), or by the GENFIELD record
+   (for member functions).  */
+
+struct dntt_type_genfield
+{
+  unsigned int extension:   1;	   /* Always zero.  */
+  unsigned int kind:       10;     /* Always DNTT_TYPE_GENFIELD.  */
+  unsigned int visibility:  2;     /* Pub = 0, prot = 1, priv = 2.  */
+  unsigned int a_union:     1;     /* 1 => anonymous union member.  */
+  unsigned int unused:	   18;
+  dnttpointer field	     ;     /* Pointer to field or qualifier.  */
+  dnttpointer nextfield      ;     /* Pointer to next field.  */
+};
+
+/* C++ virtual functions.  */
+
+struct dntt_type_vfunc
+{
+  unsigned int extension:   1;	   /* always zero */
+  unsigned int kind:       10;     /* always DNTT_TYPE_VFUNC */
+  unsigned int pure:        1;     /* pure virtual function ?       */
+  unsigned int unused:	   20;
+  dnttpointer funcptr        ;     /* points to FUNCTION symbol     */
+  unsigned long vtbl_offset  ;     /* offset into vtbl for virtual  */
+};
+
+/* Not precisely sure what this is intended for - DDE ignores it.  */
+
+struct dntt_type_memaccess
+{
+  unsigned int extension:   1;	   /* always zero */
+  unsigned int kind:       10;     /* always DNTT_TYPE_MEMACCESS */
+  unsigned int unused:	   21;
+  dnttpointer classptr	     ;     /* pointer to base class         */
+  dnttpointer field          ;     /* pointer field                 */
+};
+
+/* The DNTT_TYPE_INHERITANCE record describes derived classes.
+   In particular, the "parentlist" field of the CLASS record points
+   to a list of INHERITANCE records for classes from which we 
+   inherit members.  */
+
+struct dntt_type_inheritance
+{
+  unsigned int extension:   1;	   /* always zero */
+  unsigned int kind:       10;     /* always DNTT_TYPE_INHERITANCE */
+  unsigned int Virtual:     1;     /* virtual base class ?          */
+  unsigned int visibility:  2;     /* pub = 0, prot = 1, priv = 2   */
+  unsigned int unused:	   18;
+  dnttpointer classname      ;     /* first parent class, if any    */
+  unsigned long offset       ;     /* offset to start of base class */
+  dnttpointer next           ;     /* pointer to next K_INHERITANCE */
+  unsigned long future[2]    ;     /* padding to 3-word block end   */
+};
+
+/* C++ "friend" classes ... */
+
+struct dntt_type_friend_class
+{
+  unsigned int extension:   1;	   /* always zero */
+  unsigned int kind:       10;     /* always DNTT_TYPE_FRIEND_CLASS */
+  unsigned int unused:	   21;
+  dnttpointer classptr       ;     /* pointer to class DNTT         */
+  dnttpointer next           ;     /* next DNTT_FRIEND              */
+};
+
+struct dntt_type_friend_func
+{
+  unsigned int extension:   1;	   /* always zero */
+  unsigned int kind:       10;     /* always DNTT_TYPE_FRIEND_FUNC */
+  unsigned int unused:	   21;
+  dnttpointer funcptr        ;     /* pointer to function           */
+  dnttpointer classptr       ;     /* pointer to class DNTT         */
+  dnttpointer next           ;     /* next DNTT_FRIEND              */
+  unsigned long future[2]    ;     /* padding to 3-word block end   */
+};
+
+/* DDE appears to ignore the DNTT_TYPE_MODIFIER record.
+   It could perhaps be used to give better "ptype" output in GDB;
+   otherwise it is probably safe for GDB to ignore it also.  */
+
+struct dntt_type_modifier
+{
+  unsigned int extension:   1;	   /* always zero */
+  unsigned int kind:       10;     /* always DNTT_TYPE_MODIFIER */
+  unsigned int m_const:     1;     /* const                         */
+  unsigned int m_static:    1;     /* static                        */
+  unsigned int m_void:      1;     /* void                          */
+  unsigned int m_volatile:  1;     /* volatile                      */
+  unsigned int m_duplicate: 1;     /* duplicate                     */
+  unsigned int unused:	   16;
+  dnttpointer type           ;     /* subtype                       */
+  unsigned long future       ;     /* padding to 3-word block end   */
+};
+
+/* I'm not sure what this was intended for - DDE ignores it.  */
+
+struct dntt_type_object_id
+{
+  unsigned int extension:   1;	   /* always zero */
+  unsigned int kind:       10;     /* always DNTT_TYPE_OBJECT_ID */
+  unsigned int indirect:    1;     /* Is object_ident addr of addr? */
+  unsigned int unused:	   20;
+  unsigned long object_ident ;     /* object identifier             */
+  unsigned long offset       ;     /* offset to start of base class */
+  dnttpointer next           ;     /* pointer to next K_OBJECT_ID   */
+  unsigned long segoffset    ;     /* for linker fixup              */
+  unsigned long future       ;     /* padding to 3-word block end   */
+};
+
+/* No separate dntt_type_memfunc; same as dntt_type_func */
+
+/* Symbol records to support templates. These only get used
+   in DDE's "describe" output (like GDB's "ptype").  */
+
+/* The TEMPLATE record is the header for a template-class.
+   Like the CLASS record, a TEMPLATE record has a memberlist that
+   points to a list of template members. It also has an arglist
+   pointing to a list of TEMPLATE_ARG records.  */
+
+struct dntt_type_template
+{
+  unsigned int extension:   1;	   /* always zero */
+  unsigned int kind:       10;     /* always DNTT_TYPE_TEMPLATE */
+  unsigned int abstract:    1;     /* is this an abstract class?    */
+  unsigned int class_decl:  2;     /* 0=class,1=union,2=struct      */
+  unsigned int unused:	   18;
+  dnttpointer memberlist     ;     /* ptr to chain of K_[GEN]FIELDs */
+  long unused2               ;     /* offset in obj of ptr to vtbl  */
+  dnttpointer parentlist     ;     /* ptr to K_INHERITANCE list     */
+  unsigned long bitlength    ;     /* total at this level           */
+  dnttpointer identlist      ;     /* ptr to chain of class ident's */
+  dnttpointer friendlist     ;     /* ptr to K_FRIEND list          */
+  dnttpointer arglist        ;     /* ptr to argument list          */
+  dnttpointer expansions     ;     /* ptr to expansion list         */
+};
+
+/* Template-class arguments are a list of TEMPL_ARG records
+   chained together. The "name" field is the name of the formal.
+   E.g.:
+   
+     template <class T> class q { ... };
+   
+   Then "T" is the name of the formal argument.  */
+
+struct dntt_type_templ_arg
+{
+  unsigned int extension:   1;	   /* always zero */
+  unsigned int kind:       10;     /* always DNTT_TYPE_TEMPL_ARG */
+  unsigned int usagetype:   1;     /* 0 type-name 1 expression     */
+  unsigned int unused:	   20;
+  vtpointer name             ;     /* name of argument             */
+  dnttpointer type           ;     /* for non type arguments       */
+  dnttpointer nextarg        ;     /* Next argument if any         */
+  long future[2]             ;     /* padding to 3-word block end  */
+};
+
+/* FUNC_TEMPLATE records are sort of like FUNCTION, but are emitted
+   for template member functions. E.g.,
+   
+     template <class T> class q
+     {
+        ...
+        void f();
+        ... 
+     };
+   
+   Within the list of FIELDs/GENFIELDs defining the member list
+   of the template "q", "f" would appear as a FUNC_TEMPLATE.
+   We'll also see instances of FUNCTION "f" records for each 
+   instantiation of the template.  */
+
+struct dntt_type_func_template
+{
+  unsigned int extension:   1;	   /* always zero */
+  unsigned int kind:       10;     /* always DNTT_TYPE_FUNC_TEMPLATE */
+  unsigned int public:      1;     /* 1 => globally visible        */
+  unsigned int language:    4;     /* type of language             */
+  unsigned int level:       5;     /* nesting level (top level = 0)*/
+  unsigned int optimize:    2;     /* level of optimization        */
+  unsigned int varargs:     1;     /* ellipses.  Pascal/800 later  */ 
+  unsigned int info:        4;     /* lang-specific stuff; F_xxxx  */
+  unsigned int inlined:     1;
+  unsigned int localloc:    1;     /* 0 at top, 1 at end of block  */
+  unsigned int unused:      2;
+  vtpointer name             ;     /* name of function             */
+  vtpointer alias            ;     /* alternate name, if any       */
+  dnttpointer firstparam     ;     /* first FPARAM, if any         */
+  dnttpointer retval         ;     /* return type, if any          */
+  dnttpointer arglist        ;     /* ptr to argument list         */
+};
+
+/* LINK is apparently intended to link together function template
+   definitions with their instantiations. However, it is not clear
+   why this would be needed, except to provide the information on
+   a "ptype" command. And as far as I can tell, aCC does not 
+   generate this record.  */
+
+struct dntt_type_link
+{
+  unsigned int extension:   1;	   /* always zero */
+  unsigned int kind:       10;     /* always DNTT_TYPE_LINK */
+  unsigned int linkKind:    4;     /* always LINK_UNKNOWN          */
+  unsigned int unused:	   17;
+  long future1               ;     /* expansion                    */
+  dnttpointer ptr1           ;     /* link from template           */
+  dnttpointer ptr2           ;     /* to expansion                 */
+  long future[2]             ;     /* padding to 3-word block end  */
+};
+
+/* end of C++ specific SOM's.  */
+
+/* DNTT_TYPE_DYN_ARRAY_DESC is unused by GDB */
+/* DNTT_TYPE_DESC_SUBRANGE is unused by GDB */
+/* DNTT_TYPE_BEGIN_EXT is unused by GDB */
+/* DNTT_TYPE_INLN is unused by GDB */
+/* DNTT_TYPE_INLN_LIST is unused by GDB */
+/* DNTT_TYPE_ALIAS is unused by GDB */
+
+struct dntt_type_doc_function
+{
+  unsigned int extension: 1;   /* always zero                  */
+  unsigned int kind:     10;   /* K_DOC_FUNCTION or            */
+                               /* K_DOC_MEMFUNC                */
+  unsigned int global:    1;   /* 1 => globally visible        */
+  unsigned int language:  4;   /* type of language             */
+  unsigned int level:     5;   /* nesting level (top level = 0)*/
+  unsigned int optimize:  2;   /* level of optimization        */
+  unsigned int varargs:   1;   /* ellipses.  Pascal/800 later  */
+  unsigned int info:      4;   /* lang-specific stuff; F_xxxx  */
+  unsigned int inlined:   1;
+  unsigned int localloc:  1;   /* 0 at top, 1 at end of block  */
+  unsigned int expansion: 1;   /* 1 = function expansion       */
+  unsigned int doc_clone: 1;
+  vtpointer name;              /* name of function             */
+  vtpointer alias;             /* alternate name, if any       */
+  dnttpointer firstparam;      /* first FPARAM, if any         */
+  sltpointer address;          /* code and text locations      */
+  CORE_ADDR entryaddr;         /* address of entry point       */
+  dnttpointer retval;          /* return type, if any          */
+  CORE_ADDR lowaddr;           /* lowest address of function   */
+  CORE_ADDR hiaddr;            /* highest address of function  */
+  dnttpointer inline_list;     /* pointer to first inline    */
+  ltpointer lt_offset;         /* start of frag/cp line table  */
+  ctxtpointer ctxt_offset;     /* start of context table for this routine */
+};
+
+/* DNTT_TYPE_DOC_MEMFUNC is unused by GDB */
+
+/* DNTT_TYPE_GENERIC and DNTT_TYPE_BLOCK are convience structures
+   so we can examine a DNTT entry in a generic fashion.  */
+struct dntt_type_generic
+{
+  unsigned int word[9];
+};
+
+struct dntt_type_block
+{
+  unsigned int extension:	1;
+  unsigned int kind:            10;
+  unsigned int unused:		21;
+  unsigned int word[2];
+};
+
+/* One entry in a DNTT (either the LNTT or GNTT).  
+   This is a union of the above 60 or so structure definitions.  */
+
+union dnttentry
+{
+  struct dntt_type_srcfile dsfile;
+  struct dntt_type_module dmodule;
+  struct dntt_type_function dfunc;
+  struct dntt_type_function dentry;
+  struct dntt_type_begin dbegin;
+  struct dntt_type_end dend;
+  struct dntt_type_fparam dfparam;
+  struct dntt_type_svar dsvar;
+  struct dntt_type_dvar ddvar;
+  struct dntt_type_const dconst;
+  struct dntt_type_type dtype;
+  struct dntt_type_type dtag;
+  struct dntt_type_pointer dptr;
+  struct dntt_type_enum denum;
+  struct dntt_type_memenum dmember;
+  struct dntt_type_set dset;
+  struct dntt_type_subrange dsubr;
+  struct dntt_type_array darray;
+  struct dntt_type_struct dstruct;
+  struct dntt_type_union dunion;
+  struct dntt_type_field dfield;
+  struct dntt_type_functype dfunctype;
+  struct dntt_type_with dwith;
+  struct dntt_type_function dblockdata;
+  struct dntt_type_class_scope dclass_scope;
+  struct dntt_type_pointer dreference;
+  struct dntt_type_ptrmem dptrmem;
+  struct dntt_type_ptrmemfunc dptrmemfunc;
+  struct dntt_type_class dclass;
+  struct dntt_type_genfield dgenfield;
+  struct dntt_type_vfunc dvfunc;
+  struct dntt_type_memaccess dmemaccess;
+  struct dntt_type_inheritance dinheritance;
+  struct dntt_type_friend_class dfriend_class;
+  struct dntt_type_friend_func dfriend_func;
+  struct dntt_type_modifier dmodifier;
+  struct dntt_type_object_id dobject_id;
+  struct dntt_type_template dtemplate;
+  struct dntt_type_templ_arg dtempl_arg;
+  struct dntt_type_func_template dfunc_template;
+  struct dntt_type_link dlink;
+  struct dntt_type_doc_function ddocfunc;
+  struct dntt_type_generic dgeneric;
+  struct dntt_type_block dblock;
+};
+
+/* Source line entry types.  */
+enum slttype
+{
+  SLT_NORMAL,
+  SLT_SRCFILE,
+  SLT_MODULE,
+  SLT_FUNCTION,
+  SLT_ENTRY,
+  SLT_BEGIN,
+  SLT_END,
+  SLT_WITH,
+  SLT_EXIT,
+  SLT_ASSIST,
+  SLT_MARKER,
+  SLT_CLASS_SCOPE,
+  SLT_INLN,
+  SLT_NORMAL_OFFSET,
+};
+
+/* A normal source line entry.  Simply provides a mapping of a source
+   line number to a code address.
+
+   SLTDESC will always be SLT_NORMAL or SLT_EXIT.  */
+
+struct slt_normal
+{
+  unsigned int sltdesc:	4;
+  unsigned int line:	28;
+  CORE_ADDR address;
+};
+
+struct slt_normal_off
+{
+  unsigned int sltdesc:	4;
+  unsigned int offset:	6;
+  unsigned int line:	22;
+  CORE_ADDR address;
+};
+
+/* A special source line entry.  Provides a mapping of a declaration
+   to a line number.  These entries point back into the DNTT which
+   references them.  */
+
+struct slt_special
+{
+  unsigned int sltdesc:	4;
+  unsigned int line:	28;
+  dnttpointer backptr;
+};
+
+/* Used to describe nesting.
+
+   For nested languages, an slt_assist entry must follow each SLT_FUNC
+   entry in the SLT.  The address field will point forward to the
+   first slt_normal entry within the function's scope.  */
+
+struct slt_assist
+{
+  unsigned int sltdesc:	4;
+  unsigned int unused:	28;
+  sltpointer address;
+};
+
+struct slt_generic
+{
+  unsigned int word[2];
+};
+
+union sltentry
+{
+  struct slt_normal snorm;
+  struct slt_normal_off snormoff;
+  struct slt_special sspec;
+  struct slt_assist sasst;
+  struct slt_generic sgeneric;
+};
+
+/* $LINES$ declarations
+   This is the line table used for optimized code, which is only present 
+   in the new $PROGRAM_INFO$ debug space.  */
+
+#define DST_LN_ESCAPE_FLAG1   15
+#define DST_LN_ESCAPE_FLAG2   14
+#define DST_LN_CTX_SPEC1      13  
+#define DST_LN_CTX_SPEC2      12
+
+/* Escape function codes:  */
+
+typedef enum
+{
+  dst_ln_pad,          /* pad byte */
+  dst_ln_escape_1,     /* reserved */
+  dst_ln_dpc1_dln1,    /* 1 byte line delta, 1 byte pc delta */
+  dst_ln_dpc2_dln2,    /* 2 bytes line delta, 2 bytes pc delta */
+  dst_ln_pc4_ln4,      /* 4 bytes ABSOLUTE line number, 4 bytes ABSOLUTE pc */
+  dst_ln_dpc0_dln1,    /* 1 byte line delta, pc delta = 0 */
+  dst_ln_ln_off_1,     /* statement escape, stmt # = 1 (2nd stmt on line) */
+  dst_ln_ln_off,       /* statement escape, stmt # = next byte */
+  dst_ln_entry,        /* entry escape, next byte is entry number */
+  dst_ln_exit,         /* exit escape */
+  dst_ln_stmt_end,     /* gap escape, 4 bytes pc delta */
+  dst_ln_stmt_cp,      /* current stmt is a critical point */
+  dst_ln_escape_12,    /* reserved */
+  dst_ln_escape_13,    /* this is an exception site record */
+  dst_ln_nxt_byte,     /* next byte contains the real escape code */
+  dst_ln_end,          /* end escape, final entry follows */
+  dst_ln_escape1_END_OF_ENUM
+}
+dst_ln_escape1_t;
+
+typedef enum
+{
+  dst_ln_ctx_1,        	/* next byte describes context switch with 5-bit */
+  			/* index into the image table and 3-bit run length. */
+			/* If run length is 0, end with another cxt specifier or ctx_end */
+  dst_ln_ctx_2,        	/* next 2 bytes switch context: 13 bit index, 3 bit run length */
+  dst_ln_ctx_4,        	/* next 4 bytes switch context: 29 bit index, 3 bit run length */
+  dst_ln_ctx_end,      	/* end current context */
+  dst_ln_col_run_1,    	/* next byte is column position of start of next statement, */
+                        /* following byte is length of statement */
+  dst_ln_col_run_2,    	/* next 2 bytes is column position of start of next statement, */
+                        /* following 2 bytes is length of statement */
+  dst_ln_init_base1,   	/* next 4 bytes are absolute PC, followed by 1 byte of line number */
+  dst_ln_init_base2,   	/* next 4 bytes are absolute PC, followed by 2 bytes of line number */
+  dst_ln_init_base3,   	/* next 4 bytes are absolute PC, followed by 3 bytes of line number */
+  dst_ln_escape2_END_OF_ENUM
+}
+dst_ln_escape2_t;           
+
+typedef union
+{
+  struct
+  {
+    unsigned int     pc_delta : 4;      /* 4 bit pc delta */
+    int              ln_delta : 4;      /* 4 bit line number delta */
+  }
+  delta;
+
+  struct
+  {
+    unsigned int     esc_flag : 4;      /* alias for pc_delta  */
+    unsigned int     esc_code : 4;      /* escape function code (dst_ln_escape1_t, or ...2_t */
+  }
+  esc;
+
+  struct
+  {
+    unsigned int     esc_flag   : 4;      /* dst_ln_ctx_spec1, or dst_ln_ctx_spec2 */
+    unsigned int     run_length : 2;      
+    unsigned int     ctx_index  : 2;      /* ...spec2 contains index;  ...spec1, index - 4 */
+  }
+  ctx_spec;
+
+  char               sdata;               /* signed data byte */
+  unsigned char      udata;               /* unsigned data byte */
+}
+dst_ln_entry_t,
+  * dst_ln_entry_ptr_t;
+
+/* Warning: although the above union occupies only 1 byte the compiler treats
+   it as having size 2 (the minimum size of a struct).  Therefore a sequence of
+   dst_ln_entry_t's cannot be described as an array, and walking through such a
+   sequence requires convoluted code such as
+        ln_ptr = (dst_ln_entry_ptr_t) (char*) ln_ptr + 1
+   We regret the inconvenience.  */
+
+/* Structure for interpreting the byte following a dst_ln_ctx1 entry.  */
+typedef struct
+{
+    unsigned int          ctx1_index : 5;      /* 5 bit index into context table */
+    unsigned int          ctx1_run_length : 3; /* 3 bit run length */
+} dst_ln_ctx1_t,
+  *dst_ln_ctx1_ptr_t;
+
+/* Structure for interpreting the bytes following a dst_ln_ctx2 entry.  */
+typedef struct
+{
+    unsigned int          ctx2_index : 13;     /* 13 bit index into context table */
+    unsigned int          ctx2_run_length : 3; /* 3 bit run length */
+} dst_ln_ctx2_t,
+  *dst_ln_ctx2_ptr_t;
+
+/* Structure for interpreting the bytes following a dst_ln_ctx4 entry.  */
+typedef struct
+{
+    unsigned int          ctx4_index : 29;     /* 29 bit index into context table */
+    unsigned int          ctx4_run_length : 3; /* 3 bit run length */
+} dst_ln_ctx4_t,
+  *dst_ln_ctx4_ptr_t;
+
+
+/*  PXDB definitions.
+  
+   PXDB is a post-processor which takes the executable file
+   and massages the debug information so that the debugger may
+   start up and run more efficiently.  Some of the tasks
+   performed by PXDB are:
+  
+   o   Remove duplicate global type and variable information
+       from the GNTT,
+  
+   o   Append the GNTT onto the end of the LNTT and place both
+       back in the LNTT section,
+  
+   o   Build quick look-up tables (description follows) for
+       files, procedures, modules, and paragraphs (for Cobol),
+       placing these in the GNTT section,
+  
+   o   Reconstruct the header appearing in the header section
+       to access this information.
+  
+   The "quick look-up" tables are in the $GNTT$ sub-space, in
+   the following order:
+  
+       Procedures    -sorted by address
+       Source files  -sorted by address (of the
+                      generated code from routines)
+       Modules       -sorted by address
+       Classes       -<unsorted?>
+       Address Alias -sorted by index <?>
+       Object IDs    -sorted by object identifier
+  
+   Most quick entries have (0-based) indices into the LNTT tables to
+   the full entries for the item it describes.
+  
+   The post-PXDB header is in the $HEADER$ sub-space.  Alas, it
+   occurs in different forms, depending on the optimization level
+   in the compilation step and whether PXDB was run or not. The
+   worst part is the forms aren't self-describing, so we'll have
+   to grovel in the bits to figure out what kind we're looking at
+   (see hp_get_header in hp-psymtab-read.c).  */
+
+/* PXDB versions.  */
+
+#define PXDB_VERSION_CPLUSPLUS	1
+#define PXDB_VERSION_7_4	2
+#define PXDB_VERSION_CPP_30	3
+#define PXDB_VERSION_DDE_3_2A	4
+#define PXDB_VERSION_DDE_3_2	5
+#define PXDB_VERSION_DDE_4_0	6
+
+#define PXDB_VERSION_2_1	1
+
+/* Header version for the case that there is no DOC info
+   but the executable has been processed by pxdb (the easy
+   case, from "cc -g").  */
+
+typedef struct PXDB_struct
+{
+  int              pd_entries;   /* # of entries in function look-up table */
+  int              fd_entries;   /* # of entries in file look-up table */
+  int              md_entries;   /* # of entries in module look-up table */
+  unsigned int     pxdbed : 1;   /* 1 => file has been preprocessed      */
+  unsigned int     bighdr : 1;   /* 1 => this header contains 'time' word */
+  unsigned int     sa_header : 1;/* 1 => created by SA version of pxdb */
+			           /*   used for version check in xdb */
+  unsigned int     inlined: 1;   /* one or more functions have been inlined */
+  unsigned int     spare:12;
+  short            version;      /* pxdb header version */
+  int              globals;      /* index into the DNTT where GNTT begins */
+  unsigned int     time;         /* modify time of file before being pxdbed */
+  int              pg_entries;   /* # of entries in label look-up table */
+  int              functions;    /* actual number of functions */
+  int              files;        /* actual number of files */
+  int              cd_entries;   /* # of entries in class look-up table */
+  int              aa_entries;   /* # of entries in addr alias look-up table */
+  int              oi_entries;   /* # of entries in object id look-up table */
+} PXDB_header, *PXDB_header_ptr;
+
+/* Header version for the case that there is no DOC info and the
+   executable has NOT been processed by pxdb.  */
+
+typedef struct XDB_header_struct
+{
+  long gntt_length; 
+  long lntt_length; 
+  long slt_length; 
+  long vt_length; 
+  long xt_length; 
+} XDB_header;
+
+/* Header version for the case that there is DOC info and the
+   executable has been processed by pxdb. */
+
+typedef struct DOC_info_PXDB_header_struct
+{
+  unsigned int xdb_header: 1; 	      /* bit set if this is post-3.1 xdb */ 
+  unsigned int doc_header: 1;         /* bit set if this is doc-style header */
+  unsigned int version: 8;            /* version of pxdb see defines
+				         PXDB_VERSION_* in this file.  */
+  unsigned int reserved_for_flags: 16;/* for future use; -- must be 
+                                         set to zero.  */
+  unsigned int has_aux_pd_table: 1;   /* $GNTT$ has aux PD table */
+  unsigned int has_expr_table: 1;     /* space has $EXPR$ */       
+  unsigned int has_range_table: 1;    /* space has $RANGE$ */       
+  unsigned int has_context_table: 1;  /* space has $SRC_CTXT$ */    
+  unsigned int has_lines_table: 1;    /* space contains a $LINES$
+                                         subspace for line tables.  */
+  unsigned int has_lt_offset_map: 1;  /* space contains an lt_offset
+                                         subspace for line table mapping.  */
+  /* The following fields are the same as those in the PXDB_header in $DEBUG$ */
+  int           pd_entries;   /* # of entries in function look-up table */
+  int           fd_entries;   /* # of entries in file look-up table */
+  int           md_entries;   /* # of entries in module look-up table */
+  unsigned int  pxdbed : 1;   /* 1 => file has been preprocessed      */
+  unsigned int  bighdr : 1;   /* 1 => this header contains 'time' word */
+  unsigned int  sa_header : 1;/* 1 => created by SA version of pxdb */
+                              /*   used for version check in xdb */
+  unsigned int  inlined: 1;   /* one or more functions have been inlined */
+  unsigned int  spare : 28;
+  int      	globals;      /* index into the DNTT where GNTT begins */
+  unsigned int  time;         /* modify time of file before being pxdbed */
+  int           pg_entries;   /* # of entries in label look-up table */
+  int           functions;    /* actual number of functions */
+  int           files;        /* actual number of files */
+  int           cd_entries;   /* # of entries in class look-up table */
+  int           aa_entries;   /* # of entries in addr alias look-up table */
+  int           oi_entries;   /* # of entries in object id look-up table */
+} DOC_info_PXDB_header;
+
+/* Header version for the case that there is DOC info and the
+   executable has NOT been processed by pxdb.  */
+
+typedef struct DOC_info_header_struct
+{
+  unsigned int xdb_header: 1; 	/* bit set if this is post-3.1 xdb */ 
+  unsigned int doc_header: 1;     /* bit set if this is doc-style header*/
+  unsigned int version: 8;      /* version of debug/header 
+                                   format. For 10.0 the value 
+                                   will be 1. For "Davis" the value is 2.  */
+  unsigned int reserved_for_flags: 18; /* for future use; -- must be set to zero.  */
+  unsigned int has_range_table: 1;     /* space contains a $RANGE$ subspace for variable ranges.  */
+  unsigned int has_context_table: 1;   /* space contains a $CTXT$ subspace for context/inline table.  */
+  unsigned int has_lines_table: 1;     /* space contains a $LINES$ subspace for line tables. */
+  unsigned int has_lt_offset_map: 1;   /* space contains an lt_offset subspace for line table mapping.  */
+
+  long   gntt_length;  /* same as old header */
+  long   lntt_length;  /* same as old header */
+  long   slt_length;   /* same as old header */
+  long   vt_length;    /* same as old header */
+  long   xt_length;    /* same as old header */
+  long   ctxt_length;  /* present only if version >= 2 */
+  long   range_length; /* present only if version >= 2 */
+  long   expr_length;  /* present only if version >= 2 */
+
+} DOC_info_header;
+
+typedef union GenericDebugHeader_union
+{
+   PXDB_header          no_doc;
+   DOC_info_PXDB_header doc;
+   XDB_header           no_pxdb_no_doc;
+   DOC_info_header      no_pxdb_doc;
+} GenericDebugHeader;
+
+
+/*  Procedure Descriptor:
+    An element of the procedure quick look-up table.  */
+
+typedef struct quick_procedure
+{
+  long           isym;		/* 0-based index of first symbol
+                                   for procedure in $LNTT$, 
+                                   i.e. the procedure itself.  */
+  CORE_ADDR	 adrStart;	/* memory adr of start of proc	*/
+  CORE_ADDR	 adrEnd;	/* memory adr of end of proc	*/
+  char         	*sbAlias;	/* alias name of procedure	*/
+  char          *sbProc;	/* real name of procedure	*/
+  CORE_ADDR	 adrBp;		/* address of entry breakpoint  */
+  CORE_ADDR	 adrExitBp;	/* address of exit breakpoint   */
+  int            icd;           /* member of this class (index) */	
+  unsigned int	 ipd;		/* index of template for this   */
+                                /* function (index)           */
+  unsigned int	 unused:    5;
+  unsigned int	 no_lt_offset: 1;/* no entry in lt_offset table */
+  unsigned int	 fTemplate: 1;	/* function template		*/
+  unsigned int	 fExpansion: 1;	/* function expansion		*/
+  unsigned int	 linked	  : 1;	/* linked with other expansions	*/
+  unsigned int	 duplicate: 1;  /* clone of another procedure   */
+  unsigned int	 overloaded:1;  /* overloaded function          */
+  unsigned int	 member:    1;  /* class member function        */
+  unsigned int	 constructor:1; /* constructor function         */
+  unsigned int	 destructor:1;  /* destructor function          */
+  unsigned int   Static:    1;  /* static function              */
+  unsigned int   Virtual:   1;  /* virtual function             */
+  unsigned int   constant:  1;  /* constant function            */
+  unsigned int   pure:      1;  /* pure (virtual) function      */
+  unsigned int   language:  4;  /* procedure's language         */
+  unsigned int   inlined:   1;  /* function has been inlined    */
+  unsigned int   Operator:  1;  /* operator function            */
+  unsigned int	 stub:      1;  /* bodyless function            */
+  unsigned int	 optimize:  2;	/* optimization level   	*/
+  unsigned int	 level:     5;	/* nesting level (top=0)	*/
+} quick_procedure_entry, *quick_procedure_entry_ptr;
+
+/*  Source File Descriptor:
+    An element of the source file quick look-up table.  */
+
+typedef struct quick_source
+{
+  long	         isym;		/* 0-based index in $LNTT$ of
+                                   first symbol for this file.     */
+  CORE_ADDR      adrStart;	/* mem adr of start of file's code */
+  CORE_ADDR      adrEnd;	/* mem adr of end of file's code   */
+  char	        *sbFile;	/* name of source file		   */
+  unsigned int   fHasDecl: 1;	/* do we have a .d file?	   */
+  unsigned int   fWarned:  1;	/* have warned about age problems? */
+  unsigned int   fSrcfile: 1;   /* 0 => include 1=> source         */
+  unsigned short ilnMac;	/* lines in file (0 if don't know) */
+  int	         ipd;		/* 0-based index of first procedure
+                                   in this file, in the quick
+                                   look-up table of procedures.    */
+  unsigned int  *rgLn;		/* line pointer array, if any	   */
+} quick_file_entry, *quick_file_entry_ptr;
+
+/*  Module Descriptor:
+    An element of the module quick reference table.  */
+
+typedef struct quick_module
+{
+  long           isym;		   /* 0-based index of first
+                                      symbol for module.        */
+  CORE_ADDR	 adrStart;	   /* adr of start of mod.	*/
+  CORE_ADDR	 adrEnd;	   /* adr of end of mod.	*/
+  char	        *sbAlias;	   /* alias name of module   	*/
+  char	        *sbMod;		   /* real name of module	*/
+  unsigned int   imports:       1; /* module have any imports?  */
+  unsigned int   vars_in_front: 1; /* module globals in front?  */
+  unsigned int   vars_in_gaps:  1; /* module globals in gaps?   */
+  unsigned int   language:      4; /* type of language          */
+  unsigned int   unused      : 25;
+  unsigned int   unused2;	   /* space for future stuff	*/
+} quick_module_entry, *quick_module_entry_ptr;
+
+/*  Auxiliary Procedure Descriptor:
+    An element of the auxiliary procedure quick look-up table.  */
+
+typedef struct quick_aux_procedure
+{
+  long	 isym_inln;	/* start on inline list for proc */
+  long   spare;
+} quick_aux_procedure_entry, *quick_aux_procedure_entry_ptr;
+
+/*  Paragraph Descriptor:
+    An element of the paragraph quick look-up table.  */
+
+typedef struct quick_paragraph
+{
+  long             isym;       /* first symbol for label (index)  */
+  CORE_ADDR        adrStart;   /* memory adr of start of label    */
+  CORE_ADDR        adrEnd;     /* memory adr of end of label      */
+  char            *sbLab;      /* name of label                   */
+  unsigned int     inst;       /* Used in xdb to store inst @ bp  */
+  unsigned int     sect:    1; /* true = section, false = parag.  */
+  unsigned int     unused: 31; /* future use                      */
+} quick_paragraph_entry, *quick_paragraph_entry_ptr;
+
+/* Class Descriptor:
+   An element of the class quick look-up table.  */
+
+typedef struct quick_class
+{
+  char	         *sbClass;	/* name of class	        */
+  long            isym;         /* class symbol (tag)           */
+  unsigned int	  type : 2;	/* 0=class, 1=union, 2=struct   */
+  unsigned int	  fTemplate : 1;/* class template               */
+  unsigned int	  expansion : 1;/* template expansion           */
+  unsigned int	  unused    :28;
+  sltpointer      lowscope;	/* beginning of defined scope   */
+  sltpointer      hiscope;	/* end of defined scope         */
+} quick_class_entry, *quick_class_entry_ptr;
+
+/* Address Alias Entry
+   An element of the address alias quick look-up table.  */
+
+typedef struct quick_alias
+{
+  CORE_ADDR     low;
+  CORE_ADDR     high;
+  int           index;
+  unsigned int	unused : 31;
+  unsigned int	alternate : 1;	/* alternate unnamed aliases?   */
+} quick_alias_entry, *quick_alias_entry_ptr;
+
+/* Object Identification Entry
+   An element of the object identification quick look-up table.  */
+
+typedef struct quick_obj_ID
+{
+  CORE_ADDR    obj_ident;	/* class identifier         */
+  long         isym;		/* class symbol             */
+  long         offset;		/* offset to object start   */
+} quick_obj_ID_entry, *quick_obj_ID_entry_ptr;
+
+#endif /* HP_SYMTAB_INCLUDED */
diff --git a/binutils-2.25/include/ieee.h b/binutils-2.25/include/ieee.h
new file mode 100644
index 00000000..72fcad42
--- /dev/null
+++ b/binutils-2.25/include/ieee.h
@@ -0,0 +1,165 @@
+/* IEEE Standard 695-1980 "Universal Format for Object Modules" header file
+
+   Copyright 2001 Free Software Foundation, Inc.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.
+   
+   Contributed by Cygnus Support.  */
+
+#define N_W_VARIABLES 8
+#define Module_Beginning 0xe0
+
+typedef struct ieee_module
+  {
+    char *processor;
+    char *module_name;
+  }
+ieee_module_begin_type;
+
+#define Address_Descriptor 0xec
+typedef struct ieee_address
+  {
+    bfd_vma number_of_bits_mau;
+    bfd_vma number_of_maus_in_address;
+
+    unsigned char byte_order;
+#define IEEE_LITTLE 0xcc
+#define IEEE_BIG 0xcd
+  }
+ieee_address_descriptor_type;
+
+typedef union ieee_w_variable
+  {
+    file_ptr offset[N_W_VARIABLES];
+
+    struct
+      {
+	file_ptr extension_record;
+	file_ptr environmental_record;
+	file_ptr section_part;
+	file_ptr external_part;
+	file_ptr debug_information_part;
+	file_ptr data_part;
+	file_ptr trailer_part;
+	file_ptr me_record;
+      }
+    r;
+  }
+ieee_w_variable_type;
+
+typedef enum ieee_record
+  { 
+    ieee_number_start_enum = 0x00,
+    ieee_number_end_enum=0x7f,
+    ieee_number_repeat_start_enum = 0x80,
+    ieee_number_repeat_end_enum = 0x88,
+    ieee_number_repeat_4_enum = 0x84,
+    ieee_number_repeat_3_enum = 0x83,
+    ieee_number_repeat_2_enum = 0x82,
+    ieee_number_repeat_1_enum = 0x81,
+    ieee_module_beginning_enum = 0xe0,
+    ieee_module_end_enum = 0xe1,
+    ieee_extension_length_1_enum = 0xde,
+    ieee_extension_length_2_enum = 0xdf,
+    ieee_section_type_enum = 0xe6,
+    ieee_section_alignment_enum = 0xe7,
+    ieee_external_symbol_enum = 0xe8,
+    ieee_comma = 0x90,
+    ieee_external_reference_enum = 0xe9,
+    ieee_set_current_section_enum = 0xe5,
+    ieee_address_descriptor_enum = 0xec,
+    ieee_load_constant_bytes_enum = 0xed,
+    ieee_load_with_relocation_enum = 0xe4,
+
+    ieee_variable_A_enum = 0xc1,
+    ieee_variable_B_enum = 0xc2,
+    ieee_variable_C_enum = 0xc3,
+    ieee_variable_D_enum = 0xc4,
+    ieee_variable_E_enum = 0xc5,
+    ieee_variable_F_enum = 0xc6,
+    ieee_variable_G_enum = 0xc7,
+    ieee_variable_H_enum = 0xc8,
+    ieee_variable_I_enum = 0xc9,
+    ieee_variable_J_enum = 0xca,
+    ieee_variable_K_enum = 0xcb,
+    ieee_variable_L_enum = 0xcc,
+    ieee_variable_M_enum = 0xcd,
+    ieee_variable_N_enum = 0xce,
+    ieee_variable_O_enum = 0xcf,
+    ieee_variable_P_enum = 0xd0,
+    ieee_variable_Q_enum = 0xd1,
+    ieee_variable_R_enum = 0xd2,
+    ieee_variable_S_enum = 0xd3,
+    ieee_variable_T_enum = 0xd4,
+    ieee_variable_U_enum = 0xd5,
+    ieee_variable_V_enum = 0xd6,
+    ieee_variable_W_enum = 0xd7,
+    ieee_variable_X_enum = 0xd8,
+    ieee_variable_Y_enum = 0xd9,
+    ieee_variable_Z_enum = 0xda,
+    ieee_function_plus_enum = 0xa5,
+    ieee_function_minus_enum = 0xa6,
+    ieee_function_signed_open_b_enum = 0xba,
+    ieee_function_signed_close_b_enum = 0xbb,
+
+    ieee_function_unsigned_open_b_enum = 0xbc,
+    ieee_function_unsigned_close_b_enum = 0xbd,
+
+    ieee_function_either_open_b_enum = 0xbe,
+    ieee_function_either_close_b_enum = 0xbf,
+    ieee_record_seperator_enum = 0xdb,
+
+    ieee_e2_first_byte_enum = 0xe2,
+    ieee_section_size_enum = 0xe2d3,
+    ieee_physical_region_size_enum = 0xe2c1,
+    ieee_region_base_address_enum = 0xe2c2,
+    ieee_mau_size_enum = 0xe2c6,
+    ieee_m_value_enum = 0xe2cd,
+    ieee_section_base_address_enum = 0xe2cc,
+    ieee_asn_record_enum = 0xe2ce,
+    ieee_section_offset_enum = 0xe2d2,
+    ieee_value_starting_address_enum = 0xe2c7,
+    ieee_assign_value_to_variable_enum = 0xe2d7,
+    ieee_set_current_pc_enum = 0xe2d0,
+    ieee_value_record_enum = 0xe2c9,
+    ieee_nn_record = 0xf0,
+    ieee_at_record_enum = 0xf1,
+    ieee_ty_record_enum = 0xf2,
+    ieee_attribute_record_enum = 0xf1c9,
+    ieee_atn_record_enum = 0xf1ce,
+    ieee_external_reference_info_record_enum = 0xf1d8,
+    ieee_weak_external_reference_enum= 0xf4,
+    ieee_repeat_data_enum = 0xf7,
+    ieee_bb_record_enum = 0xf8,
+    ieee_be_record_enum = 0xf9
+  }
+ieee_record_enum_type;
+
+typedef struct ieee_section
+  {
+    unsigned int section_index;
+    unsigned int section_type;
+    char *       section_name;
+    unsigned int parent_section_index;
+    unsigned int sibling_section_index;
+    unsigned int context_index;
+  }
+ieee_section_type;
+
+#define IEEE_REFERENCE_BASE 11
+#define IEEE_PUBLIC_BASE 32
+#define IEEE_SECTION_NUMBER_BASE 1
+
diff --git a/binutils-2.25/include/leb128.h b/binutils-2.25/include/leb128.h
new file mode 100644
index 00000000..f584f72e
--- /dev/null
+++ b/binutils-2.25/include/leb128.h
@@ -0,0 +1,136 @@
+/* Utilities for reading leb128 values.
+   Copyright (C) 2012 Free Software Foundation, Inc.
+
+This file is part of the libiberty library.
+Libiberty is free software; you can redistribute it and/or
+modify it under the terms of the GNU Library General Public
+License as published by the Free Software Foundation; either
+version 2 of the License, or (at your option) any later version.
+
+Libiberty is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+Library General Public License for more details.
+
+You should have received a copy of the GNU Library General Public
+License along with libiberty; see the file COPYING.LIB.  If not, write
+to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+/* The functions defined here can be speed critical.
+   Since they are all pretty small we keep things simple and just define
+   them all as "static inline".
+
+   WARNING: This file is used by GDB which is stuck at C90. :-(
+   Though it can use stdint.h, inttypes.h.
+   Therefore if you want to add support for "long long" you need
+   to wrap it in #ifdef CC_HAS_LONG_LONG.  */
+
+#ifndef LEB128_H
+#define LEB128_H
+
+/* Get a definition for inline.  */
+#include "ansidecl.h"
+
+/* Get a definition for NULL, size_t.  */
+#include <stddef.h>
+
+#ifdef HAVE_STDINT_H
+#include <stdint.h>
+#endif
+#ifdef HAVE_INTTYPES_H
+#include <inttypes.h>
+#endif
+
+/* Decode the unsigned LEB128 constant at BUF into the variable pointed to
+   by R, and return the number of bytes read.
+   If we read off the end of the buffer, zero is returned,
+   and nothing is stored in R.
+
+   Note: The result is an int instead of a pointer to the next byte to be
+   read to avoid const-vs-non-const problems.  */
+
+static inline size_t
+read_uleb128_to_uint64 (const unsigned char *buf, const unsigned char *buf_end,
+			uint64_t *r)
+{
+  const unsigned char *p = buf;
+  unsigned int shift = 0;
+  uint64_t result = 0;
+  unsigned char byte;
+
+  while (1)
+    {
+      if (p >= buf_end)
+	return 0;
+
+      byte = *p++;
+      result |= ((uint64_t) (byte & 0x7f)) << shift;
+      if ((byte & 0x80) == 0)
+	break;
+      shift += 7;
+    }
+
+  *r = result;
+  return p - buf;
+}
+
+/* Decode the signed LEB128 constant at BUF into the variable pointed to
+   by R, and return the number of bytes read.
+   If we read off the end of the buffer, zero is returned,
+   and nothing is stored in R.
+
+   Note: The result is an int instead of a pointer to the next byte to be
+   read to avoid const-vs-non-const problems.  */
+
+static inline size_t
+read_sleb128_to_int64 (const unsigned char *buf, const unsigned char *buf_end,
+		       int64_t *r)
+{
+  const unsigned char *p = buf;
+  unsigned int shift = 0;
+  int64_t result = 0;
+  unsigned char byte;
+
+  while (1)
+    {
+      if (p >= buf_end)
+	return 0;
+
+      byte = *p++;
+      result |= ((uint64_t) (byte & 0x7f)) << shift;
+      shift += 7;
+      if ((byte & 0x80) == 0)
+	break;
+    }
+  if (shift < (sizeof (*r) * 8) && (byte & 0x40) != 0)
+    result |= -(((uint64_t) 1) << shift);
+
+  *r = result;
+  return p - buf;
+}
+
+/* Return the number of bytes to read to skip past an LEB128 number in BUF.
+   If the end isn't found before reaching BUF_END, return zero.
+
+   Note: The result is an int instead of a pointer to the next byte to be
+   read to avoid const-vs-non-const problems.  */
+
+static inline size_t
+skip_leb128 (const unsigned char *buf, const unsigned char *buf_end)
+{
+  const unsigned char *p = buf;
+  unsigned char byte;
+
+  while (1)
+    {
+      if (p == buf_end)
+	return 0;
+
+      byte = *p++;
+      if ((byte & 0x80) == 0)
+	return p - buf;
+    }
+}
+
+#endif /* LEB128_H */
diff --git a/binutils-2.25/include/libiberty.h b/binutils-2.25/include/libiberty.h
new file mode 100644
index 00000000..78c42eb8
--- /dev/null
+++ b/binutils-2.25/include/libiberty.h
@@ -0,0 +1,686 @@
+/* Function declarations for libiberty.
+
+   Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
+   2006, 2007, 2008, 2009, 2010, 2011, 2013 Free Software Foundation, Inc.
+   
+   Note - certain prototypes declared in this header file are for
+   functions whoes implementation copyright does not belong to the
+   FSF.  Those prototypes are present in this file for reference
+   purposes only and their presence in this file should not construed
+   as an indication of ownership by the FSF of the implementation of
+   those functions in any way or form whatsoever.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.
+   
+   Written by Cygnus Support, 1994.
+
+   The libiberty library provides a number of functions which are
+   missing on some operating systems.  We do not declare those here,
+   to avoid conflicts with the system header files on operating
+   systems that do support those functions.  In this file we only
+   declare those functions which are specific to libiberty.  */
+
+#ifndef LIBIBERTY_H
+#define LIBIBERTY_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ansidecl.h"
+
+/* Get a definition for size_t.  */
+#include <stddef.h>
+/* Get a definition for va_list.  */
+#include <stdarg.h>
+
+#include <stdio.h>
+
+/* If the OS supports it, ensure that the supplied stream is setup to
+   avoid any multi-threaded locking.  Otherwise leave the FILE pointer
+   unchanged.  If the stream is NULL do nothing.  */
+
+extern void unlock_stream (FILE *);
+
+/* If the OS supports it, ensure that the standard I/O streams, stdin,
+   stdout and stderr are setup to avoid any multi-threaded locking.
+   Otherwise do nothing.  */
+
+extern void unlock_std_streams (void);
+
+/* Open and return a FILE pointer.  If the OS supports it, ensure that
+   the stream is setup to avoid any multi-threaded locking.  Otherwise
+   return the FILE pointer unchanged.  */
+
+extern FILE *fopen_unlocked (const char *, const char *);
+extern FILE *fdopen_unlocked (int, const char *);
+extern FILE *freopen_unlocked (const char *, const char *, FILE *);
+
+/* Build an argument vector from a string.  Allocates memory using
+   malloc.  Use freeargv to free the vector.  */
+
+extern char **buildargv (const char *) ATTRIBUTE_MALLOC;
+
+/* Free a vector returned by buildargv.  */
+
+extern void freeargv (char **);
+
+/* Duplicate an argument vector. Allocates memory using malloc.  Use
+   freeargv to free the vector.  */
+
+extern char **dupargv (char **) ATTRIBUTE_MALLOC;
+
+/* Expand "@file" arguments in argv.  */
+
+extern void expandargv (int *, char ***);
+
+/* Write argv to an @-file, inserting necessary quoting.  */
+
+extern int writeargv (char **, FILE *);
+
+/* Return the number of elements in argv.  */
+
+extern int countargv (char**);
+
+/* Return the last component of a path name.  Note that we can't use a
+   prototype here because the parameter is declared inconsistently
+   across different systems, sometimes as "char *" and sometimes as
+   "const char *" */
+
+/* HAVE_DECL_* is a three-state macro: undefined, 0 or 1.  If it is
+   undefined, we haven't run the autoconf check so provide the
+   declaration without arguments.  If it is 0, we checked and failed
+   to find the declaration so provide a fully prototyped one.  If it
+   is 1, we found it so don't provide any declaration at all.  */
+#if !HAVE_DECL_BASENAME
+#if defined (__GNU_LIBRARY__ ) || defined (__linux__) || defined (__FreeBSD__) || defined (__OpenBSD__) || defined(__NetBSD__) || defined (__CYGWIN__) || defined (__CYGWIN32__) || defined (__MINGW32__) || defined (HAVE_DECL_BASENAME)
+extern char *basename (const char *) ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_NONNULL(1);
+#else
+/* Do not allow basename to be used if there is no prototype seen.  We
+   either need to use the above prototype or have one from
+   autoconf which would result in HAVE_DECL_BASENAME being set.  */
+#define basename basename_cannot_be_used_without_a_prototype
+#endif
+#endif
+
+/* A well-defined basename () that is always compiled in.  */
+
+extern const char *lbasename (const char *) ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_NONNULL(1);
+
+/* Same, but assumes DOS semantics (drive name, backslash is also a
+   dir separator) regardless of host.  */
+
+extern const char *dos_lbasename (const char *) ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_NONNULL(1);
+
+/* Same, but assumes Unix semantics (absolute paths always start with
+   a slash, only forward slash is accepted as dir separator)
+   regardless of host.  */
+
+extern const char *unix_lbasename (const char *) ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_NONNULL(1);
+
+/* A well-defined realpath () that is always compiled in.  */
+
+extern char *lrealpath (const char *);
+
+/* Concatenate an arbitrary number of strings.  You must pass NULL as
+   the last argument of this function, to terminate the list of
+   strings.  Allocates memory using xmalloc.  */
+
+extern char *concat (const char *, ...) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_SENTINEL;
+
+/* Concatenate an arbitrary number of strings.  You must pass NULL as
+   the last argument of this function, to terminate the list of
+   strings.  Allocates memory using xmalloc.  The first argument is
+   not one of the strings to be concatenated, but if not NULL is a
+   pointer to be freed after the new string is created, similar to the
+   way xrealloc works.  */
+
+extern char *reconcat (char *, const char *, ...) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_SENTINEL;
+
+/* Determine the length of concatenating an arbitrary number of
+   strings.  You must pass NULL as the last argument of this function,
+   to terminate the list of strings.  */
+
+extern unsigned long concat_length (const char *, ...) ATTRIBUTE_SENTINEL;
+
+/* Concatenate an arbitrary number of strings into a SUPPLIED area of
+   memory.  You must pass NULL as the last argument of this function,
+   to terminate the list of strings.  The supplied memory is assumed
+   to be large enough.  */
+
+extern char *concat_copy (char *, const char *, ...) ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_NONNULL(1) ATTRIBUTE_SENTINEL;
+
+/* Concatenate an arbitrary number of strings into a GLOBAL area of
+   memory.  You must pass NULL as the last argument of this function,
+   to terminate the list of strings.  The supplied memory is assumed
+   to be large enough.  */
+
+extern char *concat_copy2 (const char *, ...) ATTRIBUTE_RETURNS_NONNULL ATTRIBUTE_SENTINEL;
+
+/* This is the global area used by concat_copy2.  */
+
+extern char *libiberty_concat_ptr;
+
+/* Concatenate an arbitrary number of strings.  You must pass NULL as
+   the last argument of this function, to terminate the list of
+   strings.  Allocates memory using alloca.  The arguments are
+   evaluated twice!  */
+#define ACONCAT(ACONCAT_PARAMS) \
+  (libiberty_concat_ptr = (char *) alloca (concat_length ACONCAT_PARAMS + 1), \
+   concat_copy2 ACONCAT_PARAMS)
+
+/* Check whether two file descriptors refer to the same file.  */
+
+extern int fdmatch (int fd1, int fd2);
+
+/* Return the position of the first bit set in the argument.  */
+/* Prototypes vary from system to system, so we only provide a
+   prototype on systems where we know that we need it.  */
+#if defined (HAVE_DECL_FFS) && !HAVE_DECL_FFS
+extern int ffs(int);
+#endif
+
+/* Get the working directory.  The result is cached, so don't call
+   chdir() between calls to getpwd().  */
+
+extern char * getpwd (void);
+
+/* Get the current time.  */
+/* Prototypes vary from system to system, so we only provide a
+   prototype on systems where we know that we need it.  */
+#ifdef __MINGW32__
+/* Forward declaration to avoid #include <sys/time.h>.   */
+struct timeval;
+extern int gettimeofday (struct timeval *, void *); 
+#endif
+
+/* Get the amount of time the process has run, in microseconds.  */
+
+extern long get_run_time (void);
+
+/* Generate a relocated path to some installation directory.  Allocates
+   return value using malloc.  */
+
+extern char *make_relative_prefix (const char *, const char *,
+                                   const char *) ATTRIBUTE_MALLOC;
+
+/* Generate a relocated path to some installation directory without
+   attempting to follow any soft links.  Allocates
+   return value using malloc.  */
+
+extern char *make_relative_prefix_ignore_links (const char *, const char *,
+						const char *) ATTRIBUTE_MALLOC;
+
+/* Choose a temporary directory to use for scratch files.  */
+
+extern char *choose_temp_base (void) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL;
+
+/* Return a temporary file name or NULL if unable to create one.  */
+
+extern char *make_temp_file (const char *) ATTRIBUTE_MALLOC;
+
+/* Remove a link to a file unless it is special. */
+
+extern int unlink_if_ordinary (const char *);
+
+/* Allocate memory filled with spaces.  Allocates using malloc.  */
+
+extern const char *spaces (int count);
+
+/* Return the maximum error number for which strerror will return a
+   string.  */
+
+extern int errno_max (void);
+
+/* Return the name of an errno value (e.g., strerrno (EINVAL) returns
+   "EINVAL").  */
+
+extern const char *strerrno (int);
+
+/* Given the name of an errno value, return the value.  */
+
+extern int strtoerrno (const char *);
+
+/* ANSI's strerror(), but more robust.  */
+
+extern char *xstrerror (int) ATTRIBUTE_RETURNS_NONNULL;
+
+/* Return the maximum signal number for which strsignal will return a
+   string.  */
+
+extern int signo_max (void);
+
+/* Return a signal message string for a signal number
+   (e.g., strsignal (SIGHUP) returns something like "Hangup").  */
+/* This is commented out as it can conflict with one in system headers.
+   We still document its existence though.  */
+
+/*extern const char *strsignal (int);*/
+
+/* Return the name of a signal number (e.g., strsigno (SIGHUP) returns
+   "SIGHUP").  */
+
+extern const char *strsigno (int);
+
+/* Given the name of a signal, return its number.  */
+
+extern int strtosigno (const char *);
+
+/* Register a function to be run by xexit.  Returns 0 on success.  */
+
+extern int xatexit (void (*fn) (void));
+
+/* Exit, calling all the functions registered with xatexit.  */
+
+extern void xexit (int status) ATTRIBUTE_NORETURN;
+
+/* Set the program name used by xmalloc.  */
+
+extern void xmalloc_set_program_name (const char *);
+
+/* Report an allocation failure.  */
+extern void xmalloc_failed (size_t) ATTRIBUTE_NORETURN;
+
+/* Allocate memory without fail.  If malloc fails, this will print a
+   message to stderr (using the name set by xmalloc_set_program_name,
+   if any) and then call xexit.  */
+
+extern void *xmalloc (size_t) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL;
+
+/* Reallocate memory without fail.  This works like xmalloc.  Note,
+   realloc type functions are not suitable for attribute malloc since
+   they may return the same address across multiple calls. */
+
+extern void *xrealloc (void *, size_t) ATTRIBUTE_RETURNS_NONNULL;
+
+/* Allocate memory without fail and set it to zero.  This works like
+   xmalloc.  */
+
+extern void *xcalloc (size_t, size_t) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL;
+
+/* Copy a string into a memory buffer without fail.  */
+
+extern char *xstrdup (const char *) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL;
+
+/* Copy at most N characters from string into a buffer without fail.  */
+
+extern char *xstrndup (const char *, size_t) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL;
+
+/* Copy an existing memory buffer to a new memory buffer without fail.  */
+
+extern void *xmemdup (const void *, size_t, size_t) ATTRIBUTE_MALLOC ATTRIBUTE_RETURNS_NONNULL;
+
+/* Physical memory routines.  Return values are in BYTES.  */
+extern double physmem_total (void);
+extern double physmem_available (void);
+
+/* Compute the 32-bit CRC of a block of memory.  */
+extern unsigned int xcrc32 (const unsigned char *, int, unsigned int);
+
+/* These macros provide a K&R/C89/C++-friendly way of allocating structures
+   with nice encapsulation.  The XDELETE*() macros are technically
+   superfluous, but provided here for symmetry.  Using them consistently
+   makes it easier to update client code to use different allocators such
+   as new/delete and new[]/delete[].  */
+
+/* Scalar allocators.  */
+
+#define XALLOCA(T)		((T *) alloca (sizeof (T)))
+#define XNEW(T)			((T *) xmalloc (sizeof (T)))
+#define XCNEW(T)		((T *) xcalloc (1, sizeof (T)))
+#define XDUP(T, P)		((T *) xmemdup ((P), sizeof (T), sizeof (T)))
+#define XDELETE(P)		free ((void*) (P))
+
+/* Array allocators.  */
+
+#define XALLOCAVEC(T, N)	((T *) alloca (sizeof (T) * (N)))
+#define XNEWVEC(T, N)		((T *) xmalloc (sizeof (T) * (N)))
+#define XCNEWVEC(T, N)		((T *) xcalloc ((N), sizeof (T)))
+#define XDUPVEC(T, P, N)	((T *) xmemdup ((P), sizeof (T) * (N), sizeof (T) * (N)))
+#define XRESIZEVEC(T, P, N)	((T *) xrealloc ((void *) (P), sizeof (T) * (N)))
+#define XDELETEVEC(P)		free ((void*) (P))
+
+/* Allocators for variable-sized structures and raw buffers.  */
+
+#define XALLOCAVAR(T, S)	((T *) alloca ((S)))
+#define XNEWVAR(T, S)		((T *) xmalloc ((S)))
+#define XCNEWVAR(T, S)		((T *) xcalloc (1, (S)))
+#define XDUPVAR(T, P, S1, S2)	((T *) xmemdup ((P), (S1), (S2)))
+#define XRESIZEVAR(T, P, S)	((T *) xrealloc ((P), (S)))
+
+/* Type-safe obstack allocator.  */
+
+#define XOBNEW(O, T)		((T *) obstack_alloc ((O), sizeof (T)))
+#define XOBNEWVEC(O, T, N)	((T *) obstack_alloc ((O), sizeof (T) * (N)))
+#define XOBNEWVAR(O, T, S)	((T *) obstack_alloc ((O), (S)))
+#define XOBFINISH(O, T)         ((T) obstack_finish ((O)))
+
+/* hex character manipulation routines */
+
+#define _hex_array_size 256
+#define _hex_bad	99
+extern const unsigned char _hex_value[_hex_array_size];
+extern void hex_init (void);
+#define hex_p(c)	(hex_value (c) != _hex_bad)
+/* If you change this, note well: Some code relies on side effects in
+   the argument being performed exactly once.  */
+#define hex_value(c)	((unsigned int) _hex_value[(unsigned char) (c)])
+
+/* Flags for pex_init.  These are bits to be or'ed together.  */
+
+/* Record subprocess times, if possible.  */
+#define PEX_RECORD_TIMES	0x1
+
+/* Use pipes for communication between processes, if possible.  */
+#define PEX_USE_PIPES		0x2
+
+/* Save files used for communication between processes.  */
+#define PEX_SAVE_TEMPS		0x4
+
+/* Prepare to execute one or more programs, with standard output of
+   each program fed to standard input of the next.
+   FLAGS	As above.
+   PNAME	The name of the program to report in error messages.
+   TEMPBASE	A base name to use for temporary files; may be NULL to
+   		use a random name.
+   Returns NULL on error.  */
+
+extern struct pex_obj *pex_init (int flags, const char *pname,
+				 const char *tempbase) ATTRIBUTE_RETURNS_NONNULL;
+
+/* Flags for pex_run.  These are bits to be or'ed together.  */
+
+/* Last program in pipeline.  Standard output of program goes to
+   OUTNAME, or, if OUTNAME is NULL, to standard output of caller.  Do
+   not set this if you want to call pex_read_output.  After this is
+   set, pex_run may no longer be called with the same struct
+   pex_obj.  */
+#define PEX_LAST		0x1
+
+/* Search for program in executable search path.  */
+#define PEX_SEARCH		0x2
+
+/* OUTNAME is a suffix.  */
+#define PEX_SUFFIX		0x4
+
+/* Send program's standard error to standard output.  */
+#define PEX_STDERR_TO_STDOUT	0x8
+
+/* Input file should be opened in binary mode.  This flag is ignored
+   on Unix.  */
+#define PEX_BINARY_INPUT	0x10
+
+/* Output file should be opened in binary mode.  This flag is ignored
+   on Unix.  For proper behaviour PEX_BINARY_INPUT and
+   PEX_BINARY_OUTPUT have to match appropriately--i.e., a call using
+   PEX_BINARY_OUTPUT should be followed by a call using
+   PEX_BINARY_INPUT.  */
+#define PEX_BINARY_OUTPUT	0x20
+
+/* Capture stderr to a pipe.  The output can be read by
+   calling pex_read_err and reading from the returned
+   FILE object.  This flag may be specified only for
+   the last program in a pipeline.  
+
+   This flag is supported only on Unix and Windows.  */
+#define PEX_STDERR_TO_PIPE	0x40
+
+/* Capture stderr in binary mode.  This flag is ignored
+   on Unix.  */
+#define PEX_BINARY_ERROR	0x80
+
+
+/* Execute one program.  Returns NULL on success.  On error returns an
+   error string (typically just the name of a system call); the error
+   string is statically allocated.
+
+   OBJ		Returned by pex_init.
+
+   FLAGS	As above.
+
+   EXECUTABLE	The program to execute.
+
+   ARGV		NULL terminated array of arguments to pass to the program.
+
+   OUTNAME	Sets the output file name as follows:
+
+		PEX_SUFFIX set (OUTNAME may not be NULL):
+		  TEMPBASE parameter to pex_init not NULL:
+		    Output file name is the concatenation of TEMPBASE
+		    and OUTNAME.
+		  TEMPBASE is NULL:
+		    Output file name is a random file name ending in
+		    OUTNAME.
+		PEX_SUFFIX not set:
+		  OUTNAME not NULL:
+		    Output file name is OUTNAME.
+		  OUTNAME NULL, TEMPBASE not NULL:
+		    Output file name is randomly chosen using
+		    TEMPBASE.
+		  OUTNAME NULL, TEMPBASE NULL:
+		    Output file name is randomly chosen.
+
+		If PEX_LAST is not set, the output file name is the
+   		name to use for a temporary file holding stdout, if
+   		any (there will not be a file if PEX_USE_PIPES is set
+   		and the system supports pipes).  If a file is used, it
+   		will be removed when no longer needed unless
+   		PEX_SAVE_TEMPS is set.
+
+		If PEX_LAST is set, and OUTNAME is not NULL, standard
+   		output is written to the output file name.  The file
+   		will not be removed.  If PEX_LAST and PEX_SUFFIX are
+   		both set, TEMPBASE may not be NULL.
+
+   ERRNAME	If not NULL, this is the name of a file to which
+		standard error is written.  If NULL, standard error of
+		the program is standard error of the caller.
+
+   ERR		On an error return, *ERR is set to an errno value, or
+   		to 0 if there is no relevant errno.
+*/
+
+extern const char *pex_run (struct pex_obj *obj, int flags,
+			    const char *executable, char * const *argv,
+			    const char *outname, const char *errname,
+			    int *err);
+
+/* As for pex_run (), but takes an extra parameter to enable the
+   environment for the child process to be specified.
+
+   ENV		The environment for the child process, specified as
+		an array of character pointers.  Each element of the
+		array should point to a string of the form VAR=VALUE,
+                with the exception of the last element which must be
+                a null pointer.
+*/
+
+extern const char *pex_run_in_environment (struct pex_obj *obj, int flags,
+			                   const char *executable,
+                                           char * const *argv,
+                                           char * const *env,
+              	          		   const char *outname,
+					   const char *errname, int *err);
+
+/* Return a stream for a temporary file to pass to the first program
+   in the pipeline as input.  The file name is chosen as for pex_run.
+   pex_run closes the file automatically; don't close it yourself.  */
+
+extern FILE *pex_input_file (struct pex_obj *obj, int flags,
+                             const char *in_name);
+
+/* Return a stream for a pipe connected to the standard input of the
+   first program in the pipeline.  You must have passed
+   `PEX_USE_PIPES' to `pex_init'.  Close the returned stream
+   yourself.  */
+
+extern FILE *pex_input_pipe (struct pex_obj *obj, int binary);
+
+/* Read the standard output of the last program to be executed.
+   pex_run can not be called after this.  BINARY should be non-zero if
+   the file should be opened in binary mode; this is ignored on Unix.
+   Returns NULL on error.  Don't call fclose on the returned FILE; it
+   will be closed by pex_free.  */
+
+extern FILE *pex_read_output (struct pex_obj *, int binary);
+
+/* Read the standard error of the last program to be executed.
+   pex_run can not be called after this.  BINARY should be non-zero if
+   the file should be opened in binary mode; this is ignored on Unix.
+   Returns NULL on error.  Don't call fclose on the returned FILE; it
+   will be closed by pex_free.  */
+
+extern FILE *pex_read_err (struct pex_obj *, int binary);
+
+/* Return exit status of all programs in VECTOR.  COUNT indicates the
+   size of VECTOR.  The status codes in the vector are in the order of
+   the calls to pex_run.  Returns 0 on error, 1 on success.  */
+
+extern int pex_get_status (struct pex_obj *, int count, int *vector);
+
+/* Return times of all programs in VECTOR.  COUNT indicates the size
+   of VECTOR.  struct pex_time is really just struct timeval, but that
+   is not portable to all systems.  Returns 0 on error, 1 on
+   success.  */
+
+struct pex_time
+{
+  unsigned long user_seconds;
+  unsigned long user_microseconds;
+  unsigned long system_seconds;
+  unsigned long system_microseconds;
+};
+
+extern int pex_get_times (struct pex_obj *, int count,
+			  struct pex_time *vector);
+
+/* Clean up a pex_obj.  If you have not called pex_get_times or
+   pex_get_status, this will try to kill the subprocesses.  */
+
+extern void pex_free (struct pex_obj *);
+
+/* Just execute one program.  Return value is as for pex_run.
+   FLAGS	Combination of PEX_SEARCH and PEX_STDERR_TO_STDOUT.
+   EXECUTABLE	As for pex_run.
+   ARGV		As for pex_run.
+   PNAME	As for pex_init.
+   OUTNAME	As for pex_run when PEX_LAST is set.
+   ERRNAME	As for pex_run.
+   STATUS	Set to exit status on success.
+   ERR		As for pex_run.
+*/
+
+extern const char *pex_one (int flags, const char *executable,
+			    char * const *argv, const char *pname,
+			    const char *outname, const char *errname,
+			    int *status, int *err);
+
+/* pexecute and pwait are the old pexecute interface, still here for
+   backward compatibility.  Don't use these for new code.  Instead,
+   use pex_init/pex_run/pex_get_status/pex_free, or pex_one.  */
+
+/* Definitions used by the pexecute routine.  */
+
+#define PEXECUTE_FIRST   1
+#define PEXECUTE_LAST    2
+#define PEXECUTE_ONE     (PEXECUTE_FIRST + PEXECUTE_LAST)
+#define PEXECUTE_SEARCH  4
+#define PEXECUTE_VERBOSE 8
+
+/* Execute a program.  */
+
+extern int pexecute (const char *, char * const *, const char *,
+                     const char *, char **, char **, int);
+
+/* Wait for pexecute to finish.  */
+
+extern int pwait (int, int *, int);
+
+#if !HAVE_DECL_ASPRINTF
+/* Like sprintf but provides a pointer to malloc'd storage, which must
+   be freed by the caller.  */
+
+extern int asprintf (char **, const char *, ...) ATTRIBUTE_PRINTF_2;
+#endif
+
+#if !HAVE_DECL_VASPRINTF
+/* Like vsprintf but provides a pointer to malloc'd storage, which
+   must be freed by the caller.  */
+
+extern int vasprintf (char **, const char *, va_list) ATTRIBUTE_PRINTF(2,0);
+#endif
+
+#if defined(HAVE_DECL_SNPRINTF) && !HAVE_DECL_SNPRINTF
+/* Like sprintf but prints at most N characters.  */
+extern int snprintf (char *, size_t, const char *, ...) ATTRIBUTE_PRINTF_3;
+#endif
+
+#if defined(HAVE_DECL_VSNPRINTF) && !HAVE_DECL_VSNPRINTF
+/* Like vsprintf but prints at most N characters.  */
+extern int vsnprintf (char *, size_t, const char *, va_list) ATTRIBUTE_PRINTF(3,0);
+#endif
+
+#if defined(HAVE_DECL_STRVERSCMP) && !HAVE_DECL_STRVERSCMP
+/* Compare version strings.  */
+extern int strverscmp (const char *, const char *);
+#endif
+
+/* Set the title of a process */
+extern void setproctitle (const char *name, ...);
+
+/* Increase stack limit if possible.  */
+extern void stack_limit_increase (unsigned long);
+
+#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
+
+/* Drastically simplified alloca configurator.  If we're using GCC,
+   we use __builtin_alloca; otherwise we use the C alloca.  The C
+   alloca is always available.  You can override GCC by defining
+   USE_C_ALLOCA yourself.  The canonical autoconf macro C_ALLOCA is
+   also set/unset as it is often used to indicate whether code needs
+   to call alloca(0).  */
+extern void *C_alloca (size_t) ATTRIBUTE_MALLOC;
+#undef alloca
+#if GCC_VERSION >= 2000 && !defined USE_C_ALLOCA
+# define alloca(x) __builtin_alloca(x)
+# undef C_ALLOCA
+# define ASTRDUP(X) \
+  (__extension__ ({ const char *const libiberty_optr = (X); \
+   const unsigned long libiberty_len = strlen (libiberty_optr) + 1; \
+   char *const libiberty_nptr = (char *const) alloca (libiberty_len); \
+   (char *) memcpy (libiberty_nptr, libiberty_optr, libiberty_len); }))
+#else
+# define alloca(x) C_alloca(x)
+# undef USE_C_ALLOCA
+# define USE_C_ALLOCA 1
+# undef C_ALLOCA
+# define C_ALLOCA 1
+extern const char *libiberty_optr;
+extern char *libiberty_nptr;
+extern unsigned long libiberty_len;
+# define ASTRDUP(X) \
+  (libiberty_optr = (X), \
+   libiberty_len = strlen (libiberty_optr) + 1, \
+   libiberty_nptr = (char *) alloca (libiberty_len), \
+   (char *) memcpy (libiberty_nptr, libiberty_optr, libiberty_len))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ! defined (LIBIBERTY_H) */
diff --git a/binutils-2.25/include/longlong.h b/binutils-2.25/include/longlong.h
new file mode 100644
index 00000000..5f00e548
--- /dev/null
+++ b/binutils-2.25/include/longlong.h
@@ -0,0 +1,1724 @@
+/* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
+   Copyright (C) 1991-2013 Free Software Foundation, Inc.
+
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   In addition to the permissions in the GNU Lesser General Public
+   License, the Free Software Foundation gives you unlimited
+   permission to link the compiled version of this file into
+   combinations with other programs, and to distribute those
+   combinations without any restriction coming from the use of this
+   file.  (The Lesser General Public License restrictions do apply in
+   other respects; for example, they cover modification of the file,
+   and distribution when not linked into a combine executable.)
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
+
+/* You have to define the following before including this file:
+
+   UWtype -- An unsigned type, default type for operations (typically a "word")
+   UHWtype -- An unsigned type, at least half the size of UWtype.
+   UDWtype -- An unsigned type, at least twice as large a UWtype
+   W_TYPE_SIZE -- size in bits of UWtype
+
+   UQItype -- Unsigned 8 bit type.
+   SItype, USItype -- Signed and unsigned 32 bit types.
+   DItype, UDItype -- Signed and unsigned 64 bit types.
+
+   On a 32 bit machine UWtype should typically be USItype;
+   on a 64 bit machine, UWtype should typically be UDItype.  */
+
+#define __BITS4 (W_TYPE_SIZE / 4)
+#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
+#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
+#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
+
+#ifndef W_TYPE_SIZE
+#define W_TYPE_SIZE	32
+#define UWtype		USItype
+#define UHWtype		USItype
+#define UDWtype		UDItype
+#endif
+
+/* Used in glibc only.  */
+#ifndef attribute_hidden
+#define attribute_hidden
+#endif
+
+extern const UQItype __clz_tab[256] attribute_hidden;
+
+/* Define auxiliary asm macros.
+
+   1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
+   UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
+   word product in HIGH_PROD and LOW_PROD.
+
+   2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
+   UDWtype product.  This is just a variant of umul_ppmm.
+
+   3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
+   denominator) divides a UDWtype, composed by the UWtype integers
+   HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
+   in QUOTIENT and the remainder in REMAINDER.  HIGH_NUMERATOR must be less
+   than DENOMINATOR for correct operation.  If, in addition, the most
+   significant bit of DENOMINATOR must be 1, then the pre-processor symbol
+   UDIV_NEEDS_NORMALIZATION is defined to 1.
+
+   4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
+   denominator).  Like udiv_qrnnd but the numbers are signed.  The quotient
+   is rounded towards 0.
+
+   5) count_leading_zeros(count, x) counts the number of zero-bits from the
+   msb to the first nonzero bit in the UWtype X.  This is the number of
+   steps X needs to be shifted left to set the msb.  Undefined for X == 0,
+   unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
+
+   6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
+   from the least significant end.
+
+   7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
+   high_addend_2, low_addend_2) adds two UWtype integers, composed by
+   HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
+   respectively.  The result is placed in HIGH_SUM and LOW_SUM.  Overflow
+   (i.e. carry out) is not stored anywhere, and is lost.
+
+   8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
+   high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
+   composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
+   LOW_SUBTRAHEND_2 respectively.  The result is placed in HIGH_DIFFERENCE
+   and LOW_DIFFERENCE.  Overflow (i.e. carry out) is not stored anywhere,
+   and is lost.
+
+   If any of these macros are left undefined for a particular CPU,
+   C macros are used.  */
+
+/* The CPUs come in alphabetical order below.
+
+   Please add support for more CPUs here, or improve the current support
+   for the CPUs below!
+   (E.g. WE32100, IBM360.)  */
+
+#if defined (__GNUC__) && !defined (NO_ASM)
+
+/* We sometimes need to clobber "cc" with gcc2, but that would not be
+   understood by gcc1.  Use cpp to avoid major code duplication.  */
+#if __GNUC__ < 2
+#define __CLOBBER_CC
+#define __AND_CLOBBER_CC
+#else /* __GNUC__ >= 2 */
+#define __CLOBBER_CC : "cc"
+#define __AND_CLOBBER_CC , "cc"
+#endif /* __GNUC__ < 2 */
+
+#if defined (__alpha) && W_TYPE_SIZE == 64
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    UDItype __m0 = (m0), __m1 = (m1);					\
+    (ph) = __builtin_alpha_umulh (__m0, __m1);				\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define UMUL_TIME 46
+#ifndef LONGLONG_STANDALONE
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  do { UDItype __r;							\
+    (q) = __udiv_qrnnd (&__r, (n1), (n0), (d));				\
+    (r) = __r;								\
+  } while (0)
+extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
+#define UDIV_TIME 220
+#endif /* LONGLONG_STANDALONE */
+#ifdef __alpha_cix__
+#define count_leading_zeros(COUNT,X)	((COUNT) = __builtin_clzl (X))
+#define count_trailing_zeros(COUNT,X)	((COUNT) = __builtin_ctzl (X))
+#define COUNT_LEADING_ZEROS_0 64
+#else
+#define count_leading_zeros(COUNT,X) \
+  do {									\
+    UDItype __xr = (X), __t, __a;					\
+    __t = __builtin_alpha_cmpbge (0, __xr);				\
+    __a = __clz_tab[__t ^ 0xff] - 1;					\
+    __t = __builtin_alpha_extbl (__xr, __a);				\
+    (COUNT) = 64 - (__clz_tab[__t] + __a*8);				\
+  } while (0)
+#define count_trailing_zeros(COUNT,X) \
+  do {									\
+    UDItype __xr = (X), __t, __a;					\
+    __t = __builtin_alpha_cmpbge (0, __xr);				\
+    __t = ~__t & -~__t;							\
+    __a = ((__t & 0xCC) != 0) * 2;					\
+    __a += ((__t & 0xF0) != 0) * 4;					\
+    __a += ((__t & 0xAA) != 0);						\
+    __t = __builtin_alpha_extbl (__xr, __a);				\
+    __a <<= 3;								\
+    __t &= -__t;							\
+    __a += ((__t & 0xCC) != 0) * 2;					\
+    __a += ((__t & 0xF0) != 0) * 4;					\
+    __a += ((__t & 0xAA) != 0);						\
+    (COUNT) = __a;							\
+  } while (0)
+#endif /* __alpha_cix__ */
+#endif /* __alpha */
+
+#if defined (__arc__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%r" ((USItype) (ah)),					\
+	     "rIJ" ((USItype) (bh)),					\
+	     "%r" ((USItype) (al)),					\
+	     "rIJ" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "r" ((USItype) (ah)),					\
+	     "rIJ" ((USItype) (bh)),					\
+	     "r" ((USItype) (al)),					\
+	     "rIJ" ((USItype) (bl)))
+
+#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
+#ifdef __ARC_NORM__
+#define count_leading_zeros(count, x) \
+  do									\
+    {									\
+      SItype c_;							\
+									\
+      __asm__ ("norm.f\t%0,%1\n\tmov.mi\t%0,-1" : "=r" (c_) : "r" (x) : "cc");\
+      (count) = c_ + 1;							\
+    }									\
+  while (0)
+#define COUNT_LEADING_ZEROS_0 32
+#endif
+#endif
+
+#if defined (__arm__) && (defined (__thumb2__) || !defined (__thumb__)) \
+ && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%r" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "%r" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl)) __CLOBBER_CC)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "r" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "r" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl)) __CLOBBER_CC)
+# if defined(__ARM_ARCH_2__) || defined(__ARM_ARCH_2A__) \
+     || defined(__ARM_ARCH_3__)
+#  define umul_ppmm(xh, xl, a, b)					\
+  do {									\
+    register USItype __t0, __t1, __t2;					\
+    __asm__ ("%@ Inlined umul_ppmm\n"					\
+	   "	mov	%2, %5, lsr #16\n"				\
+	   "	mov	%0, %6, lsr #16\n"				\
+	   "	bic	%3, %5, %2, lsl #16\n"				\
+	   "	bic	%4, %6, %0, lsl #16\n"				\
+	   "	mul	%1, %3, %4\n"					\
+	   "	mul	%4, %2, %4\n"					\
+	   "	mul	%3, %0, %3\n"					\
+	   "	mul	%0, %2, %0\n"					\
+	   "	adds	%3, %4, %3\n"					\
+	   "	addcs	%0, %0, #65536\n"				\
+	   "	adds	%1, %1, %3, lsl #16\n"				\
+	   "	adc	%0, %0, %3, lsr #16"				\
+	   : "=&r" ((USItype) (xh)),					\
+	     "=r" ((USItype) (xl)),					\
+	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
+	   : "r" ((USItype) (a)),					\
+	     "r" ((USItype) (b)) __CLOBBER_CC );			\
+  } while (0)
+#  define UMUL_TIME 20
+# else
+#  define umul_ppmm(xh, xl, a, b)					\
+  do {									\
+    /* Generate umull, under compiler control.  */			\
+    register UDItype __t0 = (UDItype)(USItype)(a) * (USItype)(b);	\
+    (xl) = (USItype)__t0;						\
+    (xh) = (USItype)(__t0 >> 32);					\
+  } while (0)
+#  define UMUL_TIME 3
+# endif
+# define UDIV_TIME 100
+#endif /* __arm__ */
+
+#if defined(__arm__)
+/* Let gcc decide how best to implement count_leading_zeros.  */
+#define count_leading_zeros(COUNT,X)	((COUNT) = __builtin_clz (X))
+#define count_trailing_zeros(COUNT,X)   ((COUNT) = __builtin_ctz (X))
+#define COUNT_LEADING_ZEROS_0 32
+#endif
+
+#if defined (__AVR__)
+
+#if W_TYPE_SIZE == 16
+#define count_leading_zeros(COUNT,X)  ((COUNT) = __builtin_clz (X))
+#define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctz (X))
+#define COUNT_LEADING_ZEROS_0 16
+#endif /* W_TYPE_SIZE == 16 */
+
+#if W_TYPE_SIZE == 32
+#define count_leading_zeros(COUNT,X)  ((COUNT) = __builtin_clzl (X))
+#define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
+#define COUNT_LEADING_ZEROS_0 32
+#endif /* W_TYPE_SIZE == 32 */
+
+#if W_TYPE_SIZE == 64
+#define count_leading_zeros(COUNT,X)  ((COUNT) = __builtin_clzll (X))
+#define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzll (X))
+#define COUNT_LEADING_ZEROS_0 64
+#endif /* W_TYPE_SIZE == 64 */
+
+#endif /* defined (__AVR__) */
+
+#if defined (__CRIS__)
+
+#if __CRIS_arch_version >= 3
+#define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
+#define COUNT_LEADING_ZEROS_0 32
+#endif /* __CRIS_arch_version >= 3 */
+
+#if __CRIS_arch_version >= 8
+#define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
+#endif /* __CRIS_arch_version >= 8 */
+
+#if __CRIS_arch_version >= 10
+#define __umulsidi3(u,v) ((UDItype)(USItype) (u) * (UDItype)(USItype) (v))
+#else
+#define __umulsidi3 __umulsidi3
+extern UDItype __umulsidi3 (USItype, USItype);
+#endif /* __CRIS_arch_version >= 10 */
+
+#define umul_ppmm(w1, w0, u, v)		\
+  do {					\
+    UDItype __x = __umulsidi3 (u, v);	\
+    (w0) = (USItype) (__x);		\
+    (w1) = (USItype) (__x >> 32);	\
+  } while (0)
+
+/* FIXME: defining add_ssaaaa and sub_ddmmss should be advantageous for
+   DFmode ("double" intrinsics, avoiding two of the three insns handling
+   carry), but defining them as open-code C composing and doing the
+   operation in DImode (UDImode) shows that the DImode needs work:
+   register pressure from requiring neighboring registers and the
+   traffic to and from them come to dominate, in the 4.7 series.  */
+
+#endif /* defined (__CRIS__) */
+
+#if defined (__hppa) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%rM" ((USItype) (ah)),					\
+	     "rM" ((USItype) (bh)),					\
+	     "%rM" ((USItype) (al)),					\
+	     "rM" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "rM" ((USItype) (ah)),					\
+	     "rM" ((USItype) (bh)),					\
+	     "rM" ((USItype) (al)),					\
+	     "rM" ((USItype) (bl)))
+#if defined (_PA_RISC1_1)
+#define umul_ppmm(w1, w0, u, v) \
+  do {									\
+    union								\
+      {									\
+	UDItype __f;							\
+	struct {USItype __w1, __w0;} __w1w0;				\
+      } __t;								\
+    __asm__ ("xmpyu %1,%2,%0"						\
+	     : "=x" (__t.__f)						\
+	     : "x" ((USItype) (u)),					\
+	       "x" ((USItype) (v)));					\
+    (w1) = __t.__w1w0.__w1;						\
+    (w0) = __t.__w1w0.__w0;						\
+     } while (0)
+#define UMUL_TIME 8
+#else
+#define UMUL_TIME 30
+#endif
+#define UDIV_TIME 40
+#define count_leading_zeros(count, x) \
+  do {									\
+    USItype __tmp;							\
+    __asm__ (								\
+       "ldi		1,%0\n"						\
+"	extru,=		%1,15,16,%%r0		; Bits 31..16 zero?\n"	\
+"	extru,tr	%1,15,16,%1		; No.  Shift down, skip add.\n"\
+"	ldo		16(%0),%0		; Yes.  Perform add.\n"	\
+"	extru,=		%1,23,8,%%r0		; Bits 15..8 zero?\n"	\
+"	extru,tr	%1,23,8,%1		; No.  Shift down, skip add.\n"\
+"	ldo		8(%0),%0		; Yes.  Perform add.\n"	\
+"	extru,=		%1,27,4,%%r0		; Bits 7..4 zero?\n"	\
+"	extru,tr	%1,27,4,%1		; No.  Shift down, skip add.\n"\
+"	ldo		4(%0),%0		; Yes.  Perform add.\n"	\
+"	extru,=		%1,29,2,%%r0		; Bits 3..2 zero?\n"	\
+"	extru,tr	%1,29,2,%1		; No.  Shift down, skip add.\n"\
+"	ldo		2(%0),%0		; Yes.  Perform add.\n"	\
+"	extru		%1,30,1,%1		; Extract bit 1.\n"	\
+"	sub		%0,%1,%0		; Subtract it.\n"	\
+	: "=r" (count), "=r" (__tmp) : "1" (x));			\
+  } while (0)
+#endif
+
+#if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
+#if !defined (__zarch__)
+#define smul_ppmm(xh, xl, m0, m1) \
+  do {									\
+    union {DItype __ll;							\
+	   struct {USItype __h, __l;} __i;				\
+	  } __x;							\
+    __asm__ ("lr %N0,%1\n\tmr %0,%2"					\
+	     : "=&r" (__x.__ll)						\
+	     : "r" (m0), "r" (m1));					\
+    (xh) = __x.__i.__h; (xl) = __x.__i.__l;				\
+  } while (0)
+#define sdiv_qrnnd(q, r, n1, n0, d) \
+  do {									\
+    union {DItype __ll;							\
+	   struct {USItype __h, __l;} __i;				\
+	  } __x;							\
+    __x.__i.__h = n1; __x.__i.__l = n0;					\
+    __asm__ ("dr %0,%2"							\
+	     : "=r" (__x.__ll)						\
+	     : "0" (__x.__ll), "r" (d));				\
+    (q) = __x.__i.__l; (r) = __x.__i.__h;				\
+  } while (0)
+#else
+#define smul_ppmm(xh, xl, m0, m1) \
+  do {                                                                  \
+    register SItype __r0 __asm__ ("0");					\
+    register SItype __r1 __asm__ ("1") = (m0);				\
+									\
+    __asm__ ("mr\t%%r0,%3"                                              \
+	     : "=r" (__r0), "=r" (__r1)					\
+	     : "r"  (__r1),  "r" (m1));					\
+    (xh) = __r0; (xl) = __r1;						\
+  } while (0)
+
+#define sdiv_qrnnd(q, r, n1, n0, d) \
+  do {									\
+    register SItype __r0 __asm__ ("0") = (n1);				\
+    register SItype __r1 __asm__ ("1") = (n0);				\
+									\
+    __asm__ ("dr\t%%r0,%4"                                              \
+	     : "=r" (__r0), "=r" (__r1)					\
+	     : "r" (__r0), "r" (__r1), "r" (d));			\
+    (q) = __r1; (r) = __r0;						\
+  } while (0)
+#endif /* __zarch__ */
+#endif
+
+#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("mul{l} %3"							\
+	   : "=a" ((USItype) (w0)),					\
+	     "=d" ((USItype) (w1))					\
+	   : "%0" ((USItype) (u)),					\
+	     "rm" ((USItype) (v)))
+#define udiv_qrnnd(q, r, n1, n0, dv) \
+  __asm__ ("div{l} %4"							\
+	   : "=a" ((USItype) (q)),					\
+	     "=d" ((USItype) (r))					\
+	   : "0" ((USItype) (n0)),					\
+	     "1" ((USItype) (n1)),					\
+	     "rm" ((USItype) (dv)))
+#define count_leading_zeros(count, x)	((count) = __builtin_clz (x))
+#define count_trailing_zeros(count, x)	((count) = __builtin_ctz (x))
+#define UMUL_TIME 40
+#define UDIV_TIME 40
+#endif /* 80x86 */
+
+#if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"		\
+	   : "=r" ((UDItype) (sh)),					\
+	     "=&r" ((UDItype) (sl))					\
+	   : "%0" ((UDItype) (ah)),					\
+	     "rme" ((UDItype) (bh)),					\
+	     "%1" ((UDItype) (al)),					\
+	     "rme" ((UDItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"		\
+	   : "=r" ((UDItype) (sh)),					\
+	     "=&r" ((UDItype) (sl))					\
+	   : "0" ((UDItype) (ah)),					\
+	     "rme" ((UDItype) (bh)),					\
+	     "1" ((UDItype) (al)),					\
+	     "rme" ((UDItype) (bl)))
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("mul{q} %3"							\
+	   : "=a" ((UDItype) (w0)),					\
+	     "=d" ((UDItype) (w1))					\
+	   : "%0" ((UDItype) (u)),					\
+	     "rm" ((UDItype) (v)))
+#define udiv_qrnnd(q, r, n1, n0, dv) \
+  __asm__ ("div{q} %4"							\
+	   : "=a" ((UDItype) (q)),					\
+	     "=d" ((UDItype) (r))					\
+	   : "0" ((UDItype) (n0)),					\
+	     "1" ((UDItype) (n1)),					\
+	     "rm" ((UDItype) (dv)))
+#define count_leading_zeros(count, x)	((count) = __builtin_clzll (x))
+#define count_trailing_zeros(count, x)	((count) = __builtin_ctzll (x))
+#define UMUL_TIME 40
+#define UDIV_TIME 40
+#endif /* x86_64 */
+
+#if defined (__i960__) && W_TYPE_SIZE == 32
+#define umul_ppmm(w1, w0, u, v) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __l, __h;} __i;				\
+	  } __xx;							\
+  __asm__ ("emul	%2,%1,%0"					\
+	   : "=d" (__xx.__ll)						\
+	   : "%dI" ((USItype) (u)),					\
+	     "dI" ((USItype) (v)));					\
+  (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
+#define __umulsidi3(u, v) \
+  ({UDItype __w;							\
+    __asm__ ("emul	%2,%1,%0"					\
+	     : "=d" (__w)						\
+	     : "%dI" ((USItype) (u)),					\
+	       "dI" ((USItype) (v)));					\
+    __w; })
+#endif /* __i960__ */
+
+#if defined (__ia64) && W_TYPE_SIZE == 64
+/* This form encourages gcc (pre-release 3.4 at least) to emit predicated
+   "sub r=r,r" and "sub r=r,r,1", giving a 2 cycle latency.  The generic
+   code using "al<bl" arithmetically comes out making an actual 0 or 1 in a
+   register, which takes an extra cycle.  */
+#define sub_ddmmss(sh, sl, ah, al, bh, bl)				\
+  do {									\
+    UWtype __x;								\
+    __x = (al) - (bl);							\
+    if ((al) < (bl))							\
+      (sh) = (ah) - (bh) - 1;						\
+    else								\
+      (sh) = (ah) - (bh);						\
+    (sl) = __x;								\
+  } while (0)
+
+/* Do both product parts in assembly, since that gives better code with
+   all gcc versions.  Some callers will just use the upper part, and in
+   that situation we waste an instruction, but not any cycles.  */
+#define umul_ppmm(ph, pl, m0, m1)					\
+  __asm__ ("xma.hu %0 = %2, %3, f0\n\txma.l %1 = %2, %3, f0"		\
+	   : "=&f" (ph), "=f" (pl)					\
+	   : "f" (m0), "f" (m1))
+#define count_leading_zeros(count, x)					\
+  do {									\
+    UWtype _x = (x), _y, _a, _c;					\
+    __asm__ ("mux1 %0 = %1, @rev" : "=r" (_y) : "r" (_x));		\
+    __asm__ ("czx1.l %0 = %1" : "=r" (_a) : "r" (-_y | _y));		\
+    _c = (_a - 1) << 3;							\
+    _x >>= _c;								\
+    if (_x >= 1 << 4)							\
+      _x >>= 4, _c += 4;						\
+    if (_x >= 1 << 2)							\
+      _x >>= 2, _c += 2;						\
+    _c += _x >> 1;							\
+    (count) =  W_TYPE_SIZE - 1 - _c;					\
+  } while (0)
+/* similar to what gcc does for __builtin_ffs, but 0 based rather than 1
+   based, and we don't need a special case for x==0 here */
+#define count_trailing_zeros(count, x)					\
+  do {									\
+    UWtype __ctz_x = (x);						\
+    __asm__ ("popcnt %0 = %1"						\
+	     : "=r" (count)						\
+	     : "r" ((__ctz_x-1) & ~__ctz_x));				\
+  } while (0)
+#define UMUL_TIME 14
+#endif
+
+#if defined (__M32R__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  /* The cmp clears the condition bit.  */ \
+  __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl))					\
+	   : "cbit")
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  /* The cmp clears the condition bit.  */ \
+  __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl))					\
+	   : "cbit")
+#endif /* __M32R__ */
+
+#if defined (__mc68000__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
+	   : "=d" ((USItype) (sh)),					\
+	     "=&d" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "d" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
+	   : "=d" ((USItype) (sh)),					\
+	     "=&d" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "d" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+
+/* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r.  */
+#if (defined (__mc68020__) && !defined (__mc68060__))
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("mulu%.l %3,%1:%0"						\
+	   : "=d" ((USItype) (w0)),					\
+	     "=d" ((USItype) (w1))					\
+	   : "%0" ((USItype) (u)),					\
+	     "dmi" ((USItype) (v)))
+#define UMUL_TIME 45
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  __asm__ ("divu%.l %4,%1:%0"						\
+	   : "=d" ((USItype) (q)),					\
+	     "=d" ((USItype) (r))					\
+	   : "0" ((USItype) (n0)),					\
+	     "1" ((USItype) (n1)),					\
+	     "dmi" ((USItype) (d)))
+#define UDIV_TIME 90
+#define sdiv_qrnnd(q, r, n1, n0, d) \
+  __asm__ ("divs%.l %4,%1:%0"						\
+	   : "=d" ((USItype) (q)),					\
+	     "=d" ((USItype) (r))					\
+	   : "0" ((USItype) (n0)),					\
+	     "1" ((USItype) (n1)),					\
+	     "dmi" ((USItype) (d)))
+
+#elif defined (__mcoldfire__) /* not mc68020 */
+
+#define umul_ppmm(xh, xl, a, b) \
+  __asm__ ("| Inlined umul_ppmm\n"					\
+	   "	move%.l	%2,%/d0\n"					\
+	   "	move%.l	%3,%/d1\n"					\
+	   "	move%.l	%/d0,%/d2\n"					\
+	   "	swap	%/d0\n"						\
+	   "	move%.l	%/d1,%/d3\n"					\
+	   "	swap	%/d1\n"						\
+	   "	move%.w	%/d2,%/d4\n"					\
+	   "	mulu	%/d3,%/d4\n"					\
+	   "	mulu	%/d1,%/d2\n"					\
+	   "	mulu	%/d0,%/d3\n"					\
+	   "	mulu	%/d0,%/d1\n"					\
+	   "	move%.l	%/d4,%/d0\n"					\
+	   "	clr%.w	%/d0\n"						\
+	   "	swap	%/d0\n"						\
+	   "	add%.l	%/d0,%/d2\n"					\
+	   "	add%.l	%/d3,%/d2\n"					\
+	   "	jcc	1f\n"						\
+	   "	add%.l	%#65536,%/d1\n"					\
+	   "1:	swap	%/d2\n"						\
+	   "	moveq	%#0,%/d0\n"					\
+	   "	move%.w	%/d2,%/d0\n"					\
+	   "	move%.w	%/d4,%/d2\n"					\
+	   "	move%.l	%/d2,%1\n"					\
+	   "	add%.l	%/d1,%/d0\n"					\
+	   "	move%.l	%/d0,%0"					\
+	   : "=g" ((USItype) (xh)),					\
+	     "=g" ((USItype) (xl))					\
+	   : "g" ((USItype) (a)),					\
+	     "g" ((USItype) (b))					\
+	   : "d0", "d1", "d2", "d3", "d4")
+#define UMUL_TIME 100
+#define UDIV_TIME 400
+#else /* not ColdFire */
+/* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX.  */
+#define umul_ppmm(xh, xl, a, b) \
+  __asm__ ("| Inlined umul_ppmm\n"					\
+	   "	move%.l	%2,%/d0\n"					\
+	   "	move%.l	%3,%/d1\n"					\
+	   "	move%.l	%/d0,%/d2\n"					\
+	   "	swap	%/d0\n"						\
+	   "	move%.l	%/d1,%/d3\n"					\
+	   "	swap	%/d1\n"						\
+	   "	move%.w	%/d2,%/d4\n"					\
+	   "	mulu	%/d3,%/d4\n"					\
+	   "	mulu	%/d1,%/d2\n"					\
+	   "	mulu	%/d0,%/d3\n"					\
+	   "	mulu	%/d0,%/d1\n"					\
+	   "	move%.l	%/d4,%/d0\n"					\
+	   "	eor%.w	%/d0,%/d0\n"					\
+	   "	swap	%/d0\n"						\
+	   "	add%.l	%/d0,%/d2\n"					\
+	   "	add%.l	%/d3,%/d2\n"					\
+	   "	jcc	1f\n"						\
+	   "	add%.l	%#65536,%/d1\n"					\
+	   "1:	swap	%/d2\n"						\
+	   "	moveq	%#0,%/d0\n"					\
+	   "	move%.w	%/d2,%/d0\n"					\
+	   "	move%.w	%/d4,%/d2\n"					\
+	   "	move%.l	%/d2,%1\n"					\
+	   "	add%.l	%/d1,%/d0\n"					\
+	   "	move%.l	%/d0,%0"					\
+	   : "=g" ((USItype) (xh)),					\
+	     "=g" ((USItype) (xl))					\
+	   : "g" ((USItype) (a)),					\
+	     "g" ((USItype) (b))					\
+	   : "d0", "d1", "d2", "d3", "d4")
+#define UMUL_TIME 100
+#define UDIV_TIME 400
+
+#endif /* not mc68020 */
+
+/* The '020, '030, '040 and '060 have bitfield insns.
+   cpu32 disguises as a 68020, but lacks them.  */
+#if defined (__mc68020__) && !defined (__mcpu32__)
+#define count_leading_zeros(count, x) \
+  __asm__ ("bfffo %1{%b2:%b2},%0"					\
+	   : "=d" ((USItype) (count))					\
+	   : "od" ((USItype) (x)), "n" (0))
+/* Some ColdFire architectures have a ff1 instruction supported via
+   __builtin_clz. */
+#elif defined (__mcfisaaplus__) || defined (__mcfisac__)
+#define count_leading_zeros(count,x) ((count) = __builtin_clz (x))
+#define COUNT_LEADING_ZEROS_0 32
+#endif
+#endif /* mc68000 */
+
+#if defined (__m88000__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%rJ" ((USItype) (ah)),					\
+	     "rJ" ((USItype) (bh)),					\
+	     "%rJ" ((USItype) (al)),					\
+	     "rJ" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "rJ" ((USItype) (ah)),					\
+	     "rJ" ((USItype) (bh)),					\
+	     "rJ" ((USItype) (al)),					\
+	     "rJ" ((USItype) (bl)))
+#define count_leading_zeros(count, x) \
+  do {									\
+    USItype __cbtmp;							\
+    __asm__ ("ff1 %0,%1"						\
+	     : "=r" (__cbtmp)						\
+	     : "r" ((USItype) (x)));					\
+    (count) = __cbtmp ^ 31;						\
+  } while (0)
+#define COUNT_LEADING_ZEROS_0 63 /* sic */
+#if defined (__mc88110__)
+#define umul_ppmm(wh, wl, u, v) \
+  do {									\
+    union {UDItype __ll;						\
+	   struct {USItype __h, __l;} __i;				\
+	  } __xx;							\
+    __asm__ ("mulu.d	%0,%1,%2"					\
+	     : "=r" (__xx.__ll)						\
+	     : "r" ((USItype) (u)),					\
+	       "r" ((USItype) (v)));					\
+    (wh) = __xx.__i.__h;						\
+    (wl) = __xx.__i.__l;						\
+  } while (0)
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __h, __l;} __i;				\
+	  } __xx;							\
+  USItype __q;								\
+  __xx.__i.__h = (n1); __xx.__i.__l = (n0);				\
+  __asm__ ("divu.d %0,%1,%2"						\
+	   : "=r" (__q)							\
+	   : "r" (__xx.__ll),						\
+	     "r" ((USItype) (d)));					\
+  (r) = (n0) - __q * (d); (q) = __q; })
+#define UMUL_TIME 5
+#define UDIV_TIME 25
+#else
+#define UMUL_TIME 17
+#define UDIV_TIME 150
+#endif /* __mc88110__ */
+#endif /* __m88000__ */
+
+#if defined (__mn10300__)
+# if defined (__AM33__)
+#  define count_leading_zeros(COUNT,X)	((COUNT) = __builtin_clz (X))
+#  define umul_ppmm(w1, w0, u, v)		\
+    asm("mulu %3,%2,%1,%0" : "=r"(w0), "=r"(w1) : "r"(u), "r"(v))
+#  define smul_ppmm(w1, w0, u, v)		\
+    asm("mul %3,%2,%1,%0" : "=r"(w0), "=r"(w1) : "r"(u), "r"(v))
+# else
+#  define umul_ppmm(w1, w0, u, v)		\
+    asm("nop; nop; mulu %3,%0" : "=d"(w0), "=z"(w1) : "%0"(u), "d"(v))
+#  define smul_ppmm(w1, w0, u, v)		\
+    asm("nop; nop; mul %3,%0" : "=d"(w0), "=z"(w1) : "%0"(u), "d"(v))
+# endif
+# define add_ssaaaa(sh, sl, ah, al, bh, bl)	\
+  do {						\
+    DWunion __s, __a, __b;			\
+    __a.s.low = (al); __a.s.high = (ah);	\
+    __b.s.low = (bl); __b.s.high = (bh);	\
+    __s.ll = __a.ll + __b.ll;			\
+    (sl) = __s.s.low; (sh) = __s.s.high;	\
+  } while (0)
+# define sub_ddmmss(sh, sl, ah, al, bh, bl)	\
+  do {						\
+    DWunion __s, __a, __b;			\
+    __a.s.low = (al); __a.s.high = (ah);	\
+    __b.s.low = (bl); __b.s.high = (bh);	\
+    __s.ll = __a.ll - __b.ll;			\
+    (sl) = __s.s.low; (sh) = __s.s.high;	\
+  } while (0)
+# define udiv_qrnnd(q, r, nh, nl, d)		\
+  asm("divu %2,%0" : "=D"(q), "=z"(r) : "D"(d), "0"(nl), "1"(nh))
+# define sdiv_qrnnd(q, r, nh, nl, d)		\
+  asm("div %2,%0" : "=D"(q), "=z"(r) : "D"(d), "0"(nl), "1"(nh))
+# define UMUL_TIME 3
+# define UDIV_TIME 38
+#endif
+
+#if defined (__mips__) && W_TYPE_SIZE == 32
+#define umul_ppmm(w1, w0, u, v)						\
+  do {									\
+    UDItype __x = (UDItype) (USItype) (u) * (USItype) (v);		\
+    (w1) = (USItype) (__x >> 32);					\
+    (w0) = (USItype) (__x);						\
+  } while (0)
+#define UMUL_TIME 10
+#define UDIV_TIME 100
+
+#if (__mips == 32 || __mips == 64) && ! __mips16
+#define count_leading_zeros(COUNT,X)	((COUNT) = __builtin_clz (X))
+#define COUNT_LEADING_ZEROS_0 32
+#endif
+#endif /* __mips__ */
+
+#if defined (__ns32000__) && W_TYPE_SIZE == 32
+#define umul_ppmm(w1, w0, u, v) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __l, __h;} __i;				\
+	  } __xx;							\
+  __asm__ ("meid %2,%0"							\
+	   : "=g" (__xx.__ll)						\
+	   : "%0" ((USItype) (u)),					\
+	     "g" ((USItype) (v)));					\
+  (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
+#define __umulsidi3(u, v) \
+  ({UDItype __w;							\
+    __asm__ ("meid %2,%0"						\
+	     : "=g" (__w)						\
+	     : "%0" ((USItype) (u)),					\
+	       "g" ((USItype) (v)));					\
+    __w; })
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __l, __h;} __i;				\
+	  } __xx;							\
+  __xx.__i.__h = (n1); __xx.__i.__l = (n0);				\
+  __asm__ ("deid %2,%0"							\
+	   : "=g" (__xx.__ll)						\
+	   : "0" (__xx.__ll),						\
+	     "g" ((USItype) (d)));					\
+  (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
+#define count_trailing_zeros(count,x) \
+  do {									\
+    __asm__ ("ffsd     %2,%0"						\
+	    : "=r" ((USItype) (count))					\
+	    : "0" ((USItype) 0),					\
+	      "r" ((USItype) (x)));					\
+  } while (0)
+#endif /* __ns32000__ */
+
+/* FIXME: We should test _IBMR2 here when we add assembly support for the
+   system vendor compilers.
+   FIXME: What's needed for gcc PowerPC VxWorks?  __vxworks__ is not good
+   enough, since that hits ARM and m68k too.  */
+#if (defined (_ARCH_PPC)	/* AIX */				\
+     || defined (__powerpc__)	/* gcc */				\
+     || defined (__POWERPC__)	/* BEOS */				\
+     || defined (__ppc__)	/* Darwin */				\
+     || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */    \
+     || (defined (PPC) && defined (CPU_FAMILY)    /* VxWorks */               \
+	 && CPU_FAMILY == PPC)                                                \
+     ) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (bh) && (bh) == 0)				\
+      __asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0)		\
+      __asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else								\
+      __asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3"		\
+	     : "=r" (sh), "=&r" (sl)					\
+	     : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl));		\
+  } while (0)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (ah) && (ah) == 0)				\
+      __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0)		\
+      __asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == 0)			\
+      __asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0)		\
+      __asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else								\
+      __asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2"	\
+	       : "=r" (sh), "=&r" (sl)					\
+	       : "r" (ah), "r" (bh), "rI" (al), "r" (bl));		\
+  } while (0)
+#define count_leading_zeros(count, x) \
+  __asm__ ("cntlzw %0,%1" : "=r" (count) : "r" (x))
+#define COUNT_LEADING_ZEROS_0 32
+#if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
+  || defined (__ppc__)                                                    \
+  || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */       \
+  || (defined (PPC) && defined (CPU_FAMILY)    /* VxWorks */                  \
+	 && CPU_FAMILY == PPC)
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    USItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define UMUL_TIME 15
+#define smul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    SItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define SMUL_TIME 14
+#define UDIV_TIME 120
+#endif
+#endif /* 32-bit POWER architecture variants.  */
+
+/* We should test _IBMR2 here when we add assembly support for the system
+   vendor compilers.  */
+#if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (bh) && (bh) == 0)				\
+      __asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0)		\
+      __asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else								\
+      __asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3"		\
+	     : "=r" (sh), "=&r" (sl)					\
+	     : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl));		\
+  } while (0)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (ah) && (ah) == 0)				\
+      __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0)		\
+      __asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == 0)			\
+      __asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0)		\
+      __asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else								\
+      __asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2"	\
+	       : "=r" (sh), "=&r" (sl)					\
+	       : "r" (ah), "r" (bh), "rI" (al), "r" (bl));		\
+  } while (0)
+#define count_leading_zeros(count, x) \
+  __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
+#define COUNT_LEADING_ZEROS_0 64
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    UDItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define UMUL_TIME 15
+#define smul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    DItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define SMUL_TIME 14  /* ??? */
+#define UDIV_TIME 120 /* ??? */
+#endif /* 64-bit PowerPC.  */
+
+#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("a %1,%5\n\tae %0,%3"					\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("s %1,%5\n\tse %0,%3"					\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl)))
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    USItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ (								\
+       "s	r2,r2\n"						\
+"	mts	r10,%2\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	cas	%0,r2,r0\n"						\
+"	mfs	r10,%1"							\
+	     : "=r" ((USItype) (ph)),					\
+	       "=r" ((USItype) (pl))					\
+	     : "%r" (__m0),						\
+		"r" (__m1)						\
+	     : "r2");							\
+    (ph) += ((((SItype) __m0 >> 31) & __m1)				\
+	     + (((SItype) __m1 >> 31) & __m0));				\
+  } while (0)
+#define UMUL_TIME 20
+#define UDIV_TIME 200
+#define count_leading_zeros(count, x) \
+  do {									\
+    if ((x) >= 0x10000)							\
+      __asm__ ("clz	%0,%1"						\
+	       : "=r" ((USItype) (count))				\
+	       : "r" ((USItype) (x) >> 16));				\
+    else								\
+      {									\
+	__asm__ ("clz	%0,%1"						\
+		 : "=r" ((USItype) (count))				\
+		 : "r" ((USItype) (x)));					\
+	(count) += 16;							\
+      }									\
+  } while (0)
+#endif
+
+#if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32
+#ifndef __sh1__
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ (								\
+       "dmulu.l	%2,%3\n\tsts%M1	macl,%1\n\tsts%M0	mach,%0"	\
+	   : "=r<" ((USItype)(w1)),					\
+	     "=r<" ((USItype)(w0))					\
+	   : "r" ((USItype)(u)),					\
+	     "r" ((USItype)(v))						\
+	   : "macl", "mach")
+#define UMUL_TIME 5
+#endif
+
+/* This is the same algorithm as __udiv_qrnnd_c.  */
+#define UDIV_NEEDS_NORMALIZATION 1
+
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  do {									\
+    extern UWtype __udiv_qrnnd_16 (UWtype, UWtype)			\
+			__attribute__ ((visibility ("hidden")));	\
+    /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */	\
+    __asm__ (								\
+	"mov%M4 %4,r5\n"						\
+"	swap.w %3,r4\n"							\
+"	swap.w r5,r6\n"							\
+"	jsr @%5\n"							\
+"	shll16 r6\n"							\
+"	swap.w r4,r4\n"							\
+"	jsr @%5\n"							\
+"	swap.w r1,%0\n"							\
+"	or r1,%0"							\
+	: "=r" (q), "=&z" (r)						\
+	: "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16)		\
+	: "r1", "r2", "r4", "r5", "r6", "pr", "t");			\
+  } while (0)
+
+#define UDIV_TIME 80
+
+#define sub_ddmmss(sh, sl, ah, al, bh, bl)				\
+  __asm__ ("clrt;subc %5,%1; subc %4,%0"				\
+	   : "=r" (sh), "=r" (sl)					\
+	   : "0" (ah), "1" (al), "r" (bh), "r" (bl) : "t")
+
+#endif /* __sh__ */
+
+#if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
+#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
+#define count_leading_zeros(count, x) \
+  do									\
+    {									\
+      UDItype x_ = (USItype)(x);					\
+      SItype c_;							\
+									\
+      __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_));			\
+      (count) = c_ - 31;						\
+    }									\
+  while (0)
+#define COUNT_LEADING_ZEROS_0 32
+#endif
+
+#if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
+    && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%rJ" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "%rJ" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl))					\
+	   __CLOBBER_CC)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "rJ" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "rJ" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl))					\
+	   __CLOBBER_CC)
+#if defined (__sparc_v9__)
+#define umul_ppmm(w1, w0, u, v) \
+  do {									\
+    register USItype __g1 asm ("g1");					\
+    __asm__ ("umul\t%2,%3,%1\n\t"					\
+	     "srlx\t%1, 32, %0"						\
+	     : "=r" ((USItype) (w1)),					\
+	       "=r" (__g1)						\
+	     : "r" ((USItype) (u)),					\
+	       "r" ((USItype) (v)));					\
+    (w0) = __g1;							\
+  } while (0)
+#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
+  __asm__ ("mov\t%2,%%y\n\t"						\
+	   "udiv\t%3,%4,%0\n\t"						\
+	   "umul\t%0,%4,%1\n\t"						\
+	   "sub\t%3,%1,%1"						\
+	   : "=&r" ((USItype) (__q)),					\
+	     "=&r" ((USItype) (__r))					\
+	   : "r" ((USItype) (__n1)),					\
+	     "r" ((USItype) (__n0)),					\
+	     "r" ((USItype) (__d)))
+#else
+#if defined (__sparc_v8__)
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
+	   : "=r" ((USItype) (w1)),					\
+	     "=r" ((USItype) (w0))					\
+	   : "r" ((USItype) (u)),					\
+	     "r" ((USItype) (v)))
+#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
+  __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
+	   : "=&r" ((USItype) (__q)),					\
+	     "=&r" ((USItype) (__r))					\
+	   : "r" ((USItype) (__n1)),					\
+	     "r" ((USItype) (__n0)),					\
+	     "r" ((USItype) (__d)))
+#else
+#if defined (__sparclite__)
+/* This has hardware multiply but not divide.  It also has two additional
+   instructions scan (ffs from high bit) and divscc.  */
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
+	   : "=r" ((USItype) (w1)),					\
+	     "=r" ((USItype) (w0))					\
+	   : "r" ((USItype) (u)),					\
+	     "r" ((USItype) (v)))
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  __asm__ ("! Inlined udiv_qrnnd\n"					\
+"	wr	%%g0,%2,%%y	! Not a delayed write for sparclite\n"	\
+"	tst	%%g0\n"							\
+"	divscc	%3,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%0\n"						\
+"	rd	%%y,%1\n"						\
+"	bl,a 1f\n"							\
+"	add	%1,%4,%1\n"						\
+"1:	! End of inline udiv_qrnnd"					\
+	   : "=r" ((USItype) (q)),					\
+	     "=r" ((USItype) (r))					\
+	   : "r" ((USItype) (n1)),					\
+	     "r" ((USItype) (n0)),					\
+	     "rI" ((USItype) (d))					\
+	   : "g1" __AND_CLOBBER_CC)
+#define UDIV_TIME 37
+#define count_leading_zeros(count, x) \
+  do {                                                                  \
+  __asm__ ("scan %1,1,%0"                                               \
+	   : "=r" ((USItype) (count))                                   \
+	   : "r" ((USItype) (x)));					\
+  } while (0)
+/* Early sparclites return 63 for an argument of 0, but they warn that future
+   implementations might change this.  Therefore, leave COUNT_LEADING_ZEROS_0
+   undefined.  */
+#else
+/* SPARC without integer multiplication and divide instructions.
+   (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("! Inlined umul_ppmm\n"					\
+"	wr	%%g0,%2,%%y	! SPARC has 0-3 delay insn after a wr\n"\
+"	sra	%3,31,%%o5	! Don't move this insn\n"		\
+"	and	%2,%%o5,%%o5	! Don't move this insn\n"		\
+"	andcc	%%g0,0,%%g1	! Don't move this insn\n"		\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,0,%%g1\n"						\
+"	add	%%g1,%%o5,%0\n"						\
+"	rd	%%y,%1"							\
+	   : "=r" ((USItype) (w1)),					\
+	     "=r" ((USItype) (w0))					\
+	   : "%rI" ((USItype) (u)),					\
+	     "r" ((USItype) (v))						\
+	   : "g1", "o5" __AND_CLOBBER_CC)
+#define UMUL_TIME 39		/* 39 instructions */
+/* It's quite necessary to add this much assembler for the sparc.
+   The default udiv_qrnnd (in C) is more than 10 times slower!  */
+#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
+  __asm__ ("! Inlined udiv_qrnnd\n"					\
+"	mov	32,%%g1\n"						\
+"	subcc	%1,%2,%%g0\n"						\
+"1:	bcs	5f\n"							\
+"	 addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb\n"	\
+"	sub	%1,%2,%1	! this kills msb of n\n"		\
+"	addx	%1,%1,%1	! so this can't give carry\n"		\
+"	subcc	%%g1,1,%%g1\n"						\
+"2:	bne	1b\n"							\
+"	 subcc	%1,%2,%%g0\n"						\
+"	bcs	3f\n"							\
+"	 addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb\n"	\
+"	b	3f\n"							\
+"	 sub	%1,%2,%1	! this kills msb of n\n"		\
+"4:	sub	%1,%2,%1\n"						\
+"5:	addxcc	%1,%1,%1\n"						\
+"	bcc	2b\n"							\
+"	 subcc	%%g1,1,%%g1\n"						\
+"! Got carry from n.  Subtract next step to cancel this carry.\n"	\
+"	bne	4b\n"							\
+"	 addcc	%0,%0,%0	! shift n1n0 and a 0-bit in lsb\n"	\
+"	sub	%1,%2,%1\n"						\
+"3:	xnor	%0,0,%0\n"						\
+"	! End of inline udiv_qrnnd"					\
+	   : "=&r" ((USItype) (__q)),					\
+	     "=&r" ((USItype) (__r))					\
+	   : "r" ((USItype) (__d)),					\
+	     "1" ((USItype) (__n1)),					\
+	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
+#define UDIV_TIME (3+7*32)	/* 7 instructions/iteration. 32 iterations.  */
+#endif /* __sparclite__ */
+#endif /* __sparc_v8__ */
+#endif /* __sparc_v9__ */
+#endif /* sparc32 */
+
+#if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
+    && W_TYPE_SIZE == 64
+#define add_ssaaaa(sh, sl, ah, al, bh, bl)				\
+  do {									\
+    UDItype __carry = 0;						\
+    __asm__ ("addcc\t%r5,%6,%1\n\t"					\
+	     "add\t%r3,%4,%0\n\t"					\
+	     "movcs\t%%xcc, 1, %2\n\t"					\
+	     "add\t%0, %2, %0"						\
+	     : "=r" ((UDItype)(sh)),				      	\
+	       "=&r" ((UDItype)(sl)),				      	\
+	       "+r" (__carry)				      		\
+	     : "%rJ" ((UDItype)(ah)),				     	\
+	       "rI" ((UDItype)(bh)),				      	\
+	       "%rJ" ((UDItype)(al)),				     	\
+	       "rI" ((UDItype)(bl))				       	\
+	     __CLOBBER_CC);						\
+  } while (0)
+
+#define sub_ddmmss(sh, sl, ah, al, bh, bl)				\
+  do {									\
+    UDItype __carry = 0;						\
+    __asm__ ("subcc\t%r5,%6,%1\n\t"					\
+	     "sub\t%r3,%4,%0\n\t"					\
+	     "movcs\t%%xcc, 1, %2\n\t"					\
+	     "sub\t%0, %2, %0"						\
+	     : "=r" ((UDItype)(sh)),				      	\
+	       "=&r" ((UDItype)(sl)),				      	\
+	       "+r" (__carry)				      		\
+	     : "%rJ" ((UDItype)(ah)),				     	\
+	       "rI" ((UDItype)(bh)),				      	\
+	       "%rJ" ((UDItype)(al)),				     	\
+	       "rI" ((UDItype)(bl))				       	\
+	     __CLOBBER_CC);						\
+  } while (0)
+
+#define umul_ppmm(wh, wl, u, v)						\
+  do {									\
+	  UDItype tmp1, tmp2, tmp3, tmp4;				\
+	  __asm__ __volatile__ (					\
+		   "srl %7,0,%3\n\t"					\
+		   "mulx %3,%6,%1\n\t"					\
+		   "srlx %6,32,%2\n\t"					\
+		   "mulx %2,%3,%4\n\t"					\
+		   "sllx %4,32,%5\n\t"					\
+		   "srl %6,0,%3\n\t"					\
+		   "sub %1,%5,%5\n\t"					\
+		   "srlx %5,32,%5\n\t"					\
+		   "addcc %4,%5,%4\n\t"					\
+		   "srlx %7,32,%5\n\t"					\
+		   "mulx %3,%5,%3\n\t"					\
+		   "mulx %2,%5,%5\n\t"					\
+		   "sethi %%hi(0x80000000),%2\n\t"			\
+		   "addcc %4,%3,%4\n\t"					\
+		   "srlx %4,32,%4\n\t"					\
+		   "add %2,%2,%2\n\t"					\
+		   "movcc %%xcc,%%g0,%2\n\t"				\
+		   "addcc %5,%4,%5\n\t"					\
+		   "sllx %3,32,%3\n\t"					\
+		   "add %1,%3,%1\n\t"					\
+		   "add %5,%2,%0"					\
+	   : "=r" ((UDItype)(wh)),					\
+	     "=&r" ((UDItype)(wl)),					\
+	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
+	   : "r" ((UDItype)(u)),					\
+	     "r" ((UDItype)(v))						\
+	   __CLOBBER_CC);						\
+  } while (0)
+#define UMUL_TIME 96
+#define UDIV_TIME 230
+#endif /* sparc64 */
+
+#if defined (__vax__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
+	   : "=g" ((USItype) (sh)),					\
+	     "=&g" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
+	   : "=g" ((USItype) (sh)),					\
+	     "=&g" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define umul_ppmm(xh, xl, m0, m1) \
+  do {									\
+    union {								\
+	UDItype __ll;							\
+	struct {USItype __l, __h;} __i;					\
+      } __xx;								\
+    USItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("emul %1,%2,$0,%0"						\
+	     : "=r" (__xx.__ll)						\
+	     : "g" (__m0),						\
+	       "g" (__m1));						\
+    (xh) = __xx.__i.__h;						\
+    (xl) = __xx.__i.__l;						\
+    (xh) += ((((SItype) __m0 >> 31) & __m1)				\
+	     + (((SItype) __m1 >> 31) & __m0));				\
+  } while (0)
+#define sdiv_qrnnd(q, r, n1, n0, d) \
+  do {									\
+    union {DItype __ll;							\
+	   struct {SItype __l, __h;} __i;				\
+	  } __xx;							\
+    __xx.__i.__h = n1; __xx.__i.__l = n0;				\
+    __asm__ ("ediv %3,%2,%0,%1"						\
+	     : "=g" (q), "=g" (r)					\
+	     : "g" (__xx.__ll), "g" (d));				\
+  } while (0)
+#endif /* __vax__ */
+
+#ifdef _TMS320C6X
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  do									\
+    {									\
+      UDItype __ll;							\
+      __asm__ ("addu .l1 %1, %2, %0"					\
+	       : "=a" (__ll) : "a" (al), "a" (bl));			\
+      (sl) = (USItype)__ll;						\
+      (sh) = ((USItype)(__ll >> 32)) + (ah) + (bh);			\
+    }									\
+  while (0)
+
+#ifdef _TMS320C6400_PLUS
+#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
+#define umul_ppmm(w1, w0, u, v)						\
+  do {									\
+    UDItype __x = (UDItype) (USItype) (u) * (USItype) (v);		\
+    (w1) = (USItype) (__x >> 32);					\
+    (w0) = (USItype) (__x);						\
+  } while (0)
+#endif  /* _TMS320C6400_PLUS */
+
+#define count_leading_zeros(count, x)	((count) = __builtin_clz (x))
+#ifdef _TMS320C6400
+#define count_trailing_zeros(count, x)	((count) = __builtin_ctz (x))
+#endif
+#define UMUL_TIME 4
+#define UDIV_TIME 40
+#endif /* _TMS320C6X */
+
+#if defined (__xtensa__) && W_TYPE_SIZE == 32
+/* This code is not Xtensa-configuration-specific, so rely on the compiler
+   to expand builtin functions depending on what configuration features
+   are available.  This avoids library calls when the operation can be
+   performed in-line.  */
+#define umul_ppmm(w1, w0, u, v)						\
+  do {									\
+    DWunion __w;							\
+    __w.ll = __builtin_umulsidi3 (u, v);				\
+    w1 = __w.s.high;							\
+    w0 = __w.s.low;							\
+  } while (0)
+#define __umulsidi3(u, v)		__builtin_umulsidi3 (u, v)
+#define count_leading_zeros(COUNT, X)	((COUNT) = __builtin_clz (X))
+#define count_trailing_zeros(COUNT, X)	((COUNT) = __builtin_ctz (X))
+#endif /* __xtensa__ */
+
+#if defined xstormy16
+extern UHItype __stormy16_count_leading_zeros (UHItype);
+#define count_leading_zeros(count, x)					\
+  do									\
+    {									\
+      UHItype size;							\
+									\
+      /* We assume that W_TYPE_SIZE is a multiple of 16...  */		\
+      for ((count) = 0, size = W_TYPE_SIZE; size; size -= 16)		\
+	{								\
+	  UHItype c;							\
+									\
+	  c = __clzhi2 ((x) >> (size - 16));				\
+	  (count) += c;							\
+	  if (c != 16)							\
+	    break;							\
+	}								\
+    }									\
+  while (0)
+#define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
+#endif
+
+#if defined (__z8000__) && W_TYPE_SIZE == 16
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add	%H1,%H5\n\tadc	%H0,%H3"				\
+	   : "=r" ((unsigned int)(sh)),					\
+	     "=&r" ((unsigned int)(sl))					\
+	   : "%0" ((unsigned int)(ah)),					\
+	     "r" ((unsigned int)(bh)),					\
+	     "%1" ((unsigned int)(al)),					\
+	     "rQR" ((unsigned int)(bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub	%H1,%H5\n\tsbc	%H0,%H3"				\
+	   : "=r" ((unsigned int)(sh)),					\
+	     "=&r" ((unsigned int)(sl))					\
+	   : "0" ((unsigned int)(ah)),					\
+	     "r" ((unsigned int)(bh)),					\
+	     "1" ((unsigned int)(al)),					\
+	     "rQR" ((unsigned int)(bl)))
+#define umul_ppmm(xh, xl, m0, m1) \
+  do {									\
+    union {long int __ll;						\
+	   struct {unsigned int __h, __l;} __i;				\
+	  } __xx;							\
+    unsigned int __m0 = (m0), __m1 = (m1);				\
+    __asm__ ("mult	%S0,%H3"					\
+	     : "=r" (__xx.__i.__h),					\
+	       "=r" (__xx.__i.__l)					\
+	     : "%1" (__m0),						\
+	       "rQR" (__m1));						\
+    (xh) = __xx.__i.__h; (xl) = __xx.__i.__l;				\
+    (xh) += ((((signed int) __m0 >> 15) & __m1)				\
+	     + (((signed int) __m1 >> 15) & __m0));			\
+  } while (0)
+#endif /* __z8000__ */
+
+#endif /* __GNUC__ */
+
+/* If this machine has no inline assembler, use C macros.  */
+
+#if !defined (add_ssaaaa)
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  do {									\
+    UWtype __x;								\
+    __x = (al) + (bl);							\
+    (sh) = (ah) + (bh) + (__x < (al));					\
+    (sl) = __x;								\
+  } while (0)
+#endif
+
+#if !defined (sub_ddmmss)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  do {									\
+    UWtype __x;								\
+    __x = (al) - (bl);							\
+    (sh) = (ah) - (bh) - (__x > (al));					\
+    (sl) = __x;								\
+  } while (0)
+#endif
+
+/* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
+   smul_ppmm.  */
+#if !defined (umul_ppmm) && defined (smul_ppmm)
+#define umul_ppmm(w1, w0, u, v)						\
+  do {									\
+    UWtype __w1;							\
+    UWtype __xm0 = (u), __xm1 = (v);					\
+    smul_ppmm (__w1, w0, __xm0, __xm1);					\
+    (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1)		\
+		+ (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0);		\
+  } while (0)
+#endif
+
+/* If we still don't have umul_ppmm, define it using plain C.  */
+#if !defined (umul_ppmm)
+#define umul_ppmm(w1, w0, u, v)						\
+  do {									\
+    UWtype __x0, __x1, __x2, __x3;					\
+    UHWtype __ul, __vl, __uh, __vh;					\
+									\
+    __ul = __ll_lowpart (u);						\
+    __uh = __ll_highpart (u);						\
+    __vl = __ll_lowpart (v);						\
+    __vh = __ll_highpart (v);						\
+									\
+    __x0 = (UWtype) __ul * __vl;					\
+    __x1 = (UWtype) __ul * __vh;					\
+    __x2 = (UWtype) __uh * __vl;					\
+    __x3 = (UWtype) __uh * __vh;					\
+									\
+    __x1 += __ll_highpart (__x0);/* this can't give carry */		\
+    __x1 += __x2;		/* but this indeed can */		\
+    if (__x1 < __x2)		/* did we get it? */			\
+      __x3 += __ll_B;		/* yes, add it in the proper pos.  */	\
+									\
+    (w1) = __x3 + __ll_highpart (__x1);					\
+    (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0);		\
+  } while (0)
+#endif
+
+#if !defined (__umulsidi3)
+#define __umulsidi3(u, v) \
+  ({DWunion __w;							\
+    umul_ppmm (__w.s.high, __w.s.low, u, v);				\
+    __w.ll; })
+#endif
+
+/* Define this unconditionally, so it can be used for debugging.  */
+#define __udiv_qrnnd_c(q, r, n1, n0, d) \
+  do {									\
+    UWtype __d1, __d0, __q1, __q0;					\
+    UWtype __r1, __r0, __m;						\
+    __d1 = __ll_highpart (d);						\
+    __d0 = __ll_lowpart (d);						\
+									\
+    __r1 = (n1) % __d1;							\
+    __q1 = (n1) / __d1;							\
+    __m = (UWtype) __q1 * __d0;						\
+    __r1 = __r1 * __ll_B | __ll_highpart (n0);				\
+    if (__r1 < __m)							\
+      {									\
+	__q1--, __r1 += (d);						\
+	if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
+	  if (__r1 < __m)						\
+	    __q1--, __r1 += (d);					\
+      }									\
+    __r1 -= __m;							\
+									\
+    __r0 = __r1 % __d1;							\
+    __q0 = __r1 / __d1;							\
+    __m = (UWtype) __q0 * __d0;						\
+    __r0 = __r0 * __ll_B | __ll_lowpart (n0);				\
+    if (__r0 < __m)							\
+      {									\
+	__q0--, __r0 += (d);						\
+	if (__r0 >= (d))						\
+	  if (__r0 < __m)						\
+	    __q0--, __r0 += (d);					\
+      }									\
+    __r0 -= __m;							\
+									\
+    (q) = (UWtype) __q1 * __ll_B | __q0;				\
+    (r) = __r0;								\
+  } while (0)
+
+/* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
+   __udiv_w_sdiv (defined in libgcc or elsewhere).  */
+#if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
+#define udiv_qrnnd(q, r, nh, nl, d) \
+  do {									\
+    USItype __r;							\
+    (q) = __udiv_w_sdiv (&__r, nh, nl, d);				\
+    (r) = __r;								\
+  } while (0)
+#endif
+
+/* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c.  */
+#if !defined (udiv_qrnnd)
+#define UDIV_NEEDS_NORMALIZATION 1
+#define udiv_qrnnd __udiv_qrnnd_c
+#endif
+
+#if !defined (count_leading_zeros)
+#define count_leading_zeros(count, x) \
+  do {									\
+    UWtype __xr = (x);							\
+    UWtype __a;								\
+									\
+    if (W_TYPE_SIZE <= 32)						\
+      {									\
+	__a = __xr < ((UWtype)1<<2*__BITS4)				\
+	  ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4)			\
+	  : (__xr < ((UWtype)1<<3*__BITS4) ?  2*__BITS4 : 3*__BITS4);	\
+      }									\
+    else								\
+      {									\
+	for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8)			\
+	  if (((__xr >> __a) & 0xff) != 0)				\
+	    break;							\
+      }									\
+									\
+    (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a);		\
+  } while (0)
+#define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
+#endif
+
+#if !defined (count_trailing_zeros)
+/* Define count_trailing_zeros using count_leading_zeros.  The latter might be
+   defined in asm, but if it is not, the C version above is good enough.  */
+#define count_trailing_zeros(count, x) \
+  do {									\
+    UWtype __ctz_x = (x);						\
+    UWtype __ctz_c;							\
+    count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x);			\
+    (count) = W_TYPE_SIZE - 1 - __ctz_c;				\
+  } while (0)
+#endif
+
+#ifndef UDIV_NEEDS_NORMALIZATION
+#define UDIV_NEEDS_NORMALIZATION 0
+#endif
diff --git a/binutils-2.25/include/lto-symtab.h b/binutils-2.25/include/lto-symtab.h
new file mode 100644
index 00000000..9312c5d9
--- /dev/null
+++ b/binutils-2.25/include/lto-symtab.h
@@ -0,0 +1,41 @@
+/* Data types used in the IL symbol table.
+   Copyright (C) 2009 Free Software Foundation, Inc.
+   Contributed by Rafael Espindola <espindola@google.com>
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+#ifndef GCC_LTO_SYMTAB_H
+#define GCC_LTO_SYMTAB_H
+
+enum gcc_plugin_symbol_kind
+  {
+    GCCPK_DEF,
+    GCCPK_WEAKDEF,
+    GCCPK_UNDEF,
+    GCCPK_WEAKUNDEF,
+    GCCPK_COMMON
+  };
+
+enum gcc_plugin_symbol_visibility
+  {
+    GCCPV_DEFAULT,
+    GCCPV_PROTECTED,
+    GCCPV_INTERNAL,
+    GCCPV_HIDDEN
+  };
+
+#endif /* GCC_LTO_SYMTAB_H  */
diff --git a/binutils-2.25/include/mach-o/ChangeLog b/binutils-2.25/include/mach-o/ChangeLog
new file mode 100644
index 00000000..a36c5461
--- /dev/null
+++ b/binutils-2.25/include/mach-o/ChangeLog
@@ -0,0 +1,81 @@
+2012-11-14  Tristan Gingold  <gingold@adacore.com>
+
+	* external.h (mach_o_entry_point_command_external)
+	(mach_o_source_version_command_external)
+	(mach_o_data_in_code_entry_external): New structures.
+
+	* loader.h (bfd_mach_o_load_command_type): Add
+	BFD_MACH_O_LC_MAIN, BFD_MACH_O_LC_DATA_IN_CODE,
+	BFD_MACH_O_LC_SOURCE_VERSION and	BFD_MACH_O_LC_DYLIB_CODE_SIGN_DRS.
+	(BFD_MACH_O_REFERENCE_MASK): Adjust value.
+	(BFD_MACH_O_N_REF_TO_WEAK): New definition.
+	(BFD_MACH_O_N_ARM_THUMB_DEF, BFD_MACH_O_N_SYMBOL_RESOLVER): Likewise.
+	(bfd_mach_o_data_in_code_entry_kind): New enum.
+
+2012-11-14  Tristan Gingold  <gingold@adacore.com>
+
+	* arm.h: New file.
+
+2012-02-23  Iain Sandoe  <idsandoe@googlemail.com>
+
+	* external.h: Add comments about relocations fields.  Add macros
+	for non-scattered relocations.  Move scattered relocation macros to
+	here.
+	* reloc.h: Remove macros related to external representation of reloc
+	fields.
+
+2012-01-12  Iain Sandoe  <idsandoe@googlemail.com>
+
+	* loader.h (BFD_MACH_O_INDIRECT_SYM_LOCAL): New.
+	(BFD_MACH_O_INDIRECT_SYM_ABS): New
+
+2012-01-04  Tristan Gingold  <gingold@adacore.com>
+
+	* external.h (mach_o_fvmlib_command_external): New structure.
+
+2012-01-04  Tristan Gingold  <gingold@adacore.com>
+
+	* loader.h: Update copyright year.
+	(bfd_mach_o_cpu_subtype): Add ARM subtypes.
+
+2012-01-04  Tristan Gingold  <gingold@adacore.com>
+
+	* external.h: Update copyright year.
+	(mach_o_symtab_command_external): Add comments.
+	(mach_o_encryption_info_command_external): New structure.
+
+2011-12-16  Tristan Gingold  <gingold@adacore.com>
+
+	* codesign.h: New file.
+
+2011-08-08  Tristan Gingold  <gingold@adacore.com>
+
+	* loader.h (bfd_mach_o_load_command_type): Add
+	BFD_MACH_O_LC_LOAD_UPWARD_DYLIB, BFD_MACH_O_LC_VERSION_MIN_MACOSX,
+	BFD_MACH_O_LC_VERSION_MIN_IPHONEOS, BFD_MACH_O_LC_FUNCTION_STARTS,
+	and BFD_MACH_O_LC_DYLD_ENVIRONMENT.
+	* external.h (mach_o_version_min_command_external): New structure.
+
+2011-08-08  Tristan Gingold  <gingold@adacore.com>
+
+	* loader.h: Reorder declarations.
+	* x86-64.h: New file.
+	* external.h: New file.
+	* reloc.h: New file.
+
+2011-07-06  Tristan Gingold  <gingold@adacore.com>
+
+	* loader.h: New file.
+
+Copyright (C) 2011-2012 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.25/include/mach-o/arm.h b/binutils-2.25/include/mach-o/arm.h
new file mode 100644
index 00000000..f37ff77e
--- /dev/null
+++ b/binutils-2.25/include/mach-o/arm.h
@@ -0,0 +1,37 @@
+/* Mach-O arm declarations for BFD.
+   Copyright 2012
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _MACH_O_ARM_H
+#define _MACH_O_ARM_H
+
+/* ARM relocations.  */
+#define BFD_MACH_O_ARM_RELOC_VANILLA   0 /* Generic relocation.  */
+#define BFD_MACH_O_ARM_RELOC_PAIR      1 /* Second entry in a pair.  */
+#define BFD_MACH_O_ARM_RELOC_SECTDIFF  2 /* Substract with a PAIR.  */
+#define BFD_MACH_O_ARM_RELOC_LOCAL_SECTDIFF 3 /* Like above, but local ref.  */
+#define BFD_MACH_O_ARM_RELOC_PB_LA_PTR 4 /* Prebound lazy pointer.  */
+#define BFD_MACH_O_ARM_RELOC_BR24      5 /* 24bit branch.  */
+#define BFD_MACH_O_THUMB_RELOC_BR22    6 /* 22bit branch.  */
+#define BFD_MACH_O_THUMB_32BIT_BRANCH  7 /* Obselete.  */
+#define BFD_MACH_O_ARM_RELOC_HALF      8
+#define BFD_MACH_O_ARM_RELOC_HALF_SECTDIFF 9
+
+#endif /* _MACH_O_ARM_H */
diff --git a/binutils-2.25/include/mach-o/codesign.h b/binutils-2.25/include/mach-o/codesign.h
new file mode 100644
index 00000000..ee2f792a
--- /dev/null
+++ b/binutils-2.25/include/mach-o/codesign.h
@@ -0,0 +1,85 @@
+/* Mach-O support for BFD.
+   Copyright 2011
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _MACH_O_CODESIGN_H
+#define _MACH_O_CODESIGN_H
+
+/* Codesign blob magics.  */
+
+/* Superblob containing all the components.  */
+#define BFD_MACH_O_CS_MAGIC_EMBEDDED_SIGNATURE 0xfade0cc0
+
+/* Individual code requirement.  */
+#define BFD_MACH_O_CS_MAGIC_REQUIREMENT 0xfade0c00
+
+/* Collection of code requirements, indexed by type.  */
+#define BFD_MACH_O_CS_MAGIC_REQUIREMENTS 0xfade0c01
+
+/* Directory.  */
+#define BFD_MACH_O_CS_MAGIC_CODEDIRECTORY 0xfade0c02
+
+/* Entitlements blob.  */
+#define BFD_MACH_O_CS_MAGIC_EMBEDDED_ENTITLEMENTS 0xfade7171
+
+/* Blob container.  */
+#define BFD_MACH_O_CS_MAGIC_BLOB_WRAPPER 0xfade0b01
+
+struct mach_o_codesign_codedirectory_external_v1
+{
+  /* All the fields are in network byte order (big endian).  */
+  unsigned char version[4];
+  unsigned char flags[4];
+  unsigned char hash_offset[4];
+  unsigned char ident_offset[4];
+  unsigned char nbr_special_slots[4];
+  unsigned char nbr_code_slots[4];
+  unsigned char code_limit[4];
+  unsigned char hash_size[1];
+  unsigned char hash_type[1];
+  unsigned char spare1[1];
+  unsigned char page_size[1];
+  unsigned char spare2[4];
+};
+
+struct mach_o_codesign_codedirectory_v1
+{
+  unsigned int version;
+  unsigned int flags;
+  unsigned int hash_offset;
+  unsigned int ident_offset;
+  unsigned int nbr_special_slots;
+  unsigned int nbr_code_slots;
+  unsigned int code_limit;
+  unsigned char hash_size;
+  unsigned char hash_type;
+  unsigned char spare1;
+  unsigned char page_size;
+  unsigned int spare2;
+};
+
+/* Value for hash_type.  */
+#define BFD_MACH_O_CS_NO_HASH 0
+#define BFD_MACH_O_CS_HASH_SHA1 1
+#define BFD_MACH_O_CS_HASH_SHA256 2
+#define BFD_MACH_O_CS_HASH_PRESTANDARD_SKEIN_160x256 32 /* Skein, 160 bits */
+#define BFD_MACH_O_CS_HASH_PRESTANDARD_SKEIN_256x512 33 /* Skein, 256 bits */
+
+#endif /* _MACH_O_CODESIGN_H */
diff --git a/binutils-2.25/include/mach-o/external.h b/binutils-2.25/include/mach-o/external.h
new file mode 100644
index 00000000..4b0a83e8
--- /dev/null
+++ b/binutils-2.25/include/mach-o/external.h
@@ -0,0 +1,348 @@
+/* Mach-O support for BFD.
+   Copyright 2011, 2012
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _MACH_O_EXTERNAL_H
+#define _MACH_O_EXTERNAL_H
+
+struct mach_o_header_external
+{
+  unsigned char magic[4];	/* Magic number.  */
+  unsigned char cputype[4];	/* CPU that this object is for.  */
+  unsigned char cpusubtype[4];	/* CPU subtype.  */
+  unsigned char filetype[4];	/* Type of file.  */
+  unsigned char ncmds[4];	/* Number of load commands.  */
+  unsigned char sizeofcmds[4];	/* Total size of load commands.  */
+  unsigned char flags[4];	/* Flags.  */
+  unsigned char reserved[4];	/* Reserved (on 64-bit version only).  */
+};
+
+#define BFD_MACH_O_HEADER_SIZE 28
+#define BFD_MACH_O_HEADER_64_SIZE 32
+
+/* 32-bit section header.  */
+
+struct mach_o_section_32_external
+{
+  unsigned char sectname[16];   /* Section name.  */
+  unsigned char segname[16];    /* Segment that the section belongs to.  */
+  unsigned char addr[4];        /* Address of this section in memory.  */
+  unsigned char size[4];        /* Size in bytes of this section.  */
+  unsigned char offset[4];      /* File offset of this section.  */
+  unsigned char align[4];       /* log2 of this section's alignment.  */
+  unsigned char reloff[4];      /* File offset of this section's relocs.  */
+  unsigned char nreloc[4];      /* Number of relocs for this section.  */
+  unsigned char flags[4];       /* Section flags/attributes.  */
+  unsigned char reserved1[4];
+  unsigned char reserved2[4];
+};
+#define BFD_MACH_O_SECTION_SIZE 68
+
+/* 64-bit section header.  */
+
+struct mach_o_section_64_external
+{
+  unsigned char sectname[16];   /* Section name.  */
+  unsigned char segname[16];    /* Segment that the section belongs to.  */
+  unsigned char addr[8];        /* Address of this section in memory.  */
+  unsigned char size[8];        /* Size in bytes of this section.  */
+  unsigned char offset[4];      /* File offset of this section.  */
+  unsigned char align[4];       /* log2 of this section's alignment.  */
+  unsigned char reloff[4];      /* File offset of this section's relocs.  */
+  unsigned char nreloc[4];      /* Number of relocs for this section.  */
+  unsigned char flags[4];       /* Section flags/attributes.  */
+  unsigned char reserved1[4];
+  unsigned char reserved2[4];
+  unsigned char reserved3[4];
+};
+#define BFD_MACH_O_SECTION_64_SIZE 80
+
+struct mach_o_load_command_external
+{
+  unsigned char cmd[4];         /* The type of load command.  */
+  unsigned char cmdsize[4];     /* Size in bytes of entire command.  */
+};
+#define BFD_MACH_O_LC_SIZE 8
+
+struct mach_o_segment_command_32_external
+{
+  unsigned char segname[16];    /* Name of this segment.  */
+  unsigned char vmaddr[4];      /* Virtual memory address of this segment.  */
+  unsigned char vmsize[4];      /* Size there, in bytes.  */
+  unsigned char fileoff[4];     /* Offset in bytes of the data to be mapped.  */
+  unsigned char filesize[4];    /* Size in bytes on disk.  */
+  unsigned char maxprot[4];     /* Maximum permitted vm protection.  */
+  unsigned char initprot[4];    /* Initial vm protection.  */
+  unsigned char nsects[4];      /* Number of sections in this segment.  */
+  unsigned char flags[4];       /* Flags that affect the loading.  */
+};
+#define BFD_MACH_O_LC_SEGMENT_SIZE 56 /* Include the header.  */
+
+struct mach_o_segment_command_64_external
+{
+  unsigned char segname[16];    /* Name of this segment.  */
+  unsigned char vmaddr[8];      /* Virtual memory address of this segment.  */
+  unsigned char vmsize[8];      /* Size there, in bytes.  */
+  unsigned char fileoff[8];     /* Offset in bytes of the data to be mapped.  */
+  unsigned char filesize[8];    /* Size in bytes on disk.  */
+  unsigned char maxprot[4];     /* Maximum permitted vm protection.  */
+  unsigned char initprot[4];    /* Initial vm protection.  */
+  unsigned char nsects[4];      /* Number of sections in this segment.  */
+  unsigned char flags[4];       /* Flags that affect the loading.  */
+};
+#define BFD_MACH_O_LC_SEGMENT_64_SIZE 72 /* Include the header.  */
+
+struct mach_o_reloc_info_external
+{
+  unsigned char r_address[4];
+  unsigned char r_symbolnum[4];
+};
+#define BFD_MACH_O_RELENT_SIZE 8
+
+/* Relocations are based on 'address' being a section offset and an assumption
+   that sections are never more than 2^24-1 bytes in size.  Relocation data
+   also carry information on type/size/PC-relative/extern and whether scattered
+   or not [stored in the MSB of the r_address].  */
+
+#define BFD_MACH_O_SR_SCATTERED		0x80000000
+
+/* For a non-scattered reloc, the relocation info is found in r_symbolnum.
+   Bytes 1 to 3 contain the symbol number (0xffffff, in a non-scattered PAIR).
+   Byte 4 contains the relocation info - but with differing bit-positions
+   dependent on target endian-ness - as below.  */
+
+#define BFD_MACH_O_LE_PCREL		0x01
+#define BFD_MACH_O_LE_LENGTH_SHIFT	1
+#define BFD_MACH_O_LE_EXTERN		0x08
+#define BFD_MACH_O_LE_TYPE_SHIFT	4
+
+#define BFD_MACH_O_BE_PCREL		0x80
+#define BFD_MACH_O_BE_LENGTH_SHIFT	5
+#define BFD_MACH_O_BE_EXTERN		0x10
+#define BFD_MACH_O_BE_TYPE_SHIFT	0
+
+/* The field sizes are the same for both BE and LE.  */
+#define BFD_MACH_O_LENGTH_MASK		0x03
+#define BFD_MACH_O_TYPE_MASK		0x0f
+
+/* For a scattered reloc entry the info is contained in r_address.  There
+   is no need to discriminate on target endian-ness, since the design was
+   arranged to produce the same layout on both.  Scattered relocations are
+   only used for local items, therefore there is no 'extern' field.  */
+
+#define BFD_MACH_O_SR_PCREL		0x40000000
+#define BFD_MACH_O_GET_SR_LENGTH(s)	(((s) >> 28) & 0x3)
+#define BFD_MACH_O_GET_SR_TYPE(s)	(((s) >> 24) & 0x0f)
+#define BFD_MACH_O_GET_SR_ADDRESS(s)	((s) & 0x00ffffff)
+#define BFD_MACH_O_SET_SR_LENGTH(l)	(((l) & 0x3) << 28)
+#define BFD_MACH_O_SET_SR_TYPE(t)	(((t) & 0xf) << 24)
+#define BFD_MACH_O_SET_SR_ADDRESS(s)	((s) & 0x00ffffff)
+
+struct mach_o_symtab_command_external
+{
+  unsigned char symoff[4];	/* File offset of the symbol table.  */
+  unsigned char nsyms[4];	/* Number of symbols.  */
+  unsigned char stroff[4];	/* File offset of the string table.  */
+  unsigned char strsize[4];	/* String table size.  */
+};
+
+struct mach_o_nlist_external
+{
+  unsigned char n_strx[4];
+  unsigned char n_type[1];
+  unsigned char n_sect[1];
+  unsigned char n_desc[2];
+  unsigned char n_value[4];
+};
+#define BFD_MACH_O_NLIST_SIZE 12
+
+struct mach_o_nlist_64_external
+{
+  unsigned char n_strx[4];
+  unsigned char n_type[1];
+  unsigned char n_sect[1];
+  unsigned char n_desc[2];
+  unsigned char n_value[8];
+};
+#define BFD_MACH_O_NLIST_64_SIZE 16
+
+struct mach_o_thread_command_external
+{
+  unsigned char flavour[4];
+  unsigned char count[4];
+};
+
+/* For commands that just have a string or a path.  */
+struct mach_o_str_command_external
+{
+  unsigned char str[4];
+};
+
+struct mach_o_dylib_command_external
+{
+  unsigned char name[4];
+  unsigned char timestamp[4];
+  unsigned char current_version[4];
+  unsigned char compatibility_version[4];
+};
+
+struct mach_o_dysymtab_command_external
+{
+  unsigned char ilocalsym[4];	/* Index of.  */
+  unsigned char nlocalsym[4];	/* Number of.  */
+  unsigned char iextdefsym[4];
+  unsigned char nextdefsym[4];
+  unsigned char iundefsym[4];
+  unsigned char nundefsym[4];
+  unsigned char tocoff[4];
+  unsigned char ntoc[4];
+  unsigned char modtaboff[4];
+  unsigned char nmodtab[4];
+  unsigned char extrefsymoff[4];
+  unsigned char nextrefsyms[4];
+  unsigned char indirectsymoff[4];
+  unsigned char nindirectsyms[4];
+  unsigned char extreloff[4];
+  unsigned char nextrel[4];
+  unsigned char locreloff[4];
+  unsigned char nlocrel[4];
+};
+
+struct mach_o_dylib_module_external
+{
+  unsigned char module_name[4];
+  unsigned char iextdefsym[4];
+  unsigned char nextdefsym[4];
+  unsigned char irefsym[4];
+  unsigned char nrefsym[4];
+  unsigned char ilocalsym[4];
+  unsigned char nlocalsym[4];
+  unsigned char iextrel[4];
+  unsigned char nextrel[4];
+  unsigned char iinit_iterm[4];
+  unsigned char ninit_nterm[4];
+  unsigned char objc_module_info_addr[4];
+  unsigned char objc_module_info_size[4];
+};
+#define BFD_MACH_O_DYLIB_MODULE_SIZE 52
+
+struct mach_o_dylib_module_64_external
+{
+  unsigned char module_name[4];
+  unsigned char iextdefsym[4];
+  unsigned char nextdefsym[4];
+  unsigned char irefsym[4];
+  unsigned char nrefsym[4];
+  unsigned char ilocalsym[4];
+  unsigned char nlocalsym[4];
+  unsigned char iextrel[4];
+  unsigned char nextrel[4];
+  unsigned char iinit_iterm[4];
+  unsigned char ninit_nterm[4];
+  unsigned char objc_module_info_size[4];
+  unsigned char objc_module_info_addr[8];
+};
+#define BFD_MACH_O_DYLIB_MODULE_64_SIZE 56
+
+struct mach_o_dylib_table_of_contents_external
+{
+  unsigned char symbol_index[4];
+  unsigned char module_index[4];
+};
+#define BFD_MACH_O_TABLE_OF_CONTENT_SIZE 8
+
+struct mach_o_linkedit_data_command_external
+{
+  unsigned char dataoff[4];
+  unsigned char datasize[4];
+};
+
+struct mach_o_dyld_info_command_external
+{
+  unsigned char rebase_off[4];
+  unsigned char rebase_size[4];
+  unsigned char bind_off[4];
+  unsigned char bind_size[4];
+  unsigned char weak_bind_off[4];
+  unsigned char weak_bind_size[4];
+  unsigned char lazy_bind_off[4];
+  unsigned char lazy_bind_size[4];
+  unsigned char export_off[4];
+  unsigned char export_size[4];
+};
+
+struct mach_o_version_min_command_external
+{
+  unsigned char version[4];
+  unsigned char reserved[4];
+};
+
+struct mach_o_encryption_info_command_external
+{
+  unsigned char cryptoff[4];	/* File offset of the encrypted area.  */
+  unsigned char cryptsize[4];	/* Size of the encrypted area.  */
+  unsigned char cryptid[4];	/* Encryption method.  */
+};
+
+struct mach_o_fvmlib_command_external
+{
+  unsigned char name[4];	/* Offset of the name.  */
+  unsigned char minor_version[4];
+  unsigned char header_addr[4];
+};
+
+struct mach_o_entry_point_command_external
+{
+  unsigned char entryoff[8];	/* File offset of the entry point.  */
+  unsigned char stacksize[8];   /* Initial stack size, if no null.  */
+};
+
+struct mach_o_source_version_command_external
+{
+  unsigned char version[8];	/* Version A.B.C.D.E, with 10 bits for B-E,
+				   and 24 bits for A.  */
+};
+
+/* The LD_DATA_IN_CODE command use a linkedit_data_command that points to
+   a table of entries.  */
+
+struct mach_o_data_in_code_entry_external
+{
+  unsigned char offset[4];	/* Offset from the mach_header. */
+  unsigned char length[2];	/* Number of bytes.  */
+  unsigned char kind[2];	/* Kind.  See BFD_MACH_O_DICE_ values.  */
+};
+
+struct mach_o_fat_header_external
+{
+  unsigned char magic[4];
+  unsigned char nfat_arch[4];	/* Number of components.  */
+};
+
+struct mach_o_fat_arch_external
+{
+  unsigned char cputype[4];
+  unsigned char cpusubtype[4];
+  unsigned char offset[4];	/* File offset of the member.  */
+  unsigned char size[4];	/* Size of the member.  */
+  unsigned char align[4];	/* Power of 2.  */
+};
+
+#endif /* _MACH_O_EXTERNAL_H */
diff --git a/binutils-2.25/include/mach-o/loader.h b/binutils-2.25/include/mach-o/loader.h
new file mode 100644
index 00000000..952bc8f4
--- /dev/null
+++ b/binutils-2.25/include/mach-o/loader.h
@@ -0,0 +1,378 @@
+/* Mach-O support for BFD.
+   Copyright 2011, 2012
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _MACH_O_LOADER_H
+#define _MACH_O_LOADER_H
+
+/* Constants for header. */
+
+typedef enum bfd_mach_o_mach_header_magic
+{
+  BFD_MACH_O_MH_MAGIC    = 0xfeedface,
+  BFD_MACH_O_MH_CIGAM    = 0xcefaedfe,
+  BFD_MACH_O_MH_MAGIC_64 = 0xfeedfacf,
+  BFD_MACH_O_MH_CIGAM_64 = 0xcffaedfe
+}
+bfd_mach_o_mach_header_magic;
+
+#define BFD_MACH_O_CPU_IS64BIT 0x1000000
+
+typedef enum bfd_mach_o_cpu_type
+{
+  BFD_MACH_O_CPU_TYPE_VAX = 1,
+  BFD_MACH_O_CPU_TYPE_MC680x0 = 6,
+  BFD_MACH_O_CPU_TYPE_I386 = 7,
+  BFD_MACH_O_CPU_TYPE_MIPS = 8,
+  BFD_MACH_O_CPU_TYPE_MC98000 = 10,
+  BFD_MACH_O_CPU_TYPE_HPPA = 11,
+  BFD_MACH_O_CPU_TYPE_ARM = 12,
+  BFD_MACH_O_CPU_TYPE_MC88000 = 13,
+  BFD_MACH_O_CPU_TYPE_SPARC = 14,
+  BFD_MACH_O_CPU_TYPE_I860 = 15,
+  BFD_MACH_O_CPU_TYPE_ALPHA = 16,
+  BFD_MACH_O_CPU_TYPE_POWERPC = 18,
+  BFD_MACH_O_CPU_TYPE_POWERPC_64 = (BFD_MACH_O_CPU_TYPE_POWERPC | BFD_MACH_O_CPU_IS64BIT),
+  BFD_MACH_O_CPU_TYPE_X86_64 = (BFD_MACH_O_CPU_TYPE_I386 | BFD_MACH_O_CPU_IS64BIT)
+}
+bfd_mach_o_cpu_type;
+
+typedef enum bfd_mach_o_cpu_subtype
+{
+  /* i386.  */
+  BFD_MACH_O_CPU_SUBTYPE_X86_ALL = 3,
+
+  /* arm.  */
+  BFD_MACH_O_CPU_SUBTYPE_ARM_ALL = 0,
+  BFD_MACH_O_CPU_SUBTYPE_ARM_V4T = 5,
+  BFD_MACH_O_CPU_SUBTYPE_ARM_V6 = 6,
+  BFD_MACH_O_CPU_SUBTYPE_ARM_V5TEJ = 7,
+  BFD_MACH_O_CPU_SUBTYPE_ARM_XSCALE = 8,
+  BFD_MACH_O_CPU_SUBTYPE_ARM_V7 = 9
+}
+bfd_mach_o_cpu_subtype;
+
+typedef enum bfd_mach_o_filetype
+{
+  BFD_MACH_O_MH_OBJECT      = 0x01,
+  BFD_MACH_O_MH_EXECUTE     = 0x02,
+  BFD_MACH_O_MH_FVMLIB      = 0x03,
+  BFD_MACH_O_MH_CORE        = 0x04,
+  BFD_MACH_O_MH_PRELOAD     = 0x05,
+  BFD_MACH_O_MH_DYLIB       = 0x06,
+  BFD_MACH_O_MH_DYLINKER    = 0x07,
+  BFD_MACH_O_MH_BUNDLE      = 0x08,
+  BFD_MACH_O_MH_DYLIB_STUB  = 0x09,
+  BFD_MACH_O_MH_DSYM        = 0x0a,
+  BFD_MACH_O_MH_KEXT_BUNDLE = 0x0b
+}
+bfd_mach_o_filetype;
+
+typedef enum bfd_mach_o_header_flags
+{
+  BFD_MACH_O_MH_NOUNDEFS		= 0x0000001,
+  BFD_MACH_O_MH_INCRLINK		= 0x0000002,
+  BFD_MACH_O_MH_DYLDLINK		= 0x0000004,
+  BFD_MACH_O_MH_BINDATLOAD		= 0x0000008,
+  BFD_MACH_O_MH_PREBOUND		= 0x0000010,
+  BFD_MACH_O_MH_SPLIT_SEGS		= 0x0000020,
+  BFD_MACH_O_MH_LAZY_INIT		= 0x0000040,
+  BFD_MACH_O_MH_TWOLEVEL		= 0x0000080,
+  BFD_MACH_O_MH_FORCE_FLAT		= 0x0000100,
+  BFD_MACH_O_MH_NOMULTIDEFS		= 0x0000200,
+  BFD_MACH_O_MH_NOFIXPREBINDING		= 0x0000400,
+  BFD_MACH_O_MH_PREBINDABLE		= 0x0000800,
+  BFD_MACH_O_MH_ALLMODSBOUND		= 0x0001000,
+  BFD_MACH_O_MH_SUBSECTIONS_VIA_SYMBOLS = 0x0002000,
+  BFD_MACH_O_MH_CANONICAL		= 0x0004000,
+  BFD_MACH_O_MH_WEAK_DEFINES		= 0x0008000,
+  BFD_MACH_O_MH_BINDS_TO_WEAK		= 0x0010000,
+  BFD_MACH_O_MH_ALLOW_STACK_EXECUTION	= 0x0020000,
+  BFD_MACH_O_MH_ROOT_SAFE		= 0x0040000,
+  BFD_MACH_O_MH_SETUID_SAFE		= 0x0080000,
+  BFD_MACH_O_MH_NO_REEXPORTED_DYLIBS	= 0x0100000,
+  BFD_MACH_O_MH_PIE			= 0x0200000,
+  BFD_MACH_O_MH_DEAD_STRIPPABLE_DYLIB   = 0x0400000,
+  BFD_MACH_O_MH_HAS_TLV_DESCRIPTORS     = 0x0800000,
+  BFD_MACH_O_MH_NO_HEAP_EXECUTION       = 0x1000000
+}
+bfd_mach_o_header_flags;
+
+/* Load command constants.  */
+#define BFD_MACH_O_LC_REQ_DYLD 0x80000000
+
+typedef enum bfd_mach_o_load_command_type
+{
+  BFD_MACH_O_LC_SEGMENT = 0x1,		/* File segment to be mapped.  */
+  BFD_MACH_O_LC_SYMTAB = 0x2,		/* Link-edit stab symbol table info (obsolete).  */
+  BFD_MACH_O_LC_SYMSEG = 0x3,		/* Link-edit gdb symbol table info.  */
+  BFD_MACH_O_LC_THREAD = 0x4,		/* Thread.  */
+  BFD_MACH_O_LC_UNIXTHREAD = 0x5,	/* UNIX thread (includes a stack).  */
+  BFD_MACH_O_LC_LOADFVMLIB = 0x6,	/* Load a fixed VM shared library.  */
+  BFD_MACH_O_LC_IDFVMLIB = 0x7,		/* Fixed VM shared library id.  */
+  BFD_MACH_O_LC_IDENT = 0x8,		/* Object identification information (obsolete).  */
+  BFD_MACH_O_LC_FVMFILE = 0x9,		/* Fixed VM file inclusion.  */
+  BFD_MACH_O_LC_PREPAGE = 0xa,		/* Prepage command (internal use).  */
+  BFD_MACH_O_LC_DYSYMTAB = 0xb,		/* Dynamic link-edit symbol table info.  */
+  BFD_MACH_O_LC_LOAD_DYLIB = 0xc,	/* Load a dynamically linked shared library.  */
+  BFD_MACH_O_LC_ID_DYLIB = 0xd,		/* Dynamically linked shared lib identification.  */
+  BFD_MACH_O_LC_LOAD_DYLINKER = 0xe,	/* Load a dynamic linker.  */
+  BFD_MACH_O_LC_ID_DYLINKER = 0xf,	/* Dynamic linker identification.  */
+  BFD_MACH_O_LC_PREBOUND_DYLIB = 0x10,	/* Modules prebound for a dynamically.  */
+  BFD_MACH_O_LC_ROUTINES = 0x11,	/* Image routines.  */
+  BFD_MACH_O_LC_SUB_FRAMEWORK = 0x12,	/* Sub framework.  */
+  BFD_MACH_O_LC_SUB_UMBRELLA = 0x13,	/* Sub umbrella.  */
+  BFD_MACH_O_LC_SUB_CLIENT = 0x14,	/* Sub client.  */
+  BFD_MACH_O_LC_SUB_LIBRARY = 0x15,   	/* Sub library.  */
+  BFD_MACH_O_LC_TWOLEVEL_HINTS = 0x16,	/* Two-level namespace lookup hints.  */
+  BFD_MACH_O_LC_PREBIND_CKSUM = 0x17, 	/* Prebind checksum.  */
+  /* Load a dynamically linked shared library that is allowed to be
+       missing (weak).  */
+  BFD_MACH_O_LC_LOAD_WEAK_DYLIB = 0x18,
+  BFD_MACH_O_LC_SEGMENT_64 = 0x19,	/* 64-bit segment of this file to be
+                                           mapped.  */
+  BFD_MACH_O_LC_ROUTINES_64 = 0x1a,     /* Address of the dyld init routine
+                                           in a dylib.  */
+  BFD_MACH_O_LC_UUID = 0x1b,            /* 128-bit UUID of the executable.  */
+  BFD_MACH_O_LC_RPATH = 0x1c,		/* Run path addiions.  */
+  BFD_MACH_O_LC_CODE_SIGNATURE = 0x1d,	/* Local of code signature.  */
+  BFD_MACH_O_LC_SEGMENT_SPLIT_INFO = 0x1e, /* Local of info to split seg.  */
+  BFD_MACH_O_LC_REEXPORT_DYLIB = 0x1f,  /* Load and re-export lib.  */
+  BFD_MACH_O_LC_LAZY_LOAD_DYLIB = 0x20, /* Delay load of lib until use.  */
+  BFD_MACH_O_LC_ENCRYPTION_INFO = 0x21, /* Encrypted segment info.  */
+  BFD_MACH_O_LC_DYLD_INFO = 0x22,	/* Compressed dyld information.  */
+  BFD_MACH_O_LC_LOAD_UPWARD_DYLIB = 0x23, /* Load upward dylib.  */
+  BFD_MACH_O_LC_VERSION_MIN_MACOSX = 0x24,   /* Minimal MacOSX version.  */
+  BFD_MACH_O_LC_VERSION_MIN_IPHONEOS = 0x25, /* Minimal IOS version.  */
+  BFD_MACH_O_LC_FUNCTION_STARTS = 0x26,  /* Compressed table of func start.  */
+  BFD_MACH_O_LC_DYLD_ENVIRONMENT = 0x27, /* Env variable string for dyld.  */
+  BFD_MACH_O_LC_MAIN = 0x28,             /* Entry point.  */
+  BFD_MACH_O_LC_DATA_IN_CODE = 0x29,     /* Table of non-instructions.  */
+  BFD_MACH_O_LC_SOURCE_VERSION = 0x2a,   /* Source version.  */
+  BFD_MACH_O_LC_DYLIB_CODE_SIGN_DRS = 0x2b /* DRs from dylibs.  */
+}
+bfd_mach_o_load_command_type;
+
+/* Section constants.  */
+/* Constants for the type of a section.  */
+
+typedef enum bfd_mach_o_section_type
+{
+  /* Regular section.  */
+  BFD_MACH_O_S_REGULAR = 0x0,
+
+  /* Zero fill on demand section.  */
+  BFD_MACH_O_S_ZEROFILL = 0x1,
+
+  /* Section with only literal C strings.  */
+  BFD_MACH_O_S_CSTRING_LITERALS = 0x2,
+
+  /* Section with only 4 byte literals.  */
+  BFD_MACH_O_S_4BYTE_LITERALS = 0x3,
+
+  /* Section with only 8 byte literals.  */
+  BFD_MACH_O_S_8BYTE_LITERALS = 0x4,
+
+  /* Section with only pointers to literals.  */
+  BFD_MACH_O_S_LITERAL_POINTERS = 0x5,
+
+  /* For the two types of symbol pointers sections and the symbol stubs
+     section they have indirect symbol table entries.  For each of the
+     entries in the section the indirect symbol table entries, in
+     corresponding order in the indirect symbol table, start at the index
+     stored in the reserved1 field of the section structure.  Since the
+     indirect symbol table entries correspond to the entries in the
+     section the number of indirect symbol table entries is inferred from
+     the size of the section divided by the size of the entries in the
+     section.  For symbol pointers sections the size of the entries in
+     the section is 4 bytes and for symbol stubs sections the byte size
+     of the stubs is stored in the reserved2 field of the section
+     structure.  */
+
+  /* Section with only non-lazy symbol pointers.  */
+  BFD_MACH_O_S_NON_LAZY_SYMBOL_POINTERS = 0x6,
+
+  /* Section with only lazy symbol pointers.  */
+  BFD_MACH_O_S_LAZY_SYMBOL_POINTERS = 0x7,
+
+  /* Section with only symbol stubs, byte size of stub in the reserved2
+     field.  */
+  BFD_MACH_O_S_SYMBOL_STUBS = 0x8,
+
+  /* Section with only function pointers for initialization.  */
+  BFD_MACH_O_S_MOD_INIT_FUNC_POINTERS = 0x9,
+
+  /* Section with only function pointers for termination.  */
+  BFD_MACH_O_S_MOD_FINI_FUNC_POINTERS = 0xa,
+
+  /* Section contains symbols that are coalesced by the linkers.  */
+  BFD_MACH_O_S_COALESCED = 0xb,
+
+  /* Zero fill on demand section (possibly larger than 4 GB).  */
+  BFD_MACH_O_S_GB_ZEROFILL = 0xc,
+
+  /* Section with only pairs of function pointers for interposing.  */
+  BFD_MACH_O_S_INTERPOSING = 0xd,
+
+  /* Section with only 16 byte literals.  */
+  BFD_MACH_O_S_16BYTE_LITERALS = 0xe,
+
+  /* Section contains DTrace Object Format.  */
+  BFD_MACH_O_S_DTRACE_DOF = 0xf,
+
+  /* Section with only lazy symbol pointers to lazy loaded dylibs.  */
+  BFD_MACH_O_S_LAZY_DYLIB_SYMBOL_POINTERS = 0x10
+}
+bfd_mach_o_section_type;
+
+/* The flags field of a section structure is separated into two parts a section
+   type and section attributes.  The section types are mutually exclusive (it
+   can only have one type) but the section attributes are not (it may have more
+   than one attribute).  */
+
+#define BFD_MACH_O_SECTION_TYPE_MASK        0x000000ff
+
+/* Constants for the section attributes part of the flags field of a section
+   structure.  */
+#define BFD_MACH_O_SECTION_ATTRIBUTES_MASK  0xffffff00
+/* System setable attributes.  */
+#define BFD_MACH_O_SECTION_ATTRIBUTES_SYS   0x00ffff00
+/* User attributes.  */
+#define BFD_MACH_O_SECTION_ATTRIBUTES_USR   0xff000000
+
+typedef enum bfd_mach_o_section_attribute
+{
+  /* Section has no specified attibutes.  */
+  BFD_MACH_O_S_ATTR_NONE              = 0,
+
+  /* Section has local relocation entries.  */
+  BFD_MACH_O_S_ATTR_LOC_RELOC         = 0x00000100,
+
+  /* Section has external relocation entries.  */
+  BFD_MACH_O_S_ATTR_EXT_RELOC         = 0x00000200,
+
+  /* Section contains some machine instructions.  */
+  BFD_MACH_O_S_ATTR_SOME_INSTRUCTIONS = 0x00000400,
+
+  /* A debug section.  */
+  BFD_MACH_O_S_ATTR_DEBUG             = 0x02000000,
+
+  /* Used with i386 stubs.  */
+  BFD_MACH_O_S_SELF_MODIFYING_CODE    = 0x04000000,
+
+  /* Blocks are live if they reference live blocks.  */
+  BFD_MACH_O_S_ATTR_LIVE_SUPPORT      = 0x08000000,
+
+  /* No dead stripping.  */
+  BFD_MACH_O_S_ATTR_NO_DEAD_STRIP     = 0x10000000,
+
+  /* Section symbols can be stripped in files with MH_DYLDLINK flag.  */
+  BFD_MACH_O_S_ATTR_STRIP_STATIC_SYMS = 0x20000000,
+
+  /* Section contains coalesced symbols that are not to be in the TOC of an
+     archive.  */
+  BFD_MACH_O_S_ATTR_NO_TOC            = 0x40000000,
+
+  /* Section contains only true machine instructions.  */
+  BFD_MACH_O_S_ATTR_PURE_INSTRUCTIONS = 0x80000000
+}
+bfd_mach_o_section_attribute;
+
+/* Symbol constants.  */
+
+/* Symbol n_type values.  */
+#define BFD_MACH_O_N_STAB  0xe0	/* If any of these bits set, a symbolic debugging entry.  */
+#define BFD_MACH_O_N_PEXT  0x10	/* Private external symbol bit.  */
+#define BFD_MACH_O_N_TYPE  0x0e	/* Mask for the type bits.  */
+#define BFD_MACH_O_N_EXT   0x01	/* External symbol bit, set for external symbols.  */
+#define BFD_MACH_O_N_UNDF  0x00	/* Undefined, n_sect == NO_SECT.  */
+#define BFD_MACH_O_N_ABS   0x02	/* Absolute, n_sect == NO_SECT.  */
+#define BFD_MACH_O_N_INDR  0x0a	/* Indirect.  */
+#define BFD_MACH_O_N_PBUD  0x0c /* Prebound undefined (defined in a dylib).  */
+#define BFD_MACH_O_N_SECT  0x0e	/* Defined in section number n_sect.  */
+
+#define BFD_MACH_O_NO_SECT 0	/* Symbol not in any section of the image.  */
+
+/* Symbol n_desc reference flags.  */
+#define BFD_MACH_O_REFERENCE_MASK 				0x07
+#define BFD_MACH_O_REFERENCE_FLAG_UNDEFINED_NON_LAZY		0x00
+#define BFD_MACH_O_REFERENCE_FLAG_UNDEFINED_LAZY		0x01
+#define BFD_MACH_O_REFERENCE_FLAG_DEFINED			0x02
+#define BFD_MACH_O_REFERENCE_FLAG_PRIVATE_DEFINED		0x03
+#define BFD_MACH_O_REFERENCE_FLAG_PRIVATE_UNDEFINED_NON_LAZY	0x04
+#define BFD_MACH_O_REFERENCE_FLAG_PRIVATE_UNDEFINED_LAZY	0x05
+
+#define BFD_MACH_O_REFERENCED_DYNAMICALLY			0x10
+#define BFD_MACH_O_N_DESC_DISCARDED				0x20
+#define BFD_MACH_O_N_NO_DEAD_STRIP				0x20
+#define BFD_MACH_O_N_WEAK_REF					0x40
+#define BFD_MACH_O_N_WEAK_DEF					0x80
+#define BFD_MACH_O_N_REF_TO_WEAK				0x80
+
+#define BFD_MACH_O_N_ARM_THUMB_DEF				0x08
+#define BFD_MACH_O_N_SYMBOL_RESOLVER				0x100
+
+#define BFD_MACH_O_INDIRECT_SYM_LOCAL			0x80000000
+#define BFD_MACH_O_INDIRECT_SYM_ABS			0x40000000
+
+/* Constants for DATA_IN_CODE entries.  */
+typedef enum bfd_mach_o_data_in_code_entry_kind
+{
+  BFD_MACH_O_DICE_KIND_DATA         = 0x0001, /* Data */
+  BFD_MACH_O_DICE_JUMP_TABLES8      = 0x0002, /* 1 byte jump tables.  */
+  BFD_MACH_O_DICE_JUMP_TABLES16     = 0x0003, /* 2 bytes.  */
+  BFD_MACH_O_DICE_JUMP_TABLES32     = 0x0004, /* 4 bytes.  */
+  BFD_MACH_O_DICE_ABS_JUMP_TABLES32 = 0x0005  /* Absolute jump table.  */
+} bfd_mach_o_data_in_code_entry_kind;
+
+/* Thread constants.  */
+
+typedef enum bfd_mach_o_ppc_thread_flavour
+{
+  BFD_MACH_O_PPC_THREAD_STATE      = 1,
+  BFD_MACH_O_PPC_FLOAT_STATE       = 2,
+  BFD_MACH_O_PPC_EXCEPTION_STATE   = 3,
+  BFD_MACH_O_PPC_VECTOR_STATE      = 4,
+  BFD_MACH_O_PPC_THREAD_STATE64    = 5,
+  BFD_MACH_O_PPC_EXCEPTION_STATE64 = 6,
+  BFD_MACH_O_PPC_THREAD_STATE_NONE = 7
+}
+bfd_mach_o_ppc_thread_flavour;
+
+/* Defined in <mach/i386/thread_status.h> */
+typedef enum bfd_mach_o_i386_thread_flavour
+{
+  BFD_MACH_O_x86_THREAD_STATE32    = 1,
+  BFD_MACH_O_x86_FLOAT_STATE32     = 2,
+  BFD_MACH_O_x86_EXCEPTION_STATE32 = 3,
+  BFD_MACH_O_x86_THREAD_STATE64    = 4,
+  BFD_MACH_O_x86_FLOAT_STATE64     = 5,
+  BFD_MACH_O_x86_EXCEPTION_STATE64 = 6,
+  BFD_MACH_O_x86_THREAD_STATE      = 7,
+  BFD_MACH_O_x86_FLOAT_STATE       = 8,
+  BFD_MACH_O_x86_EXCEPTION_STATE   = 9,
+  BFD_MACH_O_x86_DEBUG_STATE32     = 10,
+  BFD_MACH_O_x86_DEBUG_STATE64     = 11,
+  BFD_MACH_O_x86_DEBUG_STATE       = 12,
+  BFD_MACH_O_x86_THREAD_STATE_NONE = 13
+}
+bfd_mach_o_i386_thread_flavour;
+
+#endif /* _MACH_O_LOADER_H */
diff --git a/binutils-2.25/include/mach-o/reloc.h b/binutils-2.25/include/mach-o/reloc.h
new file mode 100644
index 00000000..bab31efe
--- /dev/null
+++ b/binutils-2.25/include/mach-o/reloc.h
@@ -0,0 +1,33 @@
+/* Mach-O support for BFD.
+   Copyright 2011, 2012
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _MACH_O_RELOC_H
+#define _MACH_O_RELOC_H
+
+/* Generic relocation types (used by i386).  */
+#define BFD_MACH_O_GENERIC_RELOC_VANILLA 	0
+#define BFD_MACH_O_GENERIC_RELOC_PAIR	 	1
+#define BFD_MACH_O_GENERIC_RELOC_SECTDIFF	2
+#define BFD_MACH_O_GENERIC_RELOC_PB_LA_PTR	3
+#define BFD_MACH_O_GENERIC_RELOC_LOCAL_SECTDIFF	4
+#define BFD_MACH_O_GENERIC_RELOC_TLV		5
+
+#endif /* _MACH_O_RELOC_H */
diff --git a/binutils-2.25/include/mach-o/x86-64.h b/binutils-2.25/include/mach-o/x86-64.h
new file mode 100644
index 00000000..d06bc26a
--- /dev/null
+++ b/binutils-2.25/include/mach-o/x86-64.h
@@ -0,0 +1,37 @@
+/* Mach-O support for BFD.
+   Copyright 2011
+   Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _MACH_O_X86_64_H
+#define _MACH_O_X86_64_H
+
+/* X86-64 relocations.  */
+#define BFD_MACH_O_X86_64_RELOC_UNSIGNED   0 /* Absolute addresses.  */
+#define BFD_MACH_O_X86_64_RELOC_SIGNED     1 /* 32-bit disp.  */
+#define BFD_MACH_O_X86_64_RELOC_BRANCH     2 /* 32-bit pcrel disp.  */
+#define BFD_MACH_O_X86_64_RELOC_GOT_LOAD   3 /* Movq load of a GOT entry.  */
+#define BFD_MACH_O_X86_64_RELOC_GOT        4 /* GOT reference.  */
+#define BFD_MACH_O_X86_64_RELOC_SUBTRACTOR 5 /* Symbol difference.  */
+#define BFD_MACH_O_X86_64_RELOC_SIGNED_1   6 /* 32-bit signed disp -1.  */
+#define BFD_MACH_O_X86_64_RELOC_SIGNED_2   7 /* 32-bit signed disp -2.  */
+#define BFD_MACH_O_X86_64_RELOC_SIGNED_4   8 /* 32-bit signed disp -4.  */
+#define BFD_MACH_O_X86_64_RELOC_TLV	   9 /* Thread local variables.  */
+
+#endif /* _MACH_O_X86_64_H */
diff --git a/binutils-2.25/include/md5.h b/binutils-2.25/include/md5.h
new file mode 100644
index 00000000..6da2fefe
--- /dev/null
+++ b/binutils-2.25/include/md5.h
@@ -0,0 +1,154 @@
+/* md5.h - Declaration of functions and data types used for MD5 sum
+   computing library functions.
+   Copyright 1995, 1996, 2000 Free Software Foundation, Inc.
+   NOTE: The canonical source of this file is maintained with the GNU C
+   Library.  Bugs can be reported to bug-glibc@prep.ai.mit.edu.
+
+   This program is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 2, or (at your option) any
+   later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _MD5_H
+#define _MD5_H 1
+
+#include <stdio.h>
+
+#if defined HAVE_LIMITS_H || _LIBC
+# include <limits.h>
+#endif
+
+#include "ansidecl.h"
+
+/* The following contortions are an attempt to use the C preprocessor
+   to determine an unsigned integral type that is 32 bits wide.  An
+   alternative approach is to use autoconf's AC_CHECK_SIZEOF macro, but
+   doing that would require that the configure script compile and *run*
+   the resulting executable.  Locally running cross-compiled executables
+   is usually not possible.  */
+
+#ifdef _LIBC
+# include <sys/types.h>
+typedef u_int32_t md5_uint32;
+typedef uintptr_t md5_uintptr;
+#elif defined (HAVE_SYS_TYPES_H) && defined (HAVE_STDINT_H)
+#include <stdint.h>
+#include <sys/types.h>
+typedef uint32_t md5_uint32;
+typedef uintptr_t md5_uintptr;
+#else
+#  define INT_MAX_32_BITS 2147483647
+
+/* If UINT_MAX isn't defined, assume it's a 32-bit type.
+   This should be valid for all systems GNU cares about because
+   that doesn't include 16-bit systems, and only modern systems
+   (that certainly have <limits.h>) have 64+-bit integral types.  */
+
+# ifndef INT_MAX
+#  define INT_MAX INT_MAX_32_BITS
+# endif
+
+# if INT_MAX == INT_MAX_32_BITS
+   typedef unsigned int md5_uint32;
+# else
+#  if SHRT_MAX == INT_MAX_32_BITS
+    typedef unsigned short md5_uint32;
+#  else
+#   if LONG_MAX == INT_MAX_32_BITS
+     typedef unsigned long md5_uint32;
+#   else
+     /* The following line is intended to evoke an error.
+        Using #error is not portable enough.  */
+     "Cannot determine unsigned 32-bit data type."
+#   endif
+#  endif
+# endif
+/* We have to make a guess about the integer type equivalent in size
+   to pointers which should always be correct.  */
+typedef unsigned long int md5_uintptr;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Structure to save state of computation between the single steps.  */
+struct md5_ctx
+{
+  md5_uint32 A;
+  md5_uint32 B;
+  md5_uint32 C;
+  md5_uint32 D;
+
+  md5_uint32 total[2];
+  md5_uint32 buflen;
+  char buffer[128] ATTRIBUTE_ALIGNED_ALIGNOF(md5_uint32);
+};
+
+/*
+ * The following three functions are build up the low level used in
+ * the functions `md5_stream' and `md5_buffer'.
+ */
+
+/* Initialize structure containing state of computation.
+   (RFC 1321, 3.3: Step 3)  */
+extern void md5_init_ctx (struct md5_ctx *ctx);
+
+/* Starting with the result of former calls of this function (or the
+   initialization function update the context for the next LEN bytes
+   starting at BUFFER.
+   It is necessary that LEN is a multiple of 64!!! */
+extern void md5_process_block (const void *buffer, size_t len,
+                               struct md5_ctx *ctx);
+
+/* Starting with the result of former calls of this function (or the
+   initialization function update the context for the next LEN bytes
+   starting at BUFFER.
+   It is NOT required that LEN is a multiple of 64.  */
+extern void md5_process_bytes (const void *buffer, size_t len,
+                               struct md5_ctx *ctx);
+
+/* Process the remaining bytes in the buffer and put result from CTX
+   in first 16 bytes following RESBUF.  The result is always in little
+   endian byte order, so that a byte-wise output yields to the wanted
+   ASCII representation of the message digest.
+
+   IMPORTANT: On some systems it is required that RESBUF is correctly
+   aligned for a 32 bits value.  */
+extern void *md5_finish_ctx (struct md5_ctx *ctx, void *resbuf);
+
+
+/* Put result from CTX in first 16 bytes following RESBUF.  The result is
+   always in little endian byte order, so that a byte-wise output yields
+   to the wanted ASCII representation of the message digest.
+
+   IMPORTANT: On some systems it is required that RESBUF is correctly
+   aligned for a 32 bits value.  */
+extern void *md5_read_ctx (const struct md5_ctx *ctx, void *resbuf);
+
+
+/* Compute MD5 message digest for bytes read from STREAM.  The
+   resulting message digest number will be written into the 16 bytes
+   beginning at RESBLOCK.  */
+extern int md5_stream (FILE *stream, void *resblock);
+
+/* Compute MD5 message digest for LEN bytes beginning at BUFFER.  The
+   result is always in little endian byte order, so that a byte-wise
+   output yields to the wanted ASCII representation of the message
+   digest.  */
+extern void *md5_buffer (const char *buffer, size_t len, void *resblock);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/binutils-2.25/include/nlm/ChangeLog b/binutils-2.25/include/nlm/ChangeLog
new file mode 100644
index 00000000..9d5f54b1
--- /dev/null
+++ b/binutils-2.25/include/nlm/ChangeLog
@@ -0,0 +1,119 @@
+2010-04-15  Nick Clifton  <nickc@redhat.com>
+
+	* alpha-ext.h: Update copyright notice to use GPLv3.
+	* common.h: Likewise.
+	* external.h: Likewise.
+	* i386-ext.h: Likewise.
+	* internal.h: Likewise.
+	* ppc-ext.h: Likewise.
+	* sparc32-ext.h: Likewise.
+
+2005-05-10  Nick Clifton  <nickc@redhat.com>
+
+	* Update the address and phone number of the FSF organization in
+	the GPL notices in the following files:
+	alpha-ext.h, common.h, external.h, i386-ext.h, internal.h,
+	ppc-ext.h, sparc32-ext.h
+
+2003-08-07  Alan Modra  <amodra@bigpond.net.au>
+
+	* internal.h (Nlm_Internal_Custom_Header): Replace PTR with void *.
+
+2001-10-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* common.h (NLM_CAT, NLM_CAT3): Don't define.
+	(NLM_CAT4): Update conditions under which this is defined.  Document
+	why CONCAT4 can't be used.
+
+1994-05-06  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* external.h (nlmNAME(External_Custom_Header)): Add length,
+	dataOffset, and dataStamp field.
+	(nlmNAME(External_Cygnus_Ext_Header)): Remove.
+	* internal.h (Nlm_Internal_Custom_Header): Add hdrLength,
+	dataOffset, dataStamp and hdr fields.
+
+1994-04-22  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* external.h (struct nlmNAME(external_cygnus_ext_header)): Rename
+	from nlmNAME(external_cygnus_section_header).  Change stamp field
+	to 8 bytes.  Add bytes field.
+	* internal.h (nlm_internal_cygnus_ext_header): Rename from
+	nlm_internal_cygnus_section_header.  Change stamp field to 8
+	bytes.
+
+1994-04-21  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* internal.h (struct nlm_internal_cygnus_section_header): Define.
+	* external.h (struct nlmNAME(external_cygnus_section_header):
+	Define.
+
+1994-04-20  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* internal.h (struct nlm_internal_custom_header): Remove
+	debugRecOffset and debugRecLength fields.  Add data field.
+	* external.h (struct nlmNAME(external_custom_header)): Remove
+	debugRecOffset and debugRecLength fields.
+
+1994-02-07  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* internal.h: Change HOST_64_BIT to BFD_HOST_64_BIT.
+
+1993-12-02  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* alpha-ext.h: New file describing formats of information in Alpha
+	NetWare files.
+	* common.h: Define some non-external Alpha information.
+
+1993-11-17  Sean Eric Fagan  (sef@cygnus.com)
+
+	* external.h: Don't define external_fixed_header here.
+	* i386-ext.h, sparc32-ext.h: New header files to define
+	external_fixed_header for particular CPU's.
+
+1993-10-27  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* internal.h (Nlm_Internal_Extended_Header): Added fields
+	sharedDebugRecordOffset and sharedDebugRecordCount.
+	* external.h (NlmNAME(External_Extended_Header)): Likewise.
+
+	* common.h (NLM_SIGNATURE): Do not define (it's different for each
+	backend).
+
+1993-08-31  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* internal.h: Change length fields of type char to type unsigned
+	char.
+
+1993-07-31  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* common.h (NLM_HIBIT, NLM_HEADER_VERSION): Define.
+
+1993-07-22  Fred Fish  (fnf@deneb.cygnus.com)
+
+	* common.h (NLM_CAT*, NLM_ARCH_SIZE, NLM_TARGET_LONG_SIZE,
+	NLM_TARGET_ADDRESS_SIZE, NLM_NAME, NlmNAME, nlmNAME):  New
+	macros.
+	* external.h (TARGET_LONG_SIZE, TARGET_ADDRESS_SIZE): Remove
+	macros, convert usages to NLM_ equivalents.
+	* external.h:  Use nlmNAME and NlmNAME macros to derive both
+	32 and 64 bit versions.
+
+1993-07-20  Fred Fish  (fnf@deneb.cygnus.com)
+
+	* (common.h, external.h, internal.h):  New files for NLM/NetWare
+	support.
+
+
+Copyright (C) 1993-2012 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.25/include/nlm/alpha-ext.h b/binutils-2.25/include/nlm/alpha-ext.h
new file mode 100644
index 00000000..7dc65688
--- /dev/null
+++ b/binutils-2.25/include/nlm/alpha-ext.h
@@ -0,0 +1,167 @@
+/* Alpha NLM (NetWare Loadable Module) support for BFD.
+   Copyright 1993, 2005, 2010 Free Software Foundation, Inc.
+   By Ian Lance Taylor, Cygnus Support
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* An Alpha NLM starts with an instance of this structure.  */
+
+struct nlm32_alpha_external_prefix_header
+{
+  /* Magic number.  Must be NLM32_ALPHA_MAGIC.  */
+  unsigned char magic[4];
+  /* Format descriptor.  Current value is 2.  */
+  unsigned char format[4];
+  /* Size of prefix header.  */
+  unsigned char size[4];
+  /* Padding.  */
+  unsigned char pad1[4];
+  /* More fields may be added later, supposedly.  */
+};
+
+/* The external format of an Alpha NLM reloc.  This is the same as an
+   Alpha ECOFF reloc.  */
+
+struct nlm32_alpha_external_reloc
+{
+  unsigned char r_vaddr[8];
+  unsigned char r_symndx[4];
+  unsigned char r_bits[4];
+};
+
+/* Constants to unpack the r_bits field of a reloc.  */
+
+#define RELOC_BITS0_TYPE_LITTLE			0xff
+#define RELOC_BITS0_TYPE_SH_LITTLE		0
+
+#define RELOC_BITS1_EXTERN_LITTLE		0x01
+
+#define RELOC_BITS1_OFFSET_LITTLE		0x7e
+#define RELOC_BITS1_OFFSET_SH_LITTLE		1
+
+#define RELOC_BITS1_RESERVED_LITTLE		0x80
+#define RELOC_BITS1_RESERVED_SH_LITTLE		7
+#define RELOC_BITS2_RESERVED_LITTLE		0xff
+#define RELOC_BITS2_RESERVED_SH_LEFT_LITTLE	1
+#define RELOC_BITS3_RESERVED_LITTLE		0x03
+#define RELOC_BITS3_RESERVED_SH_LEFT_LITTLE	9
+
+#define RELOC_BITS3_SIZE_LITTLE			0xfc
+#define RELOC_BITS3_SIZE_SH_LITTLE		2
+
+/* The external format of the fixed header.  */
+
+typedef struct nlm32_alpha_external_fixed_header
+{
+
+  /* The signature field identifies the file as an NLM.  It must contain
+     the signature string, which depends upon the NLM target. */
+
+  unsigned char signature[24];
+
+  /* The version of the header.  At this time, the highest version number
+     is 4. */
+
+  unsigned char version[4];
+
+  /* The name of the module, which must be a DOS name (1-8 characters followed
+     by a period and a 1-3 character extension).  The first byte is the byte
+     length of the name and the last byte is a null terminator byte.  This
+     field is fixed length, and any unused bytes should be null bytes.  The
+     value is set by the OUTPUT keyword to NLMLINK. */
+
+  unsigned char moduleName[14];
+
+  /* Padding to make it come out correct. */
+
+  unsigned char pad1[2];
+
+  /* The byte offset of the code image from the start of the file. */
+
+  unsigned char codeImageOffset[4];
+
+  /* The size of the code image, in bytes. */
+
+  unsigned char codeImageSize[4];
+
+  /* The byte offset of the data image from the start of the file. */
+
+  unsigned char dataImageOffset[4];
+
+  /* The size of the data image, in bytes. */
+
+  unsigned char dataImageSize[4];
+
+  /* The size of the uninitialized data region that the loader is to be
+     allocated at load time.  Uninitialized data follows the initialized
+     data in the NLM address space. */
+
+  unsigned char uninitializedDataSize[4];
+
+  /* The byte offset of the custom data from the start of the file.  The
+     custom data is set by the CUSTOM keyword to NLMLINK.  It is possible
+     for this to be EOF if there is no custom data. */
+
+  unsigned char customDataOffset[4];
+
+  /* The size of the custom data, in bytes. */
+
+  unsigned char customDataSize[4];
+
+  /* The byte offset of the module dependencies from the start of the file.
+     The module dependencies are determined by the MODULE keyword in
+     NLMLINK. */
+
+  unsigned char moduleDependencyOffset[4];
+
+  /* The number of module dependencies at the moduleDependencyOffset. */
+
+  unsigned char numberOfModuleDependencies[4];
+
+  /* The byte offset of the relocation fixup data from the start of the file */
+     
+  unsigned char relocationFixupOffset[4];
+
+  unsigned char numberOfRelocationFixups[4];
+
+  unsigned char externalReferencesOffset[4];
+
+  unsigned char numberOfExternalReferences[4];
+
+  unsigned char publicsOffset[4];
+
+  unsigned char numberOfPublics[4];
+
+  /* The byte offset of the internal debug info from the start of the file.
+     It is possible for this to be EOF if there is no debug info. */
+
+  unsigned char debugInfoOffset[4];
+
+  unsigned char numberOfDebugRecords[4];
+
+  unsigned char codeStartOffset[4];
+
+  unsigned char exitProcedureOffset[4];
+
+  unsigned char checkUnloadProcedureOffset[4];
+
+  unsigned char moduleType[4];
+
+  unsigned char flags[4];
+
+} Nlm32_alpha_External_Fixed_Header;
diff --git a/binutils-2.25/include/nlm/common.h b/binutils-2.25/include/nlm/common.h
new file mode 100644
index 00000000..fcd290e0
--- /dev/null
+++ b/binutils-2.25/include/nlm/common.h
@@ -0,0 +1,123 @@
+/* NLM (NetWare Loadable Module) support for BFD.
+   Copyright 1993, 2001, 2005, 2010 Free Software Foundation, Inc.
+
+   Written by Fred Fish @ Cygnus Support
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file is part of NLM support for BFD, and contains the portions
+   that are common to both the internal and external representations.  */
+
+/* If NLM_ARCH_SIZE is not defined, default to 32.  NLM_ARCH_SIZE is
+   optionally defined by the application.  */
+
+#ifndef NLM_ARCH_SIZE
+#  define NLM_ARCH_SIZE			32
+#endif
+
+/* Due to horrible details of ANSI macro expansion, we can't use CONCAT4
+   for NLM_NAME.  CONCAT2 is used in BFD_JUMP_TABLE macros, and some of
+   them will expand to tokens that themselves are macros defined in terms
+   of NLM_NAME.  If NLM_NAME were defined using CONCAT4 (which is itself
+   defined in bfd-in.h using CONCAT2), ANSI preprocessor rules say that
+   the CONCAT2 within NLM_NAME should not be expanded.
+   So use another name.  */
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#ifdef SABER
+#define NLM_CAT4(a,b,c,d) a##b##c##d
+#else
+/* This hack is to avoid a problem with some strict ANSI C preprocessors.
+   The problem is, "32_" is not a valid preprocessing token, and we don't
+   want extra underscores (e.g., "nlm_32_").  The NLM_XCAT2 macro will
+   cause the inner CAT2 macros to be evaluated first, producing
+   still-valid pp-tokens.  Then the final concatenation can be done.  */
+#define NLM_CAT2(a,b)	  a##b
+#define NLM_XCAT2(a,b)	  NLM_CAT2(a,b)
+#define NLM_CAT4(a,b,c,d) NLM_XCAT2(NLM_CAT2(a,b),NLM_CAT2(c,d))
+#endif
+#else
+#define NLM_CAT4(a,b,c,d) a/**/b/**/c/**/d
+#endif
+
+#if NLM_ARCH_SIZE == 32
+#  define NLM_TARGET_LONG_SIZE		4
+#  define NLM_TARGET_ADDRESS_SIZE	4
+#  define NLM_NAME(x,y)			NLM_CAT4(x,32,_,y)
+#  define NLM_HIBIT			(((bfd_vma) 1) << 31)
+#endif
+#if NLM_ARCH_SIZE == 64
+#  define NLM_TARGET_LONG_SIZE		8
+#  define NLM_TARGET_ADDRESS_SIZE	8
+#  define NLM_NAME(x,y)			NLM_CAT4(x,64,_,y)
+#  define NLM_HIBIT			(((bfd_vma) 1) << 63)
+#endif
+
+#define NlmNAME(X)		NLM_NAME(Nlm,X)
+#define nlmNAME(X)		NLM_NAME(nlm,X)
+
+/* Give names to things that should not change. */
+
+#define NLM_MAX_DESCRIPTION_LENGTH		127
+#define NLM_MAX_SCREEN_NAME_LENGTH		71
+#define NLM_MAX_THREAD_NAME_LENGTH		71
+#define NLM_MAX_COPYRIGHT_MESSAGE_LENGTH	255
+#define NLM_OTHER_DATA_LENGTH 			400		/* FIXME */
+#define NLM_OLD_THREAD_NAME_LENGTH		5
+#define NLM_SIGNATURE_SIZE			24
+#define NLM_HEADER_VERSION			4
+#define NLM_MODULE_NAME_SIZE			14
+#define NLM_DEFAULT_STACKSIZE			(8 * 1024)
+
+/* Alpha information.  This should probably be in a separate Alpha
+   header file, but it can't go in alpha-ext.h because some of it is
+   needed by nlmconv.c.  */
+
+/* Magic number in Alpha prefix header.  */
+#define NLM32_ALPHA_MAGIC (0x83561840)
+
+/* The r_type field in an Alpha reloc is one of the following values.  */
+#define ALPHA_R_IGNORE		0
+#define ALPHA_R_REFLONG		1
+#define ALPHA_R_REFQUAD		2
+#define ALPHA_R_GPREL32		3
+#define ALPHA_R_LITERAL		4
+#define ALPHA_R_LITUSE		5
+#define ALPHA_R_GPDISP		6
+#define ALPHA_R_BRADDR		7
+#define ALPHA_R_HINT		8
+#define ALPHA_R_SREL16		9
+#define ALPHA_R_SREL32	       10
+#define ALPHA_R_SREL64	       11
+#define ALPHA_R_OP_PUSH	       12
+#define ALPHA_R_OP_STORE       13
+#define ALPHA_R_OP_PSUB	       14
+#define ALPHA_R_OP_PRSHIFT     15
+#define ALPHA_R_GPVALUE	       16
+#define ALPHA_R_NW_RELOC      250
+
+/* A local reloc, other than ALPHA_R_GPDISP or ALPHA_R_IGNORE, must be
+   against one of these symbol indices.  */
+#define ALPHA_RELOC_SECTION_TEXT	1
+#define ALPHA_RELOC_SECTION_DATA	3
+
+/* An ALPHA_R_NW_RELOC has one of these values in the size field.  If
+   it is SETGP, the r_vaddr field holds the GP value to use.  If it is
+   LITA, the r_vaddr field holds the address of the .lita section and
+   the r_symndx field holds the size of the .lita section.  */
+#define ALPHA_R_NW_RELOC_SETGP	1
+#define ALPHA_R_NW_RELOC_LITA	2
diff --git a/binutils-2.25/include/nlm/external.h b/binutils-2.25/include/nlm/external.h
new file mode 100644
index 00000000..eebd1cca
--- /dev/null
+++ b/binutils-2.25/include/nlm/external.h
@@ -0,0 +1,172 @@
+/* NLM (NetWare Loadable Module) support for BFD.
+   Copyright 1993, 1994, 2005, 2010 Free Software Foundation, Inc.
+
+   Written by Fred Fish @ Cygnus Support
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file is part of NLM support for BFD, and contains the portions
+   that describe how NLM is represented externally by the BFD library.
+   I.E. it describes the in-file representation of NLM.  It requires
+   the nlm/common.h file which contains the portions that are common to
+   both the internal and external representations.
+
+   Note that an NLM header consists of three parts:
+
+   (1)	A fixed length header that has specific fields of known length,
+	at specific offsets in the file. 
+
+   (2)  A variable length header that has specific fields in a specific
+        order, but some fields may be variable length.
+
+   (3)	A auxiliary header that has various optional fields in no specific
+        order.  There is no way to identify the end of the auxiliary headers
+	except by finding a header without a recognized 'stamp'.
+
+   The exact format of the fixed length header unfortunately varies
+   from one NLM target to another, due to padding.  Each target
+   defines the correct external format in a separate header file.  */
+   
+/* NLM Header.  */
+
+/* The version header is one of the optional auxiliary headers and
+   follows the fixed length and variable length NLM headers.  */
+
+typedef struct nlmNAME(external_version_header)
+{
+
+  /* The header is recognized by "VeRsIoN#" in the stamp field. */
+  char stamp[8];
+
+  unsigned char majorVersion[NLM_TARGET_LONG_SIZE];
+
+  unsigned char minorVersion[NLM_TARGET_LONG_SIZE];
+
+  unsigned char revision[NLM_TARGET_LONG_SIZE];
+
+  unsigned char year[NLM_TARGET_LONG_SIZE];
+
+  unsigned char month[NLM_TARGET_LONG_SIZE];
+
+  unsigned char day[NLM_TARGET_LONG_SIZE];
+
+} NlmNAME(External_Version_Header);
+
+
+typedef struct nlmNAME(external_copyright_header)
+{
+
+  /* The header is recognized by "CoPyRiGhT=" in the stamp field. */
+
+  char stamp[10];
+
+  unsigned char copyrightMessageLength[1];
+
+  /* There is a variable length field here called 'copyrightMessage'
+     that is the length specified by copyrightMessageLength. */
+
+} NlmNAME(External_Copyright_Header);
+
+
+typedef struct nlmNAME(external_extended_header)
+{
+
+  /* The header is recognized by "MeSsAgEs" in the stamp field. */
+
+  char stamp[8];
+
+  unsigned char languageID[NLM_TARGET_LONG_SIZE];
+
+  unsigned char messageFileOffset[NLM_TARGET_LONG_SIZE];
+
+  unsigned char messageFileLength[NLM_TARGET_LONG_SIZE];
+
+  unsigned char messageCount[NLM_TARGET_LONG_SIZE];
+
+  unsigned char helpFileOffset[NLM_TARGET_LONG_SIZE];
+
+  unsigned char helpFileLength[NLM_TARGET_LONG_SIZE];
+
+  unsigned char RPCDataOffset[NLM_TARGET_LONG_SIZE];
+
+  unsigned char RPCDataLength[NLM_TARGET_LONG_SIZE];
+
+  unsigned char sharedCodeOffset[NLM_TARGET_LONG_SIZE];
+
+  unsigned char sharedCodeLength[NLM_TARGET_LONG_SIZE];
+
+  unsigned char sharedDataOffset[NLM_TARGET_LONG_SIZE];
+
+  unsigned char sharedDataLength[NLM_TARGET_LONG_SIZE];
+
+  unsigned char sharedRelocationFixupOffset[NLM_TARGET_LONG_SIZE];
+
+  unsigned char sharedRelocationFixupCount[NLM_TARGET_LONG_SIZE];
+
+  unsigned char sharedExternalReferenceOffset[NLM_TARGET_LONG_SIZE];
+
+  unsigned char sharedExternalReferenceCount[NLM_TARGET_LONG_SIZE];
+
+  unsigned char sharedPublicsOffset[NLM_TARGET_LONG_SIZE];
+
+  unsigned char sharedPublicsCount[NLM_TARGET_LONG_SIZE];
+
+  unsigned char sharedDebugRecordOffset[NLM_TARGET_LONG_SIZE];
+
+  unsigned char sharedDebugRecordCount[NLM_TARGET_LONG_SIZE];
+
+  unsigned char sharedInitializationOffset[NLM_TARGET_ADDRESS_SIZE];
+
+  unsigned char SharedExitProcedureOffset[NLM_TARGET_ADDRESS_SIZE];
+
+  unsigned char productID[NLM_TARGET_LONG_SIZE];
+
+  unsigned char reserved0[NLM_TARGET_LONG_SIZE];
+
+  unsigned char reserved1[NLM_TARGET_LONG_SIZE];
+
+  unsigned char reserved2[NLM_TARGET_LONG_SIZE];
+
+  unsigned char reserved3[NLM_TARGET_LONG_SIZE];
+
+  unsigned char reserved4[NLM_TARGET_LONG_SIZE];
+
+  unsigned char reserved5[NLM_TARGET_LONG_SIZE];
+
+} NlmNAME(External_Extended_Header);
+
+
+typedef struct nlmNAME(external_custom_header)
+{
+
+  /* The header is recognized by "CuStHeAd" in the stamp field. */
+  char stamp[8];
+
+  /* Length of this header.  */
+  unsigned char length[NLM_TARGET_LONG_SIZE];
+
+  /* Offset to data.  */
+  unsigned char dataOffset[NLM_TARGET_LONG_SIZE];
+
+  /* Length of data.  */
+  unsigned char dataLength[NLM_TARGET_LONG_SIZE];
+
+  /* Stamp for this customer header--we recognize "CyGnUsEx".  */
+  char dataStamp[8];
+
+} NlmNAME(External_Custom_Header);
diff --git a/binutils-2.25/include/nlm/i386-ext.h b/binutils-2.25/include/nlm/i386-ext.h
new file mode 100644
index 00000000..4de8b340
--- /dev/null
+++ b/binutils-2.25/include/nlm/i386-ext.h
@@ -0,0 +1,117 @@
+/* i386 NLM (NetWare Loadable Module) support for BFD.
+   Copyright 1993, 2005, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* The external format of the fixed header.  */
+
+typedef struct nlm32_i386_external_fixed_header
+{
+
+  /* The signature field identifies the file as an NLM.  It must contain
+     the signature string, which depends upon the NLM target. */
+
+  unsigned char signature[24];
+
+  /* The version of the header.  At this time, the highest version number
+     is 4. */
+
+  unsigned char version[4];
+
+  /* The name of the module, which must be a DOS name (1-8 characters followed
+     by a period and a 1-3 character extension).  The first byte is the byte
+     length of the name and the last byte is a null terminator byte.  This
+     field is fixed length, and any unused bytes should be null bytes.  The
+     value is set by the OUTPUT keyword to NLMLINK. */
+
+  unsigned char moduleName[14];
+
+  /* The byte offset of the code image from the start of the file. */
+
+  unsigned char codeImageOffset[4];
+
+  /* The size of the code image, in bytes. */
+
+  unsigned char codeImageSize[4];
+
+  /* The byte offset of the data image from the start of the file. */
+
+  unsigned char dataImageOffset[4];
+
+  /* The size of the data image, in bytes. */
+
+  unsigned char dataImageSize[4];
+
+  /* The size of the uninitialized data region that the loader is to be
+     allocated at load time.  Uninitialized data follows the initialized
+     data in the NLM address space. */
+
+  unsigned char uninitializedDataSize[4];
+
+  /* The byte offset of the custom data from the start of the file.  The
+     custom data is set by the CUSTOM keyword to NLMLINK.  It is possible
+     for this to be EOF if there is no custom data. */
+
+  unsigned char customDataOffset[4];
+
+  /* The size of the custom data, in bytes. */
+
+  unsigned char customDataSize[4];
+
+  /* The byte offset of the module dependencies from the start of the file.
+     The module dependencies are determined by the MODULE keyword in
+     NLMLINK. */
+
+  unsigned char moduleDependencyOffset[4];
+
+  /* The number of module dependencies at the moduleDependencyOffset. */
+
+  unsigned char numberOfModuleDependencies[4];
+
+  /* The byte offset of the relocation fixup data from the start of the file */
+     
+  unsigned char relocationFixupOffset[4];
+
+  unsigned char numberOfRelocationFixups[4];
+
+  unsigned char externalReferencesOffset[4];
+
+  unsigned char numberOfExternalReferences[4];
+
+  unsigned char publicsOffset[4];
+
+  unsigned char numberOfPublics[4];
+
+  /* The byte offset of the internal debug info from the start of the file.
+     It is possible for this to be EOF if there is no debug info. */
+
+  unsigned char debugInfoOffset[4];
+
+  unsigned char numberOfDebugRecords[4];
+
+  unsigned char codeStartOffset[4];
+
+  unsigned char exitProcedureOffset[4];
+
+  unsigned char checkUnloadProcedureOffset[4];
+
+  unsigned char moduleType[4];
+
+  unsigned char flags[4];
+
+} Nlm32_i386_External_Fixed_Header;
diff --git a/binutils-2.25/include/nlm/internal.h b/binutils-2.25/include/nlm/internal.h
new file mode 100644
index 00000000..51e1f00e
--- /dev/null
+++ b/binutils-2.25/include/nlm/internal.h
@@ -0,0 +1,309 @@
+/* NLM (NetWare Loadable Module) support for BFD.
+   Copyright 1993, 1994, 2003, 2005, 2010 Free Software Foundation, Inc.
+
+   Written by Fred Fish @ Cygnus Support.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file is part of NLM support for BFD, and contains the portions
+   that describe how NLM is represented internally in the BFD library.
+   I.E. it describes the in-memory representation of NLM.  It requires
+   the nlm/common.h file which contains the portions that are common to
+   both the internal and external representations.  */
+   
+#if 0
+
+/* Types used by various structures, functions, etc.  */
+
+typedef unsigned long	Nlm32_Addr;	/* Unsigned program address */
+typedef unsigned long	Nlm32_Off;	/* Unsigned file offset */
+typedef 	 long	Nlm32_Sword;	/* Signed large integer */
+typedef unsigned long	Nlm32_Word;	/* Unsigned large integer */
+typedef unsigned short	Nlm32_Half;	/* Unsigned medium integer */
+typedef unsigned char	Nlm32_Char;	/* Unsigned tiny integer */
+
+#ifdef BFD_HOST_64_BIT
+typedef unsigned BFD_HOST_64_BIT	Nlm64_Addr;
+typedef unsigned BFD_HOST_64_BIT	Nlm64_Off;
+typedef          BFD_HOST_64_BIT	Nlm64_Sxword;
+typedef unsigned BFD_HOST_64_BIT	Nlm64_Xword;
+#endif
+typedef          long		Nlm64_Sword;
+typedef unsigned long		Nlm64_Word;
+typedef unsigned short		Nlm64_Half;
+
+#endif /* 0 */
+
+/* This structure contains the internal form of the portion of the NLM
+   header that is fixed length. */
+
+typedef struct nlm_internal_fixed_header
+{
+  /* The signature field identifies the file as an NLM.  It must contain
+     the signature string, which depends upon the NLM target. */
+
+  char signature[NLM_SIGNATURE_SIZE];
+
+  /* The version of the header.  At this time, the highest version number
+     is 4. */
+
+  long version;
+
+  /* The name of the module, which must be a DOS name (1-8 characters followed
+     by a period and a 1-3 character extension.  The first byte is the byte
+     length of the name and the last byte is a null terminator byte.  This
+     field is fixed length, and any unused bytes should be null bytes.  The
+     value is set by the OUTPUT keyword to NLMLINK. */
+
+  char moduleName[NLM_MODULE_NAME_SIZE];
+
+  /* The byte offset of the code image from the start of the file. */
+
+  file_ptr codeImageOffset;
+
+  /* The size of the code image, in bytes. */
+
+  bfd_size_type codeImageSize;
+
+  /* The byte offset of the data image from the start of the file. */
+
+  file_ptr dataImageOffset;
+
+  /* The size of the data image, in bytes. */
+
+  bfd_size_type dataImageSize;
+
+  /* The size of the uninitialized data region that the loader is to be
+     allocated at load time.  Uninitialized data follows the initialized
+     data in the NLM address space. */
+
+  bfd_size_type uninitializedDataSize;
+
+  /* The byte offset of the custom data from the start of the file.  The
+     custom data is set by the CUSTOM keyword to NLMLINK. */
+
+  file_ptr customDataOffset;
+
+  /* The size of the custom data, in bytes. */
+
+  bfd_size_type customDataSize;
+
+  /* The byte offset of the module dependencies from the start of the file.
+     The module dependencies are determined by the MODULE keyword in
+     NLMLINK. */
+
+  file_ptr moduleDependencyOffset;
+
+  /* The number of module dependencies at the moduleDependencyOffset. */
+
+  long numberOfModuleDependencies;
+
+  /* The byte offset of the relocation fixup data from the start of the file */
+
+  file_ptr relocationFixupOffset;
+  long numberOfRelocationFixups;
+  file_ptr externalReferencesOffset;
+  long numberOfExternalReferences;
+  file_ptr publicsOffset;
+  long numberOfPublics;
+  file_ptr debugInfoOffset;
+  long numberOfDebugRecords;
+  file_ptr codeStartOffset;
+  file_ptr exitProcedureOffset;
+  file_ptr checkUnloadProcedureOffset;
+  long moduleType;
+  long flags;
+} Nlm_Internal_Fixed_Header;
+
+#define nlm32_internal_fixed_header nlm_internal_fixed_header
+#define Nlm32_Internal_Fixed_Header Nlm_Internal_Fixed_Header
+#define nlm64_internal_fixed_header nlm_internal_fixed_header
+#define Nlm64_Internal_Fixed_Header Nlm_Internal_Fixed_Header
+
+/* This structure contains the portions of the NLM header that are either
+   variable in size in the external representation, or else are not at a
+   fixed offset relative to the start of the NLM header due to preceding
+   variable sized fields.
+
+   Note that all the fields must exist in the external header, and in
+   the order used here (the same order is used in the internal form
+   for consistency, not out of necessity). */
+
+typedef struct nlm_internal_variable_header
+{
+
+  /* The descriptionLength field contains the length of the text in
+     descriptionText, excluding the null terminator.  The descriptionText
+     field contains the NLM description obtained from the DESCRIPTION
+     keyword in NLMLINK plus the null byte terminator.  The descriptionText
+     can be up to NLM_MAX_DESCRIPTION_LENGTH characters. */
+     
+  unsigned char descriptionLength;
+  char descriptionText[NLM_MAX_DESCRIPTION_LENGTH + 1];
+
+  /* The stackSize field contains the size of the stack in bytes, as
+     specified by the STACK or STACKSIZE keyword in NLMLINK.  If no size
+     is specified, the default is NLM_DEFAULT_STACKSIZE. */
+     
+  long stackSize;
+
+  /* The reserved field is included only for completeness.  It should contain
+     zero. */
+
+  long reserved;
+
+  /* This field is fixed length, should contain " LONG" (note leading
+     space), and is unused. */
+
+  char oldThreadName[NLM_OLD_THREAD_NAME_LENGTH];
+
+  /* The screenNameLength field contains the length of the actual text stored
+     in the screenName field, excluding the null byte terminator.  The
+     screenName field contains the screen name as specified by the SCREENNAME
+     keyword in NLMLINK, and can be up to NLM_MAX_SCREEN_NAME_LENGTH
+     characters. */
+
+  unsigned char screenNameLength;
+  char screenName[NLM_MAX_SCREEN_NAME_LENGTH + 1];
+
+  /* The threadNameLength field contains the length of the actual text stored
+     in the threadName field, excluding the null byte terminator.  The
+     threadName field contains the thread name as specified by the THREADNAME
+     keyword in NLMLINK, and can be up to NLM_MAX_THREAD_NAME_LENGTH
+     characters. */
+
+  unsigned char threadNameLength;
+  char threadName[NLM_MAX_THREAD_NAME_LENGTH + 1];
+
+} Nlm_Internal_Variable_Header;
+
+#define nlm32_internal_variable_header nlm_internal_variable_header
+#define Nlm32_Internal_Variable_Header Nlm_Internal_Variable_Header
+#define nlm64_internal_variable_header nlm_internal_variable_header
+#define Nlm64_Internal_Variable_Header Nlm_Internal_Variable_Header
+
+/* The version header is one of the optional auxiliary headers and
+   follows the fixed length and variable length NLM headers. */
+
+typedef struct nlm_internal_version_header
+{
+  /* The header is recognized by "VeRsIoN#" in the stamp field. */
+  char stamp[8];
+  long majorVersion;
+  long minorVersion;
+  long revision;
+  long year;
+  long month;
+  long day;
+} Nlm_Internal_Version_Header;
+
+#define nlm32_internal_version_header nlm_internal_version_header
+#define Nlm32_Internal_Version_Header Nlm_Internal_Version_Header
+#define nlm64_internal_version_header nlm_internal_version_header
+#define Nlm64_Internal_Version_Header Nlm_Internal_Version_Header
+
+typedef struct nlm_internal_copyright_header
+{
+  /* The header is recognized by "CoPyRiGhT=" in the stamp field. */
+  char stamp[10];
+  unsigned char copyrightMessageLength;
+  char copyrightMessage[NLM_MAX_COPYRIGHT_MESSAGE_LENGTH];
+} Nlm_Internal_Copyright_Header;
+
+#define nlm32_internal_copyright_header nlm_internal_copyright_header
+#define Nlm32_Internal_Copyright_Header Nlm_Internal_Copyright_Header
+#define nlm64_internal_copyright_header nlm_internal_copyright_header
+#define Nlm64_Internal_Copyright_Header Nlm_Internal_Copyright_Header
+
+typedef struct nlm_internal_extended_header
+{
+  /* The header is recognized by "MeSsAgEs" in the stamp field. */
+  char stamp[8];
+  long languageID;
+  file_ptr messageFileOffset;
+  bfd_size_type messageFileLength;
+  long messageCount;
+  file_ptr helpFileOffset;
+  bfd_size_type helpFileLength;
+  file_ptr RPCDataOffset;
+  bfd_size_type RPCDataLength;
+  file_ptr sharedCodeOffset;
+  bfd_size_type sharedCodeLength;
+  file_ptr sharedDataOffset;
+  bfd_size_type sharedDataLength;
+  file_ptr sharedRelocationFixupOffset;
+  long sharedRelocationFixupCount;
+  file_ptr sharedExternalReferenceOffset;
+  long sharedExternalReferenceCount;
+  file_ptr sharedPublicsOffset;
+  long sharedPublicsCount;
+  file_ptr sharedDebugRecordOffset;
+  long sharedDebugRecordCount;
+  bfd_vma SharedInitializationOffset;
+  bfd_vma SharedExitProcedureOffset;
+  long productID;
+  long reserved0;
+  long reserved1;
+  long reserved2;
+  long reserved3;
+  long reserved4;
+  long reserved5;
+} Nlm_Internal_Extended_Header;
+
+#define nlm32_internal_extended_header nlm_internal_extended_header
+#define Nlm32_Internal_Extended_Header Nlm_Internal_Extended_Header
+#define nlm64_internal_extended_header nlm_internal_extended_header
+#define Nlm64_Internal_Extended_Header Nlm_Internal_Extended_Header
+
+/* The format of a custom header as stored internally is different
+   from the external format.  This is how we store a custom header
+   which we do not recognize.  */
+
+typedef struct nlm_internal_custom_header
+{
+  /* The header is recognized by "CuStHeAd" in the stamp field. */
+  char stamp[8];
+  bfd_size_type hdrLength;
+  file_ptr dataOffset;
+  bfd_size_type dataLength;
+  char dataStamp[8];
+  void *hdr;
+} Nlm_Internal_Custom_Header;
+
+#define nlm32_internal_custom_header nlm_internal_custom_header
+#define Nlm32_Internal_Custom_Header Nlm_Internal_Custom_Header
+#define nlm64_internal_custom_header nlm_internal_custom_header
+#define Nlm64_Internal_Custom_Header Nlm_Internal_Custom_Header
+
+/* The internal Cygnus header is written out externally as a custom
+   header.  We don't try to replicate that structure here.  */
+
+typedef struct nlm_internal_cygnus_ext_header
+{
+  /* The header is recognized by "CyGnUsEx" in the stamp field. */
+  char stamp[8];
+  /* File location of debugging information.  */
+  file_ptr offset;
+  /* Length of debugging information.  */
+  bfd_size_type length;
+} Nlm_Internal_Cygnus_Ext_Header;
+
+#define nlm32_internal_cygnus_ext_header nlm_internal_cygnus_ext_header
+#define Nlm32_Internal_Cygnus_Ext_Header Nlm_Internal_Cygnus_Ext_Header
+#define nlm64_internal_cygnus_ext_header nlm_internal_cygnus_ext_header
+#define Nlm64_Internal_Cygnus_Ext_Header Nlm_Internal_Cygnus_Ext_Header
diff --git a/binutils-2.25/include/nlm/ppc-ext.h b/binutils-2.25/include/nlm/ppc-ext.h
new file mode 100644
index 00000000..026984b8
--- /dev/null
+++ b/binutils-2.25/include/nlm/ppc-ext.h
@@ -0,0 +1,164 @@
+/* PowerPC NLM (NetWare Loadable Module) support for BFD.
+   Copyright (C) 1994, 2005, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifdef OLDFORMAT
+
+/* The format of a PowerPC NLM changed.  These structures are only
+   used in the old format.  */
+
+/* A PowerPC NLM starts with an instance of this structure.  */
+
+struct nlm32_powerpc_external_prefix_header
+{
+  /* Signature.  Must be "AppleNLM".  */
+  char signature[8];
+  /* Version number.  Current value is 1.  */
+  unsigned char headerVersion[4];
+  /* ??.  Should be set to 0.  */
+  unsigned char origins[4];
+  /* File creation date in standard Unix time format (seconds since
+     1/1/70).  */
+  unsigned char date[4];
+};
+
+#define NLM32_POWERPC_SIGNATURE "AppleNLM"
+#define NLM32_POWERPC_HEADER_VERSION 1
+
+/* The external format of a PowerPC NLM reloc.  This is the same as an
+   XCOFF dynamic reloc.  */
+
+struct nlm32_powerpc_external_reloc
+{
+  /* Address.  */
+  unsigned char l_vaddr[4];
+  /* Symbol table index.  This is 0 for .text and 1 for .data.  2
+     means .bss, but I don't know if it is used.  In XCOFF, larger
+     numbers are indices into the dynamic symbol table, but they are
+     presumably not used in an NLM.  */
+  unsigned char l_symndx[4];
+  /* Relocation type.  */
+  unsigned char l_rtype[2];
+  /* Section number being relocated.  */
+  unsigned char l_rsecnm[2];
+};
+
+#endif /* OLDFORMAT */
+
+/* The external format of the fixed header.  */
+
+typedef struct nlm32_powerpc_external_fixed_header
+{
+
+  /* The signature field identifies the file as an NLM.  It must contain
+     the signature string, which depends upon the NLM target. */
+
+  unsigned char signature[24];
+
+  /* The version of the header.  At this time, the highest version number
+     is 4. */
+
+  unsigned char version[4];
+
+  /* The name of the module, which must be a DOS name (1-8 characters followed
+     by a period and a 1-3 character extension).  The first byte is the byte
+     length of the name and the last byte is a null terminator byte.  This
+     field is fixed length, and any unused bytes should be null bytes.  The
+     value is set by the OUTPUT keyword to NLMLINK. */
+
+  unsigned char moduleName[14];
+
+  /* Padding to make it come out correct. */
+
+  unsigned char pad1[2];
+
+  /* The byte offset of the code image from the start of the file. */
+
+  unsigned char codeImageOffset[4];
+
+  /* The size of the code image, in bytes. */
+
+  unsigned char codeImageSize[4];
+
+  /* The byte offset of the data image from the start of the file. */
+
+  unsigned char dataImageOffset[4];
+
+  /* The size of the data image, in bytes. */
+
+  unsigned char dataImageSize[4];
+
+  /* The size of the uninitialized data region that the loader is to be
+     allocated at load time.  Uninitialized data follows the initialized
+     data in the NLM address space. */
+
+  unsigned char uninitializedDataSize[4];
+
+  /* The byte offset of the custom data from the start of the file.  The
+     custom data is set by the CUSTOM keyword to NLMLINK.  It is possible
+     for this to be EOF if there is no custom data. */
+
+  unsigned char customDataOffset[4];
+
+  /* The size of the custom data, in bytes. */
+
+  unsigned char customDataSize[4];
+
+  /* The byte offset of the module dependencies from the start of the file.
+     The module dependencies are determined by the MODULE keyword in
+     NLMLINK. */
+
+  unsigned char moduleDependencyOffset[4];
+
+  /* The number of module dependencies at the moduleDependencyOffset. */
+
+  unsigned char numberOfModuleDependencies[4];
+
+  /* The byte offset of the relocation fixup data from the start of the file */
+     
+  unsigned char relocationFixupOffset[4];
+
+  unsigned char numberOfRelocationFixups[4];
+
+  unsigned char externalReferencesOffset[4];
+
+  unsigned char numberOfExternalReferences[4];
+
+  unsigned char publicsOffset[4];
+
+  unsigned char numberOfPublics[4];
+
+  /* The byte offset of the internal debug info from the start of the file.
+     It is possible for this to be EOF if there is no debug info. */
+
+  unsigned char debugInfoOffset[4];
+
+  unsigned char numberOfDebugRecords[4];
+
+  unsigned char codeStartOffset[4];
+
+  unsigned char exitProcedureOffset[4];
+
+  unsigned char checkUnloadProcedureOffset[4];
+
+  unsigned char moduleType[4];
+
+  unsigned char flags[4];
+
+} Nlm32_powerpc_External_Fixed_Header;
diff --git a/binutils-2.25/include/nlm/sparc32-ext.h b/binutils-2.25/include/nlm/sparc32-ext.h
new file mode 100644
index 00000000..a5c78e34
--- /dev/null
+++ b/binutils-2.25/include/nlm/sparc32-ext.h
@@ -0,0 +1,121 @@
+/* SPARC NLM (NetWare Loadable Module) support for BFD.
+   Copyright 1993, 2005, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* The external format of the fixed header.  */
+
+typedef struct nlm32_sparc_external_fixed_header
+{
+
+  /* The signature field identifies the file as an NLM.  It must contain
+     the signature string, which depends upon the NLM target. */
+
+  unsigned char signature[24];
+
+  /* The version of the header.  At this time, the highest version number
+     is 4. */
+
+  unsigned char version[4];
+
+  /* The name of the module, which must be a DOS name (1-8 characters followed
+     by a period and a 1-3 character extension).  The first byte is the byte
+     length of the name and the last byte is a null terminator byte.  This
+     field is fixed length, and any unused bytes should be null bytes.  The
+     value is set by the OUTPUT keyword to NLMLINK. */
+
+  unsigned char moduleName[14];
+
+  /* Padding to make it come out correct. */
+
+  unsigned char pad1[2];
+
+  /* The byte offset of the code image from the start of the file. */
+
+  unsigned char codeImageOffset[4];
+
+  /* The size of the code image, in bytes. */
+
+  unsigned char codeImageSize[4];
+
+  /* The byte offset of the data image from the start of the file. */
+
+  unsigned char dataImageOffset[4];
+
+  /* The size of the data image, in bytes. */
+
+  unsigned char dataImageSize[4];
+
+  /* The size of the uninitialized data region that the loader is to be
+     allocated at load time.  Uninitialized data follows the initialized
+     data in the NLM address space. */
+
+  unsigned char uninitializedDataSize[4];
+
+  /* The byte offset of the custom data from the start of the file.  The
+     custom data is set by the CUSTOM keyword to NLMLINK.  It is possible
+     for this to be EOF if there is no custom data. */
+
+  unsigned char customDataOffset[4];
+
+  /* The size of the custom data, in bytes. */
+
+  unsigned char customDataSize[4];
+
+  /* The byte offset of the module dependencies from the start of the file.
+     The module dependencies are determined by the MODULE keyword in
+     NLMLINK. */
+
+  unsigned char moduleDependencyOffset[4];
+
+  /* The number of module dependencies at the moduleDependencyOffset. */
+
+  unsigned char numberOfModuleDependencies[4];
+
+  /* The byte offset of the relocation fixup data from the start of the file */
+     
+  unsigned char relocationFixupOffset[4];
+
+  unsigned char numberOfRelocationFixups[4];
+
+  unsigned char externalReferencesOffset[4];
+
+  unsigned char numberOfExternalReferences[4];
+
+  unsigned char publicsOffset[4];
+
+  unsigned char numberOfPublics[4];
+
+  /* The byte offset of the internal debug info from the start of the file.
+     It is possible for this to be EOF if there is no debug info. */
+
+  unsigned char debugInfoOffset[4];
+
+  unsigned char numberOfDebugRecords[4];
+
+  unsigned char codeStartOffset[4];
+
+  unsigned char exitProcedureOffset[4];
+
+  unsigned char checkUnloadProcedureOffset[4];
+
+  unsigned char moduleType[4];
+
+  unsigned char flags[4];
+
+} Nlm32_sparc_External_Fixed_Header;
diff --git a/binutils-2.25/include/oasys.h b/binutils-2.25/include/oasys.h
new file mode 100644
index 00000000..92d5c266
--- /dev/null
+++ b/binutils-2.25/include/oasys.h
@@ -0,0 +1,192 @@
+/* Oasys object format header file for BFD.
+
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.
+
+   Contributed by Cygnus Support.  */
+
+#define OASYS_MAX_SEC_COUNT 16
+/* **** */
+
+typedef struct oasys_archive_header
+  {
+    unsigned int  version;
+    char create_date[12];
+    char revision_date[12];
+    unsigned int mod_count;
+    file_ptr mod_tbl_offset;
+    unsigned int sym_tbl_size;
+    unsigned int sym_count;
+    file_ptr sym_tbl_offset;
+    unsigned int xref_count;
+    file_ptr xref_lst_offset;
+  }
+oasys_archive_header_type;
+
+typedef struct oasys_extarchive_header
+  {
+    bfd_byte version[4];
+    bfd_byte create_date[12];
+    bfd_byte revision_date[12];
+    bfd_byte mod_count[4];
+    bfd_byte mod_tbl_offset[4];
+    bfd_byte sym_tbl_size[4];
+    bfd_byte sym_count[4];
+    bfd_byte sym_tbl_offset[4];
+    bfd_byte xref_count[4];
+    bfd_byte xref_lst_offset[4];
+  }
+oasys_extarchive_header_type;
+
+typedef struct oasys_module_table
+  {
+    int mod_number;
+    char mod_date[12];
+    unsigned int mod_size;
+    unsigned int dep_count;
+    unsigned int depee_count;
+    file_ptr file_offset;
+    unsigned int sect_count;
+    char *module_name;
+    unsigned int module_name_size;
+  }
+oasys_module_table_type;
+
+typedef struct oasys_extmodule_table_a
+  {
+    bfd_byte mod_number[4];
+    bfd_byte mod_date[12];
+    bfd_byte mod_size[4];
+    bfd_byte dep_count[4];
+    bfd_byte depee_count[4];
+    bfd_byte sect_count[4];
+    bfd_byte file_offset[4];
+    bfd_byte mod_name[32];
+  }
+oasys_extmodule_table_type_a_type;
+
+typedef struct oasys_extmodule_table_b
+  {
+    bfd_byte mod_number[4];
+    bfd_byte mod_date[12];
+    bfd_byte mod_size[4];
+    bfd_byte dep_count[4];
+    bfd_byte depee_count[4];
+    bfd_byte sect_count[4];
+    bfd_byte file_offset[4];
+    bfd_byte mod_name_length[4];
+  }
+oasys_extmodule_table_type_b_type;
+
+typedef enum oasys_record
+  {
+    oasys_record_is_end_enum = 0,
+    oasys_record_is_data_enum = 1,
+    oasys_record_is_symbol_enum = 2,
+    oasys_record_is_header_enum = 3,
+    oasys_record_is_named_section_enum = 4,
+    oasys_record_is_com_enum = 5,
+    oasys_record_is_debug_enum = 6,
+    oasys_record_is_section_enum = 7,
+    oasys_record_is_debug_file_enum = 8,
+    oasys_record_is_module_enum = 9,
+    oasys_record_is_local_enum = 10
+  }
+oasys_record_enum_type;
+
+typedef struct oasys_record_header
+  {
+    unsigned char length;
+    unsigned char check_sum;
+    unsigned char type;
+    unsigned char fill;
+  }
+oasys_record_header_type;
+
+typedef struct oasys_data_record
+  {
+    oasys_record_header_type header;
+    unsigned char relb;
+    bfd_byte addr[4];
+    /* maximum total size of data record is 255 bytes */
+    bfd_byte data[246];
+  }
+oasys_data_record_type;
+
+typedef struct oasys_header_record
+  {
+    oasys_record_header_type header;
+    unsigned char version_number;
+    unsigned char rev_number;
+    char module_name[26-6];
+    char description[64-26];
+  }
+oasys_header_record_type;
+
+#define OASYS_VERSION_NUMBER 0
+#define OASYS_REV_NUMBER 0
+
+typedef struct oasys_symbol_record
+  {
+    oasys_record_header_type header;
+    unsigned char relb;
+    bfd_byte value[4];
+    bfd_byte refno[2];
+    char name[64];
+  }
+oasys_symbol_record_type;
+
+#define RELOCATION_PCREL_BIT 0x80
+#define RELOCATION_32BIT_BIT 0x40
+#define RELOCATION_TYPE_BITS 0x30
+#define RELOCATION_TYPE_ABS 0x00
+#define RELOCATION_TYPE_REL 0x10
+#define RELOCATION_TYPE_UND 0x20
+#define RELOCATION_TYPE_COM 0x30
+#define RELOCATION_SECT_BITS 0x0f
+
+typedef struct oasys_section_record
+  {
+    oasys_record_header_type header;
+    unsigned char relb;
+    bfd_byte value[4];
+    bfd_byte vma[4];
+    bfd_byte fill[3];
+  }
+oasys_section_record_type;
+
+typedef struct oasys_end_record
+  {
+    oasys_record_header_type header;
+    unsigned char relb;
+    bfd_byte entry[4];
+    bfd_byte fill[2];
+    bfd_byte zero;
+  }
+oasys_end_record_type;
+
+typedef union oasys_record_union
+  {
+    oasys_record_header_type header;
+    oasys_data_record_type data;
+    oasys_section_record_type section;
+    oasys_symbol_record_type symbol;
+    oasys_header_record_type first;
+    oasys_end_record_type end;
+    bfd_byte pad[256];
+  }
+oasys_record_union_type;
diff --git a/binutils-2.25/include/objalloc.h b/binutils-2.25/include/objalloc.h
new file mode 100644
index 00000000..52857663
--- /dev/null
+++ b/binutils-2.25/include/objalloc.h
@@ -0,0 +1,115 @@
+/* objalloc.h -- routines to allocate memory for objects
+   Copyright 1997-2012 Free Software Foundation, Inc.
+   Written by Ian Lance Taylor, Cygnus Solutions.
+
+This program is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, 51 Franklin Street - Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+#ifndef OBJALLOC_H
+#define OBJALLOC_H
+
+#include "ansidecl.h"
+
+/* These routines allocate space for an object.  The assumption is
+   that the object will want to allocate space as it goes along, but
+   will never want to free any particular block.  There is a function
+   to free a block, which also frees all more recently allocated
+   blocks.  There is also a function to free all the allocated space.
+
+   This is essentially a specialization of obstacks.  The main
+   difference is that a block may not be allocated a bit at a time.
+   Another difference is that these routines are always built on top
+   of malloc, and always pass an malloc failure back to the caller,
+   unlike more recent versions of obstacks.  */
+
+/* This is what an objalloc structure looks like.  Callers should not
+   refer to these fields, nor should they allocate these structure
+   themselves.  Instead, they should only create them via
+   objalloc_init, and only access them via the functions and macros
+   listed below.  The structure is only defined here so that we can
+   access it via macros.  */
+
+struct objalloc
+{
+  char *current_ptr;
+  unsigned int current_space;
+  void *chunks;
+};
+
+/* Work out the required alignment.  */
+
+struct objalloc_align { char x; double d; };
+
+#if defined (__STDC__) && __STDC__
+#ifndef offsetof
+#include <stddef.h>
+#endif
+#endif
+#ifndef offsetof
+#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
+#endif
+#define OBJALLOC_ALIGN offsetof (struct objalloc_align, d)
+
+/* Create an objalloc structure.  Returns NULL if malloc fails.  */
+
+extern struct objalloc *objalloc_create (void);
+
+/* Allocate space from an objalloc structure.  Returns NULL if malloc
+   fails.  */
+
+extern void *_objalloc_alloc (struct objalloc *, unsigned long);
+
+/* The macro version of objalloc_alloc.  We only define this if using
+   gcc, because otherwise we would have to evaluate the arguments
+   multiple times, or use a temporary field as obstack.h does.  */
+
+#if defined (__GNUC__) && defined (__STDC__) && __STDC__
+
+/* NextStep 2.0 cc is really gcc 1.93 but it defines __GNUC__ = 2 and
+   does not implement __extension__.  But that compiler doesn't define
+   __GNUC_MINOR__.  */
+#if __GNUC__ < 2 || (__NeXT__ && !__GNUC_MINOR__)
+#define __extension__
+#endif
+
+#define objalloc_alloc(o, l)						\
+  __extension__								\
+  ({ struct objalloc *__o = (o);					\
+     unsigned long __len = (l);						\
+     if (__len == 0)							\
+       __len = 1;							\
+     __len = (__len + OBJALLOC_ALIGN - 1) &~ (OBJALLOC_ALIGN - 1);	\
+     (__len != 0 && __len <= __o->current_space				\
+      ? (__o->current_ptr += __len,					\
+	 __o->current_space -= __len,					\
+	 (void *) (__o->current_ptr - __len))				\
+      : _objalloc_alloc (__o, __len)); })
+
+#else /* ! __GNUC__ */
+
+#define objalloc_alloc(o, l) _objalloc_alloc ((o), (l))
+
+#endif /* ! __GNUC__ */
+
+/* Free an entire objalloc structure.  */
+
+extern void objalloc_free (struct objalloc *);
+
+/* Free a block allocated by objalloc_alloc.  This also frees all more
+   recently allocated blocks.  */
+
+extern void objalloc_free_block (struct objalloc *, void *);
+
+#endif /* OBJALLOC_H */
diff --git a/binutils-2.25/include/obstack.h b/binutils-2.25/include/obstack.h
new file mode 100644
index 00000000..23487ba4
--- /dev/null
+++ b/binutils-2.25/include/obstack.h
@@ -0,0 +1,545 @@
+/* obstack.h - object stack macros
+   Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1996, 1997, 1998,
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2008
+   Free Software Foundation, Inc.
+
+
+   NOTE: The canonical source of this file is maintained with the GNU C Library.
+   Bugs can be reported to bug-glibc@gnu.org.
+
+   This program is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 2, or (at your option) any
+   later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
+   USA.  */
+
+/* Summary:
+
+All the apparent functions defined here are macros. The idea
+is that you would use these pre-tested macros to solve a
+very specific set of problems, and they would run fast.
+Caution: no side-effects in arguments please!! They may be
+evaluated MANY times!!
+
+These macros operate a stack of objects.  Each object starts life
+small, and may grow to maturity.  (Consider building a word syllable
+by syllable.)  An object can move while it is growing.  Once it has
+been "finished" it never changes address again.  So the "top of the
+stack" is typically an immature growing object, while the rest of the
+stack is of mature, fixed size and fixed address objects.
+
+These routines grab large chunks of memory, using a function you
+supply, called `obstack_chunk_alloc'.  On occasion, they free chunks,
+by calling `obstack_chunk_free'.  You must define them and declare
+them before using any obstack macros.
+
+Each independent stack is represented by a `struct obstack'.
+Each of the obstack macros expects a pointer to such a structure
+as the first argument.
+
+One motivation for this package is the problem of growing char strings
+in symbol tables.  Unless you are "fascist pig with a read-only mind"
+--Gosper's immortal quote from HAKMEM item 154, out of context--you
+would not like to put any arbitrary upper limit on the length of your
+symbols.
+
+In practice this often means you will build many short symbols and a
+few long symbols.  At the time you are reading a symbol you don't know
+how long it is.  One traditional method is to read a symbol into a
+buffer, realloc()ating the buffer every time you try to read a symbol
+that is longer than the buffer.  This is beaut, but you still will
+want to copy the symbol from the buffer to a more permanent
+symbol-table entry say about half the time.
+
+With obstacks, you can work differently.  Use one obstack for all symbol
+names.  As you read a symbol, grow the name in the obstack gradually.
+When the name is complete, finalize it.  Then, if the symbol exists already,
+free the newly read name.
+
+The way we do this is to take a large chunk, allocating memory from
+low addresses.  When you want to build a symbol in the chunk you just
+add chars above the current "high water mark" in the chunk.  When you
+have finished adding chars, because you got to the end of the symbol,
+you know how long the chars are, and you can create a new object.
+Mostly the chars will not burst over the highest address of the chunk,
+because you would typically expect a chunk to be (say) 100 times as
+long as an average object.
+
+In case that isn't clear, when we have enough chars to make up
+the object, THEY ARE ALREADY CONTIGUOUS IN THE CHUNK (guaranteed)
+so we just point to it where it lies.  No moving of chars is
+needed and this is the second win: potentially long strings need
+never be explicitly shuffled. Once an object is formed, it does not
+change its address during its lifetime.
+
+When the chars burst over a chunk boundary, we allocate a larger
+chunk, and then copy the partly formed object from the end of the old
+chunk to the beginning of the new larger chunk.  We then carry on
+accreting characters to the end of the object as we normally would.
+
+A special macro is provided to add a single char at a time to a
+growing object.  This allows the use of register variables, which
+break the ordinary 'growth' macro.
+
+Summary:
+	We allocate large chunks.
+	We carve out one object at a time from the current chunk.
+	Once carved, an object never moves.
+	We are free to append data of any size to the currently
+	  growing object.
+	Exactly one object is growing in an obstack at any one time.
+	You can run one obstack per control block.
+	You may have as many control blocks as you dare.
+	Because of the way we do it, you can `unwind' an obstack
+	  back to a previous state. (You may remove objects much
+	  as you would with a stack.)
+*/
+
+
+/* Don't do the contents of this file more than once.  */
+
+#ifndef _OBSTACK_H
+#define _OBSTACK_H 1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* We use subtraction of (char *) 0 instead of casting to int
+   because on word-addressable machines a simple cast to int
+   may ignore the byte-within-word field of the pointer.  */
+
+#ifndef __PTR_TO_INT
+# define __PTR_TO_INT(P) ((P) - (char *) 0)
+#endif
+
+#ifndef __INT_TO_PTR
+# define __INT_TO_PTR(P) ((P) + (char *) 0)
+#endif
+
+/* We need the type of the resulting object.  If __PTRDIFF_TYPE__ is
+   defined, as with GNU C, use that; that way we don't pollute the
+   namespace with <stddef.h>'s symbols.  Otherwise, if <stddef.h> is
+   available, include it and use ptrdiff_t.  In traditional C, long is
+   the best that we can do.  */
+
+#ifdef __PTRDIFF_TYPE__
+# define PTR_INT_TYPE __PTRDIFF_TYPE__
+#else
+# ifdef HAVE_STDDEF_H
+#  include <stddef.h>
+#  define PTR_INT_TYPE ptrdiff_t
+# else
+#  define PTR_INT_TYPE long
+# endif
+#endif
+
+#if defined _LIBC || defined HAVE_STRING_H
+# include <string.h>
+# define _obstack_memcpy(To, From, N) memcpy ((To), (From), (N))
+#else
+# ifdef memcpy
+#  define _obstack_memcpy(To, From, N) memcpy ((To), (char *)(From), (N))
+# else
+#  define _obstack_memcpy(To, From, N) bcopy ((char *)(From), (To), (N))
+# endif
+#endif
+
+struct _obstack_chunk		/* Lives at front of each chunk. */
+{
+  char  *limit;			/* 1 past end of this chunk */
+  struct _obstack_chunk *prev;	/* address of prior chunk or NULL */
+  char	contents[4];		/* objects begin here */
+};
+
+struct obstack		/* control current object in current chunk */
+{
+  long	chunk_size;		/* preferred size to allocate chunks in */
+  struct _obstack_chunk *chunk;	/* address of current struct obstack_chunk */
+  char	*object_base;		/* address of object we are building */
+  char	*next_free;		/* where to add next char to current object */
+  char	*chunk_limit;		/* address of char after current chunk */
+  PTR_INT_TYPE temp;		/* Temporary for some macros.  */
+  int   alignment_mask;		/* Mask of alignment for each object. */
+  /* These prototypes vary based on `use_extra_arg', and we use
+     casts to the prototypeless function type in all assignments,
+     but having prototypes here quiets -Wstrict-prototypes.  */
+  struct _obstack_chunk *(*chunkfun) (void *, long);
+  void (*freefun) (void *, struct _obstack_chunk *);
+  void *extra_arg;		/* first arg for chunk alloc/dealloc funcs */
+  unsigned use_extra_arg:1;	/* chunk alloc/dealloc funcs take extra arg */
+  unsigned maybe_empty_object:1;/* There is a possibility that the current
+				   chunk contains a zero-length object.  This
+				   prevents freeing the chunk if we allocate
+				   a bigger chunk to replace it. */
+  unsigned alloc_failed:1;	/* No longer used, as we now call the failed
+				   handler on error, but retained for binary
+				   compatibility.  */
+};
+
+/* Declare the external functions we use; they are in obstack.c.  */
+
+extern void _obstack_newchunk (struct obstack *, int);
+extern void _obstack_free (struct obstack *, void *);
+extern int _obstack_begin (struct obstack *, int, int,
+			    void *(*) (long), void (*) (void *));
+extern int _obstack_begin_1 (struct obstack *, int, int,
+			     void *(*) (void *, long),
+			     void (*) (void *, void *), void *);
+extern int _obstack_memory_used (struct obstack *);
+
+/* Do the function-declarations after the structs
+   but before defining the macros.  */
+
+void obstack_init (struct obstack *obstack);
+
+void * obstack_alloc (struct obstack *obstack, int size);
+
+void * obstack_copy (struct obstack *obstack, void *address, int size);
+void * obstack_copy0 (struct obstack *obstack, void *address, int size);
+
+void obstack_free (struct obstack *obstack, void *block);
+
+void obstack_blank (struct obstack *obstack, int size);
+
+void obstack_grow (struct obstack *obstack, void *data, int size);
+void obstack_grow0 (struct obstack *obstack, void *data, int size);
+
+void obstack_1grow (struct obstack *obstack, int data_char);
+void obstack_ptr_grow (struct obstack *obstack, void *data);
+void obstack_int_grow (struct obstack *obstack, int data);
+
+void * obstack_finish (struct obstack *obstack);
+
+int obstack_object_size (struct obstack *obstack);
+
+int obstack_room (struct obstack *obstack);
+void obstack_make_room (struct obstack *obstack, int size);
+void obstack_1grow_fast (struct obstack *obstack, int data_char);
+void obstack_ptr_grow_fast (struct obstack *obstack, void *data);
+void obstack_int_grow_fast (struct obstack *obstack, int data);
+void obstack_blank_fast (struct obstack *obstack, int size);
+
+void * obstack_base (struct obstack *obstack);
+void * obstack_next_free (struct obstack *obstack);
+int obstack_alignment_mask (struct obstack *obstack);
+int obstack_chunk_size (struct obstack *obstack);
+int obstack_memory_used (struct obstack *obstack);
+
+/* Error handler called when `obstack_chunk_alloc' failed to allocate
+   more memory.  This can be set to a user defined function.  The
+   default action is to print a message and abort.  */
+extern void (*obstack_alloc_failed_handler) (void);
+
+/* Exit value used when `print_and_abort' is used.  */
+extern int obstack_exit_failure;
+
+/* Pointer to beginning of object being allocated or to be allocated next.
+   Note that this might not be the final address of the object
+   because a new chunk might be needed to hold the final size.  */
+
+#define obstack_base(h) ((h)->object_base)
+
+/* Size for allocating ordinary chunks.  */
+
+#define obstack_chunk_size(h) ((h)->chunk_size)
+
+/* Pointer to next byte not yet allocated in current chunk.  */
+
+#define obstack_next_free(h)	((h)->next_free)
+
+/* Mask specifying low bits that should be clear in address of an object.  */
+
+#define obstack_alignment_mask(h) ((h)->alignment_mask)
+
+/* To prevent prototype warnings provide complete argument list in
+   standard C version.  */
+# define obstack_init(h) \
+  _obstack_begin ((h), 0, 0, \
+		  (void *(*) (long)) obstack_chunk_alloc, (void (*) (void *)) obstack_chunk_free)
+
+# define obstack_begin(h, size) \
+  _obstack_begin ((h), (size), 0, \
+		  (void *(*) (long)) obstack_chunk_alloc, (void (*) (void *)) obstack_chunk_free)
+
+# define obstack_specify_allocation(h, size, alignment, chunkfun, freefun) \
+  _obstack_begin ((h), (size), (alignment), \
+		    (void *(*) (long)) (chunkfun), (void (*) (void *)) (freefun))
+
+# define obstack_specify_allocation_with_arg(h, size, alignment, chunkfun, freefun, arg) \
+  _obstack_begin_1 ((h), (size), (alignment), \
+		    (void *(*) (void *, long)) (chunkfun), \
+		    (void (*) (void *, void *)) (freefun), (arg))
+
+# define obstack_chunkfun(h, newchunkfun) \
+  ((h) -> chunkfun = (struct _obstack_chunk *(*)(void *, long)) (newchunkfun))
+
+# define obstack_freefun(h, newfreefun) \
+  ((h) -> freefun = (void (*)(void *, struct _obstack_chunk *)) (newfreefun))
+
+#define obstack_1grow_fast(h,achar) (*((h)->next_free)++ = (achar))
+
+#define obstack_blank_fast(h,n) ((h)->next_free += (n))
+
+#define obstack_memory_used(h) _obstack_memory_used (h)
+
+#if defined __GNUC__ && defined __STDC__ && __STDC__
+/* NextStep 2.0 cc is really gcc 1.93 but it defines __GNUC__ = 2 and
+   does not implement __extension__.  But that compiler doesn't define
+   __GNUC_MINOR__.  */
+# if __GNUC__ < 2 || (__NeXT__ && !__GNUC_MINOR__)
+#  define __extension__
+# endif
+
+/* For GNU C, if not -traditional,
+   we can define these macros to compute all args only once
+   without using a global variable.
+   Also, we can avoid using the `temp' slot, to make faster code.  */
+
+# define obstack_object_size(OBSTACK)					\
+  __extension__								\
+  ({ struct obstack *__o = (OBSTACK);					\
+     (unsigned) (__o->next_free - __o->object_base); })
+
+# define obstack_room(OBSTACK)						\
+  __extension__								\
+  ({ struct obstack *__o = (OBSTACK);					\
+     (unsigned) (__o->chunk_limit - __o->next_free); })
+
+# define obstack_make_room(OBSTACK,length)				\
+__extension__								\
+({ struct obstack *__o = (OBSTACK);					\
+   int __len = (length);						\
+   if (__o->chunk_limit - __o->next_free < __len)			\
+     _obstack_newchunk (__o, __len);					\
+   (void) 0; })
+
+# define obstack_empty_p(OBSTACK)					\
+  __extension__								\
+  ({ struct obstack *__o = (OBSTACK);					\
+     (__o->chunk->prev == 0 && __o->next_free - __o->chunk->contents == 0); })
+
+# define obstack_grow(OBSTACK,where,length)				\
+__extension__								\
+({ struct obstack *__o = (OBSTACK);					\
+   int __len = (length);						\
+   if (__o->next_free + __len > __o->chunk_limit)			\
+     _obstack_newchunk (__o, __len);					\
+   _obstack_memcpy (__o->next_free, (where), __len);			\
+   __o->next_free += __len;						\
+   (void) 0; })
+
+# define obstack_grow0(OBSTACK,where,length)				\
+__extension__								\
+({ struct obstack *__o = (OBSTACK);					\
+   int __len = (length);						\
+   if (__o->next_free + __len + 1 > __o->chunk_limit)			\
+     _obstack_newchunk (__o, __len + 1);				\
+   _obstack_memcpy (__o->next_free, (where), __len);			\
+   __o->next_free += __len;						\
+   *(__o->next_free)++ = 0;						\
+   (void) 0; })
+
+# define obstack_1grow(OBSTACK,datum)					\
+__extension__								\
+({ struct obstack *__o = (OBSTACK);					\
+   if (__o->next_free + 1 > __o->chunk_limit)				\
+     _obstack_newchunk (__o, 1);					\
+   obstack_1grow_fast (__o, datum);					\
+   (void) 0; })
+
+/* These assume that the obstack alignment is good enough for pointers or ints,
+   and that the data added so far to the current object
+   shares that much alignment.  */
+
+# define obstack_ptr_grow(OBSTACK,datum)				\
+__extension__								\
+({ struct obstack *__o = (OBSTACK);					\
+   if (__o->next_free + sizeof (void *) > __o->chunk_limit)		\
+     _obstack_newchunk (__o, sizeof (void *));				\
+   obstack_ptr_grow_fast (__o, datum); })
+
+# define obstack_int_grow(OBSTACK,datum)				\
+__extension__								\
+({ struct obstack *__o = (OBSTACK);					\
+   if (__o->next_free + sizeof (int) > __o->chunk_limit)		\
+     _obstack_newchunk (__o, sizeof (int));				\
+   obstack_int_grow_fast (__o, datum); })
+
+# define obstack_ptr_grow_fast(OBSTACK,aptr)				\
+__extension__								\
+({ struct obstack *__o1 = (OBSTACK);					\
+   *(const void **) __o1->next_free = (aptr);				\
+   __o1->next_free += sizeof (const void *);				\
+   (void) 0; })
+
+# define obstack_int_grow_fast(OBSTACK,aint)				\
+__extension__								\
+({ struct obstack *__o1 = (OBSTACK);					\
+   *(int *) __o1->next_free = (aint);					\
+   __o1->next_free += sizeof (int);					\
+   (void) 0; })
+
+# define obstack_blank(OBSTACK,length)					\
+__extension__								\
+({ struct obstack *__o = (OBSTACK);					\
+   int __len = (length);						\
+   if (__o->chunk_limit - __o->next_free < __len)			\
+     _obstack_newchunk (__o, __len);					\
+   obstack_blank_fast (__o, __len);					\
+   (void) 0; })
+
+# define obstack_alloc(OBSTACK,length)					\
+__extension__								\
+({ struct obstack *__h = (OBSTACK);					\
+   obstack_blank (__h, (length));					\
+   obstack_finish (__h); })
+
+# define obstack_copy(OBSTACK,where,length)				\
+__extension__								\
+({ struct obstack *__h = (OBSTACK);					\
+   obstack_grow (__h, (where), (length));				\
+   obstack_finish (__h); })
+
+# define obstack_copy0(OBSTACK,where,length)				\
+__extension__								\
+({ struct obstack *__h = (OBSTACK);					\
+   obstack_grow0 (__h, (where), (length));				\
+   obstack_finish (__h); })
+
+/* The local variable is named __o1 to avoid a name conflict
+   when obstack_blank is called.  */
+# define obstack_finish(OBSTACK)  					\
+__extension__								\
+({ struct obstack *__o1 = (OBSTACK);					\
+   void *value;								\
+   value = (void *) __o1->object_base;					\
+   if (__o1->next_free == value)					\
+     __o1->maybe_empty_object = 1;					\
+   __o1->next_free							\
+     = __INT_TO_PTR ((__PTR_TO_INT (__o1->next_free)+__o1->alignment_mask)\
+		     & ~ (__o1->alignment_mask));			\
+   if (__o1->next_free - (char *)__o1->chunk				\
+       > __o1->chunk_limit - (char *)__o1->chunk)			\
+     __o1->next_free = __o1->chunk_limit;				\
+   __o1->object_base = __o1->next_free;					\
+   value; })
+
+# define obstack_free(OBSTACK, OBJ)					\
+__extension__								\
+({ struct obstack *__o = (OBSTACK);					\
+   void *__obj = (void *) (OBJ);					\
+   if (__obj > (void *)__o->chunk && __obj < (void *)__o->chunk_limit)  \
+     __o->next_free = __o->object_base = (char *) __obj;		\
+   else (obstack_free) (__o, __obj); })
+
+#else /* not __GNUC__ or not __STDC__ */
+
+# define obstack_object_size(h) \
+ (unsigned) ((h)->next_free - (h)->object_base)
+
+# define obstack_room(h)		\
+ (unsigned) ((h)->chunk_limit - (h)->next_free)
+
+# define obstack_empty_p(h) \
+ ((h)->chunk->prev == 0 && (h)->next_free - (h)->chunk->contents == 0)
+
+/* Note that the call to _obstack_newchunk is enclosed in (..., 0)
+   so that we can avoid having void expressions
+   in the arms of the conditional expression.
+   Casting the third operand to void was tried before,
+   but some compilers won't accept it.  */
+
+# define obstack_make_room(h,length)					\
+( (h)->temp = (length),							\
+  (((h)->next_free + (h)->temp > (h)->chunk_limit)			\
+   ? (_obstack_newchunk ((h), (h)->temp), 0) : 0))
+
+# define obstack_grow(h,where,length)					\
+( (h)->temp = (length),							\
+  (((h)->next_free + (h)->temp > (h)->chunk_limit)			\
+   ? (_obstack_newchunk ((h), (h)->temp), 0) : 0),			\
+  _obstack_memcpy ((h)->next_free, (where), (h)->temp),			\
+  (h)->next_free += (h)->temp)
+
+# define obstack_grow0(h,where,length)					\
+( (h)->temp = (length),							\
+  (((h)->next_free + (h)->temp + 1 > (h)->chunk_limit)			\
+   ? (_obstack_newchunk ((h), (h)->temp + 1), 0) : 0),			\
+  _obstack_memcpy ((h)->next_free, (where), (h)->temp),			\
+  (h)->next_free += (h)->temp,						\
+  *((h)->next_free)++ = 0)
+
+# define obstack_1grow(h,datum)						\
+( (((h)->next_free + 1 > (h)->chunk_limit)				\
+   ? (_obstack_newchunk ((h), 1), 0) : 0),				\
+  obstack_1grow_fast (h, datum))
+
+# define obstack_ptr_grow(h,datum)					\
+( (((h)->next_free + sizeof (char *) > (h)->chunk_limit)		\
+   ? (_obstack_newchunk ((h), sizeof (char *)), 0) : 0),		\
+  obstack_ptr_grow_fast (h, datum))
+
+# define obstack_int_grow(h,datum)					\
+( (((h)->next_free + sizeof (int) > (h)->chunk_limit)			\
+   ? (_obstack_newchunk ((h), sizeof (int)), 0) : 0),			\
+  obstack_int_grow_fast (h, datum))
+
+# define obstack_ptr_grow_fast(h,aptr)					\
+  (((const void **) ((h)->next_free += sizeof (void *)))[-1] = (aptr))
+
+# define obstack_int_grow_fast(h,aint)					\
+  (((int *) ((h)->next_free += sizeof (int)))[-1] = (aptr))
+
+# define obstack_blank(h,length)					\
+( (h)->temp = (length),							\
+  (((h)->chunk_limit - (h)->next_free < (h)->temp)			\
+   ? (_obstack_newchunk ((h), (h)->temp), 0) : 0),			\
+  obstack_blank_fast (h, (h)->temp))
+
+# define obstack_alloc(h,length)					\
+ (obstack_blank ((h), (length)), obstack_finish ((h)))
+
+# define obstack_copy(h,where,length)					\
+ (obstack_grow ((h), (where), (length)), obstack_finish ((h)))
+
+# define obstack_copy0(h,where,length)					\
+ (obstack_grow0 ((h), (where), (length)), obstack_finish ((h)))
+
+# define obstack_finish(h)  						\
+( ((h)->next_free == (h)->object_base					\
+   ? (((h)->maybe_empty_object = 1), 0)					\
+   : 0),								\
+  (h)->temp = __PTR_TO_INT ((h)->object_base),				\
+  (h)->next_free							\
+    = __INT_TO_PTR ((__PTR_TO_INT ((h)->next_free)+(h)->alignment_mask)	\
+		    & ~ ((h)->alignment_mask)),				\
+  (((h)->next_free - (char *) (h)->chunk				\
+    > (h)->chunk_limit - (char *) (h)->chunk)				\
+   ? ((h)->next_free = (h)->chunk_limit) : 0),				\
+  (h)->object_base = (h)->next_free,					\
+  (void *) __INT_TO_PTR ((h)->temp))
+
+# define obstack_free(h,obj)						\
+( (h)->temp = (char *) (obj) - (char *) (h)->chunk,			\
+  (((h)->temp > 0 && (h)->temp < (h)->chunk_limit - (char *) (h)->chunk)\
+   ? (((h)->next_free = (h)->object_base				\
+	    = (h)->temp + (char *) (h)->chunk), 0)			\
+   : ((obstack_free) ((h), (h)->temp + (char *) (h)->chunk), 0)))
+
+#endif /* not __GNUC__ or not __STDC__ */
+
+#ifdef __cplusplus
+}	/* C++ */
+#endif
+
+#endif /* obstack.h */
diff --git a/binutils-2.25/include/opcode/ChangeLog b/binutils-2.25/include/opcode/ChangeLog
new file mode 100644
index 00000000..f645a7e7
--- /dev/null
+++ b/binutils-2.25/include/opcode/ChangeLog
@@ -0,0 +1,1916 @@
+2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
+
+	* mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
+	(mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
+	For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
+	+T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
+	For MIPS, update extension character sequences after +.
+	(ASE_MSA): New define.
+	(ASE_MSA64): New define.
+	For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
+	+x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
+	For microMIPS, update extension character sequences after +.
+
+2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
+
+	PR binutils/15834
+	* i960.h: Fix typos.
+
+2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h: Remove references to "+I" and imm2_expr.
+
+2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h (M_DEXT, M_DINS): Delete.
+
+2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h (OP_OPTIONAL_REG): New mips_operand_type.
+	(mips_optional_operand_p): New function.
+
+2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
+	    Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h: Document new VU0 operand characters.
+	(OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
+	(OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
+	(OP_REG_R5900_ACC): New mips_reg_operand_types.
+	(INSN2_VU0_CHANNEL_SUFFIX): New macro.
+	(mips_vu0_channel_mask): Declare.
+
+2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
+	(mips_int_operand_min, mips_int_operand_max): New functions.
+	(mips_decode_pcrel_operand): Use mips_decode_int_operand.
+
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h (mips_decode_reg_operand): New function.
+	(INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
+	(INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
+	(INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
+	New macros.
+	(INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
+	(INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
+	(INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
+	(INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
+	(INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
+	(INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
+	(INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
+	(INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
+	(INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
+	(INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete.  Renumber other
+	macros to cover the gaps.
+	(INSN2_MOD_SP): Replace with...
+	(INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
+	(MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
+	(MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
+	(MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
+	(MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
+	Delete.
+
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
+	(MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
+	(MIPS16_INSN_COND_BRANCH): Delete.
+
+2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
+	    Kirill Yukhin  <kirill.yukhin@intel.com>
+	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+	* i386.h (BND_PREFIX_OPCODE): New.
+
+2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
+	OP_SAVE_RESTORE_LIST.
+	(decode_mips16_operand): Declare.
+
+2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h (mips_operand_type, mips_reg_operand_type): New enums.
+	(mips_operand, mips_int_operand, mips_mapped_int_operand)
+	(mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
+	(mips_pcrel_operand): New structures.
+	(mips_insert_operand, mips_extract_operand, mips_signed_operand)
+	(mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
+	(decode_mips_operand, decode_micromips_operand): Declare.
+
+2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h: Document MIPS16 "I" opcode.
+
+2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
+	(M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
+	(M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
+	(M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
+	(M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
+	(M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
+	(M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
+	(M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
+	(M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
+	(M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
+	(M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
+	(M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
+	(M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
+	Rename to...
+	(M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
+	(M_USD_AB): ...these.
+
+2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h: Remove documentation of "[" and "]".  Update documentation
+	of "k" and the MDMX formats.
+
+2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h: Update documentation of "+s" and "+S".
+
+2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h: Document "+i".
+
+2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h: Remove "mi" documentation.  Update "mh" documentation.
+	(OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
+	Delete.
+	(INSN2_WRITE_GPR_MHI): Rename to...
+	(INSN2_WRITE_GPR_MH): ...this.
+
+2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h: Remove documentation of "+D" and "+T".
+
+2013-06-26  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
+	Use "source" rather than "destination" for microMIPS "G".
+
+2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
+	values.
+
+2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
+
+2013-06-17  Catherine Moore  <clm@codesourcery.com>
+	    Maciej W. Rozycki  <macro@codesourcery.com>
+	    Chao-Ying Fu  <fu@mips.com>
+
+	* mips.h (OP_SH_EVAOFFSET): Define.
+	(OP_MASK_EVAOFFSET): Define.
+	(INSN_ASE_MASK): Delete.
+	(ASE_EVA): Define.
+	(M_CACHEE_AB, M_CACHEE_OB): New.
+	(M_LBE_OB, M_LBE_AB): New.
+	(M_LBUE_OB, M_LBUE_AB): New.
+	(M_LHE_OB, M_LHE_AB): New.
+	(M_LHUE_OB, M_LHUE_AB): New.
+	(M_LLE_AB, M_LLE_OB): New.
+	(M_LWE_OB, M_LWE_AB): New.
+	(M_LWLE_AB, M_LWLE_OB): New.
+	(M_LWRE_AB, M_LWRE_OB): New.
+	(M_PREFE_AB, M_PREFE_OB): New.
+	(M_SCE_AB, M_SCE_OB): New.
+	(M_SBE_OB, M_SBE_AB): New.
+	(M_SHE_OB, M_SHE_AB): New.
+	(M_SWE_OB, M_SWE_AB): New.
+	(M_SWLE_AB, M_SWLE_OB): New.
+	(M_SWRE_AB, M_SWRE_OB): New.
+	(MICROMIPSOP_SH_EVAOFFSET): Define.
+	(MICROMIPSOP_MASK_EVAOFFSET): Define.
+
+2013-06-12  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* nios2.h (OP_MATCH_ERET): Correct eret encoding.
+
+2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
+
+	* mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
+
+2013-05-09  Andrew Pinski  <apinski@cavium.com>
+
+	* mips.h (OP_MASK_CODE10): Correct definition.
+	(OP_SH_CODE10): Likewise.
+	Add a comment that "+J" is used now for OP_*CODE10.
+	(INSN_ASE_MASK): Update.
+	(INSN_VIRT): New macro.
+	(INSN_VIRT64): New macro
+
+2013-05-02  Nick Clifton  <nickc@redhat.com>
+
+	* msp430.h: Add patterns for MSP430X instructions.
+
+2013-04-06  David S. Miller  <davem@davemloft.net>
+
+	* sparc.h (F_PREFERRED): Define.
+	(F_PREF_ALIAS): Define.
+
+2013-04-03  Nick Clifton  <nickc@redhat.com>
+
+	* v850.h (V850_INVERSE_PCREL): Define.
+
+2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
+
+	PR binutils/15068
+	* tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
+
+2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
+
+	PR binutils/15068
+	* tic6xc-insn-formats.h (FLD): Add use of bitfield array.
+	Add 16-bit opcodes.
+	* tic6xc-opcode-table.h: Add 16-bit insns.
+	* tic6x.h: Add support for 16-bit insns.
+
+2013-03-21  Michael Schewe  <michael.schewe@gmx.net>
+
+	* h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
+	and mov.b/w/l Rs,@(d:32,ERd).
+
+2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
+
+	PR gas/15082
+	* tic6x-opcode-table.h: Rename mpydp's specific operand type macro
+	from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
+	tic6x_operand_xregpair operand coding type.
+	Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
+	opcode field, usu ORXREGD1324 for the src2 operand and remove the
+	TIC6X_FLAG_NO_CROSS.
+
+2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
+
+	PR gas/15095
+	* tic6x.h (enum tic6x_coding_method): Add
+	tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
+	separately the msb and lsb of a register pair.  This is needed to
+	encode the opcodes in the same way as TI assembler does.
+	* tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
+	and rsqrdp opcodes to use the new field coding types.
+
+2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* arm.h (CRC_EXT_ARMV8): New constant.
+	(ARCH_CRC_ARMV8): New macro.
+
+2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64.h (AARCH64_FEATURE_CRC): New macro.
+
+2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
+            Andrew Jenner <andrew@codesourcery.com>
+
+	Based on patches from Altera Corporation.
+
+	* nios2.h: New file.
+
+2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
+
+2013-01-28  Alexis Deruelle  <alexis.deruelle@gmail.com>
+
+	PR gas/15069
+	* tic6x-opcode-table.h: Fix encoding of BNOP instruction.
+
+2013-01-24  Nick Clifton  <nickc@redhat.com>
+
+	* v850.h: Add e3v5 support.
+
+2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
+
+2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
+
+	* ppc.h (PPC_OPCODE_POWER8): New define.
+	(PPC_OPCODE_HTM): Likewise.
+
+2013-01-10  Will Newton <will.newton@imgtec.com>
+
+	* metag.h: New file.
+
+2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
+
+	* cr16.h (make_instruction): Rename to cr16_make_instruction.
+	(match_opcode): Rename to cr16_match_opcode.
+
+2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
+
+	* mips.h: Add support for r5900 instructions including lq and sq.
+
+2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
+
+	* cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
+	(make_instruction,match_opcode): Added function prototypes.
+	(cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
+
+2012-11-23  Alan Modra  <amodra@gmail.com>
+
+	* ppc.h (ppc_parse_cpu): Update prototype.
+
+2012-10-14  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
+	opcodes.  Likewise, use "cM" instead of "cm" in fstqs opcodes.
+
+2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
+
+2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
+
+	* ia64.h (ia64_opnd): Add new operand types.
+
+2012-08-21  David S. Miller  <davem@davemloft.net>
+
+	* sparc.h (F3F4): New macro.
+
+2012-08-13  Ian Bolton  <ian.bolton@arm.com>
+	    Laurent Desnogues  <laurent.desnogues@arm.com>
+	    Jim MacArthur  <jim.macarthur@arm.com>
+	    Marcus Shawcroft  <marcus.shawcroft@arm.com>
+	    Nigel Stephens  <nigel.stephens@arm.com>
+	    Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+	    Richard Earnshaw  <rearnsha@arm.com>
+	    Sofiane Naci  <sofiane.naci@arm.com>
+	    Tejas Belagod  <tejas.belagod@arm.com>
+	    Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64.h: New file.
+
+2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
+	    Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h (mips_opcode): Add the exclusions field.
+	(OPCODE_IS_MEMBER): Remove macro.
+	(cpu_is_member): New inline function.
+	(opcode_is_member): Likewise.
+
+2012-07-31  Chao-Ying Fu  <fu@mips.com>
+	    Catherine Moore  <clm@codesourcery.com>
+	    Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h: Document microMIPS DSP ASE usage.
+	(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
+	microMIPS DSP ASE support.
+	(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
+	(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
+	(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
+	(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
+	(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
+	(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
+	(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
+
+2012-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h: Fix a typo in description.
+
+2012-06-07  Georg-Johann Lay  <avr@gjlay.de>
+
+	* avr.h: (AVR_ISA_XCH): New define.
+	(AVR_ISA_XMEGA): Use it.
+	(XCH, LAS, LAT, LAC): New XMEGA opcodes.
+
+2012-05-15  James Murray <jsm@jsm-net.demon.co.uk>
+
+	* m68hc11.h: Add XGate definitions.
+	(struct m68hc11_opcode): Add xg_mask field.
+
+2012-05-14  Catherine Moore  <clm@codesourcery.com>
+	    Maciej W. Rozycki  <macro@codesourcery.com>
+	    Rhonda Wittels  <rhonda@codesourcery.com>
+
+	* ppc.h (PPC_OPCODE_VLE): New definition.
+	(PPC_OP_SA): New macro.
+	(PPC_OP_SE_VLE): New macro.
+	(PPC_OP): Use a variable shift amount.
+	(powerpc_operand): Update comments.
+	(PPC_OPSHIFT_INV): New macro.
+	(PPC_OPERAND_CR): Replace with...
+	(PPC_OPERAND_CR_BIT): ...this and
+	(PPC_OPERAND_CR_REG): ...this.
+
+
+2012-05-03  Sean Keys  <skeys@ipdatasys.com>
+
+	* xgate.h: Header file for XGATE assembler.
+
+2012-04-27  David S. Miller  <davem@davemloft.net>
+
+	* sparc.h: Document new arg code' )' for crypto RS3
+	immediates.
+
+	* sparc.h (struct sparc_opcode): New field 'hwcaps'.
+	F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
+	F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
+	F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
+	(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
+	HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
+	HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
+	HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
+	HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
+	HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
+	HWCAP_CBCOND, HWCAP_CRC32): New defines.
+
+2012-03-10  Edmar Wienskoski  <edmar@freescale.com>
+
+	* ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
+
+2012-02-27  Alan Modra  <amodra@gmail.com>
+
+	* crx.h (cst4_map): Update declaration.
+
+2012-02-25  Walter Lee  <walt@tilera.com>
+
+	* tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
+	TILEGX_OPC_LD_TLS.
+	* tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
+	TILEPRO_OPC_LW_TLS_SN.
+
+2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386.h (XACQUIRE_PREFIX_OPCODE): New.
+	(XRELEASE_PREFIX_OPCODE): Likewise.
+
+2011-12-08  Andrew Pinski  <apinski@cavium.com>
+	    Adam Nemet  <anemet@caviumnetworks.com>
+
+	* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
+	(INSN_OCTEON2): New macro.
+	(CPU_OCTEON2): New macro.
+	(OPCODE_IS_MEMBER): Add Octeon2.
+
+2011-11-29  Andrew Pinski  <apinski@cavium.com>
+
+	* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
+	(INSN_OCTEONP): New macro.
+	(CPU_OCTEONP): New macro.
+	(OPCODE_IS_MEMBER): Add Octeon+.
+	(M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
+
+2011-11-01  DJ Delorie  <dj@redhat.com>
+
+	* rl78.h: New file.
+
+2011-10-24  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h: Fix a typo in description.
+
+2011-09-21  David S. Miller  <davem@davemloft.net>
+
+	* sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
+	(F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
+	F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
+	F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
+
+2011-08-09  Chao-ying Fu  <fu@mips.com>
+	    Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
+	(OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
+	(INSN_ASE_MASK): Add the MCU bit.
+	(INSN_MCU): New macro.
+	(M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
+	(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
+
+2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
+	(INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
+	(INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
+	(INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
+	(INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
+	(INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
+	(INSN2_READ_GPR_MMN): Likewise.
+	(INSN2_READ_FPR_D): Change the bit used.
+	(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
+	(INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
+	(INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
+	(INSN2_COND_BRANCH): Likewise.
+	(INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
+	(INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
+	(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
+	(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
+	(INSN2_MOD_GPR_MN): Likewise.
+
+2011-08-05  David S. Miller  <davem@davemloft.net>
+
+	* sparc.h: Document new format codes '4', '5', and '('.
+	(OPF_LOW4, RS3): New macros.
+
+2011-08-03  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h: Document the use of FP_D in MIPS16 mode.  Adjust the
+	order of flags documented.
+
+2011-07-29  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h: Clarify the description of microMIPS instruction
+	manipulation macros.
+	(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
+
+2011-07-24  Chao-ying Fu  <fu@mips.com>
+	    Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
+	(OP_MASK_STYPE, OP_SH_STYPE): Likewise.
+	(OP_MASK_CODE10, OP_SH_CODE10): Likewise.
+	(OP_MASK_TRAP, OP_SH_TRAP): Likewise.
+	(OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
+	(OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
+	(OP_MASK_RS3, OP_SH_RS3): Likewise.
+	(OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
+	(OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
+	(OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
+	(OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
+	(OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
+	(OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
+	(OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
+	(OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
+	(OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
+	(OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
+	(OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
+	(OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
+	(OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
+	(OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
+	(INSN_WRITE_GPR_S): New macro.
+	(INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
+	(INSN2_READ_FPR_D): Likewise.
+	(INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
+	(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
+	(INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
+	(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
+	(INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
+	(INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
+	(INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
+	(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
+	(CPU_MICROMIPS): New macro.
+	(M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
+	(M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
+	(M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
+	(M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
+	(M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
+	(M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
+	(M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
+	(M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
+	(M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
+	(M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
+	(M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
+	(M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
+	(M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
+	(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
+	(MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
+	(MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
+	(MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
+	(MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
+	(MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
+	(MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
+	(MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
+	(MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
+	(MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
+	(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
+	(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
+	(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
+	(MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
+	(MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
+	(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
+	(MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
+	(MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
+	(MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
+	(MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
+	(MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
+	(MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
+	(MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
+	(MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
+	(MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
+	(MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
+	(MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
+	(MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
+	(MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
+	(MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
+	(MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
+	(MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
+	(MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
+	(MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
+	(MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
+	(MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
+	(MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
+	(MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
+	(MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
+	(MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
+	(MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
+	(MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
+	(MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
+	(MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
+	(MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
+	(MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
+	(MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
+	(MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
+	(MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
+	(MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
+	(MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
+	(MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
+	(MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
+	(MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
+	(MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
+	(MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
+	(MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
+	(MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
+	(MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
+	(MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
+	(MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
+	(MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
+	(MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
+	(MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
+	(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
+	(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
+	(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
+	(MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
+	(MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
+	(MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
+	(MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
+	(MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
+	(MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
+	(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
+	(MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
+	(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
+	(MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
+	(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
+	(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
+	(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
+	(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
+	(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
+	(MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
+	(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
+	(MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
+	(MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
+	(MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
+	(MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
+	(MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
+	(MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
+	(MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
+	(MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
+	(micromips_opcodes): New declaration.
+	(bfd_micromips_num_opcodes): Likewise.
+
+2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h (INSN_TRAP): Rename to...
+	(INSN_NO_DELAY_SLOT): ... this.
+	(INSN_SYNC): Remove macro.
+
+2011-07-01  Eric B. Weddington  <eric.weddington@atmel.com>
+
+	* avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
+	a duplicate of AVR_ISA_SPM.
+
+2011-07-01  Nick Clifton  <nickc@redhat.com>
+
+	* avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
+
+2011-06-18  Robin Getz  <robin.getz@analog.com>
+
+	* bfin.h (is_macmod_signed): New func
+
+2011-06-18  Mike Frysinger  <vapier@gentoo.org>
+
+	* bfin.h (is_macmod_pmove): Add missing space before func args.
+	(is_macmod_hmove): Likewise.
+
+2011-06-13  Walter Lee  <walt@tilera.com>
+
+	* tilegx.h: New file.
+	* tilepro.h: New file.
+
+2011-05-31  Paul Brook  <paul@codesourcery.com>
+
+	* arm.h (ARM_ARCH_V7R_IDIV): Define.
+
+2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* s390.h: Replace S390_OPERAND_REG_EVEN with
+	S390_OPERAND_REG_PAIR.
+
+2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* s390.h: Add S390_OPCODE_REG_EVEN flag.
+
+2011-04-18  Julian Brown  <julian@codesourcery.com>
+
+	* arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
+
+2011-04-11  Dan McDonald  <dan@wellkeeper.com>
+
+	PR gas/12296
+	* arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
+
+2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
+
+	* avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
+	New instruction set flags.
+	(AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
+
+2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h (M_PREF_AB): New enum value.
+
+2011-02-12  Mike Frysinger  <vapier@gentoo.org>
+
+	* bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
+	M_IU): Define.
+	(is_macmod_pmove, is_macmod_hmove): New functions.
+
+2011-02-11  Mike Frysinger  <vapier@gentoo.org>
+
+	* bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
+
+2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
+
+	* tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
+	* tic6x.h (TIC6X_INSN_ATOMIC): Remove.
+
+2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	PR gas/11395
+	* hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
+	"bb" entries.
+
+2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	PR gas/11395
+	* hppa.h: Clear "d" bit in "add" and "sub" patterns.
+
+2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h: Update commentary after last commit.
+
+2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
+
+	* mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
+	(OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
+	(INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
+
+2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
+
+2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h: Fix previous commit.
+
+2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
+	(INSN_LOONGSON_3A): Clear bit 31.
+
+2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+	PR gas/12198
+	* arm.h (ARM_AEXT_V6M_ONLY): New define.
+	(ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
+	(ARM_ARCH_V6M_ONLY): New define.
+
+2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
+
+	* mips.h (INSN_LOONGSON_3A): Defined.
+	(CPU_LOONGSON_3A): Defined.
+	(OPCODE_IS_MEMBER): Add LOONGSON_3A.
+
+2010-10-09  Matt Rice  <ratmice@gmail.com>
+
+	* cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
+	(CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
+
+2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+	* arm.h (ARM_EXT_VIRT): New define.
+	(ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
+	(ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
+	Extensions.
+
+2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+	* arm.h (ARM_AEXT_ADIV): New define.
+	(ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
+
+2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+	* arm.h (ARM_EXT_OS): New define.
+	(ARM_AEXT_V6SM): Likewise.
+	(ARM_ARCH_V6SM): Likewise.
+
+2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+	* arm.h (ARM_EXT_MP): Add.
+	(ARM_ARCH_V7A_MP): Likewise.
+
+2010-09-22  Mike Frysinger  <vapier@gentoo.org>
+
+	* bfin.h: Declare pseudoChr structs/defines.
+
+2010-09-21  Mike Frysinger  <vapier@gentoo.org>
+
+	* bfin.h: Strip trailing whitespace.
+
+2010-07-29  DJ Delorie  <dj@redhat.com>
+
+	* rx.h (RX_Operand_Type): Add TwoReg.
+	(RX_Opcode_ID): Remove ediv and ediv2.
+
+2010-07-27  DJ Delorie  <dj@redhat.com>
+
+	* rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
+
+2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
+	    Ina Pandit  <ina.pandit@kpitcummins.com>
+
+	* v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
+	PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
+	PROCESSOR_V850E2_ALL.
+	Remove PROCESSOR_V850EA support.
+	(v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
+	V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
+	V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
+	V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
+	V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
+	V850_OPERAND_PERCENT.
+	Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
+	V850_NOT_R0.
+	Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
+	and V850E_PUSH_POP
+
+2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
+	(MIPS16_INSN_BRANCH): Rename to...
+	(MIPS16_INSN_COND_BRANCH): ... this.
+
+2010-07-03  Alan Modra  <amodra@gmail.com>
+
+	* ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
+	Renumber other PPC_OPCODE defines.
+
+2010-07-03  Alan Modra  <amodra@gmail.com>
+
+	* ppc.h (PPC_OPCODE_COMMON): Expand comment.
+
+2010-06-29  Alan Modra  <amodra@gmail.com>
+
+	* maxq.h: Delete file.
+
+2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
+
+	* ppc.h (PPC_OPCODE_E500): Define.
+
+2010-05-26  Catherine Moore  <clm@codesourcery.com>
+
+	* opcode/mips.h (INSN_MIPS16): Remove.
+
+2010-04-21  Joseph Myers  <joseph@codesourcery.com>
+
+	* tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
+
+2010-04-15  Nick Clifton  <nickc@redhat.com>
+
+	* alpha.h: Update copyright notice to use GPLv3.
+	* arc.h: Likewise.
+	* arm.h: Likewise.
+	* avr.h: Likewise.
+	* bfin.h: Likewise.
+	* cgen.h: Likewise.
+	* convex.h: Likewise.
+	* cr16.h: Likewise.
+	* cris.h: Likewise.
+	* crx.h: Likewise.
+	* d10v.h: Likewise.
+	* d30v.h: Likewise.
+	* dlx.h: Likewise.
+	* h8300.h: Likewise.
+	* hppa.h: Likewise.
+	* i370.h: Likewise.
+	* i386.h: Likewise.
+	* i860.h: Likewise.
+	* i960.h: Likewise.
+	* ia64.h: Likewise.
+	* m68hc11.h: Likewise.
+	* m68k.h: Likewise.
+	* m88k.h: Likewise.
+	* maxq.h: Likewise.
+	* mips.h: Likewise.
+	* mmix.h: Likewise.
+	* mn10200.h: Likewise.
+	* mn10300.h: Likewise.
+	* msp430.h: Likewise.
+	* np1.h: Likewise.
+	* ns32k.h: Likewise.
+	* or32.h: Likewise.
+	* pdp11.h: Likewise.
+	* pj.h: Likewise.
+	* pn.h: Likewise.
+	* ppc.h: Likewise.
+	* pyr.h: Likewise.
+	* rx.h: Likewise.
+	* s390.h: Likewise.
+	* score-datadep.h: Likewise.
+	* score-inst.h: Likewise.
+	* sparc.h: Likewise.
+	* spu-insns.h: Likewise.
+	* spu.h: Likewise.
+	* tic30.h: Likewise.
+	* tic4x.h: Likewise.
+	* tic54x.h: Likewise.
+	* tic80.h: Likewise.
+	* v850.h: Likewise.
+	* vax.h: Likewise.
+
+2010-03-25  Joseph Myers  <joseph@codesourcery.com>
+
+	* tic6x-control-registers.h, tic6x-insn-formats.h,
+	tic6x-opcode-table.h, tic6x.h: New.
+
+2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
+
+	* mips.h: (LOONGSON2F_NOP_INSN): New macro.
+
+2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
+
+	* opcode/ppc.h (PPC_OPCODE_TITAN): Define.
+
+2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ia64.h (ia64_find_opcode): Remove argument name.
+	(ia64_find_next_opcode): Likewise.
+	(ia64_dis_opcode): Likewise.
+	(ia64_free_opcode): Likewise.
+	(ia64_find_dependency): Likewise.
+
+2009-11-22  Doug Evans  <dje@sebabeach.org>
+
+	* cgen.h: Include bfd_stdint.h.
+	(CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
+
+2009-11-18  Paul Brook  <paul@codesourcery.com>
+
+	* arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
+
+2009-11-17  Paul Brook  <paul@codesourcery.com>
+	Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* arm.h (ARM_EXT_V6_DSP): Define.
+	(ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
+	(ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
+
+2009-11-04  DJ Delorie  <dj@redhat.com>
+
+	* rx.h (rx_decode_opcode) (mvtipl): Add.
+	(mvtcp, mvfcp, opecp): Remove.
+
+2009-11-02  Paul Brook  <paul@codesourcery.com>
+
+	* arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
+	FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
+	(FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
+	FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
+	FPU_ARCH_NEON_VFP_V4): Define.
+
+2009-10-23  Doug Evans  <dje@sebabeach.org>
+
+	* cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
+	* cgen.h: Update.  Improve multi-inclusion macro name.
+
+2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
+
+	* ppc.h (PPC_OPCODE_476): Define.
+
+2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
+
+	* ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
+
+2009-09-29  DJ Delorie  <dj@redhat.com>
+
+	* rx.h: New file.
+
+2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
+
+	* ppc.h (ppc_cpu_t): Typedef to uint64_t.
+
+2009-09-21  Ben Elliston  <bje@au.ibm.com>
+
+	* ppc.h (PPC_OPCODE_PPCA2): New.
+
+2009-09-05  Martin Thuresson  <martin@mtme.org>
+
+	* ia64.h (struct ia64_operand): Renamed member class to op_class.
+
+2009-08-29  Martin Thuresson  <martin@mtme.org>
+
+	* tic30.h (template): Rename type template to
+	insn_template. Updated code to use new name.
+	* tic54x.h (template): Rename type template to
+	insn_template.
+
+2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
+
+	* hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
+
+2009-06-11  Anthony Green  <green@moxielogic.com>
+
+	* moxie.h (MOXIE_F3_PCREL): Define.
+	(moxie_form3_opc_info): Grow.
+
+2009-06-06  Anthony Green  <green@moxielogic.com>
+
+	* moxie.h (MOXIE_F1_M): Define.
+
+2009-04-15  Anthony Green  <green@moxielogic.com>
+
+	* moxie.h: Created.
+
+2009-04-06  DJ Delorie  <dj@redhat.com>
+
+	* h8300.h: Add relaxation attributes to MOVA opcodes.
+
+2009-03-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (ppc_parse_cpu): Declare.
+
+2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
+
+	* score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
+	and _IMM11 for mbitclr and mbitset.
+	* score-datadep.h: Update dependency information.
+
+2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
+
+	* ppc.h (PPC_OPCODE_POWER7): New.
+
+2009-02-06  Doug Evans  <dje@google.com>
+
+	* i386.h: Add comment regarding sse* insns and prefixes.
+
+2009-02-03  Sandip Matte  <sandip@rmicorp.com>
+
+	* mips.h (INSN_XLR): Define.
+	(INSN_CHIP_MASK): Update.
+	(CPU_XLR): Define.
+	(OPCODE_IS_MEMBER): Update.
+	(M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
+
+2009-01-28  Doug Evans  <dje@google.com>
+
+	* opcode/i386.h: Add multiple inclusion protection.
+	(EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
+	(EDI_REG_NUM): New macros.
+	(MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
+	(SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
+	(REX_PREFIX_P): New macro.
+
+2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
+
+	* ppc.h (struct powerpc_opcode): New field "deprecated".
+	(PPC_OPCODE_NOPOWER4): Delete.
+
+2008-11-28  Joshua Kinard  <kumba@gentoo.org>
+
+	* mips.h: Define CPU_R14000, CPU_R16000.
+	(OPCODE_IS_MEMBER): Include R14000, R16000 in test.
+
+2008-11-18  Catherine Moore  <clm@codesourcery.com>
+
+	* arm.h (FPU_NEON_FP16): New.
+	(FPU_ARCH_NEON_FP16): New.
+
+2008-11-06  Chao-ying Fu  <fu@mips.com>
+
+	* mips.h: Doucument '1' for 5-bit sync type.
+
+2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
+	IA64_RS_CR.
+
+2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
+
+	* ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
+
+2008-07-30  Michael J. Eager  <eager@eagercon.com>
+
+	* ppc.h (PPC_OPCODE_405): Define.
+	(PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
+
+2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
+
+	* ppc.h (ppc_cpu_t): New typedef.
+	(struct powerpc_opcode <flags>): Use it.
+	(struct powerpc_operand <insert, extract>): Likewise.
+	(struct powerpc_macro <flags>): Likewise.
+
+2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
+
+	* mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
+	Update comment before MIPS16 field descriptors to mention MIPS16.
+	(OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
+	BBIT.
+	(OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
+	New bit masks and shift counts for cins and exts.
+
+	* mips.h: Document new field descriptors +Q.
+	(OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
+
+2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
+
+	* mips.h (INSN_MACRO): Move it up to the pinfo macros.
+	(INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
+
+2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
+
+	* ppc.h: (PPC_OPCODE_E500MC): New.
+
+2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386.h (MAX_OPERANDS): Set to 5.
+	(MAX_MNEM_SIZE): Changed to 20.
+
+2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
+
+	* avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
+
+2008-03-09  Paul Brook  <paul@codesourcery.com>
+
+	* arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
+
+2008-03-04  Paul Brook  <paul@codesourcery.com>
+
+	* arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
+	(ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
+	(ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
+
+2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
+	    Nick Clifton  <nickc@redhat.com>
+
+	PR 3134
+	* h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
+	with a 32-bit displacement but without the top bit of the 4th byte
+	set.
+
+2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+	* cr16.h (cr16_num_optab): Declared.
+
+2008-02-14  Hakan Ardo  <hakan@debian.org>
+
+	PR gas/2626
+	* avr.h (AVR_ISA_2xxe): Define.
+
+2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
+
+	* mips.h: Update copyright.
+	(INSN_CHIP_MASK): New macro.
+	(INSN_OCTEON): New macro.
+	(CPU_OCTEON): New macro.
+	(OPCODE_IS_MEMBER): Handle Octeon instructions.
+
+2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
+
+	* avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
+
+2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
+
+	* avr.h (AVR_ISA_USB162): Add new opcode set.
+	(AVR_ISA_AVR3): Likewise.
+
+2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* mips.h (INSN_LOONGSON_2E): New.
+	(INSN_LOONGSON_2F): New.
+	(CPU_LOONGSON_2E): New.
+	(CPU_LOONGSON_2F): New.
+	(OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
+
+2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* mips.h (INSN_ISA*): Redefine certain values as an
+	enumeration.  Update comments.
+	(mips_isa_table): New.
+	(ISA_MIPS*): Redefine to match enumeration.
+	(OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
+	values.
+
+2007-08-08  Ben Elliston  <bje@au.ibm.com>
+
+	* ppc.h (PPC_OPCODE_PPCPS): New.
+
+2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* m68k.h: Document j K & E.
+
+2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
+
+	* cr16.h: New file for CR16 target.
+
+2007-05-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (PPC_OPERAND_PLUS1): Update comment.
+
+2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* m68k.h (mcfisa_c): New.
+	(mcfusp, mcf_mask): Adjust.
+
+2007-04-20  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
+	(num_powerpc_operands): Declare.
+	(PPC_OPERAND_SIGNED et al): Redefine as hex.
+	(PPC_OPERAND_PLUS1): Define.
+
+2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386.h (REX_MODE64): Renamed to ...
+	(REX_W): This.
+	(REX_EXTX): Renamed to ...
+	(REX_R): This.
+	(REX_EXTY): Renamed to ...
+	(REX_X): This.
+	(REX_EXTZ): Renamed to ...
+	(REX_B): This.
+
+2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386.h: Add entries from config/tc-i386.h and move tables
+	to opcodes/i386-opc.h.
+
+2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386.h (FloatDR): Removed.
+	(i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
+
+2007-03-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* spu-insns.h: Add soma double-float insns.
+
+2007-02-20  Thiemo Seufer  <ths@mips.com>
+	    Chao-Ying Fu  <fu@mips.com>
+
+	* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
+	(INSN_DSPR2): Add flag for DSP R2 instructions.
+	(M_BALIGN): New macro.
+
+2007-02-14  Alan Modra  <amodra@bigpond.net.au>
+
+	* i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
+	and Seg3ShortFrom with Shortform.
+
+2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/4027
+	* i386.h (i386_optab): Put the real "test" before the pseudo
+	one.
+
+2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
+
+	* m68k.h (m68010up): OR fido_a.
+
+2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
+
+	* m68k.h (fido_a): New.
+
+2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
+
+	* m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
+	mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
+	values.
+
+2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
+
+2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* score-inst.h (enum score_insn_type): Add Insn_internal.
+
+2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
+	    Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
+	    Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
+	    Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* spu-insns.h: New file.
+	* spu.h: New file.
+
+2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
+
+	* ppc.h (PPC_OPCODE_CELL): Define.
+
+2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
+
+	* i386.h :  Modify opcode to support for the change in POPCNT opcode
+	in amdfam10 architecture.
+
+2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386.h: Replace CpuMNI with CpuSSSE3.
+
+2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
+	    Joseph Myers  <joseph@codesourcery.com>
+	    Ian Lance Taylor  <ian@wasabisystems.com>
+	    Ben Elliston  <bje@wasabisystems.com>
+
+	* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
+
+2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* score-datadep.h: New file.
+	* score-inst.h: New file.
+
+2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
+	movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
+	movdq2q and movq2dq.
+
+2006-07-10 Dwarakanath Rajagopal	<dwarak.rajagopal@amd.com>
+	   Michael Meissner		<michael.meissner@amd.com>
+
+	* i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
+
+2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386.h (i386_optab): Add "nop" with memory reference.
+
+2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386.h (i386_optab): Update comment for 64bit NOP.
+
+2006-06-06  Ben Elliston  <bje@au.ibm.com>
+	    Anton Blanchard  <anton@samba.org>
+
+	* ppc.h (PPC_OPCODE_POWER6): Define.
+	Adjust whitespace.
+
+2006-06-05  Thiemo Seufer  <ths@mips.com>
+
+	* mips.h: Improve description of MT flags.
+
+2006-05-25  Richard Sandiford  <richard@codesourcery.com>
+
+	* m68k.h (mcf_mask): Define.
+
+2006-05-05  Thiemo Seufer  <ths@mips.com>
+	    David Ung  <davidu@mips.com>
+
+	* mips.h (enum): Add macro M_CACHE_AB.
+
+2006-05-04  Thiemo Seufer  <ths@mips.com>
+	    Nigel Stephens  <nigel@mips.com>
+	    David Ung  <davidu@mips.com>
+
+	* mips.h: Add INSN_SMARTMIPS define.
+
+2006-04-30  Thiemo Seufer  <ths@mips.com>
+	    David Ung  <davidu@mips.com>
+
+	* mips.h: Defines udi bits and masks.  Add description of
+	characters which may appear in the args field of udi
+	instructions.
+
+2006-04-26  Thiemo Seufer  <ths@networkno.de>
+
+	* mips.h: Improve comments describing the bitfield instruction
+	fields.
+
+2006-04-26  Julian Brown  <julian@codesourcery.com>
+
+	* arm.h (FPU_VFP_EXT_V3): Define constant.
+	(FPU_NEON_EXT_V1): Likewise.
+	(FPU_VFP_HARD): Update.
+	(FPU_VFP_V3): Define macro.
+	(FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
+
+2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
+
+	* avr.h (AVR_ISA_PWMx): New.
+
+2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
+	cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
+	cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
+	cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
+	cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
+
+2006-03-10  Paul Brook  <paul@codesourcery.com>
+
+	* arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
+
+2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
+	first.  Correct mask of bb "B" opcode.
+
+2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
+
+	* i386.h (i386_optab): Support Intel Merom New Instructions.
+
+2006-02-24  Paul Brook  <paul@codesourcery.com>
+
+	* arm.h: Add V7 feature bits.
+
+2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
+
+2006-01-31  Paul Brook  <paul@codesourcery.com>
+	Richard Earnshaw <rearnsha@arm.com>
+
+	* arm.h: Use ARM_CPU_FEATURE.
+	(ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
+	(arm_feature_set): Change to a structure.
+	(ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
+	ARM_FEATURE): New macros.
+
+2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
+
+	* cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
+	(MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
+	(ADD_PC_INCR_OPCODE): Don't define.
+
+2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/1874
+	* i386.h (i386_optab): Add 64bit support for monitor and mwait.
+
+2005-11-14  David Ung  <davidu@mips.com>
+
+	* mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
+	instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
+	save/restore encoding of the args field.
+
+2005-10-28  Dave Brolley  <brolley@redhat.com>
+
+	Contribute the following changes:
+	2005-02-16  Dave Brolley  <brolley@redhat.com>
+
+	* cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
+	cgen_isa_mask_* to cgen_bitset_*.
+	* cgen.h: Likewise.
+
+	2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
+
+	* cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
+	(CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
+	(CGEN_CPU_TABLE): Make isas a ponter.
+
+	2003-09-29  Dave Brolley  <brolley@redhat.com>
+
+	* cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
+	(CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
+	(CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
+
+	2002-12-13  Dave Brolley  <brolley@redhat.com>
+
+	* cgen.h (symcat.h): #include it.
+	(cgen-bitset.h): #include it.
+	(CGEN_ATTR_VALUE_TYPE): Now a union.
+	(CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
+	(CGEN_ATTR_ENTRY): 'value' now unsigned.
+	(cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
+	* cgen-bitset.h: New file.
+
+2005-09-30  Catherine Moore  <clm@cm00re.com>
+
+	* bfin.h: New file.
+
+2005-10-24  Jan Beulich  <jbeulich@novell.com>
+
+	* ia64.h (enum ia64_opnd): Move memory operand out of set of
+	indirect operands.
+
+2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
+	Add FLAG_STRICT to pa10 ftest opcode.
+
+2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* hppa.h (pa_opcodes): Remove lha entries.
+
+2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* hppa.h (FLAG_STRICT): Revise comment.
+	(pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
+	before corresponding pa11 opcodes.  Add strict pa10 register-immediate
+	entries for "fdc".
+
+2005-09-30  Catherine Moore  <clm@cm00re.com>
+
+	* bfin.h: New file.
+
+2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
+
+2005-09-06  Chao-ying Fu  <fu@mips.com>
+
+	* mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
+	OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
+	define.
+	Document !, $, *, &, g, +t, +T operand formats for MT instructions.
+	(INSN_ASE_MASK): Update to include INSN_MT.
+	(INSN_MT): New define for MT ASE.
+
+2005-08-25  Chao-ying Fu  <fu@mips.com>
+
+	* mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
+	OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
+	OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
+	OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
+	OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
+	Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
+	instructions.
+	(INSN_DSP): New define for DSP ASE.
+
+2005-08-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* a29k.h: Delete.
+
+2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ppc.h (PPC_OPCODE_E300): Define.
+
+2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
+
+2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	PR gas/336
+ 	* hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
+	and pitlb.
+
+2005-07-27  Jan Beulich  <jbeulich@novell.com>
+
+	* i386.h (i386_optab): Add comment to movd. Use LongMem for all
+	movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
+	Add movq-s as 64-bit variants of movd-s.
+
+2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* hppa.h: Fix punctuation in comment.
+
+	* hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
+	implicit space-register addressing.  Set space-register bits on opcodes
+	using implicit space-register addressing.  Add various missing pa20
+	long-immediate opcodes.  Remove various opcodes using implicit 3-bit
+	space-register addressing.  Use "fE" instead of "fe" in various
+	fstw opcodes.
+
+2005-07-18  Jan Beulich  <jbeulich@novell.com>
+
+	* i386.h (i386_optab): Operands of aam and aad are unsigned.
+
+2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
+
+	* i386.h (i386_optab): Support Intel VMX Instructions.
+
+2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
+
+2005-07-05  Jan Beulich  <jbeulich@novell.com>
+
+	* i386.h (i386_optab): Add new insns.
+
+2005-07-01  Nick Clifton  <nickc@redhat.com>
+
+	* sparc.h: Add typedefs to structure declarations.
+
+2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 1013
+	* i386.h (i386_optab): Update comments for 64bit addressing on
+	mov. Allow 64bit addressing for mov and movq.
+
+2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
+	respectively, in various floating-point load and store patterns.
+
+2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* hppa.h (FLAG_STRICT): Correct comment.
+	(pa_opcodes): Update load and store entries to allow both PA 1.X and
+	PA 2.0 mneumonics when equivalent.  Entries with cache control
+	completers now require PA 1.1.  Adjust whitespace.
+
+2005-05-19  Anton Blanchard  <anton@samba.org>
+
+	* ppc.h (PPC_OPCODE_POWER5): Define.
+
+2005-05-10  Nick Clifton  <nickc@redhat.com>
+
+	* Update the address and phone number of the FSF organization in
+	the GPL notices in the following files:
+	a29k.h,	alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
+	crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
+	i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
+	mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
+	pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
+	tic54x.h, tic80.h, v850.h, vax.h
+
+2005-05-09  Jan Beulich  <jbeulich@novell.com>
+
+	* i386.h (i386_optab): Add ht and hnt.
+
+2005-04-18  Mark Kettenis  <kettenis@gnu.org>
+
+	* i386.h: Insert hyphens into selected VIA PadLock extensions.
+	Add xcrypt-ctr.  Provide aliases without hyphens.
+
+2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	Moved from ../ChangeLog
+
+	2005-04-12  Paul Brook  <paul@codesourcery.com>
+	* m88k.h: Rename psr macros to avoid conflicts.
+
+	2005-03-12  Zack Weinberg  <zack@codesourcery.com>
+	* arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
+	Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
+	and ARM_ARCH_V6ZKT2.
+
+	2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
+	* crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
+	Remove redundant instruction types.
+	(struct argument): X_op - new field.
+	(struct cst4_entry): Remove.
+	(no_op_insn): Declare.
+
+	2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
+	* crx.h (enum argtype): Rename types, remove unused types.
+
+	2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
+	* crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
+	(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
+	(enum operand_type): Rearrange operands, edit comments.
+	replace us<N> with ui<N> for unsigned immediate.
+	replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
+	displacements (respectively).
+	replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
+	(instruction type): Add NO_TYPE_INS.
+	(instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
+	(operand_entry): New field - 'flags'.
+	(operand flags): New.
+
+	2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
+	* crx.h (operand_type): Remove redundant types i3, i4,
+	i5, i8, i12.
+	Add new unsigned immediate types us3, us4, us5, us16.
+
+2005-04-12  Mark Kettenis  <kettenis@gnu.org>
+
+	* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
+	adjust them accordingly.
+
+2005-04-01  Jan Beulich  <jbeulich@novell.com>
+
+	* i386.h (i386_optab): Add rdtscp.
+
+2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386.h (i386_optab): Don't allow the `l' suffix for moving
+	between memory and segment register. Allow movq for moving between
+	general-purpose register and segment register.
+
+2005-02-09  Jan Beulich  <jbeulich@novell.com>
+
+	PR gas/707
+	* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
+	FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
+	fnstsw.
+
+2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* m68k.h (m68008, m68ec030, m68882): Remove.
+	(m68k_mask): New.
+	(cpu_m68k, cpu_cf): New.
+	(mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
+	mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
+
+2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
+
+	2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
+	* cgen.h (enum cgen_parse_operand_type): Add
+	CGEN_PARSE_OPERAND_SYMBOLIC.
+
+2005-01-21  Fred Fish  <fnf@specifixinc.com>
+
+	* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
+	Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
+	Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
+
+2005-01-19  Fred Fish  <fnf@specifixinc.com>
+
+	* mips.h (struct mips_opcode): Add new pinfo2 member.
+	(INSN_ALIAS): New define for opcode table entries that are
+	specific instances of another entry, such as 'move' for an 'or'
+	with a zero operand.
+	(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
+	(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
+
+2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
+
+	* mips.h (CPU_RM9000): Define.
+	(OPCODE_IS_MEMBER): Handle CPU_RM9000.
+
+2004-11-25 Jan Beulich  <jbeulich@novell.com>
+
+	* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
+	to/from test registers are illegal in 64-bit mode. Add missing
+	NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
+	(previously one had to explicitly encode a rex64 prefix). Re-enable
+	lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
+	support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
+
+2004-11-23 Jan Beulich  <jbeulich@novell.com>
+
+	* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
+	available only with SSE2. Change the MMX additions introduced by SSE
+	and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
+	instructions by their now designated identifier (since combining i686
+	and 3DNow! does not really imply 3DNow!A).
+
+2004-11-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
+	struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
+
+2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
+	    Vineet Sharma      <vineets@noida.hcltech.com>
+
+	* maxq.h: New file: Disassembly information for the maxq port.
+
+2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386.h (i386_optab): Put back "movzb".
+
+2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
+
+	* cris.h (enum cris_insn_version_usage): Tweak formatting and
+	comments.  Remove member cris_ver_sim.  Add members
+	cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
+	cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
+	(struct cris_support_reg, struct cris_cond15): New types.
+	(cris_conds15): Declare.
+	(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
+	(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
+	(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
+	(NOP_Z_BITS): Define in terms of NOP_OPCODE.
+	(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
+	SIZE_FIELD_UNSIGNED.
+
+2004-11-04 Jan Beulich  <jbeulich@novell.com>
+
+	* i386.h (sldx_Suf): Remove.
+	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
+	(q_FP): Define, implying no REX64.
+	(x_FP, sl_FP): Imply FloatMF.
+	(i386_optab): Split reg and mem forms of moving from segment registers
+	so that the memory forms can ignore the 16-/32-bit operand size
+	distinction. Adjust a few others for Intel mode. Remove *FP uses from
+	all non-floating-point instructions. Unite 32- and 64-bit forms of
+	movsx, movzx, and movd. Adjust floating point operations for the above
+	changes to the *FP macros. Add DefaultSize to floating point control
+	insns operating on larger memory ranges. Remove left over comments
+	hinting at certain insns being Intel-syntax ones where the ones
+	actually meant are already gone.
+
+2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* crx.h: Add COPS_REG_INS - Coprocessor Special register
+	instruction type.
+
+2004-09-30  Paul Brook  <paul@codesourcery.com>
+
+	* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
+	(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
+
+2004-09-11  Theodore A. Roth  <troth@openavr.org>
+
+	* avr.h: Add support for
+	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
+
+2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
+
+2004-08-24  Dmitry Diky  <diwil@spec.ru>
+
+	* msp430.h (msp430_opc): Add new instructions.
+	(msp430_rcodes): Declare new instructions.
+	(msp430_hcodes): Likewise..
+
+2004-08-13  Nick Clifton  <nickc@redhat.com>
+
+	PR/301
+	* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
+	processors.
+
+2004-08-30  Michal Ludvig  <mludvig@suse.cz>
+
+	* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
+
+2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
+
+2004-07-21  Jan Beulich  <jbeulich@novell.com>
+
+	* i386.h: Adjust instruction descriptions to better match the
+	specification.
+
+2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
+
+	* arm.h: Remove all old content.  Replace with architecture defines
+	from gas/config/tc-arm.c.
+
+2004-07-09  Andreas Schwab  <schwab@suse.de>
+
+	* m68k.h: Fix comment.
+
+2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* crx.h: New file.
+
+2004-06-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
+
+2004-05-24  Peter Barada  <peter@the-baradas.com>
+
+	* m68k.h: Add 'size' to m68k_opcode.
+
+2004-05-05  Peter Barada  <peter@the-baradas.com>
+
+	* m68k.h: Switch from ColdFire chip name to core variant.
+
+2004-04-22  Peter Barada  <peter@the-baradas.com>
+
+	* m68k.h: Add mcfmac/mcfemac definitions.  Update operand
+	descriptions for new EMAC cases.
+	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
+	handle Motorola MAC syntax.
+	Allow disassembly of ColdFire V4e object files.
+
+2004-03-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
+
+2004-03-12  Jakub Jelinek  <jakub@redhat.com>
+
+	* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
+
+2004-03-12  Michal Ludvig  <mludvig@suse.cz>
+
+	* i386.h (i386_optab): Added xstore as an alias for xstorerng.
+
+2004-03-12  Michal Ludvig  <mludvig@suse.cz>
+
+	* i386.h (i386_optab): Added xstore/xcrypt insns.
+
+2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
+
+	* h8300.h (32bit ldc/stc): Add relaxing support.
+
+2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
+
+	* h8300.h (BITOP): Pass MEMRELAX flag.
+
+2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
+
+	* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
+	except for the H8S.
+
+For older changes see ChangeLog-9103
+
+Copyright (C) 2004-2012 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.25/include/opcode/ChangeLog-9103 b/binutils-2.25/include/opcode/ChangeLog-9103
new file mode 100644
index 00000000..b56e7d53
--- /dev/null
+++ b/binutils-2.25/include/opcode/ChangeLog-9103
@@ -0,0 +1,3131 @@
+2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	2003-11-18  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+	* mips.h: Define new enum members, M_LCA_AB and M_DLCA_AB.
+
+	2003-04-04  Svein E. Seldal  <Svein.Seldal@solidas.com>
+	* tic4x.h: Namespace cleanup. Replace s/c4x/tic4x
+
+	2002-11-16  Klee Dienes  <kdienes@apple.com>
+	* m88k.h (INSTAB): Remove 'next' field.
+	(instruction): Remove definition; replace with extern declaration
+	and mark as const.
+
+	2002-08-28  Michael Hayes <m.hayes@elec.canterbury.ac.nz>
+	* tic4x.h: New file.
+
+	2002-07-25  Richard Sandiford  <rsandifo@redhat.com>
+	* mips.h (CPU_R2000): Remove.
+
+2003-10-21  Peter Barada  <pbarada@mail.wm.sps.mot.com>
+	    Bernardo Innocenti  <bernie@develer.com>
+
+	* m68k.h: Add MCFv4/MCF5528x support.
+
+2003-10-19  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* mmix.h (JMP_INSN_BYTE): Define.
+
+2003-09-30  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h: Document +E, +F, +G, +H, and +I operand types.
+	Update documentation of I, +B and +C operand types.
+	(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
+	(M_DEXT, M_DINS): New enum values.
+
+2003-09-04  Nick Clifton  <nickc@redhat.com>
+
+	* v850.h (PROCESSOR_V850E1): Define.
+
+2003-08-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (PPC_OPCODE_440): Define.  Formatting.  Use hex for other
+	PPC_OPCODE_* defines.
+
+2003-08-16  Jason Eckhardt  <jle@rice.edu>
+
+	* i860.h (fmov.ds): Expand as famov.ds.
+	(fmov.sd): Expand as famov.sd.
+	(pfmov.ds): Expand as pfamov.ds.
+
+2003-08-07  Michael Meissner  <gnu@the-meissners.org>
+
+	* cgen.h: Remove PARAM macro usage in all prototypes.
+	(CGEN_EXTRACT_INFO): Use void * instead of PTR.
+	(cgen_print_fn): Ditto.
+	(CGEN_HW_ENTRY): Ditto.
+	(CGEN_MAYBE_MULTI_IFLD): Ditto.
+	(struct cgen_insn): Ditto.
+	(CGEN_CPU_TABLE): Ditto.
+
+2003-08-07  Alan Modra  <amodra@bigpond.net.au>
+
+	* alpha.h: Remove PARAMS macro.
+	* arc.h: Likewise.
+	* d10v.h: Likewise.
+	* d30v.h: Likewise.
+	* i370.h: Likewise.
+	* or32.h: Likewise.
+	* pj.h: Likewise.
+	* ppc.h: Likewise.
+	* sparc.h: Likewise.
+	* tic80.h: Likewise.
+	* v850.h: Likewise.
+
+2003-07-18  Michael Snyder  <msnyder@redhat.com>
+
+	* include/opcode/h8sx.h (DO_MOVA1, DO_MOVA2): Reformatting.
+
+2003-07-15  Richard Sandiford  <rsandifo@redhat.com>
+
+	* mips.h (CPU_RM7000): New macro.
+	(OPCODE_IS_MEMBER): Match CPU_RM7000 against 4650 insns.
+
+2003-07-09  Alexandre Oliva  <aoliva@redhat.com>
+
+	2000-04-01  Alexandre Oliva  <aoliva@cygnus.com>
+	* mn10300.h (AM33_2): Renamed from AM33.
+	2000-03-31  Alexandre Oliva  <aoliva@cygnus.com>
+	* mn10300.h (AM332, FMT_D3): Defined.
+	(MN10300_OPERAND_FSREG, MN10300_OPERAND_FDREG): Likewise.
+	(MN10300_OPERAND_FPCR): Likewise.
+
+2003-07-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* s390.h (s390_opcode_cpu_val): Add enum for cpu type z990.
+
+2003-06-25  Richard Sandiford  <rsandifo@redhat.com>
+
+	* h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove.
+	(IMM8U, IMM8U_NS): Define.
+	(h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy.
+
+2003-06-25  Richard Sandiford  <rsandifo@redhat.com>
+
+	* h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERd and
+	mov.l ERs,@(dd:32,ERd) entries.
+
+2003-06-23  H.J. Lu <hongjiu.lu@intel.com>
+
+	* i386.h (i386_optab): Support Intel Precott New Instructions.
+
+2003-06-10  Gary Hade <garyhade@us.ibm.com>
+
+	* ppc.h (PPC_OPERAND_DQ): Define.
+
+2003-06-10  Richard Sandiford  <rsandifo@redhat.com>
+
+	* h8300.h (IMM4_NS, IMM8_NS): New.
+	(h8_opcodes): Replace IMM4 with IMM4_NS in mov.b and mov.w entries.
+	Likewise IMM8 for mov.w and mov.l.  Likewise IMM16U for mov.l.
+
+2003-06-03  Michael Snyder  <msnyder@redhat.com>
+
+	* h8300.h (enum h8_model): Add AV_H8S to distinguish from H8H.
+	(ldc): Split ccr ops from exr ops (which are only available
+	on H8S or H8SX).
+	(stc): Ditto.
+	(andc, orc, xorc): Ditto.
+	(ldmac, stmac, clrmac, mac): Change access to AV_H8S.
+
+2003-06-03  Michael Snyder  <msnyder@redhat.com>
+	and Bernd Schmidt   <bernds@redhat.com>
+	and Alexandre Oliva <aoliva@redhat.com>
+	* h8300.h: Add support for h8300sx instruction set.
+
+2003-05-23  Jason Eckhardt  <jle@rice.edu>
+
+	* i860.h (expand_type): Add XP_ONLY.
+	(scyc.b): New XP instruction.
+	(ldio.l): Likewise.
+	(ldio.s): Likewise.
+	(ldio.b): Likewise.
+	(ldint.l): Likewise.
+	(ldint.s): Likewise.
+	(ldint.b): Likewise.
+	(stio.l): Likewise.
+	(stio.s): Likewise.
+	(stio.b): Likewise.
+	(pfld.q): Likewise.
+
+2003-05-20  Jason Eckhardt  <jle@rice.edu>
+
+	* i860.h (flush): Set lower 3 bits properly and use 'L'
+	for the immediate operand type instead of 'i'.
+
+2003-05-20  Jason Eckhardt  <jle@rice.edu>
+
+	* i860.h (fzchks): Both S and R bits must be set.
+	(pfzchks): Likewise.
+	(faddp): Likewise.
+	(pfaddp): Likewise.
+	(fix.ss): Remove (invalid instruction).
+	(pfix.ss): Likewise.
+	(ftrunc.ss): Likewise.
+	(pftrunc.ss): Likewise.
+
+2003-05-18  Jason Eckhardt  <jle@rice.edu>
+
+	* i860.h (form, pform): Add missing .dd suffix.
+
+2003-05-13  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* m68hc11.h (M68HC12_BANK_VIRT): Define to 0x010000
+
+2003-04-07  Michael Snyder  <msnyder@redhat.com>
+
+	* h8300.h (ldc/stc): Fix up src/dst swaps.
+
+2003-04-09  J. Grant  <jg-binutils@jguk.org>
+
+	* mips.h: Correct comment typo.
+
+2003-03-21  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* s390.h (s390_opcode_arch_val): Rename to s390_opcode_mode_val.
+	(S390_OPCODE_ESAME): Rename to S390_OPCODE_ZARCH.
+	(s390_opcode): Remove architecture. Add modes and min_cpu.
+
+2003-03-17 D.Venkatasubramanian <dvenkat@noida.hcltech.com>
+
+	* h8300.h (O_SYS_CMDLINE): New pseudo opcode for command line
+	processing.
+
+2003-02-21  Noida D.Venkatasubramanian  <dvenkat@noida.hcltech.com>
+
+	* h8300.h (ldmac, stmac): Replace MACREG with MS32 and MD32.
+
+2003-01-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* m68hc11.h (cpu6812s): Define.
+
+2003-01-07  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h: Fix missing space in comment.
+	(INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5)
+	(INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right
+	by four bits.
+
+2003-01-02  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h: Update copyright years to include 2002 (which had
+	been missed previously) and 2003.  Make comments about "+A",
+	"+B", and "+C" operand types more descriptive.
+
+2002-12-31  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h: Note that the "+D" operand type name is now used.
+
+2002-12-30  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h: Document "+" as the start of two-character operand
+	type names, and add new "K", "+A", "+B", and "+C" operand types.
+	(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
+	(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
+	defines.
+
+2002-12-24    Dmitry Diky <diwil@mail.ru>
+
+	* msp430.h: New file.  Defines msp430 opcodes.
+
+2002-12-30 D.Venkatasubramanian <dvenkat@noida.hcltech.com>
+
+	* h8300.h: Added some more pseudo opcodes for system call
+	processing.
+
+2002-12-19  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h (OP_OP_COP0, OP_OP_COP1, OP_OP_COP2, OP_OP_COP3)
+	(OP_OP_LWC1, OP_OP_LWC2, OP_OP_LWC3, OP_OP_LDC1, OP_OP_LDC2)
+	(OP_OP_LDC3, OP_OP_SWC1, OP_OP_SWC2, OP_OP_SWC3, OP_OP_SDC1)
+	(OP_OP_SDC2, OP_OP_SDC3): Define.
+
+2002-12-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* hppa.h (completer_chars): #if 0 out.
+
+	* ns32k.h (struct ns32k_opcode): Constify "name", "operands" and
+	"default_args".
+	(struct not_wot): Constify "args".
+	(struct not): Constify "name".
+	(numopcodes): Delete.
+	(endop): Delete.
+
+2002-12-13  Alan Modra  <amodra@bigpond.net.au>
+
+	* pj.h (pj_opc_info_t): Add union.
+
+2002-12-04  David Mosberger  <davidm@hpl.hp.com>
+
+	* ia64.h: Fix copyright message.
+	(IA64_OPND_AR_CSD): New operand kind.
+
+2002-12-03  Richard Henderson  <rth@redhat.com>
+
+	* ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV.
+
+2002-12-03  Alan Modra  <amodra@bigpond.net.au>
+
+	* cgen.h (struct cgen_maybe_multi_ifield): Add "const PTR p" to union.
+	Constify "leaf" and "multi".
+
+2002-11-19  Klee Dienes  <kdienes@apple.com>
+
+	* h8300.h (h8_opcode): Remove 'noperands', 'idx', and 'size'
+	fields.
+	(h8_opcodes). Modify initializer and initializer macros to no
+	longer initialize the removed fields.
+
+2002-11-19  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+	* tic4x.h (c4x_insts): Fixed LDHI constraint
+
+2002-11-18  Klee Dienes  <kdienes@apple.com>
+
+	* h8300.h (h8_opcode): Remove 'length' field.
+	(h8_opcodes): Mark as 'const' (both the declaration and
+	definition).  Modify initializer and initializer macros to no
+	longer initialize the length field.
+
+2002-11-18  Klee Dienes  <kdienes@apple.com>
+
+	* arc.h (arc_ext_opcodes): Declare as extern.
+	(arc_ext_operands): Declare as extern.
+	* i860.h (i860_opcodes): Declare as const.
+
+2002-11-18  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+	* tic4x.h: File reordering. Added enhanced opcodes.
+
+2002-11-16  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+	* tic4x.h: Major rewrite of entire file. Define instruction
+	  classes, and put each instruction into a class.
+
+2002-11-11  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+	* tic4x.h: Added new opcodes and corrected some bugs.  Add support
+	for new DSP types.
+
+2002-10-14  Alan Modra  <amodra@bigpond.net.au>
+
+	* cgen.h: Test __BFD_H_SEEN__ rather than BFD_VERSION_DATE.
+
+2002-09-30  Gavin Romig-Koch  <gavin@redhat.com>
+	    Ken Raeburn  <raeburn@cygnus.com>
+	    Aldy Hernandez  <aldyh@redhat.com>
+	    Eric Christopher  <echristo@redhat.com>
+	    Richard Sandiford  <rsandifo@redhat.com>
+
+	* mips.h: Update comment for new opcodes.
+	(OP_MASK_VECBYTE, OP_SH_VECBYTE): New.
+	(OP_MASK_VECALIGN, OP_SH_VECALIGN): New.
+	(INSN_4111, INSN_4120, INSN_5400, INSN_5500): New.
+	(CPU_VR4120, CPU_VR5400, CPU_VR5500): New.
+	(OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags.
+	Don't match CPU_R4111 with INSN_4100.
+
+2002-08-19  Elena Zannoni <ezannoni@redhat.com>
+
+	From matthew green  <mrg@redhat.com>
+
+	* ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500
+	instructions.
+	(PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR,
+	PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the
+	e500x2 Integer select, branch locking, performance monitor,
+	cache locking and machine check APUs, respectively.
+	(PPC_OPCODE_EFS): New opcode type for efs* instructions.
+	(PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions.
+
+2002-08-13  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* m68hc11.h (M6812_OP_PAGE): Define to identify call operand.
+	(M68HC12_BANK_VIRT, M68HC12_BANK_MASK, M68HC12_BANK_BASE,
+	M68HC12_BANK_SHIFT, M68HC12_BANK_PAGE_MASK): Define for 68HC12
+	memory banks.
+	(M6811_OC1M5, M6811_OC1M4, M6811_MODF): Fix value.
+
+2002-07-09  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* mips.h (INSN_MIPS16): New define.
+
+2002-07-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* i386.h: Remove IgnoreSize from movsx and movzx.
+
+2002-06-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* a29k.h: Replace CONST with const.
+	(CONST): Don't define.
+	* convex.h: Replace CONST with const.
+	(CONST): Don't define.
+	* dlx.h: Replace CONST with const.
+	* or32.h (CONST): Don't define.
+
+2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>
+
+	* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
+	(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
+	(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
+	(INSN_MDMX): New constants, for MDMX support.
+	(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
+
+2002-05-28  Kuang Hwa Lin <kuang@sbcglobal.net>
+
+	* dlx.h: New file.
+
+2002-05-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* ia64.h: Use #include "" instead of <> for local header files.
+	* sparc.h: Likewise.
+
+2002-05-22  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
+2002-05-17  Andrey Volkov  <avolkov@sources.redhat.com>
+
+	* h8300.h: Corrected defs of all control regs
+	and eepmov instr.
+
+2002-04-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* i386.h: Add intel mode cmpsd and movsd.
+	Put them before SSE2 insns, so that rep prefix works.
+
+2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>
+
+	* mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D
+	instructions.
+	(OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks
+	may be passed along with the ISA bitmask.
+
+2002-03-05  Paul Koning  <pkoning@equallogic.com>
+
+	* pdp11.h: Add format codes for float instruction formats.
+
+2002-02-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define.
+
+Mon Feb 18 17:31:48 CET 2002  Jan Hubicka  <jh@suse.cz>
+
+	* i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands.
+
+Mon Feb 11 12:53:19 CET 2002  Jan Hubicka  <jh@suse.cz>
+
+	* i386.h (push,pop): Allow 16bit operands in 64bit mode.
+	(xchg): Fix.
+	(in, out): Disable 64bit operands.
+	(call, jmp): Avoid REX prefixes.
+	(jcxz): Prohibit in 64bit mode
+	(jrcxz, loop): Add 64bit variants.
+	(movq): Fix patterns.
+	(movmskps, pextrw, pinstrw): Add 64bit variants.
+
+2002-01-31  Ivan Guzvinec  <ivang@opencores.org>
+
+	* or32.h: New file.
+
+2002-01-22  Graydon Hoare  <graydon@redhat.com>
+
+	* cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure.
+	(CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field.
+
+2002-01-21  Thomas Klausner <wiz@danbala.ifoer.tuwien.ac.at>
+
+	* h8300.h: Comment typo fix.
+
+2002-01-03  matthew green  <mrg@redhat.com>
+
+	* ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific.
+	(PPC_OPCODE_BOOKE64): Likewise.
+
+Mon Dec 31 16:45:41 2001  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (call, ret): Move to end of table.
+	(addb, addib): PA2.0 variants should have been PA2.0W.
+	(ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler
+	happy.
+	(fldw, fldd, fstw, fstd, bb): Likewise.
+	(short loads/stores): Tweak format specifier slightly to keep
+	disassembler happy.
+	(indexed loads/stores): Likewise.
+	(absolute loads/stores): Likewise.
+
+2001-12-04  Alexandre Oliva  <aoliva@redhat.com>
+
+	* d10v.h (OPERAND_NOSP): New macro.
+
+2001-11-29  Alexandre Oliva  <aoliva@redhat.com>
+
+	* d10v.h (OPERAND_SP): New macro.
+
+2001-11-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (struct powerpc_operand <insert, extract>): Add dialect param.
+
+2001-11-11  Timothy Wall  <twall@alum.mit.edu>
+
+	* tic54x.h: Revise opcode layout; don't really need a separate
+	structure for parallel opcodes.
+
+2001-11-13  Zack Weinberg <zack@codesourcery.com>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to
+	accept WordReg.
+
+2001-11-04  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h (OPCODE_IS_MEMBER): Remove extra space.
+
+2001-10-30  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* mmix.h: New file.
+
+2001-10-18  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end
+	of the expression, to make source code merging easier.
+
+2001-10-17  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h: Sort coprocessor instruction argument characters
+	in comment, add a few more words of description for "H".
+
+2001-10-17  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h (INSN_SB1): New cpu-specific instruction bit.
+	(OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
+	if cpu is CPU_SB1.
+
+2001-10-17  matthew green  <mrg@redhat.com>
+
+	* ppc.h (PPC_OPCODE_BOOKE64): Fix typo.
+
+2001-10-12  matthew green  <mrg@redhat.com>
+
+	* ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New
+	opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403
+	instructions, respectively.
+
+2001-09-27  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* v850.h: Remove spurious comment.
+
+2001-09-21  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* h8300.h: Fix compile time warning messages
+
+2001-09-04  Richard Henderson  <rth@redhat.com>
+
+	* alpha.h (struct alpha_operand): Pack elements into bitfields.
+
+2001-08-31  Eric Christopher  <echristo@redhat.com>
+
+	* mips.h: Remove CPU_MIPS32_4K.
+
+2001-08-27  Torbjorn Granlund  <tege@swox.com>
+
+	* ppc.h (PPC_OPERAND_DS): Define.
+
+2001-08-25  Andreas Jaeger  <aj@suse.de>
+
+	* d30v.h: Fix declaration of reg_name_cnt.
+
+	* d10v.h: Fix declaration of d10v_reg_name_cnt.
+
+	* arc.h: Add prototypes from opcodes/arc-opc.c.
+
+2001-08-16  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* mips.h (INSN_10000): Define.
+	(OPCODE_IS_MEMBER): Check for INSN_10000.
+
+2001-08-10  Alan Modra  <amodra@one.net.au>
+
+	* ppc.h: Revert 2001-08-08.
+
+2001-08-10  Richard Sandiford  <rsandifo@redhat.com>
+
+	* mips.h (INSN_GP32): Remove.
+	(OPCODE_IS_MEMBER): Remove gp32 parameter.
+	(M_MOVE): New macro identifier.
+
+2001-08-08  Alan Modra  <amodra@one.net.au>
+
+	1999-10-25  Torbjorn Granlund  <tege@swox.com>
+	* ppc.h (struct powerpc_operand): New field `reloc'.
+
+2001-08-01  Aldy Hernandez  <aldyh@redhat.com>
+
+	* mips.h (INSN_ISA_MASK): Nuke bits 12-15.
+
+2001-07-12  Jeff Johnston  <jjohnstn@redhat.com>
+
+	* cgen.h (CGEN_INSN): Add regex support.
+	(build_insn_regex): Declare.
+
+2001-07-11  Frank Ch. Eigler  <fche@redhat.com>
+
+	* cgen.h (CGEN_MACH): Add insn_chunk_bitsize field.
+	(cgen_cpu_desc): Ditto.
+
+2001-07-07  Ben Elliston  <bje@redhat.com>
+
+	* m88k.h: Clean up and reformat. Remove unused code.
+
+2001-06-14  Geoffrey Keating  <geoffk@redhat.com>
+
+	* cgen.h (cgen_keyword): Add nonalpha_chars field.
+
+2001-05-23  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* mips.h (CPU_R12000): Define.
+
+2001-05-23  John Healy  <jhealy@redhat.com>
+
+	* cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48.
+
+2001-05-15  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* mips.h (INSN_ISA_MASK): Define.
+
+2001-05-12  Alan Modra  <amodra@one.net.au>
+
+	* i386.h (i386_optab): Second operand of cvtps2dq is an xmm reg,
+	not an mmx reg.  Swap xmm/mmx regs on both movdq2q and movq2dq,
+	and use InvMem as these insns must have register operands.
+
+2001-05-04  Alan Modra  <amodra@one.net.au>
+
+	* i386.h (i386_optab): Move InvMem to first operand of pmovmskb
+	and pextrw to swap reg/rm assignments.
+
+2001-04-05  Hans-Peter Nilsson  <hp@axis.com>
+
+	* cris.h (enum cris_insn_version_usage): Correct comment for
+	cris_ver_v3p.
+
+2001-03-24  Alan Modra  <alan@linuxcare.com.au>
+
+	* i386.h (i386_optab): Correct entry for "movntdq".  Add "punpcklqdq".
+	Add InvMem to first operand of "maskmovdqu".
+
+2001-03-22  Hans-Peter Nilsson  <hp@axis.com>
+
+	* cris.h (ADD_PC_INCR_OPCODE): New macro.
+
+2001-03-21  Kazu Hirata  <kazu@hxi.com>
+
+	* h8300.h: Fix formatting.
+
+2001-03-22  Alan Modra  <alan@linuxcare.com.au>
+
+	* i386.h (i386_optab): Add paddq, psubq.
+
+2001-03-19  Alan Modra  <alan@linuxcare.com.au>
+
+	* i386.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Define.
+
+2001-02-28  Igor Shevlyakov  <igor@windriver.com>
+
+	* m68k.h: new defines for Coldfire V4. Update mcf to know
+	about mcf5407.
+
+2001-02-18  lars brinkhoff  <lars@nocrew.org>
+
+	* pdp11.h: New file.
+
+2001-02-12  Jan Hubicka  <jh@suse.cz>
+
+	* i386.h (i386_optab): SSE integer converison instructions have
+	64bit versions on x86-64.
+
+2001-02-10  Nick Clifton  <nickc@redhat.com>
+
+	* mips.h: Remove extraneous whitespace.  Formating change to allow
+	for future contribution.
+
+2001-02-09  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* s390.h: New file.
+
+2001-02-02  Patrick Macdonald  <patrickm@redhat.com>
+
+	* cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short.
+	(CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES.
+	(CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.
+
+2001-01-24  Karsten Keil  <kkeil@suse.de>
+
+	* i386.h (i386_optab): Fix swapgs
+
+2001-01-14  Alan Modra  <alan@linuxcare.com.au>
+
+	* hppa.h: Describe new '<' and '>' operand types, and tidy
+	existing comments.
+	(pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw.
+	Remove duplicate "ldw j(s,b),x".  Sort some entries.
+
+2001-01-13  Jan Hubicka  <jh@suse.cz>
+
+	* i386.h (i386_optab): Fix pusha and ret templates.
+
+2001-01-11  Peter Targett  <peter.targett@arccores.com>
+
+	* arc.h (ARC_MACH_5, ARC_MACH_6, ARC_MACH_7, ARC_MACH_8): New
+	definitions for masking cpu type.
+	(arc_ext_operand_value) New structure for storing extended
+	operands.
+	(ARC_OPERAND_*) Flags for operand values.
+
+2001-01-10  Jan Hubicka  <jh@suse.cz>
+
+	* i386.h (pinsrw): Add.
+	(pshufw): Remove.
+	(cvttpd2dq): Fix operands.
+	(cvttps2dq): Likewise.
+	(movq2q): Rename to movdq2q.
+
+2001-01-10  Richard Schaal  <richard.schaal@intel.com>
+
+	* i386.h: Correct movnti instruction.
+
+2001-01-09  Jeff Johnston  <jjohnstn@redhat.com>
+
+	* cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number
+	of operands (unsigned char or unsigned short).
+	(CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE.
+	(CGEN_SYNTAX_CHAR): Changed to cast to unsigned char.
+
+2001-01-05  Jan Hubicka  <jh@suse.cz>
+
+	* i386.h (i386_optab): Make [sml]fence template to use immext field.
+
+2001-01-03  Jan Hubicka  <jh@suse.cz>
+
+	* i386.h (i386_optab): Fix 64bit pushf template; Add instructions
+	introduced by Pentium4
+
+2000-12-30  Jan Hubicka  <jh@suse.cz>
+
+	* i386.h (i386_optab): Add "rex*" instructions;
+	add swapgs; disable jmp/call far direct instructions for
+	64bit mode; add syscall and sysret; disable registers for 0xc6
+	template.  Add 'q' suffixes to extendable instructions, disable
+	obsolete instructions, add new sign/zero extension ones.
+	(i386_regtab): Add extended registers.
+	(*Suf): Add No_qSuf.
+	(q_Suf, wlq_Suf, bwlq_Suf): New.
+
+2000-12-20  Jan Hubicka  <jh@suse.cz>
+
+	* i386.h (i386_optab): Replace "Imm" with "EncImm".
+	(i386_regtab): Add flags field.
+
+2000-12-12  Nick Clifton  <nickc@redhat.com>
+
+	* mips.h: Fix formatting.
+
+2000-12-01  Chris Demetriou  <cgd@sibyte.com>
+
+	mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete.
+	(OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old
+	OP_*_SYSCALL definitions.
+	(OP_SH_CODE19, OP_MASK_CODE19): Define, for use as
+	19 bit wait codes.
+	(MIPS operand specifier comments): Remove 'm', add 'U' and
+	'J', and update the meaning of 'B' so that it's more general.
+
+	* mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4,
+	INSN_ISA5): Renumber, redefine to mean the ISA at which the
+	instruction was added.
+	(INSN_ISA32): New constant.
+	(INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32):
+	Renumber to avoid new and/or renumbered INSN_* constants.
+	(INSN_MIPS32): Delete.
+	(ISA_UNKNOWN): New constant to indicate unknown ISA.
+	(ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
+	ISA_MIPS32): New constants, defined to be the mask of INSN_*
+	constants available at that ISA level.
+	(CPU_UNKNOWN): New constant to indicate unknown CPU.
+	(CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
+	define it with a unique value.
+	(OPCODE_IS_MEMBER): Update for new ISA membership-related
+	constant meanings.
+
+	* mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
+	definitions.
+
+	* mips.h (CPU_SB1): New constant.
+
+2000-10-20  Jakub Jelinek  <jakub@redhat.com>
+
+	* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
+	Note that '3' is used for siam operand.
+
+2000-09-22  Jim Wilson  <wilson@cygnus.com>
+
+	* ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
+
+2000-09-13  Anders Norlander  <anorland@acc.umu.se>
+
+	* mips.h: Use defines instead of hard-coded processor numbers.
+	(CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010,
+	CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650,
+	CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K,
+	CPU_4KC, CPU_4KM, CPU_4KP): Define..
+	(OPCODE_IS_MEMBER): Use new defines.
+	(OP_MASK_SEL, OP_SH_SEL): Define.
+	(OP_MASK_CODE20, OP_SH_CODE20): Define.
+	Add 'P' to used characters.
+	Use 'H' for coprocessor select field.
+	Use 'm' for 20 bit breakpoint code.
+	Document new arg characters and add to used characters.
+	(INSN_MIPS32): New define for MIPS32 extensions.
+	(OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
+
+2000-09-05  Alan Modra  <alan@linuxcare.com.au>
+
+	* hppa.h: Mention cz completer.
+
+2000-08-16  Jim Wilson  <wilson@cygnus.com>
+
+	* ia64.h (IA64_OPCODE_POSTINC): New.
+
+2000-08-15  H.J. Lu  <hjl@gnu.org>
+
+	* i386.h: Swap the Intel syntax "movsx"/"movzx" due to the
+	IgnoreSize change.
+
+2000-08-08  Jason Eckhardt  <jle@cygnus.com>
+
+	* i860.h: Small formatting adjustments.
+
+2000-07-29  Marek Michalkiewicz  <marekm@linux.org.pl>
+
+	* avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros.
+	Move related opcodes closer to each other.
+	Minor changes in comments, list undefined opcodes.
+
+2000-07-26  Dave Brolley  <brolley@redhat.com>
+
+	* cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned.
+
+2000-07-22  Jason Eckhardt  <jle@cygnus.com>
+
+	* i860.h (btne, bte, bla): Changed these opcodes
+	to use sbroff ('r') instead of split16 ('s').
+	(J, K, L, M): New operand types for 16-bit aligned fields.
+	(ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
+	use I, J, K, L, M instead of just I.
+	(T, U): New operand types for split 16-bit aligned fields.
+	(st.x): Changed these opcodes to use S, T, U instead of just S.
+	(andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
+	exist on the i860.
+	(pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
+	(pfeq.ss, pfeq.dd): New opcodes.
+	(st.s): Fixed incorrect mask bits.
+	(fmlow): Fixed incorrect mask bits.
+	(fzchkl, pfzchkl): Fixed incorrect mask bits.
+	(faddz, pfaddz): Fixed incorrect mask bits.
+	(form, pform): Fixed incorrect mask bits.
+	(pfld.l): Fixed incorrect mask bits.
+	(fst.q): Fixed incorrect mask bits.
+	(all floating point opcodes): Fixed incorrect mask bits for
+	handling of dual bit.
+
+2000-07-20  Hans-Peter Nilsson  <hp@axis.com>
+
+	cris.h: New file.
+
+2000-06-26  Marek Michalkiewicz  <marekm@linux.org.pl>
+
+	* avr.h (AVR_ISA_WRAP): Remove, now assumed if not AVR_ISA_MEGA.
+	(AVR_ISA_ESPM): Remove, because ESPM removed in databook update.
+	(AVR_ISA_85xx): Remove, all uses changed back to AVR_ISA_2xxx.
+	(AVR_ISA_M83): Define for ATmega83, ATmega85.
+	(espm): Remove, because ESPM removed in databook update.
+	(eicall, eijmp): Move to the end of opcode table.
+
+2000-06-18  Stephane Carrez  <stcarrez@worldnet.fr>
+
+	* m68hc11.h: New file for support of Motorola 68hc11.
+
+Fri Jun  9 21:51:50 2000  Denis Chertykov  <denisc@overta.ru>
+
+	* avr.h: clr,lsl,rol, ... moved after add,adc, ...
+
+Wed Jun  7 21:39:54 2000  Denis Chertykov  <denisc@overta.ru>
+
+	* avr.h: New file with AVR opcodes.
+
+Wed Apr 12 17:11:20 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
+
+	* d10v.h: added ALONE attribute for d10v_opcode.exec_type.
+
+2000-05-23  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+
+	* i386.h: Allow d suffix on iret, and add DefaultSize modifier.
+
+2000-05-17  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+
+	* i386.h: Use sl_FP, not sl_Suf for fild.
+
+2000-05-16  Frank Ch. Eigler  <fche@redhat.com>
+
+	* cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32.  Check that
+	it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set.
+	(CGEN_MAX_IFMT_OPERANDS): Increase to 16.  Check that it exceeds
+	CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set.
+
+2000-05-13  Alan Modra  <alan@linuxcare.com.au>,
+
+	* i386.h (i386_optab): Cpu686 for sysenter,sysexit,fxsave,fxrestore.
+
+2000-05-13  Alan Modra  <alan@linuxcare.com.au>,
+	    Alexander Sokolov <robocop@netlink.ru>
+
+	* i386.h (i386_optab): Add cpu_flags for all instructions.
+
+2000-05-13  Alan Modra  <alan@linuxcare.com.au>
+
+	From Gavin Romig-Koch <gavin@cygnus.com>
+	* i386.h (wld_Suf): Define.  Use on pushf, popf, pusha, popa.
+
+2000-05-04  Timothy Wall  <twall@cygnus.com>
+
+	* tic54x.h: New.
+
+2000-05-03  J.T. Conklin  <jtc@redback.com>
+
+	* ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.
+	(PPC_OPERAND_VR): New operand flag for vector registers.
+
+2000-05-01  Kazu Hirata  <kazu@hxi.com>
+
+	* h8300.h (EOP): Add missing initializer.
+
+Fri Apr 21 15:03:37 2000  Jason Eckhardt  <jle@cygnus.com>
+
+	* hppa.h (pa_opcodes): New opcodes for PA2.0 wide mode
+	forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements).
+	New operand types l,y,&,fe,fE,fx added to support above forms.
+	(pa_opcodes): Replaced usage of 'x' as source/target for
+	floating point double-word loads/stores with 'fx'.
+
+Fri Apr 21 13:20:53 2000  Richard Henderson  <rth@cygnus.com>
+			  David Mosberger  <davidm@hpl.hp.com>
+			  Timothy Wall <twall@cygnus.com>
+			  Jim Wilson  <wilson@cygnus.com>
+
+	* ia64.h: New file.
+
+2000-03-27  Nick Clifton  <nickc@cygnus.com>
+
+	* d30v.h (SHORT_A1): Fix value.
+	(SHORT_AR): Renumber so that it is at the end of the list of short
+	instructions, not the end of the list of long instructions.
+
+2000-03-26  Alan Modra  <alan@linuxcare.com>
+
+	* i386.h: (UNIXWARE_COMPAT): Rename to SYSV386_COMPAT as the
+	problem isn't really specific to Unixware.
+	(OLDGCC_COMPAT): Define.
+	(i386_optab): If !OLDGCC_COMPAT, don't handle fsubp etc. with
+	destination %st(0).
+	Fix lots of comments.
+
+2000-03-02  J"orn Rennecke <amylaar@cygnus.co.uk>
+
+	* d30v.h:
+	(SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated.
+	(SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated.
+	(SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated.
+	(SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated.
+	(SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated.
+	(LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated.
+	(LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated.
+
+2000-02-25  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (fild, fistp): Change intel d_Suf form to fildd and
+	fistpd without suffix.
+
+2000-02-24  Nick Clifton  <nickc@cygnus.com>
+
+	* cgen.h (cgen_cpu_desc): Rename field 'flags' to
+	'signed_overflow_ok_p'.
+	Delete prototypes for cgen_set_flags() and cgen_get_flags().
+
+2000-02-24  Andrew Haley  <aph@cygnus.com>
+
+	* cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
+	(CGEN_CPU_TABLE): flags: new field.
+	Add prototypes for new functions.
+
+2000-02-24  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Add some more UNIXWARE_COMPAT comments.
+
+2000-02-23  Linas Vepstas <linas@linas.org>
+
+	* i370.h: New file.
+
+2000-02-22  Chandra Chavva  <cchavva@cygnus.com>
+
+	* d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation
+	cannot be combined in parallel with ADD/SUBppp.
+
+2000-02-22  Andrew Haley  <aph@cygnus.com>
+
+	* mips.h: (OPCODE_IS_MEMBER): Add comment.
+
+1999-12-30  Andrew Haley  <aph@cygnus.com>
+
+	* mips.h (OPCODE_IS_MEMBER): Add gp32 arg, which determines
+	whether synthetic opcodes (e.g. move) generate 32-bit or 64-bit
+	insns.
+
+2000-01-15  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Qualify intel mode far call and jmp with x_Suf.
+
+1999-12-27  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Add JumpAbsolute qualifier to all non-intel mode
+	indirect jumps and calls.  Add FF/3 call for intel mode.
+
+Wed Dec  1 03:05:25 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h: Add new operand types.  Add new instruction formats.
+
+Wed Nov 24 20:28:58 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb"
+	instruction.
+
+1999-11-18  Gavin Romig-Koch  <gavin@cygnus.com>
+
+	* mips.h (INSN_ISA5): New.
+
+1999-11-01  Gavin Romig-Koch  <gavin@cygnus.com>
+
+	* mips.h (OPCODE_IS_MEMBER): New.
+
+1999-10-29  Nick Clifton  <nickc@cygnus.com>
+
+	* d30v.h (SHORT_AR): Define.
+
+1999-10-18  Michael Meissner  <meissner@cygnus.com>
+
+	* alpha.h (alpha_num_opcodes): Convert to unsigned.
+	(alpha_num_operands): Ditto.
+
+Sun Oct 10 01:46:56 1999  Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org>
+
+	* hppa.h (pa_opcodes): Add load and store cache control to
+	instructions.  Add ordered access load and store.
+
+	* hppa.h (pa_opcode): Add new entries for addb and addib.
+
+	* hppa.h (pa_opcodes): Fix cmpb and cmpib entries.
+
+	* hppa.h (pa_opcodes): Add entries for cmpb and cmpib.
+
+Thu Oct  7 00:12:25 MDT 1999	Diego Novillo <dnovillo@cygnus.com>
+
+	* d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands.
+
+Thu Sep 23 07:08:38 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+
+	* hppa.h (pa_opcodes): Add "call" and "ret".  Clean up "b", "bve"
+	and "be" using completer prefixes.
+
+	* hppa.h (pa_opcodes): Add initializers to silence compiler.
+
+	* hppa.h: Update comments about character usage.
+
+Mon Sep 20 03:55:31 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning
+	up the new fstw & bve instructions.
+
+Sun Sep 19 10:40:59 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store
+	instructions.
+
+	* hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions.
+
+	* hppa.h (pa_opcodes): Add long offset double word load/store
+	instructions.
+
+	* hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and
+	stores.
+
+	* hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns.
+
+	* hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions.
+
+	* hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions.
+
+	* hppa.h (pa_opcodes): Add new syntax "be" instructions.
+
+	* hppa.h (pa_opcodes): Note use of 'M' and 'L'.
+
+	* hppa.h (pa_opcodes): Add support for "b,l".
+
+	* hppa.h (pa_opcodes): Add support for "b,gate".
+
+Sat Sep 18 11:41:16 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pa_opcodes): Use 'fX' for first register operand
+	in xmpyu.
+
+	* hppa.h (pa_opcodes): Fix mask for probe and probei.
+
+	* hppa.h (pa_opcodes): Fix mask for depwi.
+
+Tue Sep  7 13:44:25 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as
+	an explicit output argument.
+
+Mon Sep  6 04:41:42 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores.
+	Add a few PA2.0 loads and store variants.
+
+1999-09-04  Steve Chamberlain  <sac@pobox.com>
+
+	* pj.h: New file.
+
+1999-08-29  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (i386_regtab): Move %st to top of table, and split off
+	other fp reg entries.
+	(i386_float_regtab): To here.
+
+Sat Aug 28 00:25:25 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+
+	* hppa.h (pa_opcodes): Replace 'f' by 'v'.  Prefix float register args
+	by 'f'.
+
+	* hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi.
+	Add supporting args.
+
+	* hppa.h: Document new completers and args.
+	* hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor,
+	uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe.  Add pa2.0
+	extensions for ssm, rsm, pdtlb, pitlb.  Add performance instructions
+	pmenb and pmdis.
+
+	* hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl,
+	hshr, hsub, mixh, mixw, permh.
+
+	* hppa.h (pa_opcodes): Change completers in instructions to
+	use 'c' prefix.
+
+	* hppa.h (pa_opcodes): Add popbts, new forms of bb, havg,
+	hshladd, hshradd, shrpd, and shrpw instructions.  Update arg comments.
+
+	* hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg,
+	fnegabs to use 'I' instead of 'F'.
+
+1999-08-21  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Add AMD athlon instructions, pfnacc, pfpnacc, pswapd.
+	Document pf2iw and pi2fw as athlon insns.  Remove pswapw.
+	Alphabetically sort PIII insns.
+
+Wed Aug 18 18:14:40 1999  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
+
+Fri Aug  6 09:46:35 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+
+	* hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and,
+	and andcm.  Add 32 and 64 bit version of cmpclr, cmpiclr.
+
+	* hppa.h: Document 64 bit condition completers.
+
+Thu Aug  5 16:56:07 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+
+	* hppa.h (pa_opcodes): Change condition args to use '?' prefix.
+
+1999-08-04  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (i386_optab): Add DefaultSize modifier to all insns
+	that implicitly modify %esp.  #undef d_Suf, x_suf, sld_suf,
+	sldx_suf, bwld_Suf, d_FP, x_FP, sld_FP, sldx_FP at end of table.
+
+Wed Jul 28 02:04:24 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+			  Jeff Law <law@cygnus.com>
+
+	* hppa.h (pa_opcodes): Add "pushnom" and "pushbts".
+
+	* hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT.
+
+	* hppa.h (pa_opcodes): Change xmpyu, fmpyfadd,
+	and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'.
+
+1999-07-13  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw insns.
+
+Thu Jul  1 00:17:24 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (struct pa_opcode): Add new field "flags".
+	(FLAGS_STRICT): Define.
+
+Fri Jun 25 04:22:04 1999  Jerry Quinn <jquinn@nortelnetworks.com>
+			  Jeff Law <law@cygnus.com>
+
+	* hppa.h (pa_opcodes): Add pa2.0 clrbts instruction.
+
+	* hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions.
+
+1999-06-23  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Allow `l' suffix on bswap.  Allow `w' suffix on arpl,
+	lldt, lmsw, ltr, str, verr, verw.  Add FP flag to fcmov*.  Add FP
+	flag to fcomi and friends.
+
+Fri May 28 15:26:11 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pa_opcodes): Move integer arithmetic instructions after
+	integer logical instructions.
+
+1999-05-28  Linus Nordberg  <linus.nordberg@canit.se>
+
+	* m68k.h: Document new formats `E', `G', `H' and new places `N',
+	`n', `o'.
+
+	* m68k.h: Define mcf5206e, mcf5307, mcf.  Document new format `u'
+	and new places `m', `M', `h'.
+
+Thu May 27 04:13:54 1999  Joel Sherrill (joel@OARcorp.com
+
+	* hppa.h (pa_opcodes): Add several processor specific system
+	instructions.
+
+Wed May 26 16:57:44 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pa_opcodes): Add second entry for "comb", "comib",
+	"addb", and "addib" to be used by the disassembler.
+
+1999-05-12  Alan Modra  <alan@apri.levels.unisa.edu.au>
+
+	* i386.h (ReverseModrm): Remove all occurences.
+	(InvMem): Add to control/debug/test mov insns, movhlps, movlhps,
+	movmskps, pextrw, pmovmskb, maskmovq.
+	Change NoSuf to FP on all MMX, XMM and AMD insns as these all
+	ignore the data size prefix.
+
+	* i386.h (i386_optab, i386_regtab): Add support for PIII SIMD.
+	Mostly stolen from Doug Ledford <dledford@redhat.com>
+
+Sat May  8 23:27:35 1999  Richard Henderson  <rth@cygnus.com>
+
+	* ppc.h (PPC_OPCODE_64_BRIDGE): New.
+
+1999-04-14  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (CGEN_ATTR): Delete member num_nonbools.
+	(CGEN_ATTR_TYPE): Update.
+	(CGEN_ATTR_MASK): Number booleans starting at 0.
+	(CGEN_ATTR_VALUE): Update.
+	(CGEN_INSN_ATTR): Update.
+
+Mon Apr 12 23:43:27 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (fmpyfadd, fmpynfadd, fneg, fnegabs): New PA2.0
+	instructions.
+
+Tue Mar 23 11:24:38 1999  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (bb, bvb): Tweak opcode/mask.
+
+
+1999-03-22  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (CGEN_ISA,CGEN_MACH): New typedefs.
+	(struct cgen_cpu_desc): Rename member mach to machs.  New member isas.
+	New members word_bitsize,default_insn_bitsize,base_insn-bitsize,
+	min_insn_bitsize,max_insn_bitsize,isa_table,mach_table,rebuild_tables.
+	Delete member max_insn_size.
+	(enum cgen_cpu_open_arg): New enum.
+	(cpu_open): Update prototype.
+	(cpu_open_1): Declare.
+	(cgen_set_cpu): Delete.
+
+1999-03-11  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (CGEN_HW_TABLE): Delete `num_init_entries' member.
+	(CGEN_OPERAND_NIL): New macro.
+	(CGEN_OPERAND): New member `type'.
+	(@arch@_cgen_operand_table): Delete decl.
+	(CGEN_OPERAND_INDEX,CGEN_OPERAND_TYPE,CGEN_OPERAND_ENTRY): Delete.
+	(CGEN_OPERAND_TABLE): New struct.
+	(cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): Declare.
+	(CGEN_OPINST): Pointer to operand table entry replaced with enum.
+	(CGEN_CPU_TABLE): New member `isa'.  Change member `operand_table',
+	now a CGEN_OPERAND_TABLE.  Add CGEN_CPU_DESC arg to
+	{get,set}_{int,vma}_operand.
+	(@arch@_cgen_cpu_open): New arg `isa'.
+	(cgen_set_cpu): Ditto.
+
+Fri Feb 26 02:36:45 1999  Richard Henderson  <rth@cygnus.com>
+
+	* i386.h: Fill in cmov and fcmov alternates.  Add fcomi short forms.
+
+1999-02-25  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (enum cgen_asm_type): Add CGEN_ASM_NONE.
+	(CGEN_HW_ENTRY): Delete member `next'.  Change type of `type' to
+	enum cgen_hw_type.
+	(CGEN_HW_TABLE): New struct.
+	(hw_table): Delete declaration.
+	(CGEN_OPERAND): Change member hw to hw_type, change type from pointer
+	to table entry to enum.
+	(CGEN_OPINST): Ditto.
+	(CGEN_CPU_TABLE): Change member hw_list to hw_table.
+
+Sat Feb 13 14:13:44 1999  Richard Henderson  <rth@cygnus.com>
+
+	* alpha.h (AXP_OPCODE_EV6): New.
+	(AXP_OPCODE_NOPAL): Include it.
+
+1999-02-09  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (CGEN_CPU_DESC): Renamed from CGEN_OPCODE_DESC.
+	All uses updated.  New members int_insn_p, max_insn_size,
+	parse_operand,insert_operand,extract_operand,print_operand,
+	sizeof_fields,set_fields_bitsize,get_int_operand,set_int_operand,
+	get_vma_operand,set_vma_operand,parse_handlers,insert_handlers,
+	extract_handlers,print_handlers.
+	(CGEN_ATTR): Change type of num_nonbools to unsigned int.
+	(CGEN_ATTR_BOOL_OFFSET): New macro.
+	(CGEN_ATTR_MASK): Subtract it to compute bit number.
+	(CGEN_ATTR_VALUE): Redo bool/nonbool attr calculation.
+	(cgen_opcode_handler): Renamed from cgen_base.
+	(CGEN_HW_ATTR_VALUE): Renamed from CGEN_HW_ATTR, all uses updated.
+	(CGEN_OPERAND_ATTR_VALUE): Renamed from CGEN_OPERAND_ATTR,
+	all uses updated.
+	(CGEN_OPERAND_INDEX): Rewrite to use table entry, not global.
+	(enum cgen_opinst_type): Renamed from cgen_operand_instance_type.
+	(CGEN_IFLD_ATTR_VALUE): Renamed from CGEN_IFLD_ATTR, all uses updated.
+	(CGEN_OPCODE,CGEN_IBASE): New types.
+	(CGEN_INSN): Rewrite.
+	(CGEN_{ASM,DIS}_HASH*): Delete.
+	(init_opcode_table,init_ibld_table): Declare.
+	(CGEN_INSN_ATTR): New type.
+
+Mon Feb  1 21:09:14 1999  Catherine Moore  <clm@cygnus.com>
+
+	* i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define.
+	(x_FP, d_FP, dls_FP, sldx_FP): Define.
+	Change *Suf definitions to include x and d suffixes.
+	(movsx): Use w_Suf and b_Suf.
+	(movzx): Likewise.
+	(movs): Use bwld_Suf.
+	(fld): Change ordering.  Use sld_FP.
+	(fild): Add Intel Syntax equivalent of fildq.
+	(fst): Use sld_FP.
+	(fist): Use sld_FP.
+	(fstp): Use sld_FP.  Add x_FP version.
+	(fistp): LLongMem version for Intel Syntax.
+	(fcom, fcomp): Use sld_FP.
+	(fadd, fiadd, fsub): Use sld_FP.
+	(fsubr): Use sld_FP.
+	(fmul, fimul, fdvi, fidiv, fdivr): Use sld_FP.
+
+1999-01-27  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT,
+	CGEN_MODE_UINT.
+
+1999-01-16  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (bv): Fix mask.
+
+1999-01-05  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (CGEN_ATTR_VALUE_TYPE): New typedef.
+	(CGEN_ATTR): Use it.
+	(CGEN_ATTR_TYPE,CGEN_ATTR_ENTRY): Ditto.
+	(CGEN_ATTR_TABLE): New member dfault.
+
+1998-12-30  Gavin Romig-Koch  <gavin@cygnus.com>
+
+	* mips.h (MIPS16_INSN_BRANCH): New.
+
+Wed Dec  9 10:38:48 1998  David Taylor  <taylor@texas.cygnus.com>
+
+	The following is part of a change made by Edith Epstein
+	<eepstein@sophia.cygnus.com> as part of a project to merge in
+	changes by HP; HP did not create ChangeLog entries.
+
+	* hppa.h (completer_chars): list of chars to not put a space
+	after.
+
+Sun Dec  6 13:21:34 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h (i386_optab): Permit w suffix on processor control and
+	status word instructions.
+
+1998-11-30  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (struct cgen_hw_entry): Delete const on attrs member.
+	(struct cgen_keyword_entry): Ditto.
+	(struct cgen_operand): Ditto.
+	(CGEN_IFLD): New typedef, with associated access macros.
+	(CGEN_IFMT): New typedef, with associated access macros.
+	(CGEN_IFMT): Renamed from CGEN_FORMAT.  New member `iflds'.
+	(CGEN_IVALUE): New typedef.
+	(struct cgen_insn): Delete const on syntax,attrs members.
+	`format' now points to format data.  Type of `value' is now
+	CGEN_IVALUE.
+	(struct cgen_opcode_table): New member ifld_table.
+
+1998-11-18  Doug Evans  <devans@casey.cygnus.com>
+
+	* cgen.h (cgen_extract_fn): Update type of `base_insn' arg.
+	(CGEN_OPERAND_INSTANCE): New member `attrs'.
+	(CGEN_OPERAND_INSTANCE_{ATTRS,ATTR}): New macros.
+	(cgen_dis_lookup_insn): Update type of `base_insn' arg.
+	(cgen_opcode_table): Update type of dis_hash fn.
+	(extract_operand): Update type of `insn_value' arg.
+
+Thu Oct 29 11:38:36 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Delete.
+
+Tue Oct 27 08:57:59 1998  Gavin Romig-Koch  <gavin@cygnus.com>
+
+	* mips.h (INSN_MULT): Added.
+
+Tue Oct 20 11:31:34 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (MAX_MNEM_SIZE): Rename from MAX_OPCODE_SIZE.
+
+Mon Oct 19 12:50:00 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_INSN_INT): New typedef.
+	(CGEN_INT_INSN_P): Renamed from CGEN_INT_INSN.
+	(CGEN_INSN_BYTES): Renamed from cgen_insn_t.
+	(CGEN_INSN_BYTES_PTR): New typedef.
+	(CGEN_EXTRACT_INFO): New typedef.
+	(cgen_insert_fn,cgen_extract_fn): Update.
+	(cgen_opcode_table): New member `insn_endian'.
+	(assemble_insn,lookup_insn,lookup_get_insn_operands): Update.
+	(insert_operand,extract_operand): Update.
+	(cgen_get_insn_value,cgen_put_insn_value): Add prototypes.
+
+Fri Oct  9 13:38:13 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_ATTR_BOOLS): New macro.
+	(struct CGEN_HW_ENTRY): New member `attrs'.
+	(CGEN_HW_ATTR): New macro.
+	(struct CGEN_OPERAND_INSTANCE): New member `name'.
+	(CGEN_INSN_INVALID_P): New macro.
+
+Mon Oct  5 00:21:07 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h: Add "fid".
+
+Sun Oct  4 21:00:00 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	From Robert Andrew Dale <rob@nb.net>
+	* i386.h (i386_optab): Add AMD 3DNow! instructions.
+	(AMD_3DNOW_OPCODE): Define.
+
+Tue Sep 22 17:53:47 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* d30v.h (EITHER_BUT_PREFER_MU): Define.
+
+Mon Aug 10 14:09:38 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cgen.h (cgen_insn): #if 0 out element `cdx'.
+
+Mon Aug  3 12:21:57 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	Move all global state data into opcode table struct, and treat
+	opcode table as something that is "opened/closed".
+	* cgen.h (CGEN_OPCODE_DESC): New type.
+	(all fns): New first arg of opcode table descriptor.
+	(cgen_set_parse_operand_fn): Add prototype.
+	(cgen_current_machine,cgen_current_endian): Delete.
+	(CGEN_OPCODE_TABLE): New members mach,endian,operand_table,
+	parse_operand_fn,asm_hash_table,asm_hash_table_entries,
+	dis_hash_table,dis_hash_table_entries.
+	(opcode_open,opcode_close): Add prototypes.
+
+	* cgen.h (cgen_insn): New element `cdx'.
+
+Thu Jul 30 21:44:25 1998  Frank Ch. Eigler  <fche@cygnus.com>
+
+	* d30v.h (FLAG_LKR): New flag for "left-kills-right" instructions.
+
+Tue Jul 28 10:59:07 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h: Add "no_match_operands" field for instructions.
+	(MN10300_MAX_OPERANDS): Define.
+
+Fri Jul 24 11:44:24 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cgen.h (cgen_macro_insn_count): Declare.
+
+Tue Jul 21 13:12:13 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Define.
+	(cgen_insert_fn,cgen_extract_fn): New arg `pc'.
+	(get_operand,put_operand): Replaced with get_{int,vma}_operand,
+	set_{int,vma}_operand.
+
+Fri Jun 26 11:09:06 1998  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h: Add "machine" field for instructions.
+	(MN103, AM30): Define machine types.
+
+Fri Jun 19 16:09:09 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Use FP, not sl_Suf, for fxsave and fxrstor.
+
+1998-06-18  Ulrich Drepper  <drepper@cygnus.com>
+
+	* i386.h: Add support for fxsave, fxrstor, sysenter and sysexit.
+
+Sat Jun 13 11:31:35 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (i386_optab): Add general form of aad and aam.  Add ud2a
+	and ud2b.
+	(i386_regtab): Allow cr0..7, db0..7, dr0..7, tr0..7, not just
+	those that happen to be implemented on pentiums.
+
+Tue Jun  9 12:16:01 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Change occurences of Data16 to Size16, Data32 to Size32,
+	IgnoreDataSize to IgnoreSize.  Flag address and data size prefixes
+	with Size16|IgnoreSize or Size32|IgnoreSize.
+
+Mon Jun  8 12:15:52 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (REPNE): Rename to REPNE_PREFIX_OPCODE.
+	(REPE): Rename to REPE_PREFIX_OPCODE.
+	(i386_regtab_end): Remove.
+	(i386_prefixtab, i386_prefixtab_end): Remove.
+	(i386_optab): Use NULL as sentinel rather than "" to suit rewrite
+	of md_begin.
+	(MAX_OPCODE_SIZE): Define.
+	(i386_optab_end): Remove.
+	(sl_Suf): Define.
+	(sl_FP): Use sl_Suf.
+
+	* i386.h (i386_optab): Allow 16 bit displacement for `mov
+	mem,acc'.  Combine 16 and 32 bit forms of various insns.  Allow 16
+	bit form of ljmp.  Add IsPrefix modifier to prefixes.  Add addr32,
+	data32, dword, and adword prefixes.
+	(i386_regtab): Add BaseIndex modifier to valid 16 bit base/index
+	regs.
+
+Fri Jun  5 23:42:43 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (i386_regtab): Remove BaseIndex modifier from esp.
+
+	* i386.h: Allow `l' suffix on fld, fst, fstp, fcom, fcomp with
+	register operands, because this is a common idiom.  Flag them with
+	a warning.  Allow illegal faddp, fsubp, fsubrp, fmulp, fdivp,
+	fdivrp because gcc erroneously generates them.  Also flag with a
+	warning.
+
+	* i386.h: Add suffix modifiers to most insns, and tighter operand
+	checks in some cases.  Fix a number of UnixWare compatibility
+	issues with float insns.  Merge some floating point opcodes, using
+	new FloatMF modifier.
+	(WORD_PREFIX_OPCODE): Rename to DATA_PREFIX_OPCODE for
+	consistency.
+
+	* i386.h: Change occurence of ShortformW to W|ShortForm.  Add
+	IgnoreDataSize where appropriate.
+
+Wed Jun  3 18:28:45 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: (one_byte_segment_defaults): Remove.
+	(two_byte_segment_defaults): Remove.
+	(i386_regtab): Add BaseIndex to 32 bit regs reg_type.
+
+Fri May 15 15:59:04 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup.
+	(cgen_hw_lookup_by_num): Declare.
+
+Thu May  7 09:27:58 1998  Frank Ch. Eigler  <fche@cygnus.com>
+
+	* mips.h (OP_{SH,MASK}_CODE2): Added "q" operand format for lower
+	ten bits of MIPS ISA1 "break" instruction, and for "sdbbp"
+
+Thu May  7 02:14:08 1998  Doug Evans  <devans@charmed.cygnus.com>
+
+	* cgen.h (cgen_asm_init_parse): Delete.
+	(cgen_save_fixups,cgen_restore_fixups,cgen_swap_fixups): Delete.
+	(cgen_asm_record_register,cgen_asm_finish_insn): Delete.
+
+Mon Apr 27 10:13:11 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_ATTR_TYPE): Delete `const', moved to uses.
+	(cgen_asm_finish_insn): Update prototype.
+	(cgen_insn): New members num, data.
+	(CGEN_INSN_TABLE): Members asm_hash, asm_hash_table_size,
+	dis_hash, dis_hash_table_size moved to ...
+	(CGEN_OPCODE_TABLE).  Here.  Renamed from CGEN_OPCODE_DATA.
+	All uses updated.  New members asm_hash_p, dis_hash_p.
+	(CGEN_MINSN_EXPANSION): New struct.
+	(cgen_expand_macro_insn): Declare.
+	(cgen_macro_insn_count): Declare.
+	(get_insn_operands): Update prototype.
+	(lookup_get_insn_operands): Declare.
+
+Tue Apr 21 17:11:32 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (i386_optab): Change iclrKludge and imulKludge to
+	regKludge.  Add operands types for string instructions.
+
+Mon Apr 20 14:40:29 1998  Tom Tromey  <tromey@cygnus.com>
+
+	* i386.h (X): Renamed from `Z_' to preserve formatting of opcode
+	table.
+
+Sun Apr 19 13:54:06 1998  Tom Tromey  <tromey@cygnus.com>
+
+	* i386.h (Z_): Renamed from `_' to avoid clash with common alias
+	for `gettext'.
+
+Fri Apr  3 12:04:48 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h: Remove NoModrm flag from all insns: it's never checked.
+	Add IsString flag to string instructions.
+	(IS_STRING): Don't define.
+	(LOCK_PREFIX_OPCODE, CS_PREFIX_OPCODE, DS_PREFIX_OPCODE): Define.
+	(ES_PREFIX_OPCODE, FS_PREFIX_OPCODE, GS_PREFIX_OPCODE): Define.
+	(SS_PREFIX_OPCODE): Define.
+
+Mon Mar 30 21:31:56 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Revert March 24 patch; no more LinearAddress.
+
+Mon Mar 30 10:25:54 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (i386_optab): Remove fwait (9b) from all floating point
+	instructions, and instead add FWait opcode modifier.  Add short
+	form of fldenv and fstenv.
+	(FWAIT_OPCODE): Define.
+
+	* i386.h (i386_optab): Change second operand constraint of `mov
+	sreg,reg|mem' instruction from Reg16|Mem to WordReg|WordMem to
+	allow legal instructions such as `movl %gs,%esi'
+
+Fri Mar 27 18:30:52 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* h8300.h: Various changes to fully bracket initializers.
+
+Tue Mar 24 18:32:47 1998  H.J. Lu  <hjl@gnu.org>
+
+	* i386.h: Set LinearAddress for lidt and lgdt.
+
+Mon Mar  2 10:44:07 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_BOOL_ATTR): New macro.
+
+Thu Feb 26 15:54:31 1998  Michael Meissner  <meissner@cygnus.com>
+
+	* d30v.h (FLAG_DELAY): New flag for delayed branches/jumps.
+
+Mon Feb 23 10:38:21 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_CAT3): Delete.  Use CONCAT3 now.
+	(cgen_insn): Record syntax and format entries here, rather than
+	separately.
+
+Tue Feb 17 21:42:56 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* cgen.h (CGEN_SYNTAX_MAKE_FIELD): New macro.
+
+Tue Feb 17 16:00:56 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (cgen_insert_fn): Change type of result to const char *.
+	(cgen_parse_{signed,unsigned}_integer): Delete min,max arguments.
+	(CGEN_{INSN,KEYWORD,OPERAND}_NBOOL_ATTRS): Renamed from ..._MAX_ATTRS.
+
+Thu Feb 12 18:30:41 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cgen.h (lookup_insn): New argument alias_p.
+
+Thu Feb 12 03:41:00 1998  J"orn Rennecke  <amylaar@cygnus.co.uk>
+
+Fix rac to accept only a0:
+	* d10v.h (OPERAND_ACC): Split into:
+	(OPERAND_ACC0, OPERAND_ACC1) .
+	(OPERAND_GPR): Define.
+
+Wed Feb 11 17:31:53 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_FIELDS): Define here.
+	(CGEN_HW_ENTRY): New member `type'.
+	(hw_list): Delete decl.
+	(enum cgen_mode): Declare.
+	(CGEN_OPERAND): New member `hw'.
+	(enum cgen_operand_instance_type): Declare.
+	(CGEN_OPERAND_INSTANCE): New type.
+	(CGEN_INSN): New member `operands'.
+	(CGEN_OPCODE_DATA): Make hw_list const.
+	(get_insn_operands,lookup_insn): Add prototypes for.
+
+Tue Feb  3 17:11:23 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_INSN_MAX_ATTRS): Renamed from CGEN_MAX_INSN_ATTRS.
+	(CGEN_HW_ENTRY): Move `next' entry to end of struct.
+	(CGEN_KEYWORD_MAX_ATTRS): Renamed from CGEN_MAX_KEYWORD_ATTRS.
+	(CGEN_OPERAND_MAX_ATTRS): Renamed from CGEN_MAX_OPERAND_ATTRS.
+
+Mon Feb  2 19:19:15 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* cgen.h: Correct typo in comment end marker.
+
+Mon Feb  2 17:10:38 1998  Steve Haworth  <steve@pm.cse.rmit.EDU.AU>
+
+	* tic30.h: New file.
+
+Thu Jan 22 17:54:56 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* cgen.h: Add prototypes for cgen_save_fixups(),
+	cgen_restore_fixups(), and cgen_swap_fixups().  Change prototype
+	of cgen_asm_finish_insn() to return a char *.
+
+Wed Jan 14 17:21:43 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* cgen.h: Formatting changes to improve readability.
+
+Mon Jan 12 11:37:36 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (*): Clean up pass over `struct foo' usage.
+	(CGEN_ATTR): Make unsigned char.
+	(CGEN_ATTR_TYPE): Update.
+	(CGEN_ATTR_{ENTRY,TABLE}): New types.
+	(cgen_base): Move member `attrs' to cgen_insn.
+	(CGEN_KEYWORD): New member `null_entry'.
+	(CGEN_{SYNTAX,FORMAT}): New types.
+	(cgen_insn): Format and syntax separated from each other.
+
+Tue Dec 16 15:15:52 1997  Michael Meissner  <meissner@cygnus.com>
+
+	* d30v.h (d30v_opcode): Reorder flags somewhat, add new flags for
+	2 word load/store, ADDppp/SUBppp, 16/32 bit multiply.  Make
+	flags_{used,set} long.
+	(d30v_operand): Make flags field long.
+
+Mon Dec  1 12:24:44 1997  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
+
+	* m68k.h: Fix comment describing operand types.
+
+Sun Nov 23 22:31:27 1997  Michael Meissner  <meissner@cygnus.com>
+
+	* d30v.h (SHORT_CMPU): Add case for cmpu instruction, and move
+	everything else after down.
+
+Tue Nov 18 18:45:14 1997  J"orn Rennecke  <amylaar@cygnus.co.uk>
+
+	* d10v.h (OPERAND_FLAG): Split into:
+	(OPERAND_FFLAG, OPERAND_CFLAG) .
+
+Thu Nov 13 11:04:24 1997  Gavin Koch  <gavin@cygnus.com>
+
+	* mips.h (struct mips_opcode): Changed comments to reflect new
+	field usage.
+
+Fri Oct 24 22:36:20 1997  Ken Raeburn  <raeburn@cygnus.com>
+
+	* mips.h: Added to comments a quick-ref list of all assigned
+	operand type characters.
+	(OP_{MASK,SH}_PERFREG): New macros.
+
+Wed Oct 22 17:28:33 1997  Richard Henderson  <rth@cygnus.com>
+
+	* sparc.h: Add '_' and '/' for v9a asr's.
+	Patch from David Miller <davem@vger.rutgers.edu>
+
+Tue Oct 14 13:22:29 1997  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h: Bit ops with absolute addresses not in the 8 bit
+	area are not available in the base model (H8/300).
+
+Thu Sep 25 13:03:41 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* m68k.h: Remove documentation of ` operand specifier.
+
+Wed Sep 24 19:00:34 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* m68k.h: Document q and v operand specifiers.
+
+Mon Sep 15 18:28:37 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (struct v850_opcode): Add processors field.
+	(PROCESSOR_V850, PROCESSOR_ALL): New bit constants.
+	(PROCESSOR_V850E, PROCESSOR_NOT_V850): New bit constants.
+	(PROCESSOR_V850EA): New bit constants.
+
+Mon Sep 15 11:29:43 1997  Ken Raeburn  <raeburn@cygnus.com>
+
+	Merge changes from Martin Hunt:
+
+	* d30v.h: Allow up to 64 control registers. Add
+	SHORT_A5S format.
+
+	* d30v.h (LONG_Db): New form for delayed branches.
+
+	* d30v.h: (LONG_Db): New form for repeati.
+
+	* d30v.h (SHORT_D2B): New form.
+
+	* d30v.h (SHORT_A2): New form.
+
+	* d30v.h (OPERAND_2REG): Add new operand to indicate 2
+	registers are used.  Needed for VLIW optimization.
+
+Mon Sep  8 14:05:45 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* cgen.h: Move assembler interface section
+	up so cgen_parse_operand_result is defined for cgen_parse_address.
+	(cgen_parse_address): Update prototype.
+
+Tue Sep  2 15:32:32 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed.
+
+Tue Aug 26 12:21:52 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h (two_byte_segment_defaults): Correct base register 5 in
+	modes 1 and 2 to be ss rather than ds.  From Gabriel Paubert
+	<paubert@iram.es>.
+
+	* i386.h: Set ud2 to 0x0f0b.  From Gabriel Paubert
+	<paubert@iram.es>.
+
+	* i386.h: Comment fixes for ficom[p]?{s,l} from Gabriel Paubert
+	<paubert@iram.es>.
+
+	* i386.h (JUMP_ON_CX_ZERO): Uncomment (define again).
+	(JUMP_ON_ECX_ZERO): Remove commented out macro.
+
+Fri Aug 22 10:38:29 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (V850_NOT_R0): New flag.
+
+Mon Aug 18 11:05:58 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (struct v850_opcode): Remove flags field.
+
+Wed Aug 13 18:45:48 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (struct v850_opcode): Add flags field.
+	(struct v850_operand): Extend meaning of 'bits' and 'shift'
+	fields.
+	(V850E_INSTRUCTION, V850EA_INSTRUCTION): New flags.
+	(V850E_PUSH_POP, V850E_IMMEDIATE16, V850E_IMMEDIATE32): New flags.
+
+Fri Aug  8 16:58:42 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* arc.h: New file.
+
+Thu Jul 24 21:16:58 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* sparc.h (sparc_opcodes): Declare as const.
+
+Thu Jul 10 12:53:25 1997  Jeffrey A Law  (law@cygnus.com)
+
+	* mips.h (FP_S, FP_D): Define.  Bitmasks indicating if an insn
+	uses single or double precision floating point resources.
+	(INSN_NO_ISA, INSN_ISA1): Define.
+	(cpu specific INSN macros): Tweak into bitmasks outside the range
+	of INSN_ISA field.
+
+Mon Jun 16 14:10:00 1997  H.J. Lu  <hjl@gnu.ai.mit.edu>
+
+	* i386.h: Fix pand opcode.
+
+Mon Jun  2 11:35:09 1997  Gavin Koch  <gavin@cygnus.com>
+
+	* mips.h: Widen INSN_ISA and move it to a more convenient
+	bit position.  Add INSN_3900.
+
+Tue May 20 11:25:29 1997  Gavin Koch  <gavin@cygnus.com>
+
+	* mips.h (struct mips_opcode): added new field membership.
+
+Mon May 12 16:26:50 1997  H.J. Lu  <hjl@gnu.ai.mit.edu>
+
+	* i386.h (movd): only Reg32 is allowed.
+
+	* i386.h: add fcomp and ud2.  From Wayne Scott
+	<wscott@ichips.intel.com>.
+
+Mon May  5 17:16:21 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Add MMX instructions.
+
+Mon May  5 12:45:19 1997  H.J. Lu  <hjl@gnu.ai.mit.edu>
+
+	* i386.h: Remove W modifier from conditional move instructions.
+
+Mon Apr 14 14:56:58 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Change the opcodes for fsubp, fsubrp, fdivp, and fdivrp
+	with no arguments to match that generated by the UnixWare
+	assembler.
+
+Thu Apr 10 14:35:00 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* cgen.h (<cpu>_cgen_assemble_insn): New arg for errmsg.
+	(cgen_parse_operand_fn): Declare.
+	(cgen_init_parse_operand): Declare.
+	(cgen_parse_operand): Renamed from cgen_asm_parse_operand,
+	new argument `want'.
+	(enum cgen_parse_operand_result): Renamed from cgen_asm_result.
+	(enum cgen_parse_operand_type): New enum.
+
+Sat Apr  5 13:14:05 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Revert last patch for the NON_BROKEN_OPCODES cases.
+
+Fri Apr  4 11:46:11 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* cgen.h: New file.
+
+Fri Apr  4 14:02:32 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Correct opcode values for fsubp, fsubrp, fdivp, and
+	fdivrp.
+
+Tue Mar 25 22:57:26 1997  Stu Grossman  (grossman@critters.cygnus.com)
+
+	* v850.h (extract): Make unsigned.
+
+Mon Mar 24 14:38:15 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Add iclr.
+
+Thu Mar 20 19:49:10 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Change DW to W for cmpxchg and xadd, since they don't
+	take a direction bit.
+
+Sat Mar 15 19:03:29 1997  H.J. Lu  <hjl@lucon.org>
+
+	* sparc.h (sparc_opcode_lookup_arch): Use full prototype.
+
+Fri Mar 14 15:22:01 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* sparc.h: Include <ansidecl.h>.  Update function declarations to
+	use prototypes, and to use const when appropriate.
+
+Thu Mar  6 14:18:30 1997  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_RELAX): Define.
+
+Mon Feb 24 15:15:56 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h: Change pre_defined_registers to
+	d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
+
+Sat Feb 22 21:25:00 1997  Dawn Perchik  <dawn@cygnus.com>
+
+	* mips.h: Add macros for cop0, cop1 cop2 and cop3.
+	Change mips_opcodes from const array to a pointer,
+	and change bfd_mips_num_opcodes from const int to int,
+	so that we can increase the size of the mips opcodes table
+	dynamically.
+
+Fri Feb 21 16:34:18 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d30v.h (FLAG_X): Remove unused flag.
+
+Tue Feb 18 17:37:20 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d30v.h: New file.
+
+Fri Feb 14 13:16:15 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (PDS_NAME): Macro to access name field of predefined symbols.
+	(PDS_VALUE): Macro to access value field of predefined symbols.
+	(tic80_next_predefined_symbol): Add prototype.
+
+Mon Feb 10 10:32:17 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (tic80_symbol_to_value): Change prototype to match
+	change in function, added class parameter.
+
+Thu Feb  6 17:30:15 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_OPERAND_ENDMASK): Add for flagging TIc80
+	endmask fields, which are somewhat weird in that 0 and 32 are
+	treated exactly the same.
+
+Thu Jan 30 13:46:18 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h: Change all the OPERAND defines to use the form (1 << X)
+	rather than a constant that is 2**X.  Reorder them to put bits for
+	operands that have symbolic names in the upper bits, so they can
+	be packed into an int where the lower bits contain the value that
+	corresponds to that symbolic name.
+	(predefined_symbo): Add struct.
+	(tic80_predefined_symbols): Declare array of translations.
+	(tic80_num_predefined_symbols): Declare size of that array.
+	(tic80_value_to_symbol): Declare function.
+	(tic80_symbol_to_value): Declare function.
+
+Wed Jan 29 09:37:25 1997  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10200.h (MN10200_OPERAND_RELAX): Define.
+
+Sat Jan 18 15:18:59 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_NO_R0_DEST): Add for opcodes where r0 cannot
+	be the destination register.
+
+Thu Jan 16 20:48:55 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (struct tic80_opcode): Change "format" field to "flags".
+	(FMT_UNUSED, FMT_SI, FMT_LI, FMT_REG): Delete.
+	(TIC80_VECTOR): Define a flag bit for the flags.  This one means
+	that the opcode can have two vector instructions in a single
+	32 bit word and we have to encode/decode both.
+
+Tue Jan 14 19:37:09 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_OPERAND_PCREL): Renamed from
+	TIC80_OPERAND_RELATIVE for PC relative.
+	(TIC80_OPERAND_BASEREL): New flag bit for register
+	base relative.
+
+Mon Jan 13 15:56:38 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_OPERAND_FLOAT): Add for floating point operands.
+
+Mon Jan  6 10:51:15 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_OPERAND_SCALED): Operand may have optional
+	":s" modifier for scaling.
+
+Sun Jan  5 12:12:19 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_OPERAND_M_SI): Add operand modifier for ":m".
+	(TIC80_OPERAND_M_LI): Ditto
+
+Sat Jan  4 19:02:44 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_OPERAND_BITNUM): Renamed from TIC80_OPERAND_CC_SZ.
+	(TIC80_OPERAND_CC): New define for condition code operand.
+	(TIC80_OPERAND_CR): New define for control register operand.
+
+Fri Jan  3 16:22:23 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (struct tic80_opcode): Name changed.
+	(struct tic80_opcode): Remove format field.
+	(struct tic80_operand): Add insertion and extraction functions.
+	(TIC80_OPERAND_*): Remove old bogus values, start adding new
+	correct ones.
+	(FMT_*): Ditto.
+
+Tue Dec 31 15:05:41 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* v850.h (V850_OPERAND_ADJUST_SHORT_MEMORY): New flag to adjust
+	type IV instruction offsets.
+
+Fri Dec 27 22:23:10 1996  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h: New file.
+
+Wed Dec 18 10:06:31 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10200.h (MN10200_OPERAND_NOCHECK): Define.
+
+Sat Dec 14 10:48:31 1996  Fred Fish  <fnf@ninemoons.com>
+
+	* mn10200.h: Fix comment, mn10200_operand not powerpc_operand.
+	* mn10300.h: Fix comment, mn10300_operand not powerpc_operand.
+	* v850.h: Fix comment, v850_operand not powerpc_operand.
+
+Mon Dec  9 16:45:39 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10200.h: Flesh out structures and definitions needed by
+	the mn10200 assembler & disassembler.
+
+Tue Nov 26 10:46:56 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h: Add mips16 definitions.
+
+Mon Nov 25 17:56:54 1996  J.T. Conklin  <jtc@cygnus.com>
+
+	* m68k.h: Document new <, >, m, n, o and p operand specifiers.
+
+Wed Nov 20 10:59:41 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_PCREL): Define.
+	(MN10300_OPERAND_MEMADDR): Define.
+
+Tue Nov 19 13:30:40 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_REG_LIST): Define.
+
+Wed Nov  6 13:41:08 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_SPLIT): Define.
+
+Tue Nov  5 13:26:12 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_EXTENDED): Define.
+
+Mon Nov  4 12:52:48 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_REPEATED): Define.
+
+Fri Nov  1 10:31:02 1996  Richard Henderson  <rth@tamu.edu>
+
+	* alpha.h: Don't include "bfd.h"; private relocation types are now
+	negative to minimize problems with shared libraries.  Organize
+	instruction subsets by AMASK extensions and PALcode
+	implementation.
+	(struct alpha_operand): Move flags slot for better packing.
+
+Tue Oct 29 12:19:10 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* v850.h (V850_OPERAND_RELAX): New operand flag.
+
+Thu Oct 10 14:29:11 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (FMT_*): Move operand format definitions
+	here.
+
+Tue Oct  8 14:48:07 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (MN10300_OPERAND_PAREN): Define.
+
+Mon Oct  7 16:52:11 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10300.h (mn10300_opcode): Add "format" field.
+	(MN10300_OPERAND_*): Define.
+
+Thu Oct  3 10:33:46 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10x00.h: Delete.
+	* mn10200.h, mn10300.h: New files.
+
+Wed Oct  2 21:31:26 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* mn10x00.h: New file.
+
+Fri Sep 27 18:26:46 1996  Stu Grossman  (grossman@critters.cygnus.com)
+
+	* v850.h: Add new flag to indicate this instruction uses a PC
+	displacement.
+
+Fri Sep 13 14:58:13 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h (stmac): Add missing instruction.
+
+Sat Aug 31 16:02:03 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* v850.h (v850_opcode): Remove "size" field.  Add "memop"
+	field.
+
+Fri Aug 23 10:39:08 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* v850.h (V850_OPERAND_EP): Define.
+
+	* v850.h (v850_opcode): Add size field.
+
+Thu Aug 22 16:51:25 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
+
+	* v850.h (v850_operands): Add insert and extract fields, pointers
+	to functions used to handle unusual operand encoding.
+	(V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC,
+	V850_OPERAND_SIGNED): Defined.
+
+Wed Aug 21 17:45:10 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
+
+	* v850.h (v850_operands): Add flags field.
+	(OPERAND_REG, OPERAND_NUM): Defined.
+
+Tue Aug 20 14:52:02 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
+
+	* v850.h: New file.
+
+Fri Aug 16 14:44:15 1996  James G. Smith  <jsmith@cygnus.co.uk>
+
+	* mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM,
+	OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC,
+	OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT,
+	OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE,
+	OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT):
+	Defined.
+
+Fri Aug 16 00:15:15 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h (pitlb, pitlbe, iitlba, iitlbp, fic, fice): Accept
+	a 3 bit space id instead of a 2 bit space id.
+
+Thu Aug 15 13:11:46 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h: Add some additional defines to support the
+	assembler in determining which operations can be done in parallel.
+
+Tue Aug  6 11:13:22 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h (SN): Define.
+	(eepmov.b): Renamed from "eepmov"
+	(nop, bpt, rte, rts, sleep, clrmac): These have no size associated
+	with them.
+
+Fri Jul 26 11:47:10 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h (OPERAND_SHIFT): New operand flag.
+
+Thu Jul 25 12:06:22 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h: Changes for divs, parallel-only instructions, and
+	signed numbers.
+
+Mon Jul 22 11:21:15 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h (pd_reg): Define. Putting the definition here allows
+	the assembler and disassembler to share the same struct.
+
+Mon Jul 22 12:15:25 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i960.h (i960_opcodes): "halt" takes an argument.  From Stephen
+	Williams <steve@icarus.com>.
+
+Wed Jul 17 14:46:38 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+	* d10v.h: New file.
+
+Thu Jul 11 12:09:15 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h (band, bclr): Force high bit of immediate nibble to zero.
+
+Wed Jul  3 14:30:12 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
+
+	* m68k.h (mcf5200): New macro.
+	Document names of coldfire control registers.
+
+Tue Jul  2 23:05:45 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h (SRC_IN_DST): Define.
+
+	* h8300.h (UNOP3): Mark the register operand in this insn
+	as a source operand, not a destination operand.
+	(SHIFT_2, SHIFT_IMM): Remove.  Eliminate all references.
+	(UNOP3): Change SHIFT_IMM to IMM for H8/S bitops.  Mark
+	register operand with SRC_IN_DST.
+
+Fri Jun 21 13:52:17 1996  Richard Henderson  <rth@tamu.edu>
+
+	* alpha.h: New file.
+
+Thu Jun 20 15:02:57 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* rs6k.h: Remove obsolete file.
+
+Wed Jun 19 15:29:38 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Correct opcode values for faddp, fsubp, fsubrp, fmulp,
+	fdivp, and fdivrp.  Add ffreep.
+
+Tue Jun 18 16:06:00 1996  Jeffrey A. Law  <law@rtl.cygnus.com>
+
+	* h8300.h: Reorder various #defines for readability.
+	(ABS32SRC, ABS32DST, DSP32LIST, ABS32LIST, A32LIST): Define.
+	(BITOP): Accept additional (unused) argument.  All callers changed.
+	(EBITOP): Likewise.
+	(O_LAST): Bump.
+	(ldc, stc, movb, movw, movl): Use 32bit offsets and absolutes.
+
+	* h8300.h (EXR, SHIFT_2, MACREG, SHIFT_IMM, RDINC): Define.
+	(O_TAS, O_CLRMAC, O_LDMAC, O_MAC, O_LDM, O_STM): Define.
+	(BITOP, EBITOP): Handle new H8/S addressing modes for
+	bit insns.
+	(UNOP3): Handle new shift/rotate insns on the H8/S.
+	(insns using exr): New instructions.
+	(tas, mac, ldmac, clrmac, ldm, stm): New instructions.
+
+Thu May 23 16:56:48 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h (add.l): Undo Apr 5th change.  The manual I had
+	was incorrect.
+
+Mon May  6 23:38:22 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h (START): Remove.
+	(MEMRELAX): Define.  Mark absolute memory operands in mov.b, mov.w
+	and mov.l insns that can be relaxed.
+
+Tue Apr 30 18:30:58 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Remove Abs32 from lcall.
+
+Mon Apr 22 17:09:23 1996  Doug Evans  <dje@blues.cygnus.com>
+
+	* sparc.h (SPARC_OPCODE_ARCH_V9_P): New macro.
+	(SLCPOP): New macro.
+	Mark X,Y opcode letters as in use.
+
+Thu Apr 11 17:28:18 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* sparc.h (F_FLOAT, F_FBR): Define.
+
+Fri Apr  5 16:55:34 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h (ABS8MEM): Renamed from ABSMOV.  Remove ABSMOV
+	from all insns.
+	(ABS8SRC,ABS8DST): Add ABS8MEM.
+	(add.l): Fix reg+reg variant.
+	(eepmov.w): Renamed from eepmovw.
+	(ldc,stc): Fix many cases.
+
+Sun Mar 31 13:30:03 1996  Doug Evans  <dje@canuck.cygnus.com>
+
+	* sparc.h (SPARC_OPCODE_ARCH_MASK): New macro.
+
+Thu Mar  7 15:08:23 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+	* sparc.h (O): Mark operand letter as in use.
+
+Tue Feb 20 20:46:21 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+	* sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare.
+	Mark operand letters uU as in use.
+
+Mon Feb 19 01:59:08 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+	* sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_SPARCLET.
+	(sparc_opcode_arch): Delete member `conflicts'.  Add `supported'.
+	(SPARC_OPCODE_SUPPORTED): New macro.
+	(SPARC_OPCODE_CONFLICT_P): Rewrite.
+	(F_NOTV9): Delete.
+
+Fri Feb 16 12:23:34 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* sparc.h (sparc_opcode_lookup_arch) Make return type in
+	declaration consistent with return type in definition.
+
+Wed Feb 14 18:14:11 1996  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (i386_optab): Remove Data32 from pushf and popf.
+
+Thu Feb  8 14:27:21 1996  James Carlson <carlson@xylogics.com>
+
+	* i386.h (i386_regtab): Add 80486 test registers.
+
+Mon Feb  5 18:35:46 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i960.h (I_HX): Define.
+	(i960_opcodes): Add HX instruction.
+
+Mon Jan 29 12:43:39 1996  Ken Raeburn  <raeburn@cygnus.com>
+
+	* i386.h: Fix waiting forms of finit, fstenv, fsave, fstsw, fstcw,
+	and fclex.
+
+Wed Jan 24 22:36:59 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+	* sparc.h (enum sparc_opcode_arch_val): Replaces sparc_architecture.
+	(SPARC_OPCODE_CONFLICT_P): Renamed from ARCHITECTURES_CONFLICT_P.
+	(bfd_* defines): Delete.
+	(sparc_opcode_archs): Replaces architecture_pname.
+	(sparc_opcode_lookup_arch): Declare.
+	(NUMOPCODES): Delete.
+
+Mon Jan 22 08:24:32 1996  Doug Evans  <dje@charmed.cygnus.com>
+
+	* sparc.h (enum sparc_architecture): Add v9a.
+	(ARCHITECTURES_CONFLICT_P): Update.
+
+Thu Dec 28 13:27:53 1995  John Hassey  <hassey@rtp.dg.com>
+
+	* i386.h: Added Pentium Pro instructions.
+
+Thu Nov  2 22:59:22 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* m68k.h: Document new 'W' operand place.
+
+Tue Oct 24 10:49:10 1995  Jeffrey A Law  (law@cygnus.com)
+
+	* hppa.h: Add lci and syncdma instructions.
+
+Mon Oct 23 11:09:16 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
+
+	* mips.h: Added INSN_4100 flag to mark NEC VR4100 specific
+	instructions.
+
+Mon Oct 16 10:28:15 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* ppc.h (PPC_OPCODE_{COMMON,ANY}): New opcode flags for
+	assembler's -mcom and -many switches.
+
+Wed Oct 11 16:56:33 1995  Ken Raeburn  <raeburn@cygnus.com>
+
+	* i386.h: Fix cmpxchg8b extension opcode description.
+
+Thu Oct  5 18:03:36 1995  Ken Raeburn  <raeburn@cygnus.com>
+
+	* i386.h: Add Pentium instructions wrmsr, rdtsc, rdmsr, cmpxchg8b,
+	and register cr4.
+
+Tue Sep 19 15:26:43 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* m68k.h: Change comment: split type P into types 0, 1 and 2.
+
+Wed Aug 30 13:50:55 1995  Doug Evans  <dje@canuck.cygnus.com>
+
+	* sparc.h (sparc_{encode,decode}_prefetch): Declare.
+
+Tue Aug 29 15:34:58 1995  Doug Evans  <dje@canuck.cygnus.com>
+
+	* sparc.h (sparc_{encode,decode}_{asi,membar}): Declare.
+
+Wed Aug  2 18:32:19 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* m68kmri.h: Remove.
+
+	* m68k.h: Move tables into opcodes/m68k-opc.c, leaving just the
+	declarations.  Remove F_ALIAS and flag field of struct
+	m68k_opcode.  Change arch field of struct m68k_opcode to unsigned
+	int.  Make name and args fields of struct m68k_opcode const.
+
+Wed Aug  2 08:16:46 1995  Doug Evans  <dje@canuck.cygnus.com>
+
+	* sparc.h (F_NOTV9): Define.
+
+Tue Jul 11 14:20:42 1995  Jeff Spiegel  <jeffs@lsil.com>
+
+	* mips.h (INSN_4010): Define.
+
+Wed Jun 21 18:49:51 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	* m68k.h (TBL1): Reverse sense of "round" argument in result.
+
+	Changes from Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>:
+	* m68k.h: Fix argument descriptions of coprocessor
+	instructions to allow only alterable operands where appropriate.
+	[!NO_DEFAULT_SIZES]: An omitted size defaults to `w'.
+	(m68k_opcode_aliases): Add more aliases.
+
+Fri Apr 14 22:15:34 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	* m68k.h: Added explcitly short-sized conditional branches, and a
+	bunch of aliases (fmov*, ftest*, tdivul) to support gcc's
+	svr4-based configurations.
+
+Mon Mar 13 21:30:01 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	Mon Feb 27 08:36:39 1995  Bryan Ford  <baford@cs.utah.edu>
+	* i386.h: added missing Data16/Data32 flags to a few instructions.
+
+Wed Mar  8 15:19:53 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (OP_MASK_FR, OP_SH_FR): Define.
+	(OP_MASK_BCC, OP_SH_BCC): Define.
+	(OP_MASK_PREFX, OP_SH_PREFX): Define.
+	(OP_MASK_CCC, OP_SH_CCC): Define.
+	(INSN_READ_FPR_R): Define.
+	(INSN_RFE): Delete.
+
+Wed Mar  8 03:13:23 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	* m68k.h (enum m68k_architecture): Deleted.
+	(struct m68k_opcode_alias): New type.
+	(m68k_opcodes): Now const.  Deleted opcode aliases with exactly
+	matching constraints, values and flags.  As a side effect of this,
+	the MOTOROLA_SYNTAX_ONLY and MIT_SYNTAX_ONLY macros, which so far
+	as I know were never used, now may need re-examining.
+	(numopcodes): Now const.
+	(m68k_opcode_aliases, numaliases): New variables.
+	(endop): Deleted.
+	[DONT_DEFINE_TABLE]: Declare numopcodes, numaliases, and
+	m68k_opcode_aliases; update declaration of m68k_opcodes.
+
+Mon Mar  6 10:02:00 1995  Jeff Law  (law@snake.cs.utah.edu)
+
+	* hppa.h (delay_type): Delete unused enumeration.
+	(pa_opcode): Replace unused delayed field with an architecture
+	field.
+	(pa_opcodes): Mark each instruction as either PA1.0 or PA1.1.
+
+Fri Mar  3 16:10:24 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (INSN_ISA4): Define.
+
+Fri Feb 24 19:13:37 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (M_DLA_AB, M_DLI): Define.
+
+Thu Feb 23 17:33:09 1995  Jeff Law  (law@snake.cs.utah.edu)
+
+	* hppa.h (fstwx): Fix single-bit error.
+
+Wed Feb 15 12:19:52 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define.
+
+Mon Feb  6 10:35:23 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
+
+	* i386.h: added cpuid instruction , and dr[0-7] aliases for the
+	  debug registers.  From Charles Hannum (mycroft@netbsd.org).
+
+Mon Feb  6 03:31:54 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	Changes from Bryan Ford <baford@schirf.cs.utah.edu> for 16-bit
+	i386 support:
+	* i386.h (MOV_AX_DISP32): New macro.
+	(i386_optab): Added Data16 and Data32 as needed.  Added "w" forms
+	of several call/return instructions.
+	(ADDR_PREFIX_OPCODE): New macro.
+
+Mon Jan 23 16:45:43 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	Sat Jan 21 17:50:38 1995  Pat Rankin  (rankin@eql.caltech.edu)
+
+	* vax.h (struct vot_wot, field `args'): Make it pointer to const
+	char.
+	(struct vot, field `name'): ditto.
+
+Thu Jan 19 14:47:53 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	* vax.h: Supply and properly group all values in end sentinel.
+
+Tue Jan 17 10:55:30 1995  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+
+	* mips.h (INSN_ISA, INSN_4650): Define.
+
+Wed Oct 19 13:34:17 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+
+	* a29k.h: Add operand type 'I' for `inv' and `iretinv'.  On
+	systems with a separate instruction and data cache, such as the
+	29040, these instructions take an optional argument.
+
+Wed Sep 14 17:44:20 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
+
+	* mips.h (INSN_STORE_MEMORY): Correct value to not conflict with
+	INSN_TRAP.
+
+Tue Sep  6 11:39:08 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
+
+	* mips.h (INSN_STORE_MEMORY): Define.
+
+Thu Jul 28 19:28:07 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* sparc.h: Document new operand type 'x'.
+
+Tue Jul 26 17:48:05 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* i960.h (I_CX2): New instruction category.  It includes
+	instructions available on Cx and Jx processors.
+	(I_JX): New instruction category, for JX-only instructions.
+	(i960_opcodes): Put eshro and sysctl in I_CX2 category.  Added
+	Jx-only instructions, in I_JX category.
+
+Wed Jul 13 18:43:47 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* ns32k.h (endop): Made pointer const too.
+
+Sun Jul 10 11:01:09 1994  Ian Dall  (dall@hfrd.dsto.gov.au)
+
+	* ns32k.h: Drop Q operand type as there is no correct use
+	for it. Add I and Z operand types which allow better checking.
+
+Thu Jul  7 12:34:48 1994  Steve Chamberlain  (sac@jonny.cygnus.com)
+
+	* h8300.h (xor.l) :fix bit pattern.
+	(L_2): New size of operand.
+	(trapa): Use it.
+
+Fri Jun 10 16:38:11 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* m68k.h: Move "trap" before "tpcc" to change disassembly.
+
+Fri Jun  3 15:57:36 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* sparc.h: Include v9 definitions.
+
+Thu Jun  2 12:23:17 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* m68k.h (m68060): Defined.
+	(m68040up, mfloat, mmmu): Include it.
+	(struct m68k_opcode): Widen `arch' field.
+	(m68k_opcodes): Updated for M68060.  Removed comments that were
+	instructions commented out by "JF" years ago.
+
+Thu Apr 28 18:31:14 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* m68k.h (struct m68k_opcode): Shorten `arch' field to 8 bits, and
+	add a one-bit `flags' field.
+	(F_ALIAS): New macro.
+
+Wed Apr 27 11:29:52 1994  Steve Chamberlain  (sac@cygnus.com)
+
+	* h8300.h (dec, inc): Get encoding right.
+
+Mon Apr  4 13:12:43 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ppc.h (struct powerpc_operand): Removed signedp field; just use
+	a flag instead.
+	(PPC_OPERAND_SIGNED): Define.
+	(PPC_OPERAND_SIGNOPT): Define.
+
+Thu Mar 31 19:34:08 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* i386.h (IS_JUMP_ON_ECX_ZERO, "jcxz" pattern): Operand size
+	prefix is 0x66, not 0x67.  Patch from H.J. Lu (hlu@nynexst.com).
+
+Thu Mar  3 15:51:05 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* i386.h: Reverse last change.  It'll be handled in gas instead.
+
+Thu Feb 24 15:29:05 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* i386.h (sar): Disabled the two-operand Imm1 form, since it was
+	slower on the 486 and used the implicit shift count despite the
+	explicit operand.  The one-operand form is still available to get
+	the shorter form with the implicit shift count.
+
+Thu Feb 17 12:27:52 1994  Torbjorn Granlund  (tege@mexican.cygnus.com)
+
+	* hppa.h: Fix typo in fstws arg string.
+
+Wed Feb  9 21:23:52 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ppc.h (struct powerpc_opcode): Make operands field unsigned.
+
+Mon Feb  7 19:14:58 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ppc.h (PPC_OPCODE_601): Define.
+
+Fri Feb  4 23:43:50 1994  Jeffrey A. Law  (law@snake.cs.utah.edu)
+
+	* hppa.h (addb): Use '@' for addb and addib pseudo ops.
+	(so we can determine valid completers for both addb and addb[tf].)
+
+	* hppa.h (xmpyu): No floating point format specifier for the
+	xmpyu instruction.
+
+Fri Feb  4 23:36:52 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ppc.h (PPC_OPERAND_NEXT): Define.
+	(PPC_OPERAND_NEGATIVE): Change value to make room for above.
+	(struct powerpc_macro): Define.
+	(powerpc_macros, powerpc_num_macros): Declare.
+
+Fri Jan 21 19:13:50 1994  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* ppc.h: New file.  Header file for PowerPC opcode table.
+
+Mon Jan 17 00:14:23 1994  Jeffrey A. Law  (law@snake.cs.utah.edu)
+
+	* hppa.h: More minor template fixes for sfu and copr (to allow
+	for easier disassembly).
+
+	* hppa.h: Fix templates for all the sfu and copr instructions.
+
+Wed Dec 15 15:12:42 1993  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* i386.h (push): Permit Imm16 operand too.
+
+Sat Dec 11 16:14:06 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	*  h8300.h (andc): Exists in base arch.
+
+Wed Dec  1 12:15:32 1993  Jeffrey A. Law  (law@snake.cs.utah.edu)
+
+	* From Hisashi MINAMINO <minamino@sramhc.sra.co.jp>
+	* hppa.h: #undef NONE to avoid conflict with hiux include files.
+
+Sun Nov 21 22:06:57 1993  Jeffrey A. Law  (law@snake.cs.utah.edu)
+
+	* hppa.h: Add FP quadword store instructions.
+
+Wed Nov 17 17:13:16 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h: (M_J_A): Added.
+	(M_LA): Removed.
+
+Mon Nov  8 12:12:47 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h (OP_MASK_CACHE, OP_SH_CACHE): Define.  From Ted Lemon
+	<mellon@pepper.ncd.com>.
+
+Sun Nov  7 00:30:11 1993  Jeffrey A. Law  (law@snake.cs.utah.edu)
+
+	* hppa.h: Immediate field in probei instructions is unsigned,
+	not low-sign extended.
+
+Wed Nov  3 10:30:00 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* m88k.h (RRI10MASK): Change from 0xfc00ffe0 to 0xfc00fc00.
+
+Tue Nov  2 12:41:30 1993  Ken Raeburn  (raeburn@rover.cygnus.com)
+
+	* i386.h: Add "fxch" without operand.
+
+Mon Nov  1 18:13:03 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h (M_JAL_1, M_JAL_2, M_JAL_A): Added.
+
+Sat Oct  2 22:26:11 1993  Jeffrey A Law  (law@snake.cs.utah.edu)
+
+	* hppa.h: Add gfw and gfr to the opcode table.
+
+Wed Sep 29 16:23:00 1993  K. Richard Pixley  (rich@sendai.cygnus.com)
+
+	* m88k.h: extended to handle m88110.
+
+Tue Sep 28 19:19:08 1993  Jeffrey A Law  (law@snake.cs.utah.edu)
+
+	* hppa.h (be, ble): Use operand type 'z' to denote absolute branch
+	addresses.
+
+Tue Sep 14 14:04:35 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* i960.h (i960_opcodes): Properly bracket initializers.
+
+Mon Sep 13 12:50:52 1993  K. Richard Pixley  (rich@sendai.cygnus.com)
+
+	* m88k.h (BOFLAG): rewrite to avoid nested comment.
+
+Mon Sep 13 15:46:06 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* m68k.h (two): Protect second argument with parentheses.
+
+Fri Sep 10 16:29:47 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+
+	* i386.h (i386_optab): Added new instruction "rsm" (for i386sl).
+	Deleted old in/out instructions in "#if 0" section.
+
+Thu Sep  9 17:42:19 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* i386.h (i386_optab): Properly bracket initializers.
+
+Wed Aug 25 13:50:56 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+
+	* hppa.h (pa_opcode): Use '|' for movb and movib insns.  (From
+	Jeff Law, law@cs.utah.edu).
+
+Mon Aug 23 16:55:03 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+
+	* i386.h (lcall): Accept Imm32 operand also.
+
+Mon Aug 23 12:43:11 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h (M_ABSU): Removed (absolute value of unsigned number??).
+	(M_DABS): Added.
+
+Thu Aug 19 15:08:37 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h (INSN_*): Changed values.  Removed unused definitions.
+	Added INSN_COND_BRANCH_LIKELY, INSN_ISA2 and INSN_ISA3.  Split
+	INSN_LOAD_DELAY into INSN_LOAD_MEMORY_DELAY and
+	INSN_LOAD_COPROC_DELAY.  Split INSN_COPROC_DELAY into
+	INSN_COPROC_MOVE_DELAY and INSN_COPROC_MEMORY_DELAY.
+	(M_*): Added new values for r6000 and r4000 macros.
+	(ANY_DELAY): Removed.
+
+Wed Aug 18 15:37:48 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h: Added M_LI_S and M_LI_SS.
+
+Tue Aug 17 07:08:08 1993  Steve Chamberlain  (sac@phydeaux.cygnus.com)
+
+	* h8300.h: Get some rare mov.bs correct.
+
+Thu Aug  5 09:15:17 1993  Jim Kingdon  (kingdon@lioth.cygnus.com)
+
+	* sparc.h: Don't define const ourself; rely on ansidecl.h having
+	been included.
+
+Fri Jul 30 18:41:11 1993  John Gilmore  (gnu@cygnus.com)
+
+	* sparc.h (F_JSR, F_UNBR, F_CONDBR): Add new flags to mark
+	jump instructions, for use in disassemblers.
+
+Thu Jul 22 07:25:27 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* m88k.h: Make bitfields just unsigned, not unsigned long or
+	unsigned short.
+
+Wed Jul 21 11:55:31 1993  Jim Kingdon  (kingdon@deneb.cygnus.com)
+
+	* hppa.h: New argument type 'y'.  Use in various float instructions.
+
+Mon Jul 19 17:17:03 1993  Jim Kingdon  (kingdon@deneb.cygnus.com)
+
+	* hppa.h (break): First immediate field is unsigned.
+
+	* hppa.h: Add rfir instruction.
+
+Sun Jul 18 16:28:08 1993  Jim Kingdon  (kingdon@rtl.cygnus.com)
+
+	* mips.h: Split the actual table out into ../../opcodes/mips-opc.c.
+
+Fri Jul 16 09:59:29 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* mips.h: Reworked the hazard information somewhat, and fixed some
+	bugs in the instruction hazard descriptions.
+
+Thu Jul 15 12:42:01 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* m88k.h: Corrected a couple of opcodes.
+
+Tue Jul  6 15:17:35 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* mips.h: Replaced with version from Ralph Campbell and OSF.  The
+	new version includes instruction hazard information, but is
+	otherwise reasonably similar.
+
+Thu Jul  1 20:36:17 1993  Doug Evans  (dje@canuck.cygnus.com)
+
+	* h8300.h: Fix typo in UNOP3 (affected sh[al][lr].l).
+
+Fri Jun 11 18:38:44 1993  Ken Raeburn  (raeburn@cygnus.com)
+
+	Patches from Jeff Law, law@cs.utah.edu:
+	* hppa.h: Clean up some of the OLD_TABLE, non-OLD_TABLE braindamage.
+	Make the tables be the same for the following instructions:
+	"bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco",
+	"sh[123]add", "sh[123]add[lo]", "sub", "sub[obt]", "sub[bt]o",
+	"ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio",
+	"comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs",
+	"frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt",
+	"fcmp", and "ftest".
+
+	* hppa.h: Make new and old tables the same for "break", "mtctl",
+	"mfctl", "bb", "ssm", "rsm", "xmpyu", "fmpyadd", "fmpysub".
+	Fix typo in last patch.  Collapse several #ifdefs into a
+	single #ifdef.
+
+	* hppa.h: Delete remaining OLD_TABLE code.  Bring some
+	of the comments up-to-date.
+
+	* hppa.h: Update "free list" of letters and update
+	comments describing each letter's function.
+
+Thu Jul  8 09:05:26 1993  Doug Evans  (dje@canuck.cygnus.com)
+
+	* h8300.h: Lots of little fixes for the h8/300h.
+
+Tue Jun  8 12:16:03 1993  Steve Chamberlain  (sac@phydeaux.cygnus.com)
+
+	 Support for H8/300-H
+	* h8300.h: Lots of new opcodes.
+
+Fri Jun  4 15:41:37 1993  Steve Chamberlain  (sac@phydeaux.cygnus.com)
+
+	* h8300.h: checkpoint, includes H8/300-H opcodes.
+
+Thu Jun  3 15:42:59 1993  Stu Grossman  (grossman@cygnus.com)
+
+	* Patches from Jeffrey Law <law@cs.utah.edu>.
+	* hppa.h: Rework single precision FP
+	instructions so that they correctly disassemble code
+	PA1.1 code.
+
+Thu May 27 19:21:22 1993  Bruce Bauman  (boot@osf.org)
+
+	* i386.h (i386_optab, mov pattern): Remove Mem16 restriction from
+	mov to allow instructions like mov ss,xyz(ecx) to assemble.
+
+Tue May 25 00:39:40 1993  Ken Raeburn  (raeburn@cygnus.com)
+
+	* hppa.h: Use new version from Utah if OLD_TABLE isn't defined;
+	gdb will define it for now.
+
+Mon May 24 15:20:06 1993  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+
+	* sparc.h: Don't end enumerator list with comma.
+
+Fri May 14 15:15:50 1993  Ian Lance Taylor  (ian@cygnus.com)
+
+	* Based on patches from davidj@ICSI.Berkeley.EDU (David Johnson):
+	* mips.h (OP_MASK_COPZ, OP_SH_COPZ): Define.
+	("bc2t"): Correct typo.
+	("[ls]wc[023]"): Use T rather than t.
+	("c[0123]"): Define general coprocessor instructions.
+
+Mon May 10 06:02:25 1993  Ken Raeburn  (raeburn@kr-pc.cygnus.com)
+
+	* m68k.h: Move split point for gcc compilation more towards
+	middle.
+
+Fri Apr  9 13:26:16 1993  Jim Kingdon  (kingdon@cygnus.com)
+
+	* rs6k.h: Clean up instructions for primary opcode 19 (many were
+	simply wrong, ics, rfi, & rfsvc were missing).
+	Add "a" to opr_ext for "bb".  Doc fix.
+
+Thu Mar 18 13:45:31 1993  Per Bothner  (bothner@rtl.cygnus.com)
+
+	* i386.h: 486 extensions from John Hassey (hassey@dg-rtp.dg.com).
+	* mips.h: Add casts, to suppress warnings about shifting too much.
+	* m68k.h: Document the placement code '9'.
+
+Thu Feb 18 02:03:14 1993  John Gilmore  (gnu@cygnus.com)
+
+	* m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART): Add kludge which
+	allows callers to break up the large initialized struct full of
+	opcodes into two half-sized ones.  This permits GCC to compile
+	this module, since it takes exponential space for initializers.
+	(numopcodes, endop): Revise to use AND_OTHER_PART in size calcs.
+
+Thu Feb  4 02:06:56 1993  John Gilmore  (gnu@cygnus.com)
+
+	* a29k.h: Remove RCS crud, update GPL to v2, update copyrights.
+	* convex.h: Added, from GDB's convx-opcode.h.  Added CONST to all
+	initialized structs in it.
+
+Thu Jan 28 21:32:22 1993  John Gilmore  (gnu@cygnus.com)
+
+	Delta 88 changes inspired by Carl Greco, <cgreco@Creighton.Edu>:
+	* m88k.h (PMEM): Avoid previous definition from <sys/param.h>.
+	(AND): Change to AND_ to avoid ansidecl.h `AND' conflict.
+
+Sat Jan 23 18:10:49 PST 1993  Ralph Campbell  (ralphc@pyramid.com)
+
+	* mips.h: document "i" and "j" operands correctly.
+
+Thu Jan  7 15:58:13 1993  Ian Lance Taylor  (ian@tweedledumb.cygnus.com)
+
+	* mips.h: Removed endianness dependency.
+
+Sun Jan  3 14:13:35 1993  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* h8300.h: include info on number of cycles per instruction.
+
+Mon Dec 21 21:29:08 1992  Stu Grossman  (grossman at cygnus.com)
+
+	* hppa.h: Move handy aliases to the front.  Fix masks for extract
+	and deposit instructions.
+
+Sat Dec 12 16:09:48 1992  Ian Lance Taylor  (ian@cygnus.com)
+
+	* i386.h: accept shld and shrd both with and without the shift
+	count argument, which is always %cl.
+
+Fri Nov 27 17:13:18 1992  Ken Raeburn  (raeburn at cygnus.com)
+
+	* i386.h (i386_optab_end, i386_regtab_end): Now const.
+	(one_byte_segment_defaults, two_byte_segment_defaults,
+	i386_prefixtab_end): Ditto.
+
+Mon Nov 23 10:47:25 1992  Ken Raeburn  (raeburn@cygnus.com)
+
+	* vax.h (bb*): Use "v" (bitfield type), not "a" (address operand)
+	for operand 2; from John Carr, jfc@dsg.dec.com.
+
+Wed Nov  4 07:36:49 1992  Ken Raeburn  (raeburn@cygnus.com)
+
+	* m68k.h: Define FIXED_SIZE_BRANCH, so bsr and bra instructions
+	always use 16-bit offsets.  Makes calculated-size jump tables
+	feasible.
+
+Fri Oct 16 22:52:43 1992  Ken Raeburn  (raeburn@cygnus.com)
+
+	* i386.h: Fix one-operand forms of in* and out* patterns.
+
+Tue Sep 22 14:08:14 1992  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+
+	* m68k.h: Added CPU32 support.
+
+Tue Sep 22 00:38:41 1992  John Gilmore  (gnu@cygnus.com)
+
+	* mips.h (break): Disassemble the argument.  Patch from
+	jonathan@cs.stanford.edu (Jonathan Stone).
+
+Wed Sep  9 11:25:28 1992  Ian Lance Taylor  (ian@cygnus.com)
+
+	* m68k.h: merged Motorola and MIT syntax.
+
+Thu Sep  3 09:33:22 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* m68k.h (pmove): make the tests less strict, the 68k book is
+	wrong.
+
+Tue Aug 25 23:25:19 1992  Ken Raeburn  (raeburn@cambridge.cygnus.com)
+
+	* m68k.h (m68ec030): Defined as alias for 68030.
+	(m68k_opcodes): New type characters "3" for 68030 MMU regs and "t"
+	for immediate 0-7 added.  Set up some opcodes (ptest, bkpt) to use
+	them.  Tightened description of "fmovex" to distinguish it from
+	some "pmove" encodings.  Added "pmove" for 68030 MMU regs, cleaned
+	up descriptions that claimed versions were available for chips not
+	supporting them.  Added "pmovefd".
+
+Mon Aug 24 12:04:51 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* m68k.h: fix where the . goes in divull
+
+Wed Aug 19 11:22:24 1992  Ian Lance Taylor  (ian@cygnus.com)
+
+	* m68k.h: the cas2 instruction is supposed to be written with
+	indirection on the last two operands, which can be either data or
+	address registers.  Added a new operand type 'r' which accepts
+	either register type.  Added new cases for cas2l and cas2w which
+	use them.  Corrected masks for cas2 which failed to recognize use
+	of address register.
+
+Fri Aug 14 14:20:38 1992  Per Bothner  (bothner@cygnus.com)
+
+	* m68k.h: Merged in patches (mostly m68040-specific) from
+	Colin Smith <colin@wrs.com>.
+
+	* m68k.h: Merged m68kmri.h and m68k.h (using the former as a
+	base).  Also cleaned up duplicates, re-ordered instructions for
+	the sake of dis-assembling (so aliases come after standard names).
+	* m68kmri.h: Now just defines some macros, and #includes m68k.h.
+
+Wed Aug 12 16:38:15 1992  Steve Chamberlain  (sac@thepub.cygnus.com)
+
+	* m68kmri.h: added various opcodes. Moved jbxx to bxxes. Filled in
+	all missing .s
+
+Mon Aug 10 23:22:33 1992  Ken Raeburn  (raeburn@cygnus.com)
+
+	* sparc.h: Moved tables to BFD library.
+
+	* i386.h (i386_optab): Add fildq, fistpq aliases used by gcc.
+
+Sun Jun 28 13:29:03 1992  Fred Fish  (fnf@cygnus.com)
+
+	* h8300.h: Finish filling in all the holes in the opcode table,
+	so that the Lucid C compiler can digest this as well...
+
+Fri Jun 26 21:27:17 1992  John Gilmore  (gnu at cygnus.com)
+
+	* i386.h: Add setc, setnc, addr16, data16, repz, repnz aliases.
+	Fix opcodes on various sizes of fild/fist instructions
+	(16bit=no suffix, 32bit="l" suffix, 64bit="ll" suffix).
+	Use tabs to indent for comments.  Fixes suggested by Minh Tran-Le.
+
+Thu Jun 25 16:13:26 1992  Stu Grossman  (grossman at cygnus.com)
+
+	* h8300.h: Fill in all the holes in the opcode table so that the
+	losing HPUX C compiler can digest this...
+
+Thu Jun 11 12:15:25 1992  John Gilmore  (gnu at cygnus.com)
+
+	* mips.h: Fix decoding of coprocessor instructions, somewhat.
+	(Fix by Eric Anderson, 3jean@maas-neotek.arc.nasa.gov.)
+
+Thu May 28 11:17:44 1992  Jim Wilson  (wilson@sphagnum.cygnus.com)
+
+	* sparc.h: Add new architecture variant sparclite; add its scan
+	and divscc opcodes.  Define ARCHITECTURES_CONFLICT_P macro.
+
+Tue May  5 14:23:27 1992  Per Bothner  (bothner@rtl.cygnus.com)
+
+	* mips.h: Add some more opcode synonyms (from Frank Yellin,
+	fy@lucid.com).
+
+Thu Apr 16 18:25:26 1992  Per Bothner  (bothner@cygnus.com)
+
+	* rs6k.h: New version from IBM (Metin).
+
+Thu Apr  9 00:31:19 1992  Per Bothner  (bothner@rtl.cygnus.com)
+
+	* rs6k.h: Fix incorrect extended opcode for instructions `fm'
+	and `fd'.  (From metin@ibmpa.awdpa.ibm.com (Metin G. Ozisik).)
+
+Tue Apr  7 13:38:47 1992  Stu Grossman  (grossman at cygnus.com)
+
+	* rs6k.h: Move from ../../gdb/rs6k-opcode.h.
+
+Fri Apr  3 11:30:20 1992  Fred Fish  (fnf@cygnus.com)
+
+	* m68k.h (one, two): Cast macro args to unsigned to suppress
+	complaints from compiler and lint about integer overflow during
+	shift.
+
+Sun Mar 29 12:22:08 1992  John Gilmore  (gnu at cygnus.com)
+
+	* sparc.h (OP): Avoid signed overflow when shifting to high order bit.
+
+Fri Mar  6 00:22:38 1992  John Gilmore  (gnu at cygnus.com)
+
+	* mips.h: Make bitfield layout depend on the HOST compiler,
+	not on the TARGET system.
+
+Fri Feb 21 01:29:51 1992  K. Richard Pixley  (rich@cygnus.com)
+
+	* i386.h: added inb, inw, outb, outw opcodes, added att syntax for
+	  scmp, slod, smov, ssca, ssto.  Curtesy Minh Tran-Le
+	  <TRANLE@INTELLICORP.COM>.
+
+Thu Jan 30 07:31:44 1992  Steve Chamberlain  (sac at rtl.cygnus.com)
+
+	* h8300.h: turned op_type enum into #define list
+
+Thu Jan 30 01:07:24 1992  John Gilmore  (gnu at cygnus.com)
+
+	* sparc.h: Remove "cypress" architecture.  Remove "fitox" and
+	similar instructions -- they've been renamed to "fitoq", etc.
+	REALLY fix tsubcctv.  Fix "fcmpeq" and "fcmpq" which had wrong
+	number of arguments.
+	* h8300.h: Remove extra ; which produces compiler warning.
+
+Tue Jan 28 22:59:22 1992  Stu Grossman  (grossman at cygnus.com)
+
+	* sparc.h: fix opcode for tsubcctv.
+
+Tue Jan  7 17:19:39 1992  K. Richard Pixley  (rich at cygnus.com)
+
+	* sparc.h: fba and cba are now aliases for fb and cb respectively.
+
+Fri Dec 27 10:55:50 1991  Per Bothner  (bothner at cygnus.com)
+
+	* sparc.h (nop): Made the 'lose' field be even tighter,
+	so only a standard 'nop' is disassembled as a nop.
+
+Sun Dec 22 12:18:18 1991  Michael Tiemann  (tiemann at cygnus.com)
+
+	* sparc.h (nop): Add RD_GO to `lose' so that only %g0 in dest is
+	disassembled as a nop.
+
+Wed Dec 18 17:19:44 1991  Stu Grossman  (grossman at cygnus.com)
+
+	* m68k.h, sparc.h: ANSIfy enums.
+
+Tue Dec 10 00:22:20 1991  K. Richard Pixley  (rich at rtl.cygnus.com)
+
+	* sparc.h: fix a typo.
+
+Sat Nov 30 20:40:51 1991  Steve Chamberlain  (sac at rtl.cygnus.com)
+
+	* a29k.h, arm.h, h8300.h,  i386.h,  i860.h, i960.h , m68k.h,
+	m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h,
+	vax.h: Renamed from ../<foo>-opcode.h.
+
+
+Copyright (C) 1991-2003 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
+
diff --git a/binutils-2.25/include/opcode/aarch64.h b/binutils-2.25/include/opcode/aarch64.h
new file mode 100644
index 00000000..eaf3cda5
--- /dev/null
+++ b/binutils-2.25/include/opcode/aarch64.h
@@ -0,0 +1,932 @@
+/* AArch64 assembler/disassembler support.
+
+   Copyright 2009, 2010, 2011, 2012, 2013  Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is part of GNU Binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the license, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; see the file COPYING3. If not,
+   see <http://www.gnu.org/licenses/>.  */
+
+#ifndef OPCODE_AARCH64_H
+#define OPCODE_AARCH64_H
+
+#include "bfd.h"
+#include "bfd_stdint.h"
+#include <assert.h>
+#include <stdlib.h>
+
+/* The offset for pc-relative addressing is currently defined to be 0.  */
+#define AARCH64_PCREL_OFFSET		0
+
+typedef uint32_t aarch64_insn;
+
+/* The following bitmasks control CPU features.  */
+#define AARCH64_FEATURE_V8	0x00000001	/* All processors.  */
+#define AARCH64_FEATURE_CRYPTO	0x00010000	/* Crypto instructions.  */
+#define AARCH64_FEATURE_FP	0x00020000	/* FP instructions.  */
+#define AARCH64_FEATURE_SIMD	0x00040000	/* SIMD instructions.  */
+#define AARCH64_FEATURE_CRC	0x00080000	/* CRC instructions.  */
+
+/* Architectures are the sum of the base and extensions.  */
+#define AARCH64_ARCH_V8		AARCH64_FEATURE (AARCH64_FEATURE_V8, \
+						 AARCH64_FEATURE_FP  \
+						 | AARCH64_FEATURE_SIMD)
+#define AARCH64_ARCH_NONE	AARCH64_FEATURE (0, 0)
+#define AARCH64_ANY		AARCH64_FEATURE (-1, 0)	/* Any basic core.  */
+
+/* CPU-specific features.  */
+typedef unsigned long aarch64_feature_set;
+
+#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)	\
+  (((CPU) & (FEAT)) != 0)
+
+#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)	\
+  do						\
+    {						\
+      (TARG) = (F1) | (F2);			\
+    }						\
+  while (0)
+
+#define AARCH64_CLEAR_FEATURE(TARG,F1,F2)	\
+  do						\
+    { 						\
+      (TARG) = (F1) &~ (F2);			\
+    }						\
+  while (0)
+
+#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
+
+#define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT)	\
+  (((OPC) & (FEAT)) != 0)
+
+enum aarch64_operand_class
+{
+  AARCH64_OPND_CLASS_NIL,
+  AARCH64_OPND_CLASS_INT_REG,
+  AARCH64_OPND_CLASS_MODIFIED_REG,
+  AARCH64_OPND_CLASS_FP_REG,
+  AARCH64_OPND_CLASS_SIMD_REG,
+  AARCH64_OPND_CLASS_SIMD_ELEMENT,
+  AARCH64_OPND_CLASS_SISD_REG,
+  AARCH64_OPND_CLASS_SIMD_REGLIST,
+  AARCH64_OPND_CLASS_CP_REG,
+  AARCH64_OPND_CLASS_ADDRESS,
+  AARCH64_OPND_CLASS_IMMEDIATE,
+  AARCH64_OPND_CLASS_SYSTEM,
+};
+
+/* Operand code that helps both parsing and coding.
+   Keep AARCH64_OPERANDS synced.  */
+
+enum aarch64_opnd
+{
+  AARCH64_OPND_NIL,	/* no operand---MUST BE FIRST!*/
+
+  AARCH64_OPND_Rd,	/* Integer register as destination.  */
+  AARCH64_OPND_Rn,	/* Integer register as source.  */
+  AARCH64_OPND_Rm,	/* Integer register as source.  */
+  AARCH64_OPND_Rt,	/* Integer register used in ld/st instructions.  */
+  AARCH64_OPND_Rt2,	/* Integer register used in ld/st pair instructions.  */
+  AARCH64_OPND_Rs,	/* Integer register used in ld/st exclusive.  */
+  AARCH64_OPND_Ra,	/* Integer register used in ddp_3src instructions.  */
+  AARCH64_OPND_Rt_SYS,	/* Integer register used in system instructions.  */
+
+  AARCH64_OPND_Rd_SP,	/* Integer Rd or SP.  */
+  AARCH64_OPND_Rn_SP,	/* Integer Rn or SP.  */
+  AARCH64_OPND_Rm_EXT,	/* Integer Rm extended.  */
+  AARCH64_OPND_Rm_SFT,	/* Integer Rm shifted.  */
+
+  AARCH64_OPND_Fd,	/* Floating-point Fd.  */
+  AARCH64_OPND_Fn,	/* Floating-point Fn.  */
+  AARCH64_OPND_Fm,	/* Floating-point Fm.  */
+  AARCH64_OPND_Fa,	/* Floating-point Fa.  */
+  AARCH64_OPND_Ft,	/* Floating-point Ft.  */
+  AARCH64_OPND_Ft2,	/* Floating-point Ft2.  */
+
+  AARCH64_OPND_Sd,	/* AdvSIMD Scalar Sd.  */
+  AARCH64_OPND_Sn,	/* AdvSIMD Scalar Sn.  */
+  AARCH64_OPND_Sm,	/* AdvSIMD Scalar Sm.  */
+
+  AARCH64_OPND_Vd,	/* AdvSIMD Vector Vd.  */
+  AARCH64_OPND_Vn,	/* AdvSIMD Vector Vn.  */
+  AARCH64_OPND_Vm,	/* AdvSIMD Vector Vm.  */
+  AARCH64_OPND_VdD1,	/* AdvSIMD <Vd>.D[1]; for FMOV only.  */
+  AARCH64_OPND_VnD1,	/* AdvSIMD <Vn>.D[1]; for FMOV only.  */
+  AARCH64_OPND_Ed,	/* AdvSIMD Vector Element Vd.  */
+  AARCH64_OPND_En,	/* AdvSIMD Vector Element Vn.  */
+  AARCH64_OPND_Em,	/* AdvSIMD Vector Element Vm.  */
+  AARCH64_OPND_LVn,	/* AdvSIMD Vector register list used in e.g. TBL.  */
+  AARCH64_OPND_LVt,	/* AdvSIMD Vector register list used in ld/st.  */
+  AARCH64_OPND_LVt_AL,	/* AdvSIMD Vector register list for loading single
+			   structure to all lanes.  */
+  AARCH64_OPND_LEt,	/* AdvSIMD Vector Element list.  */
+
+  AARCH64_OPND_Cn,	/* Co-processor register in CRn field.  */
+  AARCH64_OPND_Cm,	/* Co-processor register in CRm field.  */
+
+  AARCH64_OPND_IDX,	/* AdvSIMD EXT index operand.  */
+  AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
+  AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
+  AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
+  AARCH64_OPND_SIMD_IMM_SFT,	/* AdvSIMD modified immediate with shift.  */
+  AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
+  AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
+			   (no encoding).  */
+  AARCH64_OPND_IMM0,	/* Immediate for #0.  */
+  AARCH64_OPND_FPIMM0,	/* Immediate for #0.0.  */
+  AARCH64_OPND_FPIMM,	/* Floating-point Immediate.  */
+  AARCH64_OPND_IMMR,	/* Immediate #<immr> in e.g. BFM.  */
+  AARCH64_OPND_IMMS,	/* Immediate #<imms> in e.g. BFM.  */
+  AARCH64_OPND_WIDTH,	/* Immediate #<width> in e.g. BFI.  */
+  AARCH64_OPND_IMM,	/* Immediate.  */
+  AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
+  AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
+  AARCH64_OPND_UIMM4,	/* Unsigned 4-bit immediate in the CRm field.  */
+  AARCH64_OPND_UIMM7,	/* Unsigned 7-bit immediate in the CRm:op2 fields.  */
+  AARCH64_OPND_BIT_NUM,	/* Immediate.  */
+  AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
+  AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
+  AARCH64_OPND_NZCV,	/* Flag bit specifier giving an alternative value for
+			   each condition flag.  */
+
+  AARCH64_OPND_LIMM,	/* Logical Immediate.  */
+  AARCH64_OPND_AIMM,	/* Arithmetic immediate.  */
+  AARCH64_OPND_HALF,	/* #<imm16>{, LSL #<shift>} operand in move wide.  */
+  AARCH64_OPND_FBITS,	/* FP #<fbits> operand in e.g. SCVTF */
+  AARCH64_OPND_IMM_MOV,	/* Immediate operand for the MOV alias.  */
+
+  AARCH64_OPND_COND,	/* Standard condition as the last operand.  */
+
+  AARCH64_OPND_ADDR_ADRP,	/* Memory address for ADRP */
+  AARCH64_OPND_ADDR_PCREL14,	/* 14-bit PC-relative address for e.g. TBZ.  */
+  AARCH64_OPND_ADDR_PCREL19,	/* 19-bit PC-relative address for e.g. LDR.  */
+  AARCH64_OPND_ADDR_PCREL21,	/* 21-bit PC-relative address for e.g. ADR.  */
+  AARCH64_OPND_ADDR_PCREL26,	/* 26-bit PC-relative address for e.g. BL.  */
+
+  AARCH64_OPND_ADDR_SIMPLE,	/* Address of ld/st exclusive.  */
+  AARCH64_OPND_ADDR_REGOFF,	/* Address of register offset.  */
+  AARCH64_OPND_ADDR_SIMM7,	/* Address of signed 7-bit immediate.  */
+  AARCH64_OPND_ADDR_SIMM9,	/* Address of signed 9-bit immediate.  */
+  AARCH64_OPND_ADDR_SIMM9_2,	/* Same as the above, but the immediate is
+				   negative or unaligned and there is
+				   no writeback allowed.  This operand code
+				   is only used to support the programmer-
+				   friendly feature of using LDR/STR as the
+				   the mnemonic name for LDUR/STUR instructions
+				   wherever there is no ambiguity.  */
+  AARCH64_OPND_ADDR_UIMM12,	/* Address of unsigned 12-bit immediate.  */
+  AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
+  AARCH64_OPND_SIMD_ADDR_POST,	/* Address of ld/st multiple post-indexed.  */
+
+  AARCH64_OPND_SYSREG,		/* System register operand.  */
+  AARCH64_OPND_PSTATEFIELD,	/* PSTATE field name operand.  */
+  AARCH64_OPND_SYSREG_AT,	/* System register <at_op> operand.  */
+  AARCH64_OPND_SYSREG_DC,	/* System register <dc_op> operand.  */
+  AARCH64_OPND_SYSREG_IC,	/* System register <ic_op> operand.  */
+  AARCH64_OPND_SYSREG_TLBI,	/* System register <tlbi_op> operand.  */
+  AARCH64_OPND_BARRIER,		/* Barrier operand.  */
+  AARCH64_OPND_BARRIER_ISB,	/* Barrier operand for ISB.  */
+  AARCH64_OPND_PRFOP,		/* Prefetch operation.  */
+};
+
+/* Qualifier constrains an operand.  It either specifies a variant of an
+   operand type or limits values available to an operand type.
+
+   N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
+
+enum aarch64_opnd_qualifier
+{
+  /* Indicating no further qualification on an operand.  */
+  AARCH64_OPND_QLF_NIL,
+
+  /* Qualifying an operand which is a general purpose (integer) register;
+     indicating the operand data size or a specific register.  */
+  AARCH64_OPND_QLF_W,	/* Wn, WZR or WSP.  */
+  AARCH64_OPND_QLF_X,	/* Xn, XZR or XSP.  */
+  AARCH64_OPND_QLF_WSP,	/* WSP.  */
+  AARCH64_OPND_QLF_SP,	/* SP.  */
+
+  /* Qualifying an operand which is a floating-point register, a SIMD
+     vector element or a SIMD vector element list; indicating operand data
+     size or the size of each SIMD vector element in the case of a SIMD
+     vector element list.
+     These qualifiers are also used to qualify an address operand to
+     indicate the size of data element a load/store instruction is
+     accessing.
+     They are also used for the immediate shift operand in e.g. SSHR.  Such
+     a use is only for the ease of operand encoding/decoding and qualifier
+     sequence matching; such a use should not be applied widely; use the value
+     constraint qualifiers for immediate operands wherever possible.  */
+  AARCH64_OPND_QLF_S_B,
+  AARCH64_OPND_QLF_S_H,
+  AARCH64_OPND_QLF_S_S,
+  AARCH64_OPND_QLF_S_D,
+  AARCH64_OPND_QLF_S_Q,
+
+  /* Qualifying an operand which is a SIMD vector register or a SIMD vector
+     register list; indicating register shape.
+     They are also used for the immediate shift operand in e.g. SSHR.  Such
+     a use is only for the ease of operand encoding/decoding and qualifier
+     sequence matching; such a use should not be applied widely; use the value
+     constraint qualifiers for immediate operands wherever possible.  */
+  AARCH64_OPND_QLF_V_8B,
+  AARCH64_OPND_QLF_V_16B,
+  AARCH64_OPND_QLF_V_4H,
+  AARCH64_OPND_QLF_V_8H,
+  AARCH64_OPND_QLF_V_2S,
+  AARCH64_OPND_QLF_V_4S,
+  AARCH64_OPND_QLF_V_1D,
+  AARCH64_OPND_QLF_V_2D,
+  AARCH64_OPND_QLF_V_1Q,
+
+  /* Constraint on value.  */
+  AARCH64_OPND_QLF_imm_0_7,
+  AARCH64_OPND_QLF_imm_0_15,
+  AARCH64_OPND_QLF_imm_0_31,
+  AARCH64_OPND_QLF_imm_0_63,
+  AARCH64_OPND_QLF_imm_1_32,
+  AARCH64_OPND_QLF_imm_1_64,
+
+  /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
+     or shift-ones.  */
+  AARCH64_OPND_QLF_LSL,
+  AARCH64_OPND_QLF_MSL,
+
+  /* Special qualifier helping retrieve qualifier information during the
+     decoding time (currently not in use).  */
+  AARCH64_OPND_QLF_RETRIEVE,
+};
+
+/* Instruction class.  */
+
+enum aarch64_insn_class
+{
+  addsub_carry,
+  addsub_ext,
+  addsub_imm,
+  addsub_shift,
+  asimdall,
+  asimddiff,
+  asimdelem,
+  asimdext,
+  asimdimm,
+  asimdins,
+  asimdmisc,
+  asimdperm,
+  asimdsame,
+  asimdshf,
+  asimdtbl,
+  asisddiff,
+  asisdelem,
+  asisdlse,
+  asisdlsep,
+  asisdlso,
+  asisdlsop,
+  asisdmisc,
+  asisdone,
+  asisdpair,
+  asisdsame,
+  asisdshf,
+  bitfield,
+  branch_imm,
+  branch_reg,
+  compbranch,
+  condbranch,
+  condcmp_imm,
+  condcmp_reg,
+  condsel,
+  cryptoaes,
+  cryptosha2,
+  cryptosha3,
+  dp_1src,
+  dp_2src,
+  dp_3src,
+  exception,
+  extract,
+  float2fix,
+  float2int,
+  floatccmp,
+  floatcmp,
+  floatdp1,
+  floatdp2,
+  floatdp3,
+  floatimm,
+  floatsel,
+  ldst_immpost,
+  ldst_immpre,
+  ldst_imm9,	/* immpost or immpre */
+  ldst_pos,
+  ldst_regoff,
+  ldst_unpriv,
+  ldst_unscaled,
+  ldstexcl,
+  ldstnapair_offs,
+  ldstpair_off,
+  ldstpair_indexed,
+  loadlit,
+  log_imm,
+  log_shift,
+  movewide,
+  pcreladdr,
+  ic_system,
+  testbranch,
+};
+
+/* Opcode enumerators.  */
+
+enum aarch64_op
+{
+  OP_NIL,
+  OP_STRB_POS,
+  OP_LDRB_POS,
+  OP_LDRSB_POS,
+  OP_STRH_POS,
+  OP_LDRH_POS,
+  OP_LDRSH_POS,
+  OP_STR_POS,
+  OP_LDR_POS,
+  OP_STRF_POS,
+  OP_LDRF_POS,
+  OP_LDRSW_POS,
+  OP_PRFM_POS,
+
+  OP_STURB,
+  OP_LDURB,
+  OP_LDURSB,
+  OP_STURH,
+  OP_LDURH,
+  OP_LDURSH,
+  OP_STUR,
+  OP_LDUR,
+  OP_STURV,
+  OP_LDURV,
+  OP_LDURSW,
+  OP_PRFUM,
+
+  OP_LDR_LIT,
+  OP_LDRV_LIT,
+  OP_LDRSW_LIT,
+  OP_PRFM_LIT,
+
+  OP_ADD,
+  OP_B,
+  OP_BL,
+
+  OP_MOVN,
+  OP_MOVZ,
+  OP_MOVK,
+
+  OP_MOV_IMM_LOG,	/* MOV alias for moving bitmask immediate.  */
+  OP_MOV_IMM_WIDE,	/* MOV alias for moving wide immediate.  */
+  OP_MOV_IMM_WIDEN,	/* MOV alias for moving wide immediate (negated).  */
+
+  OP_MOV_V,		/* MOV alias for moving vector register.  */
+
+  OP_ASR_IMM,
+  OP_LSR_IMM,
+  OP_LSL_IMM,
+
+  OP_BIC,
+
+  OP_UBFX,
+  OP_BFXIL,
+  OP_SBFX,
+  OP_SBFIZ,
+  OP_BFI,
+  OP_UBFIZ,
+  OP_UXTB,
+  OP_UXTH,
+  OP_UXTW,
+
+  OP_CINC,
+  OP_CINV,
+  OP_CNEG,
+  OP_CSET,
+  OP_CSETM,
+
+  OP_FCVT,
+  OP_FCVTN,
+  OP_FCVTN2,
+  OP_FCVTL,
+  OP_FCVTL2,
+  OP_FCVTXN_S,		/* Scalar version.  */
+
+  OP_ROR_IMM,
+
+  OP_SXTL,
+  OP_SXTL2,
+  OP_UXTL,
+  OP_UXTL2,
+
+  OP_TOTAL_NUM,		/* Pseudo.  */
+};
+
+/* Maximum number of operands an instruction can have.  */
+#define AARCH64_MAX_OPND_NUM 6
+/* Maximum number of qualifier sequences an instruction can have.  */
+#define AARCH64_MAX_QLF_SEQ_NUM 10
+/* Operand qualifier typedef; optimized for the size.  */
+typedef unsigned char aarch64_opnd_qualifier_t;
+/* Operand qualifier sequence typedef.  */
+typedef aarch64_opnd_qualifier_t	\
+	  aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
+
+/* FIXME: improve the efficiency.  */
+static inline bfd_boolean
+empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
+{
+  int i;
+  for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
+    if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
+      return FALSE;
+  return TRUE;
+}
+
+/* This structure holds information for a particular opcode.  */
+
+struct aarch64_opcode
+{
+  /* The name of the mnemonic.  */
+  const char *name;
+
+  /* The opcode itself.  Those bits which will be filled in with
+     operands are zeroes.  */
+  aarch64_insn opcode;
+
+  /* The opcode mask.  This is used by the disassembler.  This is a
+     mask containing ones indicating those bits which must match the
+     opcode field, and zeroes indicating those bits which need not
+     match (and are presumably filled in by operands).  */
+  aarch64_insn mask;
+
+  /* Instruction class.  */
+  enum aarch64_insn_class iclass;
+
+  /* Enumerator identifier.  */
+  enum aarch64_op op;
+
+  /* Which architecture variant provides this instruction.  */
+  const aarch64_feature_set *avariant;
+
+  /* An array of operand codes.  Each code is an index into the
+     operand table.  They appear in the order which the operands must
+     appear in assembly code, and are terminated by a zero.  */
+  enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
+
+  /* A list of operand qualifier code sequence.  Each operand qualifier
+     code qualifies the corresponding operand code.  Each operand
+     qualifier sequence specifies a valid opcode variant and related
+     constraint on operands.  */
+  aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
+
+  /* Flags providing information about this instruction */
+  uint32_t flags;
+};
+
+typedef struct aarch64_opcode aarch64_opcode;
+
+/* Table describing all the AArch64 opcodes.  */
+extern aarch64_opcode aarch64_opcode_table[];
+
+/* Opcode flags.  */
+#define F_ALIAS (1 << 0)
+#define F_HAS_ALIAS (1 << 1)
+/* Disassembly preference priority 1-3 (the larger the higher).  If nothing
+   is specified, it is the priority 0 by default, i.e. the lowest priority.  */
+#define F_P1 (1 << 2)
+#define F_P2 (2 << 2)
+#define F_P3 (3 << 2)
+/* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
+#define F_COND (1 << 4)
+/* Instruction has the field of 'sf'.  */
+#define F_SF (1 << 5)
+/* Instruction has the field of 'size:Q'.  */
+#define F_SIZEQ (1 << 6)
+/* Floating-point instruction has the field of 'type'.  */
+#define F_FPTYPE (1 << 7)
+/* AdvSIMD scalar instruction has the field of 'size'.  */
+#define F_SSIZE (1 << 8)
+/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
+#define F_T (1 << 9)
+/* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
+#define F_GPRSIZE_IN_Q (1 << 10)
+/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
+#define F_LDS_SIZE (1 << 11)
+/* Optional operand; assume maximum of 1 operand can be optional.  */
+#define F_OPD0_OPT (1 << 12)
+#define F_OPD1_OPT (2 << 12)
+#define F_OPD2_OPT (3 << 12)
+#define F_OPD3_OPT (4 << 12)
+#define F_OPD4_OPT (5 << 12)
+/* Default value for the optional operand when omitted from the assembly.  */
+#define F_DEFAULT(X) (((X) & 0x1f) << 15)
+/* Instruction that is an alias of another instruction needs to be
+   encoded/decoded by converting it to/from the real form, followed by
+   the encoding/decoding according to the rules of the real opcode.
+   This compares to the direct coding using the alias's information.
+   N.B. this flag requires F_ALIAS to be used together.  */
+#define F_CONV (1 << 20)
+/* Use together with F_ALIAS to indicate an alias opcode is a programmer
+   friendly pseudo instruction available only in the assembly code (thus will
+   not show up in the disassembly).  */
+#define F_PSEUDO (1 << 21)
+/* Instruction has miscellaneous encoding/decoding rules.  */
+#define F_MISC (1 << 22)
+/* Instruction has the field of 'N'; used in conjunction with F_SF.  */
+#define F_N (1 << 23)
+/* Opcode dependent field.  */
+#define F_OD(X) (((X) & 0x7) << 24)
+/* Next bit is 27.  */
+
+static inline bfd_boolean
+alias_opcode_p (const aarch64_opcode *opcode)
+{
+  return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
+}
+
+static inline bfd_boolean
+opcode_has_alias (const aarch64_opcode *opcode)
+{
+  return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
+}
+
+/* Priority for disassembling preference.  */
+static inline int
+opcode_priority (const aarch64_opcode *opcode)
+{
+  return (opcode->flags >> 2) & 0x3;
+}
+
+static inline bfd_boolean
+pseudo_opcode_p (const aarch64_opcode *opcode)
+{
+  return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
+}
+
+static inline bfd_boolean
+optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
+{
+  return (((opcode->flags >> 12) & 0x7) == idx + 1)
+    ? TRUE : FALSE;
+}
+
+static inline aarch64_insn
+get_optional_operand_default_value (const aarch64_opcode *opcode)
+{
+  return (opcode->flags >> 15) & 0x1f;
+}
+
+static inline unsigned int
+get_opcode_dependent_value (const aarch64_opcode *opcode)
+{
+  return (opcode->flags >> 24) & 0x7;
+}
+
+static inline bfd_boolean
+opcode_has_special_coder (const aarch64_opcode *opcode)
+{
+  return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
+	  | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
+    : FALSE;
+}
+
+struct aarch64_name_value_pair
+{
+  const char *  name;
+  aarch64_insn	value;
+};
+
+extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
+extern const struct aarch64_name_value_pair aarch64_sys_regs [];
+extern const struct aarch64_name_value_pair aarch64_pstatefields [];
+extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
+extern const struct aarch64_name_value_pair aarch64_prfops [32];
+
+typedef struct
+{
+  const char *template;
+  uint32_t value;
+  int has_xt;
+} aarch64_sys_ins_reg;
+
+extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
+extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
+extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
+extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
+
+/* Shift/extending operator kinds.
+   N.B. order is important; keep aarch64_operand_modifiers synced.  */
+enum aarch64_modifier_kind
+{
+  AARCH64_MOD_NONE,
+  AARCH64_MOD_MSL,
+  AARCH64_MOD_ROR,
+  AARCH64_MOD_ASR,
+  AARCH64_MOD_LSR,
+  AARCH64_MOD_LSL,
+  AARCH64_MOD_UXTB,
+  AARCH64_MOD_UXTH,
+  AARCH64_MOD_UXTW,
+  AARCH64_MOD_UXTX,
+  AARCH64_MOD_SXTB,
+  AARCH64_MOD_SXTH,
+  AARCH64_MOD_SXTW,
+  AARCH64_MOD_SXTX,
+};
+
+bfd_boolean
+aarch64_extend_operator_p (enum aarch64_modifier_kind);
+
+enum aarch64_modifier_kind
+aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
+/* Condition.  */
+
+typedef struct
+{
+  /* A list of names with the first one as the disassembly preference;
+     terminated by NULL if fewer than 3.  */
+  const char *names[3];
+  aarch64_insn value;
+} aarch64_cond;
+
+extern const aarch64_cond aarch64_conds[16];
+
+const aarch64_cond* get_cond_from_value (aarch64_insn value);
+const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
+
+/* Structure representing an operand.  */
+
+struct aarch64_opnd_info
+{
+  enum aarch64_opnd type;
+  aarch64_opnd_qualifier_t qualifier;
+  int idx;
+
+  union
+    {
+      struct
+	{
+	  unsigned regno;
+	} reg;
+      struct
+	{
+	  unsigned regno : 5;
+	  unsigned index : 4;
+	} reglane;
+      /* e.g. LVn.  */
+      struct
+	{
+	  unsigned first_regno : 5;
+	  unsigned num_regs : 3;
+	  /* 1 if it is a list of reg element.  */
+	  unsigned has_index : 1;
+	  /* Lane index; valid only when has_index is 1.  */
+	  unsigned index : 4;
+	} reglist;
+      /* e.g. immediate or pc relative address offset.  */
+      struct
+	{
+	  int64_t value;
+	  unsigned is_fp : 1;
+	} imm;
+      /* e.g. address in STR (register offset).  */
+      struct
+	{
+	  unsigned base_regno;
+	  struct
+	    {
+	      union
+		{
+		  int imm;
+		  unsigned regno;
+		};
+	      unsigned is_reg;
+	    } offset;
+	  unsigned pcrel : 1;		/* PC-relative.  */
+	  unsigned writeback : 1;
+	  unsigned preind : 1;		/* Pre-indexed.  */
+	  unsigned postind : 1;		/* Post-indexed.  */
+	} addr;
+      const aarch64_cond *cond;
+      /* The encoding of the system register.  */
+      aarch64_insn sysreg;
+      /* The encoding of the PSTATE field.  */
+      aarch64_insn pstatefield;
+      const aarch64_sys_ins_reg *sysins_op;
+      const struct aarch64_name_value_pair *barrier;
+      const struct aarch64_name_value_pair *prfop;
+    };
+
+  /* Operand shifter; in use when the operand is a register offset address,
+     add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
+  struct
+    {
+      enum aarch64_modifier_kind kind;
+      int amount;
+      unsigned operator_present: 1;	/* Only valid during encoding.  */
+      /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
+      unsigned amount_present: 1;
+    } shifter;
+
+  unsigned skip:1;	/* Operand is not completed if there is a fixup needed
+			   to be done on it.  In some (but not all) of these
+			   cases, we need to tell libopcodes to skip the
+			   constraint checking and the encoding for this
+			   operand, so that the libopcodes can pick up the
+			   right opcode before the operand is fixed-up.  This
+			   flag should only be used during the
+			   assembling/encoding.  */
+  unsigned present:1;	/* Whether this operand is present in the assembly
+			   line; not used during the disassembly.  */
+};
+
+typedef struct aarch64_opnd_info aarch64_opnd_info;
+
+/* Structure representing an instruction.
+
+   It is used during both the assembling and disassembling.  The assembler
+   fills an aarch64_inst after a successful parsing and then passes it to the
+   encoding routine to do the encoding.  During the disassembling, the
+   disassembler calls the decoding routine to decode a binary instruction; on a
+   successful return, such a structure will be filled with information of the
+   instruction; then the disassembler uses the information to print out the
+   instruction.  */
+
+struct aarch64_inst
+{
+  /* The value of the binary instruction.  */
+  aarch64_insn value;
+
+  /* Corresponding opcode entry.  */
+  const aarch64_opcode *opcode;
+
+  /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
+  const aarch64_cond *cond;
+
+  /* Operands information.  */
+  aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
+};
+
+typedef struct aarch64_inst aarch64_inst;
+
+/* Diagnosis related declaration and interface.  */
+
+/* Operand error kind enumerators.
+
+   AARCH64_OPDE_RECOVERABLE
+     Less severe error found during the parsing, very possibly because that
+     GAS has picked up a wrong instruction template for the parsing.
+
+   AARCH64_OPDE_SYNTAX_ERROR
+     General syntax error; it can be either a user error, or simply because
+     that GAS is trying a wrong instruction template.
+
+   AARCH64_OPDE_FATAL_SYNTAX_ERROR
+     Definitely a user syntax error.
+
+   AARCH64_OPDE_INVALID_VARIANT
+     No syntax error, but the operands are not a valid combination, e.g.
+     FMOV D0,S0
+
+   AARCH64_OPDE_OUT_OF_RANGE
+     Error about some immediate value out of a valid range.
+
+   AARCH64_OPDE_UNALIGNED
+     Error about some immediate value not properly aligned (i.e. not being a
+     multiple times of a certain value).
+
+   AARCH64_OPDE_REG_LIST
+     Error about the register list operand having unexpected number of
+     registers.
+
+   AARCH64_OPDE_OTHER_ERROR
+     Error of the highest severity and used for any severe issue that does not
+     fall into any of the above categories.
+
+   The enumerators are only interesting to GAS.  They are declared here (in
+   libopcodes) because that some errors are detected (and then notified to GAS)
+   by libopcodes (rather than by GAS solely).
+
+   The first three errors are only deteced by GAS while the
+   AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
+   only libopcodes has the information about the valid variants of each
+   instruction.
+
+   The enumerators have an increasing severity.  This is helpful when there are
+   multiple instruction templates available for a given mnemonic name (e.g.
+   FMOV); this mechanism will help choose the most suitable template from which
+   the generated diagnostics can most closely describe the issues, if any.  */
+
+enum aarch64_operand_error_kind
+{
+  AARCH64_OPDE_NIL,
+  AARCH64_OPDE_RECOVERABLE,
+  AARCH64_OPDE_SYNTAX_ERROR,
+  AARCH64_OPDE_FATAL_SYNTAX_ERROR,
+  AARCH64_OPDE_INVALID_VARIANT,
+  AARCH64_OPDE_OUT_OF_RANGE,
+  AARCH64_OPDE_UNALIGNED,
+  AARCH64_OPDE_REG_LIST,
+  AARCH64_OPDE_OTHER_ERROR
+};
+
+/* N.B. GAS assumes that this structure work well with shallow copy.  */
+struct aarch64_operand_error
+{
+  enum aarch64_operand_error_kind kind;
+  int index;
+  const char *error;
+  int data[3];	/* Some data for extra information.  */
+};
+
+typedef struct aarch64_operand_error aarch64_operand_error;
+
+/* Encoding entrypoint.  */
+
+extern int
+aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
+		       aarch64_insn *, aarch64_opnd_qualifier_t *,
+		       aarch64_operand_error *);
+
+extern const aarch64_opcode *
+aarch64_replace_opcode (struct aarch64_inst *,
+			const aarch64_opcode *);
+
+/* Given the opcode enumerator OP, return the pointer to the corresponding
+   opcode entry.  */
+
+extern const aarch64_opcode *
+aarch64_get_opcode (enum aarch64_op);
+
+/* Generate the string representation of an operand.  */
+extern void
+aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
+		       const aarch64_opnd_info *, int, int *, bfd_vma *);
+
+/* Miscellaneous interface.  */
+
+extern int
+aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
+
+extern aarch64_opnd_qualifier_t
+aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
+				const aarch64_opnd_qualifier_t, int);
+
+extern int
+aarch64_num_of_operands (const aarch64_opcode *);
+
+extern int
+aarch64_stack_pointer_p (const aarch64_opnd_info *);
+
+extern
+int aarch64_zero_register_p (const aarch64_opnd_info *);
+
+/* Given an operand qualifier, return the expected data element size
+   of a qualified operand.  */
+extern unsigned char
+aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
+
+extern enum aarch64_operand_class
+aarch64_get_operand_class (enum aarch64_opnd);
+
+extern const char *
+aarch64_get_operand_name (enum aarch64_opnd);
+
+extern const char *
+aarch64_get_operand_desc (enum aarch64_opnd);
+
+#ifdef DEBUG_AARCH64
+extern int debug_dump;
+
+extern void
+aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
+
+#define DEBUG_TRACE(M, ...)					\
+  {								\
+    if (debug_dump)						\
+      aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);	\
+  }
+
+#define DEBUG_TRACE_IF(C, M, ...)				\
+  {								\
+    if (debug_dump && (C))					\
+      aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);	\
+  }
+#else  /* !DEBUG_AARCH64 */
+#define DEBUG_TRACE(M, ...) ;
+#define DEBUG_TRACE_IF(C, M, ...) ;
+#endif /* DEBUG_AARCH64 */
+
+#endif /* OPCODE_AARCH64_H */
diff --git a/binutils-2.25/include/opcode/alpha.h b/binutils-2.25/include/opcode/alpha.h
new file mode 100644
index 00000000..2c0d4f6c
--- /dev/null
+++ b/binutils-2.25/include/opcode/alpha.h
@@ -0,0 +1,238 @@
+/* alpha.h -- Header file for Alpha opcode table
+   Copyright 1996, 1999, 2001, 2003, 2010 Free Software Foundation, Inc.
+   Contributed by Richard Henderson <rth@tamu.edu>,
+   patterned after the PPC opcode table written by Ian Lance Taylor.
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef OPCODE_ALPHA_H
+#define OPCODE_ALPHA_H
+
+/* The opcode table is an array of struct alpha_opcode.  */
+
+struct alpha_opcode
+{
+  /* The opcode name.  */
+  const char *name;
+
+  /* The opcode itself.  Those bits which will be filled in with
+     operands are zeroes.  */
+  unsigned opcode;
+
+  /* The opcode mask.  This is used by the disassembler.  This is a
+     mask containing ones indicating those bits which must match the
+     opcode field, and zeroes indicating those bits which need not
+     match (and are presumably filled in by operands).  */
+  unsigned mask;
+
+  /* One bit flags for the opcode.  These are primarily used to
+     indicate specific processors and environments support the
+     instructions.  The defined values are listed below. */
+  unsigned flags;
+
+  /* An array of operand codes.  Each code is an index into the
+     operand table.  They appear in the order which the operands must
+     appear in assembly code, and are terminated by a zero.  */
+  unsigned char operands[4];
+};
+
+/* The table itself is sorted by major opcode number, and is otherwise
+   in the order in which the disassembler should consider
+   instructions.  */
+extern const struct alpha_opcode alpha_opcodes[];
+extern const unsigned alpha_num_opcodes;
+
+/* Values defined for the flags field of a struct alpha_opcode.  */
+
+/* CPU Availability */
+#define AXP_OPCODE_BASE  0x0001  /* Base architecture -- all cpus.  */
+#define AXP_OPCODE_EV4   0x0002  /* EV4 specific PALcode insns.  */
+#define AXP_OPCODE_EV5   0x0004  /* EV5 specific PALcode insns.  */
+#define AXP_OPCODE_EV6   0x0008  /* EV6 specific PALcode insns.  */
+#define AXP_OPCODE_BWX   0x0100  /* Byte/word extension (amask bit 0).  */
+#define AXP_OPCODE_CIX   0x0200  /* "Count" extension (amask bit 1).  */
+#define AXP_OPCODE_MAX   0x0400  /* Multimedia extension (amask bit 8).  */
+
+#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6))
+
+/* A macro to extract the major opcode from an instruction.  */
+#define AXP_OP(i)	(((i) >> 26) & 0x3F)
+
+/* The total number of major opcodes. */
+#define AXP_NOPS	0x40
+
+
+/* The operands table is an array of struct alpha_operand.  */
+
+struct alpha_operand
+{
+  /* The number of bits in the operand.  */
+  unsigned int bits : 5;
+
+  /* How far the operand is left shifted in the instruction.  */
+  unsigned int shift : 5;
+
+  /* The default relocation type for this operand.  */
+  signed int default_reloc : 16;
+
+  /* One bit syntax flags.  */
+  unsigned int flags : 16;
+
+  /* Insertion function.  This is used by the assembler.  To insert an
+     operand value into an instruction, check this field.
+
+     If it is NULL, execute
+         i |= (op & ((1 << o->bits) - 1)) << o->shift;
+     (i is the instruction which we are filling in, o is a pointer to
+     this structure, and op is the opcode value; this assumes twos
+     complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction and the operand value.  It will return the new value
+     of the instruction.  If the ERRMSG argument is not NULL, then if
+     the operand value is illegal, *ERRMSG will be set to a warning
+     string (the operand will be inserted in any case).  If the
+     operand value is legal, *ERRMSG will be unchanged (most operands
+     can accept any value).  */
+  unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
+
+  /* Extraction function.  This is used by the disassembler.  To
+     extract this operand type from an instruction, check this field.
+
+     If it is NULL, compute
+         op = ((i) >> o->shift) & ((1 << o->bits) - 1);
+	 if ((o->flags & AXP_OPERAND_SIGNED) != 0
+	     && (op & (1 << (o->bits - 1))) != 0)
+	   op -= 1 << o->bits;
+     (i is the instruction, o is a pointer to this structure, and op
+     is the result; this assumes twos complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction value.  It will return the value of the operand.  If
+     the INVALID argument is not NULL, *INVALID will be set to
+     non-zero if this operand type can not actually be extracted from
+     this operand (i.e., the instruction does not match).  If the
+     operand is valid, *INVALID will not be changed.  */
+  int (*extract) (unsigned instruction, int *invalid);
+};
+
+/* Elements in the table are retrieved by indexing with values from
+   the operands field of the alpha_opcodes table.  */
+
+extern const struct alpha_operand alpha_operands[];
+extern const unsigned alpha_num_operands;
+
+/* Values defined for the flags field of a struct alpha_operand.  */
+
+/* Mask for selecting the type for typecheck purposes */
+#define AXP_OPERAND_TYPECHECK_MASK					\
+  (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR |		\
+   AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | 	\
+   AXP_OPERAND_UNSIGNED)
+
+/* This operand does not actually exist in the assembler input.  This
+   is used to support extended mnemonics, for which two operands fields
+   are identical.  The assembler should call the insert function with
+   any op value.  The disassembler should call the extract function,
+   ignore the return value, and check the value placed in the invalid
+   argument.  */
+#define AXP_OPERAND_FAKE	01
+
+/* The operand should be wrapped in parentheses rather than separated
+   from the previous by a comma.  This is used for the load and store
+   instructions which want their operands to look like "Ra,disp(Rb)".  */
+#define AXP_OPERAND_PARENS	02
+
+/* Used in combination with PARENS, this supresses the supression of
+   the comma.  This is used for "jmp Ra,(Rb),hint".  */
+#define AXP_OPERAND_COMMA	04
+
+/* This operand names an integer register.  */
+#define AXP_OPERAND_IR		010
+
+/* This operand names a floating point register.  */
+#define AXP_OPERAND_FPR		020
+
+/* This operand is a relative branch displacement.  The disassembler
+   prints these symbolically if possible.  */
+#define AXP_OPERAND_RELATIVE	040
+
+/* This operand takes signed values.  */
+#define AXP_OPERAND_SIGNED	0100
+
+/* This operand takes unsigned values.  This exists primarily so that
+   a flags value of 0 can be treated as end-of-arguments.  */
+#define AXP_OPERAND_UNSIGNED	0200
+
+/* Supress overflow detection on this field.  This is used for hints. */
+#define AXP_OPERAND_NOOVERFLOW	0400
+
+/* Mask for optional argument default value.  */
+#define AXP_OPERAND_OPTIONAL_MASK 07000
+
+/* This operand defaults to zero.  This is used for jump hints.  */
+#define AXP_OPERAND_DEFAULT_ZERO 01000
+
+/* This operand should default to the first (real) operand and is used
+   in conjunction with AXP_OPERAND_OPTIONAL.  This allows
+   "and $0,3,$0" to be written as "and $0,3", etc.  I don't like
+   it, but it's what DEC does.  */
+#define AXP_OPERAND_DEFAULT_FIRST 02000
+
+/* Similarly, this operand should default to the second (real) operand.
+   This allows "negl $0" instead of "negl $0,$0".  */
+#define AXP_OPERAND_DEFAULT_SECOND 04000
+
+
+/* Register common names */
+
+#define AXP_REG_V0	0
+#define AXP_REG_T0	1
+#define AXP_REG_T1	2
+#define AXP_REG_T2	3
+#define AXP_REG_T3	4
+#define AXP_REG_T4	5
+#define AXP_REG_T5	6
+#define AXP_REG_T6	7
+#define AXP_REG_T7	8
+#define AXP_REG_S0	9
+#define AXP_REG_S1	10
+#define AXP_REG_S2	11
+#define AXP_REG_S3	12
+#define AXP_REG_S4	13
+#define AXP_REG_S5	14
+#define AXP_REG_FP	15
+#define AXP_REG_A0	16
+#define AXP_REG_A1	17
+#define AXP_REG_A2	18
+#define AXP_REG_A3	19
+#define AXP_REG_A4	20
+#define AXP_REG_A5	21
+#define AXP_REG_T8	22
+#define AXP_REG_T9	23
+#define AXP_REG_T10	24
+#define AXP_REG_T11	25
+#define AXP_REG_RA	26
+#define AXP_REG_PV	27
+#define AXP_REG_T12	27
+#define AXP_REG_AT	28
+#define AXP_REG_GP	29
+#define AXP_REG_SP	30
+#define AXP_REG_ZERO	31
+
+#endif /* OPCODE_ALPHA_H */
diff --git a/binutils-2.25/include/opcode/arc.h b/binutils-2.25/include/opcode/arc.h
new file mode 100644
index 00000000..695fec1e
--- /dev/null
+++ b/binutils-2.25/include/opcode/arc.h
@@ -0,0 +1,322 @@
+/* Opcode table for the ARC.
+   Copyright 1994, 1995, 1997, 2001, 2002, 2003, 2010
+   Free Software Foundation, Inc.
+   Contributed by Doug Evans (dje@cygnus.com).
+
+   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
+   the GNU Binutils.
+
+   GAS/GDB is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS/GDB is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS or GDB; see the file COPYING3.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* List of the various cpu types.
+   The tables currently use bit masks to say whether the instruction or
+   whatever is supported by a particular cpu.  This lets us have one entry
+   apply to several cpus.
+
+   The `base' cpu must be 0. The cpu type is treated independently of
+   endianness. The complete `mach' number includes endianness.
+   These values are internal to opcodes/bfd/binutils/gas.  */
+#define ARC_MACH_5 0
+#define ARC_MACH_6 1
+#define ARC_MACH_7 2
+#define ARC_MACH_8 4
+
+/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down.  */
+#define ARC_MACH_BIG 16
+
+/* Mask of number of bits necessary to record cpu type.  */
+#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1)
+
+/* Mask of number of bits necessary to record cpu type + endianness.  */
+#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1)
+
+/* Type to denote an ARC instruction (at least a 32 bit unsigned int).  */
+
+typedef unsigned int arc_insn;
+
+struct arc_opcode {
+  char *syntax;              /* syntax of insn  */
+  unsigned long mask, value; /* recognize insn if (op&mask) == value  */
+  int flags;                 /* various flag bits  */
+
+/* Values for `flags'.  */
+
+/* Return CPU number, given flag bits.  */
+#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
+
+/* Return MACH number, given flag bits.  */
+#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK)
+
+/* First opcode flag bit available after machine mask.  */
+#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1)
+
+/* This insn is a conditional branch.  */
+#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START)
+#define SYNTAX_3OP             (ARC_OPCODE_COND_BRANCH << 1)
+#define SYNTAX_LENGTH          (SYNTAX_3OP                 )
+#define SYNTAX_2OP             (SYNTAX_3OP             << 1)
+#define OP1_MUST_BE_IMM        (SYNTAX_2OP             << 1)
+#define OP1_IMM_IMPLIED        (OP1_MUST_BE_IMM        << 1)
+#define SYNTAX_VALID           (OP1_IMM_IMPLIED        << 1)
+
+#define I(x) (((x) & 31) << 27)
+#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
+#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
+#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
+#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
+
+/* These values are used to optimize assembly and disassembly.  Each insn
+   is on a list of related insns (same first letter for assembly, same
+   insn code for disassembly).  */
+
+  struct arc_opcode *next_asm;	/* Next instr to try during assembly.  */
+  struct arc_opcode *next_dis;	/* Next instr to try during disassembly.  */
+
+/* Macros to create the hash values for the lists.  */
+#define ARC_HASH_OPCODE(string) \
+  ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26)
+#define ARC_HASH_ICODE(insn) \
+  ((unsigned int) (insn) >> 27)
+
+ /* Macros to access `next_asm', `next_dis' so users needn't care about the
+    underlying mechanism.  */
+#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm)
+#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis)
+};
+
+/* this is an "insert at front" linked list per Metaware spec
+   that new definitions override older ones.  */
+extern struct arc_opcode *arc_ext_opcodes;
+
+struct arc_operand_value {
+  char *name;          /* eg: "eq"  */
+  short value;         /* eg: 1  */
+  unsigned char type;  /* index into `arc_operands'  */
+  unsigned char flags; /* various flag bits  */
+
+/* Values for `flags'.  */
+
+/* Return CPU number, given flag bits.  */
+#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
+/* Return MACH number, given flag bits.  */
+#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK)
+};
+
+struct arc_ext_operand_value {
+  struct arc_ext_operand_value *next;
+  struct arc_operand_value operand;
+};
+
+extern struct arc_ext_operand_value *arc_ext_operands;
+
+struct arc_operand {
+/* One of the insn format chars.  */
+  unsigned char fmt;
+
+/* The number of bits in the operand (may be unused for a modifier).  */
+  unsigned char bits;
+
+/* How far the operand is left shifted in the instruction, or
+   the modifier's flag bit (may be unused for a modifier.  */
+  unsigned char shift;
+
+/* Various flag bits.  */
+  int flags;
+
+/* Values for `flags'.  */
+
+/* This operand is a suffix to the opcode.  */
+#define ARC_OPERAND_SUFFIX 1
+
+/* This operand is a relative branch displacement.  The disassembler
+   prints these symbolically if possible.  */
+#define ARC_OPERAND_RELATIVE_BRANCH 2
+
+/* This operand is an absolute branch address.  The disassembler
+   prints these symbolically if possible.  */
+#define ARC_OPERAND_ABSOLUTE_BRANCH 4
+
+/* This operand is an address.  The disassembler
+   prints these symbolically if possible.  */
+#define ARC_OPERAND_ADDRESS 8
+
+/* This operand is a long immediate value.  */
+#define ARC_OPERAND_LIMM 0x10
+
+/* This operand takes signed values.  */
+#define ARC_OPERAND_SIGNED 0x20
+
+/* This operand takes signed values, but also accepts a full positive
+   range of values.  That is, if bits is 16, it takes any value from
+   -0x8000 to 0xffff.  */
+#define ARC_OPERAND_SIGNOPT 0x40
+
+/* This operand should be regarded as a negative number for the
+   purposes of overflow checking (i.e., the normal most negative
+   number is disallowed and one more than the normal most positive
+   number is allowed).  This flag will only be set for a signed
+   operand.  */
+#define ARC_OPERAND_NEGATIVE 0x80
+
+/* This operand doesn't really exist.  The program uses these operands
+   in special ways.  */
+#define ARC_OPERAND_FAKE 0x100
+
+/* separate flags operand for j and jl instructions  */
+#define ARC_OPERAND_JUMPFLAGS 0x200
+
+/* allow warnings and errors to be issued after call to insert_xxxxxx  */
+#define ARC_OPERAND_WARN  0x400
+#define ARC_OPERAND_ERROR 0x800
+
+/* this is a load operand */
+#define ARC_OPERAND_LOAD  0x8000
+
+/* this is a store operand */
+#define ARC_OPERAND_STORE 0x10000
+
+/* Modifier values.  */
+/* A dot is required before a suffix.  Eg: .le  */
+#define ARC_MOD_DOT 0x1000
+
+/* A normal register is allowed (not used, but here for completeness).  */
+#define ARC_MOD_REG 0x2000
+
+/* An auxiliary register name is expected.  */
+#define ARC_MOD_AUXREG 0x4000
+
+/* Sum of all ARC_MOD_XXX bits.  */
+#define ARC_MOD_BITS 0x7000
+
+/* Non-zero if the operand type is really a modifier.  */
+#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS)
+
+/* enforce read/write only register restrictions  */
+#define ARC_REGISTER_READONLY    0x01
+#define ARC_REGISTER_WRITEONLY   0x02
+#define ARC_REGISTER_NOSHORT_CUT 0x04
+
+/* Insertion function.  This is used by the assembler.  To insert an
+   operand value into an instruction, check this field.
+
+   If it is NULL, execute
+   i |= (p & ((1 << o->bits) - 1)) << o->shift;
+   (I is the instruction which we are filling in, O is a pointer to
+   this structure, and OP is the opcode value; this assumes twos
+   complement arithmetic).
+   
+   If this field is not NULL, then simply call it with the
+   instruction and the operand value.  It will return the new value
+   of the instruction.  If the ERRMSG argument is not NULL, then if
+   the operand value is illegal, *ERRMSG will be set to a warning
+   string (the operand will be inserted in any case).  If the
+   operand value is legal, *ERRMSG will be unchanged.
+
+   REG is non-NULL when inserting a register value.  */
+
+  arc_insn (*insert)
+    (arc_insn insn, const struct arc_operand *operand, int mods,
+     const struct arc_operand_value *reg, long value, const char **errmsg);
+
+/* Extraction function.  This is used by the disassembler.  To
+   extract this operand type from an instruction, check this field.
+   
+   If it is NULL, compute
+     op = ((i) >> o->shift) & ((1 << o->bits) - 1);
+     if ((o->flags & ARC_OPERAND_SIGNED) != 0
+          && (op & (1 << (o->bits - 1))) != 0)
+       op -= 1 << o->bits;
+   (I is the instruction, O is a pointer to this structure, and OP
+   is the result; this assumes twos complement arithmetic).
+   
+   If this field is not NULL, then simply call it with the
+   instruction value.  It will return the value of the operand.  If
+   the INVALID argument is not NULL, *INVALID will be set to
+   non-zero if this operand type can not actually be extracted from
+   this operand (i.e., the instruction does not match).  If the
+   operand is valid, *INVALID will not be changed.
+
+   INSN is a pointer to an array of two `arc_insn's.  The first element is
+   the insn, the second is the limm if present.
+
+   Operands that have a printable form like registers and suffixes have
+   their struct arc_operand_value pointer stored in OPVAL.  */
+
+  long (*extract)
+    (arc_insn *insn, const struct arc_operand *operand, int mods,
+     const struct arc_operand_value **opval, int *invalid);
+};
+
+/* Bits that say what version of cpu we have. These should be passed to
+   arc_init_opcode_tables. At present, all there is is the cpu type.  */
+
+/* CPU number, given value passed to `arc_init_opcode_tables'.  */
+#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
+/* MACH number, given value passed to `arc_init_opcode_tables'.  */
+#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK)
+
+/* Special register values:  */
+#define ARC_REG_SHIMM_UPDATE 61
+#define ARC_REG_SHIMM 63
+#define ARC_REG_LIMM 62
+
+/* Non-zero if REG is a constant marker.  */
+#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61)
+
+/* Positions and masks of various fields:  */
+#define ARC_SHIFT_REGA 21
+#define ARC_SHIFT_REGB 15
+#define ARC_SHIFT_REGC 9
+#define ARC_MASK_REG 63
+
+/* Delay slot types.  */
+#define ARC_DELAY_NONE 0   /* no delay slot */
+#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */
+#define ARC_DELAY_JUMP 2   /* delay slot only if branch taken */
+
+/* Non-zero if X will fit in a signed 9 bit field.  */
+#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255)
+
+extern const struct arc_operand arc_operands[];
+extern const int arc_operand_count;
+extern struct arc_opcode arc_opcodes[];
+extern const int arc_opcodes_count;
+extern const struct arc_operand_value arc_suffixes[];
+extern const int arc_suffixes_count;
+extern const struct arc_operand_value arc_reg_names[];
+extern const int arc_reg_names_count;
+extern unsigned char arc_operand_map[];
+
+/* Utility fns in arc-opc.c.  */
+int arc_get_opcode_mach (int, int);
+
+/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'.  */
+void arc_opcode_init_tables (int);
+void arc_opcode_init_insert (void);
+void arc_opcode_init_extract (void);
+const struct arc_opcode *arc_opcode_lookup_asm (const char *);
+const struct arc_opcode *arc_opcode_lookup_dis (unsigned int);
+int arc_opcode_limm_p (long *);
+const struct arc_operand_value *arc_opcode_lookup_suffix
+  (const struct arc_operand *type, int value);
+int arc_opcode_supported (const struct arc_opcode *);
+int arc_opval_supported (const struct arc_operand_value *);
+int arc_limm_fixup_adjust (arc_insn);
+int arc_insn_is_j (arc_insn);
+int arc_insn_not_jl (arc_insn);
+int arc_operand_type (int);
+struct arc_operand_value *get_ext_suffix (char *);
+int arc_get_noshortcut_flag (void);
diff --git a/binutils-2.25/include/opcode/arm.h b/binutils-2.25/include/opcode/arm.h
new file mode 100644
index 00000000..851fd3c8
--- /dev/null
+++ b/binutils-2.25/include/opcode/arm.h
@@ -0,0 +1,289 @@
+/* ARM assembler/disassembler support.
+   Copyright 2004, 2010, 2011 Free Software Foundation, Inc.
+
+   This file is part of GDB and GAS.
+
+   GDB and GAS are free software; you can redistribute it and/or
+   modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 3, or (at
+   your option) any later version.
+
+   GDB and GAS are distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GDB or GAS; see the file COPYING3.  If not, write to the
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* The following bitmasks control CPU extensions:  */
+#define ARM_EXT_V1	 0x00000001	/* All processors (core set).  */
+#define ARM_EXT_V2	 0x00000002	/* Multiply instructions.  */
+#define ARM_EXT_V2S	 0x00000004	/* SWP instructions.       */
+#define ARM_EXT_V3	 0x00000008	/* MSR MRS.                */
+#define ARM_EXT_V3M	 0x00000010	/* Allow long multiplies.  */
+#define ARM_EXT_V4	 0x00000020	/* Allow half word loads.  */
+#define ARM_EXT_V4T	 0x00000040	/* Thumb.                  */
+#define ARM_EXT_V5	 0x00000080	/* Allow CLZ, etc.         */
+#define ARM_EXT_V5T	 0x00000100	/* Improved interworking.  */
+#define ARM_EXT_V5ExP	 0x00000200	/* DSP core set.           */
+#define ARM_EXT_V5E	 0x00000400	/* DSP Double transfers.   */
+#define ARM_EXT_V5J	 0x00000800	/* Jazelle extension.	   */
+#define ARM_EXT_V6       0x00001000     /* ARM V6.                 */
+#define ARM_EXT_V6K      0x00002000     /* ARM V6K.                */
+/*			 0x00004000	   Was ARM V6Z.            */
+#define ARM_EXT_V8	 0x00004000     /* is now ARMv8.           */
+#define ARM_EXT_V6T2	 0x00008000	/* Thumb-2.                */
+#define ARM_EXT_DIV	 0x00010000	/* Integer division.       */
+/* The 'M' in Arm V7M stands for Microcontroller.
+   On earlier architecture variants it stands for Multiply.  */
+#define ARM_EXT_V5E_NOTM 0x00020000	/* Arm V5E but not Arm V7M. */
+#define ARM_EXT_V6_NOTM	 0x00040000	/* Arm V6 but not Arm V7M. */
+#define ARM_EXT_V7	 0x00080000	/* Arm V7.                 */
+#define ARM_EXT_V7A	 0x00100000	/* Arm V7A.                */
+#define ARM_EXT_V7R	 0x00200000	/* Arm V7R.                */
+#define ARM_EXT_V7M	 0x00400000	/* Arm V7M.                */
+#define ARM_EXT_V6M	 0x00800000	/* ARM V6M.		    */
+#define ARM_EXT_BARRIER	 0x01000000	/* DSB/DMB/ISB.		    */
+#define ARM_EXT_THUMB_MSR 0x02000000	/* Thumb MSR/MRS.	    */
+#define ARM_EXT_V6_DSP 0x04000000	/* ARM v6 (DSP-related),
+					   not in v7-M.  */
+#define ARM_EXT_MP       0x08000000     /* Multiprocessing Extensions.  */
+#define ARM_EXT_SEC	 0x10000000	/* Security extensions.  */
+#define ARM_EXT_OS	 0x20000000	/* OS Extensions.  */
+#define ARM_EXT_ADIV	 0x40000000	/* Integer divide extensions in ARM 
+					   state.  */
+#define ARM_EXT_VIRT	 0x80000000	/* Virtualization extensions.  */
+
+/* Co-processor space extensions.  */
+#define ARM_CEXT_XSCALE   0x00000001	/* Allow MIA etc.          */
+#define ARM_CEXT_MAVERICK 0x00000002	/* Use Cirrus/DSP coprocessor.  */
+#define ARM_CEXT_IWMMXT   0x00000004    /* Intel Wireless MMX technology coprocessor.   */
+#define ARM_CEXT_IWMMXT2  0x00000008    /* Intel Wireless MMX technology coprocessor version 2.   */
+
+#define FPU_ENDIAN_PURE	 0x80000000	/* Pure-endian doubles.	      */
+#define FPU_ENDIAN_BIG	 0		/* Double words-big-endian.   */
+#define FPU_FPA_EXT_V1	 0x40000000	/* Base FPA instruction set.  */
+#define FPU_FPA_EXT_V2	 0x20000000	/* LFM/SFM.		      */
+#define FPU_MAVERICK	 0x10000000	/* Cirrus Maverick.	      */
+#define FPU_VFP_EXT_V1xD 0x08000000	/* Base VFP instruction set.  */
+#define FPU_VFP_EXT_V1	 0x04000000	/* Double-precision insns.    */
+#define FPU_VFP_EXT_V2	 0x02000000	/* ARM10E VFPr1.	      */
+#define FPU_VFP_EXT_V3xD 0x01000000	/* VFPv3 single-precision.    */
+#define FPU_VFP_EXT_V3	 0x00800000	/* VFPv3 double-precision.    */
+#define FPU_NEON_EXT_V1	 0x00400000	/* Neon (SIMD) insns.	      */
+#define FPU_VFP_EXT_D32  0x00200000	/* Registers D16-D31.	      */
+#define FPU_VFP_EXT_FP16 0x00100000	/* Half-precision extensions. */
+#define FPU_NEON_EXT_FMA 0x00080000	/* Neon fused multiply-add    */
+#define FPU_VFP_EXT_FMA	 0x00040000	/* VFP fused multiply-add     */
+#define FPU_VFP_EXT_ARMV8 0x00020000	/* FP for ARMv8.  */
+#define FPU_NEON_EXT_ARMV8 0x00010000	/* Neon for ARMv8.  */
+#define FPU_CRYPTO_EXT_ARMV8 0x00008000	/* Crypto for ARMv8.  */
+#define CRC_EXT_ARMV8	 0x00004000	/* CRC32 for ARMv8.  */
+
+/* Architectures are the sum of the base and extensions.  The ARM ARM (rev E)
+   defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
+   ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE.  To these we add
+   three more to cover cores prior to ARM6.  Finally, there are cores which
+   implement further extensions in the co-processor space.  */
+#define ARM_AEXT_V1			  ARM_EXT_V1
+#define ARM_AEXT_V2	(ARM_AEXT_V1	| ARM_EXT_V2)
+#define ARM_AEXT_V2S	(ARM_AEXT_V2	| ARM_EXT_V2S)
+#define ARM_AEXT_V3	(ARM_AEXT_V2S	| ARM_EXT_V3)
+#define ARM_AEXT_V3M	(ARM_AEXT_V3	| ARM_EXT_V3M)
+#define ARM_AEXT_V4xM	(ARM_AEXT_V3	| ARM_EXT_V4)
+#define ARM_AEXT_V4	(ARM_AEXT_V3M	| ARM_EXT_V4)
+#define ARM_AEXT_V4TxM	(ARM_AEXT_V4xM	| ARM_EXT_V4T)
+#define ARM_AEXT_V4T	(ARM_AEXT_V4	| ARM_EXT_V4T)
+#define ARM_AEXT_V5xM	(ARM_AEXT_V4xM	| ARM_EXT_V5)
+#define ARM_AEXT_V5	(ARM_AEXT_V4	| ARM_EXT_V5)
+#define ARM_AEXT_V5TxM	(ARM_AEXT_V5xM	| ARM_EXT_V4T | ARM_EXT_V5T)
+#define ARM_AEXT_V5T	(ARM_AEXT_V5	| ARM_EXT_V4T | ARM_EXT_V5T)
+#define ARM_AEXT_V5TExP	(ARM_AEXT_V5T	| ARM_EXT_V5ExP)
+#define ARM_AEXT_V5TE	(ARM_AEXT_V5TExP | ARM_EXT_V5E)
+#define ARM_AEXT_V5TEJ	(ARM_AEXT_V5TE	| ARM_EXT_V5J)
+#define ARM_AEXT_V6     (ARM_AEXT_V5TEJ | ARM_EXT_V6)
+#define ARM_AEXT_V6K    (ARM_AEXT_V6    | ARM_EXT_V6K)
+#define ARM_AEXT_V6Z    (ARM_AEXT_V6K	| ARM_EXT_SEC)
+#define ARM_AEXT_V6ZK   (ARM_AEXT_V6K	| ARM_EXT_SEC)
+#define ARM_AEXT_V6T2   (ARM_AEXT_V6 \
+    | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \
+    | ARM_EXT_V6_DSP )
+#define ARM_AEXT_V6KT2  (ARM_AEXT_V6T2 | ARM_EXT_V6K)
+#define ARM_AEXT_V6ZT2  (ARM_AEXT_V6T2 | ARM_EXT_SEC)
+#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC)
+#define ARM_AEXT_V7_ARM	(ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
+#define ARM_AEXT_V7A	(ARM_AEXT_V7_ARM | ARM_EXT_V7A)
+#define ARM_AEXT_V7R	(ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
+#define ARM_AEXT_NOTM \
+  (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \
+   | ARM_EXT_V6_DSP )
+#define ARM_AEXT_V6M_ONLY \
+  ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM))
+#define ARM_AEXT_V6M \
+  ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM))
+#define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS)
+#define ARM_AEXT_V7M \
+  ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \
+   & ~(ARM_AEXT_NOTM))
+#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
+#define ARM_AEXT_V7EM \
+  (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP)
+#define ARM_AEXT_V8A \
+  (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \
+   | ARM_EXT_VIRT | ARM_EXT_V8)
+
+/* Processors with specific extensions in the co-processor space.  */
+#define ARM_ARCH_XSCALE	ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
+#define ARM_ARCH_IWMMXT	\
+ ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT)
+#define ARM_ARCH_IWMMXT2	\
+ ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2)
+
+#define FPU_VFP_V1xD	(FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
+#define FPU_VFP_V1	(FPU_VFP_V1xD | FPU_VFP_EXT_V1)
+#define FPU_VFP_V2	(FPU_VFP_V1 | FPU_VFP_EXT_V2)
+#define FPU_VFP_V3D16	(FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3)
+#define FPU_VFP_V3	(FPU_VFP_V3D16 | FPU_VFP_EXT_D32)
+#define FPU_VFP_V3xD	(FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD)
+#define FPU_VFP_V4D16	(FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
+#define FPU_VFP_V4	(FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
+#define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
+#define FPU_VFP_ARMV8	(FPU_VFP_V4 | FPU_VFP_EXT_ARMV8)
+#define FPU_NEON_ARMV8	(FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8)
+#define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8)
+#define FPU_VFP_HARD	(FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
+			 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \
+                         | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32)
+#define FPU_FPA		(FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)
+
+/* Deprecated.  */
+#define FPU_ARCH_VFP	ARM_FEATURE (0, FPU_ENDIAN_PURE)
+
+#define FPU_ARCH_FPE	ARM_FEATURE (0, FPU_FPA_EXT_V1)
+#define FPU_ARCH_FPA	ARM_FEATURE (0, FPU_FPA)
+
+#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD)
+#define FPU_ARCH_VFP_V1	  ARM_FEATURE (0, FPU_VFP_V1)
+#define FPU_ARCH_VFP_V2	  ARM_FEATURE (0, FPU_VFP_V2)
+#define FPU_ARCH_VFP_V3D16	ARM_FEATURE (0, FPU_VFP_V3D16)
+#define FPU_ARCH_VFP_V3D16_FP16 \
+  ARM_FEATURE (0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16)
+#define FPU_ARCH_VFP_V3	  ARM_FEATURE (0, FPU_VFP_V3)
+#define FPU_ARCH_VFP_V3_FP16	ARM_FEATURE (0, FPU_VFP_V3 | FPU_VFP_EXT_FP16)
+#define FPU_ARCH_VFP_V3xD	ARM_FEATURE (0, FPU_VFP_V3xD)
+#define FPU_ARCH_VFP_V3xD_FP16	ARM_FEATURE (0, FPU_VFP_V3xD | FPU_VFP_EXT_FP16)
+#define FPU_ARCH_NEON_V1  ARM_FEATURE (0, FPU_NEON_EXT_V1)
+#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
+  ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1)
+#define FPU_ARCH_NEON_FP16 \
+  ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16)
+#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD)
+#define FPU_ARCH_VFP_V4 ARM_FEATURE(0, FPU_VFP_V4)
+#define FPU_ARCH_VFP_V4D16 ARM_FEATURE(0, FPU_VFP_V4D16)
+#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16)
+#define FPU_ARCH_NEON_VFP_V4 \
+  ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)
+#define FPU_ARCH_VFP_ARMV8 ARM_FEATURE(0, FPU_VFP_ARMV8)
+#define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE(0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8)
+#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \
+  ARM_FEATURE(0, FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8)
+#define ARCH_CRC_ARMV8 ARM_FEATURE(0, CRC_EXT_ARMV8)
+
+#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)
+
+#define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK)
+
+#define ARM_ARCH_V1	ARM_FEATURE (ARM_AEXT_V1, 0)
+#define ARM_ARCH_V2	ARM_FEATURE (ARM_AEXT_V2, 0)
+#define ARM_ARCH_V2S	ARM_FEATURE (ARM_AEXT_V2S, 0)
+#define ARM_ARCH_V3	ARM_FEATURE (ARM_AEXT_V3, 0)
+#define ARM_ARCH_V3M	ARM_FEATURE (ARM_AEXT_V3M, 0)
+#define ARM_ARCH_V4xM	ARM_FEATURE (ARM_AEXT_V4xM, 0)
+#define ARM_ARCH_V4	ARM_FEATURE (ARM_AEXT_V4, 0)
+#define ARM_ARCH_V4TxM	ARM_FEATURE (ARM_AEXT_V4TxM, 0)
+#define ARM_ARCH_V4T	ARM_FEATURE (ARM_AEXT_V4T, 0)
+#define ARM_ARCH_V5xM	ARM_FEATURE (ARM_AEXT_V5xM, 0)
+#define ARM_ARCH_V5	ARM_FEATURE (ARM_AEXT_V5, 0)
+#define ARM_ARCH_V5TxM	ARM_FEATURE (ARM_AEXT_V5TxM, 0)
+#define ARM_ARCH_V5T	ARM_FEATURE (ARM_AEXT_V5T, 0)
+#define ARM_ARCH_V5TExP	ARM_FEATURE (ARM_AEXT_V5TExP, 0)
+#define ARM_ARCH_V5TE	ARM_FEATURE (ARM_AEXT_V5TE, 0)
+#define ARM_ARCH_V5TEJ	ARM_FEATURE (ARM_AEXT_V5TEJ, 0)
+#define ARM_ARCH_V6	ARM_FEATURE (ARM_AEXT_V6, 0)
+#define ARM_ARCH_V6K	ARM_FEATURE (ARM_AEXT_V6K, 0)
+#define ARM_ARCH_V6Z	ARM_FEATURE (ARM_AEXT_V6Z, 0)
+#define ARM_ARCH_V6ZK	ARM_FEATURE (ARM_AEXT_V6ZK, 0)
+#define ARM_ARCH_V6T2	ARM_FEATURE (ARM_AEXT_V6T2, 0)
+#define ARM_ARCH_V6KT2	ARM_FEATURE (ARM_AEXT_V6KT2, 0)
+#define ARM_ARCH_V6ZT2	ARM_FEATURE (ARM_AEXT_V6ZT2, 0)
+#define ARM_ARCH_V6ZKT2	ARM_FEATURE (ARM_AEXT_V6ZKT2, 0)
+#define ARM_ARCH_V6M	ARM_FEATURE (ARM_AEXT_V6M, 0)
+#define ARM_ARCH_V6SM	ARM_FEATURE (ARM_AEXT_V6SM, 0)
+#define ARM_ARCH_V7	ARM_FEATURE (ARM_AEXT_V7, 0)
+#define ARM_ARCH_V7A	ARM_FEATURE (ARM_AEXT_V7A, 0)
+#define ARM_ARCH_V7R	ARM_FEATURE (ARM_AEXT_V7R, 0)
+#define ARM_ARCH_V7M	ARM_FEATURE (ARM_AEXT_V7M, 0)
+#define ARM_ARCH_V7EM	ARM_FEATURE (ARM_AEXT_V7EM, 0)
+#define ARM_ARCH_V8A	ARM_FEATURE (ARM_AEXT_V8A, 0)
+
+/* Some useful combinations:  */
+#define ARM_ARCH_NONE	ARM_FEATURE (0, 0)
+#define FPU_NONE	ARM_FEATURE (0, 0)
+#define ARM_ANY		ARM_FEATURE (-1, 0)	/* Any basic core.  */
+#define FPU_ANY_HARD	ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
+#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0)
+/* v7-a+sec.  */
+#define ARM_ARCH_V7A_SEC ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_SEC, 0)
+/* v7-a+mp+sec.  */
+#define ARM_ARCH_V7A_MP_SEC \
+			ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \
+				     0)
+/* v7-a+idiv+mp+sec+virt.  */
+#define ARM_ARCH_V7A_IDIV_MP_SEC_VIRT \
+			ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC \
+				     | ARM_EXT_DIV | ARM_EXT_ADIV \
+				     | ARM_EXT_VIRT, 0)
+/* v7-r+idiv.  */
+#define ARM_ARCH_V7R_IDIV	ARM_FEATURE (ARM_AEXT_V7R | ARM_EXT_ADIV, 0)
+/* Features that are present in v6M and v6S-M but not other v6 cores.  */
+#define ARM_ARCH_V6M_ONLY ARM_FEATURE (ARM_AEXT_V6M_ONLY, 0)
+/* v8-a+fp.  */
+#define ARM_ARCH_V8A_FP	ARM_FEATURE (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8)
+/* v8-a+simd (implies fp).  */
+#define ARM_ARCH_V8A_SIMD	ARM_FEATURE (ARM_AEXT_V8A, \
+					     FPU_ARCH_NEON_VFP_ARMV8)
+/* v8-a+crypto (implies simd+fp).  */
+#define ARM_ARCH_V8A_CRYPTOV1 	ARM_FEATURE (ARM_AEXT_V8A, \
+					     FPU_ARCH_CRYPTO_NEON_VFP_ARMV8)
+
+/* There are too many feature bits to fit in a single word, so use a
+   structure.  For simplicity we put all core features in one word and
+   everything else in the other.  */
+typedef struct
+{
+  unsigned long core;
+  unsigned long coproc;
+} arm_feature_set;
+
+#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
+  (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0)
+
+#define ARM_CPU_IS_ANY(CPU) \
+  ((CPU).core == ((arm_feature_set)ARM_ANY).core)
+
+#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2)	\
+  do {						\
+    (TARG).core = (F1).core | (F2).core;	\
+    (TARG).coproc = (F1).coproc | (F2).coproc;	\
+  } while (0)
+
+#define ARM_CLEAR_FEATURE(TARG,F1,F2)		\
+  do {						\
+    (TARG).core = (F1).core &~ (F2).core;	\
+    (TARG).coproc = (F1).coproc &~ (F2).coproc;	\
+  } while (0)
+
+#define ARM_FEATURE(core, coproc) {(core), (coproc)}
diff --git a/binutils-2.25/include/opcode/avr.h b/binutils-2.25/include/opcode/avr.h
new file mode 100644
index 00000000..f1d73ad9
--- /dev/null
+++ b/binutils-2.25/include/opcode/avr.h
@@ -0,0 +1,300 @@
+/* Opcode table for the Atmel AVR micro controllers.
+
+   Copyright 2000, 2001, 2004, 2006, 2008, 2010, 2012 Free Software Foundation, Inc.
+   Contributed by Denis Chertykov <denisc@overta.ru>
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define AVR_ISA_1200  0x0001 /* In the beginning there was ...  */
+#define AVR_ISA_LPM   0x0002 /* device has LPM */
+#define AVR_ISA_LPMX  0x0004 /* device has LPM Rd,Z[+] */
+#define AVR_ISA_SRAM  0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */
+#define AVR_ISA_MEGA  0x0020 /* device has >8K program memory (JMP and CALL
+				supported, no 8K wrap on RJMP and RCALL) */
+#define AVR_ISA_MUL   0x0040 /* device has new core (MUL, FMUL, ...) */
+#define AVR_ISA_ELPM  0x0080 /* device has >64K program memory (ELPM) */
+#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */
+#define AVR_ISA_SPM   0x0200 /* device can program itself */
+#define AVR_ISA_BRK   0x0400 /* device has BREAK (on-chip debug) */
+#define AVR_ISA_EIND  0x0800 /* device has >128K program memory (none yet) */
+#define AVR_ISA_MOVW  0x1000 /* device has MOVW */
+#define AVR_ISA_SPMX  0x2000 /* device has SPM Z[+] */
+#define AVR_ISA_DES   0x4000 /* device has DES */
+#define AVR_ISA_RMW   0x8000 /* device has RMW instructions XCH,LAC,LAS,LAT */
+
+#define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM)
+#define AVR_ISA_2xxx  (AVR_ISA_TINY1 | AVR_ISA_SRAM)
+/* For the attiny26 which is missing LPM Rd,Z+.  */
+#define AVR_ISA_2xxe  (AVR_ISA_2xxx | AVR_ISA_LPMX)
+#define AVR_ISA_RF401 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX)
+#define AVR_ISA_TINY2 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX | \
+                       AVR_ISA_SPM  | AVR_ISA_BRK)
+#define AVR_ISA_M603  (AVR_ISA_2xxx | AVR_ISA_MEGA)
+#define AVR_ISA_M103  (AVR_ISA_M603 | AVR_ISA_ELPM)
+#define AVR_ISA_M8    (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_MOVW | \
+                       AVR_ISA_LPMX | AVR_ISA_SPM)
+#define AVR_ISA_PWMx  (AVR_ISA_M8   | AVR_ISA_BRK)
+#define AVR_ISA_M161  (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | \
+                       AVR_ISA_LPMX | AVR_ISA_SPM)
+#define AVR_ISA_94K   (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | AVR_ISA_LPMX)
+#define AVR_ISA_M323  (AVR_ISA_M161 | AVR_ISA_BRK)
+#define AVR_ISA_M128  (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX)
+#define AVR_ISA_M256  (AVR_ISA_M128 | AVR_ISA_EIND)
+#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES)
+#define AVR_ISA_XMEGAU (AVR_ISA_XMEGA | AVR_ISA_RMW)
+
+#define AVR_ISA_AVR1   AVR_ISA_TINY1
+#define AVR_ISA_AVR2   AVR_ISA_2xxx
+#define AVR_ISA_AVR25  AVR_ISA_TINY2
+#define AVR_ISA_AVR3   AVR_ISA_M603
+#define AVR_ISA_AVR31 	AVR_ISA_M103
+#define AVR_ISA_AVR35 	(AVR_ISA_AVR3 | AVR_ISA_MOVW | \
+                        AVR_ISA_LPMX | AVR_ISA_SPM | AVR_ISA_BRK)
+#define AVR_ISA_AVR3_ALL (AVR_ISA_AVR3 | AVR_ISA_AVR31 | AVR_ISA_AVR35)
+#define AVR_ISA_AVR4   AVR_ISA_PWMx
+#define AVR_ISA_AVR5   AVR_ISA_M323
+#define AVR_ISA_AVR51  AVR_ISA_M128
+#define AVR_ISA_AVR6   (AVR_ISA_1200 | AVR_ISA_LPM | AVR_ISA_LPMX | \
+                        AVR_ISA_SRAM | AVR_ISA_MEGA | AVR_ISA_MUL | \
+                        AVR_ISA_ELPM | AVR_ISA_ELPMX | AVR_ISA_SPM | \
+                        AVR_ISA_BRK | AVR_ISA_EIND | AVR_ISA_MOVW)
+
+#define REGISTER_P(x) ((x) == 'r'		\
+		       || (x) == 'd'		\
+		       || (x) == 'w'		\
+		       || (x) == 'a'		\
+		       || (x) == 'v')
+
+/* Undefined combination of operands - does the register
+   operand overlap with pre-decremented or post-incremented
+   pointer register (like ld r31,Z+)?  */
+#define AVR_UNDEF_P(x) (((x) & 0xFFED) == 0x91E5 ||		\
+  ((x) & 0xFDEF) == 0x91AD || ((x) & 0xFDEF) == 0x91AE ||	\
+  ((x) & 0xFDEF) == 0x91C9 || ((x) & 0xFDEF) == 0x91CA ||	\
+  ((x) & 0xFDEF) == 0x91E1 || ((x) & 0xFDEF) == 0x91E2)
+
+/* Is this a skip instruction {cpse,sbic,sbis,sbrc,sbrs}?  */
+#define AVR_SKIP_P(x) (((x) & 0xFC00) == 0x1000 ||		\
+  ((x) & 0xFD00) == 0x9900 || ((x) & 0xFC08) == 0xFC00)
+
+/* Is this `ldd r,b+0' or `std b+0,r' (b={Y,Z}, disassembled as
+   `ld r,b' or `st b,r' respectively - next opcode entry)?  */
+#define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000)
+
+/* constraint letters
+   r - any register
+   d - `ldi' register (r16-r31)
+   v - `movw' even register (r0, r2, ..., r28, r30)
+   a - `fmul' register (r16-r23)
+   w - `adiw' register (r24,r26,r28,r30)
+   e - pointer registers (X,Y,Z)
+   b - base pointer register and displacement ([YZ]+disp)
+   z - Z pointer register (for [e]lpm Rd,Z[+])
+   M - immediate value from 0 to 255
+   n - immediate value from 0 to 255 ( n = ~M ). Relocation impossible
+   s - immediate value from 0 to 7
+   P - Port address value from 0 to 63. (in, out)
+   p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis)
+   K - immediate value from 0 to 63 (used in `adiw', `sbiw')
+   i - immediate value
+   l - signed pc relative offset from -64 to 63
+   L - signed pc relative offset from -2048 to 2047
+   h - absolute code address (call, jmp)
+   S - immediate value from 0 to 7 (S = s << 4)
+   E - immediate value from 0 to 15, shifted left by 4 (des)
+   ? - use this opcode entry if no parameters, else use next opcode entry
+
+   Order is important - some binary opcodes have more than one name,
+   the disassembler will only see the first match.
+
+   Remaining undefined opcodes (1699 total - some of them might work
+   as normal instructions if not all of the bits are decoded):
+
+    0x0001...0x00ff    (255) (known to be decoded as `nop' by the old core)
+   "100100xxxxxxx011"  (128) 0x9[0-3][0-9a-f][3b]
+   "100100xxxxxx1000"   (64) 0x9[0-3][0-9a-f]8
+   "1001010xxxxx0100"   (32) 0x9[45][0-9a-f]4
+   "1001010x001x1001"    (4) 0x9[45][23]9
+   "1001010x01xx1001"    (8) 0x9[45][4-7]9
+   "1001010x1xxx1001"   (16) 0x9[45][8-9a-f]9
+   "1001010xxxxx1011"   (32) 0x9[45][0-9a-f]b
+   "10010101001x1000"    (2) 0x95[23]8
+   "1001010101xx1000"    (4) 0x95[4-7]8
+   "1001010110111000"    (1) 0x95b8
+   "1001010111111000"    (1) 0x95f8 (`espm' removed in databook update)
+   "11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f]
+ */
+
+AVR_INSN (clc,  "",    "1001010010001000", 1, AVR_ISA_1200, 0x9488)
+AVR_INSN (clh,  "",    "1001010011011000", 1, AVR_ISA_1200, 0x94d8)
+AVR_INSN (cli,  "",    "1001010011111000", 1, AVR_ISA_1200, 0x94f8)
+AVR_INSN (cln,  "",    "1001010010101000", 1, AVR_ISA_1200, 0x94a8)
+AVR_INSN (cls,  "",    "1001010011001000", 1, AVR_ISA_1200, 0x94c8)
+AVR_INSN (clt,  "",    "1001010011101000", 1, AVR_ISA_1200, 0x94e8)
+AVR_INSN (clv,  "",    "1001010010111000", 1, AVR_ISA_1200, 0x94b8)
+AVR_INSN (clz,  "",    "1001010010011000", 1, AVR_ISA_1200, 0x9498)
+
+AVR_INSN (sec,  "",    "1001010000001000", 1, AVR_ISA_1200, 0x9408)
+AVR_INSN (seh,  "",    "1001010001011000", 1, AVR_ISA_1200, 0x9458)
+AVR_INSN (sei,  "",    "1001010001111000", 1, AVR_ISA_1200, 0x9478)
+AVR_INSN (sen,  "",    "1001010000101000", 1, AVR_ISA_1200, 0x9428)
+AVR_INSN (ses,  "",    "1001010001001000", 1, AVR_ISA_1200, 0x9448)
+AVR_INSN (set,  "",    "1001010001101000", 1, AVR_ISA_1200, 0x9468)
+AVR_INSN (sev,  "",    "1001010000111000", 1, AVR_ISA_1200, 0x9438)
+AVR_INSN (sez,  "",    "1001010000011000", 1, AVR_ISA_1200, 0x9418)
+
+   /* Same as {cl,se}[chinstvz] above.  */
+AVR_INSN (bclr, "S",   "100101001SSS1000", 1, AVR_ISA_1200, 0x9488)
+AVR_INSN (bset, "S",   "100101000SSS1000", 1, AVR_ISA_1200, 0x9408)
+
+AVR_INSN (icall,"",    "1001010100001001", 1, AVR_ISA_2xxx, 0x9509)
+AVR_INSN (ijmp, "",    "1001010000001001", 1, AVR_ISA_2xxx, 0x9409)
+
+AVR_INSN (lpm,  "?",   "1001010111001000", 1, AVR_ISA_TINY1,0x95c8)
+AVR_INSN (lpm,  "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004)
+AVR_INSN (elpm, "?",   "1001010111011000", 1, AVR_ISA_ELPM, 0x95d8)
+AVR_INSN (elpm, "r,z", "1001000ddddd011+", 1, AVR_ISA_ELPMX,0x9006)
+
+AVR_INSN (nop,  "",    "0000000000000000", 1, AVR_ISA_1200, 0x0000)
+AVR_INSN (ret,  "",    "1001010100001000", 1, AVR_ISA_1200, 0x9508)
+AVR_INSN (reti, "",    "1001010100011000", 1, AVR_ISA_1200, 0x9518)
+AVR_INSN (sleep,"",    "1001010110001000", 1, AVR_ISA_1200, 0x9588)
+AVR_INSN (break,"",    "1001010110011000", 1, AVR_ISA_BRK,  0x9598)
+AVR_INSN (wdr,  "",    "1001010110101000", 1, AVR_ISA_1200, 0x95a8)
+AVR_INSN (spm,  "?",   "1001010111101000", 1, AVR_ISA_SPM,  0x95e8)
+AVR_INSN (spm,  "z",   "10010101111+1000", 1, AVR_ISA_SPMX, 0x95e8)
+
+AVR_INSN (adc,  "r,r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00)
+AVR_INSN (add,  "r,r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
+AVR_INSN (and,  "r,r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000)
+AVR_INSN (cp,   "r,r", "000101rdddddrrrr", 1, AVR_ISA_1200, 0x1400)
+AVR_INSN (cpc,  "r,r", "000001rdddddrrrr", 1, AVR_ISA_1200, 0x0400)
+AVR_INSN (cpse, "r,r", "000100rdddddrrrr", 1, AVR_ISA_1200, 0x1000)
+AVR_INSN (eor,  "r,r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400)
+AVR_INSN (mov,  "r,r", "001011rdddddrrrr", 1, AVR_ISA_1200, 0x2c00)
+AVR_INSN (mul,  "r,r", "100111rdddddrrrr", 1, AVR_ISA_MUL,  0x9c00)
+AVR_INSN (or,   "r,r", "001010rdddddrrrr", 1, AVR_ISA_1200, 0x2800)
+AVR_INSN (sbc,  "r,r", "000010rdddddrrrr", 1, AVR_ISA_1200, 0x0800)
+AVR_INSN (sub,  "r,r", "000110rdddddrrrr", 1, AVR_ISA_1200, 0x1800)
+
+   /* Shorthand for {eor,add,adc,and} r,r above.  */
+AVR_INSN (clr,  "r=r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400)
+AVR_INSN (lsl,  "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
+AVR_INSN (rol,  "r=r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00)
+AVR_INSN (tst,  "r=r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000)
+
+AVR_INSN (andi, "d,M", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000)
+  /*XXX special case*/
+AVR_INSN (cbr,  "d,n", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000)
+
+AVR_INSN (ldi,  "d,M", "1110KKKKddddKKKK", 1, AVR_ISA_1200, 0xe000)
+AVR_INSN (ser,  "d",   "11101111dddd1111", 1, AVR_ISA_1200, 0xef0f)
+
+AVR_INSN (ori,  "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000)
+AVR_INSN (sbr,  "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000)
+
+AVR_INSN (cpi,  "d,M", "0011KKKKddddKKKK", 1, AVR_ISA_1200, 0x3000)
+AVR_INSN (sbci, "d,M", "0100KKKKddddKKKK", 1, AVR_ISA_1200, 0x4000)
+AVR_INSN (subi, "d,M", "0101KKKKddddKKKK", 1, AVR_ISA_1200, 0x5000)
+
+AVR_INSN (sbrc, "r,s", "1111110rrrrr0sss", 1, AVR_ISA_1200, 0xfc00)
+AVR_INSN (sbrs, "r,s", "1111111rrrrr0sss", 1, AVR_ISA_1200, 0xfe00)
+AVR_INSN (bld,  "r,s", "1111100ddddd0sss", 1, AVR_ISA_1200, 0xf800)
+AVR_INSN (bst,  "r,s", "1111101ddddd0sss", 1, AVR_ISA_1200, 0xfa00)
+
+AVR_INSN (in,   "r,P", "10110PPdddddPPPP", 1, AVR_ISA_1200, 0xb000)
+AVR_INSN (out,  "P,r", "10111PPrrrrrPPPP", 1, AVR_ISA_1200, 0xb800)
+
+AVR_INSN (adiw, "w,K", "10010110KKddKKKK", 1, AVR_ISA_2xxx, 0x9600)
+AVR_INSN (sbiw, "w,K", "10010111KKddKKKK", 1, AVR_ISA_2xxx, 0x9700)
+
+AVR_INSN (cbi,  "p,s", "10011000pppppsss", 1, AVR_ISA_1200, 0x9800)
+AVR_INSN (sbi,  "p,s", "10011010pppppsss", 1, AVR_ISA_1200, 0x9a00)
+AVR_INSN (sbic, "p,s", "10011001pppppsss", 1, AVR_ISA_1200, 0x9900)
+AVR_INSN (sbis, "p,s", "10011011pppppsss", 1, AVR_ISA_1200, 0x9b00)
+
+AVR_INSN (brcc, "l",   "111101lllllll000", 1, AVR_ISA_1200, 0xf400)
+AVR_INSN (brcs, "l",   "111100lllllll000", 1, AVR_ISA_1200, 0xf000)
+AVR_INSN (breq, "l",   "111100lllllll001", 1, AVR_ISA_1200, 0xf001)
+AVR_INSN (brge, "l",   "111101lllllll100", 1, AVR_ISA_1200, 0xf404)
+AVR_INSN (brhc, "l",   "111101lllllll101", 1, AVR_ISA_1200, 0xf405)
+AVR_INSN (brhs, "l",   "111100lllllll101", 1, AVR_ISA_1200, 0xf005)
+AVR_INSN (brid, "l",   "111101lllllll111", 1, AVR_ISA_1200, 0xf407)
+AVR_INSN (brie, "l",   "111100lllllll111", 1, AVR_ISA_1200, 0xf007)
+AVR_INSN (brlo, "l",   "111100lllllll000", 1, AVR_ISA_1200, 0xf000)
+AVR_INSN (brlt, "l",   "111100lllllll100", 1, AVR_ISA_1200, 0xf004)
+AVR_INSN (brmi, "l",   "111100lllllll010", 1, AVR_ISA_1200, 0xf002)
+AVR_INSN (brne, "l",   "111101lllllll001", 1, AVR_ISA_1200, 0xf401)
+AVR_INSN (brpl, "l",   "111101lllllll010", 1, AVR_ISA_1200, 0xf402)
+AVR_INSN (brsh, "l",   "111101lllllll000", 1, AVR_ISA_1200, 0xf400)
+AVR_INSN (brtc, "l",   "111101lllllll110", 1, AVR_ISA_1200, 0xf406)
+AVR_INSN (brts, "l",   "111100lllllll110", 1, AVR_ISA_1200, 0xf006)
+AVR_INSN (brvc, "l",   "111101lllllll011", 1, AVR_ISA_1200, 0xf403)
+AVR_INSN (brvs, "l",   "111100lllllll011", 1, AVR_ISA_1200, 0xf003)
+
+   /* Same as br?? above.  */
+AVR_INSN (brbc, "s,l", "111101lllllllsss", 1, AVR_ISA_1200, 0xf400)
+AVR_INSN (brbs, "s,l", "111100lllllllsss", 1, AVR_ISA_1200, 0xf000)
+
+AVR_INSN (rcall, "L",  "1101LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xd000)
+AVR_INSN (rjmp,  "L",  "1100LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xc000)
+
+AVR_INSN (call, "h",   "1001010hhhhh111h", 2, AVR_ISA_MEGA, 0x940e)
+AVR_INSN (jmp,  "h",   "1001010hhhhh110h", 2, AVR_ISA_MEGA, 0x940c)
+
+AVR_INSN (asr,  "r",   "1001010rrrrr0101", 1, AVR_ISA_1200, 0x9405)
+AVR_INSN (com,  "r",   "1001010rrrrr0000", 1, AVR_ISA_1200, 0x9400)
+AVR_INSN (dec,  "r",   "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a)
+AVR_INSN (inc,  "r",   "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403)
+AVR_INSN (lsr,  "r",   "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406)
+AVR_INSN (neg,  "r",   "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401)
+AVR_INSN (pop,  "r",   "1001000rrrrr1111", 1, AVR_ISA_2xxx, 0x900f)
+AVR_INSN (push, "r",   "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f)
+AVR_INSN (ror,  "r",   "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407)
+AVR_INSN (swap, "r",   "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402)
+
+   /* Atomic memory operations for XMEGA.  List before `sts'.  */
+AVR_INSN (xch,  "z,r",   "1001001rrrrr0100", 1, AVR_ISA_RMW, 0x9204)
+AVR_INSN (las,  "z,r",   "1001001rrrrr0101", 1, AVR_ISA_RMW, 0x9205)
+AVR_INSN (lac,  "z,r",   "1001001rrrrr0110", 1, AVR_ISA_RMW, 0x9206)
+AVR_INSN (lat,  "z,r",   "1001001rrrrr0111", 1, AVR_ISA_RMW, 0x9207)
+
+   /* Known to be decoded as `nop' by the old core.  */
+AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100)
+AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL,  0x0200)
+AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL,  0x0300)
+AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL,  0x0308)
+AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL,  0x0380)
+AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL,  0x0388)
+
+AVR_INSN (sts,  "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200)
+AVR_INSN (lds,  "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000)
+
+   /* Special case for b+0, `e' must be next entry after `b',
+      b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X.  */
+AVR_INSN (ldd,  "r,b", "10o0oo0dddddbooo", 1, AVR_ISA_2xxx, 0x8000)
+AVR_INSN (ld,   "r,e", "100!000dddddee-+", 1, AVR_ISA_1200, 0x8000)
+AVR_INSN (std,  "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200)
+AVR_INSN (st,   "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200)
+
+   /* These are for devices that don't exist yet
+      (>128K program memory, PC = EIND:Z).  */
+AVR_INSN (eicall, "",  "1001010100011001", 1, AVR_ISA_EIND, 0x9519)
+AVR_INSN (eijmp, "",   "1001010000011001", 1, AVR_ISA_EIND, 0x9419)
+
+/* DES instruction for encryption and decryption */
+AVR_INSN (des,  "E",   "10010100EEEE1011", 1, AVR_ISA_DES,  0x940B)
+
diff --git a/binutils-2.25/include/opcode/bfin.h b/binutils-2.25/include/opcode/bfin.h
new file mode 100755
index 00000000..26f01938
--- /dev/null
+++ b/binutils-2.25/include/opcode/bfin.h
@@ -0,0 +1,1761 @@
+/* bfin.h -- Header file for ADI Blackfin opcode table
+   Copyright 2005, 2010, 2011 Free Software Foundation, Inc.
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef OPCODE_BFIN_H
+#define OPCODE_BFIN_H
+
+/* Common to all DSP32 instructions.  */
+#define BIT_MULTI_INS 0x0800
+
+/* This just sets the multi instruction bit of a DSP32 instruction.  */
+#define SET_MULTI_INSTRUCTION_BIT(x) x->value |=  BIT_MULTI_INS;
+
+
+/* DSP instructions (32 bit) */
+
+/* mmod field.  */
+#define M_S2RND 1
+#define M_T     2
+#define M_W32   3
+#define M_FU    4
+#define M_TFU   6
+#define M_IS    8
+#define M_ISS2  9
+#define M_IH    11
+#define M_IU    12
+
+static inline int is_macmod_pmove (int x)
+{
+  return (x == 0) || (x == M_IS) || (x == M_FU) || (x == M_S2RND)
+         || (x == M_ISS2) || (x == M_IU);
+}
+
+static inline int is_macmod_hmove (int x)
+{
+  return (x == 0) || (x == M_IS) || (x == M_FU) || (x == M_IU) || (x == M_T)
+         || (x == M_TFU) || (x == M_S2RND) || (x == M_ISS2) || (x == M_IH);
+}
+
+static inline int is_macmod_signed (int x)
+{
+  return (x == 0) || (x == M_IS) || (x == M_T) || (x == M_S2RND)
+         || (x == M_ISS2) || (x == M_IH) || (x == M_W32);
+}
+
+/*   dsp32mac
++----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
+| 1  | 1  | 0 | 0 |.M.| 0  | 0  |.mmod..........|.MM|.P.|.w1|.op1...|
+|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
++----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned long opcode;
+  int bits_src1;
+  int mask_src1;
+  int bits_src0;
+  int mask_src0;
+  int bits_dst;
+  int mask_dst;
+  int bits_h10;
+  int mask_h10;
+  int bits_h00;
+  int mask_h00;
+  int bits_op0;
+  int mask_op0;
+  int bits_w0;
+  int mask_w0;
+  int bits_h11;
+  int mask_h11;
+  int bits_h01;
+  int mask_h01;
+  int bits_op1;
+  int mask_op1;
+  int bits_w1;
+  int mask_w1;
+  int bits_P;
+  int mask_P;
+  int bits_MM;
+  int mask_MM;
+  int bits_mmod;
+  int mask_mmod;
+  int bits_code2;
+  int mask_code2;
+  int bits_M;
+  int mask_M;
+  int bits_code;
+  int mask_code;
+} DSP32Mac;
+
+#define DSP32Mac_opcode			0xc0000000
+#define DSP32Mac_src1_bits		0
+#define DSP32Mac_src1_mask		0x7
+#define DSP32Mac_src0_bits		3
+#define DSP32Mac_src0_mask		0x7
+#define DSP32Mac_dst_bits		6
+#define DSP32Mac_dst_mask		0x7
+#define DSP32Mac_h10_bits		9
+#define DSP32Mac_h10_mask		0x1
+#define DSP32Mac_h00_bits		10
+#define DSP32Mac_h00_mask		0x1
+#define DSP32Mac_op0_bits		11
+#define DSP32Mac_op0_mask		0x3
+#define DSP32Mac_w0_bits		13
+#define DSP32Mac_w0_mask		0x1
+#define DSP32Mac_h11_bits		14
+#define DSP32Mac_h11_mask		0x1
+#define DSP32Mac_h01_bits		15
+#define DSP32Mac_h01_mask		0x1
+#define DSP32Mac_op1_bits		16
+#define DSP32Mac_op1_mask		0x3
+#define DSP32Mac_w1_bits		18
+#define DSP32Mac_w1_mask		0x1
+#define DSP32Mac_p_bits			19
+#define DSP32Mac_p_mask			0x1
+#define DSP32Mac_MM_bits		20
+#define DSP32Mac_MM_mask		0x1
+#define DSP32Mac_mmod_bits		21
+#define DSP32Mac_mmod_mask		0xf
+#define DSP32Mac_code2_bits		25
+#define DSP32Mac_code2_mask		0x3
+#define DSP32Mac_M_bits			27
+#define DSP32Mac_M_mask			0x1
+#define DSP32Mac_code_bits		28
+#define DSP32Mac_code_mask		0xf
+
+#define init_DSP32Mac				\
+{						\
+  DSP32Mac_opcode,				\
+  DSP32Mac_src1_bits,	DSP32Mac_src1_mask,	\
+  DSP32Mac_src0_bits,	DSP32Mac_src0_mask,	\
+  DSP32Mac_dst_bits,	DSP32Mac_dst_mask,	\
+  DSP32Mac_h10_bits,	DSP32Mac_h10_mask,	\
+  DSP32Mac_h00_bits,	DSP32Mac_h00_mask,	\
+  DSP32Mac_op0_bits,	DSP32Mac_op0_mask,	\
+  DSP32Mac_w0_bits,	DSP32Mac_w0_mask,	\
+  DSP32Mac_h11_bits,	DSP32Mac_h11_mask,	\
+  DSP32Mac_h01_bits,	DSP32Mac_h01_mask,	\
+  DSP32Mac_op1_bits,	DSP32Mac_op1_mask,	\
+  DSP32Mac_w1_bits,	DSP32Mac_w1_mask,	\
+  DSP32Mac_p_bits,	DSP32Mac_p_mask,	\
+  DSP32Mac_MM_bits,	DSP32Mac_MM_mask,	\
+  DSP32Mac_mmod_bits,	DSP32Mac_mmod_mask,	\
+  DSP32Mac_code2_bits,	DSP32Mac_code2_mask,	\
+  DSP32Mac_M_bits,	DSP32Mac_M_mask,	\
+  DSP32Mac_code_bits,	DSP32Mac_code_mask	\
+};
+
+/*  dsp32mult
++----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
+| 1  | 1  | 0 | 0 |.M.| 0  | 1  |.mmod..........|.MM|.P.|.w1|.op1...|
+|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
++----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef DSP32Mac DSP32Mult;
+#define DSP32Mult_opcode 	0xc2000000
+
+#define init_DSP32Mult				\
+{						\
+  DSP32Mult_opcode,				\
+  DSP32Mac_src1_bits,	DSP32Mac_src1_mask,	\
+  DSP32Mac_src0_bits,	DSP32Mac_src0_mask,	\
+  DSP32Mac_dst_bits,	DSP32Mac_dst_mask,	\
+  DSP32Mac_h10_bits,	DSP32Mac_h10_mask,	\
+  DSP32Mac_h00_bits,	DSP32Mac_h00_mask,	\
+  DSP32Mac_op0_bits,	DSP32Mac_op0_mask,	\
+  DSP32Mac_w0_bits,	DSP32Mac_w0_mask,	\
+  DSP32Mac_h11_bits,	DSP32Mac_h11_mask,	\
+  DSP32Mac_h01_bits,	DSP32Mac_h01_mask,	\
+  DSP32Mac_op1_bits,	DSP32Mac_op1_mask,	\
+  DSP32Mac_w1_bits,	DSP32Mac_w1_mask,	\
+  DSP32Mac_p_bits,	DSP32Mac_p_mask,	\
+  DSP32Mac_MM_bits,	DSP32Mac_MM_mask,	\
+  DSP32Mac_mmod_bits,	DSP32Mac_mmod_mask,	\
+  DSP32Mac_code2_bits,	DSP32Mac_code2_mask,	\
+  DSP32Mac_M_bits,	DSP32Mac_M_mask,	\
+  DSP32Mac_code_bits,	DSP32Mac_code_mask	\
+};
+
+/*  dsp32alu
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
+|.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned long opcode;
+  int bits_src1;
+  int mask_src1;
+  int bits_src0;
+  int mask_src0;
+  int bits_dst1;
+  int mask_dst1;
+  int bits_dst0;
+  int mask_dst0;
+  int bits_x;
+  int mask_x;
+  int bits_s;
+  int mask_s;
+  int bits_aop;
+  int mask_aop;
+  int bits_aopcde;
+  int mask_aopcde;
+  int bits_HL;
+  int mask_HL;
+  int bits_dontcare;
+  int mask_dontcare;
+  int bits_code2;
+  int mask_code2;
+  int bits_M;
+  int mask_M;
+  int bits_code;
+  int mask_code;
+} DSP32Alu;
+
+#define DSP32Alu_opcode		0xc4000000
+#define DSP32Alu_src1_bits	0
+#define DSP32Alu_src1_mask	0x7
+#define DSP32Alu_src0_bits	3
+#define DSP32Alu_src0_mask	0x7
+#define DSP32Alu_dst1_bits	6
+#define DSP32Alu_dst1_mask	0x7
+#define DSP32Alu_dst0_bits	9
+#define DSP32Alu_dst0_mask	0x7
+#define DSP32Alu_x_bits		12
+#define DSP32Alu_x_mask		0x1
+#define DSP32Alu_s_bits		13
+#define DSP32Alu_s_mask		0x1
+#define DSP32Alu_aop_bits	14
+#define DSP32Alu_aop_mask	0x3
+#define DSP32Alu_aopcde_bits	16
+#define DSP32Alu_aopcde_mask	0x1f
+#define DSP32Alu_HL_bits	21
+#define DSP32Alu_HL_mask	0x1
+#define DSP32Alu_dontcare_bits	22
+#define DSP32Alu_dontcare_mask	0x7
+#define DSP32Alu_code2_bits	25
+#define DSP32Alu_code2_mask	0x3
+#define DSP32Alu_M_bits		27
+#define DSP32Alu_M_mask		0x1
+#define DSP32Alu_code_bits	28
+#define DSP32Alu_code_mask	0xf
+
+#define init_DSP32Alu 					\
+{							\
+  DSP32Alu_opcode,					\
+  DSP32Alu_src1_bits,		DSP32Alu_src1_mask,	\
+  DSP32Alu_src0_bits,		DSP32Alu_src0_mask,	\
+  DSP32Alu_dst1_bits,		DSP32Alu_dst1_mask,	\
+  DSP32Alu_dst0_bits,		DSP32Alu_dst0_mask,	\
+  DSP32Alu_x_bits,		DSP32Alu_x_mask,	\
+  DSP32Alu_s_bits,		DSP32Alu_s_mask,	\
+  DSP32Alu_aop_bits,		DSP32Alu_aop_mask,	\
+  DSP32Alu_aopcde_bits,		DSP32Alu_aopcde_mask,	\
+  DSP32Alu_HL_bits,		DSP32Alu_HL_mask,	\
+  DSP32Alu_dontcare_bits,	DSP32Alu_dontcare_mask,	\
+  DSP32Alu_code2_bits,		DSP32Alu_code2_mask,	\
+  DSP32Alu_M_bits,		DSP32Alu_M_mask,	\
+  DSP32Alu_code_bits,		DSP32Alu_code_mask 	\
+};
+
+/*  dsp32shift
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
+|.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned long opcode;
+  int bits_src1;
+  int mask_src1;
+  int bits_src0;
+  int mask_src0;
+  int bits_dst1;
+  int mask_dst1;
+  int bits_dst0;
+  int mask_dst0;
+  int bits_HLs;
+  int mask_HLs;
+  int bits_sop;
+  int mask_sop;
+  int bits_sopcde;
+  int mask_sopcde;
+  int bits_dontcare;
+  int mask_dontcare;
+  int bits_code2;
+  int mask_code2;
+  int bits_M;
+  int mask_M;
+  int bits_code;
+  int mask_code;
+} DSP32Shift;
+
+#define DSP32Shift_opcode		0xc6000000
+#define DSP32Shift_src1_bits		0
+#define DSP32Shift_src1_mask		0x7
+#define DSP32Shift_src0_bits		3
+#define DSP32Shift_src0_mask		0x7
+#define DSP32Shift_dst1_bits		6
+#define DSP32Shift_dst1_mask		0x7
+#define DSP32Shift_dst0_bits		9
+#define DSP32Shift_dst0_mask		0x7
+#define DSP32Shift_HLs_bits		12
+#define DSP32Shift_HLs_mask		0x3
+#define DSP32Shift_sop_bits		14
+#define DSP32Shift_sop_mask		0x3
+#define DSP32Shift_sopcde_bits		16
+#define DSP32Shift_sopcde_mask		0x1f
+#define DSP32Shift_dontcare_bits	21
+#define DSP32Shift_dontcare_mask	0x3
+#define DSP32Shift_code2_bits		23
+#define DSP32Shift_code2_mask		0xf
+#define DSP32Shift_M_bits		27
+#define DSP32Shift_M_mask		0x1
+#define DSP32Shift_code_bits		28
+#define DSP32Shift_code_mask		0xf
+
+#define init_DSP32Shift						\
+{								\
+  DSP32Shift_opcode,						\
+  DSP32Shift_src1_bits,		DSP32Shift_src1_mask,		\
+  DSP32Shift_src0_bits,		DSP32Shift_src0_mask,		\
+  DSP32Shift_dst1_bits,		DSP32Shift_dst1_mask,		\
+  DSP32Shift_dst0_bits,		DSP32Shift_dst0_mask,		\
+  DSP32Shift_HLs_bits,		DSP32Shift_HLs_mask,		\
+  DSP32Shift_sop_bits,		DSP32Shift_sop_mask,		\
+  DSP32Shift_sopcde_bits,	DSP32Shift_sopcde_mask,		\
+  DSP32Shift_dontcare_bits,	DSP32Shift_dontcare_mask,	\
+  DSP32Shift_code2_bits,	DSP32Shift_code2_mask,		\
+  DSP32Shift_M_bits,		DSP32Shift_M_mask,		\
+  DSP32Shift_code_bits,		DSP32Shift_code_mask		\
+};
+
+/*  dsp32shiftimm
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
+|.sop...|.HLs...|.dst0......|.immag.................|.src1......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned long opcode;
+  int bits_src1;
+  int mask_src1;
+  int bits_immag;
+  int mask_immag;
+  int bits_dst0;
+  int mask_dst0;
+  int bits_HLs;
+  int mask_HLs;
+  int bits_sop;
+  int mask_sop;
+  int bits_sopcde;
+  int mask_sopcde;
+  int bits_dontcare;
+  int mask_dontcare;
+  int bits_code2;
+  int mask_code2;
+  int bits_M;
+  int mask_M;
+  int bits_code;
+  int mask_code;
+} DSP32ShiftImm;
+
+#define DSP32ShiftImm_opcode		0xc6800000
+#define DSP32ShiftImm_src1_bits		0
+#define DSP32ShiftImm_src1_mask		0x7
+#define DSP32ShiftImm_immag_bits	3
+#define DSP32ShiftImm_immag_mask	0x3f
+#define DSP32ShiftImm_dst0_bits		9
+#define DSP32ShiftImm_dst0_mask		0x7
+#define DSP32ShiftImm_HLs_bits		12
+#define DSP32ShiftImm_HLs_mask		0x3
+#define DSP32ShiftImm_sop_bits		14
+#define DSP32ShiftImm_sop_mask		0x3
+#define DSP32ShiftImm_sopcde_bits	16
+#define DSP32ShiftImm_sopcde_mask	0x1f
+#define DSP32ShiftImm_dontcare_bits	21
+#define DSP32ShiftImm_dontcare_mask	0x3
+#define DSP32ShiftImm_code2_bits	23
+#define DSP32ShiftImm_code2_mask	0xf
+#define DSP32ShiftImm_M_bits		27
+#define DSP32ShiftImm_M_mask		0x1
+#define DSP32ShiftImm_code_bits		28
+#define DSP32ShiftImm_code_mask		0xf
+
+#define init_DSP32ShiftImm					\
+{								\
+  DSP32ShiftImm_opcode,						\
+  DSP32ShiftImm_src1_bits,	DSP32ShiftImm_src1_mask,	\
+  DSP32ShiftImm_immag_bits,	DSP32ShiftImm_immag_mask,	\
+  DSP32ShiftImm_dst0_bits,	DSP32ShiftImm_dst0_mask,	\
+  DSP32ShiftImm_HLs_bits,	DSP32ShiftImm_HLs_mask,		\
+  DSP32ShiftImm_sop_bits,	DSP32ShiftImm_sop_mask,		\
+  DSP32ShiftImm_sopcde_bits,	DSP32ShiftImm_sopcde_mask,	\
+  DSP32ShiftImm_dontcare_bits,	DSP32ShiftImm_dontcare_mask,	\
+  DSP32ShiftImm_code2_bits,	DSP32ShiftImm_code2_mask,	\
+  DSP32ShiftImm_M_bits,		DSP32ShiftImm_M_mask,		\
+  DSP32ShiftImm_code_bits,	DSP32ShiftImm_code_mask		\
+};
+
+/* LOAD / STORE  */
+
+/*  LDSTidxI
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
+|.offset........................................................|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned long opcode;
+  int bits_offset;
+  int mask_offset;
+  int bits_reg;
+  int mask_reg;
+  int bits_ptr;
+  int mask_ptr;
+  int bits_sz;
+  int mask_sz;
+  int bits_Z;
+  int mask_Z;
+  int bits_W;
+  int mask_W;
+  int bits_code;
+  int mask_code;
+} LDSTidxI;
+
+#define LDSTidxI_opcode		0xe4000000
+#define LDSTidxI_offset_bits	0
+#define LDSTidxI_offset_mask	0xffff
+#define LDSTidxI_reg_bits	16
+#define LDSTidxI_reg_mask	0x7
+#define LDSTidxI_ptr_bits	19
+#define LDSTidxI_ptr_mask	0x7
+#define LDSTidxI_sz_bits	22
+#define LDSTidxI_sz_mask	0x3
+#define LDSTidxI_Z_bits		24
+#define LDSTidxI_Z_mask		0x1
+#define LDSTidxI_W_bits		25
+#define LDSTidxI_W_mask		0x1
+#define LDSTidxI_code_bits	26
+#define LDSTidxI_code_mask	0x3f
+
+#define init_LDSTidxI				\
+{						\
+  LDSTidxI_opcode,				\
+  LDSTidxI_offset_bits, LDSTidxI_offset_mask,	\
+  LDSTidxI_reg_bits, LDSTidxI_reg_mask,		\
+  LDSTidxI_ptr_bits, LDSTidxI_ptr_mask,		\
+  LDSTidxI_sz_bits, LDSTidxI_sz_mask,		\
+  LDSTidxI_Z_bits, LDSTidxI_Z_mask,		\
+  LDSTidxI_W_bits, LDSTidxI_W_mask,		\
+  LDSTidxI_code_bits, LDSTidxI_code_mask	\
+};
+
+
+/*  LDST
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_reg;
+  int mask_reg;
+  int bits_ptr;
+  int mask_ptr;
+  int bits_Z;
+  int mask_Z;
+  int bits_aop;
+  int mask_aop;
+  int bits_W;
+  int mask_W;
+  int bits_sz;
+  int mask_sz;
+  int bits_code;
+  int mask_code;
+} LDST;
+
+#define LDST_opcode		0x9000
+#define LDST_reg_bits		0
+#define LDST_reg_mask		0x7
+#define LDST_ptr_bits		3
+#define LDST_ptr_mask		0x7
+#define LDST_Z_bits		6
+#define LDST_Z_mask		0x1
+#define LDST_aop_bits		7
+#define LDST_aop_mask		0x3
+#define LDST_W_bits		9
+#define LDST_W_mask		0x1
+#define LDST_sz_bits		10
+#define LDST_sz_mask		0x3
+#define LDST_code_bits		12
+#define LDST_code_mask		0xf
+
+#define init_LDST			\
+{					\
+  LDST_opcode,				\
+  LDST_reg_bits,	LDST_reg_mask,	\
+  LDST_ptr_bits,	LDST_ptr_mask,	\
+  LDST_Z_bits,		LDST_Z_mask,	\
+  LDST_aop_bits,	LDST_aop_mask,	\
+  LDST_W_bits,		LDST_W_mask,	\
+  LDST_sz_bits,		LDST_sz_mask,	\
+  LDST_code_bits,	LDST_code_mask	\
+};
+
+/*  LDSTii
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_reg;
+  int mask_reg;
+  int bits_ptr;
+  int mask_ptr;
+  int bits_offset;
+  int mask_offset;
+  int bits_op;
+  int mask_op;
+  int bits_W;
+  int mask_W;
+  int bits_code;
+  int mask_code;
+} LDSTii;
+
+#define LDSTii_opcode		0xa000
+#define LDSTii_reg_bit		0
+#define LDSTii_reg_mask		0x7
+#define LDSTii_ptr_bit		3
+#define LDSTii_ptr_mask		0x7
+#define LDSTii_offset_bit	6
+#define LDSTii_offset_mask	0xf
+#define LDSTii_op_bit		10
+#define LDSTii_op_mask		0x3
+#define LDSTii_W_bit		12
+#define LDSTii_W_mask		0x1
+#define LDSTii_code_bit		13
+#define LDSTii_code_mask	0x7
+
+#define init_LDSTii 				\
+{						\
+  LDSTii_opcode,				\
+  LDSTii_reg_bit,	LDSTii_reg_mask,	\
+  LDSTii_ptr_bit,	LDSTii_ptr_mask,	\
+  LDSTii_offset_bit,    LDSTii_offset_mask, 	\
+  LDSTii_op_bit,        LDSTii_op_mask,		\
+  LDSTii_W_bit,		LDSTii_W_mask,		\
+  LDSTii_code_bit,	LDSTii_code_mask	\
+};
+
+
+/*  LDSTiiFP
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_reg;
+  int mask_reg;
+  int bits_offset;
+  int mask_offset;
+  int bits_W;
+  int mask_W;
+  int bits_code;
+  int mask_code;
+} LDSTiiFP;
+
+#define LDSTiiFP_opcode		0xb800
+#define LDSTiiFP_reg_bits	0
+#define LDSTiiFP_reg_mask	0xf
+#define LDSTiiFP_offset_bits	4
+#define LDSTiiFP_offset_mask	0x1f
+#define LDSTiiFP_W_bits		9
+#define LDSTiiFP_W_mask		0x1
+#define LDSTiiFP_code_bits	10
+#define LDSTiiFP_code_mask	0x3f
+
+#define init_LDSTiiFP				\
+{						\
+  LDSTiiFP_opcode,				\
+  LDSTiiFP_reg_bits,	LDSTiiFP_reg_mask,	\
+  LDSTiiFP_offset_bits, LDSTiiFP_offset_mask,	\
+  LDSTiiFP_W_bits,	LDSTiiFP_W_mask,	\
+  LDSTiiFP_code_bits,	LDSTiiFP_code_mask	\
+};
+
+/*  dspLDST
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_reg;
+  int mask_reg;
+  int bits_i;
+  int mask_i;
+  int bits_m;
+  int mask_m;
+  int bits_aop;
+  int mask_aop;
+  int bits_W;
+  int mask_W;
+  int bits_code;
+  int mask_code;
+} DspLDST;
+
+#define DspLDST_opcode		0x9c00
+#define DspLDST_reg_bits	0
+#define DspLDST_reg_mask	0x7
+#define DspLDST_i_bits		3
+#define DspLDST_i_mask		0x3
+#define DspLDST_m_bits		5
+#define DspLDST_m_mask		0x3
+#define DspLDST_aop_bits	7
+#define DspLDST_aop_mask	0x3
+#define DspLDST_W_bits		9
+#define DspLDST_W_mask		0x1
+#define DspLDST_code_bits	10
+#define DspLDST_code_mask	0x3f
+
+#define init_DspLDST				\
+{						\
+  DspLDST_opcode,				\
+  DspLDST_reg_bits,	DspLDST_reg_mask,	\
+  DspLDST_i_bits,	DspLDST_i_mask,		\
+  DspLDST_m_bits,	DspLDST_m_mask,		\
+  DspLDST_aop_bits,	DspLDST_aop_mask,	\
+  DspLDST_W_bits,	DspLDST_W_mask,		\
+  DspLDST_code_bits,	DspLDST_code_mask	\
+};
+
+
+/*  LDSTpmod
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_ptr;
+  int mask_ptr;
+  int bits_idx;
+  int mask_idx;
+  int bits_reg;
+  int mask_reg;
+  int bits_aop;
+  int mask_aop;
+  int bits_W;
+  int mask_W;
+  int bits_code;
+  int mask_code;
+} LDSTpmod;
+
+#define LDSTpmod_opcode		0x8000
+#define LDSTpmod_ptr_bits	0
+#define LDSTpmod_ptr_mask	0x7
+#define LDSTpmod_idx_bits	3
+#define LDSTpmod_idx_mask	0x7
+#define LDSTpmod_reg_bits	6
+#define LDSTpmod_reg_mask	0x7
+#define LDSTpmod_aop_bits	9
+#define LDSTpmod_aop_mask	0x3
+#define LDSTpmod_W_bits		11
+#define LDSTpmod_W_mask		0x1
+#define LDSTpmod_code_bits	12
+#define LDSTpmod_code_mask	0xf
+
+#define init_LDSTpmod				\
+{						\
+  LDSTpmod_opcode,				\
+  LDSTpmod_ptr_bits, 	LDSTpmod_ptr_mask,	\
+  LDSTpmod_idx_bits,	LDSTpmod_idx_mask,	\
+  LDSTpmod_reg_bits,	LDSTpmod_reg_mask,	\
+  LDSTpmod_aop_bits,	LDSTpmod_aop_mask,	\
+  LDSTpmod_W_bits,	LDSTpmod_W_mask,	\
+  LDSTpmod_code_bits,	LDSTpmod_code_mask	\
+};
+
+
+/*  LOGI2op
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_dst;
+  int mask_dst;
+  int bits_src;
+  int mask_src;
+  int bits_opc;
+  int mask_opc;
+  int bits_code;
+  int mask_code;
+} LOGI2op;
+
+#define LOGI2op_opcode		0x4800
+#define LOGI2op_dst_bits	0
+#define LOGI2op_dst_mask	0x7
+#define LOGI2op_src_bits	3
+#define LOGI2op_src_mask	0x1f
+#define LOGI2op_opc_bits	8
+#define LOGI2op_opc_mask	0x7
+#define LOGI2op_code_bits	11
+#define LOGI2op_code_mask	0x1f
+
+#define init_LOGI2op				\
+{						\
+  LOGI2op_opcode,				\
+  LOGI2op_dst_bits, 	LOGI2op_dst_mask,	\
+  LOGI2op_src_bits,	LOGI2op_src_mask,	\
+  LOGI2op_opc_bits,	LOGI2op_opc_mask,	\
+  LOGI2op_code_bits,	LOGI2op_code_mask	\
+};
+
+
+/*  ALU2op
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_dst;
+  int mask_dst;
+  int bits_src;
+  int mask_src;
+  int bits_opc;
+  int mask_opc;
+  int bits_code;
+  int mask_code;
+} ALU2op;
+
+#define ALU2op_opcode 		0x4000
+#define ALU2op_dst_bits		0
+#define ALU2op_dst_mask		0x7
+#define ALU2op_src_bits		3
+#define ALU2op_src_mask		0x7
+#define ALU2op_opc_bits		6
+#define ALU2op_opc_mask		0xf
+#define ALU2op_code_bits	10
+#define ALU2op_code_mask	0x3f
+
+#define init_ALU2op				\
+{						\
+  ALU2op_opcode,				\
+  ALU2op_dst_bits,	ALU2op_dst_mask,	\
+  ALU2op_src_bits,	ALU2op_src_mask,	\
+  ALU2op_opc_bits,	ALU2op_opc_mask,	\
+  ALU2op_code_bits,	ALU2op_code_mask	\
+};
+
+
+/*  BRCC
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_offset;
+  int mask_offset;
+  int bits_B;
+  int mask_B;
+  int bits_T;
+  int mask_T;
+  int bits_code;
+  int mask_code;
+} BRCC;
+
+#define BRCC_opcode		0x1000
+#define BRCC_offset_bits	0
+#define BRCC_offset_mask	0x3ff
+#define BRCC_B_bits		10
+#define BRCC_B_mask		0x1
+#define BRCC_T_bits		11
+#define BRCC_T_mask		0x1
+#define BRCC_code_bits		12
+#define BRCC_code_mask		0xf
+
+#define init_BRCC				\
+{						\
+  BRCC_opcode,					\
+  BRCC_offset_bits,	BRCC_offset_mask,	\
+  BRCC_B_bits,		BRCC_B_mask,		\
+  BRCC_T_bits,		BRCC_T_mask,		\
+  BRCC_code_bits,	BRCC_code_mask		\
+};
+
+
+/*  UJUMP
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 0 | 1 | 0 |.offset........................................|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_offset;
+  int mask_offset;
+  int bits_code;
+  int mask_code;
+} UJump;
+
+#define UJump_opcode		0x2000
+#define UJump_offset_bits	0
+#define UJump_offset_mask	0xfff
+#define UJump_code_bits		12
+#define UJump_code_mask		0xf
+
+#define init_UJump				\
+{						\
+  UJump_opcode,					\
+  UJump_offset_bits,	UJump_offset_mask,	\
+  UJump_code_bits,	UJump_code_mask		\
+};
+
+
+/*  ProgCtrl
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_poprnd;
+  int mask_poprnd;
+  int bits_prgfunc;
+  int mask_prgfunc;
+  int bits_code;
+  int mask_code;
+} ProgCtrl;
+
+#define ProgCtrl_opcode		0x0000
+#define ProgCtrl_poprnd_bits	0
+#define ProgCtrl_poprnd_mask	0xf
+#define ProgCtrl_prgfunc_bits	4
+#define ProgCtrl_prgfunc_mask	0xf
+#define ProgCtrl_code_bits	8
+#define ProgCtrl_code_mask	0xff
+
+#define init_ProgCtrl					\
+{							\
+  ProgCtrl_opcode,					\
+  ProgCtrl_poprnd_bits,		ProgCtrl_poprnd_mask,	\
+  ProgCtrl_prgfunc_bits,	ProgCtrl_prgfunc_mask,	\
+  ProgCtrl_code_bits,		ProgCtrl_code_mask	\
+};
+
+/*  CALLa
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
+|.lsw...........................................................|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+
+typedef struct
+{
+  unsigned long opcode;
+  int bits_addr;
+  int mask_addr;
+  int bits_S;
+  int mask_S;
+  int bits_code;
+  int mask_code;
+} CALLa;
+
+#define CALLa_opcode	0xe2000000
+#define CALLa_addr_bits	0
+#define CALLa_addr_mask	0xffffff
+#define CALLa_S_bits	24
+#define CALLa_S_mask	0x1
+#define CALLa_code_bits	25
+#define CALLa_code_mask	0x7f
+
+#define init_CALLa				\
+{						\
+  CALLa_opcode,					\
+  CALLa_addr_bits,	CALLa_addr_mask,	\
+  CALLa_S_bits,		CALLa_S_mask,		\
+  CALLa_code_bits,	CALLa_code_mask		\
+};
+
+
+/*  pseudoDEBUG
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_reg;
+  int mask_reg;
+  int bits_grp;
+  int mask_grp;
+  int bits_fn;
+  int mask_fn;
+  int bits_code;
+  int mask_code;
+} PseudoDbg;
+
+#define PseudoDbg_opcode	0xf800
+#define PseudoDbg_reg_bits	0
+#define PseudoDbg_reg_mask	0x7
+#define PseudoDbg_grp_bits	3
+#define PseudoDbg_grp_mask	0x7
+#define PseudoDbg_fn_bits	6
+#define PseudoDbg_fn_mask	0x3
+#define PseudoDbg_code_bits	8
+#define PseudoDbg_code_mask	0xff
+
+#define init_PseudoDbg				\
+{						\
+  PseudoDbg_opcode,				\
+  PseudoDbg_reg_bits,	PseudoDbg_reg_mask,	\
+  PseudoDbg_grp_bits,	PseudoDbg_grp_mask,	\
+  PseudoDbg_fn_bits,	PseudoDbg_fn_mask,	\
+  PseudoDbg_code_bits,	PseudoDbg_code_mask	\
+};
+
+/*  PseudoDbg_assert
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
+|.expected......................................................|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned long opcode;
+  int bits_expected;
+  int mask_expected;
+  int bits_regtest;
+  int mask_regtest;
+  int bits_grp;
+  int mask_grp;
+  int bits_dbgop;
+  int mask_dbgop;
+  int bits_dontcare;
+  int mask_dontcare;
+  int bits_code;
+  int mask_code;
+} PseudoDbg_Assert;
+
+#define PseudoDbg_Assert_opcode		0xf0000000
+#define PseudoDbg_Assert_expected_bits	0
+#define PseudoDbg_Assert_expected_mask	0xffff
+#define PseudoDbg_Assert_regtest_bits	16
+#define PseudoDbg_Assert_regtest_mask	0x7
+#define PseudoDbg_Assert_grp_bits	19
+#define PseudoDbg_Assert_grp_mask	0x7
+#define PseudoDbg_Assert_dbgop_bits	22
+#define PseudoDbg_Assert_dbgop_mask	0x3
+#define PseudoDbg_Assert_dontcare_bits	24
+#define PseudoDbg_Assert_dontcare_mask	0x7
+#define PseudoDbg_Assert_code_bits	27
+#define PseudoDbg_Assert_code_mask	0x1f
+
+#define init_PseudoDbg_Assert						\
+{									\
+  PseudoDbg_Assert_opcode,						\
+  PseudoDbg_Assert_expected_bits, 	PseudoDbg_Assert_expected_mask,	\
+  PseudoDbg_Assert_regtest_bits, 	PseudoDbg_Assert_regtest_mask,	\
+  PseudoDbg_Assert_grp_bits,		PseudoDbg_Assert_grp_mask,	\
+  PseudoDbg_Assert_dbgop_bits, 		PseudoDbg_Assert_dbgop_mask,	\
+  PseudoDbg_Assert_dontcare_bits, 	PseudoDbg_Assert_dontcare_mask,	\
+  PseudoDbg_Assert_code_bits,	 	PseudoDbg_Assert_code_mask	\
+};
+
+/*  pseudoChr
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_ch;
+  int mask_ch;
+  int bits_code;
+  int mask_code;
+} PseudoChr;
+
+#define PseudoChr_opcode	0xf900
+#define PseudoChr_ch_bits	0
+#define PseudoChr_ch_mask	0xff
+#define PseudoChr_code_bits	8
+#define PseudoChr_code_mask	0xff
+
+#define init_PseudoChr				\
+{						\
+  PseudoChr_opcode,				\
+  PseudoChr_ch_bits,	PseudoChr_ch_mask,	\
+  PseudoChr_code_bits,	PseudoChr_code_mask	\
+};
+
+/*  CaCTRL
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_reg;
+  int mask_reg;
+  int bits_op;
+  int mask_op;
+  int bits_a;
+  int mask_a;
+  int bits_code;
+  int mask_code;
+} CaCTRL;
+
+#define CaCTRL_opcode		0x0240
+#define CaCTRL_reg_bits		0
+#define CaCTRL_reg_mask		0x7
+#define CaCTRL_op_bits		3
+#define CaCTRL_op_mask		0x3
+#define CaCTRL_a_bits		5
+#define CaCTRL_a_mask		0x1
+#define CaCTRL_code_bits	6
+#define CaCTRL_code_mask	0x3fff
+
+#define init_CaCTRL				\
+{						\
+  CaCTRL_opcode,				\
+  CaCTRL_reg_bits,	CaCTRL_reg_mask,	\
+  CaCTRL_op_bits,	CaCTRL_op_mask,		\
+  CaCTRL_a_bits,	CaCTRL_a_mask,		\
+  CaCTRL_code_bits,	CaCTRL_code_mask	\
+};
+
+/*  PushPopMultiple
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_pr;
+  int mask_pr;
+  int bits_dr;
+  int mask_dr;
+  int bits_W;
+  int mask_W;
+  int bits_p;
+  int mask_p;
+  int bits_d;
+  int mask_d;
+  int bits_code;
+  int mask_code;
+} PushPopMultiple;
+
+#define PushPopMultiple_opcode		0x0400
+#define PushPopMultiple_pr_bits		0
+#define PushPopMultiple_pr_mask		0x7
+#define PushPopMultiple_dr_bits		3
+#define PushPopMultiple_dr_mask		0x7
+#define PushPopMultiple_W_bits		6
+#define PushPopMultiple_W_mask		0x1
+#define PushPopMultiple_p_bits		7
+#define PushPopMultiple_p_mask		0x1
+#define PushPopMultiple_d_bits		8
+#define PushPopMultiple_d_mask		0x1
+#define PushPopMultiple_code_bits	8
+#define PushPopMultiple_code_mask	0x1
+
+#define init_PushPopMultiple					\
+{								\
+  PushPopMultiple_opcode,					\
+  PushPopMultiple_pr_bits,	PushPopMultiple_pr_mask,	\
+  PushPopMultiple_dr_bits,	PushPopMultiple_dr_mask,	\
+  PushPopMultiple_W_bits,	PushPopMultiple_W_mask,		\
+  PushPopMultiple_p_bits,	PushPopMultiple_p_mask,		\
+  PushPopMultiple_d_bits,	PushPopMultiple_d_mask,		\
+  PushPopMultiple_code_bits,	PushPopMultiple_code_mask	\
+};
+
+/*  PushPopReg
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_reg;
+  int mask_reg;
+  int bits_grp;
+  int mask_grp;
+  int bits_W;
+  int mask_W;
+  int bits_code;
+  int mask_code;
+} PushPopReg;
+
+#define PushPopReg_opcode	0x0100
+#define PushPopReg_reg_bits	0
+#define PushPopReg_reg_mask	0x7
+#define PushPopReg_grp_bits	3
+#define PushPopReg_grp_mask	0x7
+#define PushPopReg_W_bits	6
+#define PushPopReg_W_mask	0x1
+#define PushPopReg_code_bits	7
+#define PushPopReg_code_mask	0x1ff
+
+#define init_PushPopReg				\
+{						\
+  PushPopReg_opcode,				\
+  PushPopReg_reg_bits,	PushPopReg_reg_mask,	\
+  PushPopReg_grp_bits,	PushPopReg_grp_mask,	\
+  PushPopReg_W_bits,	PushPopReg_W_mask,	\
+  PushPopReg_code_bits,	PushPopReg_code_mask,	\
+};
+
+/*  linkage
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
+|.framesize.....................................................|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned long opcode;
+  int bits_framesize;
+  int mask_framesize;
+  int bits_R;
+  int mask_R;
+  int bits_code;
+  int mask_code;
+} Linkage;
+
+#define Linkage_opcode		0xe8000000
+#define Linkage_framesize_bits	0
+#define Linkage_framesize_mask	0xffff
+#define Linkage_R_bits		16
+#define Linkage_R_mask		0x1
+#define Linkage_code_bits	17
+#define Linkage_code_mask	0x7fff
+
+#define init_Linkage					\
+{							\
+  Linkage_opcode,					\
+  Linkage_framesize_bits,	Linkage_framesize_mask,	\
+  Linkage_R_bits,		Linkage_R_mask,		\
+  Linkage_code_bits,		Linkage_code_mask	\
+};
+
+/*  LoopSetup
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
+|.reg...........| - | - |.eoffset...............................|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned long opcode;
+  int bits_eoffset;
+  int mask_eoffset;
+  int bits_dontcare;
+  int mask_dontcare;
+  int bits_reg;
+  int mask_reg;
+  int bits_soffset;
+  int mask_soffset;
+  int bits_c;
+  int mask_c;
+  int bits_rop;
+  int mask_rop;
+  int bits_code;
+  int mask_code;
+} LoopSetup;
+
+#define LoopSetup_opcode		0xe0800000
+#define LoopSetup_eoffset_bits		0
+#define LoopSetup_eoffset_mask		0x3ff
+#define LoopSetup_dontcare_bits		10
+#define LoopSetup_dontcare_mask		0x3
+#define LoopSetup_reg_bits		12
+#define LoopSetup_reg_mask		0xf
+#define LoopSetup_soffset_bits		16
+#define LoopSetup_soffset_mask		0xf
+#define LoopSetup_c_bits		20
+#define LoopSetup_c_mask		0x1
+#define LoopSetup_rop_bits		21
+#define LoopSetup_rop_mask		0x3
+#define LoopSetup_code_bits		23
+#define LoopSetup_code_mask		0x1ff
+
+#define init_LoopSetup						\
+{								\
+  LoopSetup_opcode,						\
+  LoopSetup_eoffset_bits,	LoopSetup_eoffset_mask,		\
+  LoopSetup_dontcare_bits,	LoopSetup_dontcare_mask,	\
+  LoopSetup_reg_bits,		LoopSetup_reg_mask,		\
+  LoopSetup_soffset_bits,	LoopSetup_soffset_mask,		\
+  LoopSetup_c_bits,		LoopSetup_c_mask,		\
+  LoopSetup_rop_bits,		LoopSetup_rop_mask,		\
+  LoopSetup_code_bits,		LoopSetup_code_mask		\
+};
+
+/*  LDIMMhalf
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
+|.hword.........................................................|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned long opcode;
+  int bits_hword;
+  int mask_hword;
+  int bits_reg;
+  int mask_reg;
+  int bits_grp;
+  int mask_grp;
+  int bits_S;
+  int mask_S;
+  int bits_H;
+  int mask_H;
+  int bits_Z;
+  int mask_Z;
+  int bits_code;
+  int mask_code;
+} LDIMMhalf;
+
+#define LDIMMhalf_opcode	0xe1000000
+#define LDIMMhalf_hword_bits	0
+#define LDIMMhalf_hword_mask	0xffff
+#define LDIMMhalf_reg_bits	16
+#define LDIMMhalf_reg_mask	0x7
+#define LDIMMhalf_grp_bits	19
+#define LDIMMhalf_grp_mask	0x3
+#define LDIMMhalf_S_bits	21
+#define LDIMMhalf_S_mask	0x1
+#define LDIMMhalf_H_bits	22
+#define LDIMMhalf_H_mask	0x1
+#define LDIMMhalf_Z_bits	23
+#define LDIMMhalf_Z_mask	0x1
+#define LDIMMhalf_code_bits	24
+#define LDIMMhalf_code_mask	0xff
+
+#define init_LDIMMhalf				\
+{						\
+  LDIMMhalf_opcode,				\
+  LDIMMhalf_hword_bits,	LDIMMhalf_hword_mask,	\
+  LDIMMhalf_reg_bits,	LDIMMhalf_reg_mask,	\
+  LDIMMhalf_grp_bits,	LDIMMhalf_grp_mask,	\
+  LDIMMhalf_S_bits,	LDIMMhalf_S_mask,	\
+  LDIMMhalf_H_bits,	LDIMMhalf_H_mask,	\
+  LDIMMhalf_Z_bits,	LDIMMhalf_Z_mask,	\
+  LDIMMhalf_code_bits,	LDIMMhalf_code_mask	\
+};
+
+
+/*  CC2dreg
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_reg;
+  int mask_reg;
+  int bits_op;
+  int mask_op;
+  int bits_code;
+  int mask_code;
+} CC2dreg;
+
+#define CC2dreg_opcode		0x0200
+#define CC2dreg_reg_bits	0
+#define CC2dreg_reg_mask	0x7
+#define CC2dreg_op_bits		3
+#define CC2dreg_op_mask		0x3
+#define CC2dreg_code_bits	5
+#define CC2dreg_code_mask	0x7fff
+
+#define init_CC2dreg				\
+{						\
+  CC2dreg_opcode,				\
+  CC2dreg_reg_bits,	CC2dreg_reg_mask,	\
+  CC2dreg_op_bits,	CC2dreg_op_mask,	\
+  CC2dreg_code_bits,	CC2dreg_code_mask	\
+};
+
+
+/*  PTR2op
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_dst;
+  int mask_dst;
+  int bits_src;
+  int mask_src;
+  int bits_opc;
+  int mask_opc;
+  int bits_code;
+  int mask_code;
+} PTR2op;
+
+#define PTR2op_opcode		0x4400
+#define PTR2op_dst_bits		0
+#define PTR2op_dst_mask		0x7
+#define PTR2op_src_bits		3
+#define PTR2op_src_mask		0x7
+#define PTR2op_opc_bits		6
+#define PTR2op_opc_mask		0x7
+#define PTR2op_code_bits	9
+#define PTR2op_code_mask	0x7f
+
+#define init_PTR2op				\
+{						\
+  PTR2op_opcode,				\
+  PTR2op_dst_bits,	PTR2op_dst_mask,	\
+  PTR2op_src_bits,	PTR2op_src_mask,	\
+  PTR2op_opc_bits,	PTR2op_opc_mask,	\
+  PTR2op_code_bits,	PTR2op_code_mask	\
+};
+
+
+/*  COMP3op
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_src0;
+  int mask_src0;
+  int bits_src1;
+  int mask_src1;
+  int bits_dst;
+  int mask_dst;
+  int bits_opc;
+  int mask_opc;
+  int bits_code;
+  int mask_code;
+} COMP3op;
+
+#define COMP3op_opcode		0x5000
+#define COMP3op_src0_bits	0
+#define COMP3op_src0_mask	0x7
+#define COMP3op_src1_bits	3
+#define COMP3op_src1_mask	0x7
+#define COMP3op_dst_bits	6
+#define COMP3op_dst_mask	0x7
+#define COMP3op_opc_bits	9
+#define COMP3op_opc_mask	0x7
+#define COMP3op_code_bits	12
+#define COMP3op_code_mask	0xf
+
+#define init_COMP3op				\
+{						\
+  COMP3op_opcode,				\
+  COMP3op_src0_bits,	COMP3op_src0_mask,	\
+  COMP3op_src1_bits,	COMP3op_src1_mask,	\
+  COMP3op_dst_bits,	COMP3op_dst_mask,	\
+  COMP3op_opc_bits,	COMP3op_opc_mask,	\
+  COMP3op_code_bits,	COMP3op_code_mask	\
+};
+
+/*  ccMV
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_src;
+  int mask_src;
+  int bits_dst;
+  int mask_dst;
+  int bits_s;
+  int mask_s;
+  int bits_d;
+  int mask_d;
+  int bits_T;
+  int mask_T;
+  int bits_code;
+  int mask_code;
+} CCmv;
+
+#define CCmv_opcode	0x0600
+#define CCmv_src_bits	0
+#define CCmv_src_mask	0x7
+#define CCmv_dst_bits	3
+#define CCmv_dst_mask	0x7
+#define CCmv_s_bits	6
+#define CCmv_s_mask	0x1
+#define CCmv_d_bits	7
+#define CCmv_d_mask	0x1
+#define CCmv_T_bits	8
+#define CCmv_T_mask	0x1
+#define CCmv_code_bits	9
+#define CCmv_code_mask	0x7f
+
+#define init_CCmv			\
+{					\
+  CCmv_opcode,				\
+  CCmv_src_bits,	CCmv_src_mask,	\
+  CCmv_dst_bits,	CCmv_dst_mask,	\
+  CCmv_s_bits,		CCmv_s_mask,	\
+  CCmv_d_bits,		CCmv_d_mask,	\
+  CCmv_T_bits,		CCmv_T_mask,	\
+  CCmv_code_bits,	CCmv_code_mask	\
+};
+
+
+/*  CCflag
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_x;
+  int mask_x;
+  int bits_y;
+  int mask_y;
+  int bits_G;
+  int mask_G;
+  int bits_opc;
+  int mask_opc;
+  int bits_I;
+  int mask_I;
+  int bits_code;
+  int mask_code;
+} CCflag;
+
+#define CCflag_opcode		0x0800
+#define CCflag_x_bits		0
+#define CCflag_x_mask		0x7
+#define CCflag_y_bits		3
+#define CCflag_y_mask		0x7
+#define CCflag_G_bits		6
+#define CCflag_G_mask		0x1
+#define CCflag_opc_bits		7
+#define CCflag_opc_mask		0x7
+#define CCflag_I_bits		10
+#define CCflag_I_mask		0x1
+#define CCflag_code_bits	11
+#define CCflag_code_mask	0x1f
+
+#define init_CCflag				\
+{						\
+  CCflag_opcode,				\
+  CCflag_x_bits,	CCflag_x_mask,		\
+  CCflag_y_bits,	CCflag_y_mask,		\
+  CCflag_G_bits,	CCflag_G_mask,		\
+  CCflag_opc_bits,	CCflag_opc_mask,	\
+  CCflag_I_bits,	CCflag_I_mask,		\
+  CCflag_code_bits,	CCflag_code_mask,	\
+};
+
+
+/*  CC2stat
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_cbit;
+  int mask_cbit;
+  int bits_op;
+  int mask_op;
+  int bits_D;
+  int mask_D;
+  int bits_code;
+  int mask_code;
+} CC2stat;
+
+#define CC2stat_opcode		0x0300
+#define CC2stat_cbit_bits	0
+#define CC2stat_cbit_mask	0x1f
+#define CC2stat_op_bits		5
+#define CC2stat_op_mask		0x3
+#define CC2stat_D_bits		7
+#define CC2stat_D_mask		0x1
+#define CC2stat_code_bits	8
+#define CC2stat_code_mask	0xff
+
+#define init_CC2stat				\
+{						\
+  CC2stat_opcode,				\
+  CC2stat_cbit_bits,	CC2stat_cbit_mask,	\
+  CC2stat_op_bits,	CC2stat_op_mask,	\
+  CC2stat_D_bits,	CC2stat_D_mask,		\
+  CC2stat_code_bits,	CC2stat_code_mask	\
+};
+
+
+/*  REGMV
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_src;
+  int mask_src;
+  int bits_dst;
+  int mask_dst;
+  int bits_gs;
+  int mask_gs;
+  int bits_gd;
+  int mask_gd;
+  int bits_code;
+  int mask_code;
+} RegMv;
+
+#define RegMv_opcode		0x3000
+#define RegMv_src_bits		0
+#define RegMv_src_mask		0x7
+#define RegMv_dst_bits		3
+#define RegMv_dst_mask		0x7
+#define RegMv_gs_bits		6
+#define RegMv_gs_mask		0x7
+#define RegMv_gd_bits		9
+#define RegMv_gd_mask		0x7
+#define RegMv_code_bits		12
+#define RegMv_code_mask		0xf
+
+#define init_RegMv			\
+{					\
+  RegMv_opcode,				\
+  RegMv_src_bits,	RegMv_src_mask,	\
+  RegMv_dst_bits,	RegMv_dst_mask,	\
+  RegMv_gs_bits,	RegMv_gs_mask,	\
+  RegMv_gd_bits,	RegMv_gd_mask,	\
+  RegMv_code_bits,	RegMv_code_mask	\
+};
+
+
+/*  COMPI2opD
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 1 | 1 | 0 | 0 |.op|.isrc......................|.dst.......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_dst;
+  int mask_dst;
+  int bits_src;
+  int mask_src;
+  int bits_op;
+  int mask_op;
+  int bits_code;
+  int mask_code;
+} COMPI2opD;
+
+#define COMPI2opD_opcode	0x6000
+#define COMPI2opD_dst_bits	0
+#define COMPI2opD_dst_mask	0x7
+#define COMPI2opD_src_bits	3
+#define COMPI2opD_src_mask	0x7f
+#define COMPI2opD_op_bits	10
+#define COMPI2opD_op_mask	0x1
+#define COMPI2opD_code_bits	11
+#define COMPI2opD_code_mask	0x1f
+
+#define init_COMPI2opD				\
+{						\
+  COMPI2opD_opcode,				\
+  COMPI2opD_dst_bits,	COMPI2opD_dst_mask,	\
+  COMPI2opD_src_bits,	COMPI2opD_src_mask,	\
+  COMPI2opD_op_bits,	COMPI2opD_op_mask,	\
+  COMPI2opD_code_bits,	COMPI2opD_code_mask	\
+};
+
+/*  COMPI2opP
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef COMPI2opD COMPI2opP;
+
+#define COMPI2opP_opcode 	0x6800
+#define COMPI2opP_dst_bits	0
+#define COMPI2opP_dst_mask	0x7
+#define COMPI2opP_src_bits	3
+#define COMPI2opP_src_mask	0x7f
+#define COMPI2opP_op_bits	10
+#define COMPI2opP_op_mask	0x1
+#define COMPI2opP_code_bits	11
+#define COMPI2opP_code_mask	0x1f
+
+#define init_COMPI2opP				\
+{						\
+  COMPI2opP_opcode,				\
+  COMPI2opP_dst_bits,	COMPI2opP_dst_mask,	\
+  COMPI2opP_src_bits,	COMPI2opP_src_mask,	\
+  COMPI2opP_op_bits,	COMPI2opP_op_mask,	\
+  COMPI2opP_code_bits,	COMPI2opP_code_mask	\
+};
+
+
+/*  dagMODim
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_i;
+  int mask_i;
+  int bits_m;
+  int mask_m;
+  int bits_op;
+  int mask_op;
+  int bits_code2;
+  int mask_code2;
+  int bits_br;
+  int mask_br;
+  int bits_code;
+  int mask_code;
+} DagMODim;
+
+#define DagMODim_opcode		0x9e60
+#define DagMODim_i_bits		0
+#define DagMODim_i_mask		0x3
+#define DagMODim_m_bits		2
+#define DagMODim_m_mask		0x3
+#define DagMODim_op_bits	4
+#define DagMODim_op_mask	0x1
+#define DagMODim_code2_bits	5
+#define DagMODim_code2_mask	0x3
+#define DagMODim_br_bits	7
+#define DagMODim_br_mask	0x1
+#define DagMODim_code_bits	8
+#define DagMODim_code_mask	0xff
+
+#define init_DagMODim				\
+{						\
+  DagMODim_opcode,				\
+  DagMODim_i_bits,	DagMODim_i_mask,	\
+  DagMODim_m_bits,	DagMODim_m_mask,	\
+  DagMODim_op_bits,	DagMODim_op_mask,	\
+  DagMODim_code2_bits,	DagMODim_code2_mask,	\
+  DagMODim_br_bits,	DagMODim_br_mask,	\
+  DagMODim_code_bits,	DagMODim_code_mask	\
+};
+
+/*  dagMODik
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
++---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
+*/
+
+typedef struct
+{
+  unsigned short opcode;
+  int bits_i;
+  int mask_i;
+  int bits_op;
+  int mask_op;
+  int bits_code;
+  int mask_code;
+} DagMODik;
+
+#define DagMODik_opcode		0x9f60
+#define DagMODik_i_bits		0
+#define DagMODik_i_mask		0x3
+#define DagMODik_op_bits	2
+#define DagMODik_op_mask	0x3
+#define DagMODik_code_bits	3
+#define DagMODik_code_mask	0xfff
+
+#define init_DagMODik				\
+{						\
+  DagMODik_opcode,				\
+  DagMODik_i_bits,	DagMODik_i_mask,	\
+  DagMODik_op_bits,	DagMODik_op_mask,	\
+  DagMODik_code_bits,	DagMODik_code_mask	\
+};
+
+#endif
diff --git a/binutils-2.25/include/opcode/cgen.h b/binutils-2.25/include/opcode/cgen.h
new file mode 100644
index 00000000..b7e82d4d
--- /dev/null
+++ b/binutils-2.25/include/opcode/cgen.h
@@ -0,0 +1,1480 @@
+/* Header file for targets using CGEN: Cpu tools GENerator.
+
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2009, 2010
+   Free Software Foundation, Inc.
+
+   This file is part of GDB, the GNU debugger, and the GNU Binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef OPCODE_CGEN_H
+#define OPCODE_CGEN_H
+
+#include "symcat.h"
+#include "cgen/bitset.h"
+
+/* ??? IWBN to replace bfd in the name.  */
+#include "bfd_stdint.h"
+
+/* ??? This file requires bfd.h but only to get bfd_vma.
+   Seems like an awful lot to require just to get such a fundamental type.
+   Perhaps the definition of bfd_vma can be moved outside of bfd.h.
+   Or perhaps one could duplicate its definition in another file.
+   Until such time, this file conditionally compiles definitions that require
+   bfd_vma using __BFD_H_SEEN__.  */
+
+/* Enums must be defined before they can be used.
+   Allow them to be used in struct definitions, even though the enum must
+   be defined elsewhere.
+   If CGEN_ARCH isn't defined, this file is being included by something other
+   than <arch>-desc.h.  */
+
+/* Prepend the arch name, defined in <arch>-desc.h, and _cgen_ to symbol S.
+   The lack of spaces in the arg list is important for non-stdc systems.
+   This file is included by <arch>-desc.h.
+   It can be included independently of <arch>-desc.h, in which case the arch
+   dependent portions will be declared as "unknown_cgen_foo".  */
+
+#ifndef CGEN_SYM
+#define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s)
+#endif
+
+/* This file contains the static (unchanging) pieces and as much other stuff
+   as we can reasonably put here.  It's generally cleaner to put stuff here
+   rather than having it machine generated if possible.  */
+
+/* The assembler syntax is made up of expressions (duh...).
+   At the lowest level the values are mnemonics, register names, numbers, etc.
+   Above that are subexpressions, if any (an example might be the
+   "effective address" in m68k cpus).  Subexpressions are wip.
+   At the second highest level are the insns themselves.  Above that are
+   pseudo-insns, synthetic insns, and macros, if any.  */
+
+/* Lots of cpu's have a fixed insn size, or one which rarely changes,
+   and it's generally easier to handle these by treating the insn as an
+   integer type, rather than an array of characters.  So we allow targets
+   to control this.  When an integer type the value is in host byte order,
+   when an array of characters the value is in target byte order.  */
+
+typedef unsigned int CGEN_INSN_INT;
+typedef int64_t CGEN_INSN_LGSINT; /* large/long SINT */
+typedef uint64_t CGEN_INSN_LGUINT; /* large/long UINT */
+
+#if CGEN_INT_INSN_P
+typedef CGEN_INSN_INT CGEN_INSN_BYTES;
+typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR;
+#else
+typedef unsigned char *CGEN_INSN_BYTES;
+typedef unsigned char *CGEN_INSN_BYTES_PTR;
+#endif
+
+#ifdef __GNUC__
+#define CGEN_INLINE __inline__
+#else
+#define CGEN_INLINE
+#endif
+
+enum cgen_endian
+{
+  CGEN_ENDIAN_UNKNOWN,
+  CGEN_ENDIAN_LITTLE,
+  CGEN_ENDIAN_BIG
+};
+
+/* Forward decl.  */
+
+typedef struct cgen_insn CGEN_INSN;
+
+/* Opaque pointer version for use by external world.  */
+
+typedef struct cgen_cpu_desc *CGEN_CPU_DESC;
+
+/* Attributes.
+   Attributes are used to describe various random things associated with
+   an object (ifield, hardware, operand, insn, whatever) and are specified
+   as name/value pairs.
+   Integer attributes computed at compile time are currently all that's
+   supported, though adding string attributes and run-time computation is
+   straightforward.  Integer attribute values are always host int's
+   (signed or unsigned).  For portability, this means 32 bits.
+   Integer attributes are further categorized as boolean, bitset, integer,
+   and enum types.  Boolean attributes appear frequently enough that they're
+   recorded in one host int.  This limits the maximum number of boolean
+   attributes to 32, though that's a *lot* of attributes.  */
+
+/* Type of attribute values.  */
+
+typedef CGEN_BITSET     CGEN_ATTR_VALUE_BITSET_TYPE;
+typedef int             CGEN_ATTR_VALUE_ENUM_TYPE;
+typedef union
+{
+  CGEN_ATTR_VALUE_BITSET_TYPE bitset;
+  CGEN_ATTR_VALUE_ENUM_TYPE   nonbitset;
+} CGEN_ATTR_VALUE_TYPE;
+
+/* Struct to record attribute information.  */
+
+typedef struct
+{
+  /* Boolean attributes.  */
+  unsigned int bool_;
+  /* Non-boolean integer attributes.  */
+  CGEN_ATTR_VALUE_TYPE nonbool[1];
+} CGEN_ATTR;
+
+/* Define a structure member for attributes with N non-boolean entries.
+   There is no maximum number of non-boolean attributes.
+   There is a maximum of 32 boolean attributes (since they are all recorded
+   in one host int).  */
+
+#define CGEN_ATTR_TYPE(n) \
+struct { unsigned int bool_; \
+	 CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; }
+
+/* Return the boolean attributes.  */
+
+#define CGEN_ATTR_BOOLS(a) ((a)->bool_)
+
+/* Non-boolean attribute numbers are offset by this much.  */
+
+#define CGEN_ATTR_NBOOL_OFFSET 32
+
+/* Given a boolean attribute number, return its mask.  */
+
+#define CGEN_ATTR_MASK(attr) (1 << (attr))
+
+/* Return the value of boolean attribute ATTR in ATTRS.  */
+
+#define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0)
+
+/* Return value of attribute ATTR in ATTR_TABLE for OBJ.
+   OBJ is a pointer to the entity that has the attributes
+   (??? not used at present but is reserved for future purposes - eventually
+   the goal is to allow recording attributes in source form and computing
+   them lazily at runtime, not sure of the details yet).  */
+
+#define CGEN_ATTR_VALUE(obj, attr_table, attr) \
+((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \
+ ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \
+ : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset))
+#define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \
+ ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset)
+
+/* Attribute name/value tables.
+   These are used to assist parsing of descriptions at run-time.  */
+
+typedef struct
+{
+  const char * name;
+  unsigned value;
+} CGEN_ATTR_ENTRY;
+
+/* For each domain (ifld,hw,operand,insn), list of attributes.  */
+
+typedef struct
+{
+  const char * name;
+  const CGEN_ATTR_ENTRY * dfault;
+  const CGEN_ATTR_ENTRY * vals;
+} CGEN_ATTR_TABLE;
+
+/* Instruction set variants.  */
+
+typedef struct {
+  const char *name;
+
+  /* Default instruction size (in bits).
+     This is used by the assembler when it encounters an unknown insn.  */
+  unsigned int default_insn_bitsize;
+
+  /* Base instruction size (in bits).
+     For non-LIW cpus this is generally the length of the smallest insn.
+     For LIW cpus its wip (work-in-progress).  For the m32r its 32.  */
+  unsigned int base_insn_bitsize;
+
+  /* Minimum/maximum instruction size (in bits).  */
+  unsigned int min_insn_bitsize;
+  unsigned int max_insn_bitsize;
+} CGEN_ISA;
+
+/* Machine variants.  */
+
+typedef struct {
+  const char *name;
+  /* The argument to bfd_arch_info->scan.  */
+  const char *bfd_name;
+  /* one of enum mach_attr */
+  int num;
+  /* parameter from mach->cpu */
+  unsigned int insn_chunk_bitsize;
+} CGEN_MACH;
+
+/* Parse result (also extraction result).
+
+   The result of parsing an insn is stored here.
+   To generate the actual insn, this is passed to the insert handler.
+   When printing an insn, the result of extraction is stored here.
+   To print the insn, this is passed to the print handler.
+
+   It is machine generated so we don't define it here,
+   but we do need a forward decl for the handler fns.
+
+   There is one member for each possible field in the insn.
+   The type depends on the field.
+   Also recorded here is the computed length of the insn for architectures
+   where it varies.
+*/
+
+typedef struct cgen_fields CGEN_FIELDS;
+
+/* Total length of the insn, as recorded in the `fields' struct.  */
+/* ??? The field insert handler has lots of opportunities for optimization
+   if it ever gets inlined.  On architectures where insns all have the same
+   size, may wish to detect that and make this macro a constant - to allow
+   further optimizations.  */
+
+#define CGEN_FIELDS_BITSIZE(fields) ((fields)->length)
+
+/* Extraction support for variable length insn sets.  */
+
+/* When disassembling we don't know the number of bytes to read at the start.
+   So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest
+   are read when needed.  This struct controls this.  It is basically the
+   disassemble_info stuff, except that we provide a cache for values already
+   read (since bytes can typically be read several times to fetch multiple
+   operands that may be in them), and that extraction of fields is needed
+   in contexts other than disassembly.  */
+
+typedef struct {
+  /* A pointer to the disassemble_info struct.
+     We don't require dis-asm.h so we use void * for the type here.
+     If NULL, BYTES is full of valid data (VALID == -1).  */
+  void *dis_info;
+  /* Points to a working buffer of sufficient size.  */
+  unsigned char *insn_bytes;
+  /* Mask of bytes that are valid in INSN_BYTES.  */
+  unsigned int valid;
+} CGEN_EXTRACT_INFO;
+
+/* Associated with each insn or expression is a set of "handlers" for
+   performing operations like parsing, printing, etc.  These require a bfd_vma
+   value to be passed around but we don't want all applications to need bfd.h.
+   So this stuff is only provided if bfd.h has been included.  */
+
+/* Parse handler.
+   CD is a cpu table descriptor.
+   INSN is a pointer to a struct describing the insn being parsed.
+   STRP is a pointer to a pointer to the text being parsed.
+   FIELDS is a pointer to a cgen_fields struct in which the results are placed.
+   If the expression is successfully parsed, *STRP is updated.
+   If not it is left alone.
+   The result is NULL if success or an error message.  */
+typedef const char * (cgen_parse_fn)
+  (CGEN_CPU_DESC, const CGEN_INSN *insn_,
+   const char **strp_, CGEN_FIELDS *fields_);
+
+/* Insert handler.
+   CD is a cpu table descriptor.
+   INSN is a pointer to a struct describing the insn being parsed.
+   FIELDS is a pointer to a cgen_fields struct from which the values
+   are fetched.
+   INSNP is a pointer to a buffer in which to place the insn.
+   PC is the pc value of the insn.
+   The result is an error message or NULL if success.  */
+
+#ifdef __BFD_H_SEEN__
+typedef const char * (cgen_insert_fn)
+  (CGEN_CPU_DESC, const CGEN_INSN *insn_,
+   CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_,
+   bfd_vma pc_);
+#else
+typedef const char * (cgen_insert_fn) ();
+#endif
+
+/* Extract handler.
+   CD is a cpu table descriptor.
+   INSN is a pointer to a struct describing the insn being parsed.
+   The second argument is a pointer to a struct controlling extraction
+   (only used for variable length insns).
+   EX_INFO is a pointer to a struct for controlling reading of further
+   bytes for the insn.
+   BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order).
+   FIELDS is a pointer to a cgen_fields struct in which the results are placed.
+   PC is the pc value of the insn.
+   The result is the length of the insn in bits or zero if not recognized.  */
+
+#ifdef __BFD_H_SEEN__
+typedef int (cgen_extract_fn)
+  (CGEN_CPU_DESC, const CGEN_INSN *insn_,
+   CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_,
+   CGEN_FIELDS *fields_, bfd_vma pc_);
+#else
+typedef int (cgen_extract_fn) ();
+#endif
+
+/* Print handler.
+   CD is a cpu table descriptor.
+   INFO is a pointer to the disassembly info.
+   Eg: disassemble_info.  It's defined as `PTR' so this file can be included
+   without dis-asm.h.
+   INSN is a pointer to a struct describing the insn being printed.
+   FIELDS is a pointer to a cgen_fields struct.
+   PC is the pc value of the insn.
+   LEN is the length of the insn, in bits.  */
+
+#ifdef __BFD_H_SEEN__
+typedef void (cgen_print_fn)
+  (CGEN_CPU_DESC, void * info_, const CGEN_INSN *insn_,
+   CGEN_FIELDS *fields_, bfd_vma pc_, int len_);
+#else
+typedef void (cgen_print_fn) ();
+#endif
+
+/* Parse/insert/extract/print handlers.
+
+   Indices into the handler tables.
+   We could use pointers here instead, but 90% of them are generally identical
+   and that's a lot of redundant data.  Making these unsigned char indices
+   into tables of pointers saves a bit of space.
+   Using indices also keeps assembler code out of the disassembler and
+   vice versa.  */
+
+struct cgen_opcode_handler
+{
+  unsigned char parse, insert, extract, print;
+};
+
+/* Assembler interface.
+
+   The interface to the assembler is intended to be clean in the sense that
+   libopcodes.a is a standalone entity and could be used with any assembler.
+   Not that one would necessarily want to do that but rather that it helps
+   keep a clean interface.  The interface will obviously be slanted towards
+   GAS, but at least it's a start.
+   ??? Note that one possible user of the assembler besides GAS is GDB.
+
+   Parsing is controlled by the assembler which calls
+   CGEN_SYM (assemble_insn).  If it can parse and build the entire insn
+   it doesn't call back to the assembler.  If it needs/wants to call back
+   to the assembler, cgen_parse_operand_fn is called which can either
+
+   - return a number to be inserted in the insn
+   - return a "register" value to be inserted
+     (the register might not be a register per pe)
+   - queue the argument and return a marker saying the expression has been
+     queued (eg: a fix-up)
+   - return an error message indicating the expression wasn't recognizable
+
+   The result is an error message or NULL for success.
+   The parsed value is stored in the bfd_vma *.  */
+
+/* Values for indicating what the caller wants.  */
+
+enum cgen_parse_operand_type
+{
+  CGEN_PARSE_OPERAND_INIT,
+  CGEN_PARSE_OPERAND_INTEGER,
+  CGEN_PARSE_OPERAND_ADDRESS,
+  CGEN_PARSE_OPERAND_SYMBOLIC
+};
+
+/* Values for indicating what was parsed.  */
+
+enum cgen_parse_operand_result
+{
+  CGEN_PARSE_OPERAND_RESULT_NUMBER,
+  CGEN_PARSE_OPERAND_RESULT_REGISTER,
+  CGEN_PARSE_OPERAND_RESULT_QUEUED,
+  CGEN_PARSE_OPERAND_RESULT_ERROR
+};
+
+#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily.  */
+typedef const char * (cgen_parse_operand_fn)
+  (CGEN_CPU_DESC,
+   enum cgen_parse_operand_type, const char **, int, int,
+   enum cgen_parse_operand_result *, bfd_vma *);
+#else
+typedef const char * (cgen_parse_operand_fn) ();
+#endif
+
+/* Set the cgen_parse_operand_fn callback.  */
+
+extern void cgen_set_parse_operand_fn
+  (CGEN_CPU_DESC, cgen_parse_operand_fn);
+
+/* Called before trying to match a table entry with the insn.  */
+
+extern void cgen_init_parse_operand (CGEN_CPU_DESC);
+
+/* Operand values (keywords, integers, symbols, etc.)  */
+
+/* Types of assembler elements.  */
+
+enum cgen_asm_type
+{
+  CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX
+};
+
+#ifndef CGEN_ARCH
+enum cgen_hw_type { CGEN_HW_MAX };
+#endif
+
+/* List of hardware elements.  */
+
+typedef struct
+{
+  char *name;
+  enum cgen_hw_type type;
+  /* There is currently no example where both index specs and value specs
+     are required, so for now both are clumped under "asm_data".  */
+  enum cgen_asm_type asm_type;
+  void *asm_data;
+#ifndef CGEN_HW_NBOOL_ATTRS
+#define CGEN_HW_NBOOL_ATTRS 1
+#endif
+  CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs;
+#define CGEN_HW_ATTRS(hw) (&(hw)->attrs)
+} CGEN_HW_ENTRY;
+
+/* Return value of attribute ATTR in HW.  */
+
+#define CGEN_HW_ATTR_VALUE(hw, attr) \
+CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr))
+
+/* Table of hardware elements for selected mach, computed at runtime.
+   enum cgen_hw_type is an index into this table (specifically `entries').  */
+
+typedef struct {
+  /* Pointer to null terminated table of all compiled in entries.  */
+  const CGEN_HW_ENTRY *init_entries;
+  unsigned int entry_size; /* since the attribute member is variable sized */
+  /* Array of all entries, initial and run-time added.  */
+  const CGEN_HW_ENTRY **entries;
+  /* Number of elements in `entries'.  */
+  unsigned int num_entries;
+  /* For now, xrealloc is called each time a new entry is added at runtime.
+     ??? May wish to keep track of some slop to reduce the number of calls to
+     xrealloc, except that there's unlikely to be many and not expected to be
+     in speed critical code.  */
+} CGEN_HW_TABLE;
+
+extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name
+  (CGEN_CPU_DESC, const char *);
+extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num
+  (CGEN_CPU_DESC, unsigned int);
+
+/* This struct is used to describe things like register names, etc.  */
+
+typedef struct cgen_keyword_entry
+{
+  /* Name (as in register name).  */
+  char * name;
+
+  /* Value (as in register number).
+     The value cannot be -1 as that is used to indicate "not found".
+     IDEA: Have "FUNCTION" attribute? [function is called to fetch value].  */
+  int value;
+
+  /* Attributes.
+     This should, but technically needn't, appear last.  It is a variable sized
+     array in that one architecture may have 1 nonbool attribute and another
+     may have more.  Having this last means the non-architecture specific code
+     needn't care.  The goal is to eventually record
+     attributes in their raw form, evaluate them at run-time, and cache the
+     values, so this worry will go away anyway.  */
+  /* ??? Moving this last should be done by treating keywords like insn lists
+     and moving the `next' fields into a CGEN_KEYWORD_LIST struct.  */
+  /* FIXME: Not used yet.  */
+#ifndef CGEN_KEYWORD_NBOOL_ATTRS
+#define CGEN_KEYWORD_NBOOL_ATTRS 1
+#endif
+  CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs;
+
+  /* ??? Putting these here means compiled in entries can't be const.
+     Not a really big deal, but something to consider.  */
+  /* Next name hash table entry.  */
+  struct cgen_keyword_entry *next_name;
+  /* Next value hash table entry.  */
+  struct cgen_keyword_entry *next_value;
+} CGEN_KEYWORD_ENTRY;
+
+/* Top level struct for describing a set of related keywords
+   (e.g. register names).
+
+   This struct supports run-time entry of new values, and hashed lookups.  */
+
+typedef struct cgen_keyword
+{
+  /* Pointer to initial [compiled in] values.  */
+  CGEN_KEYWORD_ENTRY *init_entries;
+  
+  /* Number of entries in `init_entries'.  */
+  unsigned int num_init_entries;
+  
+  /* Hash table used for name lookup.  */
+  CGEN_KEYWORD_ENTRY **name_hash_table;
+  
+  /* Hash table used for value lookup.  */
+  CGEN_KEYWORD_ENTRY **value_hash_table;
+  
+  /* Number of entries in the hash_tables.  */
+  unsigned int hash_table_size;
+  
+  /* Pointer to null keyword "" entry if present.  */
+  const CGEN_KEYWORD_ENTRY *null_entry;
+
+  /* String containing non-alphanumeric characters used
+     in keywords.  
+     At present, the highest number of entries used is 1.  */
+  char nonalpha_chars[8];
+} CGEN_KEYWORD;
+
+/* Structure used for searching.  */
+
+typedef struct
+{
+  /* Table being searched.  */
+  const CGEN_KEYWORD *table;
+  
+  /* Specification of what is being searched for.  */
+  const char *spec;
+  
+  /* Current index in hash table.  */
+  unsigned int current_hash;
+  
+  /* Current element in current hash chain.  */
+  CGEN_KEYWORD_ENTRY *current_entry;
+} CGEN_KEYWORD_SEARCH;
+
+/* Lookup a keyword from its name.  */
+
+const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name
+  (CGEN_KEYWORD *, const char *);
+
+/* Lookup a keyword from its value.  */
+
+const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value
+  (CGEN_KEYWORD *, int);
+
+/* Add a keyword.  */
+
+void cgen_keyword_add (CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *);
+
+/* Keyword searching.
+   This can be used to retrieve every keyword, or a subset.  */
+
+CGEN_KEYWORD_SEARCH cgen_keyword_search_init
+  (CGEN_KEYWORD *, const char *);
+const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next
+  (CGEN_KEYWORD_SEARCH *);
+
+/* Operand value support routines.  */
+
+extern const char *cgen_parse_keyword
+  (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *);
+#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily.  */
+extern const char *cgen_parse_signed_integer
+  (CGEN_CPU_DESC, const char **, int, long *);
+extern const char *cgen_parse_unsigned_integer
+  (CGEN_CPU_DESC, const char **, int, unsigned long *);
+extern const char *cgen_parse_address
+  (CGEN_CPU_DESC, const char **, int, int,
+   enum cgen_parse_operand_result *, bfd_vma *);
+extern const char *cgen_validate_signed_integer
+  (long, long, long);
+extern const char *cgen_validate_unsigned_integer
+  (unsigned long, unsigned long, unsigned long);
+#endif
+
+/* Operand modes.  */
+
+/* ??? This duplicates the values in arch.h.  Revisit.
+   These however need the CGEN_ prefix [as does everything in this file].  */
+/* ??? Targets may need to add their own modes so we may wish to move this
+   to <arch>-opc.h, or add a hook.  */
+
+enum cgen_mode {
+  CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */
+  CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI,
+  CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI,
+  CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF,
+  CGEN_MODE_TARGET_MAX,
+  CGEN_MODE_INT, CGEN_MODE_UINT,
+  CGEN_MODE_MAX
+};
+
+/* FIXME: Until simulator is updated.  */
+
+#define CGEN_MODE_VM CGEN_MODE_VOID
+
+/* Operands.  */
+
+#ifndef CGEN_ARCH
+enum cgen_operand_type { CGEN_OPERAND_MAX };
+#endif
+
+/* "nil" indicator for the operand instance table */
+#define CGEN_OPERAND_NIL CGEN_OPERAND_MAX
+
+/* A tree of these structs represents the multi-ifield
+   structure of an operand's hw-index value, if it exists.  */
+
+struct cgen_ifld;
+
+typedef struct cgen_maybe_multi_ifield
+{
+  int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry);
+		n: indexed by array of more cgen_maybe_multi_ifields.  */
+  union
+  {
+    const void *p;
+    const struct cgen_maybe_multi_ifield * multi;
+    const struct cgen_ifld * leaf;
+  } val;
+}
+CGEN_MAYBE_MULTI_IFLD;
+
+/* This struct defines each entry in the operand table.  */
+
+typedef struct
+{
+  /* Name as it appears in the syntax string.  */
+  char *name;
+
+  /* Operand type.  */
+  enum cgen_operand_type type;
+
+  /* The hardware element associated with this operand.  */
+  enum cgen_hw_type hw_type;
+
+  /* FIXME: We don't yet record ifield definitions, which we should.
+     When we do it might make sense to delete start/length (since they will
+     be duplicated in the ifield's definition) and replace them with a
+     pointer to the ifield entry.  */
+
+  /* Bit position.
+     This is just a hint, and may be unused in more complex operands.
+     May be unused for a modifier.  */
+  unsigned char start;
+
+  /* The number of bits in the operand.
+     This is just a hint, and may be unused in more complex operands.
+     May be unused for a modifier.  */
+  unsigned char length;
+
+  /* The (possibly-multi) ifield used as an index for this operand, if it
+     is indexed by a field at all. This substitutes / extends the start and
+     length fields above, but unsure at this time whether they are used
+     anywhere.  */
+  CGEN_MAYBE_MULTI_IFLD index_fields;
+#if 0 /* ??? Interesting idea but relocs tend to get too complicated,
+	 and ABI dependent, for simple table lookups to work.  */
+  /* Ideally this would be the internal (external?) reloc type.  */
+  int reloc_type;
+#endif
+
+  /* Attributes.
+     This should, but technically needn't, appear last.  It is a variable sized
+     array in that one architecture may have 1 nonbool attribute and another
+     may have more.  Having this last means the non-architecture specific code
+     needn't care, now or tomorrow.  The goal is to eventually record
+     attributes in their raw form, evaluate them at run-time, and cache the
+     values, so this worry will go away anyway.  */
+#ifndef CGEN_OPERAND_NBOOL_ATTRS
+#define CGEN_OPERAND_NBOOL_ATTRS 1
+#endif
+  CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs;
+#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs)
+} CGEN_OPERAND;
+
+/* Return value of attribute ATTR in OPERAND.  */
+
+#define CGEN_OPERAND_ATTR_VALUE(operand, attr) \
+CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr))
+
+/* Table of operands for selected mach/isa, computed at runtime.
+   enum cgen_operand_type is an index into this table (specifically
+   `entries').  */
+
+typedef struct {
+  /* Pointer to null terminated table of all compiled in entries.  */
+  const CGEN_OPERAND *init_entries;
+  unsigned int entry_size; /* since the attribute member is variable sized */
+  /* Array of all entries, initial and run-time added.  */
+  const CGEN_OPERAND **entries;
+  /* Number of elements in `entries'.  */
+  unsigned int num_entries;
+  /* For now, xrealloc is called each time a new entry is added at runtime.
+     ??? May wish to keep track of some slop to reduce the number of calls to
+     xrealloc, except that there's unlikely to be many and not expected to be
+     in speed critical code.  */
+} CGEN_OPERAND_TABLE;
+
+extern const CGEN_OPERAND * cgen_operand_lookup_by_name
+  (CGEN_CPU_DESC, const char *);
+extern const CGEN_OPERAND * cgen_operand_lookup_by_num
+  (CGEN_CPU_DESC, int);
+
+/* Instruction operand instances.
+
+   For each instruction, a list of the hardware elements that are read and
+   written are recorded.  */
+
+/* The type of the instance.  */
+
+enum cgen_opinst_type {
+  /* End of table marker.  */
+  CGEN_OPINST_END = 0,
+  CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT
+};
+
+typedef struct
+{
+  /* Input or output indicator.  */
+  enum cgen_opinst_type type;
+
+  /* Name of operand.  */
+  const char *name;
+
+  /* The hardware element referenced.  */
+  enum cgen_hw_type hw_type;
+
+  /* The mode in which the operand is being used.  */
+  enum cgen_mode mode;
+
+  /* The operand table entry CGEN_OPERAND_NIL if there is none
+     (i.e. an explicit hardware reference).  */
+  enum cgen_operand_type op_type;
+
+  /* If `operand' is "nil", the index (e.g. into array of registers).  */
+  int index;
+
+  /* Attributes.
+     ??? This perhaps should be a real attribute struct but there's
+     no current need, so we save a bit of space and just have a set of
+     flags.  The interface is such that this can easily be made attributes
+     should it prove useful.  */
+  unsigned int attrs;
+#define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs)
+/* Return value of attribute ATTR in OPINST.  */
+#define CGEN_OPINST_ATTR(opinst, attr) \
+((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0)
+/* Operand is conditionally referenced (read/written).  */
+#define CGEN_OPINST_COND_REF 1
+} CGEN_OPINST;
+
+/* Syntax string.
+
+   Each insn format and subexpression has one of these.
+
+   The syntax "string" consists of characters (n > 0 && n < 128), and operand
+   values (n >= 128), and is terminated by 0.  Operand values are 128 + index
+   into the operand table.  The operand table doesn't exist in C, per se, as
+   the data is recorded in the parse/insert/extract/print switch statements. */
+
+/* This should be at least as large as necessary for any target. */
+#define CGEN_MAX_SYNTAX_ELEMENTS 48
+
+/* A target may know its own precise maximum.  Assert that it falls below
+   the above limit. */
+#ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS
+#if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS
+#error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS"
+#endif
+#endif
+
+typedef unsigned short CGEN_SYNTAX_CHAR_TYPE;
+
+typedef struct
+{
+  CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS];
+} CGEN_SYNTAX;
+
+#define CGEN_SYNTAX_STRING(syn) (syn->syntax)
+#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128)
+#define CGEN_SYNTAX_CHAR(c) ((unsigned char)c)
+#define CGEN_SYNTAX_FIELD(c) ((c) - 128)
+#define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128)
+
+/* ??? I can't currently think of any case where the mnemonic doesn't come
+   first [and if one ever doesn't building the hash tables will be tricky].
+   However, we treat mnemonics as just another operand of the instruction.
+   A value of 1 means "this is where the mnemonic appears".  1 isn't
+   special other than it's a non-printable ASCII char.  */
+
+#define CGEN_SYNTAX_MNEMONIC       1
+#define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC)
+
+/* Instruction fields.
+
+   ??? We currently don't allow adding fields at run-time.
+   Easy to fix when needed.  */
+
+typedef struct cgen_ifld {
+  /* Enum of ifield.  */
+  int num;
+#define CGEN_IFLD_NUM(f) ((f)->num)
+
+  /* Name of the field, distinguishes it from all other fields.  */
+  const char *name;
+#define CGEN_IFLD_NAME(f) ((f)->name)
+
+  /* Default offset, in bits, from the start of the insn to the word
+     containing the field.  */
+  int word_offset;
+#define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset)
+
+  /* Default length of the word containing the field.  */
+  int word_size;
+#define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size)
+
+  /* Default starting bit number.
+     Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P.  */
+  int start;
+#define CGEN_IFLD_START(f) ((f)->start)
+
+  /* Length of the field, in bits.  */
+  int length;
+#define CGEN_IFLD_LENGTH(f) ((f)->length)
+
+#ifndef CGEN_IFLD_NBOOL_ATTRS
+#define CGEN_IFLD_NBOOL_ATTRS 1
+#endif
+  CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs;
+#define CGEN_IFLD_ATTRS(f) (&(f)->attrs)
+} CGEN_IFLD;
+
+/* Return value of attribute ATTR in IFLD.  */
+#define CGEN_IFLD_ATTR_VALUE(ifld, attr) \
+CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr))
+
+/* Instruction data.  */
+
+/* Instruction formats.
+
+   Instructions are grouped by format.  Associated with an instruction is its
+   format.  Each insn's opcode table entry contains a format table entry.
+   ??? There is usually very few formats compared with the number of insns,
+   so one can reduce the size of the opcode table by recording the format table
+   as a separate entity.  Given that we currently don't, format table entries
+   are also distinguished by their operands.  This increases the size of the
+   table, but reduces the number of tables.  It's all minutiae anyway so it
+   doesn't really matter [at this point in time].
+
+   ??? Support for variable length ISA's is wip.  */
+
+/* Accompanying each iformat description is a list of its fields.  */
+
+typedef struct {
+  const CGEN_IFLD *ifld;
+#define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld)
+} CGEN_IFMT_IFLD;
+
+/* This should be at least as large as necessary for any target. */
+#define CGEN_MAX_IFMT_OPERANDS 16
+
+/* A target may know its own precise maximum.  Assert that it falls below
+   the above limit. */
+#ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS
+#if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS
+#error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS"
+#endif
+#endif
+
+
+typedef struct
+{
+  /* Length that MASK and VALUE have been calculated to
+     [VALUE is recorded elsewhere].
+     Normally it is base_insn_bitsize.  On [V]LIW architectures where the base
+     insn size may be larger than the size of an insn, this field is less than
+     base_insn_bitsize.  */
+  unsigned char mask_length;
+#define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length)
+
+  /* Total length of instruction, in bits.  */
+  unsigned char length;
+#define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length)
+
+  /* Mask to apply to the first MASK_LENGTH bits.
+     Each insn's value is stored with the insn.
+     The first step in recognizing an insn for disassembly is
+     (opcode & mask) == value.  */
+  CGEN_INSN_INT mask;
+#define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask)
+
+  /* Instruction fields.
+     +1 for trailing NULL.  */
+  CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1];
+#define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds)
+} CGEN_IFMT;
+
+/* Instruction values.  */
+
+typedef struct
+{
+  /* The opcode portion of the base insn.  */
+  CGEN_INSN_INT base_value;
+
+#ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS
+  /* Extra opcode values beyond base_value.  */
+  unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS];
+#endif
+} CGEN_IVALUE;
+
+/* Instruction opcode table.
+   This contains the syntax and format data of an instruction.  */
+
+/* ??? Some ports already have an opcode table yet still need to use the rest
+   of what cgen_insn has.  Plus keeping the opcode data with the operand
+   instance data can create a pretty big file.  So we keep them separately.
+   Not sure this is a good idea in the long run.  */
+
+typedef struct
+{
+  /* Indices into parse/insert/extract/print handler tables.  */
+  struct cgen_opcode_handler handlers;
+#define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers)
+
+  /* Syntax string.  */
+  CGEN_SYNTAX syntax;
+#define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax)
+
+  /* Format entry.  */
+  const CGEN_IFMT *format;
+#define CGEN_OPCODE_FORMAT(opc) ((opc)->format)
+#define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc))
+#define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc))
+#define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc))
+
+  /* Instruction opcode value.  */
+  CGEN_IVALUE value;
+#define CGEN_OPCODE_VALUE(opc) (& (opc)->value)
+#define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value)
+#define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc))
+} CGEN_OPCODE;
+
+/* Instruction attributes.
+   This is made a published type as applications can cache a pointer to
+   the attributes for speed.  */
+
+#ifndef CGEN_INSN_NBOOL_ATTRS
+#define CGEN_INSN_NBOOL_ATTRS 1
+#endif
+typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE;
+
+/* Enum of architecture independent attributes.  */
+
+#ifndef CGEN_ARCH
+/* ??? Numbers here are recorded in two places.  */
+typedef enum cgen_insn_attr {
+  CGEN_INSN_ALIAS = 0
+} CGEN_INSN_ATTR;
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool_ & (1 << CGEN_INSN_ALIAS))
+#endif
+
+/* This struct defines each entry in the instruction table.  */
+
+typedef struct
+{
+  /* Each real instruction is enumerated.  */
+  /* ??? This may go away in time.  */
+  int num;
+#define CGEN_INSN_NUM(insn) ((insn)->base->num)
+
+  /* Name of entry (that distinguishes it from all other entries).  */
+  /* ??? If mnemonics have operands, try to print full mnemonic.  */
+  const char *name;
+#define CGEN_INSN_NAME(insn) ((insn)->base->name)
+
+  /* Mnemonic.  This is used when parsing and printing the insn.
+     In the case of insns that have operands on the mnemonics, this is
+     only the constant part.  E.g. for conditional execution of an `add' insn,
+     where the full mnemonic is addeq, addne, etc., and the condition is
+     treated as an operand, this is only "add".  */
+  const char *mnemonic;
+#define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic)
+
+  /* Total length of instruction, in bits.  */
+  int bitsize;
+#define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize)
+
+#if 0 /* ??? Disabled for now as there is a problem with embedded newlines
+	 and the table is already pretty big.  Should perhaps be moved
+	 to a file of its own.  */
+  /* Semantics, as RTL.  */
+  /* ??? Plain text or bytecodes?  */
+  /* ??? Note that the operand instance table could be computed at run-time
+     if we parse this and cache the results.  Something to eventually do.  */
+  const char *rtx;
+#define CGEN_INSN_RTX(insn) ((insn)->base->rtx)
+#endif
+
+  /* Attributes.
+     This must appear last.  It is a variable sized array in that one
+     architecture may have 1 nonbool attribute and another may have more.
+     Having this last means the non-architecture specific code needn't
+     care.  The goal is to eventually record attributes in their raw form,
+     evaluate them at run-time, and cache the values, so this worry will go
+     away anyway.  */
+  CGEN_INSN_ATTR_TYPE attrs;
+#define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs)
+/* Return value of attribute ATTR in INSN.  */
+#define CGEN_INSN_ATTR_VALUE(insn, attr) \
+CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
+#define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \
+  CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
+} CGEN_IBASE;
+
+/* Return non-zero if INSN is the "invalid" insn marker.  */
+
+#define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0)
+
+/* Main struct contain instruction information.
+   BASE is always present, the rest is present only if asked for.  */
+
+struct cgen_insn
+{
+  /* ??? May be of use to put a type indicator here.
+     Then this struct could different info for different classes of insns.  */
+  /* ??? A speedup can be had by moving `base' into this struct.
+     Maybe later.  */
+  const CGEN_IBASE *base;
+  const CGEN_OPCODE *opcode;
+  const CGEN_OPINST *opinst;
+
+  /* Regex to disambiguate overloaded opcodes */
+  void *rx;
+#define CGEN_INSN_RX(insn) ((insn)->rx)
+#define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5)
+};
+
+/* Instruction lists.
+   This is used for adding new entries and for creating the hash lists.  */
+
+typedef struct cgen_insn_list
+{
+  struct cgen_insn_list *next;
+  const CGEN_INSN *insn;
+} CGEN_INSN_LIST;
+
+/* Table of instructions.  */
+
+typedef struct
+{
+  const CGEN_INSN *init_entries;
+  unsigned int entry_size; /* since the attribute member is variable sized */
+  unsigned int num_init_entries;
+  CGEN_INSN_LIST *new_entries;
+} CGEN_INSN_TABLE;
+
+/* Return number of instructions.  This includes any added at run-time.  */
+
+extern int cgen_insn_count (CGEN_CPU_DESC);
+extern int cgen_macro_insn_count (CGEN_CPU_DESC);
+
+/* Macros to access the other insn elements not recorded in CGEN_IBASE.  */
+
+/* Fetch INSN's operand instance table.  */
+/* ??? Doesn't handle insns added at runtime.  */
+#define CGEN_INSN_OPERANDS(insn) ((insn)->opinst)
+
+/* Return INSN's opcode table entry.  */
+#define CGEN_INSN_OPCODE(insn) ((insn)->opcode)
+
+/* Return INSN's handler data.  */
+#define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn))
+
+/* Return INSN's syntax.  */
+#define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn))
+
+/* Return size of base mask in bits.  */
+#define CGEN_INSN_MASK_BITSIZE(insn) \
+  CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn))
+
+/* Return mask of base part of INSN.  */
+#define CGEN_INSN_BASE_MASK(insn) \
+  CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn))
+
+/* Return value of base part of INSN.  */
+#define CGEN_INSN_BASE_VALUE(insn) \
+  CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn))
+
+/* Standard way to test whether INSN is supported by MACH.
+   MACH is one of enum mach_attr.
+   The "|1" is because the base mach is always selected.  */
+#define CGEN_INSN_MACH_HAS_P(insn, mach) \
+((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0)
+
+/* Macro instructions.
+   Macro insns aren't real insns, they map to one or more real insns.
+   E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or
+   some such.
+
+   Macro insns can expand to nothing (e.g. a nop that is optimized away).
+   This is useful in multi-insn macros that build a constant in a register.
+   Of course this isn't the default behaviour and must be explicitly enabled.
+
+   Assembly of macro-insns is relatively straightforward.  Disassembly isn't.
+   However, disassembly of at least some kinds of macro insns is important
+   in order that the disassembled code preserve the readability of the original
+   insn.  What is attempted here is to disassemble all "simple" macro-insns,
+   where "simple" is currently defined to mean "expands to one real insn".
+
+   Simple macro-insns are handled specially.  They are emitted as ALIAS's
+   of real insns.  This simplifies their handling since there's usually more
+   of them than any other kind of macro-insn, and proper disassembly of them
+   falls out for free.  */
+
+/* For each macro-insn there may be multiple expansion possibilities,
+   depending on the arguments.  This structure is accessed via the `data'
+   member of CGEN_INSN.  */
+
+typedef struct cgen_minsn_expansion {
+  /* Function to do the expansion.
+     If the expansion fails (e.g. "no match") NULL is returned.
+     Space for the expansion is obtained with malloc.
+     It is up to the caller to free it.  */
+  const char * (* fn)
+     (const struct cgen_minsn_expansion *,
+      const char *, const char **, int *,
+      CGEN_OPERAND **);
+#define CGEN_MIEXPN_FN(ex) ((ex)->fn)
+
+  /* Instruction(s) the macro expands to.
+     The format of STR is defined by FN.
+     It is typically the assembly code of the real insn, but it could also be
+     the original Scheme expression or a tokenized form of it (with FN being
+     an appropriate interpreter).  */
+  const char * str;
+#define CGEN_MIEXPN_STR(ex) ((ex)->str)
+} CGEN_MINSN_EXPANSION;
+
+/* Normal expander.
+   When supported, this function will convert the input string to another
+   string and the parser will be invoked recursively.  The output string
+   may contain further macro invocations.  */
+
+extern const char * cgen_expand_macro_insn
+  (CGEN_CPU_DESC, const struct cgen_minsn_expansion *,
+   const char *, const char **, int *, CGEN_OPERAND **);
+
+/* The assembler insn table is hashed based on some function of the mnemonic
+   (the actually hashing done is up to the target, but we provide a few
+   examples like the first letter or a function of the entire mnemonic).  */
+
+extern CGEN_INSN_LIST * cgen_asm_lookup_insn
+  (CGEN_CPU_DESC, const char *);
+#define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string))
+#define CGEN_ASM_NEXT_INSN(insn) ((insn)->next)
+
+/* The disassembler insn table is hashed based on some function of machine
+   instruction (the actually hashing done is up to the target).  */
+
+extern CGEN_INSN_LIST * cgen_dis_lookup_insn
+  (CGEN_CPU_DESC, const char *, CGEN_INSN_INT);
+/* FIXME: delete these two */
+#define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value))
+#define CGEN_DIS_NEXT_INSN(insn) ((insn)->next)
+
+/* The CPU description.
+   A copy of this is created when the cpu table is "opened".
+   All global state information is recorded here.
+   Access macros are provided for "public" members.  */
+
+typedef struct cgen_cpu_desc
+{
+  /* Bitmap of selected machine(s) (a la BFD machine number).  */
+  int machs;
+
+  /* Bitmap of selected isa(s).  */
+  CGEN_BITSET *isas;
+#define CGEN_CPU_ISAS(cd) ((cd)->isas)
+
+  /* Current endian.  */
+  enum cgen_endian endian;
+#define CGEN_CPU_ENDIAN(cd) ((cd)->endian)
+
+  /* Current insn endian.  */
+  enum cgen_endian insn_endian;
+#define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian)
+
+  /* Word size (in bits).  */
+  /* ??? Or maybe maximum word size - might we ever need to allow a cpu table
+     to be opened for both sparc32/sparc64?
+     ??? Another alternative is to create a table of selected machs and
+     lazily fetch the data from there.  */
+  unsigned int word_bitsize;
+
+  /* Instruction chunk size (in bits), for purposes of endianness
+     conversion.  */
+  unsigned int insn_chunk_bitsize;
+
+  /* Indicator if sizes are unknown.
+     This is used by default_insn_bitsize,base_insn_bitsize if there is a
+     difference between the selected isa's.  */
+#define CGEN_SIZE_UNKNOWN 65535
+
+  /* Default instruction size (in bits).
+     This is used by the assembler when it encounters an unknown insn.  */
+  unsigned int default_insn_bitsize;
+
+  /* Base instruction size (in bits).
+     For non-LIW cpus this is generally the length of the smallest insn.
+     For LIW cpus its wip (work-in-progress).  For the m32r its 32.  */
+  unsigned int base_insn_bitsize;
+
+  /* Minimum/maximum instruction size (in bits).  */
+  unsigned int min_insn_bitsize;
+  unsigned int max_insn_bitsize;
+
+  /* Instruction set variants.  */
+  const CGEN_ISA *isa_table;
+
+  /* Machine variants.  */
+  const CGEN_MACH *mach_table;
+
+  /* Hardware elements.  */
+  CGEN_HW_TABLE hw_table;
+
+  /* Instruction fields.  */
+  const CGEN_IFLD *ifld_table;
+
+  /* Operands.  */
+  CGEN_OPERAND_TABLE operand_table;
+
+  /* Main instruction table.  */
+  CGEN_INSN_TABLE insn_table;
+#define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table)
+
+  /* Macro instructions are defined separately and are combined with real
+     insns during hash table computation.  */
+  CGEN_INSN_TABLE macro_insn_table;
+
+  /* Copy of CGEN_INT_INSN_P.  */
+  int int_insn_p;
+
+  /* Called to rebuild the tables after something has changed.  */
+  void (*rebuild_tables) (CGEN_CPU_DESC);
+
+  /* Operand parser callback.  */
+  cgen_parse_operand_fn * parse_operand_fn;
+
+  /* Parse/insert/extract/print cover fns for operands.  */
+  const char * (*parse_operand)
+    (CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_);
+#ifdef __BFD_H_SEEN__
+  const char * (*insert_operand)
+    (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_,
+     CGEN_INSN_BYTES_PTR, bfd_vma pc_);
+  int (*extract_operand)
+    (CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+     CGEN_FIELDS *fields_, bfd_vma pc_);
+  void (*print_operand)
+    (CGEN_CPU_DESC, int opindex_, void * info_, CGEN_FIELDS * fields_,
+     void const *attrs_, bfd_vma pc_, int length_);
+#else
+  const char * (*insert_operand) ();
+  int (*extract_operand) ();
+  void (*print_operand) ();
+#endif
+#define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand)
+#define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand)
+#define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand)
+#define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand)
+
+  /* Size of CGEN_FIELDS struct.  */
+  unsigned int sizeof_fields;
+#define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields)
+
+  /* Set the bitsize field.  */
+  void (*set_fields_bitsize) (CGEN_FIELDS *fields_, int size_);
+#define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize)
+
+  /* CGEN_FIELDS accessors.  */
+  int (*get_int_operand)
+    (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_);
+  void (*set_int_operand)
+    (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_);
+#ifdef __BFD_H_SEEN__
+  bfd_vma (*get_vma_operand)
+    (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_);
+  void (*set_vma_operand)
+    (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_);
+#else
+  long (*get_vma_operand) ();
+  void (*set_vma_operand) ();
+#endif
+#define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand)
+#define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand)
+#define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand)
+#define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand)
+
+  /* Instruction parse/insert/extract/print handlers.  */
+  /* FIXME: make these types uppercase.  */
+  cgen_parse_fn * const *parse_handlers;
+  cgen_insert_fn * const *insert_handlers;
+  cgen_extract_fn * const *extract_handlers;
+  cgen_print_fn * const *print_handlers;
+#define CGEN_PARSE_FN(cd, insn)   (cd->parse_handlers[(insn)->opcode->handlers.parse])
+#define CGEN_INSERT_FN(cd, insn)  (cd->insert_handlers[(insn)->opcode->handlers.insert])
+#define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract])
+#define CGEN_PRINT_FN(cd, insn)   (cd->print_handlers[(insn)->opcode->handlers.print])
+
+  /* Return non-zero if insn should be added to hash table.  */
+  int (* asm_hash_p) (const CGEN_INSN *);
+
+  /* Assembler hash function.  */
+  unsigned int (* asm_hash) (const char *);
+
+  /* Number of entries in assembler hash table.  */
+  unsigned int asm_hash_size;
+
+  /* Return non-zero if insn should be added to hash table.  */
+  int (* dis_hash_p) (const CGEN_INSN *);
+
+  /* Disassembler hash function.  */
+  unsigned int (* dis_hash) (const char *, CGEN_INSN_INT);
+
+  /* Number of entries in disassembler hash table.  */
+  unsigned int dis_hash_size;
+
+  /* Assembler instruction hash table.  */
+  CGEN_INSN_LIST **asm_hash_table;
+  CGEN_INSN_LIST *asm_hash_table_entries;
+
+  /* Disassembler instruction hash table.  */
+  CGEN_INSN_LIST **dis_hash_table;
+  CGEN_INSN_LIST *dis_hash_table_entries;
+
+  /* This field could be turned into a bitfield if room for other flags is needed.  */
+  unsigned int signed_overflow_ok_p;
+       
+} CGEN_CPU_TABLE;
+
+/* wip */
+#ifndef CGEN_WORD_ENDIAN
+#define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd)
+#endif
+#ifndef CGEN_INSN_WORD_ENDIAN
+#define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd)
+#endif
+
+/* Prototypes of major functions.  */
+/* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC.
+   Not the init fns though, as that would drag in things that mightn't be
+   used and might not even exist.  */
+
+/* Argument types to cpu_open.  */
+
+enum cgen_cpu_open_arg {
+  CGEN_CPU_OPEN_END,
+  /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified".  */
+  CGEN_CPU_OPEN_ISAS,
+  /* Select machine(s), arg is bitmap or 0 meaning "unspecified".  */
+  CGEN_CPU_OPEN_MACHS,
+  /* Select machine, arg is mach's bfd name.
+     Multiple machines can be specified by repeated use.  */
+  CGEN_CPU_OPEN_BFDMACH,
+  /* Select endian, arg is CGEN_ENDIAN_*.  */
+  CGEN_CPU_OPEN_ENDIAN
+};
+
+/* Open a cpu descriptor table for use.
+   ??? We only support ISO C stdargs here, not K&R.
+   Laziness, plus experiment to see if anything requires K&R - eventually
+   K&R will no longer be supported - e.g. GDB is currently trying this.  */
+
+extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...);
+
+/* Cover fn to handle simple case.  */
+
+extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1)
+   (const char *mach_name_, enum cgen_endian endian_);
+
+/* Close it.  */
+
+extern void CGEN_SYM (cpu_close) (CGEN_CPU_DESC);
+
+/* Initialize the opcode table for use.
+   Called by init_asm/init_dis.  */
+
+extern void CGEN_SYM (init_opcode_table) (CGEN_CPU_DESC cd_);
+
+/* build the insn selection regex.
+   called by init_opcode_table */
+
+extern char * CGEN_SYM(build_insn_regex) (CGEN_INSN *insn_);
+
+/* Initialize the ibld table for use.
+   Called by init_asm/init_dis.  */
+
+extern void CGEN_SYM (init_ibld_table) (CGEN_CPU_DESC cd_);
+
+/* Initialize an cpu table for assembler or disassembler use.
+   These must be called immediately after cpu_open.  */
+
+extern void CGEN_SYM (init_asm) (CGEN_CPU_DESC);
+extern void CGEN_SYM (init_dis) (CGEN_CPU_DESC);
+
+/* Initialize the operand instance table for use.  */
+
+extern void CGEN_SYM (init_opinst_table) (CGEN_CPU_DESC cd_);
+
+/* Assemble an instruction.  */
+
+extern const CGEN_INSN * CGEN_SYM (assemble_insn)
+  (CGEN_CPU_DESC, const char *, CGEN_FIELDS *,
+   CGEN_INSN_BYTES_PTR, char **);
+
+extern const CGEN_KEYWORD CGEN_SYM (operand_mach);
+extern int CGEN_SYM (get_mach) (const char *);
+
+/* Operand index computation.  */
+extern const CGEN_INSN * cgen_lookup_insn
+  (CGEN_CPU_DESC, const CGEN_INSN * insn_,
+   CGEN_INSN_INT int_value_, unsigned char *bytes_value_,
+   int length_, CGEN_FIELDS *fields_, int alias_p_);
+extern void cgen_get_insn_operands
+  (CGEN_CPU_DESC, const CGEN_INSN * insn_,
+   const CGEN_FIELDS *fields_, int *indices_);
+extern const CGEN_INSN * cgen_lookup_get_insn_operands
+  (CGEN_CPU_DESC, const CGEN_INSN *insn_,
+   CGEN_INSN_INT int_value_, unsigned char *bytes_value_,
+   int length_, int *indices_, CGEN_FIELDS *fields_);
+
+/* Cover fns to bfd_get/set.  */
+
+extern CGEN_INSN_INT cgen_get_insn_value
+  (CGEN_CPU_DESC, unsigned char *, int);
+extern void cgen_put_insn_value
+  (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT);
+
+/* Read in a cpu description file.
+   ??? For future concerns, including adding instructions to the assembler/
+   disassembler at run-time.  */
+
+extern const char * cgen_read_cpu_file (CGEN_CPU_DESC, const char * filename_);
+
+/* Allow signed overflow of instruction fields.  */
+extern void cgen_set_signed_overflow_ok (CGEN_CPU_DESC);
+
+/* Generate an error message if a signed field in an instruction overflows.  */
+extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC);
+
+/* Will an error message be generated if a signed field in an instruction overflows ? */
+extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC);
+
+#endif /* OPCODE_CGEN_H */
diff --git a/binutils-2.25/include/opcode/convex.h b/binutils-2.25/include/opcode/convex.h
new file mode 100644
index 00000000..4643f5e0
--- /dev/null
+++ b/binutils-2.25/include/opcode/convex.h
@@ -0,0 +1,1708 @@
+/* Information for instruction disassembly on the Convex.
+   Copyright 1989, 1993, 2002, 2010 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define xxx 0
+#define rrr 1
+#define rr 2
+#define rxr 3
+#define r 4
+#define nops 5
+#define nr 6
+#define pcrel 7
+#define lr 8
+#define rxl 9
+#define rlr 10
+#define rrl 11
+#define iml 12
+#define imr 13
+#define a1r 14
+#define a1l 15
+#define a2r 16
+#define a2l 17
+#define a3 18
+#define a4 19
+#define a5 20
+#define V 1
+#define S 2
+#define VM 3
+#define A 4
+#define VL 5
+#define VS 6
+#define VLS 7
+#define PSW 8
+/* Prevent an error during "make depend".  */
+#if !defined (PC)
+#define PC 9
+#endif
+#define ITR 10
+#define VV 11
+#define ITSR 12
+#define TOC 13
+#define CIR 14
+#define TTR 15
+#define VMU 16
+#define VML 17
+#define ICR 18
+#define TCPU 19
+#define CPUID 20
+#define TID 21
+
+const char *op[] = {
+  "",
+  "v0\0v1\0v2\0v3\0v4\0v5\0v6\0v7",
+  "s0\0s1\0s2\0s3\0s4\0s5\0s6\0s7",
+  "vm",
+  "sp\0a1\0a2\0a3\0a4\0a5\0ap\0fp",
+  "vl",
+  "vs",
+  "vls",
+  "psw",
+  "pc",
+  "itr",
+  "vv",
+  "itsr",
+  "toc",
+  "cir",
+  "ttr",
+  "vmu",
+  "vml",
+  "icr",
+  "tcpu",
+  "cpuid",
+  "tid",
+};
+
+const struct formstr format0[] = {
+  {0,0,rrr,V,S,S},	/* mov */
+  {0,0,rrr,S,S,V},	/* mov */
+  {1,1,rrr,V,V,V},	/* merg.t */
+  {2,1,rrr,V,V,V},	/* mask.t */
+  {1,2,rrr,V,S,V},	/* merg.f */
+  {2,2,rrr,V,S,V},	/* mask.f */
+  {1,1,rrr,V,S,V},	/* merg.t */
+  {2,1,rrr,V,S,V},	/* mask.t */
+  {3,3,rrr,V,V,V},	/* mul.s */
+  {3,4,rrr,V,V,V},	/* mul.d */
+  {4,3,rrr,V,V,V},	/* div.s */
+  {4,4,rrr,V,V,V},	/* div.d */
+  {3,3,rrr,V,S,V},	/* mul.s */
+  {3,4,rrr,V,S,V},	/* mul.d */
+  {4,3,rrr,V,S,V},	/* div.s */
+  {4,4,rrr,V,S,V},	/* div.d */
+  {5,0,rrr,V,V,V},	/* and */
+  {6,0,rrr,V,V,V},	/* or */
+  {7,0,rrr,V,V,V},	/* xor */
+  {8,0,rrr,V,V,V},	/* shf */
+  {5,0,rrr,V,S,V},	/* and */
+  {6,0,rrr,V,S,V},	/* or */
+  {7,0,rrr,V,S,V},	/* xor */
+  {8,0,rrr,V,S,V},	/* shf */
+  {9,3,rrr,V,V,V},	/* add.s */
+  {9,4,rrr,V,V,V},	/* add.d */
+  {10,3,rrr,V,V,V},	/* sub.s */
+  {10,4,rrr,V,V,V},	/* sub.d */
+  {9,3,rrr,V,S,V},	/* add.s */
+  {9,4,rrr,V,S,V},	/* add.d */
+  {10,3,rrr,V,S,V},	/* sub.s */
+  {10,4,rrr,V,S,V},	/* sub.d */
+  {9,5,rrr,V,V,V},	/* add.b */
+  {9,6,rrr,V,V,V},	/* add.h */
+  {9,7,rrr,V,V,V},	/* add.w */
+  {9,8,rrr,V,V,V},	/* add.l */
+  {9,5,rrr,V,S,V},	/* add.b */
+  {9,6,rrr,V,S,V},	/* add.h */
+  {9,7,rrr,V,S,V},	/* add.w */
+  {9,8,rrr,V,S,V},	/* add.l */
+  {10,5,rrr,V,V,V},	/* sub.b */
+  {10,6,rrr,V,V,V},	/* sub.h */
+  {10,7,rrr,V,V,V},	/* sub.w */
+  {10,8,rrr,V,V,V},	/* sub.l */
+  {10,5,rrr,V,S,V},	/* sub.b */
+  {10,6,rrr,V,S,V},	/* sub.h */
+  {10,7,rrr,V,S,V},	/* sub.w */
+  {10,8,rrr,V,S,V},	/* sub.l */
+  {3,5,rrr,V,V,V},	/* mul.b */
+  {3,6,rrr,V,V,V},	/* mul.h */
+  {3,7,rrr,V,V,V},	/* mul.w */
+  {3,8,rrr,V,V,V},	/* mul.l */
+  {3,5,rrr,V,S,V},	/* mul.b */
+  {3,6,rrr,V,S,V},	/* mul.h */
+  {3,7,rrr,V,S,V},	/* mul.w */
+  {3,8,rrr,V,S,V},	/* mul.l */
+  {4,5,rrr,V,V,V},	/* div.b */
+  {4,6,rrr,V,V,V},	/* div.h */
+  {4,7,rrr,V,V,V},	/* div.w */
+  {4,8,rrr,V,V,V},	/* div.l */
+  {4,5,rrr,V,S,V},	/* div.b */
+  {4,6,rrr,V,S,V},	/* div.h */
+  {4,7,rrr,V,S,V},	/* div.w */
+  {4,8,rrr,V,S,V},	/* div.l */
+};
+
+const struct formstr format1[] = {
+  {11,0,xxx,0,0,0},	/* exit */
+  {12,0,a3,0,0,0},	/* jmp */
+  {13,2,a3,0,0,0},	/* jmpi.f */
+  {13,1,a3,0,0,0},	/* jmpi.t */
+  {14,2,a3,0,0,0},	/* jmpa.f */
+  {14,1,a3,0,0,0},	/* jmpa.t */
+  {15,2,a3,0,0,0},	/* jmps.f */
+  {15,1,a3,0,0,0},	/* jmps.t */
+  {16,0,a3,0,0,0},	/* tac */
+  {17,0,a1r,A,0,0},	/* ldea */
+  {18,8,a1l,VLS,0,0},	/* ld.l */
+  {18,9,a1l,VM,0,0},	/* ld.x */
+  {19,0,a3,0,0,0},	/* tas */
+  {20,0,a3,0,0,0},	/* pshea */
+  {21,8,a2l,VLS,0,0},	/* st.l */
+  {21,9,a2l,VM,0,0},	/* st.x */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {22,0,a3,0,0,0},	/* call */
+  {23,0,a3,0,0,0},	/* calls */
+  {24,0,a3,0,0,0},	/* callq */
+  {25,0,a1r,A,0,0},	/* pfork */
+  {26,5,a2r,S,0,0},	/* ste.b */
+  {26,6,a2r,S,0,0},	/* ste.h */
+  {26,7,a2r,S,0,0},	/* ste.w */
+  {26,8,a2r,S,0,0},	/* ste.l */
+  {18,5,a1r,A,0,0},	/* ld.b */
+  {18,6,a1r,A,0,0},	/* ld.h */
+  {18,7,a1r,A,0,0},	/* ld.w */
+  {27,7,a1r,A,0,0},	/* incr.w */
+  {21,5,a2r,A,0,0},	/* st.b */
+  {21,6,a2r,A,0,0},	/* st.h */
+  {21,7,a2r,A,0,0},	/* st.w */
+  {27,8,a1r,S,0,0},	/* incr.l */
+  {18,5,a1r,S,0,0},	/* ld.b */
+  {18,6,a1r,S,0,0},	/* ld.h */
+  {18,7,a1r,S,0,0},	/* ld.w */
+  {18,8,a1r,S,0,0},	/* ld.l */
+  {21,5,a2r,S,0,0},	/* st.b */
+  {21,6,a2r,S,0,0},	/* st.h */
+  {21,7,a2r,S,0,0},	/* st.w */
+  {21,8,a2r,S,0,0},	/* st.l */
+  {18,5,a1r,V,0,0},	/* ld.b */
+  {18,6,a1r,V,0,0},	/* ld.h */
+  {18,7,a1r,V,0,0},	/* ld.w */
+  {18,8,a1r,V,0,0},	/* ld.l */
+  {21,5,a2r,V,0,0},	/* st.b */
+  {21,6,a2r,V,0,0},	/* st.h */
+  {21,7,a2r,V,0,0},	/* st.w */
+  {21,8,a2r,V,0,0},	/* st.l */
+};
+
+const struct formstr format2[] = {
+  {28,5,rr,A,A,0},	/* cvtw.b */
+  {28,6,rr,A,A,0},	/* cvtw.h */
+  {29,7,rr,A,A,0},	/* cvtb.w */
+  {30,7,rr,A,A,0},	/* cvth.w */
+  {28,5,rr,S,S,0},	/* cvtw.b */
+  {28,6,rr,S,S,0},	/* cvtw.h */
+  {29,7,rr,S,S,0},	/* cvtb.w */
+  {30,7,rr,S,S,0},	/* cvth.w */
+  {28,3,rr,S,S,0},	/* cvtw.s */
+  {31,7,rr,S,S,0},	/* cvts.w */
+  {32,3,rr,S,S,0},	/* cvtd.s */
+  {31,4,rr,S,S,0},	/* cvts.d */
+  {31,8,rr,S,S,0},	/* cvts.l */
+  {32,8,rr,S,S,0},	/* cvtd.l */
+  {33,3,rr,S,S,0},	/* cvtl.s */
+  {33,4,rr,S,S,0},	/* cvtl.d */
+  {34,0,rr,A,A,0},	/* ldpa */
+  {8,0,nr,A,0,0},	/* shf */
+  {18,6,nr,A,0,0},	/* ld.h */
+  {18,7,nr,A,0,0},	/* ld.w */
+  {33,7,rr,S,S,0},	/* cvtl.w */
+  {28,8,rr,S,S,0},	/* cvtw.l */
+  {35,1,rr,S,S,0},	/* plc.t */
+  {36,0,rr,S,S,0},	/* tzc */
+  {37,6,rr,A,A,0},	/* eq.h */
+  {37,7,rr,A,A,0},	/* eq.w */
+  {37,6,nr,A,0,0},	/* eq.h */
+  {37,7,nr,A,0,0},	/* eq.w */
+  {37,5,rr,S,S,0},	/* eq.b */
+  {37,6,rr,S,S,0},	/* eq.h */
+  {37,7,rr,S,S,0},	/* eq.w */
+  {37,8,rr,S,S,0},	/* eq.l */
+  {38,6,rr,A,A,0},	/* leu.h */
+  {38,7,rr,A,A,0},	/* leu.w */
+  {38,6,nr,A,0,0},	/* leu.h */
+  {38,7,nr,A,0,0},	/* leu.w */
+  {38,5,rr,S,S,0},	/* leu.b */
+  {38,6,rr,S,S,0},	/* leu.h */
+  {38,7,rr,S,S,0},	/* leu.w */
+  {38,8,rr,S,S,0},	/* leu.l */
+  {39,6,rr,A,A,0},	/* ltu.h */
+  {39,7,rr,A,A,0},	/* ltu.w */
+  {39,6,nr,A,0,0},	/* ltu.h */
+  {39,7,nr,A,0,0},	/* ltu.w */
+  {39,5,rr,S,S,0},	/* ltu.b */
+  {39,6,rr,S,S,0},	/* ltu.h */
+  {39,7,rr,S,S,0},	/* ltu.w */
+  {39,8,rr,S,S,0},	/* ltu.l */
+  {40,6,rr,A,A,0},	/* le.h */
+  {40,7,rr,A,A,0},	/* le.w */
+  {40,6,nr,A,0,0},	/* le.h */
+  {40,7,nr,A,0,0},	/* le.w */
+  {40,5,rr,S,S,0},	/* le.b */
+  {40,6,rr,S,S,0},	/* le.h */
+  {40,7,rr,S,S,0},	/* le.w */
+  {40,8,rr,S,S,0},	/* le.l */
+  {41,6,rr,A,A,0},	/* lt.h */
+  {41,7,rr,A,A,0},	/* lt.w */
+  {41,6,nr,A,0,0},	/* lt.h */
+  {41,7,nr,A,0,0},	/* lt.w */
+  {41,5,rr,S,S,0},	/* lt.b */
+  {41,6,rr,S,S,0},	/* lt.h */
+  {41,7,rr,S,S,0},	/* lt.w */
+  {41,8,rr,S,S,0},	/* lt.l */
+  {9,7,rr,S,A,0},	/* add.w */
+  {8,0,rr,A,A,0},	/* shf */
+  {0,0,rr,A,A,0},	/* mov */
+  {0,0,rr,S,A,0},	/* mov */
+  {0,7,rr,S,S,0},	/* mov.w */
+  {8,0,rr,S,S,0},	/* shf */
+  {0,0,rr,S,S,0},	/* mov */
+  {0,0,rr,A,S,0},	/* mov */
+  {5,0,rr,A,A,0},	/* and */
+  {6,0,rr,A,A,0},	/* or */
+  {7,0,rr,A,A,0},	/* xor */
+  {42,0,rr,A,A,0},	/* not */
+  {5,0,rr,S,S,0},	/* and */
+  {6,0,rr,S,S,0},	/* or */
+  {7,0,rr,S,S,0},	/* xor */
+  {42,0,rr,S,S,0},	/* not */
+  {40,3,rr,S,S,0},	/* le.s */
+  {40,4,rr,S,S,0},	/* le.d */
+  {41,3,rr,S,S,0},	/* lt.s */
+  {41,4,rr,S,S,0},	/* lt.d */
+  {9,3,rr,S,S,0},	/* add.s */
+  {9,4,rr,S,S,0},	/* add.d */
+  {10,3,rr,S,S,0},	/* sub.s */
+  {10,4,rr,S,S,0},	/* sub.d */
+  {37,3,rr,S,S,0},	/* eq.s */
+  {37,4,rr,S,S,0},	/* eq.d */
+  {43,6,rr,A,A,0},	/* neg.h */
+  {43,7,rr,A,A,0},	/* neg.w */
+  {3,3,rr,S,S,0},	/* mul.s */
+  {3,4,rr,S,S,0},	/* mul.d */
+  {4,3,rr,S,S,0},	/* div.s */
+  {4,4,rr,S,S,0},	/* div.d */
+  {9,6,rr,A,A,0},	/* add.h */
+  {9,7,rr,A,A,0},	/* add.w */
+  {9,6,nr,A,0,0},	/* add.h */
+  {9,7,nr,A,0,0},	/* add.w */
+  {9,5,rr,S,S,0},	/* add.b */
+  {9,6,rr,S,S,0},	/* add.h */
+  {9,7,rr,S,S,0},	/* add.w */
+  {9,8,rr,S,S,0},	/* add.l */
+  {10,6,rr,A,A,0},	/* sub.h */
+  {10,7,rr,A,A,0},	/* sub.w */
+  {10,6,nr,A,0,0},	/* sub.h */
+  {10,7,nr,A,0,0},	/* sub.w */
+  {10,5,rr,S,S,0},	/* sub.b */
+  {10,6,rr,S,S,0},	/* sub.h */
+  {10,7,rr,S,S,0},	/* sub.w */
+  {10,8,rr,S,S,0},	/* sub.l */
+  {3,6,rr,A,A,0},	/* mul.h */
+  {3,7,rr,A,A,0},	/* mul.w */
+  {3,6,nr,A,0,0},	/* mul.h */
+  {3,7,nr,A,0,0},	/* mul.w */
+  {3,5,rr,S,S,0},	/* mul.b */
+  {3,6,rr,S,S,0},	/* mul.h */
+  {3,7,rr,S,S,0},	/* mul.w */
+  {3,8,rr,S,S,0},	/* mul.l */
+  {4,6,rr,A,A,0},	/* div.h */
+  {4,7,rr,A,A,0},	/* div.w */
+  {4,6,nr,A,0,0},	/* div.h */
+  {4,7,nr,A,0,0},	/* div.w */
+  {4,5,rr,S,S,0},	/* div.b */
+  {4,6,rr,S,S,0},	/* div.h */
+  {4,7,rr,S,S,0},	/* div.w */
+  {4,8,rr,S,S,0},	/* div.l */
+};
+
+const struct formstr format3[] = {
+  {32,3,rr,V,V,0},	/* cvtd.s */
+  {31,4,rr,V,V,0},	/* cvts.d */
+  {33,4,rr,V,V,0},	/* cvtl.d */
+  {32,8,rr,V,V,0},	/* cvtd.l */
+  {0,0,rrl,S,S,VM},	/* mov */
+  {0,0,rlr,S,VM,S},	/* mov */
+  {0,0,0,0,0,0},
+  {44,0,rr,S,S,0},	/* lop */
+  {36,0,rr,V,V,0},	/* tzc */
+  {44,0,rr,V,V,0},	/* lop */
+  {0,0,0,0,0,0},
+  {42,0,rr,V,V,0},	/* not */
+  {8,0,rr,S,V,0},	/* shf */
+  {35,1,rr,V,V,0},	/* plc.t */
+  {45,2,rr,V,V,0},	/* cprs.f */
+  {45,1,rr,V,V,0},	/* cprs.t */
+  {37,3,rr,V,V,0},	/* eq.s */
+  {37,4,rr,V,V,0},	/* eq.d */
+  {43,3,rr,V,V,0},	/* neg.s */
+  {43,4,rr,V,V,0},	/* neg.d */
+  {37,3,rr,S,V,0},	/* eq.s */
+  {37,4,rr,S,V,0},	/* eq.d */
+  {43,3,rr,S,S,0},	/* neg.s */
+  {43,4,rr,S,S,0},	/* neg.d */
+  {40,3,rr,V,V,0},	/* le.s */
+  {40,4,rr,V,V,0},	/* le.d */
+  {41,3,rr,V,V,0},	/* lt.s */
+  {41,4,rr,V,V,0},	/* lt.d */
+  {40,3,rr,S,V,0},	/* le.s */
+  {40,4,rr,S,V,0},	/* le.d */
+  {41,3,rr,S,V,0},	/* lt.s */
+  {41,4,rr,S,V,0},	/* lt.d */
+  {37,5,rr,V,V,0},	/* eq.b */
+  {37,6,rr,V,V,0},	/* eq.h */
+  {37,7,rr,V,V,0},	/* eq.w */
+  {37,8,rr,V,V,0},	/* eq.l */
+  {37,5,rr,S,V,0},	/* eq.b */
+  {37,6,rr,S,V,0},	/* eq.h */
+  {37,7,rr,S,V,0},	/* eq.w */
+  {37,8,rr,S,V,0},	/* eq.l */
+  {40,5,rr,V,V,0},	/* le.b */
+  {40,6,rr,V,V,0},	/* le.h */
+  {40,7,rr,V,V,0},	/* le.w */
+  {40,8,rr,V,V,0},	/* le.l */
+  {40,5,rr,S,V,0},	/* le.b */
+  {40,6,rr,S,V,0},	/* le.h */
+  {40,7,rr,S,V,0},	/* le.w */
+  {40,8,rr,S,V,0},	/* le.l */
+  {41,5,rr,V,V,0},	/* lt.b */
+  {41,6,rr,V,V,0},	/* lt.h */
+  {41,7,rr,V,V,0},	/* lt.w */
+  {41,8,rr,V,V,0},	/* lt.l */
+  {41,5,rr,S,V,0},	/* lt.b */
+  {41,6,rr,S,V,0},	/* lt.h */
+  {41,7,rr,S,V,0},	/* lt.w */
+  {41,8,rr,S,V,0},	/* lt.l */
+  {43,5,rr,V,V,0},	/* neg.b */
+  {43,6,rr,V,V,0},	/* neg.h */
+  {43,7,rr,V,V,0},	/* neg.w */
+  {43,8,rr,V,V,0},	/* neg.l */
+  {43,5,rr,S,S,0},	/* neg.b */
+  {43,6,rr,S,S,0},	/* neg.h */
+  {43,7,rr,S,S,0},	/* neg.w */
+  {43,8,rr,S,S,0},	/* neg.l */
+};
+
+const struct formstr format4[] = {
+  {46,0,nops,0,0,0},	/* nop */
+  {47,0,pcrel,0,0,0},	/* br */
+  {48,2,pcrel,0,0,0},	/* bri.f */
+  {48,1,pcrel,0,0,0},	/* bri.t */
+  {49,2,pcrel,0,0,0},	/* bra.f */
+  {49,1,pcrel,0,0,0},	/* bra.t */
+  {50,2,pcrel,0,0,0},	/* brs.f */
+  {50,1,pcrel,0,0,0},	/* brs.t */
+};
+
+const struct formstr format5[] = {
+  {51,5,rr,V,V,0},	/* ldvi.b */
+  {51,6,rr,V,V,0},	/* ldvi.h */
+  {51,7,rr,V,V,0},	/* ldvi.w */
+  {51,8,rr,V,V,0},	/* ldvi.l */
+  {28,3,rr,V,V,0},	/* cvtw.s */
+  {31,7,rr,V,V,0},	/* cvts.w */
+  {28,8,rr,V,V,0},	/* cvtw.l */
+  {33,7,rr,V,V,0},	/* cvtl.w */
+  {52,5,rxr,V,V,0},	/* stvi.b */
+  {52,6,rxr,V,V,0},	/* stvi.h */
+  {52,7,rxr,V,V,0},	/* stvi.w */
+  {52,8,rxr,V,V,0},	/* stvi.l */
+  {52,5,rxr,S,V,0},	/* stvi.b */
+  {52,6,rxr,S,V,0},	/* stvi.h */
+  {52,7,rxr,S,V,0},	/* stvi.w */
+  {52,8,rxr,S,V,0},	/* stvi.l */
+};
+
+const struct formstr format6[] = {
+  {53,0,r,A,0,0},	/* ldsdr */
+  {54,0,r,A,0,0},	/* ldkdr */
+  {55,3,r,S,0,0},	/* ln.s */
+  {55,4,r,S,0,0},	/* ln.d */
+  {56,0,nops,0,0,0},	/* patu */
+  {57,0,r,A,0,0},	/* pate */
+  {58,0,nops,0,0,0},	/* pich */
+  {59,0,nops,0,0,0},	/* plch */
+  {0,0,lr,PSW,A,0},	/* mov */
+  {0,0,rxl,A,PSW,0},	/* mov */
+  {0,0,lr,PC,A,0},	/* mov */
+  {60,0,r,S,0,0},	/* idle */
+  {0,0,lr,ITR,S,0},	/* mov */
+  {0,0,rxl,S,ITR,0},	/* mov */
+  {0,0,0,0,0,0},
+  {0,0,rxl,S,ITSR,0},	/* mov */
+  {61,0,nops,0,0,0},	/* rtnq */
+  {62,0,nops,0,0,0},	/* cfork */
+  {63,0,nops,0,0,0},	/* rtn */
+  {64,0,nops,0,0,0},	/* wfork */
+  {65,0,nops,0,0,0},	/* join */
+  {66,0,nops,0,0,0},	/* rtnc */
+  {67,3,r,S,0,0},	/* exp.s */
+  {67,4,r,S,0,0},	/* exp.d */
+  {68,3,r,S,0,0},	/* sin.s */
+  {68,4,r,S,0,0},	/* sin.d */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {69,3,r,S,0,0},	/* cos.s */
+  {69,4,r,S,0,0},	/* cos.d */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {70,7,r,A,0,0},	/* psh.w */
+  {0,0,0,0,0,0},
+  {71,7,r,A,0,0},	/* pop.w */
+  {0,0,0,0,0,0},
+  {70,7,r,S,0,0},	/* psh.w */
+  {70,8,r,S,0,0},	/* psh.l */
+  {71,7,r,S,0,0},	/* pop.w */
+  {71,8,r,S,0,0},	/* pop.l */
+  {72,0,nops,0,0,0},	/* eni */
+  {73,0,nops,0,0,0},	/* dsi */
+  {74,0,nops,0,0,0},	/* bkpt */
+  {75,0,nops,0,0,0},	/* msync */
+  {76,0,r,S,0,0},	/* mski */
+  {77,0,r,S,0,0},	/* xmti */
+  {0,0,rxl,S,VV,0},	/* mov */
+  {78,0,nops,0,0,0},	/* tstvv */
+  {0,0,lr,VS,A,0},	/* mov */
+  {0,0,rxl,A,VS,0},	/* mov */
+  {0,0,lr,VL,A,0},	/* mov */
+  {0,0,rxl,A,VL,0},	/* mov */
+  {0,7,lr,VS,S,0},	/* mov.w */
+  {0,7,rxl,S,VS,0},	/* mov.w */
+  {0,7,lr,VL,S,0},	/* mov.w */
+  {0,7,rxl,S,VL,0},	/* mov.w */
+  {79,0,r,A,0,0},	/* diag */
+  {80,0,nops,0,0,0},	/* pbkpt */
+  {81,3,r,S,0,0},	/* sqrt.s */
+  {81,4,r,S,0,0},	/* sqrt.d */
+  {82,0,nops,0,0,0},	/* casr */
+  {0,0,0,0,0,0},
+  {83,3,r,S,0,0},	/* atan.s */
+  {83,4,r,S,0,0},	/* atan.d */
+};
+
+const struct formstr format7[] = {
+  {84,5,r,V,0,0},	/* sum.b */
+  {84,6,r,V,0,0},	/* sum.h */
+  {84,7,r,V,0,0},	/* sum.w */
+  {84,8,r,V,0,0},	/* sum.l */
+  {85,0,r,V,0,0},	/* all */
+  {86,0,r,V,0,0},	/* any */
+  {87,0,r,V,0,0},	/* parity */
+  {0,0,0,0,0,0},
+  {88,5,r,V,0,0},	/* max.b */
+  {88,6,r,V,0,0},	/* max.h */
+  {88,7,r,V,0,0},	/* max.w */
+  {88,8,r,V,0,0},	/* max.l */
+  {89,5,r,V,0,0},	/* min.b */
+  {89,6,r,V,0,0},	/* min.h */
+  {89,7,r,V,0,0},	/* min.w */
+  {89,8,r,V,0,0},	/* min.l */
+  {84,3,r,V,0,0},	/* sum.s */
+  {84,4,r,V,0,0},	/* sum.d */
+  {90,3,r,V,0,0},	/* prod.s */
+  {90,4,r,V,0,0},	/* prod.d */
+  {88,3,r,V,0,0},	/* max.s */
+  {88,4,r,V,0,0},	/* max.d */
+  {89,3,r,V,0,0},	/* min.s */
+  {89,4,r,V,0,0},	/* min.d */
+  {90,5,r,V,0,0},	/* prod.b */
+  {90,6,r,V,0,0},	/* prod.h */
+  {90,7,r,V,0,0},	/* prod.w */
+  {90,8,r,V,0,0},	/* prod.l */
+  {35,2,lr,VM,S,0},	/* plc.f */
+  {35,1,lr,VM,S,0},	/* plc.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+const struct formstr formatx[] = {
+  {0,0,0,0,0,0},
+};
+
+const struct formstr format1a[] = {
+  {91,0,imr,A,0,0},	/* halt */
+  {92,0,a4,0,0,0},	/* sysc */
+  {18,6,imr,A,0,0},	/* ld.h */
+  {18,7,imr,A,0,0},	/* ld.w */
+  {5,0,imr,A,0,0},	/* and */
+  {6,0,imr,A,0,0},	/* or */
+  {7,0,imr,A,0,0},	/* xor */
+  {8,0,imr,A,0,0},	/* shf */
+  {9,6,imr,A,0,0},	/* add.h */
+  {9,7,imr,A,0,0},	/* add.w */
+  {10,6,imr,A,0,0},	/* sub.h */
+  {10,7,imr,A,0,0},	/* sub.w */
+  {3,6,imr,A,0,0},	/* mul.h */
+  {3,7,imr,A,0,0},	/* mul.w */
+  {4,6,imr,A,0,0},	/* div.h */
+  {4,7,imr,A,0,0},	/* div.w */
+  {18,7,iml,VL,0,0},	/* ld.w */
+  {18,7,iml,VS,0,0},	/* ld.w */
+  {0,0,0,0,0,0},
+  {8,7,imr,S,0,0},	/* shf.w */
+  {93,0,a5,0,0,0},	/* trap */
+  {0,0,0,0,0,0},
+  {37,6,imr,A,0,0},	/* eq.h */
+  {37,7,imr,A,0,0},	/* eq.w */
+  {38,6,imr,A,0,0},	/* leu.h */
+  {38,7,imr,A,0,0},	/* leu.w */
+  {39,6,imr,A,0,0},	/* ltu.h */
+  {39,7,imr,A,0,0},	/* ltu.w */
+  {40,6,imr,A,0,0},	/* le.h */
+  {40,7,imr,A,0,0},	/* le.w */
+  {41,6,imr,A,0,0},	/* lt.h */
+  {41,7,imr,A,0,0},	/* lt.w */
+};
+
+const struct formstr format1b[] = {
+  {18,4,imr,S,0,0},	/* ld.d */
+  {18,10,imr,S,0,0},	/* ld.u */
+  {18,8,imr,S,0,0},	/* ld.l */
+  {18,7,imr,S,0,0},	/* ld.w */
+  {5,0,imr,S,0,0},	/* and */
+  {6,0,imr,S,0,0},	/* or */
+  {7,0,imr,S,0,0},	/* xor */
+  {8,0,imr,S,0,0},	/* shf */
+  {9,6,imr,S,0,0},	/* add.h */
+  {9,7,imr,S,0,0},	/* add.w */
+  {10,6,imr,S,0,0},	/* sub.h */
+  {10,7,imr,S,0,0},	/* sub.w */
+  {3,6,imr,S,0,0},	/* mul.h */
+  {3,7,imr,S,0,0},	/* mul.w */
+  {4,6,imr,S,0,0},	/* div.h */
+  {4,7,imr,S,0,0},	/* div.w */
+  {9,3,imr,S,0,0},	/* add.s */
+  {10,3,imr,S,0,0},	/* sub.s */
+  {3,3,imr,S,0,0},	/* mul.s */
+  {4,3,imr,S,0,0},	/* div.s */
+  {40,3,imr,S,0,0},	/* le.s */
+  {41,3,imr,S,0,0},	/* lt.s */
+  {37,6,imr,S,0,0},	/* eq.h */
+  {37,7,imr,S,0,0},	/* eq.w */
+  {38,6,imr,S,0,0},	/* leu.h */
+  {38,7,imr,S,0,0},	/* leu.w */
+  {39,6,imr,S,0,0},	/* ltu.h */
+  {39,7,imr,S,0,0},	/* ltu.w */
+  {40,6,imr,S,0,0},	/* le.h */
+  {40,7,imr,S,0,0},	/* le.w */
+  {41,6,imr,S,0,0},	/* lt.h */
+  {41,7,imr,S,0,0},	/* lt.w */
+};
+
+const struct formstr e0_format0[] = {
+  {10,3,rrr,S,V,V},	/* sub.s */
+  {10,4,rrr,S,V,V},	/* sub.d */
+  {4,3,rrr,S,V,V},	/* div.s */
+  {4,4,rrr,S,V,V},	/* div.d */
+  {10,11,rrr,S,V,V},	/* sub.s.f */
+  {10,12,rrr,S,V,V},	/* sub.d.f */
+  {4,11,rrr,S,V,V},	/* div.s.f */
+  {4,12,rrr,S,V,V},	/* div.d.f */
+  {3,11,rrr,V,V,V},	/* mul.s.f */
+  {3,12,rrr,V,V,V},	/* mul.d.f */
+  {4,11,rrr,V,V,V},	/* div.s.f */
+  {4,12,rrr,V,V,V},	/* div.d.f */
+  {3,11,rrr,V,S,V},	/* mul.s.f */
+  {3,12,rrr,V,S,V},	/* mul.d.f */
+  {4,11,rrr,V,S,V},	/* div.s.f */
+  {4,12,rrr,V,S,V},	/* div.d.f */
+  {5,2,rrr,V,V,V},	/* and.f */
+  {6,2,rrr,V,V,V},	/* or.f */
+  {7,2,rrr,V,V,V},	/* xor.f */
+  {8,2,rrr,V,V,V},	/* shf.f */
+  {5,2,rrr,V,S,V},	/* and.f */
+  {6,2,rrr,V,S,V},	/* or.f */
+  {7,2,rrr,V,S,V},	/* xor.f */
+  {8,2,rrr,V,S,V},	/* shf.f */
+  {9,11,rrr,V,V,V},	/* add.s.f */
+  {9,12,rrr,V,V,V},	/* add.d.f */
+  {10,11,rrr,V,V,V},	/* sub.s.f */
+  {10,12,rrr,V,V,V},	/* sub.d.f */
+  {9,11,rrr,V,S,V},	/* add.s.f */
+  {9,12,rrr,V,S,V},	/* add.d.f */
+  {10,11,rrr,V,S,V},	/* sub.s.f */
+  {10,12,rrr,V,S,V},	/* sub.d.f */
+  {9,13,rrr,V,V,V},	/* add.b.f */
+  {9,14,rrr,V,V,V},	/* add.h.f */
+  {9,15,rrr,V,V,V},	/* add.w.f */
+  {9,16,rrr,V,V,V},	/* add.l.f */
+  {9,13,rrr,V,S,V},	/* add.b.f */
+  {9,14,rrr,V,S,V},	/* add.h.f */
+  {9,15,rrr,V,S,V},	/* add.w.f */
+  {9,16,rrr,V,S,V},	/* add.l.f */
+  {10,13,rrr,V,V,V},	/* sub.b.f */
+  {10,14,rrr,V,V,V},	/* sub.h.f */
+  {10,15,rrr,V,V,V},	/* sub.w.f */
+  {10,16,rrr,V,V,V},	/* sub.l.f */
+  {10,13,rrr,V,S,V},	/* sub.b.f */
+  {10,14,rrr,V,S,V},	/* sub.h.f */
+  {10,15,rrr,V,S,V},	/* sub.w.f */
+  {10,16,rrr,V,S,V},	/* sub.l.f */
+  {3,13,rrr,V,V,V},	/* mul.b.f */
+  {3,14,rrr,V,V,V},	/* mul.h.f */
+  {3,15,rrr,V,V,V},	/* mul.w.f */
+  {3,16,rrr,V,V,V},	/* mul.l.f */
+  {3,13,rrr,V,S,V},	/* mul.b.f */
+  {3,14,rrr,V,S,V},	/* mul.h.f */
+  {3,15,rrr,V,S,V},	/* mul.w.f */
+  {3,16,rrr,V,S,V},	/* mul.l.f */
+  {4,13,rrr,V,V,V},	/* div.b.f */
+  {4,14,rrr,V,V,V},	/* div.h.f */
+  {4,15,rrr,V,V,V},	/* div.w.f */
+  {4,16,rrr,V,V,V},	/* div.l.f */
+  {4,13,rrr,V,S,V},	/* div.b.f */
+  {4,14,rrr,V,S,V},	/* div.h.f */
+  {4,15,rrr,V,S,V},	/* div.w.f */
+  {4,16,rrr,V,S,V},	/* div.l.f */
+};
+
+const struct formstr e0_format1[] = {
+  {0,0,0,0,0,0},
+  {94,0,a3,0,0,0},	/* tst */
+  {95,0,a3,0,0,0},	/* lck */
+  {96,0,a3,0,0,0},	/* ulk */
+  {17,0,a1r,S,0,0},	/* ldea */
+  {97,0,a1r,A,0,0},	/* spawn */
+  {98,0,a1r,A,0,0},	/* ldcmr */
+  {99,0,a2r,A,0,0},	/* stcmr */
+  {100,0,a1r,A,0,0},	/* popr */
+  {101,0,a2r,A,0,0},	/* pshr */
+  {102,7,a1r,A,0,0},	/* rcvr.w */
+  {103,7,a2r,A,0,0},	/* matm.w */
+  {104,7,a2r,A,0,0},	/* sndr.w */
+  {104,8,a2r,S,0,0},	/* sndr.l */
+  {102,8,a1r,S,0,0},	/* rcvr.l */
+  {103,8,a2r,S,0,0},	/* matm.l */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {105,7,a2r,A,0,0},	/* putr.w */
+  {105,8,a2r,S,0,0},	/* putr.l */
+  {106,7,a1r,A,0,0},	/* getr.w */
+  {106,8,a1r,S,0,0},	/* getr.l */
+  {26,13,a2r,S,0,0},	/* ste.b.f */
+  {26,14,a2r,S,0,0},	/* ste.h.f */
+  {26,15,a2r,S,0,0},	/* ste.w.f */
+  {26,16,a2r,S,0,0},	/* ste.l.f */
+  {107,7,a2r,A,0,0},	/* matr.w */
+  {108,7,a2r,A,0,0},	/* mat.w */
+  {109,7,a1r,A,0,0},	/* get.w */
+  {110,7,a1r,A,0,0},	/* rcv.w */
+  {0,0,0,0,0,0},
+  {111,7,a1r,A,0,0},	/* inc.w */
+  {112,7,a2r,A,0,0},	/* put.w */
+  {113,7,a2r,A,0,0},	/* snd.w */
+  {107,8,a2r,S,0,0},	/* matr.l */
+  {108,8,a2r,S,0,0},	/* mat.l */
+  {109,8,a1r,S,0,0},	/* get.l */
+  {110,8,a1r,S,0,0},	/* rcv.l */
+  {0,0,0,0,0,0},
+  {111,8,a1r,S,0,0},	/* inc.l */
+  {112,8,a2r,S,0,0},	/* put.l */
+  {113,8,a2r,S,0,0},	/* snd.l */
+  {18,13,a1r,V,0,0},	/* ld.b.f */
+  {18,14,a1r,V,0,0},	/* ld.h.f */
+  {18,15,a1r,V,0,0},	/* ld.w.f */
+  {18,16,a1r,V,0,0},	/* ld.l.f */
+  {21,13,a2r,V,0,0},	/* st.b.f */
+  {21,14,a2r,V,0,0},	/* st.h.f */
+  {21,15,a2r,V,0,0},	/* st.w.f */
+  {21,16,a2r,V,0,0},	/* st.l.f */
+};
+
+const struct formstr e0_format2[] = {
+  {28,5,rr,V,V,0},	/* cvtw.b */
+  {28,6,rr,V,V,0},	/* cvtw.h */
+  {29,7,rr,V,V,0},	/* cvtb.w */
+  {30,7,rr,V,V,0},	/* cvth.w */
+  {28,13,rr,V,V,0},	/* cvtw.b.f */
+  {28,14,rr,V,V,0},	/* cvtw.h.f */
+  {29,15,rr,V,V,0},	/* cvtb.w.f */
+  {30,15,rr,V,V,0},	/* cvth.w.f */
+  {31,8,rr,V,V,0},	/* cvts.l */
+  {32,7,rr,V,V,0},	/* cvtd.w */
+  {33,3,rr,V,V,0},	/* cvtl.s */
+  {28,4,rr,V,V,0},	/* cvtw.d */
+  {31,16,rr,V,V,0},	/* cvts.l.f */
+  {32,15,rr,V,V,0},	/* cvtd.w.f */
+  {33,11,rr,V,V,0},	/* cvtl.s.f */
+  {28,12,rr,V,V,0},	/* cvtw.d.f */
+  {114,0,rr,S,S,0},	/* enal */
+  {8,7,rr,S,S,0},	/* shf.w */
+  {115,0,rr,S,S,0},	/* enag */
+  {0,0,0,0,0,0},
+  {28,4,rr,S,S,0},	/* cvtw.d */
+  {32,7,rr,S,S,0},	/* cvtd.w */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {116,3,rr,S,S,0},	/* frint.s */
+  {116,4,rr,S,S,0},	/* frint.d */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {116,3,rr,V,V,0},	/* frint.s */
+  {116,4,rr,V,V,0},	/* frint.d */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {116,11,rr,V,V,0},	/* frint.s.f */
+  {116,12,rr,V,V,0},	/* frint.d.f */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {81,3,rr,V,V,0},	/* sqrt.s */
+  {81,4,rr,V,V,0},	/* sqrt.d */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {81,11,rr,V,V,0},	/* sqrt.s.f */
+  {81,12,rr,V,V,0},	/* sqrt.d.f */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+const struct formstr e0_format3[] = {
+  {32,11,rr,V,V,0},	/* cvtd.s.f */
+  {31,12,rr,V,V,0},	/* cvts.d.f */
+  {33,12,rr,V,V,0},	/* cvtl.d.f */
+  {32,16,rr,V,V,0},	/* cvtd.l.f */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {36,2,rr,V,V,0},	/* tzc.f */
+  {44,2,rr,V,V,0},	/* lop.f */
+  {117,2,rr,V,V,0},	/* xpnd.f */
+  {42,2,rr,V,V,0},	/* not.f */
+  {8,2,rr,S,V,0},	/* shf.f */
+  {35,17,rr,V,V,0},	/* plc.t.f */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {37,11,rr,V,V,0},	/* eq.s.f */
+  {37,12,rr,V,V,0},	/* eq.d.f */
+  {43,11,rr,V,V,0},	/* neg.s.f */
+  {43,12,rr,V,V,0},	/* neg.d.f */
+  {37,11,rr,S,V,0},	/* eq.s.f */
+  {37,12,rr,S,V,0},	/* eq.d.f */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {40,11,rr,V,V,0},	/* le.s.f */
+  {40,12,rr,V,V,0},	/* le.d.f */
+  {41,11,rr,V,V,0},	/* lt.s.f */
+  {41,12,rr,V,V,0},	/* lt.d.f */
+  {40,11,rr,S,V,0},	/* le.s.f */
+  {40,12,rr,S,V,0},	/* le.d.f */
+  {41,11,rr,S,V,0},	/* lt.s.f */
+  {41,12,rr,S,V,0},	/* lt.d.f */
+  {37,13,rr,V,V,0},	/* eq.b.f */
+  {37,14,rr,V,V,0},	/* eq.h.f */
+  {37,15,rr,V,V,0},	/* eq.w.f */
+  {37,16,rr,V,V,0},	/* eq.l.f */
+  {37,13,rr,S,V,0},	/* eq.b.f */
+  {37,14,rr,S,V,0},	/* eq.h.f */
+  {37,15,rr,S,V,0},	/* eq.w.f */
+  {37,16,rr,S,V,0},	/* eq.l.f */
+  {40,13,rr,V,V,0},	/* le.b.f */
+  {40,14,rr,V,V,0},	/* le.h.f */
+  {40,15,rr,V,V,0},	/* le.w.f */
+  {40,16,rr,V,V,0},	/* le.l.f */
+  {40,13,rr,S,V,0},	/* le.b.f */
+  {40,14,rr,S,V,0},	/* le.h.f */
+  {40,15,rr,S,V,0},	/* le.w.f */
+  {40,16,rr,S,V,0},	/* le.l.f */
+  {41,13,rr,V,V,0},	/* lt.b.f */
+  {41,14,rr,V,V,0},	/* lt.h.f */
+  {41,15,rr,V,V,0},	/* lt.w.f */
+  {41,16,rr,V,V,0},	/* lt.l.f */
+  {41,13,rr,S,V,0},	/* lt.b.f */
+  {41,14,rr,S,V,0},	/* lt.h.f */
+  {41,15,rr,S,V,0},	/* lt.w.f */
+  {41,16,rr,S,V,0},	/* lt.l.f */
+  {43,13,rr,V,V,0},	/* neg.b.f */
+  {43,14,rr,V,V,0},	/* neg.h.f */
+  {43,15,rr,V,V,0},	/* neg.w.f */
+  {43,16,rr,V,V,0},	/* neg.l.f */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+const struct formstr e0_format4[] = {
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+const struct formstr e0_format5[] = {
+  {51,13,rr,V,V,0},	/* ldvi.b.f */
+  {51,14,rr,V,V,0},	/* ldvi.h.f */
+  {51,15,rr,V,V,0},	/* ldvi.w.f */
+  {51,16,rr,V,V,0},	/* ldvi.l.f */
+  {28,11,rr,V,V,0},	/* cvtw.s.f */
+  {31,15,rr,V,V,0},	/* cvts.w.f */
+  {28,16,rr,V,V,0},	/* cvtw.l.f */
+  {33,15,rr,V,V,0},	/* cvtl.w.f */
+  {52,13,rxr,V,V,0},	/* stvi.b.f */
+  {52,14,rxr,V,V,0},	/* stvi.h.f */
+  {52,15,rxr,V,V,0},	/* stvi.w.f */
+  {52,16,rxr,V,V,0},	/* stvi.l.f */
+  {52,13,rxr,S,V,0},	/* stvi.b.f */
+  {52,14,rxr,S,V,0},	/* stvi.h.f */
+  {52,15,rxr,S,V,0},	/* stvi.w.f */
+  {52,16,rxr,S,V,0},	/* stvi.l.f */
+};
+
+const struct formstr e0_format6[] = {
+  {0,0,rxl,S,CIR,0},	/* mov */
+  {0,0,lr,CIR,S,0},	/* mov */
+  {0,0,lr,TOC,S,0},	/* mov */
+  {0,0,lr,CPUID,S,0},	/* mov */
+  {0,0,rxl,S,TTR,0},	/* mov */
+  {0,0,lr,TTR,S,0},	/* mov */
+  {118,0,nops,0,0,0},	/* ctrsl */
+  {119,0,nops,0,0,0},	/* ctrsg */
+  {0,0,rxl,S,VMU,0},	/* mov */
+  {0,0,lr,VMU,S,0},	/* mov */
+  {0,0,rxl,S,VML,0},	/* mov */
+  {0,0,lr,VML,S,0},	/* mov */
+  {0,0,rxl,S,ICR,0},	/* mov */
+  {0,0,lr,ICR,S,0},	/* mov */
+  {0,0,rxl,S,TCPU,0},	/* mov */
+  {0,0,lr,TCPU,S,0},	/* mov */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {120,0,nops,0,0,0},	/* stop */
+  {0,0,0,0,0,0},
+  {0,0,rxl,S,TID,0},	/* mov */
+  {0,0,lr,TID,S,0},	/* mov */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+const struct formstr e0_format7[] = {
+  {84,13,r,V,0,0},	/* sum.b.f */
+  {84,14,r,V,0,0},	/* sum.h.f */
+  {84,15,r,V,0,0},	/* sum.w.f */
+  {84,16,r,V,0,0},	/* sum.l.f */
+  {85,2,r,V,0,0},	/* all.f */
+  {86,2,r,V,0,0},	/* any.f */
+  {87,2,r,V,0,0},	/* parity.f */
+  {0,0,0,0,0,0},
+  {88,13,r,V,0,0},	/* max.b.f */
+  {88,14,r,V,0,0},	/* max.h.f */
+  {88,15,r,V,0,0},	/* max.w.f */
+  {88,16,r,V,0,0},	/* max.l.f */
+  {89,13,r,V,0,0},	/* min.b.f */
+  {89,14,r,V,0,0},	/* min.h.f */
+  {89,15,r,V,0,0},	/* min.w.f */
+  {89,16,r,V,0,0},	/* min.l.f */
+  {84,11,r,V,0,0},	/* sum.s.f */
+  {84,12,r,V,0,0},	/* sum.d.f */
+  {90,11,r,V,0,0},	/* prod.s.f */
+  {90,12,r,V,0,0},	/* prod.d.f */
+  {88,11,r,V,0,0},	/* max.s.f */
+  {88,12,r,V,0,0},	/* max.d.f */
+  {89,11,r,V,0,0},	/* min.s.f */
+  {89,12,r,V,0,0},	/* min.d.f */
+  {90,13,r,V,0,0},	/* prod.b.f */
+  {90,14,r,V,0,0},	/* prod.h.f */
+  {90,15,r,V,0,0},	/* prod.w.f */
+  {90,16,r,V,0,0},	/* prod.l.f */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+const struct formstr e1_format0[] = {
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {10,18,rrr,S,V,V},	/* sub.s.t */
+  {10,19,rrr,S,V,V},	/* sub.d.t */
+  {4,18,rrr,S,V,V},	/* div.s.t */
+  {4,19,rrr,S,V,V},	/* div.d.t */
+  {3,18,rrr,V,V,V},	/* mul.s.t */
+  {3,19,rrr,V,V,V},	/* mul.d.t */
+  {4,18,rrr,V,V,V},	/* div.s.t */
+  {4,19,rrr,V,V,V},	/* div.d.t */
+  {3,18,rrr,V,S,V},	/* mul.s.t */
+  {3,19,rrr,V,S,V},	/* mul.d.t */
+  {4,18,rrr,V,S,V},	/* div.s.t */
+  {4,19,rrr,V,S,V},	/* div.d.t */
+  {5,1,rrr,V,V,V},	/* and.t */
+  {6,1,rrr,V,V,V},	/* or.t */
+  {7,1,rrr,V,V,V},	/* xor.t */
+  {8,1,rrr,V,V,V},	/* shf.t */
+  {5,1,rrr,V,S,V},	/* and.t */
+  {6,1,rrr,V,S,V},	/* or.t */
+  {7,1,rrr,V,S,V},	/* xor.t */
+  {8,1,rrr,V,S,V},	/* shf.t */
+  {9,18,rrr,V,V,V},	/* add.s.t */
+  {9,19,rrr,V,V,V},	/* add.d.t */
+  {10,18,rrr,V,V,V},	/* sub.s.t */
+  {10,19,rrr,V,V,V},	/* sub.d.t */
+  {9,18,rrr,V,S,V},	/* add.s.t */
+  {9,19,rrr,V,S,V},	/* add.d.t */
+  {10,18,rrr,V,S,V},	/* sub.s.t */
+  {10,19,rrr,V,S,V},	/* sub.d.t */
+  {9,20,rrr,V,V,V},	/* add.b.t */
+  {9,21,rrr,V,V,V},	/* add.h.t */
+  {9,22,rrr,V,V,V},	/* add.w.t */
+  {9,23,rrr,V,V,V},	/* add.l.t */
+  {9,20,rrr,V,S,V},	/* add.b.t */
+  {9,21,rrr,V,S,V},	/* add.h.t */
+  {9,22,rrr,V,S,V},	/* add.w.t */
+  {9,23,rrr,V,S,V},	/* add.l.t */
+  {10,20,rrr,V,V,V},	/* sub.b.t */
+  {10,21,rrr,V,V,V},	/* sub.h.t */
+  {10,22,rrr,V,V,V},	/* sub.w.t */
+  {10,23,rrr,V,V,V},	/* sub.l.t */
+  {10,20,rrr,V,S,V},	/* sub.b.t */
+  {10,21,rrr,V,S,V},	/* sub.h.t */
+  {10,22,rrr,V,S,V},	/* sub.w.t */
+  {10,23,rrr,V,S,V},	/* sub.l.t */
+  {3,20,rrr,V,V,V},	/* mul.b.t */
+  {3,21,rrr,V,V,V},	/* mul.h.t */
+  {3,22,rrr,V,V,V},	/* mul.w.t */
+  {3,23,rrr,V,V,V},	/* mul.l.t */
+  {3,20,rrr,V,S,V},	/* mul.b.t */
+  {3,21,rrr,V,S,V},	/* mul.h.t */
+  {3,22,rrr,V,S,V},	/* mul.w.t */
+  {3,23,rrr,V,S,V},	/* mul.l.t */
+  {4,20,rrr,V,V,V},	/* div.b.t */
+  {4,21,rrr,V,V,V},	/* div.h.t */
+  {4,22,rrr,V,V,V},	/* div.w.t */
+  {4,23,rrr,V,V,V},	/* div.l.t */
+  {4,20,rrr,V,S,V},	/* div.b.t */
+  {4,21,rrr,V,S,V},	/* div.h.t */
+  {4,22,rrr,V,S,V},	/* div.w.t */
+  {4,23,rrr,V,S,V},	/* div.l.t */
+};
+
+const struct formstr e1_format1[] = {
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {26,20,a2r,S,0,0},	/* ste.b.t */
+  {26,21,a2r,S,0,0},	/* ste.h.t */
+  {26,22,a2r,S,0,0},	/* ste.w.t */
+  {26,23,a2r,S,0,0},	/* ste.l.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {18,20,a1r,V,0,0},	/* ld.b.t */
+  {18,21,a1r,V,0,0},	/* ld.h.t */
+  {18,22,a1r,V,0,0},	/* ld.w.t */
+  {18,23,a1r,V,0,0},	/* ld.l.t */
+  {21,20,a2r,V,0,0},	/* st.b.t */
+  {21,21,a2r,V,0,0},	/* st.h.t */
+  {21,22,a2r,V,0,0},	/* st.w.t */
+  {21,23,a2r,V,0,0},	/* st.l.t */
+};
+
+const struct formstr e1_format2[] = {
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {28,20,rr,V,V,0},	/* cvtw.b.t */
+  {28,21,rr,V,V,0},	/* cvtw.h.t */
+  {29,22,rr,V,V,0},	/* cvtb.w.t */
+  {30,22,rr,V,V,0},	/* cvth.w.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {31,23,rr,V,V,0},	/* cvts.l.t */
+  {32,22,rr,V,V,0},	/* cvtd.w.t */
+  {33,18,rr,V,V,0},	/* cvtl.s.t */
+  {28,19,rr,V,V,0},	/* cvtw.d.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {116,18,rr,V,V,0},	/* frint.s.t */
+  {116,19,rr,V,V,0},	/* frint.d.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {81,18,rr,V,V,0},	/* sqrt.s.t */
+  {81,19,rr,V,V,0},	/* sqrt.d.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+const struct formstr e1_format3[] = {
+  {32,18,rr,V,V,0},	/* cvtd.s.t */
+  {31,19,rr,V,V,0},	/* cvts.d.t */
+  {33,19,rr,V,V,0},	/* cvtl.d.t */
+  {32,23,rr,V,V,0},	/* cvtd.l.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {36,1,rr,V,V,0},	/* tzc.t */
+  {44,1,rr,V,V,0},	/* lop.t */
+  {117,1,rr,V,V,0},	/* xpnd.t */
+  {42,1,rr,V,V,0},	/* not.t */
+  {8,1,rr,S,V,0},	/* shf.t */
+  {35,24,rr,V,V,0},	/* plc.t.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {37,18,rr,V,V,0},	/* eq.s.t */
+  {37,19,rr,V,V,0},	/* eq.d.t */
+  {43,18,rr,V,V,0},	/* neg.s.t */
+  {43,19,rr,V,V,0},	/* neg.d.t */
+  {37,18,rr,S,V,0},	/* eq.s.t */
+  {37,19,rr,S,V,0},	/* eq.d.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {40,18,rr,V,V,0},	/* le.s.t */
+  {40,19,rr,V,V,0},	/* le.d.t */
+  {41,18,rr,V,V,0},	/* lt.s.t */
+  {41,19,rr,V,V,0},	/* lt.d.t */
+  {40,18,rr,S,V,0},	/* le.s.t */
+  {40,19,rr,S,V,0},	/* le.d.t */
+  {41,18,rr,S,V,0},	/* lt.s.t */
+  {41,19,rr,S,V,0},	/* lt.d.t */
+  {37,20,rr,V,V,0},	/* eq.b.t */
+  {37,21,rr,V,V,0},	/* eq.h.t */
+  {37,22,rr,V,V,0},	/* eq.w.t */
+  {37,23,rr,V,V,0},	/* eq.l.t */
+  {37,20,rr,S,V,0},	/* eq.b.t */
+  {37,21,rr,S,V,0},	/* eq.h.t */
+  {37,22,rr,S,V,0},	/* eq.w.t */
+  {37,23,rr,S,V,0},	/* eq.l.t */
+  {40,20,rr,V,V,0},	/* le.b.t */
+  {40,21,rr,V,V,0},	/* le.h.t */
+  {40,22,rr,V,V,0},	/* le.w.t */
+  {40,23,rr,V,V,0},	/* le.l.t */
+  {40,20,rr,S,V,0},	/* le.b.t */
+  {40,21,rr,S,V,0},	/* le.h.t */
+  {40,22,rr,S,V,0},	/* le.w.t */
+  {40,23,rr,S,V,0},	/* le.l.t */
+  {41,20,rr,V,V,0},	/* lt.b.t */
+  {41,21,rr,V,V,0},	/* lt.h.t */
+  {41,22,rr,V,V,0},	/* lt.w.t */
+  {41,23,rr,V,V,0},	/* lt.l.t */
+  {41,20,rr,S,V,0},	/* lt.b.t */
+  {41,21,rr,S,V,0},	/* lt.h.t */
+  {41,22,rr,S,V,0},	/* lt.w.t */
+  {41,23,rr,S,V,0},	/* lt.l.t */
+  {43,20,rr,V,V,0},	/* neg.b.t */
+  {43,21,rr,V,V,0},	/* neg.h.t */
+  {43,22,rr,V,V,0},	/* neg.w.t */
+  {43,23,rr,V,V,0},	/* neg.l.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+const struct formstr e1_format4[] = {
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+const struct formstr e1_format5[] = {
+  {51,20,rr,V,V,0},	/* ldvi.b.t */
+  {51,21,rr,V,V,0},	/* ldvi.h.t */
+  {51,22,rr,V,V,0},	/* ldvi.w.t */
+  {51,23,rr,V,V,0},	/* ldvi.l.t */
+  {28,18,rr,V,V,0},	/* cvtw.s.t */
+  {31,22,rr,V,V,0},	/* cvts.w.t */
+  {28,23,rr,V,V,0},	/* cvtw.l.t */
+  {33,22,rr,V,V,0},	/* cvtl.w.t */
+  {52,20,rxr,V,V,0},	/* stvi.b.t */
+  {52,21,rxr,V,V,0},	/* stvi.h.t */
+  {52,22,rxr,V,V,0},	/* stvi.w.t */
+  {52,23,rxr,V,V,0},	/* stvi.l.t */
+  {52,20,rxr,S,V,0},	/* stvi.b.t */
+  {52,21,rxr,S,V,0},	/* stvi.h.t */
+  {52,22,rxr,S,V,0},	/* stvi.w.t */
+  {52,23,rxr,S,V,0},	/* stvi.l.t */
+};
+
+const struct formstr e1_format6[] = {
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+const struct formstr e1_format7[] = {
+  {84,20,r,V,0,0},	/* sum.b.t */
+  {84,21,r,V,0,0},	/* sum.h.t */
+  {84,22,r,V,0,0},	/* sum.w.t */
+  {84,23,r,V,0,0},	/* sum.l.t */
+  {85,1,r,V,0,0},	/* all.t */
+  {86,1,r,V,0,0},	/* any.t */
+  {87,1,r,V,0,0},	/* parity.t */
+  {0,0,0,0,0,0},
+  {88,20,r,V,0,0},	/* max.b.t */
+  {88,21,r,V,0,0},	/* max.h.t */
+  {88,22,r,V,0,0},	/* max.w.t */
+  {88,23,r,V,0,0},	/* max.l.t */
+  {89,20,r,V,0,0},	/* min.b.t */
+  {89,21,r,V,0,0},	/* min.h.t */
+  {89,22,r,V,0,0},	/* min.w.t */
+  {89,23,r,V,0,0},	/* min.l.t */
+  {84,18,r,V,0,0},	/* sum.s.t */
+  {84,19,r,V,0,0},	/* sum.d.t */
+  {90,18,r,V,0,0},	/* prod.s.t */
+  {90,19,r,V,0,0},	/* prod.d.t */
+  {88,18,r,V,0,0},	/* max.s.t */
+  {88,19,r,V,0,0},	/* max.d.t */
+  {89,18,r,V,0,0},	/* min.s.t */
+  {89,19,r,V,0,0},	/* min.d.t */
+  {90,20,r,V,0,0},	/* prod.b.t */
+  {90,21,r,V,0,0},	/* prod.h.t */
+  {90,22,r,V,0,0},	/* prod.w.t */
+  {90,23,r,V,0,0},	/* prod.l.t */
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+char *lop[] = {
+  "mov",	/* 0 */
+  "merg",	/* 1 */
+  "mask",	/* 2 */
+  "mul",	/* 3 */
+  "div",	/* 4 */
+  "and",	/* 5 */
+  "or",	/* 6 */
+  "xor",	/* 7 */
+  "shf",	/* 8 */
+  "add",	/* 9 */
+  "sub",	/* 10 */
+  "exit",	/* 11 */
+  "jmp",	/* 12 */
+  "jmpi",	/* 13 */
+  "jmpa",	/* 14 */
+  "jmps",	/* 15 */
+  "tac",	/* 16 */
+  "ldea",	/* 17 */
+  "ld",	/* 18 */
+  "tas",	/* 19 */
+  "pshea",	/* 20 */
+  "st",	/* 21 */
+  "call",	/* 22 */
+  "calls",	/* 23 */
+  "callq",	/* 24 */
+  "pfork",	/* 25 */
+  "ste",	/* 26 */
+  "incr",	/* 27 */
+  "cvtw",	/* 28 */
+  "cvtb",	/* 29 */
+  "cvth",	/* 30 */
+  "cvts",	/* 31 */
+  "cvtd",	/* 32 */
+  "cvtl",	/* 33 */
+  "ldpa",	/* 34 */
+  "plc",	/* 35 */
+  "tzc",	/* 36 */
+  "eq",	/* 37 */
+  "leu",	/* 38 */
+  "ltu",	/* 39 */
+  "le",	/* 40 */
+  "lt",	/* 41 */
+  "not",	/* 42 */
+  "neg",	/* 43 */
+  "lop",	/* 44 */
+  "cprs",	/* 45 */
+  "nop",	/* 46 */
+  "br",	/* 47 */
+  "bri",	/* 48 */
+  "bra",	/* 49 */
+  "brs",	/* 50 */
+  "ldvi",	/* 51 */
+  "stvi",	/* 52 */
+  "ldsdr",	/* 53 */
+  "ldkdr",	/* 54 */
+  "ln",	/* 55 */
+  "patu",	/* 56 */
+  "pate",	/* 57 */
+  "pich",	/* 58 */
+  "plch",	/* 59 */
+  "idle",	/* 60 */
+  "rtnq",	/* 61 */
+  "cfork",	/* 62 */
+  "rtn",	/* 63 */
+  "wfork",	/* 64 */
+  "join",	/* 65 */
+  "rtnc",	/* 66 */
+  "exp",	/* 67 */
+  "sin",	/* 68 */
+  "cos",	/* 69 */
+  "psh",	/* 70 */
+  "pop",	/* 71 */
+  "eni",	/* 72 */
+  "dsi",	/* 73 */
+  "bkpt",	/* 74 */
+  "msync",	/* 75 */
+  "mski",	/* 76 */
+  "xmti",	/* 77 */
+  "tstvv",	/* 78 */
+  "diag",	/* 79 */
+  "pbkpt",	/* 80 */
+  "sqrt",	/* 81 */
+  "casr",	/* 82 */
+  "atan",	/* 83 */
+  "sum",	/* 84 */
+  "all",	/* 85 */
+  "any",	/* 86 */
+  "parity",	/* 87 */
+  "max",	/* 88 */
+  "min",	/* 89 */
+  "prod",	/* 90 */
+  "halt",	/* 91 */
+  "sysc",	/* 92 */
+  "trap",	/* 93 */
+  "tst",	/* 94 */
+  "lck",	/* 95 */
+  "ulk",	/* 96 */
+  "spawn",	/* 97 */
+  "ldcmr",	/* 98 */
+  "stcmr",	/* 99 */
+  "popr",	/* 100 */
+  "pshr",	/* 101 */
+  "rcvr",	/* 102 */
+  "matm",	/* 103 */
+  "sndr",	/* 104 */
+  "putr",	/* 105 */
+  "getr",	/* 106 */
+  "matr",	/* 107 */
+  "mat",	/* 108 */
+  "get",	/* 109 */
+  "rcv",	/* 110 */
+  "inc",	/* 111 */
+  "put",	/* 112 */
+  "snd",	/* 113 */
+  "enal",	/* 114 */
+  "enag",	/* 115 */
+  "frint",	/* 116 */
+  "xpnd",	/* 117 */
+  "ctrsl",	/* 118 */
+  "ctrsg",	/* 119 */
+  "stop",	/* 120 */
+};
+
+char *rop[] = {
+  "",	/* 0 */
+  ".t",	/* 1 */
+  ".f",	/* 2 */
+  ".s",	/* 3 */
+  ".d",	/* 4 */
+  ".b",	/* 5 */
+  ".h",	/* 6 */
+  ".w",	/* 7 */
+  ".l",	/* 8 */
+  ".x",	/* 9 */
+  ".u",	/* 10 */
+  ".s.f",	/* 11 */
+  ".d.f",	/* 12 */
+  ".b.f",	/* 13 */
+  ".h.f",	/* 14 */
+  ".w.f",	/* 15 */
+  ".l.f",	/* 16 */
+  ".t.f",	/* 17 */
+  ".s.t",	/* 18 */
+  ".d.t",	/* 19 */
+  ".b.t",	/* 20 */
+  ".h.t",	/* 21 */
+  ".w.t",	/* 22 */
+  ".l.t",	/* 23 */
+  ".t.t",	/* 24 */
+};
diff --git a/binutils-2.25/include/opcode/cr16.h b/binutils-2.25/include/opcode/cr16.h
new file mode 100644
index 00000000..1f1191dc
--- /dev/null
+++ b/binutils-2.25/include/opcode/cr16.h
@@ -0,0 +1,451 @@
+/* cr16.h -- Header file for CR16 opcode and register tables.
+   Copyright 2007, 2008, 2010, 2013 Free Software Foundation, Inc.
+   Contributed by M R Swami Reddy
+
+   This file is part of GAS, GDB and the GNU binutils.
+
+   GAS, GDB, and GNU binutils is free software; you can redistribute it
+   and/or modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GAS, GDB, and GNU binutils are distributed in the hope that they will be
+   useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _CR16_H_
+#define _CR16_H_
+
+/* CR16 core Registers :
+   The enums are used as indices to CR16 registers table (cr16_regtab).
+   Therefore, order MUST be preserved.  */
+
+typedef enum
+{
+  /* 16-bit general purpose registers.  */
+  r0, r1, r2, r3, 
+  r4, r5, r6, r7, 
+  r8, r9, r10, r11, 
+  r12_L = 12, r13_L = 13, ra = 14, sp_L = 15,
+
+  /* 32-bit general purpose registers.  */
+  r12 = 12, r13 = 13, r14 = 14, r15 = 15, 
+  era = 14, sp = 15, RA,
+
+  /* Not a register.  */
+  nullregister,
+  MAX_REG
+}
+reg;
+
+/* CR16 processor registers and special registers :
+   The enums are used as indices to CR16 processor registers table
+   (cr16_pregtab). Therefore, order MUST be preserved.  */
+
+typedef enum
+{
+  /* processor registers.  */
+  dbs = MAX_REG, 
+  dsr, dcrl, dcrh, 
+  car0l, car0h, car1l, car1h, 
+  cfg, psr, intbasel, intbaseh, 
+  ispl, isph, uspl, usph,
+  dcr =  dcrl, 
+  car0 = car0l, 
+  car1 = car1l, 
+  intbase = intbasel, 
+  isp =  ispl, 
+  usp =  uspl,
+  /* Not a processor register.  */
+  nullpregister = usph + 1,
+  MAX_PREG
+}
+preg;
+
+/* CR16 Register types. */
+
+typedef enum
+{
+  CR16_R_REGTYPE,    /* r<N>      */
+  CR16_RP_REGTYPE,   /* reg pair  */
+  CR16_P_REGTYPE     /* Processor register  */
+}
+reg_type;
+
+/* CR16 argument types :
+   The argument types correspond to instructions operands
+
+   Argument types :
+   r - register
+   rp - register pair
+   c - constant
+   i - immediate
+   idxr - index with register
+   idxrp - index with register pair
+   rbase - register base
+   rpbase - register pair base
+   pr - processor register.  */
+
+typedef enum
+{
+  arg_r,
+  arg_c,
+  arg_cr,
+  arg_crp,
+  arg_ic,
+  arg_icr,
+  arg_idxr,
+  arg_idxrp,
+  arg_rbase,
+  arg_rpbase,
+  arg_rp,
+  arg_pr,
+  arg_prp,
+  arg_cc,
+  arg_ra,
+  /* Not an argument.  */
+  nullargs
+}
+argtype;
+
+/* CR16 operand types:The operand types correspond to instructions operands.  */
+
+typedef enum
+{
+  dummy,
+  /* N-bit signed immediate.  */
+  imm3, imm4, imm5, imm6, imm16, imm20, imm32,
+  /* N-bit unsigned immediate.  */
+  uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32,
+  /* N-bit signed displacement.  */
+  disps5, disps17, disps25,
+  /* N-bit unsigned displacement.  */
+  dispe9,
+  /* N-bit absolute address.  */
+  abs20, abs24,
+  /* Register relative.  */
+  rra, rbase, rbase_disps20, rbase_dispe20,
+  /* Register pair relative.  */
+  rpbase_disps0, rpbase_dispe4, rpbase_disps4, rpbase_disps16,
+  rpbase_disps20, rpbase_dispe20,
+  /* Register index.  */
+  rindex7_abs20, rindex8_abs20,
+  /* Register pair index.  */
+  rpindex_disps0, rpindex_disps14, rpindex_disps20,
+  /* register.  */
+  regr, 
+  /* register pair.  */
+  regp, 
+  /* processor register.  */
+  pregr, 
+  /* processor register 32 bit.  */
+  pregrp, 
+  /* condition code - 4 bit.  */
+  cc, 
+  /* Not an operand.  */
+  nulloperand,
+  /* Maximum supported operand.  */
+  MAX_OPRD
+}
+operand_type;
+
+/* CR16 instruction types.  */
+
+#define NO_TYPE_INS       0
+#define ARITH_INS         1
+#define LD_STOR_INS       2
+#define BRANCH_INS        3
+#define ARITH_BYTE_INS    4
+#define SHIFT_INS         5
+#define BRANCH_NEQ_INS    6
+#define LD_STOR_INS_INC   7
+#define STOR_IMM_INS      8
+#define CSTBIT_INS        9
+
+/* Maximum value supported for instruction types.  */
+#define CR16_INS_MAX        (1 << 4)
+/* Mask to record an instruction type.  */
+#define CR16_INS_MASK       (CR16_INS_MAX - 1)
+/* Return instruction type, given instruction's attributes.  */
+#define CR16_INS_TYPE(attr) ((attr) & CR16_INS_MASK)
+
+/* Indicates whether this instruction has a register list as parameter.  */
+#define REG_LIST        CR16_INS_MAX
+
+/* The operands in binary and assembly are placed in reverse order.
+   load - (REVERSE_MATCH)/store - (! REVERSE_MATCH).  */
+#define REVERSE_MATCH  (1 << 5)
+
+/* Printing formats, where the instruction prefix isn't consecutive.  */
+#define FMT_1          (1 << 9)    /* 0xF0F00000 */
+#define FMT_2          (1 << 10)   /* 0xFFF0FF00 */
+#define FMT_3          (1 << 11)   /* 0xFFF00F00 */
+#define FMT_4          (1 << 12)   /* 0xFFF0F000 */
+#define FMT_5          (1 << 13)   /* 0xFFF0FFF0 */
+#define FMT_CR16       (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)
+
+/* Indicates whether this instruction can be relaxed.  */
+#define RELAXABLE      (1 << 14)
+
+/* Indicates that instruction uses user registers (and not 
+   general-purpose registers) as operands.  */
+#define USER_REG       (1 << 15)
+
+
+/* Instruction shouldn't allow 'sp' usage.  */
+#define NO_SP          (1 << 17)
+
+/* Instruction shouldn't allow to push a register which is used as a rptr.  */
+#define NO_RPTR        (1 << 18)
+
+/* Maximum operands per instruction.  */
+#define MAX_OPERANDS     5
+/* Maximum register name length. */
+#define MAX_REGNAME_LEN  10
+/* Maximum instruction length. */
+#define MAX_INST_LEN     256
+
+
+/* Values defined for the flags field of a struct operand_entry.  */
+
+/* Operand must be an unsigned number.  */
+#define OP_UNSIGNED   (1 << 0)
+/* Operand must be a signed number.  */
+#define OP_SIGNED     (1 << 1)
+/* Operand must be a negative number.  */
+#define OP_NEG        (1 << 2)
+/* A special load/stor 4-bit unsigned displacement operand.  */
+#define OP_DEC        (1 << 3)
+/* Operand must be an even number.  */
+#define OP_EVEN       (1 << 4)
+/* Operand is shifted right.  */
+#define OP_SHIFT      (1 << 5)
+/* Operand is shifted right and decremented.  */
+#define OP_SHIFT_DEC  (1 << 6)
+/* Operand has reserved escape sequences.  */
+#define OP_ESC        (1 << 7)
+/* Operand must be a ABS20 number.  */
+#define OP_ABS20      (1 << 8)
+/* Operand must be a ABS24 number.  */
+#define OP_ABS24      (1 << 9)
+/* Operand has reserved escape sequences type 1.  */
+#define OP_ESC1       (1 << 10)
+
+/* Single operand description.  */
+
+typedef struct
+{
+  /* Operand type.  */
+  operand_type op_type;
+  /* Operand location within the opcode.  */
+  unsigned int shift;
+}
+operand_desc;
+
+/* Instruction data structure used in instruction table.  */
+
+typedef struct
+{
+  /* Name.  */
+  const char *mnemonic;
+  /* Size (in words).  */
+  unsigned int size;
+  /* Constant prefix (matched by the disassembler).  */
+  unsigned long match;  /* ie opcode */
+  /* Match size (in bits).  */
+  /* MASK: if( (i & match_bits) == match ) then match */
+  int match_bits;
+  /* Attributes.  */
+  unsigned int flags;
+  /* Operands (always last, so unreferenced operands are initialized).  */
+  operand_desc operands[MAX_OPERANDS];
+}
+inst;
+
+/* Data structure for a single instruction's arguments (Operands).  */
+
+typedef struct
+{
+  /* Register or base register.  */
+  reg r;
+  /* Register pair register.  */
+  reg rp;
+  /* Index register.  */
+  reg i_r;
+  /* Processor register.  */
+  preg pr;
+  /* Processor register. 32 bit  */
+  preg prp;
+  /* Constant/immediate/absolute value.  */
+  long constant;
+  /* CC code.  */
+  unsigned int cc;
+  /* Scaled index mode.  */
+  unsigned int scale;
+  /* Argument type.  */
+  argtype type;
+  /* Size of the argument (in bits) required to represent.  */
+  int size;
+  /* The type of the expression.  */
+  unsigned char X_op;
+}
+argument;
+
+/* Internal structure to hold the various entities
+   corresponding to the current assembling instruction.  */
+
+typedef struct
+{
+  /* Number of arguments.  */
+  int nargs;
+  /* The argument data structure for storing args (operands).  */
+  argument arg[MAX_OPERANDS];
+/* The following fields are required only by CR16-assembler.  */
+#ifdef TC_CR16
+  /* Expression used for setting the fixups (if any).  */
+  expressionS exp;
+  bfd_reloc_code_real_type rtype;
+#endif /* TC_CR16 */
+  /* Instruction size (in bytes).  */
+  int size;
+}
+ins;
+
+/* Structure to hold information about predefined operands.  */
+
+typedef struct
+{
+  /* Size (in bits).  */
+  unsigned int bit_size;
+  /* Argument type.  */
+  argtype arg_type;
+  /* One bit syntax flags.  */
+  int flags;
+}
+operand_entry;
+
+/* Structure to hold trap handler information.  */
+
+typedef struct
+{
+  /* Trap name.  */
+  char *name;
+  /* Index in dispatch table.  */
+  unsigned int entry;
+}
+trap_entry;
+
+/* Structure to hold information about predefined registers.  */
+
+typedef struct
+{
+  /* Name (string representation).  */
+  char *name;
+  /* Value (enum representation).  */
+  union
+  {
+    /* Register.  */
+    reg reg_val;
+    /* processor register.  */
+    preg preg_val;
+  } value;
+  /* Register image.  */
+  int image;
+  /* Register type.  */
+  reg_type type;
+}
+reg_entry;
+
+/* CR16 opcode table.  */
+extern const inst cr16_instruction[];
+extern const unsigned int cr16_num_opcodes;
+#define NUMOPCODES cr16_num_opcodes
+
+/* CR16 operands table.  */
+extern const operand_entry cr16_optab[];
+extern const unsigned int cr16_num_optab;
+
+/* CR16 registers table.  */
+extern const reg_entry cr16_regtab[];
+extern const unsigned int cr16_num_regs;
+#define NUMREGS cr16_num_regs
+
+/* CR16 register pair table.  */
+extern const reg_entry cr16_regptab[];
+extern const unsigned int cr16_num_regps;
+#define NUMREGPS cr16_num_regps
+
+/* CR16 processor registers table.  */
+extern const reg_entry cr16_pregtab[];
+extern const unsigned int cr16_num_pregs;
+#define NUMPREGS cr16_num_pregs
+
+/* CR16 processor registers - 32 bit table.  */
+extern const reg_entry cr16_pregptab[];
+extern const unsigned int cr16_num_pregps;
+#define NUMPREGPS cr16_num_pregps
+
+/* CR16 trap/interrupt table.  */
+extern const trap_entry cr16_traps[];
+extern const unsigned int cr16_num_traps;
+#define NUMTRAPS cr16_num_traps
+
+/* CR16 CC - codes bit table.  */
+extern const char * cr16_b_cond_tab[];
+extern const unsigned int cr16_num_cc;
+#define NUMCC cr16_num_cc;
+
+
+/* Table of instructions with no operands.  */
+extern const char * cr16_no_op_insn[];
+
+/* Current instruction we're assembling.  */
+extern const inst *instruction;
+
+/* A macro for representing the instruction "constant" opcode, that is,
+   the FIXED part of the instruction. The "constant" opcode is represented
+   as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
+   over that range.  */
+#define BIN(OPC,SHIFT)        (OPC << SHIFT)
+
+/* Is the current instruction type is TYPE ?  */
+#define IS_INSN_TYPE(TYPE)              \
+  (CR16_INS_TYPE (instruction->flags) == TYPE)
+
+/* Is the current instruction mnemonic is MNEMONIC ?  */
+#define IS_INSN_MNEMONIC(MNEMONIC)    \
+  (strcmp (instruction->mnemonic, MNEMONIC) == 0)
+
+/* Does the current instruction has register list ?  */
+#define INST_HAS_REG_LIST              \
+  (instruction->flags & REG_LIST)
+
+
+/* Utility macros for string comparison.  */
+#define streq(a, b)           (strcmp (a, b) == 0)
+#define strneq(a, b, c)       (strncmp (a, b, c) == 0)
+
+/* Long long type handling.  */
+/* Replace all appearances of 'long long int' with LONGLONG.  */
+typedef long long int LONGLONG;
+typedef unsigned long long ULONGLONG;
+
+/* Data types for opcode handling.  */
+typedef unsigned long dwordU;
+typedef unsigned short wordU;
+
+/* Globals to store opcode data and build the instruction.  */
+extern wordU cr16_words[3];
+extern ULONGLONG cr16_allWords;
+extern ins cr16_currInsn;
+
+/* Prototypes for function in cr16-dis.c.  */
+extern void cr16_make_instruction (void);
+extern int  cr16_match_opcode (void);
+
+#endif /* _CR16_H_ */
diff --git a/binutils-2.25/include/opcode/cris.h b/binutils-2.25/include/opcode/cris.h
new file mode 100644
index 00000000..e57a8825
--- /dev/null
+++ b/binutils-2.25/include/opcode/cris.h
@@ -0,0 +1,367 @@
+/* cris.h -- Header file for CRIS opcode and register tables.
+   Copyright (C) 2000, 2001, 2004, 2010 Free Software Foundation, Inc.
+   Contributed by Axis Communications AB, Lund, Sweden.
+   Originally written for GAS 1.38.1 by Mikael Asker.
+   Updated, BFDized and GNUified by Hans-Peter Nilsson.
+
+   This file is part of GAS, GDB and the GNU binutils.
+
+   GAS, GDB, and GNU binutils is free software; you can redistribute it
+   and/or modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GAS, GDB, and GNU binutils are distributed in the hope that they will be
+   useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef __CRIS_H_INCLUDED_
+#define __CRIS_H_INCLUDED_
+
+#if !defined(__STDC__) && !defined(const)
+#define const
+#endif
+
+
+/* Registers.  */
+#define MAX_REG (15)
+#define REG_SP (14)
+#define REG_PC (15)
+
+/* CPU version control of disassembly and assembly of instructions.
+   May affect how the instruction is assembled, at least the size of
+   immediate operands.  */
+enum cris_insn_version_usage
+{
+  /* Any version.  */
+  cris_ver_version_all=0,
+
+  /* Indeterminate (intended for disassembly only, or obsolete).  */
+  cris_ver_warning,
+
+  /* Only for v0..3 (Etrax 1..4).  */
+  cris_ver_v0_3,
+
+  /* Only for v3 or higher (ETRAX 4 and beyond).  */
+  cris_ver_v3p,
+
+  /* Only for v8 (Etrax 100).  */
+  cris_ver_v8,
+
+  /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX).  */
+  cris_ver_v8p,
+
+  /* Only for v0..10.  FIXME: Not sure what to do with this.  */
+  cris_ver_sim_v0_10,
+
+  /* Only for v0..10.  */
+  cris_ver_v0_10,
+
+  /* Only for v3..10.  (ETRAX 4, ETRAX 100 and ETRAX 100 LX).  */
+  cris_ver_v3_10,
+
+  /* Only for v8..10 (ETRAX 100 and ETRAX 100 LX).  */
+  cris_ver_v8_10,
+
+  /* Only for v10 (ETRAX 100 LX) and same series.  */
+  cris_ver_v10,
+
+  /* Only for v10 (ETRAX 100 LX) and same series.  */
+  cris_ver_v10p,
+
+  /* Only for v32 or higher (codename GUINNESS).
+     Of course some or all these of may change to cris_ver_v32p if/when
+     there's a new revision. */
+  cris_ver_v32p
+};
+
+
+/* Special registers.  */
+struct cris_spec_reg
+{
+  const char *const name;
+  unsigned int number;
+
+  /* The size of the register.  */
+  unsigned int reg_size;
+
+  /* What CPU version the special register of that name is implemented
+     in.  If cris_ver_warning, emit an unimplemented-warning.  */
+  enum cris_insn_version_usage applicable_version;
+
+  /* There might be a specific warning for using a special register
+     here.  */
+  const char *const warning;
+};
+extern const struct cris_spec_reg cris_spec_regs[];
+
+
+/* Support registers (kind of special too, but not named as such).  */
+struct cris_support_reg
+{
+  const char *const name;
+  unsigned int number;
+};
+extern const struct cris_support_reg cris_support_regs[];
+
+struct cris_cond15
+{
+  /* The name of the condition.  */
+  const char *const name;
+
+  /* What CPU version this condition name applies to.  */
+  enum cris_insn_version_usage applicable_version;
+};
+extern const struct cris_cond15 cris_conds15[];
+
+/* Opcode-dependent constants.  */
+#define AUTOINCR_BIT (0x04)
+
+/* Prefixes.  */
+#define BDAP_QUICK_OPCODE (0x0100)
+#define BDAP_QUICK_Z_BITS (0x0e00)
+
+#define BIAP_OPCODE	  (0x0540)
+#define BIAP_Z_BITS	  (0x0a80)
+
+#define DIP_OPCODE	  (0x0970)
+#define DIP_Z_BITS	  (0xf280)
+
+#define BDAP_INDIR_LOW	  (0x40)
+#define BDAP_INDIR_LOW_Z  (0x80)
+#define BDAP_INDIR_HIGH	  (0x09)
+#define BDAP_INDIR_HIGH_Z (0x02)
+
+#define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW)
+#define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z)
+#define BDAP_PC_LOW	  (BDAP_INDIR_LOW + REG_PC)
+#define BDAP_INCR_HIGH	  (BDAP_INDIR_HIGH + AUTOINCR_BIT)
+
+/* No prefix must have this code for its "match" bits in the
+   opcode-table.  "BCC .+2" will do nicely.  */
+#define NO_CRIS_PREFIX 0
+
+/* Definitions for condition codes.  */
+#define CC_CC  0x0
+#define CC_HS  0x0
+#define CC_CS  0x1
+#define CC_LO  0x1
+#define CC_NE  0x2
+#define CC_EQ  0x3
+#define CC_VC  0x4
+#define CC_VS  0x5
+#define CC_PL  0x6
+#define CC_MI  0x7
+#define CC_LS  0x8
+#define CC_HI  0x9
+#define CC_GE  0xA
+#define CC_LT  0xB
+#define CC_GT  0xC
+#define CC_LE  0xD
+#define CC_A   0xE
+#define CC_EXT 0xF
+
+/* A table of strings "cc", "cs"... indexed with condition code
+   values as above.  */
+extern const char *const cris_cc_strings[];
+
+/* Bcc quick.  */
+#define BRANCH_QUICK_LOW  (0)
+#define BRANCH_QUICK_HIGH (0)
+#define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW)
+#define BRANCH_QUICK_Z_BITS (0x0F00)
+
+/* BA quick.  */
+#define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10)
+#define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW)
+
+/* Bcc [PC+].  */
+#define BRANCH_PC_LOW	 (0xFF)
+#define BRANCH_INCR_HIGH (0x0D)
+#define BA_PC_INCR_OPCODE \
+ ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW)
+
+/* Jump.  */
+/* Note that old versions generated special register 8 (in high bits)
+   and not-that-old versions recognized it as a jump-instruction.
+   That opcode now belongs to JUMPU.  */
+#define JUMP_INDIR_OPCODE (0x0930)
+#define JUMP_INDIR_Z_BITS (0xf2c0)
+#define JUMP_PC_INCR_OPCODE \
+ (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC)
+
+#define MOVE_M_TO_PREG_OPCODE 0x0a30
+#define MOVE_M_TO_PREG_ZBITS 0x01c0
+
+/* BDAP.D N,PC.  */
+#define MOVE_PC_INCR_OPCODE_PREFIX \
+ (((BDAP_INCR_HIGH | (REG_PC << 4)) << 8) | BDAP_PC_LOW | (2 << 4))
+#define MOVE_PC_INCR_OPCODE_SUFFIX \
+ (MOVE_M_TO_PREG_OPCODE | REG_PC | (AUTOINCR_BIT << 8))
+
+#define JUMP_PC_INCR_OPCODE_V32 (0x0DBF)
+
+/* BA DWORD (V32).  */
+#define BA_DWORD_OPCODE (0x0EBF)
+
+/* Nop.  */
+#define NOP_OPCODE (0x050F)
+#define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE)
+
+#define NOP_OPCODE_V32 (0x05B0)
+#define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32)
+
+/* For the compatibility mode, let's use "MOVE R0,P0".  Doesn't affect
+   registers or flags.  Unfortunately shuts off interrupts for one cycle
+   for < v32, but there doesn't seem to be any alternative without that
+   effect.  */
+#define NOP_OPCODE_COMMON (0x630)
+#define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON)
+
+/* LAPC.D  */
+#define LAPC_DWORD_OPCODE (0x0D7F)
+#define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE)
+
+/* Structure of an opcode table entry.  */
+enum cris_imm_oprnd_size_type
+{
+  /* No size is applicable.  */
+  SIZE_NONE,
+
+  /* Always 32 bits.  */
+  SIZE_FIX_32,
+
+  /* Indicated by size of special register.  */
+  SIZE_SPEC_REG,
+
+  /* Indicated by size field, signed.  */
+  SIZE_FIELD_SIGNED,
+
+  /* Indicated by size field, unsigned.  */
+  SIZE_FIELD_UNSIGNED,
+
+  /* Indicated by size field, no sign implied.  */
+  SIZE_FIELD
+};
+
+/* For GDB.  FIXME: Is this the best way to handle opcode
+   interpretation?  */
+enum cris_op_type
+{
+  cris_not_implemented_op = 0,
+  cris_abs_op,
+  cris_addi_op,
+  cris_asr_op,
+  cris_asrq_op,
+  cris_ax_ei_setf_op,
+  cris_bdap_prefix,
+  cris_biap_prefix,
+  cris_break_op,
+  cris_btst_nop_op,
+  cris_clearf_di_op,
+  cris_dip_prefix,
+  cris_dstep_logshift_mstep_neg_not_op,
+  cris_eight_bit_offset_branch_op,
+  cris_move_mem_to_reg_movem_op,
+  cris_move_reg_to_mem_movem_op,
+  cris_move_to_preg_op,
+  cris_muls_op,
+  cris_mulu_op,
+  cris_none_reg_mode_add_sub_cmp_and_or_move_op,
+  cris_none_reg_mode_clear_test_op,
+  cris_none_reg_mode_jump_op,
+  cris_none_reg_mode_move_from_preg_op,
+  cris_quick_mode_add_sub_op,
+  cris_quick_mode_and_cmp_move_or_op,
+  cris_quick_mode_bdap_prefix,
+  cris_reg_mode_add_sub_cmp_and_or_move_op,
+  cris_reg_mode_clear_op,
+  cris_reg_mode_jump_op,
+  cris_reg_mode_move_from_preg_op,
+  cris_reg_mode_test_op,
+  cris_scc_op,
+  cris_sixteen_bit_offset_branch_op,
+  cris_three_operand_add_sub_cmp_and_or_op,
+  cris_three_operand_bound_op,
+  cris_two_operand_bound_op,
+  cris_xor_op
+};
+
+struct cris_opcode
+{
+  /* The name of the insn.  */
+  const char *name;
+
+  /* Bits that must be 1 for a match.  */
+  unsigned int match;
+
+  /* Bits that must be 0 for a match.  */
+  unsigned int lose;
+
+  /* See the table in "opcodes/cris-opc.c".  */
+  const char *args;
+
+  /* Nonzero if this is a delayed branch instruction.  */
+  char delayed;
+
+  /* Size of immediate operands.  */
+  enum cris_imm_oprnd_size_type imm_oprnd_size;
+
+  /* Indicates which version this insn was first implemented in.  */
+  enum cris_insn_version_usage applicable_version;
+
+  /* What kind of operation this is.  */
+  enum cris_op_type op;
+};
+extern const struct cris_opcode cris_opcodes[];
+
+
+/* These macros are for the target-specific flags in disassemble_info
+   used at disassembly.  */
+
+/* This insn accesses memory.  This flag is more trustworthy than
+   checking insn_type for "dis_dref" which does not work for
+   e.g. "JSR [foo]".  */
+#define CRIS_DIS_FLAG_MEMREF (1 << 0)
+
+/* The "target" field holds a register number.  */
+#define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1)
+
+/* The "target2" field holds a register number; add it to "target".  */
+#define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2)
+
+/* Yet another add-on: the register in "target2" must be multiplied
+   by 2 before adding to "target".  */
+#define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3)
+
+/* Yet another add-on: the register in "target2" must be multiplied
+   by 4 (mutually exclusive with .._MULT2).  */ 
+#define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4)
+
+/* The register in "target2" is an indirect memory reference (of the
+   register there), add to "target".  Assumed size is dword (mutually
+   exclusive with .._MULT[24]).  */
+#define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5)
+
+/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte";
+   sign-extended before adding to "target".  */
+#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6)
+
+/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word";
+   sign-extended before adding to "target".  */
+#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7)
+
+#endif /* __CRIS_H_INCLUDED_ */
+
+/*
+ * Local variables:
+ * eval: (c-set-style "gnu")
+ * indent-tabs-mode: t
+ * End:
+ */
diff --git a/binutils-2.25/include/opcode/crx.h b/binutils-2.25/include/opcode/crx.h
new file mode 100644
index 00000000..6081ea35
--- /dev/null
+++ b/binutils-2.25/include/opcode/crx.h
@@ -0,0 +1,419 @@
+/* crx.h -- Header file for CRX opcode and register tables.
+   Copyright 2004, 2010, 2012 Free Software Foundation, Inc.
+   Contributed by Tomer Levi, NSC, Israel.
+   Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
+   Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
+
+   This file is part of GAS, GDB and the GNU binutils.
+
+   GAS, GDB, and GNU binutils is free software; you can redistribute it
+   and/or modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GAS, GDB, and GNU binutils are distributed in the hope that they will be
+   useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _CRX_H_
+#define _CRX_H_
+
+/* CRX core/debug Registers :
+   The enums are used as indices to CRX registers table (crx_regtab).
+   Therefore, order MUST be preserved.  */
+
+typedef enum
+  {
+    /* 32-bit general purpose registers.  */
+    r0, r1, r2, r3, r4, r5, r6, r7, r8, r9,
+    r10, r11, r12, r13, r14, r15, ra, sp,
+    /* 32-bit user registers.  */
+    u0, u1, u2, u3, u4, u5, u6, u7, u8, u9,
+    u10, u11, u12, u13, u14, u15, ura, usp,
+    /* hi and lo registers.  */
+    hi, lo,
+    /* hi and lo user registers.  */
+    uhi, ulo,
+    /* Processor Status Register.  */
+    psr,
+    /* Interrupt Base Register.  */
+    intbase,
+    /* Interrupt Stack Pointer Register.  */
+    isp,
+    /* Configuration Register.  */
+    cfg,
+    /* Coprocessor Configuration Register.  */
+    cpcfg,
+    /* Coprocessor Enable Register.  */
+    cen,
+    /* Not a register.  */
+    nullregister,
+    MAX_REG
+  }
+reg;
+
+/* CRX Coprocessor registers and special registers :
+   The enums are used as indices to CRX coprocessor registers table
+   (crx_copregtab). Therefore, order MUST be preserved.  */
+
+typedef enum
+  {
+    /* Coprocessor registers.  */
+    c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8,
+    c9, c10, c11, c12, c13, c14, c15,
+    /* Coprocessor special registers.  */
+    cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8,
+    cs9, cs10, cs11, cs12, cs13, cs14, cs15,
+    /* Not a Coprocessor register.  */
+    nullcopregister,
+    MAX_COPREG
+  }
+copreg;
+
+/* CRX Register types. */
+
+typedef enum
+  {
+    CRX_R_REGTYPE,    /*  r<N>	  */
+    CRX_U_REGTYPE,    /*  u<N>	  */
+    CRX_C_REGTYPE,    /*  c<N>	  */
+    CRX_CS_REGTYPE,   /*  cs<N>	  */
+    CRX_CFG_REGTYPE   /*  configuration register   */
+  }
+reg_type;
+
+/* CRX argument types :
+   The argument types correspond to instructions operands
+
+   Argument types :
+   r - register
+   c - constant
+   i - immediate
+   idxr - index register
+   rbase - register base
+   s - star ('*')
+   copr - coprocessor register
+   copsr - coprocessor special register.  */
+
+typedef enum
+  {
+    arg_r, arg_c, arg_cr, arg_ic, arg_icr, arg_sc,
+    arg_idxr, arg_rbase, arg_copr, arg_copsr,
+    /* Not an argument.  */
+    nullargs
+  }
+argtype;
+
+/* CRX operand types :
+   The operand types correspond to instructions operands.  */
+
+typedef enum
+  {
+    dummy,
+    /* 4-bit encoded constant.  */
+    cst4,
+    /* N-bit immediate.  */
+    i16, i32,
+    /* N-bit unsigned immediate.  */
+    ui3, ui4, ui5, ui16,
+    /* N-bit signed displacement.  */
+    disps9, disps17, disps25, disps32,
+    /* N-bit unsigned displacement.  */
+    dispu5, 
+    /* N-bit escaped displacement.  */
+    dispe9,
+    /* N-bit absolute address.  */
+    abs16, abs32,
+    /* Register relative.  */
+    rbase, rbase_dispu4,
+    rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32,
+    /* Register index.  */
+    rindex_disps6, rindex_disps22,
+    /* 4-bit genaral-purpose register specifier.  */
+    regr, 
+    /* 8-bit register address space.  */
+    regr8,
+    /* coprocessor register.  */
+    copregr, 
+    /* coprocessor special register.  */
+    copsregr,
+    /* Not an operand.  */
+    nulloperand,
+    /* Maximum supported operand.  */
+    MAX_OPRD
+  }
+operand_type;
+
+/* CRX instruction types.  */
+
+#define NO_TYPE_INS       0
+#define ARITH_INS         1
+#define LD_STOR_INS       2
+#define BRANCH_INS        3
+#define ARITH_BYTE_INS    4
+#define CMPBR_INS         5
+#define SHIFT_INS         6
+#define BRANCH_NEQ_INS    7
+#define LD_STOR_INS_INC   8
+#define STOR_IMM_INS	  9
+#define CSTBIT_INS       10
+#define COP_BRANCH_INS   11
+#define COP_REG_INS      12
+#define COPS_REG_INS     13
+#define DCR_BRANCH_INS   14
+
+/* Maximum value supported for instruction types.  */
+#define CRX_INS_MAX	(1 << 4)
+/* Mask to record an instruction type.  */
+#define CRX_INS_MASK	(CRX_INS_MAX - 1)
+/* Return instruction type, given instruction's attributes.  */
+#define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK)
+
+/* Indicates whether this instruction has a register list as parameter.  */
+#define REG_LIST	CRX_INS_MAX
+/* The operands in binary and assembly are placed in reverse order.
+   load - (REVERSE_MATCH)/store - (! REVERSE_MATCH).  */
+#define REVERSE_MATCH  (1 << 5)
+
+/* Kind of displacement map used DISPU[BWD]4.  */
+#define DISPUB4	       (1 << 6)
+#define DISPUW4	       (1 << 7)
+#define DISPUD4	       (1 << 8)
+#define DISPU4MAP      (DISPUB4 | DISPUW4 | DISPUD4)
+
+/* Printing formats, where the instruction prefix isn't consecutive.  */
+#define FMT_1	       (1 << 9)   /* 0xF0F00000 */
+#define FMT_2	       (1 << 10)   /* 0xFFF0FF00 */
+#define FMT_3	       (1 << 11)   /* 0xFFF00F00 */
+#define FMT_4	       (1 << 12)   /* 0xFFF0F000 */
+#define FMT_5	       (1 << 13)   /* 0xFFF0FFF0 */
+#define FMT_CRX	       (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)
+
+/* Indicates whether this instruction can be relaxed.  */
+#define RELAXABLE      (1 << 14)
+
+/* Indicates that instruction uses user registers (and not 
+   general-purpose registers) as operands.  */
+#define USER_REG       (1 << 15)
+
+/* Indicates that instruction can perfom a cst4 mapping.  */
+#define CST4MAP	       (1 << 16)
+
+/* Instruction shouldn't allow 'sp' usage.  */
+#define NO_SP	       (1 << 17)
+
+/* Instruction shouldn't allow to push a register which is used as a rptr.  */
+#define NO_RPTR	       (1 << 18)
+
+/* Maximum operands per instruction.  */
+#define MAX_OPERANDS	  5
+/* Maximum register name length. */
+#define MAX_REGNAME_LEN	  10
+/* Maximum instruction length. */
+#define MAX_INST_LEN	  256
+
+
+/* Values defined for the flags field of a struct operand_entry.  */
+
+/* Operand must be an unsigned number.  */
+#define OP_UNSIGNED   (1 << 0)
+/* Operand must be a signed number.  */
+#define OP_SIGNED     (1 << 1)
+/* A special arithmetic 4-bit constant operand.  */
+#define OP_CST4	      (1 << 2)
+/* A special load/stor 4-bit unsigned displacement operand.  */
+#define OP_DISPU4     (1 << 3)
+/* Operand must be an even number.  */
+#define OP_EVEN	      (1 << 4)
+/* Operand is shifted right.  */
+#define OP_SHIFT      (1 << 5)
+/* Operand is shifted right and decremented.  */
+#define OP_SHIFT_DEC  (1 << 6)
+/* Operand has reserved escape sequences.  */
+#define OP_ESC	      (1 << 7)
+/* Operand is used only for the upper 64 KB (FFFF0000 to FFFFFFFF).  */
+#define OP_UPPER_64KB (1 << 8)
+
+/* Single operand description.  */
+
+typedef struct
+  {
+    /* Operand type.  */
+    operand_type op_type;
+    /* Operand location within the opcode.  */
+    unsigned int shift;
+  }
+operand_desc;
+
+/* Instruction data structure used in instruction table.  */
+
+typedef struct
+  {
+    /* Name.  */
+    const char *mnemonic;
+    /* Size (in words).  */
+    unsigned int size;
+    /* Constant prefix (matched by the disassembler).  */
+    unsigned long match;
+    /* Match size (in bits).  */
+    int match_bits;
+    /* Attributes.  */
+    unsigned int flags;
+    /* Operands (always last, so unreferenced operands are initialized).  */
+    operand_desc operands[MAX_OPERANDS];
+  }
+inst;
+
+/* Data structure for a single instruction's arguments (Operands).  */
+
+typedef struct
+  {
+    /* Register or base register.  */
+    reg r;
+    /* Index register.  */
+    reg i_r;
+    /* Coprocessor register.  */
+    copreg cr;
+    /* Constant/immediate/absolute value.  */
+    long constant;
+    /* Scaled index mode.  */
+    unsigned int scale;
+    /* Argument type.  */
+    argtype type;
+    /* Size of the argument (in bits) required to represent.  */
+    int size;
+  /* The type of the expression.  */
+    unsigned char X_op;
+  }
+argument;
+
+/* Internal structure to hold the various entities
+   corresponding to the current assembling instruction.  */
+
+typedef struct
+  {
+    /* Number of arguments.  */
+    int nargs;
+    /* The argument data structure for storing args (operands).  */
+    argument arg[MAX_OPERANDS];
+/* The following fields are required only by CRX-assembler.  */
+#ifdef TC_CRX
+    /* Expression used for setting the fixups (if any).  */
+    expressionS exp;
+    bfd_reloc_code_real_type rtype;
+#endif /* TC_CRX */
+    /* Instruction size (in bytes).  */
+    int size;
+  }
+ins;
+
+/* Structure to hold information about predefined operands.  */
+
+typedef struct
+  {
+    /* Size (in bits).  */
+    unsigned int bit_size;
+    /* Argument type.  */
+    argtype arg_type;
+    /* One bit syntax flags.  */
+    int flags;
+  }
+operand_entry;
+
+/* Structure to hold trap handler information.  */
+
+typedef struct
+  {
+    /* Trap name.  */
+    char *name;
+    /* Index in dispatch table.  */
+    unsigned int entry;
+  }
+trap_entry;
+
+/* Structure to hold information about predefined registers.  */
+
+typedef struct
+  {
+    /* Name (string representation).  */
+    char *name;
+    /* Value (enum representation).  */
+    union
+    {
+      /* Register.  */
+      reg reg_val;
+      /* Coprocessor register.  */
+      copreg copreg_val;
+    } value;
+    /* Register image.  */
+    int image;
+    /* Register type.  */
+    reg_type type;
+  }
+reg_entry;
+
+/* Structure to hold a cst4 operand mapping.  */
+
+/* CRX opcode table.  */
+extern const inst crx_instruction[];
+extern const int crx_num_opcodes;
+#define NUMOPCODES crx_num_opcodes
+
+/* CRX operands table.  */
+extern const operand_entry crx_optab[];
+
+/* CRX registers table.  */
+extern const reg_entry crx_regtab[];
+extern const int crx_num_regs;
+#define NUMREGS crx_num_regs
+
+/* CRX coprocessor registers table.  */
+extern const reg_entry crx_copregtab[];
+extern const int crx_num_copregs;
+#define NUMCOPREGS crx_num_copregs
+
+/* CRX trap/interrupt table.  */
+extern const trap_entry crx_traps[];
+extern const int crx_num_traps;
+#define NUMTRAPS crx_num_traps
+
+/* cst4 operand mapping.  */
+extern const int cst4_map[];
+extern const int cst4_maps;
+
+/* Table of instructions with no operands.  */
+extern const char* no_op_insn[];
+
+/* Current instruction we're assembling.  */
+extern const inst *instruction;
+
+/* A macro for representing the instruction "constant" opcode, that is,
+   the FIXED part of the instruction. The "constant" opcode is represented
+   as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
+   over that range.  */
+#define BIN(OPC,SHIFT)	(OPC << SHIFT)
+
+/* Is the current instruction type is TYPE ?  */
+#define IS_INSN_TYPE(TYPE)	      \
+  (CRX_INS_TYPE(instruction->flags) == TYPE)
+
+/* Is the current instruction mnemonic is MNEMONIC ?  */
+#define IS_INSN_MNEMONIC(MNEMONIC)    \
+  (strcmp(instruction->mnemonic,MNEMONIC) == 0)
+
+/* Does the current instruction has register list ?  */
+#define INST_HAS_REG_LIST	      \
+  (instruction->flags & REG_LIST)
+
+/* Long long type handling.  */
+/* Replace all appearances of 'long long int' with LONGLONG.  */
+typedef long long int LONGLONG;
+typedef unsigned long long ULONGLONG;
+
+#endif /* _CRX_H_ */
diff --git a/binutils-2.25/include/opcode/d10v.h b/binutils-2.25/include/opcode/d10v.h
new file mode 100644
index 00000000..d0e115fa
--- /dev/null
+++ b/binutils-2.25/include/opcode/d10v.h
@@ -0,0 +1,209 @@
+/* d10v.h -- Header file for D10V opcode table
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2010
+   Free Software Foundation, Inc.
+   Written by Martin Hunt (hunt@cygnus.com), Cygnus Support
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef D10V_H
+#define D10V_H
+
+/* Format Specifier */
+#define FM00	0
+#define FM01	0x40000000
+#define FM10	0x80000000
+#define FM11	0xC0000000
+
+#define NOP 0x5e00
+#define OPCODE_DIVS	0x14002800
+
+/* The opcode table is an array of struct d10v_opcode.  */
+
+struct d10v_opcode
+{
+  /* The opcode name.  */
+  const char *name;
+
+  /* the opcode format */
+  int format;
+
+  /* These numbers were picked so we can do if( i & SHORT_OPCODE) */
+#define SHORT_OPCODE 1
+#define LONG_OPCODE  8
+#define SHORT_2	     1		/* short with 2 operands */
+#define SHORT_B	     3		/* short with 8-bit branch */
+#define LONG_B	     8		/* long with 16-bit branch */
+#define LONG_L       10		/* long with 3 operands */
+#define LONG_R       12		/* reserved */
+
+  /* just a placeholder for variable-length instructions */
+  /* for example, "bra" will be a fake for "bra.s" and bra.l" */
+  /* which will immediately follow in the opcode table.  */
+#define OPCODE_FAKE  32
+
+  /* the number of cycles */
+  int cycles;
+
+  /* the execution unit(s) used */
+  int unit;
+#define EITHER	0
+#define IU	1
+#define MU	2
+#define BOTH	3
+
+  /* execution type; parallel or sequential */
+  /* this field is used to decide if two instructions */
+  /* can be executed in parallel */
+  int exec_type;
+#define PARONLY 1	/* parallel only */
+#define SEQ	2	/* must be sequential */
+#define PAR	4	/* may be parallel */
+#define BRANCH_LINK 8	/* subroutine call.  must be aligned */
+#define RMEM     16	/* reads memory */
+#define WMEM     32	/* writes memory */
+#define RF0      64	/* reads f0 */
+#define WF0     128	/* modifies f0 */
+#define WCAR    256	/* write Carry */
+#define BRANCH  512	/* branch, no link */
+#define ALONE  1024	/* short but pack with a NOP if on asm line alone */
+
+  /* the opcode */
+  long opcode;
+
+  /* mask.  if( (i & mask) == opcode ) then match */
+  long mask;
+
+  /* An array of operand codes.  Each code is an index into the
+     operand table.  They appear in the order which the operands must
+     appear in assembly code, and are terminated by a zero.  */
+  unsigned char operands[6];
+};
+
+/* The table itself is sorted by major opcode number, and is otherwise
+   in the order in which the disassembler should consider
+   instructions.  */
+extern const struct d10v_opcode d10v_opcodes[];
+extern const int d10v_num_opcodes;
+
+/* The operands table is an array of struct d10v_operand.  */
+struct d10v_operand
+{
+  /* The number of bits in the operand.  */
+  int bits;
+
+  /* How far the operand is left shifted in the instruction.  */
+  int shift;
+
+  /* One bit syntax flags.  */
+  int flags;
+};
+
+/* Elements in the table are retrieved by indexing with values from
+   the operands field of the d10v_opcodes table.  */
+
+extern const struct d10v_operand d10v_operands[];
+
+/* Values defined for the flags field of a struct d10v_operand.  */
+
+/* the operand must be an even number */
+#define OPERAND_EVEN	(1)
+
+/* the operand must be an odd number */
+#define OPERAND_ODD	(2)	
+
+/* this is the destination register; it will be modified */
+/* this is used by the optimizer */
+#define OPERAND_DEST	(4)
+
+/* number or symbol */
+#define OPERAND_NUM	(8)
+
+/* address or label */
+#define OPERAND_ADDR	(0x10)
+
+/* register */
+#define OPERAND_REG	(0x20)
+
+/* postincrement +  */
+#define OPERAND_PLUS	(0x40)
+
+/* postdecrement -  */
+#define OPERAND_MINUS	(0x80)
+
+/* @  */
+#define OPERAND_ATSIGN	(0x100)
+
+/* @(  */
+#define OPERAND_ATPAR	(0x200)
+
+/* accumulator 0 */
+#define OPERAND_ACC0	(0x400)
+
+/* accumulator 1 */
+#define OPERAND_ACC1	(0x800)
+
+/* f0 / f1 flag register */
+#define OPERAND_FFLAG	(0x1000)
+
+/* c flag register */
+#define OPERAND_CFLAG	(0x2000)
+
+/* control register  */
+#define OPERAND_CONTROL	(0x4000)
+
+/* predecrement mode '@-sp'  */
+#define OPERAND_ATMINUS	(0x8000)
+
+/* signed number */
+#define OPERAND_SIGNED	(0x10000)
+
+/* special accumulator shifts need a 4-bit number */
+/* 1 <= x <= 16 */
+#define OPERAND_SHIFT	(0x20000)
+
+/* general purpose register */
+#define OPERAND_GPR	(0x40000)
+
+/* special imm3 values with range restricted to -2 <= imm3 <= 3 */
+/* needed for rac/rachi */
+#define RESTRICTED_NUM3	(0x80000)
+
+/* Pre-decrement is only supported for SP.  */
+#define OPERAND_SP      (0x100000)
+
+/* Post-decrement is not supported for SP.  Like OPERAND_EVEN, and
+   unlike OPERAND_SP, this flag doesn't prevent the instruction from
+   matching, it only fails validation later on.  */
+#define OPERAND_NOSP    (0x200000)
+
+/* Structure to hold information about predefined registers.  */
+struct pd_reg
+{
+  char *name;		/* name to recognize */
+  char *pname;		/* name to print for this register */
+  int value;
+};
+
+extern const struct pd_reg d10v_predefined_registers[];
+int d10v_reg_name_cnt (void);
+
+/* an expressionS only has one register type, so we fake it */
+/* by setting high bits to indicate type */
+#define REGISTER_MASK	0xFF
+
+#endif /* D10V_H */
diff --git a/binutils-2.25/include/opcode/d30v.h b/binutils-2.25/include/opcode/d30v.h
new file mode 100644
index 00000000..62c041da
--- /dev/null
+++ b/binutils-2.25/include/opcode/d30v.h
@@ -0,0 +1,288 @@
+/* d30v.h -- Header file for D30V opcode table
+   Copyright 1997, 1998, 1999, 2000, 2001, 2003, 2010
+   Free Software Foundation, Inc.
+   Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef D30V_H
+#define D30V_H
+
+#define NOP 0x00F00000
+
+/* Structure to hold information about predefined registers.  */
+struct pd_reg
+{
+  char *name;		/* name to recognize */
+  char *pname;		/* name to print for this register */
+  int value;
+};
+
+extern const struct pd_reg pre_defined_registers[];
+int reg_name_cnt (void);
+
+/* the number of control registers */
+#define MAX_CONTROL_REG	64
+
+/* define the format specifiers */
+#define FM00	0
+#define FM01	0x80000000
+#define FM10	0x8000000000000000LL
+#define FM11	0x8000000080000000LL
+
+/* define the opcode classes */
+#define BRA	0
+#define LOGIC	1
+#define IMEM	2
+#define IALU1	4
+#define IALU2	5
+
+/* define the execution condition codes */
+#define ECC_AL	0	/* ALways (default) */
+#define ECC_TX	1	/* F0=True, F1=Don't care */
+#define ECC_FX	2	/* F0=False, F1=Don't care */
+#define ECC_XT	3	/* F0=Don't care, F1=True */
+#define ECC_XF	4	/* F0=Don't care, F1=False */
+#define ECC_TT	5	/* F0=True, F1=True */
+#define ECC_TF	6	/* F0=True, F1=False */
+#define ECC_RESERVED	7	/* reserved */
+#define ECC_MAX	ECC_RESERVED
+
+extern const char *d30v_ecc_names[];
+
+/* condition code table for CMP and CMPU */
+extern const char *d30v_cc_names[];
+
+/* The opcode table is an array of struct d30v_opcode.  */
+struct d30v_opcode
+{
+  /* The opcode name.  */
+  const char *name;
+
+  /* the opcode */
+  int op1;	/* first part, "IALU1" for example */
+  int op2;	/* the rest of the opcode */
+
+  /* opcode format(s).  These numbers correspond to entries */
+  /* in the d30v_format_table */
+  unsigned char format[4];
+
+#define SHORT_M		1
+#define SHORT_M2	5	/* for ld2w and st2w */
+#define SHORT_A		9
+#define SHORT_B1	11
+#define SHORT_B2	12
+#define SHORT_B2r     13
+#define SHORT_B3      14
+#define SHORT_B3r     16
+#define SHORT_B3b     18
+#define SHORT_B3br    20
+#define SHORT_D1r     22
+#define SHORT_D2      24
+#define SHORT_D2r     26
+#define SHORT_D2Br    28
+#define SHORT_U       30      /* unary SHORT_A.  ABS for example */
+#define SHORT_F       31      /* SHORT_A with flag registers */
+#define SHORT_AF      33      /* SHORT_A with only the first register a flag register */
+#define SHORT_T       35      /* for trap instruction */
+#define SHORT_A5      36      /* SHORT_A with a 5-bit immediate instead of 6 */
+#define SHORT_CMP     38      /* special form for CMPcc */
+#define SHORT_CMPU    40      /* special form for CMPUcc */
+#define SHORT_A1      42      /* special form of SHORT_A for MACa opcodes where a=1 */
+#define SHORT_AA      44      /* SHORT_A with the first register an accumulator */
+#define SHORT_RA      46      /* SHORT_A with the second register an accumulator */
+#define SHORT_MODINC  48      
+#define SHORT_MODDEC  49
+#define SHORT_C1      50
+#define SHORT_C2      51
+#define SHORT_UF      52
+#define SHORT_A2      53
+#define SHORT_NONE    55      /* no operands */
+#define SHORT_AR      56      /* like SHORT_AA but only accept register as third parameter  */
+#define LONG          57
+#define LONG_U        58      /* unary LONG */
+#define LONG_Ur       59      /* LONG pc-relative */
+#define LONG_CMP      60      /* special form for CMPcc and CMPUcc */
+#define LONG_M        61      /* Memory long for ldb, stb */
+#define LONG_M2       62      /* Memory long for ld2w, st2w */
+#define LONG_2        63      /* LONG with 2 operands; jmptnz */
+#define LONG_2r       64      /* LONG with 2 operands; bratnz */
+#define LONG_2b       65      /* LONG_2 with modifier of 3 */
+#define LONG_2br      66      /* LONG_2r with modifier of 3 */
+#define LONG_D        67      /* for DJMPI */
+#define LONG_Dr       68      /* for DBRAI */
+#define LONG_Dbr      69      /* for repeati */
+
+  /* the execution unit(s) used */
+  int unit;
+#define EITHER	0
+#define IU	1
+#define MU	2
+#define EITHER_BUT_PREFER_MU 3
+
+  /* this field is used to decide if two instructions */
+  /* can be executed in parallel */
+  long flags_used;
+  long flags_set;
+#define FLAG_0		(1L<<0)
+#define FLAG_1		(1L<<1)
+#define FLAG_2		(1L<<2)
+#define FLAG_3		(1L<<3)
+#define FLAG_4		(1L<<4)		/* S (saturation) */
+#define FLAG_5		(1L<<5)		/* V (overflow) */
+#define FLAG_6		(1L<<6)		/* VA (accumulated overflow) */
+#define FLAG_7		(1L<<7)		/* C (carry/borrow) */
+#define FLAG_SM		(1L<<8)		/* SM (stack mode) */
+#define FLAG_RP		(1L<<9)		/* RP (repeat enable) */
+#define FLAG_CONTROL	(1L<<10)	/* control registers */
+#define FLAG_A0		(1L<<11)	/* A0 */
+#define FLAG_A1		(1L<<12)	/* A1 */
+#define FLAG_JMP	(1L<<13)	/* instruction is a branch */
+#define FLAG_JSR	(1L<<14)	/* subroutine call.  must be aligned */
+#define FLAG_MEM	(1L<<15)	/* reads/writes memory */
+#define FLAG_NOT_WITH_ADDSUBppp	 (1L<<16) /* Old meaning: a 2 word 4 byter operation
+					   New meaning: operation cannot be 
+					   combined in parallel with ADD/SUBppp. */
+#define FLAG_MUL16	(1L<<17)	/* 16 bit multiply */
+#define FLAG_MUL32	(1L<<18)	/* 32 bit multiply */
+#define FLAG_ADDSUBppp	(1L<<19)	/* ADDppp or SUBppp */
+#define FLAG_DELAY	(1L<<20)	/* This is a delayed branch or jump */
+#define FLAG_LKR	(1L<<21)	/* insn in left slot kills right slot */
+#define FLAG_CVVA	(FLAG_5|FLAG_6|FLAG_7)
+#define FLAG_C		FLAG_7
+#define FLAG_ALL	(FLAG_0 | \
+			 FLAG_1 | \
+			 FLAG_2 | \
+			 FLAG_3 | \
+			 FLAG_4 | \
+			 FLAG_5 | \
+			 FLAG_6 | \
+			 FLAG_7 | \
+			 FLAG_SM | \
+			 FLAG_RP | \
+			 FLAG_CONTROL)
+
+  int reloc_flag;
+#define RELOC_PCREL	1
+#define RELOC_ABS	2
+};
+
+extern const struct d30v_opcode d30v_opcode_table[];
+extern const int d30v_num_opcodes;
+
+/* The operands table is an array of struct d30v_operand.  */
+struct d30v_operand
+{
+  /* the length of the field */
+  int length;
+
+  /* The number of significant bits in the operand.  */
+  int bits;
+
+  /* position relative to Ra */
+  int position;
+
+  /* syntax flags.  */
+  long flags;
+};
+extern const struct d30v_operand d30v_operand_table[];
+
+/* Values defined for the flags field of a struct d30v_operand.  */
+
+/* this is the destination register; it will be modified */
+/* this is used by the optimizer */
+#define OPERAND_DEST	(1)
+
+/* number or symbol */
+#define OPERAND_NUM	(2)
+
+/* address or label */
+#define OPERAND_ADDR	(4)
+
+/* register */
+#define OPERAND_REG	(8)
+
+/* postincrement +  */
+#define OPERAND_PLUS	(0x10)
+
+/* postdecrement -  */
+#define OPERAND_MINUS	(0x20)
+
+/* signed number */
+#define OPERAND_SIGNED	(0x40)
+
+/* this operand must be shifted left by 3 */
+#define OPERAND_SHIFT	(0x80)
+
+/* flag register */
+#define OPERAND_FLAG	(0x100)
+
+/* control register  */
+#define OPERAND_CONTROL	(0x200)
+
+/* accumulator */
+#define OPERAND_ACC	(0x400)
+
+/* @  */
+#define OPERAND_ATSIGN	(0x800)
+
+/* @(  */
+#define OPERAND_ATPAR	(0x1000)
+
+/* predecrement mode '@-sp'  */
+#define OPERAND_ATMINUS	(0x2000)
+
+/* this operand changes the instruction name */
+/* for example, CPMcc, CMPUcc */
+#define OPERAND_NAME	(0x4000)
+
+/* fake operand for mvtsys and mvfsys */
+#define OPERAND_SPECIAL	(0x8000)
+
+/* let the optimizer know that two registers are affected */
+#define OPERAND_2REG	(0x10000)
+
+/* This operand is pc-relative.  Note that repeati can have two immediate
+   operands, one of which is pcrel, the other (the IMM6U one) is not.  */
+#define OPERAND_PCREL	(0x20000)
+
+/* The format table is an array of struct d30v_format.  */
+struct d30v_format
+{
+  int	form;		/* SHORT_A, LONG, etc */
+  int	modifier;	/* two bit modifier following opcode */
+  unsigned char operands[5];
+};
+extern const struct d30v_format d30v_format_table[];
+
+
+/* an instruction is defined by an opcode and a format */
+/* for example, "add" has one opcode, but three different */
+/* formats, 2 SHORT_A forms and a LONG form. */
+struct d30v_insn
+{
+  struct d30v_opcode *op;	/* pointer to an entry in the opcode table */
+  struct d30v_format *form;	/* pointer to an entry in the format table */
+  int ecc;			/* execution condition code */
+};
+
+/* an expressionS only has one register type, so we fake it */
+/* by setting high bits to indicate type */
+#define REGISTER_MASK	0xFF
+
+#endif /* D30V_H */
diff --git a/binutils-2.25/include/opcode/dlx.h b/binutils-2.25/include/opcode/dlx.h
new file mode 100644
index 00000000..54dadd07
--- /dev/null
+++ b/binutils-2.25/include/opcode/dlx.h
@@ -0,0 +1,283 @@
+/* Table of opcodes for the DLX microprocess.
+   Copyright 2002, 2010 Free Software Foundation, Inc.
+
+   This file is part of GDB and GAS.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.
+
+   Initially created by Kuang Hwa Lin, 2002.   */
+
+/* Following are the function codes for the Special OP (ALU).  */
+#define  ALUOP       0x00000000
+#define  SPECIALOP   0x00000000
+
+#define  NOPF        0x00000000
+#define  SLLF        0x00000004
+#define  SRLF        0x00000006
+#define  SRAF        0x00000007
+
+#define  SEQUF       0x00000010
+#define  SNEUF       0x00000011
+#define  SLTUF       0x00000012
+#define  SGTUF       0x00000013
+#define  SLEUF       0x00000014
+#define  SGEUF       0x00000015
+
+#define  ADDF        0x00000020
+#define  ADDUF       0x00000021
+#define  SUBF        0x00000022
+#define  SUBUF       0x00000023
+#define  ANDF        0x00000024
+#define  ORF         0x00000025
+#define  XORF        0x00000026
+
+#define  SEQF        0x00000028
+#define  SNEF        0x00000029
+#define  SLTF        0x0000002A
+#define  SGTF        0x0000002B
+#define  SLEF        0x0000002C
+#define  SGEF        0x0000002D
+  /* Following special functions was not mentioned in the
+     Hennessy's book but was implemented in the RTL.  */
+#define  MVTSF 	     0x00000030
+#define  MVFSF       0x00000031
+#define  BSWAPF      0x00000032
+#define  LUTF        0x00000033
+/* Following special functions was mentioned in the
+   Hennessy's book but was not implemented in the RTL.  */
+#define  MULTF       0x00000005
+#define  MULTUF      0x00000006
+#define  DIVF        0x00000007
+#define  DIVUF       0x00000008
+
+
+/* Following are the rest of the OPcodes:
+   JOP    = (0x002 << 26), JALOP  = (0x003 << 26), BEQOP = (0x004 << 26),   BNEOP  = (0x005 << 26)
+   ADDIOP = (0x008 << 26), ADDUIOP= (0x009 << 26), SUBIOP	= (0x00A << 26), SUBUIOP= (0x00B << 26)
+   ANDIOP = (0x00C << 26), ORIOP  = (0x00D << 26), XORIOP = (0x00E << 26),  LHIOP  = (0x00F << 26)
+   RFEOP  = (0x010 << 26), TRAPOP = (0x011 << 26), JROP	= (0x012 << 26), JALROP = (0x013 << 26)
+   BREAKOP= (0x014 << 26)
+   SEQIOP = (0x018 << 26), SNEIOP = (0x019 << 26), SLTIOP = (0x01A << 26),  SGTIOP = (0x01B << 26)
+   SLEIOP = (0x01C << 26), SGEIOP = (0x01D << 26)
+   LBOP   = (0x020 << 26), LHOP   = (0x021 << 26), LWOP   = (0x023 << 26),  LBUOP  = (0x024 << 26)
+   LHUOP  = (0x025 << 26), SBOP   = (0x028 << 26), SHOP   = (0x029 << 26),  SWOP   = (0x02B << 26)
+   LSBUOP = (0x026 << 26), LSHU   = (0x027 << 26), LSW    = (0x02C << 26),
+   SEQUIOP= (0x030 << 26), SNEUIOP= (0x031 << 26), SLTUIOP= (0x032 << 26),  SGTUIOP= (0x033 << 26)
+   SLEUIOP= (0x034 << 26), SGEUIOP= (0x035 << 26)
+   SLLIOP = (0x036 << 26), SRLIOP = (0x037 << 26), SRAIOP = (0x038 << 26).  */
+#define  JOP	     0x08000000
+#define  JALOP	     0x0c000000
+#define  BEQOP	     0x10000000
+#define  BNEOP	     0x14000000
+
+#define  ADDIOP	     0x20000000
+#define  ADDUIOP     0x24000000
+#define  SUBIOP	     0x28000000
+#define  SUBUIOP     0x2c000000
+#define  ANDIOP      0x30000000
+#define  ORIOP       0x34000000
+#define  XORIOP      0x38000000
+#define  LHIOP       0x3c000000
+#define  RFEOP	     0x40000000
+#define  TRAPOP      0x44000000
+#define  JROP	     0x48000000
+#define  JALROP      0x4c000000
+#define  BREAKOP     0x50000000
+
+#define  SEQIOP      0x60000000
+#define  SNEIOP      0x64000000
+#define  SLTIOP      0x68000000
+#define  SGTIOP      0x6c000000
+#define  SLEIOP      0x70000000
+#define  SGEIOP      0x74000000
+
+#define  LBOP        0x80000000
+#define  LHOP        0x84000000
+#define  LWOP        0x8c000000
+#define  LBUOP       0x90000000
+#define  LHUOP	     0x94000000
+#define  LDSTBU
+#define  LDSTHU
+#define  SBOP	     0xa0000000
+#define  SHOP        0xa4000000
+#define  SWOP        0xac000000
+#define  LDST
+
+#define  SEQUIOP     0xc0000000
+#define  SNEUIOP     0xc4000000
+#define  SLTUIOP     0xc8000000
+#define  SGTUIOP     0xcc000000
+#define  SLEUIOP     0xd0000000
+#define  SGEUIOP     0xd4000000
+
+#define  SLLIOP      0xd8000000
+#define  SRLIOP      0xdc000000
+#define  SRAIOP      0xe0000000
+
+/* Following 3 ops was added to provide the MP atonmic operation.  */
+#define  LSBUOP      0x98000000
+#define  LSHUOP      0x9c000000
+#define  LSWOP       0xb0000000
+
+/* Following opcode was defined in the Hennessy's book as
+   "normal" opcode but was implemented in the RTL as special
+   functions.  */
+#if 0
+#define  MVTSOP	     0x50000000
+#define  MVFSOP      0x54000000
+#endif
+
+struct dlx_opcode
+{
+  /* Name of the instruction.  */
+  char *name;
+
+  /* Opcode word.  */
+  unsigned long opcode;
+
+  /* A string of characters which describe the operands.
+     Valid characters are:
+     ,        Itself.  The character appears in the assembly code.
+     a        rs1      The register number is in bits 21-25 of the instruction.
+     b        rs2/rd   The register number is in bits 16-20 of the instruction.
+     c        rd.      The register number is in bits 11-15 of the instruction.
+     f        FUNC bits 0-10 of the instruction.
+     i        An immediate operand is in bits 0-16 of the instruction. 0 extended
+     I        An immediate operand is in bits 0-16 of the instruction. sign extended
+     d	      An 16 bit PC relative displacement.
+     D	      An immediate operand is in bits 0-25 of the instruction.
+     N	      No opperands needed, for nops.
+     P	      it can be a register or a 16 bit operand.  */
+  char *args;
+};
+
+static const struct dlx_opcode dlx_opcodes[] =
+  {
+  /* Arithmetic and Logic R-TYPE instructions.  */
+    { "nop",      (ALUOP|NOPF),   "N"     },  /* NOP                          */
+    { "add",      (ALUOP|ADDF),   "c,a,b" },  /* Add                          */
+    { "addu",     (ALUOP|ADDUF),  "c,a,b" },  /* Add Unsigned                 */
+    { "sub",      (ALUOP|SUBF),   "c,a,b" },  /* SUB                          */
+    { "subu",     (ALUOP|SUBUF),  "c,a,b" },  /* Sub Unsigned                 */
+    { "mult",     (ALUOP|MULTF),  "c,a,b" },  /* MULTIPLY                     */
+    { "multu",    (ALUOP|MULTUF), "c,a,b" },  /* MULTIPLY Unsigned            */
+    { "div",      (ALUOP|DIVF),   "c,a,b" },  /* DIVIDE                       */
+    { "divu",     (ALUOP|DIVUF),  "c,a,b" },  /* DIVIDE Unsigned              */
+    { "and",      (ALUOP|ANDF),   "c,a,b" },  /* AND                          */
+    { "or",       (ALUOP|ORF),    "c,a,b" },  /* OR                           */
+    { "xor",      (ALUOP|XORF),   "c,a,b" },  /* Exclusive OR                 */
+    { "sll",      (ALUOP|SLLF),   "c,a,b" },  /* SHIFT LEFT LOGICAL           */
+    { "sra",      (ALUOP|SRAF),   "c,a,b" },  /* SHIFT RIGHT ARITHMETIC       */
+    { "srl",      (ALUOP|SRLF),   "c,a,b" },  /* SHIFT RIGHT LOGICAL          */
+    { "seq",      (ALUOP|SEQF),   "c,a,b" },  /* Set if equal                 */
+    { "sne",      (ALUOP|SNEF),   "c,a,b" },  /* Set if not equal             */
+    { "slt",      (ALUOP|SLTF),   "c,a,b" },  /* Set if less                  */
+    { "sgt",      (ALUOP|SGTF),   "c,a,b" },  /* Set if greater               */
+    { "sle",      (ALUOP|SLEF),   "c,a,b" },  /* Set if less or equal         */
+    { "sge",      (ALUOP|SGEF),   "c,a,b" },  /* Set if greater or equal      */
+    { "sequ",     (ALUOP|SEQUF),  "c,a,b" },  /* Set if equal unsigned        */
+    { "sneu",     (ALUOP|SNEUF),  "c,a,b" },  /* Set if not equal unsigned    */
+    { "sltu",     (ALUOP|SLTUF),  "c,a,b" },  /* Set if less unsigned         */
+    { "sgtu",     (ALUOP|SGTUF),  "c,a,b" },  /* Set if greater unsigned      */
+    { "sleu",     (ALUOP|SLEUF),  "c,a,b" },  /* Set if less or equal unsigned*/
+    { "sgeu",     (ALUOP|SGEUF),  "c,a,b" },  /* Set if greater or equal      */
+    { "mvts",     (ALUOP|MVTSF),  "c,a"   },  /* Move to special register     */
+    { "mvfs",     (ALUOP|MVFSF),  "c,a"   },  /* Move from special register   */
+    { "bswap",    (ALUOP|BSWAPF), "c,a,b" },  /* ??? Was not documented       */
+    { "lut",      (ALUOP|LUTF),   "c,a,b" },  /* ????? same as above          */
+
+    /* Arithmetic and Logical Immediate I-TYPE instructions.  */
+    { "addi",     ADDIOP,         "b,a,I" },  /* Add Immediate                */
+    { "addui",    ADDUIOP,        "b,a,i" },  /* Add Usigned Immediate        */
+    { "subi",     SUBIOP,         "b,a,I" },  /* Sub Immediate                */
+    { "subui",    SUBUIOP,        "b,a,i" },  /* Sub Unsigned Immedated       */
+    { "andi",     ANDIOP,         "b,a,i" },  /* AND Immediate                */
+    { "ori",      ORIOP,          "b,a,i" },  /* OR  Immediate                */
+    { "xori",     XORIOP,         "b,a,i" },  /* Exclusive OR  Immediate      */
+    { "slli",     SLLIOP,         "b,a,i" },  /* SHIFT LEFT LOCICAL Immediate */
+    { "srai",     SRAIOP,         "b,a,i" },  /* SHIFT RIGHT ARITH. Immediate */
+    { "srli",     SRLIOP,         "b,a,i" },  /* SHIFT RIGHT LOGICAL Immediate*/
+    { "seqi",     SEQIOP,         "b,a,i" },  /* Set if equal                 */
+    { "snei",     SNEIOP,         "b,a,i" },  /* Set if not equal             */
+    { "slti",     SLTIOP,         "b,a,i" },  /* Set if less                  */
+    { "sgti",     SGTIOP,         "b,a,i" },  /* Set if greater               */
+    { "slei",     SLEIOP,         "b,a,i" },  /* Set if less or equal         */
+    { "sgei",     SGEIOP,         "b,a,i" },  /* Set if greater or equal      */
+    { "sequi",    SEQUIOP,        "b,a,i" },  /* Set if equal                 */
+    { "sneui",    SNEUIOP,        "b,a,i" },  /* Set if not equal             */
+    { "sltui",    SLTUIOP,        "b,a,i" },  /* Set if less                  */
+    { "sgtui",    SGTUIOP,        "b,a,i" },  /* Set if greater               */
+    { "sleui",    SLEUIOP,        "b,a,i" },  /* Set if less or equal         */
+    { "sgeui",    SGEUIOP,        "b,a,i" },  /* Set if greater or equal      */
+    /* Macros for I type instructions.  */
+    { "mov",      ADDIOP,         "b,P"   },  /* a move macro                 */
+    { "movu",     ADDUIOP,        "b,P"   },  /* a move macro, unsigned       */
+
+#if 0
+    /* Move special.  */
+    { "mvts",     MVTSOP,         "b,a"   },  /* Move From Integer to Special */
+    { "mvfs",     MVFSOP,         "b,a"   },  /* Move From Special to Integer */
+#endif
+
+    /* Load high Immediate I-TYPE instruction.  */
+    { "lhi",      LHIOP,          "b,i"   },  /* Load High Immediate          */
+    { "lui",      LHIOP,          "b,i"   },  /* Load High Immediate          */
+    { "sethi",    LHIOP,          "b,i"   },  /* Load High Immediate          */
+
+  /* LOAD/STORE BYTE 8 bits I-TYPE.  */
+    { "lb",       LBOP,           "b,a,I" },  /* Load Byte                    */
+    { "lbu",      LBUOP,          "b,a,I" },  /* Load Byte Unsigned           */
+    { "ldstbu",   LSBUOP,         "b,a,I" },  /* Load store Byte Unsigned     */
+    { "sb",       SBOP,           "b,a,I" },  /* Store Byte                   */
+
+    /* LOAD/STORE HALFWORD 16 bits.  */
+    { "lh",       LHOP,           "b,a,I" },  /* Load Halfword                */
+    { "lhu",      LHUOP,          "b,a,I" },  /* Load Halfword Unsigned       */
+    { "ldsthu",   LSHUOP,         "b,a,I" },  /* Load Store Halfword Unsigned */
+    { "sh",       SHOP,           "b,a,I" },  /* Store Halfword               */
+
+  /* LOAD/STORE WORD 32 bits.  */
+    { "lw",       LWOP,           "b,a,I" },  /* Load Word                    */
+    { "sw",       SWOP,           "b,a,I" },  /* Store Word                   */
+    { "ldstw",    LSWOP,          "b,a,I" },  /* Load Store Word              */
+
+  /* Branch PC-relative, 16 bits offset.  */
+    { "beqz",     BEQOP,          "a,d" },    /* Branch if a == 0             */
+    { "bnez",     BNEOP,          "a,d" },    /* Branch if a != 0             */
+    { "beq",      BEQOP,          "a,d" },    /* Branch if a == 0             */
+    { "bne",      BNEOP,          "a,d" },    /* Branch if a != 0             */
+
+    /* Jumps Trap and RFE J-TYPE.  */
+    { "j",        JOP,            "D" },      /* Jump, PC-relative 26 bits    */
+    { "jal",      JALOP,          "D" },      /* JAL, PC-relative 26 bits     */
+    { "break",    BREAKOP,        "D" },      /* break to OS                  */
+    { "trap" ,    TRAPOP,         "D" },      /* TRAP to OS                   */
+    { "rfe",      RFEOP,          "N" },      /* Return From Exception        */
+    /* Macros.  */
+    { "call",     JOP,            "D" },      /* Jump, PC-relative 26 bits    */
+
+    /* Jumps Trap and RFE I-TYPE.  */
+    { "jr",       JROP,           "a" },      /* Jump Register, Abs (32 bits) */
+    { "jalr",     JALROP,         "a" },      /* JALR, Abs (32 bits)          */
+    /* Macros.  */
+    { "retr",     JROP,           "a" },      /* Jump Register, Abs (32 bits) */
+
+    { "", 0x0, "" }		/* Dummy entry, not included in NUM_OPCODES.
+				   This lets code examine entry i + 1 without
+				   checking if we've run off the end of the table.  */
+  };
+
+const unsigned int num_dlx_opcodes = (((sizeof dlx_opcodes) / (sizeof dlx_opcodes[0])) - 1);
diff --git a/binutils-2.25/include/opcode/h8300.h b/binutils-2.25/include/opcode/h8300.h
new file mode 100644
index 00000000..3296deba
--- /dev/null
+++ b/binutils-2.25/include/opcode/h8300.h
@@ -0,0 +1,1892 @@
+/* Opcode table for the H8/300
+   Copyright 1991-2013 Free Software Foundation, Inc.
+   Written by Steve Chamberlain <sac@cygnus.com>.
+   
+   This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+/* Instructions are stored as a sequence of nibbles.
+   If the nibble has value 15 or less than the representation is complete.
+   Otherwise, we record what it contains with several flags.  */
+
+typedef int op_type;
+
+enum h8_flags
+{
+  L_2  =	0x10,
+  L_3  =	0x20,
+  /* 3 bit constant, zero not accepted.  */
+  L_3NZ =	0x30,
+  L_4  =	0x40,
+  L_5  =	0x50,
+  L_8  =	0x60,
+  L_8U =	0x70,
+  L_16 =	0x80,
+  L_16U =	0x90,
+  L_24 =	0xA0,
+  L_32 =	0xB0,
+  L_P  =	0xC0,
+
+  /* Mask to isolate the L_x size bits.  */
+  SIZE =	0xF0,
+
+  REG =		0x0100,
+  ABS =		0x0200,
+  MEMIND =	0x0300,
+  IMM =		0x0400,
+  DISP =	0x0500,
+  IND =		0x0600,
+  POSTINC =	0x0700,
+  POSTDEC =	0x0800,
+  PREINC =	0x0900,
+  PREDEC =	0x0A00,
+  PCREL =	0x0B00,
+  KBIT =	0x0C00,
+  DBIT =	0x0D00,
+  CONST_2 =     0x0E00,
+  CONST_4 =     0x0F00,
+  CONST_8 =     0x1000,
+  CONST_16 =    0x1100,
+  INDEXB =      0x1200,
+  INDEXW =      0x1300,
+  INDEXL =      0x1400,
+  PCIDXB =      0x1500,
+  PCIDXW =      0x1600,
+  PCIDXL =      0x1700,
+  VECIND =      0x1800,
+  LOWREG =      0x1900,
+  DATA   =      0x2000,
+
+  /* Synonyms.  */
+  INC =		POSTINC,
+  DEC =		PREDEC,
+  /* Control Registers.  */
+  CCR =		0x4000,
+  EXR =		0x4100,
+  MACH = 	0x4200,
+  MACL = 	0x4300,
+  RESERV1 = 	0x4400,
+  RESERV2 = 	0x4500,
+  VBR = 	0x4600,
+  SBR = 	0x4700,
+  MACREG =	0x4800,
+  CCR_EXR = 	0x4900,
+  VBR_SBR = 	0x4A00,
+  CC_EX_VB_SB =	0x4B00,
+  RESERV3 =	0x4C00,
+  RESERV4 = 	0x4D00,
+  RESERV5 = 	0x4E00,
+  RESERV6 = 	0x4F00,
+
+  /* Mask to isolate the addressing mode bits (REG .. PREDEC).  */
+  MODE =	0x7F00,
+
+  CTRL = 	0x4000,
+
+  NO_SYMBOLS =  0x8000,
+  SRC =		0x10000,
+  DST =		0x20000,
+  OP3 =		0x40000,
+  MEMRELAX = 	0x80000,		/* Move insn which may relax.  */
+
+  DISPREG =	0x100000,
+  IGNORE =	0x200000,
+  ABSJMP =	0x400000,
+
+  B00 =         0x800000, 		/* Bit 0 must be low.   */
+  B01 =         0x1000000, 		/* Bit 0 must be high.  */
+  B10 = 	0x2000000, 		/* Bit 1 must be low.   */
+  B11 = 	0x4000000, 		/* Bit 1 must be high.  */
+  B20 = 	0x8000000, 		/* Bit 2 must be low.   */
+  B21 = 	0x10000000, 		/* Bit 2 must be high.  */
+  B30 =		0x20000000, 		/* Bit 3 must be low.   */
+  B31 =		0x40000000,		/* Bit 3 must be high.  */
+  E =  		0x80000000,		/* End of nibble sequence.  */
+
+  /* Immediates smaller than 8 bits are always unsigned.  */
+  IMM3 =	IMM | L_3,
+  IMM4 =	IMM | L_4,
+  IMM5 =	IMM | L_5,
+  IMM3NZ =	IMM | L_3NZ,
+  IMM2 =	IMM | L_2,
+
+  IMM8 =	IMM | SRC | L_8,
+  IMM8U =	IMM | SRC | L_8U,
+  IMM16 =	IMM | SRC | L_16,
+  IMM16U =	IMM | SRC | L_16U,
+  IMM32 =	IMM | SRC | L_32,
+
+  IMM3NZ_NS =   IMM3NZ | NO_SYMBOLS,
+  IMM4_NS =	IMM4 | NO_SYMBOLS,
+  IMM8U_NS =	IMM8U | NO_SYMBOLS,
+  IMM16U_NS =   IMM16U | NO_SYMBOLS,
+
+  RD8  =	DST | L_8  | REG,
+  RD16 =	DST | L_16 | REG,
+  RD32 =	DST | L_32 | REG,
+  R3_8  =       OP3 | L_8  | REG,
+  R3_16 =       OP3 | L_16 | REG,
+  R3_32 =       OP3 | L_32 | REG,
+  RS8  =	SRC | L_8  | REG,
+  RS16 =	SRC | L_16 | REG,
+  RS32 =	SRC | L_32 | REG,
+
+  RSP =		SRC | L_P | REG,
+  RDP =		DST | L_P | REG,
+
+  PCREL8 =	PCREL | L_8,
+  PCREL16 =	PCREL | L_16,
+
+  OP3PCREL8 =	OP3 | PCREL | L_8,
+  OP3PCREL16 =	OP3 | PCREL | L_16,
+
+  INDEXB16  =	INDEXB | L_16,
+  INDEXW16  =	INDEXW | L_16,
+  INDEXL16  =	INDEXL | L_16,
+  INDEXB16D =	INDEXB | L_16 | DST,
+  INDEXW16D =	INDEXW | L_16 | DST,
+  INDEXL16D =	INDEXL | L_16 | DST,
+
+  INDEXB32  =	INDEXB | L_32,
+  INDEXW32  =	INDEXW | L_32,
+  INDEXL32  =	INDEXL | L_32,
+  INDEXB32D =	INDEXB | L_32 | DST,
+  INDEXW32D =	INDEXW | L_32 | DST,
+  INDEXL32D =	INDEXL | L_32 | DST,
+
+  DISP2SRC =	DISP | L_2  | SRC,
+  DISP16SRC =	DISP | L_16 | SRC,
+  DISP32SRC =	DISP | L_32 | SRC,
+
+  DISP2DST =	DISP | L_2  | DST,
+  DISP16DST =	DISP | L_16 | DST,
+  DISP32DST =	DISP | L_32 | DST,
+
+  DSTDISPREG =  DST | DISPREG,
+  SRCDISPREG =  SRC | DISPREG,
+
+  ABS8SRC  = 	SRC | ABS | L_8,
+  ABS16SRC = 	SRC | ABS | L_16U,
+  ABS24SRC = 	SRC | ABS | L_24,
+  ABS32SRC = 	SRC | ABS | L_32,
+
+  ABS8DST  =	DST | ABS | L_8,
+  ABS16DST = 	DST | ABS | L_16U,
+  ABS24DST = 	DST | ABS | L_24,
+  ABS32DST = 	DST | ABS | L_32,
+
+  ABS8OP3  =	OP3 | ABS | L_8,
+  ABS16OP3 = 	OP3 | ABS | L_16U,
+  ABS24OP3 = 	OP3 | ABS | L_24,
+  ABS32OP3 = 	OP3 | ABS | L_32,
+
+  RDDEC =	DST | DEC,
+  RSINC =	SRC | INC,
+  RDINC =	DST | INC,
+
+  RSPOSTINC =	SRC | POSTINC,
+  RDPOSTINC =	DST | POSTINC,
+  RSPREINC =	SRC | PREINC,
+  RDPREINC =	DST | PREINC,
+  RSPOSTDEC =	SRC | POSTDEC,
+  RDPOSTDEC =	DST | POSTDEC,
+  RSPREDEC =	SRC | PREDEC,
+  RDPREDEC =	DST | PREDEC,
+
+  RSIND =	SRC | IND,
+  RDIND =	DST | IND,
+  R3_IND = 	OP3 | IND,
+
+#define MS32	(SRC | L_32 | MACREG)
+#define MD32	(DST | L_32 | MACREG)
+
+#if 1
+  OR8  =	RS8,		/* ??? OR as in One Register.  */
+  OR16 =	RS16,
+  OR32 =	RS32,
+#else
+  OR8  =	RD8,
+  OR16 =	RD16,
+  OR32 =	RD32
+#endif
+};
+
+enum ctrlreg
+{
+  C_CCR  = 0, 
+  C_EXR  = 1, 
+  C_MACH = 2, 
+  C_MACL = 3, 
+  C_VBR  = 6, 
+  C_SBR  = 7
+};
+
+enum {MAX_CODE_NIBBLES = 33};
+
+struct code 
+{
+  op_type nib[MAX_CODE_NIBBLES];
+};
+
+struct arg 
+{
+  op_type nib[3];
+};
+
+/* Availability of instructions on processor models.  */
+enum h8_model
+{
+  AV_H8,
+  AV_H8H,
+  AV_H8S,
+  AV_H8SX
+};
+
+struct h8_opcode 
+{
+  int how;
+  enum h8_model available;
+  int time;
+  char *name;
+  struct arg args;
+  struct code data;
+};
+
+#ifdef DEFINE_TABLE
+
+#define DATA2   DATA, DATA
+#define DATA3   DATA, DATA, DATA
+#define DATA5   DATA, DATA, DATA, DATA, DATA
+#define DATA7   DATA, DATA, DATA, DATA, DATA, DATA, DATA
+
+#define IMM8LIST	IMM8,   DATA
+#define IMM16LIST	IMM16,  DATA3
+#define IMM16ULIST	IMM16U, DATA3
+#define IMM24LIST	IMM24,  DATA5
+#define IMM32LIST	IMM32,  DATA7
+
+#define DISP16LIST DISP | L_16, DATA3
+#define DISP24LIST DISP | L_24, DATA5
+#define DISP32LIST DISP | L_32, DATA7
+
+#define ABS8LIST   ABS  | L_8,   DATA
+#define ABS16LIST  ABS  | L_16U, DATA3
+#define ABS24LIST  ABS  | L_24,  DATA5
+#define ABS32LIST  ABS  | L_32,  DATA7
+
+#define DSTABS8LIST  DST | ABS | L_8,   DATA
+#define DSTABS16LIST DST | ABS | L_16U, DATA3
+#define DSTABS24LIST DST | ABS | L_24,  DATA5
+#define DSTABS32LIST DST | ABS | L_32,  DATA7
+
+#define OP3ABS8LIST  OP3 | ABS | L_8,  DATA
+#define OP3ABS16LIST OP3 | ABS | L_16, DATA3
+#define OP3ABS24LIST OP3 | ABS | L_24, DATA5
+#define OP3ABS32LIST OP3 | ABS | L_32, DATA7
+
+#define DSTDISP16LIST DST | DISP | L_16, DATA3
+#define DSTDISP24LIST DST | DISP | L_24, DATA5
+#define DSTDISP32LIST DST | DISP | L_32, DATA7
+
+#define A16LIST   L_16,  DATA3
+#define A24LIST   L_24,  DATA5
+#define A32LIST   L_32,  DATA7
+
+/* Extended Operand Prefixes:  */
+
+#define PREFIX_010	0x0, 0x1, 0x0
+#define PREFIX_015	0x0, 0x1, 0x5
+#define PREFIX_017	0x0, 0x1, 0x7
+
+#define PREFIX_0100	0x0, 0x1, 0x0, 0x0
+#define PREFIX_010_D2	0x0, 0x1, 0x0, B30 | B21 | DISP2SRC
+#define PREFIX_0101	0x0, 0x1, 0x0, 0x1
+#define PREFIX_0102	0x0, 0x1, 0x0, 0x2
+#define PREFIX_0103	0x0, 0x1, 0x0, 0x3
+#define PREFIX_0104	0x0, 0x1, 0x0, 0x4
+#define PREFIX_0105	0x0, 0x1, 0x0, 0x5
+#define PREFIX_0106	0x0, 0x1, 0x0, 0x6
+#define PREFIX_0107	0x0, 0x1, 0x0, 0x7
+#define PREFIX_0108	0x0, 0x1, 0x0, 0x8
+#define PREFIX_0109	0x0, 0x1, 0x0, 0x9
+#define PREFIX_010A	0x0, 0x1, 0x0, 0xa
+#define PREFIX_010D	0x0, 0x1, 0x0, 0xd
+#define PREFIX_010E	0x0, 0x1, 0x0, 0xe
+
+#define PREFIX_0150	0x0, 0x1, 0x5, 0x0
+#define PREFIX_015_D2	0x0, 0x1, 0x5, B30 | B21 | DISP2SRC
+#define PREFIX_0151	0x0, 0x1, 0x5, 0x1
+#define PREFIX_0152	0x0, 0x1, 0x5, 0x2
+#define PREFIX_0153	0x0, 0x1, 0x5, 0x3
+#define PREFIX_0154	0x0, 0x1, 0x5, 0x4
+#define PREFIX_0155	0x0, 0x1, 0x5, 0x5
+#define PREFIX_0156	0x0, 0x1, 0x5, 0x6
+#define PREFIX_0157	0x0, 0x1, 0x5, 0x7
+#define PREFIX_0158	0x0, 0x1, 0x5, 0x8
+#define PREFIX_0159	0x0, 0x1, 0x5, 0x9
+#define PREFIX_015A	0x0, 0x1, 0x5, 0xa
+#define PREFIX_015D	0x0, 0x1, 0x5, 0xd
+#define PREFIX_015E	0x0, 0x1, 0x5, 0xe
+#define PREFIX_015F	0x0, 0x1, 0x5, 0xf
+
+#define PREFIX_0170	0x0, 0x1, 0x7, 0x0
+#define PREFIX_017_D2S	0x0, 0x1, 0x7, B30 | B21 | DISP2SRC
+#define PREFIX_017_D2D	0x0, 0x1, 0x7, B30 | B21 | DISP2DST
+#define PREFIX_0171	0x0, 0x1, 0x7, 0x1
+#define PREFIX_0172	0x0, 0x1, 0x7, 0x2
+#define PREFIX_0173	0x0, 0x1, 0x7, 0x3
+#define PREFIX_0174	0x0, 0x1, 0x7, 0x4
+#define PREFIX_0175	0x0, 0x1, 0x7, 0x5
+#define PREFIX_0176	0x0, 0x1, 0x7, 0x6
+#define PREFIX_0177	0x0, 0x1, 0x7, 0x7
+#define PREFIX_0178	0x0, 0x1, 0x7, 0x8
+#define PREFIX_0179	0x0, 0x1, 0x7, 0x9
+#define PREFIX_017A	0x0, 0x1, 0x7, 0xa
+#define PREFIX_017D	0x0, 0x1, 0x7, 0xd
+#define PREFIX_017E	0x0, 0x1, 0x7, 0xe
+#define PREFIX_017F	0x0, 0x1, 0x7, 0xf
+
+#define PREFIX_6A15	0x6, 0xa, 0x1, 0x5
+#define PREFIX_6A35	0x6, 0xa, 0x3, 0x5
+#define PREFIX_6B15	0x6, 0xb, 0x1, 0x5
+#define PREFIX_6B35	0x6, 0xb, 0x3, 0x5
+
+#define PREFIX_78R4	0x7, 0x8, B31 | DISPREG, 0x4
+#define PREFIX_78R5	0x7, 0x8, B31 | DISPREG, 0x5
+#define PREFIX_78R6	0x7, 0x8, B31 | DISPREG, 0x6
+#define PREFIX_78R7	0x7, 0x8, B31 | DISPREG, 0x7
+
+#define PREFIX_78R4W	0x7, 0x8, B30 | DISPREG, 0x4
+#define PREFIX_78R5W	0x7, 0x8, B30 | DISPREG, 0x5
+#define PREFIX_78R6W	0x7, 0x8, B30 | DISPREG, 0x6
+#define PREFIX_78R7W	0x7, 0x8, B30 | DISPREG, 0x7
+
+#define PREFIX_78R4WD	0x7, 0x8, B30 | DSTDISPREG, 0x4
+#define PREFIX_78R5WD	0x7, 0x8, B30 | DSTDISPREG, 0x5
+#define PREFIX_78R6WD	0x7, 0x8, B30 | DSTDISPREG, 0x6
+#define PREFIX_78R7WD	0x7, 0x8, B30 | DSTDISPREG, 0x7
+
+#define PREFIX_7974	0x7, 0x9, 0x7, 0x4
+#define PREFIX_7A74	0x7, 0xa, 0x7, 0x4
+#define PREFIX_7A7C	0x7, 0xa, 0x7, 0xc
+
+
+/* Source standard fragment:  */
+#define FROM_IND	 0, RSIND
+#define FROM_POSTINC	 8, RSPOSTINC
+#define FROM_POSTDEC	10, RSPOSTDEC
+#define FROM_PREINC	 9, RSPREINC
+#define FROM_PREDEC	11, RSPREDEC
+#define FROM_DISP2	B30 | B20 | DISP2SRC, DISPREG 
+#define FROM_DISP16	12, B30 | DISPREG
+#define FROM_DISP32	12, B31 | DISPREG
+#define FROM_DISP16B	13, B30 | DISPREG
+#define FROM_DISP16W	14, B30 | DISPREG
+#define FROM_DISP16L	15, B30 | DISPREG
+#define FROM_DISP32B	13, B31 | DISPREG
+#define FROM_DISP32W	14, B31 | DISPREG
+#define FROM_DISP32L	15, B31 | DISPREG
+#define FROM_ABS16	 4, B30 | IGNORE
+#define FROM_ABS32	 4, B31 | IGNORE
+
+/* Destination standard fragment:  */
+#define TO_IND		 0, RDIND
+#define TO_IND_MOV	 0, RDIND | B30
+#define TO_POSTINC	 8, RDPOSTINC
+#define TO_POSTINC_MOV	 8, RDPOSTINC | B30
+#define TO_POSTDEC	10, RDPOSTDEC
+#define TO_POSTDEC_MOV	10, RDPOSTDEC | B30
+#define TO_PREINC	 9, RDPREINC
+#define TO_PREINC_MOV	 9, RDPREINC  | B30
+#define TO_PREDEC	11, RDPREDEC
+#define TO_PREDEC_MOV	11, RDPREDEC  | B30
+#define TO_DISP2	B30 | B20 | DISP2DST, DSTDISPREG
+#define TO_DISP2_MOV	B30 | B20 | DISP2DST, DSTDISPREG | B30
+#define TO_DISP16	12, B30 | DSTDISPREG
+#define TO_DISP32	12, B31 | DSTDISPREG
+#define TO_DISP16B	13, B30 | DSTDISPREG
+#define TO_DISP16W	14, B30 | DSTDISPREG
+#define TO_DISP16L	15, B30 | DSTDISPREG
+#define TO_DISP32B	13, B31 | DSTDISPREG
+#define TO_DISP32W	14, B31 | DSTDISPREG
+#define TO_DISP32L	15, B31 | DSTDISPREG
+#define TO_ABS16	 4, B30 | IGNORE
+#define TO_ABS32	 4, B31 | IGNORE
+
+/* Source fragment for three-word instruction:  */
+#define TFROM_IND	6,  9, B30 | RSIND, 12
+#define TFROM_DISP2	6,  9, B30 | DISPREG, 12
+#define TFROM_ABS16	6, 11, B30 | B20 | B10 | IGNORE, 12, ABS16LIST
+#define TFROM_ABS32	6, 11, B30 | B20 | B11 | IGNORE, 12, ABS32LIST
+#define TFROM_POSTINC	6, 13, B30 | RSPOSTINC, 12
+#define TFROM_PREINC	6, 13, B30 | RSPREINC, 12
+#define TFROM_POSTDEC	6, 13, B30 | RSPOSTDEC, 12
+#define TFROM_PREDEC	6, 13, B30 | RSPREDEC, 12
+#define TFROM_DISP16	6, 15, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP32	6, 11, 2, 12, DISP32LIST
+#define TFROM_DISP16B	6, 15, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP16W	6, 15, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP16L	6, 15, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP32B	6, 11, 2, 12, DISP32LIST
+#define TFROM_DISP32W	6, 11, 2, 12, DISP32LIST
+#define TFROM_DISP32L	6, 11, 2, 12, DISP32LIST
+#define TFROM_ABS16W	6, 11, 1, 12, ABS16LIST
+#define TFROM_ABS32W	6, 11, 3, 12, ABS32LIST
+
+/* Source fragment for three-word instruction:  */
+#define TFROM_IND_B	6,  8, B30 | RSIND, 12
+#define TFROM_ABS16_B	6, 10, B30 | B20 | B10 | IGNORE, 12, ABS16LIST
+#define TFROM_ABS32_B	6, 10, B30 | B20 | B11 | IGNORE, 12, ABS32LIST
+
+#define TFROM_DISP2_B	6,  8, B30 | DISPREG, 12
+#define TFROM_POSTINC_B	6, 12, B30 | RSPOSTINC, 12
+#define TFROM_PREINC_B	6, 12, B30 | RSPREINC, 12
+#define TFROM_POSTDEC_B	6, 12, B30 | RSPOSTDEC, 12
+#define TFROM_PREDEC_B	6, 12, B30 | RSPREDEC, 12
+#define TFROM_DISP16_B	6, 14, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP32_B	6, 10, 2, 12, DISP32LIST
+#define TFROM_DISP16B_B	6, 14, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP16W_B	6, 14, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP16L_B	6, 14, B30 | DISPREG, 12, DISP16LIST
+#define TFROM_DISP32B_B	6, 10, 2, 12, DISP32LIST
+#define TFROM_DISP32W_B	6, 10, 2, 12, DISP32LIST
+#define TFROM_DISP32L_B	6, 10, 2, 12, DISP32LIST
+
+#define TFROM_ABS16W_B	6, 10, 1, 12, ABS16LIST
+#define TFROM_ABS32W_B	6, 10, 3, 12, ABS32LIST
+
+/* Extended Operand Class Expanders:  */
+
+#define MOVFROM_STD(CODE, PREFIX, NAME, SRC, SRC_INFIX) \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}},  {{PREFIX, SRC_INFIX, TO_IND_MOV,     E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}},  {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}},  {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}},  {{PREFIX, SRC_INFIX, TO_PREINC_MOV,  E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}},  {{PREFIX, SRC_INFIX, TO_PREDEC_MOV,  E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}},  {{PREFIX, SRC_INFIX, TO_DISP2_MOV,   E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP16,  DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP32,  DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16B, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16W, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16L, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32B, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32W, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32L, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}},  {{PREFIX, SRC_INFIX, TO_ABS16,   DSTABS16LIST,  E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}},  {{PREFIX, SRC_INFIX, TO_ABS32,   DSTABS32LIST,  E}}}
+
+#define MOVFROM_AD(CODE, PREFIX, NAME, SRC, SRC_INFIX, SRC_SUFFIX) \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}},  {{PREFIX, SRC_INFIX, TO_IND_MOV,     SRC_SUFFIX, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}},  {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, SRC_SUFFIX, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}},  {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, SRC_SUFFIX, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}},  {{PREFIX, SRC_INFIX, TO_PREINC_MOV,  SRC_SUFFIX, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}},  {{PREFIX, SRC_INFIX, TO_PREDEC_MOV,  SRC_SUFFIX, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}},  {{PREFIX, SRC_INFIX, TO_DISP2_MOV,   SRC_SUFFIX, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP16,  SRC_SUFFIX, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP32,  SRC_SUFFIX, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16B, SRC_SUFFIX, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16W, SRC_SUFFIX, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16L, SRC_SUFFIX, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32B, SRC_SUFFIX, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32W, SRC_SUFFIX, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32L, SRC_SUFFIX, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}},  {{PREFIX, SRC_INFIX, TO_ABS16,   SRC_SUFFIX, DSTABS16LIST,  E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}},  {{PREFIX, SRC_INFIX, TO_ABS32,   SRC_SUFFIX, DSTABS32LIST,  E}}}
+
+#define MOVFROM_IMM8(CODE, PREFIX, NAME, SRC) \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}},  {{PREFIX,  0, RDIND,     IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}},  {{PREFIX,  8, RDPOSTINC, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}},  {{PREFIX, 10, RDPOSTDEC, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}},  {{PREFIX,  9, RDPREINC,  IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}},  {{PREFIX, 11, RDPREDEC,  IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}},  {{PREFIX, B30 | B20 | DISP2DST, DSTDISPREG, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}},  {{PREFIX, 12, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}},  {{PREFIX, 12, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}},  {{PREFIX, 13, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}},  {{PREFIX, 14, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}},  {{PREFIX, 15, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}},  {{PREFIX, 13, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}},  {{PREFIX, 14, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}},  {{PREFIX, 15, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}},  {{PREFIX,  4, B30 | IGNORE,     IMM8LIST, DSTABS16LIST,  E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}},  {{PREFIX,  4, B31 | IGNORE,     IMM8LIST, DSTABS32LIST,  E}}}
+
+#define MOVFROM_IMM(CODE, PREFIX, NAME, SRC, LIST) \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}},  {{PREFIX, LIST,  0, RDIND,     DATA2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}},  {{PREFIX, LIST,  8, RDPOSTINC, DATA2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}},  {{PREFIX, LIST, 10, RDPOSTDEC, DATA2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}},  {{PREFIX, LIST,  9, RDPREINC,  DATA2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}},  {{PREFIX, LIST, 11, RDPREDEC,  DATA2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}},  {{PREFIX, LIST, B30 | B20 | DISP2DST, DSTDISPREG, DATA2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}},  {{PREFIX, LIST, 12, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}},  {{PREFIX, LIST, 12, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}},  {{PREFIX, LIST, 13, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}},  {{PREFIX, LIST, 14, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}},  {{PREFIX, LIST, 15, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}},  {{PREFIX, LIST, 13, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}},  {{PREFIX, LIST, 14, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}},  {{PREFIX, LIST, 15, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}},  {{PREFIX, LIST,  4, B30 | IGNORE,     DATA2, DSTABS16LIST,  E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}},  {{PREFIX, LIST,  4, B31 | IGNORE,     DATA2, DSTABS32LIST,  E}}}
+
+#define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
+  {CODE, AV_H8,   4, NAME, {{SRC, RDIND,     E}}, {{                              6, OP1, B31 | RDIND,      SRC,                E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 3,                    6, OP3, B31 | RDPOSTINC,  SRC,                E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 1,                    6, OP3, B31 | RDPOSTDEC,  SRC,                E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, 2,                    6, OP3, B31 | RDPREINC,   SRC,                E}}}, \
+  {CODE, AV_H8,   6, NAME, {{SRC, RDPREDEC,  E}}, {{                              6, OP3, B31 | RDPREDEC,   SRC,                E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, B30 | B20 | DISP2DST, 6, OP1, B31 | DSTDISPREG, SRC,                E}}}, \
+  {CODE, AV_H8,   6, NAME, {{SRC, DISP16DST, E}}, {{                              6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8,   6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0,    6, OP2, 10,               SRC, MEMRELAX | DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 1,                    6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 2,                    6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 3,                    6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1,    6, OP2, 10,               SRC, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2,    6, OP2, 10,               SRC, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3,    6, OP2, 10,               SRC, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8,   4, NAME, {{SRC, ABS16DST,  E}}, {{                              6, OP2, 8,                SRC, RELAX16  | DSTABS16LIST, E}}}, \
+  {CODE, AV_H8,   6, NAME, {{SRC, ABS32DST,  E}}, {{                              6, OP2, 10,               SRC, MEMRELAX | DSTABS32LIST, E}}}
+
+#define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
+  {CODE, AV_H8,   4, NAME, {{RSIND,     DST, E}}, {{                              6, OP1, B30 | RSIND,     DST,             E}}}, \
+  {CODE, AV_H8,   6, NAME, {{RSPOSTINC, DST, E}}, {{                              6, OP3, B30 | RSPOSTINC, DST,             E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, 2,                    6, OP3, B30 | RSPOSTDEC, DST,             E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREINC,  DST, E}}, {{PREFIX, 1,                    6, OP3, B30 | RSPREINC,  DST,             E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREDEC,  DST, E}}, {{PREFIX, 3,                    6, OP3, B30 | RSPREDEC,  DST,             E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP2SRC,  DST, E}}, {{PREFIX, B30 | B20 | DISP2SRC, 6, OP1, B30 | DISPREG,   DST,             E}}}, \
+  {CODE, AV_H8,   6, NAME, {{DISP16SRC, DST, E}}, {{                              6, OP4, B30 | DISPREG,   DST, DISP16LIST, E}}}, \
+  {CODE, AV_H8,   6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0,       6, OP2, 2,               DST, MEMRELAX | DISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB16,  DST, E}}, {{PREFIX, 1,                    6, OP4, B30 | DISPREG,   DST, DISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW16,  DST, E}}, {{PREFIX, 2,                    6, OP4, B30 | DISPREG,   DST, DISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL16,  DST, E}}, {{PREFIX, 3,                    6, OP4, B30 | DISPREG,   DST, DISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB32,  DST, E}}, {{7, 8, B30 | DISPREG, 1,       6, OP2, 2,               DST, DISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW32,  DST, E}}, {{7, 8, B30 | DISPREG, 2,       6, OP2, 2,               DST, DISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL32,  DST, E}}, {{7, 8, B30 | DISPREG, 3,       6, OP2, 2,               DST, DISP32LIST, E}}}, \
+  {CODE, AV_H8,   4, NAME, {{ABS16SRC,  DST, E}}, {{                              6, OP2, 0,               DST, RELAX16  | ABS16LIST, E}}}, \
+  {CODE, AV_H8,   6, NAME, {{ABS32SRC,  DST, E}}, {{                              6, OP2, 2,               DST, MEMRELAX | ABS32LIST, E}}}
+
+/* Expansion macros for two-word (plus data) instructions.  */
+
+/* Expansion from one source to "standard" destinations.  */
+#define EXPAND2_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, NIB1, NIB2) \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, TO_PREINC,  NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}}, {{PREFIX, TO_PREDEC,  NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, TO_DISP2,   NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16,  NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32,  NIB1, NIB2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}}
+
+/* Expansion from one destination to "standard" sources.  */
+#define EXPAND2_STD_DST(CODE, WEIGHT, NAME, DST, PREFIX, NIB1, NIB2) \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, DST, E}}, {{PREFIX, FROM_POSTINC, NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, FROM_POSTDEC, NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREINC,  DST, E}}, {{PREFIX, FROM_PREINC,  NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREDEC,  DST, E}}, {{PREFIX, FROM_PREDEC,  NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP2SRC,  DST, E}}, {{PREFIX, FROM_DISP2,   NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, DST, E}}, {{PREFIX, FROM_DISP16,  NIB1, NIB2, DISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, DST, E}}, {{PREFIX, FROM_DISP32,  NIB1, NIB2, DISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB16,  DST, E}}, {{PREFIX, FROM_DISP16B, NIB1, NIB2, DISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW16,  DST, E}}, {{PREFIX, FROM_DISP16W, NIB1, NIB2, DISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL16,  DST, E}}, {{PREFIX, FROM_DISP16L, NIB1, NIB2, DISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB32,  DST, E}}, {{PREFIX, FROM_DISP32B, NIB1, NIB2, DISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW32,  DST, E}}, {{PREFIX, FROM_DISP32W, NIB1, NIB2, DISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL32,  DST, E}}, {{PREFIX, FROM_DISP32L, NIB1, NIB2, DISP32LIST, E}}}
+
+/* Expansion from immediate source to "standard" destinations.  */
+#define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, TO_PREINC,  OPCODE, IGN, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}}, {{PREFIX, TO_PREDEC,  OPCODE, IGN, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, TO_DISP2,   OPCODE, IGN, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16,  OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32,  OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}
+
+/* Expansion from abs/disp source to "standard" destinations.  */
+#define EXPAND2_STD_ABSDISP(CODE, WEIGHT, NAME, SRC, PREFIX, DSTLIST, NIB1, NIB2) \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, DSTLIST, TO_POSTINC, NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, DSTLIST, TO_POSTDEC, NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, DSTLIST, TO_PREINC,  NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}}, {{PREFIX, DSTLIST, TO_PREDEC,  NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, DSTLIST, TO_DISP2,   NIB1, NIB2, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, DSTLIST, TO_DISP16,  NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, DSTLIST, TO_DISP32,  NIB1, NIB2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, DSTLIST, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, DSTLIST, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, DSTLIST, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, DSTLIST, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, DSTLIST, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, DSTLIST, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}}
+
+/* Expansion from ind source to "standard" destinations.  */
+#define EXPAND2_STD_IND(CODE, WEIGHT, NAME, OPCODE, BIT) \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTINC, OPCODE, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTDEC, OPCODE, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREINC,  E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREINC,  OPCODE, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREDEC,  E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREDEC,  OPCODE, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP2DST,  E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP2,   OPCODE, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP16DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16,  OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP32DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32,  OPCODE, IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16B, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16W, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16L, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32B, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32W, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32L, OPCODE, IGNORE, DSTDISP32LIST, E}}}
+
+/* Expansion macros for three word (plus data) instructions.  */
+
+#define EXPAND3_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE)  \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX,  8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, INFIX,  9, RDPREINC,  OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}}, {{PREFIX, INFIX, 11, RDPREDEC,  OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}
+
+#define EXPAND3_L_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE)  \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}}, {{PREFIX, INFIX,  0, RDIND,     OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX,  8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}}, {{PREFIX, INFIX,  9, RDPREINC,  OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}}, {{PREFIX, INFIX, 11, RDPREDEC,  OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}}, {{PREFIX, INFIX,  4, B30 | IGNORE,     OPCODE, B30 | IGNORE, DSTABS16LIST,  E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}}, {{PREFIX, INFIX,  4, B31 | IGNORE,     OPCODE, B30 | IGNORE, DSTABS32LIST,  E}}}
+
+
+#define EXPAND_STD_MATRIX_L(CODE, NAME, OPCODE) \
+  EXPAND3_L_SRC (CODE, 6, NAME, RSIND,     PREFIX_0104,   TFROM_IND,     OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTINC, PREFIX_0104,   TFROM_POSTINC, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTDEC, PREFIX_0106,   TFROM_POSTDEC, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, RSPREINC,  PREFIX_0105,   TFROM_PREINC,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, RSPREDEC,  PREFIX_0107,   TFROM_PREDEC,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, DISP2SRC,  PREFIX_010_D2, TFROM_DISP2,   OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, DISP16SRC, PREFIX_0104,   TFROM_DISP16,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, DISP32SRC, PREFIX_78R4,   TFROM_DISP32,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, INDEXB16,  PREFIX_0105,   TFROM_DISP16B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, INDEXW16,  PREFIX_0106,   TFROM_DISP16W, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, INDEXL16,  PREFIX_0107,   TFROM_DISP16L, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, INDEXB32,  PREFIX_78R5,   TFROM_DISP32B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, INDEXW32,  PREFIX_78R6,   TFROM_DISP32W, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, INDEXL32,  PREFIX_78R7,   TFROM_DISP32L, OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, ABS16SRC,  PREFIX_0104,   TFROM_ABS16,   OPCODE), \
+  EXPAND3_L_SRC (CODE, 6, NAME, ABS32SRC,  PREFIX_0104,   TFROM_ABS32,   OPCODE)
+
+
+#define EXPAND_STD_MATRIX_W(CODE, NAME, OPCODE) \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0154,   TFROM_POSTINC, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0156,   TFROM_POSTDEC, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC,  PREFIX_0155,   TFROM_PREINC,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC,  PREFIX_0157,   TFROM_PREDEC,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC,  PREFIX_015_D2, TFROM_DISP2,   OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0154,   TFROM_DISP16,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W,  TFROM_DISP32,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16,  PREFIX_0155,   TFROM_DISP16B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16,  PREFIX_0156,   TFROM_DISP16W, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16,  PREFIX_0157,   TFROM_DISP16L, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32,  PREFIX_78R5W,  TFROM_DISP32B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32,  PREFIX_78R6W,  TFROM_DISP32W, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32,  PREFIX_78R7W,  TFROM_DISP32L, OPCODE)
+
+#define EXPAND_STD_MATRIX_B(CODE, NAME, OPCODE) \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0174,    TFROM_POSTINC_B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0176,    TFROM_POSTDEC_B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC,  PREFIX_0175,    TFROM_PREINC_B,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC,  PREFIX_0177,    TFROM_PREDEC_B,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC,  PREFIX_017_D2S, TFROM_DISP2_B,   OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0174,    TFROM_DISP16_B,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W,   TFROM_DISP32_B,  OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16,  PREFIX_0175,    TFROM_DISP16B_B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16,  PREFIX_0176,    TFROM_DISP16W_B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16,  PREFIX_0177,    TFROM_DISP16L_B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32,  PREFIX_78R5W,   TFROM_DISP32B_B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32,  PREFIX_78R6W,   TFROM_DISP32W_B, OPCODE), \
+  EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32,  PREFIX_78R7W,   TFROM_DISP32L_B, OPCODE)
+
+
+/* Use the expansion macros to fill out the opcode table.  */
+
+#define EXPAND_FROM_REG8(CODE, NAME, OP1, OP2, OP3) \
+  {CODE, AV_H8SX, 0, NAME, {{RS8, RDIND,     E}}, {{0x7, 0xd, B30 | RDIND, IGNORE,             OP1, OP2, RS8, IGNORE, E}}}, \
+  EXPAND2_STD_SRC (CODE, 2, NAME, RS8, PREFIX_0179, OP3, RS8), \
+  {CODE, AV_H8SX, 0, NAME, {{RS8, ABS8DST,   E}}, {{0x7, 0xf, DSTABS8LIST,                     OP1, OP2, RS8, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RS8, ABS16DST,  E}}, {{0x6, 0xa, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS8, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RS8, ABS32DST,  E}}, {{0x6, 0xa, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS8, IGNORE, E}}}
+
+#define EXPAND_TO_REG8(CODE, NAME, OP1, OP2, OP3) \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RD8,     E}}, {{0x7, 0xc, B30 | RSIND, IGNORE,          OP1, OP2, IGNORE, RD8, E}}}, \
+  EXPAND2_STD_DST (CODE, 2, NAME, RD8, PREFIX_017A, OP3, RD8), \
+  {CODE, AV_H8SX, 0, NAME, {{ABS8SRC,  RD8,  E}}, {{0x7, 0xe, ABS8LIST,                     OP1, OP2, IGNORE, RD8, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD8,  E}}, {{0x6, 0xa, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD8, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD8,  E}}, {{0x6, 0xa, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD8, E}}}
+
+#define EXPAND_FROM_IND8(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND,    E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_IND,   OPCODE, IGNORE, E}}}, \
+  EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B30), \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
+
+#define EXPAND_FROM_ABS16_B(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND,    E}}, {{PREFIX_6A15, ABS16LIST, TO_IND,   OPCODE, IGNORE, E}}}, \
+  EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6A15, ABS16LIST, OPCODE, IGNORE), \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
+
+#define EXPAND_FROM_ABS32_B(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND,    E}}, {{PREFIX_6A35, ABS32LIST, TO_IND,   OPCODE, IGNORE, E}}}, \
+  EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6A35, ABS32LIST, OPCODE, IGNORE), \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
+
+#define EXPAND_FROM_IMM16_W(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{IMM16, RDIND,    E}}, {{PREFIX_015E, TO_IND, OPCODE, IGNORE, IMM16LIST, E}}}, \
+  EXPAND2_STD_IMM (CODE, 2, NAME, IMM16, PREFIX_015E, OPCODE, IGNORE, IMM16LIST), \
+  {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS16DST, E}}, {{PREFIX_015E, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, IMM16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS32DST, E}}, {{PREFIX_015E, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, IMM16LIST, E}}}
+
+#define EXPAND_FROM_REG16(CODE, NAME, OP1, OP2, OP3) \
+  {CODE, AV_H8,   2, NAME, {{RS16, RDIND,    E}}, {{0x7, 0xd, B31 | RDIND, IGNORE,             OP1, OP2, RS16, IGNORE, E}}}, \
+  EXPAND2_STD_SRC (CODE, 2, NAME, RS16, PREFIX_0159, OP3, RS16), \
+  {CODE, AV_H8SX, 0, NAME, {{RS16, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS16, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RS16, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS16, IGNORE, E}}}
+
+#define EXPAND_TO_REG16(CODE, NAME, OP1, OP2, OP3) \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RD16,    E}}, {{0x7, 0xc, B31 | RSIND, IGNORE,          OP1, OP2, IGNORE, RD16, E}}}, \
+  EXPAND2_STD_DST (CODE, 2, NAME, RD16, PREFIX_015A, OP3, RD16), \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD16, E}}, {{0x6, 0xb, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD16, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD16, E}}, {{0x6, 0xb, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD16, E}}}
+
+#define EXPAND_FROM_IND16(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND,    E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \
+  EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B31), \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
+
+#define EXPAND_FROM_ABS16_W(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND,    E}}, {{PREFIX_6B15, ABS16LIST, TO_IND,   OPCODE, IGNORE, E}}}, \
+  EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6B15, ABS16LIST, OPCODE, IGNORE), \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
+
+#define EXPAND_FROM_ABS32_W(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND,    E}}, {{PREFIX_6B35, ABS32LIST, TO_IND,   OPCODE, IGNORE, E}}}, \
+  EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6B35, ABS32LIST, OPCODE, IGNORE), \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}}
+
+#define EXPAND_FROM_IMM16_L(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RDIND,    E}}, {{PREFIX_010E, TO_IND, OPCODE, B30 | IGNORE, IMM16ULIST, E}}}, \
+  EXPAND2_STD_IMM (CODE, 2, NAME, IMM16U_NS, PREFIX_010E, OPCODE, B30 | IGNORE, IMM16ULIST), \
+  {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B30 | IGNORE, DSTABS16LIST, IMM16ULIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B30 | IGNORE, DSTABS32LIST, IMM16ULIST, E}}}
+
+#define EXPAND_FROM_IMM32_L(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{IMM32, RDIND,    E}}, {{PREFIX_010E, TO_IND, OPCODE, B31 | IGNORE, IMM32LIST, E}}}, \
+  EXPAND2_STD_IMM (CODE, 2, NAME, IMM32, PREFIX_010E, OPCODE, B31 | IGNORE, IMM32LIST), \
+  {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B31 | IGNORE, DSTABS16LIST, IMM32LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B31 | IGNORE, DSTABS32LIST, IMM32LIST, E}}}
+
+#define EXPAND_FROM_REG32(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{RS32, RDIND,    E}}, {{PREFIX_0109, TO_IND,   OPCODE, B30 | RS32, E}}}, \
+  EXPAND2_STD_SRC (CODE, 2, NAME, RS32, PREFIX_0109, OPCODE, B30 | RS32), \
+  {CODE, AV_H8SX, 0, NAME, {{RS32, ABS16DST, E}}, {{PREFIX_0109, TO_ABS16, OPCODE, B30 | RS32, DSTABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RS32, ABS32DST, E}}, {{PREFIX_0109, TO_ABS32, OPCODE, B30 | RS32, DSTABS32LIST, E}}}
+
+#define EXPAND_TO_REG32(CODE, NAME, OPCODE) \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND, RD32,    E}}, {{PREFIX_010A, FROM_IND,   OPCODE, B30 | RD32, E}}}, \
+  EXPAND2_STD_DST (CODE, 2, NAME, RD32, PREFIX_010A, OPCODE, B30 | RD32), \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS16, OPCODE, B30 | RD32, ABS16LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS32, OPCODE, B30 | RD32, ABS32LIST, E}}}
+
+
+#define EXPAND_TWOOP_B(CODE, NAME, OP1, OP2, OP3, OP4, BIT) \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, RDIND,     E}}, {{0x7, 0xd,                 B30 | RDIND,            IGNORE,                      OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTINC, E}}, {{PREFIX_0174,    0x6, 0xc, B30 | RDPOSTINC,  B31 | B20 | IGNORE,                OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176,    0x6, 0xc, B30 | RDPOSTDEC,  B31 | B20 | IGNORE,                OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREINC,  E}}, {{PREFIX_0175,    0x6, 0xc, B30 | RDPREINC,   B31 | B20 | IGNORE,                OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREDEC,  E}}, {{PREFIX_0177,    0x6, 0xc, B30 | RDPREDEC,   B31 | B20 | IGNORE,                OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP2DST,  E}}, {{PREFIX_017_D2D, 0x6, 0x8, B30 | DSTDISPREG, B31 | B20 | IGNORE,                OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP16DST, E}}, {{PREFIX_0174,    0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP32DST, E}}, {{PREFIX_78R4WD,  0x6, 0xa, 2,                B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB16D, E}}, {{PREFIX_0175,    0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW16D, E}}, {{PREFIX_0176,    0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL16D, E}}, {{PREFIX_0177,    0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB32D, E}}, {{PREFIX_78R5WD,  0x6, 0xa, 2,                B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW32D, E}}, {{PREFIX_78R6WD,  0x6, 0xa, 2,                B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL32D, E}}, {{PREFIX_78R7WD,  0x6, 0xa, 2,                B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS8DST,   E}}, {{0x7, 0xf,                                                       DSTABS8LIST,   OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS16DST,  E}}, {{0x6, 0xa, 0x1,                              B31 | B20 | IGNORE, DSTABS16LIST,  OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS32DST,  E}}, {{0x6, 0xa, 0x3,                              B31 | B20 | IGNORE, DSTABS32LIST,  OP1, BIT | IGNORE, IMM8LIST, E}}}, \
+  {CODE, AV_H8,   2, NAME, {{RS8,  RD8,       E}}, {{OP2, OP3, RS8, RD8, E}}}, \
+  EXPAND_FROM_REG8      (CODE, NAME, OP2, OP3, OP4), \
+  EXPAND_TO_REG8        (CODE, NAME, OP2, OP3, OP4), \
+  EXPAND_FROM_IND8      (CODE, NAME, OP4), \
+  EXPAND_STD_MATRIX_B   (CODE, NAME, OP4), \
+  EXPAND_FROM_ABS16_B   (CODE, NAME, OP4), \
+  EXPAND_FROM_ABS32_B   (CODE, NAME, OP4)
+
+#define EXPAND_TWOOP_W(CODE, NAME, OP1, OP2, OP3) \
+  {CODE, AV_H8H,  6, NAME, {{IMM16, RD16, E}}, {{0x7, 0x9, OP3, RD16, IMM16LIST, E}}}, \
+  EXPAND_FROM_IMM16_W   (CODE, NAME, OP3), \
+  EXPAND_FROM_REG16     (CODE, NAME, OP1, OP2, OP3), \
+  EXPAND_TO_REG16       (CODE, NAME, OP1, OP2, OP3), \
+  EXPAND_FROM_IND16     (CODE, NAME, OP3), \
+  EXPAND_STD_MATRIX_W   (CODE, NAME, OP3), \
+  EXPAND_FROM_ABS16_W   (CODE, NAME, OP3), \
+  EXPAND_FROM_ABS32_W   (CODE, NAME, OP3)
+
+#define EXPAND_TWOOP_L(CODE, NAME, OP1)  \
+  {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, OP1, B31 | RD32, IMM16ULIST, E}}}, \
+  {CODE, AV_H8H,  6, NAME, {{IMM32,     RD32, E}}, {{0x7, 0xa, OP1, B30 | RD32, IMM32LIST,  E}}}, \
+  EXPAND_FROM_IMM16_L   (CODE, NAME, OP1), \
+  EXPAND_FROM_IMM32_L   (CODE, NAME, OP1), \
+  EXPAND_FROM_REG32     (CODE, NAME, OP1), \
+  EXPAND_TO_REG32       (CODE, NAME, OP1), \
+  EXPAND_STD_MATRIX_L   (CODE, NAME, OP1)
+
+
+/* Old expanders:  */
+
+#define BITOP(code, imm, name, op00, op01, op10,  op11, op20, op21, op30, op4) \
+  {code, AV_H8,  2, name, {{imm, RD8,      E}}, {{op00, op01, imm,  RD8,   E}}}, \
+  {code, AV_H8,  6, name, {{imm, RDIND,    E}}, {{op10, op11, B30 | RDIND, 0,  op00, op01, imm, 0, E}}}, \
+  {code, AV_H8,  6, name, {{imm, ABS8DST,  E}}, {{op20, op21, DSTABS8LIST,     op00, op01, imm, 0, E}}}, \
+  {code, AV_H8S, 6, name, {{imm, ABS16DST, E}}, {{0x6,  0xa,  0x1,  op30, DST | MEMRELAX | ABS16LIST , op00, op01, imm, op4, E}}}, \
+  {code, AV_H8S, 6, name, {{imm, ABS32DST, E}}, {{0x6,  0xa,  0x3,  op30, DST | MEMRELAX | ABS32LIST , op00, op01, imm, op4, E}}}
+
+#define BITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
+  {code, AV_H8SX, 0, name, {{imm, RDIND,    E}}, {{op10, op11, B30 | RDIND, 0,  op00, op01, imm, op4, E}}}, \
+  {code, AV_H8SX, 0, name, {{imm, ABS8DST,  E}}, {{op20, op21, DSTABS8LIST,     op00, op01, imm, op4, E}}}, \
+  {code, AV_H8SX, 0, name, {{imm, ABS16DST, E}}, {{0x6,  0xa,  0x1,  op30, DST | ABS16LIST, op00, op01, imm, op4, E}}}, \
+  {code, AV_H8SX, 0, name, {{imm, ABS32DST, E}}, {{0x6,  0xa,  0x3,  op30, DST | ABS32LIST, op00, op01, imm, op4, E}}}
+
+#define EBITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
+  BITOP(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \
+  BITOP(code, RS8, name, op00,   op01, op10, op11, op20, op21, op30, op4)
+
+#define EBITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
+  BITOP_B(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \
+  BITOP_B(code, RS8, name, op00,   op01, op10, op11, op20, op21, op30, op4)
+
+#define WTWOP(code, name, op1, op2) \
+  {code, AV_H8, 2, name, {{RS16, RD16, E}}, {{op1, op2, RS16, RD16, E}}}
+
+#define BRANCH(code, name, op) \
+  {code, AV_H8H, 6, name, {{PCREL16, E}}, {{0x5, 0x8, op, 0x0, PCREL16, DATA3 | B00, E}}}, \
+  {code, AV_H8,  4, name, {{PCREL8,  E}}, {{0x4, op,           PCREL8,  DATA  | B00, E}}}
+
+
+#define UNOP(code, name, op1, op2) \
+  {code, AV_H8, 2, name, {{OR8, E}}, {{op1, op2, 0, OR8, E}}}
+
+#define EXPAND_UNOP_STD_B(CODE, NAME, PREFIX, OP1, OP2, OP3) \
+  {CODE, AV_H8,   2, NAME, {{OR8,       E}}, {{                                                                  OP1, OP2, OP3, OR8,    E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND,     E}}, {{           7, 13, B30 | RSIND,             IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RSPOSTINC,   B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RSPOSTDEC,   B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREINC,  E}}, {{PREFIX, 5, 6, 12, B30 | RSPREINC,    B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREDEC,  E}}, {{PREFIX, 7, 6, 12, B30 | RSPREDEC,    B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP2SRC,  E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6,  8, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 14, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4,    6, 10, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB16,  E}}, {{PREFIX, 5, 6, 14, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW16,  E}}, {{PREFIX, 6, 6, 14, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL16,  E}}, {{PREFIX, 7, 6, 14, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB32,  E}}, {{7, 8, B30 | DISPREG, 5,    6, 10, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW32,  E}}, {{7, 8, B30 | DISPREG, 6,    6, 10, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL32,  E}}, {{7, 8, B30 | DISPREG, 7,    6, 10, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS8SRC,   E}}, {{                           7, 15,                   ABS8LIST,     OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC,  E}}, {{                           6, 10, 1, B31 | IGNORE,  ABS16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC,  E}}, {{                           6, 10, 3, B31 | IGNORE,  ABS32LIST,    OP1, OP2, OP3, IGNORE, E}}}
+
+#define EXPAND_UNOP_STD_W(CODE, NAME, PREFIX, OP1, OP2, OP3) \
+  {CODE, AV_H8H,  2, NAME, {{OR16,      E}}, {{                                                                  OP1, OP2, OP3, OR16,   E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND,     E}}, {{           7, 13, B31 | RSIND,             IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC,   B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC,   B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREINC,  E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC,    B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREDEC,  E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC,    B31 | IGNORE,                OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP2SRC,  E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6,  9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB16,  E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW16,  E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL16,  E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB32,  E}}, {{7, 8, B30 | DISPREG, 5,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW32,  E}}, {{7, 8, B30 | DISPREG, 6,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL32,  E}}, {{7, 8, B30 | DISPREG, 7,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC,  E}}, {{                           6, 11, 1, B31 | IGNORE,  ABS16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC,  E}}, {{                           6, 11, 3, B31 | IGNORE,  ABS32LIST,    OP1, OP2, OP3, IGNORE, E}}}
+
+#define EXPAND_UNOP_STD_L(CODE, NAME, PREFIX, OP1, OP2, OP3) \
+  {CODE, AV_H8H,  2, NAME, {{OR32,      E}}, {{                                                                  OP1, OP2, OP3, B30 | OR32,   E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSIND,     E}}, {{PREFIX, 4, 6,  9, B30 | RSIND,       B31 | IGNORE,                OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC,   B31 | IGNORE,                OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC,   B31 | IGNORE,                OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREINC,  E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC,    B31 | IGNORE,                OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{RSPREDEC,  E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC,    B31 | IGNORE,                OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP2SRC,  E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6,  9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B31 | DISPREG, 4,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB16,  E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW16,  E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL16,  E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG,     B31 | IGNORE,  DISP16LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXB32,  E}}, {{7, 8, B31 | DISPREG, 5,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXW32,  E}}, {{7, 8, B31 | DISPREG, 6,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{INDEXL32,  E}}, {{7, 8, B31 | DISPREG, 7,    6, 11, 2, B31 | IGNORE,  DISP32LIST,   OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS16SRC,  E}}, {{PREFIX, 4,                 6, 11, 0, B31 | IGNORE,  ABS16LIST,    OP1, OP2, OP3, B30 | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{ABS32SRC,  E}}, {{PREFIX, 4,                 6, 11, 2, B31 | IGNORE,  ABS32LIST,    OP1, OP2, OP3, B30 | IGNORE, E}}}
+
+#define EXPAND_UNOP_EXTENDED_B(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \
+  {CODE, AV_H8,   2, NAME, {{CONST, RD8,       E}}, {{                                                                     OP1, OP2, OP3, RD8,    E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND,     E}}, {{           7, 13, B30 | RDIND,             IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RDPOSTINC,   B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RDPOSTDEC,   B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC,  E}}, {{PREFIX, 5, 6, 12, B30 | RDPREINC,    B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC,  E}}, {{PREFIX, 7, 6, 12, B30 | RDPREDEC,    B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST,  E}}, {{PREFIX, B30 | B21 | DISP2DST, 6,  8, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 14, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 14, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 14, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 14, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, ABS8DST,   E}}, {{                           7, 15,                  DSTABS8LIST,      OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST,  E}}, {{                           6, 10, 1, B31 | IGNORE, DSTABS16LIST,     OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST,  E}}, {{                           6, 10, 3, B31 | IGNORE, DSTABS32LIST,     OP1, OP2, OP3, IGNORE, E}}}
+
+#define EXPAND_UNOP_EXTENDED_W(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \
+  {CODE, AV_H8,   2, NAME, {{CONST, RD16,      E}}, {{                                                                     OP1, OP2, OP3, RD16,   E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND,     E}}, {{           7, 13, B31 | RDIND,             IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC,   B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC,   B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC,  E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC,    B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC,  E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC,    B31 | IGNORE,                   OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST,  E}}, {{PREFIX, B30 | B21 | DISP2DST, 6,  9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST,  E}}, {{                           6, 11, 1, B31 | IGNORE, DSTABS16LIST,     OP1, OP2, OP3, IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST,  E}}, {{                           6, 11, 3, B31 | IGNORE, DSTABS32LIST,     OP1, OP2, OP3, IGNORE, E}}}
+
+#define EXPAND_UNOP_EXTENDED_L(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3, BIT) \
+  {CODE, AV_H8,   2, NAME, {{CONST, RD32,      E}}, {{                                                                     OP1, OP2, OP3, BIT | RD32,   E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND,     E}}, {{PREFIX, 4, 6,  9, B30 | RDIND,       B31 | IGNORE,                   OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC,   B31 | IGNORE,                   OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC,   B31 | IGNORE,                   OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC,  E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC,    B31 | IGNORE,                   OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC,  E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC,    B31 | IGNORE,                   OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST,  E}}, {{PREFIX, B30 | B21 | DISP2DST, 6,  9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B31 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG,  B31 | IGNORE, DSTDISP16LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B31 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B31 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B31 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST,    OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST,  E}}, {{PREFIX, 4,                 6, 11, 0, B31 | IGNORE, DSTABS16LIST,     OP1, OP2, OP3, BIT | IGNORE, E}}}, \
+  {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST,  E}}, {{PREFIX, 4,                 6, 11, 2, B31 | IGNORE, DSTABS32LIST,     OP1, OP2, OP3, BIT | IGNORE, E}}}
+
+#define PREFIXLDC 0x0, 0x1, 0x4, B30 | CCR_EXR | DST
+#define PREFIXSTC 0x0, 0x1, 0x4, B30 | CCR_EXR | SRC
+
+#define O(op, size)  (op * 4 + size)
+#define OP_SIZE(HOW) (HOW % 4)
+#define OP_KIND(HOW) (HOW / 4)
+
+enum h8_asm_codes
+{
+  O_RECOMPILE =	 0,
+  O_ADD,
+  O_ADDX,
+  O_AND,
+  O_BAND,
+  O_BRA,
+  O_BRAB,
+  O_BRAW,
+  O_BRAL,
+  O_BRAS,
+  O_BRABC,
+  O_BRABS,
+  O_BSRBC,
+  O_BSRBS,
+  O_BRN,
+  O_BHI,
+  O_BLS,
+  O_BCC,
+  O_BCS,
+  O_BNE,
+  O_BVC,
+  O_BVS,
+  O_BPL,
+  O_BMI,
+  O_BGE,
+  O_BLT,
+  O_BGT,
+  O_BLE,
+  O_ANDC,
+  O_BEQ,
+  O_BCLR,
+  O_BCLREQ,
+  O_BCLRNE,
+  O_BSETEQ,
+  O_BSETNE,
+  O_BFLD,
+  O_BFST,
+  O_BIAND,
+  O_BILD,
+  O_BIOR,
+  O_BIXOR,
+  O_BIST,
+  O_BISTZ,
+  O_BLD,
+  O_BNOT,
+  O_BOR,
+  O_BSET,
+  O_BSR,
+  O_BXOR,
+  O_CMP,
+  O_DAA,
+  O_DAS,
+  O_DEC,
+  O_DIVU,
+  O_DIVS,
+  O_DIVXU,
+  O_DIVXS,
+  O_INC,
+  O_LDC,
+  O_MOV,
+  O_MOVAB,
+  O_MOVAW,
+  O_MOVAL,
+  O_MOVMD,
+  O_MOVSD,
+  O_OR,
+  O_ROTL,
+  O_ROTR,
+  O_ROTXL,
+  O_ROTXR,
+  O_BPT,
+  O_SHAL,
+  O_SHAR,
+  O_SHLL,
+  O_SHLR,
+  O_SUB,
+  O_SUBS,
+  O_TRAPA,
+  O_XOR,
+  O_XORC,
+  O_BST,
+  O_BSTZ,
+  O_BTST,
+  O_EEPMOV,
+  O_EXTS,
+  O_EXTU,
+  O_JMP,
+  O_JSR,
+  O_MULU,
+  O_MULUU,
+  O_MULS,
+  O_MULSU,
+  O_MULXU,
+  O_MULXS,
+  O_NOP,
+  O_NOT,
+  O_ORC,
+  O_RTE,
+  O_RTEL,
+  O_STC,
+  O_SUBX,
+  O_NEG,
+  O_RTS,
+  O_RTSL,
+  O_SLEEP,
+  O_ILL,
+  O_ADDS,
+  O_SYSCALL,
+  O_TAS,
+  O_CLRMAC,
+  O_LDMAC,
+  O_MAC,
+  O_LDM,
+  O_STM,
+  O_STMAC,
+  O_LAST,
+  /* Change made for System Call processing.  */
+  O_SYS_CREAT,
+  O_SYS_OPEN,
+  O_SYS_READ,
+  O_SYS_WRITE,
+  O_SYS_LSEEK,
+  O_SYS_CLOSE,
+  O_SYS_STAT,
+  O_SYS_FSTAT,
+/* Space reserved for future file I/O system calls.  */
+ O_SYS_CMDLINE
+  /* End of System Call specific Changes.  */
+};
+
+enum h8_size
+{
+  SB =	 0,
+  SW =	 1,
+  SL =	 2,
+  SN =	 3
+};
+
+
+/* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences.
+   Methinks the zeroes aren't necessary.  Once confirmed, nuke 'em.  */
+
+struct h8_opcode h8_opcodes[] = 
+{
+  {O (O_ADD, SB), AV_H8,   2, "add.b", {{IMM8,      RD8,      E}}, {{0x8, RD8, IMM8LIST, E}}}, 
+  EXPAND_TWOOP_B (O (O_ADD, SB), "add.b", 0x8, 0x0, 0x8, 0x1, 0), 
+
+  {O (O_ADD, SW), AV_H8,   6, "add.w", {{RS16,      RD16,     E}}, {{0x0, 0x9, RS16,         RD16,   E}}}, 
+  {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RD16,     E}}, {{0x0, 0xa, B30 | IMM3NZ, RD16,   E}}}, 
+  {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RDIND,    E}}, {{0x7, 0xd,      B31 | RDIND,  IGNORE,       0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, 
+  {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, 
+  {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, 
+  EXPAND_TWOOP_W (O (O_ADD, SW), "add.w", 0x0, 0x9, 0x1), 
+
+  {O (O_ADD, SL), AV_H8H,  6, "add.l", {{RS32,      RD32,     E}}, {{0x0, 0xa, B31 | RS32,   B30 | RD32, E}}}, 
+  {O (O_ADD, SL), AV_H8SX, 0, "add.l", {{IMM3NZ_NS, RD32,     E}}, {{0x0, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, 
+  EXPAND_TWOOP_L (O (O_ADD, SL), "add.l", 0x1), 
+
+  {O (O_ADDS, SL), AV_H8,  2, "adds",  {{KBIT,  RDP,  E}}, {{0x0, 0xB,KBIT, RDP, E}}},
+
+  {O (O_ADDX, SB), AV_H8,   2, "addx",   {{IMM8,      RD8,       E}}, {{0x9, RD8, IMM8LIST, E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8,      RDIND,     E}}, {{0x7, 0xd, B30 | RDIND, IGNORE,                        0x9, IGNORE, IMM8LIST, E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8,      RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x9, IGNORE, IMM8LIST, E}}},
+  {O (O_ADDX, SB), AV_H8,   2, "addx",   {{RS8,       RD8,       E}}, {{0x0, 0xe, RS8,  RD8,    E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8,       RDIND,     E}}, {{0x7, 0xd, B30 | RDIND, IGNORE,                              0x0, 0xe, RS8, IGNORE, E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8,       RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31       | IGNORE, 0x0, 0xe, RS8, IGNORE, E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND,     RD8,       E}}, {{0x7, 0xc, B30 | RSIND, IGNORE,                              0x0, 0xe, IGNORE, RD8, E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RD8,       E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x0, 0xe, IGNORE, RD8, E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND,     RDIND,     E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND,     0xd, 0x0, RDIND,     0x1, IGNORE, E}}},
+  {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}},
+
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16,     RD16,      E}}, {{PREFIX_0151,                         0x7, 0x9, 0x1, RD16,   IMM16LIST, E}}}, 
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16,     RDIND,     E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, 
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16,     RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, 
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16,      RD16,      E}}, {{PREFIX_0151, 0x0, 0x9, RS16,  RD16,    E}}},
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16,      RDIND,     E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}},
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16,      RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}},
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND,     RD16,      E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}},
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RD16,      E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}},
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND,     RDIND,     E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND,     0xd, 0x0, RDIND,     0x1, IGNORE, E}}},
+  {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}},
+
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32,     RD32,      E}}, {{PREFIX_0101, 0x7, 0xa, 0x1,  RD32, IMM32LIST, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32,     RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND,     B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32,     RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32,      RD32,      E}}, {{PREFIX_0101, 0x0, 0xa, B31 | RS32,  B30 | RD32,    E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32,      RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND,     B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32,      RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND,     RD32,      E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND,     B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RD32,      E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND,     RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND,     0xd, 0x0, RDIND,     0x1, IGNORE, E}}},
+  {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}},
+
+  {O (O_AND, SB), AV_H8,   2, "and.b", {{IMM8, RD8,  E}}, {{0xe, RD8, IMM8LIST, E}}}, 
+  EXPAND_TWOOP_B (O (O_AND, SB), "and.b", 0xe, 0x1, 0x6, 0x6, 0), 
+
+  {O (O_AND, SW), AV_H8,   2, "and.w", {{RS16, RD16, E}}, {{0x6, 0x6, RS16, RD16,   E}}}, 
+  EXPAND_TWOOP_W (O (O_AND, SW), "and.w", 0x6, 0x6, 0x6), 
+
+  {O (O_AND, SL), AV_H8H,  2, "and.l", {{RS32,  RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x6, B30 | RS32, B30 | RD32, E}}},
+  EXPAND_TWOOP_L (O (O_AND, SL), "and.l", 0x6), 
+
+  {O (O_ANDC, SB), AV_H8,  2, "andc", {{IMM8,  CCR | DST, E}}, {{0x0, 0x6, IMM8LIST, E}}},
+  {O (O_ANDC, SB), AV_H8S, 2, "andc", {{IMM8,  EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x6, IMM8LIST, E}}},
+
+  BRANCH (O (O_BRA, SB), "bra", 0x0),
+
+  {O (O_BRAB, SB), AV_H8SX, 0, "bra", {{LOWREG | L_8,  E}}, {{0x5, 0x9, LOWREG | L_8  | B30, 0x5, E}}},
+  {O (O_BRAW, SW), AV_H8SX, 0, "bra", {{LOWREG | L_16, E}}, {{0x5, 0x9, LOWREG | L_16 | B30, 0x6, E}}},
+  {O (O_BRAL, SL), AV_H8SX, 0, "bra", {{RS32, E}}, {{0x5, 0x9, RS32 | B30, 0x7, E}}},
+
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND,    OP3PCREL8}},  {{0x7, 0xC, B30 | RDIND, 0x0,            0x4, B30 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST,  OP3PCREL8}},  {{0x7, 0xE, DSTABS8LIST,                 0x4, B30 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL8}},  {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST,      0x4, B30 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL8}},  {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST,      0x4, B30 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND,    OP3PCREL8}},  {{0x7, 0xC, B30 | RDIND, 0x0,            0x4, B31 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST,  OP3PCREL8}},  {{0x7, 0xE, DSTABS8LIST,                 0x4, B31 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL8}},  {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST,      0x4, B31 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL8}},  {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST,      0x4, B31 | IMM3,      OP3PCREL8,  DATA,  E}}},
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND,    OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0,       0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST,  OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST,            0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND,    OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0,       0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST,  OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST,            0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  
+  {O (O_BRAS,  SB), AV_H8SX, 0, "bra/s",  {{PCREL8, E}}, {{0x4, 0x0, PCREL8, DATA | B01, E}}},
+
+  {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, RDIND,    OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0,       0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS8DST,  OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST,            0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, RDIND,    OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0,       0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS8DST,  OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST,            0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+  {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}},
+
+  BRANCH (O (O_BRA, SB), "bt",  0x0),
+  BRANCH (O (O_BRN, SB), "brn", 0x1),
+  BRANCH (O (O_BRN, SB), "bf",  0x1),
+  BRANCH (O (O_BHI, SB), "bhi", 0x2),
+  BRANCH (O (O_BLS, SB), "bls", 0x3),
+  BRANCH (O (O_BCC, SB), "bcc", 0x4),
+  BRANCH (O (O_BCC, SB), "bhs", 0x4),
+  BRANCH (O (O_BCS, SB), "bcs", 0x5),
+  BRANCH (O (O_BCS, SB), "blo", 0x5),
+  BRANCH (O (O_BNE, SB), "bne", 0x6),
+  BRANCH (O (O_BEQ, SB), "beq", 0x7),
+  BRANCH (O (O_BVC, SB), "bvc", 0x8),
+  BRANCH (O (O_BVS, SB), "bvs", 0x9),
+  BRANCH (O (O_BPL, SB), "bpl", 0xA),
+  BRANCH (O (O_BMI, SB), "bmi", 0xB),
+  BRANCH (O (O_BGE, SB), "bge", 0xC),
+  BRANCH (O (O_BLT, SB), "blt", 0xD),
+  BRANCH (O (O_BGT, SB), "bgt", 0xE),
+  BRANCH (O (O_BLE, SB), "ble", 0xF),
+
+  EBITOP (O (O_BCLR,  SB), IMM3 | B30, "bclr",  0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
+  BITOP  (O (O_BAND,  SB), IMM3 | B30, "band",  0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  BITOP  (O (O_BIAND, SB), IMM3 | B31, "biand", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  BITOP  (O (O_BILD,  SB), IMM3 | B31, "bild",  0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  BITOP  (O (O_BIOR,  SB), IMM3 | B31, "bior",  0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  BITOP  (O (O_BIST,  SB), IMM3 | B31, "bist",  0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
+  BITOP  (O (O_BIXOR, SB), IMM3 | B31, "bixor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  BITOP  (O (O_BLD,   SB), IMM3 | B30, "bld",   0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  EBITOP (O (O_BNOT,  SB), IMM3 | B30, "bnot",  0x6, 0x1, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
+  BITOP  (O (O_BOR,   SB), IMM3 | B30, "bor",   0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  EBITOP (O (O_BSET,  SB), IMM3 | B30, "bset",  0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
+  BITOP  (O (O_BST,   SB), IMM3 | B30, "bst",   0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0),
+  EBITOP (O (O_BTST,  SB), IMM3 | B30, "btst",  0x6, 0x3, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+  BITOP  (O (O_BXOR,  SB), IMM3 | B30, "bxor",  0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0),
+
+  EBITOP_B (O (O_BCLREQ,  SB), IMM3 | B30, "bclr/eq",  0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
+  EBITOP_B (O (O_BCLRNE,  SB), IMM3 | B30, "bclr/ne",  0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6),
+  EBITOP_B (O (O_BSETEQ,  SB), IMM3 | B30, "bset/eq",  0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
+  EBITOP_B (O (O_BSETNE,  SB), IMM3 | B30, "bset/ne",  0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6),
+  BITOP_B  (O (O_BISTZ,   SB), IMM3 | B31, "bistz",    0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
+  BITOP_B  (O (O_BSTZ,    SB), IMM3 | B30, "bstz",     0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7),
+
+  {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, RDIND,    R3_8}},  {{0x7, 0xC,           B30 | RDIND, 0x0, 0xF, R3_8, IMM8LIST, E}}},
+  {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS8DST,  R3_8}},  {{0x7, 0xE,           DSTABS8LIST,      0xF, R3_8, IMM8LIST, E}}},
+  {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS16DST, R3_8}},  {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST,     0xF, R3_8, IMM8LIST, E}}},
+  {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS32DST, R3_8}},  {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST,     0xF, R3_8, IMM8LIST, E}}},
+
+  /* Because the assembler treats SRC, DST and OP3 as ordinals, 
+     I must designate the second argument, an immediate value, as DST.
+     May God have mercy on my soul.  */
+  {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, R3_IND}},   {{0x7, 0xD,           B30 | R3_IND, 0x0, 0xF, RS8, DST | IMM8LIST, E}}},
+  {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS8OP3}},  {{0x7, 0xF,           OP3ABS8LIST,       0xF, RS8, DST | IMM8LIST, E}}},
+  {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS16OP3}}, {{0x6, 0xA, 0x1, 0x8, OP3ABS16LIST,      0xF, RS8, DST | IMM8LIST, E}}},
+  {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS32OP3}}, {{0x6, 0xA, 0x3, 0x8, OP3ABS32LIST,      0xF, RS8, DST | IMM8LIST, E}}},
+
+  {O (O_BSR, SB), AV_H8,   6, "bsr", {{PCREL8,  E}}, {{0x5, 0x5,           PCREL8,  DATA,  E}}},
+  {O (O_BSR, SB), AV_H8,   6, "bsr", {{PCREL16, E}}, {{0x5, 0xC, 0x0, 0x0, PCREL16, DATA3, E}}},
+  {O (O_BSR, SB), AV_H8SX, 0, "bsr", {{LOWREG | L_8,    E}}, {{0x5, 0xd, B30 | LOWREG | L_8,  0x5, E}}},
+  {O (O_BSR, SW), AV_H8SX, 0, "bsr", {{LOWREG | L_16,   E}}, {{0x5, 0xd, B30 | LOWREG | L_16, 0x6, E}}},
+  {O (O_BSR, SL), AV_H8SX, 0, "bsr", {{OR32,   E}}, {{0x5, 0xd, B30 | OR32, 0x7, E}}},
+
+  {O (O_CMP, SB), AV_H8,   2, "cmp.b", {{IMM8, RD8, E}}, {{0xa, RD8, IMM8LIST, E}}}, 
+  EXPAND_TWOOP_B (O (O_CMP, SB), "cmp.b", 0xa, 0x1, 0xc, 0x2, B00), 
+
+  {O (O_CMP, SW), AV_H8,   2, "cmp.w", {{RS16,      RD16,     E}}, {{0x1, 0xd, RS16,         RD16,   E}}}, 
+  {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RD16,     E}}, {{0x1, 0xf, B30 | IMM3NZ, RD16,   E}}}, 
+  {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RDIND,    E}}, {{0x7, 0xd,      B31 | RDIND,  IGNORE,       0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, 
+  {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, 
+  {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, 
+  EXPAND_TWOOP_W (O (O_CMP, SW), "cmp.w", 0x1, 0xd, 0x2), 
+
+  {O (O_CMP, SL), AV_H8H,  6, "cmp.l", {{RS32,      RD32,     E}}, {{0x1, 0xf, B31 | RS32,   B30 | RD32, E}}}, 
+  {O (O_CMP, SL), AV_H8SX, 0, "cmp.l", {{IMM3NZ_NS, RD32,     E}}, {{0x1, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, 
+  EXPAND_TWOOP_L (O (O_CMP, SL), "cmp.l", 0x2), 
+
+  UNOP (O (O_DAA, SB), "daa",   0x0, 0xF),
+  UNOP (O (O_DAS, SB), "das",   0x1, 0xF),
+  UNOP (O (O_DEC, SB), "dec.b", 0x1, 0xA),
+
+  {O (O_DEC, SW), AV_H8H, 2, "dec.w", {{DBIT, RD16, E}}, {{0x1, 0xB, 0x5 | DBIT, RD16,       E}}},
+  {O (O_DEC, SL), AV_H8H, 2, "dec.l", {{DBIT, RD32, E}}, {{0x1, 0xB, 0x7 | DBIT, RD32 | B30, E}}},
+
+  {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x1, IMM4, RD16, E}}},
+  {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x1, RS16, RD16, E}}},
+  {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x3, IMM4,       B30 | RD32, E}}},
+  {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}},
+
+  {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x1, IMM4, RD16, E}}},
+  {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x1, RS16, RD16, E}}},
+  {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x3, IMM4,       B30 | RD32, E}}},
+  {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}},
+
+  {O (O_DIVXS, SB), AV_H8SX, 0,  "divxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x1, IMM4, RD16, E}}},
+  {O (O_DIVXS, SB), AV_H8H,  13, "divxs.b", {{RS8,  RD16, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x1, RS8,  RD16, E}}},
+  {O (O_DIVXS, SW), AV_H8SX, 0,  "divxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x3, IMM4, B30 | RD32, E}}},
+  {O (O_DIVXS, SW), AV_H8H,  21, "divxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x3, RS16, B30 | RD32, E}}},
+
+  {O (O_DIVXU, SB), AV_H8SX, 0,  "divxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x1, IMM4, RD16, E}}},
+  {O (O_DIVXU, SB), AV_H8,   13, "divxu.b", {{RS8,  RD16, E}}, {{0x5, 0x1,                     RS8,  RD16, E}}},
+  {O (O_DIVXU, SW), AV_H8SX, 0,  "divxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x3, IMM4, B30 | RD32, E}}},
+  {O (O_DIVXU, SW), AV_H8H,  21, "divxu.w", {{RS16, RD32, E}}, {{0x5, 0x3,                     RS16, B30 | RD32, E}}},
+
+  {O (O_EEPMOV, SB), AV_H8,  4, "eepmov.b", {{E}}, {{0x7, 0xB, 0x5, 0xC, 0x5, 0x9, 0x8, 0xF, E}}},
+  {O (O_EEPMOV, SW), AV_H8H, 4, "eepmov.w", {{E}}, {{0x7, 0xB, 0xD, 0x4, 0x5, 0x9, 0x8, 0xF, E}}},
+
+  EXPAND_UNOP_STD_W      (O (O_EXTS, SW), "exts.w",          PREFIX_015, 0x1, 0x7, 0xd),
+  EXPAND_UNOP_STD_L      (O (O_EXTS, SL), "exts.l",          PREFIX_010, 0x1, 0x7, 0xf),
+  EXPAND_UNOP_EXTENDED_L (O (O_EXTS, SL), "exts.l", CONST_2, PREFIX_010, 0x1, 0x7, 0xe, 0),
+  EXPAND_UNOP_STD_W      (O (O_EXTU, SW), "extu.w",          PREFIX_015, 0x1, 0x7, 0x5),
+  EXPAND_UNOP_STD_L      (O (O_EXTU, SL), "extu.l",          PREFIX_010, 0x1, 0x7, 0x7),
+  EXPAND_UNOP_EXTENDED_L (O (O_EXTU, SL), "extu.l", CONST_2, PREFIX_010, 0x1, 0x7, 0x6, 0),
+
+  UNOP (O (O_INC, SB), "inc", 0x0, 0xA),
+
+  {O (O_INC, SW), AV_H8H,  2, "inc.w", {{DBIT, RD16, E}},    {{0x0, 0xB, 0x5 | DBIT, RD16,       E}}},
+  {O (O_INC, SL), AV_H8H,  2, "inc.l", {{DBIT, RD32, E}},    {{0x0, 0xB, 0x7 | DBIT, RD32 | B30, E}}},
+
+  {O (O_JMP, SN), AV_H8,   4, "jmp", {{RSIND, E}},         {{0x5, 0x9, B30 | RSIND, 0x0, E}}},
+  {O (O_JMP, SN), AV_H8,   6, "jmp", {{ABSJMP | L_24, E}}, {{0x5, 0xA, SRC | ABSJMP | L_24, DATA5, E}}},
+
+  {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{ABSJMP | L_32, E}}, {{0x5, 0x9, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}},
+
+  {O (O_JMP, SN), AV_H8,   8, "jmp", {{MEMIND, E}}, {{0x5, 0xB, SRC | MEMIND, DATA, E}}},
+  {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{VECIND, E}}, {{0x5, 0x9, B31 | SRC | VECIND, DATA, E}}},
+
+  {O (O_JSR, SN), AV_H8,   6, "jsr", {{RSIND, E}},         {{0x5, 0xD, B30 | RSIND, 0x0, E}}},
+  {O (O_JSR, SN), AV_H8,   8, "jsr", {{ABSJMP | L_24, E}}, {{0x5, 0xE, SRC | ABSJMP | L_24, DATA5, E}}},
+
+  {O (O_JSR, SN), AV_H8SX, 0, "jsr", {{ABSJMP | L_32, E}}, {{0x5, 0xD, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}},
+
+  {O (O_JSR, SN), AV_H8,   8, "jsr", {{MEMIND, E}}, {{0x5, 0xF, SRC | MEMIND, DATA, E}}},
+  {O (O_JSR, SN), AV_H8SX, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}},
+
+  {O (O_LDC, SB), AV_H8,   2, "ldc", {{IMM8,       CCR     | DST, E}}, {{                           0x0, 0x7, IMM8LIST, E}}},
+  {O (O_LDC, SB), AV_H8S,  2, "ldc", {{IMM8,       EXR     | DST, E}}, {{0x0, 0x1, 0x4,  EXR | DST, 0x0, 0x7, IMM8LIST, E}}},
+  {O (O_LDC, SB), AV_H8,   2, "ldc", {{RS8,        CCR     | DST, E}}, {{0x0, 0x3, B30 | CCR | DST, RS8, E}}},
+  {O (O_LDC, SB), AV_H8S,  2, "ldc", {{RS8,        EXR     | DST, E}}, {{0x0, 0x3, B30 | EXR | DST, RS8, E}}},
+  {O (O_LDC, SW), AV_H8H,  2, "ldc", {{RSIND,      CCR     | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND,     IGNORE, E}}},
+  {O (O_LDC, SW), AV_H8S,  2, "ldc", {{RSIND,      EXR     | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND,     IGNORE, E}}},
+  {O (O_LDC, SW), AV_H8H,  2, "ldc", {{RSPOSTINC,  CCR     | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}},
+  {O (O_LDC, SW), AV_H8S,  2, "ldc", {{RSPOSTINC,  EXR     | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}},
+  {O (O_LDC, SW), AV_H8H,  2, "ldc", {{DISP16SRC,  CCR     | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG,                     IGNORE, SRC | DISP16LIST, E}}},
+  {O (O_LDC, SW), AV_H8S,  2, "ldc", {{DISP16SRC,  EXR     | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG,                     IGNORE, SRC | DISP16LIST, E}}},
+  {O (O_LDC, SW), AV_H8H,  2, "ldc", {{DISP32SRC,  CCR     | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}},
+  {O (O_LDC, SW), AV_H8S,  2, "ldc", {{DISP32SRC,  EXR     | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}},
+  {O (O_LDC, SW), AV_H8H,  2, "ldc", {{ABS16SRC,   CCR     | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}},
+  {O (O_LDC, SW), AV_H8S,  2, "ldc", {{ABS16SRC,   EXR     | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}},
+  {O (O_LDC, SW), AV_H8H,  2, "ldc", {{ABS32SRC,   CCR     | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}},
+  {O (O_LDC, SW), AV_H8S,  2, "ldc", {{ABS32SRC,   EXR     | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}},
+
+  {O (O_LDC, SL), AV_H8SX, 0, "ldc", {{RS32, B30 | VBR_SBR | DST, E}}, {{0x0, 0x3, B30 | VBR_SBR | DST, RS32, E}}},
+
+
+  {O (O_MOV, SB), AV_H8,   2, "mov.b", {{IMM8, RD8,      E}}, {{0xF, RD8,            IMM8LIST,     E}}},
+  {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xa, 0xd, IMM4, DSTABS16LIST, E}}},
+  {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xa, 0xf, IMM4, DSTABS32LIST, E}}},
+  MOVFROM_IMM8 (O (O_MOV, SB), PREFIX_017D, "mov.b", IMM8),
+
+  {O (O_MOV, SB), AV_H8,   2,    "mov.b", {{RS8, RD8,     E}}, {{0x0, 0xC, RS8, RD8,    E}}},
+  MOVFROM_REG_BW (O (O_MOV, SB), "mov.b", RS8, PREFIX_017, 8, 10, 12, 14, MEMRELAX),
+  {O (O_MOV, SB), AV_H8,   4,    "mov.b", {{RS8, ABS8DST, E}}, {{0x3, RS8, DSTABS8LIST, E}}},
+  MOVTO_REG_BW (O (O_MOV, SB),   "mov.b", RD8, PREFIX_017, 8, 10, 12, 14, MEMRELAX),
+  {O (O_MOV, SB), AV_H8,   4,    "mov.b", {{ABS8SRC, RD8, E}}, {{0x2, RD8, ABS8LIST,    E}}},
+
+  MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSIND,     FROM_IND), 
+  MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTINC, FROM_POSTINC), 
+  MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTDEC, FROM_POSTDEC), 
+  MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREINC,  FROM_PREINC), 
+  MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREDEC,  FROM_PREDEC), 
+  MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP2SRC,  FROM_DISP2), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP16SRC, FROM_DISP16,  DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP32SRC, FROM_DISP32,  DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB16,  FROM_DISP16B, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW16,  FROM_DISP16W, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL16,  FROM_DISP16L, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB32,  FROM_DISP32B, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW32,  FROM_DISP32W, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL32,  FROM_DISP32L, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS16SRC,  FROM_ABS16,   ABS16LIST), 
+  MOVFROM_AD  (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS32SRC,  FROM_ABS32,   ABS32LIST), 
+
+  {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xf, B30 | IMM3NZ, RD16,   E}}},
+  {O (O_MOV, SW), AV_H8,   4, "mov.w", {{IMM16,     RD16, E}}, {{0x7, 0x9, 0x0, RD16, IMM16LIST, E}}},
+  {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS,  ABS16DST, E}}, {{0x6, 0xb, 0xd, IMM4, DSTABS16LIST, E}}},
+  {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS,  ABS32DST, E}}, {{0x6, 0xb, 0xf, IMM4, DSTABS32LIST, E}}},
+
+  MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D,   "mov.w", IMM8U_NS),
+  MOVFROM_IMM  (O (O_MOV, SW), PREFIX_7974,   "mov.w", IMM16, IMM16LIST),
+
+  {O (O_MOV, SW), AV_H8,   2, "mov.w", {{RS16, RD16,      E}}, {{0x0, 0xD, RS16, RD16, E}}},
+  MOVFROM_REG_BW (O (O_MOV, SW), "mov.w", RS16, PREFIX_015, 9, 11, 13, 15, 0),
+  MOVTO_REG_BW   (O (O_MOV, SW), "mov.w", RD16, PREFIX_015, 9, 11, 13, 15, 0),
+
+  MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSIND,     FROM_IND), 
+  MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTINC, FROM_POSTINC), 
+  MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTDEC, FROM_POSTDEC), 
+  MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREINC,  FROM_PREINC), 
+  MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREDEC,  FROM_PREDEC), 
+  MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP2SRC,  FROM_DISP2), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP16SRC, FROM_DISP16,  DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP32SRC, FROM_DISP32,  DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB16,  FROM_DISP16B, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW16,  FROM_DISP16W, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL16,  FROM_DISP16L, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB32,  FROM_DISP32B, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW32,  FROM_DISP32W, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL32,  FROM_DISP32L, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS16SRC,  FROM_ABS16,   ABS16LIST), 
+  MOVFROM_AD  (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS32SRC,  FROM_ABS32,   ABS32LIST), 
+
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xf, B31 | IMM3NZ, B31 | RD32, E}}},
+
+  MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8U_NS),
+  MOVFROM_IMM  (O (O_MOV, SL), PREFIX_7A7C, "mov.l", IMM16U_NS, IMM16ULIST),
+
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, 0x0, B31 | RD32, IMM16ULIST, E}}},
+  {O (O_MOV, SL), AV_H8H,  4, "mov.l", {{IMM32,     RD32, E}}, {{0x7, 0xa, 0x0, B30 | RD32, IMM32LIST,  E}}},
+
+  MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A74, "mov.l", IMM32, IMM32LIST),
+
+  {O (O_MOV, SL), AV_H8H,  2, "mov.l", {{RS32, RD32,      E}}, {{0x0, 0xf, B31 | RS32, B30 | RD32, E}}},
+
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, RDIND,     E}}, {{PREFIX_0100,                       0x6, 0x9, B31 | RDIND, B30 | RS32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTINC, E}}, {{PREFIX_0103,                       0x6, 0xd, B31 | RDPOSTINC,   RS32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0101,                       0x6, 0xd, B31 | RDPOSTDEC,   RS32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPREINC,  E}}, {{PREFIX_0102,                       0x6, 0xd, B31 | RDPREINC,    RS32, E}}}, 
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, RDPREDEC,  E}}, {{PREFIX_0100,                       0x6, 0xd, B31 | RDPREDEC,    RS32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, DISP2DST,  E}}, {{PREFIX_010,  B30 | B20 | DISP2DST, 0x6, 0x9, B31 | DSTDISPREG,  RS32, E}}}, 
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100,                       0x6, 0xf, B31 | DSTDISPREG,  RS32, DSTDISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0,   0x6, 0xb, 0xa,               RS32, DSTDISP32LIST, E}}},
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100,                       0x7, 0x8, B31 | DSTDISPREG, 0x0,   0x6, 0xb, 0xa,               RS32, MEMRELAX | DSTDISP32LIST, E}}},
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100,                       0x7, 0x8, DSTDISPREG, 0x0,   0x6, 0xb, 0xa,               RS32, MEMRELAX | DSTDISP32LIST, E}}},
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101,                       0x6, 0xf, B31 | DSTDISPREG,  RS32, DSTDISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102,                       0x6, 0xf, B31 | DSTDISPREG,  RS32, DSTDISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103,                       0x6, 0xf, B31 | DSTDISPREG,  RS32, DSTDISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x1,   0x6, 0xb, 0xa,               RS32, DSTDISP32LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x2,   0x6, 0xb, 0xa,               RS32, DSTDISP32LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x3,   0x6, 0xb, 0xa,               RS32, DSTDISP32LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, ABS16DST,  E}}, {{PREFIX_0100,                       0x6, 0xb, 0x8,            RS32, DSTABS16LIST,            E}}},
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RS32, ABS32DST,  E}}, {{PREFIX_0100,                       0x6, 0xb, 0xa,            RS32, MEMRELAX | DSTABS32LIST, E}}},
+
+  {O (O_MOV, SL), AV_H8H,  4, "mov.l", {{RSIND,     RD32, E}}, {{PREFIX_0100,                       0x6, 0x9, B30 | RSIND,     RD32, E}}}, 
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{RSPOSTINC, RD32, E}}, {{PREFIX_0100,                       0x6, 0xd, B30 | RSPOSTINC, RD32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0102,                       0x6, 0xd, B30 | RSPOSTDEC, RD32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREINC,  RD32, E}}, {{PREFIX_0101,                       0x6, 0xd, B30 | RSPREINC,  RD32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREDEC,  RD32, E}}, {{PREFIX_0103,                       0x6, 0xd, B30 | RSPREDEC,  RD32, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{DISP2SRC,  RD32, E}}, {{PREFIX_010,  B30 | B20 | DISP2SRC, 0x6, 0x9, B30 | DISPREG,   RD32, E}}}, 
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{DISP16SRC, RD32, E}}, {{PREFIX_0100,                       0x6, 0xf, B30 | DISPREG,   RD32, SRC | DISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x0,      0x6, 0xb, 0x2,             RD32, SRC | DISP32LIST, E}}},
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{DISP32SRC, RD32, E}}, {{PREFIX_0100,                       0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xb, 0x2,             RD32, MEMRELAX | SRC | DISP32LIST, E}}},
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB16,  RD32, E}}, {{PREFIX_0101,                       0x6, 0xf, B30 | DISPREG,   RD32, SRC | DISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW16,  RD32, E}}, {{PREFIX_0102,                       0x6, 0xf, B30 | DISPREG,   RD32, SRC | DISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL16,  RD32, E}}, {{PREFIX_0103,                       0x6, 0xf, B30 | DISPREG,   RD32, SRC | DISP16LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB32,  RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x1,      0x6, 0xb, 0x2,             RD32, SRC | DISP32LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW32,  RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x2,      0x6, 0xb, 0x2,             RD32, SRC | DISP32LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL32,  RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x3,      0x6, 0xb, 0x2,             RD32, SRC | DISP32LIST, E}}}, 
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{ABS16SRC,  RD32, E}}, {{PREFIX_0100,                       0x6, 0xb, 0x0,             RD32, SRC | ABS16LIST,  E}}}, 
+  {O (O_MOV, SL), AV_H8H,  6, "mov.l", {{ABS32SRC,  RD32, E}}, {{PREFIX_0100,                       0x6, 0xb, 0x2,             RD32, SRC | MEMRELAX | ABS32LIST, E}}}, 
+
+  MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSIND,     FROM_IND), 
+  MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTINC, FROM_POSTINC), 
+  MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTDEC, FROM_POSTDEC), 
+  MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREINC,  FROM_PREINC), 
+  MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREDEC,  FROM_PREDEC), 
+  MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP2SRC,  FROM_DISP2), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP16SRC, FROM_DISP16,  DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP32SRC, FROM_DISP32,  DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB16,  FROM_DISP16B, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW16,  FROM_DISP16W, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL16,  FROM_DISP16L, DISP16LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB32,  FROM_DISP32B, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW32,  FROM_DISP32W, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL32,  FROM_DISP32L, DISP32LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS16SRC,  FROM_ABS16,   ABS16LIST), 
+  MOVFROM_AD  (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS32SRC,  FROM_ABS32,   ABS32LIST), 
+
+#define DO_MOVA1(TYPE, OP0, OP1) \
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, MEMRELAX | DISP16LIST, E}}}, \
+\
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, MEMRELAX | DISP32LIST, E}}}
+
+#define DO_MOVA2(TYPE, OP0, OP1, OP2) \
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, MEMRELAX | DISP16LIST, E}}}, \
+\
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}, \
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, MEMRELAX | DISP32LIST, E}}}
+
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, MEMRELAX | DISP16LIST, E}}},
+
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, MEMRELAX | DISP32LIST, E}}},
+
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0x8, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0xA, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0xC, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, MEMRELAX | DISP16LIST, E}}},
+
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0x8, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
+  {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0xA, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
+  {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8,  R3_32}}, {{0x7, 0x8, RD8,  0x8, 0x7, 0xA, 0xC, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
+  {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, MEMRELAX | DISP32LIST, E}}},
+
+  DO_MOVA1 (RDIND,     0x0, B30 | RDIND),
+  DO_MOVA1 (RDPOSTINC, 0x8, B30 | RDPOSTINC),
+  DO_MOVA1 (RDPOSTDEC, 0xA, B30 | RDPOSTDEC),
+  DO_MOVA1 (RDPREINC,  0x9, B30 | RDPREINC),
+  DO_MOVA1 (RDPREDEC,  0xB, B30 | RDPREDEC),
+  DO_MOVA1 (DISP2DST,  B30 | B20 | DISP2DST,  B30 | DSTDISPREG),
+  DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
+  DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
+  DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
+  DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
+  DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, MEMRELAX | DSTDISP16LIST),
+  DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
+  DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
+  DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, MEMRELAX | DSTDISP32LIST),
+  DO_MOVA2 (ABS16DST,  0x4, 0x0,              MEMRELAX | DSTABS16LIST),
+  DO_MOVA2 (ABS32DST,  0x4, 0x8,              MEMRELAX | DSTABS32LIST),
+
+  {O (O_MOV, SB), AV_H8, 10, "movfpe", {{ABS16SRC, RD8, E}}, {{0x6, 0xA, 0x4, RD8, ABS16SRC, DATA3, E}}},
+  {O (O_MOV, SB), AV_H8, 10, "movtpe", {{RS8, ABS16DST, E}}, {{0x6, 0xA, 0xC, RS8, ABS16DST, DATA3, E}}},
+
+  {O (O_MOVMD, SB), AV_H8SX, 0, "movmd.b", {{E}},         {{0x7, 0xb, 0x9, 0x4, E}}},
+  {O (O_MOVMD, SW), AV_H8SX, 0, "movmd.w", {{E}},         {{0x7, 0xb, 0xa, 0x4, E}}},
+  {O (O_MOVMD, SL), AV_H8SX, 0, "movmd.l", {{E}},         {{0x7, 0xb, 0xb, 0x4, E}}},
+  {O (O_MOVSD, SB), AV_H8SX, 0, "movsd.b", {{PCREL16, E}}, {{0x7, 0xb, 0x8, 0x4, PCREL16, DATA3, E}}},
+
+  {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x0, IMM4, RD16, E}}},
+  {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x0, RS16, RD16, E}}},
+  {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x2, IMM4,       B30 | RD32, E}}},
+  {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
+
+  {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x0, IMM4, RD16, E}}},
+  {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x0, RS16, RD16, E}}},
+  {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x2, IMM4,       B30 | RD32, E}}},
+  {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
+
+  {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x7, 0x5, 0x2, IMM4,       B30 | RD32, E}}},
+  {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x3, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
+  {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xf, 0x5, 0x2, IMM4,       B30 | RD32, E}}},
+  {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xb, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}},
+
+  {O (O_MULXS, SB), AV_H8SX, 0,  "mulxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x0, IMM4, RD16,       E}}},
+  {O (O_MULXS, SB), AV_H8H,  20, "mulxs.b", {{RS8,  RD16, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x0, RS8,  RD16,       E}}},
+  {O (O_MULXS, SW), AV_H8SX, 0,  "mulxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x2, IMM4, B30 | RD32, E}}},
+  {O (O_MULXS, SW), AV_H8H,  20, "mulxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x2, RS16, B30 | RD32, E}}},
+
+  {O (O_MULXU, SB), AV_H8SX, 0,  "mulxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x0, IMM4, RD16, E}}},
+  {O (O_MULXU, SB), AV_H8,   14, "mulxu.b", {{RS8,  RD16, E}}, {{0x5, 0x0,                     RS8,  RD16, E}}},
+  {O (O_MULXU, SW), AV_H8SX, 0,  "mulxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x2, IMM4, B30 | RD32, E}}},
+  {O (O_MULXU, SW), AV_H8H,  14, "mulxu.w", {{RS16, RD32, E}}, {{0x5, 0x2,                     RS16, B30 | RD32, E}}},
+
+  EXPAND_UNOP_STD_B (O (O_NEG,  SB), "neg.b", PREFIX_017, 0x1, 0x7, 0x8),
+  EXPAND_UNOP_STD_W (O (O_NEG,  SW), "neg.w", PREFIX_015, 0x1, 0x7, 0x9),
+  EXPAND_UNOP_STD_L (O (O_NEG,  SL), "neg.l", PREFIX_010, 0x1, 0x7, 0xb),
+
+  {O (O_NOP, SN), AV_H8,  2, "nop",   {{E}},  {{0x0, 0x0, 0x0, 0x0, E}}},
+
+  EXPAND_UNOP_STD_B (O (O_NOT,  SB), "not.b", PREFIX_017, 0x1, 0x7, 0x0),
+  EXPAND_UNOP_STD_W (O (O_NOT,  SW), "not.w", PREFIX_015, 0x1, 0x7, 0x1),
+  EXPAND_UNOP_STD_L (O (O_NOT,  SL), "not.l", PREFIX_010, 0x1, 0x7, 0x3),
+
+  {O (O_OR,  SB), AV_H8,  2, "or.b",  {{IMM8, RD8,  E}}, {{0xc, RD8, IMM8LIST, E}}}, 
+  EXPAND_TWOOP_B (O (O_OR, SB), "or.b", 0xc, 0x1, 0x4, 0x4, 0), 
+
+  {O (O_OR,  SW), AV_H8,  2, "or.w",  {{RS16, RD16, E}}, {{0x6, 0x4, RS16, RD16, E}}}, 
+  EXPAND_TWOOP_W (O (O_OR, SW), "or.w", 0x6, 0x4, 0x4), 
+
+  {O (O_OR,  SL), AV_H8H, 2, "or.l",  {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x4, B30 | RS32, B30 | RD32, E}}},
+  EXPAND_TWOOP_L (O (O_OR, SL), "or.l", 0x4), 
+
+  {O (O_ORC, SB), AV_H8,  2, "orc", {{IMM8, CCR | DST, E}}, {{0x0, 0x4, IMM8LIST, E}}},
+  {O (O_ORC, SB), AV_H8S, 2, "orc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x4, IMM8LIST, E}}},
+
+  {O (O_MOV, SW), AV_H8,  6, "pop.w",  {{OR16, E}}, {{0x6, 0xD, 0x7, OR16, E}}},
+  {O (O_MOV, SL), AV_H8H, 6, "pop.l",  {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0x7, OR32 | B30, E}}},
+  {O (O_MOV, SW), AV_H8,  6, "push.w", {{OR16, E}}, {{0x6, 0xD, 0xF, OR16, E}}},
+  {O (O_MOV, SL), AV_H8H, 6, "push.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0xF, OR32 | B30, E}}},
+
+  EXPAND_UNOP_STD_B      (O (O_ROTL,  SB), "rotl.b",           PREFIX_017, 0x1, 0x2, 0x8),
+  EXPAND_UNOP_EXTENDED_B (O (O_ROTL,  SB), "rotl.b",  CONST_2, PREFIX_017, 0x1, 0x2, 0xc),
+  EXPAND_UNOP_STD_W      (O (O_ROTL,  SW), "rotl.w",           PREFIX_015, 0x1, 0x2, 0x9),
+  EXPAND_UNOP_EXTENDED_W (O (O_ROTL,  SW), "rotl.w",  CONST_2, PREFIX_015, 0x1, 0x2, 0xd),
+  EXPAND_UNOP_STD_L      (O (O_ROTL,  SL), "rotl.l",           PREFIX_010, 0x1, 0x2, 0xb),
+  EXPAND_UNOP_EXTENDED_L (O (O_ROTL,  SL), "rotl.l",  CONST_2, PREFIX_010, 0x1, 0x2, 0xf, B30),
+  EXPAND_UNOP_STD_B      (O (O_ROTR,  SB), "rotr.b",           PREFIX_017, 0x1, 0x3, 0x8),
+  EXPAND_UNOP_EXTENDED_B (O (O_ROTR,  SB), "rotr.b",  CONST_2, PREFIX_017, 0x1, 0x3, 0xc),
+  EXPAND_UNOP_STD_W      (O (O_ROTR,  SW), "rotr.w",           PREFIX_015, 0x1, 0x3, 0x9),
+  EXPAND_UNOP_EXTENDED_W (O (O_ROTR,  SW), "rotr.w",  CONST_2, PREFIX_015, 0x1, 0x3, 0xd),
+  EXPAND_UNOP_STD_L      (O (O_ROTR,  SL), "rotr.l",           PREFIX_010, 0x1, 0x3, 0xb),
+  EXPAND_UNOP_EXTENDED_L (O (O_ROTR,  SL), "rotr.l",  CONST_2, PREFIX_010, 0x1, 0x3, 0xf, B30),
+  EXPAND_UNOP_STD_B      (O (O_ROTXL, SB), "rotxl.b",          PREFIX_017, 0x1, 0x2, 0x0),
+  EXPAND_UNOP_EXTENDED_B (O (O_ROTXL, SB), "rotxl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0x4),
+  EXPAND_UNOP_STD_W      (O (O_ROTXL, SW), "rotxl.w",          PREFIX_015, 0x1, 0x2, 0x1),
+  EXPAND_UNOP_EXTENDED_W (O (O_ROTXL, SW), "rotxl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0x5),
+  EXPAND_UNOP_STD_L      (O (O_ROTXL, SL), "rotxl.l",          PREFIX_010, 0x1, 0x2, 0x3),
+  EXPAND_UNOP_EXTENDED_L (O (O_ROTXL, SL), "rotxl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0x7, B30),
+  EXPAND_UNOP_STD_B      (O (O_ROTXR, SB), "rotxr.b",          PREFIX_017, 0x1, 0x3, 0x0),
+  EXPAND_UNOP_EXTENDED_B (O (O_ROTXR, SB), "rotxr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0x4),
+  EXPAND_UNOP_STD_W      (O (O_ROTXR, SW), "rotxr.w",          PREFIX_015, 0x1, 0x3, 0x1),
+  EXPAND_UNOP_EXTENDED_W (O (O_ROTXR, SW), "rotxr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0x5),
+  EXPAND_UNOP_STD_L      (O (O_ROTXR, SL), "rotxr.l",          PREFIX_010, 0x1, 0x3, 0x3),
+  EXPAND_UNOP_EXTENDED_L (O (O_ROTXR, SL), "rotxr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0x7, B30),
+
+
+  {O (O_BPT,  SN), AV_H8,  10, "bpt",   {{E}}, {{0x7, 0xA, 0xF, 0xF, E}}},
+  {O (O_RTE,  SN), AV_H8,  10, "rte",   {{E}}, {{0x5, 0x6, 0x7, 0x0, E}}},
+  {O (O_RTS,  SN), AV_H8,   8, "rts",   {{E}}, {{0x5, 0x4, 0x7, 0x0, E}}},
+  {O (O_RTEL, SN), AV_H8SX, 0, "rte/l", {{RS32, RD32, E}}, {{0x5, 0x6, RS32 | B30, RD32 | B30, E}}},
+  {O (O_RTSL, SN), AV_H8SX, 0, "rts/l", {{RS32, RD32, E}}, {{0x5, 0x4, RS32 | B30, RD32 | B30, E}}},
+
+  EXPAND_UNOP_STD_B      (O (O_SHAL, SB), "shal.b",          PREFIX_017, 0x1, 0x0, 0x8),
+  EXPAND_UNOP_EXTENDED_B (O (O_SHAL, SB), "shal.b", CONST_2, PREFIX_017, 0x1, 0x0, 0xc),
+  EXPAND_UNOP_STD_W      (O (O_SHAL, SW), "shal.w",          PREFIX_015, 0x1, 0x0, 0x9),
+  EXPAND_UNOP_EXTENDED_W (O (O_SHAL, SW), "shal.w", CONST_2, PREFIX_015, 0x1, 0x0, 0xd),
+  EXPAND_UNOP_STD_L      (O (O_SHAL, SL), "shal.l",          PREFIX_010, 0x1, 0x0, 0xb),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHAL, SL), "shal.l", CONST_2, PREFIX_010, 0x1, 0x0, 0xf, B30),
+  EXPAND_UNOP_STD_B      (O (O_SHAR, SB), "shar.b",          PREFIX_017, 0x1, 0x1, 0x8),
+  EXPAND_UNOP_EXTENDED_B (O (O_SHAR, SB), "shar.b", CONST_2, PREFIX_017, 0x1, 0x1, 0xc),
+  EXPAND_UNOP_STD_W      (O (O_SHAR, SW), "shar.w",          PREFIX_015, 0x1, 0x1, 0x9),
+  EXPAND_UNOP_EXTENDED_W (O (O_SHAR, SW), "shar.w", CONST_2, PREFIX_015, 0x1, 0x1, 0xd),
+  EXPAND_UNOP_STD_L      (O (O_SHAR, SL), "shar.l",          PREFIX_010, 0x1, 0x1, 0xb),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHAR, SL), "shar.l", CONST_2, PREFIX_010, 0x1, 0x1, 0xf, B30),
+
+  EXPAND_UNOP_STD_B      (O (O_SHLL, SB), "shll.b",          PREFIX_017, 0x1, 0x0, 0x0),
+
+  {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{RS8,  RD8,  E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x0, 0x0, RD8,  E}}},
+
+  EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_2, PREFIX_017, 0x1, 0x0, 0x4),
+  EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_4, PREFIX_017, 0x1, 0x0, 0xa),
+  {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{IMM5, RD8,  E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x0, RD8,  E}}},
+
+  EXPAND_UNOP_STD_W      (O (O_SHLL, SW), "shll.w",          PREFIX_015, 0x1, 0x0, 0x1),
+
+  {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{RS8,  RD16, E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x0, 0x1, RD16, E}}},
+
+  EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_2, PREFIX_015, 0x1, 0x0, 0x5),
+  EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_4, PREFIX_015, 0x1, 0x0, 0x2),
+  EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_8, PREFIX_015, 0x1, 0x0, 0x6),
+  {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x1, RD16, E}}},
+
+  EXPAND_UNOP_STD_L      (O (O_SHLL, SL), "shll.l",           PREFIX_010, 0x1, 0x0, 0x3),
+
+  {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{RS8,  RD32, E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x0, 0x3, B30 | RD32, E}}},
+
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_2,  PREFIX_010, 0x1, 0x0, 0x7, B30),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_4,  PREFIX_010, 0x1, 0x0, 0x3, B31),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_8,  PREFIX_010, 0x1, 0x0, 0x7, B31),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_16, PREFIX_010, 0x1, 0x0, 0xf, B31),
+  {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x3, B30 | RD32, E}}},
+
+  EXPAND_UNOP_STD_B      (O (O_SHLR, SB), "shlr.b",          PREFIX_017, 0x1, 0x1, 0x0),
+
+  {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{RS8,  RD8,  E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x1, 0x0, RD8,  E}}},
+
+  EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_2, PREFIX_017, 0x1, 0x1, 0x4),
+  EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_4, PREFIX_017, 0x1, 0x1, 0xa),
+  {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{IMM5, RD8,  E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x0, RD8,  E}}},
+
+  EXPAND_UNOP_STD_W      (O (O_SHLR, SW), "shlr.w",          PREFIX_015, 0x1, 0x1, 0x1),
+
+  {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{RS8,  RD16, E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x1, 0x1, RD16, E}}},
+
+  EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_2, PREFIX_015, 0x1, 0x1, 0x5),
+  EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_4, PREFIX_015, 0x1, 0x1, 0x2),
+  EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_8, PREFIX_015, 0x1, 0x1, 0x6),
+  {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x1, RD16, E}}},
+
+  EXPAND_UNOP_STD_L      (O (O_SHLR, SL), "shlr.l",           PREFIX_010, 0x1, 0x1, 0x3),
+
+  {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{RS8,  RD32, E}}, {{0x7, 0x8, RS8,        0x8,  0x1, 0x1, 0x3, B30 | RD32, E}}},
+
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_2,  PREFIX_010, 0x1, 0x1, 0x7, B30),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_4,  PREFIX_010, 0x1, 0x1, 0x3, B31),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_8,  PREFIX_010, 0x1, 0x1, 0x7, B31),
+  EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_16, PREFIX_010, 0x1, 0x1, 0xf, B31),
+  {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x3, B30 | RD32, E}}},
+
+  {O (O_SLEEP, SN), AV_H8, 2, "sleep", {{E}}, {{0x0, 0x1, 0x8, 0x0, E}}},
+
+  {O (O_STC, SB), AV_H8,   2, "stc", {{CCR | SRC, RD8,            E}}, {{0x0, 0x2, B30 | CCR | SRC,           RD8,    E}}},
+  {O (O_STC, SB), AV_H8S,  2, "stc", {{EXR | SRC, RD8,            E}}, {{0x0, 0x2, B30 | EXR | SRC,           RD8,    E}}},
+  {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, RDIND,          E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND,    IGNORE, E}}},
+  {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, RDIND,          E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND,    IGNORE, E}}},
+  {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, RDPREDEC,       E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}},
+  {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, RDPREDEC,       E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}},
+  {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, DISP16DST,      E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG,                   IGNORE, DSTDISP16LIST, E}}},
+  {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, DISP16DST,      E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG,                   IGNORE, DSTDISP16LIST, E}}},
+  {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, DISP32DST,      E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}},
+  {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, DISP32DST,      E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}},
+  {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, ABS16DST,       E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}},
+  {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, ABS16DST,       E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}},
+  {O (O_STC, SW), AV_H8H,  2, "stc", {{CCR | SRC, ABS32DST,       E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}},
+  {O (O_STC, SW), AV_H8S,  2, "stc", {{EXR | SRC, ABS32DST,       E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}},
+  {O (O_STC, SL), AV_H8SX, 0, "stc", {{B30 | VBR_SBR | SRC, RD32, E}}, {{0x0, 0x2, B30 | VBR_SBR | SRC, RD32, E}}},
+
+
+  EXPAND_TWOOP_B (O (O_SUB, SB), "sub.b", 0xa, 0x1, 0x8, 0x3, B01), 
+
+  {O (O_SUB, SW), AV_H8,   2, "sub.w", {{RS16,      RD16,     E}}, {{0x1, 0x9, RS16,         RD16,   E}}}, 
+  {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RD16,     E}}, {{0x1, 0xa, B30 | IMM3NZ, RD16,   E}}}, 
+  {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RDIND,    E}}, {{0x7, 0xd,      B31 | RDIND,  IGNORE,       0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, 
+  {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, 
+  {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, 
+  EXPAND_TWOOP_W (O (O_SUB, SW), "sub.w", 0x1, 0x9, 0x3), 
+
+  {O (O_SUB, SL), AV_H8H,  6, "sub.l", {{RS32,      RD32,     E}}, {{0x1, 0xa, B31 | RS32,   B30 | RD32, E}}}, 
+  {O (O_SUB, SL), AV_H8SX, 0, "sub.l", {{IMM3NZ_NS, RD32,     E}}, {{0x1, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, 
+  EXPAND_TWOOP_L (O (O_SUB, SL), "sub.l", 0x3), 
+
+  {O (O_SUBS, SL), AV_H8, 2, "subs", {{KBIT, RDP, E}}, {{0x1, 0xB,KBIT, RDP, E}}},
+
+  {O (O_SUBX, SB), AV_H8,   2, "subx",   {{IMM8,      RD8,       E}}, {{0xb, RD8, IMM8LIST, E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8,      RDIND,     E}}, {{0x7, 0xd, B30 | RDIND, IGNORE,                        0xb, IGNORE, IMM8LIST, E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8,      RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0xb, IGNORE, IMM8LIST, E}}},
+  {O (O_SUBX, SB), AV_H8,   2, "subx",   {{RS8,       RD8,       E}}, {{0x1, 0xe, RS8,  RD8,    E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8,       RDIND,     E}}, {{0x7, 0xd, B30 | RDIND, IGNORE,                              0x1, 0xe, RS8, IGNORE, E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8,       RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31       | IGNORE, 0x1, 0xe, RS8, IGNORE, E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND,     RD8,       E}}, {{0x7, 0xc, B30 | RSIND, IGNORE,                              0x1, 0xe, IGNORE, RD8, E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RD8,       E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x1, 0xe, IGNORE, RD8, E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND,     RDIND,     E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND,     0xd, 0x0, RDIND,     0x3, IGNORE, E}}},
+  {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}},
+
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16,     RD16,      E}}, {{PREFIX_0151,                         0x7, 0x9, 0x3, RD16,   IMM16LIST, E}}}, 
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16,     RDIND,     E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, 
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16,     RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, 
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16,      RD16,      E}}, {{PREFIX_0151, 0x1, 0x9, RS16,  RD16,    E}}},
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16,      RDIND,     E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}},
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16,      RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}}, 
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND,     RD16,      E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}},
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RD16,      E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}},
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND,     RDIND,     E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND,     0xd, 0x0, RDIND,     0x3, IGNORE, E}}},
+  {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}},
+
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32,     RD32,      E}}, {{PREFIX_0101, 0x7, 0xa, 0x3,  RD32, IMM32LIST, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32,     RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND,     B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32,     RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32,      RD32,      E}}, {{PREFIX_0101, 0x1, 0xa, B31 | RS32,  B30 | RD32,    E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32,      RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND,     B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32,      RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND,     RD32,      E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND,     B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RD32,      E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND,     RDIND,     E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND,     0xd, 0x0, RDIND,     0x3, IGNORE, E}}},
+  {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}},
+
+  {O (O_TRAPA, SB), AV_H8H, 2, "trapa", {{IMM2,  E}}, {{0x5, 0x7, IMM2, IGNORE, E}}},
+  {O (O_TAS,   SB), AV_H8H, 2, "tas",   {{RSIND, E}}, {{0x0, 0x1, 0xe, 0x0, 0x7, 0xb, B30 | RSIND, 0xc, E}}},
+
+  {O (O_XOR,   SB), AV_H8,  2, "xor.b", {{IMM8, RD8,  E}}, {{0xd, RD8, IMM8LIST, E}}}, 
+  EXPAND_TWOOP_B (O (O_XOR, SB), "xor.b", 0xd, 0x1, 0x5, 0x5, 0), 
+
+  {O (O_XOR,   SW), AV_H8,  2, "xor.w", {{RS16, RD16, E}}, {{0x6, 0x5, RS16, RD16, E}}}, 
+  EXPAND_TWOOP_W (O (O_XOR, SW), "xor.w", 0x6, 0x5, 0x5), 
+
+  {O (O_XOR,   SL), AV_H8H, 2, "xor.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x5, B30 | RS32, B30 | RD32, E}}},
+  EXPAND_TWOOP_L (O (O_XOR, SL), "xor.l", 0x5), 
+
+  {O (O_XORC, SB), AV_H8,  2, "xorc", {{IMM8, CCR | DST, E}}, {{0x0, 0x5, IMM8LIST, E}}},
+  {O (O_XORC, SB), AV_H8S, 2, "xorc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x5, IMM8LIST, E}}},
+
+  {O (O_CLRMAC, SN), AV_H8S, 2, "clrmac", {{E}}, {{0x0, 0x1, 0xa, 0x0, E}}},
+  {O (O_MAC,    SW), AV_H8S, 2, "mac",    {{RSPOSTINC, RDPOSTINC, E}}, {{0x0, 0x1, 0x6, 0x0, 0x6, 0xd, B30 | RSPOSTINC, B30 | RDPOSTINC, E}}},
+  {O (O_LDMAC,  SL), AV_H8S, 2, "ldmac",  {{RS32, MD32, E}}, {{0x0, 0x3, MD32, RS32, E}}},
+  {O (O_STMAC,  SL), AV_H8S, 2, "stmac",  {{MS32, RD32, E}}, {{0x0, 0x2, MS32, RD32, E}}},
+  {O (O_LDM,    SL), AV_H8H, 6, "ldm.l",  {{RSPOSTINC, RD32, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0x7, B30 | RD32, E}}},
+  {O (O_STM,    SL), AV_H8H, 6, "stm.l",  {{RS32, RDPREDEC,  E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0xF, B30 | RS32, E}}},
+  {0, 0, 0, NULL, {{0, 0, 0}}, {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}}
+};
+#else
+extern const struct h8_opcode h8_opcodes[];
+#endif
+
diff --git a/binutils-2.25/include/opcode/hppa.h b/binutils-2.25/include/opcode/hppa.h
new file mode 100644
index 00000000..489ca550
--- /dev/null
+++ b/binutils-2.25/include/opcode/hppa.h
@@ -0,0 +1,1092 @@
+/* Table of opcodes for the PA-RISC.
+   Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
+   2001, 2002, 2003, 2004, 2005, 2006, 2009, 2010
+   Free Software Foundation, Inc.
+
+   Contributed by the Center for Software Science at the
+   University of Utah (pa-gdb-bugs@cs.utah.edu).
+
+   This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
+
+   GAS/GDB is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS/GDB is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS or GDB; see the file COPYING3.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+#if !defined(__STDC__) && !defined(const)
+#define const
+#endif
+
+/*
+ * Structure of an opcode table entry.
+ */
+
+/* There are two kinds of delay slot nullification: normal which is
+ * controled by the nullification bit, and conditional, which depends
+ * on the direction of the branch and its success or failure.
+ *
+ * NONE is unfortunately #defined in the hiux system include files.  
+ * #undef it away.
+ */
+#undef NONE
+struct pa_opcode
+{
+    const char *name;
+    unsigned long int match;	/* Bits that must be set...  */
+    unsigned long int mask;	/* ... in these bits. */
+    char *args;
+    enum pa_arch arch;
+    char flags;
+};
+
+/* Enables strict matching.  Opcodes with match errors are skipped
+   when this bit is set.  */
+#define FLAG_STRICT 0x1
+
+/*
+   All hppa opcodes are 32 bits.
+
+   The match component is a mask saying which bits must match a
+   particular opcode in order for an instruction to be an instance
+   of that opcode.
+
+   The args component is a string containing one character for each operand of
+   the instruction.  Characters used as a prefix allow any second character to
+   be used without conflicting with the main operand characters.
+
+   Bit positions in this description follow HP usage of lsb = 31,
+   "at" is lsb of field.
+
+   In the args field, the following characters must match exactly:
+
+	'+,() '
+
+   In the args field, the following characters are unused:
+
+	'  "         -  /   34 6789:;    '
+	'@  C         M             [\]  '
+	'`    e g                     }  '
+
+   Here are all the characters:
+
+	' !"#$%&'()*+-,./0123456789:;<=>?'
+	'@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'
+	'`abcdefghijklmnopqrstuvwxyz{|}~ '
+
+Kinds of operands:
+   x    integer register field at 15.
+   b    integer register field at 10.
+   t    integer register field at 31.
+   a	integer register field at 10 and 15 (for PERMH)
+   5    5 bit immediate at 15.
+   s    2 bit space specifier at 17.
+   S    3 bit space specifier at 18.
+   V    5 bit immediate value at 31
+   i    11 bit immediate value at 31
+   j    14 bit immediate value at 31
+   k    21 bit immediate value at 31
+   l    16 bit immediate value at 31 (wide mode only, unusual encoding).
+   n	nullification for branch instructions
+   N	nullification for spop and copr instructions
+   w    12 bit branch displacement
+   W    17 bit branch displacement (PC relative)
+   X    22 bit branch displacement (PC relative)
+   z    17 bit branch displacement (just a number, not an address)
+
+Also these:
+
+   .    2 bit shift amount at 25
+   *    4 bit shift amount at 25
+   p    5 bit shift count at 26 (to support the SHD instruction) encoded as
+        31-p
+   ~    6 bit shift count at 20,22:26 encoded as 63-~.
+   P    5 bit bit position at 26
+   q    6 bit bit position at 20,22:26
+   T    5 bit field length at 31 (encoded as 32-T)
+   %	6 bit field length at 23,27:31 (variable extract/deposit)
+   |	6 bit field length at 19,27:31 (fixed extract/deposit)
+   A    13 bit immediate at 18 (to support the BREAK instruction)
+   ^	like b, but describes a control register
+   !    sar (cr11) register
+   D    26 bit immediate at 31 (to support the DIAG instruction)
+   $    9 bit immediate at 28 (to support POPBTS)
+
+   v    3 bit Special Function Unit identifier at 25
+   O    20 bit Special Function Unit operation split between 15 bits at 20
+        and 5 bits at 31
+   o    15 bit Special Function Unit operation at 20
+   2    22 bit Special Function Unit operation split between 17 bits at 20
+        and 5 bits at 31
+   1    15 bit Special Function Unit operation split between 10 bits at 20
+        and 5 bits at 31
+   0    10 bit Special Function Unit operation split between 5 bits at 20
+        and 5 bits at 31
+   u    3 bit coprocessor unit identifier at 25
+   F    Source Floating Point Operand Format Completer encoded 2 bits at 20
+   I    Source Floating Point Operand Format Completer encoded 1 bits at 20
+	(for 0xe format FP instructions)
+   G    Destination Floating Point Operand Format Completer encoded 2 bits at 18
+   H    Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
+        (very similar to 'F')
+
+   r	5 bit immediate value at 31 (for the break instruction)
+	(very similar to V above, except the value is unsigned instead of
+	low_sign_ext)
+   R	5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
+	(same as r above, except the value is in a different location)
+   U	10 bit immediate value at 15 (for SSM, RSM on pa2.0)
+   Q	5 bit immediate value at 10 (a bit position specified in
+	the bb instruction. It's the same as r above, except the
+        value is in a different location)
+   B	5 bit immediate value at 10 (a bit position specified in
+	the bb instruction. Similar to Q, but 64 bit handling is
+	different.
+   Z    %r1 -- implicit target of addil instruction.
+   L    ,%r2 completer for new syntax branch
+   {    Source format completer for fcnv
+   _    Destination format completer for fcnv
+   h    cbit for fcmp
+   =    gfx tests for ftest
+   d    14 bit offset for single precision FP long load/store.
+   #    14 bit offset for double precision FP load long/store.
+   J    Yet another 14 bit offset for load/store with ma,mb completers.
+   K    Yet another 14 bit offset for load/store with ma,mb completers.
+   y    16 bit offset for word aligned load/store (PA2.0 wide).
+   &    16 bit offset for dword aligned load/store (PA2.0 wide).
+   <    16 bit offset for load/store with ma,mb completers (PA2.0 wide).
+   >    16 bit offset for load/store with ma,mb completers (PA2.0 wide).
+   Y    %sr0,%r31 -- implicit target of be,l instruction.
+   @	implicit immediate value of 0
+
+Completer operands all have 'c' as the prefix:
+
+   cx   indexed load and store completer.
+   cX   indexed load and store completer.  Like cx, but emits a space
+	after in disassembler.
+   cm   short load and store completer.
+   cM   short load and store completer.  Like cm, but emits a space
+        after in disassembler.
+   cq   long load and store completer (like cm, but inserted into a
+	different location in the target instruction).
+   cs   store bytes short completer.
+   cA   store bytes short completer.  Like cs, but emits a space
+        after in disassembler.
+   ce   long load/store completer for LDW/STW with a different encoding
+	than the others
+   cc   load cache control hint
+   cd   load and clear cache control hint
+   cC   store cache control hint
+   co	ordered access
+
+   cp	branch link and push completer
+   cP	branch pop completer
+   cl	branch link completer
+   cg	branch gate completer
+
+   cw	read/write completer for PROBE
+   cW	wide completer for MFCTL
+   cL	local processor completer for cache control
+   cZ   System Control Completer (to support LPA, LHA, etc.)
+
+   ci	correction completer for DCOR
+   ca	add completer
+   cy	32 bit add carry completer
+   cY	64 bit add carry completer
+   cv	signed overflow trap completer
+   ct	trap on condition completer for ADDI, SUB
+   cT	trap on condition completer for UADDCM
+   cb	32 bit borrow completer for SUB
+   cB	64 bit borrow completer for SUB
+
+   ch	left/right half completer
+   cH	signed/unsigned saturation completer
+   cS	signed/unsigned completer at 21
+   cz	zero/sign extension completer.
+   c*	permutation completer
+
+Condition operands all have '?' as the prefix:
+
+   ?f   Floating point compare conditions (encoded as 5 bits at 31)
+
+   ?a	add conditions
+   ?A	64 bit add conditions
+   ?@   add branch conditions followed by nullify
+   ?d	non-negated add branch conditions
+   ?D	negated add branch conditions
+   ?w	wide mode non-negated add branch conditions
+   ?W	wide mode negated add branch conditions
+
+   ?s   compare/subtract conditions
+   ?S	64 bit compare/subtract conditions
+   ?t   non-negated compare and branch conditions
+   ?n   32 bit compare and branch conditions followed by nullify
+   ?N   64 bit compare and branch conditions followed by nullify
+   ?Q	64 bit compare and branch conditions for CMPIB instruction
+
+   ?l   logical conditions
+   ?L	64 bit logical conditions
+
+   ?b   branch on bit conditions
+   ?B	64 bit branch on bit conditions
+
+   ?x   shift/extract/deposit conditions
+   ?X	64 bit shift/extract/deposit conditions
+   ?y   shift/extract/deposit conditions followed by nullify for conditional
+        branches
+
+   ?u   unit conditions
+   ?U   64 bit unit conditions
+
+Floating point registers all have 'f' as a prefix:
+
+   ft	target register at 31
+   fT	target register with L/R halves at 31
+   fa	operand 1 register at 10
+   fA   operand 1 register with L/R halves at 10
+   fX   Same as fA, except prints a space before register during disasm
+   fb	operand 2 register at 15
+   fB   operand 2 register with L/R halves at 15
+   fC   operand 3 register with L/R halves at 16:18,21:23
+   fe   Like fT, but encoding is different.
+   fE   Same as fe, except prints a space before register during disasm.
+   fx	target register at 15 (only for PA 2.0 long format FLDD/FSTD). 
+
+Float registers for fmpyadd and fmpysub:
+
+   fi	mult operand 1 register at 10
+   fj	mult operand 2 register at 15
+   fk	mult target register at 20
+   fl	add/sub operand register at 25
+   fm	add/sub target register at 31
+
+*/
+
+
+#if 0
+/* List of characters not to put a space after.  Note that
+   "," is included, as the "spopN" operations use literal
+   commas in their completer sections.  */
+static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";
+#endif
+
+/* The order of the opcodes in this table is significant:
+
+   * The assembler requires that all instances of the same mnemonic be
+     consecutive.  If they aren't, the assembler will bomb at runtime.
+
+   * Immediate fields use pa_get_absolute_expression to parse the
+     string.  It will generate a "bad expression" error if passed
+     a register name.  Thus, register index variants of an opcode
+     need to precede immediate variants.
+
+   * The disassembler does not care about the order of the opcodes
+     except in cases where implicit addressing is used.
+
+   Here are the rules for ordering the opcodes of a mnemonic:
+
+   1) Opcodes with FLAG_STRICT should precede opcodes without
+      FLAG_STRICT.
+
+   2) Opcodes with FLAG_STRICT should be ordered as follows:
+      register index opcodes, short immediate opcodes, and finally
+      long immediate opcodes.  When both pa10 and pa11 variants
+      of the same opcode are available, the pa10 opcode should
+      come first for correct architectural promotion.
+
+   3) When implicit addressing is available for an opcode, the
+      implicit opcode should precede the explicit opcode.
+
+   4) Opcodes without FLAG_STRICT should be ordered as follows:
+      register index opcodes, long immediate opcodes, and finally
+      short immediate opcodes.  */
+	
+static const struct pa_opcode pa_opcodes[] =
+{
+
+/* Pseudo-instructions.  */
+
+{ "ldi",	0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */
+{ "ldi",	0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */
+
+{ "cmpib",	0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT},
+{ "cmpib", 	0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT},
+{ "comib", 	0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/
+/* This entry is for the disassembler only.  It will never be used by
+   assembler.  */
+{ "comib", 	0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/
+{ "cmpb",	0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT},
+{ "cmpb",	0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT},
+{ "comb",	0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */
+/* This entry is for the disassembler only.  It will never be used by
+   assembler.  */
+{ "comb",	0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */
+{ "addb",	0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT},
+{ "addb",	0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */
+/* This entry is for the disassembler only.  It will never be used by
+   assembler.  */
+{ "addb",	0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0},
+{ "addib",	0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT},
+{ "addib",	0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/
+/* This entry is for the disassembler only.  It will never be used by
+   assembler.  */
+{ "addib",	0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/
+{ "nop",	0x08000240, 0xffffffff, "", pa10, 0},      /* or 0,0,0 */
+{ "copy",	0x08000240, 0xffe0ffe0, "x,t", pa10, 0},   /* or r,0,t */
+{ "mtsar",	0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */
+
+/* Loads and Stores for integer registers.  */
+
+{ "ldd",	0x0c0000c0, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},
+{ "ldd",	0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT},
+{ "ldd",	0x0c0010e0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
+{ "ldd",	0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
+{ "ldd",	0x0c0010c0, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},
+{ "ldd",	0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT},
+{ "ldd",	0x50000000, 0xfc000002, "cq&(b),x", pa20w, FLAG_STRICT},
+{ "ldd",	0x50000000, 0xfc00c002, "cq#(b),x", pa20, FLAG_STRICT},
+{ "ldd",	0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT},
+{ "ldw",	0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
+{ "ldw",	0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
+{ "ldw",	0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
+{ "ldw",	0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
+{ "ldw",	0x0c0010a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
+{ "ldw",	0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
+{ "ldw",	0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
+{ "ldw",	0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
+{ "ldw",	0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
+{ "ldw",	0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
+{ "ldw",	0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT},
+{ "ldw",	0x5c000004, 0xfc000006, "ce>(b),x", pa20w, FLAG_STRICT},
+{ "ldw",	0x48000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
+{ "ldw",	0x5c000004, 0xfc00c006, "ceK(b),x", pa20, FLAG_STRICT},
+{ "ldw",	0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT},
+{ "ldw",	0x4c000000, 0xfc00c000, "ceJ(b),x", pa10, FLAG_STRICT},
+{ "ldw",	0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT},
+{ "ldw",	0x48000000, 0xfc00c000, "j(b),x", pa10, 0},
+{ "ldw",	0x48000000, 0xfc000000, "j(s,b),x", pa10, 0},
+{ "ldh",	0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
+{ "ldh",	0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
+{ "ldh",	0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
+{ "ldh",	0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
+{ "ldh",	0x0c001060, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
+{ "ldh",	0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
+{ "ldh",	0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
+{ "ldh",	0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
+{ "ldh",	0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
+{ "ldh",	0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
+{ "ldh",	0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
+{ "ldh",	0x44000000, 0xfc00c000, "j(b),x", pa10, 0},
+{ "ldh",	0x44000000, 0xfc000000, "j(s,b),x", pa10, 0},
+{ "ldb",	0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
+{ "ldb",	0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
+{ "ldb",	0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
+{ "ldb",	0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
+{ "ldb",	0x0c001020, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
+{ "ldb",	0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
+{ "ldb",	0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
+{ "ldb",	0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
+{ "ldb",	0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
+{ "ldb",	0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
+{ "ldb",	0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
+{ "ldb",	0x40000000, 0xfc00c000, "j(b),x", pa10, 0},
+{ "ldb",	0x40000000, 0xfc000000, "j(s,b),x", pa10, 0},
+{ "std",	0x0c0012e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
+{ "std",	0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
+{ "std",	0x0c0012c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT},
+{ "std",	0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT},
+{ "std",	0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT},
+{ "std",	0x70000000, 0xfc00c002, "cqx,#(b)", pa20, FLAG_STRICT},
+{ "std",	0x70000000, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT},
+{ "stw",	0x0c0012a0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
+{ "stw",	0x0c0012a0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
+{ "stw",	0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
+{ "stw",	0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
+{ "stw",	0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
+{ "stw",	0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
+{ "stw",	0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT},
+{ "stw",	0x7c000004, 0xfc000006, "cex,>(b)", pa20w, FLAG_STRICT},
+{ "stw",	0x68000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
+{ "stw",	0x7c000004, 0xfc00c006, "cex,K(b)", pa20, FLAG_STRICT},
+{ "stw",	0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT},
+{ "stw",	0x6c000000, 0xfc00c000, "cex,J(b)", pa10, FLAG_STRICT},
+{ "stw",	0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT},
+{ "stw",	0x68000000, 0xfc00c000, "x,j(b)", pa10, 0},
+{ "stw",	0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0},
+{ "sth",	0x0c001260, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
+{ "sth",	0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
+{ "sth",	0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
+{ "sth",	0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
+{ "sth",	0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
+{ "sth",	0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
+{ "sth",	0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
+{ "sth",	0x64000000, 0xfc00c000, "x,j(b)", pa10, 0},
+{ "sth",	0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0},
+{ "stb",	0x0c001220, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
+{ "stb",	0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
+{ "stb",	0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
+{ "stb",	0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
+{ "stb",	0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
+{ "stb",	0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
+{ "stb",	0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
+{ "stb",	0x60000000, 0xfc00c000, "x,j(b)", pa10, 0},
+{ "stb",	0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0},
+{ "ldwm",	0x4c000000, 0xfc00c000, "j(b),x", pa10, 0},
+{ "ldwm",	0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0},
+{ "stwm",	0x6c000000, 0xfc00c000, "x,j(b)", pa10, 0},
+{ "stwm",	0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0},
+{ "ldwx",	0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
+{ "ldwx",	0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
+{ "ldwx",	0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
+{ "ldwx",	0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
+{ "ldwx",	0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, 0},
+{ "ldwx",	0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
+{ "ldhx",	0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
+{ "ldhx",	0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
+{ "ldhx",	0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
+{ "ldhx",	0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
+{ "ldhx",	0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, 0},
+{ "ldhx",	0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
+{ "ldbx",	0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
+{ "ldbx",	0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
+{ "ldbx",	0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
+{ "ldbx",	0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
+{ "ldbx",	0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, 0},
+{ "ldbx",	0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
+{ "ldwa",	0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
+{ "ldwa",	0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
+{ "ldwa",	0x0c0011a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
+{ "ldwa",	0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
+{ "ldwa",	0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
+{ "ldcw",	0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
+{ "ldcw",	0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
+{ "ldcw",	0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT},
+{ "ldcw",	0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT},
+{ "ldcw",	0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
+{ "ldcw",	0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
+{ "ldcw",	0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT},
+{ "ldcw",	0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT},
+{ "stwa",	0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
+{ "stwa",	0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
+{ "stwa",	0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
+{ "stby",	0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, FLAG_STRICT},
+{ "stby",	0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, FLAG_STRICT},
+{ "stby",	0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT},
+{ "stby",	0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT},
+{ "ldda",	0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},
+{ "ldda",	0x0c001120, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
+{ "ldda",	0x0c001100, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},
+{ "ldcd",	0x0c000140, 0xfc00d3c0, "cxcdx(b),t", pa20, FLAG_STRICT},
+{ "ldcd",	0x0c000140, 0xfc0013c0, "cxcdx(s,b),t", pa20, FLAG_STRICT},
+{ "ldcd",	0x0c001140, 0xfc00d3c0, "cmcd5(b),t", pa20, FLAG_STRICT},
+{ "ldcd",	0x0c001140, 0xfc0013c0, "cmcd5(s,b),t", pa20, FLAG_STRICT},
+{ "stda",	0x0c0013e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
+{ "stda",	0x0c0013c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT},
+{ "ldwax",	0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
+{ "ldwax",	0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
+{ "ldwax",	0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0},
+{ "ldcwx",	0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
+{ "ldcwx",	0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
+{ "ldcwx",	0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT},
+{ "ldcwx",	0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT},
+{ "ldcwx",	0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, 0},
+{ "ldcwx",	0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
+{ "ldws",	0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
+{ "ldws",	0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
+{ "ldws",	0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
+{ "ldws",	0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
+{ "ldws",	0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, 0},
+{ "ldws",	0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
+{ "ldhs",	0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
+{ "ldhs",	0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
+{ "ldhs",	0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
+{ "ldhs",	0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
+{ "ldhs",	0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, 0},
+{ "ldhs",	0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
+{ "ldbs",	0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
+{ "ldbs",	0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
+{ "ldbs",	0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
+{ "ldbs",	0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
+{ "ldbs",	0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, 0},
+{ "ldbs",	0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
+{ "ldwas",	0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
+{ "ldwas",	0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
+{ "ldwas",	0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0},
+{ "ldcws",	0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
+{ "ldcws",	0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
+{ "ldcws",	0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT},
+{ "ldcws",	0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT},
+{ "ldcws",	0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, 0},
+{ "ldcws",	0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
+{ "stws",	0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
+{ "stws",	0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
+{ "stws",	0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
+{ "stws",	0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
+{ "stws",	0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
+{ "stws",	0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
+{ "sths",	0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
+{ "sths",	0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
+{ "sths",	0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
+{ "sths",	0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
+{ "sths",	0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
+{ "sths",	0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
+{ "stbs",	0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
+{ "stbs",	0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
+{ "stbs",	0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
+{ "stbs",	0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
+{ "stbs",	0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
+{ "stbs",	0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
+{ "stwas",	0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
+{ "stwas",	0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
+{ "stwas",	0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
+{ "stdby",	0x0c001340, 0xfc00d3c0, "cscCx,V(b)", pa20, FLAG_STRICT},
+{ "stdby",	0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT},
+{ "stbys",	0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, FLAG_STRICT},
+{ "stbys",	0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, FLAG_STRICT},
+{ "stbys",	0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT},
+{ "stbys",	0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT},
+{ "stbys",	0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, 0},
+{ "stbys",	0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0},
+
+/* Immediate instructions.  */
+{ "ldo",	0x34000000, 0xfc000000, "l(b),x", pa20w, 0},
+{ "ldo",	0x34000000, 0xfc00c000, "j(b),x", pa10, 0},
+{ "ldil",	0x20000000, 0xfc000000, "k,b", pa10, 0},
+{ "addil",	0x28000000, 0xfc000000, "k,b,Z", pa10, 0},
+{ "addil",	0x28000000, 0xfc000000, "k,b", pa10, 0},
+
+/* Branching instructions.  */
+{ "b",		0xe8008000, 0xfc00e000, "cpnXL", pa20, FLAG_STRICT},
+{ "b",		0xe800a000, 0xfc00e000, "clnXL", pa20, FLAG_STRICT},
+{ "b",		0xe8000000, 0xfc00e000, "clnW,b", pa10, FLAG_STRICT},
+{ "b",		0xe8002000, 0xfc00e000, "cgnW,b", pa10, FLAG_STRICT},
+{ "b",		0xe8000000, 0xffe0e000, "nW", pa10, 0},  /* b,l foo,r0 */
+{ "bl",		0xe8000000, 0xfc00e000, "nW,b", pa10, 0},
+{ "gate",	0xe8002000, 0xfc00e000, "nW,b", pa10, 0},
+{ "blr",	0xe8004000, 0xfc00e001, "nx,b", pa10, 0},
+{ "bv",		0xe800c000, 0xfc00fffd, "nx(b)", pa10, 0},
+{ "bv",		0xe800c000, 0xfc00fffd, "n(b)", pa10, 0},
+{ "bve",	0xe800f001, 0xfc1ffffd, "cpn(b)L", pa20, FLAG_STRICT},
+{ "bve",	0xe800f000, 0xfc1ffffd, "cln(b)L", pa20, FLAG_STRICT},
+{ "bve",	0xe800d001, 0xfc1ffffd, "cPn(b)", pa20, FLAG_STRICT},
+{ "bve",	0xe800d000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT},
+{ "be",		0xe4000000, 0xfc000000, "clnz(S,b),Y", pa10, FLAG_STRICT},
+{ "be",		0xe4000000, 0xfc000000, "clnz(b),Y", pa10, FLAG_STRICT},
+{ "be",		0xe0000000, 0xfc000000, "nz(S,b)", pa10, 0},
+{ "be",		0xe0000000, 0xfc000000, "nz(b)", pa10, 0},
+{ "ble",	0xe4000000, 0xfc000000, "nz(S,b)", pa10, 0},
+{ "movb",	0xc8000000, 0xfc000000, "?ynx,b,w", pa10, 0},
+{ "movib",	0xcc000000, 0xfc000000, "?yn5,b,w", pa10, 0},
+{ "combt",	0x80000000, 0xfc000000, "?tnx,b,w", pa10, 0},
+{ "combf",	0x88000000, 0xfc000000, "?tnx,b,w", pa10, 0},
+{ "comibt",	0x84000000, 0xfc000000, "?tn5,b,w", pa10, 0},
+{ "comibf",	0x8c000000, 0xfc000000, "?tn5,b,w", pa10, 0},
+{ "addbt",	0xa0000000, 0xfc000000, "?dnx,b,w", pa10, 0},
+{ "addbf",	0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0},
+{ "addibt",	0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0},
+{ "addibf",	0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0},
+{ "bb",		0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, 
+{ "bb",		0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, 
+{ "bb",		0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, 
+{ "bb",		0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, FLAG_STRICT}, 
+{ "bb",		0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, 0}, 
+{ "bvb",	0xc0004000, 0xffe04000, "?bnx,w", pa10, 0},
+{ "clrbts",	0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT},
+{ "popbts",	0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT},
+{ "pushnom",	0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT},
+{ "pushbts",	0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT},
+
+/* Computation Instructions.  */
+
+{ "cmpclr",	0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT},
+{ "cmpclr",	0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT},
+{ "comclr",	0x08000880, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "or",		0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
+{ "or",		0x08000240, 0xfc000fe0, "?lx,b,t", pa10, 0},
+{ "xor",	0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
+{ "xor",	0x08000280, 0xfc000fe0, "?lx,b,t", pa10, 0},
+{ "and",	0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
+{ "and",	0x08000200, 0xfc000fe0, "?lx,b,t", pa10, 0},
+{ "andcm",	0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
+{ "andcm",	0x08000000, 0xfc000fe0, "?lx,b,t", pa10, 0},
+{ "uxor",	0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT},
+{ "uxor",	0x08000380, 0xfc000fe0, "?ux,b,t", pa10, 0},
+{ "uaddcm",	0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20, FLAG_STRICT},
+{ "uaddcm",	0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10, FLAG_STRICT},
+{ "uaddcm",	0x08000980, 0xfc000fe0, "?ux,b,t", pa10, 0},
+{ "uaddcmt",	0x080009c0, 0xfc000fe0, "?ux,b,t", pa10, 0},
+{ "dcor",	0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20, FLAG_STRICT},
+{ "dcor",	0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10, FLAG_STRICT},
+{ "dcor",	0x08000b80, 0xfc1f0fe0, "?ub,t",   pa10, 0},
+{ "idcor",	0x08000bc0, 0xfc1f0fe0, "?ub,t",   pa10, 0},
+{ "addi",	0xb0000000, 0xfc000000, "ct?ai,b,x", pa10, FLAG_STRICT},
+{ "addi",	0xb4000000, 0xfc000000, "cv?ai,b,x", pa10, FLAG_STRICT},
+{ "addi",	0xb4000000, 0xfc000800, "?ai,b,x", pa10, 0},
+{ "addio",	0xb4000800, 0xfc000800, "?ai,b,x", pa10, 0},
+{ "addit",	0xb0000000, 0xfc000800, "?ai,b,x", pa10, 0},
+{ "addito",	0xb0000800, 0xfc000800, "?ai,b,x", pa10, 0},
+{ "add",	0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20, FLAG_STRICT},
+{ "add",	0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10, FLAG_STRICT},
+{ "add",	0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20, FLAG_STRICT},
+{ "add",	0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10, FLAG_STRICT},
+{ "add",	0x08000600, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "addl",	0x08000a00, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "addo",	0x08000e00, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "addc",	0x08000700, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "addco",	0x08000f00, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sub",	0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20, FLAG_STRICT},
+{ "sub",	0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10, FLAG_STRICT},
+{ "sub",	0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20, FLAG_STRICT},
+{ "sub",	0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10, FLAG_STRICT},
+{ "sub",	0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20, FLAG_STRICT},
+{ "sub",	0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10, FLAG_STRICT},
+{ "sub",	0x08000400, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "subo",	0x08000c00, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "subb",	0x08000500, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "subbo",	0x08000d00, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "subt",	0x080004c0, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "subto",	0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "ds",		0x08000440, 0xfc000fe0, "?sx,b,t", pa10, 0},
+{ "subi",	0x94000000, 0xfc000000, "cv?si,b,x", pa10, FLAG_STRICT},
+{ "subi",	0x94000000, 0xfc000800, "?si,b,x", pa10, 0},
+{ "subio",	0x94000800, 0xfc000800, "?si,b,x", pa10, 0},
+{ "cmpiclr",	0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT},
+{ "cmpiclr",	0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT},
+{ "comiclr",	0x90000000, 0xfc000800, "?si,b,x", pa10, 0},
+{ "shladd",	0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20, FLAG_STRICT},
+{ "shladd",	0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10, FLAG_STRICT},
+{ "sh1add",	0x08000640, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh1addl",	0x08000a40, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh1addo",	0x08000e40, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh2add",	0x08000680, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh2addl",	0x08000a80, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh2addo",	0x08000e80, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh3add",	0x080006c0, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh3addl",	0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10, 0},
+{ "sh3addo",	0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10, 0},
+
+/* Subword Operation Instructions.  */
+
+{ "hadd",	0x08000300, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT},
+{ "havg",	0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT},
+{ "hshl",	0xf8008800, 0xffe0fc20, "x,*,t", pa20, FLAG_STRICT},
+{ "hshladd",	0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
+{ "hshr",	0xf800c800, 0xfc1ff820, "cSb,*,t", pa20, FLAG_STRICT},
+{ "hshradd",	0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
+{ "hsub",	0x08000100, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT},
+{ "mixh",	0xf8008400, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT},
+{ "mixw",	0xf8008000, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT},
+{ "permh",	0xf8000000, 0xfc009020, "c*a,t", pa20, FLAG_STRICT},
+
+
+/* Extract and Deposit Instructions.  */
+
+{ "shrpd",	0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT},
+{ "shrpd",	0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT},
+{ "shrpw",	0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT},
+{ "shrpw",	0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT},
+{ "vshd",	0xd0000000, 0xfc001fe0, "?xx,b,t", pa10, 0},
+{ "shd",	0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, 0},
+{ "extrd",	0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20, FLAG_STRICT},
+{ "extrd",	0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20, FLAG_STRICT},
+{ "extrw",	0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10, FLAG_STRICT},
+{ "extrw",	0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10, FLAG_STRICT},
+{ "vextru",	0xd0001000, 0xfc001fe0, "?xb,T,x", pa10, 0},
+{ "vextrs",	0xd0001400, 0xfc001fe0, "?xb,T,x", pa10, 0},
+{ "extru",	0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10, 0},
+{ "extrs",	0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10, 0},
+{ "depd",	0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20, FLAG_STRICT},
+{ "depd",	0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20, FLAG_STRICT},
+{ "depdi",	0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20, FLAG_STRICT},
+{ "depdi",	0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20, FLAG_STRICT},
+{ "depw",	0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10, FLAG_STRICT},
+{ "depw",	0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10, FLAG_STRICT},
+{ "depwi",	0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10, FLAG_STRICT},
+{ "depwi",	0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10, FLAG_STRICT},
+{ "zvdep",	0xd4000000, 0xfc001fe0, "?xx,T,b", pa10, 0},
+{ "vdep",	0xd4000400, 0xfc001fe0, "?xx,T,b", pa10, 0},
+{ "zdep",	0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10, 0},
+{ "dep",	0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10, 0},
+{ "zvdepi",	0xd4001000, 0xfc001fe0, "?x5,T,b", pa10, 0},
+{ "vdepi",	0xd4001400, 0xfc001fe0, "?x5,T,b", pa10, 0},
+{ "zdepi",	0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10, 0},
+{ "depi",	0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10, 0},
+
+/* System Control Instructions.  */
+
+{ "break",	0x00000000, 0xfc001fe0, "r,A", pa10, 0},
+{ "rfi",	0x00000c00, 0xffffff1f, "cr", pa10, FLAG_STRICT},
+{ "rfi",	0x00000c00, 0xffffffff, "", pa10, 0},
+{ "rfir",	0x00000ca0, 0xffffffff, "", pa11, 0},
+{ "ssm",	0x00000d60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT},
+{ "ssm",	0x00000d60, 0xffe0ffe0, "R,t", pa10, 0},
+{ "rsm",	0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT},
+{ "rsm",	0x00000e60, 0xffe0ffe0, "R,t", pa10, 0},
+{ "mtsm",	0x00001860, 0xffe0ffff, "x", pa10, 0},
+{ "ldsid",	0x000010a0, 0xfc1fffe0, "(b),t", pa10, 0},
+{ "ldsid",	0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10, 0},
+{ "mtsp",	0x00001820, 0xffe01fff, "x,S", pa10, 0},
+{ "mtctl",	0x00001840, 0xfc00ffff, "x,^", pa10, 0},
+{ "mtsarcm",	0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT},
+{ "mfia",	0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT},
+{ "mfsp",	0x000004a0, 0xffff1fe0, "S,t", pa10, 0},
+{ "mfctl",	0x016048a0, 0xffffffe0, "cW!,t", pa20, FLAG_STRICT},
+{ "mfctl",	0x000008a0, 0xfc1fffe0, "^,t", pa10, 0},
+{ "sync",	0x00000400, 0xffffffff, "", pa10, 0},
+{ "syncdma",	0x00100400, 0xffffffff, "", pa10, 0},
+{ "probe",	0x04001180, 0xfc00ffa0, "cw(b),x,t", pa10, FLAG_STRICT},
+{ "probe",	0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT},
+{ "probei",	0x04003180, 0xfc00ffa0, "cw(b),R,t", pa10, FLAG_STRICT},
+{ "probei",	0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT},
+{ "prober",	0x04001180, 0xfc00ffe0, "(b),x,t", pa10, 0},
+{ "prober",	0x04001180, 0xfc003fe0, "(s,b),x,t", pa10, 0},
+{ "proberi",	0x04003180, 0xfc00ffe0, "(b),R,t", pa10, 0},
+{ "proberi",	0x04003180, 0xfc003fe0, "(s,b),R,t", pa10, 0},
+{ "probew",	0x040011c0, 0xfc00ffe0, "(b),x,t", pa10, 0},
+{ "probew",	0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10, 0},
+{ "probewi",	0x040031c0, 0xfc00ffe0, "(b),R,t", pa10, 0},
+{ "probewi",	0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10, 0},
+{ "lpa",	0x04001340, 0xfc00ffc0, "cZx(b),t", pa10, 0},
+{ "lpa",	0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10, 0},
+{ "lci",	0x04001300, 0xfc00ffe0, "x(b),t", pa11, 0},
+{ "lci",	0x04001300, 0xfc003fe0, "x(s,b),t", pa11, 0},
+{ "pdtlb",	0x04001600, 0xfc00ffdf, "cLcZx(b)", pa20, FLAG_STRICT},
+{ "pdtlb",	0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT},
+{ "pdtlb",	0x04001600, 0xfc1fffdf, "cLcZ@(b)", pa20, FLAG_STRICT},
+{ "pdtlb",	0x04001600, 0xfc1f3fdf, "cLcZ@(s,b)", pa20, FLAG_STRICT},
+{ "pdtlb",	0x04001200, 0xfc00ffdf, "cZx(b)", pa10, 0},
+{ "pdtlb",	0x04001200, 0xfc003fdf, "cZx(s,b)", pa10, 0},
+{ "pitlb",	0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT},
+{ "pitlb",	0x04000600, 0xfc1f1fdf, "cLcZ@(S,b)", pa20, FLAG_STRICT},
+{ "pitlb",	0x04000200, 0xfc001fdf, "cZx(S,b)", pa10, 0},
+{ "pdtlbe",	0x04001240, 0xfc00ffdf, "cZx(b)", pa10, 0},
+{ "pdtlbe",	0x04001240, 0xfc003fdf, "cZx(s,b)", pa10, 0},
+{ "pitlbe",	0x04000240, 0xfc001fdf, "cZx(S,b)", pa10, 0},
+{ "idtlba",	0x04001040, 0xfc00ffff, "x,(b)", pa10, 0},
+{ "idtlba",	0x04001040, 0xfc003fff, "x,(s,b)", pa10, 0},
+{ "iitlba",	0x04000040, 0xfc001fff, "x,(S,b)", pa10, 0},
+{ "idtlbp",	0x04001000, 0xfc00ffff, "x,(b)", pa10, 0},
+{ "idtlbp",	0x04001000, 0xfc003fff, "x,(s,b)", pa10, 0},
+{ "iitlbp",	0x04000000, 0xfc001fff, "x,(S,b)", pa10, 0},
+{ "pdc",	0x04001380, 0xfc00ffdf, "cZx(b)", pa10, 0},
+{ "pdc",	0x04001380, 0xfc003fdf, "cZx(s,b)", pa10, 0},
+{ "fdc",	0x04001280, 0xfc00ffdf, "cZx(b)", pa10, FLAG_STRICT},
+{ "fdc",	0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, FLAG_STRICT},
+{ "fdc",	0x04003280, 0xfc00ffff, "5(b)", pa20, FLAG_STRICT},
+{ "fdc",	0x04003280, 0xfc003fff, "5(s,b)", pa20, FLAG_STRICT},
+{ "fdc",	0x04001280, 0xfc00ffdf, "cZx(b)", pa10, 0},
+{ "fdc",	0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, 0},
+{ "fic",	0x040013c0, 0xfc00dfdf, "cZx(b)", pa20, FLAG_STRICT},
+{ "fic",	0x04000280, 0xfc001fdf, "cZx(S,b)", pa10, 0},
+{ "fdce",	0x040012c0, 0xfc00ffdf, "cZx(b)", pa10, 0},
+{ "fdce",	0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0},
+{ "fice",	0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0},
+{ "diag",	0x14000000, 0xfc000000, "D", pa10, 0},
+{ "idtlbt",	0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT},
+{ "iitlbt",	0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT},
+
+/* These may be specific to certain versions of the PA.  Joel claimed
+   they were 72000 (7200?) specific.  However, I'm almost certain the
+   mtcpu/mfcpu were undocumented, but available in the older 700 machines.  */
+{ "mtcpu",	0x14001600, 0xfc00ffff, "x,^", pa10, 0},
+{ "mfcpu",	0x14001A00, 0xfc00ffff, "^,x", pa10, 0},
+{ "tocen",	0x14403600, 0xffffffff, "", pa10, 0},
+{ "tocdis",	0x14401620, 0xffffffff, "", pa10, 0},
+{ "shdwgr",	0x14402600, 0xffffffff, "", pa10, 0},
+{ "grshdw",	0x14400620, 0xffffffff, "", pa10, 0},
+
+/* gfw and gfr are not in the HP PA 1.1 manual, but they are in either
+   the Timex FPU or the Mustang ERS (not sure which) manual.  */
+{ "gfw",	0x04001680, 0xfc00ffdf, "cZx(b)", pa11, 0},
+{ "gfw",	0x04001680, 0xfc003fdf, "cZx(s,b)", pa11, 0},
+{ "gfr",	0x04001a80, 0xfc00ffdf, "cZx(b)", pa11, 0},
+{ "gfr",	0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11, 0},
+
+/* Floating Point Coprocessor Instructions.  */
+ 
+{ "fldw",	0x24000000, 0xfc00df80, "cXx(b),fT", pa10, FLAG_STRICT},
+{ "fldw",	0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, FLAG_STRICT},
+{ "fldw",	0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT},
+{ "fldw",	0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT},
+{ "fldw",	0x24001020, 0xfc1ff3a0, "cocc@(b),fT", pa20, FLAG_STRICT},
+{ "fldw",	0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT},
+{ "fldw",	0x24001000, 0xfc00df80, "cM5(b),fT", pa10, FLAG_STRICT},
+{ "fldw",	0x24001000, 0xfc001f80, "cM5(s,b),fT", pa10, FLAG_STRICT},
+{ "fldw",	0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT},
+{ "fldw",	0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT},
+{ "fldw",	0x5c000000, 0xfc000004, "y(b),fe", pa20w, FLAG_STRICT},
+{ "fldw",	0x58000000, 0xfc000000, "cJy(b),fe", pa20w, FLAG_STRICT},
+{ "fldw",	0x5c000000, 0xfc00c004, "d(b),fe", pa20, FLAG_STRICT},
+{ "fldw",	0x5c000000, 0xfc000004, "d(s,b),fe", pa20, FLAG_STRICT},
+{ "fldw",	0x58000000, 0xfc00c000, "cJd(b),fe", pa20, FLAG_STRICT},
+{ "fldw",	0x58000000, 0xfc000000, "cJd(s,b),fe", pa20, FLAG_STRICT},
+{ "fldd",	0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, FLAG_STRICT},
+{ "fldd",	0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, FLAG_STRICT},
+{ "fldd",	0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT},
+{ "fldd",	0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT},
+{ "fldd",	0x2c001020, 0xfc1ff3e0, "cocc@(b),ft", pa20, FLAG_STRICT},
+{ "fldd",	0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT},
+{ "fldd",	0x2c001000, 0xfc00dfc0, "cM5(b),ft", pa10, FLAG_STRICT},
+{ "fldd",	0x2c001000, 0xfc001fc0, "cM5(s,b),ft", pa10, FLAG_STRICT},
+{ "fldd",	0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT},
+{ "fldd",	0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT},
+{ "fldd",	0x50000002, 0xfc000002, "cq&(b),fx", pa20w, FLAG_STRICT},
+{ "fldd",	0x50000002, 0xfc00c002, "cq#(b),fx", pa20, FLAG_STRICT},
+{ "fldd",	0x50000002, 0xfc000002, "cq#(s,b),fx", pa20, FLAG_STRICT},
+{ "fstw",	0x24000200, 0xfc00df80, "cXfT,x(b)", pa10, FLAG_STRICT},
+{ "fstw",	0x24000200, 0xfc001f80, "cXfT,x(s,b)", pa10, FLAG_STRICT},
+{ "fstw",	0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT},
+{ "fstw",	0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT},
+{ "fstw",	0x24001220, 0xfc1ff3a0, "cocCfT,@(b)", pa20, FLAG_STRICT},
+{ "fstw",	0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa20, FLAG_STRICT},
+{ "fstw",	0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, FLAG_STRICT},
+{ "fstw",	0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, FLAG_STRICT},
+{ "fstw",	0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, FLAG_STRICT},
+{ "fstw",	0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, FLAG_STRICT},
+{ "fstw",	0x7c000000, 0xfc000004, "fE,y(b)", pa20w, FLAG_STRICT},
+{ "fstw",	0x78000000, 0xfc000000, "cJfE,y(b)", pa20w, FLAG_STRICT},
+{ "fstw",	0x7c000000, 0xfc00c004, "fE,d(b)", pa20, FLAG_STRICT},
+{ "fstw",	0x7c000000, 0xfc000004, "fE,d(s,b)", pa20, FLAG_STRICT},
+{ "fstw",	0x78000000, 0xfc00c000, "cJfE,d(b)", pa20, FLAG_STRICT},
+{ "fstw",	0x78000000, 0xfc000000, "cJfE,d(s,b)", pa20, FLAG_STRICT},
+{ "fstd",	0x2c000200, 0xfc00dfc0, "cXft,x(b)", pa10, FLAG_STRICT},
+{ "fstd",	0x2c000200, 0xfc001fc0, "cXft,x(s,b)", pa10, FLAG_STRICT},
+{ "fstd",	0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT},
+{ "fstd",	0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT},
+{ "fstd",	0x2c001220, 0xfc1ff3e0, "cocCft,@(b)", pa20, FLAG_STRICT},
+{ "fstd",	0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa20, FLAG_STRICT},
+{ "fstd",	0x2c001200, 0xfc00dfc0, "cMft,5(b)", pa10, FLAG_STRICT},
+{ "fstd",	0x2c001200, 0xfc001fc0, "cMft,5(s,b)", pa10, FLAG_STRICT},
+{ "fstd",	0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT},
+{ "fstd",	0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT},
+{ "fstd",	0x70000002, 0xfc000002, "cqfx,&(b)", pa20w, FLAG_STRICT},
+{ "fstd",	0x70000002, 0xfc00c002, "cqfx,#(b)", pa20, FLAG_STRICT},
+{ "fstd",	0x70000002, 0xfc000002, "cqfx,#(s,b)", pa20, FLAG_STRICT},
+{ "fldwx",	0x24000000, 0xfc00df80, "cXx(b),fT", pa10, FLAG_STRICT},
+{ "fldwx",	0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, FLAG_STRICT},
+{ "fldwx",	0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT},
+{ "fldwx",	0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT},
+{ "fldwx",	0x24000000, 0xfc00df80, "cXx(b),fT", pa10, 0},
+{ "fldwx",	0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0},
+{ "flddx",	0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, FLAG_STRICT},
+{ "flddx",	0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, FLAG_STRICT},
+{ "flddx",	0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT},
+{ "flddx",	0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT},
+{ "flddx",	0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, 0},
+{ "flddx",	0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0},
+{ "fstwx",	0x24000200, 0xfc00df80, "cxfT,x(b)", pa10, FLAG_STRICT},
+{ "fstwx",	0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, FLAG_STRICT},
+{ "fstwx",	0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT},
+{ "fstwx",	0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT},
+{ "fstwx",	0x24000200, 0xfc00df80, "cxfT,x(b)", pa10, 0},
+{ "fstwx",	0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0},
+{ "fstdx",	0x2c000200, 0xfc00dfc0, "cxft,x(b)", pa10, FLAG_STRICT},
+{ "fstdx",	0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, FLAG_STRICT},
+{ "fstdx",	0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT},
+{ "fstdx",	0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT},
+{ "fstdx",	0x2c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0},
+{ "fstdx",	0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0},
+{ "fstqx",	0x3c000200, 0xfc00dfc0, "cXft,x(b)", pa10, 0},
+{ "fstqx",	0x3c000200, 0xfc001fc0, "cXft,x(s,b)", pa10, 0},
+{ "fldws",	0x24001000, 0xfc00df80, "cm5(b),fT", pa10, FLAG_STRICT},
+{ "fldws",	0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, FLAG_STRICT},
+{ "fldws",	0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT},
+{ "fldws",	0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT},
+{ "fldws",	0x24001000, 0xfc00df80, "cm5(b),fT", pa10, 0},
+{ "fldws",	0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, 0},
+{ "fldds",	0x2c001000, 0xfc00dfc0, "cm5(b),ft", pa10, FLAG_STRICT},
+{ "fldds",	0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, FLAG_STRICT},
+{ "fldds",	0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT},
+{ "fldds",	0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT},
+{ "fldds",	0x2c001000, 0xfc00dfc0, "cm5(b),ft", pa10, 0},
+{ "fldds",	0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, 0},
+{ "fstws",	0x24001200, 0xfc00df80, "cmfT,5(b)", pa10, FLAG_STRICT},
+{ "fstws",	0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, FLAG_STRICT},
+{ "fstws",	0x24001200, 0xfc00d380, "cmcCfT,5(b)", pa11, FLAG_STRICT},
+{ "fstws",	0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa11, FLAG_STRICT},
+{ "fstws",	0x24001200, 0xfc00df80, "cmfT,5(b)", pa10, 0},
+{ "fstws",	0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, 0},
+{ "fstds",	0x2c001200, 0xfc00dfc0, "cmft,5(b)", pa10, FLAG_STRICT},
+{ "fstds",	0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, FLAG_STRICT},
+{ "fstds",	0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT},
+{ "fstds",	0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT},
+{ "fstds",	0x2c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0},
+{ "fstds",	0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0},
+{ "fstqs",	0x3c001200, 0xfc00dfc0, "cMft,5(b)", pa10, 0},
+{ "fstqs",	0x3c001200, 0xfc001fc0, "cMft,5(s,b)", pa10, 0},
+{ "fadd",	0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
+{ "fadd",	0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
+{ "fsub",	0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
+{ "fsub",	0x38002600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
+{ "fmpy",	0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
+{ "fmpy",	0x38004600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
+{ "fdiv",	0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
+{ "fdiv",	0x38006600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
+{ "fsqrt",	0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
+{ "fsqrt",	0x38008000, 0xfc1fe720, "FfA,fT", pa10, 0},
+{ "fabs",	0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
+{ "fabs",	0x38006000, 0xfc1fe720, "FfA,fT", pa10, 0},
+{ "frem",	0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
+{ "frem",	0x38008600, 0xfc00e720, "FfA,fB,fT", pa10, 0},
+{ "frnd",	0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
+{ "frnd",	0x3800a000, 0xfc1fe720, "FfA,fT", pa10, 0},
+{ "fcpy",	0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
+{ "fcpy",	0x38004000, 0xfc1fe720, "FfA,fT", pa10, 0},
+{ "fcnvff",	0x30000200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
+{ "fcnvff",	0x38000200, 0xfc1f8720, "FGfA,fT", pa10, 0},
+{ "fcnvxf",	0x30008200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
+{ "fcnvxf",	0x38008200, 0xfc1f8720, "FGfA,fT", pa10, 0},
+{ "fcnvfx",	0x30010200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
+{ "fcnvfx",	0x38010200, 0xfc1f8720, "FGfA,fT", pa10, 0},
+{ "fcnvfxt",	0x30018200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
+{ "fcnvfxt",	0x38018200, 0xfc1f8720, "FGfA,fT", pa10, 0},
+{ "fmpyfadd",	0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
+{ "fmpynfadd",	0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
+{ "fneg",	0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
+{ "fneg",	0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
+{ "fnegabs",	0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
+{ "fnegabs",	0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
+{ "fcnv",	0x30000200, 0xfc1c0720, "{_fa,fT", pa20, FLAG_STRICT},
+{ "fcnv",	0x38000200, 0xfc1c0720, "FGfA,fT", pa20, FLAG_STRICT},
+{ "fcmp",	0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, FLAG_STRICT},
+{ "fcmp",	0x38000400, 0xfc00e720, "I?ffA,fB", pa10, FLAG_STRICT},
+{ "fcmp",	0x30000400, 0xfc0007e0, "F?ffa,fb,h", pa20, FLAG_STRICT},
+{ "fcmp",	0x38000400, 0xfc000720, "I?ffA,fB,h", pa20, FLAG_STRICT},
+{ "fcmp",	0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, 0},
+{ "fcmp",	0x38000400, 0xfc00e720, "I?ffA,fB", pa10, 0},
+{ "xmpyu",	0x38004700, 0xfc00e720, "fX,fB,fT", pa11, 0},
+{ "fmpyadd",	0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0},
+{ "fmpysub",	0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0},
+{ "ftest",	0x30002420, 0xffffffff, "", pa10, FLAG_STRICT},
+{ "ftest",	0x30002420, 0xffffffe0, ",=", pa20, FLAG_STRICT},
+{ "ftest",	0x30000420, 0xffff1fff, "m", pa20, FLAG_STRICT},
+{ "fid",	0x30000000, 0xffffffff, "", pa11, 0},
+
+/* Performance Monitor Instructions.  */
+
+{ "pmdis",	0x30000280, 0xffffffdf, "N", pa20, FLAG_STRICT},
+{ "pmenb",	0x30000680, 0xffffffff, "", pa20, FLAG_STRICT},
+
+/* Assist Instructions.  */
+
+{ "spop0",	0x10000000, 0xfc000600, "v,ON", pa10, 0},
+{ "spop1",	0x10000200, 0xfc000600, "v,oNt", pa10, 0},
+{ "spop2",	0x10000400, 0xfc000600, "v,1Nb", pa10, 0},
+{ "spop3",	0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0},
+{ "copr",	0x30000000, 0xfc000000, "u,2N", pa10, 0},
+{ "cldw",	0x24000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT},
+{ "cldw",	0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT},
+{ "cldw",	0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
+{ "cldw",	0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
+{ "cldw",	0x24001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT},
+{ "cldw",	0x24001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT},
+{ "cldw",	0x24001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT},
+{ "cldw",	0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT},
+{ "cldw",	0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
+{ "cldw",	0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
+{ "cldd",	0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT},
+{ "cldd",	0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT},
+{ "cldd",	0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
+{ "cldd",	0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
+{ "cldd",	0x2c001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT},
+{ "cldd",	0x2c001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT},
+{ "cldd",	0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT},
+{ "cldd",	0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT},
+{ "cldd",	0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
+{ "cldd",	0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
+{ "cstw",	0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT},
+{ "cstw",	0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT},
+{ "cstw",	0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
+{ "cstw",	0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
+{ "cstw",	0x24001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT},
+{ "cstw",	0x24001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT},
+{ "cstw",	0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT},
+{ "cstw",	0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT},
+{ "cstw",	0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
+{ "cstw",	0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
+{ "cstd",	0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT},
+{ "cstd",	0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT},
+{ "cstd",	0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
+{ "cstd",	0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
+{ "cstd",	0x2c001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT},
+{ "cstd",	0x2c001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT},
+{ "cstd",	0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT},
+{ "cstd",	0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT},
+{ "cstd",	0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
+{ "cstd",	0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
+{ "cldwx",	0x24000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT},
+{ "cldwx",	0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT},
+{ "cldwx",	0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
+{ "cldwx",	0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
+{ "cldwx",	0x24000000, 0xfc00de00, "ucXx(b),t", pa10, 0},
+{ "cldwx",	0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0},
+{ "clddx",	0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT},
+{ "clddx",	0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT},
+{ "clddx",	0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
+{ "clddx",	0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
+{ "clddx",	0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, 0},
+{ "clddx",	0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0},
+{ "cstwx",	0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT},
+{ "cstwx",	0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT},
+{ "cstwx",	0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
+{ "cstwx",	0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
+{ "cstwx",	0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, 0},
+{ "cstwx",	0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0},
+{ "cstdx",	0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT},
+{ "cstdx",	0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT},
+{ "cstdx",	0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
+{ "cstdx",	0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
+{ "cstdx",	0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, 0},
+{ "cstdx",	0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0},
+{ "cldws",	0x24001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT},
+{ "cldws",	0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT},
+{ "cldws",	0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
+{ "cldws",	0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
+{ "cldws",	0x24001000, 0xfc00de00, "ucM5(b),t", pa10, 0},
+{ "cldws",	0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0},
+{ "cldds",	0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT},
+{ "cldds",	0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT},
+{ "cldds",	0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
+{ "cldds",	0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
+{ "cldds",	0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, 0},
+{ "cldds",	0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0},
+{ "cstws",	0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT},
+{ "cstws",	0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT},
+{ "cstws",	0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
+{ "cstws",	0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
+{ "cstws",	0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, 0},
+{ "cstws",	0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0},
+{ "cstds",	0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT},
+{ "cstds",	0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT},
+{ "cstds",	0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
+{ "cstds",	0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
+{ "cstds",	0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, 0},
+{ "cstds",	0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0},
+
+/* More pseudo instructions which must follow the main table.  */
+{ "call",	0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT},
+{ "call",	0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT},
+{ "ret",	0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT},
+
+};
+
+#define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0]))
+
+/* SKV 12/18/92. Added some denotations for various operands.  */
+
+#define PA_IMM11_AT_31 'i'
+#define PA_IMM14_AT_31 'j'
+#define PA_IMM21_AT_31 'k'
+#define PA_DISP12 'w'
+#define PA_DISP17 'W'
+
+#define N_HPPA_OPERAND_FORMATS 5
diff --git a/binutils-2.25/include/opcode/i370.h b/binutils-2.25/include/opcode/i370.h
new file mode 100644
index 00000000..e3b7166d
--- /dev/null
+++ b/binutils-2.25/include/opcode/i370.h
@@ -0,0 +1,267 @@
+/* i370.h -- Header file for S/390 opcode table
+   Copyright 1994, 1995, 1998, 1999, 2000, 2003, 2010
+   Free Software Foundation, Inc.
+   PowerPC version written by Ian Lance Taylor, Cygnus Support
+   Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org>
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef I370_H
+#define I370_H
+
+/* The opcode table is an array of struct i370_opcode.  */
+typedef union
+{
+   unsigned int   i[2];
+   unsigned short s[4];
+   unsigned char  b[8];
+}  i370_insn_t;
+
+struct i370_opcode
+{
+  /* The opcode name.  */
+  const char *name;
+
+  /* the length of the instruction */
+  char len;
+
+  /* The opcode itself.  Those bits which will be filled in with
+     operands are zeroes.  */
+  i370_insn_t opcode;
+
+  /* The opcode mask.  This is used by the disassembler.  This is a
+     mask containing ones indicating those bits which must match the
+     opcode field, and zeroes indicating those bits which need not
+     match (and are presumably filled in by operands).  */
+  i370_insn_t mask;
+
+  /* One bit flags for the opcode.  These are used to indicate which
+     specific processors support the instructions.  The defined values
+     are listed below.  */
+  unsigned long flags;
+
+  /* An array of operand codes.  Each code is an index into the
+     operand table.  They appear in the order which the operands must
+     appear in assembly code, and are terminated by a zero.  */
+  unsigned char operands[8];
+};
+
+/* The table itself is sorted by major opcode number, and is otherwise
+   in the order in which the disassembler should consider
+   instructions.  */
+extern const struct i370_opcode i370_opcodes[];
+extern const int i370_num_opcodes;
+
+/* Values defined for the flags field of a struct i370_opcode.  */
+
+/* Opcode is defined for the original 360 architecture.  */
+#define I370_OPCODE_360 (0x01)
+
+/* Opcode is defined for the 370 architecture.  */
+#define I370_OPCODE_370 (0x02)
+
+/* Opcode is defined for the 370-XA architecture.  */
+#define I370_OPCODE_370_XA (0x04)
+
+/* Opcode is defined for the ESA/370 architecture.  */
+#define I370_OPCODE_ESA370 (0x08)
+
+/* Opcode is defined for the ESA/390 architecture.  */
+#define I370_OPCODE_ESA390 (0x10)
+
+/* Opcode is defined for the ESA/390 w/ BFP facility.  */
+#define I370_OPCODE_ESA390_BF (0x20)
+
+/* Opcode is defined for the ESA/390 w/ branch & set authority facility.  */
+#define I370_OPCODE_ESA390_BS (0x40)
+
+/* Opcode is defined for the ESA/390 w/ checksum facility.  */
+#define I370_OPCODE_ESA390_CK (0x80)
+
+/* Opcode is defined for the ESA/390 w/ compare & move extended facility.  */
+#define I370_OPCODE_ESA390_CM (0x100)
+
+/* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */
+#define I370_OPCODE_ESA390_FX (0x200)
+
+/* Opcode is defined for the ESA/390 w/ HFP facility. */
+#define I370_OPCODE_ESA390_HX (0x400)
+
+/* Opcode is defined for the ESA/390 w/ immediate & relative facility.  */
+#define I370_OPCODE_ESA390_IR (0x800)
+
+/* Opcode is defined for the ESA/390 w/ move-inverse facility.  */
+#define I370_OPCODE_ESA390_MI (0x1000)
+
+/* Opcode is defined for the ESA/390 w/ program-call-fast facility.  */
+#define I370_OPCODE_ESA390_PC (0x2000)
+
+/* Opcode is defined for the ESA/390 w/ perform-locked-op facility.  */
+#define I370_OPCODE_ESA390_PL (0x4000)
+
+/* Opcode is defined for the ESA/390 w/ square-root facility.  */
+#define I370_OPCODE_ESA390_QR (0x8000)
+
+/* Opcode is defined for the ESA/390 w/ resume-program facility.  */
+#define I370_OPCODE_ESA390_RP (0x10000)
+
+/* Opcode is defined for the ESA/390 w/ set-address-space-fast facility.  */
+#define I370_OPCODE_ESA390_SA (0x20000)
+
+/* Opcode is defined for the ESA/390 w/ subspace group facility.  */
+#define I370_OPCODE_ESA390_SG (0x40000)
+
+/* Opcode is defined for the ESA/390 w/ string facility.  */
+#define I370_OPCODE_ESA390_SR (0x80000)
+
+/* Opcode is defined for the ESA/390 w/ trap facility.  */
+#define I370_OPCODE_ESA390_TR (0x100000)
+
+#define I370_OPCODE_ESA390_SUPERSET (0x1fffff)
+
+
+/* The operands table is an array of struct i370_operand.  */
+
+struct i370_operand
+{
+  /* The number of bits in the operand.  */
+  int bits;
+
+  /* How far the operand is left shifted in the instruction.  */
+  int shift;
+
+  /* Insertion function.  This is used by the assembler.  To insert an
+     operand value into an instruction, check this field.
+
+     If it is NULL, execute
+         i |= (op & ((1 << o->bits) - 1)) << o->shift;
+     (i is the instruction which we are filling in, o is a pointer to
+     this structure, and op is the opcode value; this assumes twos
+     complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction and the operand value.  It will return the new value
+     of the instruction.  If the ERRMSG argument is not NULL, then if
+     the operand value is illegal, *ERRMSG will be set to a warning
+     string (the operand will be inserted in any case).  If the
+     operand value is legal, *ERRMSG will be unchanged (most operands
+     can accept any value).  */
+  i370_insn_t (*insert)
+    (i370_insn_t instruction, long op, const char **errmsg);
+
+  /* Extraction function.  This is used by the disassembler.  To
+     extract this operand type from an instruction, check this field.
+
+     If it is NULL, compute
+         op = ((i) >> o->shift) & ((1 << o->bits) - 1);
+	 if ((o->flags & I370_OPERAND_SIGNED) != 0
+           && (op & (1 << (o->bits - 1))) != 0)
+	   op -= 1 << o->bits;
+     (i is the instruction, o is a pointer to this structure, and op
+     is the result; this assumes twos complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction value.  It will return the value of the operand.  If
+     the INVALID argument is not NULL, *INVALID will be set to
+     non-zero if this operand type can not actually be extracted from
+     this operand (i.e., the instruction does not match).  If the
+     operand is valid, *INVALID will not be changed.  */
+  long (*extract) (i370_insn_t instruction, int *invalid);
+
+  /* One bit syntax flags.  */
+  unsigned long flags;
+
+  /* name -- handy for debugging, otherwise pointless */
+  char * name;
+};
+
+/* Elements in the table are retrieved by indexing with values from
+   the operands field of the i370_opcodes table.  */
+
+extern const struct i370_operand i370_operands[];
+
+/* Values defined for the flags field of a struct i370_operand.  */
+
+/* This operand should be wrapped in parentheses rather than
+   separated from the previous by a comma.  This is used for S, RS and
+   SS form instructions which want their operands to look like
+   reg,displacement(basereg) */
+#define I370_OPERAND_SBASE (0x01)
+
+/* This operand is a base register.  It may or may not appear next
+   to an index register, i.e. either of the two forms
+   reg,displacement(basereg)
+   reg,displacement(index,basereg) */
+#define I370_OPERAND_BASE (0x02)
+
+/* This pair of operands should be wrapped in parentheses rather than
+   separated from the last by a comma.  This is used for the RX form
+   instructions which want their operands to look like
+   reg,displacement(index,basereg) */
+#define I370_OPERAND_INDEX (0x04)
+
+/* This operand names a register.  The disassembler uses this to print
+   register names with a leading 'r'.  */
+#define I370_OPERAND_GPR (0x08)
+
+/* This operand names a floating point register.  The disassembler
+   prints these with a leading 'f'.  */
+#define I370_OPERAND_FPR (0x10)
+
+/* This operand is a displacement.  */
+#define I370_OPERAND_RELATIVE (0x20)
+
+/* This operand is a length, such as that in SS form instructions.  */
+#define I370_OPERAND_LENGTH (0x40)
+
+/* This operand is optional, and is zero if omitted.  This is used for
+   the optional B2 field in the shift-left, shift-right instructions.  The
+   assembler must count the number of operands remaining on the line,
+   and the number of operands remaining for the opcode, and decide
+   whether this operand is present or not.  The disassembler should
+   print this operand out only if it is not zero.  */
+#define I370_OPERAND_OPTIONAL (0x80)
+
+
+/* Define some misc macros.  We keep them with the operands table
+   for simplicity.  The macro table is an array of struct i370_macro.  */
+
+struct i370_macro
+{
+  /* The macro name.  */
+  const char *name;
+
+  /* The number of operands the macro takes.  */
+  unsigned int operands;
+
+  /* One bit flags for the opcode.  These are used to indicate which
+     specific processors support the instructions.  The values are the
+     same as those for the struct i370_opcode flags field.  */
+  unsigned long flags;
+
+  /* A format string to turn the macro into a normal instruction.
+     Each %N in the string is replaced with operand number N (zero
+     based).  */
+  const char *format;
+};
+
+extern const struct i370_macro i370_macros[];
+extern const int i370_num_macros;
+
+
+#endif /* I370_H */
diff --git a/binutils-2.25/include/opcode/i386.h b/binutils-2.25/include/opcode/i386.h
new file mode 100644
index 00000000..6021002b
--- /dev/null
+++ b/binutils-2.25/include/opcode/i386.h
@@ -0,0 +1,148 @@
+/* opcode/i386.h -- Intel 80386 opcode macros
+   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
+   Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
+   ix86 Unix assemblers, generate floating point instructions with
+   reversed source and destination registers in certain cases.
+   Unfortunately, gcc and possibly many other programs use this
+   reversed syntax, so we're stuck with it.
+
+   eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
+   `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
+   the expected st(3) = st(3) - st
+
+   This happens with all the non-commutative arithmetic floating point
+   operations with two register operands, where the source register is
+   %st, and destination register is %st(i).
+
+   The affected opcode map is dceX, dcfX, deeX, defX.  */
+
+#ifndef OPCODE_I386_H
+#define OPCODE_I386_H
+
+#ifndef SYSV386_COMPAT
+/* Set non-zero for broken, compatible instructions.  Set to zero for
+   non-broken opcodes at your peril.  gcc generates SystemV/386
+   compatible instructions.  */
+#define SYSV386_COMPAT 1
+#endif
+#ifndef OLDGCC_COMPAT
+/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
+   generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
+   reversed.  */
+#define OLDGCC_COMPAT SYSV386_COMPAT
+#endif
+
+#define MOV_AX_DISP32 0xa0
+#define POP_SEG_SHORT 0x07
+#define JUMP_PC_RELATIVE 0xeb
+#define INT_OPCODE  0xcd
+#define INT3_OPCODE 0xcc
+/* The opcode for the fwait instruction, which disassembler treats as a
+   prefix when it can.  */
+#define FWAIT_OPCODE 0x9b
+
+/* Instruction prefixes.
+   NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as
+   part of the opcode.  Other prefixes may still appear between them
+   and the 0x0f part of the opcode.  */
+#define ADDR_PREFIX_OPCODE 0x67
+#define DATA_PREFIX_OPCODE 0x66
+#define LOCK_PREFIX_OPCODE 0xf0
+#define CS_PREFIX_OPCODE 0x2e
+#define DS_PREFIX_OPCODE 0x3e
+#define ES_PREFIX_OPCODE 0x26
+#define FS_PREFIX_OPCODE 0x64
+#define GS_PREFIX_OPCODE 0x65
+#define SS_PREFIX_OPCODE 0x36
+#define REPNE_PREFIX_OPCODE 0xf2
+#define REPE_PREFIX_OPCODE  0xf3
+#define XACQUIRE_PREFIX_OPCODE 0xf2
+#define XRELEASE_PREFIX_OPCODE 0xf3
+#define BND_PREFIX_OPCODE 0xf2
+
+#define TWO_BYTE_OPCODE_ESCAPE 0x0f
+#define NOP_OPCODE (char) 0x90
+
+/* register numbers */
+#define EAX_REG_NUM 0
+#define ECX_REG_NUM 1
+#define EDX_REG_NUM 2
+#define EBX_REG_NUM 3
+#define ESP_REG_NUM 4
+#define EBP_REG_NUM 5
+#define ESI_REG_NUM 6
+#define EDI_REG_NUM 7
+
+/* modrm_byte.regmem for twobyte escape */
+#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
+/* index_base_byte.index for no index register addressing */
+#define NO_INDEX_REGISTER ESP_REG_NUM
+/* index_base_byte.base for no base register addressing */
+#define NO_BASE_REGISTER EBP_REG_NUM
+#define NO_BASE_REGISTER_16 6
+
+/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
+#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
+#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
+
+/* Extract fields from the mod/rm byte.  */
+#define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3)
+#define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7)
+#define MODRM_RM_FIELD(modrm)  (((modrm) >> 0) & 7)
+
+/* Extract fields from the sib byte.  */
+#define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3)
+#define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7)
+#define SIB_BASE_FIELD(sib)  (((sib) >> 0) & 7)
+
+/* x86-64 extension prefix.  */
+#define REX_OPCODE	0x40
+
+/* Non-zero if OPCODE is the rex prefix.  */
+#define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE)
+
+/* Indicates 64 bit operand size.  */
+#define REX_W	8
+/* High extension to reg field of modrm byte.  */
+#define REX_R	4
+/* High extension to SIB index field.  */
+#define REX_X	2
+/* High extension to base field of modrm or SIB, or reg field of opcode.  */
+#define REX_B	1
+
+/* max operands per insn */
+#define MAX_OPERANDS 5
+
+/* max immediates per insn (lcall, ljmp, insertq, extrq) */
+#define MAX_IMMEDIATE_OPERANDS 2
+
+/* max memory refs per insn (string ops) */
+#define MAX_MEMORY_OPERANDS 2
+
+/* max size of insn mnemonics.  */
+#define MAX_MNEM_SIZE 20
+
+/* max size of register name in insn mnemonics.  */
+#define MAX_REG_NAME_SIZE 8
+
+#endif /* OPCODE_I386_H */
diff --git a/binutils-2.25/include/opcode/i860.h b/binutils-2.25/include/opcode/i860.h
new file mode 100644
index 00000000..7f4aafd9
--- /dev/null
+++ b/binutils-2.25/include/opcode/i860.h
@@ -0,0 +1,507 @@
+/* Table of opcodes for the i860.
+   Copyright 1989, 1991, 2000, 2002, 2003, 2010
+   Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
+
+   GAS/GDB is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS/GDB is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS or GDB; see the file COPYING3.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+/* Structure of an opcode table entry.  */
+struct i860_opcode
+{
+    /* The opcode name.  */
+    const char *name;
+
+    /* Bits that must be set.  */
+    unsigned long match;
+
+    /* Bits that must not be set.  */
+    unsigned long lose;
+
+    const char *args;
+
+    /* Nonzero if this is a possible expand-instruction.  */
+    char expand;
+};
+
+
+enum expand_type
+{
+    E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY, XP_ONLY
+};
+
+
+/* All i860 opcodes are 32 bits, except for the pseudo-instructions
+   and the operations utilizing a 32-bit address expression, an
+   unsigned 32-bit constant, or a signed 32-bit constant.
+   These opcodes are expanded into a two-instruction sequence for
+   any situation where the immediate operand does not fit in 32 bits.
+   In the case of the add and subtract operations the expansion is
+   to a three-instruction sequence (ex: orh, or, adds).  In cases
+   where the address is to be relocated, the instruction is
+   expanded to handle the worse case, this could be optimized at
+   the final link if the actual address were known.
+
+   The pseudoinstructions are:  mov, fmov, pmov, nop, and fnop.
+   These instructions are implemented as a one or two instruction
+   sequence of other operations.
+
+   The match component is a mask saying which bits must match a
+   particular opcode in order for an instruction to be an instance
+   of that opcode.
+
+   The args component is a string containing one character
+   for each operand of the instruction.
+
+Kinds of operands:
+   #    Number used by optimizer.  It is ignored.
+   1    src1 integer register.
+   2    src2 integer register.
+   d    dest register.
+   c	ctrlreg control register.
+   i    16 bit immediate.
+   I    16 bit immediate, aligned 2^0. (ld.b)
+   J    16 bit immediate, aligned 2^1. (ld.s)
+   K    16 bit immediate, aligned 2^2. (ld.l, {p}fld.l, fst.l)
+   L    16 bit immediate, aligned 2^3. ({p}fld.d, fst.d)
+   M    16 bit immediate, aligned 2^4. ({p}fld.q, fst.q)
+   5    5 bit immediate.
+   l    lbroff 26 bit PC relative immediate.
+   r    sbroff 16 bit PC relative immediate.
+   s	split 16 bit immediate.
+   S	split 16 bit immediate, aligned 2^0. (st.b)
+   T	split 16 bit immediate, aligned 2^1. (st.s)
+   U	split 16 bit immediate, aligned 2^2. (st.l)
+   e    src1 floating point register.
+   f    src2 floating point register.
+   g    dest floating point register.  */
+
+
+/* The order of the opcodes in this table is significant. The assembler
+   requires that all instances of the same mnemonic must be consecutive.
+   If they aren't, the assembler will not function properly.
+ 
+   The order of opcodes does not affect the disassembler.  */
+
+static const struct i860_opcode i860_opcodes[] =
+{
+/* REG-Format Instructions.  */
+{ "ld.c",	0x30000000, 0xcc000000, "c,d", 0 },	/* ld.c csrc2,idest */
+{ "ld.b",	0x00000000, 0xfc000000, "1(2),d", 0 },	/* ld.b isrc1(isrc2),idest */
+{ "ld.b",	0x04000000, 0xf8000000, "I(2),d", E_ADDR },	/* ld.b #const(isrc2),idest */
+{ "ld.s",	0x10000000, 0xec000001, "1(2),d", 0 },	/* ld.s isrc1(isrc2),idest */
+{ "ld.s",	0x14000000, 0xe8000001, "J(2),d", E_ADDR },	/* ld.s #const(isrc2),idest */
+{ "ld.l",	0x10000001, 0xec000000, "1(2),d", 0 },	/* ld.l isrc1(isrc2),idest */
+{ "ld.l",	0x14000001, 0xe8000000, "K(2),d", E_ADDR },	/* ld.l #const(isrc2),idest */
+
+{ "st.c",	0x38000000, 0xc4000000, "1,c", 0 },	/* st.c isrc1ni,csrc2 */
+{ "st.b",	0x0c000000, 0xf0000000, "1,S(2)", E_ADDR },	/* st.b isrc1ni,#const(isrc2) */
+{ "st.s",	0x1c000000, 0xe0000001, "1,T(2)", E_ADDR },	/* st.s isrc1ni,#const(isrc2) */
+{ "st.l",	0x1c000001, 0xe0000000, "1,U(2)", E_ADDR },	/* st.l isrc1ni,#const(isrc2) */
+
+{ "ixfr",	0x08000000, 0xf4000000, "1,g", 0 },	/* ixfr isrc1ni,fdest */
+
+{ "fld.l",	0x20000002, 0xdc000001, "1(2),g", 0 },	/* fld.l isrc1(isrc2),fdest */
+{ "fld.l",	0x24000002, 0xd8000001, "K(2),g", E_ADDR },	/* fld.l #const(isrc2),fdest */
+{ "fld.l",	0x20000003, 0xdc000000, "1(2)++,g", 0 },	/* fld.l isrc1(isrc2)++,fdest */
+{ "fld.l",	0x24000003, 0xd8000000, "K(2)++,g", E_ADDR },	/* fld.l #const(isrc2)++,fdest */
+{ "fld.d",	0x20000000, 0xdc000007, "1(2),g", 0 },	/* fld.d isrc1(isrc2),fdest */
+{ "fld.d",	0x24000000, 0xd8000007, "L(2),g", E_ADDR },	/* fld.d #const(isrc2),fdest */
+{ "fld.d",	0x20000001, 0xdc000006, "1(2)++,g", 0 },	/* fld.d isrc1(isrc2)++,fdest */
+{ "fld.d",	0x24000001, 0xd8000006, "L(2)++,g", E_ADDR },	/* fld.d #const(isrc2)++,fdest */
+{ "fld.q",	0x20000004, 0xdc000003, "1(2),g", 0 },	/* fld.q isrc1(isrc2),fdest */
+{ "fld.q",	0x24000004, 0xd8000003, "M(2),g", E_ADDR },	/* fld.q #const(isrc2),fdest */
+{ "fld.q",	0x20000005, 0xdc000002, "1(2)++,g", 0 },	/* fld.q isrc1(isrc2)++,fdest */
+{ "fld.q",	0x24000005, 0xd8000002, "M(2)++,g", E_ADDR },	/* fld.q #const(isrc2)++,fdest */
+
+{ "pfld.l",	0x60000002, 0x9c000001, "1(2),g", 0 },	/* pfld.l isrc1(isrc2),fdest */
+{ "pfld.l",	0x64000002, 0x98000001, "K(2),g", E_ADDR },	/* pfld.l #const(isrc2),fdest */
+{ "pfld.l",	0x60000003, 0x9c000000, "1(2)++,g", 0 },	/* pfld.l isrc1(isrc2)++,fdest */
+{ "pfld.l",	0x64000003, 0x98000000, "K(2)++,g", E_ADDR },	/* pfld.l #const(isrc2)++,fdest */
+{ "pfld.d",	0x60000000, 0x9c000007, "1(2),g", 0 },	/* pfld.d isrc1(isrc2),fdest */
+{ "pfld.d",	0x64000000, 0x98000007, "L(2),g", E_ADDR },	/* pfld.d #const(isrc2),fdest */
+{ "pfld.d",	0x60000001, 0x9c000006, "1(2)++,g", 0 },	/* pfld.d isrc1(isrc2)++,fdest */
+{ "pfld.d",	0x64000001, 0x98000006, "L(2)++,g", E_ADDR },	/* pfld.d #const(isrc2)++,fdest */
+{ "pfld.q",	0x60000004, 0x9c000003, "1(2),g", XP_ONLY },	/* pfld.q isrc1(isrc2),fdest */
+{ "pfld.q",	0x64000004, 0x98000003, "L(2),g", XP_ONLY },	/* pfld.q #const(isrc2),fdest */
+{ "pfld.q",	0x60000005, 0x9c000002, "1(2)++,g", XP_ONLY },	/* pfld.q isrc1(isrc2)++,fdest */
+{ "pfld.q",	0x64000005, 0x98000002, "L(2)++,g", XP_ONLY },	/* pfld.q #const(isrc2)++,fdest */
+
+{ "fst.l",	0x28000002, 0xd4000001, "g,1(2)", 0 },	/* fst.l fdest,isrc1(isrc2) */
+{ "fst.l",	0x2c000002, 0xd0000001, "g,K(2)", E_ADDR },	/* fst.l fdest,#const(isrc2) */
+{ "fst.l",	0x28000003, 0xd4000000, "g,1(2)++", 0 },	/* fst.l fdest,isrc1(isrc2)++ */
+{ "fst.l",	0x2c000003, 0xd0000000, "g,K(2)++", E_ADDR },	/* fst.l fdest,#const(isrc2)++ */
+{ "fst.d",	0x28000000, 0xd4000007, "g,1(2)", 0 },	/* fst.d fdest,isrc1(isrc2) */
+{ "fst.d",	0x2c000000, 0xd0000007, "g,L(2)", E_ADDR },	/* fst.d fdest,#const(isrc2) */
+{ "fst.d",	0x28000001, 0xd4000006, "g,1(2)++", 0 },	/* fst.d fdest,isrc1(isrc2)++ */
+{ "fst.d",	0x2c000001, 0xd0000006, "g,L(2)++", E_ADDR },	/* fst.d fdest,#const(isrc2)++ */
+{ "fst.q",	0x28000004, 0xd4000003, "g,1(2)", 0 },	/* fst.d fdest,isrc1(isrc2) */
+{ "fst.q",	0x2c000004, 0xd0000003, "g,M(2)", E_ADDR },	/* fst.d fdest,#const(isrc2) */
+{ "fst.q",	0x28000005, 0xd4000002, "g,1(2)++", 0 },	/* fst.d fdest,isrc1(isrc2)++ */
+{ "fst.q",	0x2c000005, 0xd0000002, "g,M(2)++", E_ADDR },	/* fst.d fdest,#const(isrc2)++ */
+
+{ "pst.d",	0x3c000000, 0xc0000007, "g,L(2)", E_ADDR },	/* pst.d fdest,#const(isrc2) */
+{ "pst.d",	0x3c000001, 0xc0000006, "g,L(2)++", E_ADDR },	/* pst.d fdest,#const(isrc2)++ */
+
+{ "addu",	0x80000000, 0x7c000000, "1,2,d", 0 },	/* addu isrc1,isrc2,idest */
+{ "addu",	0x84000000, 0x78000000, "i,2,d", E_S32 },	/* addu #const,isrc2,idest */
+{ "adds",	0x90000000, 0x6c000000, "1,2,d", 0 },	/* adds isrc1,isrc2,idest */
+{ "adds",	0x94000000, 0x68000000, "i,2,d", E_S32 },	/* adds #const,isrc2,idest */
+{ "subu",	0x88000000, 0x74000000, "1,2,d", 0 },	/* subu isrc1,isrc2,idest */
+{ "subu",	0x8c000000, 0x70000000, "i,2,d", E_S32 },	/* subu #const,isrc2,idest */
+{ "subs",	0x98000000, 0x64000000, "1,2,d", 0 },	/* subs isrc1,isrc2,idest */
+{ "subs",	0x9c000000, 0x60000000, "i,2,d", E_S32 },	/* subs #const,isrc2,idest */
+
+{ "shl",	0xa0000000, 0x5c000000, "1,2,d", 0 },	/* shl isrc1,isrc2,idest */
+{ "shl",	0xa4000000, 0x58000000, "i,2,d", 0 },	/* shl #const,isrc2,idest */
+{ "shr",	0xa8000000, 0x54000000, "1,2,d", 0 },	/* shr isrc1,isrc2,idest */
+{ "shr",	0xac000000, 0x50000000, "i,2,d", 0 },	/* shr #const,isrc2,idest */
+{ "shrd",	0xb0000000, 0x4c000000, "1,2,d", 0 },	/* shrd isrc1,isrc2,idest */
+{ "shra",	0xb8000000, 0x44000000, "1,2,d", 0 },	/* shra isrc1,isrc2,idest */
+{ "shra",	0xbc000000, 0x40000000, "i,2,d", 0 },	/* shra #const,isrc2,idest */
+
+{ "mov",	0xa0000000, 0x5c00f800, "2,d", 0 },	/* shl r0,isrc2,idest */
+{ "mov",	0x94000000, 0x69e00000, "i,d", E_MOV },	/* adds #const,r0,idest */
+{ "nop",	0xa0000000, 0x5ffff800, "", 0 },	/* shl r0,r0,r0 */
+{ "fnop",	0xb0000000, 0x4ffff800, "", 0 },	/* shrd r0,r0,r0 */
+
+{ "trap",	0x44000000, 0xb8000000, "1,2,d", 0 },	/* trap isrc1ni,isrc2,idest */
+
+{ "flush",	0x34000004, 0xc81f0003, "L(2)", E_ADDR },	/* flush #const(isrc2) */
+{ "flush",	0x34000005, 0xc81f0002, "L(2)++", E_ADDR },	/* flush #const(isrc2)++ */
+
+{ "and",	0xc0000000, 0x3c000000, "1,2,d", 0 },	/* and isrc1,isrc2,idest */
+{ "and",	0xc4000000, 0x38000000, "i,2,d", E_AND },	/* and #const,isrc2,idest */
+{ "andh",	0xcc000000, 0x30000000, "i,2,d", 0 },	/* andh #const,isrc2,idest */
+{ "andnot",	0xd0000000, 0x2c000000, "1,2,d", 0 },	/* andnot isrc1,isrc2,idest */
+{ "andnot",	0xd4000000, 0x28000000, "i,2,d", E_U32 },	/* andnot #const,isrc2,idest */
+{ "andnoth",	0xdc000000, 0x20000000, "i,2,d", 0 },	/* andnoth #const,isrc2,idest */
+{ "or",		0xe0000000, 0x1c000000, "1,2,d", 0 },	/* or isrc1,isrc2,idest */
+{ "or",		0xe4000000, 0x18000000, "i,2,d", E_U32 },	/* or #const,isrc2,idest */
+{ "orh",	0xec000000, 0x10000000, "i,2,d", 0 },	/* orh #const,isrc2,idest */
+{ "xor",	0xf0000000, 0x0c000000, "1,2,d", 0 },	/* xor isrc1,isrc2,idest */
+{ "xor",	0xf4000000, 0x08000000, "i,2,d", E_U32 },	/* xor #const,isrc2,idest */
+{ "xorh",	0xfc000000, 0x00000000, "i,2,d", 0 },	/* xorh #const,isrc2,idest */
+
+{ "bte",	0x58000000, 0xa4000000, "1,2,r", 0 },	/* bte isrc1s,isrc2,sbroff */
+{ "bte",	0x5c000000, 0xa0000000, "5,2,r", 0 },	/* bte #const5,isrc2,sbroff */
+{ "btne",	0x50000000, 0xac000000, "1,2,r", 0 },	/* btne isrc1s,isrc2,sbroff */
+{ "btne",	0x54000000, 0xa8000000, "5,2,r", 0 },	/* btne #const5,isrc2,sbroff */
+{ "bla",	0xb4000000, 0x48000000, "1,2,r", E_DELAY },	/* bla isrc1s,isrc2,sbroff */
+{ "bri",	0x40000000, 0xbc000000, "1", E_DELAY },	/* bri isrc1ni */
+
+/* Core Escape Instruction Format */
+{ "lock",	0x4c000001, 0xb000001e, "", 0 },	/* lock set BL in dirbase */
+{ "calli",	0x4c000002, 0xb000001d, "1", E_DELAY },	/* calli isrc1ni */
+{ "intovr",	0x4c000004, 0xb000001b, "", 0 },	/* intovr trap on integer overflow */
+{ "unlock",	0x4c000007, 0xb0000018, "", 0 },	/* unlock clear BL in dirbase */
+{ "ldio.l",	0x4c000408, 0xb00003f7, "2,d", XP_ONLY },	/* ldio.l isrc2,idest */
+{ "ldio.s",	0x4c000208, 0xb00005f7, "2,d", XP_ONLY },	/* ldio.s isrc2,idest */
+{ "ldio.b",	0x4c000008, 0xb00007f7, "2,d", XP_ONLY },	/* ldio.b isrc2,idest */
+{ "stio.l",	0x4c000409, 0xb00003f6, "1,2", XP_ONLY },	/* stio.l isrc1ni,isrc2 */
+{ "stio.s",	0x4c000209, 0xb00005f6, "1,2", XP_ONLY },	/* stio.s isrc1ni,isrc2 */
+{ "stio.b",	0x4c000009, 0xb00007f6, "1,2", XP_ONLY },	/* stio.b isrc1ni,isrc2 */
+{ "ldint.l",	0x4c00040a, 0xb00003f5, "2,d", XP_ONLY },	/* ldint.l isrc2,idest */
+{ "ldint.s",	0x4c00020a, 0xb00005f5, "2,d", XP_ONLY },	/* ldint.s isrc2,idest */
+{ "ldint.b",	0x4c00000a, 0xb00007f5, "2,d", XP_ONLY },	/* ldint.b isrc2,idest */
+{ "scyc.b",	0x4c00000b, 0xb00007f4, "2", XP_ONLY },		/* scyc.b isrc2 */
+
+/* CTRL-Format Instructions */
+{ "br",		0x68000000, 0x94000000, "l", E_DELAY },	/* br lbroff */
+{ "call",	0x6c000000, 0x90000000, "l", E_DELAY },	/* call lbroff */
+{ "bc",		0x70000000, 0x8c000000, "l", 0 },	/* bc lbroff */
+{ "bc.t",	0x74000000, 0x88000000, "l", E_DELAY },	/* bc.t lbroff */
+{ "bnc",	0x78000000, 0x84000000, "l", 0 },	/* bnc lbroff */
+{ "bnc.t",	0x7c000000, 0x80000000, "l", E_DELAY },	/* bnc.t lbroff */
+
+/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest.  */
+{ "r2p1.ss",	0x48000400, 0xb40001ff, "e,f,g", 0 },
+{ "r2p1.sd",	0x48000480, 0xb400017f, "e,f,g", 0 },
+{ "r2p1.dd",	0x48000580, 0xb400007f, "e,f,g", 0 },
+{ "r2pt.ss",	0x48000401, 0xb40001fe, "e,f,g", 0 },
+{ "r2pt.sd",	0x48000481, 0xb400017e, "e,f,g", 0 },
+{ "r2pt.dd",	0x48000581, 0xb400007e, "e,f,g", 0 },
+{ "r2ap1.ss",	0x48000402, 0xb40001fd, "e,f,g", 0 },
+{ "r2ap1.sd",	0x48000482, 0xb400017d, "e,f,g", 0 },
+{ "r2ap1.dd",	0x48000582, 0xb400007d, "e,f,g", 0 },
+{ "r2apt.ss",	0x48000403, 0xb40001fc, "e,f,g", 0 },
+{ "r2apt.sd",	0x48000483, 0xb400017c, "e,f,g", 0 },
+{ "r2apt.dd",	0x48000583, 0xb400007c, "e,f,g", 0 },
+{ "i2p1.ss",	0x48000404, 0xb40001fb, "e,f,g", 0 },
+{ "i2p1.sd",	0x48000484, 0xb400017b, "e,f,g", 0 },
+{ "i2p1.dd",	0x48000584, 0xb400007b, "e,f,g", 0 },
+{ "i2pt.ss",	0x48000405, 0xb40001fa, "e,f,g", 0 },
+{ "i2pt.sd",	0x48000485, 0xb400017a, "e,f,g", 0 },
+{ "i2pt.dd",	0x48000585, 0xb400007a, "e,f,g", 0 },
+{ "i2ap1.ss",	0x48000406, 0xb40001f9, "e,f,g", 0 },
+{ "i2ap1.sd",	0x48000486, 0xb4000179, "e,f,g", 0 },
+{ "i2ap1.dd",	0x48000586, 0xb4000079, "e,f,g", 0 },
+{ "i2apt.ss",	0x48000407, 0xb40001f8, "e,f,g", 0 },
+{ "i2apt.sd",	0x48000487, 0xb4000178, "e,f,g", 0 },
+{ "i2apt.dd",	0x48000587, 0xb4000078, "e,f,g", 0 },
+{ "rat1p2.ss",	0x48000408, 0xb40001f7, "e,f,g", 0 },
+{ "rat1p2.sd",	0x48000488, 0xb4000177, "e,f,g", 0 },
+{ "rat1p2.dd",	0x48000588, 0xb4000077, "e,f,g", 0 },
+{ "m12apm.ss",	0x48000409, 0xb40001f6, "e,f,g", 0 },
+{ "m12apm.sd",	0x48000489, 0xb4000176, "e,f,g", 0 },
+{ "m12apm.dd",	0x48000589, 0xb4000076, "e,f,g", 0 },
+{ "ra1p2.ss",	0x4800040a, 0xb40001f5, "e,f,g", 0 },
+{ "ra1p2.sd",	0x4800048a, 0xb4000175, "e,f,g", 0 },
+{ "ra1p2.dd",	0x4800058a, 0xb4000075, "e,f,g", 0 },
+{ "m12ttpa.ss",	0x4800040b, 0xb40001f4, "e,f,g", 0 },
+{ "m12ttpa.sd",	0x4800048b, 0xb4000174, "e,f,g", 0 },
+{ "m12ttpa.dd",	0x4800058b, 0xb4000074, "e,f,g", 0 },
+{ "iat1p2.ss",	0x4800040c, 0xb40001f3, "e,f,g", 0 },
+{ "iat1p2.sd",	0x4800048c, 0xb4000173, "e,f,g", 0 },
+{ "iat1p2.dd",	0x4800058c, 0xb4000073, "e,f,g", 0 },
+{ "m12tpm.ss",	0x4800040d, 0xb40001f2, "e,f,g", 0 },
+{ "m12tpm.sd",	0x4800048d, 0xb4000172, "e,f,g", 0 },
+{ "m12tpm.dd",	0x4800058d, 0xb4000072, "e,f,g", 0 },
+{ "ia1p2.ss",	0x4800040e, 0xb40001f1, "e,f,g", 0 },
+{ "ia1p2.sd",	0x4800048e, 0xb4000171, "e,f,g", 0 },
+{ "ia1p2.dd",	0x4800058e, 0xb4000071, "e,f,g", 0 },
+{ "m12tpa.ss",	0x4800040f, 0xb40001f0, "e,f,g", 0 },
+{ "m12tpa.sd",	0x4800048f, 0xb4000170, "e,f,g", 0 },
+{ "m12tpa.dd",	0x4800058f, 0xb4000070, "e,f,g", 0 },
+
+/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest.  */
+{ "r2s1.ss",	0x48000410, 0xb40001ef, "e,f,g", 0 },
+{ "r2s1.sd",	0x48000490, 0xb400016f, "e,f,g", 0 },
+{ "r2s1.dd",	0x48000590, 0xb400006f, "e,f,g", 0 },
+{ "r2st.ss",	0x48000411, 0xb40001ee, "e,f,g", 0 },
+{ "r2st.sd",	0x48000491, 0xb400016e, "e,f,g", 0 },
+{ "r2st.dd",	0x48000591, 0xb400006e, "e,f,g", 0 },
+{ "r2as1.ss",	0x48000412, 0xb40001ed, "e,f,g", 0 },
+{ "r2as1.sd",	0x48000492, 0xb400016d, "e,f,g", 0 },
+{ "r2as1.dd",	0x48000592, 0xb400006d, "e,f,g", 0 },
+{ "r2ast.ss",	0x48000413, 0xb40001ec, "e,f,g", 0 },
+{ "r2ast.sd",	0x48000493, 0xb400016c, "e,f,g", 0 },
+{ "r2ast.dd",	0x48000593, 0xb400006c, "e,f,g", 0 },
+{ "i2s1.ss",	0x48000414, 0xb40001eb, "e,f,g", 0 },
+{ "i2s1.sd",	0x48000494, 0xb400016b, "e,f,g", 0 },
+{ "i2s1.dd",	0x48000594, 0xb400006b, "e,f,g", 0 },
+{ "i2st.ss",	0x48000415, 0xb40001ea, "e,f,g", 0 },
+{ "i2st.sd",	0x48000495, 0xb400016a, "e,f,g", 0 },
+{ "i2st.dd",	0x48000595, 0xb400006a, "e,f,g", 0 },
+{ "i2as1.ss",	0x48000416, 0xb40001e9, "e,f,g", 0 },
+{ "i2as1.sd",	0x48000496, 0xb4000169, "e,f,g", 0 },
+{ "i2as1.dd",	0x48000596, 0xb4000069, "e,f,g", 0 },
+{ "i2ast.ss",	0x48000417, 0xb40001e8, "e,f,g", 0 },
+{ "i2ast.sd",	0x48000497, 0xb4000168, "e,f,g", 0 },
+{ "i2ast.dd",	0x48000597, 0xb4000068, "e,f,g", 0 },
+{ "rat1s2.ss",	0x48000418, 0xb40001e7, "e,f,g", 0 },
+{ "rat1s2.sd",	0x48000498, 0xb4000167, "e,f,g", 0 },
+{ "rat1s2.dd",	0x48000598, 0xb4000067, "e,f,g", 0 },
+{ "m12asm.ss",	0x48000419, 0xb40001e6, "e,f,g", 0 },
+{ "m12asm.sd",	0x48000499, 0xb4000166, "e,f,g", 0 },
+{ "m12asm.dd",	0x48000599, 0xb4000066, "e,f,g", 0 },
+{ "ra1s2.ss",	0x4800041a, 0xb40001e5, "e,f,g", 0 },
+{ "ra1s2.sd",	0x4800049a, 0xb4000165, "e,f,g", 0 },
+{ "ra1s2.dd",	0x4800059a, 0xb4000065, "e,f,g", 0 },
+{ "m12ttsa.ss",	0x4800041b, 0xb40001e4, "e,f,g", 0 },
+{ "m12ttsa.sd",	0x4800049b, 0xb4000164, "e,f,g", 0 },
+{ "m12ttsa.dd",	0x4800059b, 0xb4000064, "e,f,g", 0 },
+{ "iat1s2.ss",	0x4800041c, 0xb40001e3, "e,f,g", 0 },
+{ "iat1s2.sd",	0x4800049c, 0xb4000163, "e,f,g", 0 },
+{ "iat1s2.dd",	0x4800059c, 0xb4000063, "e,f,g", 0 },
+{ "m12tsm.ss",	0x4800041d, 0xb40001e2, "e,f,g", 0 },
+{ "m12tsm.sd",	0x4800049d, 0xb4000162, "e,f,g", 0 },
+{ "m12tsm.dd",	0x4800059d, 0xb4000062, "e,f,g", 0 },
+{ "ia1s2.ss",	0x4800041e, 0xb40001e1, "e,f,g", 0 },
+{ "ia1s2.sd",	0x4800049e, 0xb4000161, "e,f,g", 0 },
+{ "ia1s2.dd",	0x4800059e, 0xb4000061, "e,f,g", 0 },
+{ "m12tsa.ss",	0x4800041f, 0xb40001e0, "e,f,g", 0 },
+{ "m12tsa.sd",	0x4800049f, 0xb4000160, "e,f,g", 0 },
+{ "m12tsa.dd",	0x4800059f, 0xb4000060, "e,f,g", 0 },
+
+/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest.  */
+{ "mr2p1.ss",	0x48000000, 0xb40005ff, "e,f,g", 0 },
+{ "mr2p1.sd",	0x48000080, 0xb400057f, "e,f,g", 0 },
+{ "mr2p1.dd",	0x48000180, 0xb400047f, "e,f,g", 0 },
+{ "mr2pt.ss",	0x48000001, 0xb40005fe, "e,f,g", 0 },
+{ "mr2pt.sd",	0x48000081, 0xb400057e, "e,f,g", 0 },
+{ "mr2pt.dd",	0x48000181, 0xb400047e, "e,f,g", 0 },
+{ "mr2mp1.ss",	0x48000002, 0xb40005fd, "e,f,g", 0 },
+{ "mr2mp1.sd",	0x48000082, 0xb400057d, "e,f,g", 0 },
+{ "mr2mp1.dd",	0x48000182, 0xb400047d, "e,f,g", 0 },
+{ "mr2mpt.ss",	0x48000003, 0xb40005fc, "e,f,g", 0 },
+{ "mr2mpt.sd",	0x48000083, 0xb400057c, "e,f,g", 0 },
+{ "mr2mpt.dd",	0x48000183, 0xb400047c, "e,f,g", 0 },
+{ "mi2p1.ss",	0x48000004, 0xb40005fb, "e,f,g", 0 },
+{ "mi2p1.sd",	0x48000084, 0xb400057b, "e,f,g", 0 },
+{ "mi2p1.dd",	0x48000184, 0xb400047b, "e,f,g", 0 },
+{ "mi2pt.ss",	0x48000005, 0xb40005fa, "e,f,g", 0 },
+{ "mi2pt.sd",	0x48000085, 0xb400057a, "e,f,g", 0 },
+{ "mi2pt.dd",	0x48000185, 0xb400047a, "e,f,g", 0 },
+{ "mi2mp1.ss",	0x48000006, 0xb40005f9, "e,f,g", 0 },
+{ "mi2mp1.sd",	0x48000086, 0xb4000579, "e,f,g", 0 },
+{ "mi2mp1.dd",	0x48000186, 0xb4000479, "e,f,g", 0 },
+{ "mi2mpt.ss",	0x48000007, 0xb40005f8, "e,f,g", 0 },
+{ "mi2mpt.sd",	0x48000087, 0xb4000578, "e,f,g", 0 },
+{ "mi2mpt.dd",	0x48000187, 0xb4000478, "e,f,g", 0 },
+{ "mrmt1p2.ss",	0x48000008, 0xb40005f7, "e,f,g", 0 },
+{ "mrmt1p2.sd",	0x48000088, 0xb4000577, "e,f,g", 0 },
+{ "mrmt1p2.dd",	0x48000188, 0xb4000477, "e,f,g", 0 },
+{ "mm12mpm.ss",	0x48000009, 0xb40005f6, "e,f,g", 0 },
+{ "mm12mpm.sd",	0x48000089, 0xb4000576, "e,f,g", 0 },
+{ "mm12mpm.dd",	0x48000189, 0xb4000476, "e,f,g", 0 },
+{ "mrm1p2.ss",	0x4800000a, 0xb40005f5, "e,f,g", 0 },
+{ "mrm1p2.sd",	0x4800008a, 0xb4000575, "e,f,g", 0 },
+{ "mrm1p2.dd",	0x4800018a, 0xb4000475, "e,f,g", 0 },
+{ "mm12ttpm.ss",0x4800000b, 0xb40005f4, "e,f,g", 0 },
+{ "mm12ttpm.sd",0x4800008b, 0xb4000574, "e,f,g", 0 },
+{ "mm12ttpm.dd",0x4800018b, 0xb4000474, "e,f,g", 0 },
+{ "mimt1p2.ss",	0x4800000c, 0xb40005f3, "e,f,g", 0 },
+{ "mimt1p2.sd",	0x4800008c, 0xb4000573, "e,f,g", 0 },
+{ "mimt1p2.dd",	0x4800018c, 0xb4000473, "e,f,g", 0 },
+{ "mm12tpm.ss",	0x4800000d, 0xb40005f2, "e,f,g", 0 },
+{ "mm12tpm.sd",	0x4800008d, 0xb4000572, "e,f,g", 0 },
+{ "mm12tpm.dd",	0x4800018d, 0xb4000472, "e,f,g", 0 },
+{ "mim1p2.ss",	0x4800000e, 0xb40005f1, "e,f,g", 0 },
+{ "mim1p2.sd",	0x4800008e, 0xb4000571, "e,f,g", 0 },
+{ "mim1p2.dd",	0x4800018e, 0xb4000471, "e,f,g", 0 },
+
+/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest.  */
+{ "mr2s1.ss",	0x48000010, 0xb40005ef, "e,f,g", 0 },
+{ "mr2s1.sd",	0x48000090, 0xb400056f, "e,f,g", 0 },
+{ "mr2s1.dd",	0x48000190, 0xb400046f, "e,f,g", 0 },
+{ "mr2st.ss",	0x48000011, 0xb40005ee, "e,f,g", 0 },
+{ "mr2st.sd",	0x48000091, 0xb400056e, "e,f,g", 0 },
+{ "mr2st.dd",	0x48000191, 0xb400046e, "e,f,g", 0 },
+{ "mr2ms1.ss",	0x48000012, 0xb40005ed, "e,f,g", 0 },
+{ "mr2ms1.sd",	0x48000092, 0xb400056d, "e,f,g", 0 },
+{ "mr2ms1.dd",	0x48000192, 0xb400046d, "e,f,g", 0 },
+{ "mr2mst.ss",	0x48000013, 0xb40005ec, "e,f,g", 0 },
+{ "mr2mst.sd",	0x48000093, 0xb400056c, "e,f,g", 0 },
+{ "mr2mst.dd",	0x48000193, 0xb400046c, "e,f,g", 0 },
+{ "mi2s1.ss",	0x48000014, 0xb40005eb, "e,f,g", 0 },
+{ "mi2s1.sd",	0x48000094, 0xb400056b, "e,f,g", 0 },
+{ "mi2s1.dd",	0x48000194, 0xb400046b, "e,f,g", 0 },
+{ "mi2st.ss",	0x48000015, 0xb40005ea, "e,f,g", 0 },
+{ "mi2st.sd",	0x48000095, 0xb400056a, "e,f,g", 0 },
+{ "mi2st.dd",	0x48000195, 0xb400046a, "e,f,g", 0 },
+{ "mi2ms1.ss",	0x48000016, 0xb40005e9, "e,f,g", 0 },
+{ "mi2ms1.sd",	0x48000096, 0xb4000569, "e,f,g", 0 },
+{ "mi2ms1.dd",	0x48000196, 0xb4000469, "e,f,g", 0 },
+{ "mi2mst.ss",	0x48000017, 0xb40005e8, "e,f,g", 0 },
+{ "mi2mst.sd",	0x48000097, 0xb4000568, "e,f,g", 0 },
+{ "mi2mst.dd",	0x48000197, 0xb4000468, "e,f,g", 0 },
+{ "mrmt1s2.ss",	0x48000018, 0xb40005e7, "e,f,g", 0 },
+{ "mrmt1s2.sd",	0x48000098, 0xb4000567, "e,f,g", 0 },
+{ "mrmt1s2.dd",	0x48000198, 0xb4000467, "e,f,g", 0 },
+{ "mm12msm.ss",	0x48000019, 0xb40005e6, "e,f,g", 0 },
+{ "mm12msm.sd",	0x48000099, 0xb4000566, "e,f,g", 0 },
+{ "mm12msm.dd",	0x48000199, 0xb4000466, "e,f,g", 0 },
+{ "mrm1s2.ss",	0x4800001a, 0xb40005e5, "e,f,g", 0 },
+{ "mrm1s2.sd",	0x4800009a, 0xb4000565, "e,f,g", 0 },
+{ "mrm1s2.dd",	0x4800019a, 0xb4000465, "e,f,g", 0 },
+{ "mm12ttsm.ss",0x4800001b, 0xb40005e4, "e,f,g", 0 },
+{ "mm12ttsm.sd",0x4800009b, 0xb4000564, "e,f,g", 0 },
+{ "mm12ttsm.dd",0x4800019b, 0xb4000464, "e,f,g", 0 },
+{ "mimt1s2.ss",	0x4800001c, 0xb40005e3, "e,f,g", 0 },
+{ "mimt1s2.sd",	0x4800009c, 0xb4000563, "e,f,g", 0 },
+{ "mimt1s2.dd",	0x4800019c, 0xb4000463, "e,f,g", 0 },
+{ "mm12tsm.ss",	0x4800001d, 0xb40005e2, "e,f,g", 0 },
+{ "mm12tsm.sd",	0x4800009d, 0xb4000562, "e,f,g", 0 },
+{ "mm12tsm.dd",	0x4800019d, 0xb4000462, "e,f,g", 0 },
+{ "mim1s2.ss",	0x4800001e, 0xb40005e1, "e,f,g", 0 },
+{ "mim1s2.sd",	0x4800009e, 0xb4000561, "e,f,g", 0 },
+{ "mim1s2.dd",	0x4800019e, 0xb4000461, "e,f,g", 0 },
+
+{ "fmul.ss",	0x48000020, 0xb40005df, "e,f,g", 0 },	/* fmul.p fsrc1,fsrc2,fdest */
+{ "fmul.sd",	0x480000a0, 0xb400055f, "e,f,g", 0 },	/* fmul.p fsrc1,fsrc2,fdest */
+{ "fmul.dd",	0x480001a0, 0xb400045f, "e,f,g", 0 },	/* fmul.p fsrc1,fsrc2,fdest */
+{ "pfmul.ss",	0x48000420, 0xb40001df, "e,f,g", 0 },	/* pfmul.p fsrc1,fsrc2,fdest */
+{ "pfmul.sd",	0x480004a0, 0xb400015f, "e,f,g", 0 },	/* pfmul.p fsrc1,fsrc2,fdest */
+{ "pfmul.dd",	0x480005a0, 0xb400005f, "e,f,g", 0 },	/* pfmul.p fsrc1,fsrc2,fdest */
+{ "pfmul3.dd",	0x480005a4, 0xb400005b, "e,f,g", 0 },	/* pfmul3.p fsrc1,fsrc2,fdest */
+{ "fmlow.dd",	0x480001a1, 0xb400045e, "e,f,g", 0 },	/* fmlow.dd fsrc1,fsrc2,fdest */
+{ "frcp.ss",	0x48000022, 0xb40005dd, "f,g", 0 },	/* frcp.p fsrc2,fdest */
+{ "frcp.sd",	0x480000a2, 0xb400055d, "f,g", 0 },	/* frcp.p fsrc2,fdest */
+{ "frcp.dd",	0x480001a2, 0xb400045d, "f,g", 0 },	/* frcp.p fsrc2,fdest */
+{ "frsqr.ss",	0x48000023, 0xb40005dc, "f,g", 0 },	/* frsqr.p fsrc2,fdest */
+{ "frsqr.sd",	0x480000a3, 0xb400055c, "f,g", 0 },	/* frsqr.p fsrc2,fdest */
+{ "frsqr.dd",	0x480001a3, 0xb400045c, "f,g", 0 },	/* frsqr.p fsrc2,fdest */
+{ "fadd.ss",	0x48000030, 0xb40005cf, "e,f,g", 0 },	/* fadd.p fsrc1,fsrc2,fdest */
+{ "fadd.sd",	0x480000b0, 0xb400054f, "e,f,g", 0 },	/* fadd.p fsrc1,fsrc2,fdest */
+{ "fadd.dd",	0x480001b0, 0xb400044f, "e,f,g", 0 },	/* fadd.p fsrc1,fsrc2,fdest */
+{ "pfadd.ss",	0x48000430, 0xb40001cf, "e,f,g", 0 },	/* pfadd.p fsrc1,fsrc2,fdest */
+{ "pfadd.sd",	0x480004b0, 0xb400014f, "e,f,g", 0 },	/* pfadd.p fsrc1,fsrc2,fdest */
+{ "pfadd.dd",	0x480005b0, 0xb400004f, "e,f,g", 0 },	/* pfadd.p fsrc1,fsrc2,fdest */
+{ "fsub.ss",	0x48000031, 0xb40005ce, "e,f,g", 0 },	/* fsub.p fsrc1,fsrc2,fdest */
+{ "fsub.sd",	0x480000b1, 0xb400054e, "e,f,g", 0 },	/* fsub.p fsrc1,fsrc2,fdest */
+{ "fsub.dd",	0x480001b1, 0xb400044e, "e,f,g", 0 },	/* fsub.p fsrc1,fsrc2,fdest */
+{ "pfsub.ss",	0x48000431, 0xb40001ce, "e,f,g", 0 },	/* pfsub.p fsrc1,fsrc2,fdest */
+{ "pfsub.sd",	0x480004b1, 0xb400014e, "e,f,g", 0 },	/* pfsub.p fsrc1,fsrc2,fdest */
+{ "pfsub.dd",	0x480005b1, 0xb400004e, "e,f,g", 0 },	/* pfsub.p fsrc1,fsrc2,fdest */
+{ "fix.sd",	0x480000b2, 0xb400054d, "e,g", 0 },	/* fix.p fsrc1,fdest */
+{ "fix.dd",	0x480001b2, 0xb400044d, "e,g", 0 },	/* fix.p fsrc1,fdest */
+{ "pfix.sd",	0x480004b2, 0xb400014d, "e,g", 0 },	/* pfix.p fsrc1,fdest */
+{ "pfix.dd",	0x480005b2, 0xb400004d, "e,g", 0 },	/* pfix.p fsrc1,fdest */
+{ "famov.ss",	0x48000033, 0xb40005cc, "e,g", 0 },	/* famov.p fsrc1,fdest */
+{ "famov.ds",	0x48000133, 0xb40004cc, "e,g", 0 },	/* famov.p fsrc1,fdest */
+{ "famov.sd",	0x480000b3, 0xb400054c, "e,g", 0 },	/* famov.p fsrc1,fdest */
+{ "famov.dd",	0x480001b3, 0xb400044c, "e,g", 0 },	/* famov.p fsrc1,fdest */
+{ "pfamov.ss",	0x48000433, 0xb40001cc, "e,g", 0 },	/* pfamov.p fsrc1,fdest */
+{ "pfamov.ds",	0x48000533, 0xb40000cc, "e,g", 0 },	/* pfamov.p fsrc1,fdest */
+{ "pfamov.sd",	0x480004b3, 0xb400014c, "e,g", 0 },	/* pfamov.p fsrc1,fdest */
+{ "pfamov.dd",	0x480005b3, 0xb400004c, "e,g", 0 },	/* pfamov.p fsrc1,fdest */
+/* Opcode pfgt has R bit cleared; pfle has R bit set.  */
+{ "pfgt.ss",	0x48000434, 0xb40001cb, "e,f,g", 0 },	/* pfgt.p fsrc1,fsrc2,fdest */
+{ "pfgt.dd",	0x48000534, 0xb40000cb, "e,f,g", 0 },	/* pfgt.p fsrc1,fsrc2,fdest */
+/* Opcode pfgt has R bit cleared; pfle has R bit set.  */
+{ "pfle.ss",	0x480004b4, 0xb400014b, "e,f,g", 0 },	/* pfle.p fsrc1,fsrc2,fdest */
+{ "pfle.dd",	0x480005b4, 0xb400004b, "e,f,g", 0 },	/* pfle.p fsrc1,fsrc2,fdest */
+{ "pfeq.ss",	0x48000435, 0xb40001ca, "e,f,g", 0 },	/* pfeq.p fsrc1,fsrc2,fdest */
+{ "pfeq.dd",	0x48000535, 0xb40000ca, "e,f,g", 0 },	/* pfeq.p fsrc1,fsrc2,fdest */
+{ "ftrunc.sd",	0x480000ba, 0xb4000545, "e,g", 0 },	/* ftrunc.p fsrc1,fdest */
+{ "ftrunc.dd",	0x480001ba, 0xb4000445, "e,g", 0 },	/* ftrunc.p fsrc1,fdest */
+{ "pftrunc.sd",	0x480004ba, 0xb4000145, "e,g", 0 },	/* pftrunc.p fsrc1,fdest */
+{ "pftrunc.dd",	0x480005ba, 0xb4000045, "e,g", 0 },	/* pftrunc.p fsrc1,fdest */
+{ "fxfr",	0x48000040, 0xb40005bf, "e,d", 0 },	/* fxfr fsrc1,idest */
+{ "fiadd.ss",	0x48000049, 0xb40005b6, "e,f,g", 0 },	/* fiadd.w fsrc1,fsrc2,fdest */
+{ "fiadd.dd",	0x480001c9, 0xb4000436, "e,f,g", 0 },	/* fiadd.w fsrc1,fsrc2,fdest */
+{ "pfiadd.ss",	0x48000449, 0xb40001b6, "e,f,g", 0 },	/* pfiadd.w fsrc1,fsrc2,fdest */
+{ "pfiadd.dd",	0x480005c9, 0xb4000036, "e,f,g", 0 },	/* pfiadd.w fsrc1,fsrc2,fdest */
+{ "fisub.ss",	0x4800004d, 0xb40005b2, "e,f,g", 0 },	/* fisub.w fsrc1,fsrc2,fdest */
+{ "fisub.dd",	0x480001cd, 0xb4000432, "e,f,g", 0 },	/* fisub.w fsrc1,fsrc2,fdest */
+{ "pfisub.ss",	0x4800044d, 0xb40001b2, "e,f,g", 0 },	/* pfisub.w fsrc1,fsrc2,fdest */
+{ "pfisub.dd",	0x480005cd, 0xb4000032, "e,f,g", 0 },	/* pfisub.w fsrc1,fsrc2,fdest */
+{ "fzchkl",	0x480001d7, 0xb4000428, "e,f,g", 0 },	/* fzchkl fsrc1,fsrc2,fdest */
+{ "pfzchkl",	0x480005d7, 0xb4000028, "e,f,g", 0 },	/* pfzchkl fsrc1,fsrc2,fdest */
+{ "fzchks",	0x480001df, 0xb4000420, "e,f,g", 0 },	/* fzchks fsrc1,fsrc2,fdest */
+{ "pfzchks",	0x480005df, 0xb4000020, "e,f,g", 0 },	/* pfzchks fsrc1,fsrc2,fdest */
+{ "faddp",	0x480001d0, 0xb400042f, "e,f,g", 0 },	/* faddp fsrc1,fsrc2,fdest */
+{ "pfaddp",	0x480005d0, 0xb400002f, "e,f,g", 0 },	/* pfaddp fsrc1,fsrc2,fdest */
+{ "faddz",	0x480001d1, 0xb400042e, "e,f,g", 0 },	/* faddz fsrc1,fsrc2,fdest */
+{ "pfaddz",	0x480005d1, 0xb400002e, "e,f,g", 0 },	/* pfaddz fsrc1,fsrc2,fdest */
+{ "form",	0x480001da, 0xb4000425, "e,g", 0 },	/* form fsrc1,fdest */
+{ "pform",	0x480005da, 0xb4000025, "e,g", 0 },	/* pform fsrc1,fdest */
+
+/* Floating point pseudo-instructions.  */
+{ "fmov.ss",	0x48000049, 0xb7e005b6, "e,g", 0 },	/* fiadd.ss fsrc1,f0,fdest */
+{ "fmov.dd",	0x480001c9, 0xb7e00436, "e,g", 0 },	/* fiadd.dd fsrc1,f0,fdest */
+{ "fmov.sd",	0x480000b3, 0xb400054c, "e,g", 0 },	/* famov.sd fsrc1,fdest */
+{ "fmov.ds",	0x48000133, 0xb40004cc, "e,g", 0 },	/* famov.ds fsrc1,fdest */
+{ "pfmov.ds",	0x48000533, 0xb40000cc, "e,g", 0 },	/* pfamov.ds fsrc1,fdest */
+{ "pfmov.dd",	0x480005c9, 0xb7e00036, "e,g", 0 },	/* pfiadd.dd fsrc1,f0,fdest */
+{ 0, 0, 0, 0, 0 },
+
+};
+
+#define NUMOPCODES ((sizeof i860_opcodes)/(sizeof i860_opcodes[0]))
+
+
diff --git a/binutils-2.25/include/opcode/i960.h b/binutils-2.25/include/opcode/i960.h
new file mode 100644
index 00000000..7b8e1f5d
--- /dev/null
+++ b/binutils-2.25/include/opcode/i960.h
@@ -0,0 +1,525 @@
+/* Basic 80960 instruction formats.
+
+   Copyright 2001-2013 Free Software Foundation, Inc.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+ 
+/* The 'COJ' instructions are actually COBR instructions with the 'b' in
+   the mnemonic replaced by a 'j';  they are ALWAYS "de-optimized" if
+   necessary: if the displacement will not fit in 13 bits, the assembler will
+   replace them with the corresponding compare and branch instructions.
+ 
+   All of the 'MEMn' instructions are the same format; the 'n' in the name
+   indicates the default index scale factor (the size of the datum operated on).
+ 
+   The FBRA formats are not actually an instruction format.  They are the
+   "convenience directives" for branching on floating-point comparisons,
+   each of which generates 2 instructions (a 'bno' and one other branch).
+ 
+   The CALLJ format is not actually an instruction format.  It indicates that
+   the instruction generated (a CTRL-format 'call') should have its relocation
+   specially flagged for link-time replacement with a 'bal' or 'calls' if
+   appropriate.  */ 
+
+#define CTRL	0
+#define COBR	1
+#define COJ	2
+#define REG	3
+#define MEM1	4
+#define MEM2	5
+#define MEM4	6
+#define MEM8	7
+#define MEM12	8
+#define MEM16	9
+#define FBRA	10
+#define CALLJ	11
+
+/* Masks for the mode bits in REG format instructions */
+#define M1		0x0800
+#define M2		0x1000
+#define M3		0x2000
+
+/* Generate the 12-bit opcode for a REG format instruction by placing the 
+ * high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits
+ * 7-10.
+ */
+
+#define REG_OPC(opc)	((opc & 0xff0) << 20) | ((opc & 0xf) << 7)
+
+/* Generate a template for a REG format instruction:  place the opcode bits
+ * in the appropriate fields and OR in mode bits for the operands that will not
+ * be used.  I.e.,
+ *		set m1=1, if src1 will not be used
+ *		set m2=1, if src2 will not be used
+ *		set m3=1, if dst  will not be used
+ *
+ * Setting the "unused" mode bits to 1 speeds up instruction execution(!).
+ * The information is also useful to us because some 1-operand REG instructions
+ * use the src1 field, others the dst field; and some 2-operand REG instructions
+ * use src1/src2, others src1/dst.  The set mode bits enable us to distinguish.
+ */
+#define R_0(opc)	( REG_OPC(opc) | M1 | M2 | M3 )	/* No operands      */
+#define R_1(opc)	( REG_OPC(opc) | M2 | M3 )	/* 1 operand: src1  */
+#define R_1D(opc)	( REG_OPC(opc) | M1 | M2 )	/* 1 operand: dst   */
+#define R_2(opc)	( REG_OPC(opc) | M3 )		/* 2 ops: src1/src2 */
+#define R_2D(opc)	( REG_OPC(opc) | M2 )		/* 2 ops: src1/dst  */
+#define R_3(opc)	( REG_OPC(opc) )		/* 3 operands       */
+
+/* DESCRIPTOR BYTES FOR REGISTER OPERANDS
+ *
+ * Interpret names as follows:
+ *	R:   global or local register only
+ *	RS:  global, local, or (if target allows) special-function register only
+ *	RL:  global or local register, or integer literal
+ *	RSL: global, local, or (if target allows) special-function register;
+ *		or integer literal
+ *	F:   global, local, or floating-point register
+ *	FL:  global, local, or floating-point register; or literal (including
+ *		floating point)
+ *
+ * A number appended to a name indicates that registers must be aligned,
+ * as follows:
+ *	2: register number must be multiple of 2
+ *	4: register number must be multiple of 4
+ */
+
+#define SFR	0x10		/* Mask for the "sfr-OK" bit */
+#define LIT	0x08		/* Mask for the "literal-OK" bit */
+#define FP	0x04		/* Mask for "floating-point-OK" bit */
+
+/* This macro ors the bits together.  Note that 'align' is a mask
+ * for the low 0, 1, or 2 bits of the register number, as appropriate.
+ */
+#define OP(align,lit,fp,sfr)	( align | lit | fp | sfr )
+
+#define R	OP( 0, 0,   0,  0   )
+#define RS	OP( 0, 0,   0,  SFR )
+#define RL	OP( 0, LIT, 0,  0   )
+#define RSL	OP( 0, LIT, 0,  SFR )
+#define F	OP( 0, 0,   FP, 0   )
+#define FL	OP( 0, LIT, FP, 0   )
+#define R2	OP( 1, 0,   0,  0   )
+#define RL2	OP( 1, LIT, 0,  0   )
+#define F2	OP( 1, 0,   FP, 0   )
+#define FL2	OP( 1, LIT, FP, 0   )
+#define R4	OP( 3, 0,   0,  0   )
+#define RL4	OP( 3, LIT, 0,  0   )
+#define F4	OP( 3, 0,   FP, 0   )
+#define FL4	OP( 3, LIT, FP, 0   )
+
+#define M	0x7f	/* Memory operand (MEMA & MEMB format instructions) */
+
+/* Macros to extract info from the register operand descriptor byte 'od'.
+ */
+#define SFR_OK(od)	(od & SFR)	/* TRUE if sfr operand allowed */
+#define LIT_OK(od)	(od & LIT)	/* TRUE if literal operand allowed */
+#define FP_OK(od)	(od & FP)	/* TRUE if floating-point op allowed */
+#define REG_ALIGN(od,n)	((od & 0x3 & n) == 0)
+					/* TRUE if reg #n is properly aligned */
+#define MEMOP(od)	(od == M)	/* TRUE if operand is a memory operand*/
+
+/* Description of a single i80960 instruction */
+struct i960_opcode {
+	long opcode;	/* 32 bits, constant fields filled in, rest zeroed */
+	char *name;	/* Assembler mnemonic				   */
+	short iclass;	/* Class: see #defines below			   */
+	char format;	/* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ	   */
+	char num_ops;	/* Number of operands				   */
+	char operand[3];/* Operand descriptors; same order as assembler instr */
+};
+
+/* Classes of 960 instructions:
+ *	- each instruction falls into one class.
+ *	- each target architecture supports one or more classes.
+ *
+ * EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!:  see targ_has_iclass().
+ */
+#define I_BASE	0x01	/* 80960 base instruction set	*/
+#define I_CX	0x02	/* 80960Cx instruction		*/
+#define I_DEC	0x04	/* Decimal instruction		*/
+#define I_FP	0x08	/* Floating point instruction	*/
+#define I_KX	0x10	/* 80960Kx instruction		*/
+#define I_MIL	0x20	/* Military instruction		*/
+#define I_CASIM	0x40	/* CA simulator instruction	*/
+#define I_CX2	0x80	/* Cx/Jx/Hx instructions	*/
+#define I_JX	0x100	/* Jx/Hx instruction		*/
+#define I_HX	0x200	/* Hx instructions		*/
+
+/******************************************************************************
+ *
+ *		TABLE OF i960 INSTRUCTION DESCRIPTIONS
+ *
+ ******************************************************************************/
+
+const struct i960_opcode i960_opcodes[] = {
+
+	/* if a CTRL instruction has an operand, it's always a displacement */
+
+	/* callj default=='call' */
+	{ 0x09000000,	"callj",	I_BASE,	CALLJ, 	1, { 0, 0, 0 } },
+	{ 0x08000000,	"b",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	{ 0x09000000,	"call",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	{ 0x0a000000,	"ret",		I_BASE,	CTRL, 	0, { 0, 0, 0 } },
+	{ 0x0b000000,	"bal",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	{ 0x10000000,	"bno",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	/* bf same as bno */
+	{ 0x10000000,	"bf",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	/* bru same as bno */
+	{ 0x10000000,	"bru",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	{ 0x11000000,	"bg",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	/* brg same as bg */
+	{ 0x11000000,	"brg",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	{ 0x12000000,	"be",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	/* bre same as be */
+	{ 0x12000000,	"bre",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	{ 0x13000000,	"bge",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	/* brge same as bge */
+	{ 0x13000000,	"brge",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	{ 0x14000000,	"bl",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	/* brl same as bl */
+	{ 0x14000000,	"brl",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	{ 0x15000000,	"bne",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	/* brlg same as bne */
+	{ 0x15000000,	"brlg",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	{ 0x16000000,	"ble",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	/* brle same as ble */
+	{ 0x16000000,	"brle",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	{ 0x17000000,	"bo",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	/* bt same as bo */
+	{ 0x17000000,	"bt",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	/* bro same as bo */
+	{ 0x17000000,	"bro",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
+	{ 0x18000000,	"faultno",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
+	/* faultf same as faultno */
+	{ 0x18000000,	"faultf",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
+	{ 0x19000000,	"faultg",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
+	{ 0x1a000000,	"faulte",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
+	{ 0x1b000000,	"faultge",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
+	{ 0x1c000000,	"faultl",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
+	{ 0x1d000000,	"faultne",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
+	{ 0x1e000000,	"faultle",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
+	{ 0x1f000000,	"faulto",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
+	/* faultt syn for faulto */
+	{ 0x1f000000,	"faultt",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
+
+	{ 0x01000000,	"syscall",	I_CASIM,CTRL, 	0, { 0, 0, 0 } },
+
+	/* If a COBR (or COJ) has 3 operands, the last one is always a
+	 * displacement and does not appear explicitly in the table.
+	 */
+
+	{ 0x20000000,	"testno",	I_BASE,	COBR,	1, { R, 0, 0 }	},
+	{ 0x21000000,	"testg",	I_BASE,	COBR,	1, { R, 0, 0 }	},
+	{ 0x22000000,	"teste",	I_BASE,	COBR,	1, { R, 0, 0 }	},
+	{ 0x23000000,	"testge",	I_BASE,	COBR,	1, { R, 0, 0 }	},
+	{ 0x24000000,	"testl",	I_BASE,	COBR,	1, { R, 0, 0 }	},
+	{ 0x25000000,	"testne",	I_BASE,	COBR,	1, { R, 0, 0 }	},
+	{ 0x26000000,	"testle",	I_BASE,	COBR,	1, { R, 0, 0 }	},
+	{ 0x27000000,	"testo",	I_BASE,	COBR,	1, { R, 0, 0 }	},
+	{ 0x30000000,	"bbc",		I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x31000000,	"cmpobg",	I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x32000000,	"cmpobe",	I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x33000000,	"cmpobge",	I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x34000000,	"cmpobl",	I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x35000000,	"cmpobne",	I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x36000000,	"cmpoble",	I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x37000000,	"bbs",		I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x38000000,	"cmpibno",	I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x39000000,	"cmpibg",	I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x3a000000,	"cmpibe",	I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x3b000000,	"cmpibge",	I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x3c000000,	"cmpibl",	I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x3d000000,	"cmpibne",	I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x3e000000,	"cmpible",	I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x3f000000,	"cmpibo",	I_BASE,	COBR,	3, { RL, RS, 0 } },
+	{ 0x31000000,	"cmpojg",	I_BASE,	COJ,	3, { RL, RS, 0 } },
+	{ 0x32000000,	"cmpoje",	I_BASE,	COJ,	3, { RL, RS, 0 } },
+	{ 0x33000000,	"cmpojge",	I_BASE,	COJ,	3, { RL, RS, 0 } },
+	{ 0x34000000,	"cmpojl",	I_BASE,	COJ,	3, { RL, RS, 0 } },
+	{ 0x35000000,	"cmpojne",	I_BASE,	COJ,	3, { RL, RS, 0 } },
+	{ 0x36000000,	"cmpojle",	I_BASE,	COJ,	3, { RL, RS, 0 } },
+	{ 0x38000000,	"cmpijno",	I_BASE,	COJ,	3, { RL, RS, 0 } },
+	{ 0x39000000,	"cmpijg",	I_BASE,	COJ,	3, { RL, RS, 0 } },
+	{ 0x3a000000,	"cmpije",	I_BASE,	COJ,	3, { RL, RS, 0 } },
+	{ 0x3b000000,	"cmpijge",	I_BASE,	COJ,	3, { RL, RS, 0 } },
+	{ 0x3c000000,	"cmpijl",	I_BASE,	COJ,	3, { RL, RS, 0 } },
+	{ 0x3d000000,	"cmpijne",	I_BASE,	COJ,	3, { RL, RS, 0 } },
+	{ 0x3e000000,	"cmpijle",	I_BASE,	COJ,	3, { RL, RS, 0 } },
+	{ 0x3f000000,	"cmpijo",	I_BASE,	COJ,	3, { RL, RS, 0 } },
+
+	{ 0x80000000,	"ldob",		I_BASE,	MEM1,	2, { M,  R,  0 } },
+	{ 0x82000000,	"stob",		I_BASE,	MEM1,	2, { R,  M,  0 } },
+	{ 0x84000000,	"bx",		I_BASE,	MEM1,	1, { M,  0,  0 } },
+	{ 0x85000000,	"balx",		I_BASE,	MEM1,	2, { M,  R,  0 } },
+	{ 0x86000000,	"callx",	I_BASE,	MEM1,	1, { M,  0,  0 } },
+	{ 0x88000000,	"ldos",		I_BASE,	MEM2,	2, { M,  R,  0 } },
+	{ 0x8a000000,	"stos",		I_BASE,	MEM2,	2, { R,  M,  0 } },
+	{ 0x8c000000,	"lda",		I_BASE,	MEM1,	2, { M,  R,  0 } },
+	{ 0x90000000,	"ld",		I_BASE,	MEM4,	2, { M,  R,  0 } },
+	{ 0x92000000,	"st",		I_BASE,	MEM4,	2, { R,  M,  0 } },
+	{ 0x98000000,	"ldl",		I_BASE,	MEM8,	2, { M,  R2, 0 } },
+	{ 0x9a000000,	"stl",		I_BASE,	MEM8,	2, { R2, M,  0 } },
+	{ 0xa0000000,	"ldt",		I_BASE,	MEM12,	2, { M,  R4, 0 } },
+	{ 0xa2000000,	"stt",		I_BASE,	MEM12,	2, { R4, M,  0 } },
+	{ 0xb0000000,	"ldq",		I_BASE,	MEM16,	2, { M,  R4, 0 } },
+	{ 0xb2000000,	"stq",		I_BASE,	MEM16,	2, { R4, M,  0 } },
+	{ 0xc0000000,	"ldib",		I_BASE,	MEM1,	2, { M,  R,  0 } },
+	{ 0xc2000000,	"stib",		I_BASE,	MEM1,	2, { R,  M,  0 } },
+	{ 0xc8000000,	"ldis",		I_BASE,	MEM2,	2, { M,  R,  0 } },
+	{ 0xca000000,	"stis",		I_BASE,	MEM2,	2, { R,  M,  0 } },
+
+	{ R_3(0x580),	"notbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x581),	"and",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x582),	"andnot",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x583),	"setbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x584),	"notand",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x586),	"xor",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x587),	"or",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x588),	"nor",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x589),	"xnor",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_2D(0x58a),	"not",		I_BASE,	REG,	2, { RSL,RS, 0 } },
+	{ R_3(0x58b),	"ornot",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x58c),	"clrbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x58d),	"notor",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x58e),	"nand",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x58f),	"alterbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x590),	"addo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x591),	"addi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x592),	"subo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x593),	"subi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x598),	"shro",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x59a),	"shrdi",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x59b),	"shri",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x59c),	"shlo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x59d),	"rotate",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x59e),	"shli",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_2(0x5a0),	"cmpo",		I_BASE,	REG,	2, { RSL,RSL, 0 } },
+	{ R_2(0x5a1),	"cmpi",		I_BASE,	REG,	2, { RSL,RSL, 0 } },
+	{ R_2(0x5a2),	"concmpo",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
+	{ R_2(0x5a3),	"concmpi",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
+	{ R_3(0x5a4),	"cmpinco",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x5a5),	"cmpinci",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x5a6),	"cmpdeco",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x5a7),	"cmpdeci",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_2(0x5ac),	"scanbyte",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
+	{ R_2(0x5ae),	"chkbit",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
+	{ R_3(0x5b0),	"addc",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x5b2),	"subc",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_2D(0x5cc),	"mov",		I_BASE,	REG,	2, { RSL,RS, 0 } },
+	{ R_2D(0x5dc),	"movl",		I_BASE,	REG,	2, { RL2,R2, 0 } },
+	{ R_2D(0x5ec),	"movt",		I_BASE,	REG,	2, { RL4,R4, 0 } },
+	{ R_2D(0x5fc),	"movq",		I_BASE,	REG,	2, { RL4,R4, 0 } },
+	{ R_3(0x610),	"atmod",	I_BASE,	REG,	3, { RS, RSL,R } },
+	{ R_3(0x612),	"atadd",	I_BASE,	REG,	3, { RS, RSL,RS } },
+	{ R_2D(0x640),	"spanbit",	I_BASE,	REG,	2, { RSL,RS, 0 } },
+	{ R_2D(0x641),	"scanbit",	I_BASE,	REG,	2, { RSL,RS, 0 } },
+	{ R_3(0x645),	"modac",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x650),	"modify",	I_BASE,	REG,	3, { RSL,RSL,R } },
+	{ R_3(0x651),	"extract",	I_BASE,	REG,	3, { RSL,RSL,R } },
+	{ R_3(0x654),	"modtc",	I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x655),	"modpc",	I_BASE,	REG,	3, { RSL,RSL,R } },
+	{ R_1(0x660),	"calls",	I_BASE,	REG,	1, { RSL, 0, 0 } },
+	{ R_0(0x66b),	"mark",		I_BASE,	REG,	0, { 0, 0, 0 }	},
+	{ R_0(0x66c),	"fmark",	I_BASE,	REG,	0, { 0, 0, 0 }	},
+	{ R_0(0x66d),	"flushreg",	I_BASE,	REG,	0, { 0, 0, 0 }	},
+	{ R_0(0x66f),	"syncf",	I_BASE,	REG,	0, { 0, 0, 0 }	},
+	{ R_3(0x670),	"emul",		I_BASE,	REG,	3, { RSL,RSL,R2 } },
+	{ R_3(0x671),	"ediv",		I_BASE,	REG,	3, { RSL,RL2,RS } },
+	{ R_2D(0x672),	"cvtadr",	I_CASIM,REG, 	2, { RL, R2, 0 } },
+	{ R_3(0x701),	"mulo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x708),	"remo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x70b),	"divo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x741),	"muli",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x748),	"remi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x749),	"modi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x74b),	"divi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
+
+	/* Floating-point instructions */
+
+	{ R_2D(0x674),	"cvtir",	I_FP,	REG,	2, { RL, F, 0 } },
+	{ R_2D(0x675),	"cvtilr",	I_FP,	REG,	2, { RL, F, 0 } },
+	{ R_3(0x676),	"scalerl",	I_FP,	REG,	3, { RL, FL2,F2 } },
+	{ R_3(0x677),	"scaler",	I_FP,	REG,	3, { RL, FL, F } },
+	{ R_3(0x680),	"atanr",	I_FP,	REG,	3, { FL, FL, F } },
+	{ R_3(0x681),	"logepr",	I_FP,	REG,	3, { FL, FL, F } },
+	{ R_3(0x682),	"logr",		I_FP,	REG,	3, { FL, FL, F } },
+	{ R_3(0x683),	"remr",		I_FP,	REG,	3, { FL, FL, F } },
+	{ R_2(0x684),	"cmpor",	I_FP,	REG,	2, { FL, FL, 0 } },
+	{ R_2(0x685),	"cmpr",		I_FP,	REG,	2, { FL, FL, 0 } },
+	{ R_2D(0x688),	"sqrtr",	I_FP,	REG,	2, { FL, F, 0 } },
+	{ R_2D(0x689),	"expr",		I_FP,	REG,	2, { FL, F, 0 } },
+	{ R_2D(0x68a),	"logbnr",	I_FP,	REG,	2, { FL, F, 0 } },
+	{ R_2D(0x68b),	"roundr",	I_FP,	REG,	2, { FL, F, 0 } },
+	{ R_2D(0x68c),	"sinr",		I_FP,	REG,	2, { FL, F, 0 } },
+	{ R_2D(0x68d),	"cosr",		I_FP,	REG,	2, { FL, F, 0 } },
+	{ R_2D(0x68e),	"tanr",		I_FP,	REG,	2, { FL, F, 0 } },
+	{ R_1(0x68f),	"classr",	I_FP,	REG,	1, { FL, 0, 0 }	},
+	{ R_3(0x690),	"atanrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
+	{ R_3(0x691),	"logeprl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
+	{ R_3(0x692),	"logrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
+	{ R_3(0x693),	"remrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
+	{ R_2(0x694),	"cmporl",	I_FP,	REG,	2, { FL2,FL2, 0 } },
+	{ R_2(0x695),	"cmprl",	I_FP,	REG,	2, { FL2,FL2, 0 } },
+	{ R_2D(0x698),	"sqrtrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
+	{ R_2D(0x699),	"exprl",	I_FP,	REG,	2, { FL2,F2, 0 } },
+	{ R_2D(0x69a),	"logbnrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
+	{ R_2D(0x69b),	"roundrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
+	{ R_2D(0x69c),	"sinrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
+	{ R_2D(0x69d),	"cosrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
+	{ R_2D(0x69e),	"tanrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
+	{ R_1(0x69f),	"classrl",	I_FP,	REG,	1, { FL2, 0, 0 } },
+	{ R_2D(0x6c0),	"cvtri",	I_FP,	REG,	2, { FL, R, 0 } },
+	{ R_2D(0x6c1),	"cvtril",	I_FP,	REG,	2, { FL, R2, 0 } },
+	{ R_2D(0x6c2),	"cvtzri",	I_FP,	REG,	2, { FL, R, 0 } },
+	{ R_2D(0x6c3),	"cvtzril",	I_FP,	REG,	2, { FL, R2, 0 } },
+	{ R_2D(0x6c9),	"movr",		I_FP,	REG,	2, { FL, F, 0 } },
+	{ R_2D(0x6d9),	"movrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
+	{ R_2D(0x6e1),	"movre",	I_FP,	REG,	2, { FL4,F4, 0 } },
+	{ R_3(0x6e2),	"cpysre",	I_FP,	REG,	3, { FL4,FL4,F4 } },
+	{ R_3(0x6e3),	"cpyrsre",	I_FP,	REG,	3, { FL4,FL4,F4 } },
+	{ R_3(0x78b),	"divr",		I_FP,	REG,	3, { FL, FL, F } },
+	{ R_3(0x78c),	"mulr",		I_FP,	REG,	3, { FL, FL, F } },
+	{ R_3(0x78d),	"subr",		I_FP,	REG,	3, { FL, FL, F } },
+	{ R_3(0x78f),	"addr",		I_FP,	REG,	3, { FL, FL, F } },
+	{ R_3(0x79b),	"divrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
+	{ R_3(0x79c),	"mulrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
+	{ R_3(0x79d),	"subrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
+	{ R_3(0x79f),	"addrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
+
+	/* These are the floating point branch instructions.  Each actually
+	 * generates 2 branch instructions:  the first a CTRL instruction with
+	 * the indicated opcode, and the second a 'bno'.
+	 */
+
+	{ 0x12000000,	"brue",		I_FP,	FBRA, 	1, { 0, 0, 0 }	},
+	{ 0x11000000,	"brug",		I_FP,	FBRA, 	1, { 0, 0, 0 }	},
+	{ 0x13000000,	"bruge",	I_FP,	FBRA, 	1, { 0, 0, 0 }	},
+	{ 0x14000000,	"brul",		I_FP,	FBRA, 	1, { 0, 0, 0 }	},
+	{ 0x16000000,	"brule",	I_FP,	FBRA, 	1, { 0, 0, 0 }	},
+	{ 0x15000000,	"brulg",	I_FP,	FBRA, 	1, { 0, 0, 0 }	},
+
+
+	/* Decimal instructions */
+
+	{ R_3(0x642),	"daddc",	I_DEC,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x643),	"dsubc",	I_DEC,	REG,	3, { RSL,RSL,RS } },
+	{ R_2D(0x644),	"dmovt",	I_DEC,	REG,	2, { RSL,RS, 0 } },
+
+
+	/* KX extensions */
+
+	{ R_2(0x600),	"synmov",	I_KX,	REG,	2, { R,  R, 0 } },
+	{ R_2(0x601),	"synmovl",	I_KX,	REG,	2, { R,  R, 0 } },
+	{ R_2(0x602),	"synmovq",	I_KX,	REG,	2, { R,  R, 0 } },
+	{ R_2D(0x615),	"synld",	I_KX,	REG,	2, { R,  R, 0 } },
+
+
+	/* MC extensions */
+
+	{ R_3(0x603),	"cmpstr",	I_MIL,	REG,	3, { R,  R,  RL } },
+	{ R_3(0x604),	"movqstr",	I_MIL,	REG,	3, { R,  R,  RL } },
+	{ R_3(0x605),	"movstr",	I_MIL,	REG,	3, { R,  R,  RL } },
+	{ R_2D(0x613),	"inspacc",	I_MIL,	REG,	2, { R,  R, 0 } },
+	{ R_2D(0x614),	"ldphy",	I_MIL,	REG,	2, { R,  R, 0 } },
+	{ R_3(0x617),	"fill",		I_MIL,	REG,	3, { R,  RL, RL } },
+	{ R_2D(0x646),	"condrec",	I_MIL,	REG,	2, { R,  R, 0 } },
+	{ R_2D(0x656),	"receive",	I_MIL,	REG,	2, { R,  R, 0 } },
+	{ R_3(0x662),	"send",		I_MIL,	REG,	3, { R,  RL, R } },
+	{ R_1(0x663),	"sendserv",	I_MIL,	REG,	1, { R, 0, 0 }	},
+	{ R_1(0x664),	"resumprcs",	I_MIL,	REG,	1, { R, 0, 0 }	},
+	{ R_1(0x665),	"schedprcs",	I_MIL,	REG,	1, { R, 0, 0 }	},
+	{ R_0(0x666),	"saveprcs",	I_MIL,	REG,	0, { 0, 0, 0 }	},
+	{ R_1(0x668),	"condwait",	I_MIL,	REG,	1, { R, 0, 0 }	},
+	{ R_1(0x669),	"wait",		I_MIL,	REG,	1, { R, 0, 0 }	},
+	{ R_1(0x66a),	"signal",	I_MIL,	REG,	1, { R, 0, 0 }	},
+	{ R_1D(0x673),	"ldtime",	I_MIL,	REG,	1, { R2, 0, 0 }	},
+
+
+	/* CX extensions */
+
+	{ R_3(0x5d8),	"eshro",	I_CX2,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x630),	"sdma",		I_CX,	REG,	3, { RSL,RSL,RL } },
+	{ R_3(0x631),	"udma",		I_CX,	REG,	0, { 0, 0, 0 }	},
+	{ R_3(0x659),	"sysctl",	I_CX2,	REG,	3, { RSL,RSL,RL } },
+
+
+	/* Jx extensions.  */
+	{ R_3(0x780),	"addono",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x790),	"addog",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7a0),	"addoe",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7b0),	"addoge",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7c0),	"addol",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7d0),	"addone",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7e0),	"addole",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7f0),	"addoo",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x781),	"addino",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x791),	"addig",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7a1),	"addie",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7b1),	"addige",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7c1),	"addil",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7d1),	"addine",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7e1),	"addile",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7f1),	"addio",	I_JX,	REG,	3, { RSL,RSL,RS } },
+
+	{ R_2D(0x5ad),	"bswap",	I_JX,	REG,	2, { RSL, RS, 0 } },
+
+	{ R_2(0x594),	"cmpob",	I_JX,	REG,	2, { RSL,RSL, 0 } },
+	{ R_2(0x595),	"cmpib",	I_JX,	REG,	2, { RSL,RSL, 0 } },
+	{ R_2(0x596),	"cmpos",	I_JX,	REG,	2, { RSL,RSL, 0 } },
+	{ R_2(0x597),	"cmpis",	I_JX,	REG,	2, { RSL,RSL, 0 } },
+
+	{ R_3(0x784),	"selno",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x794),	"selg",		I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7a4),	"sele",		I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7b4),	"selge",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7c4),	"sell",		I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7d4),	"selne",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7e4),	"selle",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7f4),	"selo",		I_JX,	REG,	3, { RSL,RSL,RS } },
+
+	{ R_3(0x782),	"subono",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x792),	"subog",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7a2),	"suboe",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7b2),	"suboge",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7c2),	"subol",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7d2),	"subone",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7e2),	"subole",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7f2),	"suboo",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x783),	"subino",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x793),	"subig",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7a3),	"subie",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7b3),	"subige",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7c3),	"subil",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7d3),	"subine",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7e3),	"subile",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_3(0x7f3),	"subio",	I_JX,	REG,	3, { RSL,RSL,RS } },
+
+	{ R_3(0x65c),	"dcctl",	I_JX,	REG,	3, { RSL,RSL,RL } },
+	{ R_3(0x65b),	"icctl",	I_JX,	REG,	3, { RSL,RSL,RS } },
+	{ R_2D(0x658),	"intctl",	I_JX,	REG,	2, { RSL, RS, 0 } },
+	{ R_0(0x5b4),	"intdis",	I_JX,	REG,	0, {   0,  0, 0 } },
+	{ R_0(0x5b5),	"inten",	I_JX,	REG,	0, {   0,  0, 0 } },
+	{ R_0(0x65d),	"halt",		I_JX,	REG,	1, { RSL,  0, 0 } },
+
+	/* Hx extensions.  */
+	{ 0xac000000,	"dcinva",	I_HX,	MEM1,	1, {   M,  0, 0 } },
+
+	/* END OF TABLE */
+
+	{ 0,		NULL,		0,	0,	0, { 0, 0, 0 }	}
+};
+
+ /* end of i960-opcode.h */
diff --git a/binutils-2.25/include/opcode/ia64.h b/binutils-2.25/include/opcode/ia64.h
new file mode 100644
index 00000000..433c5058
--- /dev/null
+++ b/binutils-2.25/include/opcode/ia64.h
@@ -0,0 +1,422 @@
+/* ia64.h -- Header file for ia64 opcode table
+   Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006, 2010
+   Free Software Foundation, Inc.
+   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef opcode_ia64_h
+#define opcode_ia64_h
+
+#include <sys/types.h>
+
+#include "bfd.h"
+
+
+typedef BFD_HOST_U_64_BIT ia64_insn;
+
+enum ia64_insn_type
+  {
+    IA64_TYPE_NIL = 0,	/* illegal type */
+    IA64_TYPE_A,	/* integer alu (I- or M-unit) */
+    IA64_TYPE_I,	/* non-alu integer (I-unit) */
+    IA64_TYPE_M,	/* memory (M-unit) */
+    IA64_TYPE_B,	/* branch (B-unit) */
+    IA64_TYPE_F,	/* floating-point (F-unit) */
+    IA64_TYPE_X,	/* long encoding (X-unit) */
+    IA64_TYPE_DYN,	/* Dynamic opcode */
+    IA64_NUM_TYPES
+  };
+
+enum ia64_unit
+  {
+    IA64_UNIT_NIL = 0,	/* illegal unit */
+    IA64_UNIT_I,	/* integer unit */
+    IA64_UNIT_M,	/* memory unit */
+    IA64_UNIT_B,	/* branching unit */
+    IA64_UNIT_F,	/* floating-point unit */
+    IA64_UNIT_L,	/* long "unit" */
+    IA64_UNIT_X,	/* may be integer or branch unit */
+    IA64_NUM_UNITS
+  };
+
+/* Changes to this enumeration must be propagated to the operand table in
+   bfd/cpu-ia64-opc.c
+ */
+enum ia64_opnd
+  {
+    IA64_OPND_NIL,	/* no operand---MUST BE FIRST!*/
+
+    /* constants */
+    IA64_OPND_AR_CSD,	/* application register csd (ar.csd) */
+    IA64_OPND_AR_CCV,	/* application register ccv (ar.ccv) */
+    IA64_OPND_AR_PFS,	/* application register pfs (ar.pfs) */
+    IA64_OPND_C1,	/* the constant 1 */
+    IA64_OPND_C8,	/* the constant 8 */
+    IA64_OPND_C16,	/* the constant 16 */
+    IA64_OPND_GR0,	/* gr0 */
+    IA64_OPND_IP,	/* instruction pointer (ip) */
+    IA64_OPND_PR,	/* predicate register (pr) */
+    IA64_OPND_PR_ROT,	/* rotating predicate register (pr.rot) */
+    IA64_OPND_PSR,	/* processor status register (psr) */
+    IA64_OPND_PSR_L,	/* processor status register L (psr.l) */
+    IA64_OPND_PSR_UM,	/* processor status register UM (psr.um) */
+
+    /* register operands: */
+    IA64_OPND_AR3,	/* third application register # (bits 20-26) */
+    IA64_OPND_B1,	/* branch register # (bits 6-8) */
+    IA64_OPND_B2,	/* branch register # (bits 13-15) */
+    IA64_OPND_CR3,	/* third control register # (bits 20-26) */
+    IA64_OPND_F1,	/* first floating-point register # */
+    IA64_OPND_F2,	/* second floating-point register # */
+    IA64_OPND_F3,	/* third floating-point register # */
+    IA64_OPND_F4,	/* fourth floating-point register # */
+    IA64_OPND_P1,	/* first predicate # */
+    IA64_OPND_P2,	/* second predicate # */
+    IA64_OPND_R1,	/* first register # */
+    IA64_OPND_R2,	/* second register # */
+    IA64_OPND_R3,	/* third register # */
+    IA64_OPND_R3_2,	/* third register # (limited to gr0-gr3) */
+    IA64_OPND_DAHR3,	/* dahr reg # ( bits 23-25) */
+
+    /* memory operands: */
+    IA64_OPND_MR3,	/* memory at addr of third register # */
+
+    /* indirect operands: */
+    IA64_OPND_CPUID_R3,	/* cpuid[reg] */
+    IA64_OPND_DBR_R3,	/* dbr[reg] */
+    IA64_OPND_DTR_R3,	/* dtr[reg] */
+    IA64_OPND_ITR_R3,	/* itr[reg] */
+    IA64_OPND_IBR_R3,	/* ibr[reg] */
+    IA64_OPND_MSR_R3,	/* msr[reg] */
+    IA64_OPND_PKR_R3,	/* pkr[reg] */
+    IA64_OPND_PMC_R3,	/* pmc[reg] */
+    IA64_OPND_PMD_R3,	/* pmd[reg] */
+    IA64_OPND_DAHR_R3,	/* dahr[reg] */
+    IA64_OPND_RR_R3,	/* rr[reg] */
+
+    /* immediate operands: */
+    IA64_OPND_CCNT5,	/* 5-bit count (31 - bits 20-24) */
+    IA64_OPND_CNT2a,	/* 2-bit count (1 + bits 27-28) */
+    IA64_OPND_CNT2b,	/* 2-bit count (bits 27-28): 1, 2, 3 */
+    IA64_OPND_CNT2c,	/* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
+    IA64_OPND_CNT5,	/* 5-bit count (bits 14-18) */
+    IA64_OPND_CNT6,	/* 6-bit count (bits 27-32) */
+    IA64_OPND_CPOS6a,	/* 6-bit count (63 - bits 20-25) */
+    IA64_OPND_CPOS6b,	/* 6-bit count (63 - bits 14-19) */
+    IA64_OPND_CPOS6c,	/* 6-bit count (63 - bits 31-36) */
+    IA64_OPND_IMM1,	/* signed 1-bit immediate (bit 36) */
+    IA64_OPND_IMMU2,	/* unsigned 2-bit immediate (bits 13-14) */
+    IA64_OPND_IMMU5b,	/* unsigned 5-bit immediate (32 + bits 14-18) */
+    IA64_OPND_IMMU7a,	/* unsigned 7-bit immediate (bits 13-19) */
+    IA64_OPND_IMMU7b,	/* unsigned 7-bit immediate (bits 20-26) */
+    IA64_OPND_SOF,	/* 8-bit stack frame size */
+    IA64_OPND_SOL,	/* 8-bit size of locals */
+    IA64_OPND_SOR,	/* 6-bit number of rotating registers (scaled by 8) */
+    IA64_OPND_IMM8,	/* signed 8-bit immediate (bits 13-19 & 36) */
+    IA64_OPND_IMM8U4,	/* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
+    IA64_OPND_IMM8M1,	/* signed 8-bit immediate -1 (bits 13-19 & 36) */
+    IA64_OPND_IMM8M1U4,	/* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
+    IA64_OPND_IMM8M1U8,	/* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
+    IA64_OPND_IMMU9,	/* unsigned 9-bit immediate (bits 33-34, 20-26) */
+    IA64_OPND_IMM9a,	/* signed 9-bit immediate (bits 6-12, 27, 36) */
+    IA64_OPND_IMM9b,	/* signed 9-bit immediate (bits 13-19, 27, 36) */
+    IA64_OPND_IMM14,	/* signed 14-bit immediate (bits 13-19, 27-32, 36) */
+    IA64_OPND_IMMU16,	/* unsigned 16-bit immediate (bits 6-9, 12-22, 36) */
+    IA64_OPND_IMM17,	/* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
+    IA64_OPND_IMMU19,	/* unsigned 19-bit immediate (bits 6-9, 12-25, 36) */
+    IA64_OPND_IMMU21,	/* unsigned 21-bit immediate (bits 6-25, 36) */
+    IA64_OPND_IMM22,	/* signed 22-bit immediate (bits 13-19, 22-36) */
+    IA64_OPND_IMMU24,	/* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
+    IA64_OPND_IMM44,	/* signed 44-bit immediate (2^16*bits 6-32, 36) */
+    IA64_OPND_IMMU62,	/* unsigned 62-bit immediate */
+    IA64_OPND_IMMU64,	/* unsigned 64-bit immediate (lotsa bits...) */
+    IA64_OPND_INC3,	/* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
+    IA64_OPND_LEN4,	/* 4-bit count (bits 27-30 + 1) */
+    IA64_OPND_LEN6,	/* 6-bit count (bits 27-32 + 1) */
+    IA64_OPND_MBTYPE4,	/* 4-bit mux type (bits 20-23) */
+    IA64_OPND_MHTYPE8,	/* 8-bit mux type (bits 20-27) */
+    IA64_OPND_POS6,	/* 6-bit count (bits 14-19) */
+    IA64_OPND_TAG13,	/* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
+    IA64_OPND_TAG13b,	/* signed 13-bit tag (ip + 16*bits 24-32) */
+    IA64_OPND_TGT25,	/* signed 25-bit (ip + 16*bits 6-25, 36) */
+    IA64_OPND_TGT25b,	/* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
+    IA64_OPND_TGT25c,	/* signed 25-bit (ip + 16*bits 13-32, 36) */
+    IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
+    IA64_OPND_LDXMOV,	/* any symbol, generates R_IA64_LDXMOV.  */
+
+    IA64_OPND_CNT6a,	/* 6-bit count  (bits 6-11) */
+    IA64_OPND_STRD5b,	/* 5-bit stride (bits 13-17) */
+
+    IA64_OPND_COUNT	/* # of operand types (MUST BE LAST!) */
+  };
+
+enum ia64_dependency_mode
+{
+  IA64_DV_RAW,
+  IA64_DV_WAW,
+  IA64_DV_WAR,
+};
+
+enum ia64_dependency_semantics
+{
+  IA64_DVS_NONE,
+  IA64_DVS_IMPLIED,
+  IA64_DVS_IMPLIEDF,
+  IA64_DVS_DATA,
+  IA64_DVS_INSTR,
+  IA64_DVS_SPECIFIC,
+  IA64_DVS_STOP,
+  IA64_DVS_OTHER,
+};
+
+enum ia64_resource_specifier
+{
+  IA64_RS_ANY,
+  IA64_RS_AR_K,
+  IA64_RS_AR_UNAT,
+  IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
+  IA64_RS_ARb, /* 48-63, 112-127 */
+  IA64_RS_BR,
+  IA64_RS_CFM,
+  IA64_RS_CPUID,
+  IA64_RS_CR_IIB,
+  IA64_RS_CR_IRR,
+  IA64_RS_CR_LRR,
+  IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */
+  IA64_RS_DAHR,
+  IA64_RS_DBR,
+  IA64_RS_FR,
+  IA64_RS_FRb,
+  IA64_RS_GR0,
+  IA64_RS_GR,
+  IA64_RS_IBR,
+  IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
+  IA64_RS_MSR,
+  IA64_RS_PKR,
+  IA64_RS_PMC,
+  IA64_RS_PMD,
+  IA64_RS_PR,  /* non-rotating, 1-15 */
+  IA64_RS_PRr, /* rotating, 16-62 */
+  IA64_RS_PR63,
+  IA64_RS_RR,
+
+  IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
+  IA64_RS_CRX, /* CRs not in RS_CR */
+  IA64_RS_PSR, /* PSR bits */
+  IA64_RS_RSE, /* implementation-specific RSE resources */
+  IA64_RS_AR_FPSR,
+
+};
+
+enum ia64_rse_resource
+{
+  IA64_RSE_N_STACKED_PHYS,
+  IA64_RSE_BOF,
+  IA64_RSE_STORE_REG,
+  IA64_RSE_LOAD_REG,
+  IA64_RSE_BSPLOAD,
+  IA64_RSE_RNATBITINDEX,
+  IA64_RSE_CFLE,
+  IA64_RSE_NDIRTY,
+};
+
+/* Information about a given resource dependency */
+struct ia64_dependency
+{
+  /* Name of the resource */
+  const char *name;
+  /* Does this dependency need further specification? */
+  enum ia64_resource_specifier specifier;
+  /* Mode of dependency */
+  enum ia64_dependency_mode mode;
+  /* Dependency semantics */
+  enum ia64_dependency_semantics semantics;
+  /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
+#define REG_NONE (-1)
+  int regindex;
+  /* Special info on semantics */
+  const char *info;
+};
+
+/* Two arrays of indexes into the ia64_dependency table.
+   chks are dependencies to check for conflicts when an opcode is
+   encountered; regs are dependencies to register (mark as used) when an
+   opcode is used.  chks correspond to readers (RAW) or writers (WAW or
+   WAR) of a resource, while regs correspond to writers (RAW or WAW) and
+   readers (WAR) of a resource.  */
+struct ia64_opcode_dependency
+{
+  int nchks;
+  const unsigned short *chks;
+  int nregs;
+  const unsigned short *regs;
+};
+
+/* encode/extract the note/index for a dependency */
+#define RDEP(N,X) (((N)<<11)|(X))
+#define NOTE(X) (((X)>>11)&0x1F)
+#define DEP(X) ((X)&0x7FF)
+
+/* A template descriptor describes the execution units that are active
+   for each of the three slots.  It also specifies the location of
+   instruction group boundaries that may be present between two slots.  */
+struct ia64_templ_desc
+  {
+    int group_boundary;	/* 0=no boundary, 1=between slot 0 & 1, etc. */
+    enum ia64_unit exec_unit[3];
+    const char *name;
+  };
+
+/* The opcode table is an array of struct ia64_opcode.  */
+
+struct ia64_opcode
+  {
+    /* The opcode name.  */
+    const char *name;
+
+    /* The type of the instruction: */
+    enum ia64_insn_type type;
+
+    /* Number of output operands: */
+    int num_outputs;
+
+    /* The opcode itself.  Those bits which will be filled in with
+       operands are zeroes.  */
+    ia64_insn opcode;
+
+    /* The opcode mask.  This is used by the disassembler.  This is a
+       mask containing ones indicating those bits which must match the
+       opcode field, and zeroes indicating those bits which need not
+       match (and are presumably filled in by operands).  */
+    ia64_insn mask;
+
+    /* An array of operand codes.  Each code is an index into the
+       operand table.  They appear in the order which the operands must
+       appear in assembly code, and are terminated by a zero.  */
+    enum ia64_opnd operands[5];
+
+    /* One bit flags for the opcode.  These are primarily used to
+       indicate specific processors and environments support the
+       instructions.  The defined values are listed below. */
+    unsigned int flags;
+
+    /* Used by ia64_find_next_opcode (). */
+    short ent_index;
+
+    /* Opcode dependencies. */
+    const struct ia64_opcode_dependency *dependencies;
+  };
+
+/* Values defined for the flags field of a struct ia64_opcode.  */
+
+#define IA64_OPCODE_FIRST	(1<<0)	/* must be first in an insn group */
+#define IA64_OPCODE_X_IN_MLX	(1<<1)	/* insn is allowed in X slot of MLX */
+#define IA64_OPCODE_LAST	(1<<2)	/* must be last in an insn group */
+#define IA64_OPCODE_PRIV	(1<<3)	/* privileged instruct */
+#define IA64_OPCODE_SLOT2	(1<<4)	/* insn allowed in slot 2 only */
+#define IA64_OPCODE_NO_PRED	(1<<5)	/* insn cannot be predicated */
+#define IA64_OPCODE_PSEUDO	(1<<6)	/* insn is a pseudo-op */
+#define IA64_OPCODE_F2_EQ_F3	(1<<7)	/* constraint: F2 == F3 */
+#define IA64_OPCODE_LEN_EQ_64MCNT	(1<<8)	/* constraint: LEN == 64-CNT */
+#define IA64_OPCODE_MOD_RRBS    (1<<9)	/* modifies all rrbs in CFM */
+#define IA64_OPCODE_POSTINC	(1<<10)	/* postincrement MR3 operand */
+
+/* A macro to extract the major opcode from an instruction.  */
+#define IA64_OP(i)	(((i) >> 37) & 0xf)
+
+enum ia64_operand_class
+  {
+    IA64_OPND_CLASS_CST,	/* constant */
+    IA64_OPND_CLASS_REG,	/* register */
+    IA64_OPND_CLASS_IND,	/* indirect register */
+    IA64_OPND_CLASS_ABS,	/* absolute value */
+    IA64_OPND_CLASS_REL,	/* IP-relative value */
+  };
+
+/* The operands table is an array of struct ia64_operand.  */
+
+struct ia64_operand
+{
+  enum ia64_operand_class op_class;
+
+  /* Set VALUE as the operand bits for the operand of type SELF in the
+     instruction pointed to by CODE.  If an error occurs, *CODE is not
+     modified and the returned string describes the cause of the
+     error.  If no error occurs, NULL is returned.  */
+  const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
+			 ia64_insn *code);
+
+  /* Extract the operand bits for an operand of type SELF from
+     instruction CODE store them in *VALUE.  If an error occurs, the
+     cause of the error is described by the string returned.  If no
+     error occurs, NULL is returned.  */
+  const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
+			  ia64_insn *value);
+
+  /* A string whose meaning depends on the operand class.  */
+
+  const char *str;
+
+  struct bit_field
+    {
+      /* The number of bits in the operand.  */
+      int bits;
+
+      /* How far the operand is left shifted in the instruction.  */
+      int shift;
+    }
+  field[4];		/* no operand has more than this many bit-fields */
+
+  unsigned int flags;
+
+  const char *desc;	/* brief description */
+};
+
+/* Values defined for the flags field of a struct ia64_operand.  */
+
+/* Disassemble as signed decimal (instead of hex): */
+#define IA64_OPND_FLAG_DECIMAL_SIGNED	(1<<0)
+/* Disassemble as unsigned decimal (instead of hex): */
+#define IA64_OPND_FLAG_DECIMAL_UNSIGNED	(1<<1)
+
+extern const struct ia64_templ_desc ia64_templ_desc[16];
+
+/* The tables are sorted by major opcode number and are otherwise in
+   the order in which the disassembler should consider instructions.  */
+extern struct ia64_opcode ia64_opcodes_a[];
+extern struct ia64_opcode ia64_opcodes_i[];
+extern struct ia64_opcode ia64_opcodes_m[];
+extern struct ia64_opcode ia64_opcodes_b[];
+extern struct ia64_opcode ia64_opcodes_f[];
+extern struct ia64_opcode ia64_opcodes_d[];
+
+
+extern struct ia64_opcode *ia64_find_opcode (const char *);
+extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *);
+
+extern struct ia64_opcode *ia64_dis_opcode (ia64_insn,
+					    enum ia64_insn_type);
+
+extern void ia64_free_opcode (struct ia64_opcode *);
+extern const struct ia64_dependency *ia64_find_dependency (int);
+
+/* To avoid circular library dependencies, this array is implemented
+   in bfd/cpu-ia64-opc.c: */
+extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
+
+#endif /* opcode_ia64_h */
diff --git a/binutils-2.25/include/opcode/m68hc11.h b/binutils-2.25/include/opcode/m68hc11.h
new file mode 100644
index 00000000..1a002008
--- /dev/null
+++ b/binutils-2.25/include/opcode/m68hc11.h
@@ -0,0 +1,456 @@
+/* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table
+   Copyright 1999, 2000, 2002, 2003, 2010, 2012
+   Free Software Foundation, Inc.
+   Written by Stephane Carrez (stcarrez@nerim.fr)
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _OPCODE_M68HC11_H
+#define _OPCODE_M68HC11_H
+
+/* Flags for the definition of the 68HC11 & 68HC12 CCR.  */
+#define M6811_S_BIT     0x80	/* Stop disable */
+#define M6811_X_BIT     0x40	/* X-interrupt mask */
+#define M6811_H_BIT     0x20	/* Half carry flag */
+#define M6811_I_BIT     0x10	/* I-interrupt mask */
+#define M6811_N_BIT     0x08	/* Negative */
+#define M6811_Z_BIT     0x04	/* Zero */
+#define M6811_V_BIT     0x02	/* Overflow */
+#define M6811_C_BIT     0x01	/* Carry */
+
+/* 68HC11 register address offsets (range 0..0x3F or 0..64).
+   The absolute address of the I/O register depends on the setting
+   of the M6811_INIT register.  At init time, the I/O registers are
+   mapped at 0x1000.  Address of registers is then:
+
+   0x1000 + M6811_xxx.  */
+#define M6811_PORTA     0x00	/* Port A register */
+#define M6811__RES1	0x01	/* Unused/Reserved */
+#define M6811_PIOC	0x02	/* Parallel I/O Control register */
+#define M6811_PORTC	0x03	/* Port C register */
+#define M6811_PORTB	0x04	/* Port B register */
+#define M6811_PORTCL	0x05	/* Alternate latched port C */
+#define M6811__RES6	0x06	/* Unused/Reserved */
+#define M6811_DDRC	0x07	/* Data direction register for port C */
+#define M6811_PORTD	0x08	/* Port D register */
+#define M6811_DDRD	0x09	/* Data direction register for port D */
+#define M6811_PORTE	0x0A	/* Port E input register */
+#define M6811_CFORC	0x0B	/* Compare Force Register */
+#define M6811_OC1M	0x0C	/* OC1 Action Mask register */
+#define M6811_OC1D	0x0D	/* OC1 Action Data register */
+#define M6811_TCTN	0x0E	/* Timer Counter Register */
+#define M6811_TCTN_H	0x0E	/* "	 "	 " High part */
+#define M6811_TCTN_L	0x0F	/* "	 "	 " Low part */
+#define M6811_TIC1	0x10	/* Input capture 1 register */
+#define M6811_TIC1_H	0x10	/* "	 "	 " High part */
+#define M6811_TIC1_L	0x11	/* "	 "	 " Low part */
+#define M6811_TIC2	0x12	/* Input capture 2 register */
+#define M6811_TIC2_H	0x12	/* "	 "	 " High part */
+#define M6811_TIC2_L	0x13	/* "	 "	 " Low part */
+#define M6811_TIC3	0x14	/* Input capture 3 register */
+#define M6811_TIC3_H	0x14	/* "	 "	 " High part */
+#define M6811_TIC3_L	0x15	/* "	 "	 " Low part */
+#define M6811_TOC1	0x16	/* Output Compare 1 register */
+#define M6811_TOC1_H	0x16	/* "	 "	 " High part */
+#define M6811_TOC1_L	0x17	/* "	 "	 " Low part */
+#define M6811_TOC2	0x18	/* Output Compare 2 register */
+#define M6811_TOC2_H	0x18	/* "	 "	 " High part */
+#define M6811_TOC2_L	0x19	/* "	 "	 " Low part */
+#define M6811_TOC3	0x1A	/* Output Compare 3 register */
+#define M6811_TOC3_H	0x1A	/* "	 "	 " High part */
+#define M6811_TOC3_L	0x1B	/* "	 "	 " Low part */
+#define M6811_TOC4	0x1C	/* Output Compare 4 register */
+#define M6811_TOC4_H	0x1C	/* "	 "	 " High part */
+#define M6811_TOC4_L	0x1D	/* "	 "	 " Low part */
+#define M6811_TOC5	0x1E	/* Output Compare 5 register */
+#define M6811_TOC5_H	0x1E	/* "	 "	 " High part */
+#define M6811_TOC5_L	0x1F	/* "	 "	 " Low part */
+#define M6811_TCTL1	0x20	/* Timer Control register 1 */
+#define M6811_TCTL2	0x21	/* Timer Control register 2 */
+#define M6811_TMSK1	0x22	/* Timer Interrupt Mask Register 1 */
+#define M6811_TFLG1	0x23	/* Timer Interrupt Flag Register 1 */
+#define M6811_TMSK2	0x24	/* Timer Interrupt Mask Register 2 */
+#define M6811_TFLG2	0x25	/* Timer Interrupt Flag Register 2 */
+#define M6811_PACTL	0x26	/* Pulse Accumulator Control Register */
+#define M6811_PACNT	0x27	/* Pulse Accumulator Count Register */
+#define M6811_SPCR	0x28	/* SPI Control register */
+#define M6811_SPSR	0x29	/* SPI Status register */
+#define M6811_SPDR	0x2A	/* SPI Data register */
+#define M6811_BAUD	0x2B	/* SCI Baud register */
+#define M6811_SCCR1	0x2C	/* SCI Control register 1 */
+#define M6811_SCCR2	0x2D	/* SCI Control register 2 */
+#define M6811_SCSR	0x2E	/* SCI Status register */
+#define M6811_SCDR	0x2F	/* SCI Data (Read => RDR, Write => TDR) */
+#define M6811_ADCTL	0x30	/* A/D Control register */
+#define M6811_ADR1	0x31	/* A/D, Analog Result register 1 */
+#define M6811_ADR2	0x32	/* A/D, Analog Result register 2 */
+#define M6811_ADR3	0x33	/* A/D, Analog Result register 3 */
+#define M6811_ADR4	0x34	/* A/D, Analog Result register 4 */
+#define M6811__RES35	0x35
+#define M6811__RES36	0x36
+#define M6811__RES37	0x37
+#define M6811__RES38	0x38
+#define M6811_OPTION	0x39	/* System Configuration Options */
+#define M6811_COPRST	0x3A	/* Arm/Reset COP Timer Circuitry */
+#define M6811_PPROG	0x3B	/* EEPROM Programming Control Register */
+#define M6811_HPRIO	0x3C	/* Highest priority I-Bit int and misc */
+#define M6811_INIT	0x3D	/* Ram and I/O mapping register */
+#define M6811_TEST1	0x3E	/* Factory test control register */
+#define M6811_CONFIG	0x3F	/* COP, ROM and EEPROM enables */
+
+
+/* Flags of the CONFIG register (in EEPROM).  */
+#define M6811_NOSEC     0x08    /* Security mode disable */
+#define M6811_NOCOP     0x04    /* COP system disable */
+#define M6811_ROMON     0x02    /* Enable on-chip rom */
+#define M6811_EEON      0x01    /* Enable on-chip eeprom */
+
+/* Flags of the PPROG register.  */
+#define M6811_BYTE	0x10	/* Byte mode */
+#define M6811_ROW       0x08	/* Row mode */
+#define M6811_ERASE	0x04	/* Erase mode select (1 = erase, 0 = read) */
+#define M6811_EELAT     0x02	/* EEPROM Latch Control */
+#define M6811_EEPGM     0x01	/* EEPROM Programming Voltage Enable */
+
+/* Flags of the PIOC register.  */
+#define M6811_STAF	0x80	/* Strobe A Interrupt Status Flag */
+#define M6811_STAI	0x40	/* Strobe A Interrupt Enable Mask */
+#define M6811_CWOM	0x20	/* Port C Wire OR mode */
+#define M6811_HNDS	0x10	/* Handshake mode */
+#define M6811_OIN	0x08	/* Output or Input handshaking */
+#define M6811_PLS	0x04	/* Pulse/Interlocked Handshake Operation */
+#define M6811_EGA	0x02	/* Active Edge for Strobe A */
+#define M6811_INVB	0x01	/* Invert Strobe B */
+
+/* Flags of the SCCR1 register.  */
+#define M6811_R8	0x80	/* Receive Data bit 8 */
+#define M6811_T8	0x40	/* Transmit data bit 8 */
+#define M6811__SCCR1_5  0x20	/* Unused */
+#define M6811_M		0x10	/* SCI Character length */
+#define M6811_WAKE	0x08	/* Wake up method select (0=idle, 1=addr mark) */
+
+/* Flags of the SCCR2 register.  */
+#define M6811_TIE	0x80	/* Transmit Interrupt enable */
+#define M6811_TCIE	0x40	/* Transmit Complete Interrupt Enable */
+#define M6811_RIE	0x20	/* Receive Interrupt Enable */
+#define M6811_ILIE	0x10	/* Idle Line Interrupt Enable */
+#define M6811_TE	0x08	/* Transmit Enable */
+#define M6811_RE	0x04	/* Receive Enable */
+#define M6811_RWU	0x02	/* Receiver Wake Up */
+#define M6811_SBK	0x01	/* Send Break */
+
+/* Flags of the SCSR register.  */
+#define M6811_TDRE	0x80	/* Transmit Data Register Empty */
+#define M6811_TC	0x40	/* Transmit Complete */
+#define M6811_RDRF	0x20	/* Receive Data Register Full */
+#define M6811_IDLE	0x10	/* Idle Line Detect */
+#define M6811_OR	0x08	/* Overrun Error */
+#define M6811_NF	0x04	/* Noise Flag */
+#define M6811_FE	0x02	/* Framing Error */
+#define M6811__SCSR_0	0x01	/* Unused */
+
+/* Flags of the BAUD register.  */
+#define M6811_TCLR	0x80	/* Clear Baud Rate (TEST mode) */
+#define M6811__BAUD_6	0x40	/* Not used */
+#define M6811_SCP1	0x20	/* SCI Baud rate prescaler select */
+#define M6811_SCP0	0x10
+#define M6811_RCKB	0x08	/* Baud Rate Clock Check (TEST mode) */
+#define M6811_SCR2	0x04	/* SCI Baud rate select */
+#define M6811_SCR1	0x02
+#define M6811_SCR0	0x01
+
+#define M6811_BAUD_DIV_1	(0)
+#define M6811_BAUD_DIV_3	(M6811_SCP0)
+#define M6811_BAUD_DIV_4	(M6811_SCP1)
+#define M6811_BAUD_DIV_13	(M6811_SCP1|M6811_SCP0)
+
+/* Flags of the SPCR register.  */
+#define M6811_SPIE	0x80	/* Serial Peripheral Interrupt Enable */
+#define M6811_SPE	0x40	/* Serial Peripheral System Enable */
+#define M6811_DWOM	0x20	/* Port D Wire-OR mode option */
+#define M6811_MSTR	0x10	/* Master Mode Select */
+#define M6811_CPOL	0x08	/* Clock Polarity */
+#define M6811_CPHA	0x04	/* Clock Phase */
+#define M6811_SPR1	0x02	/* SPI Clock Rate Select */
+#define M6811_SPR0	0x01
+
+/* Flags of the SPSR register.  */
+#define M6811_SPIF	0x80	/* SPI Transfer Complete flag */
+#define M6811_WCOL	0x40	/* Write Collision */
+#define M6811_MODF	0x10	/* Mode Fault */
+
+/* Flags of the ADCTL register.  */
+#define M6811_CCF	0x80	/* Conversions Complete Flag */
+#define M6811_SCAN	0x20	/* Continuous Scan Control */
+#define M6811_MULT	0x10	/* Multiple Channel/Single Channel Control */
+#define M6811_CD	0x08	/* Channel Select D */
+#define M6811_CC	0x04	/*                C */
+#define M6811_CB	0x02	/*                B */
+#define M6811_CA	0x01	/*                A */
+
+/* Flags of the CFORC register.  */
+#define M6811_FOC1	0x80	/* Force Output Compare 1 */
+#define M6811_FOC2	0x40	/*			2 */
+#define M6811_FOC3	0x20	/*			3 */
+#define M6811_FOC4	0x10	/*			4 */
+#define M6811_FOC5	0x08	/*			5 */
+
+/* Flags of the OC1M register.  */
+#define M6811_OC1M7	0x80	/* Output Compare 7 */
+#define M6811_OC1M6	0x40	/*                6 */
+#define M6811_OC1M5	0x20	/*                5 */
+#define M6811_OC1M4	0x10	/*                4 */
+#define M6811_OC1M3	0x08	/*                3 */
+
+/* Flags of the OC1D register.  */
+#define M6811_OC1D7	0x80
+#define M6811_OC1D6	0x40
+#define M6811_OC1D5	0x20
+#define M6811_OC1D4	0x10
+#define M6811_OC1D3	0x08
+
+/* Flags of the TCTL1 register.  */
+#define M6811_OM2	0x80	/* Output Mode 2 */
+#define M6811_OL2	0x40	/* Output Level 2 */
+#define M6811_OM3	0x20
+#define M6811_OL3	0x10
+#define M6811_OM4	0x08
+#define M6811_OL4	0x04
+#define M6811_OM5	0x02
+#define M6811_OL5	0x01
+
+/* Flags of the TCTL2 register.  */
+#define M6811_EDG1B	0x20	/* Input Edge Capture Control 1 */
+#define M6811_EDG1A	0x10
+#define M6811_EDG2B	0x08	/* Input 2 */
+#define M6811_EDG2A	0x04
+#define M6811_EDG3B	0x02	/* Input 3 */
+#define M6811_EDG3A	0x01
+
+/* Flags of the TMSK1 register.  */
+#define M6811_OC1I	0x80	/* Output Compare 1 Interrupt */
+#define M6811_OC2I	0x40	/*		  2	      */
+#define M6811_OC3I	0x20	/*		  3	      */
+#define M6811_OC4I	0x10	/*		  4	      */
+#define M6811_OC5I	0x08	/*		  5	      */
+#define M6811_IC1I	0x04	/* Input Capture  1 Interrupt */
+#define M6811_IC2I	0x02	/*		  2	      */
+#define M6811_IC3I	0x01	/*		  3	      */
+
+/* Flags of the TFLG1 register.  */
+#define M6811_OC1F	0x80	/* Output Compare 1 Flag */
+#define M6811_OC2F	0x40	/*		  2	 */
+#define M6811_OC3F	0x20	/*		  3	 */
+#define M6811_OC4F	0x10	/*		  4	 */
+#define M6811_OC5F	0x08	/*		  5	 */
+#define M6811_IC1F	0x04	/* Input Capture  1 Flag */
+#define M6811_IC2F	0x02	/*		  2	 */
+#define M6811_IC3F	0x01	/*		  3	 */
+
+/* Flags of Timer Interrupt Mask Register 2 (TMSK2).  */
+#define M6811_TOI       0x80    /* Timer Overflow Interrupt Enable */
+#define M6811_RTII      0x40    /* RTI Interrupt Enable */
+#define M6811_PAOVI     0x20    /* Pulse Accumulator Overflow Interrupt En. */
+#define M6811_PAII      0x10    /* Pulse Accumulator Interrupt Enable */
+#define M6811_PR1       0x02    /* Timer prescaler */
+#define M6811_PR0       0x01    /* Timer prescaler */
+#define M6811_TPR_1     0x00    /* " " prescale div 1 */
+#define M6811_TPR_4     0x01    /* " " prescale div 4 */
+#define M6811_TPR_8     0x02    /* " " prescale div 8 */
+#define M6811_TPR_16    0x03    /* " " prescale div 16 */
+
+/* Flags of Timer Interrupt Flag Register 2 (M6811_TFLG2).  */
+#define M6811_TOF       0x80    /* Timer overflow bit */
+#define M6811_RTIF      0x40    /* Read time interrupt flag */
+#define M6811_PAOVF     0x20    /* Pulse accumulator overflow Interrupt flag */
+#define M6811_PAIF      0x10    /* Pulse accumulator Input Edge " " " */
+
+/* Flags of Pulse Accumulator Control Register (PACTL).  */
+#define M6811_DDRA7     0x80    /* Data direction for port A bit 7 */
+#define M6811_PAEN      0x40    /* Pulse accumulator system enable */
+#define M6811_PAMOD     0x20    /* Pulse accumulator mode */
+#define M6811_PEDGE     0x10    /* Pulse accumulator edge control */
+#define M6811_RTR1      0x02    /* RTI Interrupt rates select */
+#define M6811_RTR0      0x01    /* " " " " */
+
+/* Flags of the Options register.  */
+#define M6811_ADPU      0x80    /* A/D Powerup */
+#define M6811_CSEL      0x40    /* A/D/EE Charge pump clock source select */
+#define M6811_IRQE      0x20    /* IRQ Edge/Level sensitive */
+#define M6811_DLY       0x10    /* Stop exit turn on delay */
+#define M6811_CME       0x08    /* Clock Monitor enable */
+#define M6811_CR1       0x02    /* COP timer rate select */
+#define M6811_CR0       0x01    /* COP timer rate select */
+
+/* Flags of the HPRIO register.  */
+#define M6811_RBOOT	0x80	/* Read Bootstrap ROM */
+#define M6811_SMOD	0x40	/* Special Mode */
+#define M6811_MDA	0x20	/* Mode Select A */
+#define M6811_IRV	0x10	/* Internal Read Visibility */
+#define M6811_PSEL3	0x08	/* Priority Select */
+#define M6811_PSEL2	0x04
+#define M6811_PSEL1	0x02
+#define M6811_PSEL0	0x01
+
+/* Some insns used by gas to turn relative branches into absolute ones.  */
+#define M6811_BRA	0x20
+#define M6811_JMP	0x7e
+#define M6811_BSR	0x8d
+#define M6811_JSR	0xbd
+#define M6812_JMP       0x06
+#define M6812_BSR       0x07
+#define M6812_JSR       0x16
+
+/* Instruction code pages. Code page 1 is the default.  */
+/*#define	M6811_OPCODE_PAGE1	0x00*/
+#define	M6811_OPCODE_PAGE2	0x18
+#define	M6811_OPCODE_PAGE3	0x1A
+#define	M6811_OPCODE_PAGE4	0xCD
+
+
+/* 68HC11 operands formats as stored in the m6811_opcode table.  These
+   flags do not correspond to anything in the 68HC11 or 68HC12.
+   They are only used by GAS to recognize operands.  */
+#define M6811_OP_NONE         0        /* No operand */
+#define M6811_OP_DIRECT       0x0001   /* Page 0 addressing:   *<val-8bits>  */
+#define M6811_OP_IMM8         0x0002   /*  8 bits immediat:    #<val-8bits>  */
+#define M6811_OP_IMM16        0x0004   /* 16 bits immediat:    #<val-16bits> */
+#define M6811_OP_IND16        0x0008   /* Indirect abs:        <val-16>      */
+#define M6812_OP_IND16_P2     0x0010   /* Second parameter indirect abs.     */
+#define M6812_OP_REG          0x0020   /* Register operand 1                 */
+#define M6812_OP_REG_2        0x0040   /* Register operand 2                 */
+
+#define M6811_OP_IX           0x0080   /* Indirect IX:         <val-8>,x     */
+#define M6811_OP_IY           0x0100   /* Indirect IY:         <val-8>,y     */
+#define M6812_OP_IDX          0x0200   /* Indirect: N,r N,[+-]r[+-] N:5-bits */
+#define M6812_OP_IDX_1        0x0400   /* N,r N:9-bits  */
+#define M6812_OP_IDX_2        0x0800   /* N,r N:16-bits */
+#define M6812_OP_D_IDX        0x1000   /* Indirect indexed: [D,r] */
+#define M6812_OP_D_IDX_2      0x2000   /* [N,r] N:16-bits */
+#define M6812_OP_PAGE         0x4000   /* Page number */
+#define M6811_OP_MASK         0x07FFF
+#define M6811_OP_BRANCH       0x00008000 /* Branch, jsr, call */
+#define M6811_OP_BITMASK      0x00010000 /* Bitmask:             #<val-8>    */
+#define M6811_OP_JUMP_REL     0x00020000 /* Pc-Relative:         <val-8>     */
+#define M6812_OP_JUMP_REL16   0x00040000 /* Pc-relative:         <val-16>    */
+#define M6811_OP_PAGE1        0x0000
+#define M6811_OP_PAGE2        0x00080000 /* Need a page2 opcode before       */
+#define M6811_OP_PAGE3        0x00100000 /* Need a page3 opcode before       */
+#define M6811_OP_PAGE4        0x00200000 /* Need a page4 opcode before       */
+#define M6811_MAX_OPERANDS    3     /* Max operands: brset <dst> <mask> <b> */
+
+#define M6812_ACC_OFFSET      0x00400000 /* A,r B,r D,r			    */
+#define M6812_ACC_IND         0x00800000 /* [D,r]			    */
+#define M6812_PRE_INC         0x01000000 /* n,+r   n = -8..8		    */
+#define M6812_PRE_DEC         0x02000000 /* n,-r			    */
+#define M6812_POST_INC        0x04000000 /* n,r+			    */
+#define M6812_POST_DEC        0x08000000 /* n,r-			    */
+#define M6812_INDEXED_IND     0x10000000 /* [n,r]  n = 16-bits		    */
+#define M6812_INDEXED         0x20000000 /* n,r    n = 5, 9 or 16-bits	    */
+#define M6812_OP_IDX_P2       0x40000000
+
+/* XGATE defines.
+   These overlap with HC11/12 as above but not used at the same time.  */
+#define M68XG_OP_NONE           0x0001
+#define M68XG_OP_IMM3           0x0002
+#define M68XG_OP_R              0x0004
+#define M68XG_OP_R_R            0x0008
+#define M68XG_OP_R_IMM4         0x0010
+#define M68XG_OP_R_R_R          0x0020
+#define M68XG_OP_REL9           0x0040
+#define M68XG_OP_REL10          0x0080
+#define M68XG_OP_R_R_OFFS5      0x0100
+#define M68XG_OP_RD_RB_RI       0x0200
+#define M68XG_OP_RD_RB_RIp      0x0400
+#define M68XG_OP_RD_RB_mRI      0x0800
+#define M68XG_OP_R_IMM8         0x1000
+#define M68XG_OP_R_IMM16        0x2000
+#define M68XG_OP_REG            0x4000   /* Register operand 1.  */
+#define M68XG_OP_REG_2          0x8000   /* Register operand 2.  */
+#define M68XG_MAX_OPERANDS      3        /* Max operands of triadic r1, r2, r3.  */
+
+/* Markers to identify some instructions.  */
+#define M6812_OP_EXG_MARKER   0x01000000 /* exg r1,r2 */
+#define M6812_OP_TFR_MARKER   0x02000000 /* tfr r1,r2 */
+#define M6812_OP_SEX_MARKER   0x04000000 /* sex r1,r2 */
+
+#define M6812_OP_EQ_MARKER    0x80000000 /* dbeq/ibeq/tbeq */
+#define M6812_OP_DBCC_MARKER  0x04000000 /* dbeq/dbne */
+#define M6812_OP_IBCC_MARKER  0x02000000 /* ibeq/ibne */
+#define M6812_OP_TBCC_MARKER  0x01000000
+
+/* XGATE markers.  */
+#define M68XG_OP_B_MARKER     0x04000000 /* bXX rel9 */
+#define M68XG_OP_BRA_MARKER   0x02000000 /* bra rel10 */
+
+#define M6812_OP_TRAP_ID      0x80000000 /* trap #N */
+
+#define M6811_OP_HIGH_ADDR    0x01000000 /* Used internally by gas.  */
+#define M6811_OP_LOW_ADDR     0x02000000
+
+#define M68HC12_BANK_VIRT       0x010000
+#define M68HC12_BANK_MASK     0x00003fff
+#define M68HC12_BANK_BASE     0x00008000
+#define M68HC12_BANK_SHIFT            14
+#define M68HC12_BANK_PAGE_MASK     0x0ff
+
+
+/* CPU identification.  */
+#define cpu6811 0x01
+#define cpu6812 0x02
+#define cpu6812s 0x04
+#define cpu9s12x 0x08  /* 9S12X main cpu.  */
+#define cpuxgate 0x10  /* The XGATE module itself.  */
+
+/* The opcode table is an array of struct m68hc11_opcode.  */
+struct m68hc11_opcode
+{
+  const char *   name;     /* Op-code name.  */
+  long           format;
+  unsigned char  size;
+  unsigned int   opcode;
+  unsigned char  cycles_low;
+  unsigned char  cycles_high;
+  unsigned char  set_flags_mask;
+  unsigned char  clr_flags_mask;
+  unsigned char  chg_flags_mask;
+  unsigned char  arch;
+  unsigned int   xg_mask; /* Mask with zero in register place for xgate.  */
+};
+
+/* Alias definition for 68HC12.  */
+struct m68hc12_opcode_alias 
+{
+  const char*   name;
+  const char*   translation;
+  unsigned char size;
+  unsigned char code1;
+  unsigned char code2;
+};
+
+/* The opcode table.  The table contains all the opcodes (all pages).
+   You can't rely on the order.  */
+extern const struct m68hc11_opcode m68hc11_opcodes[];
+extern const int m68hc11_num_opcodes;
+
+/* Alias table for 68HC12.  It translates some 68HC11 insn which are not
+   implemented in 68HC12 but have equivalent translations.  */
+extern const struct m68hc12_opcode_alias m68hc12_alias[];
+extern const int m68hc12_num_alias;
+
+#endif /* _OPCODE_M68HC11_H */
diff --git a/binutils-2.25/include/opcode/m68k.h b/binutils-2.25/include/opcode/m68k.h
new file mode 100644
index 00000000..f7bd8b45
--- /dev/null
+++ b/binutils-2.25/include/opcode/m68k.h
@@ -0,0 +1,378 @@
+/* Opcode table header for m680[01234]0/m6888[12]/m68851.
+   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
+   2003, 2004, 2006, 2010 Free Software Foundation, Inc.
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+/* These are used as bit flags for the arch field in the m68k_opcode
+   structure.  */
+#define	_m68k_undef  0
+#define	m68000   0x001
+#define	m68010   0x002
+#define	m68020   0x004
+#define	m68030   0x008
+#define	m68040   0x010
+#define m68060   0x020
+#define	m68881   0x040
+#define	m68851   0x080
+#define cpu32	 0x100		/* e.g., 68332 */
+#define fido_a   0x200
+#define m68k_mask  0x3ff
+
+#define mcfmac   0x400		/* ColdFire MAC. */
+#define mcfemac  0x800		/* ColdFire EMAC. */
+#define cfloat   0x1000		/* ColdFire FPU.  */
+#define mcfhwdiv 0x2000		/* ColdFire hardware divide.  */
+
+#define mcfisa_a 0x4000		/* ColdFire ISA_A.  */
+#define mcfisa_aa 0x8000	/* ColdFire ISA_A+.  */
+#define mcfisa_b 0x10000	/* ColdFire ISA_B.  */
+#define mcfisa_c 0x20000	/* ColdFire ISA_C.  */
+#define mcfusp   0x40000	/* ColdFire USP instructions.  */
+#define mcf_mask 0x7e400
+
+/* Handy aliases.  */
+#define	m68040up   (m68040 | m68060)
+#define	m68030up   (m68030 | m68040up)
+#define	m68020up   (m68020 | m68030up)
+#define	m68010up   (m68010 | cpu32 | fido_a | m68020up)
+#define	m68000up   (m68000 | m68010up)
+
+#define	mfloat  (m68881 | m68040 | m68060)
+#define	mmmu    (m68851 | m68030 | m68040 | m68060)
+
+/* The structure used to hold information for an opcode.  */
+
+struct m68k_opcode
+{
+  /* The opcode name.  */
+  const char *name;
+  /* The pseudo-size of the instruction(in bytes).  Used to determine
+     number of bytes necessary to disassemble the instruction.  */
+  unsigned int size;
+  /* The opcode itself.  */
+  unsigned long opcode;
+  /* The mask used by the disassembler.  */
+  unsigned long match;
+  /* The arguments.  */
+  const char *args;
+  /* The architectures which support this opcode.  */
+  unsigned int arch;
+};
+
+/* The structure used to hold information for an opcode alias.  */
+
+struct m68k_opcode_alias
+{
+  /* The alias name.  */
+  const char *alias;
+  /* The instruction for which this is an alias.  */
+  const char *primary;
+};
+
+/* We store four bytes of opcode for all opcodes because that is the
+   most any of them need.  The actual length of an instruction is
+   always at least 2 bytes, and is as much longer as necessary to hold
+   the operands it has.
+
+   The match field is a mask saying which bits must match particular
+   opcode in order for an instruction to be an instance of that
+   opcode.
+
+   The args field is a string containing two characters for each
+   operand of the instruction.  The first specifies the kind of
+   operand; the second, the place it is stored.
+
+   If the first char of args is '.', it indicates that the opcode is
+   two words.  This is only necessary when the match field does not
+   have any bits set in the second opcode word.  Such a '.' is skipped
+   for operand processing.  */
+
+/* Kinds of operands:
+   Characters used: AaBbCcDdEeFfGgHIiJjKkLlMmnOopQqRrSsTtUuVvWwXxYyZz01234|*~%;@!&$?/<>#^+-
+
+   D  data register only.  Stored as 3 bits.
+   A  address register only.  Stored as 3 bits.
+   a  address register indirect only.  Stored as 3 bits.
+   R  either kind of register.  Stored as 4 bits.
+   r  either kind of register indirect only.  Stored as 4 bits.
+      At the moment, used only for cas2 instruction.
+   F  floating point coprocessor register only.   Stored as 3 bits.
+   O  an offset (or width): immediate data 0-31 or data register.
+      Stored as 6 bits in special format for BF... insns.
+   +  autoincrement only.  Stored as 3 bits (number of the address register).
+   -  autodecrement only.  Stored as 3 bits (number of the address register).
+   Q  quick immediate data.  Stored as 3 bits.
+      This matches an immediate operand only when value is in range 1 .. 8.
+   M  moveq immediate data.  Stored as 8 bits.
+      This matches an immediate operand only when value is in range -128..127
+   T  trap vector immediate data.  Stored as 4 bits.
+
+   k  K-factor for fmove.p instruction.   Stored as a 7-bit constant or
+      a three bit register offset, depending on the field type.
+
+   #  immediate data.  Stored in special places (b, w or l)
+      which say how many bits to store.
+   ^  immediate data for floating point instructions.   Special places
+      are offset by 2 bytes from '#'...
+   B  pc-relative address, converted to an offset
+      that is treated as immediate data.
+   d  displacement and register.  Stores the register as 3 bits
+      and stores the displacement in the entire second word.
+
+   C  the CCR.  No need to store it; this is just for filtering validity.
+   S  the SR.  No need to store, just as with CCR.
+   U  the USP.  No need to store, just as with CCR.
+   E  the MAC ACC.  No need to store, just as with CCR.
+   e  the EMAC ACC[0123].
+   G  the MAC/EMAC MACSR.  No need to store, just as with CCR.
+   g  the EMAC ACCEXT{01,23}.
+   H  the MASK.  No need to store, just as with CCR.
+   i  the MAC/EMAC scale factor.
+
+   I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always
+      extracted from the 'd' field of word one, which means that an extended
+      coprocessor opcode can be skipped using the 'i' place, if needed.
+
+   s  System Control register for the floating point coprocessor.
+
+   J  Misc register for movec instruction, stored in 'j' format.
+	Possible values:
+	0x000	SFC	Source Function Code reg	[60, 40, 30, 20, 10]
+	0x001	DFC	Data Function Code reg		[60, 40, 30, 20, 10]
+	0x002   CACR    Cache Control Register          [60, 40, 30, 20, mcf]
+	0x003	TC	MMU Translation Control		[60, 40]
+	0x004	ITT0	Instruction Transparent
+				Translation reg 0	[60, 40]
+	0x005	ITT1	Instruction Transparent
+				Translation reg 1	[60, 40]
+	0x006	DTT0	Data Transparent
+				Translation reg 0	[60, 40]
+	0x007	DTT1	Data Transparent
+				Translation reg 1	[60, 40]
+	0x008	BUSCR	Bus Control Register		[60]
+	0x800	USP	User Stack Pointer		[60, 40, 30, 20, 10]
+        0x801   VBR     Vector Base reg                 [60, 40, 30, 20, 10, mcf]
+	0x802	CAAR	Cache Address Register		[        30, 20]
+	0x803	MSP	Master Stack Pointer		[    40, 30, 20]
+	0x804	ISP	Interrupt Stack Pointer		[    40, 30, 20]
+	0x805	MMUSR	MMU Status reg			[    40]
+	0x806	URP	User Root Pointer		[60, 40]
+	0x807	SRP	Supervisor Root Pointer		[60, 40]
+	0x808	PCR	Processor Configuration reg	[60]
+	0xC00	ROMBAR	ROM Base Address Register	[520X]
+	0xC04	RAMBAR0	RAM Base Address Register 0	[520X]
+	0xC05	RAMBAR1	RAM Base Address Register 0	[520X]
+	0xC0F	MBAR0	RAM Base Address Register 0	[520X]
+        0xC04   FLASHBAR FLASH Base Address Register    [mcf528x]
+        0xC05   RAMBAR  Static RAM Base Address Register [mcf528x]
+
+    L  Register list of the type d0-d7/a0-a7 etc.
+       (New!  Improved!  Can also hold fp0-fp7, as well!)
+       The assembler tries to see if the registers match the insn by
+       looking at where the insn wants them stored.
+
+    l  Register list like L, but with all the bits reversed.
+       Used for going the other way. . .
+
+    c  cache identifier which may be "nc" for no cache, "ic"
+       for instruction cache, "dc" for data cache, or "bc"
+       for both caches.  Used in cinv and cpush.  Always
+       stored in position "d".
+
+    u  Any register, with ``upper'' or ``lower'' specification.  Used
+       in the mac instructions with size word.
+
+ The remainder are all stored as 6 bits using an address mode and a
+ register number; they differ in which addressing modes they match.
+
+   *  all					(modes 0-6,7.0-4)
+   ~  alterable memory				(modes 2-6,7.0,7.1)
+   						(not 0,1,7.2-4)
+   %  alterable					(modes 0-6,7.0,7.1)
+						(not 7.2-4)
+   ;  data					(modes 0,2-6,7.0-4)
+						(not 1)
+   @  data, but not immediate			(modes 0,2-6,7.0-3)
+						(not 1,7.4)
+   !  control					(modes 2,5,6,7.0-3)
+						(not 0,1,3,4,7.4)
+   &  alterable control				(modes 2,5,6,7.0,7.1)
+						(not 0,1,3,4,7.2-4)
+   $  alterable data				(modes 0,2-6,7.0,7.1)
+						(not 1,7.2-4)
+   ?  alterable control, or data register	(modes 0,2,5,6,7.0,7.1)
+						(not 1,3,4,7.2-4)
+   /  control, or data register			(modes 0,2,5,6,7.0-3)
+						(not 1,3,4,7.4)
+   >  *save operands				(modes 2,4,5,6,7.0,7.1)
+						(not 0,1,3,7.2-4)
+   <  *restore operands				(modes 2,3,5,6,7.0-3)
+						(not 0,1,4,7.4)
+
+   coldfire move operands:
+   m  						(modes 0-4)
+   n						(modes 5,7.2)
+   o						(modes 6,7.0,7.1,7.3,7.4)
+   p						(modes 0-5)
+
+   coldfire bset/bclr/btst/mulsl/mulul operands:
+   q						(modes 0,2-5)
+   v						(modes 0,2-5,7.0,7.1)
+   b                                            (modes 0,2-5,7.2)
+   w                                            (modes 2-5,7.2)
+   y						(modes 2,5)
+   z						(modes 2,5,7.2)
+   x  mov3q immediate operand.
+   j  coprocessor ET operand.
+   K  coprocessor command number.
+   4						(modes 2,3,4,5)
+  */
+
+/* For the 68851:  */
+/* I didn't use much imagination in choosing the
+   following codes, so many of them aren't very
+   mnemonic. -rab
+
+   0  32 bit pmmu register
+	Possible values:
+	000	TC	Translation Control Register (68030, 68851)
+
+   1  16 bit pmmu register
+	111	AC	Access Control (68851)
+
+   2  8 bit pmmu register
+	100	CAL	Current Access Level (68851)
+	101	VAL	Validate Access Level (68851)
+	110	SCC	Stack Change Control (68851)
+
+   3  68030-only pmmu registers (32 bit)
+	010	TT0	Transparent Translation reg 0
+			(aka Access Control reg 0 -- AC0 -- on 68ec030)
+	011	TT1	Transparent Translation reg 1
+			(aka Access Control reg 1 -- AC1 -- on 68ec030)
+
+   W  wide pmmu registers
+	Possible values:
+	001	DRP	Dma Root Pointer (68851)
+	010	SRP	Supervisor Root Pointer (68030, 68851)
+	011	CRP	Cpu Root Pointer (68030, 68851)
+
+   f	function code register (68030, 68851)
+	0	SFC
+	1	DFC
+
+   V	VAL register only (68851)
+
+   X	BADx, BACx (16 bit)
+	100	BAD	Breakpoint Acknowledge Data (68851)
+	101	BAC	Breakpoint Acknowledge Control (68851)
+
+   Y	PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
+   Z	PCSR (68851)
+
+   |	memory 		(modes 2-6, 7.*)
+
+   t  address test level (68030 only)
+      Stored as 3 bits, range 0-7.
+      Also used for breakpoint instruction now.
+
+*/
+
+/* Places to put an operand, for non-general operands:
+   Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
+
+   s  source, low bits of first word.
+   d  dest, shifted 9 in first word
+   1  second word, shifted 12
+   2  second word, shifted 6
+   3  second word, shifted 0
+   4  third word, shifted 12
+   5  third word, shifted 6
+   6  third word, shifted 0
+   7  second word, shifted 7
+   8  second word, shifted 10
+   9  second word, shifted 5
+   E  second word, shifted 9
+   D  store in both place 1 and place 3; for divul and divsl.
+   B  first word, low byte, for branch displacements
+   W  second word (entire), for branch displacements
+   L  second and third words (entire), for branch displacements
+      (also overloaded for move16)
+   b  second word, low byte
+   w  second word (entire) [variable word/long branch offset for dbra]
+   W  second word (entire) (must be signed 16 bit value)
+   l  second and third word (entire)
+   g  variable branch offset for bra and similar instructions.
+      The place to store depends on the magnitude of offset.
+   t  store in both place 7 and place 8; for floating point operations
+   c  branch offset for cpBcc operations.
+      The place to store is word two if bit six of word one is zero,
+      and words two and three if bit six of word one is one.
+   i  Increment by two, to skip over coprocessor extended operands.   Only
+      works with the 'I' format.
+   k  Dynamic K-factor field.   Bits 6-4 of word 2, used as a register number.
+      Also used for dynamic fmovem instruction.
+   C  floating point coprocessor constant - 7 bits.  Also used for static
+      K-factors...
+   j  Movec register #, stored in 12 low bits of second word.
+   m  For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
+      and remaining 3 bits of register shifted 9 bits in first word.
+      Indicate upper/lower in 1 bit shifted 7 bits in second word.
+      Use with `R' or `u' format.
+   n  `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
+      with MSB shifted 6 bits in first word and remaining 3 bits of
+      register shifted 9 bits in first word.  No upper/lower
+      indication is done.)  Use with `R' or `u' format.
+   o  For M[S]ACw; 4 bits shifted 12 in second word (like `1').
+      Indicate upper/lower in 1 bit shifted 7 bits in second word.
+      Use with `R' or `u' format.
+   M  For M[S]ACw; 4 bits in low bits of first word.  Indicate
+      upper/lower in 1 bit shifted 6 bits in second word.  Use with
+      `R' or `u' format.
+   N  For M[S]ACw; 4 bits in low bits of second word.  Indicate
+      upper/lower in 1 bit shifted 6 bits in second word.  Use with
+      `R' or `u' format.
+   h  shift indicator (scale factor), 1 bit shifted 10 in second word
+
+ Places to put operand, for general operands:
+   d  destination, shifted 6 bits in first word
+   b  source, at low bit of first word, and immediate uses one byte
+   w  source, at low bit of first word, and immediate uses two bytes
+   l  source, at low bit of first word, and immediate uses four bytes
+   s  source, at low bit of first word.
+      Used sometimes in contexts where immediate is not allowed anyway.
+   f  single precision float, low bit of 1st word, immediate uses 4 bytes
+   F  double precision float, low bit of 1st word, immediate uses 8 bytes
+   x  extended precision float, low bit of 1st word, immediate uses 12 bytes
+   p  packed float, low bit of 1st word, immediate uses 12 bytes
+   G  EMAC accumulator, load  (bit 4 2nd word, !bit8 first word)
+   H  EMAC accumulator, non load  (bit 4 2nd word, bit 8 first word)
+   F  EMAC ACCx
+   f  EMAC ACCy
+   I  MAC/EMAC scale factor
+   /  Like 's', but set 2nd word, bit 5 if trailing_ampersand set
+   ]  first word, bit 10
+*/
+
+extern const struct m68k_opcode m68k_opcodes[];
+extern const struct m68k_opcode_alias m68k_opcode_aliases[];
+
+extern const int m68k_numopcodes, m68k_numaliases;
+
+/* end of m68k-opcode.h */
diff --git a/binutils-2.25/include/opcode/m88k.h b/binutils-2.25/include/opcode/m88k.h
new file mode 100644
index 00000000..739c0e90
--- /dev/null
+++ b/binutils-2.25/include/opcode/m88k.h
@@ -0,0 +1,455 @@
+/* Table of opcodes for the Motorola M88k family.
+   Copyright 1989, 1990, 1991, 1993, 2001, 2002, 2010
+   Free Software Foundation, Inc.
+
+   This file is part of GDB and GAS.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/*
+ *			Disassembler Instruction Table
+ *
+ *	The first field of the table is the opcode field. If an opcode
+ *	is specified which has any non-opcode bits on, a system error
+ *	will occur when the system attempts the install it into the
+ *	instruction table.  The second parameter is a pointer to the
+ *	instruction mnemonic. Each operand is specified by offset, width,
+ *	and type. The offset is the bit number of the least significant
+ *	bit of the operand with bit 0 being the least significant bit of
+ *	the instruction. The width is the number of bits used to specify
+ *	the operand. The type specifies the output format to be used for
+ *	the operand. The valid formats are: register, register indirect,
+ *	hex constant, and bit field specification.  The last field is a
+ *	pointer to the next instruction in the linked list.  These pointers
+ *	are initialized by init_disasm().
+ *
+ *				Revision History
+ *
+ *	Revision 1.0	11/08/85	Creation date
+ *		 1.1	02/05/86	Updated instruction mnemonic table MD
+ *		 1.2	06/16/86	Updated SIM_FLAGS for floating point
+ *		 1.3	09/20/86	Updated for new encoding
+ *		 	05/11/89	R. Trawick adapted from Motorola disassembler
+ */
+
+#include <stdio.h>
+
+/* Define the number of bits in the primary opcode field of the instruction,
+   the destination field, the source 1 and source 2 fields.  */
+
+/* Size of opcode field.  */
+#define OP 8
+
+/* Size of destination.  */
+#define DEST 6
+
+/* Size of source1.  */
+#define SOURCE1 6
+
+/* Size of source2.  */
+#define SOURCE2 6
+
+/* Number of registers.  */
+#define REGs 32
+
+/* Type definitions.  */
+
+typedef unsigned int UINT;
+#define    WORD    long
+#define    FLAG    unsigned
+#define    STATE   short
+
+/* The next four equates define the priorities that the various classes
+ * of instructions have regarding writing results back into registers and
+ * signalling exceptions.  */
+
+/* PMEM is also defined in <sys/param.h> on Delta 88's.  Sigh!  */
+#undef PMEM
+
+/* Integer priority.  */
+#define    PINT  0
+
+/* Floating point priority.  */
+#define    PFLT  1
+
+/* Memory priority.  */
+#define    PMEM  2
+
+/* Not applicable, instruction doesn't write to regs.  */
+#define    NA    3
+
+/* Highest of these priorities.  */
+#define    HIPRI 3
+
+/* The instruction registers are an artificial mechanism to speed up
+ * simulator execution.  In the real processor, an instruction register
+ * is 32 bits wide.  In the simulator, the 32 bit instruction is kept in
+ * a structure field called rawop, and the instruction is partially decoded,
+ * and split into various fields and flags which make up the other fields
+ * of the structure.
+ * The partial decode is done when the instructions are initially loaded
+ * into simulator memory.  The simulator code memory is not an array of
+ * 32 bit words, but is an array of instruction register structures.
+ * Yes this wastes memory, but it executes much quicker.
+ */
+
+struct IR_FIELDS
+{
+  unsigned op:OP,
+    dest: DEST,
+    src1: SOURCE1,
+    src2: SOURCE2;
+  int ltncy,
+    extime,
+    /* Writeback priority.  */
+    wb_pri;
+  /* Immediate size.  */
+  unsigned        imm_flags:2,
+    /* Register source 1 used.  */
+    rs1_used:1,
+    /* Register source 2 used. */
+    rs2_used:1,
+    /* Register source/dest. used.  */
+    rsd_used:1,
+    /* Complement.  */
+    c_flag:1,
+    /* Upper half word.  */
+    u_flag:1,
+    /* Execute next.  */
+    n_flag:1,
+    /* Uses writeback slot.  */
+    wb_flag:1,
+    /* Dest size.  */
+    dest_64:1,
+    /* Source 1 size.  */
+    s1_64:1,
+    /* Source 2 size.  */
+    s2_64:1,
+    scale_flag:1,
+    /* Scaled register.  */
+    brk_flg:1;
+};
+
+struct	mem_segs
+{
+  /* Pointer (returned by calloc) to segment.  */
+  struct mem_wrd *seg;			
+
+  /* Base load address from file headers.  */
+  unsigned long baseaddr;			
+
+  /* Ending address of segment.  */
+  unsigned long endaddr;		
+
+  /* Segment control flags (none defined).  */	
+  int	      flags;			
+};
+
+#define	MAXSEGS		(10)			/* max number of segment allowed */
+#define	MEMSEGSIZE	(sizeof(struct mem_segs))/* size of mem_segs structure */
+
+#if 0
+#define BRK_RD		(0x01)			/* break on memory read */
+#define BRK_WR		(0x02)			/* break on memory write */
+#define BRK_EXEC	(0x04)			/* break on execution */
+#define	BRK_CNT		(0x08)			/* break on terminal count */
+#endif
+
+struct mem_wrd
+{
+  /* Simulator instruction break down.  */
+  struct IR_FIELDS opcode;
+  union {
+    /* Memory element break down.  */
+    unsigned long  l;
+    unsigned short s[2];
+    unsigned char  c[4];
+  } mem;
+};
+
+/* Size of each 32 bit memory model.  */
+#define	MEMWRDSIZE	(sizeof (struct mem_wrd))
+
+extern struct mem_segs memory[];
+extern struct PROCESSOR m78000;
+
+struct PROCESSOR
+{
+  unsigned WORD
+  /* Execute instruction pointer.  */
+  ip, 
+    /* Vector base register.  */
+    vbr,
+    /* Processor status register.  */
+    psr;
+  
+  /* Source 1.  */
+  WORD    S1bus,
+    /* Source 2.  */
+    S2bus,
+    /* Destination.  */
+    Dbus,
+    /* Data address bus.  */
+    DAbus,
+    ALU,
+    /* Data registers.  */
+    Regs[REGs],
+    /* Max clocks before reg is available.  */
+    time_left[REGs],
+    /* Writeback priority of reg.  */
+    wb_pri[REGs], 
+    /* Integer unit control regs.  */
+    SFU0_regs[REGs],
+    /* Floating point control regs.  */
+    SFU1_regs[REGs], 
+    Scoreboard[REGs],
+    Vbr;
+  unsigned WORD   scoreboard,
+    Psw,
+    Tpsw;
+  /* Waiting for a jump instruction.  */
+  FLAG   jump_pending:1;
+};
+
+/* Size of immediate field.  */
+
+#define    i26bit      1
+#define    i16bit      2
+#define    i10bit      3
+
+/* Definitions for fields in psr.  */
+
+#define psr_mode  31
+#define psr_rbo   30
+#define psr_ser   29
+#define psr_carry 28
+#define psr_sf7m  11
+#define psr_sf6m  10
+#define psr_sf5m   9
+#define psr_sf4m   8
+#define psr_sf3m   7
+#define psr_sf2m   6
+#define psr_sf1m   5
+#define psr_mam    4
+#define psr_inm    3
+#define psr_exm    2
+#define psr_trm    1
+#define psr_ovfm   0
+
+/* The 1 clock operations.  */
+
+#define    ADDU        1
+#define    ADDC        2
+#define    ADDUC       3
+#define    ADD         4
+
+#define    SUBU    ADD+1
+#define    SUBB    ADD+2
+#define    SUBUB   ADD+3
+#define    SUB     ADD+4
+
+#define    AND_    ADD+5
+#define    OR      ADD+6
+#define    XOR     ADD+7
+#define    CMP     ADD+8
+
+/* Loads.  */
+
+#define    LDAB    CMP+1
+#define    LDAH    CMP+2
+#define    LDA     CMP+3
+#define    LDAD    CMP+4
+
+#define    LDB   LDAD+1
+#define    LDH   LDAD+2
+#define    LD    LDAD+3
+#define    LDD   LDAD+4
+#define    LDBU  LDAD+5
+#define    LDHU  LDAD+6
+
+/* Stores.  */
+
+#define    STB    LDHU+1
+#define    STH    LDHU+2
+#define    ST     LDHU+3
+#define    STD    LDHU+4
+
+/* Exchange.  */
+
+#define    XMEMBU LDHU+5
+#define    XMEM   LDHU+6
+
+/* Branches.  */
+
+#define    JSR    STD+1
+#define    BSR    STD+2
+#define    BR     STD+3
+#define    JMP    STD+4
+#define    BB1    STD+5
+#define    BB0    STD+6
+#define    RTN    STD+7
+#define    BCND   STD+8
+
+/* Traps.  */
+
+#define    TB1    BCND+1
+#define    TB0    BCND+2
+#define    TCND   BCND+3
+#define    RTE    BCND+4
+#define    TBND   BCND+5
+
+/* Misc.  */
+
+#define    MUL     TBND + 1
+#define    DIV     MUL  +2
+#define    DIVU    MUL  +3
+#define    MASK    MUL  +4
+#define    FF0     MUL  +5
+#define    FF1     MUL  +6
+#define    CLR     MUL  +7
+#define    SET     MUL  +8
+#define    EXT     MUL  +9
+#define    EXTU    MUL  +10
+#define    MAK     MUL  +11
+#define    ROT     MUL  +12
+
+/* Control register manipulations.  */
+
+#define    LDCR    ROT  +1
+#define    STCR    ROT  +2
+#define    XCR     ROT  +3
+
+#define    FLDCR    ROT  +4
+#define    FSTCR    ROT  +5
+#define    FXCR     ROT  +6
+
+#define    NOP     XCR +1
+
+/* Floating point instructions.  */
+
+#define    FADD    NOP +1
+#define    FSUB    NOP +2
+#define    FMUL    NOP +3
+#define    FDIV    NOP +4
+#define    FSQRT   NOP +5
+#define    FCMP    NOP +6
+#define    FIP     NOP +7
+#define    FLT     NOP +8
+#define    INT     NOP +9
+#define    NINT    NOP +10
+#define    TRNC    NOP +11
+#define    FLDC   NOP +12
+#define    FSTC   NOP +13
+#define    FXC    NOP +14
+
+#define UEXT(src,off,wid) \
+  ((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1))
+
+#define SEXT(src,off,wid) \
+  (((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) )
+
+#define MAKE(src,off,wid) \
+  ((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off))
+
+#define opword(n) (unsigned long) (memaddr->mem.l)
+
+/* Constants and masks.  */
+
+#define SFU0       0x80000000
+#define SFU1       0x84000000
+#define SFU7       0x9c000000
+#define RRI10      0xf0000000
+#define RRR        0xf4000000
+#define SFUMASK    0xfc00ffe0
+#define RRRMASK    0xfc00ffe0
+#define RRI10MASK  0xfc00fc00
+#define DEFMASK    0xfc000000
+#define CTRL       0x0000f000
+#define CTRLMASK   0xfc00f800
+
+/* Operands types.  */
+
+enum operand_type
+{
+  HEX = 1,
+  REG = 2,
+  CONT = 3,
+  IND = 3,
+  BF = 4,
+  /* Scaled register.  */
+  REGSC = 5,
+  /* Control register.  */
+  CRREG = 6,
+  /* Floating point control register.  */
+  FCRREG = 7,
+  PCREL = 8,
+  CONDMASK = 9,
+  /* Extended register.  */
+  XREG = 10,
+  /* Decimal.  */
+  DEC = 11
+};
+
+/* Hashing specification.  */
+
+#define HASHVAL     79
+
+/* Structure templates.  */
+
+typedef struct
+{
+  unsigned int offset;
+  unsigned int width;
+  enum operand_type type;
+} OPSPEC;
+
+struct SIM_FLAGS
+{
+  int  ltncy,   /* latency (max number of clocks needed to execute).  */
+    extime,   /* execution time (min number of clocks needed to execute).  */
+    wb_pri;   /* writeback slot priority.  */
+  unsigned         op:OP,   /* simulator version of opcode.  */
+    imm_flags:2,   /* 10,16 or 26 bit immediate flags.  */
+    rs1_used:1,   /* register source 1 used.  */
+    rs2_used:1,   /* register source 2 used.  */
+    rsd_used:1,   /* register source/dest used.  */
+    c_flag:1,   /* complement.  */
+    u_flag:1,   /* upper half word.  */
+    n_flag:1,   /* execute next.  */
+    wb_flag:1,   /* uses writeback slot.  */
+    dest_64:1,   /* double precision dest.  */
+    s1_64:1,   /* double precision source 1.  */
+    s2_64:1,   /* double precision source 2.  */
+    scale_flag:1;   /* register is scaled.  */
+};
+
+typedef struct INSTRUCTAB {
+  unsigned int  opcode;
+  char          *mnemonic;
+  OPSPEC        op1,op2,op3;
+  struct SIM_FLAGS flgs;
+} INSTAB;
+
+
+#define NO_OPERAND {0,0,0}
+
+extern const INSTAB  instructions[];
+
+/*
+ * Local Variables:
+ * fill-column: 131
+ * End:
+ */
diff --git a/binutils-2.25/include/opcode/metag.h b/binutils-2.25/include/opcode/metag.h
new file mode 100644
index 00000000..c9bb6680
--- /dev/null
+++ b/binutils-2.25/include/opcode/metag.h
@@ -0,0 +1,2079 @@
+/* Imagination Technologies Meta opcode table.
+   Copyright (C) 2013 Free Software Foundation, Inc.
+   Contributed by Imagination Technologies Ltd.
+
+   This file is part of GDB and GAS.
+
+   GDB and GAS are free software; you can redistribute it and/or
+   modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 3, or (at
+   your option) any later version.
+
+   GDB and GAS are distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GDB or GAS; see the file COPYING3.  If not, write to the
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+enum metag_unit
+{
+  UNIT_CT,
+  UNIT_D0,
+  UNIT_D1,
+  UNIT_A0,
+  UNIT_A1,
+  UNIT_PC,
+  UNIT_RD,
+  UNIT_TR,
+  UNIT_TT,
+  UNIT_FX,
+  UNIT_DT,			/* DSP Template Table */
+  UNIT_ACC_D0,
+  UNIT_ACC_D1,
+  UNIT_RAM_D0,
+  UNIT_RAM_D1,
+};
+
+typedef struct
+{
+  const char *     name;
+  enum metag_unit  unit;
+  unsigned int     no;
+} metag_reg;
+
+static const metag_reg metag_regtab[] =
+  {
+    { "TXENABLE",   UNIT_CT,  0 },
+    { "CT.0",       UNIT_CT,  0 },
+    { "TXMODE",     UNIT_CT,  1 },
+    { "CT.1",       UNIT_CT,  1 },
+    { "TXSTATUS",   UNIT_CT,  2 },
+    { "CT.2",       UNIT_CT,  2 },
+    { "TXRPT",      UNIT_CT,  3 },
+    { "CT.3",       UNIT_CT,  3 },
+    { "TXTIMER",    UNIT_CT,  4 },
+    { "CT.4",       UNIT_CT,  4 },
+    { "TXL1START",  UNIT_CT,  5 },
+    { "CT.5",       UNIT_CT,  5 },
+    { "TXL1END",    UNIT_CT,  6 },
+    { "CT.6",       UNIT_CT,  6 },
+    { "TXL1COUNT",  UNIT_CT,  7 },
+    { "CT.7",       UNIT_CT,  7 },
+    { "TXL2START",  UNIT_CT,  8 },
+    { "CT.8",       UNIT_CT,  8 },
+    { "TXL2END",    UNIT_CT,  9 },
+    { "CT.9",       UNIT_CT,  9 },
+    { "TXL2COUNT",  UNIT_CT, 10 },
+    { "CT.10",      UNIT_CT, 10 },
+    { "TXBPOBITS",  UNIT_CT, 11 },
+    { "CT.11",      UNIT_CT, 11 },
+    { "TXMRSIZE",   UNIT_CT, 12 },
+    { "CT.12",      UNIT_CT, 12 },
+    { "TXTIMERI",   UNIT_CT, 13 },
+    { "CT.13",      UNIT_CT, 13 },
+    { "TXDRCTRL",   UNIT_CT, 14 },
+    { "CT.14",      UNIT_CT, 14 },
+    { "TXDRSIZE",   UNIT_CT, 15 },
+    { "CT.15",      UNIT_CT, 15 },
+    { "TXCATCH0",   UNIT_CT, 16 },
+    { "CT.16",      UNIT_CT, 16 },
+    { "TXCATCH1",   UNIT_CT, 17 },
+    { "CT.17",      UNIT_CT, 17 },
+    { "TXCATCH2",   UNIT_CT, 18 },
+    { "CT.18",      UNIT_CT, 18 },
+    { "TXCATCH3",   UNIT_CT, 19 },
+    { "CT.19",      UNIT_CT, 19 },
+    { "TXDEFR",     UNIT_CT, 20 },
+    { "CT.20",      UNIT_CT, 20 },
+    { "TXCPRS",     UNIT_CT, 21 },
+    { "CT.21",      UNIT_CT, 21 },
+    { "TXCLKCTRL",  UNIT_CT, 22 },
+    { "CT.22",      UNIT_CT, 22 },
+    { "TXINTERN0",  UNIT_CT, 23 },
+    { "TXSTATE",    UNIT_CT, 23 },
+    { "CT.23",      UNIT_CT, 23 },
+    { "TXAMAREG0",  UNIT_CT, 24 },
+    { "CT.24",      UNIT_CT, 24 },
+    { "TXAMAREG1",  UNIT_CT, 25 },
+    { "CT.25",      UNIT_CT, 25 },
+    { "TXAMAREG2",  UNIT_CT, 26 },
+    { "CT.26",      UNIT_CT, 26 },
+    { "TXAMAREG3",  UNIT_CT, 27 },
+    { "CT.27",      UNIT_CT, 27 },
+    { "TXDIVTIME",  UNIT_CT, 28 },
+    { "CT.28",      UNIT_CT, 28 },
+    { "TXPRIVEXT",  UNIT_CT, 29 },
+    { "CT.29",      UNIT_CT, 29 },
+    { "TXTACTCYC",  UNIT_CT, 30 },
+    { "TXACTCYC",   UNIT_CT, 30 },
+    { "CT.30",      UNIT_CT, 30 },
+    { "TXIDLECYC",  UNIT_CT, 31 },
+    { "CT.31",      UNIT_CT, 31 },
+
+    { "D0Re0",      UNIT_D0,  0 },
+    { "D0.0",       UNIT_D0,  0 },
+    { "D0Ar6",      UNIT_D0,  1 },
+    { "D0.1",       UNIT_D0,  1 },
+    { "D0Ar4",      UNIT_D0,  2 },
+    { "D0.2",       UNIT_D0,  2 },
+    { "D0Ar2",      UNIT_D0,  3 },
+    { "D0.3",       UNIT_D0,  3 },
+    { "D0FrT",      UNIT_D0,  4 },
+    { "D0.4",       UNIT_D0,  4 },
+    { "D0.5",       UNIT_D0,  5 },
+    { "D0.6",       UNIT_D0,  6 },
+    { "D0.7",       UNIT_D0,  7 },
+    { "D0.8",       UNIT_D0,  8 },
+    { "D0.9",       UNIT_D0,  9 },
+    { "D0.10",      UNIT_D0, 10 },
+    { "D0.11",      UNIT_D0, 11 },
+    { "D0.12",      UNIT_D0, 12 },
+    { "D0.13",      UNIT_D0, 13 },
+    { "D0.14",      UNIT_D0, 14 },
+    { "D0.15",      UNIT_D0, 15 },
+    { "D0.16",      UNIT_D0, 16 },
+    { "D0.17",      UNIT_D0, 17 },
+    { "D0.18",      UNIT_D0, 18 },
+    { "D0.19",      UNIT_D0, 19 },
+    { "D0.20",      UNIT_D0, 20 },
+    { "D0.21",      UNIT_D0, 21 },
+    { "D0.22",      UNIT_D0, 22 },
+    { "D0.23",      UNIT_D0, 23 },
+    { "D0.24",      UNIT_D0, 24 },
+    { "D0.25",      UNIT_D0, 25 },
+    { "D0.26",      UNIT_D0, 26 },
+    { "D0.27",      UNIT_D0, 27 },
+    { "D0.28",      UNIT_D0, 28 },
+    { "D0.29",      UNIT_D0, 29 },
+    { "D0.30",      UNIT_D0, 30 },
+    { "D0.31",      UNIT_D0, 31 },
+
+    { "D1Re0",      UNIT_D1,  0 },
+    { "D1.0",       UNIT_D1,  0 },
+    { "D1Ar5",      UNIT_D1,  1 },
+    { "D1.1",       UNIT_D1,  1 },
+    { "D1Ar3",      UNIT_D1,  2 },
+    { "D1.2",       UNIT_D1,  2 },
+    { "D1Ar1",      UNIT_D1,  3 },
+    { "D1.3",       UNIT_D1,  3 },
+    { "D1RtP",      UNIT_D1,  4 },
+    { "D1.4",       UNIT_D1,  4 },
+    { "D1.5",       UNIT_D1,  5 },
+    { "D1.6",       UNIT_D1,  6 },
+    { "D1.7",       UNIT_D1,  7 },
+    { "D1.8",       UNIT_D1,  8 },
+    { "D1.9",       UNIT_D1,  9 },
+    { "D1.10",      UNIT_D1, 10 },
+    { "D1.11",      UNIT_D1, 11 },
+    { "D1.12",      UNIT_D1, 12 },
+    { "D1.13",      UNIT_D1, 13 },
+    { "D1.14",      UNIT_D1, 14 },
+    { "D1.15",      UNIT_D1, 15 },
+    { "D1.16",      UNIT_D1, 16 },
+    { "D1.17",      UNIT_D1, 17 },
+    { "D1.18",      UNIT_D1, 18 },
+    { "D1.19",      UNIT_D1, 19 },
+    { "D1.20",      UNIT_D1, 20 },
+    { "D1.21",      UNIT_D1, 21 },
+    { "D1.22",      UNIT_D1, 22 },
+    { "D1.23",      UNIT_D1, 23 },
+    { "D1.24",      UNIT_D1, 24 },
+    { "D1.25",      UNIT_D1, 25 },
+    { "D1.26",      UNIT_D1, 26 },
+    { "D1.27",      UNIT_D1, 27 },
+    { "D1.28",      UNIT_D1, 28 },
+    { "D1.29",      UNIT_D1, 29 },
+    { "D1.30",      UNIT_D1, 30 },
+    { "D1.31",      UNIT_D1, 31 },
+
+    { "A0StP",      UNIT_A0,  0 },
+    { "A0.0",       UNIT_A0,  0 },
+    { "A0FrP",      UNIT_A0,  1 },
+    { "A0.1",       UNIT_A0,  1 },
+    { "A0.2",       UNIT_A0,  2 },
+    { "A0.3",       UNIT_A0,  3 },
+    { "A0.4",       UNIT_A0,  4 },
+    { "A0.5",       UNIT_A0,  5 },
+    { "A0.6",       UNIT_A0,  6 },
+    { "A0.7",       UNIT_A0,  7 },
+    { "A0.8",       UNIT_A0,  8 },
+    { "A0.9",       UNIT_A0,  9 },
+    { "A0.10",      UNIT_A0, 10 },
+    { "A0.11",      UNIT_A0, 11 },
+    { "A0.12",      UNIT_A0, 12 },
+    { "A0.13",      UNIT_A0, 13 },
+    { "A0.14",      UNIT_A0, 14 },
+    { "A0.15",      UNIT_A0, 15 },
+    { "CPC0",       UNIT_A0, 16 },
+
+    { "A1GbP",      UNIT_A1,  0 },
+    { "A1.0",       UNIT_A1,  0 },
+    { "A1LbP",      UNIT_A1,  1 },
+    { "A1.1",       UNIT_A1,  1 },
+    { "A1.2",       UNIT_A1,  2 },
+    { "A1.3",       UNIT_A1,  3 },
+    { "A1.4",       UNIT_A1,  4 },
+    { "A1.5",       UNIT_A1,  5 },
+    { "A1.6",       UNIT_A1,  6 },
+    { "A1.7",       UNIT_A1,  7 },
+    { "A1.8",       UNIT_A1,  8 },
+    { "A1.9",       UNIT_A1,  9 },
+    { "A1.10",      UNIT_A1, 10 },
+    { "A1.11",      UNIT_A1, 11 },
+    { "A1.12",      UNIT_A1, 12 },
+    { "A1.13",      UNIT_A1, 13 },
+    { "A1.14",      UNIT_A1, 14 },
+    { "A1.15",      UNIT_A1, 15 },
+    { "CPC1",       UNIT_A1, 16 },
+
+    { "PC",         UNIT_PC,  0 },
+    { "PCX",        UNIT_PC,  1 },
+
+    { "RD",         UNIT_RD,  0 },
+    { "RA",         UNIT_RD, 16 },
+    { "RD",         UNIT_RD, 16 },
+    { "RAPF",       UNIT_RD, 17 },
+    { "RAM8X32",    UNIT_RD, 22 },
+    { "RAM8X",      UNIT_RD, 23 },
+    { "RABZ",       UNIT_RD, 24 },
+    { "RAWZ",       UNIT_RD, 25 },
+    { "RADZ",       UNIT_RD, 26 },
+    { "RABX",       UNIT_RD, 28 },
+    { "RAWX",       UNIT_RD, 29 },
+    { "RADX",       UNIT_RD, 30 },
+    { "RAMX",       UNIT_RD, 31 },
+    { "RAM16X",     UNIT_RD, 31 },
+
+    { "TXSTAT",     UNIT_TR,  0 },
+    { "TR.0",       UNIT_TR,  0 },
+    { "TXMASK",     UNIT_TR,  1 },
+    { "TR.1",       UNIT_TR,  1 },
+    { "TXSTATI",    UNIT_TR,  2 },
+    { "TR.2",       UNIT_TR,  2 },
+    { "TXMASKI",    UNIT_TR,  3 },
+    { "TR.3",       UNIT_TR,  3 },
+    { "TXPOLL",     UNIT_TR,  4 },
+    { "TR.4",       UNIT_TR,  4 },
+    { "TXGPIOI",    UNIT_TR,  5 },
+    { "TR.5",       UNIT_TR,  5 },
+    { "TXPOLLI",    UNIT_TR,  6 },
+    { "TR.6",       UNIT_TR,  6 },
+    { "TXGPIOO",    UNIT_TR,  7 },
+    { "TR.7",       UNIT_TR,  7 },
+
+    { "TTEXEC",     UNIT_TT,  0 },
+    { "TT.0",       UNIT_TT,  0 },
+    { "TTCTRL",     UNIT_TT,  1 },
+    { "TT.1",       UNIT_TT,  1 },
+    { "TTMARK",     UNIT_TT,  2 },
+    { "TT.2",       UNIT_TT,  2 },
+    { "TTREC",      UNIT_TT,  3 },
+    { "TT.3",       UNIT_TT,  3 },
+    { "GTEXEC",     UNIT_TT,  4 },
+    { "TT.4",       UNIT_TT,  4 },
+
+    { "FX.0",       UNIT_FX,  0 },
+    { "FX.1",       UNIT_FX,  1 },
+    { "FX.2",       UNIT_FX,  2 },
+    { "FX.3",       UNIT_FX,  3 },
+    { "FX.4",       UNIT_FX,  4 },
+    { "FX.5",       UNIT_FX,  5 },
+    { "FX.6",       UNIT_FX,  6 },
+    { "FX.7",       UNIT_FX,  7 },
+    { "FX.8",       UNIT_FX,  8 },
+    { "FX.9",       UNIT_FX,  9 },
+    { "FX.10",      UNIT_FX, 10 },
+    { "FX.11",      UNIT_FX, 11 },
+    { "FX.12",      UNIT_FX, 12 },
+    { "FX.13",      UNIT_FX, 13 },
+    { "FX.14",      UNIT_FX, 14 },
+    { "FX.15",      UNIT_FX, 15 },
+  };
+
+static const metag_reg metag_dsp_regtab[] =
+  {
+    { "D0AR.0",   UNIT_RAM_D0,  0 },
+    { "D0AR.1",   UNIT_RAM_D0,  1 },
+    { "D0AW.0",   UNIT_RAM_D0,  2 },
+    { "D0AW.1",   UNIT_RAM_D0,  3 },
+    { "D0BR.0",   UNIT_RAM_D0,  4 },
+    { "D0BR.1",   UNIT_RAM_D0,  5 },
+    { "D0BW.0",   UNIT_RAM_D0,  6 },
+    { "D0BW.1",   UNIT_RAM_D0,  7 },
+    { "D0ARI.0",  UNIT_RAM_D0,  8 },
+    { "D0ARI.1",  UNIT_RAM_D0,  9 },
+    { "D0AWI.0",  UNIT_RAM_D0, 10 },
+    { "D0AWI.1",  UNIT_RAM_D0, 11 },
+    { "D0BRI.0",  UNIT_RAM_D0, 12 },
+    { "D0BRI.1",  UNIT_RAM_D0, 13 },
+    { "D0BWI.0",  UNIT_RAM_D0, 14 },
+    { "D0BWI.1",  UNIT_RAM_D0, 15 },
+
+    { "AC0.0",    UNIT_ACC_D0, 16 },
+    { "AC0.1",    UNIT_ACC_D0, 17 },
+    { "AC0.2",    UNIT_ACC_D0, 18 },
+    { "AC0.3",    UNIT_ACC_D0, 19 },
+
+    { "D1AR.0",   UNIT_RAM_D1,  0 },
+    { "D1AR.1",   UNIT_RAM_D1,  1 },
+    { "D1AW.0",   UNIT_RAM_D1,  2 },
+    { "D1AW.1",   UNIT_RAM_D1,  3 },
+    { "D1BR.0",   UNIT_RAM_D1,  4 },
+    { "D1BR.1",   UNIT_RAM_D1,  5 },
+    { "D1BW.0",   UNIT_RAM_D1,  6 },
+    { "D1BW.1",   UNIT_RAM_D1,  7 },
+    { "D1ARI.0",  UNIT_RAM_D1,  8 },
+    { "D1ARI.1",  UNIT_RAM_D1,  9 },
+    { "D1AWI.0",  UNIT_RAM_D1, 10 },
+    { "D1AWI.1",  UNIT_RAM_D1, 11 },
+    { "D1BRI.0",  UNIT_RAM_D1, 12 },
+    { "D1BRI.1",  UNIT_RAM_D1, 13 },
+    { "D1BWI.0",  UNIT_RAM_D1, 14 },
+    { "D1BWI.1",  UNIT_RAM_D1, 15 },
+
+    { "AC1.0",    UNIT_ACC_D1, 16 },
+    { "AC1.1",    UNIT_ACC_D1, 17 },
+    { "AC1.2",    UNIT_ACC_D1, 18 },
+    { "AC1.3",    UNIT_ACC_D1, 19 },
+
+    { "T0",       UNIT_DT,  0 },
+    { "T1",       UNIT_DT,  1 },
+    { "T2",       UNIT_DT,  2 },
+    { "T3",       UNIT_DT,  3 },
+    { "T4",       UNIT_DT,  4 },
+    { "T5",       UNIT_DT,  5 },
+    { "T6",       UNIT_DT,  6 },
+    { "T7",       UNIT_DT,  7 },
+    { "T8",       UNIT_DT,  8 },
+    { "T9",       UNIT_DT,  9 },
+    { "TA",       UNIT_DT, 10 },
+    { "TB",       UNIT_DT, 11 },
+    { "TC",       UNIT_DT, 12 },
+    { "TD",       UNIT_DT, 13 },
+    { "TE",       UNIT_DT, 14 },
+    { "TF",       UNIT_DT, 15 },
+  };
+
+/* This table differs from 'metag_dsp_regtab' in that the number
+   fields in this table are suitable for insertion into DSPRAM
+   template definition instruction encodings.
+
+   The table is indexed by "load". The main benefit of this is that we
+   can implicitly check that the correct DSPRAM register has been used
+   when parsing, e.g. the read pointer only appears in the load table
+   and the write pointer only exists in the store table.
+
+   The ordering of the table entries might look a bit weird but it is
+   based on matching the longest register string. */
+static const metag_reg metag_dsp_tmpl_regtab[2][56] =
+  {
+    {
+      { "D0AW.0+D0AWI.0++", UNIT_RAM_D0, 18 },
+      { "D0AW.0+D0AWI.0",   UNIT_RAM_D0, 18 },
+      { "D0AW.0+D0AWI.1++", UNIT_RAM_D0, 19 },
+      { "D0AW.0+D0AWI.1",   UNIT_RAM_D0, 19 },
+      { "D0AW.0++",         UNIT_RAM_D0, 17 },
+      { "D0AW.0",           UNIT_RAM_D0, 16 },
+      { "D0AWI.0",          UNIT_RAM_D0, 18 },
+      { "D0AWI.1",          UNIT_RAM_D0, 19 },
+      { "D0AW.1+D0AWI.0++", UNIT_RAM_D0, 22 },
+      { "D0AW.1+D0AWI.0",   UNIT_RAM_D0, 22 },
+      { "D0AW.1+D0AWI.1++", UNIT_RAM_D0, 23 },
+      { "D0AW.1+D0AWI.1",   UNIT_RAM_D0, 23 },
+      { "D0AW.1++",         UNIT_RAM_D0, 21 },
+      { "D0AW.1",           UNIT_RAM_D0, 20 },
+      { "D0BW.0+D0BWI.0++", UNIT_RAM_D0, 26 },
+      { "D0BW.0+D0BWI.0",   UNIT_RAM_D0, 26 },
+      { "D0BW.0+D0BWI.1++", UNIT_RAM_D0, 27 },
+      { "D0BW.0+D0BWI.1",   UNIT_RAM_D0, 27 },
+      { "D0BW.0++",         UNIT_RAM_D0, 25 },
+      { "D0BW.0",           UNIT_RAM_D0, 24 },
+      { "D0BWI.0",          UNIT_RAM_D0, 18 },
+      { "D0BWI.1",          UNIT_RAM_D0, 19 },
+      { "D0BW.1+D0BWI.0++", UNIT_RAM_D0, 30 },
+      { "D0BW.1+D0BWI.0",   UNIT_RAM_D0, 30 },
+      { "D0BW.1+D0BWI.1++", UNIT_RAM_D0, 31 },
+      { "D0BW.1+D0BWI.1",   UNIT_RAM_D0, 31 },
+      { "D0BW.1++",         UNIT_RAM_D0, 29 },
+      { "D0BW.1",           UNIT_RAM_D0, 28 },
+
+      { "D1AW.0+D1AWI.0++", UNIT_RAM_D1, 18 },
+      { "D1AW.0+D1AWI.0",   UNIT_RAM_D1, 18 },
+      { "D1AW.0+D1AWI.1++", UNIT_RAM_D1, 19 },
+      { "D1AW.0+D1AWI.1",   UNIT_RAM_D1, 19 },
+      { "D1AW.0++",         UNIT_RAM_D1, 17 },
+      { "D1AW.0",           UNIT_RAM_D1, 16 },
+      { "D1AWI.0",          UNIT_RAM_D1, 18 },
+      { "D1AWI.1",          UNIT_RAM_D1, 19 },
+      { "D1AW.1+D1AWI.0++", UNIT_RAM_D1, 22 },
+      { "D1AW.1+D1AWI.0",   UNIT_RAM_D1, 22 },
+      { "D1AW.1+D1AWI.1++", UNIT_RAM_D1, 23 },
+      { "D1AW.1+D1AWI.1",   UNIT_RAM_D1, 23 },
+      { "D1AW.1++",         UNIT_RAM_D1, 21 },
+      { "D1AW.1",           UNIT_RAM_D1, 20 },
+      { "D1BW.0+D1BWI.0++", UNIT_RAM_D1, 26 },
+      { "D1BW.0+D1BWI.0",   UNIT_RAM_D1, 26 },
+      { "D1BW.0+D1BWI.1++", UNIT_RAM_D1, 27 },
+      { "D1BW.0+D1BWI.1",   UNIT_RAM_D1, 27 },
+      { "D1BW.0++",         UNIT_RAM_D1, 25 },
+      { "D1BW.0",           UNIT_RAM_D1, 24 },
+      { "D1BWI.0",          UNIT_RAM_D1, 18 },
+      { "D1BWI.1",          UNIT_RAM_D1, 19 },
+      { "D1BW.1+D1BWI.0++", UNIT_RAM_D1, 30 },
+      { "D1BW.1+D1BWI.0",   UNIT_RAM_D1, 30 },
+      { "D1BW.1+D1BWI.1++", UNIT_RAM_D1, 31 },
+      { "D1BW.1+D1BWI.1",   UNIT_RAM_D1, 31 },
+      { "D1BW.1++",         UNIT_RAM_D1, 29 },
+      { "D1BW.1",           UNIT_RAM_D1, 28 },
+    },
+
+    {
+      { "D0AR.0+D0ARI.0++", UNIT_RAM_D0, 18 },
+      { "D0AR.0+D0ARI.0",   UNIT_RAM_D0, 18 },
+      { "D0AR.0+D0ARI.1++", UNIT_RAM_D0, 19 },
+      { "D0AR.0+D0ARI.1",   UNIT_RAM_D0, 19 },
+      { "D0AR.0++",         UNIT_RAM_D0, 17 },
+      { "D0AR.0",           UNIT_RAM_D0, 16 },
+      { "D0ARI.0",          UNIT_RAM_D0, 18 },
+      { "D0ARI.1",          UNIT_RAM_D0, 19 },
+      { "D0AR.1+D0ARI.0++", UNIT_RAM_D0, 22 },
+      { "D0AR.1+D0ARI.0",   UNIT_RAM_D0, 22 },
+      { "D0AR.1+D0ARI.1++", UNIT_RAM_D0, 23 },
+      { "D0AR.1+D0ARI.1",   UNIT_RAM_D0, 23 },
+      { "D0AR.1++",         UNIT_RAM_D0, 21 },
+      { "D0AR.1",           UNIT_RAM_D0, 20 },
+      { "D0BR.0+D0BRI.0++", UNIT_RAM_D0, 26 },
+      { "D0BR.0+D0BRI.0",   UNIT_RAM_D0, 26 },
+      { "D0BR.0+D0BRI.1++", UNIT_RAM_D0, 27 },
+      { "D0BR.0+D0BRI.1",   UNIT_RAM_D0, 27 },
+      { "D0BR.0++",         UNIT_RAM_D0, 25 },
+      { "D0BR.0",           UNIT_RAM_D0, 24 },
+      { "D0BRI.0",          UNIT_RAM_D0, 18 },
+      { "D0BRI.1",          UNIT_RAM_D0, 19 },
+      { "D0BR.1+D0BRI.0++", UNIT_RAM_D0, 30 },
+      { "D0BR.1+D0BRI.0",   UNIT_RAM_D0, 30 },
+      { "D0BR.1+D0BRI.1++", UNIT_RAM_D0, 31 },
+      { "D0BR.1+D0BRI.1",   UNIT_RAM_D0, 31 },
+      { "D0BR.1++",         UNIT_RAM_D0, 29 },
+      { "D0BR.1",           UNIT_RAM_D0, 28 },
+
+      { "D1AR.0+D1ARI.0++", UNIT_RAM_D1, 18 },
+      { "D1AR.0+D1ARI.0",   UNIT_RAM_D1, 18 },
+      { "D1AR.0+D1ARI.1++", UNIT_RAM_D1, 19 },
+      { "D1AR.0+D1ARI.1",   UNIT_RAM_D1, 19 },
+      { "D1AR.0++",         UNIT_RAM_D1, 17 },
+      { "D1AR.0",           UNIT_RAM_D1, 16 },
+      { "D1ARI.0",          UNIT_RAM_D1, 18 },
+      { "D1ARI.1",          UNIT_RAM_D1, 19 },
+      { "D1AR.1+D1ARI.0++", UNIT_RAM_D1, 22 },
+      { "D1AR.1+D1ARI.0",   UNIT_RAM_D1, 22 },
+      { "D1AR.1+D1ARI.1++", UNIT_RAM_D1, 23 },
+      { "D1AR.1+D1ARI.1",   UNIT_RAM_D1, 23 },
+      { "D1AR.1++",         UNIT_RAM_D1, 21 },
+      { "D1AR.1",           UNIT_RAM_D1, 20 },
+      { "D1BR.0+D1BRI.0++", UNIT_RAM_D1, 26 },
+      { "D1BR.0+D1BRI.0",   UNIT_RAM_D1, 26 },
+      { "D1BR.0+D1BRI.1++", UNIT_RAM_D1, 27 },
+      { "D1BR.0+D1BRI.1",   UNIT_RAM_D1, 27 },
+      { "D1BR.0++",         UNIT_RAM_D1, 25 },
+      { "D1BR.0",           UNIT_RAM_D1, 24 },
+      { "D1BR.1+D1BRI.0++", UNIT_RAM_D1, 30 },
+      { "D1BR.1+D1BRI.0",   UNIT_RAM_D1, 30 },
+      { "D1BR.1+D1BRI.1++", UNIT_RAM_D1, 31 },
+      { "D1BR.1+D1BRI.1",   UNIT_RAM_D1, 31 },
+      { "D1BR.1++",         UNIT_RAM_D1, 29 },
+      { "D1BR.1",           UNIT_RAM_D1, 28 },
+      { "D1BRI.0",          UNIT_RAM_D1, 18 },
+      { "D1BRI.1",          UNIT_RAM_D1, 19 },
+    },
+  };
+
+typedef struct
+{
+  const char *  name;
+  unsigned int  part;
+} metag_acf;
+
+static const metag_acf metag_acftab[] =
+  {
+    { "ACF.0", 0},
+    { "ACF.1", 1},
+    { "ACF.2", 2},
+    { "ACF.3", 3},
+  };
+
+enum insn_encoding
+{
+  ENC_NONE,
+  ENC_MOV_U2U,
+  ENC_MOV_PORT,
+  ENC_MMOV,
+  ENC_MDRD,
+  ENC_MOVL_TTREC,
+  ENC_GET_SET,
+  ENC_GET_SET_EXT,
+  ENC_MGET_MSET,
+  ENC_COND_SET,
+  ENC_XFR,
+  ENC_MOV_CT,
+  ENC_SWAP,
+  ENC_JUMP,
+  ENC_CALLR,
+  ENC_ALU,
+  ENC_SHIFT,
+  ENC_MIN_MAX,
+  ENC_BITOP,
+  ENC_CMP,
+  ENC_BRANCH,
+  ENC_KICK,
+  ENC_SWITCH,
+  ENC_CACHER,
+  ENC_CACHEW,
+  ENC_ICACHE,
+  ENC_LNKGET,
+  ENC_FMOV,
+  ENC_FMMOV,
+  ENC_FMOV_DATA,
+  ENC_FMOV_I,
+  ENC_FPACK,
+  ENC_FSWAP,
+  ENC_FCMP,
+  ENC_FMINMAX,
+  ENC_FCONV,
+  ENC_FCONVX,
+  ENC_FBARITH,
+  ENC_FEARITH,
+  ENC_FREC,
+  ENC_FSIMD,
+  ENC_FGET_SET_ACF,
+  ENC_DGET_SET,
+  ENC_DTEMPLATE,
+  ENC_DALU,
+  ENC_MAX,
+};
+
+enum insn_type
+{
+  INSN_GP,
+  INSN_FPU,
+  INSN_DSP,
+  INSN_DSP_FPU,
+};
+
+typedef struct
+{
+  const char *name;
+
+  unsigned int core_flags;
+#define CoreMeta11             0x1 /* The earliest Meta core we support */
+#define CoreMeta12             0x2
+#define CoreMeta21             0x4
+
+#define FpuMeta21             0x21
+
+#define DspMeta21             0x100
+
+  unsigned int meta_opcode;
+  unsigned int meta_mask;
+
+  enum insn_type insn_type;
+
+  enum insn_encoding encoding;
+
+#define DSP_ARGS_1    0x0000001 /* De.r,Dx.r,De.r (3 register operands) */
+#define DSP_ARGS_ACC2 0x0000002 /* Accumulator source operand 2 */
+#define DSP_ARGS_QR   0x0000004 /* QUICKRoT */
+#define DSP_ARGS_XACC 0x0000008 /* Cross-unit accumulator op */
+#define DSP_ARGS_DACC 0x0000010 /* Target accumulator as destination */
+#define DSP_ARGS_SRD  0x0000020 /* Source the RD port */
+#define DSP_ARGS_2    0x0000040 /* De.r,Dx.r (2 register operands) */
+#define DSP_ARGS_DSP_SRC1   0x0000080 /* Source a DSP register */
+#define DSP_ARGS_DSP_SRC2   0x0000100 /* Source a DSP register */
+#define DSP_ARGS_IMM 0x0000200 /* Immediate value for src 2 */
+#define DSP_ARGS_SPLIT8  0x0000400 /* Data unit split 8 operations */
+#define DSP_ARGS_12  0x0000800 /* De.r,Dx.r */
+#define DSP_ARGS_13  0x0001000 /* Dx.r,Rx.r */
+#define DSP_ARGS_14  0x0002000 /* DSPe.r,Dx.r */
+#define DSP_ARGS_15  0x0004000 /* DSPx.r,#I16 */
+#define DSP_ARGS_16  0x0008000 /* De.r,DSPx.r */
+#define DSP_ARGS_17  0x0010000 /* De.r|ACe.r,Dx.r,Rx.r|RD */
+#define DSP_ARGS_18  0x0020000 /* De.r,Dx.r|ACx.r */
+#define DSP_ARGS_20  0x0080000 /* De.r,Dx.r|ACx.r,De.r */
+#define DSP_ARGS_21  0x0100000 /* De.r,Dx.r|ACx.r,#I5 */
+#define DSP_ARGS_22  0x0200000 /* De.r,Dx.r|ACx.r,De.r|#I5 */
+#define DSP_ARGS_23  0x0400000 /* Ux.r,Dx.r|ACx.r,De.r|#I5 */
+#define GP_ARGS_QR   0x0000001 /* QUICKRoT */
+  unsigned int arg_type;
+} insn_template;
+
+enum major_opcode
+{
+  OPC_ADD,
+  OPC_SUB,
+  OPC_AND,
+  OPC_OR,
+  OPC_XOR,
+  OPC_SHIFT,
+  OPC_MUL,
+  OPC_CMP,
+  OPC_ADDR,
+  OPC_9,
+  OPC_MISC,
+  OPC_SET,
+  OPC_GET,
+  OPC_XFR,
+  OPC_CPR,
+  OPC_FPU,
+};
+
+#define GET_EXT_MINOR        0x7
+#define MOV_EXT_MINOR        0x6
+#define MOVL_MINOR           0x2
+
+#define MAJOR_OPCODE(opcode) (((opcode) >> 28) & 0xf)
+#define MINOR_OPCODE(opcode) (((opcode) >> 24) & 0xf)
+
+enum cond_code
+{
+  COND_A,
+  COND_EQ,
+  COND_NE,
+  COND_CS,
+  COND_CC,
+  COND_MI,
+  COND_PL,
+  COND_VS,
+  COND_VC,
+  COND_HI,
+  COND_LS,
+  COND_GE,
+  COND_LT,
+  COND_GT,
+  COND_LE,
+  COND_NV,
+};
+
+enum scond_code
+{
+  SCOND_A,
+  SCOND_LEQ,
+  SCOND_LNE,
+  SCOND_LLO,
+  SCOND_LHS,
+  SCOND_HEQ,
+  SCOND_HNE,
+  SCOND_HLO,
+  SCOND_HHS,
+  SCOND_LGR,
+  SCOND_LLE,
+  SCOND_HGR,
+  SCOND_HLE,
+  SCOND_EEQ,
+  SCOND_ELO,
+  SCOND_NV,
+};
+
+typedef struct
+{
+  const char *name;
+  enum scond_code code;
+} split_condition;
+
+static const split_condition metag_scondtab[] =
+  {
+    { "LEQ",   SCOND_LEQ },
+    { "LEZ",   SCOND_LEQ },
+    { "LNE",   SCOND_LNE },
+    { "LNZ",   SCOND_LNE },
+    { "LLO",   SCOND_LLO },
+    { "LCS",   SCOND_LLO },
+    { "LHS",   SCOND_LHS },
+    { "LCC",   SCOND_LHS },
+    { "HEQ",   SCOND_HEQ },
+    { "HEZ",   SCOND_HEQ },
+    { "HNE",   SCOND_HNE },
+    { "HNZ",   SCOND_HNE },
+    { "HLO",   SCOND_HLO },
+    { "HCS",   SCOND_HLO },
+    { "HHS",   SCOND_HHS },
+    { "HCC",   SCOND_HHS },
+    { "LGR",   SCOND_LGR },
+    { "LHI",   SCOND_LGR },
+    { "LLE",   SCOND_LLE },
+    { "LLS",   SCOND_LLE },
+    { "HGR",   SCOND_HGR },
+    { "HHI",   SCOND_HGR },
+    { "HLE",   SCOND_HLE },
+    { "HLS",   SCOND_HLE },
+    { "EEQ",   SCOND_EEQ },
+    { "EEZ",   SCOND_EEQ },
+    { "ELO",   SCOND_ELO },
+    { "ECS",   SCOND_ELO },
+  };
+
+static const split_condition metag_dsp_scondtab[] =
+  {
+    { "LEQ",   SCOND_LEQ },
+    { "LEZ",   SCOND_LEQ },
+    { "LNE",   SCOND_LNE },
+    { "LNZ",   SCOND_LNE },
+    { "LCS",   SCOND_LLO },
+    { "LLO",   SCOND_LLO },
+    { "LCC",   SCOND_LHS },
+    { "LHS",   SCOND_LHS },
+    { "HEQ",   SCOND_HEQ },
+    { "HEZ",   SCOND_HEQ },
+    { "HNE",   SCOND_HNE },
+    { "HNZ",   SCOND_HNE },
+    { "HCS",   SCOND_HLO },
+    { "HLO",   SCOND_HLO },
+    { "HCC",   SCOND_HHS },
+    { "HHS",   SCOND_HHS },
+    { "LHI",   SCOND_LGR },
+    { "LGR",   SCOND_LGR },
+    { "LLS",   SCOND_LLE },
+    { "LLE",   SCOND_LLE },
+    { "HHI",   SCOND_HGR },
+    { "HGR",   SCOND_HGR },
+    { "HLS",   SCOND_HLE },
+    { "HLE",   SCOND_HLE },
+    { "EEQ",   SCOND_EEQ },
+    { "EEZ",   SCOND_EEQ },
+    { "ECS",   SCOND_ELO },
+    { "ELO",   SCOND_ELO },
+  };
+
+static const split_condition metag_fpu_scondtab[] =
+  {
+    { "LEQ",   SCOND_LEQ },
+    { "LEZ",   SCOND_LEQ },
+    { "LNE",   SCOND_LNE },
+    { "LNZ",   SCOND_LNE },
+    { "LLO",   SCOND_LLO },
+    { "LCS",   SCOND_LLO },
+    { "LHS",   SCOND_LHS },
+    { "LCC",   SCOND_LHS },
+    { "HEQ",   SCOND_HEQ },
+    { "HEZ",   SCOND_HEQ },
+    { "HNE",   SCOND_HNE },
+    { "HNZ",   SCOND_HNE },
+    { "HLO",   SCOND_HLO },
+    { "HCS",   SCOND_HLO },
+    { "HHS",   SCOND_HHS },
+    { "HCC",   SCOND_HHS },
+    { "LGR",   SCOND_LGR },
+    { "LHI",   SCOND_LGR },
+    { "LLE",   SCOND_LLE },
+    { "LLS",   SCOND_LLE },
+    { "HGR",   SCOND_HGR },
+    { "HHI",   SCOND_HGR },
+    { "HLE",   SCOND_HLE },
+    { "HLS",   SCOND_HLE },
+    { "EEQ",   SCOND_EEQ },
+    { "EEZ",   SCOND_EEQ },
+    { "ELO",   SCOND_ELO },
+    { "ECS",   SCOND_ELO },
+  };
+
+enum fcond_code
+{
+  FCOND_A,
+  FCOND_FEQ,
+  FCOND_UNE,
+  FCOND_FLT,
+  FCOND_UGE,
+
+  FCOND_UVS = 7,
+  FCOND_FVC,
+  FCOND_UGT,
+  FCOND_FLE,
+  FCOND_FGE,
+  FCOND_ULT,
+  FCOND_FGT,
+  FCOND_ULE,
+  FCOND_NV,
+};
+
+#define COND_INSN(mnemonic, suffix, field_shift, flags, meta_opcode,	\
+		  meta_mask, insn_type,	encoding, args)			\
+  { mnemonic suffix, flags, meta_opcode, meta_mask,			\
+      insn_type, encoding, args },					\
+  { mnemonic "A" suffix, flags, meta_opcode, meta_mask,			\
+      insn_type, encoding, args },					\
+  { mnemonic "EQ" suffix, flags, meta_opcode | (COND_EQ << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "Z" suffix, flags, meta_opcode | (COND_EQ << field_shift),	\
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "NE" suffix, flags, meta_opcode | (COND_NE << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "NZ" suffix, flags, meta_opcode | (COND_NE << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "CS" suffix, flags, meta_opcode | (COND_CS << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "LO" suffix, flags, meta_opcode | (COND_CS << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "CC" suffix, flags, meta_opcode | (COND_CC << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "HS" suffix, flags, meta_opcode | (COND_CC << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "MI" suffix, flags, meta_opcode | (COND_MI << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "N" suffix, flags, meta_opcode | (COND_MI << field_shift),	\
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "PL" suffix, flags, meta_opcode | (COND_PL << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "NC" suffix, flags, meta_opcode | (COND_PL << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "VS" suffix, flags, meta_opcode | (COND_VS << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "VC" suffix, flags, meta_opcode | (COND_VC << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "HI" suffix, flags, meta_opcode | (COND_HI << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "LS" suffix, flags, meta_opcode | (COND_LS << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "GE" suffix, flags, meta_opcode | (COND_GE << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "LT" suffix, flags, meta_opcode | (COND_LT << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "GT" suffix, flags, meta_opcode | (COND_GT << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "LE" suffix, flags, meta_opcode | (COND_LE << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "NV" suffix, flags, meta_opcode | (COND_NV << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "FEQ" suffix, flags, meta_opcode |				\
+      (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FZ" suffix, flags, meta_opcode |				\
+      (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "UNE" suffix, flags, meta_opcode |				\
+      (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "UNZ" suffix, flags, meta_opcode |				\
+      (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FLT" suffix, flags, meta_opcode |				\
+      (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FLO" suffix, flags, meta_opcode |				\
+      (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "UGE" suffix, flags, meta_opcode |				\
+      (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "UHS" suffix, flags, meta_opcode |				\
+      (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "UVS" suffix, flags, meta_opcode |				\
+      (FCOND_UVS << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FVC" suffix, flags, meta_opcode |				\
+      (FCOND_FVC << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "UGT" suffix, flags, meta_opcode |				\
+      (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "UHI" suffix, flags, meta_opcode |				\
+      (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FLE" suffix, flags, meta_opcode |				\
+      (FCOND_FLE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FGE" suffix, flags, meta_opcode |				\
+      (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FHS" suffix, flags, meta_opcode |				\
+      (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "ULT" suffix, flags, meta_opcode |				\
+      (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "ULO" suffix, flags, meta_opcode |				\
+      (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FGT" suffix, flags, meta_opcode |				\
+      (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FHI" suffix, flags, meta_opcode |				\
+      (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "ULE" suffix, flags, meta_opcode |				\
+      (FCOND_ULE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "NV" suffix, flags, meta_opcode |				\
+      (FCOND_NV << field_shift), meta_mask, INSN_FPU, encoding, args }
+
+#define FCOND_INSN(mnemonic, suffix, field_shift, flags, meta_opcode,	\
+		  meta_mask, insn_type,	encoding, args)			\
+  { mnemonic suffix, flags, meta_opcode, meta_mask,			\
+      insn_type, encoding, args },					\
+  { mnemonic "A" suffix, flags, meta_opcode, meta_mask,			\
+      insn_type, encoding, args },					\
+  { mnemonic "FEQ" suffix, flags, meta_opcode |				\
+      (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FZ" suffix, flags, meta_opcode |				\
+      (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "UNE" suffix, flags, meta_opcode |				\
+      (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "UNZ" suffix, flags, meta_opcode |				\
+      (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FLO" suffix, flags, meta_opcode |				\
+      (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FLT" suffix, flags, meta_opcode |				\
+      (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "UHS" suffix, flags, meta_opcode |				\
+      (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "UGE" suffix, flags, meta_opcode |				\
+      (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "UVS" suffix, flags, meta_opcode |				\
+      (FCOND_UVS << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FVC" suffix, flags, meta_opcode |				\
+      (FCOND_FVC << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "UHI" suffix, flags, meta_opcode |				\
+      (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "UGT" suffix, flags, meta_opcode |				\
+      (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FLE" suffix, flags, meta_opcode |				\
+      (FCOND_FLE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FGE" suffix, flags, meta_opcode |				\
+      (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FHS" suffix, flags, meta_opcode |				\
+      (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "ULT" suffix, flags, meta_opcode |				\
+      (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "ULO" suffix, flags, meta_opcode |				\
+      (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FGT" suffix, flags, meta_opcode |				\
+      (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "FHI" suffix, flags, meta_opcode |				\
+      (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "ULE" suffix, flags, meta_opcode |				\
+      (FCOND_ULE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
+  { mnemonic "NV" suffix, flags, meta_opcode |				\
+      (FCOND_NV << field_shift), meta_mask, INSN_FPU, encoding, args },	\
+  { mnemonic "EQ" suffix, flags, meta_opcode | (COND_EQ << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "Z" suffix, flags, meta_opcode | (COND_EQ << field_shift),	\
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "NE" suffix, flags, meta_opcode | (COND_NE << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "NZ" suffix, flags, meta_opcode | (COND_NE << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "CS" suffix, flags, meta_opcode | (COND_CS << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "LO" suffix, flags, meta_opcode | (COND_CS << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "CC" suffix, flags, meta_opcode | (COND_CC << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "HS" suffix, flags, meta_opcode | (COND_CC << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "MI" suffix, flags, meta_opcode | (COND_MI << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "N" suffix, flags, meta_opcode | (COND_MI << field_shift),	\
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "PL" suffix, flags, meta_opcode | (COND_PL << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "NC" suffix, flags, meta_opcode | (COND_PL << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "VS" suffix, flags, meta_opcode | (COND_VS << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "VC" suffix, flags, meta_opcode | (COND_VC << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "HI" suffix, flags, meta_opcode | (COND_HI << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "LS" suffix, flags, meta_opcode | (COND_LS << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "GE" suffix, flags, meta_opcode | (COND_GE << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "LT" suffix, flags, meta_opcode | (COND_LT << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "GT" suffix, flags, meta_opcode | (COND_GT << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "LE" suffix, flags, meta_opcode | (COND_LE << field_shift), \
+      meta_mask, insn_type, encoding, args },				\
+  { mnemonic "NV" suffix, flags, meta_opcode | (COND_NV << field_shift), \
+      meta_mask, insn_type, encoding, args }
+
+#define TEMPLATE_INSN(flags, meta_opcode, meta_mask, insn_type)		\
+  { "T0", flags, meta_opcode | 0x0, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+  { "T1", flags, meta_opcode | 0x1, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+  { "T2", flags, meta_opcode | 0x2, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+  { "T3", flags, meta_opcode | 0x3, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+  { "T4", flags, meta_opcode | 0x4, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+  { "T5", flags, meta_opcode | 0x5, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+  { "T6", flags, meta_opcode | 0x6, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+  { "T7", flags, meta_opcode | 0x7, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+  { "T8", flags, meta_opcode | 0x8, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+  { "T9", flags, meta_opcode | 0x9, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+  { "TA", flags, meta_opcode | 0xa, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+  { "TB", flags, meta_opcode | 0xb, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+  { "TC", flags, meta_opcode | 0xc, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+  { "TD", flags, meta_opcode | 0xd, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+  { "TE", flags, meta_opcode | 0xe, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
+  { "TF", flags, meta_opcode | 0xf, meta_mask, insn_type, ENC_DTEMPLATE, 0 }
+
+
+/* Unimplemented GP instructions:
+     CPR - coprocessor read
+     CPW - coprocessor write
+     MORT - morton order operation
+     VPACK, VADD, VSUB - vector instructions
+  
+   The order of the entries in this table is extremely important. DO
+   NOT modify it unless you know what you're doing. If you do modify
+   it, be sure to run the entire testsuite to make sure you haven't
+   caused a regression.  */
+
+static const insn_template metag_optab[] =
+  {
+    /* Port-to-unit MOV */
+    COND_INSN ("MOVB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0xa1800000, 0xfff83e1f, INSN_GP, ENC_MOV_PORT, 0),
+    COND_INSN ("MOVW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0xa1800001, 0xfff83e1f, INSN_GP, ENC_MOV_PORT, 0),
+    COND_INSN ("MOVD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0xa1800200, 0xfff83e1f, INSN_GP, ENC_MOV_PORT, 0),
+    COND_INSN ("MOVL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0xa2800000, 0xfff8019f, INSN_GP, ENC_MOV_PORT, 0),
+
+    /* Read pipeline prime/drain */
+    { "MMOVD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xca000000, 0xff00001f, INSN_GP, ENC_MMOV, 0 },
+    { "MMOVL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xcb000000, 0xff00001f, INSN_GP, ENC_MMOV, 0 },
+    { "MMOVD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xcc000000, 0xff07c067, INSN_GP, ENC_MMOV, 0 },
+    { "MMOVL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xcd000000, 0xff07c067, INSN_GP, ENC_MMOV, 0 },
+
+    /* Read pipeline flush */
+    { "MDRD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xcc000002, 0xffffc07f, INSN_GP, ENC_MDRD, 0 },
+
+    /* Unit-to-TTREC MOVL */
+    COND_INSN ("MOVL", "", 1, CoreMeta12|CoreMeta21,
+	       0xa2002001, 0xff003e7f, INSN_GP, ENC_MOVL_TTREC, 0),
+
+    /* MOV to RA (extended) */
+    { "MOVB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa6000000, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
+    { "MOVW", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa6000002, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
+    { "MOVD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa6000004, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
+    { "MOVL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa6000006, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
+
+    /* Extended GET */
+    { "GETB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa7000000, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+    { "GETW", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa7000002, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+    { "GETD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa7000004, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+    { "GETL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa7000006, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+
+    /* Extended SET */
+    { "SETB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa5000000, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+    { "SETW", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa5000002, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+    { "SETD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa5000004, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+    { "SETL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa5000006, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
+
+    /* MOV to RA */
+    { "MOVB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xc000000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
+    { "MOVW", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xc100000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
+    { "MOVD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xc400000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
+    { "MOVL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xc500000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
+
+    /* Standard GET */
+    { "GETB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xc0000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+    { "GETW", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xc1000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+    { "GETD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xc4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+    /* GET is a synonym for GETD. */
+    { "GET", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xc4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+    { "GETL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xc5000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+
+    /* Standard SET */
+    { "SETB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xb0000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+    { "SETW", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xb1000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+    { "SETD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xb4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+    /* SET is a synonym for SETD. */
+    { "SET", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xb4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+    { "SETL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xb5000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
+
+    /* Multiple GET */
+    { "MGETD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xc8000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
+    { "MGETL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xc9000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
+
+    /* Multiple SET */
+    { "MSETD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xb8000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
+    { "MSETL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xb9000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
+
+    /* Conditional SET */
+    COND_INSN ("SETB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0xa4000000, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+    COND_INSN ("SETW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0xa4000001, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+    COND_INSN ("SETD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0xa4000200, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+    COND_INSN ("SETL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0xa4000201, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+    { "XFRD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xd0000000, 0xf2000000, INSN_GP, ENC_XFR, 0 },
+    { "XFRL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xd2000000, 0xf2000000, INSN_GP, ENC_XFR, 0 },
+
+    /* Fast control register setup */
+    { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa9000000, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
+    { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa9000001, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
+    { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa9000004, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
+    { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa9000005, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
+
+    /* Internal transfer operations */
+    { "JUMP", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xac000000, 0xff000004, INSN_GP, ENC_JUMP, 0 },
+    { "CALL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xac000004, 0xff000004, INSN_GP, ENC_JUMP, 0 },
+    { "CALLR", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xab000000, 0xff000000, INSN_GP, ENC_CALLR, 0 },
+
+    /* Address unit ALU operations */
+    { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x80000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+    { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x82000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x82000005, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x80000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+    { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x82000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "ADDT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x82000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x86000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+    COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x84000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x86000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+    { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x88000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+    { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x8a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "NEGT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x8a000005, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x88000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+    { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x8a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "SUBT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x8a000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x8e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+    COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x8c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x8e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+
+    /* Data unit ALU operations */
+    { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x00000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+    { "MOVS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x08000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+    { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x02000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "MOVS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x0a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x02000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "MOVST", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x0a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "ADD", DspMeta21,
+      0x00000100, 0xfe000104, INSN_DSP, ENC_DALU,
+      DSP_ARGS_1|DSP_ARGS_ACC2|DSP_ARGS_XACC|DSP_ARGS_IMM },
+    { "ADD", DspMeta21,
+      0x02000003, 0xfe000003, INSN_DSP, ENC_DALU,
+      DSP_ARGS_1|DSP_ARGS_IMM },
+    COND_INSN ("ADD", "", 1, DspMeta21,
+	       0x040001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
+    { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x00000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+    { "ADDS", DspMeta21,
+      0x08000100, 0xfe000104, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_ACC2 },
+    { "ADDS", DspMeta21,
+      0x0a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+    { "ADDS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x08000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+    { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x02000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "ADDS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x0a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "ADDT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x02000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "ADDST", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x0a000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x06000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+    COND_INSN ("ADDS", "", 1, DspMeta21,
+	       0x0c0001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
+    { "ADDS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x0e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+    COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x04000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("ADDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x0c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x06000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("ADDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x0e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+    { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x10000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+    { "NEGS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x18000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+    { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x12000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "NEGS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x1a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "NEGT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x12000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "NEGST", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x1a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "SUB", DspMeta21,
+      0x10000100, 0xfe000104, INSN_DSP, ENC_DALU,
+      DSP_ARGS_1|DSP_ARGS_ACC2|DSP_ARGS_XACC },
+    { "SUB", DspMeta21,
+      0x12000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+    { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x10000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+    { "SUBS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x18000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
+    { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x12000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "SUBS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x1a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "SUBT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x12000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "SUBS", DspMeta21,
+      0x18000100, 0xfe000104, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_ACC2 },
+    { "SUBS", DspMeta21,
+      0x1a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+    { "SUBST", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x1a000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x16000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+    { "SUBS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x1e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+    COND_INSN ("SUBS", "", 1, DspMeta21,
+	       0x1c0001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
+    COND_INSN ("SUB", "", 1, DspMeta21,
+	       0x140001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
+    COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x14000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("SUBS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x1c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x16000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("SUBS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x1e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+    { "AND", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x20000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+    { "ANDS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x28000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+    { "ANDQ", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x20000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
+    { "ANDSQ", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x28000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
+    { "AND", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x22000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "ANDMB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x22000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "ANDS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x2a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "ANDSMB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x2a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "ANDT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x22000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "ANDMT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x22000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "ANDST", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x2a000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "ANDSMT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x2a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "AND", DspMeta21,
+      0x20000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+    { "AND", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x26000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+    { "ANDS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x2e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+    { "ANDQ", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x26000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
+    { "ANDSQ", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x2e000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
+    { "ANDQ", DspMeta21,
+      0x20000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
+    COND_INSN ("ANDQ", "", 1, DspMeta21,
+	       0x240001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
+	       DSP_ARGS_1|DSP_ARGS_QR),
+    COND_INSN ("AND", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x24000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+    { "ANDSQ", DspMeta21,
+      0x28000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
+    COND_INSN ("ANDSQ", "", 1, DspMeta21,
+	       0x2c0001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
+	       DSP_ARGS_1|DSP_ARGS_QR),
+    COND_INSN ("ANDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x2c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("AND", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x26000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("ANDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x2e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("ANDQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x26000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
+    COND_INSN ("ANDSQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x2e000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
+    { "OR", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x30000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+    { "ORS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x38000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+    { "ORQ", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x30000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
+    { "ORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x38000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
+    { "OR", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x32000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "ORMB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x32000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "ORS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x3a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "ORSMB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x3a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "ORT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x32000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "ORMT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x32000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "ORST", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x3a000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "ORSMT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x3a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "OR", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x36000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+    { "ORS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x3e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+    { "ORQ", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x36000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
+    { "ORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x3e000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
+    { "ORQ", DspMeta21,
+      0x30000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
+    COND_INSN ("ORQ", "", 1, DspMeta21,
+	       0x340001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
+	       DSP_ARGS_1|DSP_ARGS_QR),
+    COND_INSN ("OR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x34000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+    { "ORSQ", DspMeta21,
+      0x38000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
+    COND_INSN ("ORSQ", "", 1, DspMeta21,
+	       0x3c0001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
+	       DSP_ARGS_1|DSP_ARGS_QR),
+    COND_INSN ("ORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x3c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("OR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x36000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("ORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x3e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("ORQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x36000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
+    COND_INSN ("ORSQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x3e000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
+    { "XOR", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x40000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+    { "XORS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x48000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+    { "XORQ", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x40000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
+    { "XORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x48000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
+    { "XOR", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x42000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "XORMB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x42000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "XORS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x4a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "XORSMB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x4a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "XORT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x42000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "XORMT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x42000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "XORST", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x4a000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "XORSMT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x4a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "XOR", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x46000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+    { "XORS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x4e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+    { "XORQ", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x46000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
+    { "XORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x4e000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
+    { "XORQ", DspMeta21,
+      0x40000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
+    COND_INSN ("XORQ", "", 1, DspMeta21,
+	       0x440001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
+	       DSP_ARGS_1|DSP_ARGS_QR),
+    COND_INSN ("XOR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x44000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+    { "XORSQ", DspMeta21,
+      0x48000140, 0xfe000140, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
+    COND_INSN ("XORSQ", "", 1, DspMeta21,
+	       0x4c0001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
+	       DSP_ARGS_1|DSP_ARGS_QR),
+    COND_INSN ("XORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x4c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("XOR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x46000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("XORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x4e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("XORQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x46000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
+    COND_INSN ("XORSQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x4e000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
+    { "LSL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x50000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+    { "LSL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x54000020, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+    COND_INSN ("LSL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x54000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+    { "LSLS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x58000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+    { "LSLS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x5c000020, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+    COND_INSN ("LSLS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x5c000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+    { "LSR", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x50000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+    { "LSR", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x54000060, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+    COND_INSN ("LSR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x54000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+    { "LSRS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x58000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+    { "LSRS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x5c000060, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+    COND_INSN ("LSRS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x5c000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+    { "ASL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x50000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+    { "ASL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x540000a0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+    COND_INSN ("ASL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x54000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+    { "ASLS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x58000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+    { "ASLS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x5c0000a0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+    COND_INSN ("ASLS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x5c000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+    { "ASR", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x500000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+    { "ASR", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x540000e0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+    COND_INSN ("ASR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x540000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+    { "ASRS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x580000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
+    { "ASRS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x5c0000e0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
+    COND_INSN ("ASRS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x5c0000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
+    { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x60000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+    { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x60000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+    /* MUL is a synonym from MULD. */
+    { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x60000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
+    { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x62000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x62000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x62000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
+    { "MULWT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x62000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "MULDT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x62000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "MULT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x62000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
+    { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x64000020, 0xfe0001e0, INSN_GP, ENC_ALU, 0 },
+    { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x64000060, 0xfe0001e0, INSN_GP, ENC_ALU, 0 },
+    { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x64000060, 0xfe0001e0, INSN_GP, ENC_ALU, 0 },
+    { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x66000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+    { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x66000021, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+    { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x66000021, 0xfe000021, INSN_GP, ENC_ALU, 0 },
+    COND_INSN ("MULW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x64000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("MULD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x64000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("MUL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x64000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("MULW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x66000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("MULD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x66000001, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+    COND_INSN ("MUL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x66000001, 0xfe00003f, INSN_GP, ENC_ALU, 0),
+    { "MIN", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x70000020, 0xfe0001ff, INSN_GP, ENC_MIN_MAX, 0 },
+    { "MAX", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x70000024, 0xfe0001ff, INSN_GP, ENC_MIN_MAX, 0 },
+    { "FFB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x70000004, 0xfe003fff, INSN_GP, ENC_BITOP, 0 },
+    { "NORM", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x70000008, 0xfe003fff, INSN_GP, ENC_BITOP, 0 },
+    { "ABS", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x70000028, 0xfe003fff, INSN_GP, ENC_BITOP, 0 },
+    { "XSDB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xaa000000, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+    { "XSDSB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xaa000008, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+    { "XSDW", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xaa000002, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+    { "XSDSW", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xaa00000a, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+    { "RTDW", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xaa000006, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+    { "RTDSW", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xaa00000e, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+    { "NMIN", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x7000002c, 0xfe0001ff, INSN_GP, ENC_MIN_MAX, 0 },
+
+    /* Condition setting operations */
+    { "CMP", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x70000000, 0xfef801fe, INSN_GP, ENC_CMP, 0 },
+    { "TST", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x78000000, 0xfef801fe, INSN_GP, ENC_CMP, 0 },
+    { "CMP", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x72000000, 0xfe000005, INSN_GP, ENC_CMP, 0 },
+    { "CMPMB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x72000004, 0xfe000005, INSN_GP, ENC_CMP, 0 },
+    { "TST", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x7a000000, 0xfe000005, INSN_GP, ENC_CMP, 0 },
+    { "TSTMB", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x7a000004, 0xfe000005, INSN_GP, ENC_CMP, 0 },
+    { "CMPT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x72000001, 0xfe000007, INSN_GP, ENC_CMP, 0 },
+    { "CMPMT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x72000005, 0xfe000007, INSN_GP, ENC_CMP, 0 },
+    { "TSTT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x7a000001, 0xfe000007, INSN_GP, ENC_CMP, 0 },
+    { "TSTMT", CoreMeta11|CoreMeta12|CoreMeta21,
+      0x7a000005, 0xfe000007, INSN_GP, ENC_CMP, 0 },
+    COND_INSN ("CMP", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x74000000, 0xfef801fe, INSN_GP, ENC_CMP, 0),
+    COND_INSN ("TST", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x7c000000, 0xfef801fe, INSN_GP, ENC_CMP, 0),
+    COND_INSN ("CMP", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x76000000, 0xfef8003e, INSN_GP, ENC_CMP, 0),
+    COND_INSN ("TST", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0x7e000000, 0xfef8003e, INSN_GP, ENC_CMP, 0),
+
+    /* No-op (BNV) */
+    { "NOP", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa0fffffe, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+
+    /* Branch */
+    COND_INSN ("B", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0xa0000000, 0xff00001f, INSN_GP, ENC_BRANCH, 0),
+    COND_INSN ("B", "R", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0xa0000001, 0xff00001f, INSN_GP, ENC_BRANCH, 0),
+
+    /* System operations */
+    { "LOCK0", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa8000000, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+    { "LOCK1", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa8000001, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+    { "LOCK2", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa8000003, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+    { "RTI", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa3ffffff, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+    { "RTH", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xa37fffff, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+    COND_INSN ("KICK", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0xa3000001, 0xff003e1f, INSN_GP, ENC_KICK, 0),
+    { "SWITCH", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xaf000000, 0xff000000, INSN_GP, ENC_SWITCH, 0 },
+    { "DCACHE", CoreMeta11|CoreMeta12|CoreMeta21,
+      0xad000000, 0xff000087, INSN_GP, ENC_CACHEW, 0 },
+    { "ICACHEEXIT", CoreMeta12|CoreMeta21,
+      0xae000000, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+    { "ICACHEEXITR", CoreMeta12|CoreMeta21,
+      0xae000001, 0xffffffff, INSN_GP, ENC_NONE, 0 },
+    { "ICACHE", CoreMeta12|CoreMeta21,
+      0xae000000, 0xff0001e1, INSN_GP, ENC_ICACHE, 0 },
+    { "ICACHER", CoreMeta12|CoreMeta21,
+      0xae000001, 0xff0001e1, INSN_GP, ENC_ICACHE, 0 },
+
+    /* Meta 2 instructions */
+    { "CACHERD", CoreMeta21,
+      0xad000081, 0xff000087, INSN_GP, ENC_CACHER, 0 },
+    { "CACHERL", CoreMeta21,
+      0xad000083, 0xff000087, INSN_GP, ENC_CACHER, 0 },
+    { "CACHEWD", CoreMeta21,
+      0xad000001, 0xff000087, INSN_GP, ENC_CACHEW, 0 },
+    { "CACHEWL", CoreMeta21,
+      0xad000003, 0xff000087, INSN_GP, ENC_CACHEW, 0 },
+    COND_INSN ("DEFR", "", 1, CoreMeta21,
+	       0xa3002001, 0xff003e1f, INSN_GP, ENC_KICK, 0),
+    { "BEXD", CoreMeta21,
+      0xaa000004, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+    { "BEXSD", CoreMeta21,
+      0xaa00000c, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+    { "BEXL", CoreMeta21,
+      0xaa000014, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+    { "BEXSL", CoreMeta21,
+      0xaa00001c, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
+    { "LNKGETB", CoreMeta21,
+      0xad000080, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
+    { "LNKGETW", CoreMeta21,
+      0xad000082, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
+    { "LNKGETD", CoreMeta21,
+      0xad000084, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
+    { "LNKGETL", CoreMeta21,
+      0xad000086, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
+    COND_INSN ("LNKSETB", "", 1, CoreMeta21,
+	       0xa4000080, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+    COND_INSN ("LNKSETW", "", 1, CoreMeta21,
+	       0xa4000081, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+    COND_INSN ("LNKSETD", "", 1, CoreMeta21,
+	       0xa4000280, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+    COND_INSN ("LNKSETL", "", 1, CoreMeta21,
+	       0xa4000281, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
+
+    /* Meta 2 FPU instructions */
+
+    /* Port-to-unit MOV */
+    COND_INSN ("MOVL", "", 1, FpuMeta21,
+	       0xa1800201, 0xfff83e1f, INSN_FPU, ENC_MOV_PORT, 0),
+
+    /* Read pipeline drain */
+    { "MMOVD", FpuMeta21,
+      0xce000006, 0xfffc007f, INSN_FPU, ENC_MMOV, 0 },
+    { "MMOVL", FpuMeta21,
+      0xcf000006, 0xfffc007f, INSN_FPU, ENC_MMOV, 0 },
+
+    /* FP data movement instructions */
+    FCOND_INSN ("ABS", "", 1, FpuMeta21,
+		0xf0000080, 0xff843f9f, INSN_FPU, ENC_FMOV, 0),
+    { "MMOVD", FpuMeta21,
+      0xbe000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
+    { "MMOVL", FpuMeta21,
+      0xbf000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
+    { "MMOVD", FpuMeta21,
+      0xce000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
+    { "MMOVL", FpuMeta21,
+      0xcf000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
+    { "MOVD", FpuMeta21,
+      0x08000144, 0xfe03e1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
+    { "MOVD", FpuMeta21,
+      0x080001c4, 0xfe83c1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
+    { "MOVL", FpuMeta21,
+      0x08000154, 0xfe03e1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
+    { "MOVL", FpuMeta21,
+      0x080001d4, 0xfe83c1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
+    FCOND_INSN ("MOV", "", 1, FpuMeta21,
+		0xf0000000, 0xff843f9f, INSN_FPU, ENC_FMOV, 0),
+    { "MOV", FpuMeta21,
+      0xf0000001, 0xff800001, INSN_FPU, ENC_FMOV_I, 0 },
+    FCOND_INSN ("NEG", "", 1, FpuMeta21,
+		0xf0000100, 0xff843f9f, INSN_FPU, ENC_FMOV, 0),
+    { "PACK", FpuMeta21,
+      0xf0000180, 0xff8c21ff, INSN_FPU, ENC_FPACK, 0 },
+    { "SWAP", FpuMeta21,
+      0xf00001c0, 0xff8c7fff, INSN_FPU, ENC_FSWAP, 0 },
+
+    /* FP comparison instructions */
+    FCOND_INSN ("CMP", "", 1, FpuMeta21,
+		0xf3000000, 0xfff4201f, INSN_FPU, ENC_FCMP, 0),
+    FCOND_INSN ("MAX", "", 1, FpuMeta21,
+		0xf3000081, 0xff84219f, INSN_FPU, ENC_FMINMAX, 0),
+    FCOND_INSN ("MIN", "", 1, FpuMeta21,
+		0xf3000001, 0xff84219f, INSN_FPU, ENC_FMINMAX, 0),
+
+    /* FP data conversion instructions */
+    FCOND_INSN ("DTOF", "", 1, FpuMeta21,
+		0xf2000121, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
+    FCOND_INSN ("FTOD", "", 1, FpuMeta21,
+		0xf2000101, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
+    FCOND_INSN ("DTOH", "", 1, FpuMeta21,
+		0xf2000320, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
+    FCOND_INSN ("FTOH", "", 1, FpuMeta21,
+		0xf2000300, 0xff843fbf, INSN_FPU, ENC_FCONV, 0),
+    FCOND_INSN ("DTOI", "", 1, FpuMeta21,
+		0xf2002120, 0xff842fff, INSN_FPU, ENC_FCONV, 0),
+    FCOND_INSN ("FTOI", "", 1, FpuMeta21,
+		0xf2002100, 0xff842fbf, INSN_FPU, ENC_FCONV, 0),
+    FCOND_INSN ("DTOL", "", 1, FpuMeta21,
+		0xf2002320, 0xff8c6fff, INSN_FPU, ENC_FCONV, 0),
+
+    FCOND_INSN ("DTOX", "", 1, FpuMeta21,
+		0xf2000020, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
+    FCOND_INSN ("FTOX", "", 1, FpuMeta21,
+		0xf2000000, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
+    FCOND_INSN ("DTOXL", "", 1, FpuMeta21,
+		0xf20000a0, 0xff8c40ff, INSN_FPU, ENC_FCONVX, 0),
+
+    FCOND_INSN ("HTOD", "", 1, FpuMeta21,
+		0xf2000321, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
+    FCOND_INSN ("HTOF", "", 1, FpuMeta21,
+		0xf2000301, 0xff843fbf, INSN_FPU, ENC_FCONV, 0),
+    FCOND_INSN ("ITOD", "", 1, FpuMeta21,
+		0xf2002121, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
+    FCOND_INSN ("ITOF", "", 1, FpuMeta21,
+		0xf2002101, 0xff843fbf, INSN_FPU, ENC_FCONV, 0),
+    FCOND_INSN ("LTOD", "", 1, FpuMeta21,
+		0xf2002321, 0xff8c7fff, INSN_FPU, ENC_FCONV, 0),
+
+    FCOND_INSN ("XTOD", "", 1, FpuMeta21,
+		0xf2000021, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
+    FCOND_INSN ("XTOF", "", 1, FpuMeta21,
+		0xf2000001, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
+    FCOND_INSN ("XLTOD", "", 1, FpuMeta21,
+		0xf20000a1, 0xff8c40ff, INSN_FPU, ENC_FCONVX, 0),
+
+    /* FP basic arithmetic instructions */
+    FCOND_INSN ("ADD", "", 1, FpuMeta21,
+		0xf1000001, 0xff84211f, INSN_FPU, ENC_FBARITH, 0),
+    FCOND_INSN ("MUL", "", 1, FpuMeta21,
+		0xf1000100, 0xff84211f, INSN_FPU, ENC_FBARITH, 0),
+    FCOND_INSN ("SUB", "", 1, FpuMeta21,
+		0xf1000101, 0xff84211f, INSN_FPU, ENC_FBARITH, 0),
+
+    /* FP extended arithmetic instructions */
+    { "MAC", FpuMeta21,
+      0xf6000000, 0xfffc219f, INSN_FPU, ENC_FEARITH, 0 },
+    { "MACS", FpuMeta21,
+      0xf6000100, 0xfffc219f, INSN_FPU, ENC_FEARITH, 0 },
+
+    { "MAR", FpuMeta21,
+      0xf6000004, 0xff84211f, INSN_FPU, ENC_FEARITH, 0 },
+    { "MARS", FpuMeta21,
+      0xf6000104, 0xff84211f, INSN_FPU, ENC_FEARITH, 0 },
+
+    { "MAW", FpuMeta21,
+      0xf6000008, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
+    { "MAWS", FpuMeta21,
+      0xf6000108, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
+    { "MAW1", FpuMeta21,
+      0xf6000009, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
+    { "MAWS1", FpuMeta21,
+      0xf6000109, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
+
+    FCOND_INSN ("MXA", "", 1, FpuMeta21,
+		0xf5000000, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
+    FCOND_INSN ("MXAS", "", 1, FpuMeta21,
+		0xf5000100, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
+    FCOND_INSN ("MXA1", "", 1, FpuMeta21,
+		0xf5000001, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
+    FCOND_INSN ("MXAS1", "", 1, FpuMeta21,
+		0xf5000101, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
+
+    { "MUZ", FpuMeta21,
+      0xf6000010, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
+    { "MUZS", FpuMeta21,
+      0xf6000110, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
+    { "MUZ1", FpuMeta21,
+      0xf6000011, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
+    { "MUZS1", FpuMeta21,
+      0xf6000111, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
+
+    { "RCP", FpuMeta21,
+      0xf7000000, 0xff84391f, INSN_FPU, ENC_FREC, 0 },
+    { "RSQ", FpuMeta21,
+      0xf7000100, 0xff84391f, INSN_FPU, ENC_FREC, 0 },
+
+    /* FP SIMD arithmetic instructions */
+    { "ADDRE", FpuMeta21,
+      0xf4000000, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 },
+    { "MULRE", FpuMeta21,
+      0xf4000001, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 },
+    { "SUBRE", FpuMeta21,
+      0xf4000100, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 },
+
+    /* FP memory instructions */
+    { "MGETD", FpuMeta21,
+      0xce000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
+    { "MGET", FpuMeta21,
+      0xce000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
+    { "MGETL", FpuMeta21,
+      0xcf000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
+
+    { "MSETD", FpuMeta21,
+      0xbe000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
+    { "MSET", FpuMeta21,
+      0xbe000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
+    { "MSETL", FpuMeta21,
+      0xbf000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
+
+    /* FP accumulator memory instructions */
+    { "GETL", FpuMeta21,
+      0xcf000004, 0xffe03f9f, INSN_FPU, ENC_FGET_SET_ACF, 0 },
+    { "SETL", FpuMeta21,
+      0xbf000004, 0xffe03f9f, INSN_FPU, ENC_FGET_SET_ACF, 0 },
+
+    /* DSP FPU data movement */
+    { "MOV", DspMeta21|FpuMeta21,
+      0x08000146, 0xfe0001ee, INSN_DSP_FPU, ENC_DALU,
+      DSP_ARGS_2|DSP_ARGS_DSP_SRC1 },
+    { "MOV", DspMeta21|FpuMeta21,
+      0x080001c6, 0xfe0001ee, INSN_DSP_FPU, ENC_DALU,
+      DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
+
+    /* Unit-to-unit MOV */
+    COND_INSN ("MOV", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0xa3000000, 0xff00021f, INSN_GP, ENC_MOV_U2U, 0),
+    COND_INSN ("TTMOV", "", 1, CoreMeta12|CoreMeta21,
+	       0xa3000201, 0xff00021f, INSN_GP, ENC_MOV_U2U, 0),
+    COND_INSN ("SWAP", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
+	       0xa3000200, 0xff00021f, INSN_GP, ENC_SWAP, 0),
+
+    /* DSP memory instructions */
+    { "GETD", DspMeta21,
+      0x94000100, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
+    { "SETD", DspMeta21,
+      0x94000000, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
+    { "GETL", DspMeta21,
+      0x94000104, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
+    { "SETL", DspMeta21,
+      0x94000004, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
+
+    /* DSP read pipeline prime/drain */
+    { "MMOVD", DspMeta21,
+      0xca000001, 0xff00001f, INSN_DSP, ENC_MMOV, 0 },
+    { "MMOVL", DspMeta21,
+      0xcb000001, 0xff00001f, INSN_DSP, ENC_MMOV, 0 },
+    { "MMOVD", DspMeta21,
+      0xcc000001, 0xff07c067, INSN_DSP, ENC_MMOV, 0 },
+    { "MMOVL", DspMeta21,
+      0xcd000001, 0xff07c067, INSN_DSP, ENC_MMOV, 0 },
+
+    /* DSP Template instantiation */
+    TEMPLATE_INSN (DspMeta21, 0x90000000, 0xff00000f, INSN_DSP),
+    TEMPLATE_INSN (DspMeta21, 0x93000000, 0xff0001ff, INSN_DSP),
+    TEMPLATE_INSN (DspMeta21, 0x95000000, 0xff00000f, INSN_DSP),
+
+    { "AND", DspMeta21,
+      0x22000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+    { "ANDS", DspMeta21,
+      0x28000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+    { "ANDS", DspMeta21,
+      0x2a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+    { "MAX", DspMeta21,
+      0x70000124, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+    { "MIN", DspMeta21,
+      0x70000120, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+    { "NMIN", DspMeta21,
+      0x7000012c, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+    { "OR", DspMeta21,
+      0x30000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+    { "OR", DspMeta21,
+      0x32000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+    { "ORS", DspMeta21,
+      0x38000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+    { "ORS", DspMeta21,
+      0x3a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+    { "XOR", DspMeta21,
+      0x40000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+    { "XOR", DspMeta21,
+      0x42000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+    { "XORS", DspMeta21,
+      0x48000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
+    { "XORS", DspMeta21,
+      0x4a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+    { "ADDB8", DspMeta21,
+      0x20000108, 0xfe00010c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+    { "ADDT8", DspMeta21,
+      0x2000010c, 0xfe00010c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+    { "ADDSB8", DspMeta21,
+      0x28000108, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+    { "ADDST8", DspMeta21,
+      0x2800010c, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+    { "MULB8", DspMeta21,
+      0x40000108, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+    { "MULT8", DspMeta21,
+      0x4000010c, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+    { "MULSB8", DspMeta21,
+      0x48000108, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+    { "MULST8", DspMeta21,
+      0x4800010c, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+    { "SUBB8", DspMeta21,
+      0x30000108, 0xfe00010c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+    { "SUBT8", DspMeta21,
+      0x3000010c, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+    { "SUBSB8", DspMeta21,
+      0x38000108, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+    { "SUBST8", DspMeta21,
+      0x3800010c, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
+    { "MUL", DspMeta21,
+      0x60000100, 0xfe000100, INSN_DSP, ENC_DALU,
+      DSP_ARGS_1|DSP_ARGS_DACC },
+    { "MUL", DspMeta21,
+      0x62000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
+    { "ABS", DspMeta21,
+      0x70000128, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+    { "FFB", DspMeta21,
+      0x70000104, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+    { "NORM", DspMeta21,
+      0x70000108, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+    { "CMP", DspMeta21,
+      0x70000000, 0xfe0000ec, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
+    { "CMP", DspMeta21,
+      0x72000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
+    { "TST", DspMeta21,
+      0x78000100, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
+    { "TST", DspMeta21,
+      0x7a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
+    { "MOV", DspMeta21,
+      0x00000104, 0xfe078146, INSN_DSP, ENC_DALU,
+      DSP_ARGS_2|DSP_ARGS_DSP_SRC1|DSP_ARGS_DSP_SRC2|DSP_ARGS_IMM },
+    { "MOVS", DspMeta21,
+      0x08000104, 0xfe000146, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
+    { "MOV", DspMeta21,
+      0x91000000, 0xff000000, INSN_DSP, ENC_DALU,
+      DSP_ARGS_2|DSP_ARGS_DSP_SRC1|DSP_ARGS_IMM },
+    { "MOV", DspMeta21,
+      0x92000000, 0xff000000, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
+    { "NEG", DspMeta21,
+      0x10000104, 0xfe000146, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
+    { "NEGS", DspMeta21,
+      0x18000104, 0xfe000146, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
+    { "XSDB", DspMeta21,
+      0xaa000100, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+    { "XSD", DspMeta21,
+      0xaa000100, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+    { "XSDW", DspMeta21,
+      0xaa000102, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+    { "XSDSB", DspMeta21,
+      0xaa000108, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+    { "XSDS", DspMeta21,
+      0xaa000108, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+    { "XSDSW", DspMeta21,
+      0xaa00010a, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+    { "LSL", DspMeta21,
+      0x50000100, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+    { "LSR", DspMeta21,
+      0x50000140, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+    { "ASL", DspMeta21,
+      0x50000180, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+    { "ASR", DspMeta21,
+      0x500001c0, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+    { "LSL", DspMeta21,
+      0x54000120, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
+    { "LSR", DspMeta21,
+      0x54000160, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
+    { "ASL", DspMeta21,
+      0x540001a0, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
+    { "ASR", DspMeta21,
+      0x540001e0, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
+    COND_INSN ("LSL", "", 1, DspMeta21,
+	       0x54000100, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+    COND_INSN ("LSR", "", 1, DspMeta21,
+	       0x54000140, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+    COND_INSN ("ASL", "", 1, DspMeta21,
+	       0x54000180, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+    COND_INSN ("ASR", "", 1, DspMeta21,
+	       0x540001c0, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+    { "LSLS", DspMeta21,
+      0x58000100, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+    { "LSRS", DspMeta21,
+      0x58000140, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+    { "ASLS", DspMeta21,
+      0x58000180, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+    { "ASRS", DspMeta21,
+      0x580001c0, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
+    COND_INSN ("LSLS", "", 1, DspMeta21,
+	       0x5c000100, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+    COND_INSN ("LSRS", "", 1, DspMeta21,
+	       0x5c000140, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+    COND_INSN ("ASLS", "", 1, DspMeta21,
+	       0x5c000180, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+    COND_INSN ("ASRS", "", 1, DspMeta21,
+	       0x5c0001c0, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
+    { "LSLS", DspMeta21,
+      0x5c000120, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
+    { "LSRS", DspMeta21,
+      0x5c000160, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
+    { "ASLS", DspMeta21,
+      0x5c0001a0, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
+    { "ASRS", DspMeta21,
+      0x5c0001e0, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
+    { "RTDW", DspMeta21,
+      0xaa000106, 0xff00010e, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+    { "RTDSW", DspMeta21,
+      0xaa00010e, 0xff00010e, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
+  };
+
+#define UNIT_MASK                  0xf
+#define SHORT_UNIT_MASK            0x3
+#define EXT_BASE_REG_MASK          0x1
+#define REG_MASK                  0x1f
+#define CC_MASK                    0xf
+#define RMASK_MASK                0x7f
+#define GET_SET_IMM_MASK          0x3f
+#define GET_SET_IMM_BITS             6
+#define GET_SET_EXT_IMM_MASK     0xfff
+#define GET_SET_EXT_IMM_BITS        12
+#define DGET_SET_IMM_MASK          0x3
+#define DGET_SET_IMM_BITS            2
+#define MGET_MSET_MAX_REGS           8
+#define MMOV_MAX_REGS                8
+#define IMM16_MASK              0xffff
+#define IMM16_BITS                  16
+#define IMM19_MASK             0x7ffff
+#define IMM19_BITS                  19
+#define IMM8_MASK                 0xff
+#define IMM8_BITS                    8
+#define IMM24_MASK            0xffffff
+#define IMM24_BITS                  24
+#define IMM5_MASK                 0x1f
+#define IMM5_BITS                    5
+#define IMM6_MASK                 0x3f
+#define IMM6_BITS                    6
+#define IMM15_MASK              0x7fff
+#define IMM15_BITS                  15
+#define IMM4_MASK                 0x1f
+#define IMM4_BITS                    4
+#define CALLR_REG_MASK             0x7
+#define CPC_REG_MASK               0xf
+#define O2R_REG_MASK               0x7
+#define ACF_PART_MASK              0x3
+#define DSP_REG_MASK               0xf
+#define DSP_PART_MASK             0x17
+#define TEMPLATE_NUM_REGS            4
+#define TEMPLATE_REGS_MASK         0xf
+
+#define IS_TEMPLATE_DEF(insn) (insn->dsp_daoppame_flags & DSP_DAOPPAME_TEMP)
+
+unsigned int metag_get_set_size_bytes (unsigned int opcode);
+unsigned int metag_get_set_ext_size_bytes (unsigned int opcode);
+unsigned int metag_cond_set_size_bytes (unsigned int opcode);
diff --git a/binutils-2.25/include/opcode/mips.h b/binutils-2.25/include/opcode/mips.h
new file mode 100644
index 00000000..cb16d2a4
--- /dev/null
+++ b/binutils-2.25/include/opcode/mips.h
@@ -0,0 +1,2151 @@
+/* mips.h.  Mips opcode list for GDB, the GNU debugger.
+   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+   2003, 2004, 2005, 2008, 2009, 2010, 2013
+   Free Software Foundation, Inc.
+   Contributed by Ralph Campbell and OSF
+   Commented and modified by Ian Lance Taylor, Cygnus Support
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _MIPS_H_
+#define _MIPS_H_
+
+#include "bfd.h"
+
+/* These are bit masks and shift counts to use to access the various
+   fields of an instruction.  To retrieve the X field of an
+   instruction, use the expression
+	(i >> OP_SH_X) & OP_MASK_X
+   To set the same field (to j), use
+	i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
+
+   Make sure you use fields that are appropriate for the instruction,
+   of course.
+
+   The 'i' format uses OP, RS, RT and IMMEDIATE.
+
+   The 'j' format uses OP and TARGET.
+
+   The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
+
+   The 'b' format uses OP, RS, RT and DELTA.
+
+   The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
+
+   The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
+
+   A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
+   breakpoint instruction are not defined; Kane says the breakpoint
+   code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
+   only use ten bits).  An optional two-operand form of break/sdbbp
+   allows the lower ten bits to be set too, and MIPS32 and later
+   architectures allow 20 bits to be set with a signal operand
+   (using CODE20).
+
+   The syscall instruction uses CODE20.
+
+   The general coprocessor instructions use COPZ.  */
+
+#define OP_MASK_OP		0x3f
+#define OP_SH_OP		26
+#define OP_MASK_RS		0x1f
+#define OP_SH_RS		21
+#define OP_MASK_FR		0x1f
+#define OP_SH_FR		21
+#define OP_MASK_FMT		0x1f
+#define OP_SH_FMT		21
+#define OP_MASK_BCC		0x7
+#define OP_SH_BCC		18
+#define OP_MASK_CODE		0x3ff
+#define OP_SH_CODE		16
+#define OP_MASK_CODE2		0x3ff
+#define OP_SH_CODE2		6
+#define OP_MASK_RT		0x1f
+#define OP_SH_RT		16
+#define OP_MASK_FT		0x1f
+#define OP_SH_FT		16
+#define OP_MASK_CACHE		0x1f
+#define OP_SH_CACHE		16
+#define OP_MASK_RD		0x1f
+#define OP_SH_RD		11
+#define OP_MASK_FS		0x1f
+#define OP_SH_FS		11
+#define OP_MASK_PREFX		0x1f
+#define OP_SH_PREFX		11
+#define OP_MASK_CCC		0x7
+#define OP_SH_CCC		8
+#define OP_MASK_CODE20		0xfffff /* 20 bit syscall/breakpoint code.  */
+#define OP_SH_CODE20		6
+#define OP_MASK_SHAMT		0x1f
+#define OP_SH_SHAMT		6
+#define OP_MASK_EXTLSB		OP_MASK_SHAMT
+#define OP_SH_EXTLSB		OP_SH_SHAMT
+#define OP_MASK_STYPE		OP_MASK_SHAMT
+#define OP_SH_STYPE		OP_SH_SHAMT
+#define OP_MASK_FD		0x1f
+#define OP_SH_FD		6
+#define OP_MASK_TARGET		0x3ffffff
+#define OP_SH_TARGET		0
+#define OP_MASK_COPZ		0x1ffffff
+#define OP_SH_COPZ		0
+#define OP_MASK_IMMEDIATE	0xffff
+#define OP_SH_IMMEDIATE		0
+#define OP_MASK_DELTA		0xffff
+#define OP_SH_DELTA		0
+#define OP_MASK_FUNCT		0x3f
+#define OP_SH_FUNCT		0
+#define OP_MASK_SPEC		0x3f
+#define OP_SH_SPEC		0
+#define OP_SH_LOCC              8       /* FP condition code.  */
+#define OP_SH_HICC              18      /* FP condition code.  */
+#define OP_MASK_CC              0x7
+#define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
+#define OP_MASK_COP1NORM        0x1     /* a single bit.  */
+#define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
+#define OP_MASK_COP1SPEC        0xf
+#define OP_MASK_COP1SCLR        0x4
+#define OP_MASK_COP1CMP         0x3
+#define OP_SH_COP1CMP           4
+#define OP_SH_FORMAT            21      /* FP short format field.  */
+#define OP_MASK_FORMAT          0x7
+#define OP_SH_TRUE              16
+#define OP_MASK_TRUE            0x1
+#define OP_SH_GE                17
+#define OP_MASK_GE              0x01
+#define OP_SH_UNSIGNED          16
+#define OP_MASK_UNSIGNED        0x1
+#define OP_SH_HINT              16
+#define OP_MASK_HINT            0x1f
+#define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
+#define OP_MASK_MMI             0x3f
+#define OP_SH_MMISUB            6
+#define OP_MASK_MMISUB          0x1f
+#define OP_MASK_PERFREG		0x1f	/* Performance monitoring.  */
+#define OP_SH_PERFREG		1
+#define OP_SH_SEL		0	/* Coprocessor select field.  */
+#define OP_MASK_SEL		0x7	/* The sel field of mfcZ and mtcZ.  */
+#define OP_SH_CODE19		6       /* 19 bit wait code.  */
+#define OP_MASK_CODE19		0x7ffff
+#define OP_SH_ALN		21
+#define OP_MASK_ALN		0x7
+#define OP_SH_VSEL		21
+#define OP_MASK_VSEL		0x1f
+#define OP_MASK_VECBYTE		0x7	/* Selector field is really 4 bits,
+					   but 0x8-0xf don't select bytes.  */
+#define OP_SH_VECBYTE		22
+#define OP_MASK_VECALIGN	0x7	/* Vector byte-align (alni.ob) op.  */
+#define OP_SH_VECALIGN		21
+#define OP_MASK_INSMSB		0x1f	/* "ins" MSB.  */
+#define OP_SH_INSMSB		11
+#define OP_MASK_EXTMSBD		0x1f	/* "ext" MSBD.  */
+#define OP_SH_EXTMSBD		11
+
+/* MIPS DSP ASE */
+#define OP_SH_DSPACC		11
+#define OP_MASK_DSPACC  	0x3
+#define OP_SH_DSPACC_S  	21
+#define OP_MASK_DSPACC_S	0x3
+#define OP_SH_DSPSFT		20
+#define OP_MASK_DSPSFT  	0x3f
+#define OP_SH_DSPSFT_7  	19
+#define OP_MASK_DSPSFT_7	0x7f
+#define OP_SH_SA3		21
+#define OP_MASK_SA3		0x7
+#define OP_SH_SA4		21
+#define OP_MASK_SA4		0xf
+#define OP_SH_IMM8		16
+#define OP_MASK_IMM8		0xff
+#define OP_SH_IMM10		16
+#define OP_MASK_IMM10		0x3ff
+#define OP_SH_WRDSP		11
+#define OP_MASK_WRDSP		0x3f
+#define OP_SH_RDDSP		16
+#define OP_MASK_RDDSP		0x3f
+#define OP_SH_BP		11
+#define OP_MASK_BP		0x3
+
+/* MIPS MT ASE */
+#define OP_SH_MT_U		5
+#define OP_MASK_MT_U		0x1
+#define OP_SH_MT_H		4
+#define OP_MASK_MT_H		0x1
+#define OP_SH_MTACC_T		18
+#define OP_MASK_MTACC_T		0x3
+#define OP_SH_MTACC_D		13
+#define OP_MASK_MTACC_D		0x3
+
+/* MIPS MCU ASE */
+#define OP_MASK_3BITPOS		0x7
+#define OP_SH_3BITPOS		12
+#define OP_MASK_OFFSET12	0xfff
+#define OP_SH_OFFSET12		0
+
+#define	OP_OP_COP0		0x10
+#define	OP_OP_COP1		0x11
+#define	OP_OP_COP2		0x12
+#define	OP_OP_COP3		0x13
+#define	OP_OP_LWC1		0x31
+#define	OP_OP_LWC2		0x32
+#define	OP_OP_LWC3		0x33	/* a.k.a. pref */
+#define	OP_OP_LDC1		0x35
+#define	OP_OP_LDC2		0x36
+#define	OP_OP_LDC3		0x37	/* a.k.a. ld */
+#define	OP_OP_SWC1		0x39
+#define	OP_OP_SWC2		0x3a
+#define	OP_OP_SWC3		0x3b
+#define	OP_OP_SDC1		0x3d
+#define	OP_OP_SDC2		0x3e
+#define	OP_OP_SDC3		0x3f	/* a.k.a. sd */
+
+/* MIPS VIRT ASE */
+#define OP_MASK_CODE10		0x3ff
+#define OP_SH_CODE10		11
+
+/* Values in the 'VSEL' field.  */
+#define MDMX_FMTSEL_IMM_QH	0x1d
+#define MDMX_FMTSEL_IMM_OB	0x1e
+#define MDMX_FMTSEL_VEC_QH	0x15
+#define MDMX_FMTSEL_VEC_OB	0x16
+
+/* UDI */
+#define OP_SH_UDI1		6
+#define OP_MASK_UDI1		0x1f
+#define OP_SH_UDI2		6
+#define OP_MASK_UDI2		0x3ff
+#define OP_SH_UDI3		6
+#define OP_MASK_UDI3		0x7fff
+#define OP_SH_UDI4		6
+#define OP_MASK_UDI4		0xfffff
+
+/* Octeon */
+#define OP_SH_BBITIND		16
+#define OP_MASK_BBITIND		0x1f
+#define OP_SH_CINSPOS		6
+#define OP_MASK_CINSPOS		0x1f
+#define OP_SH_CINSLM1		11
+#define OP_MASK_CINSLM1		0x1f
+#define OP_SH_SEQI		6
+#define OP_MASK_SEQI		0x3ff
+
+/* Loongson */
+#define OP_SH_OFFSET_A		6
+#define OP_MASK_OFFSET_A	0xff
+#define OP_SH_OFFSET_B		3
+#define OP_MASK_OFFSET_B	0xff
+#define OP_SH_OFFSET_C		6
+#define OP_MASK_OFFSET_C	0x1ff
+#define OP_SH_RZ		0
+#define OP_MASK_RZ		0x1f
+#define OP_SH_FZ		0
+#define OP_MASK_FZ		0x1f
+
+/* Every MICROMIPSOP_X definition requires a corresponding OP_X
+   definition, and vice versa.  This simplifies various parts
+   of the operand handling in GAS.  The fields below only exist
+   in the microMIPS encoding, so define each one to have an empty
+   range.  */
+#define OP_MASK_TRAP		0
+#define OP_SH_TRAP		0
+#define OP_MASK_OFFSET10	0
+#define OP_SH_OFFSET10		0
+#define OP_MASK_RS3		0
+#define OP_SH_RS3		0
+#define OP_MASK_MB		0
+#define OP_SH_MB		0
+#define OP_MASK_MC		0
+#define OP_SH_MC		0
+#define OP_MASK_MD		0
+#define OP_SH_MD		0
+#define OP_MASK_ME		0
+#define OP_SH_ME		0
+#define OP_MASK_MF		0
+#define OP_SH_MF		0
+#define OP_MASK_MG		0
+#define OP_SH_MG		0
+#define OP_MASK_MH		0
+#define OP_SH_MH		0
+#define OP_MASK_MJ		0
+#define OP_SH_MJ		0
+#define OP_MASK_ML		0
+#define OP_SH_ML		0
+#define OP_MASK_MM		0
+#define OP_SH_MM		0
+#define OP_MASK_MN		0
+#define OP_SH_MN		0
+#define OP_MASK_MP		0
+#define OP_SH_MP		0
+#define OP_MASK_MQ		0
+#define OP_SH_MQ		0
+#define OP_MASK_IMMA		0
+#define OP_SH_IMMA		0
+#define OP_MASK_IMMB		0
+#define OP_SH_IMMB		0
+#define OP_MASK_IMMC		0
+#define OP_SH_IMMC		0
+#define OP_MASK_IMMF		0
+#define OP_SH_IMMF		0
+#define OP_MASK_IMMG		0
+#define OP_SH_IMMG		0
+#define OP_MASK_IMMH		0
+#define OP_SH_IMMH		0
+#define OP_MASK_IMMI		0
+#define OP_SH_IMMI		0
+#define OP_MASK_IMMJ		0
+#define OP_SH_IMMJ		0
+#define OP_MASK_IMML		0
+#define OP_SH_IMML		0
+#define OP_MASK_IMMM		0
+#define OP_SH_IMMM		0
+#define OP_MASK_IMMN		0
+#define OP_SH_IMMN		0
+#define OP_MASK_IMMO		0
+#define OP_SH_IMMO		0
+#define OP_MASK_IMMP		0
+#define OP_SH_IMMP		0
+#define OP_MASK_IMMQ		0
+#define OP_SH_IMMQ		0
+#define OP_MASK_IMMU		0
+#define OP_SH_IMMU		0
+#define OP_MASK_IMMW		0
+#define OP_SH_IMMW		0
+#define OP_MASK_IMMX		0
+#define OP_SH_IMMX		0
+#define OP_MASK_IMMY		0
+#define OP_SH_IMMY		0
+
+/* Enhanced VA Scheme */
+#define OP_SH_EVAOFFSET		7
+#define OP_MASK_EVAOFFSET	0x1ff
+
+/* Enumerates the various types of MIPS operand.  */
+enum mips_operand_type {
+  /* Described by mips_int_operand.  */
+  OP_INT,
+
+  /* Described by mips_mapped_int_operand.  */
+  OP_MAPPED_INT,
+
+  /* Described by mips_msb_operand.  */
+  OP_MSB,
+
+  /* Described by mips_reg_operand.  */
+  OP_REG,
+
+  /* Like OP_REG, but can be omitted if the register is the same as the
+     previous operand.  */
+  OP_OPTIONAL_REG,
+
+  /* Described by mips_reg_pair_operand.  */
+  OP_REG_PAIR,
+
+  /* Described by mips_pcrel_operand.  */
+  OP_PCREL,
+
+  /* A performance register.  The field is 5 bits in size, but the supported
+     values are much more restricted.  */
+  OP_PERF_REG,
+
+  /* The final operand in a microMIPS ADDIUSP instruction.  It mostly acts
+     as a normal 9-bit signed offset that is multiplied by four, but there
+     are four special cases:
+
+     -2 * 4 => -258 * 4
+     -1 * 4 => -257 * 4
+      0 * 4 =>  256 * 4
+      1 * 4 =>  257 * 4.  */
+  OP_ADDIUSP_INT,
+
+  /* The target of a (D)CLO or (D)CLZ instruction.  The operand spans two
+     5-bit register fields, both of which must be set to the destination
+     register.  */
+  OP_CLO_CLZ_DEST,
+
+  /* A register list for a microMIPS LWM or SWM instruction.  The operand
+     size determines whether the 16-bit or 32-bit encoding is required.  */
+  OP_LWM_SWM_LIST,
+
+  /* The register list for an emulated MIPS16 ENTRY or EXIT instruction.  */
+  OP_ENTRY_EXIT_LIST,
+
+  /* The register list and frame size for a MIPS16 SAVE or RESTORE
+     instruction.  */
+  OP_SAVE_RESTORE_LIST,
+
+  /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions:
+
+     V      Meaning
+     -----  -------
+     0EEE0  8 copies of $vN[E], OB format
+     0EE01  4 copies of $vN[E], QH format
+     10110  all 8 elements of $vN, OB format
+     10101  all 4 elements of $vN, QH format
+     11110  8 copies of immediate N, OB format
+     11101  4 copies of immediate N, QH format.  */
+  OP_MDMX_IMM_REG,
+
+  /* A register operand that must match the destination register.  */
+  OP_REPEAT_DEST_REG,
+
+  /* A register operand that must match the previous register.  */
+  OP_REPEAT_PREV_REG,
+
+  /* $pc, which has no encoding in the architectural instruction.  */
+  OP_PC,
+
+  /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines
+     which.  */
+  OP_VU0_SUFFIX,
+
+  /* Like OP_VU0_SUFFIX, but used when the operand's value has already
+     been set.  Any suffix used here must match the previous value.  */
+  OP_VU0_MATCH_SUFFIX,
+
+  /* An index selected by an integer, e.g. [1].  */
+  OP_IMM_INDEX,
+
+  /* An index selected by a register, e.g. [$2].  */
+  OP_REG_INDEX
+};
+
+/* Enumerates the types of MIPS register.  */
+enum mips_reg_operand_type {
+  /* General registers $0-$31.  Software names like $at can also be used.  */
+  OP_REG_GP,
+
+  /* Floating-point registers $f0-$f31.  */
+  OP_REG_FP,
+
+  /* Coprocessor condition code registers $cc0-$cc7.  FPU condition codes
+     can also be written $fcc0-$fcc7.  */
+  OP_REG_CCC,
+
+  /* FPRs used in a vector capacity.  They can be written $f0-$f31
+     or $v0-$v31, although the latter form is not used for the VR5400
+     vector instructions.  */
+  OP_REG_VEC,
+
+  /* DSP accumulator registers $ac0-$ac3.  */
+  OP_REG_ACC,
+
+  /* Coprocessor registers $0-$31.  Mnemonic names like c0_cause can
+     also be used in some contexts.  */
+  OP_REG_COPRO,
+
+  /* Hardware registers $0-$31.  Mnemonic names like hwr_cpunum can
+     also be used in some contexts.  */
+  OP_REG_HW,
+
+  /* Floating-point registers $vf0-$vf31.  */
+  OP_REG_VF,
+
+  /* Integer registers $vi0-$vi31.  */
+  OP_REG_VI,
+
+  /* R5900 VU0 registers $I, $Q, $R and $ACC.  */
+  OP_REG_R5900_I,
+  OP_REG_R5900_Q,
+  OP_REG_R5900_R,
+  OP_REG_R5900_ACC,
+
+  /* MSA registers $w0-$w31.  */
+  OP_REG_MSA,
+
+  /* MSA control registers $0-$31.  */
+  OP_REG_MSA_CTRL
+};
+
+/* Base class for all operands.  */
+struct mips_operand
+{
+  /* The type of the operand.  */
+  enum mips_operand_type type;
+
+  /* The operand occupies SIZE bits of the instruction, starting at LSB.  */
+  unsigned short size;
+  unsigned short lsb;
+};
+
+/* Describes an integer operand with a regular encoding pattern.  */
+struct mips_int_operand
+{
+  struct mips_operand root;
+
+  /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT.
+     The cyclically previous field value encodes 1 << SHIFT less than that,
+     and so on.  E.g.
+
+     - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves,
+       but 15 encodes -1.
+
+     - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is
+       shifted left two places.
+
+     - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except
+       that 0 encodes 8.
+
+     - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3.  */
+  unsigned int max_val;
+  int bias;
+  unsigned int shift;
+
+  /* True if the operand should be printed as hex rather than decimal.  */
+  bfd_boolean print_hex;
+};
+
+/* Uses a lookup table to describe a small integer operand.  */
+struct mips_mapped_int_operand
+{
+  struct mips_operand root;
+
+  /* Maps each encoding value to the integer that it represents.  */
+  const int *int_map;
+
+  /* True if the operand should be printed as hex rather than decimal.  */
+  bfd_boolean print_hex;
+};
+
+/* An operand that encodes the most significant bit position of a bitfield.
+   Given a bitfield that spans bits [MSB, LSB], some operands of this type
+   encode MSB directly while others encode MSB - LSB.  Each operand of this
+   type is preceded by an integer operand that specifies LSB.
+
+   The assembly form varies between instructions.  For some instructions,
+   such as EXT, the operand is written as the bitfield size.  For others,
+   such as EXTS, it is written in raw MSB - LSB form.  */
+struct mips_msb_operand
+{
+  struct mips_operand root;
+
+  /* The assembly-level operand encoded by a field value of 0.  */
+  int bias;
+
+  /* True if the operand encodes MSB directly, false if it encodes
+     MSB - LSB.  */
+  bfd_boolean add_lsb;
+
+  /* The maximum value of MSB + 1.  */
+  unsigned int opsize;
+};
+
+/* Describes a single register operand.  */
+struct mips_reg_operand
+{
+  struct mips_operand root;
+
+  /* The type of register.  */
+  enum mips_reg_operand_type reg_type;
+
+  /* If nonnull, REG_MAP[N] gives the register associated with encoding N,
+     otherwise the encoding is the same as the register number.  */
+  const unsigned char *reg_map;
+};
+
+/* Describes an operand that encodes a pair of registers.  */
+struct mips_reg_pair_operand
+{
+  struct mips_operand root;
+
+  /* The type of register.  */
+  enum mips_reg_operand_type reg_type;
+
+  /* Encoding N represents REG1_MAP[N], REG2_MAP[N].  */
+  unsigned char *reg1_map;
+  unsigned char *reg2_map;
+};
+
+/* Describes an operand that is calculated relative to a base PC.
+   The base PC is usually the address of the following instruction,
+   but the rules for MIPS16 instructions like ADDIUPC are more complicated.  */
+struct mips_pcrel_operand
+{
+  /* Encodes the offset.  */
+  struct mips_int_operand root;
+
+  /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC',
+     which is then added to the offset encoded by ROOT.  */
+  unsigned int align_log2 : 8;
+
+  /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then
+     reinstated.  This is true for jumps and branches and false for
+     PC-relative data instructions.  */
+  unsigned int include_isa_bit : 1;
+
+  /* If FLIP_ISA_BIT, the ISA bit of the result is inverted.
+     This is true for JALX and false otherwise.  */
+  unsigned int flip_isa_bit : 1;
+};
+
+/* Return true if the assembly syntax allows OPERAND to be omitted.  */
+
+static inline bfd_boolean
+mips_optional_operand_p (const struct mips_operand *operand)
+{
+  return (operand->type == OP_OPTIONAL_REG
+	  || operand->type == OP_REPEAT_PREV_REG);
+}
+
+/* Return a version of INSN in which the field specified by OPERAND
+   has value UVAL.  */
+
+static inline unsigned int
+mips_insert_operand (const struct mips_operand *operand, unsigned int insn,
+		     unsigned int uval)
+{
+  unsigned int mask;
+
+  mask = (1 << operand->size) - 1;
+  insn &= ~(mask << operand->lsb);
+  insn |= (uval & mask) << operand->lsb;
+  return insn;
+}
+
+/* Extract OPERAND from instruction INSN.  */
+
+static inline unsigned int
+mips_extract_operand (const struct mips_operand *operand, unsigned int insn)
+{
+  return (insn >> operand->lsb) & ((1 << operand->size) - 1);
+}
+
+/* UVAL is the value encoded by OPERAND.  Return it in signed form.  */
+
+static inline int
+mips_signed_operand (const struct mips_operand *operand, unsigned int uval)
+{
+  unsigned int sign_bit, mask;
+
+  mask = (1 << operand->size) - 1;
+  sign_bit = 1 << (operand->size - 1);
+  return ((uval + sign_bit) & mask) - sign_bit;
+}
+
+/* Return the integer that OPERAND encodes as UVAL.  */
+
+static inline int
+mips_decode_int_operand (const struct mips_int_operand *operand,
+			 unsigned int uval)
+{
+  uval |= (operand->max_val - uval) & -(1 << operand->root.size);
+  uval += operand->bias;
+  uval <<= operand->shift;
+  return uval;
+}
+
+/* Return the maximum value that can be encoded by OPERAND.  */
+
+static inline int
+mips_int_operand_max (const struct mips_int_operand *operand)
+{
+  return (operand->max_val + operand->bias) << operand->shift;
+}
+
+/* Return the minimum value that can be encoded by OPERAND.  */
+
+static inline int
+mips_int_operand_min (const struct mips_int_operand *operand)
+{
+  unsigned int mask;
+
+  mask = (1 << operand->root.size) - 1;
+  return mips_int_operand_max (operand) - (mask << operand->shift);
+}
+
+/* Return the register that OPERAND encodes as UVAL.  */
+
+static inline int
+mips_decode_reg_operand (const struct mips_reg_operand *operand,
+			 unsigned int uval)
+{
+  if (operand->reg_map)
+    uval = operand->reg_map[uval];
+  return uval;
+}
+
+/* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC.
+   Return the address that it encodes.  */
+
+static inline bfd_vma
+mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand,
+			   bfd_vma base_pc, unsigned int uval)
+{
+  bfd_vma addr;
+
+  addr = base_pc & -(1 << operand->align_log2);
+  addr += mips_decode_int_operand (&operand->root, uval);
+  if (operand->include_isa_bit)
+    addr |= base_pc & 1;
+  if (operand->flip_isa_bit)
+    addr ^= 1;
+  return addr;
+}
+
+/* This structure holds information for a particular instruction.  */
+
+struct mips_opcode
+{
+  /* The name of the instruction.  */
+  const char *name;
+  /* A string describing the arguments for this instruction.  */
+  const char *args;
+  /* The basic opcode for the instruction.  When assembling, this
+     opcode is modified by the arguments to produce the actual opcode
+     that is used.  If pinfo is INSN_MACRO, then this is 0.  */
+  unsigned long match;
+  /* If pinfo is not INSN_MACRO, then this is a bit mask for the
+     relevant portions of the opcode when disassembling.  If the
+     actual opcode anded with the match field equals the opcode field,
+     then we have found the correct instruction.  If pinfo is
+     INSN_MACRO, then this field is the macro identifier.  */
+  unsigned long mask;
+  /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
+     of bits describing the instruction, notably any relevant hazard
+     information.  */
+  unsigned long pinfo;
+  /* A collection of additional bits describing the instruction. */
+  unsigned long pinfo2;
+  /* A collection of bits describing the instruction sets of which this
+     instruction or macro is a member. */
+  unsigned long membership;
+  /* A collection of bits describing the ASE of which this instruction
+     or macro is a member.  */
+  unsigned long ase;
+  /* A collection of bits describing the instruction sets of which this
+     instruction or macro is not a member.  */
+  unsigned long exclusions;
+};
+
+/* These are the characters which may appear in the args field of an
+   instruction.  They appear in the order in which the fields appear
+   when the instruction is used.  Commas and parentheses in the args
+   string are ignored when assembling, and written into the output
+   when disassembling.
+
+   Each of these characters corresponds to a mask field defined above.
+
+   "1" 5 bit sync type (OP_*_STYPE)
+   "<" 5 bit shift amount (OP_*_SHAMT)
+   ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
+   "a" 26 bit target address (OP_*_TARGET)
+   "+i" likewise, but flips bit 0
+   "b" 5 bit base register (OP_*_RS)
+   "c" 10 bit breakpoint code (OP_*_CODE)
+   "d" 5 bit destination register specifier (OP_*_RD)
+   "h" 5 bit prefx hint (OP_*_PREFX)
+   "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
+   "j" 16 bit signed immediate (OP_*_DELTA)
+   "k" 5 bit cache opcode in target register position (OP_*_CACHE)
+   "o" 16 bit signed offset (OP_*_DELTA)
+   "p" 16 bit PC relative branch target address (OP_*_DELTA)
+   "q" 10 bit extra breakpoint code (OP_*_CODE2)
+   "r" 5 bit same register used as both source and target (OP_*_RS)
+   "s" 5 bit source register specifier (OP_*_RS)
+   "t" 5 bit target register (OP_*_RT)
+   "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
+   "v" 5 bit same register used as both source and destination (OP_*_RS)
+   "w" 5 bit same register used as both target and destination (OP_*_RT)
+   "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
+       (used by clo and clz)
+   "C" 25 bit coprocessor function code (OP_*_COPZ)
+   "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
+   "J" 19 bit wait function code (OP_*_CODE19)
+   "x" accept and ignore register name
+   "z" must be zero register
+   "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
+   "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
+        LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
+        microMIPS compatibility).
+	Enforces: 0 <= pos < 32.
+   "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
+	Requires that "+A" or "+E" occur first to set position.
+	Enforces: 0 < (pos+size) <= 32.
+   "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
+	Requires that "+A" or "+E" occur first to set position.
+	Enforces: 0 < (pos+size) <= 32.
+	(Also used by "dext" w/ different limits, but limits for
+	that are checked by the M_DEXT macro.)
+   "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
+	Enforces: 32 <= pos < 64.
+   "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
+	Requires that "+A" or "+E" occur first to set position.
+	Enforces: 32 < (pos+size) <= 64.
+   "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
+	Requires that "+A" or "+E" occur first to set position.
+	Enforces: 32 < (pos+size) <= 64.
+   "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
+	Requires that "+A" or "+E" occur first to set position.
+	Enforces: 32 < (pos+size) <= 64.
+
+   Floating point instructions:
+   "D" 5 bit destination register (OP_*_FD)
+   "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
+   "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
+   "S" 5 bit fs source 1 register (OP_*_FS)
+   "T" 5 bit ft source 2 register (OP_*_FT)
+   "R" 5 bit fr source 3 register (OP_*_FR)
+   "V" 5 bit same register used as floating source and destination (OP_*_FS)
+   "W" 5 bit same register used as floating target and destination (OP_*_FT)
+
+   Coprocessor instructions:
+   "E" 5 bit target register (OP_*_RT)
+   "G" 5 bit destination register (OP_*_RD)
+   "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
+   "P" 5 bit performance-monitor register (OP_*_PERFREG)
+   "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
+   "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
+
+   Macro instructions:
+   "A" General 32 bit expression
+   "I" 32 bit immediate (value placed in imm_expr).
+   "F" 64 bit floating point constant in .rdata
+   "L" 64 bit floating point constant in .lit8
+   "f" 32 bit floating point constant
+   "l" 32 bit floating point constant in .lit4
+
+   MDMX and VR5400 instruction operands (note that while these use the
+   FP register fields, the MDMX instructions accept both $fN and $vN names
+   for the registers):
+   "O"	alignment offset (OP_*_ALN)
+   "Q"	vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
+   "X"	destination register (OP_*_FD)
+   "Y"	source register (OP_*_FS)
+   "Z"	source register (OP_*_FT)
+
+   R5900 VU0 Macromode instructions:
+   "+5" 5 bit floating point register (FD)
+   "+6" 5 bit floating point register (FS)
+   "+7" 5 bit floating point register (FT)
+   "+8" 5 bit integer register (FD)
+   "+9" 5 bit integer register (FS)
+   "+0" 5 bit integer register (FT)
+   "+K" match an existing 4-bit channel mask starting at bit 21
+   "+L" 2-bit channel index starting at bit 21
+   "+M" 2-bit channel index starting at bit 23
+   "+N" match an existing 2-bit channel index starting at bit 0
+   "+f" 15 bit immediate for VCALLMS
+   "+g" 5 bit signed immediate for VIADDI
+   "+m" $ACC register (syntax only)
+   "+q" $Q register (syntax only)
+   "+r" $R register (syntax only)
+   "+y" $I register (syntax only)
+   "#+" "++" decorator in ($reg++) sequence
+   "#-" "--" decorator in (--$reg) sequence
+
+   DSP ASE usage:
+   "2" 2 bit unsigned immediate for byte align (OP_*_BP)
+   "3" 3 bit unsigned immediate (OP_*_SA3)
+   "4" 4 bit unsigned immediate (OP_*_SA4)
+   "5" 8 bit unsigned immediate (OP_*_IMM8)
+   "6" 5 bit unsigned immediate (OP_*_RS)
+   "7" 2 bit dsp accumulator register (OP_*_DSPACC)
+   "8" 6 bit unsigned immediate (OP_*_WRDSP)
+   "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
+   "0" 6 bit signed immediate (OP_*_DSPSFT)
+   ":" 7 bit signed immediate (OP_*_DSPSFT_7)
+   "'" 6 bit unsigned immediate (OP_*_RDDSP)
+   "@" 10 bit signed immediate (OP_*_IMM10)
+
+   MT ASE usage:
+   "!" 1 bit usermode flag (OP_*_MT_U)
+   "$" 1 bit load high flag (OP_*_MT_H)
+   "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
+   "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
+   "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
+   "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
+
+   MCU ASE usage:
+   "~" 12 bit offset (OP_*_OFFSET12)
+   "\" 3 bit position for aset and aclr (OP_*_3BITPOS)
+
+   VIRT ASE usage:
+   "+J" 10-bit hypcall code (OP_*CODE10)
+
+   UDI immediates:
+   "+1" UDI immediate bits 6-10
+   "+2" UDI immediate bits 6-15
+   "+3" UDI immediate bits 6-20
+   "+4" UDI immediate bits 6-25
+
+   Octeon:
+   "+x" Bit index field of bbit.  Enforces: 0 <= index < 32.
+   "+X" Bit index field of bbit aliasing bbit32.  Matches if 32 <= index < 64,
+	otherwise skips to next candidate.
+   "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
+   "+P" Position field of cins/exts aliasing cins32/exts32.  Matches if
+	32 <= pos < 64, otherwise skips to next candidate.
+   "+Q" Immediate field of seqi/snei.  Enforces -512 <= imm < 512.
+   "+s" Length-minus-one field of cins32/exts32.  Requires msb position
+	of the field to be <= 31.
+   "+S" Length-minus-one field of cins/exts.  Requires msb position
+	of the field to be <= 63.
+
+   Loongson-3A:
+   "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
+   "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
+   "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
+   "+z" 5-bit rz register (OP_*_RZ)
+   "+Z" 5-bit fz register (OP_*_FZ)
+
+   Enhanced VA Scheme:
+   "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
+
+   MSA Extension:
+   "+d" 5-bit MSA register (FD)
+   "+e" 5-bit MSA register (FS)
+   "+h" 5-bit MSA register (FT)
+   "+k" 5-bit GPR at bit 6
+   "+l" 5-bit MSA control register at bit 6
+   "+n" 5-bit MSA control register at bit 11
+   "+o" 5-bit vector element index at bit 16
+   "+u" 4-bit vector element index at bit 16
+   "+v" 3-bit vector element index at bit 16
+   "+w" 2-bit vector element index at bit 16
+   "+T" (-512 .. 511) << 0 at bit 16
+   "+U" (-512 .. 511) << 1 at bit 16
+   "+V" (-512 .. 511) << 2 at bit 16
+   "+W" (-512 .. 511) << 3 at bit 16
+   "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
+   "+!" 3 bit unsigned bit position at bit 16
+   "+@" 4 bit unsigned bit position at bit 16
+   "+#" 6 bit unsigned bit position at bit 16
+   "+$" 5 bit unsigned immediate at bit 16
+   "+%" 5 bit signed immediate at bit 16
+   "+^" 10 bit signed immediate at bit 11
+   "+&" 0 vector element index
+   "+*" 5-bit register vector element index at bit 16
+   "+|" 8-bit mask at bit 16
+
+   Other:
+   "()" parens surrounding optional value
+   ","  separates operands
+   "+"  Start of extension sequence.
+
+   Characters used so far, for quick reference when adding more:
+   "1234567890"
+   "%[]<>(),+:'@!#$*&\~"
+   "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
+   "abcdefghijklopqrstuvwxz"
+
+   Extension character sequences used so far ("+" followed by the
+   following), for quick reference when adding more:
+   "1234567890"
+   "~!@#$%^&*|"
+   "ABCEFGHJKLMNPQSTUVWXZ"
+   "abcdefghijklmnopqrstuvwxyz"
+*/
+
+/* These are the bits which may be set in the pinfo field of an
+   instructions, if it is not equal to INSN_MACRO.  */
+
+/* Writes to operand number N.  */
+#define INSN_WRITE_SHIFT            0
+#define INSN_WRITE_1                0x00000001
+#define INSN_WRITE_2                0x00000002
+#define INSN_WRITE_ALL              0x00000003
+/* Reads from operand number N.  */
+#define INSN_READ_SHIFT             2
+#define INSN_READ_1                 0x00000004
+#define INSN_READ_2                 0x00000008
+#define INSN_READ_3                 0x00000010
+#define INSN_READ_4                 0x00000020
+#define INSN_READ_ALL               0x0000003c
+/* Modifies general purpose register 31.  */
+#define INSN_WRITE_GPR_31           0x00000040
+/* Modifies coprocessor condition code.  */
+#define INSN_WRITE_COND_CODE        0x00000080
+/* Reads coprocessor condition code.  */
+#define INSN_READ_COND_CODE         0x00000100
+/* TLB operation.  */
+#define INSN_TLB                    0x00000200
+/* Reads coprocessor register other than floating point register.  */
+#define INSN_COP                    0x00000400
+/* Instruction loads value from memory, requiring delay.  */
+#define INSN_LOAD_MEMORY_DELAY      0x00000800
+/* Instruction loads value from coprocessor, requiring delay.  */
+#define INSN_LOAD_COPROC_DELAY	    0x00001000
+/* Instruction has unconditional branch delay slot.  */
+#define INSN_UNCOND_BRANCH_DELAY    0x00002000
+/* Instruction has conditional branch delay slot.  */
+#define INSN_COND_BRANCH_DELAY      0x00004000
+/* Conditional branch likely: if branch not taken, insn nullified.  */
+#define INSN_COND_BRANCH_LIKELY	    0x00008000
+/* Moves to coprocessor register, requiring delay.  */
+#define INSN_COPROC_MOVE_DELAY      0x00010000
+/* Loads coprocessor register from memory, requiring delay.  */
+#define INSN_COPROC_MEMORY_DELAY    0x00020000
+/* Reads the HI register.  */
+#define INSN_READ_HI		    0x00040000
+/* Reads the LO register.  */
+#define INSN_READ_LO		    0x00080000
+/* Modifies the HI register.  */
+#define INSN_WRITE_HI		    0x00100000
+/* Modifies the LO register.  */
+#define INSN_WRITE_LO		    0x00200000
+/* Not to be placed in a branch delay slot, either architecturally
+   or for ease of handling (such as with instructions that take a trap).  */
+#define INSN_NO_DELAY_SLOT	    0x00400000
+/* Instruction stores value into memory.  */
+#define INSN_STORE_MEMORY	    0x00800000
+/* Instruction uses single precision floating point.  */
+#define FP_S			    0x01000000
+/* Instruction uses double precision floating point.  */
+#define FP_D			    0x02000000
+/* Instruction is part of the tx39's integer multiply family.    */
+#define INSN_MULT                   0x04000000
+/* Reads general purpose register 24.  */
+#define INSN_READ_GPR_24            0x08000000
+/* Writes to general purpose register 24.  */
+#define INSN_WRITE_GPR_24           0x10000000
+/* A user-defined instruction.  */
+#define INSN_UDI                    0x20000000
+/* Instruction is actually a macro.  It should be ignored by the
+   disassembler, and requires special treatment by the assembler.  */
+#define INSN_MACRO                  0xffffffff
+
+/* These are the bits which may be set in the pinfo2 field of an
+   instruction. */
+
+/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
+#define	INSN2_ALIAS		    0x00000001
+/* Instruction reads MDMX accumulator. */
+#define INSN2_READ_MDMX_ACC	    0x00000002
+/* Instruction writes MDMX accumulator. */
+#define INSN2_WRITE_MDMX_ACC	    0x00000004
+/* Macro uses single-precision floating-point instructions.  This should
+   only be set for macros.  For instructions, FP_S in pinfo carries the
+   same information.  */
+#define INSN2_M_FP_S		    0x00000008
+/* Macro uses double-precision floating-point instructions.  This should
+   only be set for macros.  For instructions, FP_D in pinfo carries the
+   same information.  */
+#define INSN2_M_FP_D		    0x00000010
+/* Instruction has a branch delay slot that requires a 16-bit instruction.  */
+#define INSN2_BRANCH_DELAY_16BIT    0x00000020
+/* Instruction has a branch delay slot that requires a 32-bit instruction.  */
+#define INSN2_BRANCH_DELAY_32BIT    0x00000040
+/* Writes to the stack pointer ($29).  */
+#define INSN2_WRITE_SP		    0x00000080
+/* Reads from the stack pointer ($29).  */
+#define INSN2_READ_SP		    0x00000100
+/* Reads the RA ($31) register.  */
+#define INSN2_READ_GPR_31	    0x00000200
+/* Reads the program counter ($pc).  */
+#define INSN2_READ_PC		    0x00000400
+/* Is an unconditional branch insn. */
+#define INSN2_UNCOND_BRANCH	    0x00000800
+/* Is a conditional branch insn. */
+#define INSN2_COND_BRANCH	    0x00001000
+/* Reads from $16.  This is true of the MIPS16 0x6500 nop.  */
+#define INSN2_READ_GPR_16           0x00002000
+/* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask.  */
+#define INSN2_VU0_CHANNEL_SUFFIX    0x00004000
+
+/* Masks used to mark instructions to indicate which MIPS ISA level
+   they were introduced in.  INSN_ISA_MASK masks an enumeration that
+   specifies the base ISA level(s).  The remainder of a 32-bit
+   word constructed using these macros is a bitmask of the remaining
+   INSN_* values below.  */
+
+#define INSN_ISA_MASK		  0x0000000ful
+
+/* We cannot start at zero due to ISA_UNKNOWN below.  */
+#define INSN_ISA1                 1
+#define INSN_ISA2                 2
+#define INSN_ISA3                 3
+#define INSN_ISA4                 4
+#define INSN_ISA5                 5
+#define INSN_ISA32                6
+#define INSN_ISA32R2              7
+#define INSN_ISA64                8
+#define INSN_ISA64R2              9
+/* Below this point the INSN_* values correspond to combinations of ISAs.
+   They are only for use in the opcodes table to indicate membership of
+   a combination of ISAs that cannot be expressed using the usual inclusion
+   ordering on the above INSN_* values.  */
+#define INSN_ISA3_32              10
+#define INSN_ISA3_32R2            11
+#define INSN_ISA4_32              12
+#define INSN_ISA4_32R2            13
+#define INSN_ISA5_32R2            14
+
+/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
+   INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
+   this table describes whether at least one of the ISAs described by X
+   is/are implemented by ISA Y.  (Think of Y as the ISA level supported by
+   a particular core and X as the ISA level(s) at which a certain instruction
+   is defined.)  The ISA(s) described by X is/are implemented by Y iff
+   (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
+   is non-zero.  */
+static const unsigned int mips_isa_table[] =
+  { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
+
+/* Masks used for Chip specific instructions.  */
+#define INSN_CHIP_MASK		  0xc3ff0f20
+
+/* Cavium Networks Octeon instructions.  */
+#define INSN_OCTEON		  0x00000800
+#define INSN_OCTEONP		  0x00000200
+#define INSN_OCTEON2		  0x00000100
+
+/* MIPS R5900 instruction */
+#define INSN_5900                 0x00004000
+
+/* MIPS R4650 instruction.  */
+#define INSN_4650                 0x00010000
+/* LSI R4010 instruction.  */
+#define INSN_4010                 0x00020000
+/* NEC VR4100 instruction.  */
+#define INSN_4100                 0x00040000
+/* Toshiba R3900 instruction.  */
+#define INSN_3900                 0x00080000
+/* MIPS R10000 instruction.  */
+#define INSN_10000                0x00100000
+/* Broadcom SB-1 instruction.  */
+#define INSN_SB1                  0x00200000
+/* NEC VR4111/VR4181 instruction.  */
+#define INSN_4111                 0x00400000
+/* NEC VR4120 instruction.  */
+#define INSN_4120                 0x00800000
+/* NEC VR5400 instruction.  */
+#define INSN_5400		  0x01000000
+/* NEC VR5500 instruction.  */
+#define INSN_5500		  0x02000000
+
+/* ST Microelectronics Loongson 2E.  */
+#define INSN_LOONGSON_2E          0x40000000
+/* ST Microelectronics Loongson 2F.  */
+#define INSN_LOONGSON_2F          0x80000000
+/* Loongson 3A.  */
+#define INSN_LOONGSON_3A          0x00000400
+/* RMI Xlr instruction */
+#define INSN_XLR                 0x00000020
+
+/* DSP ASE */
+#define ASE_DSP			0x00000001
+#define ASE_DSP64		0x00000002
+/* DSP R2 ASE  */
+#define ASE_DSPR2		0x00000004
+/* Enhanced VA Scheme */
+#define ASE_EVA			0x00000008
+/* MCU (MicroController) ASE */
+#define ASE_MCU			0x00000010
+/* MDMX ASE */
+#define ASE_MDMX		0x00000020
+/* MIPS-3D ASE */
+#define ASE_MIPS3D		0x00000040
+/* MT ASE */
+#define ASE_MT			0x00000080
+/* SmartMIPS ASE  */
+#define ASE_SMARTMIPS		0x00000100
+/* Virtualization ASE */
+#define ASE_VIRT		0x00000200
+#define ASE_VIRT64		0x00000400
+/* MSA Extension  */
+#define ASE_MSA			0x00000800
+#define ASE_MSA64		0x00001000
+
+/* MIPS ISA defines, use instead of hardcoding ISA level.  */
+
+#define       ISA_UNKNOWN     0               /* Gas internal use.  */
+#define       ISA_MIPS1       INSN_ISA1
+#define       ISA_MIPS2       INSN_ISA2
+#define       ISA_MIPS3       INSN_ISA3
+#define       ISA_MIPS4       INSN_ISA4
+#define       ISA_MIPS5       INSN_ISA5
+
+#define       ISA_MIPS32      INSN_ISA32
+#define       ISA_MIPS64      INSN_ISA64
+
+#define       ISA_MIPS32R2    INSN_ISA32R2
+#define       ISA_MIPS64R2    INSN_ISA64R2
+
+
+/* CPU defines, use instead of hardcoding processor number. Keep this
+   in sync with bfd/archures.c in order for machine selection to work.  */
+#define CPU_UNKNOWN	0               /* Gas internal use.  */
+#define CPU_R3000	3000
+#define CPU_R3900	3900
+#define CPU_R4000	4000
+#define CPU_R4010	4010
+#define CPU_VR4100	4100
+#define CPU_R4111	4111
+#define CPU_VR4120	4120
+#define CPU_R4300	4300
+#define CPU_R4400	4400
+#define CPU_R4600	4600
+#define CPU_R4650	4650
+#define CPU_R5000	5000
+#define CPU_VR5400	5400
+#define CPU_VR5500	5500
+#define CPU_R5900	5900
+#define CPU_R6000	6000
+#define CPU_RM7000	7000
+#define CPU_R8000	8000
+#define CPU_RM9000	9000
+#define CPU_R10000	10000
+#define CPU_R12000	12000
+#define CPU_R14000	14000
+#define CPU_R16000	16000
+#define CPU_MIPS16	16
+#define CPU_MIPS32	32
+#define CPU_MIPS32R2	33
+#define CPU_MIPS5       5
+#define CPU_MIPS64      64
+#define CPU_MIPS64R2	65
+#define CPU_SB1         12310201        /* octal 'SB', 01.  */
+#define CPU_LOONGSON_2E 3001
+#define CPU_LOONGSON_2F 3002
+#define CPU_LOONGSON_3A 3003
+#define CPU_OCTEON	6501
+#define CPU_OCTEONP	6601
+#define CPU_OCTEON2	6502
+#define CPU_XLR     	887682   	/* decimal 'XLR'   */
+
+/* Return true if the given CPU is included in INSN_* mask MASK.  */
+
+static inline bfd_boolean
+cpu_is_member (int cpu, unsigned int mask)
+{
+  switch (cpu)
+    {
+    case CPU_R4650:
+    case CPU_RM7000:
+    case CPU_RM9000:
+      return (mask & INSN_4650) != 0;
+
+    case CPU_R4010:
+      return (mask & INSN_4010) != 0;
+
+    case CPU_VR4100:
+      return (mask & INSN_4100) != 0;
+
+    case CPU_R3900:
+      return (mask & INSN_3900) != 0;
+
+    case CPU_R10000:
+    case CPU_R12000:
+    case CPU_R14000:
+    case CPU_R16000:
+      return (mask & INSN_10000) != 0;
+
+    case CPU_SB1:
+      return (mask & INSN_SB1) != 0;
+
+    case CPU_R4111:
+      return (mask & INSN_4111) != 0;
+
+    case CPU_VR4120:
+      return (mask & INSN_4120) != 0;
+
+    case CPU_VR5400:
+      return (mask & INSN_5400) != 0;
+
+    case CPU_VR5500:
+      return (mask & INSN_5500) != 0;
+
+    case CPU_R5900:
+      return (mask & INSN_5900) != 0;
+
+    case CPU_LOONGSON_2E:
+      return (mask & INSN_LOONGSON_2E) != 0;
+
+    case CPU_LOONGSON_2F:
+      return (mask & INSN_LOONGSON_2F) != 0;
+
+    case CPU_LOONGSON_3A:
+      return (mask & INSN_LOONGSON_3A) != 0;
+
+    case CPU_OCTEON:
+      return (mask & INSN_OCTEON) != 0;
+
+    case CPU_OCTEONP:
+      return (mask & INSN_OCTEONP) != 0;
+
+    case CPU_OCTEON2:
+      return (mask & INSN_OCTEON2) != 0;
+
+    case CPU_XLR:
+      return (mask & INSN_XLR) != 0;
+
+    default:
+      return FALSE;
+    }
+}
+
+/* Test for membership in an ISA including chip specific ISAs.  INSN
+   is pointer to an element of the opcode table; ISA is the specified
+   ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
+   test, or zero if no CPU specific ISA test is desired.  Return true
+   if instruction INSN is available to the given ISA and CPU. */
+
+static inline bfd_boolean
+opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
+{
+  if (!cpu_is_member (cpu, insn->exclusions))
+    {
+      /* Test for ISA level compatibility.  */
+      if ((isa & INSN_ISA_MASK) != 0
+	  && (insn->membership & INSN_ISA_MASK) != 0
+	  && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
+	       >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
+	return TRUE;
+
+      /* Test for ASE compatibility.  */
+      if ((ase & insn->ase) != 0)
+	return TRUE;
+
+      /* Test for processor-specific extensions.  */
+      if (cpu_is_member (cpu, insn->membership))
+	return TRUE;
+    }
+  return FALSE;
+}
+
+/* This is a list of macro expanded instructions.
+
+   _I appended means immediate
+   _A appended means target address of a jump
+   _AB appended means address with (possibly zero) base register
+   _D appended means 64 bit floating point constant
+   _S appended means 32 bit floating point constant.  */
+
+enum
+{
+  M_ABS,
+  M_ACLR_AB,
+  M_ADD_I,
+  M_ADDU_I,
+  M_AND_I,
+  M_ASET_AB,
+  M_BALIGN,
+  M_BC1FL,
+  M_BC1TL,
+  M_BC2FL,
+  M_BC2TL,
+  M_BEQ,
+  M_BEQ_I,
+  M_BEQL,
+  M_BEQL_I,
+  M_BGE,
+  M_BGEL,
+  M_BGE_I,
+  M_BGEL_I,
+  M_BGEU,
+  M_BGEUL,
+  M_BGEU_I,
+  M_BGEUL_I,
+  M_BGEZ,
+  M_BGEZL,
+  M_BGEZALL,
+  M_BGT,
+  M_BGTL,
+  M_BGT_I,
+  M_BGTL_I,
+  M_BGTU,
+  M_BGTUL,
+  M_BGTU_I,
+  M_BGTUL_I,
+  M_BGTZ,
+  M_BGTZL,
+  M_BLE,
+  M_BLEL,
+  M_BLE_I,
+  M_BLEL_I,
+  M_BLEU,
+  M_BLEUL,
+  M_BLEU_I,
+  M_BLEUL_I,
+  M_BLEZ,
+  M_BLEZL,
+  M_BLT,
+  M_BLTL,
+  M_BLT_I,
+  M_BLTL_I,
+  M_BLTU,
+  M_BLTUL,
+  M_BLTU_I,
+  M_BLTUL_I,
+  M_BLTZ,
+  M_BLTZL,
+  M_BLTZALL,
+  M_BNE,
+  M_BNEL,
+  M_BNE_I,
+  M_BNEL_I,
+  M_CACHE_AB,
+  M_CACHEE_AB,
+  M_DABS,
+  M_DADD_I,
+  M_DADDU_I,
+  M_DDIV_3,
+  M_DDIV_3I,
+  M_DDIVU_3,
+  M_DDIVU_3I,
+  M_DIV_3,
+  M_DIV_3I,
+  M_DIVU_3,
+  M_DIVU_3I,
+  M_DLA_AB,
+  M_DLCA_AB,
+  M_DLI,
+  M_DMUL,
+  M_DMUL_I,
+  M_DMULO,
+  M_DMULO_I,
+  M_DMULOU,
+  M_DMULOU_I,
+  M_DREM_3,
+  M_DREM_3I,
+  M_DREMU_3,
+  M_DREMU_3I,
+  M_DSUB_I,
+  M_DSUBU_I,
+  M_DSUBU_I_2,
+  M_J_A,
+  M_JAL_1,
+  M_JAL_2,
+  M_JAL_A,
+  M_JALS_1,
+  M_JALS_2,
+  M_JALS_A,
+  M_JRADDIUSP,
+  M_JRC,
+  M_L_DAB,
+  M_LA_AB,
+  M_LB_AB,
+  M_LBE_AB,
+  M_LBU_AB,
+  M_LBUE_AB,
+  M_LCA_AB,
+  M_LD_AB,
+  M_LDC1_AB,
+  M_LDC2_AB,
+  M_LQC2_AB,
+  M_LDC3_AB,
+  M_LDL_AB,
+  M_LDM_AB,
+  M_LDP_AB,
+  M_LDR_AB,
+  M_LH_AB,
+  M_LHE_AB,
+  M_LHU_AB,
+  M_LHUE_AB,
+  M_LI,
+  M_LI_D,
+  M_LI_DD,
+  M_LI_S,
+  M_LI_SS,
+  M_LL_AB,
+  M_LLD_AB,
+  M_LLE_AB,
+  M_LQ_AB,
+  M_LW_AB,
+  M_LWE_AB,
+  M_LWC0_AB,
+  M_LWC1_AB,
+  M_LWC2_AB,
+  M_LWC3_AB,
+  M_LWL_AB,
+  M_LWLE_AB,
+  M_LWM_AB,
+  M_LWP_AB,
+  M_LWR_AB,
+  M_LWRE_AB,
+  M_LWU_AB,
+  M_MSGSND,
+  M_MSGLD,
+  M_MSGLD_T,
+  M_MSGWAIT,
+  M_MSGWAIT_T,
+  M_MOVE,
+  M_MOVEP,
+  M_MUL,
+  M_MUL_I,
+  M_MULO,
+  M_MULO_I,
+  M_MULOU,
+  M_MULOU_I,
+  M_NOR_I,
+  M_OR_I,
+  M_PREF_AB,
+  M_PREFE_AB,
+  M_REM_3,
+  M_REM_3I,
+  M_REMU_3,
+  M_REMU_3I,
+  M_DROL,
+  M_ROL,
+  M_DROL_I,
+  M_ROL_I,
+  M_DROR,
+  M_ROR,
+  M_DROR_I,
+  M_ROR_I,
+  M_S_DA,
+  M_S_DAB,
+  M_S_S,
+  M_SAA_AB,
+  M_SAAD_AB,
+  M_SC_AB,
+  M_SCD_AB,
+  M_SCE_AB,
+  M_SD_AB,
+  M_SDC1_AB,
+  M_SDC2_AB,
+  M_SQC2_AB,
+  M_SDC3_AB,
+  M_SDL_AB,
+  M_SDM_AB,
+  M_SDP_AB,
+  M_SDR_AB,
+  M_SEQ,
+  M_SEQ_I,
+  M_SGE,
+  M_SGE_I,
+  M_SGEU,
+  M_SGEU_I,
+  M_SGT,
+  M_SGT_I,
+  M_SGTU,
+  M_SGTU_I,
+  M_SLE,
+  M_SLE_I,
+  M_SLEU,
+  M_SLEU_I,
+  M_SLT_I,
+  M_SLTU_I,
+  M_SNE,
+  M_SNE_I,
+  M_SB_AB,
+  M_SBE_AB,
+  M_SH_AB,
+  M_SHE_AB,
+  M_SQ_AB,
+  M_SW_AB,
+  M_SWE_AB,
+  M_SWC0_AB,
+  M_SWC1_AB,
+  M_SWC2_AB,
+  M_SWC3_AB,
+  M_SWL_AB,
+  M_SWLE_AB,
+  M_SWM_AB,
+  M_SWP_AB,
+  M_SWR_AB,
+  M_SWRE_AB,
+  M_SUB_I,
+  M_SUBU_I,
+  M_SUBU_I_2,
+  M_TEQ_I,
+  M_TGE_I,
+  M_TGEU_I,
+  M_TLT_I,
+  M_TLTU_I,
+  M_TNE_I,
+  M_TRUNCWD,
+  M_TRUNCWS,
+  M_ULD_AB,
+  M_ULH_AB,
+  M_ULHU_AB,
+  M_ULW_AB,
+  M_USH_AB,
+  M_USW_AB,
+  M_USD_AB,
+  M_XOR_I,
+  M_COP0,
+  M_COP1,
+  M_COP2,
+  M_COP3,
+  M_NUM_MACROS
+};
+
+
+/* The order of overloaded instructions matters.  Label arguments and
+   register arguments look the same. Instructions that can have either
+   for arguments must apear in the correct order in this table for the
+   assembler to pick the right one. In other words, entries with
+   immediate operands must apear after the same instruction with
+   registers.
+
+   Many instructions are short hand for other instructions (i.e., The
+   jal <register> instruction is short for jalr <register>).  */
+
+extern const struct mips_operand mips_vu0_channel_mask;
+extern const struct mips_operand *decode_mips_operand (const char *);
+extern const struct mips_opcode mips_builtin_opcodes[];
+extern const int bfd_mips_num_builtin_opcodes;
+extern struct mips_opcode *mips_opcodes;
+extern int bfd_mips_num_opcodes;
+#define NUMOPCODES bfd_mips_num_opcodes
+
+
+/* The rest of this file adds definitions for the mips16 TinyRISC
+   processor.  */
+
+/* These are the bitmasks and shift counts used for the different
+   fields in the instruction formats.  Other than OP, no masks are
+   provided for the fixed portions of an instruction, since they are
+   not needed.
+
+   The I format uses IMM11.
+
+   The RI format uses RX and IMM8.
+
+   The RR format uses RX, and RY.
+
+   The RRI format uses RX, RY, and IMM5.
+
+   The RRR format uses RX, RY, and RZ.
+
+   The RRI_A format uses RX, RY, and IMM4.
+
+   The SHIFT format uses RX, RY, and SHAMT.
+
+   The I8 format uses IMM8.
+
+   The I8_MOVR32 format uses RY and REGR32.
+
+   The IR_MOV32R format uses REG32R and MOV32Z.
+
+   The I64 format uses IMM8.
+
+   The RI64 format uses RY and IMM5.
+   */
+
+#define MIPS16OP_MASK_OP	0x1f
+#define MIPS16OP_SH_OP		11
+#define MIPS16OP_MASK_IMM11	0x7ff
+#define MIPS16OP_SH_IMM11	0
+#define MIPS16OP_MASK_RX	0x7
+#define MIPS16OP_SH_RX		8
+#define MIPS16OP_MASK_IMM8	0xff
+#define MIPS16OP_SH_IMM8	0
+#define MIPS16OP_MASK_RY	0x7
+#define MIPS16OP_SH_RY		5
+#define MIPS16OP_MASK_IMM5	0x1f
+#define MIPS16OP_SH_IMM5	0
+#define MIPS16OP_MASK_RZ	0x7
+#define MIPS16OP_SH_RZ		2
+#define MIPS16OP_MASK_IMM4	0xf
+#define MIPS16OP_SH_IMM4	0
+#define MIPS16OP_MASK_REGR32	0x1f
+#define MIPS16OP_SH_REGR32	0
+#define MIPS16OP_MASK_REG32R	0x1f
+#define MIPS16OP_SH_REG32R	3
+#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
+#define MIPS16OP_MASK_MOVE32Z	0x7
+#define MIPS16OP_SH_MOVE32Z	0
+#define MIPS16OP_MASK_IMM6	0x3f
+#define MIPS16OP_SH_IMM6	5
+
+/* These are the characters which may appears in the args field of a MIPS16
+   instruction.  They appear in the order in which the fields appear when the
+   instruction is used.  Commas and parentheses in the args string are ignored
+   when assembling, and written into the output when disassembling.
+
+   "y" 3 bit register (MIPS16OP_*_RY)
+   "x" 3 bit register (MIPS16OP_*_RX)
+   "z" 3 bit register (MIPS16OP_*_RZ)
+   "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
+   "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
+   "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
+   "0" zero register ($0)
+   "S" stack pointer ($sp or $29)
+   "P" program counter
+   "R" return address register ($ra or $31)
+   "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
+   "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
+   "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
+   "a" 26 bit jump address
+   "i" likewise, but flips bit 0
+   "e" 11 bit extension value
+   "l" register list for entry instruction
+   "L" register list for exit instruction
+
+   "I" an immediate value used for macros
+
+   The remaining codes may be extended.  Except as otherwise noted,
+   the full extended operand is a 16 bit signed value.
+   "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
+   ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
+   "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
+   "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
+   "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
+   "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
+   "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
+   "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
+   "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
+   "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
+   "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
+   "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
+   "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
+   "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
+   "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
+   "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
+   "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
+   "q" 11 bit branch address (MIPS16OP_*_IMM11)
+   "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
+   "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
+   "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
+   "m" 7 bit register list for save instruction (18 bit extended)
+   "M" 7 bit register list for restore instruction (18 bit extended)
+  */
+
+/* Save/restore encoding for the args field when all 4 registers are
+   either saved as arguments or saved/restored as statics.  */
+#define MIPS16_ALL_ARGS    0xe
+#define MIPS16_ALL_STATICS 0xb
+
+/* The following flags have the same value for the mips16 opcode
+   table:
+
+   INSN_ISA3
+
+   INSN_UNCOND_BRANCH_DELAY
+   INSN_COND_BRANCH_DELAY
+   INSN_COND_BRANCH_LIKELY (never used)
+   INSN_READ_HI
+   INSN_READ_LO
+   INSN_WRITE_HI
+   INSN_WRITE_LO
+   INSN_TRAP
+   FP_D (never used)
+   */
+
+extern const struct mips_operand *decode_mips16_operand (char, bfd_boolean);
+extern const struct mips_opcode mips16_opcodes[];
+extern const int bfd_mips16_num_opcodes;
+
+/* These are the bit masks and shift counts used for the different fields
+   in the microMIPS instruction formats.  No masks are provided for the
+   fixed portions of an instruction, since they are not needed.  */
+
+#define MICROMIPSOP_MASK_IMMEDIATE	0xffff
+#define MICROMIPSOP_SH_IMMEDIATE	0
+#define MICROMIPSOP_MASK_DELTA		0xffff
+#define MICROMIPSOP_SH_DELTA		0
+#define MICROMIPSOP_MASK_CODE10		0x3ff
+#define MICROMIPSOP_SH_CODE10		16	/* 10-bit wait code.  */
+#define MICROMIPSOP_MASK_TRAP		0xf
+#define MICROMIPSOP_SH_TRAP		12	/* 4-bit trap code.  */
+#define MICROMIPSOP_MASK_SHAMT		0x1f
+#define MICROMIPSOP_SH_SHAMT		11
+#define MICROMIPSOP_MASK_TARGET		0x3ffffff
+#define MICROMIPSOP_SH_TARGET		0
+#define MICROMIPSOP_MASK_EXTLSB		0x1f	/* "ext" LSB.  */
+#define MICROMIPSOP_SH_EXTLSB		6
+#define MICROMIPSOP_MASK_EXTMSBD	0x1f	/* "ext" MSBD.  */
+#define MICROMIPSOP_SH_EXTMSBD		11
+#define MICROMIPSOP_MASK_INSMSB		0x1f	/* "ins" MSB.  */
+#define MICROMIPSOP_SH_INSMSB		11
+#define MICROMIPSOP_MASK_CODE		0x3ff
+#define MICROMIPSOP_SH_CODE		16	/* 10-bit higher break code. */
+#define MICROMIPSOP_MASK_CODE2		0x3ff
+#define MICROMIPSOP_SH_CODE2		6	/* 10-bit lower break code.  */
+#define MICROMIPSOP_MASK_CACHE		0x1f
+#define MICROMIPSOP_SH_CACHE		21	/* 5-bit cache op.  */
+#define MICROMIPSOP_MASK_SEL		0x7
+#define MICROMIPSOP_SH_SEL		11
+#define MICROMIPSOP_MASK_OFFSET12	0xfff
+#define MICROMIPSOP_SH_OFFSET12		0
+#define MICROMIPSOP_MASK_3BITPOS	0x7
+#define MICROMIPSOP_SH_3BITPOS		21
+#define MICROMIPSOP_MASK_STYPE		0x1f
+#define MICROMIPSOP_SH_STYPE		16
+#define MICROMIPSOP_MASK_OFFSET10	0x3ff
+#define MICROMIPSOP_SH_OFFSET10		6
+#define MICROMIPSOP_MASK_RS		0x1f
+#define MICROMIPSOP_SH_RS		16
+#define MICROMIPSOP_MASK_RT		0x1f
+#define MICROMIPSOP_SH_RT		21
+#define MICROMIPSOP_MASK_RD		0x1f
+#define MICROMIPSOP_SH_RD		11
+#define MICROMIPSOP_MASK_FS		0x1f
+#define MICROMIPSOP_SH_FS		16
+#define MICROMIPSOP_MASK_FT		0x1f
+#define MICROMIPSOP_SH_FT		21
+#define MICROMIPSOP_MASK_FD		0x1f
+#define MICROMIPSOP_SH_FD		11
+#define MICROMIPSOP_MASK_FR		0x1f
+#define MICROMIPSOP_SH_FR		6
+#define MICROMIPSOP_MASK_RS3		0x1f
+#define MICROMIPSOP_SH_RS3		6
+#define MICROMIPSOP_MASK_PREFX		0x1f
+#define MICROMIPSOP_SH_PREFX		11
+#define MICROMIPSOP_MASK_BCC		0x7
+#define MICROMIPSOP_SH_BCC		18
+#define MICROMIPSOP_MASK_CCC		0x7
+#define MICROMIPSOP_SH_CCC		13
+#define MICROMIPSOP_MASK_COPZ		0x7fffff
+#define MICROMIPSOP_SH_COPZ		3
+
+#define MICROMIPSOP_MASK_MB		0x7
+#define MICROMIPSOP_SH_MB		23
+#define MICROMIPSOP_MASK_MC		0x7
+#define MICROMIPSOP_SH_MC		4
+#define MICROMIPSOP_MASK_MD		0x7
+#define MICROMIPSOP_SH_MD		7
+#define MICROMIPSOP_MASK_ME		0x7
+#define MICROMIPSOP_SH_ME		1
+#define MICROMIPSOP_MASK_MF		0x7
+#define MICROMIPSOP_SH_MF		3
+#define MICROMIPSOP_MASK_MG		0x7
+#define MICROMIPSOP_SH_MG		0
+#define MICROMIPSOP_MASK_MH		0x7
+#define MICROMIPSOP_SH_MH		7
+#define MICROMIPSOP_MASK_MJ		0x1f
+#define MICROMIPSOP_SH_MJ		0
+#define MICROMIPSOP_MASK_ML		0x7
+#define MICROMIPSOP_SH_ML		4
+#define MICROMIPSOP_MASK_MM		0x7
+#define MICROMIPSOP_SH_MM		1
+#define MICROMIPSOP_MASK_MN		0x7
+#define MICROMIPSOP_SH_MN		4
+#define MICROMIPSOP_MASK_MP		0x1f
+#define MICROMIPSOP_SH_MP		5
+#define MICROMIPSOP_MASK_MQ		0x7
+#define MICROMIPSOP_SH_MQ		7
+
+#define MICROMIPSOP_MASK_IMMA		0x7f
+#define MICROMIPSOP_SH_IMMA		0
+#define MICROMIPSOP_MASK_IMMB		0x7
+#define MICROMIPSOP_SH_IMMB		1
+#define MICROMIPSOP_MASK_IMMC		0xf
+#define MICROMIPSOP_SH_IMMC		0
+#define MICROMIPSOP_MASK_IMMD		0x3ff
+#define MICROMIPSOP_SH_IMMD		0
+#define MICROMIPSOP_MASK_IMME		0x7f
+#define MICROMIPSOP_SH_IMME		0
+#define MICROMIPSOP_MASK_IMMF		0xf
+#define MICROMIPSOP_SH_IMMF		0
+#define MICROMIPSOP_MASK_IMMG		0xf
+#define MICROMIPSOP_SH_IMMG		0
+#define MICROMIPSOP_MASK_IMMH		0xf
+#define MICROMIPSOP_SH_IMMH		0
+#define MICROMIPSOP_MASK_IMMI		0x7f
+#define MICROMIPSOP_SH_IMMI		0
+#define MICROMIPSOP_MASK_IMMJ		0xf
+#define MICROMIPSOP_SH_IMMJ		0
+#define MICROMIPSOP_MASK_IMML		0xf
+#define MICROMIPSOP_SH_IMML		0
+#define MICROMIPSOP_MASK_IMMM		0x7
+#define MICROMIPSOP_SH_IMMM		1
+#define MICROMIPSOP_MASK_IMMN		0x3
+#define MICROMIPSOP_SH_IMMN		4
+#define MICROMIPSOP_MASK_IMMO		0xf
+#define MICROMIPSOP_SH_IMMO		0
+#define MICROMIPSOP_MASK_IMMP		0x1f
+#define MICROMIPSOP_SH_IMMP		0
+#define MICROMIPSOP_MASK_IMMQ		0x7fffff
+#define MICROMIPSOP_SH_IMMQ		0
+#define MICROMIPSOP_MASK_IMMU		0x1f
+#define MICROMIPSOP_SH_IMMU		0
+#define MICROMIPSOP_MASK_IMMW		0x3f
+#define MICROMIPSOP_SH_IMMW		1
+#define MICROMIPSOP_MASK_IMMX		0xf
+#define MICROMIPSOP_SH_IMMX		1
+#define MICROMIPSOP_MASK_IMMY		0x1ff
+#define MICROMIPSOP_SH_IMMY		1
+
+/* MIPS DSP ASE */
+#define MICROMIPSOP_MASK_DSPACC		0x3
+#define MICROMIPSOP_SH_DSPACC		14
+#define MICROMIPSOP_MASK_DSPSFT		0x3f
+#define MICROMIPSOP_SH_DSPSFT		16
+#define MICROMIPSOP_MASK_SA3		0x7
+#define MICROMIPSOP_SH_SA3		13
+#define MICROMIPSOP_MASK_SA4		0xf
+#define MICROMIPSOP_SH_SA4		12
+#define MICROMIPSOP_MASK_IMM8		0xff
+#define MICROMIPSOP_SH_IMM8		13
+#define MICROMIPSOP_MASK_IMM10		0x3ff
+#define MICROMIPSOP_SH_IMM10		16
+#define MICROMIPSOP_MASK_WRDSP		0x3f
+#define MICROMIPSOP_SH_WRDSP		14
+#define MICROMIPSOP_MASK_BP		0x3
+#define MICROMIPSOP_SH_BP		14
+
+/* Placeholders for fields that only exist in the traditional 32-bit
+   instruction encoding; see the comment above for details.  */
+#define MICROMIPSOP_MASK_CODE20		0
+#define MICROMIPSOP_SH_CODE20		0
+#define MICROMIPSOP_MASK_PERFREG	0
+#define MICROMIPSOP_SH_PERFREG		0
+#define MICROMIPSOP_MASK_CODE19		0
+#define MICROMIPSOP_SH_CODE19		0
+#define MICROMIPSOP_MASK_ALN		0
+#define MICROMIPSOP_SH_ALN		0
+#define MICROMIPSOP_MASK_VECBYTE	0
+#define MICROMIPSOP_SH_VECBYTE		0
+#define MICROMIPSOP_MASK_VECALIGN	0
+#define MICROMIPSOP_SH_VECALIGN		0
+#define MICROMIPSOP_MASK_DSPACC_S	0
+#define MICROMIPSOP_SH_DSPACC_S	 	0
+#define MICROMIPSOP_MASK_DSPSFT_7	0
+#define MICROMIPSOP_SH_DSPSFT_7	 	0
+#define MICROMIPSOP_MASK_RDDSP		0
+#define MICROMIPSOP_SH_RDDSP		0
+#define MICROMIPSOP_MASK_MT_U		0
+#define MICROMIPSOP_SH_MT_U		0
+#define MICROMIPSOP_MASK_MT_H		0
+#define MICROMIPSOP_SH_MT_H		0
+#define MICROMIPSOP_MASK_MTACC_T	0
+#define MICROMIPSOP_SH_MTACC_T		0
+#define MICROMIPSOP_MASK_MTACC_D	0
+#define MICROMIPSOP_SH_MTACC_D		0
+#define MICROMIPSOP_MASK_BBITIND	0
+#define MICROMIPSOP_SH_BBITIND		0
+#define MICROMIPSOP_MASK_CINSPOS	0
+#define MICROMIPSOP_SH_CINSPOS		0
+#define MICROMIPSOP_MASK_CINSLM1	0
+#define MICROMIPSOP_SH_CINSLM1		0
+#define MICROMIPSOP_MASK_SEQI		0
+#define MICROMIPSOP_SH_SEQI		0
+#define MICROMIPSOP_SH_OFFSET_A		0
+#define MICROMIPSOP_MASK_OFFSET_A	0
+#define MICROMIPSOP_SH_OFFSET_B		0
+#define MICROMIPSOP_MASK_OFFSET_B	0
+#define MICROMIPSOP_SH_OFFSET_C		0
+#define MICROMIPSOP_MASK_OFFSET_C	0
+#define MICROMIPSOP_SH_RZ		0
+#define MICROMIPSOP_MASK_RZ		0
+#define MICROMIPSOP_SH_FZ		0
+#define MICROMIPSOP_MASK_FZ		0
+
+/* microMIPS Enhanced VA Scheme */
+#define MICROMIPSOP_SH_EVAOFFSET	0
+#define MICROMIPSOP_MASK_EVAOFFSET	0x1ff
+
+/* These are the characters which may appears in the args field of a microMIPS
+   instruction.  They appear in the order in which the fields appear
+   when the instruction is used.  Commas and parentheses in the args
+   string are ignored when assembling, and written into the output
+   when disassembling.
+
+   The followings are for 16-bit microMIPS instructions.
+
+   "ma" must be $28
+   "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
+        The same register used as both source and target.
+   "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
+   "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
+        The same register used as both source and target.
+   "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
+   "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
+   "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7
+   "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
+   "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
+   "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
+   "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
+   "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
+   "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
+   "mr" must be program counter
+   "ms" must be $29
+   "mt" must be the same as the previous register
+   "mx" must be the same as the destination register
+   "my" must be $31
+   "mz" must be $0
+
+   "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
+   "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
+   "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
+        32768, 65535) (MICROMIPSOP_*_IMMC)
+   "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
+   "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
+   "mF" 4-bit immediate (0 .. 15)  (MICROMIPSOP_*_IMMF)
+   "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
+   "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
+   "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
+   "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
+   "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
+   "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
+   "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
+   "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
+   "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
+   "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
+   "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
+   "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
+   "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
+   "mZ" must be zero
+
+   In most cases 32-bit microMIPS instructions use the same characters
+   as MIPS (with ADDIUPC being a notable exception, but there are some
+   others too).
+
+   "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
+   "1" 5-bit sync type (MICROMIPSOP_*_STYPE)
+   "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
+   ">" shift amount between 32 and 63, stored after subtracting 32
+       (MICROMIPSOP_*_SHAMT)
+   "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS)
+   "|" 4-bit trap code (MICROMIPSOP_*_TRAP)
+   "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
+   "a" 26-bit target address (MICROMIPSOP_*_TARGET)
+   "+i" likewise, but flips bit 0
+   "b" 5-bit base register (MICROMIPSOP_*_RS)
+   "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
+   "d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
+   "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
+   "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
+   "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
+   "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
+   "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
+   "o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
+   "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
+   "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
+   "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
+   "s" 5-bit source register specifier (MICROMIPSOP_*_RS)
+   "t" 5-bit target register (MICROMIPSOP_*_RT)
+   "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
+   "v" 5-bit same register used as both source and destination
+       (MICROMIPSOP_*_RS)
+   "w" 5-bit same register used as both target and destination
+       (MICROMIPSOP_*_RT)
+   "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
+   "z" must be zero register
+   "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
+   "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
+   "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
+
+   "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
+        LSB (MICROMIPSOP_*_EXTLSB).
+	Enforces: 0 <= pos < 32.
+   "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
+	Requires that "+A" or "+E" occur first to set position.
+	Enforces: 0 < (pos+size) <= 32.
+   "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
+	Requires that "+A" or "+E" occur first to set position.
+	Enforces: 0 < (pos+size) <= 32.
+	(Also used by DEXT w/ different limits, but limits for
+	that are checked by the M_DEXT macro.)
+   "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
+	Enforces: 32 <= pos < 64.
+   "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
+	Requires that "+A" or "+E" occur first to set position.
+	Enforces: 32 < (pos+size) <= 64.
+   "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
+	Requires that "+A" or "+E" occur first to set position.
+	Enforces: 32 < (pos+size) <= 64.
+   "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
+	Requires that "+A" or "+E" occur first to set position.
+	Enforces: 32 < (pos+size) <= 64.
+
+   PC-relative addition (ADDIUPC) instruction:
+   "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
+   "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
+
+   Floating point instructions:
+   "D" 5-bit destination register (MICROMIPSOP_*_FD)
+   "M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
+   "N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
+   "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
+   "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
+   "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
+   "V" 5-bit same register used as floating source and destination or target
+       (MICROMIPSOP_*_FS)
+
+   Coprocessor instructions:
+   "E" 5-bit target register (MICROMIPSOP_*_RT)
+   "G" 5-bit source register (MICROMIPSOP_*_RS)
+   "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
+
+   Macro instructions:
+   "A" general 32 bit expression
+   "I" 32-bit immediate (value placed in imm_expr).
+   "F" 64-bit floating point constant in .rdata
+   "L" 64-bit floating point constant in .lit8
+   "f" 32-bit floating point constant
+   "l" 32-bit floating point constant in .lit4
+
+   DSP ASE usage:
+   "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP)
+   "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3)
+   "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4)
+   "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8)
+   "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS)
+   "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC)
+   "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP)
+   "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT)
+   "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
+   "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
+
+   microMIPS Enhanced VA Scheme:
+   "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
+
+   MSA Extension:
+   "+d" 5-bit MSA register (FD)
+   "+e" 5-bit MSA register (FS)
+   "+h" 5-bit MSA register (FT)
+   "+k" 5-bit GPR at bit 6
+   "+l" 5-bit MSA control register at bit 6
+   "+n" 5-bit MSA control register at bit 11
+   "+o" 5-bit vector element index at bit 16
+   "+u" 4-bit vector element index at bit 16
+   "+v" 3-bit vector element index at bit 16
+   "+w" 2-bit vector element index at bit 16
+   "+x" 5-bit shift amount at bit 16
+   "+T" (-512 .. 511) << 0 at bit 16
+   "+U" (-512 .. 511) << 1 at bit 16
+   "+V" (-512 .. 511) << 2 at bit 16
+   "+W" (-512 .. 511) << 3 at bit 16
+   "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
+   "+!" 3 bit unsigned bit position at bit 16
+   "+@" 4 bit unsigned bit position at bit 16
+   "+#" 6 bit unsigned bit position at bit 16
+   "+$" 5 bit unsigned immediate at bit 16
+   "+%" 5 bit signed immediate at bit 16
+   "+^" 10 bit signed immediate at bit 11
+   "+&" 0 vector element index
+   "+*" 5-bit register vector element index at bit 16
+   "+|" 8-bit mask at bit 16
+
+   Other:
+   "()" parens surrounding optional value
+   ","  separates operands
+   "+"  start of extension sequence
+   "m"  start of microMIPS extension sequence
+
+   Characters used so far, for quick reference when adding more:
+   "12345678 0"
+   "<>(),+.@\^|~"
+   "ABCDEFGHI KLMN   RST V    "
+   "abcd f hijklmnopqrstuvw yz"
+
+   Extension character sequences used so far ("+" followed by the
+   following), for quick reference when adding more:
+   ""
+   "~!@#$%^&*|"
+   "ABCEFGHTUVW"
+   "dehijklnouvwx"
+
+   Extension character sequences used so far ("m" followed by the
+   following), for quick reference when adding more:
+   ""
+   ""
+   " BCDEFGHIJ LMNOPQ   U WXYZ"
+   " bcdefghij lmn pq st   xyz"
+*/
+
+extern const struct mips_operand *decode_micromips_operand (const char *);
+extern const struct mips_opcode micromips_opcodes[];
+extern const int bfd_micromips_num_opcodes;
+
+/* A NOP insn impemented as "or at,at,zero".
+   Used to implement -mfix-loongson2f.  */
+#define LOONGSON2F_NOP_INSN	0x00200825
+
+#endif /* _MIPS_H_ */
diff --git a/binutils-2.25/include/opcode/mmix.h b/binutils-2.25/include/opcode/mmix.h
new file mode 100644
index 00000000..f931545d
--- /dev/null
+++ b/binutils-2.25/include/opcode/mmix.h
@@ -0,0 +1,187 @@
+/* mmix.h -- Header file for MMIX opcode table
+   Copyright (C) 2001, 2003, 2010 Free Software Foundation, Inc.
+   Written by Hans-Peter Nilsson (hp@bitrange.com)
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* We could have just a char*[] table indexed by the register number, but
+   that would not allow for synonyms.  The table is terminated with an
+   entry with a NULL name.  */
+struct mmix_spec_reg
+{
+  const char *name;
+  unsigned int number;
+};
+
+/* General indication of the type of instruction.  */
+enum mmix_insn_type
+ {
+   mmix_type_pseudo,
+   mmix_type_normal,
+   mmix_type_branch,
+   mmix_type_condbranch,
+   mmix_type_memaccess_octa,
+   mmix_type_memaccess_tetra,
+   mmix_type_memaccess_wyde,
+   mmix_type_memaccess_byte,
+   mmix_type_memaccess_block,
+   mmix_type_jsr
+ };
+
+/* Type of operands an instruction takes.  Use when parsing assembly code
+   and disassembling.  */
+enum mmix_operands_type
+ {
+   mmix_operands_none = 0,
+
+   /* All operands are registers: "$X,$Y,$Z".  */
+   mmix_operands_regs,
+
+   /* "$X,YZ", like SETH.  */
+   mmix_operands_reg_yz,
+
+   /* The regular "$X,$Y,$Z|Z".
+      The Z is optional; if only "$X,$Y" is given, then "$X,$Y,0" is
+      assumed.  */
+   mmix_operands_regs_z_opt,
+
+   /* The regular "$X,$Y,$Z|Z".  */
+   mmix_operands_regs_z,
+
+   /* "Address"; only JMP.  Zero operands allowed unless GNU syntax.  */
+   mmix_operands_jmp,
+
+   /* "$X|X,$Y,$Z|Z": PUSHGO; like "3", but X can be expressed as an
+      integer.  */
+   mmix_operands_pushgo,
+
+   /* Two registers or a register and a byte, like FLOT, possibly with
+      rounding: "$X,$Z|Z" or "$X,ROUND_MODE,$Z|Z".  */
+   mmix_operands_roundregs_z,
+
+   /* "X,YZ", POP.  Unless GNU syntax, zero or one operand is allowed.  */
+   mmix_operands_pop,
+
+   /* Two registers, possibly with rounding: "$X,$Z" or
+      "$X,ROUND_MODE,$Z".  */
+   mmix_operands_roundregs,
+
+   /* "XYZ", like SYNC.  */
+   mmix_operands_sync,
+
+   /* "X,$Y,$Z|Z", like SYNCD.  */
+   mmix_operands_x_regs_z,
+
+   /* "$X,Y,$Z|Z", like NEG and NEGU.  The Y field is optional, default 0.  */
+   mmix_operands_neg,
+
+   /* "$X,Address, like GETA or branches.  */
+   mmix_operands_regaddr,
+
+   /* "$X|X,Address, like PUSHJ.  */
+   mmix_operands_pushj,
+
+   /* "$X,spec_reg"; GET.  */
+   mmix_operands_get,
+
+   /* "spec_reg,$Z|Z"; PUT.  */
+   mmix_operands_put,
+
+   /* Two registers, "$X,$Y".  */
+   mmix_operands_set,
+
+   /* "$X,0"; SAVE.  */
+   mmix_operands_save,
+
+   /* "0,$Z"; UNSAVE. */
+   mmix_operands_unsave,
+
+   /* "X,Y,Z"; like SWYM or TRAP.  Zero (or 1 if GNU syntax) to three
+      operands, interpreted as 0; XYZ; X, YZ and X, Y, Z.  */
+   mmix_operands_xyz_opt,
+
+   /* Just "Z", like RESUME.  Unless GNU syntax, the operand can be omitted
+      and will then be assumed zero.  */
+   mmix_operands_resume,
+
+   /* These are specials to handle that pseudo-directives are specified
+      like ordinary insns when being mmixal-compatible.  They signify the
+      specific pseudo-directive rather than the operands type.  */
+
+   /* LOC.  */
+   mmix_operands_loc,
+
+   /* PREFIX.  */
+   mmix_operands_prefix,
+
+   /* BYTE.  */
+   mmix_operands_byte,
+
+   /* WYDE.  */
+   mmix_operands_wyde,
+
+   /* TETRA.  */
+   mmix_operands_tetra,
+
+   /* OCTA.  */
+   mmix_operands_octa,
+
+   /* LOCAL.  */
+   mmix_operands_local,
+
+   /* BSPEC.  */
+   mmix_operands_bspec,
+
+   /* ESPEC.  */
+   mmix_operands_espec,
+ };
+
+struct mmix_opcode
+ {
+   const char *name;
+   unsigned long match;
+   unsigned long lose;
+   enum mmix_operands_type operands;
+
+   /* This is used by the disassembly function.  */
+   enum mmix_insn_type type;
+ };
+
+/* Declare the actual tables.  */
+extern const struct mmix_opcode mmix_opcodes[];
+
+/* This one is terminated with an entry with a NULL name.  */
+extern const struct mmix_spec_reg mmix_spec_regs[];
+
+/* Some insn values we use when padding and synthesizing address loads.  */
+#define IMM_OFFSET_BIT 1
+#define COND_INV_BIT 0x8
+#define PRED_INV_BIT 0x10
+
+#define PUSHGO_INSN_BYTE 0xbe
+#define GO_INSN_BYTE 0x9e
+#define SETL_INSN_BYTE 0xe3
+#define INCML_INSN_BYTE 0xe6
+#define INCMH_INSN_BYTE 0xe5
+#define INCH_INSN_BYTE 0xe4
+#define SWYM_INSN_BYTE 0xfd
+#define JMP_INSN_BYTE 0xf0
+
+/* We can have 256 - 32 (local registers) - 1 ($255 is not allocatable)
+   global registers.  */
+#define MAX_GREGS 223
diff --git a/binutils-2.25/include/opcode/mn10200.h b/binutils-2.25/include/opcode/mn10200.h
new file mode 100644
index 00000000..b597d7b4
--- /dev/null
+++ b/binutils-2.25/include/opcode/mn10200.h
@@ -0,0 +1,111 @@
+/* mn10200.h -- Header file for Matsushita 10200 opcode table
+   Copyright 1996, 1997, 2010 Free Software Foundation, Inc.
+   Written by Jeff Law, Cygnus Support
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef MN10200_H
+#define MN10200_H
+
+/* The opcode table is an array of struct mn10200_opcode.  */
+
+struct mn10200_opcode
+{
+  /* The opcode name.  */
+  const char *name;
+
+  /* The opcode itself.  Those bits which will be filled in with
+     operands are zeroes.  */
+  unsigned long opcode;
+
+  /* The opcode mask.  This is used by the disassembler.  This is a
+     mask containing ones indicating those bits which must match the
+     opcode field, and zeroes indicating those bits which need not
+     match (and are presumably filled in by operands).  */
+  unsigned long mask;
+
+  /* The format of this opcode.  */
+  unsigned char format;
+
+  /* An array of operand codes.  Each code is an index into the
+     operand table.  They appear in the order which the operands must
+     appear in assembly code, and are terminated by a zero.  */
+  unsigned char operands[8];
+};
+
+/* The table itself is sorted by major opcode number, and is otherwise
+   in the order in which the disassembler should consider
+   instructions.  */
+extern const struct mn10200_opcode mn10200_opcodes[];
+extern const int mn10200_num_opcodes;
+
+
+/* The operands table is an array of struct mn10200_operand.  */
+
+struct mn10200_operand
+{
+  /* The number of bits in the operand.  */
+  int bits;
+
+  /* How far the operand is left shifted in the instruction.  */
+  int shift;
+
+  /* One bit syntax flags.  */
+  int flags;
+};
+
+/* Elements in the table are retrieved by indexing with values from
+   the operands field of the mn10200_opcodes table.  */
+
+extern const struct mn10200_operand mn10200_operands[];
+
+/* Values defined for the flags field of a struct mn10200_operand.  */
+#define MN10200_OPERAND_DREG 0x1
+
+#define MN10200_OPERAND_AREG 0x2
+
+#define MN10200_OPERAND_PSW 0x4
+
+#define MN10200_OPERAND_MDR 0x8
+
+#define MN10200_OPERAND_SIGNED 0x10
+
+#define MN10200_OPERAND_PROMOTE 0x20
+
+#define MN10200_OPERAND_PAREN 0x40
+
+#define MN10200_OPERAND_REPEATED 0x80
+
+#define MN10200_OPERAND_EXTENDED 0x100
+
+#define MN10200_OPERAND_NOCHECK 0x200
+
+#define MN10200_OPERAND_PCREL 0x400
+
+#define MN10200_OPERAND_MEMADDR 0x800
+
+#define MN10200_OPERAND_RELAX 0x1000
+
+#define FMT_1 1
+#define FMT_2 2
+#define FMT_3 3
+#define FMT_4 4
+#define FMT_5 5
+#define FMT_6 6
+#define FMT_7 7
+#endif /* MN10200_H */
diff --git a/binutils-2.25/include/opcode/mn10300.h b/binutils-2.25/include/opcode/mn10300.h
new file mode 100644
index 00000000..16a139bc
--- /dev/null
+++ b/binutils-2.25/include/opcode/mn10300.h
@@ -0,0 +1,170 @@
+/* mn10300.h -- Header file for Matsushita 10300 opcode table
+   Copyright 1996, 1997, 1998, 1999, 2003, 2010 Free Software Foundation, Inc.
+   Written by Jeff Law, Cygnus Support
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef MN10300_H
+#define MN10300_H
+
+/* The opcode table is an array of struct mn10300_opcode.  */
+
+#define MN10300_MAX_OPERANDS 8
+struct mn10300_opcode
+{
+  /* The opcode name.  */
+  const char *name;
+
+  /* The opcode itself.  Those bits which will be filled in with
+     operands are zeroes.  */
+  unsigned long opcode;
+
+  /* The opcode mask.  This is used by the disassembler.  This is a
+     mask containing ones indicating those bits which must match the
+     opcode field, and zeroes indicating those bits which need not
+     match (and are presumably filled in by operands).  */
+  unsigned long mask;
+
+  /* A bitmask.  For each operand, nonzero if it must not have the same
+     register specification as all other operands with a nonzero bit in
+     this flag.  ie 0x81 would indicate that operands 7 and 0 must not
+     match.  Note that we count operands from left to right as they appear
+     in the operands specification below.  */
+  unsigned int no_match_operands;
+
+  /* The format of this opcode.  */
+  unsigned char format;
+
+  /* Bitmask indicating what cpu variants this opcode is available on.
+     We assume mn10300 base opcodes are available everywhere, so we only
+     have to note opcodes which are available on other variants.  */
+  unsigned int machine;
+
+  /* An array of operand codes.  Each code is an index into the
+     operand table.  They appear in the order which the operands must
+     appear in assembly code, and are terminated by a zero.  */
+  unsigned char operands[MN10300_MAX_OPERANDS];
+};
+
+/* The table itself is sorted by major opcode number, and is otherwise
+   in the order in which the disassembler should consider
+   instructions.  */
+extern const struct mn10300_opcode mn10300_opcodes[];
+extern const int mn10300_num_opcodes;
+
+
+/* The operands table is an array of struct mn10300_operand.  */
+
+struct mn10300_operand
+{
+  /* The number of bits in the operand.  */
+  int bits;
+
+  /* How far the operand is left shifted in the instruction.  */
+  int shift;
+
+  /* One bit syntax flags.  */
+  int flags;
+};
+
+/* Elements in the table are retrieved by indexing with values from
+   the operands field of the mn10300_opcodes table.  */
+
+extern const struct mn10300_operand mn10300_operands[];
+
+/* Values defined for the flags field of a struct mn10300_operand.  */
+#define MN10300_OPERAND_DREG 0x1
+
+#define MN10300_OPERAND_AREG 0x2
+
+#define MN10300_OPERAND_SP 0x4
+
+#define MN10300_OPERAND_PSW 0x8
+
+#define MN10300_OPERAND_MDR 0x10
+
+#define MN10300_OPERAND_SIGNED 0x20
+
+#define MN10300_OPERAND_PROMOTE 0x40
+
+#define MN10300_OPERAND_PAREN 0x80
+
+#define MN10300_OPERAND_REPEATED 0x100
+
+#define MN10300_OPERAND_EXTENDED 0x200
+
+#define MN10300_OPERAND_SPLIT 0x400
+
+#define MN10300_OPERAND_REG_LIST 0x800
+
+#define MN10300_OPERAND_PCREL 0x1000
+
+#define MN10300_OPERAND_MEMADDR 0x2000
+
+#define MN10300_OPERAND_RELAX 0x4000
+
+#define MN10300_OPERAND_USP 0x8000
+
+#define MN10300_OPERAND_SSP 0x10000
+
+#define MN10300_OPERAND_MSP 0x20000
+
+#define MN10300_OPERAND_PC 0x40000
+
+#define MN10300_OPERAND_EPSW 0x80000
+
+#define MN10300_OPERAND_RREG 0x100000
+
+#define MN10300_OPERAND_XRREG 0x200000
+
+#define MN10300_OPERAND_PLUS 0x400000
+
+#define MN10300_OPERAND_24BIT 0x800000
+
+#define MN10300_OPERAND_FSREG 0x1000000
+
+#define MN10300_OPERAND_FDREG 0x2000000
+
+#define MN10300_OPERAND_FPCR 0x4000000
+
+/* Opcode Formats.  */
+#define FMT_S0 1
+#define FMT_S1 2
+#define FMT_S2 3
+#define FMT_S4 4
+#define FMT_S6 5
+#define FMT_D0 6
+#define FMT_D1 7
+#define FMT_D2 8
+#define FMT_D4 9
+#define FMT_D5 10
+#define FMT_D6 11
+#define FMT_D7 12
+#define FMT_D8 13
+#define FMT_D9 14
+#define FMT_D10 15
+#define FMT_D3 16
+
+/* Variants of the mn10300 which have additional opcodes.  */
+#define MN103 300
+#define AM30  300
+
+#define AM33 330
+#define AM33_2 332
+
+#endif /* MN10300_H */
diff --git a/binutils-2.25/include/opcode/moxie.h b/binutils-2.25/include/opcode/moxie.h
new file mode 100644
index 00000000..dae40c8e
--- /dev/null
+++ b/binutils-2.25/include/opcode/moxie.h
@@ -0,0 +1,74 @@
+/* Definitions for decoding the moxie opcode table.
+   Copyright 2009 Free Software Foundation, Inc.
+   Contributed by Anthony Green (green@moxielogic.com).
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+/* Form 1 instructions come in different flavors:
+
+    Some have no arguments                          (MOXIE_F1_NARG)
+    Some only use the A operand                     (MOXIE_F1_A)
+    Some use A and B registers                      (MOXIE_F1_AB)
+    Some use A and consume a 4 byte immediate value (MOXIE_F1_A4)
+    Some use just a 4 byte immediate value          (MOXIE_F1_4)
+    Some use just a 4 byte memory address           (MOXIE_F1_M)
+    Some use B and an indirect A                    (MOXIE_F1_AiB)
+    Some use A and an indirect B                    (MOXIE_F1_ABi)
+    Some consume a 4 byte immediate value and use X (MOXIE_F1_4A)
+    Some use B and an indirect A plus 4 bytes       (MOXIE_F1_AiB4)
+    Some use A and an indirect B plus 4 bytes       (MOXIE_F1_ABi4)
+
+  Form 2 instructions also come in different flavors:
+
+    Some have no arguments                          (MOXIE_F2_NARG)
+    Some use the A register and an 8-bit value      (MOXIE_F2_A8V)
+
+  Form 3 instructions also come in different flavors:
+
+    Some have no arguments                          (MOXIE_F3_NARG)
+    Some have a 10-bit PC relative operand          (MOXIE_F3_PCREL).  */
+
+#define MOXIE_F1_NARG 0x100
+#define MOXIE_F1_A    0x101
+#define MOXIE_F1_AB   0x102
+/* #define MOXIE_F1_ABC  0x103 */
+#define MOXIE_F1_A4   0x104
+#define MOXIE_F1_4    0x105
+#define MOXIE_F1_AiB  0x106
+#define MOXIE_F1_ABi  0x107
+#define MOXIE_F1_4A   0x108
+#define MOXIE_F1_AiB4 0x109
+#define MOXIE_F1_ABi4 0x10a
+#define MOXIE_F1_M    0x10b
+
+#define MOXIE_F2_NARG 0x200
+#define MOXIE_F2_A8V  0x201
+
+#define MOXIE_F3_NARG  0x300
+#define MOXIE_F3_PCREL 0x301
+
+#define MOXIE_BAD     0x400
+
+typedef struct moxie_opc_info_t
+{
+  short         opcode;
+  unsigned      itype;
+  const char *  name;
+} moxie_opc_info_t;
+
+extern const moxie_opc_info_t moxie_form1_opc_info[128];
+extern const moxie_opc_info_t moxie_form2_opc_info[4];
+extern const moxie_opc_info_t moxie_form3_opc_info[16];
diff --git a/binutils-2.25/include/opcode/msp430-decode.h b/binutils-2.25/include/opcode/msp430-decode.h
new file mode 100644
index 00000000..0653aded
--- /dev/null
+++ b/binutils-2.25/include/opcode/msp430-decode.h
@@ -0,0 +1,130 @@
+/* Opcode decoder for the TI MSP430
+   Copyright 2012-2013 Free Software Foundation, Inc.
+   Written by DJ Delorie <dj@redhat.com>
+
+   This file is part of GDB, the GNU Debugger.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+typedef enum
+{
+  MSO_unknown,
+  /* Double-operand instructions - all repeat .REPEATS times. */
+  MSO_mov,	/* dest = src */
+  MSO_add,	/* dest += src */
+  MSO_addc,	/* dest += src + carry */
+  MSO_subc,	/* dest -= (src-1) + carry */
+  MSO_sub,	/* dest -= src */
+  MSO_cmp,	/* dest - src -> status */
+  MSO_dadd,	/* dest += src (as BCD) */
+  MSO_bit,	/* dest & src -> status */
+  MSO_bic,	/* dest &= ~src (bit clear) */
+  MSO_bis,	/* dest |= src (bit set, OR) */
+  MSO_xor,	/* dest ^= src */
+  MSO_and,	/* dest &= src */
+
+  /* Single-operand instructions.  */
+  MSO_rrc,	/* Rotate through carry, dest >>= .REPEATS.  */
+  MSO_swpb,	/* Swap lower bytes of operand.  */
+  MSO_rra,	/* Signed shift dest >>= .REPEATS.  */
+  MSO_sxt,	/* Sign extend lower byte.  */
+  MSO_push,	/* Push .REPEATS registers (or other op) starting at SRC going towards R0.  */
+  MSO_pop,	/* Pop .REPEATS registers starting at DEST going towards R15.  */
+  MSO_call,
+  MSO_reti,
+
+  /* Jumps.  */
+  MSO_jmp,	/* PC = SRC if .COND true.  */
+
+  /* Extended single-operand instructions.  */
+  MSO_rru,	/* Unsigned shift right, dest >>= .REPEATS.  */
+
+} MSP430_Opcode_ID;
+
+typedef enum
+{
+  MSP430_Operand_None,
+  MSP430_Operand_Immediate,
+  MSP430_Operand_Register,
+  MSP430_Operand_Indirect,
+  MSP430_Operand_Indirect_Postinc
+} MSP430_Operand_Type;
+
+typedef enum
+{
+  MSR_0 = 0,
+  MSR_PC = 0,
+  MSR_SP = 1,
+  MSR_SR = 2,
+  MSR_CG = 3,
+  MSR_None = 16,
+} MSP430_Register;
+
+typedef struct
+{
+  MSP430_Operand_Type  type;
+  int                  addend;
+  MSP430_Register      reg : 8;
+  MSP430_Register      reg2 : 8;
+  unsigned char	       bit_number : 4;
+  unsigned char	       condition : 3;
+} MSP430_Opcode_Operand;
+
+typedef enum
+{
+  MSP430_Byte = 0,
+  MSP430_Word,
+  MSP430_Addr
+} MSP430_Size;
+
+/* These numerically match the bit encoding.  */
+typedef enum
+{
+  MSC_nz = 0,
+  MSC_z,
+  MSC_nc,
+  MSC_c,
+  MSC_n,
+  MSC_ge,
+  MSC_l,
+  MSC_true,
+} MSP430_Condition;
+
+#define MSP430_FLAG_C	0x01
+#define MSP430_FLAG_Z	0x02
+#define MSP430_FLAG_N	0x04
+#define MSP430_FLAG_V	0x80
+
+typedef struct
+{
+  int lineno;
+  MSP430_Opcode_ID	id;
+  unsigned		flags_1:8;	/* These flags are set to '1' by the insn.  */
+  unsigned		flags_0:8;	/* These flags are set to '0' by the insn.  */
+  unsigned		flags_set:8;	/* These flags are set appropriately by the insn.  */
+  unsigned		zc:1;		/* If set, pretend the carry bit is zero.  */
+  unsigned		repeat_reg:1;	/* If set, count is in REG[repeats].  */
+  unsigned		ofs_430x:1;	/* If set, the offset in any operand is 430x (else use 430 compatibility mode).  */
+  unsigned		repeats:5;	/* Contains COUNT-1, or register number.  */
+  int			n_bytes;	/* Opcode size in BYTES.  */
+  char *		syntax;
+  MSP430_Size		size;		/* Operand size in BITS.  */
+  MSP430_Condition	cond;
+  /* By convention, these are [0]destination, [1]source.  */
+  MSP430_Opcode_Operand	op[2];
+} MSP430_Opcode_Decoded;
+
+int msp430_decode_opcode (unsigned long, MSP430_Opcode_Decoded *, int (*)(void *), void *);
diff --git a/binutils-2.25/include/opcode/msp430.h b/binutils-2.25/include/opcode/msp430.h
new file mode 100644
index 00000000..caddc42d
--- /dev/null
+++ b/binutils-2.25/include/opcode/msp430.h
@@ -0,0 +1,194 @@
+/* Opcode table for the TI MSP430 microcontrollers
+
+   Copyright 2002-2013 Free Software Foundation, Inc.
+   Contributed by Dmitry Diky <diwil@mail.ru>
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef __MSP430_H_
+#define __MSP430_H_
+
+struct msp430_operand_s
+{
+  int ol;	/* Operand length words.  */
+  int am;	/* Addr mode.  */
+  int reg;	/* Register.  */
+  int mode;	/* Pperand mode.  */
+#define OP_REG		0
+#define OP_EXP		1
+#ifndef DASM_SECTION
+  expressionS	exp;
+#endif
+};
+
+#define BYTE_OPERATION  (1 << 6)  /* Byte operation flag for all instructions.  */
+
+struct  msp430_opcode_s
+{
+  char *name;
+  int fmt;
+  int insn_opnumb;
+  int bin_opcode;
+  int bin_mask;
+};
+
+#define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask }
+
+static struct msp430_opcode_s msp430_opcodes[] = 
+{
+  MSP_INSN (and,   1, 2, 0xf000, 0xf000),
+  MSP_INSN (inv,   0, 1, 0xe330, 0xfff0),
+  MSP_INSN (xor,   1, 2, 0xe000, 0xf000),
+  MSP_INSN (setz,  0, 0, 0xd322, 0xffff),
+  MSP_INSN (setc,  0, 0, 0xd312, 0xffff),
+  MSP_INSN (eint,  0, 0, 0xd232, 0xffff),
+  MSP_INSN (setn,  0, 0, 0xd222, 0xffff),
+  MSP_INSN (bis,   1, 2, 0xd000, 0xf000),
+  MSP_INSN (clrz,  0, 0, 0xc322, 0xffff),
+  MSP_INSN (clrc,  0, 0, 0xc312, 0xffff),
+  MSP_INSN (dint,  0, 0, 0xc232, 0xffff),
+  MSP_INSN (clrn,  0, 0, 0xc222, 0xffff),
+  MSP_INSN (bic,   1, 2, 0xc000, 0xf000),
+  MSP_INSN (bit,   1, 2, 0xb000, 0xf000),
+  MSP_INSN (dadc,  0, 1, 0xa300, 0xff30),
+  MSP_INSN (dadd,  1, 2, 0xa000, 0xf000),
+  MSP_INSN (tst,   0, 1, 0x9300, 0xff30),
+  MSP_INSN (cmp,   1, 2, 0x9000, 0xf000),
+  MSP_INSN (decd,  0, 1, 0x8320, 0xff30),
+  MSP_INSN (dec,   0, 1, 0x8310, 0xff30),
+  MSP_INSN (sub,   1, 2, 0x8000, 0xf000),
+  MSP_INSN (sbc,   0, 1, 0x7300, 0xff30),
+  MSP_INSN (subc,  1, 2, 0x7000, 0xf000),
+  MSP_INSN (adc,   0, 1, 0x6300, 0xff30),
+  MSP_INSN (rlc,   0, 2, 0x6000, 0xf000),
+  MSP_INSN (addc,  1, 2, 0x6000, 0xf000),
+  MSP_INSN (incd,  0, 1, 0x5320, 0xff30),
+  MSP_INSN (inc,   0, 1, 0x5310, 0xff30),
+  MSP_INSN (rla,   0, 2, 0x5000, 0xf000),
+  MSP_INSN (add,   1, 2, 0x5000, 0xf000),
+  MSP_INSN (nop,   0, 0, 0x4303, 0xffff),
+  MSP_INSN (clr,   0, 1, 0x4300, 0xff30),
+  MSP_INSN (ret,   0, 0, 0x4130, 0xff30),
+  MSP_INSN (pop,   0, 1, 0x4130, 0xff30),
+  MSP_INSN (br,    0, 3, 0x4000, 0xf000),
+  MSP_INSN (mov,   1, 2, 0x4000, 0xf000),
+  MSP_INSN (jmp,   3, 1, 0x3c00, 0xfc00),
+  MSP_INSN (jl,    3, 1, 0x3800, 0xfc00),
+  MSP_INSN (jge,   3, 1, 0x3400, 0xfc00),
+  MSP_INSN (jn,    3, 1, 0x3000, 0xfc00),
+  MSP_INSN (jc,    3, 1, 0x2c00, 0xfc00),
+  MSP_INSN (jhs,   3, 1, 0x2c00, 0xfc00),
+  MSP_INSN (jnc,   3, 1, 0x2800, 0xfc00),
+  MSP_INSN (jlo,   3, 1, 0x2800, 0xfc00),
+  MSP_INSN (jz,    3, 1, 0x2400, 0xfc00),
+  MSP_INSN (jeq,   3, 1, 0x2400, 0xfc00),
+  MSP_INSN (jnz,   3, 1, 0x2000, 0xfc00),
+  MSP_INSN (jne,   3, 1, 0x2000, 0xfc00),
+  MSP_INSN (reti,  2, 0, 0x1300, 0xffc0),
+  MSP_INSN (call,  2, 1, 0x1280, 0xffc0),
+  MSP_INSN (push,  2, 1, 0x1200, 0xff80),
+  MSP_INSN (sxt,   2, 1, 0x1180, 0xffc0),
+  MSP_INSN (rra,   2, 1, 0x1100, 0xff80),
+  MSP_INSN (swpb,  2, 1, 0x1080, 0xffc0),
+  MSP_INSN (rrc,   2, 1, 0x1000, 0xff80),
+  /* Simple polymorphs.  */
+  MSP_INSN (beq,   4, 0, 0, 0xffff),
+  MSP_INSN (bne,   4, 1, 0, 0xffff),
+  MSP_INSN (blt,   4, 2, 0, 0xffff),
+  MSP_INSN (bltu,  4, 3, 0, 0xffff),
+  MSP_INSN (bge,   4, 4, 0, 0xffff),
+  MSP_INSN (bgeu,  4, 5, 0, 0xffff),
+  MSP_INSN (bltn,  4, 6, 0, 0xffff),
+  MSP_INSN (jump,  4, 7, 0, 0xffff),
+  /* Long polymorphs.  */
+  MSP_INSN (bgt,   5, 0, 0, 0xffff),
+  MSP_INSN (bgtu,  5, 1, 0, 0xffff),
+  MSP_INSN (bleu,  5, 2, 0, 0xffff),
+  MSP_INSN (ble,   5, 3, 0, 0xffff),
+
+  /* MSP430X instructions - these ones use an extension word.
+     A negative format indicates an MSP430X instruction.  */
+  MSP_INSN (addcx, -2, 2, 0x6000, 0xf000),
+  MSP_INSN (addx,  -2, 2, 0x5000, 0xf000),
+  MSP_INSN (andx,  -2, 2, 0xf000, 0xf000),
+  MSP_INSN (bicx,  -2, 2, 0xc000, 0xf000),
+  MSP_INSN (bisx,  -2, 2, 0xd000, 0xf000),
+  MSP_INSN (bitx,  -2, 2, 0xb000, 0xf000),
+  MSP_INSN (cmpx,  -2, 2, 0x9000, 0xf000),
+  MSP_INSN (daddx, -2, 2, 0xa000, 0xf000),
+  MSP_INSN (movx,  -2, 2, 0x4000, 0xf000),
+  MSP_INSN (subcx, -2, 2, 0x7000, 0xf000),
+  MSP_INSN (subx,  -2, 2, 0x8000, 0xf000),
+  MSP_INSN (xorx,  -2, 2, 0xe000, 0xf000),
+
+  /* MSP430X Synthetic instructions.  */
+  MSP_INSN (adcx,  -1, 1, 0x6300, 0xff30),
+  MSP_INSN (clra,  -1, 1, 0x4300, 0xff30),
+  MSP_INSN (clrx,  -1, 1, 0x4300, 0xff30),
+  MSP_INSN (dadcx, -1, 1, 0xa300, 0xff30),
+  MSP_INSN (decx,  -1, 1, 0x8310, 0xff30),  
+  MSP_INSN (decda, -1, 1, 0x8320, 0xff30),
+  MSP_INSN (decdx, -1, 1, 0x8320, 0xff30),
+  MSP_INSN (incx,  -1, 1, 0x5310, 0xff30),  
+  MSP_INSN (incda, -1, 1, 0x5320, 0xff30),
+  MSP_INSN (incdx, -1, 1, 0x5320, 0xff30),
+  MSP_INSN (invx,  -1, 1, 0xe330, 0xfff0),
+  MSP_INSN (popx,  -1, 1, 0x4130, 0xff30),
+  MSP_INSN (rlax,  -1, 2, 0x5000, 0xf000),  
+  MSP_INSN (rlcx,  -1, 2, 0x6000, 0xf000),
+  MSP_INSN (sbcx,  -1, 1, 0x7300, 0xff30),
+  MSP_INSN (tsta,  -1, 1, 0x9300, 0xff30),
+  MSP_INSN (tstx,  -1, 1, 0x9300, 0xff30),
+
+  MSP_INSN (pushx, -3, 1, 0x1200, 0xff80),
+  MSP_INSN (rrax,  -3, 1, 0x1100, 0xff80),
+  MSP_INSN (rrcx,  -3, 1, 0x1000, 0xff80),
+  MSP_INSN (swpbx, -3, 1, 0x1080, 0xffc0),
+  MSP_INSN (sxtx,  -3, 1, 0x1180, 0xffc0),
+
+  /* MSP430X Address instructions - no extension word needed.
+     The insn_opnumb field is used to encode the nature of the
+     instruction for assembly and disassembly purposes.  */
+  MSP_INSN (calla, -1, 4, 0x1300, 0xff00),
+
+  MSP_INSN (popm,  -1, 5, 0x1600, 0xfe00),
+  MSP_INSN (pushm, -1, 5, 0x1400, 0xfe00),
+
+  MSP_INSN (rrcm,  -1, 6, 0x0040, 0xf3e0),
+  MSP_INSN (rram,  -1, 6, 0x0140, 0xf3e0),
+  MSP_INSN (rlam,  -1, 6, 0x0240, 0xf3e0),
+  MSP_INSN (rrum,  -1, 6, 0x0340, 0xf3e0),
+
+  MSP_INSN (rrux,  -1, 7, 0x0340, 0xffe0), /* Synthesized in terms of RRUM.  */
+
+  MSP_INSN (adda,  -1, 8, 0x00a0, 0xf0b0),
+  MSP_INSN (cmpa,  -1, 8, 0x0090, 0xf0b0),
+  MSP_INSN (suba,  -1, 8, 0x00b0, 0xf0b0),
+
+  MSP_INSN (reta,  -1, 9, 0x0110, 0xffff),
+  MSP_INSN (bra,   -1, 9, 0x0000, 0xf0cf),
+  MSP_INSN (mova,  -1, 9, 0x0000, 0xf080),
+  MSP_INSN (mova,  -1, 9, 0x0080, 0xf0b0),
+  MSP_INSN (mova,  -1, 9, 0x00c0, 0xf0f0),
+
+  /* Pseudo instruction to set the repeat field in the extension word.  */
+  MSP_INSN (rpt,   -1, 10, 0x0000, 0x0000),
+
+  /* End of instruction set.  */
+  { NULL, 0, 0, 0, 0 }
+};
+
+#endif
diff --git a/binutils-2.25/include/opcode/nios2.h b/binutils-2.25/include/opcode/nios2.h
new file mode 100644
index 00000000..aa670981
--- /dev/null
+++ b/binutils-2.25/include/opcode/nios2.h
@@ -0,0 +1,522 @@
+/* Nios II opcode list for GAS, the GNU assembler.
+   Copyright (C) 2012, 2013 Free Software Foundation, Inc.
+   Contributed by Nigel Gray (ngray@altera.com).
+   Contributed by Mentor Graphics, Inc.
+
+   This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
+
+   GAS/GDB is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS/GDB is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS or GDB; see the file COPYING3.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+#ifndef _NIOS2_H_
+#define _NIOS2_H_
+
+#include "bfd.h"
+
+/****************************************************************************
+ * This file contains structures, bit masks and shift counts used
+ * by the GNU toolchain to define the Nios II instruction set and
+ * access various opcode fields.
+ ****************************************************************************/
+
+/* Identify different overflow situations for error messages.  */
+enum overflow_type
+{
+  call_target_overflow = 0,
+  branch_target_overflow,
+  address_offset_overflow,
+  signed_immed16_overflow,
+  unsigned_immed16_overflow,
+  unsigned_immed5_overflow,
+  custom_opcode_overflow,
+  no_overflow
+};
+
+/* This structure holds information for a particular instruction. 
+
+   The args field is a string describing the operands.  The following
+   letters can appear in the args:
+     c - a 5-bit control register index
+     d - a 5-bit destination register index
+     s - a 5-bit left source register index
+     t - a 5-bit right source register index
+     i - a 16-bit signed immediate
+     u - a 16-bit unsigned immediate
+     o - a 16-bit signed program counter relative offset
+     j - a 5-bit unsigned immediate
+     b - a 5-bit break instruction constant
+     l - a 8-bit custom instruction constant
+     m - a 26-bit unsigned immediate
+   Literal ',', '(', and ')' characters may also appear in the args as
+   delimiters.
+
+   The pinfo field is INSN_MACRO for a macro.  Otherwise, it is a collection
+   of bits describing the instruction, notably any relevant hazard
+   information.
+
+   When assembling, the match field contains the opcode template, which
+   is modified by the arguments to produce the actual opcode
+   that is emitted.  If pinfo is INSN_MACRO, then this is 0.
+
+   If pinfo is INSN_MACRO, the mask field stores the macro identifier.
+   Otherwise this is a bit mask for the relevant portions of the opcode
+   when disassembling.  If the actual opcode anded with the match field
+   equals the opcode field, then we have found the correct instruction.  */
+
+struct nios2_opcode
+{
+  const char *name;		/* The name of the instruction.  */
+  const char *args;		/* A string describing the arguments for this 
+				   instruction.  */
+  const char *args_test;	/* Like args, but with an extra argument for 
+				   the expected opcode.  */
+  unsigned long num_args;	/* The number of arguments the instruction 
+				   takes.  */
+  unsigned long match;		/* The basic opcode for the instruction.  */
+  unsigned long mask;		/* Mask for the opcode field of the 
+				   instruction.  */
+  unsigned long pinfo;		/* Is this a real instruction or instruction 
+				   macro?  */
+  enum overflow_type overflow_msg;  /* Used to generate informative 
+				       message when fixup overflows.  */
+};
+
+/* This value is used in the nios2_opcode.pinfo field to indicate that the 
+   instruction is a macro or pseudo-op.  This requires special treatment by 
+   the assembler, and is used by the disassembler to determine whether to 
+   check for a nop.  */
+#define NIOS2_INSN_MACRO	0x80000000
+#define NIOS2_INSN_MACRO_MOV	0x80000001
+#define NIOS2_INSN_MACRO_MOVI	0x80000002
+#define NIOS2_INSN_MACRO_MOVIA	0x80000004
+
+#define NIOS2_INSN_RELAXABLE	0x40000000
+#define NIOS2_INSN_UBRANCH	0x00000010
+#define NIOS2_INSN_CBRANCH	0x00000020
+#define NIOS2_INSN_CALL		0x00000040
+
+#define NIOS2_INSN_ADDI		0x00000080
+#define NIOS2_INSN_ANDI		0x00000100
+#define NIOS2_INSN_ORI		0x00000200
+#define NIOS2_INSN_XORI		0x00000400
+
+
+/* Associates a register name ($6) with a 5-bit index (eg 6).  */
+struct nios2_reg
+{
+  const char *name;
+  const int index;
+};
+
+
+/* These are bit masks and shift counts for accessing the various
+   fields of a Nios II instruction.  */
+
+/* Macros for getting and setting an instruction field.  */
+#define GET_INSN_FIELD(X, i) \
+  (((i) & OP_MASK_##X) >> OP_SH_##X)
+#define SET_INSN_FIELD(X, i, j) \
+  ((i) = (((i) & ~OP_MASK_##X) | (((j) << OP_SH_##X) & OP_MASK_##X)))
+
+/* Instruction field definitions.  */
+#define IW_A_LSB 27
+#define IW_A_MSB 31
+#define IW_A_SZ 5
+#define IW_A_MASK 0x1f
+
+#define IW_B_LSB 22
+#define IW_B_MSB 26
+#define IW_B_SZ 5
+#define IW_B_MASK 0x1f
+
+#define IW_C_LSB 17
+#define IW_C_MSB 21
+#define IW_C_SZ 5
+#define IW_C_MASK 0x1f
+
+#define IW_IMM16_LSB 6
+#define IW_IMM16_MSB 21
+#define IW_IMM16_SZ 16
+#define IW_IMM16_MASK 0xffff
+
+#define IW_IMM26_LSB 6
+#define IW_IMM26_MSB 31
+#define IW_IMM26_SZ 26
+#define IW_IMM26_MASK 0x3ffffff
+
+#define IW_OP_LSB 0
+#define IW_OP_MSB 5
+#define IW_OP_SZ 6
+#define IW_OP_MASK 0x3f
+
+#define IW_OPX_LSB 11
+#define IW_OPX_MSB 16
+#define IW_OPX_SZ 6
+#define IW_OPX_MASK 0x3f
+
+#define IW_SHIFT_IMM5_LSB 6
+#define IW_SHIFT_IMM5_MSB 10
+#define IW_SHIFT_IMM5_SZ 5
+#define IW_SHIFT_IMM5_MASK 0x1f
+
+#define IW_CONTROL_REGNUM_LSB 6
+#define IW_CONTROL_REGNUM_MSB 9
+#define IW_CONTROL_REGNUM_SZ 4
+#define IW_CONTROL_REGNUM_MASK 0xf
+
+/* Operator mask and shift.  */
+#define OP_MASK_OP		(IW_OP_MASK << IW_OP_LSB)
+#define OP_SH_OP		IW_OP_LSB
+
+/* Masks and shifts for I-type instructions.  */
+#define OP_MASK_IOP		(IW_OP_MASK << IW_OP_LSB)
+#define OP_SH_IOP		IW_OP_LSB
+
+#define OP_MASK_IMM16		(IW_IMM16_MASK << IW_IMM16_LSB)
+#define OP_SH_IMM16		IW_IMM16_LSB
+
+#define OP_MASK_IRD		(IW_B_MASK << IW_B_LSB)
+#define OP_SH_IRD		IW_B_LSB /* The same as T for I-type.  */
+
+#define OP_MASK_IRT		(IW_B_MASK << IW_B_LSB)
+#define OP_SH_IRT		IW_B_LSB
+
+#define OP_MASK_IRS		(IW_A_MASK << IW_A_LSB)
+#define OP_SH_IRS		IW_A_LSB
+
+/* Masks and shifts for R-type instructions.  */
+#define OP_MASK_ROP		(IW_OP_MASK << IW_OP_LSB)
+#define OP_SH_ROP		IW_OP_LSB
+
+#define OP_MASK_ROPX		(IW_OPX_MASK << IW_OPX_LSB)
+#define OP_SH_ROPX		IW_OPX_LSB
+
+#define OP_MASK_RRD		(IW_C_MASK << IW_C_LSB)
+#define OP_SH_RRD		IW_C_LSB
+
+#define OP_MASK_RRT		(IW_B_MASK << IW_B_LSB)
+#define OP_SH_RRT		IW_B_LSB
+
+#define OP_MASK_RRS		(IW_A_MASK << IW_A_LSB)
+#define OP_SH_RRS		IW_A_LSB
+
+/* Masks and shifts for J-type instructions.  */
+#define OP_MASK_JOP		(IW_OP_MASK << IW_OP_LSB)
+#define OP_SH_JOP		IW_OP_LSB
+
+#define OP_MASK_IMM26		(IW_IMM26_MASK << IW_IMM26_LSB)
+#define OP_SH_IMM26		IW_IMM26_LSB
+
+/* Masks and shifts for CTL instructions.  */
+#define OP_MASK_RCTL	0x000007c0
+#define OP_SH_RCTL	6
+
+/* Break instruction imm5 field.  */
+#define OP_MASK_TRAP_IMM5 0x000007c0
+#define OP_SH_TRAP_IMM5	  6
+
+/* Instruction imm5 field.  */
+#define OP_MASK_IMM5		(IW_SHIFT_IMM5_MASK << IW_SHIFT_IMM5_LSB)
+#define OP_SH_IMM5		IW_SHIFT_IMM5_LSB
+
+/* Cache operation fields (type j,i(s)).  */
+#define OP_MASK_CACHE_OPX	(IW_B_MASK << IW_B_LSB)
+#define OP_SH_CACHE_OPX		IW_B_LSB
+#define OP_MASK_CACHE_RRS	(IW_A_MASK << IW_A_LSB)
+#define OP_SH_CACHE_RRS		IW_A_LSB
+
+/* Custom instruction masks.  */
+#define OP_MASK_CUSTOM_A	0x00010000
+#define OP_SH_CUSTOM_A		16
+
+#define OP_MASK_CUSTOM_B	0x00008000
+#define OP_SH_CUSTOM_B		15
+
+#define OP_MASK_CUSTOM_C	0x00004000
+#define OP_SH_CUSTOM_C		14
+
+#define OP_MASK_CUSTOM_N	0x00003fc0
+#define OP_SH_CUSTOM_N		6
+#define OP_MAX_CUSTOM_N		255
+
+/* OP instruction values. */
+#define OP_ADDI 4
+#define OP_ANDHI 44
+#define OP_ANDI 12
+#define OP_BEQ 38
+#define OP_BGE 14
+#define OP_BGEU 46
+#define OP_BLT 22
+#define OP_BLTU 54
+#define OP_BNE 30
+#define OP_BR 6
+#define OP_CALL 0
+#define OP_CMPEQI 32
+#define OP_CMPGEI 8
+#define OP_CMPGEUI 40
+#define OP_CMPLTI 16
+#define OP_CMPLTUI 48
+#define OP_CMPNEI 24
+#define OP_CUSTOM 50
+#define OP_FLUSHD 59
+#define OP_FLUSHDA 27
+#define OP_INITD 51
+#define OP_INITDA 19
+#define OP_JMPI 1
+#define OP_LDB 7
+#define OP_LDBIO 39
+#define OP_LDBU 3
+#define OP_LDBUIO 35
+#define OP_LDH 15
+#define OP_LDHIO 47
+#define OP_LDHU 11
+#define OP_LDHUIO 43
+#define OP_LDL 31
+#define OP_LDW 23
+#define OP_LDWIO 55
+#define OP_MULI 36
+#define OP_OPX 58
+#define OP_ORHI 52
+#define OP_ORI 20
+#define OP_RDPRS 56
+#define OP_STB 5
+#define OP_STBIO 37
+#define OP_STC 29
+#define OP_STH 13
+#define OP_STHIO 45
+#define OP_STW 21
+#define OP_STWIO 53
+#define OP_XORHI 60
+#define OP_XORI 28
+
+/* OPX instruction values.  */
+#define OPX_ADD 49
+#define OPX_AND 14
+#define OPX_BREAK 52
+#define OPX_BRET 9
+#define OPX_CALLR 29
+#define OPX_CMPEQ 32
+#define OPX_CMPGE 8
+#define OPX_CMPGEU 40
+#define OPX_CMPLT 16
+#define OPX_CMPLTU 48
+#define OPX_CMPNE 24
+#define OPX_CRST 62
+#define OPX_DIV 37
+#define OPX_DIVU 36
+#define OPX_ERET 1
+#define OPX_FLUSHI 12
+#define OPX_FLUSHP 4
+#define OPX_HBREAK 53
+#define OPX_INITI 41
+#define OPX_INTR 61
+#define OPX_JMP 13
+#define OPX_MUL 39
+#define OPX_MULXSS 31
+#define OPX_MULXSU 23
+#define OPX_MULXUU 7
+#define OPX_NEXTPC 28
+#define OPX_NOR 6
+#define OPX_OR 22
+#define OPX_RDCTL 38
+#define OPX_RET 5
+#define OPX_ROL 3
+#define OPX_ROLI 2
+#define OPX_ROR 11
+#define OPX_SLL 19
+#define OPX_SLLI 18
+#define OPX_SRA 59
+#define OPX_SRAI 58
+#define OPX_SRL 27
+#define OPX_SRLI 26
+#define OPX_SUB 57
+#define OPX_SYNC 54
+#define OPX_TRAP 45
+#define OPX_WRCTL 46
+#define OPX_WRPRS 20
+#define OPX_XOR 30
+
+/* The following macros define the opcode matches for each
+   instruction code & OP_MASK_INST == OP_MATCH_INST.  */
+
+/* OP instruction matches.  */
+#define OP_MATCH_ADDI		OP_ADDI
+#define OP_MATCH_ANDHI		OP_ANDHI
+#define OP_MATCH_ANDI		OP_ANDI
+#define OP_MATCH_BEQ		OP_BEQ
+#define OP_MATCH_BGE		OP_BGE
+#define OP_MATCH_BGEU		OP_BGEU
+#define OP_MATCH_BLT		OP_BLT
+#define OP_MATCH_BLTU		OP_BLTU
+#define OP_MATCH_BNE		OP_BNE
+#define OP_MATCH_BR		OP_BR
+#define OP_MATCH_FLUSHD		OP_FLUSHD
+#define OP_MATCH_FLUSHDA	OP_FLUSHDA
+#define OP_MATCH_INITD		OP_INITD
+#define OP_MATCH_INITDA		OP_INITDA
+#define OP_MATCH_CALL		OP_CALL
+#define OP_MATCH_CMPEQI		OP_CMPEQI
+#define OP_MATCH_CMPGEI		OP_CMPGEI
+#define OP_MATCH_CMPGEUI	OP_CMPGEUI
+#define OP_MATCH_CMPLTI		OP_CMPLTI
+#define OP_MATCH_CMPLTUI	OP_CMPLTUI
+#define OP_MATCH_CMPNEI		OP_CMPNEI
+#define OP_MATCH_JMPI		OP_JMPI
+#define OP_MATCH_LDB		OP_LDB
+#define OP_MATCH_LDBIO		OP_LDBIO
+#define OP_MATCH_LDBU		OP_LDBU
+#define OP_MATCH_LDBUIO		OP_LDBUIO
+#define OP_MATCH_LDH		OP_LDH
+#define OP_MATCH_LDHIO		OP_LDHIO
+#define OP_MATCH_LDHU		OP_LDHU
+#define OP_MATCH_LDHUIO		OP_LDHUIO
+#define OP_MATCH_LDL		OP_LDL
+#define OP_MATCH_LDW		OP_LDW
+#define OP_MATCH_LDWIO		OP_LDWIO
+#define OP_MATCH_MULI		OP_MULI
+#define OP_MATCH_OPX		OP_OPX
+#define OP_MATCH_ORHI		OP_ORHI
+#define OP_MATCH_ORI		OP_ORI
+#define OP_MATCH_RDPRS		OP_RDPRS
+#define OP_MATCH_STB		OP_STB
+#define OP_MATCH_STBIO		OP_STBIO
+#define OP_MATCH_STC		OP_STC
+#define OP_MATCH_STH		OP_STH
+#define OP_MATCH_STHIO		OP_STHIO
+#define OP_MATCH_STW		OP_STW
+#define OP_MATCH_STWIO		OP_STWIO
+#define OP_MATCH_CUSTOM		OP_CUSTOM
+#define OP_MATCH_XORHI		OP_XORHI
+#define OP_MATCH_XORI		OP_XORI
+#define OP_MATCH_OPX		OP_OPX
+
+/* OPX instruction values.  */
+#define OPX_MATCH(code) ((code << IW_OPX_LSB) | OP_OPX)
+
+#define OP_MATCH_ADD		OPX_MATCH (OPX_ADD)
+#define OP_MATCH_AND		OPX_MATCH (OPX_AND)
+#define OP_MATCH_BREAK		((0x1e << 17) | OPX_MATCH (OPX_BREAK))
+#define OP_MATCH_BRET		(0xf0000000 | OPX_MATCH (OPX_BRET))
+#define OP_MATCH_CALLR		((0x1f << 17) | OPX_MATCH (OPX_CALLR))
+#define OP_MATCH_CMPEQ		OPX_MATCH (OPX_CMPEQ)
+#define OP_MATCH_CMPGE		OPX_MATCH (OPX_CMPGE)
+#define OP_MATCH_CMPGEU		OPX_MATCH (OPX_CMPGEU)
+#define OP_MATCH_CMPLT		OPX_MATCH (OPX_CMPLT)
+#define OP_MATCH_CMPLTU		OPX_MATCH (OPX_CMPLTU)
+#define OP_MATCH_CMPNE		OPX_MATCH (OPX_CMPNE)
+#define OP_MATCH_DIV		OPX_MATCH (OPX_DIV)
+#define OP_MATCH_DIVU		OPX_MATCH (OPX_DIVU)
+#define OP_MATCH_JMP		OPX_MATCH (OPX_JMP)
+#define OP_MATCH_MUL		OPX_MATCH (OPX_MUL)
+#define OP_MATCH_MULXSS		OPX_MATCH (OPX_MULXSS)
+#define OP_MATCH_MULXSU		OPX_MATCH (OPX_MULXSU)
+#define OP_MATCH_MULXUU		OPX_MATCH (OPX_MULXUU)
+#define OP_MATCH_NEXTPC		OPX_MATCH (OPX_NEXTPC)
+#define OP_MATCH_NOR		OPX_MATCH (OPX_NOR)
+#define OP_MATCH_OR		OPX_MATCH (OPX_OR)
+#define OP_MATCH_RDCTL		OPX_MATCH (OPX_RDCTL)
+#define OP_MATCH_RET		(0xf8000000 | OPX_MATCH (OPX_RET))
+#define OP_MATCH_ROL		OPX_MATCH (OPX_ROL)
+#define OP_MATCH_ROLI		OPX_MATCH (OPX_ROLI)
+#define OP_MATCH_ROR		OPX_MATCH (OPX_ROR)
+#define OP_MATCH_SLL		OPX_MATCH (OPX_SLL)
+#define OP_MATCH_SLLI		OPX_MATCH (OPX_SLLI)
+#define OP_MATCH_SRA		OPX_MATCH (OPX_SRA)
+#define OP_MATCH_SRAI		OPX_MATCH (OPX_SRAI)
+#define OP_MATCH_SRL		OPX_MATCH (OPX_SRL)
+#define OP_MATCH_SRLI		OPX_MATCH (OPX_SRLI)
+#define OP_MATCH_SUB		OPX_MATCH (OPX_SUB)
+#define OP_MATCH_SYNC		OPX_MATCH (OPX_SYNC)
+#define OP_MATCH_TRAP		((0x1d << 17) | OPX_MATCH (OPX_TRAP))
+#define OP_MATCH_ERET		(0xef800000 | OPX_MATCH (OPX_ERET))
+#define OP_MATCH_WRCTL		OPX_MATCH (OPX_WRCTL)
+#define OP_MATCH_WRPRS		OPX_MATCH (OPX_WRPRS)
+#define OP_MATCH_XOR		OPX_MATCH (OPX_XOR)
+#define OP_MATCH_FLUSHI		OPX_MATCH (OPX_FLUSHI)
+#define OP_MATCH_FLUSHP		OPX_MATCH (OPX_FLUSHP)
+#define OP_MATCH_INITI		OPX_MATCH (OPX_INITI)
+
+/* Some unusual op masks.  */
+#define OP_MASK_BREAK		((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \
+				  | OP_MASK_ROPX | OP_MASK_OP) \
+				 & 0xfffff03f)
+#define OP_MASK_CALLR		((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
+				  | OP_MASK_OP))
+#define OP_MASK_JMP		((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
+				  | OP_MASK_OP))
+#define OP_MASK_SYNC		((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
+				  | OP_MASK_OP))
+#define OP_MASK_TRAP		((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \
+				  | OP_MASK_ROPX | OP_MASK_OP) \
+				 & 0xfffff83f)
+#define OP_MASK_WRCTL		((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
+				  | OP_MASK_OP))	/*& 0xfffff83f */
+#define OP_MASK_NEXTPC		((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \
+				  | OP_MASK_OP))
+#define OP_MASK_FLUSHI		((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
+				  | OP_MASK_OP))
+#define OP_MASK_INITI		((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
+				  | OP_MASK_OP))
+
+#define OP_MASK_ROLI		((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
+#define OP_MASK_SLLI		((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
+#define OP_MASK_SRAI		((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
+#define OP_MASK_SRLI		((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
+#define OP_MASK_RDCTL		((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \
+				  | OP_MASK_OP))	/*& 0xfffff83f */
+
+#ifndef OP_MASK
+#define OP_MASK				0xffffffff
+#endif
+
+/* These convenience macros to extract instruction fields are used by GDB.  */
+#define GET_IW_A(Iw) \
+    (((Iw) >> IW_A_LSB) & IW_A_MASK)
+#define GET_IW_B(Iw) \
+    (((Iw) >> IW_B_LSB) & IW_B_MASK)
+#define GET_IW_C(Iw) \
+    (((Iw) >> IW_C_LSB) & IW_C_MASK)
+#define GET_IW_CONTROL_REGNUM(Iw) \
+    (((Iw) >> IW_CONTROL_REGNUM_LSB) & IW_CONTROL_REGNUM_MASK)
+#define GET_IW_IMM16(Iw) \
+    (((Iw) >> IW_IMM16_LSB) & IW_IMM16_MASK)
+#define GET_IW_IMM26(Iw) \
+    (((Iw) >> IW_IMM26_LSB) & IW_IMM26_MASK)
+#define GET_IW_OP(Iw) \
+    (((Iw) >> IW_OP_LSB) & IW_OP_MASK)
+#define GET_IW_OPX(Iw) \
+    (((Iw) >> IW_OPX_LSB) & IW_OPX_MASK)
+
+/* These are the data structures we use to hold the instruction information.  */
+extern const struct nios2_opcode nios2_builtin_opcodes[];
+extern const int bfd_nios2_num_builtin_opcodes;
+extern struct nios2_opcode *nios2_opcodes;
+extern int bfd_nios2_num_opcodes;
+
+/* These are the data structures used to hold the register information.  */
+extern const struct nios2_reg nios2_builtin_regs[];
+extern struct nios2_reg *nios2_regs;
+extern const int nios2_num_builtin_regs;
+extern int nios2_num_regs;
+
+/* Machine-independent macro for number of opcodes.  */
+#define NUMOPCODES bfd_nios2_num_opcodes
+#define NUMREGISTERS nios2_num_regs;
+
+/* This is made extern so that the assembler can use it to find out
+   what instruction caused an error.  */
+extern const struct nios2_opcode *nios2_find_opcode_hash (unsigned long);
+
+#endif /* _NIOS2_H */
diff --git a/binutils-2.25/include/opcode/np1.h b/binutils-2.25/include/opcode/np1.h
new file mode 100644
index 00000000..6dadafde
--- /dev/null
+++ b/binutils-2.25/include/opcode/np1.h
@@ -0,0 +1,421 @@
+/* Print GOULD NPL instructions for GDB, the GNU debugger.
+   Copyright 1986, 1987, 1989, 1991, 2010 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   GDB is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GDB is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GDB; see the file COPYING3.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+struct gld_opcode
+{
+  char *name;
+  unsigned long opcode;
+  unsigned long mask;
+  char *args;
+  int length;
+};
+
+/* We store four bytes of opcode for all opcodes because that
+   is the most any of them need.  The actual length of an instruction
+   is always at least 2 bytes, and at most four.  The length of the
+   instruction is based on the opcode.
+
+   The mask component is a mask saying which bits must match
+   particular opcode in order for an instruction to be an instance
+   of that opcode.
+
+   The args component is a string containing characters
+   that are used to format the arguments to the instruction.  */
+
+/* Kinds of operands:
+   r  Register in first field
+   R  Register in second field
+   b  Base register in first field
+   B  Base register in second field
+   v  Vector register in first field
+   V  Vector register in first field
+   A  Optional address register (base register)
+   X  Optional index register
+   I  Immediate data (16bits signed)
+   O  Offset field (16bits signed)
+   h  Offset field (15bits signed)
+   d  Offset field (14bits signed)
+   S  Shift count field
+
+   any other characters are printed as is...  */
+
+/* The assembler requires that this array be sorted as follows:
+   all instances of the same mnemonic must be consecutive.
+   All instances of the same mnemonic with the same number of operands
+   must be consecutive.   */
+struct gld_opcode gld_opcodes[] =
+{
+{ "lb",		0xb4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lnb",	0xb8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lbs",	0xec080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lh",		0xb4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "lnh",	0xb8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "lw",		0xb4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lnw",	0xb8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "ld",		0xb4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "lnd",	0xb8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "li",		0xf8000000,	0xfc7f0000,	"r,I",		4 },
+{ "lpa",	0x50080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "la",		0x50000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "labr",	0x58080000,	0xfc080000,	"b,xOA,X",	4 },
+{ "lbp",	0x90080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lhp",	0x90000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "lwp",	0x90000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "ldp",	0x90000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "suabr",	0x58000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "lf",		0xbc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lfbr",	0xbc080000,	0xfc080000,	"b,xOA,X",	4 },
+{ "lwbr",	0x5c000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "stb",	0xd4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sth",	0xd4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "stw",	0xd4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "std",	0xd4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "stf",	0xdc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stfbr",	0xdc080000,	0xfc080000,	"b,xOA,X",	4 },
+{ "stwbr",	0x54000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "zmb",	0xd8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "zmh",	0xd8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "zmw",	0xd8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "zmd",	0xd8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "stbp",	0x94080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sthp",	0x94000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "stwp",	0x94000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stdp",	0x94000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "lil",	0xf80b0000,	0xfc7f0000,	"r,D",		4 },
+{ "lwsl1",	0xec000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lwsl2",	0xfc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lwsl3",	0xfc080000,	0xfc080000,	"r,xOA,X",	4 },
+
+{ "lvb",	0xb0080000,	0xfc080000,	"v,xOA,X",	4 },
+{ "lvh",	0xb0000001,	0xfc080001,	"v,xOA,X",	4 },
+{ "lvw",	0xb0000000,	0xfc080000,	"v,xOA,X",	4 },
+{ "lvd",	0xb0000002,	0xfc080002,	"v,xOA,X",	4 },
+{ "liv",	0x3c040000,	0xfc0f0000,	"v,R",		2 },
+{ "livf",	0x3c080000,	0xfc0f0000,	"v,R",		2 },
+{ "stvb",	0xd0080000,	0xfc080000,	"v,xOA,X",	4 },
+{ "stvh",	0xd0000001,	0xfc080001,	"v,xOA,X",	4 },
+{ "stvw",	0xd0000000,	0xfc080000,	"v,xOA,X",	4 },
+{ "stvd",	0xd0000002,	0xfc080002,	"v,xOA,X",	4 },
+
+{ "trr",	0x2c000000,	0xfc0f0000,	"r,R",		2 },
+{ "trn",	0x2c040000,	0xfc0f0000,	"r,R",		2 },
+{ "trnd",	0x2c0c0000,	0xfc0f0000,	"r,R",		2 },
+{ "trabs",	0x2c010000,	0xfc0f0000,	"r,R",		2 },
+{ "trabsd",	0x2c090000,	0xfc0f0000,	"r,R",		2 },
+{ "trc",	0x2c030000,	0xfc0f0000,	"r,R",		2 },
+{ "xcr",	0x28040000,	0xfc0f0000,	"r,R",		2 },
+{ "cxcr",	0x2c060000,	0xfc0f0000,	"r,R",		2 },
+{ "cxcrd",	0x2c0e0000,	0xfc0f0000,	"r,R",		2 },
+{ "tbrr",	0x2c020000,	0xfc0f0000,	"r,B",		2 },
+{ "trbr",	0x28030000,	0xfc0f0000,	"b,R",		2 },
+{ "xcbr",	0x28020000,	0xfc0f0000,	"b,B",		2 },
+{ "tbrbr",	0x28010000,	0xfc0f0000,	"b,B",		2 },
+
+{ "trvv",	0x28050000,	0xfc0f0000,	"v,V",		2 },
+{ "trvvn",	0x2c050000,	0xfc0f0000,	"v,V",		2 },
+{ "trvvnd",	0x2c0d0000,	0xfc0f0000,	"v,V",		2 },
+{ "trvab",	0x2c070000,	0xfc0f0000,	"v,V",		2 },
+{ "trvabd",	0x2c0f0000,	0xfc0f0000,	"v,V",		2 },
+{ "cmpv",	0x14060000,	0xfc0f0000,	"v,V",		2 },
+{ "expv",	0x14070000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvvlt",	0x10030000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvvle",	0x10040000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvvgt",	0x14030000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvvge",	0x14040000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvveq",	0x10050000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvvne",	0x10050000,	0xfc0f0000,	"v,V",		2 },
+{ "mrvrlt",	0x100d0000,	0xfc0f0000,	"v,R",		2 },
+{ "mrvrle",	0x100e0000,	0xfc0f0000,	"v,R",		2 },
+{ "mrvrgt",	0x140d0000,	0xfc0f0000,	"v,R",		2 },
+{ "mrvrge",	0x140e0000,	0xfc0f0000,	"v,R",		2 },
+{ "mrvreq",	0x100f0000,	0xfc0f0000,	"v,R",		2 },
+{ "mrvrne",	0x140f0000,	0xfc0f0000,	"v,R",		2 },
+{ "trvr",	0x140b0000,	0xfc0f0000,	"r,V",		2 },
+{ "trrv",	0x140c0000,	0xfc0f0000,	"v,R",		2 },
+
+{ "bu",		0x40000000,	0xff880000,	"xOA,X",	4 },
+{ "bns",	0x70080000,	0xff880000,	"xOA,X",	4 },
+{ "bnco",	0x70880000,	0xff880000,	"xOA,X",	4 },
+{ "bge",	0x71080000,	0xff880000,	"xOA,X",	4 },
+{ "bne",	0x71880000,	0xff880000,	"xOA,X",	4 },
+{ "bunge",	0x72080000,	0xff880000,	"xOA,X",	4 },
+{ "bunle",	0x72880000,	0xff880000,	"xOA,X",	4 },
+{ "bgt",	0x73080000,	0xff880000,	"xOA,X",	4 },
+{ "bnany",	0x73880000,	0xff880000,	"xOA,X",	4 },
+{ "bs"	,	0x70000000,	0xff880000,	"xOA,X",	4 },
+{ "bco",	0x70800000,	0xff880000,	"xOA,X",	4 },
+{ "blt",	0x71000000,	0xff880000,	"xOA,X",	4 },
+{ "beq",	0x71800000,	0xff880000,	"xOA,X",	4 },
+{ "buge",	0x72000000,	0xff880000,	"xOA,X",	4 },
+{ "bult",	0x72800000,	0xff880000,	"xOA,X",	4 },
+{ "ble",	0x73000000,	0xff880000,	"xOA,X",	4 },
+{ "bany",	0x73800000,	0xff880000,	"xOA,X",	4 },
+{ "brlnk",	0x44000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bib",	0x48000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bih",	0x48080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "biw",	0x4c000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bid",	0x4c080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bivb",	0x60000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bivh",	0x60080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bivw",	0x64000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bivd",	0x64080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bvsb",	0x68000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bvsh",	0x68080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bvsw",	0x6c000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bvsd",	0x6c080000,	0xfc080000,	"r,xOA,X",	4 },
+
+{ "camb",	0x80080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "camh",	0x80000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "camw",	0x80000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "camd",	0x80000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "car",	0x10000000,	0xfc0f0000,	"r,R",		2 },
+{ "card",	0x14000000,	0xfc0f0000,	"r,R",		2 },
+{ "ci",		0xf8050000,	0xfc7f0000,	"r,I",		4 },
+{ "chkbnd",	0x5c080000,	0xfc080000,	"r,xOA,X",	4 },
+
+{ "cavv",	0x10010000,	0xfc0f0000,	"v,V",		2 },
+{ "cavr",	0x10020000,	0xfc0f0000,	"v,R",		2 },
+{ "cavvd",	0x10090000,	0xfc0f0000,	"v,V",		2 },
+{ "cavrd",	0x100b0000,	0xfc0f0000,	"v,R",		2 },
+
+{ "anmb",	0x84080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "anmh",	0x84000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "anmw",	0x84000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "anmd",	0x84000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "anr",	0x04000000,	0xfc0f0000,	"r,R",		2 },
+{ "ani",	0xf8080000,	0xfc7f0000,	"r,I",		4 },
+{ "ormb",	0xb8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "ormh",	0xb8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "ormw",	0xb8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "ormd",	0xb8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "orr",	0x08000000,	0xfc0f0000,	"r,R",		2 },
+{ "oi",		0xf8090000,	0xfc7f0000,	"r,I",		4 },
+{ "eomb",	0x8c080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "eomh",	0x8c000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "eomw",	0x8c000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "eomd",	0x8c000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "eor",	0x0c000000,	0xfc0f0000,	"r,R",		2 },
+{ "eoi",	0xf80a0000,	0xfc7f0000,	"r,I",		4 },
+
+{ "anvv",	0x04010000,	0xfc0f0000,	"v,V",		2 },
+{ "anvr",	0x04020000,	0xfc0f0000,	"v,R",		2 },
+{ "orvv",	0x08010000,	0xfc0f0000,	"v,V",		2 },
+{ "orvr",	0x08020000,	0xfc0f0000,	"v,R",		2 },
+{ "eovv",	0x0c010000,	0xfc0f0000,	"v,V",		2 },
+{ "eovr",	0x0c020000,	0xfc0f0000,	"v,R",		2 },
+
+{ "sacz",	0x100c0000,	0xfc0f0000,	"r,R",		2 },
+{ "sla",	0x1c400000,	0xfc600000,	"r,S",		2 },
+{ "sll",	0x1c600000,	0xfc600000,	"r,S",		2 },
+{ "slc",	0x24400000,	0xfc600000,	"r,S",		2 },
+{ "slad",	0x20400000,	0xfc600000,	"r,S",		2 },
+{ "slld",	0x20600000,	0xfc600000,	"r,S",		2 },
+{ "sra",	0x1c000000,	0xfc600000,	"r,S",		2 },
+{ "srl",	0x1c200000,	0xfc600000,	"r,S",		2 },
+{ "src",	0x24000000,	0xfc600000,	"r,S",		2 },
+{ "srad",	0x20000000,	0xfc600000,	"r,S",		2 },
+{ "srld",	0x20200000,	0xfc600000,	"r,S",		2 },
+{ "sda",	0x3c030000,	0xfc0f0000,	"r,R",		2 },
+{ "sdl",	0x3c020000,	0xfc0f0000,	"r,R",		2 },
+{ "sdc",	0x3c010000,	0xfc0f0000,	"r,R",		2 },
+{ "sdad",	0x3c0b0000,	0xfc0f0000,	"r,R",		2 },
+{ "sdld",	0x3c0a0000,	0xfc0f0000,	"r,R",		2 },
+
+{ "svda",	0x3c070000,	0xfc0f0000,	"v,R",		2 },
+{ "svdl",	0x3c060000,	0xfc0f0000,	"v,R",		2 },
+{ "svdc",	0x3c050000,	0xfc0f0000,	"v,R",		2 },
+{ "svdad",	0x3c0e0000,	0xfc0f0000,	"v,R",		2 },
+{ "svdld",	0x3c0d0000,	0xfc0f0000,	"v,R",		2 },
+
+{ "sbm",	0xac080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "zbm",	0xac000000,	0xfc080000,	"f,xOA,X",	4 },
+{ "tbm",	0xa8080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "incmb",	0xa0000000,	0xfc080000,	"xOA,X",	4 },
+{ "incmh",	0xa0080000,	0xfc080000,	"xOA,X",	4 },
+{ "incmw",	0xa4000000,	0xfc080000,	"xOA,X",	4 },
+{ "incmd",	0xa4080000,	0xfc080000,	"xOA,X",	4 },
+{ "sbmd",	0x7c080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "zbmd",	0x7c000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "tbmd",	0x78080000,	0xfc080000,	"r,xOA,X",	4 },
+
+{ "ssm",	0x9c080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "zsm",	0x9c000000,	0xfc080000,	"f,xOA,X",	4 },
+{ "tsm",	0x98080000,	0xfc080000,	"f,xOA,X",	4 },
+
+{ "admb",	0xc8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "admh",	0xc8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "admw",	0xc8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "admd",	0xc8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "adr",	0x38000000,	0xfc0f0000,	"r,R",		2 },
+{ "armb",	0xe8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "armh",	0xe8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "armw",	0xe8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "armd",	0xe8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "adi",	0xf8010000,	0xfc0f0000,	"r,I",		4 },
+{ "sumb",	0xcc080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sumh",	0xcc000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "sumw",	0xcc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sumd",	0xcc000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "sur",	0x3c000000,	0xfc0f0000,	"r,R",		2 },
+{ "sui",	0xf8020000,	0xfc0f0000,	"r,I",		4 },
+{ "mpmb",	0xc0080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpmh",	0xc0000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "mpmw",	0xc0000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpr",	0x38020000,	0xfc0f0000,	"r,R",		2 },
+{ "mprd",	0x3c0f0000,	0xfc0f0000,	"r,R",		2 },
+{ "mpi",	0xf8030000,	0xfc0f0000,	"r,I",		4 },
+{ "dvmb",	0xc4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "dvmh",	0xc4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "dvmw",	0xc4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "dvr",	0x380a0000,	0xfc0f0000,	"r,R",		2 },
+{ "dvi",	0xf8040000,	0xfc0f0000,	"r,I",		4 },
+{ "exs",	0x38080000,	0xfc0f0000,	"r,R",		2 },
+
+{ "advv",	0x30000000,	0xfc0f0000,	"v,V",		2 },
+{ "advvd",	0x30080000,	0xfc0f0000,	"v,V",		2 },
+{ "adrv",	0x34000000,	0xfc0f0000,	"v,R",		2 },
+{ "adrvd",	0x34080000,	0xfc0f0000,	"v,R",		2 },
+{ "suvv",	0x30010000,	0xfc0f0000,	"v,V",		2 },
+{ "suvvd",	0x30090000,	0xfc0f0000,	"v,V",		2 },
+{ "surv",	0x34010000,	0xfc0f0000,	"v,R",		2 },
+{ "survd",	0x34090000,	0xfc0f0000,	"v,R",		2 },
+{ "mpvv",	0x30020000,	0xfc0f0000,	"v,V",		2 },
+{ "mprv",	0x34020000,	0xfc0f0000,	"v,R",		2 },
+
+{ "adfw",	0xe0080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "adfd",	0xe0080002,	0xfc080002,	"r,xOA,X",	4 },
+{ "adrfw",	0x38010000,	0xfc0f0000,	"r,R",		2 },
+{ "adrfd",	0x38090000,	0xfc0f0000,	"r,R",		2 },
+{ "surfw",	0xe0000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "surfd",	0xe0000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "surfw",	0x38030000,	0xfc0f0000,	"r,R",		2 },
+{ "surfd",	0x380b0000,	0xfc0f0000,	"r,R",		2 },
+{ "mpfw",	0xe4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpfd",	0xe4080002,	0xfc080002,	"r,xOA,X",	4 },
+{ "mprfw",	0x38060000,	0xfc0f0000,	"r,R",		2 },
+{ "mprfd",	0x380e0000,	0xfc0f0000,	"r,R",		2 },
+{ "rfw",	0xe4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "rfd",	0xe4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "rrfw",	0x0c0e0000,	0xfc0f0000,	"r",		2 },
+{ "rrfd",	0x0c0f0000,	0xfc0f0000,	"r",		2 },
+
+{ "advvfw",	0x30040000,	0xfc0f0000,	"v,V",		2 },
+{ "advvfd",	0x300c0000,	0xfc0f0000,	"v,V",		2 },
+{ "adrvfw",	0x34040000,	0xfc0f0000,	"v,R",		2 },
+{ "adrvfd",	0x340c0000,	0xfc0f0000,	"v,R",		2 },
+{ "suvvfw",	0x30050000,	0xfc0f0000,	"v,V",		2 },
+{ "suvvfd",	0x300d0000,	0xfc0f0000,	"v,V",		2 },
+{ "survfw",	0x34050000,	0xfc0f0000,	"v,R",		2 },
+{ "survfd",	0x340d0000,	0xfc0f0000,	"v,R",		2 },
+{ "mpvvfw",	0x30060000,	0xfc0f0000,	"v,V",		2 },
+{ "mpvvfd",	0x300e0000,	0xfc0f0000,	"v,V",		2 },
+{ "mprvfw",	0x34060000,	0xfc0f0000,	"v,R",		2 },
+{ "mprvfd",	0x340e0000,	0xfc0f0000,	"v,R",		2 },
+{ "rvfw",	0x30070000,	0xfc0f0000,	"v",		2 },
+{ "rvfd",	0x300f0000,	0xfc0f0000,	"v",		2 },
+
+{ "fltw",	0x38070000,	0xfc0f0000,	"r,R",		2 },
+{ "fltd",	0x380f0000,	0xfc0f0000,	"r,R",		2 },
+{ "fixw",	0x38050000,	0xfc0f0000,	"r,R",		2 },
+{ "fixd",	0x380d0000,	0xfc0f0000,	"r,R",		2 },
+{ "cfpds",	0x3c090000,	0xfc0f0000,	"r,R",		2 },
+
+{ "fltvw",	0x080d0000,	0xfc0f0000,	"v,V",		2 },
+{ "fltvd",	0x080f0000,	0xfc0f0000,	"v,V",		2 },
+{ "fixvw",	0x080c0000,	0xfc0f0000,	"v,V",		2 },
+{ "fixvd",	0x080e0000,	0xfc0f0000,	"v,V",		2 },
+{ "cfpvds",	0x0c0d0000,	0xfc0f0000,	"v,V",		2 },
+
+{ "orvrn",	0x000a0000,	0xfc0f0000,	"r,V",		2 },
+{ "andvrn",	0x00080000,	0xfc0f0000,	"r,V",		2 },
+{ "frsteq",	0x04090000,	0xfc0f0000,	"r,V",		2 },
+{ "sigma",	0x0c080000,	0xfc0f0000,	"r,V",		2 },
+{ "sigmad",	0x0c0a0000,	0xfc0f0000,	"r,V",		2 },
+{ "sigmf",	0x08080000,	0xfc0f0000,	"r,V",		2 },
+{ "sigmfd",	0x080a0000,	0xfc0f0000,	"r,V",		2 },
+{ "prodf",	0x04080000,	0xfc0f0000,	"r,V",		2 },
+{ "prodfd",	0x040a0000,	0xfc0f0000,	"r,V",		2 },
+{ "maxv",	0x10080000,	0xfc0f0000,	"r,V",		2 },
+{ "maxvd",	0x100a0000,	0xfc0f0000,	"r,V",		2 },
+{ "minv",	0x14080000,	0xfc0f0000,	"r,V",		2 },
+{ "minvd",	0x140a0000,	0xfc0f0000,	"r,V",		2 },
+
+{ "lpsd",	0xf0000000,	0xfc080000,	"xOA,X",	4 },
+{ "ldc",	0xf0080000,	0xfc080000,	"xOA,X",	4 },
+{ "spm",	0x040c0000,	0xfc0f0000,	"r",		2 },
+{ "rpm",	0x040d0000,	0xfc0f0000,	"r",		2 },
+{ "tritr",	0x00070000,	0xfc0f0000,	"r",		2 },
+{ "trrit",	0x00060000,	0xfc0f0000,	"r",		2 },
+{ "rpswt",	0x04080000,	0xfc0f0000,	"r",		2 },
+{ "exr",	0xf8070000,	0xfc0f0000,	"",		4 },
+{ "halt",	0x00000000,	0xfc0f0000,	"",		2 },
+{ "wait",	0x00010000,	0xfc0f0000,	"",		2 },
+{ "nop",	0x00020000,	0xfc0f0000,	"",		2 },
+{ "eiae",	0x00030000,	0xfc0f0000,	"",		2 },
+{ "efae",	0x000d0000,	0xfc0f0000,	"",		2 },
+{ "diae",	0x000e0000,	0xfc0f0000,	"",		2 },
+{ "dfae",	0x000f0000,	0xfc0f0000,	"",		2 },
+{ "spvc",	0xf8060000,	0xfc0f0000,	"r,T,N",	4 },
+{ "rdsts",	0x00090000,	0xfc0f0000,	"r",		2 },
+{ "setcpu",	0x000c0000,	0xfc0f0000,	"r",		2 },
+{ "cmc",	0x000b0000,	0xfc0f0000,	"r",		2 },
+{ "trrcu",	0x00040000,	0xfc0f0000,	"r",		2 },
+{ "attnio",	0x00050000,	0xfc0f0000,	"",		2 },
+{ "fudit",	0x28080000,	0xfc0f0000,	"",		2 },
+{ "break",	0x28090000,	0xfc0f0000,	"",		2 },
+{ "frzss",	0x280a0000,	0xfc0f0000,	"",		2 },
+{ "ripi",	0x04040000,	0xfc0f0000,	"r,R",		2 },
+{ "xcp",	0x04050000,	0xfc0f0000,	"r",		2 },
+{ "block",	0x04060000,	0xfc0f0000,	"",		2 },
+{ "unblock",	0x04070000,	0xfc0f0000,	"",		2 },
+{ "trsc",	0x08060000,	0xfc0f0000,	"r,R",		2 },
+{ "tscr",	0x08070000,	0xfc0f0000,	"r,R",		2 },
+{ "fq",		0x04080000,	0xfc0f0000,	"r",		2 },
+{ "flupte",	0x2c080000,	0xfc0f0000,	"r",		2 },
+{ "rviu",	0x040f0000,	0xfc0f0000,	"",		2 },
+{ "ldel",	0x280c0000,	0xfc0f0000,	"r,R",		2 },
+{ "ldu",	0x280d0000,	0xfc0f0000,	"r,R",		2 },
+{ "stdecc",	0x280b0000,	0xfc0f0000,	"r,R",		2 },
+{ "trpc",	0x08040000,	0xfc0f0000,	"r",		2 },
+{ "tpcr",	0x08050000,	0xfc0f0000,	"r",		2 },
+{ "ghalt",	0x0c050000,	0xfc0f0000,	"r",		2 },
+{ "grun",	0x0c040000,	0xfc0f0000,	"",		2 },
+{ "tmpr",	0x2c0a0000,	0xfc0f0000,	"r,R",		2 },
+{ "trmp",	0x2c0b0000,	0xfc0f0000,	"r,R",		2 },
+
+{ "trrve",	0x28060000,	0xfc0f0000,	"r",		2 },
+{ "trver",	0x28070000,	0xfc0f0000,	"r",		2 },
+{ "trvlr",	0x280f0000,	0xfc0f0000,	"r",		2 },
+
+{ "linkfl",	0x18000000,	0xfc0f0000,	"r,R",		2 },
+{ "linkbl",	0x18020000,	0xfc0f0000,	"r,R",		2 },
+{ "linkfp",	0x18010000,	0xfc0f0000,	"r,R",		2 },
+{ "linkbp",	0x18030000,	0xfc0f0000,	"r,R",		2 },
+{ "linkpl",	0x18040000,	0xfc0f0000,	"r,R",		2 },
+{ "ulinkl",	0x18080000,	0xfc0f0000,	"r,R",		2 },
+{ "ulinkp",	0x18090000,	0xfc0f0000,	"r,R",		2 },
+{ "ulinktl",	0x180a0000,	0xfc0f0000,	"r,R",		2 },
+{ "ulinktp",	0x180b0000,	0xfc0f0000,	"r,R",		2 },
+};
+
+int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]);
+
+struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) /
+		 		sizeof(gld_opcodes[0]);
diff --git a/binutils-2.25/include/opcode/ns32k.h b/binutils-2.25/include/opcode/ns32k.h
new file mode 100644
index 00000000..34c42f87
--- /dev/null
+++ b/binutils-2.25/include/opcode/ns32k.h
@@ -0,0 +1,487 @@
+/* ns32k-opcode.h -- Opcode table for National Semi 32k processor
+   Copyright 1987, 1991, 1994, 2002, 2010 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING3.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+#ifdef SEQUENT_COMPATABILITY
+#define DEF_MODEC 20
+#define DEF_MODEL 21
+#endif
+
+#ifndef DEF_MODEC
+#define DEF_MODEC 20
+#endif
+
+#ifndef DEF_MODEL
+#define DEF_MODEL 20
+#endif
+/*
+   After deciding the instruction entry (via hash.c) the instruction parser
+   will try to match the operands after the instruction to the required set
+   given in the entry operandfield. Every operand will result in a change in
+   the opcode or the addition of data to the opcode.
+   The operands in the source instruction are checked for inconsistent
+   semantics.
+
+	F : 32 bit float	general form
+	L : 64 bit float	    "
+	B : byte		    "
+	W : word		    "
+	D : double-word		    "
+	A : double-word		gen-address-form ie no regs, no immediate
+	I : integer writeable   gen int except immediate (A + reg)
+	Z : floating writeable	gen float except immediate (Z + freg)
+	d : displacement
+	b : displacement - pc relative addressing  acb
+	p : displacement - pc relative addressing  br bcond bsr cxp
+	q : quick
+	i : immediate (8 bits)
+	    This is not a standard ns32k operandtype, it is used to build
+	    instructions like    svc arg1,arg2
+	    Svc is the instruction SuperVisorCall and is sometimes used to
+	    call OS-routines from usermode. Some args might be handy!
+	r : register number (3 bits)
+	O : setcfg instruction optionslist
+	C : cinv instruction optionslist
+	S : stringinstruction optionslist
+	U : registerlist	save,enter
+	u : registerlist	restore,exit
+	M : mmu register
+	P : cpu register
+	g : 3:rd operand of inss or exts instruction
+	G : 4:th operand of inss or exts instruction
+	    Those operands are encoded in the same byte.
+	    This byte is placed last in the instruction.
+	f : operand of sfsr
+	H : sequent-hack for bsr (Warning)
+
+column	1 	instructions
+	2 	number of bits in opcode.
+	3 	number of bits in opcode explicitly
+		determined by the instruction type.
+	4 	opcodeseed, the number we build our opcode
+		from.
+	5 	operandtypes, used by operandparser.
+	6 	size in bytes of immediate
+*/
+struct ns32k_opcode {
+  const char *name;
+  unsigned char opcode_id_size; /* not used by the assembler */
+  unsigned char opcode_size;
+  unsigned long opcode_seed;
+  const char *operands;
+  unsigned char im_size;	/* not used by dissassembler */
+  const char *default_args;	/* default to those args when none given */
+  char default_modec;		/* default to this addr-mode when ambigous
+				   ie when the argument of a general addr-mode
+				   is a plain constant */
+  char default_model;		/* is a plain label */
+};
+
+#ifdef comment
+/* This section was from the gdb version of this file. */
+
+#ifndef ns32k_opcodeT
+#define ns32k_opcodeT int
+#endif /* no ns32k_opcodeT */
+
+struct not_wot			/* ns32k opcode table: wot to do with this */
+				/* particular opcode */
+{
+  int obits;			/* number of opcode bits */
+  int ibits;			/* number of instruction bits */
+  ns32k_opcodeT code;		/* op-code (may be > 8 bits!) */
+  const char *args;		/* how to compile said opcode */
+};
+
+struct not			/* ns32k opcode text */
+{
+  const char *name;		/* opcode name: lowercase string  [key]  */
+  struct not_wot detail;	/* rest of opcode table          [datum] */
+};
+
+/* Instructions look like this:
+
+   basic instruction--1, 2, or 3 bytes
+   index byte for operand A, if operand A is indexed--1 byte
+   index byte for operand B, if operand B is indexed--1 byte
+   addressing extension for operand A
+   addressing extension for operand B
+   implied operands
+
+   Operand A is the operand listed first in the following opcode table.
+   Operand B is the operand listed second in the following opcode table.
+   All instructions have at most 2 general operands, so this is enough.
+   The implied operands are associated with operands other than A and B.
+
+   Each operand has a digit and a letter.
+
+   The digit gives the position in the assembly language.  The letter,
+   one of the following, tells us what kind of operand it is.  */
+
+/* F : 32 bit float
+ * L : 64 bit float
+ * B : byte
+ * W : word
+ * D : double-word
+ * I : integer not immediate
+ * Z : floating not immediate
+ * d : displacement
+ * q : quick
+ * i : immediate (8 bits)
+ * r : register number (3 bits)
+ * p : displacement - pc relative addressing
+*/
+
+
+#endif /* comment */
+
+static const struct ns32k_opcode ns32k_opcodes[]=
+{
+  { "absf",	14,24,	0x35be,	"1F2Z",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "absl",	14,24,	0x34be,	"1L2Z",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "absb",	14,24,	0x304e, "1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "absw",	14,24,	0x314e, "1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "absd",	14,24,	0x334e, "1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "acbb",	 7,16,	0x4c,	"2I1q3p",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "acbw",	 7,16,	0x4d,	"2I1q3p",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "acbd",	 7,16,	0x4f,	"2I1q3p",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addf",	14,24,	0x01be,	"1F2Z",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addl",	14,24,	0x00be, "1L2Z",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addb",	 6,16,	0x00,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addw",	 6,16,	0x01,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addd",	 6,16,	0x03,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addcb",	 6,16,	0x10,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addcw",	 6,16,	0x11,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addcd",	 6,16,	0x13,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addpb",	14,24,	0x3c4e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addpw",	14,24,	0x3d4e,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addpd",	14,24,	0x3f4e,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addqb",	 7,16,	0x0c,	"2I1q",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addqw",	 7,16,	0x0d,	"2I1q",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addqd",	 7,16,	0x0f,	"2I1q",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "addr",	 6,16,	0x27,	"1A2I",		4,	"",	21,21	},
+  { "adjspb",	11,16,	0x057c,	"1B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "adjspw",	11,16,	0x057d,	"1W", 		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "adjspd",	11,16,	0x057f,	"1D", 		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "andb",	 6,16,	0x28,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "andw",	 6,16,	0x29,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "andd",	 6,16,	0x2b,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ashb",	14,24,	0x044e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ashw",	14,24,	0x054e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ashd",	14,24,	0x074e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "beq",	 8,8,	0x0a,	"1p",		0,	"",	21,21	},
+  { "bne",	 8,8,	0x1a,	"1p",		0,	"",	21,21	},
+  { "bcs",	 8,8,	0x2a,	"1p",		0,	"",	21,21	},
+  { "bcc",	 8,8,	0x3a,	"1p",		0,	"",	21,21	},
+  { "bhi",	 8,8,	0x4a,	"1p",		0,	"",	21,21	},
+  { "bls",	 8,8,	0x5a,	"1p",		0,	"",	21,21	},
+  { "bgt",	 8,8,	0x6a,	"1p",		0,	"",	21,21	},
+  { "ble",	 8,8,	0x7a,	"1p",		0,	"",	21,21	},
+  { "bfs",	 8,8,	0x8a,	"1p",		0,	"",	21,21	},
+  { "bfc",	 8,8,	0x9a,	"1p",		0,	"",	21,21	},
+  { "blo",	 8,8,	0xaa,	"1p",		0,	"",	21,21	},
+  { "bhs",	 8,8,	0xba,	"1p",		0,	"",	21,21	},
+  { "blt",	 8,8,	0xca,	"1p",		0,	"",	21,21	},
+  { "bge",	 8,8,	0xda,	"1p",		0,	"",	21,21	},
+  { "but",	 8,8,	0xea,	"1p",		0,	"",	21,21	},
+  { "buf",	 8,8,	0xfa,	"1p",		0,	"",	21,21	},
+  { "bicb",	 6,16,	0x08,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "bicw",	 6,16,	0x09,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "bicd",	 6,16,	0x0b,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "bicpsrb",	11,16,	0x17c,	"1B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "bicpsrw",	11,16,	0x17d,	"1W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "bispsrb",	11,16,	0x37c,	"1B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "bispsrw",	11,16,	0x37d,	"1W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "bpt",	 8,8,	0xf2,	"",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "br",	 8,8,	0xea,	"1p",		0,	"",	21,21	},
+#ifdef SEQUENT_COMPATABILITY
+  { "bsr",	 8,8,	0x02,	"1H",		0,	"",	21,21	},
+#else
+  { "bsr",	 8,8,	0x02,	"1p",		0,	"",	21,21	},
+#endif
+  { "caseb",	11,16,	0x77c,	"1B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "casew",	11,16,	0x77d,	"1W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cased",	11,16,	0x77f,	"1D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cbitb",	14,24,	0x084e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cbitw",	14,24,	0x094e,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cbitd",	14,24,	0x0b4e,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cbitib",	14,24,	0x0c4e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cbitiw",	14,24,	0x0d4e,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cbitid",	14,24,	0x0f4e,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "checkb",	11,24,	0x0ee,	"2A3B1r",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "checkw",	11,24,	0x1ee,	"2A3W1r",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "checkd",	11,24,	0x3ee,	"2A3D1r",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cinv",	14,24,	0x271e,	"2D1C",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpf",	14,24,	0x09be,	"1F2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpl",	14,24,	0x08be,	"1L2L",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpb",	 6,16,	0x04,	"1B2B",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpw",	 6,16,	0x05,	"1W2W",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpd",	 6,16,	0x07,	"1D2D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpmb",	14,24,	0x04ce,	"1A2A3b",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpmw",	14,24,	0x05ce,	"1A2A3b",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpmd",	14,24,	0x07ce,	"1A2A3b",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpqb",	 7,16,	0x1c,	"2B1q",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpqw",	 7,16,	0x1d,	"2W1q",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpqd",	 7,16,	0x1f,	"2D1q",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cmpsb",	16,24,	0x040e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "cmpsw",	16,24,	0x050e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "cmpsd",	16,24,	0x070e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "cmpst",	16,24,	0x840e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "comb",	14,24,	0x344e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "comw",	14,24,	0x354e,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "comd",	14,24,	0x374e,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cvtp",	11,24,	0x036e,	"2A3D1r",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "cxp",	 8,8,	0x22,	"1p",		0,	"",	21,21	},
+  { "cxpd",	11,16,	0x07f,	"1A",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "deib",	14,24,	0x2cce,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "deiw",	14,24,	0x2dce,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "deid",	14,24,	0x2fce,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "dia",	 8,8,	0xc2,	"",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "divf",	14,24,	0x21be,	"1F2Z",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "divl",	14,24,	0x20be,	"1L2Z",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "divb",	14,24,	0x3cce,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "divw",	14,24,	0x3dce,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "divd",	14,24,	0x3fce,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "enter",	 8,8,	0x82,	"1U2d",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "exit",	 8,8,	0x92,	"1u",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "extb",	11,24,	0x02e,	"2I3B1r4d",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "extw",	11,24,	0x12e,	"2I3W1r4d",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "extd",	11,24,	0x32e,	"2I3D1r4d",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "extsb",	14,24,	0x0cce,	"1I2I4G3g",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "extsw",	14,24,	0x0dce,	"1I2I4G3g",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "extsd",	14,24,	0x0fce,	"1I2I4G3g",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ffsb",	14,24,	0x046e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ffsw",	14,24,	0x056e,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ffsd",	14,24,	0x076e,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "flag",	 8,8,	0xd2,	"",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "floorfb",	14,24,	0x3c3e,	"1F2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "floorfw",	14,24,	0x3d3e,	"1F2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "floorfd",	14,24,	0x3f3e,	"1F2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "floorlb",	14,24,	0x383e,	"1L2I",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "floorlw",	14,24,	0x393e,	"1L2I",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "floorld",	14,24,	0x3b3e,	"1L2I",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ibitb",	14,24,	0x384e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ibitw",	14,24,	0x394e,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ibitd",	14,24,	0x3b4e,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "indexb",	11,24,	0x42e,	"2B3B1r",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "indexw",	11,24,	0x52e,	"2W3W1r",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "indexd",	11,24,	0x72e,	"2D3D1r",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "insb",	11,24,	0x0ae,	"2B3I1r4d",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "insw",	11,24,	0x1ae,	"2W3I1r4d",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "insd",	11,24,	0x3ae,	"2D3I1r4d",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "inssb",	14,24,	0x08ce,	"1B2I4G3g",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "inssw",	14,24,	0x09ce,	"1W2I4G3g",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "inssd",	14,24,	0x0bce,	"1D2I4G3g",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "jsr",	11,16,	0x67f,	"1A",		4,	"",	21,21	},
+  { "jump",	11,16,	0x27f,	"1A",		4,	"",	21,21	},
+  { "lfsr",	19,24,	0x00f3e,"1D",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "lmr",	15,24,	0x0b1e,	"2D1M",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "lprb",	 7,16,	0x6c,	"2B1P",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "lprw",	 7,16,	0x6d,	"2W1P",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "lprd",	 7,16,	0x6f,	"2D1P",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "lshb",	14,24,	0x144e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "lshw",	14,24,	0x154e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "lshd",	14,24,	0x174e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "meib",	14,24,	0x24ce,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "meiw",	14,24,	0x25ce,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "meid",	14,24,	0x27ce,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "modb",	14,24,	0x38ce,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "modw",	14,24,	0x39ce,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "modd",	14,24,	0x3bce,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movf",	14,24,	0x05be,	"1F2Z",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movl",	14,24,	0x04be,	"1L2Z",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movb",	 6,16,	0x14,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movw",	 6,16,	0x15,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movd",	 6,16,	0x17,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movbf",	14,24,	0x043e,	"1B2Z",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movwf",	14,24,	0x053e,	"1W2Z",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movdf",	14,24,	0x073e,	"1D2Z",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movbl",	14,24,	0x003e,	"1B2Z",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movwl",	14,24,	0x013e,	"1W2Z",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movdl",	14,24,	0x033e,	"1D2Z",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movfl",	14,24,	0x1b3e,	"1F2Z",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movlf",	14,24,	0x163e,	"1L2Z",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movmb",	14,24,	0x00ce,	"1A2A3b",	1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movmw",	14,24,	0x01ce,	"1A2A3b",	2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movmd",	14,24,	0x03ce,	"1A2A3b",	4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movqb",	 7,16,	0x5c,	"2I1q",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movqw",	 7,16,	0x5d,	"2I1q",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movqd",	 7,16,	0x5f,	"2I1q",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movsb",	16,24,	0x000e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "movsw",	16,24,	0x010e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "movsd",	16,24,	0x030e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "movst",	16,24,	0x800e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "movsub",	14,24,	0x0cae,	"1A2A",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movsuw",	14,24,	0x0dae,	"1A2A",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movsud",	14,24,	0x0fae,	"1A2A",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movusb",	14,24,	0x1cae,	"1A2A",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movusw",	14,24,	0x1dae,	"1A2A",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movusd",	14,24,	0x1fae,	"1A2A",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movxbd",	14,24,	0x1cce,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movxwd",	14,24,	0x1dce,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movxbw",	14,24,	0x10ce,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movzbd",	14,24,	0x18ce,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movzwd",	14,24,	0x19ce,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "movzbw",	14,24,	0x14ce,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "mulf",	14,24,	0x31be,	"1F2Z",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "mull",	14,24,	0x30be,	"1L2Z",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "mulb",	14,24,	0x20ce, "1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "mulw",	14,24,	0x21ce, "1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "muld",	14,24,	0x23ce, "1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "negf",	14,24,	0x15be, "1F2Z",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "negl",	14,24,	0x14be, "1L2Z",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "negb",	14,24,	0x204e, "1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "negw",	14,24,	0x214e, "1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "negd",	14,24,	0x234e, "1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "nop",	 8,8,	0xa2,	"",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "notb",	14,24,	0x244e, "1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "notw",	14,24,	0x254e, "1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "notd",	14,24,	0x274e, "1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "orb",	 6,16,	0x18,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "orw",	 6,16,	0x19,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ord",	 6,16,	0x1b,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "quob",	14,24,	0x30ce,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "quow",	14,24,	0x31ce,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "quod",	14,24,	0x33ce,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "rdval",	19,24,	0x0031e,"1A",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "remb",	14,24,	0x34ce,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "remw",	14,24,	0x35ce,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "remd",	14,24,	0x37ce,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "restore",	 8,8,	0x72,	"1u",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "ret",	 8,8,	0x12,	"1d",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "reti",	 8,8,	0x52,	"",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "rett",	 8,8,	0x42,	"1d",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "rotb",	14,24,	0x004e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "rotw",	14,24,	0x014e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "rotd",	14,24,	0x034e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "roundfb",	14,24,	0x243e,	"1F2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "roundfw",	14,24,	0x253e,	"1F2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "roundfd",	14,24,	0x273e,	"1F2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "roundlb",	14,24,	0x203e,	"1L2I",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "roundlw",	14,24,	0x213e,	"1L2I",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "roundld",	14,24,	0x233e,	"1L2I",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "rxp",	 8,8,	0x32,	"1d",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "seqb",	11,16,	0x3c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "seqw",	11,16,	0x3d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "seqd",	11,16,	0x3f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sneb",	11,16,	0xbc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "snew",	11,16,	0xbd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sned",	11,16,	0xbf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "scsb",	11,16,	0x13c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "scsw",	11,16,	0x13d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "scsd",	11,16,	0x13f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sccb",	11,16,	0x1bc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sccw",	11,16,	0x1bd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sccd",	11,16,	0x1bf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "shib",	11,16,	0x23c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "shiw",	11,16,	0x23d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "shid",	11,16,	0x23f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "slsb",	11,16,	0x2bc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "slsw",	11,16,	0x2bd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "slsd",	11,16,	0x2bf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sgtb",	11,16,	0x33c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sgtw",	11,16,	0x33d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sgtd",	11,16,	0x33f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sleb",	11,16,	0x3bc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "slew",	11,16,	0x3bd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sled",	11,16,	0x3bf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sfsb",	11,16,	0x43c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sfsw",	11,16,	0x43d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sfsd",	11,16,	0x43f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sfcb",	11,16,	0x4bc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sfcw",	11,16,	0x4bd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sfcd",	11,16,	0x4bf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "slob",	11,16,	0x53c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "slow",	11,16,	0x53d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "slod",	11,16,	0x53f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "shsb",	11,16,	0x5bc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "shsw",	11,16,	0x5bd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "shsd",	11,16,	0x5bf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sltb",	11,16,	0x63c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sltw",	11,16,	0x63d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sltd",	11,16,	0x63f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sgeb",	11,16,	0x6bc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sgew",	11,16,	0x6bd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sged",	11,16,	0x6bf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sutb",	11,16,	0x73c,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sutw",	11,16,	0x73d,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sutd",	11,16,	0x73f,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sufb",	11,16,	0x7bc,	"1B",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sufw",	11,16,	0x7bd,	"1W",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sufd",	11,16,	0x7bf,	"1D",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "save",	 8,8,	0x62,	"1U",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sbitb",    14,24,	0x184e,	"1B2A",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sbitw",	14,24,	0x194e,	"1W2A",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sbitd",	14,24,	0x1b4e,	"1D2A",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sbitib",	14,24,	0x1c4e,	"1B2A",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sbitiw",	14,24,	0x1d4e,	"1W2A",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sbitid",	14,24,	0x1f4e,	"1D2A",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "setcfg",	15,24,	0x0b0e,	"1O",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sfsr",	14,24,	0x373e,	"1f",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "skpsb",	16,24,	0x0c0e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "skpsw",	16,24,	0x0d0e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "skpsd",	16,24,	0x0f0e, "1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "skpst",	16,24,	0x8c0e,	"1S",		0,	"[]",	DEF_MODEC,DEF_MODEL	},
+  { "smr",	15,24,	0x0f1e,	"2I1M",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sprb",	 7,16,	0x2c,	"2I1P",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sprw",	 7,16,	0x2d,	"2I1P",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "sprd",	 7,16,	0x2f,	"2I1P",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subf",	14,24,	0x11be,	"1F2Z",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subl",	14,24,	0x10be,	"1L2Z",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subb",	 6,16,	0x20,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subw",	 6,16,	0x21,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subd",	 6,16,	0x23,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subcb",	 6,16,	0x30,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subcw",	 6,16,	0x31,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subcd",	 6,16,	0x33,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subpb",	14,24,	0x2c4e,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subpw",	14,24,	0x2d4e,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "subpd",	14,24,	0x2f4e,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+#ifdef NS32K_SVC_IMMED_OPERANDS
+  { "svc",	 8,8,	0xe2,	"2i1i",		1,	"",	DEF_MODEC,DEF_MODEL	}, /* not really, but some unix uses it */
+#else
+  { "svc",	 8,8,	0xe2,	"",		0,	"",	DEF_MODEC,DEF_MODEL	},
+#endif
+  { "tbitb",	 6,16,	0x34,	"1B2A",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "tbitw",	 6,16,	0x35,	"1W2A",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "tbitd",	 6,16,	0x37,	"1D2A",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "truncfb",	14,24,	0x2c3e,	"1F2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "truncfw",	14,24,	0x2d3e,	"1F2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "truncfd",	14,24,	0x2f3e,	"1F2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "trunclb",	14,24,	0x283e,	"1L2I",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "trunclw",	14,24,	0x293e,	"1L2I",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "truncld",	14,24,	0x2b3e,	"1L2I",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "wait",	 8,8,	0xb2,	"",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "wrval",	19,24,	0x0071e,"1A",		0,	"",	DEF_MODEC,DEF_MODEL	},
+  { "xorb",	 6,16,	0x38,	"1B2I",		1,	"",	DEF_MODEC,DEF_MODEL	},
+  { "xorw",	 6,16,	0x39,	"1W2I",		2,	"",	DEF_MODEC,DEF_MODEL	},
+  { "xord",	 6,16,	0x3b,	"1D2I",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "dotf",	14,24,  0x0dfe, "1F2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "dotl",	14,24,  0x0cfe, "1L2L",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "logbf",	14,24,  0x15fe, "1F2Z",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "logbl",	14,24,  0x14fe, "1L2Z",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "polyf",	14,24,  0x09fe, "1F2F",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "polyl",	14,24,  0x08fe, "1L2L",		8,	"",	DEF_MODEC,DEF_MODEL	},
+  { "scalbf",	14,24,  0x11fe, "1F2Z",		4,	"",	DEF_MODEC,DEF_MODEL	},
+  { "scalbl",	14,24,  0x10fe, "1L2Z",		8,	"",	DEF_MODEC,DEF_MODEL	},
+};
+
+#define MAX_ARGS 4
+#define ARG_LEN 50
+
diff --git a/binutils-2.25/include/opcode/or32.h b/binutils-2.25/include/opcode/or32.h
new file mode 100644
index 00000000..153d91ec
--- /dev/null
+++ b/binutils-2.25/include/opcode/or32.h
@@ -0,0 +1,181 @@
+/* Table of opcodes for the OpenRISC 1000 ISA.
+   Copyright 2002, 2003, 2010 Free Software Foundation, Inc.
+   Contributed by Damjan Lampret (lampret@opencores.org).
+   
+   This file is part of or1k_gen_isa, or1ksim, GDB and GAS.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* We treat all letters the same in encode/decode routines so
+   we need to assign some characteristics to them like signess etc.  */
+
+#ifndef OR32_H_ISA
+#define OR32_H_ISA
+
+#define NUM_UNSIGNED (0)
+#define NUM_SIGNED (1)
+
+#define MAX_GPRS 32
+#define PAGE_SIZE 4096
+#undef __HALF_WORD_INSN__
+
+#define OPERAND_DELIM (',')
+
+#define OR32_IF_DELAY (1)
+#define OR32_W_FLAG   (2)
+#define OR32_R_FLAG   (4)
+
+struct or32_letter
+{
+  char letter;
+  int  sign;
+  /* int  reloc; relocation per letter ??  */
+};
+
+/* Main instruction specification array.  */
+struct or32_opcode
+{
+  /* Name of the instruction.  */
+  char *name;
+
+  /* A string of characters which describe the operands.
+     Valid characters are:
+     ,() Itself.  Characters appears in the assembly code.
+     rA	 Register operand.
+     rB  Register operand.
+     rD  Register operand.
+     I	 An immediate operand, range -32768 to 32767.
+     J	 An immediate operand, range . (unused)
+     K	 An immediate operand, range 0 to 65535.
+     L	 An immediate operand, range 0 to 63.
+     M	 An immediate operand, range . (unused)
+     N	 An immediate operand, range -33554432 to 33554431.
+     O	 An immediate operand, range . (unused).  */
+  char *args;
+  
+  /* Opcode and operand encoding.  */
+  char *encoding;
+  void (*exec) (void);
+  unsigned int flags;
+};
+
+#define OPTYPE_LAST (0x80000000)
+#define OPTYPE_OP   (0x40000000)
+#define OPTYPE_REG  (0x20000000)
+#define OPTYPE_SIG  (0x10000000)
+#define OPTYPE_DIS  (0x08000000)
+#define OPTYPE_DST  (0x04000000)
+#define OPTYPE_SBIT (0x00001F00)
+#define OPTYPE_SHR  (0x0000001F)
+#define OPTYPE_SBIT_SHR (8)
+
+/* MM: Data how to decode operands.  */
+extern struct insn_op_struct
+{
+  unsigned long type;
+  unsigned long data;
+} **op_start;
+
+#ifdef HAS_EXECUTION
+extern void l_invalid (void);
+extern void l_sfne    (void);
+extern void l_bf      (void);
+extern void l_add     (void);
+extern void l_sw      (void);
+extern void l_sb      (void);
+extern void l_sh      (void);
+extern void l_lwz     (void);
+extern void l_lbs     (void);
+extern void l_lbz     (void);
+extern void l_lhs     (void);
+extern void l_lhz     (void);
+extern void l_movhi   (void);
+extern void l_and     (void);
+extern void l_or      (void);
+extern void l_xor     (void);
+extern void l_sub     (void);
+extern void l_mul     (void);
+extern void l_div     (void);
+extern void l_divu    (void);
+extern void l_sll     (void);
+extern void l_sra     (void);
+extern void l_srl     (void);
+extern void l_j       (void);
+extern void l_jal     (void);
+extern void l_jalr    (void);
+extern void l_jr      (void);
+extern void l_rfe     (void);
+extern void l_nop     (void);
+extern void l_bnf     (void);
+extern void l_sfeq    (void);
+extern void l_sfgts   (void);
+extern void l_sfges   (void);
+extern void l_sflts   (void);
+extern void l_sfles   (void);
+extern void l_sfgtu   (void);
+extern void l_sfgeu   (void);
+extern void l_sfltu   (void);
+extern void l_sfleu   (void);
+extern void l_mtspr   (void);
+extern void l_mfspr   (void);
+extern void l_sys     (void);
+extern void l_trap    (void); /* CZ 21/06/01.  */
+extern void l_macrc   (void);
+extern void l_mac     (void);
+extern void l_msb     (void);
+extern void l_invalid (void);
+extern void l_cust1   (void);
+extern void l_cust2   (void);
+extern void l_cust3   (void);
+extern void l_cust4   (void);
+#endif
+extern void l_none    (void);
+
+extern const struct or32_letter or32_letters[];
+
+extern const struct  or32_opcode or32_opcodes[];
+
+extern const unsigned int or32_num_opcodes;
+
+/* Calculates instruction length in bytes.  Always 4 for OR32.  */
+extern int insn_len (int);
+
+/* Is individual insn's operand signed or unsigned?  */
+extern int letter_signed (char);
+
+/* Number of letters in the individual lettered operand.  */
+extern int letter_range (char);
+
+/* MM: Returns index of given instruction name.  */
+extern int insn_index (char *);
+
+/* MM: Returns instruction name from index.  */
+extern const char *insn_name (int);
+
+/* MM: Constructs new FSM, based on or32_opcodes.  */ 
+extern void build_automata (void);
+
+/* MM: Destructs FSM.  */ 
+extern void destruct_automata (void);
+
+/* MM: Decodes instruction using FSM.  Call build_automata first.  */
+extern int insn_decode (unsigned int);
+
+/* Disassemble one instruction from insn to disassemble.
+   Return the size of the instruction.  */
+int disassemble_insn (unsigned long);
+
+#endif
diff --git a/binutils-2.25/include/opcode/pdp11.h b/binutils-2.25/include/opcode/pdp11.h
new file mode 100644
index 00000000..24e13b25
--- /dev/null
+++ b/binutils-2.25/include/opcode/pdp11.h
@@ -0,0 +1,84 @@
+/* PDP-11 opcde list.
+   Copyright 2001, 2002, 2010 Free Software Foundation, Inc.
+
+   This file is part of GDB and GAS.
+
+   GDB and GAS are free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GDB and GAS are distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GDB or GAS; see the file COPYING3.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+/* PDP-11 opcode types.  */
+
+#define PDP11_OPCODE_NO_OPS	 0
+#define PDP11_OPCODE_REG	 1	/* register */
+#define PDP11_OPCODE_OP		 2	/* generic operand */
+#define PDP11_OPCODE_REG_OP	 3	/* register and generic operand */
+#define PDP11_OPCODE_REG_OP_REV	 4	/* register and generic operand,
+					   reversed syntax */
+#define PDP11_OPCODE_AC_FOP	 5	/* fpu accumulator and generic float
+					   operand */
+#define PDP11_OPCODE_OP_OP	 6	/* two generic operands */
+#define PDP11_OPCODE_DISPL	 7	/* pc-relative displacement */
+#define PDP11_OPCODE_REG_DISPL	 8	/* redister and pc-relative
+					   displacement */
+#define PDP11_OPCODE_IMM8	 9	/* 8-bit immediate */
+#define PDP11_OPCODE_IMM6	10	/* 6-bit immediate */
+#define PDP11_OPCODE_IMM3	11	/* 3-bit immediate */
+#define PDP11_OPCODE_ILLEGAL	12	/* illegal instruction */
+#define PDP11_OPCODE_FOP_AC	13	/* generic float argument, then fpu
+					   accumulator */
+#define PDP11_OPCODE_FOP	14	/* generic float operand */
+#define PDP11_OPCODE_AC_OP	15	/* fpu accumulator and generic int
+					   operand */
+#define PDP11_OPCODE_OP_AC	16	/* generic int argument, then fpu
+					   accumulator */
+
+/*
+ * PDP-11 instruction set extensions.
+ *
+ * Please keep the numbers low, as they are used as indices into
+ * an array.
+ */
+
+#define PDP11_NONE	 0	/* not in instruction set */
+#define PDP11_BASIC	 1	/* basic instruction set (11/20 etc) */
+#define PDP11_CSM	 2	/* commercial instruction set */
+#define PDP11_CIS	 3	/* commercial instruction set */
+#define PDP11_EIS	 4	/* extended instruction set (11/45 etc) */
+#define PDP11_FIS	 5	/* KEV11 floating-point instructions */
+#define PDP11_FPP	 6	/* FP-11 floating-point instructions */
+#define PDP11_LEIS	 7	/* limited extended instruction set
+				   (11/40 etc) */
+#define PDP11_MFPT	 8	/* move from processor type */
+#define PDP11_MPROC	 9	/* multiprocessor instructions: tstset,
+				   wrtlck */
+#define PDP11_MXPS	10	/* move from/to processor status */
+#define PDP11_SPL	11	/* set priority level */
+#define PDP11_UCODE	12	/* microcode instructions: ldub, med, xfc */
+#define PDP11_EXT_NUM	13	/* total number of extension types */
+
+struct pdp11_opcode
+{
+  const char *name;
+  int opcode;
+  int mask;
+  int type;
+  int extension;
+};
+
+extern const struct pdp11_opcode pdp11_opcodes[];
+extern const struct pdp11_opcode pdp11_aliases[];
+extern const int pdp11_num_opcodes, pdp11_num_aliases;
+
+/* end of pdp11.h */
diff --git a/binutils-2.25/include/opcode/pj.h b/binutils-2.25/include/opcode/pj.h
new file mode 100644
index 00000000..e6ffacc4
--- /dev/null
+++ b/binutils-2.25/include/opcode/pj.h
@@ -0,0 +1,49 @@
+/* Definitions for decoding the picoJava opcode table.
+   Copyright 1999, 2002, 2003, 2010 Free Software Foundation, Inc.
+   Contributed by Steve Chamberlain of Transmeta (sac@pobox.com).
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* Names used to describe the type of instruction arguments, used by
+   the assembler and disassembler.  Attributes are encoded in various fields. */
+
+/*            reloc  size pcrel    uns */
+#define O_N    0
+#define O_16  (1<<4 | 2 | (0<<6) | (0<<3))
+#define O_U16 (1<<4 | 2 | (0<<6) | (1<<3))
+#define O_R16 (2<<4 | 2 | (1<<6) | (0<<3))
+#define O_8   (3<<4 | 1 | (0<<6) | (0<<3))
+#define O_U8  (3<<4 | 1 | (0<<6) | (1<<3))
+#define O_R8  (4<<4 | 1 | (0<<6) | (0<<3))
+#define O_R32 (5<<4 | 4 | (1<<6) | (0<<3))
+#define O_32  (6<<4 | 4 | (0<<6) | (0<<3))
+
+#define ASIZE(x)  ((x) & 0x7)
+#define PCREL(x)  (!!((x) & (1<<6)))
+#define UNS(x)    (!!((x) & (1<<3)))
+
+                  
+typedef struct pj_opc_info_t
+{
+  short opcode;
+  short opcode_next;
+  char len;
+  unsigned char arg[2];
+  union {
+    const char *name;
+    void (*func) (struct pj_opc_info_t *, char *);
+  } u;
+} pj_opc_info_t;
diff --git a/binutils-2.25/include/opcode/pn.h b/binutils-2.25/include/opcode/pn.h
new file mode 100644
index 00000000..6674030c
--- /dev/null
+++ b/binutils-2.25/include/opcode/pn.h
@@ -0,0 +1,283 @@
+/* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger.
+   Copyright 1986, 1987, 1989, 1991, 2010 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   GDB is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GDB is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GDB; see the file COPYING3.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+struct gld_opcode
+{
+  char *name;
+  unsigned long opcode;
+  unsigned long mask;
+  char *args;
+  int length;
+};
+
+/* We store four bytes of opcode for all opcodes because that
+   is the most any of them need.  The actual length of an instruction
+   is always at least 2 bytes, and at most four.  The length of the
+   instruction is based on the opcode.
+
+   The mask component is a mask saying which bits must match
+   particular opcode in order for an instruction to be an instance
+   of that opcode.
+
+   The args component is a string containing characters
+   that are used to format the arguments to the instruction. */
+
+/* Kinds of operands:
+   r  Register in first field
+   R  Register in second field
+   b  Base register in first field
+   B  Base register in second field
+   v  Vector register in first field
+   V  Vector register in first field
+   A  Optional address register (base register)
+   X  Optional index register
+   I  Immediate data (16bits signed)
+   O  Offset field (16bits signed)
+   h  Offset field (15bits signed)
+   d  Offset field (14bits signed)
+   S  Shift count field
+
+   any other characters are printed as is...
+*/
+
+/* The assembler requires that this array be sorted as follows:
+   all instances of the same mnemonic must be consecutive.
+   All instances of the same mnemonic with the same number of operands
+   must be consecutive.
+ */
+struct gld_opcode gld_opcodes[] =
+{
+{ "abm",	0xa0080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "abr",	0x18080000,	0xfc0c0000,	"r,f",		2 },
+{ "aci",	0xfc770000,	0xfc7f8000,	"r,I",		4 },
+{ "adfd",	0xe0080002,	0xfc080002,	"r,xOA,X",	4 },
+{ "adfw",	0xe0080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "adi",	0xc8010000,	0xfc7f0000,	"r,I",		4 },
+{ "admb",	0xb8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "admd",	0xb8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "admh",	0xb8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "admw",	0xb8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "adr",	0x38000000,	0xfc0f0000,	"r,R",		2 },
+{ "adrfd",	0x38090000,	0xfc0f0000,	"r,R",		2 },
+{ "adrfw",	0x38010000,	0xfc0f0000,	"r,R",		2 },
+{ "adrm",	0x38080000,	0xfc0f0000,	"r,R",		2 },
+{ "ai", 	0xfc030000,	0xfc07ffff,	"I",		4 },
+{ "anmb",	0x84080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "anmd",	0x84000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "anmh",	0x84000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "anmw",	0x84000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "anr",	0x04000000,	0xfc0f0000,	"r,R",		2 },
+{ "armb",	0xe8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "armd",	0xe8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "armh",	0xe8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "armw",	0xe8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "bcf",	0xf0000000,	0xfc080000,	"I,xOA,X",	4 },
+{ "bct",	0xec000000,	0xfc080000,	"I,xOA,X",	4 },
+{ "bei",	0x00060000,	0xffff0000,	"",		2 },
+{ "bft",	0xf0000000,	0xff880000,	"xOA,X",	4 },
+{ "bib",	0xf4000000,	0xfc780000,	"r,xOA",	4 },
+{ "bid",	0xf4600000,	0xfc780000,	"r,xOA",	4 },
+{ "bih",	0xf4200000,	0xfc780000,	"r,xOA",	4 },
+{ "biw",	0xf4400000,	0xfc780000,	"r,xOA",	4 },
+{ "bl", 	0xf8800000,	0xff880000,	"xOA,X",	4 },
+{ "bsub",	0x5c080000,	0xff8f0000,	"",		2 },
+{ "bsubm",	0x28080000,	0xfc080000,	"",		4 },
+{ "bu", 	0xec000000,	0xff880000,	"xOA,X",	4 },
+{ "call",	0x28080000,	0xfc0f0000,	"",		2 },
+{ "callm",	0x5c080000,	0xff880000,	"",		4 },
+{ "camb",	0x90080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "camd",	0x90000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "camh",	0x90000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "camw",	0x90000000,	0xfc080000,	"r.xOA,X",	4 },
+{ "car",	0x10000000,	0xfc0f0000,	"r,R",		2 },
+{ "cd", 	0xfc060000,	0xfc070000,	"r,f",		4 },
+{ "cea",	0x000f0000,	0xffff0000,	"",		2 },
+{ "ci", 	0xc8050000,	0xfc7f0000,	"r,I",		4 },
+{ "cmc",	0x040a0000,	0xfc7f0000,	"r",		2 },
+{ "cmmb",	0x94080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "cmmd",	0x94000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "cmmh",	0x94000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "cmmw",	0x94000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "cmr",	0x14000000,	0xfc0f0000,	"r,R",		2 },
+{ "daci",	0xfc7f0000,	0xfc7f8000,	"r,I",		4 },
+{ "dae",	0x000e0000,	0xffff0000,	"",		2 },
+{ "dai",	0xfc040000,	0xfc07ffff,	"I",		4 },
+{ "dci",	0xfc6f0000,	0xfc7f8000,	"r,I",		4 },
+{ "di", 	0xfc010000,	0xfc07ffff,	"I",		4 },
+{ "dvfd",	0xe4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "dvfw",	0xe4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "dvi",	0xc8040000,	0xfc7f0000,	"r,I",		4 },
+{ "dvmb",	0xc4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "dvmh",	0xc4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "dvmw",	0xc4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "dvr",	0x380a0000,	0xfc0f0000,	"r,R",		2 },
+{ "dvrfd",	0x380c0000,	0xfc0f0000,	"r,R",		4 },
+{ "dvrfw",	0x38040000,	0xfc0f0000,	"r,xOA,X",	4 },
+{ "eae",	0x00080000,	0xffff0000,	"",		2 },
+{ "eci",	0xfc670000,	0xfc7f8080,	"r,I",		4 },
+{ "ecwcs",	0xfc4f0000,	0xfc7f8000,	"",		4 },
+{ "ei", 	0xfc000000,	0xfc07ffff,	"I",		4 },
+{ "eomb",	0x8c080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "eomd",	0x8c000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "eomh",	0x8c000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "eomw",	0x8c000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "eor",	0x0c000000,	0xfc0f0000,	"r,R",		2 },
+{ "eorm",	0x0c080000,	0xfc0f0000,	"r,R",		2 },
+{ "es", 	0x00040000,	0xfc7f0000,	"r",		2 },
+{ "exm",	0xa8000000,	0xff880000,	"xOA,X",	4 },
+{ "exr",	0xc8070000,	0xfc7f0000,	"r",		2 },
+{ "exrr",	0xc8070002,	0xfc7f0002,	"r",		2 },
+{ "fixd",	0x380d0000,	0xfc0f0000,	"r,R",		2 },
+{ "fixw",	0x38050000,	0xfc0f0000,	"r,R",		2 },
+{ "fltd",	0x380f0000,	0xfc0f0000,	"r,R",		2 },
+{ "fltw",	0x38070000,	0xfc0f0000,	"r,R",		2 },
+{ "grio",	0xfc3f0000,	0xfc7f8000,	"r,I",		4 },
+{ "halt",	0x00000000,	0xffff0000,	"",		2 },
+{ "hio",	0xfc370000,	0xfc7f8000,	"r,I",		4 },
+{ "jwcs",	0xfa080000,	0xff880000,	"xOA,X",	4 },
+{ "la", 	0x50000000,	0xfc000000,	"r,xOA,X",	4 },
+{ "labr",	0x58080000,	0xfc080000,	"b,xOA,X",	4 },
+{ "lb", 	0xac080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lcs", 	0x00030000,	0xfc7f0000,	"r",		2 },
+{ "ld", 	0xac000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "lear", 	0x80000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lf", 	0xcc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lfbr", 	0xcc080000,	0xfc080000,	"b,xOA,X",	4 },
+{ "lh", 	0xac000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "li", 	0xc8000000,	0xfc7f0000,	"r,I",		4 },
+{ "lmap",	0x2c070000,	0xfc7f0000,	"r",		2 },
+{ "lmb",	0xb0080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lmd",	0xb0000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "lmh",	0xb0000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "lmw",	0xb0000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lnb",	0xb4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lnd",	0xb4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "lnh",	0xb4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "lnw",	0xb4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lpsd",	0xf9800000,	0xff880000,	"r,xOA,X",	4 },
+{ "lpsdcm",	0xfa800000,	0xff880000,	"r,xOA,X",	4 },
+{ "lw", 	0xac000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "lwbr", 	0x5c000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "mpfd",	0xe4080002,	0xfc080002,	"r,xOA,X",	4 },
+{ "mpfw",	0xe4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpi",	0xc8030000,	0xfc7f0000,	"r,I",		4 },
+{ "mpmb",	0xc0080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpmh",	0xc0000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "mpmw",	0xc0000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "mpr",	0x38020000,	0xfc0f0000,	"r,R",		2 },
+{ "mprfd",	0x380e0000,	0xfc0f0000,	"r,R",		2 },
+{ "mprfw",	0x38060000,	0xfc0f0000,	"r,R",		2 },
+{ "nop",	0x00020000,	0xffff0000,	"",		2 },
+{ "ormb",	0x88080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "ormd",	0x88000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "ormh",	0x88000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "ormw",	0x88000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "orr",	0x08000000,	0xfc0f0000,	"r,R",		2 },
+{ "orrm",	0x08080000,	0xfc0f0000,	"r,R",		2 },
+{ "rdsts",	0x00090000,	0xfc7f0000,	"r",		2 },
+{ "return",	0x280e0000,	0xfc7f0000,	"",		2 },
+{ "ri", 	0xfc020000,	0xfc07ffff,	"I",		4 },
+{ "rnd",	0x00050000,	0xfc7f0000,	"r",		2 },
+{ "rpswt",	0x040b0000,	0xfc7f0000,	"r",		2 },
+{ "rschnl",	0xfc2f0000,	0xfc7f8000,	"r,I",		4 },
+{ "rsctl",	0xfc470000,	0xfc7f8000,	"r,I",		4 },
+{ "rwcs",	0x000b0000,	0xfc0f0000,	"r,R",		2 },
+{ "sacz",	0x10080000,	0xfc0f0000,	"r,R",		2 },
+{ "sbm",	0x98080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "sbr",	0x18000000,	0xfc0c0000,	"r,f",		4 },
+{ "sea",	0x000d0000,	0xffff0000,	"",		2 },
+{ "setcpu",	0x2c090000,	0xfc7f0000,	"r",		2 },
+{ "sio",	0xfc170000,	0xfc7f8000,	"r,I",		4 },
+{ "sipu",	0x000a0000,	0xffff0000,	"",		2 },
+{ "sla",	0x1c400000,	0xfc600000,	"r,S",		2 },
+{ "slad",	0x20400000,	0xfc600000,	"r,S",		2 },
+{ "slc",	0x24400000,	0xfc600000,	"r,S",		2 },
+{ "sll",	0x1c600000,	0xfc600000,	"r,S",		2 },
+{ "slld",	0x20600000,	0xfc600000,	"r,S",		2 },
+{ "smc",	0x04070000,	0xfc070000,	"",		2 },
+{ "sra",	0x1c000000,	0xfc600000,	"r,S",		2 },
+{ "srad",	0x20000000,	0xfc600000,	"r,S",		2 },
+{ "src",	0x24000000,	0xfc600000,	"r,S",		2 },
+{ "srl",	0x1c200000,	0xfc600000,	"r,S",		2 },
+{ "srld",	0x20200000,	0xfc600000,	"r,S",		2 },
+{ "stb",	0xd4080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "std",	0xd4000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "stf",	0xdc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stfbr",	0x54000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "sth",	0xd4000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "stmb",	0xd8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stmd",	0xd8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "stmh",	0xd8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "stmw",	0xd8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stpio",	0xfc270000,	0xfc7f8000,	"r,I",		4 },
+{ "stw",	0xd4000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "stwbr",	0x54000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "suabr",	0x58000000,	0xfc080000,	"b,xOA,X",	4 },
+{ "sufd",	0xe0000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "sufw",	0xe0000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sui",	0xc8020000,	0xfc7f0000,	"r,I",		4 },
+{ "sumb",	0xbc080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sumd",	0xbc000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "sumh",	0xbc000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "sumw",	0xbc000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "sur",	0x3c000000,	0xfc0f0000,	"r,R",		2 },
+{ "surfd",	0x380b0000,	0xfc0f0000,	"r,xOA,X",	4 },
+{ "surfw",	0x38030000,	0xfc0f0000,	"r,R",		2 },
+{ "surm",	0x3c080000,	0xfc0f0000,	"r,R",		2 },
+{ "svc",	0xc8060000,	0xffff0000,	"",		4 },
+{ "tbm",	0xa4080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "tbr",	0x180c0000,	0xfc0c0000,	"r,f",		2 },
+{ "tbrr",	0x2c020000,	0xfc0f0000,	"r,B",		2 },
+{ "tccr",	0x28040000,	0xfc7f0000,	"",		2 },
+{ "td", 	0xfc050000,	0xfc070000,	"r,f",		4 },
+{ "tio",	0xfc1f0000,	0xfc7f8000,	"r,I",		4 },
+{ "tmapr",	0x2c0a0000,	0xfc0f0000,	"r,R",		2 },
+{ "tpcbr",	0x280c0000,	0xfc7f0000,	"r",		2 },
+{ "trbr",	0x2c010000,	0xfc0f0000,	"b,R",		2 },
+{ "trc",	0x2c030000,	0xfc0f0000,	"r,R",		2 },
+{ "trcc",	0x28050000,	0xfc7f0000,	"",		2 },
+{ "trcm",	0x2c0b0000,	0xfc0f0000,	"r,R",		2 },
+{ "trn",	0x2c040000,	0xfc0f0000,	"r,R",		2 },
+{ "trnm",	0x2c0c0000,	0xfc0f0000,	"r,R",		2 },
+{ "trr",	0x2c000000,	0xfc0f0000,	"r,R",		2 },
+{ "trrm",	0x2c080000,	0xfc0f0000,	"r,R",		2 },
+{ "trsc",	0x2c0e0000,	0xfc0f0000,	"r,R",		2 },
+{ "trsw",	0x28000000,	0xfc7f0000,	"r",		2 },
+{ "tscr",	0x2c0f0000,	0xfc0f0000,	"r,R",		2 },
+{ "uei",	0x00070000,	0xffff0000,	"",		2 },
+{ "wait",	0x00010000,	0xffff0000,	"",		2 },
+{ "wcwcs",	0xfc5f0000,	0xfc7f8000,	"",		4 },
+{ "wwcs",	0x000c0000,	0xfc0f0000,	"r,R",		2 },
+{ "xcbr",	0x28020000,	0xfc0f0000,	"b,B",		2 },
+{ "xcr",	0x2c050000,	0xfc0f0000,	"r,R",		2 },
+{ "xcrm",	0x2c0d0000,	0xfc0f0000,	"r,R",		2 },
+{ "zbm",	0x9c080000,	0xfc080000,	"f,xOA,X",	4 },
+{ "zbr",	0x18040000,	0xfc0c0000,	"r,f",		2 },
+{ "zmb",	0xf8080000,	0xfc080000,	"r,xOA,X",	4 },
+{ "zmd",	0xf8000002,	0xfc080002,	"r,xOA,X",	4 },
+{ "zmh",	0xf8000001,	0xfc080001,	"r,xOA,X",	4 },
+{ "zmw",	0xf8000000,	0xfc080000,	"r,xOA,X",	4 },
+{ "zr", 	0x0c000000,	0xfc0f0000,	"r",		2 },
+};
+
+int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]);
+
+struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) /
+		sizeof(gld_opcodes[0]);
diff --git a/binutils-2.25/include/opcode/ppc.h b/binutils-2.25/include/opcode/ppc.h
new file mode 100644
index 00000000..df971302
--- /dev/null
+++ b/binutils-2.25/include/opcode/ppc.h
@@ -0,0 +1,413 @@
+/* ppc.h -- Header file for PowerPC opcode table
+   Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
+   2007, 2008, 2009, 2010, 2012 Free Software Foundation, Inc.
+   Written by Ian Lance Taylor, Cygnus Support
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef PPC_H
+#define PPC_H
+
+#include "bfd_stdint.h"
+
+typedef uint64_t ppc_cpu_t;
+
+/* The opcode table is an array of struct powerpc_opcode.  */
+
+struct powerpc_opcode
+{
+  /* The opcode name.  */
+  const char *name;
+
+  /* The opcode itself.  Those bits which will be filled in with
+     operands are zeroes.  */
+  unsigned long opcode;
+
+  /* The opcode mask.  This is used by the disassembler.  This is a
+     mask containing ones indicating those bits which must match the
+     opcode field, and zeroes indicating those bits which need not
+     match (and are presumably filled in by operands).  */
+  unsigned long mask;
+
+  /* One bit flags for the opcode.  These are used to indicate which
+     specific processors support the instructions.  The defined values
+     are listed below.  */
+  ppc_cpu_t flags;
+
+  /* One bit flags for the opcode.  These are used to indicate which
+     specific processors no longer support the instructions.  The defined
+     values are listed below.  */
+  ppc_cpu_t deprecated;
+
+  /* An array of operand codes.  Each code is an index into the
+     operand table.  They appear in the order which the operands must
+     appear in assembly code, and are terminated by a zero.  */
+  unsigned char operands[8];
+};
+
+/* The table itself is sorted by major opcode number, and is otherwise
+   in the order in which the disassembler should consider
+   instructions.  */
+extern const struct powerpc_opcode powerpc_opcodes[];
+extern const int powerpc_num_opcodes;
+extern const struct powerpc_opcode vle_opcodes[];
+extern const int vle_num_opcodes;
+
+/* Values defined for the flags field of a struct powerpc_opcode.  */
+
+/* Opcode is defined for the PowerPC architecture.  */
+#define PPC_OPCODE_PPC			 1
+
+/* Opcode is defined for the POWER (RS/6000) architecture.  */
+#define PPC_OPCODE_POWER		 2
+
+/* Opcode is defined for the POWER2 (Rios 2) architecture.  */
+#define PPC_OPCODE_POWER2		 4
+
+/* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
+   is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
+   but it also supports many additional POWER instructions.  */
+#define PPC_OPCODE_601			 8
+
+/* Opcode is supported in both the Power and PowerPC architectures
+   (ie, compiler's -mcpu=common or assembler's -mcom).  More than just
+   the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
+   and PPC_OPCODE_POWER2 because many instructions changed mnemonics
+   between POWER and POWERPC.  */
+#define PPC_OPCODE_COMMON	      0x10
+
+/* Opcode is supported for any Power or PowerPC platform (this is
+   for the assembler's -many option, and it eliminates duplicates).  */
+#define PPC_OPCODE_ANY		      0x20
+
+/* Opcode is only defined on 64 bit architectures.  */
+#define PPC_OPCODE_64		      0x40
+
+/* Opcode is supported as part of the 64-bit bridge.  */
+#define PPC_OPCODE_64_BRIDGE	      0x80
+
+/* Opcode is supported by Altivec Vector Unit */
+#define PPC_OPCODE_ALTIVEC	     0x100
+
+/* Opcode is supported by PowerPC 403 processor.  */
+#define PPC_OPCODE_403		     0x200
+
+/* Opcode is supported by PowerPC BookE processor.  */
+#define PPC_OPCODE_BOOKE	     0x400
+
+/* Opcode is supported by PowerPC 440 processor.  */
+#define PPC_OPCODE_440		     0x800
+
+/* Opcode is only supported by Power4 architecture.  */
+#define PPC_OPCODE_POWER4	    0x1000
+
+/* Opcode is only supported by Power7 architecture.  */
+#define PPC_OPCODE_POWER7	    0x2000
+
+/* Opcode is only supported by e500x2 Core.  */
+#define PPC_OPCODE_SPE		    0x4000
+
+/* Opcode is supported by e500x2 Integer select APU.  */
+#define PPC_OPCODE_ISEL		    0x8000
+
+/* Opcode is an e500 SPE floating point instruction.  */
+#define PPC_OPCODE_EFS		   0x10000
+
+/* Opcode is supported by branch locking APU.  */
+#define PPC_OPCODE_BRLOCK	   0x20000
+
+/* Opcode is supported by performance monitor APU.  */
+#define PPC_OPCODE_PMR		   0x40000
+
+/* Opcode is supported by cache locking APU.  */
+#define PPC_OPCODE_CACHELCK	   0x80000
+
+/* Opcode is supported by machine check APU.  */
+#define PPC_OPCODE_RFMCI	  0x100000
+
+/* Opcode is only supported by Power5 architecture.  */
+#define PPC_OPCODE_POWER5	  0x200000
+
+/* Opcode is supported by PowerPC e300 family.  */
+#define PPC_OPCODE_E300           0x400000
+
+/* Opcode is only supported by Power6 architecture.  */
+#define PPC_OPCODE_POWER6	  0x800000
+
+/* Opcode is only supported by PowerPC Cell family.  */
+#define PPC_OPCODE_CELL		 0x1000000
+
+/* Opcode is supported by CPUs with paired singles support.  */
+#define PPC_OPCODE_PPCPS	 0x2000000
+
+/* Opcode is supported by Power E500MC */
+#define PPC_OPCODE_E500MC        0x4000000
+
+/* Opcode is supported by PowerPC 405 processor.  */
+#define PPC_OPCODE_405		 0x8000000
+
+/* Opcode is supported by Vector-Scalar (VSX) Unit */
+#define PPC_OPCODE_VSX		0x10000000
+
+/* Opcode is supported by A2.  */
+#define PPC_OPCODE_A2	 	0x20000000
+
+/* Opcode is supported by PowerPC 476 processor.  */
+#define PPC_OPCODE_476		0x40000000
+
+/* Opcode is supported by AppliedMicro Titan core */
+#define PPC_OPCODE_TITAN        0x80000000
+
+/* Opcode which is supported by the e500 family */
+#define PPC_OPCODE_E500	       0x100000000ull
+
+/* Opcode is supported by Extended Altivec Vector Unit */
+#define PPC_OPCODE_ALTIVEC2    0x200000000ull
+
+/* Opcode is supported by Power E6500 */
+#define PPC_OPCODE_E6500       0x400000000ull
+
+/* Opcode is supported by Thread management APU */
+#define PPC_OPCODE_TMR         0x800000000ull
+
+/* Opcode which is supported by the VLE extension.  */
+#define PPC_OPCODE_VLE	      0x1000000000ull
+
+/* Opcode is only supported by Power8 architecture.  */
+#define PPC_OPCODE_POWER8     0x2000000000ull
+
+/* Opcode which is supported by the Hardware Transactional Memory extension.  */
+/* Currently, this is the same as the POWER8 mask.  If another cpu comes out
+   that isn't a superset of POWER8, we can define this to its own mask.  */
+#define PPC_OPCODE_HTM        PPC_OPCODE_POWER8
+
+/* A macro to extract the major opcode from an instruction.  */
+#define PPC_OP(i) (((i) >> 26) & 0x3f)
+
+/* A macro to determine if the instruction is a 2-byte VLE insn.  */
+#define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
+
+/* A macro to extract the major opcode from a VLE instruction.  */
+#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
+
+/* A macro to convert a VLE opcode to a VLE opcode segment.  */
+#define VLE_OP_TO_SEG(i) ((i) >> 1)
+
+/* The operands table is an array of struct powerpc_operand.  */
+
+struct powerpc_operand
+{
+  /* A bitmask of bits in the operand.  */
+  unsigned int bitm;
+
+  /* The shift operation to be applied to the operand.  No shift
+     is made if this is zero.  For positive values, the operand
+     is shifted left by SHIFT.  For negative values, the operand
+     is shifted right by -SHIFT.  Use PPC_OPSHIFT_INV to indicate
+     that BITM and SHIFT cannot be used to determine where the
+     operand goes in the insn.  */
+  int shift;
+
+  /* Insertion function.  This is used by the assembler.  To insert an
+     operand value into an instruction, check this field.
+
+     If it is NULL, execute
+	 if (o->shift >= 0)
+	   i |= (op & o->bitm) << o->shift;
+	 else
+	   i |= (op & o->bitm) >> -o->shift;
+     (i is the instruction which we are filling in, o is a pointer to
+     this structure, and op is the operand value).
+
+     If this field is not NULL, then simply call it with the
+     instruction and the operand value.  It will return the new value
+     of the instruction.  If the ERRMSG argument is not NULL, then if
+     the operand value is illegal, *ERRMSG will be set to a warning
+     string (the operand will be inserted in any case).  If the
+     operand value is legal, *ERRMSG will be unchanged (most operands
+     can accept any value).  */
+  unsigned long (*insert)
+    (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
+
+  /* Extraction function.  This is used by the disassembler.  To
+     extract this operand type from an instruction, check this field.
+
+     If it is NULL, compute
+	 if (o->shift >= 0)
+	   op = (i >> o->shift) & o->bitm;
+	 else
+	   op = (i << -o->shift) & o->bitm;
+	 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
+	   sign_extend (op);
+     (i is the instruction, o is a pointer to this structure, and op
+     is the result).
+
+     If this field is not NULL, then simply call it with the
+     instruction value.  It will return the value of the operand.  If
+     the INVALID argument is not NULL, *INVALID will be set to
+     non-zero if this operand type can not actually be extracted from
+     this operand (i.e., the instruction does not match).  If the
+     operand is valid, *INVALID will not be changed.  */
+  long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
+
+  /* One bit syntax flags.  */
+  unsigned long flags;
+};
+
+/* Elements in the table are retrieved by indexing with values from
+   the operands field of the powerpc_opcodes table.  */
+
+extern const struct powerpc_operand powerpc_operands[];
+extern const unsigned int num_powerpc_operands;
+
+/* Use with the shift field of a struct powerpc_operand to indicate
+     that BITM and SHIFT cannot be used to determine where the operand
+     goes in the insn.  */
+#define PPC_OPSHIFT_INV (-1 << 31)
+
+/* Values defined for the flags field of a struct powerpc_operand.  */
+
+/* This operand takes signed values.  */
+#define PPC_OPERAND_SIGNED (0x1)
+
+/* This operand takes signed values, but also accepts a full positive
+   range of values when running in 32 bit mode.  That is, if bits is
+   16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
+   this flag is ignored.  */
+#define PPC_OPERAND_SIGNOPT (0x2)
+
+/* This operand does not actually exist in the assembler input.  This
+   is used to support extended mnemonics such as mr, for which two
+   operands fields are identical.  The assembler should call the
+   insert function with any op value.  The disassembler should call
+   the extract function, ignore the return value, and check the value
+   placed in the valid argument.  */
+#define PPC_OPERAND_FAKE (0x4)
+
+/* The next operand should be wrapped in parentheses rather than
+   separated from this one by a comma.  This is used for the load and
+   store instructions which want their operands to look like
+       reg,displacement(reg)
+   */
+#define PPC_OPERAND_PARENS (0x8)
+
+/* This operand may use the symbolic names for the CR fields, which
+   are
+       lt  0	gt  1	eq  2	so  3	un  3
+       cr0 0	cr1 1	cr2 2	cr3 3
+       cr4 4	cr5 5	cr6 6	cr7 7
+   These may be combined arithmetically, as in cr2*4+gt.  These are
+   only supported on the PowerPC, not the POWER.  */
+#define PPC_OPERAND_CR_BIT (0x10)
+
+/* This operand names a register.  The disassembler uses this to print
+   register names with a leading 'r'.  */
+#define PPC_OPERAND_GPR (0x20)
+
+/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
+#define PPC_OPERAND_GPR_0 (0x40)
+
+/* This operand names a floating point register.  The disassembler
+   prints these with a leading 'f'.  */
+#define PPC_OPERAND_FPR (0x80)
+
+/* This operand is a relative branch displacement.  The disassembler
+   prints these symbolically if possible.  */
+#define PPC_OPERAND_RELATIVE (0x100)
+
+/* This operand is an absolute branch address.  The disassembler
+   prints these symbolically if possible.  */
+#define PPC_OPERAND_ABSOLUTE (0x200)
+
+/* This operand is optional, and is zero if omitted.  This is used for
+   example, in the optional BF field in the comparison instructions.  The
+   assembler must count the number of operands remaining on the line,
+   and the number of operands remaining for the opcode, and decide
+   whether this operand is present or not.  The disassembler should
+   print this operand out only if it is not zero.  */
+#define PPC_OPERAND_OPTIONAL (0x400)
+
+/* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
+   is omitted, then for the next operand use this operand value plus
+   1, ignoring the next operand field for the opcode.  This wretched
+   hack is needed because the Power rotate instructions can take
+   either 4 or 5 operands.  The disassembler should print this operand
+   out regardless of the PPC_OPERAND_OPTIONAL field.  */
+#define PPC_OPERAND_NEXT (0x800)
+
+/* This operand should be regarded as a negative number for the
+   purposes of overflow checking (i.e., the normal most negative
+   number is disallowed and one more than the normal most positive
+   number is allowed).  This flag will only be set for a signed
+   operand.  */
+#define PPC_OPERAND_NEGATIVE (0x1000)
+
+/* This operand names a vector unit register.  The disassembler
+   prints these with a leading 'v'.  */
+#define PPC_OPERAND_VR (0x2000)
+
+/* This operand is for the DS field in a DS form instruction.  */
+#define PPC_OPERAND_DS (0x4000)
+
+/* This operand is for the DQ field in a DQ form instruction.  */
+#define PPC_OPERAND_DQ (0x8000)
+
+/* Valid range of operand is 0..n rather than 0..n-1.  */
+#define PPC_OPERAND_PLUS1 (0x10000)
+
+/* Xilinx APU and FSL related operands */
+#define PPC_OPERAND_FSL (0x20000)
+#define PPC_OPERAND_FCR (0x40000)
+#define PPC_OPERAND_UDI (0x80000)
+
+/* This operand names a vector-scalar unit register.  The disassembler
+   prints these with a leading 'vs'.  */
+#define PPC_OPERAND_VSR (0x100000)
+
+/* This is a CR FIELD that does not use symbolic names.  */
+#define PPC_OPERAND_CR_REG (0x200000)
+
+/* The POWER and PowerPC assemblers use a few macros.  We keep them
+   with the operands table for simplicity.  The macro table is an
+   array of struct powerpc_macro.  */
+
+struct powerpc_macro
+{
+  /* The macro name.  */
+  const char *name;
+
+  /* The number of operands the macro takes.  */
+  unsigned int operands;
+
+  /* One bit flags for the opcode.  These are used to indicate which
+     specific processors support the instructions.  The values are the
+     same as those for the struct powerpc_opcode flags field.  */
+  ppc_cpu_t flags;
+
+  /* A format string to turn the macro into a normal instruction.
+     Each %N in the string is replaced with operand number N (zero
+     based).  */
+  const char *format;
+};
+
+extern const struct powerpc_macro powerpc_macros[];
+extern const int powerpc_num_macros;
+
+extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
+
+#endif /* PPC_H */
diff --git a/binutils-2.25/include/opcode/pyr.h b/binutils-2.25/include/opcode/pyr.h
new file mode 100644
index 00000000..2fffd946
--- /dev/null
+++ b/binutils-2.25/include/opcode/pyr.h
@@ -0,0 +1,305 @@
+/* pyramid.opcode.h -- gdb initial attempt.
+
+   Copyright 2001, 2010 Free Software Foundation, Inc.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+   
+/* pyramid opcode table: wot to do with this
+   particular opcode */
+
+struct pyr_datum
+{
+  char              nargs;
+  char *            args;	/* how to compile said opcode */
+  unsigned long     mask;	/* Bit vector: which operand modes are valid
+				   for this opcode */
+  unsigned char     code;	/* op-code (always 6(?) bits */
+};
+
+typedef struct pyr_insn_format
+{
+    unsigned int mode :4;
+    unsigned int operator :8;
+    unsigned int index_scale :2;
+    unsigned int index_reg :6;
+    unsigned int operand_1 :6;
+    unsigned int operand_2:6;
+} pyr_insn_format;
+	
+
+/* We store four bytes of opcode for all opcodes.
+   Pyramid is sufficiently RISCy that:
+      - insns are always an integral number of words;
+      - the length of any insn can be told from the first word of
+        the insn. (ie, if there are zero, one, or two words of
+	immediate operand/offset).
+
+   
+   The args component is a string containing two characters for each
+   operand of the instruction.  The first specifies the kind of operand;
+   the second, the place it is stored. */
+
+/* Kinds of operands:
+   mask	 assembler syntax	description
+   0x0001:  movw Rn,Rn		register to register
+   0x0002:  movw K,Rn		quick immediate to register
+   0x0004:  movw I,Rn		long immediate to register
+   0x0008:  movw (Rn),Rn	register indirect to register
+   	    movw (Rn)[x],Rn	register indirect to register
+   0x0010:  movw I(Rn),Rn	offset register indirect to register
+   	    movw I(Rn)[x],Rn	offset register indirect, indexed, to register
+
+   0x0020:  movw Rn,(Rn)	register to register indirect                
+   0x0040:  movw K,(Rn)		quick immediate to register indirect         
+   0x0080:  movw I,(Rn)		long immediate to register indirect          
+   0x0100:  movw (Rn),(Rn)	register indirect to-register indirect       
+   0x0100:  movw (Rn),(Rn)	register indirect to-register indirect       
+   0x0200:  movw I(Rn),(Rn)	register indirect+offset to register indirect
+   0x0200:  movw I(Rn),(Rn)	register indirect+offset to register indirect
+
+   0x0400:  movw Rn,I(Rn)	register to register indirect+offset
+   0x0800:  movw K,I(Rn)	quick immediate to register indirect+offset
+   0x1000:  movw I,I(Rn)	long immediate to register indirect+offset
+   0x1000:  movw (Rn),I(Rn)	register indirect to-register indirect+offset
+   0x1000:  movw I(Rn),I(Rn)	register indirect+offset to register indirect
+   					+offset
+   0x0000:  (irregular)		???
+   
+
+   Each insn has a four-bit field encoding the type(s) of its operands.
+*/
+
+/* Some common combinations
+   */
+
+/* the first 5,(0x1|0x2|0x4|0x8|0x10) ie (1|2|4|8|16), ie ( 32 -1)*/
+#define GEN_TO_REG (31)
+
+#define	UNKNOWN ((unsigned long)-1)
+#define ANY (GEN_TO_REG | (GEN_TO_REG << 5) | (GEN_TO_REG << 15))
+
+#define CONVERT (1|8|0x10|0x20|0x200)
+
+#define K_TO_REG (2)
+#define I_TO_REG (4)
+#define NOTK_TO_REG (GEN_TO_REG & ~K_TO_REG)
+#define NOTI_TO_REG (GEN_TO_REG & ~I_TO_REG)
+
+/* The assembler requires that this array be sorted as follows:
+   all instances of the same mnemonic must be consecutive.
+   All instances of the same mnemonic with the same number of operands
+   must be consecutive.
+ */
+
+struct pyr_opcode		/* pyr opcode text */
+{
+  char *            name;	/* opcode name: lowercase string  [key]  */
+  struct pyr_datum  datum;	/* rest of opcode table          [datum] */
+};
+
+#define pyr_how args
+#define pyr_nargs nargs
+#define pyr_mask mask
+#define pyr_name name
+
+struct pyr_opcode pyr_opcodes[] =
+{
+  {"movb",	{ 2, "", UNKNOWN,		0x11}, },
+  {"movh",	{ 2, "", UNKNOWN,		0x12} },
+  {"movw",	{ 2, "", ANY,			0x10} },
+  {"movl",	{ 2, "", ANY,			0x13} },
+  {"mnegw",	{ 2, "", (0x1|0x8|0x10),	0x14} },
+  {"mnegf",	{ 2, "", 0x1,			0x15} },
+  {"mnegd",	{ 2, "", 0x1,			0x16} },
+  {"mcomw",	{ 2, "", (0x1|0x8|0x10),	0x17} },
+  {"mabsw",	{ 2, "", (0x1|0x8|0x10),	0x18} },
+  {"mabsf",	{ 2, "", 0x1,			0x19} },
+  {"mabsd",	{ 2, "", 0x1,			0x1a} },
+  {"mtstw",	{ 2, "", (0x1|0x8|0x10),	0x1c} },
+  {"mtstf",	{ 2, "", 0x1,			0x1d} },
+  {"mtstd",	{ 2, "", 0x1,			0x1e} },
+  {"mova",	{ 2, "", 0x8|0x10,		0x1f} },
+  {"movzbw",	{ 2, "", (0x1|0x8|0x10),	0x20} },
+  {"movzhw",	{ 2, "", (0x1|0x8|0x10),	0x21} },
+				/* 2 insns out of order here */
+  {"movbl",	{ 2, "", 1,			0x4f} },
+  {"filbl",	{ 2, "", 1,			0x4e} },
+
+  {"cvtbw",	{ 2, "", CONVERT,		0x22} },
+  {"cvthw",	{ 2, "", CONVERT,		0x23} },
+  {"cvtwb",	{ 2, "", CONVERT,		0x24} },
+  {"cvtwh",	{ 2, "", CONVERT,		0x25} },
+  {"cvtwf",	{ 2, "", CONVERT,		0x26} },
+  {"cvtwd",	{ 2, "", CONVERT,		0x27} },
+  {"cvtfw",	{ 2, "", CONVERT,		0x28} },
+  {"cvtfd",	{ 2, "", CONVERT,		0x29} },
+  {"cvtdw",	{ 2, "", CONVERT,		0x2a} },
+  {"cvtdf",	{ 2, "", CONVERT,		0x2b} },
+
+  {"addw",	{ 2, "", GEN_TO_REG,		0x40} },
+  {"addwc",	{ 2, "", GEN_TO_REG,		0x41} },
+  {"subw",	{ 2, "", GEN_TO_REG,		0x42} },
+  {"subwb",	{ 2, "", GEN_TO_REG,		0x43} },
+  {"rsubw",	{ 2, "", GEN_TO_REG,		0x44} },
+  {"mulw",	{ 2, "", GEN_TO_REG,		0x45} },
+  {"emul",	{ 2, "", GEN_TO_REG,		0x47} },
+  {"umulw",	{ 2, "", GEN_TO_REG,		0x46} },
+  {"divw",	{ 2, "", GEN_TO_REG,		0x48} },
+  {"ediv",	{ 2, "", GEN_TO_REG,		0x4a} },
+  {"rdivw",	{ 2, "", GEN_TO_REG,		0x4b} },
+  {"udivw",	{ 2, "", GEN_TO_REG,		0x49} },
+  {"modw",	{ 2, "", GEN_TO_REG,		0x4c} },
+  {"umodw",	{ 2, "", GEN_TO_REG,		0x4d} },
+
+
+  {"addf",	{ 2, "", 1,			0x50} },
+  {"addd",	{ 2, "", 1,			0x51} },
+  {"subf",	{ 2, "", 1,			0x52} },
+  {"subd",	{ 2, "", 1,			0x53} },
+  {"mulf",	{ 2, "", 1,			0x56} },
+  {"muld",	{ 2, "", 1,			0x57} },
+  {"divf",	{ 2, "", 1,			0x58} },
+  {"divd",	{ 2, "", 1,			0x59} },
+
+
+  {"cmpb",	{ 2, "", UNKNOWN,		0x61} },
+  {"cmph",	{ 2, "", UNKNOWN,		0x62} },
+  {"cmpw",	{ 2, "", UNKNOWN,		0x60} },
+  {"ucmpb",	{ 2, "", UNKNOWN,		0x66} },
+  /* WHY no "ucmph"??? */
+  {"ucmpw",	{ 2, "", UNKNOWN,		0x65} },
+  {"xchw",	{ 2, "", UNKNOWN,		0x0f} },
+
+
+  {"andw",	{ 2, "", GEN_TO_REG,		0x30} },
+  {"orw",	{ 2, "", GEN_TO_REG,		0x31} },
+  {"xorw",	{ 2, "", GEN_TO_REG,		0x32} },
+  {"bicw",	{ 2, "", GEN_TO_REG,		0x33} },
+  {"lshlw",	{ 2, "", GEN_TO_REG,		0x38} },
+  {"ashlw",	{ 2, "", GEN_TO_REG,		0x3a} },
+  {"ashll",	{ 2, "", GEN_TO_REG,		0x3c} },
+  {"ashrw",	{ 2, "", GEN_TO_REG,		0x3b} },
+  {"ashrl",	{ 2, "", GEN_TO_REG,		0x3d} },
+  {"rotlw",	{ 2, "", GEN_TO_REG,		0x3e} },
+  {"rotrw",	{ 2, "", GEN_TO_REG,		0x3f} },
+
+  /* push and pop insns are "going away next release". */
+  {"pushw",	{ 2, "", GEN_TO_REG,		0x0c} },
+  {"popw",	{ 2, "", (0x1|0x8|0x10),	0x0d} },
+  {"pusha",	{ 2, "", (0x8|0x10),		0x0e} },
+
+  {"bitsw",	{ 2, "", UNKNOWN,		0x35} },
+  {"bitcw",	{ 2, "", UNKNOWN,		0x36} },
+  /* some kind of ibra/dbra insns??*/
+  {"icmpw",	{ 2, "", UNKNOWN,		0x67} },
+  {"dcmpw",	{ 2, "", (1|4|0x20|0x80|0x400|0x1000),	0x69} },/*FIXME*/
+  {"acmpw",	{ 2, "", 1,			0x6b} },
+
+  /* Call is written as a 1-op insn, but is always (dis)assembled as a 2-op
+     insn with a 2nd op of tr14.   The assembler will have to grok this.  */
+  {"call",	{ 2, "", GEN_TO_REG,		0x04} },
+  {"call",	{ 1, "", GEN_TO_REG,		0x04} },
+
+  {"callk",	{ 1, "", UNKNOWN,		0x06} },/* system call?*/
+  /* Ret is usually written as a 0-op insn, but gets disassembled as a
+     1-op insn. The operand is always tr15. */
+  {"ret",	{ 0, "", UNKNOWN,		0x09} },
+  {"ret",	{ 1, "", UNKNOWN,		0x09} },
+  {"adsf",	{ 2, "", (1|2|4),		0x08} },
+  {"retd",	{ 2, "", UNKNOWN,		0x0a} },
+  {"btc",	{ 2, "", UNKNOWN,		0x01} },
+  {"bfc",	{ 2, "", UNKNOWN,		0x02} },
+  /* Careful: halt is 0x00000000. Jump must have some other (mode?)bit set?? */
+  {"jump",	{ 1, "", UNKNOWN,		0x00} },
+  {"btp",	{ 2, "", UNKNOWN,		0xf00} },
+  /* read control-stack pointer is another 1-or-2 operand insn. */
+  {"rcsp",	{ 2, "", UNKNOWN,		0x01f} },
+  {"rcsp",	{ 1, "", UNKNOWN,		0x01f} }
+};
+
+/* end: pyramid.opcode.h */
+/* One day I will have to take the time to find out what operands
+   are valid for these insns, and guess at what they mean.
+
+   I can't imagine what the "I???" insns (iglob, etc) do.
+
+   the arithmetic-sounding insns ending in "p" sound awfully like BCD
+   arithmetic insns:
+   	dshlp -> Decimal SHift Left Packed
+	dshrp -> Decimal SHift Right Packed
+   and cvtlp would be convert long to packed.
+   I have no idea how the operands are interpreted; but having them be
+   a long register with (address, length) of an in-memory packed BCD operand
+   would not be surprising.
+   They are unlikely to be a packed bcd string: 64 bits of long give
+   is only 15 digits+sign, which isn't enough for COBOL.
+ */ 
+#if 0
+  {"wcsp",	{ 2, "", UNKNOWN,		0x00} }, /*write csp?*/
+  /* The OSx Operating System Porting Guide claims SSL does things
+     with tr12 (a register reserved to it) to do with static block-structure
+     references.  SSL=Set Static Link?  It's "Going away next release". */
+  {"ssl",	{ 2, "", UNKNOWN,		0x00} },
+  {"ccmps",	{ 2, "", UNKNOWN,		0x00} },
+  {"lcd",	{ 2, "", UNKNOWN,		0x00} },
+  {"uemul",	{ 2, "", UNKNOWN,		0x00} }, /*unsigned emul*/
+  {"srf",	{ 2, "", UNKNOWN,		0x00} }, /*Gidget time???*/
+  {"mnegp",	{ 2, "", UNKNOWN,		0x00} }, /move-neg phys?*/
+  {"ldp",	{ 2, "", UNKNOWN,		0x00} }, /*load phys?*/
+  {"ldti",	{ 2, "", UNKNOWN,		0x00} },
+  {"ldb",	{ 2, "", UNKNOWN,		0x00} },
+  {"stp",	{ 2, "", UNKNOWN,		0x00} },
+  {"stti",	{ 2, "", UNKNOWN,		0x00} },
+  {"stb",	{ 2, "", UNKNOWN,		0x00} },
+  {"stu",	{ 2, "", UNKNOWN,		0x00} },
+  {"addp",	{ 2, "", UNKNOWN,		0x00} },
+  {"subp",	{ 2, "", UNKNOWN,		0x00} },
+  {"mulp",	{ 2, "", UNKNOWN,		0x00} },
+  {"divp",	{ 2, "", UNKNOWN,		0x00} },
+  {"dshlp",	{ 2, "", UNKNOWN,		0x00} },  /* dec shl packed? */
+  {"dshrp",	{ 2, "", UNKNOWN,		0x00} }, /* dec shr packed? */
+  {"movs",	{ 2, "", UNKNOWN,		0x00} }, /*move (string?)?*/
+  {"cmpp",	{ 2, "", UNKNOWN,		0x00} }, /* cmp phys?*/
+  {"cmps",	{ 2, "", UNKNOWN,		0x00} }, /* cmp (string?)?*/
+  {"cvtlp",	{ 2, "", UNKNOWN,		0x00} }, /* cvt long to p??*/
+  {"cvtpl",	{ 2, "", UNKNOWN,		0x00} }, /* cvt p to l??*/
+  {"dintr",	{ 2, "", UNKNOWN,		0x00} }, /* ?? intr ?*/
+  {"rphysw",	{ 2, "", UNKNOWN,		0x00} }, /* read phys word?*/
+  {"wphysw",	{ 2, "", UNKNOWN,		0x00} }, /* write phys word?*/
+  {"cmovs",	{ 2, "", UNKNOWN,		0x00} },
+  {"rsubw",	{ 2, "", UNKNOWN,		0x00} },
+  {"bicpsw",	{ 2, "", UNKNOWN,		0x00} }, /* clr bit in psw? */
+  {"bispsw",	{ 2, "", UNKNOWN,		0x00} }, /* set bit in psw? */
+  {"eio",	{ 2, "", UNKNOWN,		0x00} }, /* ?? ?io ? */
+  {"callp",	{ 2, "", UNKNOWN,		0x00} }, /* call phys?*/
+  {"callr",	{ 2, "", UNKNOWN,		0x00} },
+  {"lpcxt",	{ 2, "", UNKNOWN,		0x00} }, /*load proc context*/
+  {"rei",	{ 2, "", UNKNOWN,		0x00} }, /*ret from intrpt*/
+  {"rport",	{ 2, "", UNKNOWN,		0x00} }, /*read-port?*/
+  {"rtod",	{ 2, "", UNKNOWN,		0x00} }, /*read-time-of-day?*/
+  {"ssi",	{ 2, "", UNKNOWN,		0x00} },
+  {"vtpa",	{ 2, "", UNKNOWN,		0x00} }, /*virt-to-phys-addr?*/
+  {"wicl",	{ 2, "", UNKNOWN,		0x00} }, /* write icl ? */
+  {"wport",	{ 2, "", UNKNOWN,		0x00} }, /*write-port?*/
+  {"wtod",	{ 2, "", UNKNOWN,		0x00} }, /*write-time-of-day?*/
+  {"flic",	{ 2, "", UNKNOWN,		0x00} },
+  {"iglob",	{ 2, "", UNKNOWN,		0x00} }, /* I global? */
+  {"iphys",	{ 2, "", UNKNOWN,		0x00} }, /* I physical? */
+  {"ipid",	{ 2, "", UNKNOWN,		0x00} }, /* I pid? */
+  {"ivect",	{ 2, "", UNKNOWN,		0x00} }, /* I vector? */
+  {"lamst",	{ 2, "", UNKNOWN,		0x00} },
+  {"tio",	{ 2, "", UNKNOWN,		0x00} },
+#endif
diff --git a/binutils-2.25/include/opcode/rl78.h b/binutils-2.25/include/opcode/rl78.h
new file mode 100644
index 00000000..0f3c64d6
--- /dev/null
+++ b/binutils-2.25/include/opcode/rl78.h
@@ -0,0 +1,168 @@
+/* Opcode decoder for the Renesas RL78
+   Copyright 2011
+   Free Software Foundation, Inc.
+   Written by DJ Delorie <dj@redhat.com>
+
+   This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+/* The RL78 decoder in libopcodes is used by the simulator, gdb's
+   analyzer, and the disassembler.  Given an opcode data source, it
+   decodes the next opcode into the following structures.  */
+
+#ifndef RL78_OPCODES_H_INCLUDED
+#define RL78_OPCODES_H_INCLUDED
+
+/* For the purposes of these structures, the RL78 registers are as
+   follows, despite most of these being memory-mapped and
+   bank-switched:  */
+typedef enum {
+  RL78_Reg_None,
+  /* The order of these matches the encodings.  */
+  RL78_Reg_X,
+  RL78_Reg_A,
+  RL78_Reg_C,
+  RL78_Reg_B,
+  RL78_Reg_E,
+  RL78_Reg_D,
+  RL78_Reg_L,
+  RL78_Reg_H,
+  /* The order of these matches the encodings.  */
+  RL78_Reg_AX,
+  RL78_Reg_BC,
+  RL78_Reg_DE,
+  RL78_Reg_HL,
+  /* Unordered.  */
+  RL78_Reg_SP,
+  RL78_Reg_PSW,
+  RL78_Reg_CS,
+  RL78_Reg_ES,
+  RL78_Reg_PMC,
+  RL78_Reg_MEM
+} RL78_Register;
+
+typedef enum
+{
+  RL78_Byte = 0,
+  RL78_Word
+} RL78_Size;
+
+typedef enum {
+  RL78_Condition_T,
+  RL78_Condition_F,
+  RL78_Condition_C,
+  RL78_Condition_NC,
+  RL78_Condition_H,
+  RL78_Condition_NH,
+  RL78_Condition_Z,
+  RL78_Condition_NZ
+} RL78_Condition;
+
+typedef enum {
+  RL78_Operand_None = 0,
+  RL78_Operand_Immediate,	/* #addend */
+  RL78_Operand_Register,	/* reg */
+  RL78_Operand_Indirect,	/* [reg + reg2 + addend] */
+  RL78_Operand_Bit,		/* reg.bit */
+  RL78_Operand_BitIndirect,	/* [reg+reg2+addend].bit */
+  RL78_Operand_PreDec,		/* [--reg] = push */
+  RL78_Operand_PostInc		/* [reg++] = pop */
+} RL78_Operand_Type;
+
+typedef enum
+{
+  RLO_unknown,
+  RLO_add,			/* d += s */
+  RLO_addc,			/* d += s + CY */
+  RLO_and,			/* d &= s (byte, word, bit) */
+  RLO_branch,			/* pc = d */
+  RLO_branch_cond,		/* pc = d if cond(src) */
+  RLO_branch_cond_clear,	/* pc = d if cond(src), and clear(src) */
+  RLO_break,			/* BRK */
+  RLO_call,			/* call */
+  RLO_cmp,			/* cmp d, s */
+  RLO_divhu,			/* DIVHU */
+  RLO_divwu,			/* DIVWU */
+  RLO_halt,			/* HALT */
+  RLO_mov,			/* d = s */
+  RLO_mach,			/* MACH */
+  RLO_machu,			/* MACHU */
+  RLO_mulu,			/* MULU */
+  RLO_mulh,			/* MULH */
+  RLO_mulhu,			/* MULHU */
+  RLO_nop,			/* NOP */
+  RLO_or,			/* d |= s */
+  RLO_ret,			/* RET */
+  RLO_reti,			/* RETI */
+  RLO_rol,			/* d <<= s, MSB to LSB and CY */
+  RLO_rolc,			/* d <<= s, MSB to CY, CY, to LSB */
+  RLO_ror,			/* d >>= s, LSB to MSB and CY */
+  RLO_rorc,			/* d >>= s, LSB to CY, CY, to MSB */
+  RLO_sar,			/* d >>= s, signed */
+  RLO_sel,			/* rb = s */
+  RLO_shr,			/* d >>= s, unsigned */
+  RLO_shl,			/* d <<= s */
+  RLO_skip,			/* skip next insn is cond(s) */
+  RLO_stop,			/* STOP */
+  RLO_sub,			/* d -= s */
+  RLO_subc,			/* d -= s - CY */
+  RLO_xch,			/* swap d, s  */
+  RLO_xor,			/* d ^= s */
+} RL78_Opcode_ID;
+
+typedef struct {
+  RL78_Operand_Type  type;
+  int              addend;
+  RL78_Register	   reg : 8;
+  RL78_Register	   reg2 : 8;
+  unsigned char	   bit_number : 4;
+  unsigned char	   condition : 3;
+  unsigned char	   use_es : 1;
+} RL78_Opcode_Operand;
+
+/* PSW flag bits */
+#define RL78_PSW_IE	0x80
+#define RL78_PSW_Z	0x40
+#define RL78_PSW_RBS1	0x20
+#define RL78_PSW_AC	0x10
+#define	RL78_PSW_RBS0	0x08
+#define	RL78_PSW_ISP1	0x04
+#define	RL78_PSW_ISP0	0x02
+#define RL78_PSW_CY	0x01
+
+#define	RL78_SFR_SP	0xffff8
+#define	RL78_SFR_PSW	0xffffa
+#define	RL78_SFR_CS	0xffffc
+#define	RL78_SFR_ES	0xffffd
+#define	RL78_SFR_PMC	0xffffe
+#define	RL78_SFR_MEM	0xfffff
+
+typedef struct
+{
+  int lineno;
+  RL78_Opcode_ID	id:24;
+  unsigned		flags:8; /* PSW mask, for side effects only */
+  int			n_bytes;
+  char *		syntax;
+  RL78_Size		size;
+  /* By convention, these are destination, source.  */
+  RL78_Opcode_Operand	op[2];
+} RL78_Opcode_Decoded;
+
+int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *);
+
+#endif
diff --git a/binutils-2.25/include/opcode/rx.h b/binutils-2.25/include/opcode/rx.h
new file mode 100644
index 00000000..aa85fe4a
--- /dev/null
+++ b/binutils-2.25/include/opcode/rx.h
@@ -0,0 +1,215 @@
+/* Opcode decoder for the Renesas RX
+   Copyright 2008, 2009, 2010
+   Free Software Foundation, Inc.
+   Written by DJ Delorie <dj@redhat.com>
+
+   This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+/* The RX decoder in libopcodes is used by the simulator, gdb's
+   analyzer, and the disassembler.  Given an opcode data source,
+   it decodes the next opcode into the following structures.  */
+
+typedef enum
+{
+  RX_AnySize = 0,
+  RX_Byte, /* undefined extension */
+  RX_UByte,
+  RX_SByte,
+  RX_Word, /* undefined extension */
+  RX_UWord,
+  RX_SWord,
+  RX_3Byte,
+  RX_Long,
+} RX_Size;
+
+typedef enum
+{
+  RX_Operand_None,
+  RX_Operand_Immediate,	/* #addend */
+  RX_Operand_Register,	/* Rn */
+  RX_Operand_Indirect,	/* [Rn + addend] */
+  RX_Operand_Postinc,	/* [Rn+] */
+  RX_Operand_Predec,	/* [-Rn] */
+  RX_Operand_Condition,	/* eq, gtu, etc */
+  RX_Operand_Flag,	/* [UIOSZC] */
+  RX_Operand_TwoReg,	/* [Rn + scale*R2] */
+} RX_Operand_Type;
+
+typedef enum
+{
+  RXO_unknown,
+  RXO_mov,	/* d = s (signed) */
+  RXO_movbi,	/* d = [s,s2] (signed) */
+  RXO_movbir,	/* [s,s2] = d (signed) */
+  RXO_pushm,	/* s..s2 */
+  RXO_popm,	/* s..s2 */
+  RXO_xchg,	/* s <-> d */
+  RXO_stcc,	/* d = s if cond(s2) */
+  RXO_rtsd,	/* rtsd, 1=imm, 2-0 = reg if reg type */
+
+  /* These are all either d OP= s or, if s2 is set, d = s OP s2.  Note
+     that d may be "None".  */
+  RXO_and,
+  RXO_or,
+  RXO_xor,
+  RXO_add,
+  RXO_sub,
+  RXO_mul,
+  RXO_div,
+  RXO_divu,
+  RXO_shll,
+  RXO_shar,
+  RXO_shlr,
+
+  RXO_adc,	/* d = d + s + carry */
+  RXO_sbb,	/* d = d - s - ~carry */
+  RXO_abs,	/* d = |s| */
+  RXO_max,	/* d = max(d,s) */
+  RXO_min,	/* d = min(d,s) */
+  RXO_emul,	/* d:64 = d:32 * s */
+  RXO_emulu,	/* d:64 = d:32 * s (unsigned) */
+
+  RXO_rolc,	/* d <<= 1 through carry */
+  RXO_rorc,	/* d >>= 1 through carry*/
+  RXO_rotl,	/* d <<= #s without carry */
+  RXO_rotr,	/* d >>= #s without carry*/
+  RXO_revw,	/* d = revw(s) */
+  RXO_revl,	/* d = revl(s) */
+  RXO_branch,	/* pc = d if cond(s) */
+  RXO_branchrel,/* pc += d if cond(s) */
+  RXO_jsr,	/* pc = d */
+  RXO_jsrrel,	/* pc += d */
+  RXO_rts,
+  RXO_nop,
+  RXO_nop2,
+  RXO_nop3,
+
+  RXO_scmpu,
+  RXO_smovu,
+  RXO_smovb,
+  RXO_suntil,
+  RXO_swhile,
+  RXO_smovf,
+  RXO_sstr,
+
+  RXO_rmpa,
+  RXO_mulhi,
+  RXO_mullo,
+  RXO_machi,
+  RXO_maclo,
+  RXO_mvtachi,
+  RXO_mvtaclo,
+  RXO_mvfachi,
+  RXO_mvfacmi,
+  RXO_mvfaclo,
+  RXO_racw,
+
+  RXO_sat,	/* sat(d) */
+  RXO_satr,
+
+  RXO_fadd,	/* d op= s */
+  RXO_fcmp,
+  RXO_fsub,
+  RXO_ftoi,
+  RXO_fmul,
+  RXO_fdiv,
+  RXO_round,
+  RXO_itof,
+
+  RXO_bset,	/* d |= (1<<s) */
+  RXO_bclr,	/* d &= ~(1<<s) */
+  RXO_btst,	/* s & (1<<s2) */
+  RXO_bnot,	/* d ^= (1<<s) */
+  RXO_bmcc,	/* d<s> = cond(s2) */
+
+  RXO_clrpsw,	/* flag index in d */
+  RXO_setpsw,	/* flag index in d */
+  RXO_mvtipl,	/* new IPL in s */
+
+  RXO_rtfi,
+  RXO_rte,
+  RXO_rtd,	/* undocumented */
+  RXO_brk,
+  RXO_dbt,	/* undocumented */
+  RXO_int,	/* vector id in s */
+  RXO_stop,
+  RXO_wait,
+
+  RXO_sccnd,	/* d = cond(s) ? 1 : 0 */
+} RX_Opcode_ID;
+
+/* Condition bitpatterns, as registers.  */
+#define RXC_eq		0
+#define RXC_z		0
+#define RXC_ne		1
+#define RXC_nz		1
+#define RXC_c		2
+#define RXC_nc		3
+#define RXC_gtu		4
+#define RXC_leu		5
+#define RXC_pz		6
+#define RXC_n		7
+#define RXC_ge		8
+#define RXC_lt		9
+#define RXC_gt		10
+#define RXC_le		11
+#define RXC_o		12
+#define RXC_no		13
+#define RXC_always	14
+#define RXC_never	15
+
+typedef struct
+{
+  RX_Operand_Type  type;
+  int              reg;
+  int              addend;
+  RX_Size          size;
+} RX_Opcode_Operand;
+
+typedef struct
+{
+  RX_Opcode_ID      id;
+  int               n_bytes;
+  int               prefix;
+  char *            syntax;
+  RX_Size           size;
+  /* By convention, these are destination, source1, source2.  */
+  RX_Opcode_Operand op[3];
+
+  /* The logic here is:
+     newflags = (oldflags & ~(int)flags_0) | flags_1 | (op_flags & flags_s)
+     Only the O, S, Z, and C flags are affected.  */
+  char flags_0; /* This also clears out flags-to-be-set.  */
+  char flags_1;
+  char flags_s;
+} RX_Opcode_Decoded;
+
+/* Within the syntax, %c-style format specifiers are as follows:
+
+   %% = '%' character
+   %0 = operand[0] (destination)
+   %1 = operand[1] (source)
+   %2 = operand[2] (2nd source)
+   %s = operation size (b/w/l)
+   %SN = operand size [N] (N=0,1,2)
+   %aN = op[N] as an address (N=0,1,2)
+
+   Register numbers 0..15 are general registers.  16..31 are control
+   registers.  32..47 are condition codes.  */
+
+int rx_decode_opcode (unsigned long, RX_Opcode_Decoded *, int (*)(void *), void *);
diff --git a/binutils-2.25/include/opcode/s390.h b/binutils-2.25/include/opcode/s390.h
new file mode 100644
index 00000000..531011e0
--- /dev/null
+++ b/binutils-2.25/include/opcode/s390.h
@@ -0,0 +1,154 @@
+/* s390.h -- Header file for S390 opcode table
+   Copyright 2000, 2001, 2003, 2010 Free Software Foundation, Inc.
+   Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#ifndef S390_H
+#define S390_H
+
+/* List of instruction sets variations. */
+
+enum s390_opcode_mode_val
+  {
+    S390_OPCODE_ESA = 0,
+    S390_OPCODE_ZARCH
+  };
+
+enum s390_opcode_cpu_val
+  {
+    S390_OPCODE_G5 = 0,
+    S390_OPCODE_G6,
+    S390_OPCODE_Z900,
+    S390_OPCODE_Z990,
+    S390_OPCODE_Z9_109,
+    S390_OPCODE_Z9_EC,
+    S390_OPCODE_Z10,
+    S390_OPCODE_Z196,
+    S390_OPCODE_ZEC12,
+    S390_OPCODE_MAXCPU
+  };
+
+/* The opcode table is an array of struct s390_opcode.  */
+
+struct s390_opcode
+  {
+    /* The opcode name.  */
+    const char * name;
+
+    /* The opcode itself.  Those bits which will be filled in with
+       operands are zeroes.  */
+    unsigned char opcode[6];
+
+    /* The opcode mask.  This is used by the disassembler.  This is a
+       mask containing ones indicating those bits which must match the
+       opcode field, and zeroes indicating those bits which need not
+       match (and are presumably filled in by operands).  */
+    unsigned char mask[6];
+
+    /* The opcode length in bytes. */
+    int oplen;
+
+    /* An array of operand codes.  Each code is an index into the
+       operand table.  They appear in the order which the operands must
+       appear in assembly code, and are terminated by a zero.  */
+    unsigned char operands[6];
+
+    /* Bitmask of execution modes this opcode is available for.  */
+    unsigned int modes;
+
+    /* First cpu this opcode is available for.  */
+    enum s390_opcode_cpu_val min_cpu;
+  };
+
+/* The table itself is sorted by major opcode number, and is otherwise
+   in the order in which the disassembler should consider
+   instructions.  */
+extern const struct s390_opcode s390_opcodes[];
+extern const int                s390_num_opcodes;
+
+/* A opcode format table for the .insn pseudo mnemonic.  */
+extern const struct s390_opcode s390_opformats[];
+extern const int                s390_num_opformats;
+
+/* Values defined for the flags field of a struct powerpc_opcode.  */
+
+/* The operands table is an array of struct s390_operand.  */
+
+struct s390_operand
+  {
+    /* The number of bits in the operand.  */
+    int bits;
+
+    /* How far the operand is left shifted in the instruction.  */
+    int shift;
+
+    /* One bit syntax flags.  */
+    unsigned long flags;
+  };
+
+/* Elements in the table are retrieved by indexing with values from
+   the operands field of the powerpc_opcodes table.  */
+
+extern const struct s390_operand s390_operands[];
+
+/* Values defined for the flags field of a struct s390_operand.  */
+
+/* This operand names a register.  The disassembler uses this to print
+   register names with a leading 'r'.  */
+#define S390_OPERAND_GPR 0x1
+
+/* This operand names a floating point register.  The disassembler
+   prints these with a leading 'f'. */
+#define S390_OPERAND_FPR 0x2
+
+/* This operand names an access register.  The disassembler
+   prints these with a leading 'a'.  */
+#define S390_OPERAND_AR 0x4
+
+/* This operand names a control register.  The disassembler
+   prints these with a leading 'c'.  */
+#define S390_OPERAND_CR 0x8
+
+/* This operand is a displacement.  */
+#define S390_OPERAND_DISP 0x10
+
+/* This operand names a base register.  */
+#define S390_OPERAND_BASE 0x20
+
+/* This operand names an index register, it can be skipped.  */
+#define S390_OPERAND_INDEX 0x40
+
+/* This operand is a relative branch displacement.  The disassembler
+   prints these symbolically if possible.  */
+#define S390_OPERAND_PCREL 0x80
+
+/* This operand takes signed values.  */
+#define S390_OPERAND_SIGNED 0x100
+
+/* This operand is a length.  */
+#define S390_OPERAND_LENGTH 0x200
+
+/* This operand is optional. Only a single operand at the end of
+   the instruction may be optional.  */
+#define S390_OPERAND_OPTIONAL 0x400
+
+/* The operand needs to be a valid GP or FP register pair.  */
+#define S390_OPERAND_REG_PAIR 0x800
+
+	#endif /* S390_H */
diff --git a/binutils-2.25/include/opcode/score-datadep.h b/binutils-2.25/include/opcode/score-datadep.h
new file mode 100644
index 00000000..10ddf32f
--- /dev/null
+++ b/binutils-2.25/include/opcode/score-datadep.h
@@ -0,0 +1,65 @@
+/* score-datadep.h -- Score Instructions data dependency table
+   Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+   Contributed by: 
+   Brain.lin (brain.lin@sunplusct.com)
+   Mei Ligang (ligang@sunnorth.com.cn)
+   Pei-Lin Tsai (pltsai@sunplus.com)
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING3.  If not, write to the Free
+   Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+#ifndef SCORE_DATA_DEPENDENCY_H
+#define SCORE_DATA_DEPENDENCY_H
+
+#define INSN_NAME_LEN 16
+
+enum insn_type_for_dependency
+{
+  D_mtcr,
+  D_all_insn
+};
+
+struct insn_to_dependency
+{
+  char *insn_name;
+  enum insn_type_for_dependency type;
+};
+
+struct data_dependency
+{
+  enum insn_type_for_dependency pre_insn_type;
+  char pre_reg[6];
+  enum insn_type_for_dependency cur_insn_type;
+  char cur_reg[6];
+  int bubblenum_7;
+  int bubblenum_3;
+  int warn_or_error;           /* warning - 0; error - 1  */
+};
+
+static const struct insn_to_dependency insn_to_dependency_table[] =
+{
+  /* move spectial instruction.  */
+  {"mtcr",      D_mtcr},
+};
+
+static const struct data_dependency data_dependency_table[] =
+{
+  /* Status regiser.  */
+  {D_mtcr, "cr0", D_all_insn, "", 5, 1, 0},
+};
+
+#endif
diff --git a/binutils-2.25/include/opcode/score-inst.h b/binutils-2.25/include/opcode/score-inst.h
new file mode 100644
index 00000000..ecb18da2
--- /dev/null
+++ b/binutils-2.25/include/opcode/score-inst.h
@@ -0,0 +1,236 @@
+/* score-inst.h -- Score Instructions Table
+   Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+   Contributed by: 
+   Brain.lin (brain.lin@sunplusct.com)
+   Mei Ligang (ligang@sunnorth.com.cn)
+   Pei-Lin Tsai (pltsai@sunplus.com)
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING3.  If not, write to the Free
+   Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#ifndef SCORE_INST_H
+#define SCORE_INST_H
+
+#define LDST_UNALIGN_MASK 0x0000007f
+#define UA_LCB		  0x00000060
+#define UA_LCW		  0x00000062
+#define UA_LCE		  0x00000066
+#define UA_SCB		  0x00000068
+#define UA_SCW		  0x0000006a
+#define UA_SCE		  0x0000006e
+#define UA_LL		  0x0000000c
+#define UA_SC		  0x0000000e
+#define LDST16_RR_MASK   0x0000000f
+#define N16_LW           8
+#define N16_LH           9
+#define N16_POP          10
+#define N16_LBU          11
+#define N16_SW           12
+#define N16_SH           13
+#define N16_PUSH         14
+#define N16_SB           15
+#define LDST16_RI_MASK   0x7007
+#define N16_LWP          0x7000
+#define N16_LHP          0x7001
+#define N16_LBUP         0x7003
+#define N16_SWP          0x7004
+#define N16_SHP          0x7005
+#define N16_SBP          0x7007
+#define N16_LIU          0x5000
+
+#define OPC_PSEUDOLDST_MASK	0x00000007
+
+enum
+{
+  INSN_LW = 0,
+  INSN_LH = 1,
+  INSN_LHU = 2,
+  INSN_LB = 3,
+  INSN_SW = 4,
+  INSN_SH = 5,
+  INSN_LBU = 6,
+  INSN_SB = 7,
+};
+
+/* Sub opcdoe opcode.  */
+enum
+{
+  INSN16_LBU = 11,
+  INSN16_LH = 9,
+  INSN16_LW = 8,
+  INSN16_SB = 15,
+  INSN16_SH = 13,
+  INSN16_SW = 12,
+};
+
+enum
+{
+  LDST_NOUPDATE = 0,
+  LDST_PRE = 1,
+  LDST_POST = 2,
+};
+
+enum score_insn_type
+{
+  Rd_I4,
+  Rd_I5,
+  Rd_rvalueBP_I5,
+  Rd_lvalueBP_I5,
+  Rd_Rs_I5,
+  x_Rs_I5,
+  x_I5_x,
+  Rd_I8,
+  Rd_Rs_I14,
+  I15,
+  Rd_I16,
+  Rd_I30, 
+  Rd_I32, 
+  Rd_rvalueRs_SI10,
+  Rd_lvalueRs_SI10,
+  Rd_rvalueRs_preSI12,
+  Rd_rvalueRs_postSI12,
+  Rd_lvalueRs_preSI12,
+  Rd_lvalueRs_postSI12,
+  Rd_Rs_SI14,
+  Rd_rvalueRs_SI15,
+  Rd_lvalueRs_SI15,
+  Rd_SI5,
+  Rd_SI6,
+  Rd_SI16,
+  PC_DISP8div2,
+  PC_DISP11div2,
+  PC_DISP19div2,
+  PC_DISP24div2,
+  Rd_Rs_Rs,
+  x_Rs_x,
+  x_Rs_Rs,
+  Rd_Rs_x,
+  Rd_x_Rs,
+  Rd_x_x,
+  Rd_Rs,
+  Rd_HighRs,
+  Rd_lvalueRs,
+  Rd_rvalueRs,
+  Rd_lvalue32Rs,
+  Rd_rvalue32Rs,
+  x_Rs,
+  NO_OPD,
+  NO16_OPD,
+  OP5_rvalueRs_SI15,
+  I5_Rs_Rs_I5_OP5,
+  x_rvalueRs_post4,
+  Rd_rvalueRs_post4,
+  Rd_x_I5,
+  Rd_lvalueRs_post4,
+  x_lvalueRs_post4,
+  Rd_LowRs,
+  Rd_Rs_Rs_imm,
+  Insn_Type_PCE,
+  Insn_Type_SYN,
+  Insn_GP,
+  Insn_PIC,
+  Insn_internal,
+  Insn_BCMP,
+  Ra_I9_I5,
+};
+
+enum score_data_type
+{
+  _IMM4 = 0,
+  _IMM5,
+  _IMM8,
+  _IMM14,
+  _IMM15,
+  _IMM16,
+  _SIMM10 = 6,
+  _SIMM12,
+  _SIMM14,
+  _SIMM15,
+  _SIMM16,
+  _SIMM14_NEG = 11,
+  _IMM16_NEG,
+  _SIMM16_NEG,
+  _IMM20,
+  _IMM25,
+  _DISP8div2 = 16,
+  _DISP11div2,
+  _DISP19div2,
+  _DISP24div2,
+  _VALUE,
+  _VALUE_HI16,
+  _VALUE_LO16,
+  _VALUE_LDST_LO16 = 23,
+  _SIMM16_LA,
+  _IMM5_RSHIFT_1,
+  _IMM5_RSHIFT_2,
+  _SIMM16_LA_POS,
+  _IMM5_RANGE_8_31,
+  _IMM10_RSHIFT_2,
+  _GP_IMM15 = 30,
+  _GP_IMM14 = 31,
+  _SIMM16_pic = 42,   /* Index in score_df_range.  */
+  _IMM16_LO16_pic = 43,
+  _IMM16_pic = 44,
+
+  _SIMM5 = 45,
+  _SIMM6 = 46,
+  _IMM32 = 47,
+  _SIMM32 = 48,
+  _IMM11 = 49,
+  _IMM5_MULTI_LOAD = 50,
+};
+
+#define REG_TMP			  1
+
+#define OP_REG_TYPE             (1 << 6)
+#define OP_IMM_TYPE             (1 << 7)
+#define OP_SH_REGD              (OP_REG_TYPE |20)
+#define	OP_SH_REGS1             (OP_REG_TYPE |15)
+#define OP_SH_REGS2             (OP_REG_TYPE |10)
+#define OP_SH_I                 (OP_IMM_TYPE | 1)
+#define OP_SH_RI15              (OP_IMM_TYPE | 0)
+#define OP_SH_I12               (OP_IMM_TYPE | 3)
+#define OP_SH_DISP24            (OP_IMM_TYPE | 1)
+#define OP_SH_DISP19_p1         (OP_IMM_TYPE |15)
+#define OP_SH_DISP19_p2         (OP_IMM_TYPE | 1)
+#define OP_SH_I5                (OP_IMM_TYPE |10)
+#define OP_SH_I10               (OP_IMM_TYPE | 5)
+#define OP_SH_COPID             (OP_IMM_TYPE | 5)
+#define OP_SH_TRAPI5            (OP_IMM_TYPE |15)
+#define OP_SH_I15               (OP_IMM_TYPE |10)
+
+#define OP16_SH_REGD            (OP_REG_TYPE | 8)
+#define	OP16_SH_REGS1           (OP_REG_TYPE | 4)
+#define	OP16_SH_I45             (OP_IMM_TYPE | 3)
+#define	OP16_SH_I8              (OP_IMM_TYPE | 0)
+#define OP16_SH_DISP8           (OP_IMM_TYPE | 0)
+#define OP16_SH_DISP11          (OP_IMM_TYPE | 1)
+
+enum insn_class
+{
+  INSN_CLASS_16,
+  INSN_CLASS_32,
+  INSN_CLASS_48,
+  INSN_CLASS_PCE,
+  INSN_CLASS_SYN
+};
+
+/* s3_s7: Globals for both tc-score.c and elf32-score.c.  */
+extern int score3;
+extern int score7;
+
+#endif
diff --git a/binutils-2.25/include/opcode/sparc.h b/binutils-2.25/include/opcode/sparc.h
new file mode 100644
index 00000000..f05909fe
--- /dev/null
+++ b/binutils-2.25/include/opcode/sparc.h
@@ -0,0 +1,280 @@
+/* Definitions for opcode table for the sparc.
+   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
+   2003, 2005, 2010, 2011 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
+   the GNU Binutils.
+
+   GAS/GDB is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS/GDB is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS or GDB; see the file COPYING3.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+#include "ansidecl.h"
+
+/* The SPARC opcode table (and other related data) is defined in
+   the opcodes library in sparc-opc.c.  If you change anything here, make
+   sure you fix up that file, and vice versa.  */
+
+ /* FIXME-someday: perhaps the ,a's and such should be embedded in the
+    instruction's name rather than the args.  This would make gas faster, pinsn
+    slower, but would mess up some macros a bit.  xoxorich. */
+
+/* List of instruction sets variations.
+   These values are such that each element is either a superset of a
+   preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
+   returns non-zero.
+   The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
+   Don't change this without updating sparc-opc.c.  */
+
+enum sparc_opcode_arch_val
+{
+  SPARC_OPCODE_ARCH_V6 = 0,
+  SPARC_OPCODE_ARCH_V7,
+  SPARC_OPCODE_ARCH_V8,
+  SPARC_OPCODE_ARCH_LEON,
+  SPARC_OPCODE_ARCH_SPARCLET,
+  SPARC_OPCODE_ARCH_SPARCLITE,
+  /* V9 variants must appear last.  */
+  SPARC_OPCODE_ARCH_V9,
+  SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions.  */
+  SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions.  */
+  SPARC_OPCODE_ARCH_BAD  /* Error return from sparc_opcode_lookup_arch.  */
+};
+
+/* The highest architecture in the table.  */
+#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
+
+/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
+   insn encoding/decoding.  */
+#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
+
+/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9.  */
+#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
+
+/* Table of cpu variants.  */
+
+typedef struct sparc_opcode_arch
+{
+  const char *name;
+  /* Mask of sparc_opcode_arch_val's supported.
+     EG: For v7 this would be
+     (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
+     These are short's because sparc_opcode.architecture is.  */
+  short supported;
+} sparc_opcode_arch;
+
+extern const struct sparc_opcode_arch sparc_opcode_archs[];
+
+/* Given architecture name, look up it's sparc_opcode_arch_val value.  */
+extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *);
+
+/* Return the bitmask of supported architectures for ARCH.  */
+#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
+
+/* Non-zero if ARCH1 conflicts with ARCH2.
+   IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa.  */
+#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
+ (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
+   != SPARC_OPCODE_SUPPORTED (ARCH1)) \
+  && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
+     != SPARC_OPCODE_SUPPORTED (ARCH2)))
+
+/* Structure of an opcode table entry.  */
+
+typedef struct sparc_opcode
+{
+  const char *name;
+  unsigned long match;	/* Bits that must be set.  */
+  unsigned long lose;	/* Bits that must not be set.  */
+  const char *args;
+  /* This was called "delayed" in versions before the flags.  */
+  unsigned int flags;
+  unsigned int hwcaps;
+  short architecture;	/* Bitmask of sparc_opcode_arch_val's.  */
+} sparc_opcode;
+
+/* FIXME: Add F_ANACHRONISTIC flag for v9.  */
+#define	F_DELAYED	0x00000001 /* Delayed branch.  */
+#define	F_ALIAS		0x00000002 /* Alias for a "real" instruction.  */
+#define	F_UNBR		0x00000004 /* Unconditional branch.  */
+#define	F_CONDBR	0x00000008 /* Conditional branch.  */
+#define	F_JSR		0x00000010 /* Subroutine call.  */
+#define F_FLOAT		0x00000020 /* Floating point instruction (not a branch).  */
+#define F_FBR		0x00000040 /* Floating point branch.  */
+#define F_PREFERRED	0x00000080 /* A preferred alias.  */
+
+#define F_PREF_ALIAS	(F_ALIAS|F_PREFERRED)
+
+/* These must match the HWCAP_* values precisely.  */
+#define HWCAP_MUL32	0x00000001 /* umul/umulcc/smul/smulcc insns */
+#define HWCAP_DIV32	0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
+#define HWCAP_FSMULD	0x00000004 /* 'fsmuld' insn */
+#define HWCAP_V8PLUS	0x00000008 /* v9 insns available to 32bit */
+#define HWCAP_POPC	0x00000010 /* 'popc' insn */
+#define HWCAP_VIS	0x00000020 /* VIS insns */
+#define HWCAP_VIS2	0x00000040 /* VIS2 insns */
+#define HWCAP_ASI_BLK_INIT	\
+			0x00000080 /* block init ASIs */
+#define HWCAP_FMAF	0x00000100 /* fused multiply-add */
+#define HWCAP_VIS3	0x00000400 /* VIS3 insns */
+#define HWCAP_HPC	0x00000800 /* HPC insns */
+#define HWCAP_RANDOM	0x00001000 /* 'random' insn */
+#define HWCAP_TRANS	0x00002000 /* transaction insns */
+#define HWCAP_FJFMAU	0x00004000 /* unfused multiply-add */
+#define HWCAP_IMA	0x00008000 /* integer multiply-add */
+#define HWCAP_ASI_CACHE_SPARING \
+			0x00010000 /* cache sparing ASIs */
+#define HWCAP_AES	0x00020000 /* AES crypto insns */
+#define HWCAP_DES	0x00040000 /* DES crypto insns */
+#define HWCAP_KASUMI	0x00080000 /* KASUMI crypto insns */
+#define HWCAP_CAMELLIA 	0x00100000 /* CAMELLIA crypto insns */
+#define HWCAP_MD5	0x00200000 /* MD5 hashing insns */
+#define HWCAP_SHA1	0x00400000 /* SHA1 hashing insns */
+#define HWCAP_SHA256	0x00800000 /* SHA256 hashing insns */
+#define HWCAP_SHA512	0x01000000 /* SHA512 hashing insns */
+#define HWCAP_MPMUL	0x02000000 /* Multiple Precision Multiply */
+#define HWCAP_MONT	0x04000000 /* Montgomery Mult/Sqrt */
+#define HWCAP_PAUSE	0x08000000 /* Pause insn */
+#define HWCAP_CBCOND	0x10000000 /* Compare and Branch insns */
+#define HWCAP_CRC32C	0x20000000 /* CRC32C insn */
+
+/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
+   macro), which is 64 bits. It is handled as a special case.
+
+   The match component is a mask saying which bits must match a particular
+   opcode in order for an instruction to be an instance of that opcode.
+
+   The args component is a string containing one character for each operand of the
+   instruction.
+
+   Kinds of operands:
+	#	Number used by optimizer.	It is ignored.
+	1	rs1 register.
+	2	rs2 register.
+	d	rd register.
+	e	frs1 floating point register.
+	v	frs1 floating point register (double/even).
+	V	frs1 floating point register (quad/multiple of 4).
+	f	frs2 floating point register.
+	B	frs2 floating point register (double/even).
+	R	frs2 floating point register (quad/multiple of 4).
+	4	frs3 floating point register.
+	5	frs3 floating point register (doube/even).
+	g	frsd floating point register.
+	H	frsd floating point register (double/even).
+	J	frsd floating point register (quad/multiple of 4).
+	b	crs1 coprocessor register
+	c	crs2 coprocessor register
+	D	crsd coprocessor register
+	m	alternate space register (asr) in rd
+	M	alternate space register (asr) in rs1
+	h	22 high bits.
+	X	5 bit unsigned immediate
+	Y	6 bit unsigned immediate
+	3	SIAM mode (3 bits). (v9b)
+	K	MEMBAR mask (7 bits). (v9)
+	j	10 bit Immediate. (v9)
+	I	11 bit Immediate. (v9)
+	i	13 bit Immediate.
+	n	22 bit immediate.
+	k	2+14 bit PC relative immediate. (v9)
+	G	19 bit PC relative immediate. (v9)
+	l	22 bit PC relative immediate.
+	L	30 bit PC relative immediate.
+	a	Annul.	The annul bit is set.
+	A	Alternate address space. Stored as 8 bits.
+	C	Coprocessor state register.
+	F	floating point state register.
+	p	Processor state register.
+	N	Branch predict clear ",pn" (v9)
+	T	Branch predict set ",pt" (v9)
+	z	%icc. (v9)
+	Z	%xcc. (v9)
+	q	Floating point queue.
+	r	Single register that is both rs1 and rd.
+	O	Single register that is both rs2 and rd.
+	Q	Coprocessor queue.
+	S	Special case.
+	t	Trap base register.
+	w	Window invalid mask register.
+	y	Y register.
+	u	sparclet coprocessor registers in rd position
+	U	sparclet coprocessor registers in rs1 position
+	E	%ccr. (v9)
+	s	%fprs. (v9)
+	P	%pc.  (v9)
+	W	%tick.	(v9)
+	o	%asi. (v9)
+	6	%fcc0. (v9)
+	7	%fcc1. (v9)
+	8	%fcc2. (v9)
+	9	%fcc3. (v9)
+	!	Privileged Register in rd (v9)
+	?	Privileged Register in rs1 (v9)
+	*	Prefetch function constant. (v9)
+	x	OPF field (v9 impdep).
+	0	32/64 bit immediate for set or setx (v9) insns
+	_	Ancillary state register in rd (v9a)
+	/	Ancillary state register in rs1 (v9a)
+	(	entire floating point state register (%efsr)
+	)	5 bit immediate placed in RS3 field
+	=	2+8 bit PC relative immediate. (v9)  */
+
+#define OP2(x)		(((x) & 0x7) << 22)  /* Op2 field of format2 insns.  */
+#define OP3(x)		(((x) & 0x3f) << 19) /* Op3 field of format3 insns.  */
+#define OP(x)		((unsigned) ((x) & 0x3) << 30) /* Op field of all insns.  */
+#define OPF(x)		(((x) & 0x1ff) << 5) /* Opf field of float insns.  */
+#define OPF_LOW5(x)	OPF ((x) & 0x1f)     /* V9.  */
+#define OPF_LOW4(x)	OPF ((x) & 0xf)      /* V9.  */
+#define F3F(x, y, z)	(OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns.  */
+#define F3F4(x, y, z)	(OP (x) | OP3 (y) | OPF_LOW4 (z))
+#define F3I(x)		(((x) & 0x1) << 13)  /* Immediate field of format 3 insns.  */
+#define F2(x, y)	(OP (x) | OP2(y))    /* Format 2 insns.  */
+#define F3(x, y, z)	(OP (x) | OP3(y) | F3I(z)) /* Format3 insns.  */
+#define F1(x)		(OP (x))
+#define DISP30(x)	((x) & 0x3fffffff)
+#define ASI(x)		(((x) & 0xff) << 5)  /* Asi field of format3 insns.  */
+#define RS2(x)		((x) & 0x1f)         /* Rs2 field.  */
+#define SIMM13(x)	((x) & 0x1fff)       /* Simm13 field.  */
+#define RD(x)		(((x) & 0x1f) << 25) /* Destination register field.  */
+#define RS1(x)		(((x) & 0x1f) << 14) /* Rs1 field.  */
+#define RS3(x)		(((x) & 0x1f) << 9)  /* Rs3 field.  */
+#define ASI_RS2(x)	(SIMM13 (x))
+#define MEMBAR(x)	((x) & 0x7f)
+#define SLCPOP(x)	(((x) & 0x7f) << 6)  /* Sparclet cpop.  */
+
+#define ANNUL	(1 << 29)
+#define BPRED	(1 << 19)	/* V9.  */
+#define	IMMED	F3I (1)
+#define RD_G0	RD (~0)
+#define	RS1_G0	RS1 (~0)
+#define	RS2_G0	RS2 (~0)
+
+extern const struct sparc_opcode sparc_opcodes[];
+extern const int sparc_num_opcodes;
+
+extern int sparc_encode_asi (const char *);
+extern const char *sparc_decode_asi (int);
+extern int sparc_encode_membar (const char *);
+extern const char *sparc_decode_membar (int);
+extern int sparc_encode_prefetch (const char *);
+extern const char *sparc_decode_prefetch (int);
+extern int sparc_encode_sparclet_cpreg (const char *);
+extern const char *sparc_decode_sparclet_cpreg (int);
+
+/* Local Variables:
+   fill-column: 131
+   comment-column: 0
+   End: */
+
diff --git a/binutils-2.25/include/opcode/spu-insns.h b/binutils-2.25/include/opcode/spu-insns.h
new file mode 100644
index 00000000..d6c260aa
--- /dev/null
+++ b/binutils-2.25/include/opcode/spu-insns.h
@@ -0,0 +1,417 @@
+/* SPU ELF support for BFD.
+
+   Copyright 2006, 2007, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+/* SPU Opcode Table
+
+-=-=-= FORMAT =-=-=-
+                                             		                                             
+       +----+-------+-------+-------+-------+  		       +------------+-------+-------+-------+
+RRR    | op |  RC   |  RB   |  RA   |  RT   |		RI7    | op         |  I7   |  RA   |  RT   |
+       +----+-------+-------+-------+-------+		       +------------+-------+-------+-------+
+        0  3       1       1       2       3		        0          1       1       2       3 
+                   0       7       4       1		                   0       7       4       1 
+
+       +-----------+--------+-------+-------+		       +---------+----------+-------+-------+
+RI8    | op        |   I8   |  RA   |  RT   |		RI10   | op      |   I10    |  RA   |  RT   |
+       +-----------+--------+-------+-------+		       +---------+----------+-------+-------+
+        0         9        1       2       3		        0       7          1       2       3 
+                           7       4       1		                           7       4       1 
+
+       +----------+-----------------+-------+		       +--------+-------------------+-------+
+RI16   | op       |       I16       |  RT   |		RI18   | op     |       I18         |  RT   |
+       +----------+-----------------+-------+		       +--------+-------------------+-------+
+        0        8                 2       3		        0      6                   2       3 
+                                   4       1		                                   4       1 
+
+       +------------+-------+-------+-------+		       +-------+--+-----------------+-------+
+RR     | op         |  RB   |  RA   |  RT   |		LBT    | op    |RO|       I16       |  RO   |
+       +------------+-------+-------+-------+		       +-------+--+-----------------+-------+
+        0          1       1       2       3		        0     6  8                 2       3 
+                   0       7       4       1		                                   4       1 
+
+							       +------------+----+--+-------+-------+
+							LBTI   | op         | // |RO|  RA   |  RO   |
+							       +------------+----+--+-------+-------+
+							        0          1    1  1       2       3
+							                   0    5  7       4       1
+
+-=-=-= OPCODE =-=-=-
+
+OPCODE field specifies the most significant 11bit of the instruction. Some formats don't have 11bits for opcode field, and in this
+case, bit field other than op are defined as 0s. For example, opcode of fma instruction which is RRR format is defined as 0x700,
+since 0x700 -> 11'b11100000000, this means opcode is 4'b1110, and other 7bits are defined as 7'b0000000.
+
+-=-=-= ASM_FORMAT =-=-=-
+
+RRR category						RI7 category                               
+	ASM_RRR		mnemonic RC, RA, RB, RT		        ASM_RI4         mnemonic RT, RA, I4
+							        ASM_RI7         mnemonic RT, RA, I7
+
+RI8 category						RI10 category                               
+	ASM_RUI8	mnemonic RT, RA, UI8		        ASM_AI10        mnemonic RA, I10    
+							        ASM_RI10        mnemonic RT, RA, R10
+							        ASM_RI10IDX     mnemonic RT, I10(RA)
+
+RI16 category						RI18 category                           
+	ASM_I16W	mnemonic I16W			        ASM_RI18        mnemonic RT, I18
+	ASM_RI16	mnemonic RT, I16
+	ASM_RI16W	mnemonic RT, I16W
+
+RR category						LBT category                                    
+	ASM_MFSPR	mnemonic RT, SA			        ASM_LBT         mnemonic brinst, brtarg 
+	ASM_MTSPR	mnemonic SA, RT			                                                
+	ASM_NOOP	mnemonic			LBTI category                                   
+	ASM_RA		mnemonic RA			        ASM_LBTI        mnemonic brinst, RA     
+	ASM_RAB		mnemonic RA, RB
+	ASM_RDCH	mnemonic RT, CA
+	ASM_RR		mnemonic RT, RA, RB
+	ASM_RT		mnemonic RT
+	ASM_RTA		mnemonic RT, RA
+	ASM_WRCH	mnemonic CA, RT
+
+Note that RRR instructions have the names for RC and RT reversed from
+what's in the ISA, in order to put RT in the same position it appears
+for other formats.
+
+-=-=-= DEPENDENCY =-=-=-
+
+DEPENDENCY filed consists of 5 digits. This represents which register is used as source and which register is used as target.
+The first(most significant) digit is always 0. Then it is followd by RC, RB, RA and RT digits.
+If the digit is 0, this means the corresponding register is not used in the instruction.
+If the digit is 1, this means the corresponding register is used as a source in the instruction.
+If the digit is 2, this means the corresponding register is used as a target in the instruction.
+If the digit is 3, this means the corresponding register is used as both source and target in the instruction.
+For example, fms instruction has 00113 as the DEPENDENCY field. This means RC is not used in this operation, RB and RA are
+used as sources and RT is the target.
+
+-=-=-= PIPE =-=-=-
+
+This field shows which execution pipe is used for the instruction
+
+pipe0 execution pipelines:
+	FP6	SP floating pipeline
+	FP7	integer operations executed in SP floating pipeline
+	FPD	DP floating pipeline
+	FX2	FXU pipeline
+	FX3	Rotate/Shift pipeline
+	FXB	Byte pipeline
+	NOP	No pipeline
+
+pipe1 execution pipelines:
+	BR	Branch pipeline
+	LNOP	No pipeline
+	LS	Load/Store pipeline
+	SHUF	Shuffle pipeline
+	SPR	SPR/CH pipeline
+
+*/
+
+#define _A0() {0}
+#define _A1(a) {1,a}
+#define _A2(a,b) {2,a,b}
+#define _A3(a,b,c) {3,a,b,c}
+#define _A4(a,b,c,d) {4,a,b,c,d}
+
+/*    TAG		FORMAT	OPCODE	MNEMONIC	ASM_FORMAT	DEPENDENCY	PIPE	COMMENT				*/
+/*									0[RC][RB][RA][RT]					*/
+/*									1:src, 2:target						*/
+
+APUOP(M_BR,		RI16,	0x190,	"br",		_A1(A_R18),	00000,	BR)	/* BRel          IP<-IP+I16 */
+APUOP(M_BRSL,		RI16,	0x198,	"brsl",		_A2(A_T,A_R18),	00002,	BR)	/* BRelSetLink   RT,IP<-IP,IP+I16 */
+APUOP(M_BRA,		RI16,	0x180,	"bra",		_A1(A_S18),	00000,	BR)	/* BRAbs         IP<-I16 */
+APUOP(M_BRASL,		RI16,	0x188,	"brasl",	_A2(A_T,A_S18),	00002,	BR)	/* BRAbsSetLink  RT,IP<-IP,I16 */
+APUOP(M_FSMBI,		RI16,	0x194,	"fsmbi",	_A2(A_T,A_X16),	00002,	SHUF)	/* FormSelMask%I RT<-fsm(I16) */
+APUOP(M_LQA,		RI16,	0x184,	"lqa",		_A2(A_T,A_S18),	00002,	LS)	/* LoadQAbs      RT<-M[I16] */
+APUOP(M_LQR,		RI16,	0x19C,	"lqr",		_A2(A_T,A_R18),	00002,	LS)	/* LoadQRel      RT<-M[IP+I16] */
+APUOP(M_STOP,		RR,	0x000,	"stop",		_A0(),		00000,	BR)	/* STOP          stop */
+APUOP(M_STOP2,		RR,	0x000,	"stop",		_A1(A_U14),	00000,	BR)	/* STOP          stop */
+APUOP(M_STOPD,		RR,	0x140,	"stopd",	_A3(A_T,A_A,A_B),         00111,	BR)	/* STOPD         stop (with register dependencies) */
+APUOP(M_LNOP,		RR,	0x001,	"lnop",		_A0(),		00000,	LNOP)	/* LNOP          no_operation */
+APUOP(M_SYNC,		RR,	0x002,	"sync",		_A0(),		00000,	BR)	/* SYNC          flush_pipe */
+APUOP(M_DSYNC,		RR,	0x003,	"dsync",	_A0(),		00000,	BR)	/* DSYNC         flush_store_queue */
+APUOP(M_MFSPR,		RR,	0x00c,	"mfspr",	_A2(A_T,A_S),	00002,	SPR)	/* MFSPR         RT<-SA */
+APUOP(M_RDCH,		RR,	0x00d,	"rdch",		_A2(A_T,A_H),	00002,	SPR)	/* ReaDCHannel   RT<-CA:data */
+APUOP(M_RCHCNT,		RR,	0x00f,	"rchcnt",	_A2(A_T,A_H),	00002,	SPR)	/* ReaDCHanCouNT RT<-CA:count */
+APUOP(M_HBRA,		LBT,	0x080,	"hbra",		_A2(A_S11,A_S18),	00000,	LS)	/* HBRA          BTB[B9]<-M[I16] */
+APUOP(M_HBRR,		LBT,	0x090,	"hbrr",		_A2(A_S11,A_R18),	00000,	LS)	/* HBRR          BTB[B9]<-M[IP+I16] */
+APUOP(M_BRZ,		RI16,	0x100,	"brz",		_A2(A_T,A_R18),	00001,	BR)	/* BRZ           IP<-IP+I16_if(RT) */
+APUOP(M_BRNZ,		RI16,	0x108,	"brnz",		_A2(A_T,A_R18),	00001,	BR)	/* BRNZ          IP<-IP+I16_if(RT) */
+APUOP(M_BRHZ,		RI16,	0x110,	"brhz",		_A2(A_T,A_R18),	00001,	BR)	/* BRHZ          IP<-IP+I16_if(RT) */
+APUOP(M_BRHNZ,		RI16,	0x118,	"brhnz",	_A2(A_T,A_R18),	00001,	BR)	/* BRHNZ         IP<-IP+I16_if(RT) */
+APUOP(M_STQA,		RI16,	0x104,	"stqa",		_A2(A_T,A_S18),	00001,	LS)	/* SToreQAbs     M[I16]<-RT */
+APUOP(M_STQR,		RI16,	0x11C,	"stqr",		_A2(A_T,A_R18),	00001,	LS)	/* SToreQRel     M[IP+I16]<-RT */
+APUOP(M_MTSPR,		RR,	0x10c,	"mtspr",	_A2(A_S,A_T),	00001,	SPR)	/* MTSPR         SA<-RT */
+APUOP(M_WRCH,		RR,	0x10d,	"wrch",		_A2(A_H,A_T),	00001,	SPR)	/* ChanWRite     CA<-RT */
+APUOP(M_LQD,		RI10,	0x1a0,	"lqd",		_A4(A_T,A_S14,A_P,A_A),	00012,	LS)	/* LoadQDisp     RT<-M[Ra+I10] */
+APUOP(M_BI,		RR,	0x1a8,	"bi",		_A1(A_A),		00010,	BR)	/* BI            IP<-RA */
+APUOP(M_BISL,		RR,	0x1a9,	"bisl",		_A2(A_T,A_A),	00012,	BR)	/* BISL          RT,IP<-IP,RA */
+APUOP(M_IRET,  		RR,	0x1aa,	"iret",	        _A1(A_A), 	00010,	BR)	/* IRET          IP<-SRR0 */
+APUOP(M_IRET2, 		RR,	0x1aa,	"iret",	        _A0(),	 	00010,	BR)	/* IRET          IP<-SRR0 */
+APUOP(M_BISLED,		RR,	0x1ab,	"bisled",	_A2(A_T,A_A),	00012,	BR)	/* BISLED        RT,IP<-IP,RA_if(ext) */
+APUOP(M_HBR,		LBTI,	0x1ac,	"hbr",		_A2(A_S11I,A_A),	00010,	LS)	/* HBR           BTB[B9]<-M[Ra] */
+APUOP(M_FREST,		RR,	0x1b8,	"frest",	_A2(A_T,A_A),	00012,	SHUF)	/* FREST         RT<-recip(RA) */
+APUOP(M_FRSQEST,	RR,	0x1b9,	"frsqest",	_A2(A_T,A_A),	00012,	SHUF)	/* FRSQEST       RT<-rsqrt(RA) */
+APUOP(M_FSM,		RR,	0x1b4,	"fsm",		_A2(A_T,A_A),	00012,	SHUF)	/* FormSelMask%  RT<-expand(Ra) */
+APUOP(M_FSMH,		RR,	0x1b5,	"fsmh",		_A2(A_T,A_A),	00012,	SHUF)	/* FormSelMask%  RT<-expand(Ra) */
+APUOP(M_FSMB,		RR,	0x1b6,	"fsmb",		_A2(A_T,A_A),	00012,	SHUF)	/* FormSelMask%  RT<-expand(Ra) */
+APUOP(M_GB,		RR,	0x1b0,	"gb",		_A2(A_T,A_A),	00012,	SHUF)	/* GatherBits%   RT<-gather(RA) */
+APUOP(M_GBH,		RR,	0x1b1,	"gbh",		_A2(A_T,A_A),	00012,	SHUF)	/* GatherBits%   RT<-gather(RA) */
+APUOP(M_GBB,		RR,	0x1b2,	"gbb",		_A2(A_T,A_A),	00012,	SHUF)	/* GatherBits%   RT<-gather(RA) */
+APUOP(M_CBD,		RI7,	0x1f4,	"cbd",		_A4(A_T,A_U7,A_P,A_A),	00012,	SHUF)	/* genCtl%%insD  RT<-sta(Ra+I4,siz) */
+APUOP(M_CHD,		RI7,	0x1f5,	"chd",		_A4(A_T,A_U7,A_P,A_A),	00012,	SHUF)	/* genCtl%%insD  RT<-sta(Ra+I4,siz) */
+APUOP(M_CWD,		RI7,	0x1f6,	"cwd",		_A4(A_T,A_U7,A_P,A_A),	00012,	SHUF)	/* genCtl%%insD  RT<-sta(Ra+I4,siz) */
+APUOP(M_CDD,		RI7,	0x1f7,	"cdd",		_A4(A_T,A_U7,A_P,A_A),	00012,	SHUF)	/* genCtl%%insD  RT<-sta(Ra+I4,siz) */
+APUOP(M_ROTQBII,	RI7,	0x1f8,	"rotqbii",	_A3(A_T,A_A,A_U3),	00012,	SHUF)	/* ROTQBII       RT<-RA<<<I7 */
+APUOP(M_ROTQBYI,	RI7,	0x1fc,	"rotqbyi",	_A3(A_T,A_A,A_S7N),	00012,	SHUF)	/* ROTQBYI       RT<-RA<<<(I7*8) */
+APUOP(M_ROTQMBII,	RI7,	0x1f9,	"rotqmbii",	_A3(A_T,A_A,A_S3),	00012,	SHUF)	/* ROTQMBII      RT<-RA<<I7 */
+APUOP(M_ROTQMBYI,	RI7,	0x1fd,	"rotqmbyi",	_A3(A_T,A_A,A_S6),	00012,	SHUF)	/* ROTQMBYI      RT<-RA<<I7 */
+APUOP(M_SHLQBII,	RI7,	0x1fb,	"shlqbii",	_A3(A_T,A_A,A_U3),	00012,	SHUF)	/* SHLQBII       RT<-RA<<I7 */
+APUOP(M_SHLQBYI,	RI7,	0x1ff,	"shlqbyi",	_A3(A_T,A_A,A_U5),	00012,	SHUF)	/* SHLQBYI       RT<-RA<<I7 */
+APUOP(M_STQD,		RI10,	0x120,	"stqd",		_A4(A_T,A_S14,A_P,A_A),	00011,	LS)	/* SToreQDisp    M[Ra+I10]<-RT */
+APUOP(M_BIHNZ,		RR,	0x12b,	"bihnz",	_A2(A_T,A_A),	00011,	BR)	/* BIHNZ         IP<-RA_if(RT) */
+APUOP(M_BIHZ,		RR,	0x12a,	"bihz",		_A2(A_T,A_A),	00011,	BR)	/* BIHZ          IP<-RA_if(RT) */
+APUOP(M_BINZ,		RR,	0x129,	"binz",		_A2(A_T,A_A),	00011,	BR)	/* BINZ          IP<-RA_if(RT) */
+APUOP(M_BIZ,		RR,	0x128,	"biz",		_A2(A_T,A_A),	00011,	BR)	/* BIZ           IP<-RA_if(RT) */
+APUOP(M_CBX,		RR,	0x1d4,	"cbx",		_A3(A_T,A_A,A_B),		00112,	SHUF)	/* genCtl%%insX  RT<-sta(Ra+Rb,siz) */
+APUOP(M_CHX,		RR,	0x1d5,	"chx",		_A3(A_T,A_A,A_B),		00112,	SHUF)	/* genCtl%%insX  RT<-sta(Ra+Rb,siz) */
+APUOP(M_CWX,		RR,	0x1d6,	"cwx",		_A3(A_T,A_A,A_B),		00112,	SHUF)	/* genCtl%%insX  RT<-sta(Ra+Rb,siz) */
+APUOP(M_CDX,		RR,	0x1d7,	"cdx",		_A3(A_T,A_A,A_B),		00112,	SHUF)	/* genCtl%%insX  RT<-sta(Ra+Rb,siz) */
+APUOP(M_LQX,		RR,	0x1c4,	"lqx",		_A3(A_T,A_A,A_B),		00112,	LS)	/* LoadQindeX    RT<-M[Ra+Rb] */
+APUOP(M_ROTQBI,		RR,	0x1d8,	"rotqbi",	_A3(A_T,A_A,A_B),		00112,	SHUF)	/* ROTQBI        RT<-RA<<<Rb */
+APUOP(M_ROTQMBI,	RR,	0x1d9,	"rotqmbi",	_A3(A_T,A_A,A_B),		00112,	SHUF)	/* ROTQMBI       RT<-RA<<Rb */
+APUOP(M_SHLQBI,		RR,	0x1db,	"shlqbi",	_A3(A_T,A_A,A_B),		00112,	SHUF)	/* SHLQBI        RT<-RA<<Rb */
+APUOP(M_ROTQBY,		RR,	0x1dc,	"rotqby",	_A3(A_T,A_A,A_B),		00112,		SHUF)	/* ROTQBY        RT<-RA<<<(Rb*8) */
+APUOP(M_ROTQMBY,	RR,	0x1dd,	"rotqmby",	_A3(A_T,A_A,A_B),		00112,		SHUF)	/* ROTQMBY       RT<-RA<<Rb */
+APUOP(M_SHLQBY,		RR,	0x1df,	"shlqby",	_A3(A_T,A_A,A_B),		00112,	SHUF)	/* SHLQBY        RT<-RA<<Rb */
+APUOP(M_ROTQBYBI,	RR,	0x1cc,	"rotqbybi",	_A3(A_T,A_A,A_B),		00112,		SHUF)	/* ROTQBYBI      RT<-RA<<Rb */
+APUOP(M_ROTQMBYBI,	RR,	0x1cd,	"rotqmbybi",	_A3(A_T,A_A,A_B),		00112,		SHUF)	/* ROTQMBYBI     RT<-RA<<Rb */
+APUOP(M_SHLQBYBI,	RR,	0x1cf,	"shlqbybi",	_A3(A_T,A_A,A_B),		00112,	SHUF)	/* SHLQBYBI      RT<-RA<<Rb */
+APUOP(M_STQX,		RR,	0x144,	"stqx",		_A3(A_T,A_A,A_B),		00111,	LS)	/* SToreQindeX   M[Ra+Rb]<-RT */
+APUOP(M_SHUFB,		RRR,	0x580,	"shufb",	_A4(A_C,A_A,A_B,A_T),	02111,	SHUF)	/* SHUFfleBytes  RC<-f(RA,RB,RT) */
+APUOP(M_IL,		RI16,	0x204,	"il",		_A2(A_T,A_S16),	00002,	FX2)	/* ImmLoad       RT<-sxt(I16) */
+APUOP(M_ILH,		RI16,	0x20c,	"ilh",		_A2(A_T,A_X16),	00002,	FX2)	/* ImmLoadH      RT<-I16 */
+APUOP(M_ILHU,		RI16,	0x208,	"ilhu",		_A2(A_T,A_X16),	00002,	FX2)	/* ImmLoadHUpper RT<-I16<<16 */
+APUOP(M_ILA,		RI18,	0x210,	"ila",		_A2(A_T,A_U18),	00002,	FX2)	/* ImmLoadAddr   RT<-zxt(I18) */
+APUOP(M_NOP,		RR,	0x201,	"nop",		_A1(A_T),		00000,	NOP)	/* XNOP          no_operation */
+APUOP(M_NOP2,		RR,	0x201,	"nop",		_A0(),		00000,	NOP)	/* XNOP          no_operation */
+APUOP(M_IOHL,		RI16,	0x304,	"iohl",		_A2(A_T,A_X16),	00003,	FX2)	/* AddImmeXt     RT<-RT+sxt(I16) */
+APUOP(M_ANDBI,		RI10,	0x0b0,	"andbi",	_A3(A_T,A_A,A_S10B),	00012,	FX2)	/* AND%I         RT<-RA&I10 */
+APUOP(M_ANDHI,		RI10,	0x0a8,	"andhi",	_A3(A_T,A_A,A_S10),	00012,	FX2)	/* AND%I         RT<-RA&I10 */
+APUOP(M_ANDI,		RI10,	0x0a0,	"andi",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* AND%I         RT<-RA&I10 */
+APUOP(M_ORBI,		RI10,	0x030,	"orbi",		_A3(A_T,A_A,A_S10B),	00012,	FX2)	/* OR%I          RT<-RA|I10 */
+APUOP(M_ORHI,		RI10,	0x028,	"orhi",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* OR%I          RT<-RA|I10 */
+APUOP(M_ORI,		RI10,	0x020,	"ori",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* OR%I          RT<-RA|I10 */
+APUOP(M_ORX,		RR,	0x1f0,	"orx",		_A2(A_T,A_A),		00012,	BR)	/* ORX           RT<-RA.w0|RA.w1|RA.w2|RA.w3 */
+APUOP(M_XORBI,		RI10,	0x230,	"xorbi",	_A3(A_T,A_A,A_S10B),	00012,	FX2)	/* XOR%I         RT<-RA^I10 */
+APUOP(M_XORHI,		RI10,	0x228,	"xorhi",	_A3(A_T,A_A,A_S10),	00012,	FX2)	/* XOR%I         RT<-RA^I10 */
+APUOP(M_XORI,		RI10,	0x220,	"xori",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* XOR%I         RT<-RA^I10 */
+APUOP(M_AHI,		RI10,	0x0e8,	"ahi",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* Add%Immed     RT<-RA+I10 */
+APUOP(M_AI,		RI10,	0x0e0,	"ai",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* Add%Immed     RT<-RA+I10 */
+APUOP(M_SFHI,		RI10,	0x068,	"sfhi",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* SubFrom%Imm   RT<-I10-RA */
+APUOP(M_SFI,		RI10,	0x060,	"sfi",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* SubFrom%Imm   RT<-I10-RA */
+APUOP(M_CGTBI,		RI10,	0x270,	"cgtbi",	_A3(A_T,A_A,A_S10B),	00012,	FX2)	/* CGT%I         RT<-(RA>I10) */
+APUOP(M_CGTHI,		RI10,	0x268,	"cgthi",	_A3(A_T,A_A,A_S10),	00012,	FX2)	/* CGT%I         RT<-(RA>I10) */
+APUOP(M_CGTI,		RI10,	0x260,	"cgti",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* CGT%I         RT<-(RA>I10) */
+APUOP(M_CLGTBI,		RI10,	0x2f0,	"clgtbi",	_A3(A_T,A_A,A_S10B),	00012,	FX2)	/* CLGT%I        RT<-(RA>I10) */
+APUOP(M_CLGTHI,		RI10,	0x2e8,	"clgthi",	_A3(A_T,A_A,A_S10),	00012,	FX2)	/* CLGT%I        RT<-(RA>I10) */
+APUOP(M_CLGTI,		RI10,	0x2e0,	"clgti",	_A3(A_T,A_A,A_S10),	00012,	FX2)	/* CLGT%I        RT<-(RA>I10) */
+APUOP(M_CEQBI,		RI10,	0x3f0,	"ceqbi",	_A3(A_T,A_A,A_S10B),	00012,	FX2)	/* CEQ%I         RT<-(RA=I10) */
+APUOP(M_CEQHI,		RI10,	0x3e8,	"ceqhi",	_A3(A_T,A_A,A_S10),	00012,	FX2)	/* CEQ%I         RT<-(RA=I10) */
+APUOP(M_CEQI,		RI10,	0x3e0,	"ceqi",		_A3(A_T,A_A,A_S10),	00012,	FX2)	/* CEQ%I         RT<-(RA=I10) */
+APUOP(M_HGTI,		RI10,	0x278,	"hgti",		_A3(A_T,A_A,A_S10),	00010,	FX2)	/* HaltGTI       halt_if(RA>I10) */
+APUOP(M_HGTI2,		RI10,	0x278,	"hgti",		_A2(A_A,A_S10),	00010,	FX2)	/* HaltGTI       halt_if(RA>I10) */
+APUOP(M_HLGTI,		RI10,	0x2f8,	"hlgti",	_A3(A_T,A_A,A_S10),	00010,	FX2)	/* HaltLGTI      halt_if(RA>I10) */
+APUOP(M_HLGTI2,		RI10,	0x2f8,	"hlgti",	_A2(A_A,A_S10),	00010,	FX2)	/* HaltLGTI      halt_if(RA>I10) */
+APUOP(M_HEQI,		RI10,	0x3f8,	"heqi",		_A3(A_T,A_A,A_S10),	00010,	FX2)	/* HaltEQImm     halt_if(RA=I10) */
+APUOP(M_HEQI2,		RI10,	0x3f8,	"heqi",		_A2(A_A,A_S10),	00010,	FX2)	/* HaltEQImm     halt_if(RA=I10) */
+APUOP(M_MPYI,		RI10,	0x3a0,	"mpyi",		_A3(A_T,A_A,A_S10),	00012,	FP7)	/* MPYI          RT<-RA*I10 */
+APUOP(M_MPYUI,		RI10,	0x3a8,	"mpyui",	_A3(A_T,A_A,A_S10),	00012,	FP7)	/* MPYUI         RT<-RA*I10 */
+APUOP(M_CFLTS,		RI8,	0x3b0,	"cflts",	_A3(A_T,A_A,A_U7A),	00012,	FP7)	/* CFLTS         RT<-int(RA,I8) */
+APUOP(M_CFLTU,		RI8,	0x3b2,	"cfltu",	_A3(A_T,A_A,A_U7A),	00012,	FP7)	/* CFLTU         RT<-int(RA,I8) */
+APUOP(M_CSFLT,		RI8,	0x3b4,	"csflt",	_A3(A_T,A_A,A_U7B),	00012,	FP7)	/* CSFLT         RT<-flt(RA,I8) */
+APUOP(M_CUFLT,		RI8,	0x3b6,	"cuflt",	_A3(A_T,A_A,A_U7B),	00012,	FP7)	/* CUFLT         RT<-flt(RA,I8) */
+APUOP(M_FESD,		RR,	0x3b8,	"fesd",		_A2(A_T,A_A),	00012,	FPD)	/* FESD          RT<-double(RA) */
+APUOP(M_FRDS,		RR,	0x3b9,	"frds",		_A2(A_T,A_A),	00012,	FPD)	/* FRDS          RT<-single(RA) */
+APUOP(M_FSCRRD,		RR,	0x398,	"fscrrd",	_A1(A_T),		00002,	FPD)	/* FSCRRD        RT<-FP_status */
+APUOP(M_FSCRWR,		RR,	0x3ba,	"fscrwr",	_A2(A_T,A_A),	00010,	FP7)	/* FSCRWR        FP_status<-RA */
+APUOP(M_FSCRWR2,	RR,	0x3ba,	"fscrwr",	_A1(A_A),		00010,	FP7)	/* FSCRWR        FP_status<-RA */
+APUOP(M_CLZ,		RR,	0x2a5,	"clz",		_A2(A_T,A_A),	00012,	FX2)	/* CLZ           RT<-clz(RA) */
+APUOP(M_CNTB,		RR,	0x2b4,	"cntb",		_A2(A_T,A_A),	00012,	FXB)	/* CNT           RT<-pop(RA) */
+APUOP(M_XSBH,		RR,	0x2b6,	"xsbh",		_A2(A_T,A_A),	00012,	FX2)	/* eXtSignBtoH   RT<-sign_ext(RA) */
+APUOP(M_XSHW,		RR,	0x2ae,	"xshw",		_A2(A_T,A_A),	00012,	FX2)	/* eXtSignHtoW   RT<-sign_ext(RA) */
+APUOP(M_XSWD,		RR,	0x2a6,	"xswd",		_A2(A_T,A_A),	00012,	FX2)	/* eXtSignWtoD   RT<-sign_ext(RA) */
+APUOP(M_ROTI,		RI7,	0x078,	"roti",		_A3(A_T,A_A,A_S7N),	00012,	FX3)	/* ROT%I         RT<-RA<<<I7 */
+APUOP(M_ROTMI,		RI7,	0x079,	"rotmi",	_A3(A_T,A_A,A_S7),	00012,	FX3)	/* ROT%MI        RT<-RA<<I7 */
+APUOP(M_ROTMAI,		RI7,	0x07a,	"rotmai",	_A3(A_T,A_A,A_S7),	00012,	FX3)	/* ROTMA%I       RT<-RA<<I7 */
+APUOP(M_SHLI,		RI7,	0x07b,	"shli",		_A3(A_T,A_A,A_U6),	00012,	FX3)	/* SHL%I         RT<-RA<<I7 */
+APUOP(M_ROTHI,		RI7,	0x07c,	"rothi",	_A3(A_T,A_A,A_S7N),	00012,	FX3)	/* ROT%I         RT<-RA<<<I7 */
+APUOP(M_ROTHMI,		RI7,	0x07d,	"rothmi",	_A3(A_T,A_A,A_S6),	00012,	FX3)	/* ROT%MI        RT<-RA<<I7 */
+APUOP(M_ROTMAHI,	RI7,	0x07e,	"rotmahi",	_A3(A_T,A_A,A_S6),	00012,	FX3)	/* ROTMA%I       RT<-RA<<I7 */
+APUOP(M_SHLHI,		RI7,	0x07f,	"shlhi",	_A3(A_T,A_A,A_U5),	00012,	FX3)	/* SHL%I         RT<-RA<<I7 */
+APUOP(M_A,		RR,	0x0c0,	"a",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* Add%          RT<-RA+RB */
+APUOP(M_AH,		RR,	0x0c8,	"ah",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* Add%          RT<-RA+RB */
+APUOP(M_SF,		RR,	0x040,	"sf",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* SubFrom%      RT<-RB-RA */
+APUOP(M_SFH,		RR,	0x048,	"sfh",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* SubFrom%      RT<-RB-RA */
+APUOP(M_CGT,		RR,	0x240,	"cgt",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* CGT%          RT<-(RA>RB) */
+APUOP(M_CGTB,		RR,	0x250,	"cgtb",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* CGT%          RT<-(RA>RB) */
+APUOP(M_CGTH,		RR,	0x248,	"cgth",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* CGT%          RT<-(RA>RB) */
+APUOP(M_CLGT,		RR,	0x2c0,	"clgt",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* CLGT%         RT<-(RA>RB) */
+APUOP(M_CLGTB,		RR,	0x2d0,	"clgtb",	_A3(A_T,A_A,A_B),		00112,	FX2)	/* CLGT%         RT<-(RA>RB) */
+APUOP(M_CLGTH,		RR,	0x2c8,	"clgth",	_A3(A_T,A_A,A_B),		00112,	FX2)	/* CLGT%         RT<-(RA>RB) */
+APUOP(M_CEQ,		RR,	0x3c0,	"ceq",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* CEQ%          RT<-(RA=RB) */
+APUOP(M_CEQB,		RR,	0x3d0,	"ceqb",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* CEQ%          RT<-(RA=RB) */
+APUOP(M_CEQH,		RR,	0x3c8,	"ceqh",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* CEQ%          RT<-(RA=RB) */
+APUOP(M_HGT,		RR,	0x258,	"hgt",		_A3(A_T,A_A,A_B),		00110,	FX2)	/* HaltGT        halt_if(RA>RB) */
+APUOP(M_HGT2,		RR,	0x258,	"hgt",		_A2(A_A,A_B),	00110,	FX2)	/* HaltGT        halt_if(RA>RB) */
+APUOP(M_HLGT,		RR,	0x2d8,	"hlgt",		_A3(A_T,A_A,A_B),		00110,	FX2)	/* HaltLGT       halt_if(RA>RB) */
+APUOP(M_HLGT2,		RR,	0x2d8,	"hlgt",		_A2(A_A,A_B),	00110,	FX2)	/* HaltLGT       halt_if(RA>RB) */
+APUOP(M_HEQ,		RR,	0x3d8,	"heq",		_A3(A_T,A_A,A_B),		00110,	FX2)	/* HaltEQ        halt_if(RA=RB) */
+APUOP(M_HEQ2,		RR,	0x3d8,	"heq",		_A2(A_A,A_B),	00110,	FX2)	/* HaltEQ        halt_if(RA=RB) */
+APUOP(M_FCEQ,		RR,	0x3c2,	"fceq",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* FCEQ          RT<-(RA=RB) */
+APUOP(M_FCMEQ,		RR,	0x3ca,	"fcmeq",	_A3(A_T,A_A,A_B),		00112,	FX2)	/* FCMEQ         RT<-(|RA|=|RB|) */
+APUOP(M_FCGT,		RR,	0x2c2,	"fcgt",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* FCGT          RT<-(RA<RB) */
+APUOP(M_FCMGT,		RR,	0x2ca,	"fcmgt",	_A3(A_T,A_A,A_B),		00112,	FX2)	/* FCMGT         RT<-(|RA|<|RB|) */
+APUOP(M_AND,		RR,	0x0c1,	"and",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* AND           RT<-RA&RB */
+APUOP(M_NAND,		RR,	0x0c9,	"nand",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* NAND          RT<-!(RA&RB) */
+APUOP(M_OR,		RR,	0x041,	"or",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* OR            RT<-RA|RB */
+APUOP(M_NOR,		RR,	0x049,	"nor",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* NOR           RT<-!(RA&RB) */
+APUOP(M_XOR,		RR,	0x241,	"xor",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* XOR           RT<-RA^RB */
+APUOP(M_EQV,		RR,	0x249,	"eqv",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* EQuiValent    RT<-!(RA^RB) */
+APUOP(M_ANDC,		RR,	0x2c1,	"andc",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* ANDComplement RT<-RA&!RB */
+APUOP(M_ORC,		RR,	0x2c9,	"orc",		_A3(A_T,A_A,A_B),		00112,	FX2)	/* ORComplement  RT<-RA|!RB */
+APUOP(M_ABSDB,		RR,	0x053,	"absdb",	_A3(A_T,A_A,A_B),		00112,	FXB)	/* ABSoluteDiff  RT<-|RA-RB| */
+APUOP(M_AVGB,		RR,	0x0d3,	"avgb",		_A3(A_T,A_A,A_B),		00112,	FXB)	/* AVG%          RT<-(RA+RB+1)/2 */
+APUOP(M_SUMB,		RR,	0x253,	"sumb",		_A3(A_T,A_A,A_B),		00112,	FXB)	/* SUM%          RT<-f(RA,RB) */
+APUOP(M_DFA,		RR,	0x2cc,	"dfa",		_A3(A_T,A_A,A_B),		00112,	FPD)	/* DFAdd         RT<-RA+RB */
+APUOP(M_DFM,		RR,	0x2ce,	"dfm",		_A3(A_T,A_A,A_B),		00112,	FPD)	/* DFMul         RT<-RA*RB */
+APUOP(M_DFS,		RR,	0x2cd,	"dfs",		_A3(A_T,A_A,A_B),		00112,	FPD)	/* DFSub         RT<-RA-RB */
+APUOP(M_FA,		RR,	0x2c4,	"fa",		_A3(A_T,A_A,A_B),		00112,	FP6)	/* FAdd          RT<-RA+RB */
+APUOP(M_FM,		RR,	0x2c6,	"fm",		_A3(A_T,A_A,A_B),		00112,	FP6)	/* FMul          RT<-RA*RB */
+APUOP(M_FS,		RR,	0x2c5,	"fs",		_A3(A_T,A_A,A_B),		00112,	FP6)	/* FSub          RT<-RA-RB */
+APUOP(M_MPY,		RR,	0x3c4,	"mpy",		_A3(A_T,A_A,A_B),		00112,	FP7)	/* MPY           RT<-RA*RB */
+APUOP(M_MPYH,		RR,	0x3c5,	"mpyh",		_A3(A_T,A_A,A_B),		00112,	FP7)	/* MPYH          RT<-(RAh*RB)<<16 */
+APUOP(M_MPYHH,		RR,	0x3c6,	"mpyhh",	_A3(A_T,A_A,A_B),		00112,	FP7)	/* MPYHH         RT<-RAh*RBh */
+APUOP(M_MPYHHU,		RR,	0x3ce,	"mpyhhu",	_A3(A_T,A_A,A_B),		00112,	FP7)	/* MPYHHU        RT<-RAh*RBh */
+APUOP(M_MPYS,		RR,	0x3c7,	"mpys",		_A3(A_T,A_A,A_B),		00112,	FP7)	/* MPYS          RT<-(RA*RB)>>16 */
+APUOP(M_MPYU,		RR,	0x3cc,	"mpyu",		_A3(A_T,A_A,A_B),		00112,	FP7)	/* MPYU          RT<-RA*RB */
+APUOP(M_FI,		RR,	0x3d4,	"fi",		_A3(A_T,A_A,A_B),		00112,	FP7)	/* FInterpolate  RT<-f(RA,RB) */
+APUOP(M_ROT,		RR,	0x058,	"rot",		_A3(A_T,A_A,A_B),		00112,	FX3)	/* ROT%          RT<-RA<<<RB */
+APUOP(M_ROTM,		RR,	0x059,	"rotm",		_A3(A_T,A_A,A_B),		00112,	FX3)	/* ROT%M         RT<-RA<<Rb */
+APUOP(M_ROTMA,		RR,	0x05a,	"rotma",	_A3(A_T,A_A,A_B),		00112,	FX3)	/* ROTMA%        RT<-RA<<Rb */
+APUOP(M_SHL,		RR,	0x05b,	"shl",		_A3(A_T,A_A,A_B),		00112,	FX3)	/* SHL%          RT<-RA<<Rb */
+APUOP(M_ROTH,		RR,	0x05c,	"roth",		_A3(A_T,A_A,A_B),		00112,	FX3)	/* ROT%          RT<-RA<<<RB */
+APUOP(M_ROTHM,		RR,	0x05d,	"rothm",	_A3(A_T,A_A,A_B),		00112,	FX3)	/* ROT%M         RT<-RA<<Rb */
+APUOP(M_ROTMAH,		RR,	0x05e,	"rotmah",	_A3(A_T,A_A,A_B),		00112,	FX3)	/* ROTMA%        RT<-RA<<Rb */
+APUOP(M_SHLH,		RR,	0x05f,	"shlh",		_A3(A_T,A_A,A_B),		00112,	FX3)	/* SHL%          RT<-RA<<Rb */
+APUOP(M_MPYHHA,		RR,	0x346,	"mpyhha",	_A3(A_T,A_A,A_B),		00113,	FP7)	/* MPYHHA        RT<-RAh*RBh+RT */
+APUOP(M_MPYHHAU,	RR,	0x34e,	"mpyhhau",	_A3(A_T,A_A,A_B),		00113,	FP7)	/* MPYHHAU       RT<-RAh*RBh+RT */
+APUOP(M_DFMA,		RR,	0x35c,	"dfma",		_A3(A_T,A_A,A_B),		00113,	FPD)	/* DFMAdd        RT<-RT+RA*RB */
+APUOP(M_DFMS,		RR,	0x35d,	"dfms",		_A3(A_T,A_A,A_B),		00113,	FPD)	/* DFMSub        RT<-RA*RB-RT */
+APUOP(M_DFNMS,		RR,	0x35e,	"dfnms",	_A3(A_T,A_A,A_B),		00113,	FPD)	/* DFNMSub       RT<-RT-RA*RB */
+APUOP(M_DFNMA,		RR,	0x35f,	"dfnma",	_A3(A_T,A_A,A_B),		00113,	FPD)	/* DFNMAdd       RT<-(-RT)-RA*RB */
+APUOP(M_FMA,		RRR,	0x700,	"fma",		_A4(A_C,A_A,A_B,A_T),	02111,	FP6)	/* FMAdd         RC<-RT+RA*RB */
+APUOP(M_FMS,		RRR,	0x780,	"fms",		_A4(A_C,A_A,A_B,A_T),	02111,	FP6)	/* FMSub         RC<-RA*RB-RT */
+APUOP(M_FNMS,		RRR,	0x680,	"fnms",		_A4(A_C,A_A,A_B,A_T),	02111,	FP6)	/* FNMSub        RC<-RT-RA*RB */
+APUOP(M_MPYA,		RRR,	0x600,	"mpya",		_A4(A_C,A_A,A_B,A_T),	02111,	FP7)	/* MPYA          RC<-RA*RB+RT */
+APUOP(M_SELB,		RRR,	0x400,	"selb",		_A4(A_C,A_A,A_B,A_T),	02111,	FX2)	/* SELectBits    RC<-RA&RT|RB&!RT */
+/* for system function call, this uses op-code of mtspr */
+APUOP(M_SYSCALL,	RI7,    0x10c,	"syscall",      _A3(A_T,A_A,A_S7N),	00002,	SPR)        /* System Call */
+/*
+pseudo instruction:
+system call
+value of I9	operation
+0	halt
+1		rt[0] = open(MEM[ra[0]],	ra[1])
+2		rt[0] = close(ra[0])
+3		rt[0] = read(ra[0],	MEM[ra[1]],	ra[2])
+4		rt[0] = write(ra[0],	MEM[ra[1]],	ra[2])
+5		printf(MEM[ra[0]],	ra[1],	ra[2],	ra[3])
+42		rt[0] = clock()
+52		rt[0] = lseek(ra0,	ra1,	ra2)
+
+*/
+
+
+/* new multiprecision add/sub */
+APUOP(M_ADDX,		RR,	0x340,	"addx",		_A3(A_T,A_A,A_B),		00113,		FX2)	/* Add_eXtended  RT<-RA+RB+RT */
+APUOP(M_CG,		RR,	0x0c2,	"cg",		_A3(A_T,A_A,A_B),		00112,		FX2)	/* CarryGenerate RT<-cout(RA+RB) */
+APUOP(M_CGX,		RR,	0x342,	"cgx",		_A3(A_T,A_A,A_B),		00113,		FX2)	/* CarryGen_eXtd RT<-cout(RA+RB+RT) */
+APUOP(M_SFX,		RR,	0x341,	"sfx",		_A3(A_T,A_A,A_B),		00113,		FX2)	/* Add_eXtended  RT<-RA+RB+RT */
+APUOP(M_BG,		RR,	0x042,	"bg",		_A3(A_T,A_A,A_B),		00112,		FX2)	/* CarryGenerate RT<-cout(RA+RB) */
+APUOP(M_BGX,		RR,	0x343,	"bgx",		_A3(A_T,A_A,A_B),		00113,		FX2)	/* CarryGen_eXtd RT<-cout(RA+RB+RT) */
+
+/*
+
+The following ops are a subset of above except with feature bits set.
+Feature bits are bits 11-17 of the instruction:
+
+  11 - C & P feature bit
+  12 - disable interrupts
+  13 - enable interrupts
+
+*/
+APUOPFB(M_BID,		RR,	0x1a8,	0x20,	"bid",		_A1(A_A),		00010,	BR)	/* BI            IP<-RA */
+APUOPFB(M_BIE,		RR,	0x1a8,	0x10,	"bie",		_A1(A_A),		00010,	BR)	/* BI            IP<-RA */
+APUOPFB(M_BISLD,	RR,	0x1a9,	0x20,	"bisld",	_A2(A_T,A_A),	00012,	BR)	/* BISL          RT,IP<-IP,RA */
+APUOPFB(M_BISLE,	RR,	0x1a9,	0x10,	"bisle",	_A2(A_T,A_A),	00012,	BR)	/* BISL          RT,IP<-IP,RA */
+APUOPFB(M_IRETD,  	RR,	0x1aa,	0x20,	"iretd",	_A1(A_A), 	00010,	BR)	/* IRET          IP<-SRR0 */
+APUOPFB(M_IRETD2,  	RR,	0x1aa,	0x20,	"iretd",	_A0(),	 	00010,	BR)	/* IRET          IP<-SRR0 */
+APUOPFB(M_IRETE,  	RR,	0x1aa,	0x10,	"irete",	_A1(A_A), 	00010,	BR)	/* IRET          IP<-SRR0 */
+APUOPFB(M_IRETE2,  	RR,	0x1aa,	0x10,	"irete",	_A0(),	 	00010,	BR)	/* IRET          IP<-SRR0 */
+APUOPFB(M_BISLEDD,	RR,	0x1ab,	0x20,	"bisledd",	_A2(A_T,A_A),	00012,	BR)	/* BISLED        RT,IP<-IP,RA_if(ext) */
+APUOPFB(M_BISLEDE,	RR,	0x1ab,	0x10,	"bislede",	_A2(A_T,A_A),	00012,	BR)	/* BISLED        RT,IP<-IP,RA_if(ext) */
+APUOPFB(M_BIHNZD,	RR,	0x12b,	0x20,	"bihnzd",	_A2(A_T,A_A),	00011,	BR)	/* BIHNZ         IP<-RA_if(RT) */
+APUOPFB(M_BIHNZE,	RR,	0x12b,	0x10,	"bihnze",	_A2(A_T,A_A),	00011,	BR)	/* BIHNZ         IP<-RA_if(RT) */
+APUOPFB(M_BIHZD,	RR,	0x12a,	0x20,	"bihzd",	_A2(A_T,A_A),	00011,	BR)	/* BIHZ          IP<-RA_if(RT) */
+APUOPFB(M_BIHZE,	RR,	0x12a,	0x10,	"bihze",	_A2(A_T,A_A),	00011,	BR)	/* BIHZ          IP<-RA_if(RT) */
+APUOPFB(M_BINZD,	RR,	0x129,	0x20,	"binzd",	_A2(A_T,A_A),	00011,	BR)	/* BINZ          IP<-RA_if(RT) */
+APUOPFB(M_BINZE,	RR,	0x129,	0x10,	"binze",	_A2(A_T,A_A),	00011,	BR)	/* BINZ          IP<-RA_if(RT) */
+APUOPFB(M_BIZD,		RR,	0x128,	0x20,	"bizd",		_A2(A_T,A_A),	00011,	BR)	/* BIZ           IP<-RA_if(RT) */
+APUOPFB(M_BIZE,		RR,	0x128,	0x10,	"bize",		_A2(A_T,A_A),	00011,	BR)	/* BIZ           IP<-RA_if(RT) */
+APUOPFB(M_SYNCC,	RR,	0x002,	0x40,	"syncc",	_A0(),		00000,	BR)	/* SYNCC          flush_pipe */
+APUOPFB(M_HBRP,		LBTI,	0x1ac,	0x40,	"hbrp",		_A0(),	        00010,	LS)	/* HBR           BTB[B9]<-M[Ra] */
+
+/* Synonyms required by the AS manual. */
+APUOP(M_LR,		RI10,	0x020,	"lr",		_A2(A_T,A_A),	00012,	FX2)	/* OR%I          RT<-RA|I10 */
+APUOP(M_BIHT,		RR,	0x12b,	"biht", 	_A2(A_T,A_A),	00011,	BR)	/* BIHNZ         IP<-RA_if(RT) */
+APUOP(M_BIHF,		RR,	0x12a,	"bihf",		_A2(A_T,A_A),	00011,	BR)	/* BIHZ          IP<-RA_if(RT) */
+APUOP(M_BIT,		RR,	0x129,	"bit",		_A2(A_T,A_A),	00011,	BR)	/* BINZ          IP<-RA_if(RT) */
+APUOP(M_BIF,		RR,	0x128,	"bif",		_A2(A_T,A_A),	00011,	BR)	/* BIZ           IP<-RA_if(RT) */
+APUOPFB(M_BIHTD,	RR,	0x12b,	0x20,	"bihtd",	_A2(A_T,A_A),	00011,	BR)	/* BIHNF         IP<-RA_if(RT) */
+APUOPFB(M_BIHTE,	RR,	0x12b,	0x10,	"bihte",	_A2(A_T,A_A),	00011,	BR)	/* BIHNF         IP<-RA_if(RT) */
+APUOPFB(M_BIHFD,	RR,	0x12a,	0x20,	"bihfd",	_A2(A_T,A_A),	00011,	BR)	/* BIHZ          IP<-RA_if(RT) */
+APUOPFB(M_BIHFE,	RR,	0x12a,	0x10,	"bihfe",	_A2(A_T,A_A),	00011,	BR)	/* BIHZ          IP<-RA_if(RT) */
+APUOPFB(M_BITD, 	RR,	0x129,	0x20,	"bitd", 	_A2(A_T,A_A),	00011,	BR)	/* BINF          IP<-RA_if(RT) */
+APUOPFB(M_BITE, 	RR,	0x129,	0x10,	"bite", 	_A2(A_T,A_A),	00011,	BR)	/* BINF          IP<-RA_if(RT) */
+APUOPFB(M_BIFD,		RR,	0x128,	0x20,	"bifd",		_A2(A_T,A_A),	00011,	BR)	/* BIZ           IP<-RA_if(RT) */
+APUOPFB(M_BIFE,		RR,	0x128,	0x10,	"bife",		_A2(A_T,A_A),	00011,	BR)	/* BIZ           IP<-RA_if(RT) */
+
+/* New soma double-float insns.  */
+APUOP(M_DFCEQ,		RR,	0x3c3,	"dfceq",	_A3(A_T,A_A,A_B),	00112,	FX2)	/* DFCEQ         RT<-(RA=RB) */
+APUOP(M_DFCMEQ,		RR,	0x3cb,	"dfcmeq",	_A3(A_T,A_A,A_B),	00112,	FX2)	/* DFCMEQ        RT<-(|RA|=|RB|) */
+APUOP(M_DFCGT,		RR,	0x2c3,	"dfcgt",	_A3(A_T,A_A,A_B),	00112,	FX2)	/* DFCGT         RT<-(RA>RB) */
+APUOP(M_DFCMGT,		RR,	0x2cb,	"dfcmgt",	_A3(A_T,A_A,A_B),	00112,	FX2)	/* DFCMGT        RT<-(|RA|>|RB|) */
+APUOP(M_DFTSV,		RI7,	0x3bf,	"dftsv",	_A3(A_T,A_A,A_U7),	00012,	FX2)	/* DFTSV         RT<-testspecial(RA,I7) */
+
+#undef _A0
+#undef _A1
+#undef _A2
+#undef _A3
+#undef _A4
diff --git a/binutils-2.25/include/opcode/spu.h b/binutils-2.25/include/opcode/spu.h
new file mode 100644
index 00000000..c6468303
--- /dev/null
+++ b/binutils-2.25/include/opcode/spu.h
@@ -0,0 +1,125 @@
+/* SPU ELF support for BFD.
+
+   Copyright 2006, 2010 Free Software Foundation, Inc.
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+/* These two enums are from rel_apu/common/spu_asm_format.h */
+/* definition of instruction format */
+typedef enum {
+  RRR,
+  RI18,
+  RI16,
+  RI10,
+  RI8,
+  RI7,
+  RR,
+  LBT,
+  LBTI,
+  IDATA,
+  UNKNOWN_IFORMAT
+} spu_iformat;
+
+/* These values describe assembly instruction arguments.  They indicate
+ * how to encode, range checking and which relocation to use. */
+typedef enum {
+  A_T,  /* register at pos 0 */
+  A_A,  /* register at pos 7 */
+  A_B,  /* register at pos 14 */
+  A_C,  /* register at pos 21 */
+  A_S,  /* special purpose register at pos 7 */
+  A_H,  /* channel register at pos 7 */
+  A_P,  /* parenthesis, this has to separate regs from immediates */
+  A_S3,
+  A_S6,
+  A_S7N,
+  A_S7,
+  A_U7A,
+  A_U7B,
+  A_S10B,
+  A_S10,
+  A_S11,
+  A_S11I,
+  A_S14,
+  A_S16,
+  A_S18,
+  A_R18,
+  A_U3,
+  A_U5,
+  A_U6,
+  A_U7,
+  A_U14,
+  A_X16,
+  A_U18,
+  A_MAX
+} spu_aformat;
+
+enum spu_insns {
+#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
+	TAG,
+#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
+	TAG,
+#include "opcode/spu-insns.h"
+#undef APUOP
+#undef APUOPFB
+        M_SPU_MAX
+};
+
+struct spu_opcode
+{
+   spu_iformat insn_type;
+   unsigned int opcode;
+   char *mnemonic;
+   int arg[5];
+};
+
+#define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size))
+#define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1))
+
+#define DECODE_INSN_RT(insn) (insn & 0x7f)
+#define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f)
+#define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f)
+#define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f)
+
+#define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14)
+#define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14)
+
+/* For branching, immediate loads, hbr and  lqa/stqa. */
+#define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7)
+#define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7)
+
+/* for stop */
+#define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0)
+
+/* For ila */
+#define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7)
+#define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7)
+
+/* For rotate and shift and generate control mask */
+#define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14)
+#define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14)
+
+/* For float <-> int conversion */
+#define DECODE_INSN_I8(insn)  SIGNED_EXTRACT(insn,8,14)
+#define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14)
+
+/* For hbr  */
+#define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
+#define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
+#define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
+#define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
+
diff --git a/binutils-2.25/include/opcode/tahoe.h b/binutils-2.25/include/opcode/tahoe.h
new file mode 100644
index 00000000..70fcf623
--- /dev/null
+++ b/binutils-2.25/include/opcode/tahoe.h
@@ -0,0 +1,232 @@
+/*
+ * Ported by the State University of New York at Buffalo by the Distributed
+ * Computer Systems Lab, Department of Computer Science, 1991.
+ */
+/* Copyright 2012 Free Software Foundation, Inc.
+
+   This file is part of GDB and BINUTILS.
+
+   GDB and BINUTILS are free software; you can redistribute them and/or
+   modify them under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 3, or (at
+   your option) any later version.
+
+   GDB and BINUTILS are distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GDB or BINUTILS; see the file COPYING3.  If not, write
+   to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+
+#ifndef tahoe_opcodeT
+#define tahoe_opcodeT int
+#endif /* no tahoe_opcodeT */
+
+struct vot_wot                  /* tahoe opcode table: wot to do with this */
+                                /* particular opcode */
+{
+  char *            args;       /* how to compile said opcode */
+  tahoe_opcodeT       code;     /* op-code (may be > 8 bits!) */
+};
+
+struct vot                      /* tahoe opcode text */
+{
+  char *            name;       /* opcode name: lowercase string  [key]  */
+  struct vot_wot    detail;     /* rest of opcode table          [datum] */
+};
+
+#define vot_how args
+#define vot_code code
+#define vot_detail detail
+#define vot_name name
+
+static struct vot
+votstrs[] =
+{
+{    "halt",	{"",			0x00	} },
+{    "sinf",    {"",                    0x05    } },
+{    "ldf",     {"rl",                  0x06    } },
+{    "ldd",     {"rq",                  0x07    } },
+{    "addb2",	{"rbmb",		0x08	} },
+{    "movb",	{"rbwb",		0x09	} },
+{    "addw2",	{"rwmw",		0x0a	} },
+{    "movw",	{"rwww",		0x0b	} },
+{    "addl2",	{"rlml",		0x0c	} },
+{    "movl",	{"rlwl",		0x0d	} },
+{    "bbs",	{"rlvlbw",		0x0e	} },
+{    "nop",     {"",                    0x10    } },
+{    "brb",	{"bb",			0x11	} },
+{    "brw",	{"bw",			0x13	} },
+{    "cosf",    {"",                    0x15    } },
+{    "lnf",     {"rl",                  0x16    } },
+{    "lnd",     {"rq",                  0x17    } },
+{    "addb3",	{"rbrbwb",		0x18	} },
+{    "cmpb",	{"rbwb",		0x19	} }, 
+{    "addw3",	{"rwrwww",		0x1a	} },
+{    "cmpw",	{"rwww",		0x1b	} },
+{    "addl3",	{"rlrlwl",		0x1c	} },
+{    "cmpl",	{"rlwl",		0x1d	} },
+{    "bbc",	{"rlvlbw",		0x1e	} },
+{    "rei",	{"",			0x20	} },
+{    "bneq",	{"bb",			0x21	} },
+{    "bnequ",	{"bb",			0x21	} },
+{    "cvtwl",	{"rwwl",		0x23	} },
+{    "stf",     {"wl",                  0x26    } },
+{    "std",     {"wq",                  0x27    } },
+{    "subb2",	{"rbmb",		0x28	} },
+{    "mcomb",	{"rbwb",		0x29	} },
+{    "subw2",	{"rwmw",		0x2a	} },
+{    "mcomw",	{"rwww",		0x2b	} },
+{    "subl2",   {"rlml",                0x2c    } },
+{    "mcoml",   {"rlwl",                0x2d    } },
+{    "emul",	{"rlrlrlwq",		0x2e	} },
+{    "aoblss",	{"rlmlbw",		0x2f	} },
+{    "bpt",	{"",			0x30	} },
+{    "beql",	{"bb",			0x31	} },
+{    "beqlu",	{"bb",			0x31	} },
+{    "cvtwb",	{"rwwb",		0x33	} },
+{    "logf",    {"",                    0x35    } },
+{    "cmpf",    {"rl",                  0x36    } },
+{    "cmpd",    {"rq",                  0x37    } },
+{    "subb3",	{"rbrbwb",		0x38	} },
+{    "bitb",	{"rbrb",		0x39	} },
+{    "subw3",	{"rwrwww",		0x3a	} },
+{    "bitw",	{"rwrw",		0x3b	} },
+{    "subl3",	{"rlrlwl",		0x3c	} },
+{    "bitl",	{"rlrl",		0x3d	} },
+{    "ediv",	{"rlrqwlwl",		0x3e	} },
+{    "aobleq",	{"rlmlbw",		0x3f	} },
+{    "ret",	{"",			0x40	} },
+{    "bgtr",	{"bb",			0x41	} },
+{    "sqrtf",   {"",                    0x45    } },
+{    "cmpf2",   {"rl",                  0x46    } },
+{    "cmpd2",   {"rqrq",                0x47    } },
+{    "shll",    {"rbrlwl",              0x48    } },
+{    "clrb",	{"wb",			0x49	} },
+{    "shlq",	{"rbrqwq",		0x4a	} },
+{    "clrw",	{"ww",			0x4b	} },
+{    "mull2",	{"rlml",		0x4c	} },
+{    "clrl",	{"wl",			0x4d	} },
+{    "shal",    {"rbrlwl",		0x4e	} },
+{    "bleq",	{"bb",			0x51	} },
+{    "expf",    {"",                    0x55    } },
+{    "tstf",    {"",                    0x56    } },
+{    "tstd",    {"",                    0x57    } },
+{    "shrl",    {"rbrlwl",		0x58	} },
+{    "tstb",	{"rb",			0x59	} },
+{    "shrq",    {"rbrqwq",		0x5a	} },
+{    "tstw",	{"rw",			0x5b	} },
+{    "mull3",	{"rlrlwl",		0x5c	} },
+{    "tstl",	{"rl",			0x5d	} },
+{    "shar",	{"rbrlwl",		0x5e	} },
+{    "bbssi",	{"rlmlbw",		0x5f	} },
+{    "ldpctx",	{"",			0x60	} },
+{    "pushd",   {"",                    0x67    } },
+{    "incb",	{"mb",			0x69	} },
+{    "incw",	{"mw",			0x6b	} },
+{    "divl2",	{"rlml",		0x6c	} },
+{    "incl",	{"ml",			0x6d	} },
+{    "cvtlb",	{"rlwb",		0x6f	} },
+{    "svpctx",	{"",			0x70	} },
+{    "jmp",	{"ab",			0x71	} },
+{    "cvlf",    {"rl",                  0x76    } },
+{    "cvld",    {"rl",                  0x77    } },
+{    "decb",	{"mb",			0x79	} },
+{    "decw",	{"mw",			0x7b	} },
+{    "divl3",	{"rlrlwl",		0x7c	} },
+{    "decl",	{"ml",			0x7d	} },
+{    "cvtlw",	{"rlww",		0x7f	} },
+{    "bgeq",	{"bb",			0x81	} },
+{    "movs2",	{"abab",		0x82	} },
+{    "cvfl",    {"wl",                  0x86    } },
+{    "cvdl",    {"wl",                  0x87    } },
+{    "orb2",	{"rbmb",		0x88	} },
+{    "cvtbl",	{"rbwl",		0x89	} },
+{    "orw2",	{"rwmw",		0x8a	} },
+{    "bispsw",	{"rw",			0x8b	} },
+{    "orl2",    {"rlml",                0x8c    } },
+{    "adwc",	{"rlml",		0x8d	} },
+{    "adda", 	{"rlml",		0x8e	} },
+{    "blss",	{"bb",			0x91	} },
+{    "cmps2",   {"abab",		0x92	} },
+{    "ldfd",    {"rl",                  0x97    } },
+{    "orb3",	{"rbrbwb",		0x98	} },
+{    "cvtbw",	{"rbww",		0x99	} },
+{    "orw3",   	{"rwrwww",		0x9a	} },
+{    "bicpsw",	{"rw",			0x9b	} },
+{    "orl3",    {"rlrlwl",              0x9c    } },
+{    "sbwc",	{"rlml",		0x9d	} },
+{    "suba",    {"rlml",                0x9e    } },
+{    "bgtru",	{"bb",			0xa1	} },
+{    "cvdf",    {"",                    0xa6    } },
+{    "andb2",   {"rbmb",		0xa8    } },
+{    "movzbl",	{"rbwl",		0xa9	} },
+{    "andw2",   {"rwmw",		0xaa    } },
+{    "loadr",   {"rwal",		0xab	} },
+{    "andl2",   {"rlml",		0xac    } },
+{    "mtpr",	{"rlrl",		0xad	} },
+{    "ffs",	{"rlwl",		0xae	} },
+{    "blequ",	{"bb",			0xb1	} },
+{    "negf",    {"",                    0xb6    } },
+{    "negd",    {"",                    0xb7    } },
+{    "andb3",   {"rbrbwb",              0xb8    } },
+{    "movzbw",	{"rbww",		0xb9	} },
+{    "andw3",   {"rwrwww",		0xba    } },
+{    "storer",  {"rwal",                0xbb    } },
+{    "andl3",   {"rlrlwl",		0xbc    } },
+{    "mfpr",	{"rlwl",		0xbd	} },
+{    "ffc",	{"rlwl",		0xbe	} },
+{    "calls",	{"rbab",		0xbf	} },
+{    "prober",	{"rbabrl",		0xc0	} },
+{    "bvc",	{"bb",			0xc1	} },
+{    "movs3",	{"ababrw",		0xc2	} },
+{    "movzwl",	{"rwwl",		0xc3	} },
+{    "addf",    {"rl",                  0xc6    } },
+{    "addd",    {"rq",                  0xc7    } },
+{    "xorb2",   {"rbmb",                0xc8    } },
+{    "movob",   {"rbwb",                0xc9    } },
+{    "xorw2",   {"rwmw",                0xca    } },
+{    "movow",   {"rwww",                0xcb	} },
+{    "xorl2",	{"rlml",                0xcc    } },
+{    "movpsl",  {"wl",                  0xcd    } },
+{    "kcall",   {"rw",			0xcf	} },
+{    "probew",  {"rbabrl",		0xd0	} },
+{    "bvs",     {"bb",			0xd1	} },
+{    "cmps3",   {"ababrw",		0xd2	} },
+{    "subf",    {"rq",                  0xd6    } },
+{    "subd",    {"rq",                  0xd7    } },
+{    "xorb3",	{"rbrbwb",		0xd8	} },
+{    "pushb",   {"rb",			0xd9	} },
+{    "xorw3",	{"rwrwww",		0xda	} },
+{    "pushw",   {"rw", 			0xdb	} },
+{    "xorl3",	{"rlrlwl",		0xdc	} },
+{    "pushl",	{"rl",			0xdd	} },
+{    "insque",	{"abab",		0xe0	} },
+{    "bcs",	{"bb",			0xe1	} },
+{    "bgequ",	{"bb",			0xe1	} },
+{    "mulf",    {"rq",                  0xe6    } },
+{    "muld",    {"rq",                  0xe7    } },
+{    "mnegb",	{"rbwb",		0xe8	} },
+{    "movab",	{"abwl",		0xe9	} },
+{    "mnegw",	{"rwww",		0xea	} },
+{    "movaw",	{"awwl",		0xeb	} },
+{    "mnegl",	{"rlwl",		0xec	} },
+{    "moval",	{"alwl",		0xed	} },
+{    "remque",	{"ab",  		0xf0	} },
+{    "bcc",	{"bb",			0xf1	} },
+{    "blssu",	{"bb",			0xf1	} },
+{    "divf",    {"rq",                  0xf6    } },
+{    "divd",    {"rq",                  0xf7    } },
+{    "movblk",  {"alalrw",              0xf8	} },
+{    "pushab",	{"ab",			0xf9	} },
+{    "pushaw",	{"aw",			0xfb	} },
+{    "casel",	{"rlrlrl",		0xfc	} },
+{    "pushal",	{"al",			0xfd	} },
+{    "callf",	{"rbab",		0xfe	} },
+{      ""       ,   ""          } /* empty is end sentinel */
+
+};
diff --git a/binutils-2.25/include/opcode/tic30.h b/binutils-2.25/include/opcode/tic30.h
new file mode 100644
index 00000000..3f4d3071
--- /dev/null
+++ b/binutils-2.25/include/opcode/tic30.h
@@ -0,0 +1,691 @@
+/* tic30.h -- Header file for TI TMS320C30 opcode table
+   Copyright 1998, 2005, 2009, 2010 Free Software Foundation, Inc.
+   Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+/* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a
+   header file.  */
+
+#ifndef _TMS320_H_
+#define _TMS320_H_
+
+struct _register
+{
+  char *name;
+  unsigned char opcode;
+  unsigned char regtype;
+};
+
+typedef struct _register reg;
+
+#define REG_Rn    0x01
+#define REG_ARn   0x02
+#define REG_DP    0x03
+#define REG_OTHER 0x04
+
+static const reg tic30_regtab[] = {
+  { "r0", 0x00, REG_Rn },
+  { "r1", 0x01, REG_Rn },
+  { "r2", 0x02, REG_Rn },
+  { "r3", 0x03, REG_Rn },
+  { "r4", 0x04, REG_Rn },
+  { "r5", 0x05, REG_Rn },
+  { "r6", 0x06, REG_Rn },
+  { "r7", 0x07, REG_Rn },
+  { "ar0",0x08, REG_ARn },
+  { "ar1",0x09, REG_ARn },
+  { "ar2",0x0A, REG_ARn },
+  { "ar3",0x0B, REG_ARn },
+  { "ar4",0x0C, REG_ARn },
+  { "ar5",0x0D, REG_ARn },
+  { "ar6",0x0E, REG_ARn },
+  { "ar7",0x0F, REG_ARn },
+  { "dp", 0x10, REG_DP },
+  { "ir0",0x11, REG_OTHER },
+  { "ir1",0x12, REG_OTHER },
+  { "bk", 0x13, REG_OTHER },
+  { "sp", 0x14, REG_OTHER },
+  { "st", 0x15, REG_OTHER },
+  { "ie", 0x16, REG_OTHER },
+  { "if", 0x17, REG_OTHER },
+  { "iof",0x18, REG_OTHER },
+  { "rs", 0x19, REG_OTHER },
+  { "re", 0x1A, REG_OTHER },
+  { "rc", 0x1B, REG_OTHER },
+  { "R0", 0x00, REG_Rn },
+  { "R1", 0x01, REG_Rn },
+  { "R2", 0x02, REG_Rn },
+  { "R3", 0x03, REG_Rn },
+  { "R4", 0x04, REG_Rn },
+  { "R5", 0x05, REG_Rn },
+  { "R6", 0x06, REG_Rn },
+  { "R7", 0x07, REG_Rn },
+  { "AR0",0x08, REG_ARn },
+  { "AR1",0x09, REG_ARn },
+  { "AR2",0x0A, REG_ARn },
+  { "AR3",0x0B, REG_ARn },
+  { "AR4",0x0C, REG_ARn },
+  { "AR5",0x0D, REG_ARn },
+  { "AR6",0x0E, REG_ARn },
+  { "AR7",0x0F, REG_ARn },
+  { "DP", 0x10, REG_DP },
+  { "IR0",0x11, REG_OTHER },
+  { "IR1",0x12, REG_OTHER },
+  { "BK", 0x13, REG_OTHER },
+  { "SP", 0x14, REG_OTHER },
+  { "ST", 0x15, REG_OTHER },
+  { "IE", 0x16, REG_OTHER },
+  { "IF", 0x17, REG_OTHER },
+  { "IOF",0x18, REG_OTHER },
+  { "RS", 0x19, REG_OTHER },
+  { "RE", 0x1A, REG_OTHER },
+  { "RC", 0x1B, REG_OTHER },
+  { "",   0, 0 }
+};
+
+static const reg *const tic30_regtab_end
+  = tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]);
+
+/* Indirect Addressing Modes Modification Fields */
+/* Indirect Addressing with Displacement */
+#define PreDisp_Add        0x00
+#define PreDisp_Sub        0x01
+#define PreDisp_Add_Mod    0x02
+#define PreDisp_Sub_Mod    0x03
+#define PostDisp_Add_Mod   0x04
+#define PostDisp_Sub_Mod   0x05
+#define PostDisp_Add_Circ  0x06
+#define PostDisp_Sub_Circ  0x07
+/* Indirect Addressing with Index Register IR0 */
+#define PreIR0_Add         0x08
+#define PreIR0_Sub         0x09
+#define PreIR0_Add_Mod     0x0A
+#define PreIR0_Sub_Mod     0x0B
+#define PostIR0_Add_Mod    0x0C
+#define PostIR0_Sub_Mod    0x0D
+#define PostIR0_Add_Circ   0x0E
+#define PostIR0_Sub_Circ   0x0F
+/* Indirect Addressing with Index Register IR1 */
+#define PreIR1_Add         0x10
+#define PreIR1_Sub         0x11
+#define PreIR1_Add_Mod     0x12
+#define PreIR1_Sub_Mod     0x13
+#define PostIR1_Add_Mod    0x14
+#define PostIR1_Sub_Mod    0x15
+#define PostIR1_Add_Circ   0x16
+#define PostIR1_Sub_Circ   0x17
+/* Indirect Addressing (Special Cases) */
+#define IndirectOnly       0x18
+#define PostIR0_Add_BitRev 0x19
+
+typedef struct {
+  char *syntax;
+  unsigned char modfield;
+  unsigned char displacement;
+} ind_addr_type;
+
+#define IMPLIED_DISP  0x01
+#define DISP_REQUIRED 0x02
+#define NO_DISP       0x03
+
+static const ind_addr_type tic30_indaddr_tab[] = {
+  { "*+ar",       PreDisp_Add,        IMPLIED_DISP },
+  { "*-ar",       PreDisp_Sub,        IMPLIED_DISP },
+  { "*++ar",      PreDisp_Add_Mod,    IMPLIED_DISP },
+  { "*--ar",      PreDisp_Sub_Mod,    IMPLIED_DISP },
+  { "*ar++",      PostDisp_Add_Mod,   IMPLIED_DISP },
+  { "*ar--",      PostDisp_Sub_Mod,   IMPLIED_DISP },
+  { "*ar++%",     PostDisp_Add_Circ,  IMPLIED_DISP },
+  { "*ar--%",     PostDisp_Sub_Circ,  IMPLIED_DISP },
+  { "*+ar()",     PreDisp_Add,        DISP_REQUIRED },
+  { "*-ar()",     PreDisp_Sub,        DISP_REQUIRED },
+  { "*++ar()",    PreDisp_Add_Mod,    DISP_REQUIRED },
+  { "*--ar()",    PreDisp_Sub_Mod,    DISP_REQUIRED },
+  { "*ar++()",    PostDisp_Add_Mod,   DISP_REQUIRED },
+  { "*ar--()",    PostDisp_Sub_Mod,   DISP_REQUIRED },
+  { "*ar++()%",   PostDisp_Add_Circ,  DISP_REQUIRED },
+  { "*ar--()%",   PostDisp_Sub_Circ,  DISP_REQUIRED },
+  { "*+ar(ir0)",  PreIR0_Add,         NO_DISP },
+  { "*-ar(ir0)",  PreIR0_Sub,         NO_DISP },
+  { "*++ar(ir0)", PreIR0_Add_Mod,     NO_DISP },
+  { "*--ar(ir0)", PreIR0_Sub_Mod,     NO_DISP },
+  { "*ar++(ir0)", PostIR0_Add_Mod,    NO_DISP },
+  { "*ar--(ir0)", PostIR0_Sub_Mod,    NO_DISP },
+  { "*ar++(ir0)%",PostIR0_Add_Circ,   NO_DISP },
+  { "*ar--(ir0)%",PostIR0_Sub_Circ,   NO_DISP },
+  { "*+ar(ir1)",  PreIR1_Add,         NO_DISP },
+  { "*-ar(ir1)",  PreIR1_Sub,         NO_DISP },
+  { "*++ar(ir1)", PreIR1_Add_Mod,     NO_DISP },
+  { "*--ar(ir1)", PreIR1_Sub_Mod,     NO_DISP },
+  { "*ar++(ir1)", PostIR1_Add_Mod,    NO_DISP },
+  { "*ar--(ir1)", PostIR1_Sub_Mod,    NO_DISP },
+  { "*ar++(ir1)%",PostIR1_Add_Circ,   NO_DISP },
+  { "*ar--(ir1)%",PostIR1_Sub_Circ,   NO_DISP },
+  { "*ar",        IndirectOnly,       NO_DISP },
+  { "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP },
+  { "",           0,0 }
+};
+
+static const ind_addr_type *const tic30_indaddrtab_end
+  = tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]);
+
+/* Possible operand types */
+/* Register types */
+#define Rn       0x0001
+#define ARn      0x0002
+#define DPReg    0x0004
+#define OtherReg 0x0008
+/* Addressing mode types */
+#define Direct   0x0010
+#define Indirect 0x0020
+#define Imm16    0x0040
+#define Disp     0x0080
+#define Imm24    0x0100
+#define Abs24    0x0200
+/* 3 operand addressing mode types */
+#define op3T1    0x0400
+#define op3T2    0x0800
+/* Interrupt vector */
+#define IVector  0x1000
+/* Not required */
+#define NotReq   0x2000
+
+#define GAddr1   Rn | Direct | Indirect | Imm16
+#define GAddr2   GAddr1 | AllReg
+#define TAddr1   op3T1 | Rn | Indirect
+#define TAddr2   op3T2 | Rn | Indirect
+#define Reg      Rn | ARn
+#define AllReg   Reg | DPReg | OtherReg
+
+typedef struct _template
+{
+  char *name;
+  unsigned int operands; /* how many operands */
+  unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */
+  /* the bits in opcode_modifier are used to generate the final opcode from
+     the base_opcode.  These bits also are used to detect alternate forms of
+     the same instruction */
+  unsigned int opcode_modifier;
+
+  /* opcode_modifier bits: */
+#define AddressMode 0x00600000
+#define PCRel       0x02000000
+#define StackOp     0x001F0000
+#define Rotate      StackOp
+  
+  /* operand_types[i] describes the type of operand i.  This is made
+     by OR'ing together all of the possible type masks.  (e.g.
+     'operand_types[i] = Reg|Imm' specifies that operand i can be
+     either a register or an immediate operand */
+  unsigned int operand_types[3];
+  /* This defines the number type of an immediate argument to an instruction. */
+  int imm_arg_type;
+#define Imm_None  0
+#define Imm_Float 1
+#define Imm_SInt  2
+#define Imm_UInt  3
+}
+insn_template;
+
+static const insn_template tic30_optab[] = {
+  { "absf"   ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "absi"   ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "addc"   ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "addc3"  ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "addf"   ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "addf3"  ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
+  { "addi"   ,2,0x02000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "addi3"  ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "and"    ,2,0x02800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "and3"   ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "andn"   ,2,0x03000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "andn3"  ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "ash"    ,2,0x03800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ash3"   ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "b"      ,1,0x68000000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bu"     ,1,0x68000000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "blo"    ,1,0x68010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bls"    ,1,0x68020000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bhi"    ,1,0x68030000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bhs"    ,1,0x68040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "beq"    ,1,0x68050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bne"    ,1,0x68060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "blt"    ,1,0x68070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "ble"    ,1,0x68080000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bgt"    ,1,0x68090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bge"    ,1,0x680A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bz"     ,1,0x68050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnz"    ,1,0x68060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bp"     ,1,0x68090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bn"     ,1,0x68070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnn"    ,1,0x680A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnv"    ,1,0x680C0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bv"     ,1,0x680D0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnuf"   ,1,0x680E0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "buf"    ,1,0x680F0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnc"    ,1,0x68040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bc"     ,1,0x68010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnlv"   ,1,0x68100000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "blv"    ,1,0x68110000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnluf"  ,1,0x68120000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bluf"   ,1,0x68130000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bzuf"   ,1,0x68140000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bd"     ,1,0x68200000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bud"    ,1,0x68200000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "blod"   ,1,0x68210000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "blsd"   ,1,0x68220000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bhid"   ,1,0x68230000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bhsd"   ,1,0x68240000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "beqd"   ,1,0x68250000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bned"   ,1,0x68260000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bltd"   ,1,0x68270000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bled"   ,1,0x68280000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bgtd"   ,1,0x68290000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bged"   ,1,0x682A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bzd"    ,1,0x68250000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnzd"   ,1,0x68260000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bpd"    ,1,0x68290000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnd"    ,1,0x68270000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnnd"   ,1,0x682A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnvd"   ,1,0x682C0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bvd"    ,1,0x682D0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnufd"  ,1,0x682E0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bufd"   ,1,0x682F0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bncd"   ,1,0x68240000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bcd"    ,1,0x68210000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnlvd"  ,1,0x68300000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "blvd"   ,1,0x68310000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnlufd" ,1,0x68320000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "blufd"  ,1,0x68330000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bzufd"  ,1,0x68340000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "br"     ,1,0x60000000,0,           { Imm24, 0, 0 }, Imm_UInt },
+  { "brd"    ,1,0x61000000,0,           { Imm24, 0, 0 }, Imm_UInt },
+  { "call"   ,1,0x62000000,0,           { Imm24, 0, 0 }, Imm_UInt },
+  { "callu"  ,1,0x70000000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "calllo" ,1,0x70010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callls" ,1,0x70020000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callhi" ,1,0x70030000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callhs" ,1,0x70040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "calleq" ,1,0x70050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callne" ,1,0x70060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "calllt" ,1,0x70070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callle" ,1,0x70080000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callgt" ,1,0x70090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callge" ,1,0x700A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callz"  ,1,0x70050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callnz" ,1,0x70060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callp"  ,1,0x70090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "calln"  ,1,0x70070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callnn" ,1,0x700A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callnv" ,1,0x700C0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callv"  ,1,0x700D0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callnuf",1,0x700E0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "calluf" ,1,0x700F0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callnc" ,1,0x70040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callc"  ,1,0x70010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callnlv",1,0x70100000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "calllv" ,1,0x70110000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callnluf",1,0x70120000,PCRel,      { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callluf",1,0x70130000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callzuf",1,0x70140000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "cmpf"   ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "cmpf3"  ,2,0x23000000,AddressMode, { TAddr1, TAddr2, 0 }, Imm_None },
+  { "cmpi"   ,2,0x04800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "cmpi3"  ,2,0x23800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None },
+  { "db"     ,2,0x6C000000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbu"    ,2,0x6C000000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dblo"   ,2,0x6C010000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbls"   ,2,0x6C020000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbhi"   ,2,0x6C030000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbhs"   ,2,0x6C040000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbeq"   ,2,0x6C050000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbne"   ,2,0x6C060000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dblt"   ,2,0x6C070000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dble"   ,2,0x6C080000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbgt"   ,2,0x6C090000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbge"   ,2,0x6C0A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbz"    ,2,0x6C050000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnz"   ,2,0x6C060000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbp"    ,2,0x6C090000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbn"    ,2,0x6C070000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnn"   ,2,0x6C0A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnv"   ,2,0x6C0C0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbv"    ,2,0x6C0D0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnuf"  ,2,0x6C0E0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbuf"   ,2,0x6C0F0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnc"   ,2,0x6C040000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbc"    ,2,0x6C010000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnlv"  ,2,0x6C100000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dblv"   ,2,0x6C110000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnluf" ,2,0x6C120000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbluf"  ,2,0x6C130000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbzuf"  ,2,0x6C140000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbd"    ,2,0x6C200000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbud"   ,2,0x6C200000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dblod"  ,2,0x6C210000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dblsd"  ,2,0x6C220000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbhid"  ,2,0x6C230000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbhsd"  ,2,0x6C240000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbeqd"  ,2,0x6C250000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbned"  ,2,0x6C260000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbltd"  ,2,0x6C270000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbled"  ,2,0x6C280000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbgtd"  ,2,0x6C290000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbged"  ,2,0x6C2A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbzd"   ,2,0x6C250000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnzd"  ,2,0x6C260000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbpd"   ,2,0x6C290000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnd"   ,2,0x6C270000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnnd"  ,2,0x6C2A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnvd"  ,2,0x6C2C0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbvd"   ,2,0x6C2D0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnufd" ,2,0x6C2E0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbufd"  ,2,0x6C2F0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbncd"  ,2,0x6C240000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbcd"   ,2,0x6C210000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnlvd" ,2,0x6C300000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dblvd"  ,2,0x6C310000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnlufd",2,0x6C320000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dblufd" ,2,0x6C330000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbzufd" ,2,0x6C340000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "fix"    ,2,0x05000000,AddressMode, { GAddr1, AllReg, 0 }, Imm_Float },
+  { "float"  ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt },
+  { "iack"   ,1,0x1B000000,AddressMode, { Direct|Indirect, 0, 0 }, Imm_None },
+  { "idle"   ,0,0x06000000,0,           { 0, 0, 0 }, Imm_None },
+  { "idle2"  ,0,0x06000001,0,           { 0, 0, 0 }, Imm_None }, /* LC31 Only */
+  { "lde"    ,2,0x06800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldf"    ,2,0x07000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfu"   ,2,0x40000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldflo"  ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfls"  ,2,0x41000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfhi"  ,2,0x41800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfhs"  ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfeq"  ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfne"  ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldflt"  ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfle"  ,2,0x44000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfgt"  ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfge"  ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfz"   ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfnz"  ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfp"   ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfn"   ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfnn"  ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfnv"  ,2,0x46000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfv"   ,2,0x46800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfnuf" ,2,0x47000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfuf"  ,2,0x47800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfnc"  ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfc"   ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfnlv" ,2,0x48000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldflv"  ,2,0x48800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfnluf",2,0x49000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfluf" ,2,0x49800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfzuf" ,2,0x4A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfi"   ,2,0x07800000,AddressMode, { Direct|Indirect, Rn, 0 }, Imm_None },
+  { "ldi"    ,2,0x08000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldiu"   ,2,0x50000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldilo"  ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldils"  ,2,0x51000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldihi"  ,2,0x51800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldihs"  ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldieq"  ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldine"  ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldilt"  ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldile"  ,2,0x54000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldigt"  ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldige"  ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldiz"   ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldinz"  ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldip"   ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldin"   ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldinn"  ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldinv"  ,2,0x56000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldiv"   ,2,0x56800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldinuf" ,2,0x57000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldiuf"  ,2,0x57800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldinc"  ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldic"   ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldinlv" ,2,0x58000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldilv"  ,2,0x58800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldinluf",2,0x59000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldiluf" ,2,0x59800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldizuf" ,2,0x5A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldii"   ,2,0x08800000,AddressMode, { Direct|Indirect, AllReg, 0 }, Imm_None },
+  { "ldm"    ,2,0x09000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldp"    ,2,0x08700000,0,           { Abs24|Direct, DPReg|NotReq, 0 }, Imm_UInt },
+  { "lopower",0,0x10800001,0,           { 0, 0, 0 }, Imm_None }, /* LC31 Only */
+  { "lsh"    ,2,0x09800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "lsh3"   ,3,0x24000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "maxspeed",0,0x10800000,0,          { 0, 0, 0 }, Imm_None }, /* LC31 Only */
+  { "mpyf"   ,2,0x0A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "mpyf3"  ,3,0x24800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
+  { "mpyi"   ,2,0x0A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "mpyi3"  ,3,0x25000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "negb"   ,2,0x0B000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "negf"   ,2,0x0B800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "negi"   ,2,0x0C000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "nop"    ,1,0x0C800000,AddressMode, { AllReg|Indirect|NotReq, 0, 0 }, Imm_None },
+  { "norm"   ,2,0x0D000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, /*Check another source*/
+  { "not"    ,2,0x0D800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "or"     ,2,0x10000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "or3"    ,3,0x25800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "pop"    ,1,0x0E200000,StackOp,     { AllReg, 0, 0 }, Imm_None },
+  { "popf"   ,1,0x0EA00000,StackOp,     { Rn, 0, 0 }, Imm_None },
+  { "push"   ,1,0x0F200000,StackOp,     { AllReg, 0, 0 }, Imm_None },
+  { "pushf"  ,1,0x0FA00000,StackOp,     { Rn, 0, 0 }, Imm_None },
+  { "reti"   ,0,0x78000000,0,           { 0, 0, 0 }, Imm_None },
+  { "retiu"  ,0,0x78000000,0,           { 0, 0, 0 }, Imm_None },
+  { "retilo" ,0,0x78010000,0,           { 0, 0, 0 }, Imm_None },
+  { "retils" ,0,0x78020000,0,           { 0, 0, 0 }, Imm_None },
+  { "retihi" ,0,0x78030000,0,           { 0, 0, 0 }, Imm_None },
+  { "retihs" ,0,0x78040000,0,           { 0, 0, 0 }, Imm_None },
+  { "retieq" ,0,0x78050000,0,           { 0, 0, 0 }, Imm_None },
+  { "retine" ,0,0x78060000,0,           { 0, 0, 0 }, Imm_None },
+  { "retilt" ,0,0x78070000,0,           { 0, 0, 0 }, Imm_None },
+  { "retile" ,0,0x78080000,0,           { 0, 0, 0 }, Imm_None },
+  { "retigt" ,0,0x78090000,0,           { 0, 0, 0 }, Imm_None },
+  { "retige" ,0,0x780A0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retiz"  ,0,0x78050000,0,           { 0, 0, 0 }, Imm_None },
+  { "retinz" ,0,0x78060000,0,           { 0, 0, 0 }, Imm_None },
+  { "retip"  ,0,0x78090000,0,           { 0, 0, 0 }, Imm_None },
+  { "retin"  ,0,0x78070000,0,           { 0, 0, 0 }, Imm_None },
+  { "retinn" ,0,0x780A0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retinv" ,0,0x780C0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retiv"  ,0,0x780D0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retinuf",0,0x780E0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retiuf" ,0,0x780F0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retinc" ,0,0x78040000,0,           { 0, 0, 0 }, Imm_None },
+  { "retic"  ,0,0x78010000,0,           { 0, 0, 0 }, Imm_None },
+  { "retinlv",0,0x78100000,0,           { 0, 0, 0 }, Imm_None },
+  { "retilv" ,0,0x78110000,0,           { 0, 0, 0 }, Imm_None },
+  { "retinluf",0,0x78120000,0,          { 0, 0, 0 }, Imm_None },
+  { "retiluf",0,0x78130000,0,           { 0, 0, 0 }, Imm_None },
+  { "retizuf",0,0x78140000,0,           { 0, 0, 0 }, Imm_None },
+  { "rets"   ,0,0x78800000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsu"  ,0,0x78800000,0,           { 0, 0, 0 }, Imm_None },
+  { "retslo" ,0,0x78810000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsls" ,0,0x78820000,0,           { 0, 0, 0 }, Imm_None },
+  { "retshi" ,0,0x78830000,0,           { 0, 0, 0 }, Imm_None },
+  { "retshs" ,0,0x78840000,0,           { 0, 0, 0 }, Imm_None },
+  { "retseq" ,0,0x78850000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsne" ,0,0x78860000,0,           { 0, 0, 0 }, Imm_None },
+  { "retslt" ,0,0x78870000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsle" ,0,0x78880000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsgt" ,0,0x78890000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsge" ,0,0x788A0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsz"  ,0,0x78850000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsnz" ,0,0x78860000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsp"  ,0,0x78890000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsn"  ,0,0x78870000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsnn" ,0,0x788A0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsnv" ,0,0x788C0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsv"  ,0,0x788D0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsnuf",0,0x788E0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsuf" ,0,0x788F0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsnc" ,0,0x78840000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsc"  ,0,0x78810000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsnlv",0,0x78900000,0,           { 0, 0, 0 }, Imm_None },
+  { "retslv" ,0,0x78910000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsnluf",0,0x78920000,0,          { 0, 0, 0 }, Imm_None },
+  { "retsluf",0,0x78930000,0,           { 0, 0, 0 }, Imm_None },
+  { "retszuf",0,0x78940000,0,           { 0, 0, 0 }, Imm_None },
+  { "rnd"    ,2,0x11000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "rol"    ,1,0x11E00001,Rotate,      { AllReg, 0, 0 }, Imm_None },
+  { "rolc"   ,1,0x12600001,Rotate,      { AllReg, 0, 0 }, Imm_None },
+  { "ror"    ,1,0x12E0FFFF,Rotate,      { AllReg, 0, 0 }, Imm_None },
+  { "rorc"   ,1,0x1360FFFF,Rotate,      { AllReg, 0, 0 }, Imm_None },
+  { "rptb"   ,1,0x64000000,0,           { Imm24, 0, 0 }, Imm_UInt },
+  { "rpts"   ,1,0x139B0000,AddressMode, { GAddr2, 0, 0 }, Imm_UInt },
+  { "sigi"   ,0,0x16000000,0,           { 0, 0, 0 }, Imm_None },
+  { "stf"    ,2,0x14000000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float },
+  { "stfi"   ,2,0x14800000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float },
+  { "sti"    ,2,0x15000000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt },
+  { "stii"   ,2,0x15800000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt },
+  { "subb"   ,2,0x16800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "subb3"  ,3,0x26000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "subc"   ,2,0x17000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "subf"   ,2,0x17800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "subf3"  ,3,0x26800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
+  { "subi"   ,2,0x18000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "subi3"  ,3,0x27000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "subrb"  ,2,0x18800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "subrf"  ,2,0x19000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "subri"  ,2,0x19800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "swi"    ,0,0x66000000,0,           { 0, 0, 0 }, Imm_None },
+  { "trap"   ,1,0x74800020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapu"  ,1,0x74800020,0,           { IVector, 0, 0 }, Imm_None },
+  { "traplo" ,1,0x74810020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapls" ,1,0x74820020,0,           { IVector, 0, 0 }, Imm_None },
+  { "traphi" ,1,0x74830020,0,           { IVector, 0, 0 }, Imm_None },
+  { "traphs" ,1,0x74840020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapeq" ,1,0x74850020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapne" ,1,0x74860020,0,           { IVector, 0, 0 }, Imm_None },
+  { "traplt" ,1,0x74870020,0,           { IVector, 0, 0 }, Imm_None },
+  { "traple" ,1,0x74880020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapgt" ,1,0x74890020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapge" ,1,0x748A0020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapz"  ,1,0x74850020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapnz" ,1,0x74860020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapp"  ,1,0x74890020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapn"  ,1,0x74870020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapnn" ,1,0x748A0020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapnv" ,1,0x748C0020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapv"  ,1,0x748D0020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapnuf",1,0x748E0020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapuf" ,1,0x748F0020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapnc" ,1,0x74840020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapc"  ,1,0x74810020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapnlv",1,0x74900020,0,           { IVector, 0, 0 }, Imm_None },
+  { "traplv" ,1,0x74910020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapnluf",1,0x74920020,0,          { IVector, 0, 0 }, Imm_None },
+  { "trapluf",1,0x74930020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapzuf",1,0x74940020,0,           { IVector, 0, 0 }, Imm_None },
+  { "tstb"   ,2,0x1A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "tstb3"  ,2,0x27800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None },
+  { "xor"    ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "xor3"   ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { ""       ,0,0x00000000,0,           { 0, 0, 0 }, 0 }
+};
+
+static const insn_template *const tic30_optab_end =
+  tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]);
+
+typedef struct {
+  char *name;
+  unsigned int operands_1;
+  unsigned int operands_2;
+  unsigned int base_opcode;
+  unsigned int operand_types[2][3];
+  /* Which operand fits into which part of the final opcode word. */
+  int oporder;
+} partemplate;
+
+/* oporder defines - not very descriptive. */
+#define OO_4op1   0
+#define OO_4op2   1
+#define OO_4op3   2
+#define OO_5op1   3
+#define OO_5op2   4
+#define OO_PField 5
+
+static const partemplate tic30_paroptab[] = {
+  { "q_absf_stf",   2,2,0xC8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_absi_sti",   2,2,0xCA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_addf3_stf",  3,2,0xCC000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
+	OO_5op1 },
+  { "q_addi3_sti",  3,2,0xCE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
+	OO_5op1 },
+  { "q_and3_sti",   3,2,0xD0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
+	OO_5op1 },
+  { "q_ash3_sti",   3,2,0xD2000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
+	OO_5op2 },
+  { "q_fix_sti",    2,2,0xD4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_float_stf",  2,2,0xD6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_ldf_ldf",    2,2,0xC4000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } },
+	OO_4op2 },
+  { "q_ldf_stf",    2,2,0xD8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_ldi_ldi",    2,2,0xC6000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } },
+	OO_4op2 },
+  { "q_ldi_sti",    2,2,0xDA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_lsh3_sti",   3,2,0xDC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
+	OO_5op2 },
+  { "q_mpyf3_addf3",3,3,0x80000000, { { Rn | Indirect, Rn | Indirect, Rn },
+ 	                              { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
+  { "q_mpyf3_stf",  3,2,0xDE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
+	OO_5op1 },
+  { "q_mpyf3_subf3",3,3,0x84000000, { { Rn | Indirect, Rn | Indirect, Rn },
+	                              { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
+  { "q_mpyi3_addi3",3,3,0x88000000, { { Rn | Indirect, Rn | Indirect, Rn },
+	                              { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
+  { "q_mpyi3_sti",  3,2,0xE0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
+	OO_5op1 },
+  { "q_mpyi3_subi3",3,3,0x8C000000, { { Rn | Indirect, Rn | Indirect, Rn },
+	                              { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
+  { "q_negf_stf",   2,2,0xE2000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_negi_sti",   2,2,0xE4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_not_sti",    2,2,0xE6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_or3_sti",    3,2,0xE8000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
+	OO_5op1 },
+  { "q_stf_stf",    2,2,0xC0000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } },
+	OO_4op3 },
+  { "q_sti_sti",    2,2,0xC2000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } },
+	OO_4op3 },
+  { "q_subf3_stf",  3,2,0xEA000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
+	OO_5op2 },
+  { "q_subi3_sti",  3,2,0xEC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
+	OO_5op2 },
+  { "q_xor3_sti",   3,2,0xEE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
+	OO_5op1 },
+  { "",             0,0,0x00000000, { { 0, 0, 0 }, { 0, 0, 0 } }, 0 }
+};
+
+static const partemplate *const tic30_paroptab_end =
+  tic30_paroptab + sizeof(tic30_paroptab)/sizeof(tic30_paroptab[0]);
+
+#endif
diff --git a/binutils-2.25/include/opcode/tic4x.h b/binutils-2.25/include/opcode/tic4x.h
new file mode 100644
index 00000000..6f16fcb4
--- /dev/null
+++ b/binutils-2.25/include/opcode/tic4x.h
@@ -0,0 +1,1079 @@
+/* Table of opcodes for the Texas Instruments TMS320C[34]X family.
+
+   Copyright (C) 2002, 2003, 2010 Free Software Foundation.
+  
+   Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#define IS_CPU_TIC3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33)
+#define IS_CPU_TIC4X(v) ((v) ==  0 || (v) == 40 || (v) == 44)
+
+/* Define some bitfield extraction/insertion macros.  */
+#define EXTR(inst, m, l)          ((inst) << (31 - (m)) >> (31 - ((m) - (l)))) 
+#define EXTRU(inst, m, l)         EXTR ((unsigned long)(inst), (m), (l))
+#define EXTRS(inst, m, l)         EXTR ((long)(inst), (m), (l))
+#define INSERTU(inst, val, m, l)  (inst |= ((val) << (l))) 
+#define INSERTS(inst, val, m, l)  INSERTU (inst, ((val) & ((1 << ((m) - (l) + 1)) - 1)), m, l)
+
+/* Define register numbers.  */
+typedef enum
+  {
+    REG_R0, REG_R1, REG_R2, REG_R3,
+    REG_R4, REG_R5, REG_R6, REG_R7,
+    REG_AR0, REG_AR1, REG_AR2, REG_AR3,
+    REG_AR4, REG_AR5, REG_AR6, REG_AR7,
+    REG_DP, REG_IR0, REG_IR1, REG_BK,
+    REG_SP, REG_ST, REG_DIE, REG_IIE,
+    REG_IIF, REG_RS, REG_RE, REG_RC,
+    REG_R8, REG_R9, REG_R10, REG_R11,
+    REG_IVTP, REG_TVTP
+  }
+c4x_reg_t;
+
+/* Note that the actual register numbers for IVTP is 0 and TVTP is 1.  */
+
+#define REG_IE REG_DIE		/* C3x only */
+#define REG_IF REG_IIE		/* C3x only */
+#define REG_IOF REG_IIF		/* C3x only */
+
+#define TIC3X_REG_MAX REG_RC
+#define TIC4X_REG_MAX REG_TVTP
+
+/* Register table size including C4x expansion regs.  */
+#define REG_TABLE_SIZE (TIC4X_REG_MAX + 1)
+
+struct tic4x_register
+{
+  char *        name;
+  unsigned long regno;
+};
+
+typedef struct tic4x_register tic4x_register_t;
+
+/* We could store register synonyms here.  */
+static const tic4x_register_t tic3x_registers[] =
+{
+  {"f0",  REG_R0},
+  {"r0",  REG_R0},
+  {"f1",  REG_R1},
+  {"r1",  REG_R1},
+  {"f2",  REG_R2},
+  {"r2",  REG_R2},
+  {"f3",  REG_R3},
+  {"r3",  REG_R3},
+  {"f4",  REG_R4},
+  {"r4",  REG_R4},
+  {"f5",  REG_R5},
+  {"r5",  REG_R5},
+  {"f6",  REG_R6},
+  {"r6",  REG_R6},
+  {"f7",  REG_R7},
+  {"r7",  REG_R7},
+  {"ar0", REG_AR0},
+  {"ar1", REG_AR1},
+  {"ar2", REG_AR2},
+  {"ar3", REG_AR3},
+  {"ar4", REG_AR4},
+  {"ar5", REG_AR5},
+  {"ar6", REG_AR6},
+  {"ar7", REG_AR7},
+  {"dp",  REG_DP},
+  {"ir0", REG_IR0},
+  {"ir1", REG_IR1},
+  {"bk",  REG_BK},
+  {"sp",  REG_SP},
+  {"st",  REG_ST},
+  {"ie",  REG_IE},
+  {"if",  REG_IF},
+  {"iof", REG_IOF},
+  {"rs",  REG_RS},
+  {"re",  REG_RE},
+  {"rc",  REG_RC},
+  {"", 0}
+};
+
+const unsigned int tic3x_num_registers = (((sizeof tic3x_registers) / (sizeof tic3x_registers[0])) - 1);
+
+/* Define C4x registers in addition to C3x registers.  */
+static const tic4x_register_t tic4x_registers[] =
+{
+  {"die", REG_DIE},		/* Clobbers C3x REG_IE */
+  {"iie", REG_IIE},		/* Clobbers C3x REG_IF */
+  {"iif", REG_IIF},		/* Clobbers C3x REG_IOF */
+  {"f8",  REG_R8},
+  {"r8",  REG_R8},
+  {"f9",  REG_R9},
+  {"r9",  REG_R9},
+  {"f10", REG_R10},
+  {"r10", REG_R10},
+  {"f11", REG_R11},
+  {"r11", REG_R11},
+  {"ivtp", REG_IVTP},
+  {"tvtp", REG_TVTP},
+  {"", 0}
+};
+
+const unsigned int tic4x_num_registers = (((sizeof tic4x_registers) / (sizeof tic4x_registers[0])) - 1);
+
+struct tic4x_cond
+{
+  char *        name;
+  unsigned long cond;
+};
+
+typedef struct tic4x_cond tic4x_cond_t;
+
+/* Define conditional branch/load suffixes.  Put desired form for
+   disassembler last.  */
+static const tic4x_cond_t tic4x_conds[] =
+{
+  { "u",    0x00 },
+  { "c",    0x01 }, { "lo",  0x01 },
+  { "ls",   0x02 },
+  { "hi",   0x03 },
+  { "nc",   0x04 }, { "hs",  0x04 },
+  { "z",    0x05 }, { "eq",  0x05 },
+  { "nz",   0x06 }, { "ne",  0x06 },
+  { "n",    0x07 }, { "l",   0x07 }, { "lt",  0x07 },
+  { "le",   0x08 },
+  { "p",    0x09 }, { "gt",  0x09 },
+  { "nn",   0x0a }, { "ge",  0x0a },
+  { "nv",   0x0c },
+  { "v",    0x0d },
+  { "nuf",  0x0e },
+  { "uf",   0x0f },
+  { "nlv",  0x10 },
+  { "lv",   0x11 },
+  { "nluf", 0x12 },
+  { "luf",  0x13 },
+  { "zuf",  0x14 },
+  /* Dummy entry, not included in num_conds.  This
+     lets code examine entry i+1 without checking
+     if we've run off the end of the table.  */
+  { "",      0x0}
+};
+
+const unsigned int tic4x_num_conds = (((sizeof tic4x_conds) / (sizeof tic4x_conds[0])) - 1);
+
+struct tic4x_indirect
+{
+  char *        name;
+  unsigned long modn;
+};
+
+typedef struct tic4x_indirect tic4x_indirect_t;
+
+/* Define indirect addressing modes where:
+   d displacement (signed)
+   y ir0
+   z ir1  */
+
+static const tic4x_indirect_t tic4x_indirects[] =
+{
+  { "*+a(d)",   0x00 },
+  { "*-a(d)",   0x01 },
+  { "*++a(d)",  0x02 },
+  { "*--a(d)",  0x03 },
+  { "*a++(d)",  0x04 },
+  { "*a--(d)",  0x05 },
+  { "*a++(d)%", 0x06 },
+  { "*a--(d)%", 0x07 },
+  { "*+a(y)",   0x08 },
+  { "*-a(y)",   0x09 },
+  { "*++a(y)",  0x0a },
+  { "*--a(y)",  0x0b },
+  { "*a++(y)",  0x0c },
+  { "*a--(y)",  0x0d },
+  { "*a++(y)%", 0x0e },
+  { "*a--(y)%", 0x0f },
+  { "*+a(z)",   0x10 },
+  { "*-a(z)",   0x11 },
+  { "*++a(z)",  0x12 },
+  { "*--a(z)",  0x13 },
+  { "*a++(z)",  0x14 },
+  { "*a--(z)",  0x15 },
+  { "*a++(z)%", 0x16 },
+  { "*a--(z)%", 0x17 },
+  { "*a",       0x18 },
+  { "*a++(y)b", 0x19 },
+  /* Dummy entry, not included in num_indirects.  This
+     lets code examine entry i+1 without checking
+     if we've run off the end of the table.  */
+  { "",      0x0}
+};
+
+#define TIC3X_MODN_MAX 0x19
+
+const unsigned int tic4x_num_indirects = (((sizeof tic4x_indirects) / (sizeof tic4x_indirects[0])) - 1);
+
+/* Instruction template.  */
+struct tic4x_inst
+{
+  char *        name;
+  unsigned long opcode;
+  unsigned long opmask;
+  char *        args;
+  unsigned long oplevel;
+};
+
+typedef struct tic4x_inst tic4x_inst_t;
+
+/* Opcode infix
+   B  condition              16--20   U,C,Z,LO,HI, etc.
+   C  condition              23--27   U,C,Z,LO,HI, etc.
+
+   Arguments
+   ,  required arg follows
+   ;  optional arg follows
+
+   Argument types             bits    [classes] - example
+   -----------------------------------------------------------
+   *  indirect (all)          0--15   [A,AB,AU,AF,A2,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - *+AR0(5), *++AR0(IR0)
+   #  direct (for LDP)        0--15   [Z] - @start, start
+   @  direct                  0--15   [A,AB,AU,AF,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - @start, start
+   A  address register       22--24   [D] - AR0, AR7
+   B  unsigned integer        0--23   [I,I2] - @start, start  (absolute on C3x, relative on C4x)
+   C  indirect (disp - C4x)   0--7    [S,SC,S2,T,TC,T2,T2C] - *+AR0(5)
+   E  register (all)          0--7    [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
+   e  register (0-11)         0--7    [S,SC,S2] - R0, R7, R11
+   F  short float immediate   0--15   [AF,B,BA,BB] - 3.5, 0e-3.5e-1
+   G  register (all)          8--15   [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
+   g  register (0-11)         0--7    [S,SC,S2] - R0, R7, R11
+   H  register (0-7)         18--16   [LS,M,P,Q] - R0, R7
+   I  indirect (no disp)      0--7    [S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
+   i  indirect (enhanced)     0--7    [LL,LS,M,P,Q,QC] - *+AR0(1), R5
+   J  indirect (no disp)      8--15   [LL,LS,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
+   j  indirect (enhanced)     8--15   [M] - *+AR0(1), R5
+   K  register               19--21   [LL,M,Q,QC] - R0, R7
+   L  register               22--24   [LL,LS,P,Q,QC] - R0, R7
+   M  register (R2,R3)       22--22   [M] R2, R3
+   N  register (R0,R1)       23--23   [M] R0, R1
+   O  indirect(disp - C4x)    8--15   [S,SC,S2,T,TC,T2] - *+AR0(5)
+   P  displacement (PC Rel)   0--15   [D,J,JS] - @start, start
+   Q  register (all)          0--15   [A,AB,AU,A2,A3,AY,BA,BI,D,I2,J,JS] - R0, AR0, DP, SP
+   q  register (0-11)         0--15   [AF,B,BB] - R0, R7, R11
+   R  register (all)         16--20   [A,AB,AU,AF,A6,A7,R,T,TC] - R0, AR0, DP, SP
+   r  register (0-11)        16--20   [B,BA,BB,BI,B6,B7,RF,S,SC] - R0, R1, R11
+   S  short int immediate     0--15   [A,AB,AY,BI] - -5, 5
+   T  integer (C4x)          16--20   [Z] - -5, 12
+   U  unsigned integer        0--15   [AU,A3] - 0, 65535
+   V  vector (C4x: 0--8)      0--4    [Z] - 25, 7
+   W  short int (C4x)         0--7    [T,TC,T2,T2C] - -3, 5
+   X  expansion reg (C4x)     0--4    [Z] - IVTP, TVTP
+   Y  address reg (C4x)      16--20   [Z] - AR0, DP, SP, IR0
+   Z  expansion reg (C4x)    16--20   [Z] - IVTP, TVTP
+*/
+
+#define TIC4X_OPERANDS_MAX 7	/* Max number of operands for an inst.  */
+#define TIC4X_NAME_MAX 16	/* Max number of chars in parallel name.  */
+
+/* Define the instruction level */
+#define OP_C3X   0x1   /* C30 support - supported by all */
+#define OP_C4X   0x2   /* C40 support - C40, C44 */
+#define OP_ENH   0x4   /* Class LL,LS,M,P,Q,QC enhancements. Argument type
+                          I and J is enhanced in these classes - C31>=6.0,
+                          C32>=2.0, C33 */
+#define OP_LPWR  0x8   /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0,
+                          LC31, C31>=5.0, C32 */
+#define OP_IDLE2 0x10  /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0,
+                          C32, C33, C40>=5.0, C44 */
+
+/* The following class definition is a classification scheme for
+   putting instructions with similar type of arguments together. It
+   simplifies the op-code definitions significantly, as we then only
+   need to use the class macroes for 95% of the DSP's opcodes.
+*/
+
+/* A: General 2-operand integer operations
+   Syntax: <i> src, dst
+      src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
+      dst = Register (R)
+   Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI,
+                SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn,
+                MBn, MHn, MPYSHI, MPYUHI
+*/
+#define A_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \
+  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
+  { name, opcode|0x00600000, 0xffe00000, "S,R", level }
+
+/* AB: General 2-operand integer operation with condition
+   Syntax: <i>c src, dst
+       c   = Condition
+       src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
+       dst = Register (R)
+   Instr: 1/0 - LDIc
+*/
+#define AB_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x40000000, 0xf0600000, "Q;R", level }, \
+  { name, opcode|0x40200000, 0xf0600000, "@,R", level }, \
+  { name, opcode|0x40400000, 0xf0600000, "*,R", level }, \
+  { name, opcode|0x40600000, 0xf0600000, "S,R", level }
+
+/* AU: General 2-operand unsigned integer operation
+   Syntax: <i> src, dst
+        src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
+        dst = Register (R)
+   Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn
+*/
+#define AU_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \
+  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
+  { name, opcode|0x00600000, 0xffe00000, "U,R", level }
+
+/* AF: General 2-operand float to integer operation
+   Syntax: <i> src, dst
+        src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
+        dst = Register (R)
+   Instr: 1/0 - FIX
+*/
+#define AF_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "q;R", level }, \
+  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
+  { name, opcode|0x00600000, 0xffe00000, "F,R", level }
+
+/* A2: Limited 1-operand (integer) operation
+   Syntax: <i> src
+       src = Register (Q), Indirect (*), None
+   Instr: 1/0 - NOP
+*/
+#define A2_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "Q", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*", level }, \
+  { name, opcode|0x00000000, 0xffe00000, "" , level }
+
+/* A3: General 1-operand unsigned integer operation
+   Syntax: <i> src
+        src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
+   Instr: 1/0 - RPTS
+*/
+#define A3_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffff0000, "Q", level }, \
+  { name, opcode|0x00200000, 0xffff0000, "@", level }, \
+  { name, opcode|0x00400000, 0xffff0000, "*", level }, \
+  { name, opcode|0x00600000, 0xffff0000, "U", level }
+
+/* A6: Limited 2-operand integer operation
+   Syntax: <i> src, dst
+       src = Direct (@), Indirect (*)
+       dst = Register (R)
+   Instr: 1/1 - LDII, C4x: SIGI
+*/
+#define A6_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,R", level }
+
+/* A7: Limited 2-operand integer store operation
+   Syntax: <i> src, dst
+       src = Register (R)
+       dst = Direct (@), Indirect (*)
+   Instr: 2/0 - STI, STII
+*/
+#define A7_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00200000, 0xffe00000, "R,@", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "R,*", level }
+
+/* AY: General 2-operand signed address load operation
+   Syntax: <i> src, dst
+        src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
+        dst = Address register - ARx, IRx, DP, BK, SP (Y)
+   Instr: 0/1 - C4x: LDA
+   Note: Q and Y should *never* be the same register
+*/
+#define AY_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "Q,Y", level }, \
+  { name, opcode|0x00200000, 0xffe00000, "@,Y", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,Y", level }, \
+  { name, opcode|0x00600000, 0xffe00000, "S,Y", level }
+
+/* B: General 2-operand float operation
+   Syntax: <i> src, dst
+       src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
+       dst = Register 0-11 (r)
+   Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND,
+                 SUBF, SUBRF, C4x: RSQRF, TOIEEE
+*/
+#define B_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "q;r", level }, \
+  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
+  { name, opcode|0x00600000, 0xffe00000, "F,r", level }
+
+/* BA: General 2-operand integer to float operation
+   Syntax: <i> src, dst
+       src = Register (Q), Direct (@), Indirect (*), Float immediate (F)
+       dst = Register 0-11 (r)
+   Instr: 0/1 - C4x: CRCPF
+*/
+#define BA_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \
+  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
+  { name, opcode|0x00600000, 0xffe00000, "F,r", level }
+
+/* BB: General 2-operand conditional float operation
+   Syntax: <i>c src, dst
+       c   = Condition
+       src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
+       dst = Register 0-11 (r)
+   Instr: 1/0 - LDFc
+*/
+#define BB_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x40000000, 0xf0600000, "q;r", level }, \
+  { name, opcode|0x40200000, 0xf0600000, "@,r", level }, \
+  { name, opcode|0x40400000, 0xf0600000, "*,r", level }, \
+  { name, opcode|0x40600000, 0xf0600000, "F,r", level }
+
+/* BI: General 2-operand integer to float operation (yet different to BA)
+   Syntax: <i> src, dst
+       src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
+       dst = Register 0-11 (r)
+   Instr: 1/0 - FLOAT
+*/
+#define BI_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \
+  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
+  { name, opcode|0x00600000, 0xffe00000, "S,r", level }
+
+/* B6: Limited 2-operand float operation 
+   Syntax: <i> src, dst
+       src = Direct (@), Indirect (*)
+       dst = Register 0-11 (r)
+   Instr: 1/1 - LDFI, C4x: FRIEEE
+*/
+#define B6_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "*,r", level }
+
+/* B7: Limited 2-operand float store operation
+   Syntax: <i> src, dst
+       src = Register 0-11 (r)
+       dst = Direct (@), Indirect (*)
+   Instr: 2/0 - STF, STFI
+*/
+#define B7_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x00200000, 0xffe00000, "r,@", level }, \
+  { name, opcode|0x00400000, 0xffe00000, "r,*", level }
+
+/* D: Decrement and brach operations
+   Syntax: <i>c ARn, dst
+       c   = condition
+       ARn = AR register 0-7 (A)
+       dst = Register (Q), PC-relative (P)
+   Instr: 2/0 - DBc, DBcD
+   Alias: <name1> <name2>
+*/
+#define D_CLASS_INSN(name1, name2, opcode, level) \
+  { name1, opcode|0x00000000, 0xfe200000, "A,Q", level }, \
+  { name1, opcode|0x02000000, 0xfe200000, "A,P", level }, \
+  { name2, opcode|0x00000000, 0xfe200000, "A,Q", level }, \
+  { name2, opcode|0x02000000, 0xfe200000, "A,P", level }
+
+/* I: General branch operations
+   Syntax: <i> dst
+       dst = Address (B)
+   Instr: 3/1 - BR, BRD, CALL, C4x: LAJ
+*/
+
+/* I2: General branch operations (C4x addition)
+   Syntax: <i> dst
+       dst = Address (B), C4x: Register (Q)
+   Instr: 2/0 - RPTB, RPTBD
+*/
+
+/* J: General conditional branch operations
+   Syntax: <i>c dst
+       c   = Condition
+       dst = Register (Q), PC-relative (P)
+   Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc
+   Alias: <name1> <name2>
+*/
+#define J_CLASS_INSN(name1, name2, opcode, level) \
+  { name1, opcode|0x00000000, 0xffe00000, "Q", level }, \
+  { name1, opcode|0x02000000, 0xffe00000, "P", level }, \
+  { name2, opcode|0x00000000, 0xffe00000, "Q", level }, \
+  { name2, opcode|0x02000000, 0xffe00000, "P", level }
+
+/* JS: General conditional branch operations
+   Syntax: <i>c dst
+       c   = Condition
+       dst = Register (Q), PC-relative (P)
+   Instr: 1/1 - CALLc, C4X: LAJc
+*/
+
+/* LL: Load-load parallell operation
+   Syntax: <i> src2, dst2 || <i> src1, dst1
+       src1 = Indirect 0,1,IR0,IR1 (J)
+       dst1 = Register 0-7 (K)
+       src2 = Indirect 0,1,IR0,IR1, ENH: Register (i)
+       dst2 = Register 0-7 (L)
+   Instr: 2/0 - LDF||LDF, LDI||LDI
+   Alias: i||i, i1||i2, i2||i1
+*/
+#define LL_CLASS_INSN(name, opcode, level) \
+  { name "_"  name    , opcode, 0xfe000000, "i;L|J,K", level }, \
+  { name "2_" name "1", opcode, 0xfe000000, "i;L|J,K", level }, \
+  { name "1_" name "2", opcode, 0xfe000000, "J,K|i;L", level }
+
+/* LS: Store-store parallell operation
+   Syntax: <i> src2, dst2 || <i> src1, dst1
+       src1 = Register 0-7 (H)
+       dst1 = Indirect 0,1,IR0,IR1 (J)
+       src2 = Register 0-7 (L)
+       dst2 = Indirect 0,1,IR0,IR1, ENH: register (i)
+   Instr: 2/0 - STF||STF, STI||STI
+   Alias: i||i, i1||i2, i2||i1.
+*/
+#define LS_CLASS_INSN(name, opcode, level) \
+  { name "_"  name    , opcode, 0xfe000000, "L;i|H,J", level }, \
+  { name "2_" name "1", opcode, 0xfe000000, "L;i|H,J", level }, \
+  { name "1_" name "2", opcode, 0xfe000000, "H,J|L;i", level }
+
+/* M: General multiply and add/sub operations
+   Syntax: <ia> src3,src4,dst1 || <ib> src2,src1,dst2 [00] - Manual
+           <ia> src3,src1,dst1 || <ib> src2,src4,dst2 [01] - Manual
+           <ia> src1,src3,dst1 || <ib> src2,src4,dst2 [01]
+           <ia> src1,src2,dst1 || <ib> src4,src3,dst2 [02] - Manual
+           <ia> src3,src1,dst1 || <ib> src4,src2,dst2 [03] - Manual
+           <ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03]
+       src1 = Register 0-7 (K)
+       src2 = Register 0-7 (H)
+       src3 = Indirect 0,1,IR0,IR1, ENH: register (j)
+       src4 = Indirect 0,1,IR0,IR1, ENH: register (i)
+       dst1 = Register 0-1 (N)
+       dst2 = Register 2-3 (M)
+   Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3
+   Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3
+*/
+#define M_CLASS_INSN(namea, nameb, opcode, level) \
+  { namea "_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
+  { namea "_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
+  { namea "_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
+  { namea "_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
+  { namea "_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
+  { namea "_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
+  { namea "3_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
+  { namea "3_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
+  { namea "3_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
+  { namea "3_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
+  { namea "3_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
+  { namea "3_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
+  { namea "_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
+  { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
+  { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
+  { namea "_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
+  { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
+  { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
+  { namea "3_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
+  { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
+  { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
+  { namea "3_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
+  { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
+  { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
+  { nameb "_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
+  { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
+  { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
+  { nameb "_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
+  { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
+  { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
+  { nameb "3_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
+  { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
+  { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
+  { nameb "3_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
+  { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
+  { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
+  { nameb "_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
+  { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
+  { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
+  { nameb "_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
+  { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
+  { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
+  { nameb "3_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
+  { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
+  { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
+  { nameb "3_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
+  { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
+  { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }
+
+/* P: General 2-operand operation with parallell store
+   Syntax: <ia> src2, dst1 || <ib> src3, dst2
+       src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
+       dst1 = Register 0-7 (L)
+       src3 = Register 0-7 (H)
+       dst2 = Indirect 0,1,IR0,IR1 (J)
+   Instr: 9/2 - ABSF||STF, ABSI||STI, FIX||STI, FLOAT||STF, LDF||STF,
+                LDI||STI, NEGF||STF, NEGI||STI, NOT||STI, C4x: FRIEEE||STF,
+                TOIEEE||STF
+   Alias: a||b, b||a
+*/
+#define P_CLASS_INSN(namea, nameb, opcode, level) \
+  { namea "_" nameb, opcode, 0xfe000000, "i;L|H,J", level }, \
+  { nameb "_" namea, opcode, 0xfe000000, "H,J|i;L", level }
+
+/* Q: General 3-operand operation with parallell store
+   Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2
+       src1 = Register 0-7 (K)
+       src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
+       dst1 = Register 0-7 (L)
+       src3 = Register 0-7 (H)
+       dst2 = Indirect 0,1,IR0,IR1 (J)
+   Instr: 4/0 - ASH3||STI, LSH3||STI, SUBF3||STF, SUBI3||STI
+   Alias: a||b, b||a, a3||b, b||a3
+*/
+#define Q_CLASS_INSN(namea, nameb, opcode, level) \
+  { namea "_"  nameb    , opcode, 0xfe000000, "K,i;L|H,J", level }, \
+  { nameb "_"  namea    , opcode, 0xfe000000, "H,J|K,i;L", level }, \
+  { namea "3_" nameb    , opcode, 0xfe000000, "K,i;L|H,J", level }, \
+  { nameb "_"  namea "3", opcode, 0xfe000000, "H,J|K,i;L", level }
+
+/* QC: General commutative 3-operand operation with parallell store
+   Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2
+           <ia> src1, src2, dst1 || <ib> src3, dst2 - Manual
+       src1 = Register 0-7 (K)
+       src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
+       dst1 = Register 0-7 (L)
+       src3 = Register 0-7 (H)
+       dst2 = Indirect 0,1,IR0,IR1 (J)
+   Instr: 7/0 - ADDF3||STF, ADDI3||STI, AND3||STI, MPYF3||STF, MPYI3||STI,
+                OR3||STI, XOR3||STI
+   Alias: a||b, b||a, a3||b, b||a3
+*/
+#define QC_CLASS_INSN(namea, nameb, opcode, level) \
+  { namea "_"  nameb    , opcode, 0xfe000000, "i;K;L|H,J", level }, \
+  { namea "_"  nameb    , opcode, 0xfe000000, "K;i;L|H,J", level }, \
+  { nameb "_"  namea    , opcode, 0xfe000000, "H,J|i;K;L", level }, \
+  { nameb "_"  namea    , opcode, 0xfe000000, "H,J|K;i;L", level }, \
+  { namea "3_" nameb    , opcode, 0xfe000000, "i;K;L|H,J", level }, \
+  { namea "3_" nameb    , opcode, 0xfe000000, "K;i;L|H,J", level }, \
+  { nameb "_"  namea "3", opcode, 0xfe000000, "H,J|i;K;L", level }, \
+  { nameb "_"  namea "3", opcode, 0xfe000000, "H,J|K;i;L", level }
+
+/* R: General register integer operation
+   Syntax: <i> dst
+       dst = Register (R)
+   Instr: 6/0 - POP, PUSH, ROL, ROLC, ROR, RORC
+*/
+#define R_CLASS_INSN(name, opcode, level) \
+  { name, opcode, 0xffe0ffff, "R", level }
+
+/* RF: General register float operation
+   Syntax: <i> dst
+       dst = Register 0-11 (r)
+   Instr: 2/0 - POPF, PUSHF
+*/
+#define RF_CLASS_INSN(name, opcode, level) \
+  { name, opcode, 0xffe0ffff, "r", level }
+
+/* S: General 3-operand float operation
+   Syntax: <i> src2, src1, dst
+       src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
+       src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+       dst  = Register 0-11 (r)
+   Instr: 1/0 - SUBF3
+   Alias: i, i3
+*/
+#define S_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x20000000, 0xffe00000, "e,g;r", level  }, \
+  { name, opcode|0x20200000, 0xffe00000, "e,J,r", level  }, \
+  { name, opcode|0x20400000, 0xffe00000, "I,g;r", level  }, \
+  { name, opcode|0x20600000, 0xffe00000, "I,J,r", level  }, \
+  { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
+  { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \
+  { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level  }, \
+  { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level  }, \
+  { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level  }, \
+  { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level  }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
+  { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }
+
+/* SC: General commutative 3-operand float operation
+   Syntax: <i> src2, src1, dst - Manual
+           <i> src1, src2, dst
+       src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
+       src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+       dst  = Register 0-11 (r)
+   Instr: 2/0 - ADDF3, MPYF3
+   Alias: i, i3
+*/
+#define SC_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x20000000, 0xffe00000, "e,g;r", level  }, \
+  { name, opcode|0x20200000, 0xffe00000, "e,J,r", level  }, \
+  { name, opcode|0x20400000, 0xffe00000, "I,g;r", level  }, \
+  { name, opcode|0x20600000, 0xffe00000, "I,J,r", level  }, \
+  { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
+  { name, opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \
+  { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \
+  { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level  }, \
+  { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level  }, \
+  { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level  }, \
+  { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level  }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
+  { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }
+
+/* S2: General 3-operand float operation with 2 args
+   Syntax: <i> src2, src1
+       src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
+       src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+   Instr: 1/0 - CMPF3
+   Alias: i, i3
+*/
+#define S2_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x20000000, 0xffe00000, "e,g", level  }, \
+  { name, opcode|0x20200000, 0xffe00000, "e,J", level  }, \
+  { name, opcode|0x20400000, 0xffe00000, "I,g", level  }, \
+  { name, opcode|0x20600000, 0xffe00000, "I,J", level  }, \
+  { name, opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \
+  { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
+  { name "3", opcode|0x20000000, 0xffe00000, "e,g", level  }, \
+  { name "3", opcode|0x20200000, 0xffe00000, "e,J", level  }, \
+  { name "3", opcode|0x20400000, 0xffe00000, "I,g", level  }, \
+  { name "3", opcode|0x20600000, 0xffe00000, "I,J", level  }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \
+  { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
+
+/* T: General 3-operand integer operand
+   Syntax: <i> src2, src1, dst
+       src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
+       src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+       dst  = Register (R)
+   Instr: 5/0 - ANDN3, ASH3, LSH3, SUBB3, SUBI3
+   Alias: i, i3
+*/
+#define T_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x20000000, 0xffe00000, "E,G;R", level  }, \
+  { name, opcode|0x20200000, 0xffe00000, "E,J,R", level  }, \
+  { name, opcode|0x20400000, 0xffe00000, "I,G;R", level  }, \
+  { name, opcode|0x20600000, 0xffe00000, "I,J,R", level  }, \
+  { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
+  { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
+  { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
+  { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \
+  { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level  }, \
+  { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level  }, \
+  { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level  }, \
+  { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level  }, \
+  { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
+  { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
+  { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }
+
+/* TC: General commutative 3-operand integer operation
+   Syntax: <i> src2, src1, dst
+           <i> src1, src2, dst
+       src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
+       src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+       dst  = Register (R)
+   Instr: 6/2 - ADDC3, ADDI3, AND3, MPYI3, OR3, XOR3, C4x: MPYSHI, MPYUHI
+   Alias: i, i3
+*/
+#define TC_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x20000000, 0xffe00000, "E,G;R", level  }, \
+  { name, opcode|0x20200000, 0xffe00000, "E,J,R", level  }, \
+  { name, opcode|0x20400000, 0xffe00000, "I,G;R", level  }, \
+  { name, opcode|0x20600000, 0xffe00000, "I,J,R", level  }, \
+  { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
+  { name, opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \
+  { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
+  { name, opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \
+  { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
+  { name, opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \
+  { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \
+  { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level  }, \
+  { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level  }, \
+  { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level  }, \
+  { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level  }, \
+  { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
+  { name "3", opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \
+  { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
+  { name "3", opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \
+  { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }
+
+/* T2: General 3-operand integer operation with 2 args
+   Syntax: <i> src2, src1
+       src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
+       src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+   Instr: 1/0 - CMPI3
+   Alias: i, i3
+*/
+#define T2_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x20000000, 0xffe00000, "E,G", level  }, \
+  { name, opcode|0x20200000, 0xffe00000, "E,J", level  }, \
+  { name, opcode|0x20400000, 0xffe00000, "I,G", level  }, \
+  { name, opcode|0x20600000, 0xffe00000, "I,J", level  }, \
+  { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
+  { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
+  { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
+  { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
+  { name "3", opcode|0x20000000, 0xffe00000, "E,G", level  }, \
+  { name "3", opcode|0x20200000, 0xffe00000, "E,J", level  }, \
+  { name "3", opcode|0x20400000, 0xffe00000, "I,G", level  }, \
+  { name "3", opcode|0x20600000, 0xffe00000, "I,J", level  }, \
+  { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
+  { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
+  { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
+
+/* T2C: General commutative 3-operand integer operation with 2 args 
+   Syntax: <i> src2, src1 - Manual
+           <i> src1, src2 
+       src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
+       src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (0)
+   Instr: 1/0 - TSTB3
+   Alias: i, i3
+*/
+#define T2C_CLASS_INSN(name, opcode, level) \
+  { name, opcode|0x20000000, 0xffe00000, "E,G", level  }, \
+  { name, opcode|0x20200000, 0xffe00000, "E,J", level  }, \
+  { name, opcode|0x20400000, 0xffe00000, "I,G", level  }, \
+  { name, opcode|0x20600000, 0xffe00000, "I,J", level  }, \
+  { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
+  { name, opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \
+  { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
+  { name, opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \
+  { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
+  { name, opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \
+  { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
+  { name "3", opcode|0x20000000, 0xffe00000, "E,G", level  }, \
+  { name "3", opcode|0x20200000, 0xffe00000, "E,J", level  }, \
+  { name "3", opcode|0x20400000, 0xffe00000, "I,G", level  }, \
+  { name "3", opcode|0x20600000, 0xffe00000, "I,J", level  }, \
+  { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
+  { name "3", opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
+  { name "3", opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \
+  { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
+  { name "3", opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \
+  { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
+
+/* Z: Misc operations with or without arguments
+   Syntax: <i> <arg1>,...
+   Instr: 16 - RETIc, RETSc, SIGI(c3X), SWI, IDLE, IDLE2, RETIcD, 
+               TRAPc, LATc, LDEP, LDEHI, LDEPE, LDPK, STIK, LDP, IACK
+*/
+
+
+/* Define tic4x opcodes for assembler and disassembler.  */
+static const tic4x_inst_t tic4x_insts[] =
+{
+  /* Put synonyms after the desired forms in table so that they get
+     overwritten in the lookup table.  The disassembler will thus
+     print the `proper' mnemonics.  Note that the disassembler
+     only decodes the 11 MSBs, so instructions like ldp @0x500 will
+     be printed as ldiu 5, dp.  Note that with parallel instructions,
+     the second part is executed before the first part, unless
+     the sti1||sti2 form is used.  We also allow sti2||sti1
+     which is equivalent to the default sti||sti form.
+  */
+  B_CLASS_INSN(  "absf",          0x00000000, OP_C3X   ),
+  P_CLASS_INSN(  "absf",  "stf",  0xc8000000, OP_C3X   ),
+  A_CLASS_INSN(  "absi",          0x00800000, OP_C3X   ),
+  P_CLASS_INSN(  "absi",  "sti",  0xca000000, OP_C3X   ),
+  A_CLASS_INSN(  "addc",          0x01000000, OP_C3X   ),
+  TC_CLASS_INSN( "addc",          0x00000000, OP_C3X   ),
+  B_CLASS_INSN(  "addf",          0x01800000, OP_C3X   ),
+  SC_CLASS_INSN( "addf",          0x00800000, OP_C3X   ),
+  QC_CLASS_INSN( "addf",  "stf",  0xcc000000, OP_C3X   ),
+  A_CLASS_INSN(  "addi",          0x02000000, OP_C3X   ),
+  TC_CLASS_INSN( "addi",          0x01000000, OP_C3X   ),
+  QC_CLASS_INSN( "addi",  "sti",  0xce000000, OP_C3X   ),
+  AU_CLASS_INSN( "and",           0x02800000, OP_C3X   ),
+  TC_CLASS_INSN( "and",           0x01800000, OP_C3X   ),
+  QC_CLASS_INSN( "and",   "sti",  0xd0000000, OP_C3X   ),
+  AU_CLASS_INSN( "andn",          0x03000000, OP_C3X   ),
+  T_CLASS_INSN(  "andn",          0x02000000, OP_C3X   ),
+  A_CLASS_INSN(  "ash",           0x03800000, OP_C3X   ),
+  T_CLASS_INSN(  "ash",           0x02800000, OP_C3X   ),
+  Q_CLASS_INSN(  "ash",   "sti",  0xd2000000, OP_C3X   ),
+  J_CLASS_INSN(  "bB",    "b",    0x68000000, OP_C3X   ),
+  J_CLASS_INSN(  "bBd",   "bd",   0x68200000, OP_C3X   ),
+  J_CLASS_INSN(  "bBaf",  "baf",  0x68a00000, OP_C4X   ),
+  J_CLASS_INSN(  "bBat",  "bat",  0x68600000, OP_C4X   ),
+  { "br",     0x60000000, 0xff000000, "B"   , OP_C3X   },  /* I_CLASS */
+  { "brd",    0x61000000, 0xff000000, "B"   , OP_C3X   },  /* I_CLASS */
+  { "call",   0x62000000, 0xff000000, "B"   , OP_C3X   },  /* I_CLASS */
+  { "callB",  0x70000000, 0xffe00000, "Q"   , OP_C3X   },  /* JS_CLASS */
+  { "callB",  0x72000000, 0xffe00000, "P"   , OP_C3X   },  /* JS_CLASS */
+  B_CLASS_INSN(  "cmpf",          0x04000000, OP_C3X   ),
+  S2_CLASS_INSN( "cmpf",          0x03000000, OP_C3X   ),
+  A_CLASS_INSN(  "cmpi",          0x04800000, OP_C3X   ),
+  T2_CLASS_INSN( "cmpi",          0x03800000, OP_C3X   ),
+  D_CLASS_INSN(  "dbB",   "db",   0x6c000000, OP_C3X   ),
+  D_CLASS_INSN(  "dbBd",  "dbd",  0x6c200000, OP_C3X   ),
+  AF_CLASS_INSN( "fix",           0x05000000, OP_C3X   ),
+  P_CLASS_INSN(  "fix",   "sti",  0xd4000000, OP_C3X   ),
+  BI_CLASS_INSN( "float",         0x05800000, OP_C3X   ),
+  P_CLASS_INSN(  "float", "stf",  0xd6000000, OP_C3X   ),
+  B6_CLASS_INSN( "frieee",        0x1c000000, OP_C4X   ),
+  P_CLASS_INSN(  "frieee","stf",  0xf2000000, OP_C4X   ),
+  { "iack",   0x1b200000, 0xffe00000, "@"   , OP_C3X   },  /* Z_CLASS */
+  { "iack",   0x1b400000, 0xffe00000, "*"   , OP_C3X   },  /* Z_CLASS */
+  { "idle",   0x06000000, 0xffffffff, ""    , OP_C3X   },  /* Z_CLASS */
+  { "idlez",  0x06000000, 0xffffffff, ""    , OP_C3X   },  /* Z_CLASS */
+  { "idle2",  0x06000001, 0xffffffff, ""    , OP_IDLE2 },  /* Z_CLASS */
+  { "laj",    0x63000000, 0xff000000, "B"   , OP_C4X   },  /* I_CLASS */
+  { "lajB",   0x70200000, 0xffe00000, "Q"   , OP_C4X   },  /* JS_CLASS */
+  { "lajB",   0x72200000, 0xffe00000, "P"   , OP_C4X   },  /* JS_CLASS */
+  { "latB",   0x74800000, 0xffe00000, "V"   , OP_C4X   },  /* Z_CLASS */
+  A_CLASS_INSN(  "lb0",           0xb0000000, OP_C4X   ),
+  A_CLASS_INSN(  "lb1",           0xb0800000, OP_C4X   ),
+  A_CLASS_INSN(  "lb2",           0xb1000000, OP_C4X   ),
+  A_CLASS_INSN(  "lb3",           0xb1800000, OP_C4X   ),
+  AU_CLASS_INSN( "lbu0",          0xb2000000, OP_C4X   ),
+  AU_CLASS_INSN( "lbu1",          0xb2800000, OP_C4X   ),
+  AU_CLASS_INSN( "lbu2",          0xb3000000, OP_C4X   ),
+  AU_CLASS_INSN( "lbu3",          0xb3800000, OP_C4X   ),
+  AY_CLASS_INSN( "lda",           0x1e800000, OP_C4X   ),
+  B_CLASS_INSN(  "lde",           0x06800000, OP_C3X   ),
+  { "ldep",   0x76000000, 0xffe00000, "X,R" , OP_C4X   },  /* Z_CLASS */
+  B_CLASS_INSN(  "ldf",           0x07000000, OP_C3X   ),
+  LL_CLASS_INSN( "ldf",           0xc4000000, OP_C3X   ),
+  P_CLASS_INSN(  "ldf",   "stf",  0xd8000000, OP_C3X   ),
+  BB_CLASS_INSN( "ldfC",          0x00000000, OP_C3X   ),
+  B6_CLASS_INSN( "ldfi",          0x07800000, OP_C3X   ),
+  { "ldhi",   0x1fe00000, 0xffe00000, "U,R" , OP_C4X   },  /* Z_CLASS */
+  { "ldhi",   0x1fe00000, 0xffe00000, "#,R" , OP_C4X   },  /* Z_CLASS */
+  A_CLASS_INSN(  "ldi",           0x08000000, OP_C3X   ),
+  LL_CLASS_INSN( "ldi",           0xc6000000, OP_C3X   ),
+  P_CLASS_INSN(  "ldi",   "sti",  0xda000000, OP_C3X   ),
+  AB_CLASS_INSN( "ldiC",          0x10000000, OP_C3X   ),
+  A6_CLASS_INSN( "ldii",          0x08800000, OP_C3X   ),
+  { "ldp",    0x50700000, 0xffff0000, "#"   , OP_C3X   },  /* Z_CLASS - synonym for ldiu #,dp */
+  B_CLASS_INSN(  "ldm",           0x09000000, OP_C3X   ),
+  { "ldpe",   0x76800000, 0xffe00000, "Q,Z" , OP_C4X   },  /* Z_CLASS */
+  { "ldpk",   0x1F700000, 0xffff0000, "#"   , OP_C4X   },  /* Z_CLASS */
+  A_CLASS_INSN(  "lh0",           0xba000000, OP_C4X   ),
+  A_CLASS_INSN(  "lh1",           0xba800000, OP_C4X   ),
+  AU_CLASS_INSN( "lhu0",          0xbb000000, OP_C4X   ),
+  AU_CLASS_INSN( "lhu1",          0xbb800000, OP_C4X   ),
+  { "lopower", 0x10800001,0xffffffff, ""    , OP_LPWR  },  /* Z_CLASS */
+  A_CLASS_INSN(  "lsh",           0x09800000, OP_C3X   ),
+  T_CLASS_INSN(  "lsh",           0x04000000, OP_C3X   ),
+  Q_CLASS_INSN(  "lsh",   "sti",  0xdc000000, OP_C3X   ),
+  A_CLASS_INSN(  "lwl0",          0xb4000000, OP_C4X   ),
+  A_CLASS_INSN(  "lwl1",          0xb4800000, OP_C4X   ),
+  A_CLASS_INSN(  "lwl2",          0xb5000000, OP_C4X   ),
+  A_CLASS_INSN(  "lwl3",          0xb5800000, OP_C4X   ),
+  A_CLASS_INSN(  "lwr0",          0xb6000000, OP_C4X   ),
+  A_CLASS_INSN(  "lwr1",          0xb6800000, OP_C4X   ),
+  A_CLASS_INSN(  "lwr2",          0xb7000000, OP_C4X   ),
+  A_CLASS_INSN(  "lwr3",          0xb7800000, OP_C4X   ),
+  { "maxspeed",0x10800000,0xffffffff, ""    , OP_LPWR  },  /* Z_CLASS */
+  A_CLASS_INSN(  "mb0",           0xb8000000, OP_C4X   ),
+  A_CLASS_INSN(  "mb1",           0xb8800000, OP_C4X   ),
+  A_CLASS_INSN(  "mb2",           0xb9000000, OP_C4X   ),
+  A_CLASS_INSN(  "mb3",           0xb9800000, OP_C4X   ),
+  A_CLASS_INSN(  "mh0",           0xbc000000, OP_C4X   ),
+  A_CLASS_INSN(  "mh1",           0xbc800000, OP_C4X   ),
+  A_CLASS_INSN(  "mh2",           0xbd000000, OP_C4X   ),
+  A_CLASS_INSN(  "mh3",           0xbd800000, OP_C4X   ),
+  B_CLASS_INSN(  "mpyf",          0x0a000000, OP_C3X   ),
+  SC_CLASS_INSN( "mpyf",          0x04800000, OP_C3X   ),
+  M_CLASS_INSN(  "mpyf",  "addf", 0x80000000, OP_C3X   ),
+  QC_CLASS_INSN( "mpyf",  "stf",  0xde000000, OP_C3X   ),
+  M_CLASS_INSN(  "mpyf",  "subf", 0x84000000, OP_C3X   ),
+  A_CLASS_INSN(  "mpyi",          0x0a800000, OP_C3X   ),
+  TC_CLASS_INSN( "mpyi",          0x05000000, OP_C3X   ),
+  M_CLASS_INSN(  "mpyi",  "addi", 0x88000000, OP_C3X   ),
+  QC_CLASS_INSN( "mpyi",  "sti",  0xe0000000, OP_C3X   ),
+  M_CLASS_INSN(  "mpyi",  "subi", 0x8c000000, OP_C3X   ),
+  A_CLASS_INSN(  "mpyshi",        0x1d800000, OP_C4X   ),
+  TC_CLASS_INSN( "mpyshi",        0x28800000, OP_C4X   ),
+  A_CLASS_INSN(  "mpyuhi",        0x1e000000, OP_C4X   ),
+  TC_CLASS_INSN( "mpyuhi",        0x29000000, OP_C4X   ),
+  A_CLASS_INSN(  "negb",          0x0b000000, OP_C3X   ),
+  B_CLASS_INSN(  "negf",          0x0b800000, OP_C3X   ),
+  P_CLASS_INSN(  "negf",  "stf",  0xe2000000, OP_C3X   ),
+  A_CLASS_INSN(  "negi",          0x0c000000, OP_C3X   ),
+  P_CLASS_INSN(  "negi",  "sti",  0xe4000000, OP_C3X   ),
+  A2_CLASS_INSN( "nop",           0x0c800000, OP_C3X   ),
+  B_CLASS_INSN(  "norm",          0x0d000000, OP_C3X   ),
+  AU_CLASS_INSN( "not",           0x0d800000, OP_C3X   ),
+  P_CLASS_INSN(  "not",   "sti",  0xe6000000, OP_C3X   ),
+  AU_CLASS_INSN( "or",            0x10000000, OP_C3X   ),
+  TC_CLASS_INSN( "or",            0x05800000, OP_C3X   ),
+  QC_CLASS_INSN( "or",    "sti",  0xe8000000, OP_C3X   ),
+  R_CLASS_INSN(  "pop",           0x0e200000, OP_C3X   ),
+  RF_CLASS_INSN( "popf",          0x0ea00000, OP_C3X   ),
+  R_CLASS_INSN(  "push",          0x0f200000, OP_C3X   ),
+  RF_CLASS_INSN( "pushf",         0x0fa00000, OP_C3X   ),
+  BA_CLASS_INSN( "rcpf",          0x1d000000, OP_C4X   ),
+  { "retiB",  0x78000000, 0xffe00000, ""    , OP_C3X   },  /* Z_CLASS */
+  { "reti",   0x78000000, 0xffe00000, ""    , OP_C3X   },  /* Z_CLASS  - Alias for retiu */
+  { "retiBd", 0x78200000, 0xffe00000, ""    , OP_C4X   },  /* Z_CLASS */
+  { "retid",  0x78200000, 0xffe00000, ""    , OP_C4X   },  /* Z_CLASS - Alias for retiud */
+  { "retsB",  0x78800000, 0xffe00000, ""    , OP_C3X   },  /* Z_CLASS */
+  { "rets",   0x78800000, 0xffe00000, ""    , OP_C3X   },  /* Z_CLASS  - Alias for retsu */
+  B_CLASS_INSN(  "rnd",           0x11000000, OP_C3X   ),
+  R_CLASS_INSN(  "rol",           0x11e00001, OP_C3X   ),
+  R_CLASS_INSN(  "rolc",          0x12600001, OP_C3X   ),
+  R_CLASS_INSN(  "ror",           0x12e0ffff, OP_C3X   ),
+  R_CLASS_INSN(  "rorc",          0x1360ffff, OP_C3X   ),
+  { "rptb",   0x64000000, 0xff000000, "B"   , OP_C3X   },  /* I2_CLASS */
+  { "rptb",   0x79000000, 0xff000000, "Q"   , OP_C4X   },  /* I2_CLASS */
+  { "rptbd",  0x65000000, 0xff000000, "B"   , OP_C4X   },  /* I2_CLASS */ 
+  { "rptbd",  0x79800000, 0xff000000, "Q"   , OP_C4X   },  /* I2_CLASS */
+  A3_CLASS_INSN( "rpts",          0x139b0000, OP_C3X   ),
+  B_CLASS_INSN(  "rsqrf",         0x1c800000, OP_C4X   ),
+  { "sigi",   0x16000000, 0xffe00000, ""    , OP_C3X   },  /* Z_CLASS */
+  A6_CLASS_INSN( "sigi",          0x16000000, OP_C4X   ),
+  B7_CLASS_INSN( "stf",           0x14000000, OP_C3X   ),
+  LS_CLASS_INSN( "stf",           0xc0000000, OP_C3X   ),
+  B7_CLASS_INSN( "stfi",          0x14800000, OP_C3X   ),
+  A7_CLASS_INSN( "sti",           0x15000000, OP_C3X   ),
+  { "sti",    0x15000000, 0xffe00000, "T,@" , OP_C4X   },  /* Class A7 - Alias for stik */
+  { "sti",    0x15600000, 0xffe00000, "T,*" , OP_C4X   },  /* Class A7 */
+  LS_CLASS_INSN( "sti",           0xc2000000, OP_C3X   ),
+  A7_CLASS_INSN( "stii",          0x15800000, OP_C3X   ),
+  { "stik",   0x15000000, 0xffe00000, "T,@" , OP_C4X   },  /* Z_CLASS */
+  { "stik",   0x15600000, 0xffe00000, "T,*" , OP_C4X   },  /* Z_CLASS */
+  A_CLASS_INSN(  "subb",          0x16800000, OP_C3X   ),
+  T_CLASS_INSN(  "subb",          0x06000000, OP_C3X   ),
+  A_CLASS_INSN(  "subc",          0x17000000, OP_C3X   ),
+  B_CLASS_INSN(  "subf",          0x17800000, OP_C3X   ),
+  S_CLASS_INSN(  "subf",          0x06800000, OP_C3X   ),
+  Q_CLASS_INSN(  "subf",  "stf",  0xea000000, OP_C3X   ),
+  A_CLASS_INSN(  "subi",          0x18000000, OP_C3X   ),
+  T_CLASS_INSN(  "subi",          0x07000000, OP_C3X   ),
+  Q_CLASS_INSN(  "subi",  "sti",  0xec000000, OP_C3X   ),
+  A_CLASS_INSN(  "subrb",         0x18800000, OP_C3X   ),
+  B_CLASS_INSN(  "subrf",         0x19000000, OP_C3X   ),
+  A_CLASS_INSN(  "subri",         0x19800000, OP_C3X   ),
+  { "swi",    0x66000000, 0xffffffff, ""    , OP_C3X   },  /* Z_CLASS */
+  B_CLASS_INSN(  "toieee",        0x1b800000, OP_C4X   ),
+  P_CLASS_INSN(  "toieee","stf",  0xf0000000, OP_C4X   ),
+  { "trapB",  0x74000000, 0xffe00000, "V"   , OP_C3X   },  /* Z_CLASS */
+  { "trap",   0x74000000, 0xffe00000, "V"   , OP_C3X   },  /* Z_CLASS - Alias for trapu */
+  AU_CLASS_INSN( "tstb",          0x1a000000, OP_C3X   ),
+  T2C_CLASS_INSN("tstb",          0x07800000, OP_C3X   ),
+  AU_CLASS_INSN( "xor",           0x1a800000, OP_C3X   ),
+  TC_CLASS_INSN( "xor",           0x08000000, OP_C3X   ),
+  QC_CLASS_INSN( "xor",   "sti",  0xee000000, OP_C3X   ),
+
+  /* Dummy entry, not included in tic4x_num_insts.  This
+     lets code examine entry i + 1 without checking
+     if we've run off the end of the table.  */
+  { "",      0x0, 0x00, "", 0 }
+};
+
+const unsigned int tic4x_num_insts = (((sizeof tic4x_insts) / (sizeof tic4x_insts[0])) - 1);
diff --git a/binutils-2.25/include/opcode/tic54x.h b/binutils-2.25/include/opcode/tic54x.h
new file mode 100644
index 00000000..f468714e
--- /dev/null
+++ b/binutils-2.25/include/opcode/tic54x.h
@@ -0,0 +1,163 @@
+/* tic54x.h -- Header file for TI TMS320C54X opcode table
+   Copyright 1999, 2000, 2001, 2005, 2009, 2010 Free Software Foundation, Inc.
+   Written by Timothy Wall (twall@cygnus.com)
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#ifndef _opcode_tic54x_h_
+#define _opcode_tic54x_h_
+
+typedef struct _symbol
+{
+  const char *name;
+  unsigned short value;
+} symbol;
+
+enum optype {
+  OPT = 0x8000,
+  OP_None = 0x0,
+
+  OP_Xmem, /* AR3 or AR4, indirect */
+  OP_Ymem, /* AR3 or AR4, indirect */
+  OP_pmad, /* PROG mem, direct */
+  OP_dmad, /* DATA mem, direct */
+  OP_Smem,
+  OP_Lmem, /* 32-bit single-addressed (direct/indirect) */
+  OP_MMR,
+  OP_PA,
+  OP_Sind,
+  OP_xpmad,
+  OP_xpmad_ms7,
+  OP_MMRX,
+  OP_MMRY,
+
+  OP_SRC1, /* src accumulator in bit 8 */
+  OP_SRC, /* src accumulator in bit 9 */
+  OP_RND, /* rounded result dst accumulator, opposite of bit 8 */
+  OP_DST, /* dst accumulator in bit 8 */
+  OP_ARX, /* arX in bits 0-3 */
+  OP_SHIFT, /* -16 to 15 (SHIFT), bits 0-4 */
+  OP_SHFT, /*   0 to 15 (SHIFT1 in summary), bits 0-3 */
+  OP_B, /* ACC B only */
+  OP_A, /* ACC A only */
+
+  OP_lk, /* 16-bit immediate, '#' optional */
+  OP_TS,
+  OP_k8, /* -128 <= k <= 128 */
+  OP_16, /* literal "16" */
+  OP_BITC, /* 0 to 16 */
+  OP_CC, /* condition code */
+  OP_CC2, /* 4-bit condition code */
+  OP_CC3, /* 2-bit condition code */
+  OP_123, /* 1, 2, or 3 */
+  OP_031, /* 0-31, numeric */
+  OP_k5, /* 0 to 31 */
+  OP_k8u, /* 0 to 255 */
+  OP_ASM, /* "ASM" */
+  OP_T, /* "T" */
+  OP_DP, /* "DP" */
+  OP_ARP, /* "ARP" */
+  OP_k3, /* 0-7 */
+  OP_lku, /* 0 to 65535 */
+  OP_N, /* 0/1 or ST0/ST1 */
+  OP_SBIT, /* status bit or 0-15 */
+  OP_12, /* one or two */
+  OP_k9, /* 9 bits of data page (DP) address */
+  OP_TRN, /* "TRN" */
+
+};
+
+typedef struct _template
+{
+  /* The opcode mnemonic */
+  const char *name;
+  unsigned int words; /* insn size in words */
+  int minops, maxops; /* min/max operand count */
+  /* The significant bits in the opcode.  Other bits are zero. 
+     Instructions with more than 16 bits of opcode store the rest in the upper
+     16 bits.
+   */
+  unsigned short opcode;
+#define INDIRECT(OP)    ((OP)&0x80)
+#define MOD(OP)         (((OP)>>3)&0xF)
+#define ARF(OP)         ((OP)&0x7)
+#define IS_LKADDR(OP)   (INDIRECT(OP) && MOD(OP)>=12)
+#define SRC(OP)         ((OP)&0x200)
+#define DST(OP)         ((OP)&0x100)
+#define SRC1(OP)        ((OP)&0x100)
+#define SHIFT(OP)       (((OP)&0x10)?(((OP)&0x1F)-32):((OP)&0x1F))
+#define SHFT(OP)        ((OP)&0xF)
+#define ARX(OP)         ((OP)&0x7)
+#define XMEM(OP)        (((OP)&0x00F0)>>4)
+#define YMEM(OP)        ((OP)&0x000F)
+#define XMOD(C)        (((C)&0xC)>>2)
+#define XARX(C)        (((C)&0x3)+2)
+#define CC3(OP)         (((OP)>>8)&0x3)
+#define SBIT(OP)        ((OP)&0xF)
+#define MMR(OP)         ((OP)&0x7F)
+#define MMRX(OP)        ((((OP)>>4)&0xF)+16)
+#define MMRY(OP)        (((OP)&0xF)+16)
+
+#define OPTYPE(X)       ((X)&~OPT)
+
+  /* Ones in this mask indicate which bits must match the opcode field.
+     Zeroes indicate don't care bits (operands and/or opcode options) */
+  unsigned short mask;
+
+  /* An array of operand codes (at most 4 operands) */
+#define MAX_OPERANDS 4
+  enum optype operand_types[MAX_OPERANDS];
+
+  /* Special purpose flags (e.g. branch type, parallel, delay, etc) 
+   */
+  unsigned short flags;
+#define B_NEXT      0 /* normal execution, next insn is next address */
+#define B_BRANCH    1 /* next insn is in opcode */
+#define B_RET       2 /* next insn is on stack */
+#define B_BACC      3 /* next insn is in acc */
+#define B_REPEAT    4 /* next insn repeats */
+#define FL_BMASK    0x07
+
+#define FL_DELAY    0x10 /* instruction uses delay slots */
+#define FL_EXT      0x20 /* instruction takes two words */   
+#define FL_FAR      0x40 /* far mode addressing */
+#define FL_LP       0x80 /* LP-only instruction */
+#define FL_NR       0x100 /* no repeat allowed */
+#define FL_SMR      0x200 /* Smem read (for flagging write-only *+ARx */
+
+#define FL_PAR      0x400 /* Parallel instruction. */
+
+  unsigned short opcode2, mask2;   /* some insns have an extended opcode */
+
+  const char* parname;
+  enum optype paroperand_types[MAX_OPERANDS];
+
+} insn_template;
+
+extern const insn_template tic54x_unknown_opcode;
+extern const insn_template tic54x_optab[];
+extern const insn_template tic54x_paroptab[];
+extern const symbol mmregs[], regs[];
+extern const symbol condition_codes[], cc2_codes[], status_bits[];
+extern const symbol cc3_codes[];
+extern const char *misc_symbols[];
+struct disassemble_info;
+extern const insn_template* tic54x_get_insn (struct disassemble_info *, 
+                                        bfd_vma, unsigned short, int *);
+
+#endif /* _opcode_tic54x_h_ */
diff --git a/binutils-2.25/include/opcode/tic6x-control-registers.h b/binutils-2.25/include/opcode/tic6x-control-registers.h
new file mode 100644
index 00000000..b4387779
--- /dev/null
+++ b/binutils-2.25/include/opcode/tic6x-control-registers.h
@@ -0,0 +1,56 @@
+/* TI C6X control register information.
+   Copyright 2010
+   Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* Define the CTRL macro before including this file; it takes as
+   arguments the fields from tic6x_ctrl (defined in tic6x.h).  The
+   control register name is given as an identifier; the isa_variants
+   field without the leading TIC6X_INSN_; the rw field without the
+   leading tic6x_rw_.  */
+
+CTRL(amr, C62X, read_write, 0x0, 0x10)
+CTRL(csr, C62X, read_write, 0x1, 0x10)
+CTRL(dnum, C64XP, read, 0x11, 0x1f)
+CTRL(ecr, C64XP, write, 0x1d, 0x1f)
+CTRL(efr, C64XP, read, 0x1d, 0x1f)
+CTRL(fadcr, C67X, read_write, 0x12, 0x1f)
+CTRL(faucr, C67X, read_write, 0x13, 0x1f)
+CTRL(fmcr, C67X, read_write, 0x14, 0x1f)
+CTRL(gfpgfr, C64X, read_write, 0x18, 0x1f)
+CTRL(gplya, C64XP, read_write, 0x16, 0x1f)
+CTRL(gplyb, C64XP, read_write, 0x17, 0x1f)
+CTRL(icr, C62X, write, 0x3, 0x10)
+CTRL(ier, C62X, read_write, 0x4, 0x10)
+CTRL(ierr, C64XP, read_write, 0x1f, 0x1f)
+CTRL(ifr, C62X, read, 0x2, 0x1d)
+CTRL(ilc, C64XP, read_write, 0xd, 0x1f)
+CTRL(irp, C62X, read_write, 0x6, 0x10)
+CTRL(isr, C62X, write, 0x2, 0x10)
+CTRL(istp, C62X, read_write, 0x5, 0x10)
+CTRL(itsr, C64XP, read_write, 0x1b, 0x1f)
+CTRL(nrp, C62X, read_write, 0x7, 0x10)
+CTRL(ntsr, C64XP, read_write, 0x1c, 0x1f)
+CTRL(pce1, C62X, read, 0x10, 0xf)
+CTRL(rep, C64XP, read_write, 0xf, 0x1f)
+CTRL(rilc, C64XP, read_write, 0xe, 0x1f)
+CTRL(ssr, C64XP, read_write, 0x15, 0x1f)
+CTRL(tsch, C64XP, read, 0xb, 0x1f)
+/* Contrary to Table 3-26 in SPRUFE8, this register is read-write, as
+   documented in section 2.9.13.  */
+CTRL(tscl, C64XP, read_write, 0xa, 0x1f)
+CTRL(tsr, C64XP, read_write, 0x1a, 0x1f)
diff --git a/binutils-2.25/include/opcode/tic6x-insn-formats.h b/binutils-2.25/include/opcode/tic6x-insn-formats.h
new file mode 100644
index 00000000..80bc9fac
--- /dev/null
+++ b/binutils-2.25/include/opcode/tic6x-insn-formats.h
@@ -0,0 +1,616 @@
+/* TI C6X instruction format information.
+   Copyright 2010-2013 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* Define the FMT macro before including this file; it takes a name
+   and the fields from tic6x_insn_format (defined in tic6x.h).  */
+
+/* Expansion fields values for 16 bits insn.  */
+#define SAT(a) (((a) & 1) << TIC6X_COMPACT_SAT_POS)
+#define BR(a) (((a) & 1) << TIC6X_COMPACT_BR_POS)
+#define DSZ(a) (((a) & 7) << TIC6X_COMPACT_DSZ_POS)
+/* Composite fields for 16 bits insn.  */
+#define BFLD(low_pos, width, pos) { (low_pos), (width), (pos) }
+#define BFLD1(a) 1, { a }
+#define BFLD2(a, b) 2, { a, b }
+#define BFLD3(a, b, c) 3, { a, b, c }
+#define BFLD4(a, b, c, d) 4, { a, b, c, d }
+#define COMPFLD(name, bitfields) { CONCAT2(tic6x_field_,name),  bitfields }
+/**/
+#define FLD(name, pos, width) { CONCAT2(tic6x_field_,name), BFLD1(BFLD(pos, width, 0)) }
+#define CFLDS FLD(p, 0, 1), FLD(creg, 29, 3), FLD(z, 28, 1)
+#define CFLDS2(a, b) 5, { CFLDS, a, b }
+#define CFLDS3(a, b, c) 6, { CFLDS, a, b, c }
+#define CFLDS4(a, b, c, d) 7, { CFLDS, a, b, c, d }
+#define CFLDS5(a, b, c, d, e) 8, { CFLDS, a, b, c, d, e }
+#define CFLDS6(a, b, c, d, e, f) 9, { CFLDS, a, b, c, d, e, f }
+#define CFLDS7(a, b, c, d, e, f, g) 10, { CFLDS, a, b, c, d, e, f, g }
+#define CFLDS8(a, b, c, d, e, f, g, h) 11, { CFLDS, a, b, c, d, e, f, g, h }
+#define NFLDS FLD(p, 0, 1)
+#define NFLDS1(a) 2, { NFLDS, a }
+#define NFLDS2(a, b) 3, { NFLDS, a, b }
+#define NFLDS3(a, b, c) 4, { NFLDS, a, b, c }
+#define NFLDS5(a, b, c, d, e) 6, { NFLDS, a, b, c, d, e }
+#define NFLDS6(a, b, c, d, e, f) 7, { NFLDS, a, b, c, d, e, f }
+#define NFLDS7(a, b, c, d, e, f, g) 8, { NFLDS, a, b, c, d, e, f, g }
+/* 16 bits insn */
+#define FLDS1(a) 1, { a }
+#define FLDS2(a, b) 2, { a, b }
+#define FLDS3(a, b, c) 3, { a, b, c }
+#define FLDS4(a, b, c, d) 4, { a, b, c, d }
+#define FLDS5(a, b, c, d, e) 5, { a, b, c, d, e }
+#define SFLDS FLD(s, 0, 1)
+#define SFLDS1(a) 2, { SFLDS, a }
+#define SFLDS2(a, b) 3, { SFLDS, a, b }
+#define SFLDS3(a, b, c) 4, { SFLDS, a, b, c }
+#define SFLDS4(a, b, c, d) 5, { SFLDS, a, b, c, d }
+#define SFLDS5(a, b, c, d, e) 6, { SFLDS, a, b, c, d, e }
+#define SFLDS6(a, b, c, d, e, f) 7, { SFLDS, a, b, c, d, e, f }
+#define SFLDS7(a, b, c, d, e, f, g) 8, { SFLDS, a, b, c, d, e, f, g }
+/**/
+
+/* These are in the order from SPRUFE8, appendices C-H.  */
+
+/* Appendix C 32-bit formats.  */
+
+FMT(d_1_or_2_src, 32, 0x40, 0x7c,
+    CFLDS5(FLD(s, 1, 1), FLD(op, 7, 6), FLD(src1, 13, 5), FLD(src2, 18, 5),
+	   FLD(dst, 23, 5)))
+FMT(d_ext_1_or_2_src, 32, 0x830, 0xc3c,
+    CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(d_load_store, 32, 0x4, 0xc,
+    CFLDS8(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(r, 8, 1),
+	   FLD(mode, 9, 4), FLD(offsetR, 13, 5), FLD(baseR, 18, 5),
+	   FLD(srcdst, 23, 5)))
+/* The nonaligned loads and stores have the formats shown in the
+   individual instruction descriptions; the appendix is incorrect.  */
+FMT(d_load_nonaligned, 32, 0x124, 0x17c,
+    CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5),
+	   FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(dst, 24, 4)))
+FMT(d_store_nonaligned, 32, 0x174, 0x17c,
+    CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5),
+	   FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(src, 24, 4)))
+FMT(d_load_store_long, 32, 0xc, 0xc,
+    CFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15),
+	   FLD(dst, 23, 5)))
+FMT(d_adda_long, 32, 0x1000000c, 0xf000000c,
+    NFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15),
+	   FLD(dst, 23, 5)))
+
+/* Appendix C 16-bit formats will go here.  */
+
+/* C-8 */
+FMT(d_doff4_dsz_0xx, 16, DSZ(0) | 0x0004, DSZ(0x4) | 0x0406,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
+           COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) 
+FMT(d_doff4_dsz_100, 16, DSZ(4) | 0x0004, DSZ(0x7) | 0x0406,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
+           COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) 
+FMT(d_doff4_dsz_000, 16, DSZ(0) | 0x0004, DSZ(0x7) | 0x0406,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
+           COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) 
+FMT(d_doff4_dsz_x01, 16, DSZ(1) | 0x0004, DSZ(0x3) | 0x0406,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
+           COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) 
+FMT(d_doff4_dsz_01x, 16, DSZ(2) | 0x0004, DSZ(0x6) | 0x0406,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
+           COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) 
+FMT(d_doff4_dsz_111, 16, DSZ(7) | 0x0004, DSZ(0x7) | 0x0406,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
+           COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) 
+FMT(d_doff4_dsz_x11, 16, DSZ(3) | 0x0004, DSZ(0x3) | 0x0406,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
+           COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) 
+FMT(d_doff4_dsz_010, 16, DSZ(2) | 0x0004, DSZ(0x7) | 0x0406,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
+           COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) 
+FMT(d_doff4_dsz_110, 16, DSZ(6) | 0x0004, DSZ(0x7) | 0x0406,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
+           COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) 
+
+/* C-9 */
+FMT(d_doff4dw, 16, DSZ(4) | 0x0004, DSZ(0x4) | 0x0406,
+    SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
+           COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3))))) 
+
+/* C-10 */
+FMT(d_dind_dsz_0xx, 16, DSZ(0) | 0x0404, DSZ(0x4) | 0x0c06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(src1, 13, 3)))
+
+FMT(d_dind_dsz_x01, 16, DSZ(1) | 0x0404, DSZ(0x3) | 0x0c06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(src1, 13, 3)))
+
+FMT(d_dind_dsz_x11, 16, DSZ(3) | 0x0404, DSZ(0x3) | 0x0c06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(src1, 13, 3)))
+
+FMT(d_dind_dsz_01x, 16, DSZ(2) | 0x0404, DSZ(0x6) | 0x0c06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(src1, 13, 3)))
+
+FMT(d_dind_dsz_000, 16, DSZ(0) | 0x0404, DSZ(0x7) | 0x0c06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(src1, 13, 3)))
+
+FMT(d_dind_dsz_010, 16, DSZ(2) | 0x0404, DSZ(0x7) | 0x0c06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(src1, 13, 3)))
+
+FMT(d_dind_dsz_100, 16, DSZ(4) | 0x0404, DSZ(0x7) | 0x0c06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(src1, 13, 3)))
+
+FMT(d_dind_dsz_110, 16, DSZ(6) | 0x0404, DSZ(0x7) | 0x0c06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(src1, 13, 3)))
+
+FMT(d_dind_dsz_111, 16, DSZ(7) | 0x0404, DSZ(0x7) | 0x0c06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(src1, 13, 3)))
+
+/* C-11 */
+FMT(d_dinddw, 16, DSZ(4) | 0x0404, DSZ(0x4) | 0x0c06,
+    SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2),
+           FLD(sz, 9, 1), FLD(t, 12, 1), FLD(src1, 13, 3)))
+
+/* C-12 */
+FMT(d_dinc_dsz_x01, 16, DSZ(1) | 0x0c04, DSZ(0x3) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_dinc_dsz_0xx, 16, DSZ(0) | 0x0c04, DSZ(0x4) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_dinc_dsz_01x, 16, DSZ(2) | 0x0c04, DSZ(0x6) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_dinc_dsz_x11,16, DSZ(3) | 0x0c04, DSZ(0x3) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_dinc_dsz_000, 16, DSZ(0) | 0x0c04, DSZ(0x7) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_dinc_dsz_010, 16, DSZ(2) | 0x0c04, DSZ(0x7) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_dinc_dsz_100, 16, DSZ(4) | 0x0c04, DSZ(0x7) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_dinc_dsz_110, 16, DSZ(6) | 0x0c04, DSZ(0x7) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_dinc_dsz_111, 16, DSZ(7) | 0x0c04, DSZ(0x7) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+/* C-13*/
+FMT(d_dincdw, 16, DSZ(4) | 0x0c04, DSZ(0x4) | 0xcc06,
+    SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2),
+           FLD(sz, 9, 1), FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+/* C-14 */
+FMT(d_ddec_dsz_01x, 16, DSZ(2) | 0x4c04, DSZ(0x6) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_ddec_dsz_0xx, 16, DSZ(0) | 0x4c04, DSZ(0x4) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_ddec_dsz_x01, 16, DSZ(1) | 0x4c04, DSZ(0x3) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_ddec_dsz_x11, 16, DSZ(3) | 0x4c04, DSZ(0x3) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_ddec_dsz_000, 16, DSZ(0) | 0x4c04, DSZ(0x7) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_ddec_dsz_010, 16, DSZ(2) | 0x4c04, DSZ(0x7) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_ddec_dsz_100, 16, DSZ(4) | 0x4c04, DSZ(0x7) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_ddec_dsz_110, 16, DSZ(6) | 0x4c04, DSZ(0x7) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+FMT(d_ddec_dsz_111, 16, DSZ(7) | 0x4c04, DSZ(0x7) | 0xcc06,
+    SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
+           FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+/* C-15 */
+FMT(d_ddecdw, 16, DSZ(4) | 0x4c04, DSZ(0x4) | 0xcc06,
+    SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1),  FLD(srcdst, 5, 2), FLD(ptr, 7, 2),
+           FLD(sz, 9, 1), FLD(t, 12, 1), FLD(cst, 13, 1)))
+
+/* C-16 */
+FMT(d_dstk, 16, 0x8c04, 0x8c06,
+    SFLDS4(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(t, 12, 1),
+           COMPFLD(cst, BFLD2(BFLD(7, 3, 2), BFLD(13, 2, 0)))))
+
+/* C-17 */
+FMT(d_dx2op, 16, 0x0036, 0x047e,
+    SFLDS4(FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), FLD(srcdst, 13, 3)))
+
+/* C-18 */
+FMT(d_dx5, 16, 0x0436, 0x047e,
+    SFLDS2(FLD(dst, 7, 3), 
+           COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
+
+/* C-19 */
+FMT(d_dx5p, 16, 0x0c76, 0x1c7e,
+    SFLDS2(FLD(op, 7, 1),
+           COMPFLD(cst, BFLD2(BFLD(8, 2, 3), BFLD(13, 3, 0)))))
+
+/* C-20 */
+FMT(d_dx1, 16, 0x1876, 0x1c7e,
+    SFLDS2(FLD(srcdst, 7, 3), FLD(op, 13, 3)))
+
+/* C-21 */
+FMT(d_dpp, 16, 0x0077, 0x087f,
+    SFLDS5(FLD(srcdst, 7, 4), FLD(t, 12, 1), FLD(cst, 13, 1), FLD(op, 14, 1),
+           FLD(dw, 15, 1)))
+
+/* Appendix D 32-bit formats.  */
+
+FMT(l_1_or_2_src, 32, 0x18, 0x1c,
+    CFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(l_1_or_2_src_noncond, 32, 0x10000018, 0xf000001c,
+    NFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(l_unary, 32, 0x358, 0xffc,
+    CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
+	   FLD(dst, 23, 5)))
+
+/* Appendix D 16-bit formats will go here.  */
+
+/* D-4 */
+FMT(l_l3_sat_0, 16, SAT(0) | 0x0000, SAT(1) | 0x040e,
+    SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
+           FLD(src1, 13, 3)))
+
+FMT(l_l3_sat_1, 16, SAT(1) | 0x0000, SAT(1) | 0x040e,
+    SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
+           FLD(src1, 13, 3)))
+
+/* D-5 - combine cst3 and n fields into a single field cst */
+FMT(l_l3i, 16, 0x0400, 0x040e,
+    SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(sn, 11, 1), FLD(x, 12, 1),
+           COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
+
+/* D-6 Mtbd ? */
+
+/* D-7 */
+FMT(l_l2c, 16, 0x0408, 0x040e,
+    SFLDS5(FLD(dst, 4, 1), FLD(src2, 7, 3), FLD(x, 12, 1), FLD(src1, 13, 3),
+           COMPFLD(op, BFLD2(BFLD(5, 2, 0), BFLD(11, 1, 2)))))
+
+/* D-8 */
+FMT(l_lx5, 16, 0x0426, 0x047e,
+    SFLDS2(FLD(dst, 7, 3),
+           COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
+
+/* D-9 */
+FMT(l_lx3c, 16, 0x0026, 0x147e,
+    SFLDS3(FLD(src2, 7, 3), FLD(dst, 11, 1), FLD(cst, 13, 3)))
+
+/* D-10 */
+FMT(l_lx1c, 16, 0x1026, 0x147e,
+    SFLDS4(FLD(src2, 7, 3), FLD(dst, 11, 1), FLD(cst, 13, 1), FLD(op, 14, 2)))
+
+/* D-11 */
+FMT(l_lx1, 16, 0x1866, 0x1c7e,
+    SFLDS2(FLD(srcdst, 7, 3), FLD(op, 13, 3)))
+
+/* Appendix E 32-bit formats.  */
+
+FMT(m_compound, 32, 0x30, 0x83c,
+    CFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(m_1_or_2_src, 32, 0x10000030, 0xf000083c,
+    NFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+/* Contrary to SPRUFE8, this does have predicate fields.  */
+FMT(m_unary, 32, 0xf0, 0xffc,
+    CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
+	   FLD(dst, 23, 5)))
+
+/* M-unit formats missing from Appendix E.  */
+FMT(m_mpy, 32, 0x0, 0x7c,
+    CFLDS6(FLD(s, 1, 1), FLD(op, 7, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+
+/* Appendix E 16-bit formats will go here.  */
+FMT(m_m3_sat_0, 16, SAT(0) | 0x001e, SAT(1) | 0x001e,
+    SFLDS5(FLD(op, 5, 2), FLD(src2, 7, 3), FLD(dst, 10, 2),
+           FLD(x, 12, 1), FLD(src1, 13, 3)))
+FMT(m_m3_sat_1, 16, SAT(1) | 0x001e, SAT(1) | 0x001e,
+    SFLDS5(FLD(op, 5, 2), FLD(src2, 7, 3), FLD(dst, 10, 2),
+           FLD(x, 12, 1), FLD(src1, 13, 3)))
+
+/* Appendix F 32-bit formats.  */
+
+FMT(s_1_or_2_src, 32, 0x20, 0x3c,
+    CFLDS6(FLD(s, 1, 1), FLD(op, 6, 6), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23 ,5)))
+FMT(s_ext_1_or_2_src, 32, 0xc30, 0xc3c,
+    CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+FMT(s_ext_1_or_2_src_noncond, 32, 0xc30, 0xe0000c3c,
+    NFLDS7(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5), FLD(z, 28, 1)))
+FMT(s_unary, 32, 0xf20, 0xffc,
+    CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
+	   FLD(dst, 23, 5)))
+FMT(s_ext_branch_cond_imm, 32, 0x10, 0x7c,
+    CFLDS2(FLD(s, 1, 1), FLD(cst, 7, 21)))
+FMT(s_call_imm_nop, 32, 0x10, 0xe000007c,
+    NFLDS3(FLD(s, 1, 1), FLD(cst, 7, 21), FLD(z, 28, 1)))
+FMT(s_branch_nop_cst, 32, 0x120, 0x1ffc,
+    CFLDS3(FLD(s, 1, 1), FLD(src1, 13, 3), FLD(src2, 16, 12)))
+FMT(s_branch_nop_reg, 32, 0x800360, 0xf830ffc,
+    CFLDS4(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src1, 13, 3), FLD(src2, 18, 5)))
+FMT(s_branch, 32, 0x360, 0xf83effc,
+    CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src2, 18, 5)))
+FMT(s_mvk, 32, 0x28, 0x3c,
+    CFLDS4(FLD(s, 1, 1), FLD(h, 6, 1), FLD(cst, 7, 16), FLD(dst, 23, 5)))
+FMT(s_field, 32, 0x8, 0x3c,
+    CFLDS6(FLD(s, 1, 1), FLD(op, 6, 2), FLD(cstb, 8, 5), FLD(csta, 13, 5),
+	   FLD(src2, 18, 5), FLD(dst, 23, 5)))
+
+/* S-unit formats missing from Appendix F.  */
+FMT(s_addk, 32, 0x50, 0x7c,
+    CFLDS3(FLD(s, 1, 1), FLD(cst, 7, 16), FLD(dst, 23, 5)))
+FMT(s_addkpc, 32, 0x160, 0x1ffc,
+    CFLDS4(FLD(s, 1, 1), FLD(src2, 13, 3), FLD(src1, 16, 7), FLD(dst, 23, 5)))
+FMT(s_b_irp, 32, 0x1800e0, 0x7feffc,
+    CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5)))
+FMT(s_b_nrp, 32, 0x1c00e0, 0x7feffc,
+    CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5)))
+FMT(s_bdec, 32, 0x1020, 0x1ffc,
+    CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5)))
+FMT(s_bpos, 32, 0x20, 0x1ffc,
+    CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5)))
+
+/* Appendix F 16-bit formats will go here.  */
+
+/* F-17 Sbs7 Instruction Format */
+FMT(s_sbs7, 16, BR(1) | 0x000a, BR(1) | 0x003e,
+    SFLDS2(FLD(cst, 6, 7), FLD(n, 13, 3)))
+
+/* F-18 Sbu8 Instruction Format */
+FMT(s_sbu8, 16, BR(1) | 0xc00a, BR(1) | 0xc03e,
+    SFLDS1(FLD(cst, 6, 8)))
+
+/* F-19 Scs10 Instruction Format */
+FMT(s_scs10, 16, BR(1) | 0x001a, BR(1) | 0x003e,
+    SFLDS1(FLD(cst, 6, 10)))
+
+/* F-20 Sbs7c Instruction Format */
+FMT(s_sbs7c, 16, BR(1) | 0x002a, BR(1) | 0x002e,
+    SFLDS3(FLD(z, 4, 1), FLD(cst, 6, 7), FLD(n, 13, 3)))
+
+/* F-21 Sbu8c Instruction Format */
+FMT(s_sbu8c, 16, BR(1) | 0xc02a, BR(1) |  0xc02e,
+    SFLDS2(FLD(z, 4, 1), FLD(cst, 6, 8)))
+
+/* F-22 S3 Instruction Format */
+FMT(s_s3, 16, BR(0) | 0x000a, BR(1) | 0x040e,
+    SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
+          FLD(src1, 13, 3)))
+
+FMT(s_s3_sat_x, 16, BR(0) | SAT(0) | 0x000a, BR(1) | SAT(0) | 0x040e,
+    SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
+          FLD(src1, 13, 3)))
+
+FMT(s_s3_sat_0, 16, BR(0) | SAT(0) | 0x000a, BR(1) | SAT(1) | 0x040e,
+    SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
+          FLD(src1, 13, 3)))
+
+FMT(s_s3_sat_1, 16, BR(0) | SAT(1) | 0x000a, BR(1) | SAT(1) |	 0x040e,
+    SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
+          FLD(src1, 13, 3)))
+
+/* F-23 S3i Instruction Format */
+FMT(s_s3i, 16, BR(0) | 0x040a, BR(1) | 0x040e,
+    SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
+           FLD(cst, 13, 3)))
+
+/* F-24 Smvk8 Instruction Format */
+FMT(s_smvk8, 16, 0x0012, 0x001e,
+    SFLDS2(FLD(dst, 7, 3),
+           COMPFLD(cst, BFLD4(BFLD(10, 1, 7), BFLD(5, 2, 5), BFLD(11, 2, 3), BFLD(13, 3, 0)))))
+
+/* F-25 Ssh5 Instruction Format */
+FMT(s_ssh5_sat_x, 16, SAT(0) | 0x0402, SAT(0) | 0x041e,
+    SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3),
+           COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
+FMT(s_ssh5_sat_0, 16, SAT(0) | 0x0402, SAT(1) | 0x041e,
+    SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3),
+           COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
+FMT(s_ssh5_sat_1, 16, SAT(1) | 0x0402, SAT(1) | 0x041e,
+    SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3),
+           COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
+
+/* F-26 S2sh Instruction Format */
+FMT(s_s2sh, 16, 0x0462, 0x047e,
+    SFLDS3(FLD(srcdst, 7, 3), FLD(op, 11, 2), FLD(src1, 13, 3)))
+
+/* F-27 Sc5 Instruction Format */
+FMT(s_sc5, 16, 0x0002, 0x041e,
+    SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3),
+           COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
+
+/* F-28 S2ext Instruction Format */
+FMT(s_s2ext, 16, 0x0062, 0x047e,
+    SFLDS3(FLD(src, 7, 3), FLD(op, 11, 2), FLD(dst, 13, 3)))
+
+/* F-29 Sx2op Instruction Format */
+FMT(s_sx2op, 16, 0x002e, 0x047e,
+    SFLDS4(FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
+           FLD(srcdst, 13, 3)))
+
+/* F-30 Sx5 Instruction Format */
+FMT(s_sx5, 16, 0x042e, 0x047e,
+    SFLDS2(FLD(dst, 7, 3),
+           COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
+
+/* F-31 Sx1 Instruction Format */
+FMT(s_sx1, 16, 0x186e, 0x1c7e,
+    SFLDS2(FLD(srcdst, 7, 3), FLD(op, 13, 3)))
+
+/* F-32 Sx1b Instruction Format */
+FMT(s_sx1b, 16, 0x006e, 0x187e,
+    SFLDS2(FLD(src2, 7, 4), FLD(n, 13, 3)))
+
+/* Appendix G 16-bit formats will go here.  */
+FMT(lsdmvto, 16, 0x0006, 0x0066,
+    SFLDS4(FLD(unit, 3, 2), 
+           FLD(x, 12, 1), FLD(dst, 13, 3),
+           COMPFLD(src2, BFLD2(BFLD(10, 2, 3), BFLD(7, 3, 0)))))
+
+FMT(lsdmvfr, 16, 0x0046, 0x0066,
+    SFLDS4(FLD(unit, 3, 2), FLD(src2, 7, 3), FLD(x, 12, 1),
+           COMPFLD(dst, BFLD2(BFLD(10, 2, 3), BFLD(13, 3, 0)))))
+
+/* G-3 */
+FMT(lsdx1c, 16, 0x0866, 0x1c66,
+    SFLDS4(FLD(unit, 3, 2), FLD(dst, 7, 3), FLD(cst, 13, 1),
+           FLD(cc, 14, 2)))
+
+/* G-4 */
+FMT(lsdx1, 16, 0x1866, 0x1c66,
+    SFLDS3(FLD(unit, 3, 2), FLD(srcdst, 7, 3), FLD(op, 13, 3)))
+
+/* Appendix H 32-bit formats.  */
+
+FMT(nfu_loop_buffer, 32, 0x00020000, 0x00021ffc,
+    CFLDS4(FLD(s, 1, 1), FLD(op, 13, 4), FLD(csta, 18, 5), FLD(cstb, 23, 5)))
+/* Corrected relative to Appendix H.  */
+FMT(nfu_nop_idle, 32, 0x00000000, 0xfffe1ffc,
+    NFLDS2(FLD(s, 1, 1), FLD(op, 13, 4)))
+
+/* No-unit formats missing from Appendix H (given the NOP and IDLE
+   correction).  */
+FMT(nfu_dint, 32, 0x10004000, 0xfffffffc,
+    NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_rint, 32, 0x10006000, 0xfffffffc,
+    NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_swe, 32, 0x10000000, 0xfffffffc,
+    NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_swenr, 32, 0x10002000, 0xfffffffc,
+    NFLDS1(FLD(s, 1, 1)))
+/* Although formally covered by the loop buffer format, the fields in
+   that format are not useful for all such instructions and not all
+   instructions can be predicated.  */
+FMT(nfu_spkernel, 32, 0x00034000, 0xf03ffffc,
+    NFLDS2(FLD(s, 1, 1), FLD(fstgfcyc, 22, 6)))
+FMT(nfu_spkernelr, 32, 0x00036000, 0xfffffffc,
+    NFLDS1(FLD(s, 1, 1)))
+FMT(nfu_spmask, 32, 0x00020000, 0xfc021ffc,
+    NFLDS3(FLD(s, 1, 1), FLD(op, 13, 4), FLD(mask, 18, 8)))
+
+/* Appendix H 16-bit formats will go here.  */
+
+/* H-5 */
+FMT(nfu_uspl, 16, 0x0c66, 0xbc7e,
+   FLDS2(FLD(op, 0, 1), COMPFLD(ii, BFLD2(BFLD(7, 3, 0), BFLD(14, 1, 3)))))
+
+/* H-6 */
+/* make up some fields to pretend to have s and z fields s for this format
+   so as to fit in other predicated compact instruction to avoid special-
+   casing this instruction in tic6x-dis.c 
+   use op field as a predicate adress register selector (s field)
+   use the first zeroed bit as a z value as this insn only supports [a0]
+   and [b0] predicate forms.
+*/
+FMT(nfu_uspldr, 16, 0x8c66, 0xbc7e,
+   FLDS4(FLD(op, 0, 1), FLD(s, 0, 1), FLD(z, 3, 1),
+         COMPFLD(ii, BFLD2(BFLD(7, 3, 0), BFLD(14, 1, 3)))))
+
+/* H-7 */
+FMT(nfu_uspk, 16, 0x1c66, 0x3c7e,
+   FLDS1(COMPFLD(fstgfcyc, BFLD3(BFLD(0, 1, 0), BFLD(7, 3, 1), BFLD(14, 2, 4)))))
+
+/* H-8a */
+FMT(nfu_uspma, 16, 0x2c66, 0x3c7e,
+   FLDS1(COMPFLD(mask, BFLD3(BFLD(0, 1, 0), BFLD(7, 3, 1), BFLD(14, 2, 4)))))
+
+/* H-8b */
+FMT(nfu_uspmb, 16, 0x3c66, 0x3c7e,
+   FLDS1(COMPFLD(mask, BFLD3(BFLD(0, 1, 0), BFLD(7, 3, 1), BFLD(14, 2, 4)))))
+
+/* H-9 */
+FMT(nfu_unop, 16, 0x0c6e, 0x1fff,
+   FLDS1(FLD(n, 13, 3)))
+
+#undef FLD
+#undef CFLDS
+#undef CFLDS2
+#undef CFLDS3
+#undef CFLDS4
+#undef CFLDS5
+#undef CFLDS6
+#undef CFLDS7
+#undef CFLDS8
+#undef NFLDS
+#undef NFLDS1
+#undef NFLDS2
+#undef NFLDS3
+#undef NFLDS5
+#undef NFLDS6
+#undef NFLDS7
+#undef SFLDS
+#undef SFLDS1
+#undef SFLDS2
+#undef SFLDS3
+#undef SFLDS4
+#undef SFLDS5
+#undef SFLDS6
+#undef SFLDS7
+#undef BFLD
+#undef BFLD1
+#undef BFLD2
+#undef BFLD3
+#undef BFLD4
+#undef FLDS1
+#undef FLDS2
+#undef FLDS3
+#undef FLDS4
+#undef FLDS5
+#undef COMPFLD
+#undef DSZ
+#undef BR
+#undef SAT
diff --git a/binutils-2.25/include/opcode/tic6x-opcode-table.h b/binutils-2.25/include/opcode/tic6x-opcode-table.h
new file mode 100644
index 00000000..d876c564
--- /dev/null
+++ b/binutils-2.25/include/opcode/tic6x-opcode-table.h
@@ -0,0 +1,3677 @@
+/* TI C6X opcode table.
+   Copyright 2010-2013 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* Define the INSN macro before including this file; it takes as
+   arguments the fields from tic6x_opcode (defined in tic6x.h).  The
+   name is given as an identifier; the subsequent four operands should
+   have "tic6x_func_unit_", "tic6x_insn_format_", "tic6x_pipeline_"
+   and "TIC6X_INSN_", respectively, prepended to them by the macro
+   definition.  Also define INSNE, which has a second argument that
+   goes after tic6x_opcode_NAME_ to form the enumeration value for
+   this instruction, where the value otherwise formed from the name,
+   functional unit and format is ambiguous, but otherwise has the same
+   arguments as INSN.  */
+
+#define TIC6X_INSN_C64X_AND_C67X TIC6X_INSN_C64X|TIC6X_INSN_C67X
+#define tic6x_insn_format_nfu_s_branch_nop_cst	\
+  tic6x_insn_format_s_branch_nop_cst
+#define tic6x_insn_format_s_l_1_or_2_src tic6x_insn_format_l_1_or_2_src
+#define RAN(id, min, max) { CONCAT2(tic6x_field_,id), (min), (max) }
+#define FIX(id, val) RAN(id, val, val)
+#define FIX0() 0, { { 0, 0, 0 } }
+#define FIX1(a) 1, { a }
+#define FIX2(a, b) 2, { a, b }
+#define FIX3(a, b, c) 3, { a, b, c }
+#define FIX4(a, b, c, d) 4, { a, b, c, d }
+#define OP0() 0, { { 0, 0, FALSE, 0, 0, 0, 0 } }
+#define OP1(a) 1, { a }
+#define OP2(a, b) 2, { a, b }
+#define OP3(a, b, c) 3, { a, b, c }
+#define OP4(a, b, c, d) 4, { a, b, c, d }
+#define OACST { tic6x_operand_asm_const, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define OLCST { tic6x_operand_link_const, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define OHWCSTM1 { tic6x_operand_hw_const_minus_1, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define OHWCST0 { tic6x_operand_hw_const_0, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define OHWCST1 { tic6x_operand_hw_const_1, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define OHWCST5 { tic6x_operand_hw_const_5, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define OHWCST16 { tic6x_operand_hw_const_16, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define OHWCST24 { tic6x_operand_hw_const_24, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define OHWCST31 { tic6x_operand_hw_const_31, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define OFULIST { tic6x_operand_func_unit, 0, tic6x_rw_none, 0, 0, 0, 0 }
+#define ORIRP1 { tic6x_operand_irp, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORNRP1 { tic6x_operand_nrp, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define OWREG1 { tic6x_operand_reg, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define OWREG1Z { tic6x_operand_zreg, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define OWREG1NORS { tic6x_operand_reg_nors, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define ORREG1B { tic6x_operand_reg_bside, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define ORREG1BNORS { tic6x_operand_reg_bside_nors, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define OWRETREG1 { tic6x_operand_retreg, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define ORREG1 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORDREG1 { tic6x_operand_dreg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORTREG1 { tic6x_operand_treg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORWREG1 { tic6x_operand_reg, 4, tic6x_rw_read_write, 1, 1, 0, 0 }
+#define ORB15REG1 { tic6x_operand_b15reg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define OWB15REG1 { tic6x_operand_b15reg, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define ORAREG1 { tic6x_operand_areg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORXREG1 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define ORREG12 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 2, 0, 0 }
+#define ORREG14 { tic6x_operand_reg, 4, tic6x_rw_read, 1, 4, 0, 0 }
+#define ORXREG14 { tic6x_operand_xreg, 4, tic6x_rw_read, 1, 4, 0, 0 }
+#define OWREG2 { tic6x_operand_reg, 4, tic6x_rw_write, 2, 2, 0, 0 }
+#define OWREG4 { tic6x_operand_reg, 4, tic6x_rw_write, 4, 4, 0, 0 }
+#define OWREG9 { tic6x_operand_reg, 4, tic6x_rw_write, 9, 9, 0, 0 }
+#define OWDREG5 { tic6x_operand_dreg, 4, tic6x_rw_write, 5, 5, 0, 0 }
+#define OWTREG5 { tic6x_operand_treg, 4, tic6x_rw_write, 5, 5, 0, 0 }
+#define OWREGL1 { tic6x_operand_regpair, 5, tic6x_rw_write, 1, 1, 1, 1 }
+#define ORREGL1 { tic6x_operand_regpair, 5, tic6x_rw_read, 1, 1, 1, 1 }
+#define OWREGD1 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 1, 1 }
+#define OWREGD12 { tic6x_operand_regpair, 8, tic6x_rw_write, 1, 1, 2, 2 }
+#define OWREGD4 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 4, 4 }
+#define ORREGD1 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 1, 1 }
+#define OWREGD45 { tic6x_operand_regpair, 8, tic6x_rw_write, 4, 4, 5, 5 }
+#define OWREGD67 { tic6x_operand_regpair, 8, tic6x_rw_write, 6, 6, 7, 7 }
+#define ORDREGD1 { tic6x_operand_dregpair, 8, tic6x_rw_read, 1, 1, 1, 1 }
+#define ORTREGD1 { tic6x_operand_tregpair, 8, tic6x_rw_read, 1, 1, 1, 1 }
+#define OWDREGD5 { tic6x_operand_dregpair, 8, tic6x_rw_write, 5, 5, 5, 5 }
+#define OWTREGD5 { tic6x_operand_tregpair, 8, tic6x_rw_write, 5, 5, 5, 5 }
+#define ORREGD12 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 2, 2 }
+#define ORXREGD12 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 1, 2, 2 }
+#define ORREGD1234 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 2, 3, 4 }
+#define ORXREGD1324 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 3, 2, 4 }
+#define OWREGD910 { tic6x_operand_regpair, 8, tic6x_rw_write, 9, 9, 10, 10 }
+#define ORCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_read, 1, 1, 0, 0 }
+#define OWCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define OWILC1 { tic6x_operand_ilc, 4, tic6x_rw_write, 1, 1, 0, 0 }
+#define ORMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMDW { tic6x_operand_mem_deref, 4, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSB { tic6x_operand_mem_short, 1, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMLB { tic6x_operand_mem_long, 1, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSH { tic6x_operand_mem_short, 2, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMLH { tic6x_operand_mem_long, 2, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSW { tic6x_operand_mem_short, 4, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMLW { tic6x_operand_mem_long, 4, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMSD { tic6x_operand_mem_short, 8, tic6x_rw_write, 3, 3, 0, 0 }
+#define ORMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_read, 3, 3, 0, 0 }
+#define OWMEMND { tic6x_operand_mem_ndw, 8, tic6x_rw_write, 3, 3, 0, 0 }
+#define ENC(id, meth, op) {			\
+    CONCAT2(tic6x_field_,id),			\
+    CONCAT2(tic6x_coding_,meth),		\
+    op						\
+  }
+#define ENC0() 0, { { 0, 0, 0 } }
+#define ENC1(a) 1, { a }
+#define ENC2(a, b) 2, { a, b }
+#define ENC3(a, b, c) 3, { a, b, c }
+#define ENC4(a, b, c, d) 4, { a, b, c, d }
+#define ENC5(a, b, c, d, e) 5, { a, b, c, d, e }
+#define ENC6(a, b, c, d, e, f) 6, { a, b, c, d, e, f }
+#define ENC7(a, b, c, d, e, f, g) 7, { a, b, c, d, e, f, g }
+
+INSN(abs, l, unary, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+INSN(abs, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(op, 0x38), FIX(x, 0), FIX(src1, 0)),
+     OP2(ORREGL1, OWREGL1),
+     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(abs2, l, unary, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x4)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(absdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x2c), FIX(x, 0)),
+     OP2(ORREGD1, OWREGD12),
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(abssp, s, unary, 1cycle, C67X, 0,
+     FIX1(FIX(op, 0)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSNE(add, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x3)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x23)),
+      OP3(ORREG1, ORXREG1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x21)),
+      OP3(ORXREG1, ORREGL1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x2)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x20), FIX(x, 0)),
+      OP3(OACST, ORREGL1, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(add, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x7)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, s_s5_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x6)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, d_si_si_si, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x10)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(add, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x12)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+INSNE(add, d_si_xsi_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0xa)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(add, d_xsi_s5_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0xb)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, scst, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(add, l, l3_sat_0, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x0)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+          ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(add, l, l3i, 1cycle, C64XP, 0,
+     FIX0(),
+     OP3(OACST, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(cst, scst_l3i, 0),
+          ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(add, l, lx1, 1cycle, C64XP,
+     TIC6X_FLAG_NO_CROSS,
+     FIX1(FIX(op, 0x3)),
+     OP3(OHWCSTM1, ORREG1, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2)))
+INSN(add, s, s3_sat_0, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x0)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+          ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(add, s, sx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x3)),
+      OP3(OHWCSTM1, ORREG1, OWREG1),
+      ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2)))
+INSN(add, s, sx2op, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 0x0)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2),
+           ENC(src2, reg, 1), ENC(x, xpath, 1)))
+INSN(add, d, dx2op, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x0)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 1), ENC(srcdst, reg, 0),
+          ENC(src2, reg, 1), ENC(srcdst, reg, 2)))
+INSNU(add, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x5), FIX(unit, 0x0)),
+     OP3(ORREG1, OHWCST1, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))
+INSNU(add, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x5), FIX(unit, 0x1)),
+     OP3(ORREG1, OHWCST1, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))
+INSNU(add, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x5), FIX(unit, 0x2)),
+     OP3(ORREG1, OHWCST1, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))
+/**/
+
+INSNE(addab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x30)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(addab, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x32)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+INSN(addab, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 3)),
+     OP3(ORAREG1, OLCST, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 1),
+	  ENC(dst, reg, 2)))
+
+INSNE(addad, d_si_si_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X,
+      TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x3c)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(addad, d_si_u5_si, d, 1_or_2_src, 1cycle, C64X_AND_C67X,
+      TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x3d)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+
+INSNE(addah, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x34)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(addah, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x36)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+INSN(addah, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 5)),
+     OP3(ORAREG1, OLCST, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 1),
+	  ENC(dst, reg, 2)))
+
+INSNE(addaw, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x38)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(addaw, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x3a)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+INSN(addaw, d, adda_long, 1cycle, C64XP, TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 7)),
+     OP3(ORAREG1, OLCST, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 1),
+	  ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(addaw, d, dx5, 1cycle, C64XP, TIC6X_FLAG_INSN16_BSIDE,
+     FIX0(),
+     OP3(ORB15REG1, OACST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, ucst, 1), ENC(dst, reg, 2)))
+INSN(addaw, d, dx5p, 1cycle, C64XP, TIC6X_FLAG_INSN16_BSIDE,
+     FIX1(FIX(op, 0)),
+     OP3(ORB15REG1, OACST, OWB15REG1),
+     ENC2(ENC(s, fu, 0), ENC(cst, ucst, 1)))
+/**/
+
+INSN(adddp, l, 1_or_2_src, addsubdp, C67X, 0,
+     FIX1(FIX(op, 0x18)),
+     OP3(ORREGD12, ORXREGD12, OWREGD67),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(adddp, s, l_1_or_2_src, addsubdp, C67XP, 0,
+     FIX1(FIX(op, 0x72)),
+     OP3(ORREGD12, ORXREGD12, OWREGD67),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(addk, s, addk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX0(),
+     OP2(OLCST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1)))
+
+/* 16 bits insn */
+INSN(addk, s, sx5, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX0(),
+     OP2(OACST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1)))
+/**/
+
+INSN(addkpc, s, addkpc, 1cycle, C64X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_SIDE_B_ONLY,
+     FIX1(FIX(s, 1)),
+     OP3(OLCST, OWREG1, OACST),
+     ENC3(ENC(src1, pcrel, 0), ENC(dst, reg, 1), ENC(src2, ucst, 2)))
+
+INSN(addsp, l, 1_or_2_src, 4cycle, C67X, 0,
+     FIX1(FIX(op, 0x10)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(addsp, s, l_1_or_2_src, 4cycle, C67XP, 0,
+     FIX1(FIX(op, 0x70)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(addsub, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0xc)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(addsub2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0xd)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(addu, l_ui_xui_ul, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x2b)),
+      OP3(ORREG1, ORXREG1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(addu, l_xui_ul_ul, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x29)),
+      OP3(ORXREG1, ORREGL1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(add2, s, 1_or_2_src, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0x1)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(add2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x5)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(add2, d, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x4)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(add4, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x65)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(and, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x7b)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x7a)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x1f)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x1e)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x6)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(and, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x7)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(and, l, l2c, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 0)),
+      OP3(ORREG1, ORXREG1, OWREG1NORS),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/**/
+
+INSN(andn, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x7c)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(andn, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x6)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(andn, d, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x0)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(avg2, m, compound, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x13)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(avgu4, m, compound, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x12)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(b, s, ext_branch_cond_imm, branch, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX0(),
+     OP1(OLCST),
+     ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(b, s, branch, branch, C62X, TIC6X_FLAG_SIDE_B_ONLY,
+     FIX1(FIX(s, 1)),
+     OP1(ORXREG1),
+     ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(b, s, b_irp, branch, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORIRP1),
+     ENC0())
+INSN(b, s, b_nrp, branch, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORNRP1),
+     ENC0())
+
+INSN(bdec, s, bdec, branch, C64X, TIC6X_FLAG_NO_CROSS,
+     FIX0(),
+     OP2(OLCST, ORWREG1),
+     ENC3(ENC(s, fu, 0), ENC(src, pcrel, 0), ENC(dst, reg, 1)))
+
+INSN(bitc4, m, unary, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x1e)),
+     OP2(ORXREG1, OWREG2),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(bitr, m, unary, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x1f)),
+     OP2(ORXREG1, OWREG2),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(bnop, s, branch_nop_cst, branch, C64X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP,
+     FIX0(),
+     OP2(OLCST, OACST),
+     ENC3(ENC(s, fu, 0), ENC(src2, pcrel_half, 0), ENC(src1, ucst, 1)))
+INSN(bnop, nfu, s_branch_nop_cst, branch, C64XP,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP,
+     FIX1(FIX(s, 0)),
+     OP2(OLCST, OACST),
+     ENC2(ENC(src2, pcrel, 0), ENC(src1, ucst, 1)))
+INSN(bnop, s, branch_nop_reg, branch, C64X,
+     TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MCNOP,
+     FIX1(FIX(s, 1)),
+     OP2(ORXREG1, OACST),
+     ENC3(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1)))
+
+/* 16 bits insn format */
+INSN(bnop, s, sbu8, branch, C64XP,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP,
+     FIX0(),
+     OP2(OLCST, OHWCST5),
+     ENC2(ENC(s, fu, 0), ENC(cst, pcrel_half_unsigned, 0)))
+INSN(bnop, s, sbs7, branch, C64XP,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP,
+     FIX0(),
+     OP2(OLCST, OACST),
+     ENC3(ENC(s, fu, 0), ENC(cst, pcrel_half, 0), ENC(n, ucst, 1)))
+INSN(bnop, s, sbu8c, branch, C64XP,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_INSN16_SPRED,
+     FIX0(),
+     OP2(OLCST, OHWCST5),
+     ENC2(ENC(s, fu, 0), ENC(cst, pcrel_half_unsigned, 0)))
+INSN(bnop, s, sbs7c, branch, C64XP,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_INSN16_SPRED,
+     FIX0(),
+     OP2(OLCST, OACST),
+     ENC3(ENC(s, fu, 0), ENC(cst, pcrel_half, 0), ENC(n, ucst, 1)))
+INSN(bnop, s, sx1b, branch, C64XP,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP,
+     FIX0(),
+     OP2(ORREG1BNORS, OACST),
+     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(n, ucst, 1)))
+/**/
+
+INSN(bpos, s, bpos, branch, C64X, TIC6X_FLAG_NO_CROSS,
+     FIX0(),
+     OP2(OLCST, ORREG1),
+     ENC3(ENC(s, fu, 0), ENC(src, pcrel, 0), ENC(dst, reg, 1)))
+
+INSN(call, s, ext_branch_cond_imm, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+     FIX0(),
+     OP1(OLCST),
+     ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(call, s, branch, branch, C62X,
+     TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+     FIX1(FIX(s, 1)),
+     OP1(ORXREG1),
+     ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(call, s, b_irp, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORIRP1),
+     ENC0())
+INSN(call, s, b_nrp, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORNRP1),
+     ENC0())
+
+INSN(callnop, s, branch_nop_cst, branch, C64X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL,
+     FIX0(),
+     OP2(OLCST, OACST),
+     ENC3(ENC(s, fu, 0), ENC(src2, pcrel, 0), ENC(src1, ucst, 1)))
+INSN(callnop, nfu, s_branch_nop_cst, branch, C64XP,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL,
+     FIX1(FIX(s, 0)),
+     OP2(OLCST, OACST),
+     ENC2(ENC(src2, pcrel, 0), ENC(src1, ucst, 1)))
+INSN(callnop, s, branch_nop_reg, branch, C64X,
+     TIC6X_FLAG_MACRO|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MCNOP|TIC6X_FLAG_CALL,
+     FIX1(FIX(s, 1)),
+     OP2(ORXREG1, OACST),
+     ENC3(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1)))
+
+
+INSN(callp, s, call_imm_nop, branch, C64XP,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP,
+     FIX1(FIX(z, 1)),
+     OP2(OLCST, OWRETREG1),
+     ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+
+/* 16 bits insn format */
+INSN(callp, s, scs10, branch, C64XP,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP,
+     FIX0(),
+     OP2(OLCST, OWRETREG1),
+     ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+/**/
+
+INSN(callret, s, ext_branch_cond_imm, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+     FIX0(),
+     OP1(OLCST),
+     ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(callret, s, branch, branch, C62X,
+     TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+     FIX1(FIX(s, 1)),
+     OP1(ORXREG1),
+     ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(callret, s, b_irp, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORIRP1),
+     ENC0())
+INSN(callret, s, b_nrp, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_CALL|TIC6X_FLAG_RETURN,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORNRP1),
+     ENC0())
+
+INSN(clr, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX1(FIX(op, 0x3)),
+     OP4(ORREG1, OACST, OACST, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+	  ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(clr, s, 1_or_2_src, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0x3f)),
+     OP3(ORXREG1, ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(clr, s, sc5, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 2)),
+     OP4(ORREG1, OACST, OACST, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(cst, ucst, 1),
+          ENC(cst, ucst, 2), ENC(srcdst, reg, 3)))
+/**/
+
+INSNE(cmpeq, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x53)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpeq, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x52)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpeq, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x51)),
+      OP3(ORXREG1, ORREGL1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpeq, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x50), FIX(x, 0)),
+      OP3(OACST, ORREGL1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(cmpeq, l, lx3c, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+      FIX0(),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(src2, reg, 1),
+           ENC(dst, reg, 2)))
+
+INSN(cmpeq, l, l2c, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 3)),
+      OP3(ORREG1, ORXREG1, OWREG1NORS),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/**/
+
+INSN(cmpeq2, s, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x1d)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpeq4, s, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x1c)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpeqdp, s, 1_or_2_src, dpcmp, C67X, 0,
+     FIX1(FIX(op, 0x28)),
+     OP3(ORREGD12, ORXREGD12, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpeqsp, s, 1_or_2_src, 1cycle, C67X, 0,
+     FIX1(FIX(op, 0x38)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmpgt, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x47)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x46)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x45)),
+      OP3(ORXREG1, ORREGL1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x44), FIX(x, 0)),
+      OP3(OACST, ORREGL1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(cmpgt, l_xsi_si_ui, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x57)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_xsi_s5_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX1(FIX(op, 0x56)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_sl_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX1(FIX(op, 0x55)),
+      OP3(ORREGL1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmpgt, l_sl_s5_ui, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x54), FIX(x, 0)),
+      OP3(ORREGL1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, scst, 1), ENC(src2, reg, 0),
+	   ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(cmpgt, l, lx1c, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 1)),
+     OP3(OACST, ORREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(src2, reg, 1),
+          ENC(dst, reg, 2)))
+INSN(cmpgt, l, l2c, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 5)),
+      OP3(ORREG1, ORXREG1, OWREG1NORS),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/**/
+
+INSN(cmpgt2, s, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x14)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpgtdp, s, 1_or_2_src, dpcmp, C67X, 0,
+     FIX1(FIX(op, 0x29)),
+     OP3(ORREGD12, ORXREGD12, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpgtsp, s, 1_or_2_src, 1cycle, C67X, 0,
+     FIX1(FIX(op, 0x39)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmpgtu, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x4f)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_u4_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX2(FIX(op, 0x4e), RAN(src1, 0, 15)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/* Although not mentioned in SPRUFE8, CMPGTU and CMPLTU support a
+   5-bit unsigned constant operand on C64X and above.  */
+INSNE(cmpgtu, l_u5_xui_ui, l, 1_or_2_src, 1cycle, C64X, 0,
+      FIX2(FIX(op, 0x4e), RAN(src1, 16, 31)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_xui_ul_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x4d)),
+      OP3(ORXREG1, ORREGL1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_u4_ul_ui, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX3(FIX(op, 0x4c), FIX(x, 0), RAN(src1, 0, 15)),
+      OP3(OACST, ORREGL1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(cmpgtu, l_u5_ul_ui, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+      FIX3(FIX(op, 0x4c), FIX(x, 0), RAN(src1, 16, 31)),
+      OP3(OACST, ORREGL1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(cmpgtu, l, lx1c, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 3)),
+     OP3(OACST, ORREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(src2, reg, 1),
+          ENC(dst, reg, 2)))
+INSN(cmpgtu, l, l2c, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 7)),
+      OP3(ORREG1, ORXREG1, OWREG1NORS),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/**/
+
+INSN(cmpgtu4, s, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x15)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmplt, l_si_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x57)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmplt, l_s5_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x56)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmplt, l_xsi_sl_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x55)),
+      OP3(ORXREG1, ORREGL1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmplt, l_s5_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x54), FIX(x, 0)),
+      OP3(OACST, ORREGL1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(cmplt, l_xsi_si_ui, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x47)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmplt, l_xsi_s5_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX1(FIX(op, 0x46)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmplt, l_sl_xsi_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX1(FIX(op, 0x45)),
+      OP3(ORREGL1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(cmplt, l_sl_s5_ui, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x44), FIX(x, 0)),
+      OP3(ORREGL1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, scst, 1), ENC(src2, reg, 0),
+	   ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(cmplt, l, lx1c, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0)),
+     OP3(OACST, ORREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(src2, reg, 1),
+          ENC(dst, reg, 2)))
+INSN(cmplt, l, l2c, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 4)),
+      OP3(ORREG1, ORXREG1, OWREG1NORS),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/**/
+
+INSN(cmplt2, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x14)),
+     OP3(ORXREG1, ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpltdp, s, 1_or_2_src, dpcmp, C67X, 0,
+     FIX1(FIX(op, 0x2a)),
+     OP3(ORREGD12, ORXREGD12, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpltsp, s, 1_or_2_src, 1cycle, C67X, 0,
+     FIX1(FIX(op, 0x3a)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(cmpltu, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x5f)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u4_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX2(FIX(op, 0x5e), RAN(src1, 0, 15)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u5_xui_ui, l, 1_or_2_src, 1cycle, C64X, 0,
+      FIX2(FIX(op, 0x5e), RAN(src1, 16, 31)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, ucst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_xui_ul_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x5d)),
+      OP3(ORXREG1, ORREGL1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u4_ul_ui, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX3(FIX(op, 0x5c), FIX(x, 0), RAN(src1, 0, 15)),
+      OP3(OACST, ORREGL1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(cmpltu, l_u5_ul_ui, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+      FIX3(FIX(op, 0x5c), FIX(x, 0), RAN(src1, 16, 31)),
+      OP3(OACST, ORREGL1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, ucst, 0), ENC(src2, reg, 1),
+	   ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(cmpltu, l, lx1c, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 2)),
+     OP3(OACST, ORREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(src2, reg, 1),
+          ENC(dst, reg, 2)))
+INSN(cmpltu, l, l2c, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 6)),
+      OP3(ORREG1, ORXREG1, OWREG1NORS),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/**/
+
+INSN(cmpltu4, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x15)),
+     OP3(ORXREG1, ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpy, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0xa)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpyr, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0xb)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmpyr1, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0xc)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(cmtl, d, 1_or_2_src, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(s, 1), FIX(op, 0xe), FIX(src1, 0)),
+     OP2(ORMEMDW, OWDREG5),
+     ENC2(ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(ddotp4, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x18)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotph2, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x17)),
+     OP3(ORREGD1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotph2r, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x15)),
+     OP3(ORREGD1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotpl2, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x16)),
+     OP3(ORREGD1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(ddotpl2r, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x14)),
+     OP3(ORREGD1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(deal, m, unary, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x1d)),
+     OP2(ORXREG1, OWREG2),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(dint, nfu, dint, 1cycle, C64XP, 0,
+     FIX1(FIX(s, 0)),
+     OP0(),
+     ENC0())
+
+INSN(dmv, s, ext_1_or_2_src, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0xb)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(dotp2, m_s2_xs2_si, m, compound, 4cycle, C64X, 0,
+      FIX1(FIX(op, 0xc)),
+      OP3(ORREG1, ORXREG1, OWREG4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(dotp2, m_s2_xs2_sll, m, compound, 4cycle, C64X, 0,
+      FIX1(FIX(op, 0xb)),
+      OP3(ORREG1, ORXREG1, OWREGD4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpn2, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x9)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpnrsu2, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x7)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpnrus2, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x7)),
+     OP3(ORXREG1, ORREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotprsu2, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0xd)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotprus2, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0xd)),
+     OP3(ORXREG1, ORREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpsu4, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x2)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpus4, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x2)),
+     OP3(ORXREG1, ORREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dotpu4, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x6)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dpack2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x34)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dpackx2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x33)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(dpint, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x8), FIX(x, 0)),
+     OP2(ORREGD1, OWREG4),
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(dpsp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x9), FIX(x, 0)),
+     OP2(ORREGD1, OWREG4),
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(dptrunc, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x1), FIX(x, 0)),
+     OP2(ORREGD1, OWREG4),
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(ext, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX1(FIX(op, 0x1)),
+     OP4(ORREG1, OACST, OACST, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+	  ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(ext, s, 1_or_2_src, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0x2f)),
+     OP3(ORXREG1, ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSNE(ext, hwcst16, s, s2ext, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x0)),
+     OP4(ORREG1, OHWCST16, OHWCST16, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(src, reg, 0), ENC(dst, reg, 3)))
+INSNE(ext, hwcst24, s, s2ext, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x1)),
+     OP4(ORREG1, OHWCST24, OHWCST24, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(src, reg, 0), ENC(dst, reg, 3)))
+/**/
+
+INSN(extu, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX1(FIX(op, 0x0)),
+     OP4(ORREG1, OACST, OACST, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+	  ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(extu, s, 1_or_2_src, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0x2b)),
+     OP3(ORXREG1, ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSNE(extu, hwcst16, s, s2ext, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x2)),
+     OP4(ORREG1, OHWCST16, OHWCST16, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(src, reg, 0), ENC(dst, reg, 3)))
+INSNE(extu, hwcst24, s, s2ext, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x3)),
+     OP4(ORREG1, OHWCST24, OHWCST24, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(src, reg, 0), ENC(dst, reg, 3)))
+INSN(extu, s, sc5, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0)),
+     OP4(ORREG1, OACST, OHWCST31, OWREG1Z),
+     ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(cst, ucst, 1)))
+/**/
+
+INSN(gmpy, m, 1_or_2_src, 4cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x1f), FIX(x, 0)),
+     OP3(ORREG1, ORREG1, OWREG4),
+     ENC4(ENC(s, fu, 0), ENC(src1, reg, 0), ENC(src2, reg, 1),
+	  ENC(dst, reg, 2)))
+
+/* This instruction can be predicated as usual; SPRUFE8 is incorrect
+   where it shows the "z" field as fixed to 1.  */
+INSN(gmpy4, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x11)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(idle, nfu, nop_idle, nop, C62X, TIC6X_FLAG_MCNOP,
+     FIX2(FIX(s, 0), FIX(op, 0xf)),
+     OP0(),
+     ENC0())
+
+INSN(intdp, l, 1_or_2_src, intdp, C67X, 0,
+     FIX2(FIX(op, 0x39), FIX(src1, 0)),
+     OP2(ORXREG1, OWREGD45),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(intdpu, l, 1_or_2_src, intdp, C67X, 0,
+     FIX2(FIX(op, 0x3b), FIX(src1, 0)),
+     OP2(ORXREG1, OWREGD45),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(intsp, l, 1_or_2_src, 4cycle, C67X, 0,
+     FIX2(FIX(op, 0x4a), FIX(src1, 0)),
+     OP2(ORXREG1, OWREG4),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(intspu, l, 1_or_2_src, 4cycle, C67X, 0,
+     FIX2(FIX(op, 0x49), FIX(src1, 0)),
+     OP2(ORXREG1, OWREG4),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(ldb, d, load_store, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 2), FIX(r, 0)),
+     OP2(ORMEMSB, OWDREG5),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+	  ENC(srcdst, reg, 1)))
+INSN(ldb, d, load_store_long, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 2)),
+     OP2(ORMEMLB, OWDREG5),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 0),
+	  ENC(dst, reg, 1)))
+
+/* 16 bits insn */
+INSN(ldb, d, doff4_dsz_x01, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSB, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset, 0)))
+INSN(ldb, d, dind_dsz_x01, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSB, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0)))
+INSN(ldb, d, dinc_dsz_x01, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSB, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0),  ENC(cst, mem_offset_minus_one, 0)))
+INSN(ldb, d, ddec_dsz_x01, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSB, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0)))
+/**/
+
+INSN(ldbu, d, load_store, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 1), FIX(r, 0)),
+     OP2(ORMEMSB, OWDREG5),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+	  ENC(srcdst, reg, 1)))
+INSN(ldbu, d, load_store_long, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 1)),
+     OP2(ORMEMLB, OWDREG5),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_byte, 0),
+	  ENC(dst, reg, 1)))
+
+/* 16 bits insn */
+INSN(ldbu, d, dinc_dsz_000, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSB, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset_minus_one, 0),
+          ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1)))
+INSN(ldbu, d, dind_dsz_000, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSB, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset, 0),
+          ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1)))
+INSN(ldbu, d, doff4_dsz_000, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSB, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset, 0),
+          ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1)))
+INSN(ldbu, d, ddec_dsz_000, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSB, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset_minus_one, 0),
+          ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1)))
+/**/
+
+INSN(lddw, d, load_store, load, C64X_AND_C67X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 6), FIX(r, 1)),
+     OP2(ORMEMSD, OWDREGD5),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+	  ENC(srcdst, reg, 1)))
+
+/* 16 bits insn */
+INSN(lddw, d, dpp, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREINCR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS,
+     FIX2(FIX(op, 1), FIX(dw, 1)),
+     OP2(ORMEMSD, OWDREGD5),
+     ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+	  ENC(cst, mem_offset_minus_one, 0)))
+INSN(lddw, d, ddecdw, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX3(FIX(op, 1), FIX(na, 0), FIX(sz, 0)),
+     OP2(ORMEMSD, OWTREGD5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0)))
+INSN(lddw, d, dincdw, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX3(FIX(op, 1), FIX(na, 0), FIX(sz, 0)),
+     OP2(ORMEMSD, OWTREGD5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0)))
+INSN(lddw, d, dinddw, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX3(FIX(op, 1), FIX(na, 0), FIX(sz, 0)),
+     OP2(ORMEMSD, OWTREGD5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset, 0),
+          ENC(ptr, reg_ptr, 0), ENC(srcdst, reg_shift, 1)))
+INSN(lddw, d, doff4dw, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX3(FIX(op, 1), FIX(na, 0), FIX(sz, 0)),
+     OP2(ORMEMSD, OWTREGD5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset, 0),
+          ENC(ptr, reg_ptr, 0), ENC(srcdst, reg_shift, 1)))
+/**/
+
+INSN(ldh, d, load_store, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 4), FIX(r, 0)),
+     OP2(ORMEMSH, OWDREG5),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+	  ENC(srcdst, reg, 1)))
+INSN(ldh, d, load_store_long, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 4)),
+     OP2(ORMEMLH, OWDREG5),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 0),
+	  ENC(dst, reg, 1)))
+
+/* 16 bits insn */
+INSN(ldh, d, doff4_dsz_x11, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSH, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset, 0),
+          ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1)))
+INSN(ldh, d, dind_dsz_x11, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSH, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0)))
+INSN(ldh, d, dinc_dsz_x11, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSH, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0)))
+INSN(ldh, d, ddec_dsz_x11, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSH, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0)))
+/**/
+
+INSN(ldhu, d, load_store, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 0), FIX(r, 0)),
+     OP2(ORMEMSH, OWDREG5),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+	  ENC(srcdst, reg, 1)))
+INSN(ldhu, d, load_store_long, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 0)),
+     OP2(ORMEMLH, OWDREG5),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_half, 0),
+	  ENC(dst, reg, 1)))
+
+/* 16 bits insn */
+INSN(ldhu, d, doff4_dsz_010, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSH, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset, 0),
+          ENC(ptr, reg_ptr, 0), ENC(srcdst, reg, 1)))
+INSN(ldhu, d, dind_dsz_010, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSH, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0)))
+INSN(ldhu, d, dinc_dsz_010, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSH, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0)))
+INSN(ldhu, d, ddec_dsz_010, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSH, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0)))
+/**/
+
+INSN(ldndw, d, load_nonaligned, load, C64X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+     FIX0(),
+     OP2(ORMEMND, OWDREGD5),
+     ENC7(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset_noscale, 0), ENC(baseR, reg, 0),
+	  ENC(sc, scaled, 0), ENC(dst, reg_shift, 1)))
+
+/* 16 bits insn */
+INSN(ldndw, d, ddecdw, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX3(FIX(op, 1), FIX(na, 1), FIX(sz, 0)),
+     OP2(ORMEMND, OWTREGD5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one_noscale, 0)))
+INSN(ldndw, d, dincdw, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX3(FIX(op, 1), FIX(na, 1), FIX(sz, 0)),
+     OP2(ORMEMND, OWTREGD5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one_noscale, 0)))
+INSN(ldndw, d, dinddw, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX3(FIX(op, 1), FIX(na, 1), FIX(sz, 0)),
+     OP2(ORMEMND, OWTREGD5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset_noscale, 0),
+          ENC(ptr, reg_ptr, 0), ENC(srcdst, reg_shift, 1)))
+INSN(ldndw, d, doff4dw, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX3(FIX(op, 1), FIX(na, 1), FIX(sz, 0)),
+     OP2(ORMEMND, OWTREGD5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset_noscale, 0),
+          ENC(ptr, reg_ptr, 0), ENC(srcdst, reg_shift, 1)))
+/**/
+
+INSN(ldnw, d, load_store, load, C64X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+     FIX2(FIX(op, 3), FIX(r, 1)),
+     OP2(ORMEMSW, OWDREG5),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+	  ENC(srcdst, reg, 1)))
+
+/* 16 bits insn */
+INSN(ldnw, d, doff4_dsz_110, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSW, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset, 0)))
+INSN(ldnw, d, dind_dsz_110, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSW, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0)))
+INSN(ldnw, d, dinc_dsz_110, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSW, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0)))
+INSN(ldnw, d, ddec_dsz_110, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSW, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0)))
+/**/
+
+INSN(ldw, d, load_store, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 6), FIX(r, 0)),
+     OP2(ORMEMSW, OWDREG5),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 0),
+	  ENC(offsetR, mem_offset, 0), ENC(baseR, reg, 0),
+	  ENC(srcdst, reg, 1)))
+INSN(ldw, d, load_store_long, load, C62X,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 6)),
+     OP2(ORMEMLW, OWDREG5),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 0), ENC(offsetR, ulcst_dpr_word, 0),
+	  ENC(dst, reg, 1)))
+
+/* 16 bits insn */
+INSN(ldw, d, doff4_dsz_0xx, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX2(FIX(op, 1), FIX(sz, 0)),
+     OP2(ORMEMSW, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset, 0)))
+INSN(ldw, d, doff4_dsz_100, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSW, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset, 0)))
+INSN(ldw, d, dind_dsz_0xx, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX2(FIX(op, 1), FIX(sz, 0)),
+     OP2(ORMEMSW, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0)))
+INSN(ldw, d, dind_dsz_100, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSW, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(src1, mem_offset, 0)))
+INSN(ldw, d, dinc_dsz_0xx, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX2(FIX(op, 1), FIX(sz, 0)),
+     OP2(ORMEMSW, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0)))
+INSN(ldw, d, dinc_dsz_100, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSW, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0)))
+INSN(ldw, d, ddec_dsz_0xx, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX2(FIX(op, 1), FIX(sz, 0)),
+     OP2(ORMEMSW, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0)))
+INSN(ldw, d, ddec_dsz_100, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX2(FIX(op, 1), FIX(sz, 1)),
+     OP2(ORMEMSW, OWTREG5),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+          ENC(ptr, reg_ptr, 0), ENC(cst, mem_offset_minus_one, 0)))
+INSN(ldw, d, dpp, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREINCR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS,
+     FIX2(FIX(op, 1), FIX(dw, 0)),
+     OP2(ORMEMSW, OWTREG5),
+     ENC4(ENC(s, fu, 0), ENC(t, rside, 0),  ENC(srcdst, reg, 1),
+	  ENC(cst, mem_offset_minus_one, 0)))
+INSN(ldw, d, dstk, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE)|TIC6X_FLAG_INSN16_B15PTR,
+     FIX2(FIX(op, 0x1), FIX(s, 1)),
+     OP2(ORMEMSW, OWTREG5),
+     ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1),
+	  ENC(cst, mem_offset, 0)))
+/**/
+
+INSN(ll, d, 1_or_2_src, load, C64XP,
+     TIC6X_FLAG_LOAD|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(s, 1), FIX(op, 0xc), FIX(src1, 0)),
+     OP2(ORMEMDW, OWDREG5),
+     ENC2(ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSNE(lmbd, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x6b)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(lmbd, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x6a)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(max2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x42)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(max2, s, ext_1_or_2_src, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0xd)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(maxu4, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x43)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(min2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x41)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(min2, s, ext_1_or_2_src, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0xc)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(minu4, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x48)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpy, m_sl16_xsl16_si, m, mpy, 1616_m, C62X, 0,
+      FIX1(FIX(op, 0x19)),
+      OP3(ORREG1, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpy, m_s5_xsl16_si, m, mpy, 1616_m, C62X, 0,
+      FIX1(FIX(op, 0x18)),
+      OP3(OACST, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* 16-bit insn.  */
+INSN(mpy, m, m3_sat_0, 1616_m, C67X, 0,
+      FIX1(FIX(op, 0x0)),
+      OP3(ORREG1, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg_shift, 2)))
+
+INSN(mpydp, m, mpy, mpydp, C67X, 0,
+     FIX1(FIX(op, 0x0e)),
+     OP3(ORREGD1234, ORXREGD1324, OWREGD910),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyh, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x01)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(mpyh, m, m3_sat_0, 1616_m, C67X, 0,
+      FIX1(FIX(op, 0x1)),
+      OP3(ORREG1, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg_shift, 2)))
+/**/ 
+
+INSN(mpyhi, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x14)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhir, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x10)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhl, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x09)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(mpyhl, m, m3_sat_0, 1616_m, C67X, 0,
+      FIX1(FIX(op, 0x3)),
+      OP3(ORREG1, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg_shift, 2)))
+/**/ 
+
+INSN(mpyhlu, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x0f)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhslu, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x0b)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhsu, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x03)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhu, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x07)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhuls, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x0d)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyhus, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x05)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpyi, m_si_xsi_si, m, mpy, mpyi, C67X, 0,
+      FIX1(FIX(op, 0x04)),
+      OP3(ORREG14, ORXREG14, OWREG9),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpyi, m_s5_xsi_si, m, mpy, mpyi, C67X, 0,
+      FIX1(FIX(op, 0x06)),
+      OP3(OACST, ORXREG14, OWREG9),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpyid, m_si_xsi_sll, m, mpy, mpyid, C67X, 0,
+      FIX1(FIX(op, 0x08)),
+      OP3(ORREG14, ORXREG14, OWREGD910),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpyid, m_s5_xsi_sll, m, mpy, mpyid, C67X, 0,
+      FIX1(FIX(op, 0x0c)),
+      OP3(OACST, ORXREG14, OWREGD910),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyih, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x14)),
+     OP3(ORXREG1, ORREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyihr, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x10)),
+     OP3(ORXREG1, ORREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyil, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x15)),
+     OP3(ORXREG1, ORREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyilr, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x0e)),
+     OP3(ORXREG1, ORREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpylh, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x11)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(mpylh, m, m3_sat_0, 1616_m, C67X, 0,
+      FIX1(FIX(op, 0x2)),
+      OP3(ORREG1, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg_shift, 2)))
+/**/ 
+
+INSN(mpylhu, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x17)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyli, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x15)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpylir, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x0e)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpylshu, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x13)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyluhs, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x15)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpysp, m, mpy, 4cycle, C67X, 0,
+     FIX1(FIX(op, 0x1c)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* Contrary to SPRU733A, MPYSPDP and MPYSP2DP are on both C67X and
+   C67X+.  */
+INSN(mpyspdp, m, compound, mpyspdp, C67X, 0,
+     FIX1(FIX(op, 0x16)),
+     OP3(ORREG12, ORXREGD12, OWREGD67),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpysp2dp, m, compound, mpyspdp, C67X, 0,
+     FIX1(FIX(op, 0x17)),
+     OP3(ORREG1, ORXREG1, OWREGD45),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpysu, m_sl16_xul16_si, m, mpy, 1616_m, C62X, 0,
+      FIX1(FIX(op, 0x1b)),
+      OP3(ORREG1, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpysu, m_s5_xul16_si, m, mpy, 1616_m, C62X, 0,
+      FIX1(FIX(op, 0x1e)),
+      OP3(OACST, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpysu4, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x05)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyu, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x1f)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyu4, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x04)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyus, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x1d)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpyus4, m, compound, 4cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x05)),
+     OP3(ORXREG1, ORREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy2, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x00)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy2ir, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x0f)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(mpy32, 32_32_32, m, mpy, 4cycle, C64XP, 0,
+      FIX1(FIX(op, 0x10)),
+      OP3(ORREG1, ORXREG1, OWREG4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(mpy32, 32_32_64, m, mpy, 4cycle, C64XP, 0,
+      FIX1(FIX(op, 0x14)),
+      OP3(ORREG1, ORXREG1, OWREGD4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy32su, m, mpy, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x16)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy32u, m, compound, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x18)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(mpy32us, m, compound, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x19)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* "or" forms of "mv" are preferred over "add" forms when available
+   because "or" uses less power.  However, 40-bit moves are only
+   available through "add", and before C64X D-unit moves are only
+   available through "add" (without cross paths being available).  */
+INSNE(mv, l_xui_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX2(FIX(op, 0x7e), FIX(src1, 0)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(dst, reg, 1)))
+INSNE(mv, l_sl_sl, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+      FIX3(FIX(op, 0x20), FIX(x, 0), FIX(src1, 0)),
+      OP2(ORREGL1, OWREGL1),
+      ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+INSNE(mv, s_xui_ui, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX2(FIX(op, 0x1a), FIX(src1, 0)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(dst, reg, 1)))
+INSNE(mv, d_si_si, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(0),
+      FIX2(FIX(op, 0x12), FIX(src1, 0)),
+      OP2(ORREG1, OWREG1),
+      ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+INSNE(mv, d_xui_ui, d, ext_1_or_2_src, 1cycle, C64X,
+      TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1),
+      FIX2(FIX(op, 0x3), FIX(src1, 0)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(dst, reg, 1)))
+
+/* 16 bits insn */
+INSNU(mv, l, lsdmvto, 1cycle, C64X, 0,
+      FIX1(FIX(unit, 0x0)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1)))
+
+INSNU(mv, s, lsdmvto, 1cycle, C64X, 0,
+      FIX1(FIX(unit, 0x1)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1)))
+
+INSNU(mv, d, lsdmvto, 1cycle, C64X, 0,
+      FIX1(FIX(unit, 0x2)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1)))
+
+INSNU(mv, l, lsdmvfr, 1cycle, C64X, 0,
+      FIX1(FIX(unit, 0x0)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1)))
+
+INSNU(mv, s, lsdmvfr, 1cycle, C64X, 0,
+      FIX1(FIX(unit, 0x1)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1)))
+
+INSNU(mv, d, lsdmvfr, 1cycle, C64X, 0,
+      FIX1(FIX(unit, 0x2)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(x, xpath, 0), ENC(dst, reg, 1)))
+/**/
+
+INSNE(mvc, from_cr, s, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_NO_CROSS,
+      FIX3(FIX(s, 1), FIX(op, 0x0f), FIX(x, 0)),
+      OP2(ORCREG1, OWREG1),
+      ENC3(ENC(src1, crhi, 0), ENC(src2, crlo, 0), ENC(dst, reg, 1)))
+INSNE(mvc, to_cr, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_SIDE_B_ONLY,
+      FIX2(FIX(s, 1), FIX(op, 0x0e)),
+      OP2(ORXREG1, OWCREG1),
+      ENC4(ENC(x, xpath, 0), ENC(src2, reg, 0), ENC(src1, crhi, 1),
+	   ENC(dst, crlo, 1)))
+
+/* 16 bits insn */
+INSN(mvc, s, sx1, 1cycle, C64XP,
+      TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x6)),
+      OP2(ORREG1B, OWILC1),
+      ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 0)))
+/**/
+
+INSN(mvd, m, unary, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x1a)),
+     OP2(ORXREG1, OWREG4),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(mvk, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX1(FIX(h, 0)),
+     OP2(OLCST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1)))
+INSN(mvk, l, unary, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(x, 0), FIX(op, 0x05)),
+     OP2(OACST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(src2, scst, 0), ENC(dst, reg, 1)))
+INSN(mvk, d, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x00), FIX(src2, 0)),
+     OP2(OACST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(dst, reg, 1)))
+
+/* 16 bits insn */
+INSN(mvk, l, lx5, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX0(),
+     OP2(OLCST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, scst, 0), ENC(dst, reg, 1)))
+INSN(mvk, s, smvk8, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX0(),
+     OP2(OLCST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1)))
+INSNU(mvk, l, lsdx1c, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_SPRED,
+     FIX1(FIX(unit, 0x0)),
+     OP2(OACST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1)))
+INSNU(mvk, s, lsdx1c, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_SPRED,
+     FIX1(FIX(unit, 0x1)),
+     OP2(OACST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1)))
+INSNU(mvk, d, lsdx1c, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_SPRED,
+     FIX1(FIX(unit, 0x2)),
+     OP2(OACST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, ucst, 0), ENC(dst, reg, 1)))
+INSNUE(mvk, zero, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0), FIX(unit, 0x0)),
+     OP2(OHWCST0, OWREG1),
+     ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1)))
+INSNUE(mvk, zero, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0), FIX(unit, 0x1)),
+     OP2(OHWCST0, OWREG1),
+     ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1)))
+INSNUE(mvk, zero, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0), FIX(unit, 0x2)),
+     OP2(OHWCST0, OWREG1),
+     ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1)))
+INSNUE(mvk, one, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 1), FIX(unit, 0x0)),
+     OP2(OHWCST1, OWREG1),
+     ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1)))
+INSNUE(mvk, one, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 1), FIX(unit, 0x1)),
+     OP2(OHWCST1, OWREG1),
+     ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1)))
+INSNUE(mvk, one, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 1), FIX(unit, 0x2)),
+     OP2(OHWCST1, OWREG1),
+     ENC2(ENC(s, fu, 0), ENC(srcdst, reg, 1)))
+/**/
+
+INSN(mvkh, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX1(FIX(h, 1)),
+     OP2(OLCST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, lcst_high16, 0), ENC(dst, reg, 1)))
+
+INSN(mvklh, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+     FIX1(FIX(h, 1)),
+     OP2(OLCST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, lcst_low16, 0), ENC(dst, reg, 1)))
+
+INSN(mvkl, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+     FIX1(FIX(h, 0)),
+     OP2(OLCST, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(cst, lcst_low16, 0), ENC(dst, reg, 1)))
+
+INSNE(neg, s_xsi_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX2(FIX(op, 0x16), FIX(src1, 0)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(dst, reg, 1)))
+INSNE(neg, l_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX2(FIX(op, 0x06), FIX(src1, 0)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(dst, reg, 1)))
+INSNE(neg, l_sl_sl, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+      FIX2(FIX(op, 0x24), FIX(src1, 0)),
+      OP2(ORREGL1, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(dst, reg, 1)))
+
+INSN(nop, nfu, nop_idle, nop, C62X, 0,
+     FIX2(FIX(s, 0), RAN(op, 0, 8)),
+     OP1(OACST),
+     ENC1(ENC(op, ucst_minus_one, 0)))
+INSNE(nop, 1, nfu, nop_idle, nop, C62X, TIC6X_FLAG_MACRO,
+      FIX2(FIX(s, 0), FIX(op, 0)),
+      OP0(),
+      ENC0())
+
+/* 16 bits insn */
+/* contrary to sprufe8b.pdf p767, and accordingly to
+ * dis6x.exe output, unop3 opcode is decoded as NOP N3 + 1 */
+INSN(nop, nfu, unop, nop, C64XP, 0,
+     FIX0(),
+     OP1(OACST),
+     ENC1(ENC(n, ucst_minus_one, 0)))
+/**/
+
+INSNE(norm, l_xsi_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX2(FIX(op, 0x63), FIX(src1, 0)),
+      OP2(ORXREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(dst, reg, 1)))
+INSNE(norm, l_sl_ui, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX3(FIX(op, 0x60), FIX(x, 0), FIX(src1, 0)),
+      OP2(ORREGL1, OWREG1),
+      ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(not, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+     FIX2(FIX(op, 0x6e), FIX(src1, 0x1f)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+INSN(not, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+     FIX2(FIX(op, 0x0a), FIX(src1, 0x1f)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+INSN(not, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX2(FIX(op, 0xf), FIX(src1, 0x1f)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSNE(or, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x2)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x3)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x7f)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x7e)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x1b)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(or, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x1a)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(or, l, l2c, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 1)),
+      OP3(ORREG1, ORXREG1, OWREG1NORS),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/**/
+
+INSN(pack2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x0)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(pack2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0xf)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packh2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x1e)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(packh2, s, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x9)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packh4, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x69)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packhl2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x1c)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(packhl2, s, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x8)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packlh2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x1b)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(packlh2, s, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x10)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(packl4, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x68)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(rcpdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x2d), FIX(x, 0)),
+     OP2(ORREGD1, OWREGD12),
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(rcpsp, s, 1_or_2_src, 1cycle, C67X, 0,
+     FIX2(FIX(op, 0x3d), FIX(src1, 0)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(ret, s, ext_branch_cond_imm, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+     FIX0(),
+     OP1(OLCST),
+     ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+INSN(ret, s, branch, branch, C62X,
+     TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+     FIX1(FIX(s, 1)),
+     OP1(ORXREG1),
+     ENC2(ENC(x, xpath, 0), ENC(src2, reg, 0)))
+INSN(ret, s, b_irp, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORIRP1),
+     ENC0())
+INSN(ret, s, b_nrp, branch, C62X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+     FIX3(FIX(s, 1), FIX(x, 0), FIX(dst, 0)),
+     OP1(ORNRP1),
+     ENC0())
+
+INSN(retp, s, call_imm_nop, branch, C64XP,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MCNOP|TIC6X_FLAG_MACRO|TIC6X_FLAG_RETURN,
+     FIX1(FIX(z, 1)),
+     OP2(OLCST, OWRETREG1),
+     ENC2(ENC(s, fu, 0), ENC(cst, pcrel, 0)))
+
+INSN(rint, nfu, rint, 1cycle, C64XP, 0,
+     FIX1(FIX(s, 0)),
+     OP0(),
+     ENC0())
+
+INSNE(rotl, m_ui_xui_ui, m, compound, 1616_m, C64X, 0,
+      FIX1(FIX(op, 0x1d)),
+      OP3(ORXREG1, ORREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(rotl, m_u5_xui_ui, m, compound, 1616_m, C64X, 0,
+      FIX1(FIX(op, 0x1e)),
+      OP3(ORXREG1, OACST, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(rpack2, s, ext_1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX2(FIX(op, 0xb), FIX(z, 1)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(rsqrdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x2e), FIX(x, 0)),
+     OP2(ORREGD1, OWREGD12),
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(rsqrsp, s, 1_or_2_src, 1cycle, C67X, 0,
+     FIX2(FIX(op, 0x3e), FIX(src1, 0)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSNE(sadd, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x13)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, l_xsi_sl_sl, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x31)),
+      OP3(ORXREG1, ORREGL1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x12)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x30)),
+      OP3(OACST, ORREGL1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sadd, s_si_xsi_si, s, 1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x20)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(sadd, l, l3_sat_1, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+          ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sadd, s, s3_sat_1, 1cycle, C64XP,0,
+     FIX1(FIX(op, 0x0)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+          ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/**/
+
+INSN(sadd2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x0)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddsub, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x0e)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddsub2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x0f)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddsu2, s, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO,
+     FIX1(FIX(op, 0x1)),
+     OP3(ORXREG1, ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddus2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x1)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(saddu4, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x3)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sat, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(op, 0x40), FIX(x, 0), FIX(src1, 0)),
+     OP2(ORREGL1, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+INSN(set, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+     FIX1(FIX(op, 0x2)),
+     OP4(ORREG1, OACST, OACST, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(csta, ucst, 1),
+	  ENC(cstb, ucst, 2), ENC(dst, reg, 3)))
+INSN(set, s, 1_or_2_src, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0x3b)),
+     OP3(ORXREG1, ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(set, s, sc5, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 1)),
+     OP4(ORREG1, OACST, OACST, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(cst, ucst, 1),
+          ENC(cst, ucst, 2), ENC(srcdst, reg, 3)))
+/**/
+
+INSN(shfl, m, unary, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x1c)),
+     OP2(ORXREG1, OWREG2),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(shfl3, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x36)),
+     OP3(ORREG1, ORXREG1, OWREGD1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(shl, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x33)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shl, s_sl_ui_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x31), FIX(x, 0)),
+      OP3(ORREGL1, ORREG1, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(shl, s_xui_ui_ul, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x13)),
+      OP3(ORXREG1, ORREG1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shl, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x32)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+INSNE(shl, s_sl_u5_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x30), FIX(x, 0)),
+      OP3(ORREGL1, OACST, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+INSNE(shl, s_xui_u5_ul, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x12)),
+      OP3(ORXREG1, OACST, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+/* 16bit insn */
+INSN(shl, s, s3i, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 0x0)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+           ENC(cst, cst_s3i, 1), ENC(dst, reg, 2)))
+INSN(shl, s, ssh5_sat_x, 1cycle, C64XP,
+      TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x0)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0),
+           ENC(cst, ucst, 1),  ENC(srcdst, reg, 2)))
+INSN(shl, s, s2sh, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 0x0)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(src1, reg, 1),
+           ENC(srcdst, reg, 2)))
+/**/
+
+INSN(shlmb, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x61)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(shlmb, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x9)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(shr, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x37)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shr, s_sl_ui_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x35), FIX(x, 0)),
+      OP3(ORREGL1, ORREG1, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(shr, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x36)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+INSNE(shr, s_sl_u5_sl, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x34), FIX(x, 0)),
+      OP3(ORREGL1, OACST, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+
+/* 16bit insn */
+INSN(shr, s, s3i, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 0x1)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+           ENC(cst, cst_s3i, 1), ENC(dst, reg, 2)))
+INSN(shr, s, ssh5_sat_x, 1cycle, C64XP,
+      TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x1)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0),
+           ENC(cst, ucst, 1),  ENC(srcdst, reg, 2)))
+INSN(shr, s, s2sh, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 0x1)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(src1, reg, 1),
+           ENC(srcdst, reg, 2)))
+/**/
+
+INSNE(shr2, s_xs2_ui_s2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x7)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shr2, s_xs2_u5_s2, s, 1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x18)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(shrmb, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x62)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(shrmb, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0xa)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(shru, s_xui_ui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x27)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shru, s_ul_ui_ul, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x25), FIX(x, 0)),
+      OP3(ORREGL1, ORREG1, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(shru, s_xui_u5_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x26)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+INSNE(shru, s_ul_u5_ul, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x24), FIX(x, 0)),
+      OP3(ORREGL1, OACST, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(shru, s, ssh5_sat_0, 1cycle, C64XP,
+      TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x2)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0),
+           ENC(cst, ucst, 1),  ENC(srcdst, reg, 2)))
+INSN(shru, s, s2sh, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 0x2)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(src1, reg, 1),
+           ENC(srcdst, reg, 2)))
+/**/
+
+INSNE(shru2, s_xu2_ui_u2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x8)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(shru2, s_xu2_u5_u2, s, 1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0x19)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+INSN(sl, d, 1_or_2_src, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_SIDE_T2_ONLY|TIC6X_FLAG_NO_CROSS,
+     FIX3(FIX(s, 1), FIX(op, 0xd), FIX(src1, 0)),
+     OP2(ORDREG1, OWMEMDW),
+     ENC2(ENC(dst, reg, 0), ENC(src2, reg, 1)))
+
+INSN(smpy, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x1a)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(smpy, m, m3_sat_1, 1616_m, C67X, 0,
+      FIX1(FIX(op, 0x0)),
+      OP3(ORREG1, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg_shift, 2)))
+/**/ 
+
+INSN(smpyh, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x02)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(smpyh, m, m3_sat_1, 1616_m, C67X, 0,
+      FIX1(FIX(op, 0x1)),
+      OP3(ORREG1, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg_shift, 2)))
+/**/ 
+
+INSN(smpyhl, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x0a)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(smpyhl, m, m3_sat_1, 1616_m, C67X, 0,
+      FIX1(FIX(op, 0x3)),
+      OP3(ORREG1, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg_shift, 2)))
+/**/ 
+
+INSN(smpylh, m, mpy, 1616_m, C62X, 0,
+     FIX1(FIX(op, 0x12)),
+     OP3(ORREG1, ORXREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(smpylh, m, m3_sat_1, 1616_m, C67X, 0,
+      FIX1(FIX(op, 0x2)),
+      OP3(ORREG1, ORXREG1, OWREG2),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg_shift, 2)))
+/**/ 
+
+INSN(smpy2, m, compound, 4cycle, C64X, 0,
+     FIX1(FIX(op, 0x01)),
+     OP3(ORREG1, ORXREG1, OWREGD4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* Contrary to SPRUFE8, this is the correct operand order for this
+   instruction.  */
+INSN(smpy32, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x19)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(spack2, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x2)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(spacku4, s, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x4)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(spdp, s, 1_or_2_src, 2cycle_dp, C67X, 0,
+     FIX2(FIX(op, 0x02), FIX(src1, 0)),
+     OP2(ORXREG1, OWREGD12),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(spint, l, 1_or_2_src, 4cycle, C67X, 0,
+     FIX2(FIX(op, 0x0a), FIX(src1, 0)),
+     OP2(ORXREG1, OWREG4),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSNE(spkernel, nfu_2, nfu, spkernel, 1cycle, C64XP,
+      TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL,
+      FIX1(FIX(s, 0)),
+      OP2(OACST, OACST),
+      ENC2(ENC(fstgfcyc, fstg, 0), ENC(fstgfcyc, fcyc, 1)))
+INSNE(spkernel, nfu_0, nfu, spkernel, 1cycle, C64XP,
+      TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL|TIC6X_FLAG_MACRO,
+      FIX2(FIX(s, 0), FIX(fstgfcyc, 0)),
+      OP0(),
+      ENC0())
+
+/* 16 bits insn */
+INSN(spkernel, nfu, uspk, 1cycle, C64XP,
+      TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL,
+      FIX0(),
+      OP2(OACST, OACST),
+      ENC2(ENC(fstgfcyc, fstg, 0), ENC(fstgfcyc, fcyc, 1)))
+/**/
+
+INSN(spkernelr, nfu, spkernelr, 1cycle, C64XP,
+     TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPKERNEL,
+     FIX1(FIX(s, 0)),
+     OP0(),
+     ENC0())
+
+INSN(sploop, nfu, loop_buffer, 1cycle, C64XP,
+     TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP,
+     FIX4(FIX(s, 0), FIX(op, 0xc), FIX(csta, 0), RAN(cstb, 0, 13)),
+     OP1(OACST),
+     ENC1(ENC(cstb, ucst_minus_one, 0)))
+
+INSN(sploopd, nfu, loop_buffer, 1cycle, C64XP,
+     TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP,
+     FIX4(FIX(s, 0), FIX(op, 0xd), FIX(csta, 0), RAN(cstb, 0, 13)),
+     OP1(OACST),
+     ENC1(ENC(cstb, ucst_minus_one, 0)))
+
+INSN(sploopw, nfu, loop_buffer, 1cycle, C64XP,
+     TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP,
+     FIX4(FIX(s, 0), FIX(op, 0xf), FIX(csta, 0), RAN(cstb, 0, 13)),
+     OP1(OACST),
+     ENC1(ENC(cstb, ucst_minus_one, 0)))
+
+/* 16 bits insn */
+INSN(sploop, nfu, uspl, 1cycle, C64XP,
+     TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP,
+     FIX1(FIX(op, 0)),
+     OP1(OACST),
+     ENC1(ENC(ii, ucst_minus_one, 0)))
+
+INSN(sploopd, nfu, uspl, 1cycle, C64XP,
+     TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP,
+     FIX1(FIX(op, 1)),
+     OP1(OACST),
+     ENC1(ENC(ii, ucst_minus_one, 0)))
+
+INSN(sploopd, nfu, uspldr, 1cycle, C64XP,
+     TIC6X_FLAG_FIRST|TIC6X_FLAG_NO_MCNOP|TIC6X_FLAG_SPLOOP|TIC6X_FLAG_INSN16_SPRED,
+     FIX0(),
+     OP1(OACST),
+     ENC1(ENC(ii, ucst_minus_one, 0)))
+/**/
+
+
+/* Contrary to SPRUFE8, this is the correct encoding for this
+   instruction.  */
+INSN(spmask, nfu, spmask, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK,
+     FIX2(FIX(s, 0), FIX(op, 0x8)),
+     OP1(OFULIST),
+     ENC1(ENC(mask, spmask, 0)))
+
+/* 16 bits insn */
+INSN(spmask, nfu, uspma, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK,
+     FIX0(),
+     OP1(OFULIST),
+     ENC1(ENC(mask, spmask, 0)))
+/**/
+
+INSN(spmaskr, nfu, spmask, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK,
+     FIX2(FIX(s, 0), FIX(op, 0x9)),
+     OP1(OFULIST),
+     ENC1(ENC(mask, spmask, 0)))
+
+/* 16 bits insn */
+INSN(spmaskr, nfu, uspmb, 1cycle, C64XP, TIC6X_FLAG_FIRST|TIC6X_FLAG_SPMASK,
+     FIX0(),
+     OP1(OFULIST),
+     ENC1(ENC(mask, spmask, 0)))
+/**/
+
+INSN(sptrunc, l, 1_or_2_src, 4cycle, C67X, 0,
+     FIX2(FIX(op, 0x0b), FIX(src1, 0)),
+     OP2(ORXREG1, OWREG4),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSNE(sshl, s_xsi_ui_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x23)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(sshl, s_xsi_u5_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x22)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, ucst, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(sshl, s, ssh5_sat_1, 1cycle, C64XP,
+      TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x2)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0),
+           ENC(cst, ucst, 1),  ENC(srcdst, reg, 2)))
+INSN(sshl, s, s2sh, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 0x3)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(src1, reg, 1),
+           ENC(srcdst, reg, 2)))
+/**/
+
+INSN(sshvl, m, compound, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x1c)),
+     OP3(ORXREG1, ORREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+/* Contrary to SPRUFE8, this is the correct encoding for this
+   instruction.  */
+INSN(sshvr, m, compound, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x1a)),
+     OP3(ORXREG1, ORREG1, OWREG2),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(ssub, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x0f)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(ssub, l_xsi_si_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x1f)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(ssub, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x0e)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(ssub, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x2c)),
+      OP3(OACST, ORREGL1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(ssub, l, l3_sat_1, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 1)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+          ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/**/
+
+INSN(ssub2, l, 1_or_2_src, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x64)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(stb, d, load_store, store, C62X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 3), FIX(r, 0)),
+     OP2(ORDREG1, OWMEMSB),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+	  ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+	  ENC(srcdst, reg, 0)))
+INSN(stb, d, load_store_long, store, C62X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 3)),
+     OP2(ORDREG1, OWMEMLB),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_byte, 1),
+	  ENC(dst, reg, 0)))
+
+/* 16 bits insn */
+INSN(stb, d, doff4_dsz_000, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSB),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1)))
+INSN(stb, d, doff4_dsz_x01, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSB),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1)))
+INSN(stb, d, dind_dsz_000, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSB),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset, 1),
+          ENC(ptr, reg_ptr, 1), ENC(srcdst, reg, 0)))
+INSN(stb, d, dind_dsz_x01, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSB),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset, 1),
+          ENC(ptr, reg_ptr, 1), ENC(srcdst, reg, 0)))
+INSN(stb, d, dinc_dsz_000, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSB),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+INSN(stb, d, dinc_dsz_x01, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSB),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+INSN(stb, d, ddec_dsz_000, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSB),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+INSN(stb, d, ddec_dsz_x01, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSB),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+/**/
+
+INSN(stdw, d, load_store, store, C64X, TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 4), FIX(r, 1)),
+     OP2(ORDREGD1, OWMEMSD),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+	  ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+	  ENC(srcdst, reg, 0)))
+
+/* 16 bits insn */
+INSN(stdw, d, dpp, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTDECR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS,
+     FIX3(FIX(op, 0), FIX(dw, 1), FIX(s, 1)),
+     OP2(ORTREGD1, OWMEMSD),
+     ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+	  ENC(cst, mem_offset_minus_one, 1)))
+INSN(stdw, d, ddecdw, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX3(FIX(op, 0), FIX(na, 0), FIX(sz, 0)),
+     OP2(ORTREGD1, OWMEMSD),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+INSN(stdw, d, dincdw, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX3(FIX(op, 0), FIX(na, 0), FIX(sz, 0)),
+     OP2(ORTREGD1, OWMEMSD),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+INSN(stdw, d, dinddw, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX3(FIX(op, 0), FIX(na, 0), FIX(sz, 0)),
+     OP2(ORTREGD1, OWMEMSD),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset, 1),
+          ENC(ptr, reg_ptr, 1), ENC(srcdst, reg_shift, 0)))
+INSN(stdw, d, doff4dw, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX3(FIX(op, 0), FIX(na, 0), FIX(sz, 0)),
+     OP2(ORTREGD1, OWMEMSD),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset, 1),
+          ENC(ptr, reg_ptr, 1), ENC(srcdst, reg_shift, 0)))
+/**/
+
+INSN(sth, d, load_store, store, C62X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 5), FIX(r, 0)),
+     OP2(ORDREG1, OWMEMSH),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+	  ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+	  ENC(srcdst, reg, 0)))
+INSN(sth, d, load_store_long, store, C62X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 5)),
+     OP2(ORDREG1, OWMEMLH),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_half, 1),
+	  ENC(dst, reg, 0)))
+
+/* 16 bits insn */
+INSN(sth, d, doff4_dsz_01x, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSH),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1)))
+INSN(sth, d, doff4_dsz_111, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSH),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1)))
+INSN(sth, d, dind_dsz_01x, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSH),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(src1, mem_offset, 1)))
+INSN(sth, d, dind_dsz_111, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSH),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(src1, mem_offset, 1)))
+INSN(sth, d, dinc_dsz_01x, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSH),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+INSN(sth, d, dinc_dsz_111, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSH),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+INSN(sth, d, ddec_dsz_01x, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSH),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+INSN(sth, d, ddec_dsz_111, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSH),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+/**/
+
+INSN(stndw, d, store_nonaligned, store, C64X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+     FIX0(),
+     OP2(ORDREGD1, OWMEMND),
+     ENC7(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+	  ENC(offsetR, mem_offset_noscale, 1), ENC(baseR, reg, 1),
+	  ENC(sc, scaled, 1), ENC(src, reg_shift, 0)))
+
+/* 16 bits insn */
+INSN(stndw, d, ddecdw, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX3(FIX(op, 0), FIX(na, 1), FIX(sz, 0)),
+     OP2(ORTREGD1, OWMEMND),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one_noscale, 1)))
+INSN(stndw, d, dincdw, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX3(FIX(op, 0), FIX(na, 1), FIX(sz, 0)),
+     OP2(ORTREGD1, OWMEMND),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg_shift, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one_noscale, 1)))
+INSN(stndw, d, dinddw, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX3(FIX(op, 0), FIX(na, 1), FIX(sz, 0)),
+     OP2(ORTREGD1, OWMEMND),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(src1, mem_offset_noscale, 1),
+          ENC(ptr, reg_ptr, 1), ENC(srcdst, reg_shift, 0)))
+INSN(stndw, d, doff4dw, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX3(FIX(op, 0), FIX(na, 1), FIX(sz, 0)),
+     OP2(ORTREGD1, OWMEMND),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(cst, mem_offset_noscale, 1),
+          ENC(ptr, reg_ptr, 1), ENC(srcdst, reg_shift, 0)))
+/**/
+
+INSN(stnw, d, load_store, store, C64X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_UNALIGNED,
+     FIX2(FIX(op, 5), FIX(r, 1)),
+     OP2(ORDREG1, OWMEMSW),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+	  ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+	  ENC(srcdst, reg, 0)))
+
+/* 16 bits insn */
+INSN(stnw, d, doff4_dsz_110, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSW),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1)))
+INSN(stnw, d, dind_dsz_110, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSW),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(src1, mem_offset, 1)))
+INSN(stnw, d, dinc_dsz_110, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSW),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+INSN(stnw, d, ddec_dsz_110, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSW),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+/**/
+
+INSN(stw, d, load_store, store, C62X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+     FIX2(FIX(op, 7), FIX(r, 0)),
+     OP2(ORDREG1, OWMEMSW),
+     ENC6(ENC(s, data_fu, 0), ENC(y, fu, 0), ENC(mode, mem_mode, 1),
+	  ENC(offsetR, mem_offset, 1), ENC(baseR, reg, 1),
+	  ENC(srcdst, reg, 0)))
+INSN(stw, d, load_store_long, store, C62X,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_SIDE_B_ONLY|TIC6X_FLAG_PREFER(0),
+     FIX1(FIX(op, 7)),
+     OP2(ORDREG1, OWMEMLW),
+     ENC4(ENC(s, data_fu, 0), ENC(y, areg, 1), ENC(offsetR, ulcst_dpr_word, 1),
+	  ENC(dst, reg, 0)))
+
+/* 16 bits insn */
+INSN(stw, d, doff4_dsz_0xx, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX2(FIX(op, 0), FIX(sz, 0)),
+     OP2(ORTREG1, OWMEMSW),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1)))
+INSN(stw, d, doff4_dsz_100, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSW),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset, 1)))
+INSN(stw, d, dind_dsz_0xx, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX2(FIX(op, 0), FIX(sz, 0)),
+     OP2(ORTREG1, OWMEMSW),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(src1, mem_offset, 1)))
+INSN(stw, d, dind_dsz_100, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(REG_POSITIVE),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSW),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(src1, mem_offset, 1)))
+INSN(stw, d, dinc_dsz_0xx, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX2(FIX(op, 0), FIX(sz, 0)),
+     OP2(ORTREG1, OWMEMSW),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+INSN(stw, d, dinc_dsz_100, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTINCR),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSW),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+INSN(stw, d, ddec_dsz_0xx, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX2(FIX(op, 0), FIX(sz, 0)),
+     OP2(ORTREG1, OWMEMSW),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+INSN(stw, d, ddec_dsz_100, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREDECR),
+     FIX2(FIX(op, 0), FIX(sz, 1)),
+     OP2(ORTREG1, OWMEMSW),
+     ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+          ENC(ptr, reg_ptr, 1), ENC(cst, mem_offset_minus_one, 1)))
+INSN(stw, d, dpp, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSTDECR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS,
+     FIX2(FIX(op, 0), FIX(dw, 0)),
+     OP2(ORTREG1, OWMEMSW),
+     ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+	  ENC(cst, mem_offset_minus_one, 1)))
+INSN(stw, d, dstk, store, C64XP,
+     TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE)|TIC6X_FLAG_INSN16_B15PTR,
+     FIX2(FIX(op, 0x0), FIX(s, 1)),
+     OP2(ORTREG1, OWMEMSW),
+     ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 0),
+	  ENC(cst, mem_offset, 1)))
+/**/
+
+INSNE(sub, l_si_xsi_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x07)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_xsi_si_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x17)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_si_xsi_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x27)),
+      OP3(ORREG1, ORXREG1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_xsi_si_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x37)),
+      OP3(ORXREG1, ORREG1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_s5_xsi_si, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x06)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_s5_sl_sl, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x24)),
+      OP3(OACST, ORREGL1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, l_xsi_s5_si, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX1(FIX(op, 0x2)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst_negate, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(sub, l_sl_s5_sl, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+      FIX2(FIX(op, 0x20), FIX(x, 0)),
+      OP3(ORREGL1, OACST, OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src1, scst_negate, 1), ENC(src2, reg, 0),
+	   ENC(dst, reg, 2)))
+INSNE(sub, s_si_xsi_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x17)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, s_s5_xsi_si, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x16)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+/* Contrary to SPRUFE8, this is the correct encoding for this
+   instruction; this instruction can be predicated.  */
+INSNE(sub, s_xsi_si_si, s, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x5)),
+      OP3(ORXREG1, ORREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+INSNE(sub, s_xsi_s5_si, s, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_MACRO,
+      FIX1(FIX(op, 0x6)),
+      OP3(ORXREG1, OACST, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst_negate, 1),
+	   ENC(src2, reg, 0), ENC(dst, reg, 2)))
+INSNE(sub, d_si_si_si, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x11)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(sub, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x13)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+INSNE(sub, d_si_xsi_si, d, ext_1_or_2_src, 1cycle, C64X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0xc)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(sub, l, l3_sat_0, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x1)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+          ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(sub, l, lx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX1(FIX(op, 0x2)),
+     OP3(OHWCST0, ORREG1, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2)))
+INSN(sub, s, sx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x2)),
+      OP3(OHWCST0, ORREG1, OWREG1),
+      ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 1), ENC(srcdst, reg, 2)))
+INSN(sub, s, sx2op, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 0x1)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2),
+           ENC(src2, reg, 1), ENC(x, xpath, 1)))
+INSN(sub, s, s3_sat_x, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x1)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+          ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(sub, d, dx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX1(FIX(op, 0x3)),
+     OP3(ORREG1, OHWCST1, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))
+INSN(sub, d, dx2op, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 0x1)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(srcdst, reg, 0),
+          ENC(src2, reg, 1), ENC(srcdst, reg, 2)))
+/**/
+
+INSNE(subab, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x31)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(subab, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x33)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+
+INSN(subabs4, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x5a)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subah, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x35)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(subah, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x37)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+
+INSNE(subaw, d_si_si_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x39)),
+      OP3(ORREG1, ORREG1, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, reg, 1),
+	   ENC(dst, reg, 2)))
+INSNE(subaw, d_si_u5_si, d, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
+      FIX1(FIX(op, 0x3b)),
+      OP3(ORREG1, OACST, OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(src1, ucst, 1),
+	   ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(subaw, d, dx5p, 1cycle, C64XP, 0,
+     FIX1(FIX(op, 1)),
+     OP3(ORB15REG1, OACST, OWB15REG1),
+     ENC2(ENC(s, fu, 0), ENC(cst, ucst, 1)))
+/**/
+
+INSN(subc, l, 1_or_2_src, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0x4b)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subdp, l_dp_xdp_dp, l, 1_or_2_src, addsubdp, C67X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x19)),
+      OP3(ORREGD12, ORXREGD12, OWREGD67),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subdp, l_xdp_dp_dp, l, 1_or_2_src, addsubdp, C67X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x1d)),
+      OP3(ORXREGD12, ORREGD12, OWREGD67),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subdp, s_dp_xdp_dp, s, l_1_or_2_src, addsubdp, C67XP,
+      TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x73)),
+      OP3(ORREGD12, ORXREGD12, OWREGD67),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subdp, s_xdp_dp_dp, s, l_1_or_2_src, addsubdp, C67XP,
+      TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x77)),
+      OP3(ORXREGD12, ORREGD12, OWREGD67),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subsp, l_sp_xsp_sp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x11)),
+      OP3(ORREG1, ORXREG1, OWREG4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subsp, l_xsp_sp_sp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x15)),
+      OP3(ORXREG1, ORREG1, OWREG4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subsp, s_sp_xsp_sp, s, l_1_or_2_src, 4cycle, C67XP,
+      TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x71)),
+      OP3(ORREG1, ORXREG1, OWREG4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subsp, s_xsp_sp_sp, s, l_1_or_2_src, 4cycle, C67XP,
+      TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x75)),
+      OP3(ORXREG1, ORREG1, OWREG4),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	   ENC(src1, reg, 1), ENC(dst, reg, 2)))
+
+INSNE(subu, l_ui_xui_ul, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(1),
+      FIX1(FIX(op, 0x2f)),
+      OP3(ORREG1, ORXREG1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(subu, l_xui_ui_ul, l, 1_or_2_src, 1cycle, C62X, TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x3f)),
+      OP3(ORXREG1, ORREG1, OWREGL1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sub2, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x04)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(sub2, s, 1_or_2_src, 1cycle, C62X, 0,
+     FIX1(FIX(op, 0x11)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSN(sub2, d, ext_1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x5)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(sub4, l, 1_or_2_src, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x66)),
+     OP3(ORREG1, ORXREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(swap2, l, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x1b), FIX(x, 0)),
+     OP2(ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 0), ENC(dst, reg, 1)))
+INSN(swap2, s, 1_or_2_src, 1cycle, C64X, TIC6X_FLAG_MACRO|TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x10), FIX(x, 0)),
+     OP2(ORREG1, OWREG1),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 0), ENC(dst, reg, 1)))
+
+/* Contrary to SPRUFE8, this is the correct encoding for this
+   instruction.  */
+INSN(swap4, l, unary, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x1)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(swe, nfu, swe, 1cycle, C64XP, 0,
+     FIX1(FIX(s, 0)),
+     OP0(),
+     ENC0())
+
+INSN(swenr, nfu, swenr, 1cycle, C64XP, 0,
+     FIX1(FIX(s, 0)),
+     OP0(),
+     ENC0())
+
+INSN(unpkhu4, l, unary, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x03)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+INSN(unpkhu4, s, unary, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x03)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(unpklu4, l, unary, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x02)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+INSN(unpklu4, s, unary, 1cycle, C64X, 0,
+     FIX1(FIX(op, 0x02)),
+     OP2(ORXREG1, OWREG1),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSNE(xor, l_ui_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x6f)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, l_s5_xui_ui, l, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x6e)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, s_ui_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x0b)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, s_s5_xui_ui, s, 1_or_2_src, 1cycle, C62X, 0,
+      FIX1(FIX(op, 0x0a)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, d_ui_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0xe)),
+      OP3(ORREG1, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNE(xor, d_s5_xui_ui, d, ext_1_or_2_src, 1cycle, C64X, 0,
+      FIX1(FIX(op, 0xf)),
+      OP3(OACST, ORXREG1, OWREG1),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
+	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+/* 16 bits insn */
+INSN(xor, l, l2c, 1cycle, C64XP, 0,
+      FIX1(FIX(op, 0x2)),
+      OP3(ORREG1, ORXREG1, OWREG1NORS),
+      ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg, 2)))
+INSNU(xor, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x7), FIX(unit, 0x0)),
+     OP3(ORREG1, OHWCST1, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))
+INSNU(xor, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x7), FIX(unit, 0x1)),
+     OP3(ORREG1, OHWCST1, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))
+INSNU(xor, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS,
+     FIX2(FIX(op, 0x7), FIX(unit, 0x2)),
+     OP3(ORREG1, OHWCST1, OWREG1),
+     ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2)))
+/**/
+
+INSN(xormpy, m, 1_or_2_src, 4cycle, C64XP, 0,
+     FIX1(FIX(op, 0x1b)),
+     OP3(ORREG1, ORXREG1, OWREG4),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
+
+INSN(xpnd2, m, unary, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x19)),
+     OP2(ORXREG1, OWREG2),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(xpnd4, m, unary, 1616_m, C64X, 0,
+     FIX1(FIX(op, 0x18)),
+     OP2(ORXREG1, OWREG2),
+     ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
+	  ENC(dst, reg, 1)))
+
+INSN(zero, s, mvk, 1cycle, C62X, TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+     FIX2(FIX(h, 0), FIX(cst, 0)),
+     OP1(OWREG1),
+     ENC2(ENC(s, fu, 0), ENC(dst, reg, 0)))
+INSN(zero, l, unary, 1cycle, C64X,
+     TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1),
+     FIX3(FIX(x, 0), FIX(op, 0x05), FIX(src2, 0)),
+     OP1(OWREG1),
+     ENC2(ENC(s, fu, 0), ENC(dst, reg, 0)))
+INSNE(zero, l_sub, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+      FIX2(FIX(op, 0x07), FIX(x, 0)),
+      OP1(OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src1, reg_unused, 0), ENC(src2, reg_unused, 0),
+	   ENC(dst, reg, 0)))
+INSNE(zero, l_sub_sl, l, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO,
+      FIX2(FIX(op, 0x27), FIX(x, 0)),
+      OP1(OWREGL1),
+      ENC4(ENC(s, fu, 0), ENC(src1, reg_unused, 0), ENC(src2, reg_unused, 0),
+	   ENC(dst, reg, 0)))
+INSNE(zero, d_mvk, d, 1_or_2_src, 1cycle, C64X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(1),
+      FIX3(FIX(op, 0x00), FIX(src1, 0), FIX(src2, 0)),
+      OP1(OWREG1),
+      ENC2(ENC(s, fu, 0), ENC(dst, reg, 0)))
+INSNE(zero, d_sub, d, 1_or_2_src, 1cycle, C62X,
+      TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_MACRO|TIC6X_FLAG_PREFER(0),
+      FIX1(FIX(op, 0x11)),
+      OP1(OWREG1),
+      ENC4(ENC(s, fu, 0), ENC(src2, reg_unused, 0), ENC(src1, reg_unused, 0),
+	   ENC(dst, reg, 0)))
+
+#undef TIC6X_INSN_C64X_AND_C67X
+#undef tic6x_insn_format_nfu_s_branch_nop_cst
+#undef tic6x_insn_format_s_l_1_or_2_src
+#undef RAN
+#undef FIX
+#undef FIX0
+#undef FIX1
+#undef FIX2
+#undef FIX3
+#undef FIX4
+#undef OP0
+#undef OP1
+#undef OP2
+#undef OP3
+#undef OP4
+#undef OACST
+#undef OLCST
+#undef OHWCSTM1
+#undef OHWCST0
+#undef OHWCST1
+#undef OHWCST5
+#undef OHWCST16
+#undef OHWCST24
+#undef OHWCST31
+#undef OFULIST
+#undef ORIRP1
+#undef ORNRP1
+#undef OWREG1
+#undef OWRETREG1
+#undef ORREG1
+#undef ORDREG1
+#undef ORWREG1
+#undef ORAREG1
+#undef ORXREG1
+#undef ORREG12
+#undef ORREG14
+#undef ORXREG14
+#undef OWREG2
+#undef OWREG4
+#undef OWREG9
+#undef OWDREG5
+#undef OWREGL1
+#undef ORREGL1
+#undef OWREGD1
+#undef ORTREG1
+#undef ORTREGD1
+#undef OWTREG5
+#undef OWTREGD5
+#undef OWREGD12
+#undef OWREGD4
+#undef ORREGD1
+#undef OWREGD45
+#undef OWREGD67
+#undef ORDREGD1
+#undef OWDREGD5
+#undef ORREGD12
+#undef ORXREGD12
+#undef ORXREGD1234
+#undef ORREGD1324
+#undef OWREGD910
+#undef OWILC1
+#undef ORCREG1
+#undef OWCREG1
+#undef OWREG1Z
+#undef ORB15REG1
+#undef OWB15REG1
+#undef ORMEMDW
+#undef OWMEMDW
+#undef ORMEMSB
+#undef OWMEMSB
+#undef ORMEMLB
+#undef OWMEMLB
+#undef ORMEMSH
+#undef OWMEMSH
+#undef ORMEMLH
+#undef OWMEMLH
+#undef ORMEMSW
+#undef OWMEMSW
+#undef ORMEMLW
+#undef OWMEMLW
+#undef ORMEMSD
+#undef OWMEMSD
+#undef ORMEMND
+#undef OWMEMND
+#undef ENC
+#undef ENC0
+#undef ENC1
+#undef ENC2
+#undef ENC3
+#undef ENC4
+#undef ENC5
+#undef ENC6
+#undef ENC7
diff --git a/binutils-2.25/include/opcode/tic6x.h b/binutils-2.25/include/opcode/tic6x.h
new file mode 100644
index 00000000..d76c5e1a
--- /dev/null
+++ b/binutils-2.25/include/opcode/tic6x.h
@@ -0,0 +1,718 @@
+/* TI C6X opcode information.
+   Copyright 2010-2013 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef OPCODE_TIC6X_H
+#define OPCODE_TIC6X_H
+
+#include "bfd.h"
+#include "symcat.h"
+
+/* A field in an instruction format.  The names are based on those
+   used in the architecture manuals.  */
+typedef enum
+  {
+    tic6x_field_baseR,
+    tic6x_field_cc,
+    tic6x_field_creg,
+    tic6x_field_cst,
+    tic6x_field_csta,
+    tic6x_field_cstb,
+    tic6x_field_dst,
+    tic6x_field_dstms,
+    tic6x_field_dw,
+    tic6x_field_fstgfcyc,
+    tic6x_field_h,
+    tic6x_field_ii,
+    tic6x_field_mask,
+    tic6x_field_mode,
+    tic6x_field_n,
+    tic6x_field_na,
+    tic6x_field_offsetR,
+    tic6x_field_op,
+    tic6x_field_p,
+    tic6x_field_ptr,
+    tic6x_field_r,
+    tic6x_field_s,
+    tic6x_field_sc,
+    tic6x_field_src,
+    tic6x_field_src1,
+    tic6x_field_src2,
+    tic6x_field_srcdst,
+    tic6x_field_srcms,
+    tic6x_field_sn,
+    tic6x_field_sz,
+    tic6x_field_unit,
+    tic6x_field_t,
+    tic6x_field_x,
+    tic6x_field_y,
+    tic6x_field_z
+  } tic6x_insn_field_id;
+
+typedef struct
+{
+  /* The least-significant bit position in the field.  */
+  unsigned short low_pos; 
+
+  /* The number of bits in the field.  */
+  unsigned short width;
+  /* The position of the bitfield in the field. */
+  unsigned short pos;
+} tic6x_bitfield;
+
+/* Maximum number of subfields in composite field.  */
+#define TIC6X_MAX_BITFIELDS 4
+
+typedef struct
+{
+  /* The name used to reference the field.  */
+  tic6x_insn_field_id field_id;
+  unsigned int num_bitfields;
+  tic6x_bitfield bitfields[TIC6X_MAX_BITFIELDS];
+} tic6x_insn_field;
+
+/* Maximum number of variable fields in an instruction format.  */
+#define TIC6X_MAX_INSN_FIELDS 11
+
+/* A particular instruction format.  */
+typedef struct
+{
+  /* How many bits in the instruction.  */
+  unsigned int num_bits;
+
+  /* Constant bits in the instruction.  */
+  unsigned int cst_bits;
+
+  /* Mask matching those bits.  */
+  unsigned int mask;
+
+  /* The number of instruction fields.  */
+  unsigned int num_fields;
+
+  /* Descriptions of instruction fields.  */
+  tic6x_insn_field fields[TIC6X_MAX_INSN_FIELDS];
+} tic6x_insn_format;
+
+/* An index into the table of instruction formats.  */
+typedef enum
+  {
+#define FMT(name, num_bits, cst_bits, mask, fields)	\
+  CONCAT2(tic6x_insn_format_, name),
+#include "tic6x-insn-formats.h"
+#undef FMT
+    tic6x_insn_format_max
+  } tic6x_insn_format_id;
+
+/* The table itself.  */
+extern const tic6x_insn_format tic6x_insn_format_table[tic6x_insn_format_max];
+
+/* If instruction format FMT has a field FIELD, return a pointer to
+   the description of that field; otherwise return NULL.  */
+
+const tic6x_insn_field *tic6x_field_from_fmt (const tic6x_insn_format *fmt,
+					      tic6x_insn_field_id field);
+
+/* Description of a field (in an instruction format) whose value is
+   fixed, or constrained to be in a particular range, in a particular
+   opcode.  */
+typedef struct
+{
+  /* The name of the field.  */
+  tic6x_insn_field_id field_id;
+
+  /* The least value of the field in this instruction.  */
+  unsigned int min_val;
+
+  /* The greatest value of the field in this instruction.  */
+  unsigned int max_val;
+} tic6x_fixed_field;
+
+/* Pseudo opcode fields position for compact instructions
+   If 16 bits instruction detected, the opcode is enriched
+   [DSZ/3][BR][SAT][opcode] */
+#define TIC6X_COMPACT_SAT_POS 16
+#define TIC6X_COMPACT_BR_POS 17
+#define TIC6X_COMPACT_DSZ_POS 18
+
+/* Bit-masks for defining instructions present on some subset of
+   processors; each indicates an instruction present on that processor
+   and those that are supersets of it.  The options passed to the
+   assembler determine a bit-mask ANDed with the bit-mask indicating
+   when the instruction was added to determine whether the instruction
+   is enabled.  */
+#define TIC6X_INSN_C62X		0x0001
+#define TIC6X_INSN_C64X		0x0002
+#define TIC6X_INSN_C64XP	0x0004
+#define TIC6X_INSN_C67X		0x0008
+#define TIC6X_INSN_C67XP	0x0010
+#define TIC6X_INSN_C674X	0x0020
+
+/* Flags with further information about an opcode table entry.  */
+
+/* Only used by the assembler, not the disassembler.  */
+#define TIC6X_FLAG_MACRO	0x0001
+
+/* Must be first in its execute packet.  */
+#define TIC6X_FLAG_FIRST	0x0002
+
+/* Multi-cycle NOP (not used for the NOP n instruction itself, which
+   is only a multicycle NOP if n > 1).  */
+#define TIC6X_FLAG_MCNOP	0x0004
+
+/* Cannot be in parallel with a multi-cycle NOP.  */
+#define TIC6X_FLAG_NO_MCNOP	0x0008
+
+/* Load instruction.  */
+#define TIC6X_FLAG_LOAD		0x0010
+
+/* Store instruction.  */
+#define TIC6X_FLAG_STORE	0x0020
+
+/* Unaligned memory operation.  */
+#define TIC6X_FLAG_UNALIGNED	0x0040
+
+/* Only on side B.  */
+#define TIC6X_FLAG_SIDE_B_ONLY	0x0080
+
+/* Only on data path T2.  */
+#define TIC6X_FLAG_SIDE_T2_ONLY	0x0100
+
+/* Does not support cross paths.  */
+#define TIC6X_FLAG_NO_CROSS	0x0200
+
+/* Annotate this branch instruction as a call.  */
+#define TIC6X_FLAG_CALL		0x0400
+
+/* Annotate this branch instruction as a return.  */
+#define TIC6X_FLAG_RETURN	0x0800
+
+/* This instruction starts a software pipelined loop.  */
+#define TIC6X_FLAG_SPLOOP	0x1000
+
+/* This instruction ends a software pipelined loop.  */
+#define TIC6X_FLAG_SPKERNEL	0x2000
+
+/* This instruction takes a list of functional units as parameters;
+   although described as having one parameter, the number may be 0 to
+   8.  */
+#define TIC6X_FLAG_SPMASK	0x4000
+
+/* When more than one opcode matches the assembly source, prefer the
+   one with the highest value for this bit-field.  If two opcode table
+   entries can match the same syntactic form, they must have different
+   values here.  */
+#define TIC6X_PREFER_VAL(n)	(((n) & 0x8000) >> 15)
+#define TIC6X_FLAG_PREFER(n)	((n) << 15)
+
+/* 16 bits opcode is predicated by register a0 (s = 0) or b0 (s = 1) */
+#define TIC6X_FLAG_INSN16_SPRED      0x00100000
+/* 16 bits opcode ignores RS bit of fetch packet header */
+#define TIC6X_FLAG_INSN16_NORS       0x00200000
+/* 16 bits opcode only on side B */
+#define TIC6X_FLAG_INSN16_BSIDE      0x00400000
+/* 16 bits opcode ptr reg is b15 */
+#define TIC6X_FLAG_INSN16_B15PTR     0x00800000
+/* 16 bits opcode memory access modes */
+#define TIC6X_INSN16_MEM_MODE(n)           ((n) << 16)
+#define TIC6X_INSN16_MEM_MODE_VAL(n) (((n) & 0x000F0000) >> 16)
+#define TIC6X_MEM_MODE_NEGATIVE      0
+#define TIC6X_MEM_MODE_POSITIVE      1
+#define TIC6X_MEM_MODE_REG_NEGATIVE  4
+#define TIC6X_MEM_MODE_REG_POSITIVE  5
+#define TIC6X_MEM_MODE_PREDECR       8
+#define TIC6X_MEM_MODE_PREINCR       9
+#define TIC6X_MEM_MODE_POSTDECR      10
+#define TIC6X_MEM_MODE_POSTINCR      11
+
+#define TIC6X_FLAG_INSN16_MEM_MODE(mode) TIC6X_INSN16_MEM_MODE(TIC6X_MEM_MODE_##mode)
+
+#define TIC6X_NUM_PREFER	2
+
+/* Maximum number of fixed fields for a particular opcode.  */
+#define TIC6X_MAX_FIXED_FIELDS 4
+
+/* Maximum number of operands in the opcode table for a particular
+   opcode.  */
+#define TIC6X_MAX_OPERANDS 4
+
+/* Maximum number of operands in the source code for a particular
+   opcode (different from the number in the opcode table for SPMASK
+   and SPMASKR).  */
+#define TIC6X_MAX_SOURCE_OPERANDS 8
+
+/* Maximum number of variable fields for a particular opcode.  */
+#define TIC6X_MAX_VAR_FIELDS 7
+
+/* Which functional units an opcode uses.  This only describes the
+   basic choice of D, L, M, S or no functional unit; other fields are
+   used to describe further restrictions (instructions only operating
+   on one side), use of cross paths and load/store instructions using
+   one side for the address and the other side for the source or
+   destination register.  */
+typedef enum
+  {
+    tic6x_func_unit_d,
+    tic6x_func_unit_l,
+    tic6x_func_unit_m,
+    tic6x_func_unit_s,
+    tic6x_func_unit_nfu
+  } tic6x_func_unit_base;
+
+/* Possible forms of source operand.  */
+typedef enum
+  {
+    /* An assembly-time constant.  */
+    tic6x_operand_asm_const,
+    /* A link-time constant.  */
+    tic6x_operand_link_const,
+    /* A register, from the same side as the functional unit
+       selected.  */
+    tic6x_operand_reg,
+    /* A register, from the same side as the functional unit
+       selected that ignore RS header bit */
+    tic6x_operand_reg_nors,
+    /* A register, from the b side */
+    tic6x_operand_reg_bside,
+    /* A register, from the b side and from the low register set */
+    tic6x_operand_reg_bside_nors,
+    /* A register, that is from the other side if a cross path is
+       used.  */
+    tic6x_operand_xreg,
+    /* A register, that is from the side of the data path
+       selected.  */
+    tic6x_operand_dreg,
+    /* An address register usable with 15-bit offsets (B14 or B15).
+       This is from the same side as the functional unit if a cross
+       path is not used, and the other side if a cross path is
+       used.  */
+    tic6x_operand_areg,
+    /* The B15 register */
+    tic6x_operand_b15reg,
+    /* A register coded as an offset from either A16 or B16 depending
+       on the value of the t bit. */
+    tic6x_operand_treg,
+    /* A register (A0 or B0), from the same side as the
+       functional unit selected.  */
+    tic6x_operand_zreg,
+    /* A return address register (A3 or B3), from the same side as the
+       functional unit selected.  */
+    tic6x_operand_retreg,
+    /* A register pair, from the same side as the functional unit
+       selected.  */
+    tic6x_operand_regpair,
+    /* A register pair, that is from the other side if a cross path is
+       used.  */
+    tic6x_operand_xregpair,
+    /* A register pair, from the side of the data path selected.  */
+    tic6x_operand_dregpair,
+    /* A register pair coded as an offset from either A16 or B16 depending
+       on the value of the t bit. */
+    tic6x_operand_tregpair,
+    /* The literal string "irp" (case-insensitive).  */
+    tic6x_operand_irp,
+    /* The literal string "nrp" (case-insensitive).  */
+    tic6x_operand_nrp,
+    /* The literal string "ilc" (case-insensitive).  */
+	tic6x_operand_ilc,
+    /* A control register.  */
+    tic6x_operand_ctrl,
+    /* A memory reference (base and offset registers from the side of
+       the functional unit selected), using either unsigned 5-bit
+       constant or register offset, if any offset; register offsets
+       cannot use unscaled () syntax.  */
+    tic6x_operand_mem_short,
+    /* A memory reference (base and offset registers from the side of
+       the functional unit selected), using either unsigned 5-bit
+       constant or register offset, if any offset; register offsets
+       can use unscaled () syntax (for LDNDW and STNDW).  */
+    tic6x_operand_mem_ndw,
+    /* A memory reference using 15-bit link-time constant offset
+       relative to B14 or B15.  */
+    tic6x_operand_mem_long,
+    /* A memory reference that only dereferences a register with no
+       further adjustments (*REG), that register being from the side
+       of the functional unit selected.  */
+    tic6x_operand_mem_deref,
+    /* A functional unit name or a list thereof (for SPMASK and
+       SPMASKR).  */
+    tic6x_operand_func_unit,
+    /* Hardwired constant '5' in Sbu8 Scs10 and Sbu8c 16 bits
+       instruction formats - spru732j.pdf Appendix F.4 */
+    tic6x_operand_hw_const_minus_1,
+    tic6x_operand_hw_const_0,
+    tic6x_operand_hw_const_1,
+    tic6x_operand_hw_const_5,
+    tic6x_operand_hw_const_16,
+    tic6x_operand_hw_const_24,
+    tic6x_operand_hw_const_31
+  } tic6x_operand_form;
+
+/* Whether something is, or can be, read or written.  */
+typedef enum
+  {
+    tic6x_rw_none,
+    tic6x_rw_read,
+    tic6x_rw_write,
+    tic6x_rw_read_write
+  } tic6x_rw;
+
+/* Description of a source operand and how it is used.  */
+typedef struct
+{
+  /* The syntactic form of the operand.  */
+  tic6x_operand_form form;
+
+  /* For non-constant operands, the size in bytes (1, 2, 4, 5 or
+     8).  Ignored for constant operands.  */
+  unsigned int size;
+
+  /* Whether the operand is read, written or both.  In addition to the
+     operations described here, address registers are read on cycle 1
+     regardless of when the memory operand is read or written, and may
+     be modified as described by the addressing mode, and control
+     registers may be implicitly read by some instructions.  There are
+     also some special cases not fully described by this
+     structure.
+
+     - For mpydp, the low part of src2 is read on cycles 1 and 3 but
+       not 2, and the high part on cycles 2 and 4 but not 3.
+
+     - The swap2 pseudo-operation maps to packlh2, reading the first
+       operand of swap2 twice.  */
+  tic6x_rw rw;
+
+  /* The first and last cycles (1 for E1, etc.) at which the operand,
+     or the low part for two-register operands, is read or
+     written.  */
+  unsigned short low_first;
+  unsigned short low_last;
+
+  /* Likewise, for the high part.  */
+  unsigned short high_first;
+  unsigned short high_last;
+} tic6x_operand_info;
+
+/* Ways of converting an operand or functional unit specifier to a
+   field value.  */
+typedef enum
+  {
+    /* Store an unsigned assembly-time constant (which must fit) in
+       the field.  */
+    tic6x_coding_ucst,
+    /* Store a signed constant (which must fit) in the field.  This
+       may be used both for assembly-time constants and for link-time
+       constants.  */
+    tic6x_coding_scst,
+    /* Subtract one from an unsigned assembly-time constant (which
+       must be strictly positive before the subtraction) and store the
+       value (which must fit) in the field.  */
+    tic6x_coding_ucst_minus_one,
+    /* Negate a signed assembly-time constant, and store the result of
+       negation (which must fit) in the field.  Used only for
+       pseudo-operations.  */
+    tic6x_coding_scst_negate,
+    /* Store an unsigned link-time constant, implicitly DP-relative
+       and counting in bytes, in the field.  For expression operands,
+       assembly-time constants are encoded as-is.  For memory
+       reference operands, the offset is encoded as-is if [] syntax is
+       used and shifted if () is used.  */
+    tic6x_coding_ulcst_dpr_byte,
+    /* Store an unsigned link-time constant, implicitly DP-relative
+       and counting in half-words, in the field.  For expression
+       operands, assembly-time constants are encoded as-is.  For
+       memory reference operands, the offset is encoded as-is if []
+       syntax is used and shifted if () is used.  */
+    tic6x_coding_ulcst_dpr_half,
+    /* Store an unsigned link-time constant, implicitly DP-relative
+       and counting in words, in the field.  For expression operands,
+       assembly-time constants are encoded as-is.  For memory
+       reference operands, the offset is encoded as-is if [] syntax is
+       used and shifted if () is used.  */
+    tic6x_coding_ulcst_dpr_word,
+    /* Store the low 16 bits of a link-time constant in the field;
+       considered unsigned for disassembly.  */
+    tic6x_coding_lcst_low16,
+    /* Store the high 16 bits of a link-time constant in the field;
+       considered unsigned for disassembly.  */
+    tic6x_coding_lcst_high16,
+    /* Store a signed PC-relative value (address of label minus
+       address of fetch packet containing the current instruction,
+       counted in words) in the field.  */
+    tic6x_coding_pcrel,
+    /* Likewise, but counting in half-words if in a header-based fetch
+       packet.  */
+    tic6x_coding_pcrel_half,
+    /* Store an unsigned PC-relative value used in compact insn */
+    tic6x_coding_pcrel_half_unsigned,
+    /* Encode the register number (even number for a register pair) in
+       the field.  When applied to a memory reference, encode the base
+       register.  */
+    tic6x_coding_reg,
+    /* Encode the register-pair's lsb (even register) for instructions
+       that use src1 as port for loading lsb of double-precision
+       operand value (absdp, dpint, dpsp, dptrunc, rcpdp, rsqrdp).  */
+    tic6x_coding_regpair_lsb,
+    /* Encode the register-pair's msb (odd register), see above.  */ 
+    tic6x_coding_regpair_msb,
+    /* Store 0 for register B14, 1 for register B15.  When applied to
+       a memory reference, encode the base register.  */
+    tic6x_coding_areg,
+    /* Compact instruction offset base register */
+    tic6x_coding_reg_ptr,
+    /* Store the low part of a control register address.  */
+    tic6x_coding_crlo,
+    /* Store the high part of a control register address.  */
+    tic6x_coding_crhi,
+    /* Encode the even register number for a register pair, shifted
+       right by one bit.  */
+    tic6x_coding_reg_shift,
+    /* Store either the offset register or the 5-bit unsigned offset
+       for a memory reference.  If an offset uses the unscaled ()
+       form, which is only permitted with constants, it is scaled
+       according to the access size of the operand before being
+       stored.  */
+    tic6x_coding_mem_offset,
+    /* Store either the offset register or the 5-bit unsigned offset
+       for a memory reference, but with no scaling applied to the
+       offset (for nonaligned doubleword operations).  */
+    tic6x_coding_mem_offset_noscale,
+    /* Store the addressing mode for a memory reference.  */
+    tic6x_coding_mem_mode,
+    /* Store whether a memory reference is scaled.  */
+    tic6x_coding_scaled,
+    /* Store the stage in an SPKERNEL instruction in the upper part of
+       the field.  */
+    tic6x_coding_fstg,
+    /* Store the cycle in an SPKERNEL instruction in the lower part of
+       the field.  */
+    tic6x_coding_fcyc,
+    /* Store the mask bits for functional units in the field in an
+       SPMASK or SPMASKR instruction.  */
+    tic6x_coding_spmask,
+    /* Store the number of a register that is unused, or minimally
+       used, in this execute packet.  The number must be the same for
+       all uses of this coding in a single instruction, but may be
+       different for different instructions in the execute packet.
+       This is for the "zero" pseudo-operation.  This is not safe when
+       reads may occur from instructions in previous execute packets;
+       in such cases the programmer or compiler should use explicit
+       "sub" instructions for those cases of "zero" that cannot be
+       implemented as "mvk" for the processor specified.  */
+    tic6x_coding_reg_unused,
+    /* Store 1 if the functional unit used is on side B, 0 for side
+       A.  */
+    tic6x_coding_fu,
+    /* Store 1 if the data path used (source register for store,
+       destination for load) is on side B, 0 for side A.  */
+    tic6x_coding_data_fu,
+    /* Store 1 if the cross path is being used, 0 otherwise.  */
+    tic6x_coding_xpath,
+    /* L3i constant coding */
+    tic6x_coding_scst_l3i,
+    /* S3i constant coding */
+    tic6x_coding_cst_s3i,
+    /* mem offset minus 1 */
+    tic6x_coding_mem_offset_minus_one,
+    /* non aligned mem offset minus 1 */
+    tic6x_coding_mem_offset_minus_one_noscale,
+    tic6x_coding_rside
+  } tic6x_coding_method;
+
+/* How to generate the value of a particular field.  */
+typedef struct
+{
+  /* The name of the field.  */
+  tic6x_insn_field_id field_id;
+
+  /* How it is encoded.  */
+  tic6x_coding_method coding_method;
+
+  /* Source operand number, if any.  */
+  unsigned int operand_num;
+} tic6x_coding_field;
+
+/* Types of instruction for pipeline purposes.  The type determines
+   functional unit and cross path latency (when the same functional
+   unit can be used by other instructions, when the same cross path
+   can be used by other instructions).  */
+typedef enum
+  {
+    tic6x_pipeline_nop,
+    tic6x_pipeline_1cycle,
+    tic6x_pipeline_1616_m,
+    tic6x_pipeline_store,
+    tic6x_pipeline_mul_ext,
+    tic6x_pipeline_load,
+    tic6x_pipeline_branch,
+    tic6x_pipeline_2cycle_dp,
+    tic6x_pipeline_4cycle,
+    tic6x_pipeline_intdp,
+    tic6x_pipeline_dpcmp,
+    tic6x_pipeline_addsubdp,
+    tic6x_pipeline_mpyi,
+    tic6x_pipeline_mpyid,
+    tic6x_pipeline_mpydp,
+    tic6x_pipeline_mpyspdp,
+    tic6x_pipeline_mpysp2dp
+  } tic6x_pipeline_type;
+
+/* Description of a control register.  */
+typedef struct
+{
+  /* The name of the register.  */
+  const char *name;
+
+  /* Which ISA variants include this control register.  */
+  unsigned short isa_variants;
+
+  /* Whether it can be read, written or both (in supervisor mode).
+     Some registers use the same address, but different names, for
+     reading and writing.  */
+  tic6x_rw rw;
+
+  /* crlo value for this register.  */
+  unsigned int crlo;
+
+  /* Mask that, ANDed with the crhi value in the instruction, must be
+     0.  0 is always generated when generating code.  */
+  unsigned int crhi_mask;
+} tic6x_ctrl;
+
+/* An index into the table of control registers.  */
+typedef enum
+  {
+#define CTRL(name, isa, rw, crlo, crhi_mask)	\
+    CONCAT2(tic6x_ctrl_,name),
+#include "tic6x-control-registers.h"
+#undef CTRL
+    tic6x_ctrl_max
+  } tic6x_ctrl_id;
+
+/* The table itself.  */
+extern const tic6x_ctrl tic6x_ctrl_table[tic6x_ctrl_max];
+
+/* An entry in the opcode table.  */
+typedef struct
+{
+  /* The name of the instruction.  */
+  const char *name;
+
+  /* Functional unit used by this instruction (basic information).  */
+  tic6x_func_unit_base func_unit;
+
+  /* The format of this instruction.  */
+  tic6x_insn_format_id format;
+
+  /* The pipeline type of this instruction.  */
+  tic6x_pipeline_type type;
+
+  /* Which ISA variants include this instruction.  */
+  unsigned short isa_variants;
+
+  /* Flags for this instruction.  */
+  unsigned int flags;
+
+  /* Number of fixed fields, or fields with restricted value ranges,
+     for this instruction.  */
+  unsigned int num_fixed_fields;
+
+  /* Values of fields fixed for this instruction.  */
+  tic6x_fixed_field fixed_fields[TIC6X_MAX_FIXED_FIELDS];
+
+  /* The number of operands in the source form of this
+     instruction.  */
+  unsigned int num_operands;
+
+  /* Information about individual operands.  */
+  tic6x_operand_info operand_info[TIC6X_MAX_OPERANDS];
+
+  /* The number of variable fields for this instruction with encoding
+     instructions explicitly given.  */
+  unsigned int num_variable_fields;
+
+  /* How fields (other than ones with fixed value) are computed from
+     the source operands and functional unit specifiers.  In addition
+     to fields specified here:
+
+     - creg, if present, is set from the predicate, along with z which
+       must be present if creg is present.
+
+     - p, if present (on all non-compact instructions), is set from
+       the parallel bars.
+  */
+  tic6x_coding_field variable_fields[TIC6X_MAX_VAR_FIELDS];
+} tic6x_opcode;
+
+/* An index into the table of opcodes.  */
+typedef enum
+  {
+#define INSN(name, func_unit, format, type, isa, flags, fixed, ops, var) \
+    CONCAT6(tic6x_opcode_,name,_,func_unit,_,format),
+#define INSNE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
+    CONCAT4(tic6x_opcode_,name,_,e),
+#define INSNU(name, func_unit, format, type, isa, flags, fixed, ops, var) \
+    CONCAT6(tic6x_opcode_,name,_,func_unit,_,format),
+#define INSNUE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
+    CONCAT6(tic6x_opcode_,name,_,func_unit,_,e),
+#include "tic6x-opcode-table.h"
+#undef INSN
+#undef INSNE
+#undef INSNU
+#undef INSNUE
+    tic6x_opcode_max
+  } tic6x_opcode_id;
+
+/* The table itself.  */
+extern const tic6x_opcode tic6x_opcode_table[tic6x_opcode_max];
+
+/* A linked list of opcodes.  */
+typedef struct tic6x_opcode_list_tag
+{
+  tic6x_opcode_id id;
+  struct tic6x_opcode_list_tag *next;
+} tic6x_opcode_list;
+
+/* The information from a fetch packet header.  */
+typedef struct
+{
+  /* The header itself.  */
+  unsigned int header;
+
+  /* Whether each word uses compact instructions.  */
+  bfd_boolean word_compact[7];
+
+  /* Whether loads are protected.  */
+  bfd_boolean prot;
+
+  /* Whether instructions use the high register set.  */
+  bfd_boolean rs;
+
+  /* Data size.  */
+  unsigned int dsz;
+
+  /* Whether compact instructions in the S unit are decoded as
+     branches.  */
+  bfd_boolean br;
+
+  /* Whether compact instructions saturate.  */
+  bfd_boolean sat;
+
+  /* P-bits.  */
+  bfd_boolean p_bits[14];
+} tic6x_fetch_packet_header;
+
+#endif /* OPCODE_TIC6X_H */
diff --git a/binutils-2.25/include/opcode/tic80.h b/binutils-2.25/include/opcode/tic80.h
new file mode 100644
index 00000000..43c84be5
--- /dev/null
+++ b/binutils-2.25/include/opcode/tic80.h
@@ -0,0 +1,283 @@
+/* tic80.h -- Header file for TI TMS320C80 (MV) opcode table
+   Copyright 1996, 1997, 2003, 2010 Free Software Foundation, Inc.
+   Written by Fred Fish (fnf@cygnus.com), Cygnus Support
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef TIC80_H
+#define TIC80_H
+
+/* The opcode table is an array of struct tic80_opcode.  */
+
+struct tic80_opcode
+{
+  /* The opcode name.  */
+
+  const char *name;
+
+  /* The opcode itself.  Those bits which will be filled in with operands
+     are zeroes.  */
+
+  unsigned long opcode;
+
+  /* The opcode mask.  This is used by the disassembler.  This is a mask
+     containing ones indicating those bits which must match the opcode
+     field, and zeroes indicating those bits which need not match (and are
+     presumably filled in by operands).  */
+
+  unsigned long mask;
+
+  /* Special purpose flags for this opcode. */
+
+  unsigned char flags;
+
+  /* An array of operand codes.  Each code is an index into the operand
+     table.  They appear in the order which the operands must appear in
+     assembly code, and are terminated by a zero.  FIXME: Adjust size to
+     match actual requirements when TIc80 support is complete */
+
+  unsigned char operands[8];
+};
+
+/* The table itself is sorted by major opcode number, and is otherwise in
+   the order in which the disassembler should consider instructions.
+   FIXME: This isn't currently true. */
+
+extern const struct tic80_opcode tic80_opcodes[];
+extern const int tic80_num_opcodes;
+
+
+/* The operands table is an array of struct tic80_operand.  */
+
+struct tic80_operand
+{
+  /* The number of bits in the operand.  */
+
+  int bits;
+
+  /* How far the operand is left shifted in the instruction.  */
+
+  int shift;
+
+  /* Insertion function.  This is used by the assembler.  To insert an
+     operand value into an instruction, check this field.
+
+     If it is NULL, execute
+         i |= (op & ((1 << o->bits) - 1)) << o->shift;
+     (i is the instruction which we are filling in, o is a pointer to
+     this structure, and op is the opcode value; this assumes twos
+     complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction and the operand value.  It will return the new value
+     of the instruction.  If the ERRMSG argument is not NULL, then if
+     the operand value is illegal, *ERRMSG will be set to a warning
+     string (the operand will be inserted in any case).  If the
+     operand value is legal, *ERRMSG will be unchanged (most operands
+     can accept any value).  */
+
+  unsigned long (*insert)
+    (unsigned long instruction, long op, const char **errmsg);
+
+  /* Extraction function.  This is used by the disassembler.  To
+     extract this operand type from an instruction, check this field.
+
+     If it is NULL, compute
+         op = ((i) >> o->shift) & ((1 << o->bits) - 1);
+	 if ((o->flags & TIC80_OPERAND_SIGNED) != 0
+	     && (op & (1 << (o->bits - 1))) != 0)
+	   op -= 1 << o->bits;
+     (i is the instruction, o is a pointer to this structure, and op
+     is the result; this assumes twos complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction value.  It will return the value of the operand.  If
+     the INVALID argument is not NULL, *INVALID will be set to
+     non-zero if this operand type can not actually be extracted from
+     this operand (i.e., the instruction does not match).  If the
+     operand is valid, *INVALID will not be changed.  */
+
+  long (*extract) (unsigned long instruction, int *invalid);
+
+  /* One bit syntax flags.  */
+
+  unsigned long flags;
+};
+
+/* Elements in the table are retrieved by indexing with values from
+   the operands field of the tic80_opcodes table.  */
+
+extern const struct tic80_operand tic80_operands[];
+
+
+/* Values defined for the flags field of a struct tic80_operand.
+
+   Note that flags for all predefined symbols, such as the general purpose
+   registers (ex: r10), control registers (ex: FPST), condition codes (ex:
+   eq0.b), bit numbers (ex: gt.b), etc are large enough that they can be
+   or'd into an int where the lower bits contain the actual numeric value
+   that correponds to this predefined symbol.  This way a single int can
+   contain both the value of the symbol and it's type.
+ */
+
+/* This operand must be an even register number.  Floating point numbers
+   for example are stored in even/odd register pairs. */
+
+#define TIC80_OPERAND_EVEN	(1 << 0)
+
+/* This operand must be an odd register number and must be one greater than
+   the register number of the previous operand.  I.E. the second register in
+   an even/odd register pair. */
+
+#define TIC80_OPERAND_ODD	(1 << 1)
+
+/* This operand takes signed values.  */
+
+#define TIC80_OPERAND_SIGNED	(1 << 2)
+
+/* This operand may be either a predefined constant name or a numeric value.
+   An example would be a condition code like "eq0.b" which has the numeric
+   value 0x2. */
+
+#define TIC80_OPERAND_NUM	(1 << 3)
+
+/* This operand should be wrapped in parentheses rather than separated
+   from the previous one by a comma.  This is used for various
+   instructions, like the load and store instructions, which want
+   their operands to look like "displacement(reg)" */
+
+#define TIC80_OPERAND_PARENS	(1 << 4)
+
+/* This operand is a PC relative branch offset.  The disassembler prints
+   these symbolically if possible.  Note that the offsets are taken as word
+   offsets. */
+
+#define TIC80_OPERAND_PCREL	(1 << 5)
+
+/* This flag is a hint to the disassembler for using hex as the prefered
+   printing format, even for small positive or negative immediate values.
+   Normally values in the range -999 to 999 are printed as signed decimal
+   values and other values are printed in hex. */
+
+#define TIC80_OPERAND_BITFIELD	(1 << 6)
+
+/* This operand may have a ":m" modifier specified by bit 17 in a short
+   immediate form instruction. */
+
+#define TIC80_OPERAND_M_SI	(1 << 7)
+
+/* This operand may have a ":m" modifier specified by bit 15 in a long
+   immediate or register form instruction. */
+
+#define TIC80_OPERAND_M_LI	(1 << 8)
+
+/* This operand may have a ":s" modifier specified in bit 11 in a long
+   immediate or register form instruction. */
+
+#define TIC80_OPERAND_SCALED	(1 << 9)
+
+/* This operand is a floating point value */
+
+#define TIC80_OPERAND_FLOAT	(1 << 10)
+
+/* This operand is an byte offset from a base relocation. The lower
+ two bits of the final relocated address are ignored when the value is
+ written to the program counter. */
+
+#define TIC80_OPERAND_BASEREL	(1 << 11)
+
+/* This operand is an "endmask" field for a shift instruction.
+   It is treated special in that it can have values of 0-32,
+   where 0 and 32 result in the same instruction.  The assembler
+   must be able to accept both endmask values.  This disassembler
+   has no way of knowing from the instruction which value was 
+   given at assembly time, so it just uses '0'. */
+
+#define TIC80_OPERAND_ENDMASK	(1 << 12)
+
+/* This operand is one of the 32 general purpose registers.
+   The disassembler prints these with a leading 'r'. */
+
+#define TIC80_OPERAND_GPR	(1 << 27)
+
+/* This operand is a floating point accumulator register.
+   The disassembler prints these with a leading 'a'. */
+
+#define TIC80_OPERAND_FPA	( 1 << 28)
+
+/* This operand is a control register number, either numeric or
+   symbolic (like "EIF", "EPC", etc).
+   The disassembler prints these symbolically. */
+
+#define TIC80_OPERAND_CR	(1 << 29)
+
+/* This operand is a condition code, either numeric or
+   symbolic (like "eq0.b", "ne0.w", etc).
+   The disassembler prints these symbolically. */
+
+#define TIC80_OPERAND_CC	(1 << 30)
+
+/* This operand is a bit number, either numeric or
+   symbolic (like "eq.b", "or.f", etc).
+   The disassembler prints these symbolically.
+   Note that they appear in the instruction in 1's complement relative
+   to the values given in the manual. */
+
+#define TIC80_OPERAND_BITNUM	(1 << 31)
+
+/* This mask is used to strip operand bits from an int that contains
+   both operand bits and a numeric value in the lsbs. */
+
+#define TIC80_OPERAND_MASK	(TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR | TIC80_OPERAND_CC | TIC80_OPERAND_BITNUM)
+
+
+/* Flag bits for the struct tic80_opcode flags field. */
+
+#define TIC80_VECTOR		01	/* Is a vector instruction */
+#define TIC80_NO_R0_DEST	02	/* Register r0 cannot be a destination register */
+
+
+/* The opcodes library contains a table that allows translation from predefined
+   symbol names to numeric values, and vice versa. */
+
+/* Structure to hold information about predefined symbols.  */
+
+struct predefined_symbol
+{
+  char *name;		/* name to recognize */
+  int value;
+};
+
+#define PDS_NAME(pdsp) ((pdsp) -> name)
+#define PDS_VALUE(pdsp) ((pdsp) -> value)
+
+/* Translation array.  */
+extern const struct predefined_symbol tic80_predefined_symbols[];
+/* How many members in the array.  */
+extern const int tic80_num_predefined_symbols;
+
+/* Translate value to symbolic name.  */
+const char *tic80_value_to_symbol (int val, int class);
+
+/* Translate symbolic name to value.  */
+int tic80_symbol_to_value (char *name, int class);
+
+const struct predefined_symbol *tic80_next_predefined_symbol
+  (const struct predefined_symbol *);
+
+#endif /* TIC80_H */
diff --git a/binutils-2.25/include/opcode/tilegx.h b/binutils-2.25/include/opcode/tilegx.h
new file mode 100644
index 00000000..c11fc166
--- /dev/null
+++ b/binutils-2.25/include/opcode/tilegx.h
@@ -0,0 +1,1304 @@
+/* TILE-Gx opcode information.
+ *
+ *    Copyright 2011 Free Software Foundation, Inc.
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 3 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ *    MA 02110-1301, USA.
+ */
+
+#ifndef opcode_tile_h
+#define opcode_tile_h
+
+typedef unsigned long long tilegx_bundle_bits;
+
+
+enum
+{
+  TILEGX_MAX_OPERANDS = 4 /* bfexts */
+};
+
+typedef enum
+{
+  TILEGX_OPC_BPT,
+  TILEGX_OPC_INFO,
+  TILEGX_OPC_INFOL,
+  TILEGX_OPC_LD4S_TLS,
+  TILEGX_OPC_LD_TLS,
+  TILEGX_OPC_MOVE,
+  TILEGX_OPC_MOVEI,
+  TILEGX_OPC_MOVELI,
+  TILEGX_OPC_PREFETCH,
+  TILEGX_OPC_PREFETCH_ADD_L1,
+  TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
+  TILEGX_OPC_PREFETCH_ADD_L2,
+  TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
+  TILEGX_OPC_PREFETCH_ADD_L3,
+  TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
+  TILEGX_OPC_PREFETCH_L1,
+  TILEGX_OPC_PREFETCH_L1_FAULT,
+  TILEGX_OPC_PREFETCH_L2,
+  TILEGX_OPC_PREFETCH_L2_FAULT,
+  TILEGX_OPC_PREFETCH_L3,
+  TILEGX_OPC_PREFETCH_L3_FAULT,
+  TILEGX_OPC_RAISE,
+  TILEGX_OPC_ADD,
+  TILEGX_OPC_ADDI,
+  TILEGX_OPC_ADDLI,
+  TILEGX_OPC_ADDX,
+  TILEGX_OPC_ADDXI,
+  TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXSC,
+  TILEGX_OPC_AND,
+  TILEGX_OPC_ANDI,
+  TILEGX_OPC_BEQZ,
+  TILEGX_OPC_BEQZT,
+  TILEGX_OPC_BFEXTS,
+  TILEGX_OPC_BFEXTU,
+  TILEGX_OPC_BFINS,
+  TILEGX_OPC_BGEZ,
+  TILEGX_OPC_BGEZT,
+  TILEGX_OPC_BGTZ,
+  TILEGX_OPC_BGTZT,
+  TILEGX_OPC_BLBC,
+  TILEGX_OPC_BLBCT,
+  TILEGX_OPC_BLBS,
+  TILEGX_OPC_BLBST,
+  TILEGX_OPC_BLEZ,
+  TILEGX_OPC_BLEZT,
+  TILEGX_OPC_BLTZ,
+  TILEGX_OPC_BLTZT,
+  TILEGX_OPC_BNEZ,
+  TILEGX_OPC_BNEZT,
+  TILEGX_OPC_CLZ,
+  TILEGX_OPC_CMOVEQZ,
+  TILEGX_OPC_CMOVNEZ,
+  TILEGX_OPC_CMPEQ,
+  TILEGX_OPC_CMPEQI,
+  TILEGX_OPC_CMPEXCH,
+  TILEGX_OPC_CMPEXCH4,
+  TILEGX_OPC_CMPLES,
+  TILEGX_OPC_CMPLEU,
+  TILEGX_OPC_CMPLTS,
+  TILEGX_OPC_CMPLTSI,
+  TILEGX_OPC_CMPLTU,
+  TILEGX_OPC_CMPLTUI,
+  TILEGX_OPC_CMPNE,
+  TILEGX_OPC_CMUL,
+  TILEGX_OPC_CMULA,
+  TILEGX_OPC_CMULAF,
+  TILEGX_OPC_CMULF,
+  TILEGX_OPC_CMULFR,
+  TILEGX_OPC_CMULH,
+  TILEGX_OPC_CMULHR,
+  TILEGX_OPC_CRC32_32,
+  TILEGX_OPC_CRC32_8,
+  TILEGX_OPC_CTZ,
+  TILEGX_OPC_DBLALIGN,
+  TILEGX_OPC_DBLALIGN2,
+  TILEGX_OPC_DBLALIGN4,
+  TILEGX_OPC_DBLALIGN6,
+  TILEGX_OPC_DRAIN,
+  TILEGX_OPC_DTLBPR,
+  TILEGX_OPC_EXCH,
+  TILEGX_OPC_EXCH4,
+  TILEGX_OPC_FDOUBLE_ADD_FLAGS,
+  TILEGX_OPC_FDOUBLE_ADDSUB,
+  TILEGX_OPC_FDOUBLE_MUL_FLAGS,
+  TILEGX_OPC_FDOUBLE_PACK1,
+  TILEGX_OPC_FDOUBLE_PACK2,
+  TILEGX_OPC_FDOUBLE_SUB_FLAGS,
+  TILEGX_OPC_FDOUBLE_UNPACK_MAX,
+  TILEGX_OPC_FDOUBLE_UNPACK_MIN,
+  TILEGX_OPC_FETCHADD,
+  TILEGX_OPC_FETCHADD4,
+  TILEGX_OPC_FETCHADDGEZ,
+  TILEGX_OPC_FETCHADDGEZ4,
+  TILEGX_OPC_FETCHAND,
+  TILEGX_OPC_FETCHAND4,
+  TILEGX_OPC_FETCHOR,
+  TILEGX_OPC_FETCHOR4,
+  TILEGX_OPC_FINV,
+  TILEGX_OPC_FLUSH,
+  TILEGX_OPC_FLUSHWB,
+  TILEGX_OPC_FNOP,
+  TILEGX_OPC_FSINGLE_ADD1,
+  TILEGX_OPC_FSINGLE_ADDSUB2,
+  TILEGX_OPC_FSINGLE_MUL1,
+  TILEGX_OPC_FSINGLE_MUL2,
+  TILEGX_OPC_FSINGLE_PACK1,
+  TILEGX_OPC_FSINGLE_PACK2,
+  TILEGX_OPC_FSINGLE_SUB1,
+  TILEGX_OPC_ICOH,
+  TILEGX_OPC_ILL,
+  TILEGX_OPC_INV,
+  TILEGX_OPC_IRET,
+  TILEGX_OPC_J,
+  TILEGX_OPC_JAL,
+  TILEGX_OPC_JALR,
+  TILEGX_OPC_JALRP,
+  TILEGX_OPC_JR,
+  TILEGX_OPC_JRP,
+  TILEGX_OPC_LD,
+  TILEGX_OPC_LD1S,
+  TILEGX_OPC_LD1S_ADD,
+  TILEGX_OPC_LD1U,
+  TILEGX_OPC_LD1U_ADD,
+  TILEGX_OPC_LD2S,
+  TILEGX_OPC_LD2S_ADD,
+  TILEGX_OPC_LD2U,
+  TILEGX_OPC_LD2U_ADD,
+  TILEGX_OPC_LD4S,
+  TILEGX_OPC_LD4S_ADD,
+  TILEGX_OPC_LD4U,
+  TILEGX_OPC_LD4U_ADD,
+  TILEGX_OPC_LD_ADD,
+  TILEGX_OPC_LDNA,
+  TILEGX_OPC_LDNA_ADD,
+  TILEGX_OPC_LDNT,
+  TILEGX_OPC_LDNT1S,
+  TILEGX_OPC_LDNT1S_ADD,
+  TILEGX_OPC_LDNT1U,
+  TILEGX_OPC_LDNT1U_ADD,
+  TILEGX_OPC_LDNT2S,
+  TILEGX_OPC_LDNT2S_ADD,
+  TILEGX_OPC_LDNT2U,
+  TILEGX_OPC_LDNT2U_ADD,
+  TILEGX_OPC_LDNT4S,
+  TILEGX_OPC_LDNT4S_ADD,
+  TILEGX_OPC_LDNT4U,
+  TILEGX_OPC_LDNT4U_ADD,
+  TILEGX_OPC_LDNT_ADD,
+  TILEGX_OPC_LNK,
+  TILEGX_OPC_MF,
+  TILEGX_OPC_MFSPR,
+  TILEGX_OPC_MM,
+  TILEGX_OPC_MNZ,
+  TILEGX_OPC_MTSPR,
+  TILEGX_OPC_MUL_HS_HS,
+  TILEGX_OPC_MUL_HS_HU,
+  TILEGX_OPC_MUL_HS_LS,
+  TILEGX_OPC_MUL_HS_LU,
+  TILEGX_OPC_MUL_HU_HU,
+  TILEGX_OPC_MUL_HU_LS,
+  TILEGX_OPC_MUL_HU_LU,
+  TILEGX_OPC_MUL_LS_LS,
+  TILEGX_OPC_MUL_LS_LU,
+  TILEGX_OPC_MUL_LU_LU,
+  TILEGX_OPC_MULA_HS_HS,
+  TILEGX_OPC_MULA_HS_HU,
+  TILEGX_OPC_MULA_HS_LS,
+  TILEGX_OPC_MULA_HS_LU,
+  TILEGX_OPC_MULA_HU_HU,
+  TILEGX_OPC_MULA_HU_LS,
+  TILEGX_OPC_MULA_HU_LU,
+  TILEGX_OPC_MULA_LS_LS,
+  TILEGX_OPC_MULA_LS_LU,
+  TILEGX_OPC_MULA_LU_LU,
+  TILEGX_OPC_MULAX,
+  TILEGX_OPC_MULX,
+  TILEGX_OPC_MZ,
+  TILEGX_OPC_NAP,
+  TILEGX_OPC_NOP,
+  TILEGX_OPC_NOR,
+  TILEGX_OPC_OR,
+  TILEGX_OPC_ORI,
+  TILEGX_OPC_PCNT,
+  TILEGX_OPC_REVBITS,
+  TILEGX_OPC_REVBYTES,
+  TILEGX_OPC_ROTL,
+  TILEGX_OPC_ROTLI,
+  TILEGX_OPC_SHL,
+  TILEGX_OPC_SHL16INSLI,
+  TILEGX_OPC_SHL1ADD,
+  TILEGX_OPC_SHL1ADDX,
+  TILEGX_OPC_SHL2ADD,
+  TILEGX_OPC_SHL2ADDX,
+  TILEGX_OPC_SHL3ADD,
+  TILEGX_OPC_SHL3ADDX,
+  TILEGX_OPC_SHLI,
+  TILEGX_OPC_SHLX,
+  TILEGX_OPC_SHLXI,
+  TILEGX_OPC_SHRS,
+  TILEGX_OPC_SHRSI,
+  TILEGX_OPC_SHRU,
+  TILEGX_OPC_SHRUI,
+  TILEGX_OPC_SHRUX,
+  TILEGX_OPC_SHRUXI,
+  TILEGX_OPC_SHUFFLEBYTES,
+  TILEGX_OPC_ST,
+  TILEGX_OPC_ST1,
+  TILEGX_OPC_ST1_ADD,
+  TILEGX_OPC_ST2,
+  TILEGX_OPC_ST2_ADD,
+  TILEGX_OPC_ST4,
+  TILEGX_OPC_ST4_ADD,
+  TILEGX_OPC_ST_ADD,
+  TILEGX_OPC_STNT,
+  TILEGX_OPC_STNT1,
+  TILEGX_OPC_STNT1_ADD,
+  TILEGX_OPC_STNT2,
+  TILEGX_OPC_STNT2_ADD,
+  TILEGX_OPC_STNT4,
+  TILEGX_OPC_STNT4_ADD,
+  TILEGX_OPC_STNT_ADD,
+  TILEGX_OPC_SUB,
+  TILEGX_OPC_SUBX,
+  TILEGX_OPC_SUBXSC,
+  TILEGX_OPC_SWINT0,
+  TILEGX_OPC_SWINT1,
+  TILEGX_OPC_SWINT2,
+  TILEGX_OPC_SWINT3,
+  TILEGX_OPC_TBLIDXB0,
+  TILEGX_OPC_TBLIDXB1,
+  TILEGX_OPC_TBLIDXB2,
+  TILEGX_OPC_TBLIDXB3,
+  TILEGX_OPC_V1ADD,
+  TILEGX_OPC_V1ADDI,
+  TILEGX_OPC_V1ADDUC,
+  TILEGX_OPC_V1ADIFFU,
+  TILEGX_OPC_V1AVGU,
+  TILEGX_OPC_V1CMPEQ,
+  TILEGX_OPC_V1CMPEQI,
+  TILEGX_OPC_V1CMPLES,
+  TILEGX_OPC_V1CMPLEU,
+  TILEGX_OPC_V1CMPLTS,
+  TILEGX_OPC_V1CMPLTSI,
+  TILEGX_OPC_V1CMPLTU,
+  TILEGX_OPC_V1CMPLTUI,
+  TILEGX_OPC_V1CMPNE,
+  TILEGX_OPC_V1DDOTPU,
+  TILEGX_OPC_V1DDOTPUA,
+  TILEGX_OPC_V1DDOTPUS,
+  TILEGX_OPC_V1DDOTPUSA,
+  TILEGX_OPC_V1DOTP,
+  TILEGX_OPC_V1DOTPA,
+  TILEGX_OPC_V1DOTPU,
+  TILEGX_OPC_V1DOTPUA,
+  TILEGX_OPC_V1DOTPUS,
+  TILEGX_OPC_V1DOTPUSA,
+  TILEGX_OPC_V1INT_H,
+  TILEGX_OPC_V1INT_L,
+  TILEGX_OPC_V1MAXU,
+  TILEGX_OPC_V1MAXUI,
+  TILEGX_OPC_V1MINU,
+  TILEGX_OPC_V1MINUI,
+  TILEGX_OPC_V1MNZ,
+  TILEGX_OPC_V1MULTU,
+  TILEGX_OPC_V1MULU,
+  TILEGX_OPC_V1MULUS,
+  TILEGX_OPC_V1MZ,
+  TILEGX_OPC_V1SADAU,
+  TILEGX_OPC_V1SADU,
+  TILEGX_OPC_V1SHL,
+  TILEGX_OPC_V1SHLI,
+  TILEGX_OPC_V1SHRS,
+  TILEGX_OPC_V1SHRSI,
+  TILEGX_OPC_V1SHRU,
+  TILEGX_OPC_V1SHRUI,
+  TILEGX_OPC_V1SUB,
+  TILEGX_OPC_V1SUBUC,
+  TILEGX_OPC_V2ADD,
+  TILEGX_OPC_V2ADDI,
+  TILEGX_OPC_V2ADDSC,
+  TILEGX_OPC_V2ADIFFS,
+  TILEGX_OPC_V2AVGS,
+  TILEGX_OPC_V2CMPEQ,
+  TILEGX_OPC_V2CMPEQI,
+  TILEGX_OPC_V2CMPLES,
+  TILEGX_OPC_V2CMPLEU,
+  TILEGX_OPC_V2CMPLTS,
+  TILEGX_OPC_V2CMPLTSI,
+  TILEGX_OPC_V2CMPLTU,
+  TILEGX_OPC_V2CMPLTUI,
+  TILEGX_OPC_V2CMPNE,
+  TILEGX_OPC_V2DOTP,
+  TILEGX_OPC_V2DOTPA,
+  TILEGX_OPC_V2INT_H,
+  TILEGX_OPC_V2INT_L,
+  TILEGX_OPC_V2MAXS,
+  TILEGX_OPC_V2MAXSI,
+  TILEGX_OPC_V2MINS,
+  TILEGX_OPC_V2MINSI,
+  TILEGX_OPC_V2MNZ,
+  TILEGX_OPC_V2MULFSC,
+  TILEGX_OPC_V2MULS,
+  TILEGX_OPC_V2MULTS,
+  TILEGX_OPC_V2MZ,
+  TILEGX_OPC_V2PACKH,
+  TILEGX_OPC_V2PACKL,
+  TILEGX_OPC_V2PACKUC,
+  TILEGX_OPC_V2SADAS,
+  TILEGX_OPC_V2SADAU,
+  TILEGX_OPC_V2SADS,
+  TILEGX_OPC_V2SADU,
+  TILEGX_OPC_V2SHL,
+  TILEGX_OPC_V2SHLI,
+  TILEGX_OPC_V2SHLSC,
+  TILEGX_OPC_V2SHRS,
+  TILEGX_OPC_V2SHRSI,
+  TILEGX_OPC_V2SHRU,
+  TILEGX_OPC_V2SHRUI,
+  TILEGX_OPC_V2SUB,
+  TILEGX_OPC_V2SUBSC,
+  TILEGX_OPC_V4ADD,
+  TILEGX_OPC_V4ADDSC,
+  TILEGX_OPC_V4INT_H,
+  TILEGX_OPC_V4INT_L,
+  TILEGX_OPC_V4PACKSC,
+  TILEGX_OPC_V4SHL,
+  TILEGX_OPC_V4SHLSC,
+  TILEGX_OPC_V4SHRS,
+  TILEGX_OPC_V4SHRU,
+  TILEGX_OPC_V4SUB,
+  TILEGX_OPC_V4SUBSC,
+  TILEGX_OPC_WH64,
+  TILEGX_OPC_XOR,
+  TILEGX_OPC_XORI,
+  TILEGX_OPC_NONE
+} tilegx_mnemonic;
+
+/* 64-bit pattern for a { bpt ; nop } bundle. */
+#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
+
+
+
+static __inline unsigned int
+get_BFEnd_X0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 24)) & 0xf);
+}
+
+static __inline unsigned int
+get_BFStart_X0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 18)) & 0x3f);
+}
+
+static __inline unsigned int
+get_BrOff_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 31)) & 0x0000003f) |
+         (((unsigned int)(n >> 37)) & 0x0001ffc0);
+}
+
+static __inline unsigned int
+get_BrType_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 54)) & 0x1f);
+}
+
+static __inline unsigned int
+get_Dest_Imm8_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 31)) & 0x0000003f) |
+         (((unsigned int)(n >> 43)) & 0x000000c0);
+}
+
+static __inline unsigned int
+get_Dest_X0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 0)) & 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 31)) & 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_Y0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 0)) & 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_Y1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 31)) & 0x3f);
+}
+
+static __inline unsigned int
+get_Imm16_X0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0xffff);
+}
+
+static __inline unsigned int
+get_Imm16_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0xffff);
+}
+
+static __inline unsigned int
+get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 20)) & 0xff);
+}
+
+static __inline unsigned int
+get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 51)) & 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_X0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_Y0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_Y1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0xff);
+}
+
+static __inline unsigned int
+get_JumpOff_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 31)) & 0x7ffffff);
+}
+
+static __inline unsigned int
+get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 58)) & 0x1);
+}
+
+static __inline unsigned int
+get_MF_Imm14_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 37)) & 0x3fff);
+}
+
+static __inline unsigned int
+get_MT_Imm14_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 31)) & 0x0000003f) |
+         (((unsigned int)(n >> 37)) & 0x00003fc0);
+}
+
+static __inline unsigned int
+get_Mode(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 62)) & 0x3);
+}
+
+static __inline unsigned int
+get_Opcode_X0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 28)) & 0x7);
+}
+
+static __inline unsigned int
+get_Opcode_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 59)) & 0x7);
+}
+
+static __inline unsigned int
+get_Opcode_Y0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 27)) & 0xf);
+}
+
+static __inline unsigned int
+get_Opcode_Y1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 58)) & 0xf);
+}
+
+static __inline unsigned int
+get_Opcode_Y2(tilegx_bundle_bits n)
+{
+  return (((n >> 26)) & 0x00000001) |
+         (((unsigned int)(n >> 56)) & 0x00000002);
+}
+
+static __inline unsigned int
+get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 18)) & 0x3ff);
+}
+
+static __inline unsigned int
+get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 49)) & 0x3ff);
+}
+
+static __inline unsigned int
+get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 18)) & 0x3);
+}
+
+static __inline unsigned int
+get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 49)) & 0x3);
+}
+
+static __inline unsigned int
+get_ShAmt_X0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_ShAmt_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+static __inline unsigned int
+get_ShAmt_Y0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_ShAmt_Y1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+static __inline unsigned int
+get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 18)) & 0x3ff);
+}
+
+static __inline unsigned int
+get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 49)) & 0x3ff);
+}
+
+static __inline unsigned int
+get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 18)) & 0x3);
+}
+
+static __inline unsigned int
+get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 49)) & 0x3);
+}
+
+static __inline unsigned int
+get_SrcA_X0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 6)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcA_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 37)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcA_Y0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 6)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcA_Y1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 37)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcA_Y2(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 20)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcBDest_Y2(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 51)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcB_X0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcB_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcB_Y0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcB_Y1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+static __inline unsigned int
+get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+static __inline unsigned int
+get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+
+static __inline int
+sign_extend(int n, int num_bits)
+{
+  int shift = (int)(sizeof(int) * 8 - num_bits);
+  return (n << shift) >> shift;
+}
+
+
+
+static __inline tilegx_bundle_bits
+create_BFEnd_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_BFOpcodeExtension_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0xf) << 24);
+}
+
+static __inline tilegx_bundle_bits
+create_BFStart_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 18);
+}
+
+static __inline tilegx_bundle_bits
+create_BrOff_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
+         (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
+}
+
+static __inline tilegx_bundle_bits
+create_BrType_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
+}
+
+static __inline tilegx_bundle_bits
+create_Dest_Imm8_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
+         (((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_Dest_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 0);
+}
+
+static __inline tilegx_bundle_bits
+create_Dest_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
+}
+
+static __inline tilegx_bundle_bits
+create_Dest_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 0);
+}
+
+static __inline tilegx_bundle_bits
+create_Dest_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm16_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0xffff) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm16_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm8OpcodeExtension_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0xff) << 20);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm8OpcodeExtension_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0xff)) << 51);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm8_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0xff) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm8_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0xff)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm8_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0xff) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm8_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0xff)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_JumpOff_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
+}
+
+static __inline tilegx_bundle_bits
+create_JumpOpcodeExtension_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x1)) << 58);
+}
+
+static __inline tilegx_bundle_bits
+create_MF_Imm14_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
+}
+
+static __inline tilegx_bundle_bits
+create_MT_Imm14_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
+         (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
+}
+
+static __inline tilegx_bundle_bits
+create_Mode(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3)) << 62);
+}
+
+static __inline tilegx_bundle_bits
+create_Opcode_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x7) << 28);
+}
+
+static __inline tilegx_bundle_bits
+create_Opcode_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x7)) << 59);
+}
+
+static __inline tilegx_bundle_bits
+create_Opcode_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0xf) << 27);
+}
+
+static __inline tilegx_bundle_bits
+create_Opcode_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0xf)) << 58);
+}
+
+static __inline tilegx_bundle_bits
+create_Opcode_Y2(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x00000001) << 26) |
+         (((tilegx_bundle_bits)(n & 0x00000002)) << 56);
+}
+
+static __inline tilegx_bundle_bits
+create_RRROpcodeExtension_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3ff) << 18);
+}
+
+static __inline tilegx_bundle_bits
+create_RRROpcodeExtension_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
+}
+
+static __inline tilegx_bundle_bits
+create_RRROpcodeExtension_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3) << 18);
+}
+
+static __inline tilegx_bundle_bits
+create_RRROpcodeExtension_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3)) << 49);
+}
+
+static __inline tilegx_bundle_bits
+create_ShAmt_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_ShAmt_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_ShAmt_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_ShAmt_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3ff) << 18);
+}
+
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
+}
+
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3) << 18);
+}
+
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3)) << 49);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcA_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 6);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcA_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcA_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 6);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcA_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcA_Y2(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 20);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcBDest_Y2(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcB_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcB_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcB_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcB_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
+}
+
+
+typedef enum
+{
+  TILEGX_PIPELINE_X0,
+  TILEGX_PIPELINE_X1,
+  TILEGX_PIPELINE_Y0,
+  TILEGX_PIPELINE_Y1,
+  TILEGX_PIPELINE_Y2,
+} tilegx_pipeline;
+
+#define tilegx_is_x_pipeline(p) ((int)(p) <= (int)TILEGX_PIPELINE_X1)
+
+typedef enum
+{
+  TILEGX_OP_TYPE_REGISTER,
+  TILEGX_OP_TYPE_IMMEDIATE,
+  TILEGX_OP_TYPE_ADDRESS,
+  TILEGX_OP_TYPE_SPR
+} tilegx_operand_type;
+
+/* These are the bits that determine if a bundle is in the X encoding. */
+#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
+
+enum
+{
+  /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
+  TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
+
+  /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
+  TILEGX_NUM_PIPELINE_ENCODINGS = 5,
+
+  /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
+  TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
+
+  /* Instructions take this many bytes. */
+  TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
+
+  /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
+  TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
+
+  /* Bundles should be aligned modulo this number of bytes. */
+  TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
+    (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
+
+  /* Number of registers (some are magic, such as network I/O). */
+  TILEGX_NUM_REGISTERS = 64,
+};
+
+
+struct tilegx_operand
+{
+  /* Is this operand a register, immediate or address? */
+  tilegx_operand_type type;
+
+  /* The default relocation type for this operand.  */
+  signed int default_reloc : 16;
+
+  /* How many bits is this value? (used for range checking) */
+  unsigned int num_bits : 5;
+
+  /* Is the value signed? (used for range checking) */
+  unsigned int is_signed : 1;
+
+  /* Is this operand a source register? */
+  unsigned int is_src_reg : 1;
+
+  /* Is this operand written? (i.e. is it a destination register) */
+  unsigned int is_dest_reg : 1;
+
+  /* Is this operand PC-relative? */
+  unsigned int is_pc_relative : 1;
+
+  /* By how many bits do we right shift the value before inserting? */
+  unsigned int rightshift : 2;
+
+  /* Return the bits for this operand to be ORed into an existing bundle. */
+  tilegx_bundle_bits (*insert) (int op);
+
+  /* Extract this operand and return it. */
+  unsigned int (*extract) (tilegx_bundle_bits bundle);
+};
+
+
+extern const struct tilegx_operand tilegx_operands[];
+
+/* One finite-state machine per pipe for rapid instruction decoding. */
+extern const unsigned short * const
+tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS];
+
+
+struct tilegx_opcode
+{
+  /* The opcode mnemonic, e.g. "add" */
+  const char *name;
+
+  /* The enum value for this mnemonic. */
+  tilegx_mnemonic mnemonic;
+
+  /* A bit mask of which of the five pipes this instruction
+     is compatible with:
+     X0  0x01
+     X1  0x02
+     Y0  0x04
+     Y1  0x08
+     Y2  0x10 */
+  unsigned char pipes;
+
+  /* How many operands are there? */
+  unsigned char num_operands;
+
+  /* Which register does this write implicitly, or TREG_ZERO if none? */
+  unsigned char implicitly_written_register;
+
+  /* Can this be bundled with other instructions (almost always true). */
+  unsigned char can_bundle;
+
+  /* The description of the operands. Each of these is an
+   * index into the tilegx_operands[] table. */
+  unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS];
+
+#if !defined(__KERNEL__) && !defined(_LIBC)
+  /* A mask of which bits have predefined values for each pipeline.
+   * This is useful for disassembly. */
+  tilegx_bundle_bits fixed_bit_masks[TILEGX_NUM_PIPELINE_ENCODINGS];
+
+  /* For each bit set in fixed_bit_masks, what the value is for this
+   * instruction. */
+  tilegx_bundle_bits fixed_bit_values[TILEGX_NUM_PIPELINE_ENCODINGS];
+#endif
+};
+
+extern const struct tilegx_opcode tilegx_opcodes[];
+
+/* Used for non-textual disassembly into structs. */
+struct tilegx_decoded_instruction
+{
+  const struct tilegx_opcode *opcode;
+  const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS];
+  long long operand_values[TILEGX_MAX_OPERANDS];
+};
+
+
+/* Disassemble a bundle into a struct for machine processing. */
+extern int parse_insn_tilegx(tilegx_bundle_bits bits,
+                             unsigned long long pc,
+                             struct tilegx_decoded_instruction
+                             decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]);
+
+
+#if !defined(__KERNEL__) && !defined(_LIBC)
+/* Canonical names of all the registers. */
+/* ISSUE: This table lives in "tile-dis.c" */
+extern const char * const tilegx_register_names[];
+
+/* Descriptor for a special-purpose register. */
+struct tilegx_spr
+{
+  /* The number */
+  int number;
+
+  /* The name */
+  const char *name;
+};
+
+/* List of all the SPRs; ordered by increasing number. */
+extern const struct tilegx_spr tilegx_sprs[];
+
+/* Number of special-purpose registers. */
+extern const int tilegx_num_sprs;
+
+extern const char *
+get_tilegx_spr_name (int num);
+#endif /* !__KERNEL__ && !_LIBC */
+
+/* Make a few "tile_" variables to simply common code between
+   architectures.  */
+
+typedef tilegx_bundle_bits tile_bundle_bits;
+#define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES
+#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
+#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
+  TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
+
+#endif /* opcode_tilegx_h */
diff --git a/binutils-2.25/include/opcode/tilepro.h b/binutils-2.25/include/opcode/tilepro.h
new file mode 100644
index 00000000..767926bd
--- /dev/null
+++ b/binutils-2.25/include/opcode/tilepro.h
@@ -0,0 +1,1638 @@
+/* TILEPro opcode information.
+ *
+ *    Copyright 2011 Free Software Foundation, Inc.
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 3 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ *    MA 02110-1301, USA.
+ */
+
+#ifndef opcode_tilepro_h
+#define opcode_tilepro_h
+
+typedef unsigned long long tilepro_bundle_bits;
+
+
+enum
+{
+  TILEPRO_MAX_OPERANDS = 5 /* mm */
+};
+
+typedef enum
+{
+  TILEPRO_OPC_BPT,
+  TILEPRO_OPC_INFO,
+  TILEPRO_OPC_INFOL,
+  TILEPRO_OPC_J,
+  TILEPRO_OPC_JAL,
+  TILEPRO_OPC_LW_TLS,
+  TILEPRO_OPC_LW_TLS_SN,
+  TILEPRO_OPC_MOVE,
+  TILEPRO_OPC_MOVE_SN,
+  TILEPRO_OPC_MOVEI,
+  TILEPRO_OPC_MOVEI_SN,
+  TILEPRO_OPC_MOVELI,
+  TILEPRO_OPC_MOVELI_SN,
+  TILEPRO_OPC_MOVELIS,
+  TILEPRO_OPC_PREFETCH,
+  TILEPRO_OPC_RAISE,
+  TILEPRO_OPC_ADD,
+  TILEPRO_OPC_ADD_SN,
+  TILEPRO_OPC_ADDB,
+  TILEPRO_OPC_ADDB_SN,
+  TILEPRO_OPC_ADDBS_U,
+  TILEPRO_OPC_ADDBS_U_SN,
+  TILEPRO_OPC_ADDH,
+  TILEPRO_OPC_ADDH_SN,
+  TILEPRO_OPC_ADDHS,
+  TILEPRO_OPC_ADDHS_SN,
+  TILEPRO_OPC_ADDI,
+  TILEPRO_OPC_ADDI_SN,
+  TILEPRO_OPC_ADDIB,
+  TILEPRO_OPC_ADDIB_SN,
+  TILEPRO_OPC_ADDIH,
+  TILEPRO_OPC_ADDIH_SN,
+  TILEPRO_OPC_ADDLI,
+  TILEPRO_OPC_ADDLI_SN,
+  TILEPRO_OPC_ADDLIS,
+  TILEPRO_OPC_ADDS,
+  TILEPRO_OPC_ADDS_SN,
+  TILEPRO_OPC_ADIFFB_U,
+  TILEPRO_OPC_ADIFFB_U_SN,
+  TILEPRO_OPC_ADIFFH,
+  TILEPRO_OPC_ADIFFH_SN,
+  TILEPRO_OPC_AND,
+  TILEPRO_OPC_AND_SN,
+  TILEPRO_OPC_ANDI,
+  TILEPRO_OPC_ANDI_SN,
+  TILEPRO_OPC_AULI,
+  TILEPRO_OPC_AVGB_U,
+  TILEPRO_OPC_AVGB_U_SN,
+  TILEPRO_OPC_AVGH,
+  TILEPRO_OPC_AVGH_SN,
+  TILEPRO_OPC_BBNS,
+  TILEPRO_OPC_BBNS_SN,
+  TILEPRO_OPC_BBNST,
+  TILEPRO_OPC_BBNST_SN,
+  TILEPRO_OPC_BBS,
+  TILEPRO_OPC_BBS_SN,
+  TILEPRO_OPC_BBST,
+  TILEPRO_OPC_BBST_SN,
+  TILEPRO_OPC_BGEZ,
+  TILEPRO_OPC_BGEZ_SN,
+  TILEPRO_OPC_BGEZT,
+  TILEPRO_OPC_BGEZT_SN,
+  TILEPRO_OPC_BGZ,
+  TILEPRO_OPC_BGZ_SN,
+  TILEPRO_OPC_BGZT,
+  TILEPRO_OPC_BGZT_SN,
+  TILEPRO_OPC_BITX,
+  TILEPRO_OPC_BITX_SN,
+  TILEPRO_OPC_BLEZ,
+  TILEPRO_OPC_BLEZ_SN,
+  TILEPRO_OPC_BLEZT,
+  TILEPRO_OPC_BLEZT_SN,
+  TILEPRO_OPC_BLZ,
+  TILEPRO_OPC_BLZ_SN,
+  TILEPRO_OPC_BLZT,
+  TILEPRO_OPC_BLZT_SN,
+  TILEPRO_OPC_BNZ,
+  TILEPRO_OPC_BNZ_SN,
+  TILEPRO_OPC_BNZT,
+  TILEPRO_OPC_BNZT_SN,
+  TILEPRO_OPC_BYTEX,
+  TILEPRO_OPC_BYTEX_SN,
+  TILEPRO_OPC_BZ,
+  TILEPRO_OPC_BZ_SN,
+  TILEPRO_OPC_BZT,
+  TILEPRO_OPC_BZT_SN,
+  TILEPRO_OPC_CLZ,
+  TILEPRO_OPC_CLZ_SN,
+  TILEPRO_OPC_CRC32_32,
+  TILEPRO_OPC_CRC32_32_SN,
+  TILEPRO_OPC_CRC32_8,
+  TILEPRO_OPC_CRC32_8_SN,
+  TILEPRO_OPC_CTZ,
+  TILEPRO_OPC_CTZ_SN,
+  TILEPRO_OPC_DRAIN,
+  TILEPRO_OPC_DTLBPR,
+  TILEPRO_OPC_DWORD_ALIGN,
+  TILEPRO_OPC_DWORD_ALIGN_SN,
+  TILEPRO_OPC_FINV,
+  TILEPRO_OPC_FLUSH,
+  TILEPRO_OPC_FNOP,
+  TILEPRO_OPC_ICOH,
+  TILEPRO_OPC_ILL,
+  TILEPRO_OPC_INTHB,
+  TILEPRO_OPC_INTHB_SN,
+  TILEPRO_OPC_INTHH,
+  TILEPRO_OPC_INTHH_SN,
+  TILEPRO_OPC_INTLB,
+  TILEPRO_OPC_INTLB_SN,
+  TILEPRO_OPC_INTLH,
+  TILEPRO_OPC_INTLH_SN,
+  TILEPRO_OPC_INV,
+  TILEPRO_OPC_IRET,
+  TILEPRO_OPC_JALB,
+  TILEPRO_OPC_JALF,
+  TILEPRO_OPC_JALR,
+  TILEPRO_OPC_JALRP,
+  TILEPRO_OPC_JB,
+  TILEPRO_OPC_JF,
+  TILEPRO_OPC_JR,
+  TILEPRO_OPC_JRP,
+  TILEPRO_OPC_LB,
+  TILEPRO_OPC_LB_SN,
+  TILEPRO_OPC_LB_U,
+  TILEPRO_OPC_LB_U_SN,
+  TILEPRO_OPC_LBADD,
+  TILEPRO_OPC_LBADD_SN,
+  TILEPRO_OPC_LBADD_U,
+  TILEPRO_OPC_LBADD_U_SN,
+  TILEPRO_OPC_LH,
+  TILEPRO_OPC_LH_SN,
+  TILEPRO_OPC_LH_U,
+  TILEPRO_OPC_LH_U_SN,
+  TILEPRO_OPC_LHADD,
+  TILEPRO_OPC_LHADD_SN,
+  TILEPRO_OPC_LHADD_U,
+  TILEPRO_OPC_LHADD_U_SN,
+  TILEPRO_OPC_LNK,
+  TILEPRO_OPC_LNK_SN,
+  TILEPRO_OPC_LW,
+  TILEPRO_OPC_LW_SN,
+  TILEPRO_OPC_LW_NA,
+  TILEPRO_OPC_LW_NA_SN,
+  TILEPRO_OPC_LWADD,
+  TILEPRO_OPC_LWADD_SN,
+  TILEPRO_OPC_LWADD_NA,
+  TILEPRO_OPC_LWADD_NA_SN,
+  TILEPRO_OPC_MAXB_U,
+  TILEPRO_OPC_MAXB_U_SN,
+  TILEPRO_OPC_MAXH,
+  TILEPRO_OPC_MAXH_SN,
+  TILEPRO_OPC_MAXIB_U,
+  TILEPRO_OPC_MAXIB_U_SN,
+  TILEPRO_OPC_MAXIH,
+  TILEPRO_OPC_MAXIH_SN,
+  TILEPRO_OPC_MF,
+  TILEPRO_OPC_MFSPR,
+  TILEPRO_OPC_MINB_U,
+  TILEPRO_OPC_MINB_U_SN,
+  TILEPRO_OPC_MINH,
+  TILEPRO_OPC_MINH_SN,
+  TILEPRO_OPC_MINIB_U,
+  TILEPRO_OPC_MINIB_U_SN,
+  TILEPRO_OPC_MINIH,
+  TILEPRO_OPC_MINIH_SN,
+  TILEPRO_OPC_MM,
+  TILEPRO_OPC_MNZ,
+  TILEPRO_OPC_MNZ_SN,
+  TILEPRO_OPC_MNZB,
+  TILEPRO_OPC_MNZB_SN,
+  TILEPRO_OPC_MNZH,
+  TILEPRO_OPC_MNZH_SN,
+  TILEPRO_OPC_MTSPR,
+  TILEPRO_OPC_MULHH_SS,
+  TILEPRO_OPC_MULHH_SS_SN,
+  TILEPRO_OPC_MULHH_SU,
+  TILEPRO_OPC_MULHH_SU_SN,
+  TILEPRO_OPC_MULHH_UU,
+  TILEPRO_OPC_MULHH_UU_SN,
+  TILEPRO_OPC_MULHHA_SS,
+  TILEPRO_OPC_MULHHA_SS_SN,
+  TILEPRO_OPC_MULHHA_SU,
+  TILEPRO_OPC_MULHHA_SU_SN,
+  TILEPRO_OPC_MULHHA_UU,
+  TILEPRO_OPC_MULHHA_UU_SN,
+  TILEPRO_OPC_MULHHSA_UU,
+  TILEPRO_OPC_MULHHSA_UU_SN,
+  TILEPRO_OPC_MULHL_SS,
+  TILEPRO_OPC_MULHL_SS_SN,
+  TILEPRO_OPC_MULHL_SU,
+  TILEPRO_OPC_MULHL_SU_SN,
+  TILEPRO_OPC_MULHL_US,
+  TILEPRO_OPC_MULHL_US_SN,
+  TILEPRO_OPC_MULHL_UU,
+  TILEPRO_OPC_MULHL_UU_SN,
+  TILEPRO_OPC_MULHLA_SS,
+  TILEPRO_OPC_MULHLA_SS_SN,
+  TILEPRO_OPC_MULHLA_SU,
+  TILEPRO_OPC_MULHLA_SU_SN,
+  TILEPRO_OPC_MULHLA_US,
+  TILEPRO_OPC_MULHLA_US_SN,
+  TILEPRO_OPC_MULHLA_UU,
+  TILEPRO_OPC_MULHLA_UU_SN,
+  TILEPRO_OPC_MULHLSA_UU,
+  TILEPRO_OPC_MULHLSA_UU_SN,
+  TILEPRO_OPC_MULLL_SS,
+  TILEPRO_OPC_MULLL_SS_SN,
+  TILEPRO_OPC_MULLL_SU,
+  TILEPRO_OPC_MULLL_SU_SN,
+  TILEPRO_OPC_MULLL_UU,
+  TILEPRO_OPC_MULLL_UU_SN,
+  TILEPRO_OPC_MULLLA_SS,
+  TILEPRO_OPC_MULLLA_SS_SN,
+  TILEPRO_OPC_MULLLA_SU,
+  TILEPRO_OPC_MULLLA_SU_SN,
+  TILEPRO_OPC_MULLLA_UU,
+  TILEPRO_OPC_MULLLA_UU_SN,
+  TILEPRO_OPC_MULLLSA_UU,
+  TILEPRO_OPC_MULLLSA_UU_SN,
+  TILEPRO_OPC_MVNZ,
+  TILEPRO_OPC_MVNZ_SN,
+  TILEPRO_OPC_MVZ,
+  TILEPRO_OPC_MVZ_SN,
+  TILEPRO_OPC_MZ,
+  TILEPRO_OPC_MZ_SN,
+  TILEPRO_OPC_MZB,
+  TILEPRO_OPC_MZB_SN,
+  TILEPRO_OPC_MZH,
+  TILEPRO_OPC_MZH_SN,
+  TILEPRO_OPC_NAP,
+  TILEPRO_OPC_NOP,
+  TILEPRO_OPC_NOR,
+  TILEPRO_OPC_NOR_SN,
+  TILEPRO_OPC_OR,
+  TILEPRO_OPC_OR_SN,
+  TILEPRO_OPC_ORI,
+  TILEPRO_OPC_ORI_SN,
+  TILEPRO_OPC_PACKBS_U,
+  TILEPRO_OPC_PACKBS_U_SN,
+  TILEPRO_OPC_PACKHB,
+  TILEPRO_OPC_PACKHB_SN,
+  TILEPRO_OPC_PACKHS,
+  TILEPRO_OPC_PACKHS_SN,
+  TILEPRO_OPC_PACKLB,
+  TILEPRO_OPC_PACKLB_SN,
+  TILEPRO_OPC_PCNT,
+  TILEPRO_OPC_PCNT_SN,
+  TILEPRO_OPC_RL,
+  TILEPRO_OPC_RL_SN,
+  TILEPRO_OPC_RLI,
+  TILEPRO_OPC_RLI_SN,
+  TILEPRO_OPC_S1A,
+  TILEPRO_OPC_S1A_SN,
+  TILEPRO_OPC_S2A,
+  TILEPRO_OPC_S2A_SN,
+  TILEPRO_OPC_S3A,
+  TILEPRO_OPC_S3A_SN,
+  TILEPRO_OPC_SADAB_U,
+  TILEPRO_OPC_SADAB_U_SN,
+  TILEPRO_OPC_SADAH,
+  TILEPRO_OPC_SADAH_SN,
+  TILEPRO_OPC_SADAH_U,
+  TILEPRO_OPC_SADAH_U_SN,
+  TILEPRO_OPC_SADB_U,
+  TILEPRO_OPC_SADB_U_SN,
+  TILEPRO_OPC_SADH,
+  TILEPRO_OPC_SADH_SN,
+  TILEPRO_OPC_SADH_U,
+  TILEPRO_OPC_SADH_U_SN,
+  TILEPRO_OPC_SB,
+  TILEPRO_OPC_SBADD,
+  TILEPRO_OPC_SEQ,
+  TILEPRO_OPC_SEQ_SN,
+  TILEPRO_OPC_SEQB,
+  TILEPRO_OPC_SEQB_SN,
+  TILEPRO_OPC_SEQH,
+  TILEPRO_OPC_SEQH_SN,
+  TILEPRO_OPC_SEQI,
+  TILEPRO_OPC_SEQI_SN,
+  TILEPRO_OPC_SEQIB,
+  TILEPRO_OPC_SEQIB_SN,
+  TILEPRO_OPC_SEQIH,
+  TILEPRO_OPC_SEQIH_SN,
+  TILEPRO_OPC_SH,
+  TILEPRO_OPC_SHADD,
+  TILEPRO_OPC_SHL,
+  TILEPRO_OPC_SHL_SN,
+  TILEPRO_OPC_SHLB,
+  TILEPRO_OPC_SHLB_SN,
+  TILEPRO_OPC_SHLH,
+  TILEPRO_OPC_SHLH_SN,
+  TILEPRO_OPC_SHLI,
+  TILEPRO_OPC_SHLI_SN,
+  TILEPRO_OPC_SHLIB,
+  TILEPRO_OPC_SHLIB_SN,
+  TILEPRO_OPC_SHLIH,
+  TILEPRO_OPC_SHLIH_SN,
+  TILEPRO_OPC_SHR,
+  TILEPRO_OPC_SHR_SN,
+  TILEPRO_OPC_SHRB,
+  TILEPRO_OPC_SHRB_SN,
+  TILEPRO_OPC_SHRH,
+  TILEPRO_OPC_SHRH_SN,
+  TILEPRO_OPC_SHRI,
+  TILEPRO_OPC_SHRI_SN,
+  TILEPRO_OPC_SHRIB,
+  TILEPRO_OPC_SHRIB_SN,
+  TILEPRO_OPC_SHRIH,
+  TILEPRO_OPC_SHRIH_SN,
+  TILEPRO_OPC_SLT,
+  TILEPRO_OPC_SLT_SN,
+  TILEPRO_OPC_SLT_U,
+  TILEPRO_OPC_SLT_U_SN,
+  TILEPRO_OPC_SLTB,
+  TILEPRO_OPC_SLTB_SN,
+  TILEPRO_OPC_SLTB_U,
+  TILEPRO_OPC_SLTB_U_SN,
+  TILEPRO_OPC_SLTE,
+  TILEPRO_OPC_SLTE_SN,
+  TILEPRO_OPC_SLTE_U,
+  TILEPRO_OPC_SLTE_U_SN,
+  TILEPRO_OPC_SLTEB,
+  TILEPRO_OPC_SLTEB_SN,
+  TILEPRO_OPC_SLTEB_U,
+  TILEPRO_OPC_SLTEB_U_SN,
+  TILEPRO_OPC_SLTEH,
+  TILEPRO_OPC_SLTEH_SN,
+  TILEPRO_OPC_SLTEH_U,
+  TILEPRO_OPC_SLTEH_U_SN,
+  TILEPRO_OPC_SLTH,
+  TILEPRO_OPC_SLTH_SN,
+  TILEPRO_OPC_SLTH_U,
+  TILEPRO_OPC_SLTH_U_SN,
+  TILEPRO_OPC_SLTI,
+  TILEPRO_OPC_SLTI_SN,
+  TILEPRO_OPC_SLTI_U,
+  TILEPRO_OPC_SLTI_U_SN,
+  TILEPRO_OPC_SLTIB,
+  TILEPRO_OPC_SLTIB_SN,
+  TILEPRO_OPC_SLTIB_U,
+  TILEPRO_OPC_SLTIB_U_SN,
+  TILEPRO_OPC_SLTIH,
+  TILEPRO_OPC_SLTIH_SN,
+  TILEPRO_OPC_SLTIH_U,
+  TILEPRO_OPC_SLTIH_U_SN,
+  TILEPRO_OPC_SNE,
+  TILEPRO_OPC_SNE_SN,
+  TILEPRO_OPC_SNEB,
+  TILEPRO_OPC_SNEB_SN,
+  TILEPRO_OPC_SNEH,
+  TILEPRO_OPC_SNEH_SN,
+  TILEPRO_OPC_SRA,
+  TILEPRO_OPC_SRA_SN,
+  TILEPRO_OPC_SRAB,
+  TILEPRO_OPC_SRAB_SN,
+  TILEPRO_OPC_SRAH,
+  TILEPRO_OPC_SRAH_SN,
+  TILEPRO_OPC_SRAI,
+  TILEPRO_OPC_SRAI_SN,
+  TILEPRO_OPC_SRAIB,
+  TILEPRO_OPC_SRAIB_SN,
+  TILEPRO_OPC_SRAIH,
+  TILEPRO_OPC_SRAIH_SN,
+  TILEPRO_OPC_SUB,
+  TILEPRO_OPC_SUB_SN,
+  TILEPRO_OPC_SUBB,
+  TILEPRO_OPC_SUBB_SN,
+  TILEPRO_OPC_SUBBS_U,
+  TILEPRO_OPC_SUBBS_U_SN,
+  TILEPRO_OPC_SUBH,
+  TILEPRO_OPC_SUBH_SN,
+  TILEPRO_OPC_SUBHS,
+  TILEPRO_OPC_SUBHS_SN,
+  TILEPRO_OPC_SUBS,
+  TILEPRO_OPC_SUBS_SN,
+  TILEPRO_OPC_SW,
+  TILEPRO_OPC_SWADD,
+  TILEPRO_OPC_SWINT0,
+  TILEPRO_OPC_SWINT1,
+  TILEPRO_OPC_SWINT2,
+  TILEPRO_OPC_SWINT3,
+  TILEPRO_OPC_TBLIDXB0,
+  TILEPRO_OPC_TBLIDXB0_SN,
+  TILEPRO_OPC_TBLIDXB1,
+  TILEPRO_OPC_TBLIDXB1_SN,
+  TILEPRO_OPC_TBLIDXB2,
+  TILEPRO_OPC_TBLIDXB2_SN,
+  TILEPRO_OPC_TBLIDXB3,
+  TILEPRO_OPC_TBLIDXB3_SN,
+  TILEPRO_OPC_TNS,
+  TILEPRO_OPC_TNS_SN,
+  TILEPRO_OPC_WH64,
+  TILEPRO_OPC_XOR,
+  TILEPRO_OPC_XOR_SN,
+  TILEPRO_OPC_XORI,
+  TILEPRO_OPC_XORI_SN,
+  TILEPRO_OPC_NONE
+} tilepro_mnemonic;
+
+/* 64-bit pattern for a { bpt ; nop } bundle. */
+#define TILEPRO_BPT_BUNDLE 0x400b3cae70166000ULL
+
+#ifndef DISASM_ONLY
+
+enum
+{
+  TILEPRO_SN_MAX_OPERANDS = 6 /* route */
+};
+
+typedef enum
+{
+  TILEPRO_SN_OPC_BZ,
+  TILEPRO_SN_OPC_BNZ,
+  TILEPRO_SN_OPC_JRR,
+  TILEPRO_SN_OPC_FNOP,
+  TILEPRO_SN_OPC_BLZ,
+  TILEPRO_SN_OPC_NOP,
+  TILEPRO_SN_OPC_MOVEI,
+  TILEPRO_SN_OPC_MOVE,
+  TILEPRO_SN_OPC_BGEZ,
+  TILEPRO_SN_OPC_JR,
+  TILEPRO_SN_OPC_BLEZ,
+  TILEPRO_SN_OPC_BBNS,
+  TILEPRO_SN_OPC_JALRR,
+  TILEPRO_SN_OPC_BPT,
+  TILEPRO_SN_OPC_JALR,
+  TILEPRO_SN_OPC_SHR1,
+  TILEPRO_SN_OPC_BGZ,
+  TILEPRO_SN_OPC_BBS,
+  TILEPRO_SN_OPC_SHL8II,
+  TILEPRO_SN_OPC_ADDI,
+  TILEPRO_SN_OPC_HALT,
+  TILEPRO_SN_OPC_ROUTE,
+  TILEPRO_SN_OPC_NONE
+} tilepro_sn_mnemonic;
+
+extern const unsigned char tilepro_sn_route_encode[6 * 6 * 6];
+extern const signed char tilepro_sn_route_decode[256][3];
+extern const char tilepro_sn_direction_names[6][5];
+extern const signed char tilepro_sn_dest_map[6][6];
+#endif /* DISASM_ONLY */
+
+
+static __inline unsigned int
+get_BrOff_SN(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 0)) & 0x3ff);
+}
+
+static __inline unsigned int
+get_BrOff_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0x00007fff) |
+         (((unsigned int)(n >> 20)) & 0x00018000);
+}
+
+static __inline unsigned int
+get_BrType_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 31)) & 0xf);
+}
+
+static __inline unsigned int
+get_Dest_Imm8_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 31)) & 0x0000003f) |
+         (((unsigned int)(n >> 43)) & 0x000000c0);
+}
+
+static __inline unsigned int
+get_Dest_SN(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 2)) & 0x3);
+}
+
+static __inline unsigned int
+get_Dest_X0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 0)) & 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 31)) & 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_Y0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 0)) & 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_Y1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 31)) & 0x3f);
+}
+
+static __inline unsigned int
+get_Imm16_X0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0xffff);
+}
+
+static __inline unsigned int
+get_Imm16_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0xffff);
+}
+
+static __inline unsigned int
+get_Imm8_SN(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 0)) & 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_X0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_Y0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_Y1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0xff);
+}
+
+static __inline unsigned int
+get_ImmOpcodeExtension_X0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 20)) & 0x7f);
+}
+
+static __inline unsigned int
+get_ImmOpcodeExtension_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 51)) & 0x7f);
+}
+
+static __inline unsigned int
+get_ImmRROpcodeExtension_SN(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 8)) & 0x3);
+}
+
+static __inline unsigned int
+get_JOffLong_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0x00007fff) |
+         (((unsigned int)(n >> 20)) & 0x00018000) |
+         (((unsigned int)(n >> 14)) & 0x001e0000) |
+         (((unsigned int)(n >> 16)) & 0x07e00000) |
+         (((unsigned int)(n >> 31)) & 0x18000000);
+}
+
+static __inline unsigned int
+get_JOff_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0x00007fff) |
+         (((unsigned int)(n >> 20)) & 0x00018000) |
+         (((unsigned int)(n >> 14)) & 0x001e0000) |
+         (((unsigned int)(n >> 16)) & 0x07e00000) |
+         (((unsigned int)(n >> 31)) & 0x08000000);
+}
+
+static __inline unsigned int
+get_MF_Imm15_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 37)) & 0x00003fff) |
+         (((unsigned int)(n >> 44)) & 0x00004000);
+}
+
+static __inline unsigned int
+get_MMEnd_X0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 18)) & 0x1f);
+}
+
+static __inline unsigned int
+get_MMEnd_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 49)) & 0x1f);
+}
+
+static __inline unsigned int
+get_MMStart_X0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 23)) & 0x1f);
+}
+
+static __inline unsigned int
+get_MMStart_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 54)) & 0x1f);
+}
+
+static __inline unsigned int
+get_MT_Imm15_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 31)) & 0x0000003f) |
+         (((unsigned int)(n >> 37)) & 0x00003fc0) |
+         (((unsigned int)(n >> 44)) & 0x00004000);
+}
+
+static __inline unsigned int
+get_Mode(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 63)) & 0x1);
+}
+
+static __inline unsigned int
+get_NoRegOpcodeExtension_SN(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 0)) & 0xf);
+}
+
+static __inline unsigned int
+get_Opcode_SN(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 10)) & 0x3f);
+}
+
+static __inline unsigned int
+get_Opcode_X0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 28)) & 0x7);
+}
+
+static __inline unsigned int
+get_Opcode_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 59)) & 0xf);
+}
+
+static __inline unsigned int
+get_Opcode_Y0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 27)) & 0xf);
+}
+
+static __inline unsigned int
+get_Opcode_Y1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 59)) & 0xf);
+}
+
+static __inline unsigned int
+get_Opcode_Y2(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 56)) & 0x7);
+}
+
+static __inline unsigned int
+get_RROpcodeExtension_SN(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 4)) & 0xf);
+}
+
+static __inline unsigned int
+get_RRROpcodeExtension_X0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 18)) & 0x1ff);
+}
+
+static __inline unsigned int
+get_RRROpcodeExtension_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 49)) & 0x1ff);
+}
+
+static __inline unsigned int
+get_RRROpcodeExtension_Y0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 18)) & 0x3);
+}
+
+static __inline unsigned int
+get_RRROpcodeExtension_Y1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 49)) & 0x3);
+}
+
+static __inline unsigned int
+get_RouteOpcodeExtension_SN(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 0)) & 0x3ff);
+}
+
+static __inline unsigned int
+get_S_X0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 27)) & 0x1);
+}
+
+static __inline unsigned int
+get_S_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 58)) & 0x1);
+}
+
+static __inline unsigned int
+get_ShAmt_X0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0x1f);
+}
+
+static __inline unsigned int
+get_ShAmt_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0x1f);
+}
+
+static __inline unsigned int
+get_ShAmt_Y0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0x1f);
+}
+
+static __inline unsigned int
+get_ShAmt_Y1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0x1f);
+}
+
+static __inline unsigned int
+get_SrcA_X0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 6)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcA_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 37)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcA_Y0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 6)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcA_Y1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 37)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcA_Y2(tilepro_bundle_bits n)
+{
+  return (((n >> 26)) & 0x00000001) |
+         (((unsigned int)(n >> 50)) & 0x0000003e);
+}
+
+static __inline unsigned int
+get_SrcBDest_Y2(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 20)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcB_X0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcB_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcB_Y0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcB_Y1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+static __inline unsigned int
+get_Src_SN(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 0)) & 0x3);
+}
+
+static __inline unsigned int
+get_UnOpcodeExtension_X0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0x1f);
+}
+
+static __inline unsigned int
+get_UnOpcodeExtension_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0x1f);
+}
+
+static __inline unsigned int
+get_UnOpcodeExtension_Y0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 12)) & 0x1f);
+}
+
+static __inline unsigned int
+get_UnOpcodeExtension_Y1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 43)) & 0x1f);
+}
+
+static __inline unsigned int
+get_UnShOpcodeExtension_X0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 17)) & 0x3ff);
+}
+
+static __inline unsigned int
+get_UnShOpcodeExtension_X1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 48)) & 0x3ff);
+}
+
+static __inline unsigned int
+get_UnShOpcodeExtension_Y0(tilepro_bundle_bits num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 17)) & 0x7);
+}
+
+static __inline unsigned int
+get_UnShOpcodeExtension_Y1(tilepro_bundle_bits n)
+{
+  return (((unsigned int)(n >> 48)) & 0x7);
+}
+
+
+static __inline int
+sign_extend(int n, int num_bits)
+{
+  int shift = (int)(sizeof(int) * 8 - num_bits);
+  return (n << shift) >> shift;
+}
+
+
+
+static __inline tilepro_bundle_bits
+create_BrOff_SN(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3ff) << 0);
+}
+
+static __inline tilepro_bundle_bits
+create_BrOff_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) |
+         (((tilepro_bundle_bits)(n & 0x00018000)) << 20);
+}
+
+static __inline tilepro_bundle_bits
+create_BrType_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0xf)) << 31);
+}
+
+static __inline tilepro_bundle_bits
+create_Dest_Imm8_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x0000003f)) << 31) |
+         (((tilepro_bundle_bits)(n & 0x000000c0)) << 43);
+}
+
+static __inline tilepro_bundle_bits
+create_Dest_SN(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3) << 2);
+}
+
+static __inline tilepro_bundle_bits
+create_Dest_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 0);
+}
+
+static __inline tilepro_bundle_bits
+create_Dest_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x3f)) << 31);
+}
+
+static __inline tilepro_bundle_bits
+create_Dest_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 0);
+}
+
+static __inline tilepro_bundle_bits
+create_Dest_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x3f)) << 31);
+}
+
+static __inline tilepro_bundle_bits
+create_Imm16_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0xffff) << 12);
+}
+
+static __inline tilepro_bundle_bits
+create_Imm16_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0xffff)) << 43);
+}
+
+static __inline tilepro_bundle_bits
+create_Imm8_SN(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0xff) << 0);
+}
+
+static __inline tilepro_bundle_bits
+create_Imm8_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0xff) << 12);
+}
+
+static __inline tilepro_bundle_bits
+create_Imm8_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0xff)) << 43);
+}
+
+static __inline tilepro_bundle_bits
+create_Imm8_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0xff) << 12);
+}
+
+static __inline tilepro_bundle_bits
+create_Imm8_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0xff)) << 43);
+}
+
+static __inline tilepro_bundle_bits
+create_ImmOpcodeExtension_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x7f) << 20);
+}
+
+static __inline tilepro_bundle_bits
+create_ImmOpcodeExtension_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x7f)) << 51);
+}
+
+static __inline tilepro_bundle_bits
+create_ImmRROpcodeExtension_SN(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3) << 8);
+}
+
+static __inline tilepro_bundle_bits
+create_JOffLong_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) |
+         (((tilepro_bundle_bits)(n & 0x00018000)) << 20) |
+         (((tilepro_bundle_bits)(n & 0x001e0000)) << 14) |
+         (((tilepro_bundle_bits)(n & 0x07e00000)) << 16) |
+         (((tilepro_bundle_bits)(n & 0x18000000)) << 31);
+}
+
+static __inline tilepro_bundle_bits
+create_JOff_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) |
+         (((tilepro_bundle_bits)(n & 0x00018000)) << 20) |
+         (((tilepro_bundle_bits)(n & 0x001e0000)) << 14) |
+         (((tilepro_bundle_bits)(n & 0x07e00000)) << 16) |
+         (((tilepro_bundle_bits)(n & 0x08000000)) << 31);
+}
+
+static __inline tilepro_bundle_bits
+create_MF_Imm15_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x00003fff)) << 37) |
+         (((tilepro_bundle_bits)(n & 0x00004000)) << 44);
+}
+
+static __inline tilepro_bundle_bits
+create_MMEnd_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x1f) << 18);
+}
+
+static __inline tilepro_bundle_bits
+create_MMEnd_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x1f)) << 49);
+}
+
+static __inline tilepro_bundle_bits
+create_MMStart_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x1f) << 23);
+}
+
+static __inline tilepro_bundle_bits
+create_MMStart_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x1f)) << 54);
+}
+
+static __inline tilepro_bundle_bits
+create_MT_Imm15_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x0000003f)) << 31) |
+         (((tilepro_bundle_bits)(n & 0x00003fc0)) << 37) |
+         (((tilepro_bundle_bits)(n & 0x00004000)) << 44);
+}
+
+static __inline tilepro_bundle_bits
+create_Mode(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x1)) << 63);
+}
+
+static __inline tilepro_bundle_bits
+create_NoRegOpcodeExtension_SN(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0xf) << 0);
+}
+
+static __inline tilepro_bundle_bits
+create_Opcode_SN(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 10);
+}
+
+static __inline tilepro_bundle_bits
+create_Opcode_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x7) << 28);
+}
+
+static __inline tilepro_bundle_bits
+create_Opcode_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0xf)) << 59);
+}
+
+static __inline tilepro_bundle_bits
+create_Opcode_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0xf) << 27);
+}
+
+static __inline tilepro_bundle_bits
+create_Opcode_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0xf)) << 59);
+}
+
+static __inline tilepro_bundle_bits
+create_Opcode_Y2(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x7)) << 56);
+}
+
+static __inline tilepro_bundle_bits
+create_RROpcodeExtension_SN(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0xf) << 4);
+}
+
+static __inline tilepro_bundle_bits
+create_RRROpcodeExtension_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x1ff) << 18);
+}
+
+static __inline tilepro_bundle_bits
+create_RRROpcodeExtension_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x1ff)) << 49);
+}
+
+static __inline tilepro_bundle_bits
+create_RRROpcodeExtension_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3) << 18);
+}
+
+static __inline tilepro_bundle_bits
+create_RRROpcodeExtension_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x3)) << 49);
+}
+
+static __inline tilepro_bundle_bits
+create_RouteOpcodeExtension_SN(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3ff) << 0);
+}
+
+static __inline tilepro_bundle_bits
+create_S_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x1) << 27);
+}
+
+static __inline tilepro_bundle_bits
+create_S_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x1)) << 58);
+}
+
+static __inline tilepro_bundle_bits
+create_ShAmt_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x1f) << 12);
+}
+
+static __inline tilepro_bundle_bits
+create_ShAmt_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x1f)) << 43);
+}
+
+static __inline tilepro_bundle_bits
+create_ShAmt_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x1f) << 12);
+}
+
+static __inline tilepro_bundle_bits
+create_ShAmt_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x1f)) << 43);
+}
+
+static __inline tilepro_bundle_bits
+create_SrcA_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 6);
+}
+
+static __inline tilepro_bundle_bits
+create_SrcA_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x3f)) << 37);
+}
+
+static __inline tilepro_bundle_bits
+create_SrcA_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 6);
+}
+
+static __inline tilepro_bundle_bits
+create_SrcA_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x3f)) << 37);
+}
+
+static __inline tilepro_bundle_bits
+create_SrcA_Y2(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x00000001) << 26) |
+         (((tilepro_bundle_bits)(n & 0x0000003e)) << 50);
+}
+
+static __inline tilepro_bundle_bits
+create_SrcBDest_Y2(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 20);
+}
+
+static __inline tilepro_bundle_bits
+create_SrcB_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 12);
+}
+
+static __inline tilepro_bundle_bits
+create_SrcB_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x3f)) << 43);
+}
+
+static __inline tilepro_bundle_bits
+create_SrcB_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3f) << 12);
+}
+
+static __inline tilepro_bundle_bits
+create_SrcB_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x3f)) << 43);
+}
+
+static __inline tilepro_bundle_bits
+create_Src_SN(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3) << 0);
+}
+
+static __inline tilepro_bundle_bits
+create_UnOpcodeExtension_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x1f) << 12);
+}
+
+static __inline tilepro_bundle_bits
+create_UnOpcodeExtension_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x1f)) << 43);
+}
+
+static __inline tilepro_bundle_bits
+create_UnOpcodeExtension_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x1f) << 12);
+}
+
+static __inline tilepro_bundle_bits
+create_UnOpcodeExtension_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x1f)) << 43);
+}
+
+static __inline tilepro_bundle_bits
+create_UnShOpcodeExtension_X0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x3ff) << 17);
+}
+
+static __inline tilepro_bundle_bits
+create_UnShOpcodeExtension_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x3ff)) << 48);
+}
+
+static __inline tilepro_bundle_bits
+create_UnShOpcodeExtension_Y0(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return ((n & 0x7) << 17);
+}
+
+static __inline tilepro_bundle_bits
+create_UnShOpcodeExtension_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilepro_bundle_bits)(n & 0x7)) << 48);
+}
+
+
+
+typedef enum
+{
+  TILEPRO_PIPELINE_X0,
+  TILEPRO_PIPELINE_X1,
+  TILEPRO_PIPELINE_Y0,
+  TILEPRO_PIPELINE_Y1,
+  TILEPRO_PIPELINE_Y2,
+} tilepro_pipeline;
+
+#define tilepro_is_x_pipeline(p) ((int)(p) <= (int)TILEPRO_PIPELINE_X1)
+
+typedef enum
+{
+  TILEPRO_OP_TYPE_REGISTER,
+  TILEPRO_OP_TYPE_IMMEDIATE,
+  TILEPRO_OP_TYPE_ADDRESS,
+  TILEPRO_OP_TYPE_SPR
+} tilepro_operand_type;
+
+/* This is the bit that determines if a bundle is in the Y encoding. */
+#define TILEPRO_BUNDLE_Y_ENCODING_MASK ((tilepro_bundle_bits)1 << 63)
+
+enum
+{
+  /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
+  TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
+
+  /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
+  TILEPRO_NUM_PIPELINE_ENCODINGS = 5,
+
+  /* Log base 2 of TILEPRO_BUNDLE_SIZE_IN_BYTES. */
+  TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
+
+  /* Instructions take this many bytes. */
+  TILEPRO_BUNDLE_SIZE_IN_BYTES = 1 << TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES,
+
+  /* Log base 2 of TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES. */
+  TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
+
+  /* Bundles should be aligned modulo this number of bytes. */
+  TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES =
+    (1 << TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
+
+  /* Log base 2 of TILEPRO_SN_INSTRUCTION_SIZE_IN_BYTES. */
+  TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1,
+
+  /* Static network instructions take this many bytes. */
+  TILEPRO_SN_INSTRUCTION_SIZE_IN_BYTES =
+    (1 << TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES),
+
+  /* Number of registers (some are magic, such as network I/O). */
+  TILEPRO_NUM_REGISTERS = 64,
+
+  /* Number of static network registers. */
+  TILEPRO_NUM_SN_REGISTERS = 4
+};
+
+
+struct tilepro_operand
+{
+  /* Is this operand a register, immediate or address? */
+  tilepro_operand_type type;
+
+  /* The default relocation type for this operand.  */
+  signed int default_reloc : 16;
+
+  /* How many bits is this value? (used for range checking) */
+  unsigned int num_bits : 5;
+
+  /* Is the value signed? (used for range checking) */
+  unsigned int is_signed : 1;
+
+  /* Is this operand a source register? */
+  unsigned int is_src_reg : 1;
+
+  /* Is this operand written? (i.e. is it a destination register) */
+  unsigned int is_dest_reg : 1;
+
+  /* Is this operand PC-relative? */
+  unsigned int is_pc_relative : 1;
+
+  /* By how many bits do we right shift the value before inserting? */
+  unsigned int rightshift : 2;
+
+  /* Return the bits for this operand to be ORed into an existing bundle. */
+  tilepro_bundle_bits (*insert) (int op);
+
+  /* Extract this operand and return it. */
+  unsigned int (*extract) (tilepro_bundle_bits bundle);
+};
+
+
+extern const struct tilepro_operand tilepro_operands[];
+
+/* One finite-state machine per pipe for rapid instruction decoding. */
+extern const unsigned short * const
+tilepro_bundle_decoder_fsms[TILEPRO_NUM_PIPELINE_ENCODINGS];
+
+
+struct tilepro_opcode
+{
+  /* The opcode mnemonic, e.g. "add" */
+  const char *name;
+
+  /* The enum value for this mnemonic. */
+  tilepro_mnemonic mnemonic;
+
+  /* A bit mask of which of the five pipes this instruction
+     is compatible with:
+     X0  0x01
+     X1  0x02
+     Y0  0x04
+     Y1  0x08
+     Y2  0x10 */
+  unsigned char pipes;
+
+  /* How many operands are there? */
+  unsigned char num_operands;
+
+  /* Which register does this write implicitly, or TREG_ZERO if none? */
+  unsigned char implicitly_written_register;
+
+  /* Can this be bundled with other instructions (almost always true). */
+  unsigned char can_bundle;
+
+  /* The description of the operands. Each of these is an
+   * index into the tilepro_operands[] table. */
+  unsigned char operands[TILEPRO_NUM_PIPELINE_ENCODINGS][TILEPRO_MAX_OPERANDS];
+
+#if !defined(__KERNEL__) && !defined(_LIBC)
+  /* A mask of which bits have predefined values for each pipeline.
+   * This is useful for disassembly. */
+  tilepro_bundle_bits fixed_bit_masks[TILEPRO_NUM_PIPELINE_ENCODINGS];
+
+  /* For each bit set in fixed_bit_masks, what the value is for this
+   * instruction. */
+  tilepro_bundle_bits fixed_bit_values[TILEPRO_NUM_PIPELINE_ENCODINGS];
+#endif
+};
+
+extern const struct tilepro_opcode tilepro_opcodes[];
+
+#if !defined(__KERNEL__) && !defined(_LIBC)
+
+typedef unsigned short tilepro_sn_instruction_bits;
+
+struct tilepro_sn_opcode
+{
+  /* The opcode mnemonic, e.g. "add" */
+  const char *name;
+
+  /* The enum value for this mnemonic. */
+  tilepro_sn_mnemonic mnemonic;
+
+  /* How many operands are there? */
+  unsigned char num_operands;
+
+  /* The description of the operands. Each of these is an
+   * index into the tilepro_operands[] table. */
+  unsigned char operands[TILEPRO_SN_MAX_OPERANDS];
+
+  /* A mask of which bits have predefined values.
+   * This is useful for disassembly. */
+  tilepro_sn_instruction_bits fixed_bit_mask;
+
+  /* For each bit set in fixed_bit_masks, what its value is. */
+  tilepro_sn_instruction_bits fixed_bit_values;
+};
+
+extern const struct tilepro_sn_opcode tilepro_sn_opcodes[];
+
+#endif /* !__KERNEL__ && !_LIBC */
+
+/* Used for non-textual disassembly into structs. */
+struct tilepro_decoded_instruction
+{
+  const struct tilepro_opcode *opcode;
+  const struct tilepro_operand *operands[TILEPRO_MAX_OPERANDS];
+  int operand_values[TILEPRO_MAX_OPERANDS];
+};
+
+
+/* Disassemble a bundle into a struct for machine processing. */
+extern int parse_insn_tilepro(tilepro_bundle_bits bits,
+                              unsigned int pc,
+                              struct tilepro_decoded_instruction
+                              decoded[TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE]);
+
+
+/* Given a set of bundle bits and a specific pipe, returns which
+ * instruction the bundle contains in that pipe.
+ */
+extern const struct tilepro_opcode *
+find_opcode(tilepro_bundle_bits bits, tilepro_pipeline pipe);
+
+
+#if !defined(__KERNEL__) && !defined(_LIBC)
+/* Canonical names of all the registers. */
+/* ISSUE: This table lives in "tilepro-dis.c" */
+extern const char * const tilepro_register_names[];
+
+/* Descriptor for a special-purpose register. */
+struct tilepro_spr
+{
+  /* The number */
+  int number;
+
+  /* The name */
+  const char *name;
+};
+
+/* List of all the SPRs; ordered by increasing number. */
+extern const struct tilepro_spr tilepro_sprs[];
+
+/* Number of special-purpose registers. */
+extern const int tilepro_num_sprs;
+
+extern const char *
+get_tilepro_spr_name (int num);
+#endif /* !__KERNEL__ && !_LIBC */
+
+/* Make a few "tile_" variables to simply common code between
+   architectures.  */
+
+typedef tilepro_bundle_bits tile_bundle_bits;
+#define TILE_BUNDLE_SIZE_IN_BYTES TILEPRO_BUNDLE_SIZE_IN_BYTES
+#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES
+#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
+  TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
+
+#endif /* opcode_tilepro_h */
diff --git a/binutils-2.25/include/opcode/v850.h b/binutils-2.25/include/opcode/v850.h
new file mode 100644
index 00000000..02ef3d4c
--- /dev/null
+++ b/binutils-2.25/include/opcode/v850.h
@@ -0,0 +1,240 @@
+/* v850.h -- Header file for NEC V850 opcode table
+   Copyright 1996-2013 Free Software Foundation, Inc.
+   Written by J.T. Conklin, Cygnus Support
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version 3,
+   or (at your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef V850_H
+#define V850_H
+
+/* The opcode table is an array of struct v850_opcode.  */
+
+struct v850_opcode
+{
+  /* The opcode name.  */
+  const char *name;
+
+  /* The opcode itself.  Those bits which will be filled in with
+     operands are zeroes.  */
+  unsigned long opcode;
+
+  /* The opcode mask.  This is used by the disassembler.  This is a
+     mask containing ones indicating those bits which must match the
+     opcode field, and zeroes indicating those bits which need not
+     match (and are presumably filled in by operands).  */
+  unsigned long mask;
+
+  /* An array of operand codes.  Each code is an index into the
+     operand table.  They appear in the order which the operands must
+     appear in assembly code, and are terminated by a zero.  */
+  unsigned char operands[8];
+
+  /* Which (if any) operand is a memory operand.  */
+  unsigned int memop;
+
+  /* Target processor(s).  A bit field of processors which support
+     this instruction.  Note a bit field is used as some instructions
+     are available on multiple, different processor types, whereas
+     other instructions are only available on one specific type.  */
+  unsigned int processors;
+};
+
+/* Values for architecture number.  */
+#define arch_V850      0
+#define arch_V850E     (arch_V850 + 1)
+#define arch_V850E1    (arch_V850E + 1)
+#define arch_V850E2    (arch_V850E1 + 1)
+#define arch_V850E2V3  (arch_V850E2 + 1)
+#define arch_V850E3V5  (arch_V850E2V3 + 1)
+#define arch_separator (arch_V850E3V5 + 1)
+
+#define opt_EXTENSION  (arch_separator)
+#define opt_ALIAS      (opt_EXTENSION + 1)
+
+/* Values for the processors field in the v850_opcode structure.  */
+#define PROCESSOR_V850       (1 << (arch_V850))     /* Just the V850.  */
+#define PROCESSOR_V850E      (1 << (arch_V850E))    /* Just the V850E.  */
+#define PROCESSOR_V850E1     (1 << (arch_V850E1))   /* Just the V850E1.  */
+#define PROCESSOR_V850E2     (1 << (arch_V850E2))   /* Just the V850E2.  */
+#define PROCESSOR_V850E2V3   (1 << (arch_V850E2V3)) /* Just the V850E2V3.  */
+#define PROCESSOR_V850E3V5   (1 << (arch_V850E3V5)) /* Just the V850E3V5.  */
+
+/* UPPERS */
+#define PROCESSOR_V850E3V5_UP (PROCESSOR_V850E3V5)
+#define PROCESSOR_V850E2V3_UP (PROCESSOR_V850E2V3 | PROCESSOR_V850E3V5_UP)
+#define PROCESSOR_V850E2_UP   (PROCESSOR_V850E2   | PROCESSOR_V850E2V3_UP)
+#define PROCESSOR_V850E_UP    (PROCESSOR_V850E    | PROCESSOR_V850E1 | PROCESSOR_V850E2_UP)
+#define PROCESSOR_ALL         (PROCESSOR_V850     | PROCESSOR_V850E_UP)
+
+#define PROCESSOR_MASK        (PROCESSOR_ALL)
+#define PROCESSOR_NOT_V850    (PROCESSOR_ALL & (~ PROCESSOR_V850))         /* Any processor except the V850.  */
+
+#define PROCESSOR_UNKNOWN    ~(PROCESSOR_MASK)
+
+/* OPTIONS */
+#define PROCESSOR_OPTION_EXTENSION (1 << (opt_EXTENSION))                  /* Enable extension opcodes.  */
+#define PROCESSOR_OPTION_ALIAS     (1 << (opt_ALIAS))                      /* Enable alias opcodes.  */
+
+#define SET_PROCESSOR_MASK(mask,set)	((mask) = ((mask) & ~PROCESSOR_MASK) | (set))
+
+/* The table itself is sorted by major opcode number, and is otherwise
+   in the order in which the disassembler should consider
+   instructions.  */
+extern const struct v850_opcode v850_opcodes[];
+extern const int v850_num_opcodes;
+
+
+/* The operands table is an array of struct v850_operand.  */
+
+struct v850_operand
+{
+  /* The number of bits in the operand.  */
+  /* If this value is -1 then the operand's bits are in a discontinous
+     distribution in the instruction. */
+  int bits;
+
+  /* (bits >= 0):  How far the operand is left shifted in the instruction.  */
+  /* (bits == -1): Bit mask of the bits in the operand.  */
+  int shift;
+
+  /* Insertion function.  This is used by the assembler.  To insert an
+     operand value into an instruction, check this field.
+
+     If it is NULL, execute
+         i |= (op & ((1 << o->bits) - 1)) << o->shift;
+     (i is the instruction which we are filling in, o is a pointer to
+     this structure, and op is the opcode value; this assumes twos
+     complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction and the operand value.  It will return the new value
+     of the instruction.  If the ERRMSG argument is not NULL, then if
+     the operand value is illegal, *ERRMSG will be set to a warning
+     string (the operand will be inserted in any case).  If the
+     operand value is legal, *ERRMSG will be unchanged (most operands
+     can accept any value).  */
+  unsigned long (* insert)
+    (unsigned long instruction, long op, const char ** errmsg);
+
+  /* Extraction function.  This is used by the disassembler.  To
+     extract this operand type from an instruction, check this field.
+
+     If it is NULL, compute
+         op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1);
+	 if (o->flags & V850_OPERAND_SIGNED)
+	     op = (op << (32 - o->bits)) >> (32 - o->bits);
+     (i is the instruction, o is a pointer to this structure, and op
+     is the result; this assumes twos complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction value.  It will return the value of the operand.  If
+     the INVALID argument is not NULL, *INVALID will be set to
+     non-zero if this operand type can not actually be extracted from
+     this operand (i.e., the instruction does not match).  If the
+     operand is valid, *INVALID will not be changed.  */
+  unsigned long (* extract) (unsigned long instruction, int * invalid);
+
+  /* One bit syntax flags.  */
+  int flags;
+
+  int default_reloc;
+};
+
+/* Elements in the table are retrieved by indexing with values from
+   the operands field of the v850_opcodes table.  */
+
+extern const struct v850_operand v850_operands[];
+
+/* Values defined for the flags field of a struct v850_operand.  */
+
+/* This operand names a general purpose register.  */
+#define V850_OPERAND_REG	0x01
+
+/* This operand is the ep register.  */
+#define V850_OPERAND_EP		0x02
+
+/* This operand names a system register.  */
+#define V850_OPERAND_SRG	0x04
+
+/* Prologue eilogue type instruction, V850E specific.  */
+#define V850E_OPERAND_REG_LIST	0x08
+
+/* This operand names a condition code used in the setf instruction.  */
+#define V850_OPERAND_CC		0x10
+
+#define V850_OPERAND_FLOAT_CC	0x20
+
+/* This operand names a vector purpose register.  */
+#define V850_OPERAND_VREG	0x40
+
+/* 16 bit immediate follows instruction, V850E specific.  */
+#define V850E_IMMEDIATE16	0x80
+
+/* hi16 bit immediate follows instruction, V850E specific.  */
+#define V850E_IMMEDIATE16HI	0x100
+
+/* 23 bit immediate follows instruction, V850E specific.  */
+#define V850E_IMMEDIATE23	0x200
+
+/* 32 bit immediate follows instruction, V850E specific.  */
+#define V850E_IMMEDIATE32	0x400
+
+/* This is a relaxable operand.   Only used for D9->D22 branch relaxing
+   right now.  We may need others in the future (or maybe handle them like
+   promoted operands on the mn10300?).  */
+#define V850_OPERAND_RELAX	0x800
+
+/* This operand takes signed values.  */
+#define V850_OPERAND_SIGNED	0x1000
+
+/* This operand is a displacement.  */
+#define V850_OPERAND_DISP	0x2000
+
+/* This operand is a PC displacement.  */
+#define V850_PCREL		0x4000
+
+/* The register specified must be even number.  */
+#define V850_REG_EVEN		0x8000
+
+/* The register specified must not be r0.  */
+#define V850_NOT_R0	        0x20000
+
+/* The register specified must not be 0.  */
+#define V850_NOT_IMM0	        0x40000
+
+/* The condition code must not be SA CONDITION.  */
+#define V850_NOT_SA		0x80000
+
+/* The operand has '!' prefix.  */
+#define V850_OPERAND_BANG	0x100000
+
+/* The operand has '%' prefix.  */
+#define V850_OPERAND_PERCENT	0x200000
+
+/* This operand is a cache oparation.  */
+#define V850_OPERAND_CACHEOP	0x400000
+
+/* This operand is a prefetch oparation.  */
+#define V850_OPERAND_PREFOP	0x800000
+
+/* A PC-relative displacement where a positive value indicates a backwards displacement.  */
+#define V850_INVERSE_PCREL	0x1000000
+
+extern int v850_msg_is_out_of_range (const char *);
+
+#endif /* V850_H */
diff --git a/binutils-2.25/include/opcode/vax.h b/binutils-2.25/include/opcode/vax.h
new file mode 100644
index 00000000..f5cdd243
--- /dev/null
+++ b/binutils-2.25/include/opcode/vax.h
@@ -0,0 +1,383 @@
+/* Vax opcde list.
+   Copyright 1989, 1991, 1992, 1995, 2010 Free Software Foundation, Inc.
+
+   This file is part of GDB and GAS.
+
+   GDB and GAS are free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GDB and GAS are distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GDB or GAS; see the file COPYING3.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+#ifndef vax_opcodeT
+#define vax_opcodeT int
+#endif /* no vax_opcodeT */
+
+struct vot_wot			/* vax opcode table: wot to do with this */
+				/* particular opcode */
+{
+  const char       *args;	/* how to compile said opcode */
+  vax_opcodeT       code;	/* op-code (may be > 8 bits!) */
+};
+
+struct vot			/* vax opcode text */
+{
+  const char       *name;	/* opcode name: lowercase string  [key]  */
+  struct vot_wot    detail;	/* rest of opcode table          [datum] */
+};
+
+#define vot_how args
+#define vot_code code
+#define vot_detail detail
+#define vot_name name
+
+static const struct vot
+votstrs[] =
+{
+{    "halt",	{"",			0x00	} },
+{    "nop",	{"",			0x01	} },
+{    "rei",	{"",			0x02	} },
+{    "bpt",	{"",			0x03	} },
+{    "ret",	{"",			0x04	} },
+{    "rsb",	{"",			0x05	} },
+{    "ldpctx",	{"",			0x06	} },
+{    "svpctx",	{"",			0x07	} },
+{    "cvtps",	{"rwabrwab",		0x08	} },
+{    "cvtsp",	{"rwabrwab",		0x09	} },
+{    "index",	{"rlrlrlrlrlwl",	0x0a	} },
+{    "crc",	{"abrlrwab",		0x0b	} },
+{    "prober",	{"rbrwab",		0x0c	} },
+{    "probew",	{"rbrwab",	        0x0d	} },
+{    "insque",	{"abab",		0x0e	} },
+{    "remque",	{"abwl",		0x0f	} },
+{    "bsbb",	{"bb",			0x10	} },
+{    "brb",	{"bb",			0x11	} },
+{    "bneq",	{"bb",			0x12	} },
+{    "bnequ",	{"bb",			0x12	} },
+{    "beql",	{"bb",			0x13	} },
+{    "beqlu",	{"bb",			0x13	} },
+{    "bgtr",	{"bb",			0x14	} },
+{    "bleq",	{"bb",			0x15	} },
+{    "jsb",	{"ab",			0x16	} },
+{    "jmp",	{"ab",			0x17	} },
+{    "bgeq",	{"bb",			0x18	} },
+{    "blss",	{"bb",			0x19	} },
+{    "bgtru",	{"bb",			0x1a	} },
+{    "blequ",	{"bb",			0x1b	} },
+{    "bvc",	{"bb",			0x1c	} },
+{    "bvs",	{"bb",			0x1d	} },
+{    "bcc",	{"bb",			0x1e	} },
+{    "bgequ",	{"bb",			0x1e	} },
+{    "blssu",	{"bb",			0x1f	} },
+{    "bcs",	{"bb",			0x1f	} },
+{    "addp4",	{"rwabrwab",		0x20	} },
+{    "addp6",	{"rwabrwabrwab",	0x21	} },
+{    "subp4",	{"rwabrwab",		0x22	} },
+{    "subp6",	{"rwabrwabrwab",	0x23	} },
+{    "cvtpt",	{"rwababrwab",		0x24	} },
+{    "mulp",	{"rwabrwabrwab",	0x25	} },
+{    "cvttp",	{"rwababrwab",		0x26	} },
+{    "divp",	{"rwabrwabrwab",	0x27	} },
+{    "movc3",	{"rwabab",		0x28	} },
+{    "cmpc3",	{"rwabab",		0x29	} },
+{    "scanc",	{"rwababrb",		0x2a	} },
+{    "spanc",	{"rwababrb",		0x2b	} },
+{    "movc5",	{"rwabrbrwab",		0x2c	} },
+{    "cmpc5",	{"rwabrbrwab",		0x2d	} },
+{    "movtc",	{"rwabrbabrwab",	0x2e	} },
+{    "movtuc",	{"rwabrbabrwab",	0x2f	} },
+{    "bsbw",	{"bw",			0x30	} },
+{    "brw",	{"bw",			0x31	} },
+{    "cvtwl",	{"rwwl",		0x32	} },
+{    "cvtwb",	{"rwwb",		0x33	} },
+{    "movp",	{"rwabab",		0x34	} },
+{    "cmpp3",	{"rwabab",		0x35	} },
+{    "cvtpl",	{"rwabwl",		0x36	} },
+{    "cmpp4",	{"rwabrwab",		0x37	} },
+{    "editpc",	{"rwababab",		0x38	} },
+{    "matchc",	{"rwabrwab",		0x39	} },
+{    "locc",	{"rbrwab",		0x3a	} },
+{    "skpc",	{"rbrwab",		0x3b	} },
+{    "movzwl",	{"rwwl",		0x3c	} },
+{    "acbw",	{"rwrwmwbw",		0x3d	} },
+{    "movaw",	{"awwl",		0x3e	} },
+{    "pushaw",	{"aw",			0x3f	} },
+{    "addf2",	{"rfmf",		0x40	} },
+{    "addf3",	{"rfrfwf",		0x41	} },
+{    "subf2",	{"rfmf",		0x42	} },
+{    "subf3",	{"rfrfwf",		0x43	} },
+{    "mulf2",	{"rfmf",		0x44	} },
+{    "mulf3",	{"rfrfwf",		0x45	} },
+{    "divf2",	{"rfmf",		0x46	} },
+{    "divf3",	{"rfrfwf",		0x47	} },
+{    "cvtfb",	{"rfwb",		0x48	} },
+{    "cvtfw",	{"rfww",		0x49	} },
+{    "cvtfl",	{"rfwl",		0x4a	} },
+{    "cvtrfl",	{"rfwl",		0x4b	} },
+{    "cvtbf",	{"rbwf",		0x4c	} },
+{    "cvtwf",	{"rwwf",		0x4d	} },
+{    "cvtlf",	{"rlwf",		0x4e	} },
+{    "acbf",	{"rfrfmfbw",		0x4f	} },
+{    "movf",	{"rfwf",		0x50	} },
+{    "cmpf",	{"rfrf",		0x51	} },
+{    "mnegf",	{"rfwf",		0x52	} },
+{    "tstf",	{"rf",			0x53	} },
+{    "emodf",	{"rfrbrfwlwf",		0x54	} },
+{    "polyf",	{"rfrwab",		0x55	} },
+{    "cvtfd",	{"rfwd",		0x56	} },
+                                        /* opcode 57 is not defined yet */
+{    "adawi",	{"rwmw",		0x58	} },
+                                        /* opcode 59 is not defined yet */
+                                        /* opcode 5a is not defined yet */
+                                        /* opcode 5b is not defined yet */
+{    "insqhi",	{"abaq",		0x5c	} },
+{    "insqti",	{"abaq",		0x5d	} },
+{    "remqhi",	{"aqwl",		0x5e	} },
+{    "remqti",	{"aqwl",		0x5f	} },
+{    "addd2",	{"rdmd",		0x60	} },
+{    "addd3",	{"rdrdwd",		0x61	} },
+{    "subd2",	{"rdmd",		0x62	} },
+{    "subd3",	{"rdrdwd",		0x63	} },
+{    "muld2",	{"rdmd",		0x64	} },
+{    "muld3",	{"rdrdwd",		0x65	} },
+{    "divd2",	{"rdmd",		0x66	} },
+{    "divd3",	{"rdrdwd",		0x67	} },
+{    "cvtdb",	{"rdwb",		0x68	} },
+{    "cvtdw",	{"rdww",		0x69	} },
+{    "cvtdl",	{"rdwl",		0x6a	} },
+{    "cvtrdl",	{"rdwl",		0x6b	} },
+{    "cvtbd",	{"rbwd",		0x6c	} },
+{    "cvtwd",	{"rwwd",		0x6d	} },
+{    "cvtld",	{"rlwd",		0x6e	} },
+{    "acbd",	{"rdrdmdbw",		0x6f	} },
+{    "movd",	{"rdwd",		0x70	} },
+{    "cmpd",	{"rdrd",		0x71	} },
+{    "mnegd",	{"rdwd",		0x72	} },
+{    "tstd",	{"rd",			0x73	} },
+{    "emodd",	{"rdrbrdwlwd",		0x74	} },
+{    "polyd",	{"rdrwab",		0x75	} },
+{    "cvtdf",	{"rdwf",		0x76	} },
+                                        /* opcode 77 is not defined yet */
+{    "ashl",	{"rbrlwl",		0x78	} },
+{    "ashq",	{"rbrqwq",		0x79	} },
+{    "emul",	{"rlrlrlwq",		0x7a	} },
+{    "ediv",	{"rlrqwlwl",		0x7b	} },
+{    "clrd",	{"wd",			0x7c	} },
+{    "clrg",	{"wg",			0x7c	} },
+{    "clrq",	{"wd",			0x7c	} },
+{    "movq",	{"rqwq",		0x7d	} },
+{    "movaq",	{"aqwl",		0x7e	} },
+{    "movad",	{"adwl",		0x7e	} },
+{    "pushaq",	{"aq",			0x7f	} },
+{    "pushad",	{"ad",			0x7f	} },
+{    "addb2",	{"rbmb",		0x80	} },
+{    "addb3",	{"rbrbwb",		0x81	} },
+{    "subb2",	{"rbmb",		0x82	} },
+{    "subb3",	{"rbrbwb",		0x83	} },
+{    "mulb2",	{"rbmb",		0x84	} },
+{    "mulb3",	{"rbrbwb",		0x85	} },
+{    "divb2",	{"rbmb",		0x86	} },
+{    "divb3",	{"rbrbwb",		0x87	} },
+{    "bisb2",	{"rbmb",		0x88	} },
+{    "bisb3",	{"rbrbwb",		0x89	} },
+{    "bicb2",	{"rbmb",		0x8a	} },
+{    "bicb3",	{"rbrbwb",		0x8b	} },
+{    "xorb2",	{"rbmb",		0x8c	} },
+{    "xorb3",	{"rbrbwb",		0x8d	} },
+{    "mnegb",	{"rbwb",		0x8e	} },
+{    "caseb",	{"rbrbrb",		0x8f	} },
+{    "movb",	{"rbwb",		0x90	} },
+{    "cmpb",	{"rbrb",		0x91	} },
+{    "mcomb",	{"rbwb",		0x92	} },
+{    "bitb",	{"rbrb",		0x93	} },
+{    "clrb",	{"wb",			0x94	} },
+{    "tstb",	{"rb",			0x95	} },
+{    "incb",	{"mb",			0x96	} },
+{    "decb",	{"mb",			0x97	} },
+{    "cvtbl",	{"rbwl",		0x98	} },
+{    "cvtbw",	{"rbww",		0x99	} },
+{    "movzbl",	{"rbwl",		0x9a	} },
+{    "movzbw",	{"rbww",		0x9b	} },
+{    "rotl",	{"rbrlwl",		0x9c	} },
+{    "acbb",	{"rbrbmbbw",		0x9d	} },
+{    "movab",	{"abwl",		0x9e	} },
+{    "pushab",	{"ab",			0x9f	} },
+{    "addw2",	{"rwmw",		0xa0	} },
+{    "addw3",	{"rwrwww",		0xa1	} },
+{    "subw2",	{"rwmw",		0xa2	} },
+{    "subw3",	{"rwrwww",		0xa3	} },
+{    "mulw2",	{"rwmw",		0xa4	} },
+{    "mulw3",	{"rwrwww",		0xa5	} },
+{    "divw2",	{"rwmw",		0xa6	} },
+{    "divw3",	{"rwrwww",		0xa7	} },
+{    "bisw2",	{"rwmw",		0xa8	} },
+{    "bisw3",	{"rwrwww",		0xa9	} },
+{    "bicw2",	{"rwmw",		0xaa	} },
+{    "bicw3",	{"rwrwww",		0xab	} },
+{    "xorw2",	{"rwmw",		0xac	} },
+{    "xorw3",	{"rwrwww",		0xad	} },
+{    "mnegw",	{"rwww",		0xae	} },
+{    "casew",	{"rwrwrw",		0xaf	} },
+{    "movw",	{"rwww",		0xb0	} },
+{    "cmpw",	{"rwrw",		0xb1	} },
+{    "mcomw",	{"rwww",		0xb2	} },
+{    "bitw",	{"rwrw",		0xb3	} },
+{    "clrw",	{"ww",			0xb4	} },
+{    "tstw",	{"rw",			0xb5	} },
+{    "incw",	{"mw",			0xb6	} },
+{    "decw",	{"mw",			0xb7	} },
+{    "bispsw",	{"rw",			0xb8	} },
+{    "bicpsw",	{"rw",			0xb9	} },
+{    "popr",	{"rw",			0xba	} },
+{    "pushr",	{"rw",			0xbb	} },
+{    "chmk",	{"rw",			0xbc	} },
+{    "chme",	{"rw",			0xbd	} },
+{    "chms",	{"rw",			0xbe	} },
+{    "chmu",	{"rw",			0xbf	} },
+{    "addl2",	{"rlml",		0xc0	} },
+{    "addl3",	{"rlrlwl",		0xc1	} },
+{    "subl2",	{"rlml",		0xc2	} },
+{    "subl3",	{"rlrlwl",		0xc3	} },
+{    "mull2",	{"rlml",		0xc4	} },
+{    "mull3",	{"rlrlwl",		0xc5	} },
+{    "divl2",	{"rlml",		0xc6	} },
+{    "divl3",	{"rlrlwl",		0xc7	} },
+{    "bisl2",	{"rlml",		0xc8	} },
+{    "bisl3",	{"rlrlwl",		0xc9	} },
+{    "bicl2",	{"rlml",		0xca	} },
+{    "bicl3",	{"rlrlwl",		0xcb	} },
+{    "xorl2",	{"rlml",		0xcc	} },
+{    "xorl3",	{"rlrlwl",		0xcd	} },
+{    "mnegl",	{"rlwl",		0xce	} },
+{    "casel",	{"rlrlrl",		0xcf	} },
+{    "movl",	{"rlwl",		0xd0	} },
+{    "cmpl",	{"rlrl",		0xd1	} },
+{    "mcoml",	{"rlwl",		0xd2	} },
+{    "bitl",	{"rlrl",		0xd3	} },
+{    "clrf",	{"wf",			0xd4	} },
+{    "clrl",	{"wl",			0xd4	} },
+{    "tstl",	{"rl",			0xd5	} },
+{    "incl",	{"ml",			0xd6	} },
+{    "decl",	{"ml",			0xd7	} },
+{    "adwc",	{"rlml",		0xd8	} },
+{    "sbwc",	{"rlml",		0xd9	} },
+{    "mtpr",	{"rlrl",		0xda	} },
+{    "mfpr",	{"rlwl",		0xdb	} },
+{    "movpsl",	{"wl",			0xdc	} },
+{    "pushl",	{"rl",			0xdd	} },
+{    "moval",	{"alwl",		0xde	} },
+{    "movaf",	{"afwl",		0xde	} },
+{    "pushal",	{"al",			0xdf	} },
+{    "pushaf",	{"af",			0xdf	} },
+{    "bbs",	{"rlvbbb",		0xe0	} },
+{    "bbc",	{"rlvbbb",		0xe1	} },
+{    "bbss",	{"rlvbbb",		0xe2	} },
+{    "bbcs",	{"rlvbbb",		0xe3	} },
+{    "bbsc",	{"rlvbbb",		0xe4	} },
+{    "bbcc",	{"rlvbbb",		0xe5	} },
+{    "bbssi",	{"rlvbbb",		0xe6	} },
+{    "bbcci",	{"rlvbbb",		0xe7	} },
+{    "blbs",	{"rlbb",		0xe8	} },
+{    "blbc",	{"rlbb",		0xe9	} },
+{    "ffs",	{"rlrbvbwl",		0xea	} },
+{    "ffc",	{"rlrbvbwl",		0xeb	} },
+{    "cmpv",	{"rlrbvbrl",		0xec	} },
+{    "cmpzv",	{"rlrbvbrl",		0xed	} },
+{    "extv",	{"rlrbvbwl",		0xee	} },
+{    "extzv",	{"rlrbvbwl",		0xef	} },
+{    "insv",	{"rlrlrbvb",		0xf0	} },
+{    "acbl",	{"rlrlmlbw",		0xf1	} },
+{    "aoblss",	{"rlmlbb",		0xf2	} },
+{    "aobleq",	{"rlmlbb",		0xf3	} },
+{    "sobgeq",	{"mlbb",		0xf4	} },
+{    "sobgtr",	{"mlbb",		0xf5	} },
+{    "cvtlb",	{"rlwb",		0xf6	} },
+{    "cvtlw",	{"rlww",		0xf7	} },
+{    "ashp",	{"rbrwabrbrwab",	0xf8	} },
+{    "cvtlp",	{"rlrwab",		0xf9	} },
+{    "callg",	{"abab",		0xfa	} },
+{    "calls",	{"rlab",		0xfb	} },
+{    "xfc",	{"",			0xfc	} },
+                                        /* undefined opcodes here */
+{    "cvtdh",	{"rdwh",		0x32fd	} },
+{    "cvtgf",	{"rgwh",		0x33fd	} },
+{    "addg2",	{"rgmg",		0x40fd	} },
+{    "addg3",	{"rgrgwg",		0x41fd	} },
+{    "subg2",	{"rgmg",		0x42fd	} },
+{    "subg3",	{"rgrgwg",		0x43fd	} },
+{    "mulg2",	{"rgmg",		0x44fd	} },
+{    "mulg3",	{"rgrgwg",		0x45fd	} },
+{    "divg2",	{"rgmg",		0x46fd	} },
+{    "divg3",	{"rgrgwg",		0x47fd	} },
+{    "cvtgb",	{"rgwb",		0x48fd	} },
+{    "cvtgw",	{"rgww",		0x49fd	} },
+{    "cvtgl",	{"rgwl",		0x4afd	} },
+{    "cvtrgl",	{"rgwl",		0x4bfd	} },
+{    "cvtbg",	{"rbwg",		0x4cfd	} },
+{    "cvtwg",	{"rwwg",		0x4dfd	} },
+{    "cvtlg",	{"rlwg",		0x4efd	} },
+{    "acbg",	{"rgrgmgbw",		0x4ffd	} },
+{    "movg",	{"rgwg",		0x50fd	} },
+{    "cmpg",	{"rgrg",		0x51fd	} },
+{    "mnegg",	{"rgwg",		0x52fd	} },
+{    "tstg",	{"rg",			0x53fd	} },
+{    "emodg",	{"rgrwrgwlwg",		0x54fd	} },
+{    "polyg",	{"rgrwab",		0x55fd	} },
+{    "cvtgh",	{"rgwh",		0x56fd	} },
+                                        /* undefined opcodes here */
+{    "addh2",	{"rhmh",		0x60fd	} },
+{    "addh3",	{"rhrhwh",		0x61fd	} },
+{    "subh2",	{"rhmh",		0x62fd	} },
+{    "subh3",	{"rhrhwh",		0x63fd	} },
+{    "mulh2",	{"rhmh",		0x64fd	} },
+{    "mulh3",	{"rhrhwh",		0x65fd	} },
+{    "divh2",	{"rhmh",		0x66fd	} },
+{    "divh3",	{"rhrhwh",		0x67fd	} },
+{    "cvthb",	{"rhwb",		0x68fd	} },
+{    "cvthw",	{"rhww",		0x69fd	} },
+{    "cvthl",	{"rhwl",		0x6afd	} },
+{    "cvtrhl",	{"rhwl",		0x6bfd	} },
+{    "cvtbh",	{"rbwh",		0x6cfd	} },
+{    "cvtwh",	{"rwwh",		0x6dfd	} },
+{    "cvtlh",	{"rlwh",		0x6efd	} },
+{    "acbh",	{"rhrhmhbw",		0x6ffd	} },
+{    "movh",	{"rhwh",		0x70fd	} },
+{    "cmph",	{"rhrh",		0x71fd	} },
+{    "mnegh",	{"rhwh",		0x72fd	} },
+{    "tsth",	{"rh",			0x73fd	} },
+{    "emodh",	{"rhrwrhwlwh",		0x74fd	} },
+{    "polyh",	{"rhrwab",		0x75fd	} },
+{    "cvthg",	{"rhwg",		0x76fd	} },
+                                        /* undefined opcodes here */
+{    "clrh",	{"wh",			0x7cfd	} },
+{    "clro",	{"wo",			0x7cfd	} },
+{    "movo",	{"rowo",		0x7dfd	} },
+{    "movah",	{"ahwl",		0x7efd	} },
+{    "movao",	{"aowl",		0x7efd	} },
+{    "pushah",	{"ah",			0x7ffd	} },
+{    "pushao",	{"ao",			0x7ffd	} },
+                                        /* undefined opcodes here */
+{    "cvtfh",	{"rfwh",		0x98fd	} },
+{    "cvtfg",	{"rfwg",		0x99fd	} },
+                                        /* undefined opcodes here */
+{    "cvthf",	{"rhwf",		0xf6fd	} },
+{    "cvthd",	{"rhwd",		0xf7fd	} },
+                                        /* undefined opcodes here */
+{    "bugl",	{"rl",			0xfdff	} },
+{    "bugw",	{"rw",			0xfeff	} },
+                                        /* undefined opcodes here */
+
+{      "",	{"", 0} }		/* empty is end sentinel */
+
+};				/* votstrs */
+
+/* end: vax.opcode.h */
diff --git a/binutils-2.25/include/opcode/xgate.h b/binutils-2.25/include/opcode/xgate.h
new file mode 100644
index 00000000..8451e66c
--- /dev/null
+++ b/binutils-2.25/include/opcode/xgate.h
@@ -0,0 +1,100 @@
+/* xgate.h -- Freescale XGATE opcode list
+   Copyright 2010, 2011, 2012 Free Software Foundation, Inc.
+   Written by Sean Keys (skeys@ipdatasys.com)
+
+   This file is part of the GNU opcodes library.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA. */
+
+#ifndef _OPCODE_XGATE_H
+#define _OPCODE_XGATE_H
+
+/* XGATE CCR flag definitions.  */
+#define XGATE_N_BIT   0x08	/* XGN - Sign Flag */
+#define XGATE_Z_BIT   0x04	/* XGZ - Zero Flag */
+#define XGATE_V_BIT   0x02	/* XGV - Overflow Flag */
+#define XGATE_C_BIT   0x01	/* XGC - Carry Flag */
+
+/* Access Detail Notation
+   V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
+   P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
+   r — 8-bit data read: lasts for at least one RISC core cycle
+   R — 16-bit data read: lasts for at least one RISC core cycle
+   w — 8-bit data write: lasts for at least one RISC core cycle
+   W — 16-bit data write: lasts for at least one RISC core cycle
+   A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles
+   f — Free cycle: no read or write, lasts for one RISC core cycles.  */
+#define XGATE_CYCLE_V	0x01
+#define XGATE_CYCLE_P	0x02
+#define XGATE_CYCLE_r	0x04
+#define XGATE_CYCLE_R	0x08
+#define XGATE_CYCLE_w	0x10
+#define XGATE_CYCLE_W	0x20
+#define XGATE_CYCLE_A	0x40
+#define XGATE_CYCLE_f	0x80
+
+/* XGATE operand formats as stored in the XGATE_opcode table.
+   They are only used by GAS to recognize operands.  */
+#define XGATE_OP_INH                  ""  /* Inherent.  */
+#define XGATE_OP_TRI		 "r,r,r"  /* Register followed by two registers.                    */
+#define XGATE_OP_DYA		   "r,r"  /* Register followed by a register.                       */
+#define XGATE_OP_IMM16            "r,if"  /* Register followed by 16-bit value.                    */
+#define XGATE_OP_IMM8	          "r,i8"  /* Register followed by 8-bit value.                      */
+#define XGATE_OP_IMM4             "r,i4"  /* Register followed by 4-bit value.                     */
+#define XGATE_OP_IMM3	            "i3"  /* Register followed by 3-bit value.                      */
+#define XGATE_OP_MON		     "r"  /* Single register.                                       */
+#define XGATE_OP_MON_R_C	   "r,c"  /* General register followed by ccr register.             */
+#define XGATE_OP_MON_C_R	   "c,r"  /* CCR register followed by a general register.           */
+#define XGATE_OP_MON_R_P	   "r,p"  /* General register followed by pc register.              */
+#define XGATE_OP_IDR		 "r,r,+"  /* Three registers with the third having a -/+ directive. */
+#define XGATE_OP_IDO5	        "r,r,i5"  /* Two general registers followed by an immediate value.  */
+#define XGATE_OP_REL9	            "b9"  /* 9-bit value that is relative to the current pc.        */
+#define XGATE_OP_REL10	            "ba"  /* 10-bit value that is relative to the current pc.       */
+#define XGATE_OP_DYA_MON	    "=r"
+/* Macro definitions.  */
+#define XGATE_OP_IMM16mADD    "r,if; addl addh"
+#define XGATE_OP_IMM16mAND    "r,if; andl andh"
+#define XGATE_OP_IMM16mCPC    "r,if; cmpl cpch"
+#define XGATE_OP_IMM16mSUB    "r,if; subl subh"
+#define XGATE_OP_IMM16mLDW    "r,if; ldl ldh"
+
+/* CPU variant identification.  */
+#define XGATE_V1 0x1
+#define XGATE_V2 0x2
+#define XGATE_V3 0x4
+
+/* The opcode table definitions.  */
+struct xgate_opcode
+{
+  char * name;                  /* Op-code name.  */
+  char * constraints;           /* Constraint chars.  */
+  char * format;                /* Bit definitions.  */
+  unsigned int size;            /* Opcode size in bytes.  */
+  unsigned int bin_opcode;      /* Binary opcode with operands masked off.  */
+  unsigned char cycles_min;     /* Minimum cpu cycles needed.  */
+  unsigned char cycles_max;     /* Maximum cpu cycles needed.  */
+  unsigned char set_flags_mask; /* CCR flags set.  */
+  unsigned char clr_flags_mask; /* CCR flags cleared.  */
+  unsigned char chg_flags_mask; /* CCR flags changed.  */
+  unsigned char arch;           /* CPU variant.  */
+};
+
+/* The opcode table.  The table contains all the opcodes (all pages).
+   You can't rely on the order.  */
+extern const struct xgate_opcode xgate_opcodes[];
+extern const int xgate_num_opcodes;
+
+#endif /* _OPCODE_XGATE_H */
diff --git a/binutils-2.25/include/os9k.h b/binutils-2.25/include/os9k.h
new file mode 100644
index 00000000..e8baee17
--- /dev/null
+++ b/binutils-2.25/include/os9k.h
@@ -0,0 +1,181 @@
+/* os9k.h  -  OS-9000 i386 module header definitions
+   Copyright 2000 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+   
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+#if !defined(_MODULE_H)
+#define _MODULE_H
+
+#define _MPF386
+
+/* Size of common header less parity field.  */
+#define N_M_PARITY  (sizeof(mh_com)-sizeof(unisgned short))
+#define OLD_M_PARITY 46
+#define M_PARITY N_M_PARITY
+
+#ifdef _MPF68K
+#define MODSYNC 0x4afc		/* Module header sync code for 680x0 processors.  */
+#endif
+
+#ifdef _MPF386
+#define MODSYNC 0x4afc		/* Module header sync code for 80386 processors.  */
+#endif
+
+#define MODREV	1		/* Module format revision 1.  */
+#define CRCCON	0x800063	/* CRC polynomial constant.  */
+
+/* Module access permission values.  */
+#define MP_OWNER_READ	0x0001
+#define MP_OWNER_WRITE	0x0002
+#define MP_OWNER_EXEC	0x0004
+#define MP_GROUP_READ	0x0010
+#define MP_GROUP_WRITE	0x0020
+#define MP_GROUP_EXEC	0x0040
+#define MP_WORLD_READ	0x0100
+#define MP_WORLD_WRITE	0x0200
+#define MP_WORLD_EXEC	0x0400
+#define MP_WORLD_ACCESS	0x0777
+#define MP_OWNER_MASK	0x000f
+#define MP_GROUP_MASK	0x00f0
+#define MP_WORLD_MASK	0x0f00
+#define MP_SYSTM_MASK	0xf000
+
+/* Module Type/Language values.  */
+#define MT_ANY		0
+#define MT_PROGRAM	0x0001
+#define MT_SUBROUT	0x0002
+#define MT_MULTI	0x0003
+#define MT_DATA		0x0004
+#define MT_TRAPLIB	0x000b
+#define MT_SYSTEM	0x000c
+#define MT_FILEMAN	0x000d
+#define MT_DEVDRVR	0x000e 
+#define MT_DEVDESC	0x000f
+#define MT_MASK		0xff00
+
+#define ML_ANY		0
+#define ML_OBJECT	1
+#define ML_ICODE	2
+#define ML_PCODE	3
+#define ML_CCODE	4
+#define ML_CBLCODE	5
+#define ML_FRTNCODE	6
+#define ML_MASK		0x00ff
+
+#define mktypelang(type, lang)	(((type) << 8) | (lang))
+
+/* Module Attribute values.  */
+#define MA_REENT	0x80
+#define MA_GHOST	0x40
+#define MA_SUPER	0x20
+#define MA_MASK		0xff00
+#define MR_MASK		0x00ff
+
+#define mkattrevs(attr, revs)	(((attr) << 8) | (revs))
+
+#define m_user 		m_owner.grp_usr.usr
+#define m_group 	m_owner.grp_usr.grp
+#define m_group_user	m_owner.group_user
+
+/* Macro definitions for accessing module header fields.  */
+#define MODNAME(mod) ((u_char*)((u_char*)mod + ((Mh_com)mod)->m_name))
+#if 0
+/* Appears not to be used, and the u_int32 typedef is gone (because it
+   conflicted with a Mach header.  */
+#define MODSIZE(mod) ((u_int32)((Mh_com)mod)->m_size)
+#endif /* 0 */
+#define MHCOM_BYTES_SIZE 80
+#define N_BADMAG(a) (((a).a_info) != MODSYNC)
+
+typedef struct mh_com
+{
+  /* Sync bytes ($4afc).  */
+  unsigned char m_sync[2];
+  unsigned char m_sysrev[2];	/* System revision check value.  */
+  unsigned char m_size[4];	/* Module size.  */
+  unsigned char m_owner[4];	/* Group/user id.  */
+  unsigned char m_name[4];	/* Offset to module name.  */
+  unsigned char m_access[2];	/* Access permissions.  */
+  unsigned char m_tylan[2];	/* Type/lang.  */
+  unsigned char m_attrev[2];	/* Rev/attr.  */
+  unsigned char m_edit[2];	/* Edition.  */
+  unsigned char m_needs[4];	/* Module hardware requirements flags. (reserved).  */
+  unsigned char m_usage[4];	/* Comment string offset.  */
+  unsigned char m_symbol[4];	/* Symbol table offset.  */
+  unsigned char m_exec[4];	/* Offset to execution entry point.  */
+  unsigned char m_excpt[4];	/* Offset to exception entry point.  */
+  unsigned char m_data[4];	/* Data storage requirement.  */
+  unsigned char m_stack[4];	/* Stack size.  */
+  unsigned char m_idata[4];	/* Offset to initialized data.  */
+  unsigned char m_idref[4];	/* Offset to data reference lists.  */
+  unsigned char m_init[4];	/* Initialization routine offset.  */
+  unsigned char m_term[4];	/* Termination routine offset.  */
+  unsigned char m_ident[2];	/* Ident code for ident program.  */
+  char          m_spare[8];	/* Reserved bytes.  */
+  unsigned char m_parity[2]; 	/* Header parity.  */
+} mh_com,*Mh_com;
+
+/* Executable memory module.  */
+typedef mh_com *Mh_exec,mh_exec;
+
+/* Data memory module.  */
+typedef mh_com *Mh_data,mh_data;
+
+/* File manager memory module.  */
+typedef mh_com *Mh_fman,mh_fman;
+
+/* Device driver module.  */
+typedef mh_com *Mh_drvr,mh_drvr;
+
+/* Trap handler module.  */
+typedef	mh_com mh_trap, *Mh_trap;
+
+/* Device descriptor module.  */
+typedef	mh_com *Mh_dev,mh_dev;
+
+/* Configuration module.  */
+typedef mh_com *Mh_config, mh_config;
+
+#if 0 
+
+#if !defined(_MODDIR_H)
+/* Go get _os_fmod (and others).  */
+#include <moddir.h>
+#endif
+
+error_code _os_crc (void *, u_int32, int *);
+error_code _os_datmod (char *, u_int32, u_int16 *, u_int16 *, u_int32, void **, mh_data **);
+error_code _os_get_moddir (void *, u_int32 *);
+error_code _os_initdata (mh_com *, void *);
+error_code _os_link (char **, mh_com **, void **, u_int16 *, u_int16 *);
+error_code _os_linkm (mh_com *, void **, u_int16 *, u_int16 *);
+error_code _os_load (char *, mh_com **, void **, u_int32, u_int16 *, u_int16 *, u_int32);
+error_code _os_mkmodule (char *, u_int32, u_int16 *, u_int16 *, u_int32, void **, mh_com **, u_int32);
+error_code _os_modaddr (void *, mh_com **);
+error_code _os_setcrc (mh_com *);
+error_code _os_slink (u_int32, char *, void **, void **, mh_com **);
+error_code _os_slinkm (u_int32, mh_com *, void **, void **);
+error_code _os_unlink (mh_com *);
+error_code _os_unload (char *, u_int32);
+error_code _os_tlink (u_int32, char *, void **, mh_trap **, void *, u_int32);
+error_code _os_tlinkm (u_int32, mh_com *, void **, void *, u_int32);
+error_code _os_iodel (mh_com *);
+error_code _os_vmodul (mh_com *, mh_com *, u_int32);
+#endif /* 0 */
+
+#endif
diff --git a/binutils-2.25/include/partition.h b/binutils-2.25/include/partition.h
new file mode 100644
index 00000000..d8b554f8
--- /dev/null
+++ b/binutils-2.25/include/partition.h
@@ -0,0 +1,82 @@
+/* List implementation of a partition of consecutive integers.
+   Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc.
+   Contributed by CodeSourcery, LLC.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+/* This package implements a partition of consecutive integers.  The
+   elements are partitioned into classes.  Each class is represented
+   by one of its elements, the canonical element, which is chosen
+   arbitrarily from elements in the class.  The principal operations
+   on a partition are FIND, which takes an element, determines its
+   class, and returns the canonical element for that class, and UNION,
+   which unites the two classes that contain two given elements into a
+   single class.
+
+   The list implementation used here provides constant-time finds.  By
+   storing the size of each class with the class's canonical element,
+   it is able to perform unions over all the classes in the partition
+   in O (N log N) time.  */
+
+#ifndef _PARTITION_H
+#define _PARTITION_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "ansidecl.h"
+#include <stdio.h>
+
+struct partition_elem
+{
+  /* The canonical element that represents the class containing this
+     element.  */
+  int class_element;
+  /* The next element in this class.  Elements in each class form a
+     circular list.  */
+  struct partition_elem* next;
+  /* The number of elements in this class.  Valid only if this is the
+     canonical element for its class.  */
+  unsigned class_count;
+};
+
+typedef struct partition_def 
+{
+  /* The number of elements in this partition.  */
+  int num_elements;
+  /* The elements in the partition.  */
+  struct partition_elem elements[1];
+} *partition;
+
+extern partition partition_new (int);
+extern void partition_delete (partition);
+extern int partition_union (partition, int, int);
+extern void partition_print (partition,	FILE*);
+
+/* Returns the canonical element corresponding to the class containing
+   ELEMENT__ in PARTITION__.  */
+
+#define partition_find(partition__, element__) \
+    ((partition__)->elements[(element__)].class_element)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _PARTITION_H */
diff --git a/binutils-2.25/include/plugin-api.h b/binutils-2.25/include/plugin-api.h
new file mode 100644
index 00000000..5797d4dc
--- /dev/null
+++ b/binutils-2.25/include/plugin-api.h
@@ -0,0 +1,432 @@
+/* plugin-api.h -- External linker plugin API.  */
+
+/* Copyright 2009, 2010 Free Software Foundation, Inc.
+   Written by Cary Coutant <ccoutant@google.com>.
+
+   This file is part of binutils.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* This file defines the interface for writing a linker plugin, which is
+   described at < http://gcc.gnu.org/wiki/whopr/driver >.  */
+
+#ifndef PLUGIN_API_H
+#define PLUGIN_API_H
+
+#ifdef HAVE_STDINT_H
+#include <stdint.h>
+#elif defined(HAVE_INTTYPES_H)
+#include <inttypes.h>
+#endif
+#include <sys/types.h>
+#if !defined(HAVE_STDINT_H) && !defined(HAVE_INTTYPES_H) && \
+    !defined(UINT64_MAX) && !defined(uint64_t)
+#error can not find uint64_t type
+#endif
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Status code returned by most API routines.  */
+
+enum ld_plugin_status
+{
+  LDPS_OK = 0,
+  LDPS_NO_SYMS,         /* Attempt to get symbols that haven't been added. */
+  LDPS_BAD_HANDLE,      /* No claimed object associated with given handle. */
+  LDPS_ERR
+  /* Additional Error codes TBD.  */
+};
+
+/* The version of the API specification.  */
+
+enum ld_plugin_api_version
+{
+  LD_PLUGIN_API_VERSION = 1
+};
+
+/* The type of output file being generated by the linker.  */
+
+enum ld_plugin_output_file_type
+{
+  LDPO_REL,
+  LDPO_EXEC,
+  LDPO_DYN,
+  LDPO_PIE
+};
+
+/* An input file managed by the plugin library.  */
+
+struct ld_plugin_input_file
+{
+  const char *name;
+  int fd;
+  off_t offset;
+  off_t filesize;
+  void *handle;
+};
+
+/* A symbol belonging to an input file managed by the plugin library.  */
+
+struct ld_plugin_symbol
+{
+  char *name;
+  char *version;
+  int def;
+  int visibility;
+  uint64_t size;
+  char *comdat_key;
+  int resolution;
+};
+
+/* An object's section.  */
+
+struct ld_plugin_section
+{
+  const void* handle;
+  unsigned int shndx;
+};
+
+/* Whether the symbol is a definition, reference, or common, weak or not.  */
+
+enum ld_plugin_symbol_kind
+{
+  LDPK_DEF,
+  LDPK_WEAKDEF,
+  LDPK_UNDEF,
+  LDPK_WEAKUNDEF,
+  LDPK_COMMON
+};
+
+/* The visibility of the symbol.  */
+
+enum ld_plugin_symbol_visibility
+{
+  LDPV_DEFAULT,
+  LDPV_PROTECTED,
+  LDPV_INTERNAL,
+  LDPV_HIDDEN
+};
+
+/* How a symbol is resolved.  */
+
+enum ld_plugin_symbol_resolution
+{
+  LDPR_UNKNOWN = 0,
+
+  /* Symbol is still undefined at this point.  */
+  LDPR_UNDEF,
+
+  /* This is the prevailing definition of the symbol, with references from
+     regular object code.  */
+  LDPR_PREVAILING_DEF,
+
+  /* This is the prevailing definition of the symbol, with no
+     references from regular objects.  It is only referenced from IR
+     code.  */
+  LDPR_PREVAILING_DEF_IRONLY,
+
+  /* This definition was pre-empted by a definition in a regular
+     object file.  */
+  LDPR_PREEMPTED_REG,
+
+  /* This definition was pre-empted by a definition in another IR file.  */
+  LDPR_PREEMPTED_IR,
+
+  /* This symbol was resolved by a definition in another IR file.  */
+  LDPR_RESOLVED_IR,
+
+  /* This symbol was resolved by a definition in a regular object
+     linked into the main executable.  */
+  LDPR_RESOLVED_EXEC,
+
+  /* This symbol was resolved by a definition in a shared object.  */
+  LDPR_RESOLVED_DYN,
+
+  /* This is the prevailing definition of the symbol, with no
+     references from regular objects.  It is only referenced from IR
+     code, but the symbol is exported and may be referenced from
+     a dynamic object (not seen at link time).  */
+  LDPR_PREVAILING_DEF_IRONLY_EXP
+};
+
+/* The plugin library's "claim file" handler.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_claim_file_handler) (
+  const struct ld_plugin_input_file *file, int *claimed);
+
+/* The plugin library's "all symbols read" handler.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_all_symbols_read_handler) (void);
+
+/* The plugin library's cleanup handler.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_cleanup_handler) (void);
+
+/* The linker's interface for registering the "claim file" handler.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_register_claim_file) (ld_plugin_claim_file_handler handler);
+
+/* The linker's interface for registering the "all symbols read" handler.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_register_all_symbols_read) (
+  ld_plugin_all_symbols_read_handler handler);
+
+/* The linker's interface for registering the cleanup handler.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_register_cleanup) (ld_plugin_cleanup_handler handler);
+
+/* The linker's interface for adding symbols from a claimed input file.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_add_symbols) (void *handle, int nsyms,
+                          const struct ld_plugin_symbol *syms);
+
+/* The linker's interface for getting the input file information with
+   an open (possibly re-opened) file descriptor.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_get_input_file) (const void *handle,
+                             struct ld_plugin_input_file *file);
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_get_view) (const void *handle, const void **viewp);
+
+/* The linker's interface for releasing the input file.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_release_input_file) (const void *handle);
+
+/* The linker's interface for retrieving symbol resolution information.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_get_symbols) (const void *handle, int nsyms,
+                          struct ld_plugin_symbol *syms);
+
+/* The linker's interface for adding a compiled input file.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_add_input_file) (const char *pathname);
+
+/* The linker's interface for adding a library that should be searched.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_add_input_library) (const char *libname);
+
+/* The linker's interface for adding a library path that should be searched.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_set_extra_library_path) (const char *path);
+
+/* The linker's interface for issuing a warning or error message.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_message) (int level, const char *format, ...);
+
+/* The linker's interface for retrieving the number of sections in an object.
+   The handle is obtained in the claim_file handler.  This interface should
+   only be invoked in the claim_file handler.   This function sets *COUNT to
+   the number of sections in the object.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_get_input_section_count) (const void* handle, unsigned int *count);
+
+/* The linker's interface for retrieving the section type of a specific
+   section in an object.  This interface should only be invoked in the
+   claim_file handler.  This function sets *TYPE to an ELF SHT_xxx value.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_get_input_section_type) (const struct ld_plugin_section section,
+                                     unsigned int *type);
+
+/* The linker's interface for retrieving the name of a specific section in
+   an object. This interface should only be invoked in the claim_file handler.
+   This function sets *SECTION_NAME_PTR to a null-terminated buffer allocated
+   by malloc.  The plugin must free *SECTION_NAME_PTR.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_get_input_section_name) (const struct ld_plugin_section section,
+                                     char **section_name_ptr);
+
+/* The linker's interface for retrieving the contents of a specific section
+   in an object.  This interface should only be invoked in the claim_file
+   handler.  This function sets *SECTION_CONTENTS to point to a buffer that is
+   valid until clam_file handler returns.  It sets *LEN to the size of the
+   buffer.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_get_input_section_contents) (const struct ld_plugin_section section,
+                                         const unsigned char **section_contents,
+                                         size_t* len);
+
+/* The linker's interface for specifying the desired order of sections.
+   The sections should be specifed using the array SECTION_LIST in the
+   order in which they should appear in the final layout.  NUM_SECTIONS
+   specifies the number of entries in each array.  This should be invoked
+   in the all_symbols_read handler.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_update_section_order) (const struct ld_plugin_section *section_list,
+				   unsigned int num_sections);
+
+/* The linker's interface for specifying that reordering of sections is
+   desired so that the linker can prepare for it.  This should be invoked
+   before update_section_order, preferably in the claim_file handler.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_allow_section_ordering) (void);
+
+/* The linker's interface for specifying that a subset of sections is
+   to be mapped to a unique segment.  If the plugin wants to call
+   unique_segment_for_sections, it must call this function from a
+   claim_file_handler or when it is first loaded.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_allow_unique_segment_for_sections) (void);
+
+/* The linker's interface for specifying that a specific set of sections
+   must be mapped to a unique segment.  ELF segments do not have names
+   and the NAME is used as the name of the newly created output section
+   that is then placed in the unique PT_LOAD segment.  FLAGS is used to
+   specify if any additional segment flags need to be set.  For instance,
+   a specific segment flag can be set to identify this segment.  Unsetting
+   segment flags that would be set by default is not possible.  The
+   parameter SEGMENT_ALIGNMENT when non-zero will override the default.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_unique_segment_for_sections) (
+    const char* segment_name,
+    uint64_t segment_flags,
+    uint64_t segment_alignment,
+    const struct ld_plugin_section * section_list,
+    unsigned int num_sections);
+
+enum ld_plugin_level
+{
+  LDPL_INFO,
+  LDPL_WARNING,
+  LDPL_ERROR,
+  LDPL_FATAL
+};
+
+/* Values for the tv_tag field of the transfer vector.  */
+
+enum ld_plugin_tag
+{
+  LDPT_NULL = 0,
+  LDPT_API_VERSION = 1,
+  LDPT_GOLD_VERSION = 2,
+  LDPT_LINKER_OUTPUT = 3,
+  LDPT_OPTION = 4,
+  LDPT_REGISTER_CLAIM_FILE_HOOK = 5,
+  LDPT_REGISTER_ALL_SYMBOLS_READ_HOOK = 6,
+  LDPT_REGISTER_CLEANUP_HOOK = 7,
+  LDPT_ADD_SYMBOLS = 8,
+  LDPT_GET_SYMBOLS = 9,
+  LDPT_ADD_INPUT_FILE = 10,
+  LDPT_MESSAGE = 11,
+  LDPT_GET_INPUT_FILE = 12,
+  LDPT_RELEASE_INPUT_FILE = 13,
+  LDPT_ADD_INPUT_LIBRARY = 14,
+  LDPT_OUTPUT_NAME = 15,
+  LDPT_SET_EXTRA_LIBRARY_PATH = 16,
+  LDPT_GNU_LD_VERSION = 17,
+  LDPT_GET_VIEW = 18,
+  LDPT_GET_INPUT_SECTION_COUNT = 19,
+  LDPT_GET_INPUT_SECTION_TYPE = 20,
+  LDPT_GET_INPUT_SECTION_NAME = 21,
+  LDPT_GET_INPUT_SECTION_CONTENTS = 22,
+  LDPT_UPDATE_SECTION_ORDER = 23,
+  LDPT_ALLOW_SECTION_ORDERING = 24,
+  LDPT_GET_SYMBOLS_V2 = 25,
+  LDPT_ALLOW_UNIQUE_SEGMENT_FOR_SECTIONS = 26,
+  LDPT_UNIQUE_SEGMENT_FOR_SECTIONS = 27
+};
+
+/* The plugin transfer vector.  */
+
+struct ld_plugin_tv
+{
+  enum ld_plugin_tag tv_tag;
+  union
+  {
+    int tv_val;
+    const char *tv_string;
+    ld_plugin_register_claim_file tv_register_claim_file;
+    ld_plugin_register_all_symbols_read tv_register_all_symbols_read;
+    ld_plugin_register_cleanup tv_register_cleanup;
+    ld_plugin_add_symbols tv_add_symbols;
+    ld_plugin_get_symbols tv_get_symbols;
+    ld_plugin_add_input_file tv_add_input_file;
+    ld_plugin_message tv_message;
+    ld_plugin_get_input_file tv_get_input_file;
+    ld_plugin_get_view tv_get_view;
+    ld_plugin_release_input_file tv_release_input_file;
+    ld_plugin_add_input_library tv_add_input_library;
+    ld_plugin_set_extra_library_path tv_set_extra_library_path;
+    ld_plugin_get_input_section_count tv_get_input_section_count;
+    ld_plugin_get_input_section_type tv_get_input_section_type;
+    ld_plugin_get_input_section_name tv_get_input_section_name;
+    ld_plugin_get_input_section_contents tv_get_input_section_contents;
+    ld_plugin_update_section_order tv_update_section_order;
+    ld_plugin_allow_section_ordering tv_allow_section_ordering;
+    ld_plugin_allow_unique_segment_for_sections tv_allow_unique_segment_for_sections; 
+    ld_plugin_unique_segment_for_sections tv_unique_segment_for_sections;
+  } tv_u;
+};
+
+/* The plugin library's "onload" entry point.  */
+
+typedef
+enum ld_plugin_status
+(*ld_plugin_onload) (struct ld_plugin_tv *tv);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(PLUGIN_API_H) */
diff --git a/binutils-2.25/include/progress.h b/binutils-2.25/include/progress.h
new file mode 100644
index 00000000..80ffbe24
--- /dev/null
+++ b/binutils-2.25/include/progress.h
@@ -0,0 +1,38 @@
+/* Default definitions for progress macros.
+   Copyright 1994, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+/* The default definitions below are intended to be replaced by real
+   definitions, if building the tools for an interactive programming
+   environment.  */
+
+#ifndef _PROGRESS_H
+#define _PROGRESS_H
+
+#ifndef START_PROGRESS
+#define START_PROGRESS(STR,N)
+#endif
+
+#ifndef PROGRESS
+#define PROGRESS(X)
+#endif
+
+#ifndef END_PROGRESS
+#define END_PROGRESS(STR)
+#endif
+
+#endif /* _PROGRESS_H */
diff --git a/binutils-2.25/include/safe-ctype.h b/binutils-2.25/include/safe-ctype.h
new file mode 100644
index 00000000..0266bf1a
--- /dev/null
+++ b/binutils-2.25/include/safe-ctype.h
@@ -0,0 +1,150 @@
+/* <ctype.h> replacement macros.
+
+   Copyright (C) 2000, 2001 Free Software Foundation, Inc.
+   Contributed by Zack Weinberg <zackw@stanford.edu>.
+
+This file is part of the libiberty library.
+Libiberty is free software; you can redistribute it and/or
+modify it under the terms of the GNU Library General Public
+License as published by the Free Software Foundation; either
+version 2 of the License, or (at your option) any later version.
+
+Libiberty is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+Library General Public License for more details.
+
+You should have received a copy of the GNU Library General Public
+License along with libiberty; see the file COPYING.LIB.  If
+not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+/* This is a compatible replacement of the standard C library's <ctype.h>
+   with the following properties:
+
+   - Implements all isxxx() macros required by C99.
+   - Also implements some character classes useful when
+     parsing C-like languages.
+   - Does not change behavior depending on the current locale.
+   - Behaves properly for all values in the range of a signed or
+     unsigned char.
+
+   To avoid conflicts, this header defines the isxxx functions in upper
+   case, e.g. ISALPHA not isalpha.  */
+
+#ifndef SAFE_CTYPE_H
+#define SAFE_CTYPE_H
+
+/* Determine host character set.  */
+#define HOST_CHARSET_UNKNOWN 0
+#define HOST_CHARSET_ASCII   1
+#define HOST_CHARSET_EBCDIC  2
+
+#if  '\n' == 0x0A && ' ' == 0x20 && '0' == 0x30 \
+   && 'A' == 0x41 && 'a' == 0x61 && '!' == 0x21
+#  define HOST_CHARSET HOST_CHARSET_ASCII
+#else
+# if '\n' == 0x15 && ' ' == 0x40 && '0' == 0xF0 \
+   && 'A' == 0xC1 && 'a' == 0x81 && '!' == 0x5A
+#  define HOST_CHARSET HOST_CHARSET_EBCDIC
+# else
+#  define HOST_CHARSET HOST_CHARSET_UNKNOWN
+# endif
+#endif
+
+/* Categories.  */
+
+enum {
+  /* In C99 */
+  _sch_isblank  = 0x0001,	/* space \t */
+  _sch_iscntrl  = 0x0002,	/* nonprinting characters */
+  _sch_isdigit  = 0x0004,	/* 0-9 */
+  _sch_islower  = 0x0008,	/* a-z */
+  _sch_isprint  = 0x0010,	/* any printing character including ' ' */
+  _sch_ispunct  = 0x0020,	/* all punctuation */
+  _sch_isspace  = 0x0040,	/* space \t \n \r \f \v */
+  _sch_isupper  = 0x0080,	/* A-Z */
+  _sch_isxdigit = 0x0100,	/* 0-9A-Fa-f */
+
+  /* Extra categories useful to cpplib.  */
+  _sch_isidst	= 0x0200,	/* A-Za-z_ */
+  _sch_isvsp    = 0x0400,	/* \n \r */
+  _sch_isnvsp   = 0x0800,	/* space \t \f \v \0 */
+
+  /* Combinations of the above.  */
+  _sch_isalpha  = _sch_isupper|_sch_islower,	/* A-Za-z */
+  _sch_isalnum  = _sch_isalpha|_sch_isdigit,	/* A-Za-z0-9 */
+  _sch_isidnum  = _sch_isidst|_sch_isdigit,	/* A-Za-z0-9_ */
+  _sch_isgraph  = _sch_isalnum|_sch_ispunct,	/* isprint and not space */
+  _sch_iscppsp  = _sch_isvsp|_sch_isnvsp,	/* isspace + \0 */
+  _sch_isbasic  = _sch_isprint|_sch_iscppsp     /* basic charset of ISO C
+						   (plus ` and @)  */
+};
+
+/* Character classification.  */
+extern const unsigned short _sch_istable[256];
+
+#define _sch_test(c, bit) (_sch_istable[(c) & 0xff] & (unsigned short)(bit))
+
+#define ISALPHA(c)  _sch_test(c, _sch_isalpha)
+#define ISALNUM(c)  _sch_test(c, _sch_isalnum)
+#define ISBLANK(c)  _sch_test(c, _sch_isblank)
+#define ISCNTRL(c)  _sch_test(c, _sch_iscntrl)
+#define ISDIGIT(c)  _sch_test(c, _sch_isdigit)
+#define ISGRAPH(c)  _sch_test(c, _sch_isgraph)
+#define ISLOWER(c)  _sch_test(c, _sch_islower)
+#define ISPRINT(c)  _sch_test(c, _sch_isprint)
+#define ISPUNCT(c)  _sch_test(c, _sch_ispunct)
+#define ISSPACE(c)  _sch_test(c, _sch_isspace)
+#define ISUPPER(c)  _sch_test(c, _sch_isupper)
+#define ISXDIGIT(c) _sch_test(c, _sch_isxdigit)
+
+#define ISIDNUM(c)	_sch_test(c, _sch_isidnum)
+#define ISIDST(c)	_sch_test(c, _sch_isidst)
+#define IS_ISOBASIC(c)	_sch_test(c, _sch_isbasic)
+#define IS_VSPACE(c)	_sch_test(c, _sch_isvsp)
+#define IS_NVSPACE(c)	_sch_test(c, _sch_isnvsp)
+#define IS_SPACE_OR_NUL(c)	_sch_test(c, _sch_iscppsp)
+
+/* Character transformation.  */
+extern const unsigned char  _sch_toupper[256];
+extern const unsigned char  _sch_tolower[256];
+#define TOUPPER(c) _sch_toupper[(c) & 0xff]
+#define TOLOWER(c) _sch_tolower[(c) & 0xff]
+
+/* Prevent the users of safe-ctype.h from accidently using the routines
+   from ctype.h.  Initially, the approach was to produce an error when
+   detecting that ctype.h has been included.  But this was causing
+   trouble as ctype.h might get indirectly included as a result of
+   including another system header (for instance gnulib's stdint.h).
+   So we include ctype.h here and then immediately redefine its macros.  */
+
+#include <ctype.h>
+#undef isalpha
+#define isalpha(c) do_not_use_isalpha_with_safe_ctype
+#undef isalnum
+#define isalnum(c) do_not_use_isalnum_with_safe_ctype
+#undef iscntrl
+#define iscntrl(c) do_not_use_iscntrl_with_safe_ctype
+#undef isdigit
+#define isdigit(c) do_not_use_isdigit_with_safe_ctype
+#undef isgraph
+#define isgraph(c) do_not_use_isgraph_with_safe_ctype
+#undef islower
+#define islower(c) do_not_use_islower_with_safe_ctype
+#undef isprint
+#define isprint(c) do_not_use_isprint_with_safe_ctype
+#undef ispunct
+#define ispunct(c) do_not_use_ispunct_with_safe_ctype
+#undef isspace
+#define isspace(c) do_not_use_isspace_with_safe_ctype
+#undef isupper
+#define isupper(c) do_not_use_isupper_with_safe_ctype
+#undef isxdigit
+#define isxdigit(c) do_not_use_isxdigit_with_safe_ctype
+#undef toupper
+#define toupper(c) do_not_use_toupper_with_safe_ctype
+#undef tolower
+#define tolower(c) do_not_use_tolower_with_safe_ctype
+
+#endif /* SAFE_CTYPE_H */
diff --git a/binutils-2.25/include/sha1.h b/binutils-2.25/include/sha1.h
new file mode 100644
index 00000000..4da5c37f
--- /dev/null
+++ b/binutils-2.25/include/sha1.h
@@ -0,0 +1,146 @@
+/* Declarations of functions and data types used for SHA1 sum
+   library functions.
+   Copyright (C) 2000, 2001, 2003, 2005, 2006, 2008, 2010
+   Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 3, or (at your option) any
+   later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef SHA1_H
+# define SHA1_H 1
+
+#include <stdio.h>
+
+#if defined HAVE_LIMITS_H || _LIBC
+# include <limits.h>
+#endif
+
+#include "ansidecl.h"
+
+/* The following contortions are an attempt to use the C preprocessor
+   to determine an unsigned integral type that is 32 bits wide.  An
+   alternative approach is to use autoconf's AC_CHECK_SIZEOF macro, but
+   doing that would require that the configure script compile and *run*
+   the resulting executable.  Locally running cross-compiled executables
+   is usually not possible.  */
+
+#ifdef _LIBC
+# include <sys/types.h>
+typedef u_int32_t sha1_uint32;
+typedef uintptr_t sha1_uintptr;
+#elif defined (HAVE_SYS_TYPES_H) && defined (HAVE_STDINT_H)
+#include <stdint.h>
+#include <sys/types.h>
+typedef uint32_t sha1_uint32;
+typedef uintptr_t sha1_uintptr;
+#else
+#  define INT_MAX_32_BITS 2147483647
+
+/* If UINT_MAX isn't defined, assume it's a 32-bit type.
+   This should be valid for all systems GNU cares about because
+   that doesn't include 16-bit systems, and only modern systems
+   (that certainly have <limits.h>) have 64+-bit integral types.  */
+
+# ifndef INT_MAX
+#  define INT_MAX INT_MAX_32_BITS
+# endif
+
+# if INT_MAX == INT_MAX_32_BITS
+   typedef unsigned int sha1_uint32;
+# else
+#  if SHRT_MAX == INT_MAX_32_BITS
+    typedef unsigned short sha1_uint32;
+#  else
+#   if LONG_MAX == INT_MAX_32_BITS
+     typedef unsigned long sha1_uint32;
+#   else
+     /* The following line is intended to evoke an error.
+        Using #error is not portable enough.  */
+     "Cannot determine unsigned 32-bit data type."
+#   endif
+#  endif
+# endif
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Structure to save state of computation between the single steps.  */
+struct sha1_ctx
+{
+  sha1_uint32 A;
+  sha1_uint32 B;
+  sha1_uint32 C;
+  sha1_uint32 D;
+  sha1_uint32 E;
+
+  sha1_uint32 total[2];
+  sha1_uint32 buflen;
+  sha1_uint32 buffer[32];
+};
+
+
+/* Initialize structure containing state of computation. */
+extern void sha1_init_ctx (struct sha1_ctx *ctx);
+
+/* Starting with the result of former calls of this function (or the
+   initialization function update the context for the next LEN bytes
+   starting at BUFFER.
+   It is necessary that LEN is a multiple of 64!!! */
+extern void sha1_process_block (const void *buffer, size_t len,
+				struct sha1_ctx *ctx);
+
+/* Starting with the result of former calls of this function (or the
+   initialization function update the context for the next LEN bytes
+   starting at BUFFER.
+   It is NOT required that LEN is a multiple of 64.  */
+extern void sha1_process_bytes (const void *buffer, size_t len,
+				struct sha1_ctx *ctx);
+
+/* Process the remaining bytes in the buffer and put result from CTX
+   in first 20 bytes following RESBUF.  The result is always in little
+   endian byte order, so that a byte-wise output yields to the wanted
+   ASCII representation of the message digest.
+
+   IMPORTANT: On some systems it is required that RESBUF be correctly
+   aligned for a 32 bits value.  */
+extern void *sha1_finish_ctx (struct sha1_ctx *ctx, void *resbuf);
+
+
+/* Put result from CTX in first 20 bytes following RESBUF.  The result is
+   always in little endian byte order, so that a byte-wise output yields
+   to the wanted ASCII representation of the message digest.
+
+   IMPORTANT: On some systems it is required that RESBUF is correctly
+   aligned for a 32 bits value.  */
+extern void *sha1_read_ctx (const struct sha1_ctx *ctx, void *resbuf);
+
+
+/* Compute SHA1 message digest for bytes read from STREAM.  The
+   resulting message digest number will be written into the 20 bytes
+   beginning at RESBLOCK.  */
+extern int sha1_stream (FILE *stream, void *resblock);
+
+/* Compute SHA1 message digest for LEN bytes beginning at BUFFER.  The
+   result is always in little endian byte order, so that a byte-wise
+   output yields to the wanted ASCII representation of the message
+   digest.  */
+extern void *sha1_buffer (const char *buffer, size_t len, void *resblock);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/binutils-2.25/include/simple-object.h b/binutils-2.25/include/simple-object.h
new file mode 100644
index 00000000..c4786757
--- /dev/null
+++ b/binutils-2.25/include/simple-object.h
@@ -0,0 +1,204 @@
+/* simple-object.h -- simple routines to read and write object files
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Ian Lance Taylor, Google.
+
+This program is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, 51 Franklin Street - Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+#ifndef SIMPLE_OBJECT_H
+#define SIMPLE_OBJECT_H
+
+#include <stddef.h>
+#include <sys/types.h>
+
+#ifdef HAVE_UNISTD_H
+#include <unistd.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* This header file provides four types with associated functions.
+   They are used to read and write object files.  This is a minimal
+   interface, intended to support the needs of gcc without bringing in
+   all the power and complexity of BFD.  */
+
+/* The type simple_object_read * is used to read an existing object
+   file.  */
+
+typedef struct simple_object_read_struct simple_object_read;
+
+/* Create an simple_object_read given DESCRIPTOR, an open file
+   descriptor, and OFFSET, an offset within the file.  The offset is
+   for use with archives, and should be 0 for an ordinary object file.
+   The descriptor must remain open until done with the returned
+   simple_object_read.  SEGMENT_NAME is used on Mach-O and is required
+   on that platform: it means to only look at sections within the
+   segment with that name.  It is ignored for other object file
+   formats.  On error, this function returns NULL, and sets *ERRMSG to
+   an error string and sets *ERR to an errno value or 0 if there is no
+   relevant errno.  */
+
+extern simple_object_read *
+simple_object_start_read (int descriptor, off_t offset,
+			  const char *segment_name, const char **errmsg,
+			  int *err);
+
+/* Call PFN for each section in SIMPLE_OBJECT, passing it the section
+   name, offset within the file of the section contents, and length of
+   the section contents.  The offset within the file is relative to
+   the offset passed to simple_object_start_read.  The DATA argument
+   to simple_object_find_sections is passed on to PFN.  If PFN returns
+   0, the loop is stopped and simple_object_find_sections returns.  If
+   PFN returns non-zero, the loop continues.  On success this returns
+   NULL.  On error it returns an error string, and sets *ERR to an
+   errno value or 0 if there is no relevant errno.  */
+
+extern const char *
+simple_object_find_sections (simple_object_read *simple_object,
+			     int (*pfn) (void *data, const char *,
+					 off_t offset, off_t length),
+			     void *data,
+			     int *err);
+
+/* Look for the section NAME in SIMPLE_OBJECT.  This returns
+   information for the first section NAME in SIMPLE_OBJECT.  Note that
+   calling this multiple times is inefficient; use
+   simple_object_find_sections instead.
+
+   If found, return 1 and set *OFFSET to the offset in the file of the
+   section contents and set *LENGTH to the length of the section
+   contents.  *OFFSET will be relative to the offset passed to
+   simple_object_start_read.
+
+   If the section is not found, and no error occurs, return 0 and set
+   *ERRMSG to NULL.
+
+   If an error occurs, return 0, set *ERRMSG to an error message, and
+   set *ERR to an errno value or 0 if there is no relevant errno.  */
+
+extern int
+simple_object_find_section (simple_object_read *simple_object,
+			    const char *name, off_t *offset, off_t *length,
+			    const char **errmsg, int *err);
+
+/* Release all resources associated with SIMPLE_OBJECT.  This does not
+   close the file descriptor.  */
+
+extern void
+simple_object_release_read (simple_object_read *);
+
+/* The type simple_object_attributes holds the attributes of an object
+   file that matter for creating a file or ensuring that two files are
+   compatible.  This is a set of magic numbers.  */
+
+typedef struct simple_object_attributes_struct simple_object_attributes;
+
+/* Fetch the attributes of SIMPLE_OBJECT.  This information will
+   persist until simple_object_attributes_release is called, even if
+   SIMPLE_OBJECT is closed.  On error this returns NULL, sets *ERRMSG
+   to an error message, and sets *ERR to an errno value or 0 if there
+   isn't one.  */
+
+extern simple_object_attributes *
+simple_object_fetch_attributes (simple_object_read *simple_object,
+				const char **errmsg, int *err);
+
+/* Merge the FROM attributes into TO.  If two objects with these
+   attributes could be linked together without error, returns NULL.
+   Otherwise, returns an error message, and sets *ERR to an errno
+   value or 0 if there isn't one.  */
+
+extern const char *
+simple_object_attributes_merge (simple_object_attributes *to,
+				simple_object_attributes *from,
+				int *err);
+
+/* Release all resources associated with ATTRS.  */
+
+extern void
+simple_object_release_attributes (simple_object_attributes *attrs);
+
+/* The type simple_object_write is used to create a new object file.  */
+
+typedef struct simple_object_write_struct simple_object_write;
+
+/* Start creating a new object file which is like ATTRS.  You must
+   fetch attribute information from an existing object file before you
+   can create a new one.  There is currently no support for creating
+   an object file de novo.  The segment name is only used on Mach-O,
+   where it is required.  It means that all sections are created
+   within that segment.  It is ignored for other object file formats.
+   On error this function returns NULL, sets *ERRMSG to an error
+   message, and sets *ERR to an errno value or 0 if there isn't
+   one.  */
+
+extern simple_object_write *
+simple_object_start_write (simple_object_attributes *attrs,
+			   const char *segment_name,
+			   const char **errmsg, int *err);
+
+/* The type simple_object_write_section is a handle for a section
+   which is being written.  */
+
+typedef struct simple_object_write_section_struct simple_object_write_section;
+
+/* Add a section to SIMPLE_OBJECT.  NAME is the name of the new
+   section.  ALIGN is the required alignment expressed as the number
+   of required low-order 0 bits (e.g., 2 for alignment to a 32-bit
+   boundary).  The section is created as containing data, readable,
+   not writable, not executable, not loaded at runtime.  On error this
+   returns NULL, sets *ERRMSG to an error message, and sets *ERR to an
+   errno value or 0 if there isn't one.  */
+
+extern simple_object_write_section *
+simple_object_write_create_section (simple_object_write *simple_object,
+				    const char *name, unsigned int align,
+				    const char **errmsg, int *err);
+
+/* Add data BUFFER/SIZE to SECTION in SIMPLE_OBJECT.  If COPY is
+   non-zero, the data will be copied into memory if necessary.  If
+   COPY is zero, BUFFER must persist until SIMPLE_OBJECT is released.
+   On success this returns NULL.  On error this returns an error
+   message, and sets *ERR to an errno value or 0 if there isn't
+   one.  */
+
+extern const char *
+simple_object_write_add_data (simple_object_write *simple_object,
+			      simple_object_write_section *section,
+			      const void *buffer, size_t size,
+			      int copy, int *err);
+
+/* Write the complete object file to DESCRIPTOR, an open file
+   descriptor.  This returns NULL on success.  On error this returns
+   an error message, and sets *ERR to an errno value or 0 if there
+   isn't one.  */
+
+extern const char *
+simple_object_write_to_file (simple_object_write *simple_object,
+			     int descriptor, int *err);
+
+/* Release all resources associated with SIMPLE_OBJECT, including any
+   simple_object_write_section's that may have been created.  */
+
+extern void
+simple_object_release_write (simple_object_write *);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/binutils-2.25/include/som/ChangeLog b/binutils-2.25/include/som/ChangeLog
new file mode 100644
index 00000000..e1f1ec59
--- /dev/null
+++ b/binutils-2.25/include/som/ChangeLog
@@ -0,0 +1,20 @@
+2010-06-10  Tristan Gingold  <gingold@adacore.com>
+
+	* aout.h: New file.
+	* clock.h: Likewise.
+	* lst.h: Likewise.
+	* reloc.h: Likewise.
+	* internal.h: Likewise.
+
+Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.25/include/som/aout.h b/binutils-2.25/include/som/aout.h
new file mode 100644
index 00000000..c3845edf
--- /dev/null
+++ b/binutils-2.25/include/som/aout.h
@@ -0,0 +1,249 @@
+/* SOM a.out definitions for BFD.
+   Copyright 2010  Free Software Foundation, Inc.
+   Contributed by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _SOM_AOUT_H
+#define _SOM_AOUT_H
+
+#include "clock.h"
+
+/* Note: SOM uses bit-field in its structure.  All you need to know is:
+   - CPUs supported by SOM (hppa) are big-endian,
+   - the MSB is numbered 0.  */
+
+struct som_external_header
+{
+  unsigned char system_id[2];
+  unsigned char a_magic[2];
+  unsigned char version_id[4];
+  struct som_external_clock file_time;
+  unsigned char entry_space[4];
+  unsigned char entry_subspace[4];
+  unsigned char entry_offset[4];
+  unsigned char aux_header_location[4];
+  unsigned char aux_header_size[4];
+  unsigned char som_length[4];
+  unsigned char presumed_dp[4];
+  unsigned char space_location[4];
+  unsigned char space_total[4];
+  unsigned char subspace_location[4];
+  unsigned char subspace_total[4];
+  unsigned char loader_fixup_location[4];
+  unsigned char loader_fixup_total[4];
+  unsigned char space_strings_location[4];
+  unsigned char space_strings_size[4];
+  unsigned char init_array_location[4];
+  unsigned char init_array_total[4];
+  unsigned char compiler_location[4];
+  unsigned char compiler_total[4];
+  unsigned char symbol_location[4];
+  unsigned char symbol_total[4];
+  unsigned char fixup_request_location[4];
+  unsigned char fixup_request_total[4];
+  unsigned char symbol_strings_location[4];
+  unsigned char symbol_strings_size[4];
+  unsigned char unloadable_sp_location[4];
+  unsigned char unloadable_sp_size[4];
+  unsigned char checksum[4];
+};
+
+#define OLD_VERSION_ID 85082112
+#define NEW_VERSION_ID 87102412
+
+#define EXECLIBMAGIC	0x0104
+#define RELOC_MAGIC	0x0106
+#define EXEC_MAGIC	0x0107
+#define SHARE_MAGIC	0x0108
+#define SHMEM_MAGIC	0x0109
+#define DEMAND_MAGIC	0x010b
+#define DL_MAGIC	0x010d
+#define SHL_MAGIC	0x010e
+
+struct som_external_aux_id
+{
+  unsigned char flags[4];
+  unsigned char length[4];
+};
+
+/* Aux id types.  */
+#define VERSION_AUX_ID 6
+#define COPYRIGHT_AUX_ID 9
+
+/* Aux id flags.  */
+#define SOM_AUX_ID_MANDATORY	(1 << 31)
+#define SOM_AUX_ID_COPY		(1 << 30)
+#define SOM_AUX_ID_APPEND	(1 << 29)
+#define SOM_AUX_ID_IGNORE	(1 << 28)
+#define SOM_AUX_ID_TYPE_SH	0
+#define SOM_AUX_ID_TYPE_MASK	0xffff
+
+struct som_external_string_auxhdr
+{
+  struct som_external_aux_id header_id;
+
+  /* Length of the string, without the NUL.  */
+  unsigned char string_length[4];
+
+  /* The string.  */
+};
+
+struct som_external_exec_auxhdr
+{
+  struct som_external_aux_id som_auxhdr;
+
+  unsigned char exec_tsize[4];
+  unsigned char exec_tmem[4];
+  unsigned char exec_tfile[4];
+  unsigned char exec_dsize[4];
+  unsigned char exec_dmem[4];
+  unsigned char exec_dfile[4];
+  unsigned char exec_bsize[4];
+  unsigned char exec_entry[4];
+  unsigned char exec_flags[4];
+  unsigned char exec_bfill[4];
+};
+
+#define AUX_HDR_SIZE sizeof (struct som_external_exec_auxhdr)
+
+struct som_external_space_dictionary_record
+{
+  unsigned char name[4];
+  unsigned char flags[4];
+  unsigned char space_number[4];
+  unsigned char subspace_index[4];
+  unsigned char subspace_quantity[4];
+  unsigned char loader_fix_index[4];
+  unsigned char loader_fix_quantity[4];
+  unsigned char init_pointer_index[4];
+  unsigned char init_pointer_quantity[4];
+};
+
+#define SOM_SPACE_IS_LOADABLE		(1 << 31)
+#define SOM_SPACE_IS_DEFINED		(1 << 30)
+#define SOM_SPACE_IS_PRIVATE		(1 << 29)
+#define SOM_SPACE_HAS_INTERMEDIATE_CODE (1 << 28)
+#define SOM_SPACE_IS_TSPECIFIC		(1 << 27)
+#define SOM_SPACE_SORT_KEY_SH		8
+#define SOM_SPACE_SORT_KEY_MASK		0xff
+
+struct som_external_subspace_dictionary_record
+{
+  unsigned char space_index[4];
+  unsigned char flags[4];
+  unsigned char file_loc_init_value[4];
+  unsigned char initialization_length[4];
+  unsigned char subspace_start[4];
+  unsigned char subspace_length[4];
+  unsigned char alignment[4];
+  unsigned char name[4];
+  unsigned char fixup_request_index[4];
+  unsigned char fixup_request_quantity[4];
+};
+
+#define SOM_SUBSPACE_ACCESS_CONTROL_BITS_SH	25
+#define SOM_SUBSPACE_ACCESS_CONTROL_BITS_MASK	0x7f
+#define SOM_SUBSPACE_MEMORY_RESIDENT		(1 << 24)
+#define SOM_SUBSPACE_DUP_COMMON			(1 << 23)
+#define SOM_SUBSPACE_IS_COMMON			(1 << 22)
+#define SOM_SUBSPACE_IS_LOADABLE		(1 << 21)
+#define SOM_SUBSPACE_QUADRANT_SH		19
+#define SOM_SUBSPACE_QUADRANT_MASK		0x3
+#define SOM_SUBSPACE_INITIALLY_FROZEN		(1 << 18)
+#define SOM_SUBSPACE_IS_FIRST			(1 << 17)
+#define SOM_SUBSPACE_CODE_ONLY			(1 << 16)
+#define SOM_SUBSPACE_SORT_KEY_SH		8
+#define SOM_SUBSPACE_SORT_KEY_MASK		0xff
+#define SOM_SUBSPACE_REPLICATE_INIT		(1 << 7)
+#define SOM_SUBSPACE_CONTINUATION		(1 << 6)
+#define SOM_SUBSPACE_IS_TSPECIFIC		(1 << 5)
+#define SOM_SUBSPACE_IS_COMDAT			(1 << 4)
+
+struct som_external_compilation_unit
+{
+  unsigned char name[4];
+  unsigned char language_name[4];
+  unsigned char product_id[4];
+  unsigned char version_id[4];
+  unsigned char flags[4];
+  struct som_external_clock compile_time;
+  struct som_external_clock source_time;
+};
+
+struct som_external_symbol_dictionary_record
+{
+  unsigned char flags[4];
+  unsigned char name[4];
+  unsigned char qualifier_name[4];
+  unsigned char info[4];
+  unsigned char symbol_value[4];
+};
+
+/* Flags fields.  */
+#define SOM_SYMBOL_HIDDEN (1 << 31)
+#define SOM_SYMBOL_SECONDARY_DEF (1 << 30)
+#define SOM_SYMBOL_TYPE_SH 24
+#define SOM_SYMBOL_TYPE_MASK 0x3f
+#define SOM_SYMBOL_SCOPE_SH 20
+#define SOM_SYMBOL_SCOPE_MASK 0xf
+#define SOM_SYMBOL_CHECK_LEVEL_SH 17
+#define SOM_SYMBOL_CHECK_LEVEL_MASK 0x7
+#define SOM_SYMBOL_MUST_QUALIFY (1 << 16)
+#define SOM_SYMBOL_INITIALLY_FROZEN (1 << 15)
+#define SOM_SYMBOL_MEMORY_RESIDENT (1 << 14)
+#define SOM_SYMBOL_IS_COMMON (1 << 13)
+#define SOM_SYMBOL_DUP_COMMON (1 << 12)
+#define SOM_SYMBOL_XLEAST_SH 10
+#define SOM_SYMBOL_XLEAT_MASK 0x3
+#define SOM_SYMBOL_ARG_RELOC_SH 0
+#define SOM_SYMBOL_ARG_RELOC_MASK 0x3ff
+
+/* Info fields.  */
+#define SOM_SYMBOL_HAS_LONG_RETURN (1 << 31)
+#define SOM_SYMBOL_NO_RELOCATION (1 << 30)
+#define SOM_SYMBOL_IS_COMDAT (1 << 29)
+#define SOM_SYMBOL_SYMBOL_INFO_SH 0
+#define SOM_SYMBOL_SYMBOL_INFO_MASK 0xffffff
+
+/* Symbol type definition.  */
+#define ST_NULL		0
+#define ST_ABSOLUTE	1
+#define ST_DATA		2
+#define ST_CODE		3
+#define ST_PRI_PROG	4
+#define ST_SEC_PROG	5
+#define ST_ENTRY	6
+#define ST_STORAGE	7
+#define ST_STUB		8
+#define ST_MODULE	9
+#define ST_SYM_EXT	10
+#define ST_ARG_EXT	11
+#define ST_MILLICODE	12
+#define ST_PLABEL	13
+#define ST_OCT_DIS	14
+#define ST_MILLI_EXT	15
+#define ST_TSTORAGE	16
+#define ST_COMDAT	17
+
+/* Symbol scope.  */
+#define SS_UNSAT	0
+#define SS_EXTERNAL	1
+#define SS_LOCAL	2
+#define SS_UNIVERSAL	3
+
+#endif /* _SOM_AOUT_H */
diff --git a/binutils-2.25/include/som/clock.h b/binutils-2.25/include/som/clock.h
new file mode 100644
index 00000000..e2a7ba6d
--- /dev/null
+++ b/binutils-2.25/include/som/clock.h
@@ -0,0 +1,30 @@
+/* SOM clock definition for BFD.
+   Copyright 2010  Free Software Foundation, Inc.
+   Contributed by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _SOM_CLOCK_H
+#define _SOM_CLOCK_H
+
+struct som_external_clock
+{
+  unsigned char secs[4];
+  unsigned char nanosecs[4];
+};
+
+#endif /* _SOM_CLOCK_H */
diff --git a/binutils-2.25/include/som/internal.h b/binutils-2.25/include/som/internal.h
new file mode 100644
index 00000000..e3889fb5
--- /dev/null
+++ b/binutils-2.25/include/som/internal.h
@@ -0,0 +1,206 @@
+/* SOM internal definitions for BFD.
+   Copyright 2010  Free Software Foundation, Inc.
+   Contributed by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _SOM_INTERNAL_H
+#define _SOM_INTERNAL_H
+
+struct som_clock
+{
+  unsigned int secs;
+  unsigned int nanosecs;
+};
+
+struct som_header
+{
+  unsigned short system_id;
+  unsigned short a_magic;
+  unsigned int version_id;
+  struct som_clock file_time;
+  unsigned int entry_space;
+  unsigned int entry_subspace;
+  unsigned int entry_offset;
+  unsigned int aux_header_location;
+  unsigned int aux_header_size;
+  unsigned int som_length;
+  unsigned int presumed_dp;
+  unsigned int space_location;
+  unsigned int space_total;
+  unsigned int subspace_location;
+  unsigned int subspace_total;
+  unsigned int loader_fixup_location;
+  unsigned int loader_fixup_total;
+  unsigned int space_strings_location;
+  unsigned int space_strings_size;
+  unsigned int init_array_location;
+  unsigned int init_array_total;
+  unsigned int compiler_location;
+  unsigned int compiler_total;
+  unsigned int symbol_location;
+  unsigned int symbol_total;
+  unsigned int fixup_request_location;
+  unsigned int fixup_request_total;
+  unsigned int symbol_strings_location;
+  unsigned int symbol_strings_size;
+  unsigned int unloadable_sp_location;
+  unsigned int unloadable_sp_size;
+  unsigned int checksum;
+};
+
+struct som_aux_id
+{
+  unsigned int mandatory : 1;
+  unsigned int copy : 1;
+  unsigned int append : 1;
+  unsigned int ignore : 1;
+  unsigned int reserved : 12;
+
+  /* Header type.  */
+  unsigned int type : 16;
+
+  /* Length of the header in bytes, without the two word identifier.  */
+  unsigned int length;
+};
+
+/* Generic auxiliary string header.  */
+struct som_string_auxhdr
+{
+  struct som_aux_id header_id;
+
+  /* Length of the string, without the NUL.  */
+  unsigned int string_length;
+
+  /* The string.  */
+  char string[1];
+};
+
+struct som_name_pt
+{
+  char *name;
+  unsigned int strx;
+};
+
+struct som_compilation_unit
+{
+  /* Source file that produced the SOM.  */
+  struct som_name_pt name;
+
+  /* Name of the language used when creating this SOM.  */
+  struct som_name_pt language_name;
+
+  /* Identificaton of the compiler.  */
+  struct som_name_pt product_id;
+
+  /* Version id of the compiler.  */
+  struct som_name_pt version_id;
+
+  unsigned int flags;
+  struct som_clock compile_time;
+  struct som_clock source_time;
+};
+
+struct som_exec_auxhdr
+{
+  struct som_aux_id som_auxhdr;
+
+  long exec_tsize;
+  long exec_tmem;
+  long exec_tfile;
+  long exec_dsize;
+  long exec_dmem;
+  long exec_dfile;
+  long exec_bsize;
+  long exec_entry;
+  long exec_flags;
+  long exec_bfill;
+};
+
+struct som_space_dictionary_record
+{
+  unsigned int name;
+  unsigned int is_loadable : 1;
+  unsigned int is_defined : 1;
+  unsigned int is_private : 1;
+  unsigned int has_intermediate_code : 1;
+  unsigned int is_tspecific : 1;
+  unsigned int reserved : 11;
+  unsigned int sort_key : 8;
+  unsigned int reserved2 : 8;
+  int space_number;
+  int subspace_index;
+  unsigned int subspace_quantity;
+  int loader_fix_index;
+  unsigned int loader_fix_quantity;
+  int init_pointer_index;
+  unsigned int init_pointer_quantity;
+};
+
+struct som_subspace_dictionary_record
+{
+  int space_index;
+  unsigned int access_control_bits : 7;
+  unsigned int memory_resident : 1;
+  unsigned int dup_common : 1;
+  unsigned int is_common : 1;
+  unsigned int is_loadable : 1;
+  unsigned int quadrant : 2;
+  unsigned int initially_frozen : 1;
+  unsigned int is_first : 1;
+  unsigned int code_only : 1;
+  unsigned int sort_key : 8;
+  unsigned int replicate_init : 1;
+  unsigned int continuation : 1;
+  unsigned int is_tspecific : 1;
+  unsigned int is_comdat : 1;
+  unsigned int reserved : 4;
+  int file_loc_init_value;
+  unsigned int initialization_length;
+  unsigned int subspace_start;
+  unsigned int subspace_length;
+  unsigned int reserved2 : 5;
+  unsigned int alignment : 27;
+  unsigned int name;
+  int fixup_request_index;
+  unsigned int fixup_request_quantity;
+};
+
+struct som_lst_header
+{
+  unsigned short system_id;
+  unsigned short a_magic;
+  unsigned int version_id;
+  struct som_clock file_time;
+  unsigned int hash_loc;
+  unsigned int hash_size;
+  unsigned int module_count;
+  unsigned int module_limit;
+  unsigned int dir_loc;
+  unsigned int export_loc;
+  unsigned int export_count;
+  unsigned int import_loc;
+  unsigned int aux_loc;
+  unsigned int aux_size;
+  unsigned int string_loc;
+  unsigned int string_size;
+  unsigned int free_list;
+  unsigned int file_end;
+  unsigned int checksum;
+};
+
+#endif /* _SOM_INTERNAL_H */
diff --git a/binutils-2.25/include/som/lst.h b/binutils-2.25/include/som/lst.h
new file mode 100644
index 00000000..6088b47c
--- /dev/null
+++ b/binutils-2.25/include/som/lst.h
@@ -0,0 +1,93 @@
+/* SOM lst definitions for BFD.
+   Copyright 2010  Free Software Foundation, Inc.
+   Contributed by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _SOM_LST_H
+#define _SOM_LST_H
+
+#include "clock.h"
+
+/* See 4.2 Libraray Symbol Table Header Record.  */
+struct som_external_lst_header
+{
+  unsigned char system_id[2];
+  unsigned char a_magic[2];
+  unsigned char version_id[4];
+  struct som_external_clock file_time;
+  unsigned char hash_loc[4];
+  unsigned char hash_size[4];
+  unsigned char module_count[4];
+  unsigned char module_limit[4];
+  unsigned char dir_loc[4];
+  unsigned char export_loc[4];
+  unsigned char export_count[4];
+  unsigned char import_loc[4];
+  unsigned char aux_loc[4];
+  unsigned char aux_size[4];
+  unsigned char string_loc[4];
+  unsigned char string_size[4];
+  unsigned char free_list[4];
+  unsigned char file_end[4];
+  unsigned char checksum[4];
+};
+
+#define VERSION_ID 85082112
+#define LIBMAGIC 0x0619
+#define LIBMAGIC_EXEC 0x0104
+
+struct som_external_lst_symbol_record
+{
+  unsigned char flags[4];
+  unsigned char name[4];
+  unsigned char qualifier_name[4];
+  unsigned char symbol_info[4];
+  unsigned char symbol_value[4];
+  unsigned char symbol_descriptor[4];
+  unsigned char reserved;
+  unsigned char max_num_args;
+  unsigned char min_num_args;
+  unsigned char num_args;
+  unsigned char som_index[4];
+  unsigned char symbol_key[4];
+  unsigned char next_entry[4];
+};
+
+/* Fields of flags.  */
+#define LST_SYMBOL_HIDDEN		(1 << 31)
+#define LST_SYMBOL_SECONDARY_DEF	(1 << 30)
+#define LST_SYMBOL_SYMBOL_TYPE_SH	24
+#define LST_SYMBOL_SYMBOL_SCOPE_SH	20
+#define LST_SYMBOL_CHECK_LEVEL_SH	17
+#define LST_SYMBOL_MUST_QUALIFY		(1 << 16)
+#define LST_SYMBOL_INITIALY_FROZEN	(1 << 15)
+#define LST_SYMBOL_MEMORY_RESIDENT	(1 << 14)
+#define LST_SYMBOL_IS_COMMON		(1 << 13)
+#define LST_SYMBOL_DUP_COMMON		(1 << 12)
+#define LST_SYMBOL_XLEAST_SH		10
+#define LST_SYMBOL_ARG_RELOC_SH		0
+
+/* According to 4.3.2 SOM Directory.  */
+
+struct som_external_som_entry
+{
+  unsigned char location[4];
+  unsigned char length[4];
+};
+
+#endif /* _SOM_LST_H */
diff --git a/binutils-2.25/include/som/reloc.h b/binutils-2.25/include/som/reloc.h
new file mode 100644
index 00000000..417b5ee1
--- /dev/null
+++ b/binutils-2.25/include/som/reloc.h
@@ -0,0 +1,79 @@
+/* SOM relocation definitions for BFD.
+   Copyright 2010  Free Software Foundation, Inc.
+   Contributed by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef _SOM_RELOC_H
+#define _SOM_RELOC_H
+
+#define R_NO_RELOCATION		0
+#define R_ZEROES		0x20
+#define R_UNINIT		0x22
+#define R_RELOCATION		0x24
+#define R_DATA_ONE_SYMBOL	0x25
+#define R_DATA_PLABEL		0x27
+#define R_SPACE_REF		0x29
+#define R_REPEATED_INIT		0x2a
+#define R_PCREL_CALL		0x30
+#define R_SHORT_PCREL_MODE	0x3e
+#define R_LONG_PCREL_MODE	0x3f
+#define R_ABS_CALL		0x40
+#define R_DP_RELATIVE		0x50
+#define R_DATA_GPREL		0x72
+#define R_INDIRECT_CALL		0x76
+#define R_PLT_REL		0x77
+#define R_DLT_REL		0x78
+#define R_CODE_ONE_SYMBOL	0x80
+#define R_MILLI_REL		0xae
+#define R_CODE_PLABEL		0xb0
+#define R_BREAKPOINT		0xb2
+#define R_ENTRY			0xb3
+#define R_ALT_ENTRY		0xb5
+#define R_EXIT			0xb6
+#define R_BEGIN_TRY		0xb7
+#define R_END_TRY		0xb8
+#define R_BEGIN_BRTAB		0xbb
+#define R_END_BRTAB		0xbc
+#define R_STATEMENT		0xbd
+#define R_DATA_EXPR		0xc0
+#define R_CODE_EXPR		0xc1
+#define R_FSEL			0xc2
+#define R_LSEL			0xc3
+#define R_RSEL			0xc4
+#define R_N_MODE		0xc5
+#define R_S_MODE		0xc6
+#define R_D_MODE		0xc7
+#define R_R_MODE		0xc8
+#define R_DATA_OVERRIDE		0xc9
+#define R_TRANSLATED		0xce
+#define R_AUX_UNWIND		0xcf
+#define R_COMP1			0xd0
+#define R_COMP2			0xd1
+#define R_COMP3			0xd2
+#define R_PREV_FIXUP		0xd3
+#define R_SEC_STMT		0xd7
+#define R_N0SEL			0xd8
+#define R_N1SEL			0xd9
+#define R_LINETAB		0xda
+#define R_LINETAB_ESC		0xdb
+#define R_LTP_OVERRIDE		0xdc
+#define R_COMMENT		0xdd
+#define R_TP_OVERRIDE		0xde
+#define R_RESERVED		0xdf
+
+#endif /* _SOM_RELOC_H */
diff --git a/binutils-2.25/include/sort.h b/binutils-2.25/include/sort.h
new file mode 100644
index 00000000..582af816
--- /dev/null
+++ b/binutils-2.25/include/sort.h
@@ -0,0 +1,48 @@
+/* Sorting algorithms.
+   Copyright (C) 2000, 2002 Free Software Foundation, Inc.
+   Contributed by Mark Mitchell <mark@codesourcery.com>.
+
+This file is part of GCC.
+   
+GCC is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+#ifndef SORT_H
+#define SORT_H
+
+#include <sys/types.h> /* For size_t */
+#ifdef __STDC__
+#include <stddef.h>
+#endif	/* __STDC__ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "ansidecl.h"
+
+/* Sort an array of pointers.  */
+
+extern void sort_pointers (size_t, void **, void **);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SORT_H */
+
+
+   
+   
diff --git a/binutils-2.25/include/splay-tree.h b/binutils-2.25/include/splay-tree.h
new file mode 100644
index 00000000..a26135a0
--- /dev/null
+++ b/binutils-2.25/include/splay-tree.h
@@ -0,0 +1,161 @@
+/* A splay-tree datatype.  
+   Copyright 1998, 1999, 2000, 2002, 2005, 2007, 2009, 2010
+   Free Software Foundation, Inc.
+   Contributed by Mark Mitchell (mark@markmitchell.com).
+
+   This file is part of GCC.
+   
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+/* For an easily readable description of splay-trees, see:
+
+     Lewis, Harry R. and Denenberg, Larry.  Data Structures and Their
+     Algorithms.  Harper-Collins, Inc.  1991.  
+
+   The major feature of splay trees is that all basic tree operations
+   are amortized O(log n) time for a tree with n nodes.  */
+
+#ifndef _SPLAY_TREE_H
+#define _SPLAY_TREE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "ansidecl.h"
+
+#ifdef HAVE_STDINT_H
+#include <stdint.h>
+#endif
+#ifdef HAVE_INTTYPES_H
+#include <inttypes.h>
+#endif
+
+#ifndef GTY
+#define GTY(X)
+#endif
+
+/* Use typedefs for the key and data types to facilitate changing
+   these types, if necessary.  These types should be sufficiently wide
+   that any pointer or scalar can be cast to these types, and then
+   cast back, without loss of precision.  */
+typedef uintptr_t splay_tree_key;
+typedef uintptr_t splay_tree_value;
+
+/* Forward declaration for a node in the tree.  */
+typedef struct splay_tree_node_s *splay_tree_node;
+
+/* The type of a function which compares two splay-tree keys.  The
+   function should return values as for qsort.  */
+typedef int (*splay_tree_compare_fn) (splay_tree_key, splay_tree_key);
+
+/* The type of a function used to deallocate any resources associated
+   with the key.  */
+typedef void (*splay_tree_delete_key_fn) (splay_tree_key);
+
+/* The type of a function used to deallocate any resources associated
+   with the value.  */
+typedef void (*splay_tree_delete_value_fn) (splay_tree_value);
+
+/* The type of a function used to iterate over the tree.  */
+typedef int (*splay_tree_foreach_fn) (splay_tree_node, void*);
+
+/* The type of a function used to allocate memory for tree root and
+   node structures.  The first argument is the number of bytes needed;
+   the second is a data pointer the splay tree functions pass through
+   to the allocator.  This function must never return zero.  */
+typedef void *(*splay_tree_allocate_fn) (int, void *);
+
+/* The type of a function used to free memory allocated using the
+   corresponding splay_tree_allocate_fn.  The first argument is the
+   memory to be freed; the latter is a data pointer the splay tree
+   functions pass through to the freer.  */
+typedef void (*splay_tree_deallocate_fn) (void *, void *);
+
+/* The nodes in the splay tree.  */
+struct GTY(()) splay_tree_node_s {
+  /* The key.  */
+  splay_tree_key GTY ((use_param1)) key;
+
+  /* The value.  */
+  splay_tree_value GTY ((use_param2)) value;
+
+  /* The left and right children, respectively.  */
+  splay_tree_node GTY ((use_params)) left;
+  splay_tree_node GTY ((use_params)) right;
+};
+
+/* The splay tree itself.  */
+struct GTY(()) splay_tree_s {
+  /* The root of the tree.  */
+  splay_tree_node GTY ((use_params)) root;
+
+  /* The comparision function.  */
+  splay_tree_compare_fn comp;
+
+  /* The deallocate-key function.  NULL if no cleanup is necessary.  */
+  splay_tree_delete_key_fn delete_key;
+
+  /* The deallocate-value function.  NULL if no cleanup is necessary.  */
+  splay_tree_delete_value_fn delete_value;
+
+  /* Node allocate function.  Takes allocate_data as a parameter. */
+  splay_tree_allocate_fn allocate;
+
+  /* Free function for nodes and trees.  Takes allocate_data as a parameter.  */
+  splay_tree_deallocate_fn deallocate;
+
+  /* Parameter for allocate/free functions.  */
+  void * GTY((skip)) allocate_data;
+};
+
+typedef struct splay_tree_s *splay_tree;
+
+extern splay_tree splay_tree_new (splay_tree_compare_fn,
+				  splay_tree_delete_key_fn,
+				  splay_tree_delete_value_fn);
+extern splay_tree splay_tree_new_with_allocator (splay_tree_compare_fn,
+						 splay_tree_delete_key_fn,
+						 splay_tree_delete_value_fn,
+						 splay_tree_allocate_fn,
+						 splay_tree_deallocate_fn,
+						 void *);
+extern splay_tree splay_tree_new_typed_alloc (splay_tree_compare_fn,
+					      splay_tree_delete_key_fn,
+					      splay_tree_delete_value_fn,
+					      splay_tree_allocate_fn,
+					      splay_tree_allocate_fn,
+					      splay_tree_deallocate_fn,
+					      void *);
+extern void splay_tree_delete (splay_tree);
+extern splay_tree_node splay_tree_insert (splay_tree,
+					  splay_tree_key,
+					  splay_tree_value);
+extern void splay_tree_remove	(splay_tree, splay_tree_key);
+extern splay_tree_node splay_tree_lookup (splay_tree, splay_tree_key);
+extern splay_tree_node splay_tree_predecessor (splay_tree, splay_tree_key);
+extern splay_tree_node splay_tree_successor (splay_tree, splay_tree_key);
+extern splay_tree_node splay_tree_max (splay_tree);
+extern splay_tree_node splay_tree_min (splay_tree);
+extern int splay_tree_foreach (splay_tree, splay_tree_foreach_fn, void*);
+extern int splay_tree_compare_ints (splay_tree_key, splay_tree_key);
+extern int splay_tree_compare_pointers (splay_tree_key,	splay_tree_key);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SPLAY_TREE_H */
diff --git a/binutils-2.25/include/symcat.h b/binutils-2.25/include/symcat.h
new file mode 100644
index 00000000..b4612879
--- /dev/null
+++ b/binutils-2.25/include/symcat.h
@@ -0,0 +1,55 @@
+/* Symbol concatenation utilities.
+
+   Copyright (C) 1998, 2000, 2010 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+ 
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef SYM_CAT_H
+#define SYM_CAT_H
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define CONCAT2(a,b)	 a##b
+#define CONCAT3(a,b,c)	 a##b##c
+#define CONCAT4(a,b,c,d) a##b##c##d
+#define CONCAT5(a,b,c,d,e) a##b##c##d##e
+#define CONCAT6(a,b,c,d,e,f) a##b##c##d##e##f
+#define STRINGX(s) #s
+#else
+/* Note one should never pass extra whitespace to the CONCATn macros,
+   e.g. CONCAT2(foo, bar) because traditonal C will keep the space between
+   the two labels instead of concatenating them.  Instead, make sure to
+   write CONCAT2(foo,bar).  */
+#define CONCAT2(a,b)	 a/**/b
+#define CONCAT3(a,b,c)	 a/**/b/**/c
+#define CONCAT4(a,b,c,d) a/**/b/**/c/**/d
+#define CONCAT5(a,b,c,d,e) a/**/b/**/c/**/d/**/e
+#define CONCAT6(a,b,c,d,e,f) a/**/b/**/c/**/d/**/e/**/f
+#define STRINGX(s) "s"
+#endif
+
+#define XCONCAT2(a,b)     CONCAT2(a,b)
+#define XCONCAT3(a,b,c)   CONCAT3(a,b,c)
+#define XCONCAT4(a,b,c,d) CONCAT4(a,b,c,d)
+#define XCONCAT5(a,b,c,d,e) CONCAT5(a,b,c,d,e)
+#define XCONCAT6(a,b,c,d,e,f) CONCAT6(a,b,c,d,e,f)
+
+/* Note the layer of indirection here is typically used to allow
+   stringification of the expansion of macros.  I.e. "#define foo
+   bar", "XSTRING(foo)", to yield "bar".  Be aware that this only
+   works for __STDC__, not for traditional C which will still resolve
+   to "foo".  */
+#define XSTRING(s) STRINGX(s) 
+
+#endif /* SYM_CAT_H */
diff --git a/binutils-2.25/include/timeval-utils.h b/binutils-2.25/include/timeval-utils.h
new file mode 100644
index 00000000..1caf9b36
--- /dev/null
+++ b/binutils-2.25/include/timeval-utils.h
@@ -0,0 +1,40 @@
+/* Basic struct timeval utilities.
+   Copyright (C) 2011 Free Software Foundation, Inc.
+
+This file is part of the libiberty library.
+Libiberty is free software; you can redistribute it and/or
+modify it under the terms of the GNU Library General Public
+License as published by the Free Software Foundation; either
+version 2 of the License, or (at your option) any later version.
+
+Libiberty is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+Library General Public License for more details.
+
+You should have received a copy of the GNU Library General Public
+License along with libiberty; see the file COPYING.LIB.  If not,
+write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+#ifndef TIMEVAL_UTILS_H
+#define TIMEVAL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* forward decl */
+struct timeval;
+
+extern void timeval_add (struct timeval *result,
+			 const struct timeval *a, const struct timeval *b);
+
+extern void timeval_sub (struct timeval *result,
+			 const struct timeval *a, const struct timeval *b);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* TIMEVAL_UTILS_H */
diff --git a/binutils-2.25/include/vms/ChangeLog b/binutils-2.25/include/vms/ChangeLog
new file mode 100644
index 00000000..8d5e91d3
--- /dev/null
+++ b/binutils-2.25/include/vms/ChangeLog
@@ -0,0 +1,87 @@
+2012-03-08  Tristan Gingold  <gingold@adacore.com>
+
+	* lbr.h (struct vms_lhd): Add comments.
+
+2010-05-27  Tristan Gingold  <gingold@adacore.com>
+
+	* lbr.h: Improve comments.
+
+2010-05-17  Tristan Gingold  <gingold@adacore.com>
+
+	* eidc.h: New file.
+	* esgps.h: New file.
+
+2010-05-03  Tristan Gingold  <gingold@adacore.com>
+
+	* dmt.h: Improve comments.
+
+2010-04-30  Tristan Gingold  <gingold@adacore.com>
+
+	* lbr.h (struct vms_kbn): New structure.
+
+2010-04-30  Tristan Gingold  <gingold@adacore.com>
+
+	* lbr.h (LBR__C_TYP_ISHSTB): Added.
+	(LHD_SANEID4): Renamed to ...
+	(LHD_SANEID6): ...  this.
+	(LBR_MAJORID, LBR_ELFMAJORID): New macros.
+	(struct vms_rfa): New structure.
+	(struct vms_idxdef): Renamed to ...
+	(struct vms_idx): ... this.
+	(struct vms_idxdef2): Renamed to ...
+	(struct vms_elfidx): ... this.
+	(ELFIDX__WEAK, ELFIDX__GROUP, ELFIDX__LISTRFA, ELFIDX__SYMESC): New
+	macros.
+	(struct vms_lhs, struct vms_lns): New structures.
+	(struct vms_mhd): Add missing fields.
+	(MHD__C_MHDLEN): New macro.
+
+2010-03-31  Tristan Gingold  <gingold@adacore.com>
+
+	* dcx.h: New file.
+	* dsc.h: New file.
+	* esdfm.h: New file.
+	* esdfv.h: New file.
+	* internal.h: New file.
+	* lbr.h: New file.
+	* prt.h: New file.
+	* shl.h (struct vms_shl): Add comments.
+	* esrf.h (ESRF__B_NAMLNG): New macro.
+	* esdf.h (ESDF__B_NAMLNG): New macro.
+	* emh.h: Add macros for fields maximum value.
+	* eisd.h (EISD__M_PROTECT): Fix typo in comment.
+	Add macros for offsets, version, section type and match control.
+	Merge vms_eisd_ext into vms_eisd.
+	* eihvn.h (EIHVN__MULTI_PROCESSING_BIT, EIHVN__GALAXY_BIT): Added.
+	* eihs.h: Remove blank line.
+	* eihd.h (struct vms_eihd): Add comments, add image subtype names.
+	* eiha.h (struct vms_eiha): Add inishr and inishr_h fields.
+	* eiaf.h (struct vms_eiaf): Fix base_va size.
+	* egsy.h: Add comments.
+	* egsd.h: Remove blank line.
+	* egps.h: Add flag names.
+	* eeom.h (EEOM__M_WKTFR): Added.
+	* dst.h (DST__K_CXX): Added, and reident languages.
+	(DST__K_SRC_INCRLNUM_B): Added.
+	Indent and order pcline commands.
+	Add record begin/end, enumerations, type specification, value
+	specification, label, discontinue range definitions.
+
+2010-02-17  Tristan Gingold  <gingold@adacore.com>
+
+	* dmt.h, dst.h, eeom.h, egps.h, egsd.h, egst.h, egsy.h: New Files.
+	* eiaf.h, eicp.h, eiha.h, eihd.h, eihi.h, eihs.h, eihvn.h: Ditto.
+	* eisd.h, emh.h, eobjrec.h, esdf.h, esrf.h, etir.h, shl.h: Ditto.
+
+Copyright (C) 2010-2012 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.25/include/vms/dcx.h b/binutils-2.25/include/vms/dcx.h
new file mode 100644
index 00000000..b6f373ab
--- /dev/null
+++ b/binutils-2.25/include/vms/dcx.h
@@ -0,0 +1,50 @@
+/* Alpha VMS external format for DeCompression.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_DCX_H
+#define _VMS_DCX_H
+
+struct vms_dcxmap
+{
+  unsigned char size[4];
+  unsigned char version[2];
+
+  unsigned char pad[2];
+  unsigned char sanity[4];
+  unsigned char flags[4];
+  unsigned char nsubs[2];
+  unsigned char sub0[2];
+};
+
+struct vms_dcxsbm
+{
+  unsigned char size[2];
+  unsigned char min_char;
+  unsigned char max_char;
+  unsigned char escape;
+  unsigned char flags_bits;
+  unsigned char flags[2];
+  unsigned char nodes[2];
+  unsigned char next[2];
+};
+
+#endif /* _VMS_DCX_H */
diff --git a/binutils-2.25/include/vms/dmt.h b/binutils-2.25/include/vms/dmt.h
new file mode 100644
index 00000000..f2aad6e9
--- /dev/null
+++ b/binutils-2.25/include/vms/dmt.h
@@ -0,0 +1,48 @@
+/* Alpha VMS external format of Debug Module Table.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_DMT_H
+#define _VMS_DMT_H
+
+struct vms_dmt_header
+{
+  /* Offset in the DST of the module.  */
+  unsigned char modbeg[4];
+
+  /* Size of the DST chunk for this module.  */
+  unsigned char size[4];
+
+  /* Number of psect for this module.  */
+  unsigned char psect_count[2];
+
+  unsigned char mbz[2];
+};
+
+struct vms_dmt_psect
+{
+  /* Address of the psect.  */
+  unsigned char start[4];
+
+  /* Length of the psect.  */
+  unsigned char length[4];
+};
+#endif /* _VMS_DMT_H */
diff --git a/binutils-2.25/include/vms/dsc.h b/binutils-2.25/include/vms/dsc.h
new file mode 100644
index 00000000..5a1b0e23
--- /dev/null
+++ b/binutils-2.25/include/vms/dsc.h
@@ -0,0 +1,129 @@
+/* Alpha VMS external format of Descriptors.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_DSC_H
+#define _VMS_DSC_H
+
+/* Descriptors.  */
+#define DSC__K_DTYPE_Z	  0 /* Unspecified.  */
+#define DSC__K_DTYPE_V	  1 /* Bit.  */
+#define DSC__K_DTYPE_BU   2 /* Byte logical.  */
+#define DSC__K_DTYPE_WU   3 /* Word logical.  */
+#define DSC__K_DTYPE_LU   4 /* Longword logical.  */
+#define DSC__K_DTYPE_QU   5 /* Quadword logical.  */
+#define DSC__K_DTYPE_B    6 /* Byte integer.  */
+#define DSC__K_DTYPE_W    7 /* Word integer.  */
+#define DSC__K_DTYPE_L    8 /* Longword integer.  */
+#define DSC__K_DTYPE_Q    9 /* Quadword integer.  */
+#define DSC__K_DTYPE_F   10 /* Single-precision floating.  */
+#define DSC__K_DTYPE_D   11 /* Double-precision floating.  */
+#define DSC__K_DTYPE_FC  12 /* Complex.  */
+#define DSC__K_DTYPE_DC  13 /* Double-precision Complex.  */
+#define DSC__K_DTYPE_T   14 /* ASCII text string.  */
+#define DSC__K_DTYPE_NU  15 /* Numeric string, unsigned.  */
+#define DSC__K_DTYPE_NL  16 /* Numeric string, left separate sign.  */
+#define DSC__K_DTYPE_NLO 17 /* Numeric string, left overpunched sign.  */
+#define DSC__K_DTYPE_NR  18 /* Numeric string, right separate sign.  */
+#define DSC__K_DTYPE_NRO 19 /* Numeric string, right overpunched sign.  */
+#define DSC__K_DTYPE_NZ  20 /* Numeric string, zoned sign.  */
+#define DSC__K_DTYPE_P   21 /* Packed decimal string.  */
+#define DSC__K_DTYPE_ZI  22 /* Sequence of instructions.  */
+#define DSC__K_DTYPE_ZEM 23 /* Procedure entry mask.  */
+#define DSC__K_DTYPE_DSC 24 /* Descriptor, used for arrays of dyn strings.  */
+#define DSC__K_DTYPE_OU  25 /* Octaword logical.  */
+#define DSC__K_DTYPE_O   26 /* Octaword integer.  */
+#define DSC__K_DTYPE_G   27 /* Double precision G floating, 64 bit.  */
+#define DSC__K_DTYPE_H   28 /* Quadruple precision floating, 128 bit.  */
+#define DSC__K_DTYPE_GC  29 /* Double precision complex, G floating.  */
+#define DSC__K_DTYPE_HC  30 /* Quadruple precision complex, H floating.  */
+#define DSC__K_DTYPE_CIT 31 /* COBOL intermediate temporary.  */
+#define DSC__K_DTYPE_BPV 32 /* Bound Procedure Value.  */
+#define DSC__K_DTYPE_BLV 33 /* Bound Label Value.  */
+#define DSC__K_DTYPE_VU  34 /* Bit Unaligned.  */
+#define DSC__K_DTYPE_ADT 35 /* Absolute Date-Time.  */
+#define DSC__K_DTYPE_VT  37 /* Varying Text.  */
+#define DSC__K_DTYPE_T2  38 /* 16-bit char.  */
+#define DSC__K_DTYPE_VT2 39 /* 16-bit varying char.  */
+
+#define DSC__K_CLASS_S     1 /* Fixed-length scalar/string.  */
+#define DSC__K_CLASS_D     2 /* Dynamic string.  */
+#define DSC__K_CLASS_V     3 /* Reserved.  */
+#define DSC__K_CLASS_A     4 /* Contiguous array.  */
+#define DSC__K_CLASS_P     5 /* Procedure argument descriptor.  */
+#define DSC__K_CLASS_PI    6 /* Procedure incarnation descriptor.  */
+#define DSC__K_CLASS_J     7 /* Reserved.  */
+#define DSC__K_CLASS_JI    8 /* Obsolete.  */
+#define DSC__K_CLASS_SD    9 /* Decimal (scalar) string.  */
+#define DSC__K_CLASS_NCA  10 /* Non-contiguous array.  */
+#define DSC__K_CLASS_VS   11 /* Varying string.  */
+#define DSC__K_CLASS_VSA  12 /* Varying string array.  */
+#define DSC__K_CLASS_UBS  13 /* Unaligned bit string.  */
+#define DSC__K_CLASS_UBA  14 /* Unaligned bit array.  */
+#define DSC__K_CLASS_SB   15 /* String with bounds.  */
+#define DSC__K_CLASS_UBSB 16 /* Unaligned bit string with bounds.  */
+
+/* Common part.  */
+
+struct vms_dsc
+{
+  unsigned char length[2];
+  unsigned char dtype;
+  unsigned char bclass;
+  unsigned char pointer[4];
+};
+
+struct vms_dsc64
+{
+  unsigned char mbo[2];
+  unsigned char dtype;
+  unsigned char bclass;
+  unsigned char mbmo[4];
+  unsigned char length[8];
+  unsigned char pointer[8];
+};
+
+struct vms_dsc_nca
+{
+  unsigned char length[2];
+  unsigned char dtype;
+  unsigned char bclass;
+  unsigned char pointer[4];
+
+  unsigned char scale;
+  unsigned char digits;
+  unsigned char aflags;
+  unsigned char dimct;
+
+  unsigned char arsize[4];
+  unsigned char a0[4];
+};
+
+struct vms_dsc_ubs
+{
+  unsigned char length[2];
+  unsigned char dtype;
+  unsigned char bclass;
+  unsigned char base[4];
+  unsigned char pos[4];
+};
+
+#endif /* _VMS_DSC_H */
diff --git a/binutils-2.25/include/vms/dst.h b/binutils-2.25/include/vms/dst.h
new file mode 100644
index 00000000..231d3970
--- /dev/null
+++ b/binutils-2.25/include/vms/dst.h
@@ -0,0 +1,274 @@
+/* Alpha VMS external format of Debug Symbol Table.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_DST_H
+#define _VMS_DST_H
+
+/* Also available in vms freeware v5.0 debug/alpha_dstrecrds.sdl.  */
+
+struct vms_dst_header
+{
+  /* Length.  */
+  unsigned char length[2];
+
+  /* Type.  */
+  unsigned char type[2];
+};
+
+/* Beginning of module.  */
+#define DST__K_MODBEG 188
+
+/* Some well known languages.  */
+#define DST__K_MACRO	0
+#define DST__K_BLISS	2
+#define DST__K_C	7
+#define DST__K_ADA	9
+#define DST__K_CXX	15
+
+struct vms_dst_modbeg
+{
+  unsigned char flags;
+  unsigned char unused;
+  unsigned char language[4];
+  unsigned char major[2];
+  unsigned char minor[2];
+  /* Module name ASCIC.  */
+  /* Ident name ASCIC.  */
+};
+
+/* Routine begin.  */
+#define DST__K_RTNBEG 190
+
+struct vms_dst_rtnbeg
+{
+  unsigned char flags;
+
+  /* Address of the code.  */
+  unsigned char address[4];
+
+  /* Procedure descriptor address.  */
+  unsigned char pd_address[4];
+
+  /* Name: ASCIC  */
+};
+
+/* Line number.  */
+#define DST__K_LINE_NUM 185
+
+struct vms_dst_pcline
+{
+  unsigned char pcline_command;
+  unsigned char field[4];
+};
+
+#define DST__K_DELTA_PC_W	1
+#define DST__K_INCR_LINUM	2
+#define DST__K_INCR_LINUM_W	3
+#define DST__K_SET_LINUM_INCR	4
+#define DST__K_SET_LINUM_INCR_W	5
+#define DST__K_RESET_LINUM_INCR	6
+#define DST__K_BEG_STMT_MODE	7
+#define DST__K_END_STMT_MODE	8
+#define DST__K_SET_LINUM	9
+#define DST__K_SET_PC		10
+#define DST__K_SET_PC_W		11
+#define DST__K_SET_PC_L		12
+#define DST__K_SET_STMTNUM	13
+#define DST__K_TERM		14
+#define DST__K_TERM_W		15
+#define DST__K_SET_ABS_PC	16
+#define DST__K_DELTA_PC_L	17
+#define DST__K_INCR_LINUM_L	18
+#define DST__K_SET_LINUM_B	19
+#define DST__K_SET_LINUM_L	20
+#define DST__K_TERM_L		21
+
+/* Routine end.  */
+#define DST__K_RTNEND 191
+
+struct vms_dst_rtnend
+{
+  unsigned char unused;
+  unsigned char size[4];
+};
+
+/* Prologue.  */
+#define DST__K_PROLOG 162
+
+struct vms_dst_prolog
+{
+  unsigned char bkpt_addr[4];
+};
+
+/* Epilog.  */
+#define DST__K_EPILOG 127
+
+struct vms_dst_epilog
+{
+  unsigned char flags;
+  unsigned char count[4];
+};
+
+/* Module end.  */
+#define DST__K_MODEND 189
+
+/* Block begin.  */
+#define DST__K_BLKBEG 176
+
+struct vms_dst_blkbeg
+{
+  unsigned char unused;
+  unsigned char address[4];
+  /* Name ASCIC.  */
+};
+
+/* Block end.  */
+#define DST__K_BLKEND 177
+
+struct vms_dst_blkend
+{
+  unsigned char unused;
+  unsigned char size[4];
+};
+
+/* Source correlation.  */
+#define DST__K_SOURCE 155
+
+#define DST__K_SRC_DECLFILE    1
+#define DST__K_SRC_SETFILE     2
+#define DST__K_SRC_SETREC_L    3
+#define DST__K_SRC_SETREC_W    4
+#define DST__K_SRC_SETLNUM_L   5
+#define DST__K_SRC_SETLNUM_W   6
+#define DST__K_SRC_INCRLNUM_B  7
+#define DST__K_SRC_DEFLINES_W 10
+#define DST__K_SRC_DEFLINES_B 11
+#define DST__K_SRC_FORMFEED   16
+
+struct vms_dst_src_decl_src
+{
+  unsigned char length;
+  unsigned char flags;
+  unsigned char fileid[2];
+  unsigned char rms_cdt[8];
+  unsigned char rms_ebk[4];
+  unsigned char rms_ffb[2];
+  unsigned char rms_rfo;
+  /* Filename ASCIC.  */
+};
+
+/* Record begin.  */
+#define DST__K_RECBEG 171
+
+struct vms_dst_recbeg
+{
+  unsigned char vflags;
+  unsigned char value[4];
+  /* Filename ASCIC.  */
+};
+
+/* Record end.  */
+#define DST__K_RECEND 172
+
+/* Enumeration begin.  */
+#define DST__K_ENUMBEG 165
+
+/* Enumeration element.  */
+#define DST__K_ENUMELT 164
+
+/* Enumeration end.  */
+#define DST__K_ENUMEND 166
+
+/* Separate type specification.  */
+#define DST__K_SEPTYP 163
+
+/* Type specification.  */
+#define DST__K_TYPSPEC 175
+
+#define DST__K_TS_ATOM          1	/* Atomic.  */
+#define DST__K_TS_DSC           2	/* VMS Standard descriptor.  */
+#define DST__K_TS_IND           3	/* Indirect.  */
+#define DST__K_TS_TPTR          4	/* Typed pointer.  */
+#define DST__K_TS_PTR           5	/* Pointer.  */
+#define DST__K_TS_PIC           6	/* Pictured.  */
+#define DST__K_TS_ARRAY         7
+#define DST__K_TS_SET           8
+#define DST__K_TS_SUBRANGE      9	/* Subrange.  */
+#define DST__K_TS_ADA_DSC      10	/* Ada descriptor.  */
+#define DST__K_TS_FILE         11
+#define DST__K_TS_AREA         12	/* Area (PL/I).  */
+#define DST__K_TS_OFFSET       13	/* Offset (PL/I).  */
+#define DST__K_TS_NOV_LENG     14	/* Novel Length.  */
+#define DST__K_TS_IND_TSPEC    15	/* Internal to debugger.  */
+#define DST__K_TS_SELF_REL_LABEL 16	/* Self-relative label (PL/I).  */
+#define DST__K_TS_RFA          17	/* (Basic).  */
+#define DST__K_TS_TASK         18	/* (Ada).  */
+#define DST__K_TS_ADA_ARRAY    19
+#define DST__K_TS_XMOD_IND     20	/* Cross-module indirect type spec.  */
+#define DST__K_TS_CONSTRAINED  21	/* (Ada).  */
+#define DST__K_TS_MAYBE_CONSTR 22	/* Might-be-constrained (Ada).  */
+#define DST__K_TS_DYN_LOV_LENG 23
+#define DST__K_TS_TPTR_D       24	/* Typed pointer to descriptor.  */
+#define DST__K_TS_SCAN_TREE    25
+#define DST__K_TS_SCAN_TREEPTR 26
+#define DST__K_TS_INCOMPLETE   27
+#define DST__K_TS_BLISS_BLOCK  28
+#define DST__K_TS_TPTR_64      29
+#define DST__K_TS_PTR_64       30
+#define DST__K_TS_REF          31	/* C++ referenced type.  */
+#define DST__K_TS_REF_64       32
+
+/* Value Specification.  */
+#define DST__K_VFLAGS_NOVAL	128 /* No value.  */
+#define DST__K_VFLAGS_NOTACTIVE	248 /* Not active at current PC.  */
+#define DST__K_VFLAGS_UNALLOC	249 /* Not allocated.  */
+#define DST__K_VFLAGS_DSC	250 /* Descriptor format.  */
+#define DST__K_VFLAGS_TVS	251 /* Trailing value spec.  */
+#define DST__K_VS_FOLLOWS	253 /* Value specification follow.  */
+#define DST__K_VFLAGS_BITOFFS	255 /* Value is a bit offset.  */
+
+/* Vflags fields.  */
+#define DST__K_VALKIND_MASK 0x03
+#define DST__K_INDIR        0x04
+#define DST__K_DISP         0x08
+#define DST__K_REGNUM_MASK  0xf0
+#define DST__K_REGNUM_SHIFT  4
+
+#define DST__K_VALKIND_LITERAL 0
+#define DST__K_VALKIND_ADDR    1
+#define DST__K_VALKIND_DESC    2
+#define DST__K_VALKIND_REG     3
+
+/* Label.  */
+#define DST__K_LABEL 187
+
+struct vms_dst_label
+{
+  unsigned char unused;
+
+  unsigned char value[4];
+  unsigned char name[1];
+};
+
+/* Discontiguous range.  */
+#define DST__K_DIS_RANGE 118
+#endif /* _VMS_DST_H */
diff --git a/binutils-2.25/include/vms/eeom.h b/binutils-2.25/include/vms/eeom.h
new file mode 100644
index 00000000..807e4485
--- /dev/null
+++ b/binutils-2.25/include/vms/eeom.h
@@ -0,0 +1,62 @@
+/* Alpha VMS external format of Extended End Of Module.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EEOM_H
+#define _VMS_EEOM_H
+
+/* Completion flags.  */
+#define EEOM__C_SUCCESS 0
+#define EEOM__C_WARNING 1
+#define EEOM__C_ERROR   2
+#define EEOM__C_ABORT   3
+
+struct vms_eeom
+{
+  /* Record type.  */
+  unsigned char rectyp[2];
+
+  /* Record size.  */
+  unsigned char size[2];
+
+  /* Number of conditional linkage pairs.  */
+  unsigned char total_lps[4];
+
+  /* Completion code.  */
+  unsigned char comcod[2];
+
+
+  /* Transfer address flags.  */
+  unsigned char tfrflg;
+
+  /* Pad for alignment.  */
+  unsigned char temp;
+
+  /* Psect of transfer address.  */
+  unsigned char psindx[4];
+
+  /* Transfer address.  */
+  unsigned char tfradr[8];
+};
+
+#define EEOM__M_WKTFR (1 << 0)	/* Transfer address is weak.  */
+
+#endif /* _VMS_EEOM_H */
diff --git a/binutils-2.25/include/vms/egps.h b/binutils-2.25/include/vms/egps.h
new file mode 100644
index 00000000..e92df810
--- /dev/null
+++ b/binutils-2.25/include/vms/egps.h
@@ -0,0 +1,64 @@
+/* Alpha VMS external format of Extended Program Section Definition.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EGPS_H
+#define _VMS_EGPS_H
+
+struct vms_egps
+{
+  /* Entry type.  */
+  unsigned char gsdtyp[2];
+
+  /* Length of the entry.  */
+  unsigned char gsdsiz[2];
+
+  /* Psect alignment.  */
+  unsigned char align;
+
+  /* Pad for alignment.  */
+  unsigned char temp;
+
+  unsigned char flags[2];
+
+  /* Length of this contribution.  */
+  unsigned char alloc[4];
+
+  /* Name.  */
+  unsigned char namlng;
+  unsigned char name[31];
+};
+
+#define EGPS__V_PIC (1 << 0)	/* Not meaningful.  */
+#define EGPS__V_LIB (1 << 1)	/* Defined in a shareable image.  */
+#define EGPS__V_OVR (1 << 2)	/* Overlaid contribution.  */
+#define EGPS__V_REL (1 << 3)	/* Relocatable.  */
+#define EGPS__V_GBL (1 << 4)	/* Global.  */
+#define EGPS__V_SHR (1 << 5)	/* Shareable.  */
+#define EGPS__V_EXE (1 << 6)	/* Executable.  */
+#define EGPS__V_RD  (1 << 7)	/* Readable.  */
+#define EGPS__V_WRT (1 << 8)	/* Writable.  */
+#define EGPS__V_VEC (1 << 9)	/* Change mode dispatch or message vectors.  */
+#define EGPS__V_NOMOD (1 << 10)	/* Demand-zero.  */
+#define EGPS__V_COM (1 << 11)	/* Conditional storage.  */
+#define EGPS__V_ALLOC_64BIT (1 << 12)	/* Allocated in 64-bit space.  */
+
+#endif /* _VMS_EGPS_H */
diff --git a/binutils-2.25/include/vms/egsd.h b/binutils-2.25/include/vms/egsd.h
new file mode 100644
index 00000000..f9be3981
--- /dev/null
+++ b/binutils-2.25/include/vms/egsd.h
@@ -0,0 +1,60 @@
+/* Alpha VMS external format of Extended Global Symbol Directory.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EGSD_H
+#define _VMS_EGSD_H
+
+#define EGSD__K_ENTRIES 2	/* Offset to first entry in record.	*/
+#define EGSD__C_ENTRIES 2	/* Offset to first entry in record.	*/
+#define EGSD__C_PSC 0		/* Psect definition.			*/
+#define EGSD__C_SYM 1		/* Symbol specification.		*/
+#define EGSD__C_IDC 2		/* Random entity check.			*/
+#define EGSD__C_SPSC 5		/* Shareable image psect definition.	*/
+#define EGSD__C_SYMV 6		/* Vectored (dual-valued) versions of SYM.  */
+#define EGSD__C_SYMM 7		/* Masked versions of SYM.		*/
+#define EGSD__C_SYMG 8		/* EGST - gst version of SYM.		*/
+#define EGSD__C_MAXRECTYP 8	/* Maximum entry type defined.		*/
+
+struct vms_egsd
+{
+  /* Record type.  */
+  unsigned char rectyp[2];
+
+  /* Record size.  */
+  unsigned char recsiz[2];
+
+  /* Padding for alignment.  */
+  unsigned char alignlw[4];
+
+  /* Followed by egsd entries.  */
+};
+
+struct vms_egsd_entry
+{
+  /* Entry type.  */
+  unsigned char gsdtyp[2];
+
+  /* Length of the entry.  */
+  unsigned char gsdsiz[2];
+};
+
+#endif /* _VMS_EGSD_H */
diff --git a/binutils-2.25/include/vms/egst.h b/binutils-2.25/include/vms/egst.h
new file mode 100644
index 00000000..d4244842
--- /dev/null
+++ b/binutils-2.25/include/vms/egst.h
@@ -0,0 +1,39 @@
+/* Alpha VMS external format of Extended Global Symbol Definition.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EGST_H
+#define _VMS_EGST_H
+
+struct vms_egst
+{
+  struct vms_egsy header;
+
+  unsigned char value[8];
+  unsigned char lp_1[8];
+  unsigned char lp_2[8];
+
+  unsigned char psindx[4];
+  unsigned char namlng;
+  unsigned char name[31];
+};
+
+#endif /* _VMS_EGST_H */
diff --git a/binutils-2.25/include/vms/egsy.h b/binutils-2.25/include/vms/egsy.h
new file mode 100644
index 00000000..dd36ab21
--- /dev/null
+++ b/binutils-2.25/include/vms/egsy.h
@@ -0,0 +1,54 @@
+/* Alpha VMS external format of Extended Global Symbol.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EGSY_H
+#define _VMS_EGSY_H
+
+#define EGSY__W_FLAGS  6
+
+#define EGSY__V_WEAK		0x0001	/* Weak symbol definition.  */
+#define EGSY__V_DEF		0x0002	/* Symbol definition.  */
+#define EGSY__V_UNI		0x0004	/* Reserved.  */
+#define EGSY__V_REL		0x0008	/* Relocatable (vs absolute).  */
+#define EGSY__V_COMM		0x0010	/* Conditional symbol def.  */
+#define EGSY__V_VECEP		0x0020	/* Reserved.  */
+#define EGSY__V_NORM		0x0040	/* Normal procedure definition.  */
+#define EGSY__V_QUAD_VAL	0x0080	/* Value exceed 32 bits.  */
+
+struct vms_egsy
+{
+  /* Entry type.  */
+  unsigned char gsdtyp[2];
+
+  /* Length of the entry.  */
+  unsigned char gsdsiz[2];
+
+  /* Data type.  */
+  unsigned char datyp;
+
+  /* Pad for alignment.  */
+  unsigned char temp;
+
+  unsigned char flags[2];
+};
+
+#endif /* _VMS_EGSY_H */
diff --git a/binutils-2.25/include/vms/eiaf.h b/binutils-2.25/include/vms/eiaf.h
new file mode 100644
index 00000000..c3c39884
--- /dev/null
+++ b/binutils-2.25/include/vms/eiaf.h
@@ -0,0 +1,80 @@
+/* Alpha VMS external format of Extended Image Activator Fixup section.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EIAF_H
+#define _VMS_EIAF_H
+
+struct vms_eiaf
+{
+  /* Version.  */
+  unsigned char majorid[4];
+  unsigned char minorid[4];
+
+  /* Link for image activator use.  */
+  unsigned char iaflink[8];
+
+  /* Link for sharable image fixups.  */
+  unsigned char fixuplnk[8];
+
+  /* Size of EIAF fixed part.  */
+  unsigned char size[4];
+
+  /* Flags.  */
+  unsigned char flags[4];
+
+  /* Offsets to quadword and longword relocation fixup data.  */
+  unsigned char qrelfixoff[4];
+  unsigned char lrelfixoff[4];
+
+  /* Offsets to quardword and longword .address fixup data.  */
+  unsigned char qdotadroff[4];
+  unsigned char ldotadroff[4];
+
+  /* Offset to code address fixup data.  */
+  unsigned char codeadroff[4];
+
+  /* Offset to linkage part fixup data.  */
+  unsigned char lpfixoff[4];
+
+  /* Offset to isect change protection data.  */
+  unsigned char chgprtoff[4];
+
+  /* Offset to shareable image list.  */
+  unsigned char shlstoff[4];
+
+  /* Number of shareable images.  */
+  unsigned char shrimgcnt[4];
+
+  /* Number of extra shareable images allowed.  */
+  unsigned char shlextra[4];
+
+  /* Permanent shareable image context.  */
+  unsigned char permctx[4];
+
+  /* Base address of the image itself.  */
+  unsigned char base_va[4];
+
+  /* Offset to linkage pair with procedure signature fixups.  */
+  unsigned char lppsbfixoff[4];
+};
+
+#endif /* _VMS_EIAF_H */
diff --git a/binutils-2.25/include/vms/eicp.h b/binutils-2.25/include/vms/eicp.h
new file mode 100644
index 00000000..9c769f76
--- /dev/null
+++ b/binutils-2.25/include/vms/eicp.h
@@ -0,0 +1,38 @@
+/* Alpha VMS external format of Extended Image section Change Protection.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EICP_H
+#define _VMS_EICP_H
+
+struct vms_eicp
+{
+  /* Start of section.  */
+  unsigned char baseva[8];
+
+  /* Size in bytes of the image section.  */
+  unsigned char size[4];
+
+  /* New protections.  */
+  unsigned char newprt[4];
+};
+
+#endif /* _VMS_EICP_H */
diff --git a/binutils-2.25/include/vms/eidc.h b/binutils-2.25/include/vms/eidc.h
new file mode 100644
index 00000000..987e8c24
--- /dev/null
+++ b/binutils-2.25/include/vms/eidc.h
@@ -0,0 +1,49 @@
+/* Alpha VMS external format of Ident Consistency check.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EIDC_H
+#define _VMS_EIDC_H
+
+struct vms_eidc
+{
+  /* Record type.  */
+  unsigned char rectyp[2];
+
+  /* Record size.  */
+  unsigned char recsiz[2];
+
+  unsigned char flags[4];
+
+  /* Entity name (ASCIC).  */
+  /* Object name (ASCIC).  */
+  /* Ident string (ASCIC or binary BINIDENT set).  */
+  unsigned char name[1];
+};
+
+/* Fields of flags.  */
+#define EIDC__V_BINIDENT	(1 << 0)	/* Ident is a longword.  */
+#define EIDC__V_IDMATCH_SH	1		/* Ident match control.  */
+#define EIDC__V_IDMATCH_MASK	3
+#define EIDC__V_ERRSEV_SH	3		/* Error severity.  */
+#define EIDC__V_ERRSEV_MASK	7
+
+#endif /* _VMS_EIDC_H */
diff --git a/binutils-2.25/include/vms/eiha.h b/binutils-2.25/include/vms/eiha.h
new file mode 100644
index 00000000..5965ef97
--- /dev/null
+++ b/binutils-2.25/include/vms/eiha.h
@@ -0,0 +1,54 @@
+/* Alpha VMS external format of Extended Image Activation.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EIHA_H
+#define _VMS_EIHA_H
+
+struct vms_eiha
+{
+  /* Size of the struct.  */
+  unsigned char size[4];
+
+  unsigned char spare[4];
+
+  /* First transfer address.  */
+  unsigned char tfradr1[4];
+  unsigned char tfradr1_h[4];
+
+  /* Second.  */
+  unsigned char tfradr2[4];
+  unsigned char tfradr2_h[4];
+
+  /* Third.  */
+  unsigned char tfradr3[4];
+  unsigned char tfradr3_h[4];
+
+  /* Fourth (must be 0).  */
+  unsigned char tfradr4[4];
+  unsigned char tfradr4_h[4];
+
+  /* Shared image initialization (only if EIHD__V_INISHR is set).  */
+  unsigned char inishr[4];
+  unsigned char inishr_h[4];
+};
+
+#endif /* _VMS_EIHA_H */
diff --git a/binutils-2.25/include/vms/eihd.h b/binutils-2.25/include/vms/eihd.h
new file mode 100644
index 00000000..fdb3a6ec
--- /dev/null
+++ b/binutils-2.25/include/vms/eihd.h
@@ -0,0 +1,145 @@
+/* Alpha VMS external format of Extended Image Header.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EIHD_H
+#define _VMS_EIHD_H
+
+/* Extended Image Header (eihd) structure.  */
+struct vms_eihd
+{
+  /* Version of this EIHD.  */
+  unsigned char majorid[4];
+  unsigned char minorid[4];
+
+  /* Size in bytes of the header.  */
+  unsigned char size[4];
+
+  /* Byte offset to ISD (Image Section Descriptors) list.  */
+  unsigned char isdoff[4];
+
+  /* Byte offset to activation data (off=16).  */
+  unsigned char activoff[4];
+
+  /* Byte offset to symbol table and debugging data.  */ 
+  unsigned char symdbgoff[4];
+
+  /* Byte offset to image ident.  */
+  unsigned char imgidoff[4];
+
+  /* Byte offset to patch data.  */
+  unsigned char patchoff[4];
+
+  /* RVA of fixup info (off=32).  */
+  unsigned char iafva[8];
+
+  /* RVA of symbol vector.  */
+  unsigned char symvva[8];
+
+  /* Byte offset to version number array (off=48).  */
+  unsigned char version_array_off[4];
+
+  /* Image type.  */
+  unsigned char imgtype[4];
+
+  /* Image subtype.  */
+  unsigned char subtype[4];
+
+  /* Size in bytes of image I/O section requested.  */
+  unsigned char imgiocnt[4];
+
+  /* Nbr of channels requested (off=64).  */
+  unsigned char iochancnt[4];
+
+  /* Requested privilege mask.  */
+  unsigned char privreqs[8];
+
+  /* Number of header diskblocks.  */
+  unsigned char hdrblkcnt[4];
+
+  /* Linker produced image flags.  */
+  unsigned char lnkflags[4];
+
+  /* GBL SEC ident value for linkable image.  */
+  unsigned char ident[4];
+
+  /* SYS$K_VERSION or 0 if not linked with exec.  */
+  unsigned char sysver[4];
+
+  /* Linker match control.  */
+  unsigned char matchctl;
+  unsigned char fill_1[3];
+
+  /* Size of the symbol vector in bytes.  */
+  unsigned char symvect_size[4];
+
+  /* Value of /BPAGE.  */
+  unsigned char virt_mem_block_size[4];
+
+  /* Byte offset to extended fixup data.  */
+  unsigned char ext_fixup_off[4];
+
+  /* Byte offset to no_optimize psect table.  */
+  unsigned char noopt_psect_off[4];
+
+  unsigned char fill_2[398];
+
+  /* CODE identifies image type to MOM.  */
+  unsigned char alias[2];
+};
+
+#define EIHD__K_MAJORID	3	/* Major id constant	*/
+#define EIHD__K_MINORID	0	/* Minor id constant	*/
+
+/* Image type.  */
+#define EIHD__K_EXE		1	/* Executable image	*/
+#define EIHD__K_LIM		2	/* Linkable image.  */
+
+/* Image subtype.  */
+#define EIHD__C_NATIVE		0	/* Alpha native image.  */
+#define EIHD__C_CLI		1	/* Image is a CLI, run LOGINOUT.  */
+
+/* Linker image flags.  */
+#define EIHD__M_LNKDEBUG	0x0001	/* Full debugging requested.  */
+#define EIHD__M_LNKNOTFR	0x0002	/* No first transfer address.  */
+#define EIHD__M_NOP0BUFS	0x0004	/* No RMS use of P0 for image I/O.  */
+#define EIHD__M_PICIMG		0x0008	/* PIC image.  */
+#define EIHD__M_P0IMAGE		0x0010	/* P0 only image.  */
+#define EIHD__M_DBGDMT		0x0020	/* Image header has dmt fields.  */
+#define EIHD__M_INISHR		0x0040	/* Transfer array contains LNISHR.  */
+#define EIHD__M_XLATED		0x0080	/* Translated image.  */
+#define EIHD__M_BIND_CODE_SEC	0x0100	/* EXE sect can be put into S0.  */
+#define EIHD__M_BIND_DATA_SEC	0x0200	/* DATA sect can be put into S0.  */
+#define EIHD__M_MKTHREADS	0x0400	/* Multiple kernel threads.  */
+#define EIHD__M_UPCALLS		0x0800	/* Upcalls enabled.  */
+#define EIHD__M_OMV_READY	0x1000	/* Can be processed by OMV.  */
+#define EIHD__M_EXT_BIND_SECT	0x2000	/* May be moved, using ext fixups.  */
+
+/* Offsets of some fields.  */
+#define EIHD__L_SIZE		8
+#define EIHD__L_ISDOFF		12
+#define EIHD__L_SYMDBGOFF	20
+#define EIHD__Q_SYMVVA		40
+#define EIHD__L_IMGTYPE		52
+
+#define EIHD__C_LENGTH 104
+
+#endif /* _VMS_EIHD_H */
diff --git a/binutils-2.25/include/vms/eihi.h b/binutils-2.25/include/vms/eihi.h
new file mode 100644
index 00000000..97d3d895
--- /dev/null
+++ b/binutils-2.25/include/vms/eihi.h
@@ -0,0 +1,50 @@
+/* Alpha VMS external format of Extended Image Identification.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EIHI_H
+#define _VMS_EIHI_H
+
+#define EIHI__K_MAJORID 1
+#define EIHI__K_MINORID 2
+
+struct vms_eihi
+{
+  unsigned char majorid[4];
+  unsigned char minorid[4];
+
+  /* Time when this image was linked.  */
+  unsigned char linktime[8];
+
+  /* Image name.  */
+  unsigned char imgnam[40];
+
+  /* Image ident.  */
+  unsigned char imgid[16];
+
+  /* Linker ident.  */
+  unsigned char linkid[16];
+
+  /* Image build ident.  */
+  unsigned char imgbid[16];
+};
+
+#endif /* _VMS_EIHI_H */
diff --git a/binutils-2.25/include/vms/eihs.h b/binutils-2.25/include/vms/eihs.h
new file mode 100644
index 00000000..cf048b13
--- /dev/null
+++ b/binutils-2.25/include/vms/eihs.h
@@ -0,0 +1,62 @@
+/* Alpha VMS external format of Extended Image Symbols and debug table.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EIHS_H
+#define _VMS_EIHS_H
+
+#define EIHS__K_MAJORID 1
+#define EIHS__K_MINORID 1
+
+struct vms_eihs
+{
+  unsigned char majorid[4];
+  unsigned char minorid[4];
+
+  /* Debug symbol table virtual block number (vbn).  */
+  unsigned char dstvbn[4];
+
+  /* Debug symbol table size.  */
+  unsigned char dstsize[4];
+
+  /* Global symbol table vbn.  */
+  unsigned char gstvbn[4];
+
+  /* Global symtol table size.  */
+  unsigned char gstsize[4];
+
+  /* Debug module table vbn.  */
+  unsigned char dmtvbn[4];
+
+  /* Debug module table size.  */
+  unsigned char dmtsize[4];
+};
+
+/* Various offsets.  */
+
+#define EIHS__L_DSTVBN		 8
+#define EIHS__L_DSTSIZE		12
+#define EIHS__L_GSTVBN		16
+#define EIHS__L_GSTSIZE		20
+#define EIHS__L_DMTVBN		24
+#define EIHS__L_DMTBYTES	28
+
+#endif /* _VMS_EIHS_H */
diff --git a/binutils-2.25/include/vms/eihvn.h b/binutils-2.25/include/vms/eihvn.h
new file mode 100644
index 00000000..07f9eeed
--- /dev/null
+++ b/binutils-2.25/include/vms/eihvn.h
@@ -0,0 +1,58 @@
+/* Alpha VMS external format of Extended Image Header Version.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EIHVN_H
+#define _VMS_EIHVN_H
+
+struct vms_eihvn
+{
+  unsigned char subsystem_mask[4];
+};
+
+struct vms_eihvn_subversion
+{
+  unsigned char minor[2];
+  unsigned char major[2];
+};
+
+#define EIHVN__BASE_IMAGE_BIT		0
+#define EIHVN__MEMORY_MANAGEMENT_BIT	1
+#define EIHVN__IO_BIT			2
+#define EIHVN__FILES_VOLUMES_BIT	3
+#define EIHVN__PROCESS_SCHED_BIT	4
+#define EIHVN__SYSGEN_BIT		5
+#define EIHVN__CLUSTERS_LOCKMGR_BIT	6
+#define EIHVN__LOGICAL_NAMES_BIT	7
+#define EIHVN__SECURITY_BIT		8
+#define EIHVN__IMAGE_ACTIVATOR_BIT	9
+#define EIHVN__NETWORKS_BIT		10
+#define EIHVN__COUNTERS_BIT		11
+#define EIHVN__STABLE_BIT		12
+#define EIHVN__MISC_BIT			13
+#define EIHVN__CPU_BIT			14
+#define EIHVN__VOLATILE_BIT		15
+#define EIHVN__SHELL_BIT		16
+#define EIHVN__POSIX_BIT		17
+#define EIHVN__MULTI_PROCESSING_BIT	18
+#define EIHVN__GALAXY_BIT		19
+
+#endif /* _VMS_EIHVN_H */
diff --git a/binutils-2.25/include/vms/eisd.h b/binutils-2.25/include/vms/eisd.h
new file mode 100644
index 00000000..7579e72b
--- /dev/null
+++ b/binutils-2.25/include/vms/eisd.h
@@ -0,0 +1,118 @@
+/* Alpha VMS external format of Extended Image Section Descriptor.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EISD_H
+#define _VMS_EISD_H
+
+/* Flags.  */
+#define EISD__M_GBL		0x0001	/* Global.  */
+#define EISD__M_CRF		0x0002	/* Copy on reference.  */
+#define EISD__M_DZRO		0x0004	/* Demand zero page.  */
+#define EISD__M_WRT		0x0008	/* Writable.  */
+#define EISD__M_INITALCODE	0x0010	/* Part of initialization code.  */
+#define EISD__M_BASED		0x0020	/* Isect is based.  */
+#define EISD__M_FIXUPVEC	0x0040	/* Isect is fixup section.  */
+#define EISD__M_RESIDENT	0x0080	/* Isect is memory resident.  */
+#define EISD__M_VECTOR		0x0100	/* Vector contained in isect.  */
+#define EISD__M_PROTECT		0x0200	/* Isect is protected.  */
+#define EISD__M_LASTCLU		0x0400	/* Last cluster.  */
+#define EISD__M_EXE		0x0800	/* Code isect.  */
+#define EISD__M_NONSHRADR	0x1000	/* Contains non-shareable data.  */
+#define EISD__M_QUAD_LENGTH	0x2000	/* Quad length field valid.  */
+#define EISD__M_ALLOC_64BIT	0x4000	/* Allocate 64-bit space.  */
+
+#define EISD__K_LEN 36
+#define EISD__K_LENEND 12	/* For end marker or next block.  */
+#define EISD__K_MAXLENGLBL 84
+
+#define EISD__K_GBLNAMLEN 44	/* Size of the field.  */
+
+struct vms_eisd
+{
+  unsigned char majorid[4];
+  unsigned char minorid[4];
+
+  /* Size (in bytes) of this eisd.  */
+  unsigned char eisdsize[4];
+
+  /* Size (in bytes) of the section.  */
+  unsigned char secsize[4];
+
+  /* Virtual address of the section.  */
+  unsigned char virt_addr[8];
+
+  /* Flags.  */
+  unsigned char flags[4];
+
+  /* Base virtual block number.  */
+  unsigned char vbn[4];
+
+  /* Page fault cluster.  */
+  unsigned char pfc;
+
+  /* Linker match control.  */
+  unsigned char matchctl;
+
+  /* Section type.  */
+  unsigned char type;
+
+  unsigned char fill_1;
+
+  /* End of structure for normal records.  */
+
+  /* Ident for global section.  */
+  unsigned char ident[4];
+      
+  /* Global name ascic.  First 8 bytes are quad length field.  */
+  unsigned char gblnam[EISD__K_GBLNAMLEN];
+};
+
+/* Versions.  */
+#define EISD__K_MAJORID 1
+#define EISD__K_MINORID 1
+
+/* Match control.  */
+#define EISD__K_MATALL 0	/* Match always.  */
+#define EISD__K_MATEQU 1	/* Match if equal.  */
+#define EISD__K_MATLEQ 2	/* Match if less or equal.  */
+#define EISD__K_MATNEV 3	/* Match never.  */
+
+/* Section type.  */
+#define EISD__K_NORMAL 0	/* Normal program image section.  */
+#define EISD__K_SHRFXD 1	/* Shareable fixed section.  */
+#define EISD__K_PRVFXD 2	/* Private fixed section.  */
+#define EISD__K_SHRPIC 3	/* Shareable pic section.  */
+#define EISD__K_PRVPIC 4	/* Private PIC section.  */
+#define EISD__K_USRSTACK 253	/* User stack section.  */
+
+/* EISD offsets.  */
+
+#define EISD__L_EISDSIZE	 8
+#define EISD__L_SECSIZE		12
+#define EISD__Q_VIR_ADDR	16
+#define EISD__L_FLAGS		24
+#define EISD__L_VBN		28
+#define EISD__R_CONTROL		32
+#define EISD__L_IDENT		36
+#define EISD__T_GBLNAM		40
+
+#endif /* _VMS_EISD_H */
diff --git a/binutils-2.25/include/vms/emh.h b/binutils-2.25/include/vms/emh.h
new file mode 100644
index 00000000..973d71ea
--- /dev/null
+++ b/binutils-2.25/include/vms/emh.h
@@ -0,0 +1,79 @@
+/* Alpha VMS external format of Extended Module Header.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EMH_H
+#define _VMS_EMH_H
+
+#define EMH__C_MHD 0		/* Main header record.		*/
+#define EMH__C_LNM 1		/* Language name and version.	*/
+#define EMH__C_SRC 2		/* Source file specification.	*/
+#define EMH__C_TTL 3		/* Title text of module.	*/
+#define EMH__C_CPR 4		/* Copyright notice.		*/
+#define EMH__C_MTC 5		/* Maintenance status.		*/
+#define EMH__C_GTX 6		/* General text.		*/
+#define EMH__C_MAXHDRTYP 6	/* Maximum allowable type.	*/
+
+struct vms_emh_common
+{
+  /* Record type.  */
+  unsigned char rectyp[2];
+
+  /* Record size.  */
+  unsigned char size[2];
+
+  /* Subtype.  */
+  unsigned char subtyp[2];
+};
+
+struct vms_emh_mhd
+{
+  struct vms_emh_common common;
+
+  unsigned char strlvl;
+
+  unsigned char temp;
+
+  unsigned char arch1[4];
+  unsigned char arch2[4];
+
+  unsigned char recsiz[4];
+
+  /* Module name: ASCIC.  */
+  /* Module version: ASCIC.  */
+  /* Compile data: ASCIC.  */
+};
+
+#define EOBJ__C_MAXRECSIZ 8192  /* Maximum legal record size.  */
+#define EOBJ__C_STRLVL 2	/* Structure level.  */
+#define EOBJ__C_SYMSIZ 64	/* Maximum symbol length.  */
+#define EOBJ__C_SECSIZ 31	/* Maximum section name length.  */
+#define EOBJ__C_STOREPLIM -1	/* Maximum repeat count on store commands.  */
+#define EOBJ__C_PSCALILIM 16	/* Maximum p-sect alignment.  */
+
+struct vms_emh_lnm
+{
+  struct vms_emh_common common;
+
+  /* Language processor name: ASCII.  */
+};
+
+#endif /* _VMS_EMH_H */
diff --git a/binutils-2.25/include/vms/eobjrec.h b/binutils-2.25/include/vms/eobjrec.h
new file mode 100644
index 00000000..985fda78
--- /dev/null
+++ b/binutils-2.25/include/vms/eobjrec.h
@@ -0,0 +1,48 @@
+/* Alpha VMS external format of Extended Object Records.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_EOBJREC_H
+#define _VMS_EOBJREC_H
+
+#define EOBJ__C_EMH 8		/* EVAX mdule header record.  */
+#define EOBJ__C_EEOM 9		/* EVAX ed of module record.  */
+#define EOBJ__C_EGSD 10		/* EVAX gobal symbol definition record.  */
+#define EOBJ__C_ETIR 11		/* EVAX txt information record.  */
+#define EOBJ__C_EDBG 12		/* EVAX Dbugger information record.  */
+#define EOBJ__C_ETBT 13		/* EVAX Taceback information record.  */
+#define EOBJ__C_MAXRECTYP 13	/* EVAX Lst assigned record type.  */
+
+struct vms_eobjrec
+{
+  /* Record type.  */
+  unsigned char rectyp[2];
+
+  /* Record size.  */
+  unsigned char size[2];
+
+#if 0
+  /* Record subtype.  */
+  unsigned char subtyp[2];
+#endif
+};
+
+#endif /* _VMS_EOBJREC_H */
diff --git a/binutils-2.25/include/vms/esdf.h b/binutils-2.25/include/vms/esdf.h
new file mode 100644
index 00000000..79ee3d61
--- /dev/null
+++ b/binutils-2.25/include/vms/esdf.h
@@ -0,0 +1,41 @@
+/* Alpha VMS external format of Extended GSD Global Symbol Definition.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_ESDF_H
+#define _VMS_ESDF_H
+
+struct vms_esdf
+{
+  struct vms_egsy header;
+
+  unsigned char value[8];
+  unsigned char code_address[8];
+  unsigned char ca_psindx[4];
+
+  unsigned char psindx[4];
+  unsigned char namlng;
+  unsigned char name[31];
+};
+
+#define ESDF__B_NAMLNG		32
+
+#endif /* _VMS_ESDF_H */
diff --git a/binutils-2.25/include/vms/esdfm.h b/binutils-2.25/include/vms/esdfm.h
new file mode 100644
index 00000000..e00e44a1
--- /dev/null
+++ b/binutils-2.25/include/vms/esdfm.h
@@ -0,0 +1,49 @@
+/* Alpha VMS external format of Extended Symbol Definition for version Mask.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_ESDFM_H
+#define _VMS_ESDFM_H
+
+struct vms_esdfm
+{
+  /* Entry type.  */
+  unsigned char gsdtyp[2];
+
+  /* Length of the entry.  */
+  unsigned char size[2];
+
+  /* Data type.  */
+  unsigned char datyp;
+
+  /* Pad for alignment.  */
+  unsigned char temp;
+
+  unsigned char flags[2];
+
+  unsigned char value[8];
+  unsigned char psindx[4];
+  unsigned char version_mask[4];
+  unsigned char namlng;
+  unsigned char name[31];
+};
+
+#endif /* _VMS_ESDFM_H */
diff --git a/binutils-2.25/include/vms/esdfv.h b/binutils-2.25/include/vms/esdfv.h
new file mode 100644
index 00000000..fae0dbc1
--- /dev/null
+++ b/binutils-2.25/include/vms/esdfv.h
@@ -0,0 +1,49 @@
+/* Alpha VMS external format of Extended Symbol Def for Vectored symbols.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_ESDFV_H
+#define _VMS_ESDFV_H
+
+struct vms_esdfv
+{
+  /* Entry type.  */
+  unsigned char gsdtyp[2];
+
+  /* Length of the entry.  */
+  unsigned char size[2];
+
+  /* Data type.  */
+  unsigned char datyp;
+
+  /* Pad for alignment.  */
+  unsigned char temp;
+
+  unsigned char flags[2];
+
+  unsigned char value[8];
+  unsigned char psindx[4];
+  unsigned char vector[4];
+  unsigned char namlng;
+  unsigned char name[31];
+};
+
+#endif /* _VMS_ESDFV_H */
diff --git a/binutils-2.25/include/vms/esgps.h b/binutils-2.25/include/vms/esgps.h
new file mode 100644
index 00000000..e668a874
--- /dev/null
+++ b/binutils-2.25/include/vms/esgps.h
@@ -0,0 +1,72 @@
+/* Alpha VMS external format of Extended Shared Program Section Definition.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_ESGPS_H
+#define _VMS_ESGPS_H
+
+struct vms_esgps
+{
+  /* Entry type.  */
+  unsigned char gsdtyp[2];
+
+  /* Length of the entry.  */
+  unsigned char gsdsiz[2];
+
+  /* Psect alignment.  */
+  unsigned char align;
+
+  /* Pad for alignment.  */
+  unsigned char temp;
+
+  unsigned char flags[2];
+
+  /* Length of this contribution.  */
+  unsigned char alloc[4];
+
+  /* Image offset of the psect.  */
+  unsigned char base[4];
+
+  /* Symbol vector offset.  */
+  unsigned char value[8];
+
+  /* Name.  */
+  unsigned char namlng;
+  unsigned char name[31];
+};
+
+/* These are the same as EGPS flags.  */
+
+#define ESGPS__V_PIC (1 << 0)	/* Not meaningful.  */
+#define ESGPS__V_LIB (1 << 1)	/* Defined in a shareable image.  */
+#define ESGPS__V_OVR (1 << 2)	/* Overlaid contribution.  */
+#define ESGPS__V_REL (1 << 3)	/* Relocatable.  */
+#define ESGPS__V_GBL (1 << 4)	/* Global.  */
+#define ESGPS__V_SHR (1 << 5)	/* Shareable.  */
+#define ESGPS__V_EXE (1 << 6)	/* Executable.  */
+#define ESGPS__V_RD  (1 << 7)	/* Readable.  */
+#define ESGPS__V_WRT (1 << 8)	/* Writable.  */
+#define ESGPS__V_VEC (1 << 9)	/* Change mode dispatch or message vectors.  */
+#define ESGPS__V_NOMOD (1 << 10)	/* Demand-zero.  */
+#define ESGPS__V_COM (1 << 11)	/* Conditional storage.  */
+#define ESGPS__V_ALLOC_64BIT (1 << 12)	/* Allocated in 64-bit space.  */
+
+#endif /* _VMS_ESGPS_H */
diff --git a/binutils-2.25/include/vms/esrf.h b/binutils-2.25/include/vms/esrf.h
new file mode 100644
index 00000000..291250c9
--- /dev/null
+++ b/binutils-2.25/include/vms/esrf.h
@@ -0,0 +1,36 @@
+/* Alpha VMS external format of Extended GSD Global Symbol Reference.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_ESRF_H
+#define _VMS_ESRF_H
+
+struct vms_esrf
+{
+  struct vms_egsy header;
+
+  unsigned char namlng;
+  unsigned char name[31];
+};
+
+#define ESRF__B_NAMLNG   8
+
+#endif /* _VMS_ESRF_H */
diff --git a/binutils-2.25/include/vms/etir.h b/binutils-2.25/include/vms/etir.h
new file mode 100644
index 00000000..4d922dc3
--- /dev/null
+++ b/binutils-2.25/include/vms/etir.h
@@ -0,0 +1,114 @@
+/* Alpha VMS external format of Extended Text Information and Relocation.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_ETIR_H
+#define _VMS_ETIR_H
+
+#define ETIR__C_MINSTACOD 0	/* Minimum stack code.		*/
+#define ETIR__C_STA_GBL   0	/* Stack global symbol value.	*/
+#define ETIR__C_STA_LW    1	/* Stack longword.		*/
+#define ETIR__C_STA_QW    2	/* Stack quadword.		*/
+#define ETIR__C_STA_PQ    3	/* Stack psect base + quadword off.  */
+#define ETIR__C_STA_LI    4	/* Stack literal.		*/
+#define ETIR__C_STA_MOD   5	/* Stack module.		*/
+#define ETIR__C_STA_CKARG 6	/* Check Arguments.		*/
+#define ETIR__C_MAXSTACOD 6	/* Maximum stack code.		*/
+
+#define ETIR__C_MINSTOCOD  50	/* Minimum store code.		*/
+#define ETIR__C_STO_B      50	/* Store byte.			*/
+#define ETIR__C_STO_W      51	/* Store word.			*/
+#define ETIR__C_STO_LW     52	/* Store longword.		*/
+#define ETIR__C_STO_QW     53	/* Store quadword.		*/
+#define ETIR__C_STO_IMMR   54	/* Store immediate Repeated.	*/
+#define ETIR__C_STO_GBL    55	/* Store global.		*/
+#define ETIR__C_STO_CA     56	/* Store code address.		*/
+#define ETIR__C_STO_RB     57	/* Store relative branch.	*/
+#define ETIR__C_STO_AB     58	/* Store absolute branch.	*/
+#define ETIR__C_STO_OFF    59	/* Store offset within psect.	*/
+#define ETIR__C_STO_IMM    61	/* Store immediate.		*/
+#define ETIR__C_STO_GBL_LW 62	/* Store global Longword.	*/
+#define ETIR__C_STO_LP_PSB 63	/* STO_LP_PSB not valid in level 2 use STC_LP_PSB.  */
+#define ETIR__C_STO_HINT_GBL 64  /* Store 14 bit HINT at global address.  */
+#define ETIR__C_STO_HINT_PS  65  /* Store 14 bit HINT at psect + offset */
+#define ETIR__C_MAXSTOCOD    65  /* Maximum store code.		*/
+
+/* Operate codes.  */
+#define ETIR__C_MINOPRCOD 100	/* Minimum operate code.	*/
+#define ETIR__C_OPR_NOP   100	/* No-op.			*/
+#define ETIR__C_OPR_ADD   101	/* Add.				*/
+#define ETIR__C_OPR_SUB   102	/* Subtract.			*/
+#define ETIR__C_OPR_MUL   103	/* Multiply.			*/
+#define ETIR__C_OPR_DIV   104	/* Divide.			*/
+#define ETIR__C_OPR_AND   105	/* Logical AND.			*/
+#define ETIR__C_OPR_IOR   106	/* Logical inclusive OR.	*/
+#define ETIR__C_OPR_EOR   107	/* Logical exclusive OR.	*/
+#define ETIR__C_OPR_NEG   108	/* Negate.			*/
+#define ETIR__C_OPR_COM   109	/* Complement.			*/
+#define ETIR__C_OPR_INSV  110	/* Insert bit field.		*/
+#define ETIR__C_OPR_ASH   111	/* Arithmetic shift.		*/
+#define ETIR__C_OPR_USH   112	/* Unsigned shift.		*/
+#define ETIR__C_OPR_ROT   113	/* Rotate.			*/
+#define ETIR__C_OPR_SEL   114	/* Select one of 3 long on top of stack.   */
+#define ETIR__C_OPR_REDEF 115	/* Redefine this symbol after pass 2.  */
+#define ETIR__C_OPR_DFLIT 116	/* Define a literal.		*/
+#define ETIR__C_MAXOPRCOD 116	/* Maximum operate code.	*/
+
+/* Control codes.  */
+#define ETIR__C_MINCTLCOD 150	/* Minimum control code.	*/
+#define ETIR__C_CTL_SETRB 150	/* Set relocation base.		*/
+#define ETIR__C_CTL_AUGRB 151	/* Augment relocation base.	*/
+#define ETIR__C_CTL_DFLOC 152	/* Define debug location.	*/
+#define ETIR__C_CTL_STLOC 153	/* Set debug location.		*/
+#define ETIR__C_CTL_STKDL 154	/* Stack debug location.	*/
+#define ETIR__C_MAXCTLCOD 154	/* Maximum control code.	*/
+
+/* Store-conditional (STC) codes.  */
+#define ETIR__C_MINSTCCOD   200 /* Minimum store-conditional code.   */
+#define ETIR__C_STC_LP      200 /* STC Linkage Pair.   */
+#define ETIR__C_STC_LP_PSB  201 /* STC Linkage Pair with Proc Signature.  */
+#define ETIR__C_STC_GBL     202 /* STC Address at global address.  */
+#define ETIR__C_STC_GCA     203 /* STC Code Address at global address.  */
+#define ETIR__C_STC_PS      204 /* STC Address at psect + offset.  */
+#define ETIR__C_STC_NOP_GBL 205 /* STC NOP at address of global.  */
+#define ETIR__C_STC_NOP_PS  206 /* STC NOP at pect + offset.  */
+#define ETIR__C_STC_BSR_GBL 207 /* STC BSR at global address.  */
+#define ETIR__C_STC_BSR_PS  208 /* STC BSR at pect + offset.  */
+#define ETIR__C_STC_LDA_GBL 209 /* STC LDA at global address.  */
+#define ETIR__C_STC_LDA_PS  210 /* STC LDA at psect + offset.  */
+#define ETIR__C_STC_BOH_GBL 211 /* STC BSR or Hint at global address.  */
+#define ETIR__C_STC_BOH_PS  212 /* STC BSR or Hint at pect + offset.  */
+#define ETIR__C_STC_NBH_GBL 213 /* STC NOP,BSR or HINT at global address.  */
+#define ETIR__C_STC_NBH_PS  214 /* STC NOP,BSR or HINT at psect + offset.  */
+#define ETIR__C_MAXSTCCOD   214 /* Maximum store-conditional code.   */
+
+#define ETIR__C_HEADER_SIZE 4	/* Size of the header of a command */
+
+struct vms_etir
+{
+  /* Commands.  See above.  */
+  unsigned char rectyp[2];
+
+  /* Size (including this header).  */
+  unsigned char size[2];
+};
+
+#endif /* _VMS_ETIR_H */
diff --git a/binutils-2.25/include/vms/internal.h b/binutils-2.25/include/vms/internal.h
new file mode 100644
index 00000000..1c8c4724
--- /dev/null
+++ b/binutils-2.25/include/vms/internal.h
@@ -0,0 +1,63 @@
+/* Alpha VMS internal format.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_INTERNAL_H
+#define _VMS_INTERNAL_H
+
+struct vms_internal_eisd
+{
+  unsigned int majorid;		/* Version.  */
+  unsigned int minorid;
+  unsigned int eisdsize;	/* Size (in bytes) of this eisd.  */
+  unsigned int secsize;		/* Size (in bytes) of the section.  */
+  bfd_vma virt_addr;		/* Virtual address of the section.  */
+  unsigned int flags;		/* Flags.  */
+  unsigned int vbn;		/* Base virtual block number.  */
+  unsigned char pfc;		/* Page fault cluster.  */
+  unsigned char matchctl;	/* Linker match control.  */
+  unsigned char type;		/* Section type.  */
+};
+
+struct vms_internal_gbl_eisd
+{
+  struct vms_internal_eisd common;
+
+  unsigned int ident;		/* Ident for global section.  */
+  unsigned char gblnam[44];	/* Global name ascic.  */
+};
+
+struct vms_internal_eisd_map
+{
+  /* Next eisd in the list.  */
+  struct vms_internal_eisd_map *next;
+
+  /* Offset in output file.  */
+  file_ptr file_pos;
+
+  union
+  {
+    struct vms_internal_eisd eisd;
+    struct vms_internal_gbl_eisd gbl_eisd;
+  } u;
+};
+
+#endif /* _VMS_INTERNAL_H */
diff --git a/binutils-2.25/include/vms/lbr.h b/binutils-2.25/include/vms/lbr.h
new file mode 100644
index 00000000..fd3c256a
--- /dev/null
+++ b/binutils-2.25/include/vms/lbr.h
@@ -0,0 +1,332 @@
+/* Alpha VMS external format of Libraries.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_LBR_H
+#define _VMS_LBR_H
+
+/* Libray HeaDer.  */
+
+/* Magic numbers.  Should match the major version.  */
+
+#define LHD_SANEID_DCX 319232342
+#define LHD_SANEID3 233579905
+#define LHD_SANEID6 233579911
+
+/* Library type.  */
+#define LBR__C_TYP_UNK    0	/* Unknown / unspecified.  */
+#define LBR__C_TYP_OBJ    1	/* Vax object.  */
+#define LBR__C_TYP_MLB    2	/* Macro.  */
+#define LBR__C_TYP_HLP    3	/* Help.  */
+#define LBR__C_TYP_TXT    4	/* Text.  */
+#define LBR__C_TYP_SHSTB  5	/* Vax shareable image.  */
+#define LBR__C_TYP_NCS    6	/* NCS.  */
+#define LBR__C_TYP_EOBJ   7	/* Alpha object.  */
+#define LBR__C_TYP_ESHSTB 8	/* Alpha shareable image.  */
+#define LBR__C_TYP_IOBJ   9	/* IA-64 object.  */
+#define LBR__C_TYP_ISHSTB 10	/* IA-64 shareable image.  */
+
+struct vms_lhd
+{
+  /* Type of the library.  See above.  */
+  unsigned char type;
+
+  /* Number of indexes.  Generally 1, 2 for object libraries.  */
+  unsigned char nindex;
+
+  unsigned char fill_1[2];
+
+  /* Sanity Id.  */
+  unsigned char sanity[4];
+
+  /* Version.  */
+  unsigned char majorid[2];
+  unsigned char minorid[2];
+
+  /* Tool name.  */
+  unsigned char lbrver[32];
+
+  /* Create time.  */
+  unsigned char credat[8];
+
+  /* Update time.  */
+  unsigned char updtim[8];
+
+  /* Size of the MHD.  */
+  unsigned char mhdusz;
+
+  unsigned char idxblkf[2];	/* Unused.  */
+  unsigned char fill_2;
+  unsigned char closerror[2];
+
+  unsigned char spareword[2];
+
+  /* First free block, and number of free blocks.  */
+  unsigned char freevbn[4];
+  unsigned char freeblk[4];
+
+  unsigned char nextrfa[6];
+  unsigned char nextvbn[4];
+
+  /* Free pre-allocated index block.  */
+  /* Number of free blocks.  */
+  unsigned char freidxblk[4];
+  /* VBN of a simply linked list of free blocks.  The list is terminated by a
+     nul VBN.  */
+  unsigned char freeidx[4];
+
+  /* Highest pre-allocated index block and in use.  */
+  unsigned char hipreal[4];
+  unsigned char hiprusd[4];
+
+  /* Number of index blocks in use.  */
+  unsigned char idxblks[4];
+
+  /* Number of index entries.  */
+  unsigned char idxcnt[4];
+
+  /* Number of modules entries.  */
+  unsigned char modcnt[4];
+
+  unsigned char fill_3[2];
+
+  /* Number of module headers.  */
+  unsigned char modhdrs[4];
+
+  /* Overhead index pointers.  */
+  unsigned char idxovh[4];
+
+  /* Update history records.  */
+  unsigned char maxluhrec[2];
+  unsigned char numluhrec[2];
+  unsigned char begluhrfa[6];
+  unsigned char endluhrfa[6];
+
+  /* DCX map.  */
+  unsigned char dcxmapvbn[4];
+
+  unsigned char fill_4[4 * 13];
+};
+
+/* Known major ids.  */
+#define LBR_MAJORID 3		/* Alpha libraries.  */
+#define LBR_ELFMAJORID 6	/* Elf libraries (new index, new data).  */
+
+/* Offset of the first IDD.  */
+#define LHD_IDXDESC 196
+
+/* InDex Description.  */
+struct vms_idd
+{
+  unsigned char flags[2];
+
+  /* Max length of the key.  */
+  unsigned char keylen[2];
+
+  /* First index block.  */
+  unsigned char vbn[4];
+};
+
+/* IDD flags.  */
+#define IDD__FLAGS_ASCII 1
+#define IDD__FLAGS_LOCKED 2
+#define IDD__FLAGS_VARLENIDX 4
+#define IDD__FLAGS_NOCASECMP 8
+#define IDD__FLAGS_NOCASENTR 16
+#define IDD__FLAGS_UPCASNTRY 32
+
+#define IDD_LENGTH 8
+
+/* Index block.  */
+#define INDEXDEF__LENGTH 512
+#define INDEXDEF__BLKSIZ 500
+
+struct vms_indexdef
+{
+  /* Number of bytes used.  */
+  unsigned char used[2];
+
+  /* VBN of the parent.  */
+  unsigned char parent[4];
+
+  unsigned char fill_1[6];
+
+  /* The key field contains vms_idx/vms_elfidx structures, which are
+     simply a key (= a string) and a rfa.  */
+  unsigned char keys[INDEXDEF__BLKSIZ];
+};
+
+/* An offset in a file.  */
+
+struct vms_rfa
+{
+  /* Logical block number, 1 based.
+     0 means that the field is absent.  Block size is 512.  */
+  unsigned char vbn[4];
+
+  /* Offset within the block.  */
+  unsigned char offset[2];
+};
+
+/* Index keys.  For version 3.  */
+
+struct vms_idx
+{
+  /* Offset from the start of the vbn, so minimum should be
+     DATA__DATA (ie 6).  */
+  struct vms_rfa rfa;
+
+  unsigned char keylen;
+  /* The length of this field is in fact keylen.  */
+  unsigned char keyname[256];
+};
+
+/* Index keys, for version 4 and later.  */
+
+struct vms_elfidx
+{
+  struct vms_rfa rfa;
+
+  unsigned char keylen[2];
+  unsigned char flags;
+  unsigned char keyname[256];
+};
+
+/* Flags of elfidx.  */
+
+#define ELFIDX__WEAK 0x01	/* Weak symbol.  */
+#define ELFIDX__GROUP 0x02	/* Group symbol.  */
+#define ELFIDX__LISTRFA 0x04	/* RFA field points to an LHS.  */
+#define ELFIDX__SYMESC 0x08	/* Long symbol.  */
+
+#define RFADEF__C_INDEX 0xffff
+
+/* List head structure.  That's what is pointed by rfa when LISTRFA flag
+   is set in elfidx.  */
+
+struct vms_lhs
+{
+  struct vms_rfa ng_g_rfa;	/* Non-group global.  */
+  struct vms_rfa ng_wk_rfa;	/* Non-group weak.  */
+  struct vms_rfa g_g_rfa;	/* Group global.  */
+  struct vms_rfa g_wk_rfa;	/* Group weak.  */
+  unsigned char flags;
+};
+
+/* List node structure.  Fields of LHS point to this structure.  */
+
+struct vms_lns
+{
+  /* Next node in the list.  */
+  struct vms_rfa nxtrfa;
+
+  /* Module associated with the key.  */
+  struct vms_rfa modrfa;
+};
+
+struct vms_datadef
+{
+  /* Number of records in this block.  */
+  unsigned char recs;
+  unsigned char fill_1;
+
+  /* Next vbn.  */
+  unsigned char link[4];
+
+  /* Data.  The first word is the record length, followed by record
+     data and a possible pad byte so that record length is always aligned.  */
+  unsigned char data[506];
+};
+#define DATA__LENGTH 512
+#define DATA__DATA 6
+
+/* Key name block.  This is used for keys longer than 128 bytes.  */
+
+struct vms_kbn
+{
+  /* Length of the key chunk.  */
+  unsigned char keylen[2];
+
+  /* RFA of the next chunk.  */
+  struct vms_rfa rfa;
+
+  /* Followed by the key chunk.  */
+};
+
+/* Module header.  */
+struct vms_mhd
+{
+  /* Fixed part.  */
+  unsigned char lbrflag;
+  unsigned char id;
+  unsigned char fill_1[2];
+  unsigned char refcnt[4];
+  unsigned char datim[8];
+
+  unsigned char objstat;
+  /* Ident or GSMATCH.  */
+  unsigned char objidlng;
+  unsigned char objid[31];
+
+  unsigned char pad1[3];
+  unsigned char otherefcnt[4];
+  unsigned char modsize[4];
+  unsigned char pad2[4];
+};
+
+#define MHD__C_MHDID 0xad	/* Value for id.  */
+#define MHD__C_MHDLEN 16	/* Fixed part length.  */
+#define MHD__C_USRDAT 16
+
+/* Flags for objstat.  */
+#define MHD__M_SELSRC 0x1	/* Selective search.  */
+#define MHD__M_OBJTIR 0x2
+#define MHD__M_WKSYM  0x4
+
+struct vms_luh
+{
+  unsigned char nxtluhblk[4];
+  unsigned char spare[2];
+  unsigned char data[506];
+};
+
+struct vms_luhdef
+{
+  unsigned char rechdr[2];
+  unsigned char reclen[2];
+};
+#define LUH__RECHDRLEN 4
+#define LUH__RECHDRMRK 0xabba
+#define LUH__DATAFLDLEN 506
+
+/* Entry in the history.  */
+
+struct vms_leh
+{
+  unsigned char date[8];
+  unsigned char nbr_units[2];
+  unsigned char action[2]; /* 1: delete, 2: insert, 3: replaced.  */
+  unsigned char idlen;
+  /* username
+     modules... */
+};
+
+#endif /* _VMS_LBR_H */
diff --git a/binutils-2.25/include/vms/prt.h b/binutils-2.25/include/vms/prt.h
new file mode 100644
index 00000000..8b8d27b5
--- /dev/null
+++ b/binutils-2.25/include/vms/prt.h
@@ -0,0 +1,43 @@
+/* Alpha VMS external format of Protection values.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_PRT_H
+#define _VMS_PRT_H
+
+#define PRT__C_NA	0	/* No access.  */
+#define PRT__C_RESERVED 1
+#define PRT__C_KW	2	/* Kernel RW.  */
+#define PRT__C_KR	3	/* Kernel RO. */
+#define PRT__C_UW	4	/* User RW.  */
+#define PRT__C_EW	5	/* Executive RW.  */
+#define PRT__C_ERKW	6	/* Executive RO, Kernel RW.  */
+#define PRT__C_ER	7	/* Executive RO.  */
+#define PRT__C_SW	8	/* Supervisor RW.  */
+#define PRT__C_SREW	9	/* Supervisor RO, Executive RW.  */
+#define PRT__C_SRKW	10	/* Supervisor RO, Kernel RW.  */
+#define PRT__C_SR	11	/* Supervisor RO.  */
+#define PRT__C_URSW	12	/* User RO, Supervisor RW.  */
+#define PRT__C_UREW	13	/* User RO, Executive RW.  */
+#define PRT__C_URKW	14	/* User RO, Kernel RW.  */
+#define PRT__C_UR	15	/* User RO.  */
+
+#endif /* _VMS_PRT_H */
diff --git a/binutils-2.25/include/vms/shl.h b/binutils-2.25/include/vms/shl.h
new file mode 100644
index 00000000..d1d9fae9
--- /dev/null
+++ b/binutils-2.25/include/vms/shl.h
@@ -0,0 +1,55 @@
+/* Alpha VMS external format of Shareable image List.
+
+   Copyright 2010 Free Software Foundation, Inc.
+   Written by Tristan Gingold <gingold@adacore.com>, AdaCore.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef _VMS_SHL_H
+#define _VMS_SHL_H
+
+struct vms_shl
+{
+  /* Base address of this shareable image.  */
+  unsigned char baseva[4];
+
+  /* Point in SHL shareable image to SHL in executable image.  */
+  unsigned char shlptr[4];
+
+  /* GSMATCH.  */
+  unsigned char ident[4];
+
+  /* Permanent shareable image context.  */
+  unsigned char permctx[4];
+
+  /* Size of this structure.  */
+  unsigned char size;
+
+  unsigned char fill_1[2];
+
+  /* Flags.  */
+  unsigned char flags;
+
+  /* Address of the image control block (in memory).  */
+  unsigned char icb[4];
+
+  /* Image name.  ASCIC.  */
+  unsigned char imgnam[40];
+};
+
+#endif /* _VMS_SHL_H */
diff --git a/binutils-2.25/include/vtv-change-permission.h b/binutils-2.25/include/vtv-change-permission.h
new file mode 100644
index 00000000..1adcb974
--- /dev/null
+++ b/binutils-2.25/include/vtv-change-permission.h
@@ -0,0 +1,55 @@
+/* Copyright (C) 2013
+   Free Software Foundation
+  
+   This file is part of GCC.
+  
+   modify it under the terms of the GNU Library General Public License
+   as published by the Free Software Foundation; either version 2, or
+   (at your option) any later version.
+
+   In addition to the permissions in the GNU Library General Public
+   License, the Free Software Foundation gives you unlimited
+   permission to link the compiled version of this file into
+   combinations with other programs, and to distribute those
+   combinations without any restriction coming from the use of this
+   file.  (The Library Public License restrictions do apply in other
+   respects; for example, they cover modification of the file, and
+   distribution when not linked into a combined executable.)
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Library General Public License for more details.
+
+   You should have received a copy of the GNU Library General Public
+   License along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+
+#ifndef __VTV_H__
+#define __VTV_H__
+
+/* We could have used an enumeration here but it just makes it more
+   difficult for the compiler to generate a call to this.  These are
+   used as arguments to the function __VLTChangePermission, declared
+   below.  */
+#define __VLTP_READ_ONLY  0
+#define __VLTP_READ_WRITE 1
+
+#ifdef __cplusplus
+extern "C" void __VLTChangePermission (int);
+#else
+extern void __VLTChangePermission (int);
+#endif
+
+#ifdef BIG_PAGE_SIZE
+/* TODO - Replace '4096' below with correct big page size.  */
+#define VTV_PAGE_SIZE 4096
+#else 
+#define VTV_PAGE_SIZE 4096
+#endif
+
+
+
+#endif /* __VTV_H__ */
diff --git a/binutils-2.25/include/xregex.h b/binutils-2.25/include/xregex.h
new file mode 100644
index 00000000..4c5ef934
--- /dev/null
+++ b/binutils-2.25/include/xregex.h
@@ -0,0 +1,29 @@
+/* This file redefines all regex external names before including
+   a renamed copy of glibc's regex.h.  */
+
+#ifndef _XREGEX_H
+#define _XREGEX_H 1
+
+#  define regfree xregfree 
+#  define regexec xregexec
+#  define regcomp xregcomp
+#  define regerror xregerror
+#  define regoff_t xregoff_t
+#  define re_set_registers xre_set_registers
+#  define re_match_2 xre_match_2
+#  define re_match xre_match
+#  define re_search xre_search
+#  define re_compile_pattern xre_compile_pattern
+#  define re_set_syntax xre_set_syntax
+#  define re_search_2 xre_search_2
+#  define re_compile_fastmap xre_compile_fastmap
+#  define re_syntax_options xre_syntax_options
+#  define re_max_failures xre_max_failures
+
+#  define _REGEX_RE_COMP
+#  define re_comp xre_comp
+#  define re_exec xre_exec
+
+#include "xregex2.h"
+
+#endif /* xregex.h */
diff --git a/binutils-2.25/include/xregex2.h b/binutils-2.25/include/xregex2.h
new file mode 100644
index 00000000..d3d0da14
--- /dev/null
+++ b/binutils-2.25/include/xregex2.h
@@ -0,0 +1,565 @@
+/* Definitions for data structures and routines for the regular
+   expression library, version 0.12.
+
+   Copyright (C) 1985, 1989, 1990, 1991, 1992, 1993, 1995, 1996, 1997,
+   1998, 2000, 2005 Free Software Foundation, Inc.
+
+   This file is part of the GNU C Library.  Its master source is NOT part of
+   the C library, however.  The master source lives in /gd/gnu/lib.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, write to the Free
+   Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+   02110-1301 USA.  */
+
+#ifndef _REGEX_H
+#define _REGEX_H 1
+
+/* Allow the use in C++ code.  */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* POSIX says that <sys/types.h> must be included (by the caller) before
+   <regex.h>.  */
+
+#if !defined _POSIX_C_SOURCE && !defined _POSIX_SOURCE && defined VMS
+/* VMS doesn't have `size_t' in <sys/types.h>, even though POSIX says it
+   should be there.  */
+# include <stddef.h>
+#endif
+
+/* The following two types have to be signed and unsigned integer type
+   wide enough to hold a value of a pointer.  For most ANSI compilers
+   ptrdiff_t and size_t should be likely OK.  Still size of these two
+   types is 2 for Microsoft C.  Ugh... */
+typedef long int s_reg_t;
+typedef unsigned long int active_reg_t;
+
+/* The following bits are used to determine the regexp syntax we
+   recognize.  The set/not-set meanings are chosen so that Emacs syntax
+   remains the value 0.  The bits are given in alphabetical order, and
+   the definitions shifted by one from the previous bit; thus, when we
+   add or remove a bit, only one other definition need change.  */
+typedef unsigned long int reg_syntax_t;
+
+/* If this bit is not set, then \ inside a bracket expression is literal.
+   If set, then such a \ quotes the following character.  */
+#define RE_BACKSLASH_ESCAPE_IN_LISTS ((unsigned long int) 1)
+
+/* If this bit is not set, then + and ? are operators, and \+ and \? are
+     literals.
+   If set, then \+ and \? are operators and + and ? are literals.  */
+#define RE_BK_PLUS_QM (RE_BACKSLASH_ESCAPE_IN_LISTS << 1)
+
+/* If this bit is set, then character classes are supported.  They are:
+     [:alpha:], [:upper:], [:lower:],  [:digit:], [:alnum:], [:xdigit:],
+     [:space:], [:print:], [:punct:], [:graph:], and [:cntrl:].
+   If not set, then character classes are not supported.  */
+#define RE_CHAR_CLASSES (RE_BK_PLUS_QM << 1)
+
+/* If this bit is set, then ^ and $ are always anchors (outside bracket
+     expressions, of course).
+   If this bit is not set, then it depends:
+        ^  is an anchor if it is at the beginning of a regular
+           expression or after an open-group or an alternation operator;
+        $  is an anchor if it is at the end of a regular expression, or
+           before a close-group or an alternation operator.
+
+   This bit could be (re)combined with RE_CONTEXT_INDEP_OPS, because
+   POSIX draft 11.2 says that * etc. in leading positions is undefined.
+   We already implemented a previous draft which made those constructs
+   invalid, though, so we haven't changed the code back.  */
+#define RE_CONTEXT_INDEP_ANCHORS (RE_CHAR_CLASSES << 1)
+
+/* If this bit is set, then special characters are always special
+     regardless of where they are in the pattern.
+   If this bit is not set, then special characters are special only in
+     some contexts; otherwise they are ordinary.  Specifically,
+     * + ? and intervals are only special when not after the beginning,
+     open-group, or alternation operator.  */
+#define RE_CONTEXT_INDEP_OPS (RE_CONTEXT_INDEP_ANCHORS << 1)
+
+/* If this bit is set, then *, +, ?, and { cannot be first in an re or
+     immediately after an alternation or begin-group operator.  */
+#define RE_CONTEXT_INVALID_OPS (RE_CONTEXT_INDEP_OPS << 1)
+
+/* If this bit is set, then . matches newline.
+   If not set, then it doesn't.  */
+#define RE_DOT_NEWLINE (RE_CONTEXT_INVALID_OPS << 1)
+
+/* If this bit is set, then . doesn't match NUL.
+   If not set, then it does.  */
+#define RE_DOT_NOT_NULL (RE_DOT_NEWLINE << 1)
+
+/* If this bit is set, nonmatching lists [^...] do not match newline.
+   If not set, they do.  */
+#define RE_HAT_LISTS_NOT_NEWLINE (RE_DOT_NOT_NULL << 1)
+
+/* If this bit is set, either \{...\} or {...} defines an
+     interval, depending on RE_NO_BK_BRACES.
+   If not set, \{, \}, {, and } are literals.  */
+#define RE_INTERVALS (RE_HAT_LISTS_NOT_NEWLINE << 1)
+
+/* If this bit is set, +, ? and | aren't recognized as operators.
+   If not set, they are.  */
+#define RE_LIMITED_OPS (RE_INTERVALS << 1)
+
+/* If this bit is set, newline is an alternation operator.
+   If not set, newline is literal.  */
+#define RE_NEWLINE_ALT (RE_LIMITED_OPS << 1)
+
+/* If this bit is set, then `{...}' defines an interval, and \{ and \}
+     are literals.
+  If not set, then `\{...\}' defines an interval.  */
+#define RE_NO_BK_BRACES (RE_NEWLINE_ALT << 1)
+
+/* If this bit is set, (...) defines a group, and \( and \) are literals.
+   If not set, \(...\) defines a group, and ( and ) are literals.  */
+#define RE_NO_BK_PARENS (RE_NO_BK_BRACES << 1)
+
+/* If this bit is set, then \<digit> matches <digit>.
+   If not set, then \<digit> is a back-reference.  */
+#define RE_NO_BK_REFS (RE_NO_BK_PARENS << 1)
+
+/* If this bit is set, then | is an alternation operator, and \| is literal.
+   If not set, then \| is an alternation operator, and | is literal.  */
+#define RE_NO_BK_VBAR (RE_NO_BK_REFS << 1)
+
+/* If this bit is set, then an ending range point collating higher
+     than the starting range point, as in [z-a], is invalid.
+   If not set, then when ending range point collates higher than the
+     starting range point, the range is ignored.  */
+#define RE_NO_EMPTY_RANGES (RE_NO_BK_VBAR << 1)
+
+/* If this bit is set, then an unmatched ) is ordinary.
+   If not set, then an unmatched ) is invalid.  */
+#define RE_UNMATCHED_RIGHT_PAREN_ORD (RE_NO_EMPTY_RANGES << 1)
+
+/* If this bit is set, succeed as soon as we match the whole pattern,
+   without further backtracking.  */
+#define RE_NO_POSIX_BACKTRACKING (RE_UNMATCHED_RIGHT_PAREN_ORD << 1)
+
+/* If this bit is set, do not process the GNU regex operators.
+   If not set, then the GNU regex operators are recognized. */
+#define RE_NO_GNU_OPS (RE_NO_POSIX_BACKTRACKING << 1)
+
+/* If this bit is set, turn on internal regex debugging.
+   If not set, and debugging was on, turn it off.
+   This only works if regex.c is compiled -DDEBUG.
+   We define this bit always, so that all that's needed to turn on
+   debugging is to recompile regex.c; the calling code can always have
+   this bit set, and it won't affect anything in the normal case. */
+#define RE_DEBUG (RE_NO_GNU_OPS << 1)
+
+/* If this bit is set, a syntactically invalid interval is treated as
+   a string of ordinary characters.  For example, the ERE 'a{1' is
+   treated as 'a\{1'.  */
+#define RE_INVALID_INTERVAL_ORD (RE_DEBUG << 1)
+
+/* This global variable defines the particular regexp syntax to use (for
+   some interfaces).  When a regexp is compiled, the syntax used is
+   stored in the pattern buffer, so changing this does not affect
+   already-compiled regexps.  */
+extern reg_syntax_t re_syntax_options;
+
+/* Define combinations of the above bits for the standard possibilities.
+   (The [[[ comments delimit what gets put into the Texinfo file, so
+   don't delete them!)  */
+/* [[[begin syntaxes]]] */
+#define RE_SYNTAX_EMACS 0
+
+#define RE_SYNTAX_AWK							\
+  (RE_BACKSLASH_ESCAPE_IN_LISTS   | RE_DOT_NOT_NULL			\
+   | RE_NO_BK_PARENS              | RE_NO_BK_REFS			\
+   | RE_NO_BK_VBAR                | RE_NO_EMPTY_RANGES			\
+   | RE_DOT_NEWLINE		  | RE_CONTEXT_INDEP_ANCHORS		\
+   | RE_UNMATCHED_RIGHT_PAREN_ORD | RE_NO_GNU_OPS)
+
+#define RE_SYNTAX_GNU_AWK						\
+  ((RE_SYNTAX_POSIX_EXTENDED | RE_BACKSLASH_ESCAPE_IN_LISTS | RE_DEBUG)	\
+   & ~(RE_DOT_NOT_NULL | RE_INTERVALS | RE_CONTEXT_INDEP_OPS))
+
+#define RE_SYNTAX_POSIX_AWK 						\
+  (RE_SYNTAX_POSIX_EXTENDED | RE_BACKSLASH_ESCAPE_IN_LISTS		\
+   | RE_INTERVALS	    | RE_NO_GNU_OPS)
+
+#define RE_SYNTAX_GREP							\
+  (RE_BK_PLUS_QM              | RE_CHAR_CLASSES				\
+   | RE_HAT_LISTS_NOT_NEWLINE | RE_INTERVALS				\
+   | RE_NEWLINE_ALT)
+
+#define RE_SYNTAX_EGREP							\
+  (RE_CHAR_CLASSES        | RE_CONTEXT_INDEP_ANCHORS			\
+   | RE_CONTEXT_INDEP_OPS | RE_HAT_LISTS_NOT_NEWLINE			\
+   | RE_NEWLINE_ALT       | RE_NO_BK_PARENS				\
+   | RE_NO_BK_VBAR)
+
+#define RE_SYNTAX_POSIX_EGREP						\
+  (RE_SYNTAX_EGREP | RE_INTERVALS | RE_NO_BK_BRACES			\
+   | RE_INVALID_INTERVAL_ORD)
+
+/* P1003.2/D11.2, section 4.20.7.1, lines 5078ff.  */
+#define RE_SYNTAX_ED RE_SYNTAX_POSIX_BASIC
+
+#define RE_SYNTAX_SED RE_SYNTAX_POSIX_BASIC
+
+/* Syntax bits common to both basic and extended POSIX regex syntax.  */
+#define _RE_SYNTAX_POSIX_COMMON						\
+  (RE_CHAR_CLASSES | RE_DOT_NEWLINE      | RE_DOT_NOT_NULL		\
+   | RE_INTERVALS  | RE_NO_EMPTY_RANGES)
+
+#define RE_SYNTAX_POSIX_BASIC						\
+  (_RE_SYNTAX_POSIX_COMMON | RE_BK_PLUS_QM)
+
+/* Differs from ..._POSIX_BASIC only in that RE_BK_PLUS_QM becomes
+   RE_LIMITED_OPS, i.e., \? \+ \| are not recognized.  Actually, this
+   isn't minimal, since other operators, such as \`, aren't disabled.  */
+#define RE_SYNTAX_POSIX_MINIMAL_BASIC					\
+  (_RE_SYNTAX_POSIX_COMMON | RE_LIMITED_OPS)
+
+#define RE_SYNTAX_POSIX_EXTENDED					\
+  (_RE_SYNTAX_POSIX_COMMON  | RE_CONTEXT_INDEP_ANCHORS			\
+   | RE_CONTEXT_INDEP_OPS   | RE_NO_BK_BRACES				\
+   | RE_NO_BK_PARENS        | RE_NO_BK_VBAR				\
+   | RE_CONTEXT_INVALID_OPS | RE_UNMATCHED_RIGHT_PAREN_ORD)
+
+/* Differs from ..._POSIX_EXTENDED in that RE_CONTEXT_INDEP_OPS is
+   removed and RE_NO_BK_REFS is added.  */
+#define RE_SYNTAX_POSIX_MINIMAL_EXTENDED				\
+  (_RE_SYNTAX_POSIX_COMMON  | RE_CONTEXT_INDEP_ANCHORS			\
+   | RE_CONTEXT_INVALID_OPS | RE_NO_BK_BRACES				\
+   | RE_NO_BK_PARENS        | RE_NO_BK_REFS				\
+   | RE_NO_BK_VBAR	    | RE_UNMATCHED_RIGHT_PAREN_ORD)
+/* [[[end syntaxes]]] */
+
+/* Maximum number of duplicates an interval can allow.  Some systems
+   (erroneously) define this in other header files, but we want our
+   value, so remove any previous define.  */
+#ifdef RE_DUP_MAX
+# undef RE_DUP_MAX
+#endif
+/* If sizeof(int) == 2, then ((1 << 15) - 1) overflows.  */
+#define RE_DUP_MAX (0x7fff)
+
+
+/* POSIX `cflags' bits (i.e., information for `regcomp').  */
+
+/* If this bit is set, then use extended regular expression syntax.
+   If not set, then use basic regular expression syntax.  */
+#define REG_EXTENDED 1
+
+/* If this bit is set, then ignore case when matching.
+   If not set, then case is significant.  */
+#define REG_ICASE (REG_EXTENDED << 1)
+
+/* If this bit is set, then anchors do not match at newline
+     characters in the string.
+   If not set, then anchors do match at newlines.  */
+#define REG_NEWLINE (REG_ICASE << 1)
+
+/* If this bit is set, then report only success or fail in regexec.
+   If not set, then returns differ between not matching and errors.  */
+#define REG_NOSUB (REG_NEWLINE << 1)
+
+
+/* POSIX `eflags' bits (i.e., information for regexec).  */
+
+/* If this bit is set, then the beginning-of-line operator doesn't match
+     the beginning of the string (presumably because it's not the
+     beginning of a line).
+   If not set, then the beginning-of-line operator does match the
+     beginning of the string.  */
+#define REG_NOTBOL 1
+
+/* Like REG_NOTBOL, except for the end-of-line.  */
+#define REG_NOTEOL (1 << 1)
+
+
+/* If any error codes are removed, changed, or added, update the
+   `re_error_msg' table in regex.c.  */
+typedef enum
+{
+#ifdef _XOPEN_SOURCE
+  REG_ENOSYS = -1,	/* This will never happen for this implementation.  */
+#endif
+
+  REG_NOERROR = 0,	/* Success.  */
+  REG_NOMATCH,		/* Didn't find a match (for regexec).  */
+
+  /* POSIX regcomp return error codes.  (In the order listed in the
+     standard.)  */
+  REG_BADPAT,		/* Invalid pattern.  */
+  REG_ECOLLATE,		/* Not implemented.  */
+  REG_ECTYPE,		/* Invalid character class name.  */
+  REG_EESCAPE,		/* Trailing backslash.  */
+  REG_ESUBREG,		/* Invalid back reference.  */
+  REG_EBRACK,		/* Unmatched left bracket.  */
+  REG_EPAREN,		/* Parenthesis imbalance.  */
+  REG_EBRACE,		/* Unmatched \{.  */
+  REG_BADBR,		/* Invalid contents of \{\}.  */
+  REG_ERANGE,		/* Invalid range end.  */
+  REG_ESPACE,		/* Ran out of memory.  */
+  REG_BADRPT,		/* No preceding re for repetition op.  */
+
+  /* Error codes we've added.  */
+  REG_EEND,		/* Premature end.  */
+  REG_ESIZE,		/* Compiled pattern bigger than 2^16 bytes.  */
+  REG_ERPAREN		/* Unmatched ) or \); not returned from regcomp.  */
+} reg_errcode_t;
+
+/* This data structure represents a compiled pattern.  Before calling
+   the pattern compiler, the fields `buffer', `allocated', `fastmap',
+   `translate', and `no_sub' can be set.  After the pattern has been
+   compiled, the `re_nsub' field is available.  All other fields are
+   private to the regex routines.  */
+
+#ifndef RE_TRANSLATE_TYPE
+# define RE_TRANSLATE_TYPE char *
+#endif
+
+struct re_pattern_buffer
+{
+/* [[[begin pattern_buffer]]] */
+	/* Space that holds the compiled pattern.  It is declared as
+          `unsigned char *' because its elements are
+           sometimes used as array indexes.  */
+  unsigned char *buffer;
+
+	/* Number of bytes to which `buffer' points.  */
+  unsigned long int allocated;
+
+	/* Number of bytes actually used in `buffer'.  */
+  unsigned long int used;
+
+        /* Syntax setting with which the pattern was compiled.  */
+  reg_syntax_t syntax;
+
+        /* Pointer to a fastmap, if any, otherwise zero.  re_search uses
+           the fastmap, if there is one, to skip over impossible
+           starting points for matches.  */
+  char *fastmap;
+
+        /* Either a translate table to apply to all characters before
+           comparing them, or zero for no translation.  The translation
+           is applied to a pattern when it is compiled and to a string
+           when it is matched.  */
+  RE_TRANSLATE_TYPE translate;
+
+	/* Number of subexpressions found by the compiler.  */
+  size_t re_nsub;
+
+        /* Zero if this pattern cannot match the empty string, one else.
+           Well, in truth it's used only in `re_search_2', to see
+           whether or not we should use the fastmap, so we don't set
+           this absolutely perfectly; see `re_compile_fastmap' (the
+           `duplicate' case).  */
+  unsigned can_be_null : 1;
+
+        /* If REGS_UNALLOCATED, allocate space in the `regs' structure
+             for `max (RE_NREGS, re_nsub + 1)' groups.
+           If REGS_REALLOCATE, reallocate space if necessary.
+           If REGS_FIXED, use what's there.  */
+#define REGS_UNALLOCATED 0
+#define REGS_REALLOCATE 1
+#define REGS_FIXED 2
+  unsigned regs_allocated : 2;
+
+        /* Set to zero when `regex_compile' compiles a pattern; set to one
+           by `re_compile_fastmap' if it updates the fastmap.  */
+  unsigned fastmap_accurate : 1;
+
+        /* If set, `re_match_2' does not return information about
+           subexpressions.  */
+  unsigned no_sub : 1;
+
+        /* If set, a beginning-of-line anchor doesn't match at the
+           beginning of the string.  */
+  unsigned not_bol : 1;
+
+        /* Similarly for an end-of-line anchor.  */
+  unsigned not_eol : 1;
+
+        /* If true, an anchor at a newline matches.  */
+  unsigned newline_anchor : 1;
+
+/* [[[end pattern_buffer]]] */
+};
+
+typedef struct re_pattern_buffer regex_t;
+
+/* Type for byte offsets within the string.  POSIX mandates this.  */
+typedef int regoff_t;
+
+
+/* This is the structure we store register match data in.  See
+   regex.texinfo for a full description of what registers match.  */
+struct re_registers
+{
+  unsigned num_regs;
+  regoff_t *start;
+  regoff_t *end;
+};
+
+
+/* If `regs_allocated' is REGS_UNALLOCATED in the pattern buffer,
+   `re_match_2' returns information about at least this many registers
+   the first time a `regs' structure is passed.  */
+#ifndef RE_NREGS
+# define RE_NREGS 30
+#endif
+
+
+/* POSIX specification for registers.  Aside from the different names than
+   `re_registers', POSIX uses an array of structures, instead of a
+   structure of arrays.  */
+typedef struct
+{
+  regoff_t rm_so;  /* Byte offset from string's start to substring's start.  */
+  regoff_t rm_eo;  /* Byte offset from string's start to substring's end.  */
+} regmatch_t;
+
+/* Declarations for routines.  */
+
+/* To avoid duplicating every routine declaration -- once with a
+   prototype (if we are ANSI), and once without (if we aren't) -- we
+   use the following macro to declare argument types.  This
+   unfortunately clutters up the declarations a bit, but I think it's
+   worth it.  */
+
+/* Sets the current default syntax to SYNTAX, and return the old syntax.
+   You can also simply assign to the `re_syntax_options' variable.  */
+extern reg_syntax_t re_set_syntax (reg_syntax_t syntax);
+
+/* Compile the regular expression PATTERN, with length LENGTH
+   and syntax given by the global `re_syntax_options', into the buffer
+   BUFFER.  Return NULL if successful, and an error string if not.  */
+extern const char *re_compile_pattern (const char *pattern, size_t length,
+                                       struct re_pattern_buffer *buffer);
+
+
+/* Compile a fastmap for the compiled pattern in BUFFER; used to
+   accelerate searches.  Return 0 if successful and -2 if was an
+   internal error.  */
+extern int re_compile_fastmap (struct re_pattern_buffer *buffer);
+
+
+/* Search in the string STRING (with length LENGTH) for the pattern
+   compiled into BUFFER.  Start searching at position START, for RANGE
+   characters.  Return the starting position of the match, -1 for no
+   match, or -2 for an internal error.  Also return register
+   information in REGS (if REGS and BUFFER->no_sub are nonzero).  */
+extern int re_search (struct re_pattern_buffer *buffer, const char *string,
+                      int length, int start, int range,
+                      struct re_registers *regs);
+
+
+/* Like `re_search', but search in the concatenation of STRING1 and
+   STRING2.  Also, stop searching at index START + STOP.  */
+extern int re_search_2 (struct re_pattern_buffer *buffer, const char *string1,
+                        int length1, const char *string2, int length2,
+                        int start, int range, struct re_registers *regs,
+                        int stop);
+
+
+/* Like `re_search', but return how many characters in STRING the regexp
+   in BUFFER matched, starting at position START.  */
+extern int re_match (struct re_pattern_buffer *buffer, const char *string,
+                     int length, int start, struct re_registers *regs);
+
+
+/* Relates to `re_match' as `re_search_2' relates to `re_search'.  */
+extern int re_match_2 (struct re_pattern_buffer *buffer, const char *string1,
+                       int length1, const char *string2, int length2,
+                       int start, struct re_registers *regs, int stop);
+
+
+/* Set REGS to hold NUM_REGS registers, storing them in STARTS and
+   ENDS.  Subsequent matches using BUFFER and REGS will use this memory
+   for recording register information.  STARTS and ENDS must be
+   allocated with malloc, and must each be at least `NUM_REGS * sizeof
+   (regoff_t)' bytes long.
+
+   If NUM_REGS == 0, then subsequent matches should allocate their own
+   register data.
+
+   Unless this function is called, the first search or match using
+   PATTERN_BUFFER will allocate its own register data, without
+   freeing the old data.  */
+extern void re_set_registers (struct re_pattern_buffer *buffer,
+                              struct re_registers *regs,
+                              unsigned num_regs, regoff_t *starts,
+                              regoff_t *ends);
+
+#if defined _REGEX_RE_COMP || defined _LIBC
+# ifndef _CRAY
+/* 4.2 bsd compatibility.  */
+extern char *re_comp (const char *);
+extern int re_exec (const char *);
+# endif
+#endif
+
+/* GCC 2.95 and later have "__restrict"; C99 compilers have
+   "restrict", and "configure" may have defined "restrict".  */
+#ifndef __restrict
+# if ! (2 < __GNUC__ || (2 == __GNUC__ && 95 <= __GNUC_MINOR__))
+#  if defined restrict || 199901L <= __STDC_VERSION__
+#   define __restrict restrict
+#  else
+#   define __restrict
+#  endif
+# endif
+#endif
+
+/* GCC 3.1 and later support declaring arrays as non-overlapping
+   using the syntax array_name[restrict]  */
+#ifndef __restrict_arr
+# if ! (3 < __GNUC__ || (3 == __GNUC__ && 1 <= __GNUC_MINOR__)) || defined (__GNUG__)
+#  define __restrict_arr
+# else
+#  define __restrict_arr __restrict
+# endif
+#endif
+
+/* POSIX compatibility.  */
+extern int regcomp (regex_t *__restrict __preg,
+                    const char *__restrict __pattern,
+                    int __cflags);
+
+#if (__GNUC__)
+__extension__
+#endif
+extern int regexec (const regex_t *__restrict __preg,
+                    const char *__restrict __string, size_t __nmatch,
+                    regmatch_t __pmatch[__restrict_arr],
+                    int __eflags);
+
+extern size_t regerror (int __errcode, const regex_t *__preg,
+                        char *__errbuf, size_t __errbuf_size);
+
+extern void regfree (regex_t *__preg);
+
+
+#ifdef __cplusplus
+}
+#endif	/* C++ */
+
+#endif /* regex.h */
+
+/*
+Local variables:
+make-backup-files: t
+version-control: t
+trim-versions-without-asking: nil
+End:
+*/
diff --git a/binutils-2.25/include/xtensa-config.h b/binutils-2.25/include/xtensa-config.h
new file mode 100644
index 00000000..30f4f41a
--- /dev/null
+++ b/binutils-2.25/include/xtensa-config.h
@@ -0,0 +1,177 @@
+/* Xtensa configuration settings.
+   Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
+   Free Software Foundation, Inc.
+   Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef XTENSA_CONFIG_H
+#define XTENSA_CONFIG_H
+
+/* The macros defined here match those with the same names in the Xtensa
+   compile-time HAL (Hardware Abstraction Layer).  Please refer to the
+   Xtensa System Software Reference Manual for documentation of these
+   macros.  */
+
+#undef XCHAL_HAVE_BE
+#define XCHAL_HAVE_BE			1
+
+#undef XCHAL_HAVE_DENSITY
+#define XCHAL_HAVE_DENSITY		1
+
+#undef XCHAL_HAVE_CONST16
+#define XCHAL_HAVE_CONST16		0
+
+#undef XCHAL_HAVE_ABS
+#define XCHAL_HAVE_ABS			1
+
+#undef XCHAL_HAVE_ADDX
+#define XCHAL_HAVE_ADDX			1
+
+#undef XCHAL_HAVE_L32R
+#define XCHAL_HAVE_L32R			1
+
+#undef XSHAL_USE_ABSOLUTE_LITERALS
+#define XSHAL_USE_ABSOLUTE_LITERALS	0
+
+#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
+#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals.  */
+
+#undef XCHAL_HAVE_MAC16
+#define XCHAL_HAVE_MAC16		0
+
+#undef XCHAL_HAVE_MUL16
+#define XCHAL_HAVE_MUL16		1
+
+#undef XCHAL_HAVE_MUL32
+#define XCHAL_HAVE_MUL32		1
+
+#undef XCHAL_HAVE_MUL32_HIGH
+#define XCHAL_HAVE_MUL32_HIGH		0
+
+#undef XCHAL_HAVE_DIV32
+#define XCHAL_HAVE_DIV32		1
+
+#undef XCHAL_HAVE_NSA
+#define XCHAL_HAVE_NSA			1
+
+#undef XCHAL_HAVE_MINMAX
+#define XCHAL_HAVE_MINMAX		1
+
+#undef XCHAL_HAVE_SEXT
+#define XCHAL_HAVE_SEXT			1
+
+#undef XCHAL_HAVE_LOOPS
+#define XCHAL_HAVE_LOOPS		1
+
+#undef XCHAL_HAVE_THREADPTR
+#define XCHAL_HAVE_THREADPTR		1
+
+#undef XCHAL_HAVE_RELEASE_SYNC
+#define XCHAL_HAVE_RELEASE_SYNC		1
+
+#undef XCHAL_HAVE_S32C1I
+#define XCHAL_HAVE_S32C1I		1
+
+#undef XCHAL_HAVE_BOOLEANS
+#define XCHAL_HAVE_BOOLEANS		0
+
+#undef XCHAL_HAVE_FP
+#define XCHAL_HAVE_FP			0
+
+#undef XCHAL_HAVE_FP_DIV
+#define XCHAL_HAVE_FP_DIV		0
+
+#undef XCHAL_HAVE_FP_RECIP
+#define XCHAL_HAVE_FP_RECIP		0
+
+#undef XCHAL_HAVE_FP_SQRT
+#define XCHAL_HAVE_FP_SQRT		0
+
+#undef XCHAL_HAVE_FP_RSQRT
+#define XCHAL_HAVE_FP_RSQRT		0
+
+#undef XCHAL_HAVE_DFP_accel
+#define XCHAL_HAVE_DFP_accel			0
+#undef XCHAL_HAVE_WINDOWED
+#define XCHAL_HAVE_WINDOWED		1
+
+#undef XCHAL_NUM_AREGS
+#define XCHAL_NUM_AREGS			32
+
+#undef XCHAL_HAVE_WIDE_BRANCHES
+#define XCHAL_HAVE_WIDE_BRANCHES	0
+
+#undef XCHAL_HAVE_PREDICTED_BRANCHES
+#define XCHAL_HAVE_PREDICTED_BRANCHES	0
+
+
+#undef XCHAL_ICACHE_SIZE
+#define XCHAL_ICACHE_SIZE		16384
+
+#undef XCHAL_DCACHE_SIZE
+#define XCHAL_DCACHE_SIZE		16384
+
+#undef XCHAL_ICACHE_LINESIZE
+#define XCHAL_ICACHE_LINESIZE		32
+
+#undef XCHAL_DCACHE_LINESIZE
+#define XCHAL_DCACHE_LINESIZE		32
+
+#undef XCHAL_ICACHE_LINEWIDTH
+#define XCHAL_ICACHE_LINEWIDTH		5
+
+#undef XCHAL_DCACHE_LINEWIDTH
+#define XCHAL_DCACHE_LINEWIDTH		5
+
+#undef XCHAL_DCACHE_IS_WRITEBACK
+#define XCHAL_DCACHE_IS_WRITEBACK	1
+
+
+#undef XCHAL_HAVE_MMU
+#define XCHAL_HAVE_MMU			1
+
+#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
+#define XCHAL_MMU_MIN_PTE_PAGE_SIZE	12
+
+
+#undef XCHAL_HAVE_DEBUG
+#define XCHAL_HAVE_DEBUG		1
+
+#undef XCHAL_NUM_IBREAK
+#define XCHAL_NUM_IBREAK		2
+
+#undef XCHAL_NUM_DBREAK
+#define XCHAL_NUM_DBREAK		2
+
+#undef XCHAL_DEBUGLEVEL
+#define XCHAL_DEBUGLEVEL		6
+
+
+#undef XCHAL_MAX_INSTRUCTION_SIZE
+#define XCHAL_MAX_INSTRUCTION_SIZE	3
+
+#undef XCHAL_INST_FETCH_WIDTH
+#define XCHAL_INST_FETCH_WIDTH		4
+
+
+#undef XSHAL_ABI
+#undef XTHAL_ABI_WINDOWED
+#undef XTHAL_ABI_CALL0
+#define XSHAL_ABI			XTHAL_ABI_WINDOWED
+#define XTHAL_ABI_WINDOWED		0
+#define XTHAL_ABI_CALL0			1
+
+#endif /* !XTENSA_CONFIG_H */
diff --git a/binutils-2.25/include/xtensa-isa-internal.h b/binutils-2.25/include/xtensa-isa-internal.h
new file mode 100644
index 00000000..6c727366
--- /dev/null
+++ b/binutils-2.25/include/xtensa-isa-internal.h
@@ -0,0 +1,234 @@
+/* Internal definitions for configurable Xtensa ISA support.
+   Copyright 2003, 2004, 2005, 2008, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
+   USA.  */
+
+#ifndef XTENSA_ISA_INTERNAL_H
+#define XTENSA_ISA_INTERNAL_H
+
+/* Flags.  */
+
+#define XTENSA_OPERAND_IS_REGISTER	0x00000001
+#define XTENSA_OPERAND_IS_PCRELATIVE	0x00000002
+#define XTENSA_OPERAND_IS_INVISIBLE	0x00000004
+#define XTENSA_OPERAND_IS_UNKNOWN	0x00000008
+
+#define XTENSA_OPCODE_IS_BRANCH		0x00000001
+#define XTENSA_OPCODE_IS_JUMP		0x00000002
+#define XTENSA_OPCODE_IS_LOOP		0x00000004
+#define XTENSA_OPCODE_IS_CALL		0x00000008
+
+#define XTENSA_STATE_IS_EXPORTED	0x00000001
+#define XTENSA_STATE_IS_SHARED_OR	0x00000002
+
+#define XTENSA_INTERFACE_HAS_SIDE_EFFECT 0x00000001
+
+/* Function pointer typedefs */
+typedef void (*xtensa_format_encode_fn) (xtensa_insnbuf);
+typedef void (*xtensa_get_slot_fn) (const xtensa_insnbuf, xtensa_insnbuf);
+typedef void (*xtensa_set_slot_fn) (xtensa_insnbuf, const xtensa_insnbuf);
+typedef int (*xtensa_opcode_decode_fn) (const xtensa_insnbuf);
+typedef uint32 (*xtensa_get_field_fn) (const xtensa_insnbuf);
+typedef void (*xtensa_set_field_fn) (xtensa_insnbuf, uint32);
+typedef int (*xtensa_immed_decode_fn) (uint32 *);
+typedef int (*xtensa_immed_encode_fn) (uint32 *);
+typedef int (*xtensa_do_reloc_fn) (uint32 *, uint32);
+typedef int (*xtensa_undo_reloc_fn) (uint32 *, uint32);
+typedef void (*xtensa_opcode_encode_fn) (xtensa_insnbuf);
+typedef int (*xtensa_format_decode_fn) (const xtensa_insnbuf);
+typedef int (*xtensa_length_decode_fn) (const unsigned char *);
+
+typedef struct xtensa_format_internal_struct
+{
+  const char *name;			/* Instruction format name.  */
+  int length;				/* Instruction length in bytes.  */
+  xtensa_format_encode_fn encode_fn;
+  int num_slots;
+  int *slot_id;				/* Array[num_slots] of slot IDs.  */
+} xtensa_format_internal;
+
+typedef struct xtensa_slot_internal_struct
+{
+  const char *name;			/* Not necessarily unique.  */
+  const char *format;
+  int position;
+  xtensa_get_slot_fn get_fn;
+  xtensa_set_slot_fn set_fn;
+  xtensa_get_field_fn *get_field_fns;	/* Array[field_id].  */
+  xtensa_set_field_fn *set_field_fns;	/* Array[field_id].  */
+  xtensa_opcode_decode_fn opcode_decode_fn;
+  const char *nop_name;
+} xtensa_slot_internal;
+
+typedef struct xtensa_operand_internal_struct
+{
+  const char *name;
+  int field_id;
+  xtensa_regfile regfile;		/* Register file.  */
+  int num_regs;				/* Usually 1; 2 for reg pairs, etc.  */
+  uint32 flags;				/* See XTENSA_OPERAND_* flags.  */
+  xtensa_immed_encode_fn encode;	/* Encode the operand value.  */
+  xtensa_immed_decode_fn decode;	/* Decode the value from the field.  */
+  xtensa_do_reloc_fn do_reloc;		/* Perform a PC-relative reloc.  */
+  xtensa_undo_reloc_fn undo_reloc;	/* Undo a PC-relative relocation.  */
+} xtensa_operand_internal;
+
+typedef struct xtensa_arg_internal_struct
+{
+  union {
+    int operand_id;			/* For normal operands.  */
+    xtensa_state state;			/* For stateOperands.  */
+  } u;
+  char inout;				/* Direction: 'i', 'o', or 'm'.  */
+} xtensa_arg_internal;
+
+typedef struct xtensa_iclass_internal_struct
+{
+  int num_operands;			/* Size of "operands" array.  */
+  xtensa_arg_internal *operands;	/* Array[num_operands].  */
+
+  int num_stateOperands;		/* Size of "stateOperands" array.  */
+  xtensa_arg_internal *stateOperands;	/* Array[num_stateOperands].  */
+
+  int num_interfaceOperands;		/* Size of "interfaceOperands".  */
+  xtensa_interface *interfaceOperands;	/* Array[num_interfaceOperands].  */
+} xtensa_iclass_internal;
+
+typedef struct xtensa_opcode_internal_struct
+{
+  const char *name;			/* Opcode mnemonic.  */
+  int iclass_id;			/* Iclass for this opcode.  */
+  uint32 flags;				/* See XTENSA_OPCODE_* flags.  */
+  xtensa_opcode_encode_fn *encode_fns;	/* Array[slot_id].  */
+  int num_funcUnit_uses;		/* Number of funcUnit_use entries.  */
+  xtensa_funcUnit_use *funcUnit_uses;	/* Array[num_funcUnit_uses].  */
+} xtensa_opcode_internal;
+
+typedef struct xtensa_regfile_internal_struct
+{
+  const char *name;			/* Full name of the regfile.  */
+  const char *shortname;		/* Abbreviated name.  */
+  xtensa_regfile parent;		/* View parent (or identity).  */
+  int num_bits;				/* Width of the registers.  */
+  int num_entries;			/* Number of registers.  */
+} xtensa_regfile_internal;
+
+typedef struct xtensa_interface_internal_struct
+{
+  const char *name;			/* Interface name.  */
+  int num_bits;				/* Width of the interface.  */
+  uint32 flags;				/* See XTENSA_INTERFACE_* flags.  */
+  int class_id;				/* Class of related interfaces.  */
+  char inout;				/* "i" or "o".  */
+} xtensa_interface_internal;
+
+typedef struct xtensa_funcUnit_internal_struct
+{
+  const char *name;			/* Functional unit name.  */
+  int num_copies;			/* Number of instances.  */
+} xtensa_funcUnit_internal;
+
+typedef struct xtensa_state_internal_struct
+{
+  const char *name;			/* State name.  */
+  int num_bits;				/* Number of state bits.  */
+  uint32 flags;				/* See XTENSA_STATE_* flags.  */
+} xtensa_state_internal;
+
+typedef struct xtensa_sysreg_internal_struct
+{
+  const char *name;			/* Register name.  */
+  int number;				/* Register number.  */
+  int is_user;				/* Non-zero if a "user register".  */
+} xtensa_sysreg_internal;
+
+typedef struct xtensa_lookup_entry_struct
+{
+  const char *key;
+  union
+  {
+    xtensa_opcode opcode;		/* Internal opcode number.  */
+    xtensa_sysreg sysreg;		/* Internal sysreg number.  */
+    xtensa_state state;			/* Internal state number.  */
+    xtensa_interface intf;		/* Internal interface number.  */
+    xtensa_funcUnit fun;		/* Internal funcUnit number.  */
+  } u;
+} xtensa_lookup_entry;
+
+typedef struct xtensa_isa_internal_struct
+{
+  int is_big_endian;			/* Endianness.  */
+  int insn_size;			/* Maximum length in bytes.  */
+  int insnbuf_size;			/* Number of insnbuf_words.  */
+
+  int num_formats;
+  xtensa_format_internal *formats;
+  xtensa_format_decode_fn format_decode_fn;
+  xtensa_length_decode_fn length_decode_fn;
+
+  int num_slots;
+  xtensa_slot_internal *slots;
+
+  int num_fields;
+
+  int num_operands;
+  xtensa_operand_internal *operands;
+
+  int num_iclasses;
+  xtensa_iclass_internal *iclasses;
+
+  int num_opcodes;
+  xtensa_opcode_internal *opcodes;
+  xtensa_lookup_entry *opname_lookup_table;
+
+  int num_regfiles;
+  xtensa_regfile_internal *regfiles;
+
+  int num_states;
+  xtensa_state_internal *states;
+  xtensa_lookup_entry *state_lookup_table;
+
+  int num_sysregs;
+  xtensa_sysreg_internal *sysregs;
+  xtensa_lookup_entry *sysreg_lookup_table;
+
+  /* The current Xtensa ISA only supports 256 of each kind of sysreg so
+     we can get away with implementing lookups with tables indexed by
+     the register numbers.  If we ever allow larger sysreg numbers, this
+     may have to be reimplemented.  The first entry in the following
+     arrays corresponds to "special" registers and the second to "user"
+     registers.  */
+  int max_sysreg_num[2];
+  xtensa_sysreg *sysreg_table[2];
+
+  int num_interfaces;
+  xtensa_interface_internal *interfaces;
+  xtensa_lookup_entry *interface_lookup_table;
+
+  int num_funcUnits;
+  xtensa_funcUnit_internal *funcUnits;
+  xtensa_lookup_entry *funcUnit_lookup_table;
+
+} xtensa_isa_internal;
+
+extern int xtensa_isa_name_compare (const void *, const void *);
+
+extern xtensa_isa_status xtisa_errno;
+extern char xtisa_error_msg[];
+
+#endif /* !XTENSA_ISA_INTERNAL_H */
diff --git a/binutils-2.25/include/xtensa-isa.h b/binutils-2.25/include/xtensa-isa.h
new file mode 100644
index 00000000..c3c740da
--- /dev/null
+++ b/binutils-2.25/include/xtensa-isa.h
@@ -0,0 +1,813 @@
+/* Interface definition for configurable Xtensa ISA support.
+   Copyright 2003, 2004, 2005, 2006, 2008, 2010 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, 
+   USA.  */
+
+#ifndef XTENSA_LIBISA_H
+#define XTENSA_LIBISA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Version number: This is intended to help support code that works with
+   versions of this library from multiple Xtensa releases.  */
+
+#define XTENSA_ISA_VERSION 7000
+
+#ifndef uint32
+#define uint32 unsigned int
+#endif
+
+/* This file defines the interface to the Xtensa ISA library.  This
+   library contains most of the ISA-specific information for a
+   particular Xtensa processor.  For example, the set of valid
+   instructions, their opcode encodings and operand fields are all
+   included here.
+
+   This interface basically defines a number of abstract data types.
+
+   . an instruction buffer - for holding the raw instruction bits
+   . ISA info - information about the ISA as a whole
+   . instruction formats - instruction size and slot structure
+   . opcodes - information about individual instructions
+   . operands - information about register and immediate instruction operands
+   . stateOperands - information about processor state instruction operands
+   . interfaceOperands - information about interface instruction operands
+   . register files - register file information
+   . processor states - internal processor state information
+   . system registers - "special registers" and "user registers"
+   . interfaces - TIE interfaces that are external to the processor
+   . functional units - TIE shared functions
+
+   The interface defines a set of functions to access each data type.
+   With the exception of the instruction buffer, the internal
+   representations of the data structures are hidden.  All accesses must
+   be made through the functions defined here.  */
+
+typedef struct xtensa_isa_opaque { int unused; } *xtensa_isa;
+
+
+/* Most of the Xtensa ISA entities (e.g., opcodes, regfiles, etc.) are
+   represented here using sequential integers beginning with 0.  The
+   specific values are only fixed for a particular instantiation of an
+   xtensa_isa structure, so these values should only be used
+   internally.  */
+
+typedef int xtensa_opcode;
+typedef int xtensa_format;
+typedef int xtensa_regfile;
+typedef int xtensa_state;
+typedef int xtensa_sysreg;
+typedef int xtensa_interface;
+typedef int xtensa_funcUnit;
+
+
+/* Define a unique value for undefined items.  */
+
+#define XTENSA_UNDEFINED -1
+
+
+/* Overview of using this interface to decode/encode instructions:
+
+   Each Xtensa instruction is associated with a particular instruction
+   format, where the format defines a fixed number of slots for
+   operations.  The formats for the core Xtensa ISA have only one slot,
+   but FLIX instructions may have multiple slots.  Within each slot,
+   there is a single opcode and some number of associated operands.
+
+   The encoding and decoding functions operate on instruction buffers,
+   not on the raw bytes of the instructions.  The same instruction
+   buffer data structure is used for both entire instructions and
+   individual slots in those instructions -- the contents of a slot need
+   to be extracted from or inserted into the buffer for the instruction
+   as a whole.
+
+   Decoding an instruction involves first finding the format, which
+   identifies the number of slots, and then decoding each slot
+   separately.  A slot is decoded by finding the opcode and then using
+   the opcode to determine how many operands there are.  For example:
+
+   xtensa_insnbuf_from_chars
+   xtensa_format_decode
+   for each slot {
+     xtensa_format_get_slot
+     xtensa_opcode_decode
+     for each operand {
+       xtensa_operand_get_field
+       xtensa_operand_decode
+     }
+   }
+
+   Encoding an instruction is roughly the same procedure in reverse:
+
+   xtensa_format_encode
+   for each slot {
+     xtensa_opcode_encode
+     for each operand {
+       xtensa_operand_encode
+       xtensa_operand_set_field
+     }
+     xtensa_format_set_slot
+   }
+   xtensa_insnbuf_to_chars
+*/
+
+
+/* Error handling.  */
+
+/* Error codes.  The code for the most recent error condition can be
+   retrieved with the "errno" function.  For any result other than
+   xtensa_isa_ok, an error message containing additional information
+   about the problem can be retrieved using the "error_msg" function.
+   The error messages are stored in an internal buffer, which should
+   not be freed and may be overwritten by subsequent operations.  */
+
+typedef enum xtensa_isa_status_enum
+{
+  xtensa_isa_ok = 0,
+  xtensa_isa_bad_format,
+  xtensa_isa_bad_slot,
+  xtensa_isa_bad_opcode,
+  xtensa_isa_bad_operand,
+  xtensa_isa_bad_field,
+  xtensa_isa_bad_iclass,
+  xtensa_isa_bad_regfile,
+  xtensa_isa_bad_sysreg,
+  xtensa_isa_bad_state,
+  xtensa_isa_bad_interface,
+  xtensa_isa_bad_funcUnit,
+  xtensa_isa_wrong_slot,
+  xtensa_isa_no_field,
+  xtensa_isa_out_of_memory,
+  xtensa_isa_buffer_overflow,
+  xtensa_isa_internal_error,
+  xtensa_isa_bad_value
+} xtensa_isa_status;
+
+extern xtensa_isa_status
+xtensa_isa_errno (xtensa_isa isa);
+
+extern char *
+xtensa_isa_error_msg (xtensa_isa isa);
+
+
+
+/* Instruction buffers.  */
+
+typedef uint32 xtensa_insnbuf_word;
+typedef xtensa_insnbuf_word *xtensa_insnbuf;
+
+
+/* Get the size in "insnbuf_words" of the xtensa_insnbuf array.  */
+
+extern int
+xtensa_insnbuf_size (xtensa_isa isa); 
+
+
+/* Allocate an xtensa_insnbuf of the right size.  */
+
+extern xtensa_insnbuf
+xtensa_insnbuf_alloc (xtensa_isa isa);
+
+
+/* Release an xtensa_insnbuf.  */
+
+extern void
+xtensa_insnbuf_free (xtensa_isa isa, xtensa_insnbuf buf);
+
+
+/* Conversion between raw memory (char arrays) and our internal
+   instruction representation.  This is complicated by the Xtensa ISA's
+   variable instruction lengths.  When converting to chars, the buffer
+   must contain a valid instruction so we know how many bytes to copy;
+   thus, the "to_chars" function returns the number of bytes copied or
+   XTENSA_UNDEFINED on error.  The "from_chars" function first reads the
+   minimal number of bytes required to decode the instruction length and
+   then proceeds to copy the entire instruction into the buffer; if the
+   memory does not contain a valid instruction, it copies the maximum
+   number of bytes required for the longest Xtensa instruction.  The
+   "num_chars" argument may be used to limit the number of bytes that
+   can be read or written.  Otherwise, if "num_chars" is zero, the
+   functions may read or write past the end of the code.  */
+
+extern int
+xtensa_insnbuf_to_chars (xtensa_isa isa, const xtensa_insnbuf insn,
+			 unsigned char *cp, int num_chars);
+
+extern void
+xtensa_insnbuf_from_chars (xtensa_isa isa, xtensa_insnbuf insn,
+			   const unsigned char *cp, int num_chars);
+
+
+
+/* ISA information.  */
+
+/* Initialize the ISA information.  */
+
+extern xtensa_isa
+xtensa_isa_init (xtensa_isa_status *errno_p, char **error_msg_p);
+
+
+/* Deallocate an xtensa_isa structure.  */
+
+extern void
+xtensa_isa_free (xtensa_isa isa);
+
+
+/* Get the maximum instruction size in bytes.  */
+
+extern int
+xtensa_isa_maxlength (xtensa_isa isa); 
+
+
+/* Decode the length in bytes of an instruction in raw memory (not an
+   insnbuf).  This function reads only the minimal number of bytes
+   required to decode the instruction length.  Returns
+   XTENSA_UNDEFINED on error.  */
+
+extern int
+xtensa_isa_length_from_chars (xtensa_isa isa, const unsigned char *cp);
+
+
+/* Get the number of stages in the processor's pipeline.  The pipeline
+   stage values returned by other functions in this library will range
+   from 0 to N-1, where N is the value returned by this function.
+   Note that the stage numbers used here may not correspond to the
+   actual processor hardware, e.g., the hardware may have additional
+   stages before stage 0.  Returns XTENSA_UNDEFINED on error.  */
+
+extern int
+xtensa_isa_num_pipe_stages (xtensa_isa isa); 
+
+
+/* Get the number of various entities that are defined for this processor.  */
+
+extern int
+xtensa_isa_num_formats (xtensa_isa isa);
+
+extern int
+xtensa_isa_num_opcodes (xtensa_isa isa);
+
+extern int
+xtensa_isa_num_regfiles (xtensa_isa isa);
+
+extern int
+xtensa_isa_num_states (xtensa_isa isa);
+
+extern int
+xtensa_isa_num_sysregs (xtensa_isa isa);
+
+extern int
+xtensa_isa_num_interfaces (xtensa_isa isa);
+
+extern int
+xtensa_isa_num_funcUnits (xtensa_isa isa);
+
+
+
+/* Instruction formats.  */
+
+/* Get the name of a format.  Returns null on error.  */
+
+extern const char *
+xtensa_format_name (xtensa_isa isa, xtensa_format fmt);
+
+
+/* Given a format name, return the format number.  Returns
+   XTENSA_UNDEFINED if the name is not a valid format.  */
+
+extern xtensa_format
+xtensa_format_lookup (xtensa_isa isa, const char *fmtname);
+
+
+/* Decode the instruction format from a binary instruction buffer.
+   Returns XTENSA_UNDEFINED if the format is not recognized.  */
+
+extern xtensa_format
+xtensa_format_decode (xtensa_isa isa, const xtensa_insnbuf insn);
+
+
+/* Set the instruction format field(s) in a binary instruction buffer.
+   All the other fields are set to zero.  Returns non-zero on error.  */
+
+extern int
+xtensa_format_encode (xtensa_isa isa, xtensa_format fmt, xtensa_insnbuf insn);
+
+
+/* Find the length (in bytes) of an instruction.  Returns
+   XTENSA_UNDEFINED on error.  */
+
+extern int
+xtensa_format_length (xtensa_isa isa, xtensa_format fmt);
+
+
+/* Get the number of slots in an instruction.  Returns XTENSA_UNDEFINED
+   on error.  */
+
+extern int
+xtensa_format_num_slots (xtensa_isa isa, xtensa_format fmt);
+
+
+/* Get the opcode for a no-op in a particular slot.
+   Returns XTENSA_UNDEFINED on error.  */
+
+extern xtensa_opcode
+xtensa_format_slot_nop_opcode (xtensa_isa isa, xtensa_format fmt, int slot);
+
+
+/* Get the bits for a specified slot out of an insnbuf for the
+   instruction as a whole and put them into an insnbuf for that one
+   slot, and do the opposite to set a slot.  Return non-zero on error.  */
+
+extern int
+xtensa_format_get_slot (xtensa_isa isa, xtensa_format fmt, int slot,
+			const xtensa_insnbuf insn, xtensa_insnbuf slotbuf);
+
+extern int
+xtensa_format_set_slot (xtensa_isa isa, xtensa_format fmt, int slot,
+			xtensa_insnbuf insn, const xtensa_insnbuf slotbuf);
+
+
+
+/* Opcode information.  */
+
+/* Translate a mnemonic name to an opcode.  Returns XTENSA_UNDEFINED if
+   the name is not a valid opcode mnemonic.  */
+
+extern xtensa_opcode
+xtensa_opcode_lookup (xtensa_isa isa, const char *opname);
+
+
+/* Decode the opcode for one instruction slot from a binary instruction
+   buffer.  Returns the opcode or XTENSA_UNDEFINED if the opcode is
+   illegal.  */
+
+extern xtensa_opcode
+xtensa_opcode_decode (xtensa_isa isa, xtensa_format fmt, int slot,
+		      const xtensa_insnbuf slotbuf);
+
+
+/* Set the opcode field(s) for an instruction slot.  All other fields
+   in the slot are set to zero.  Returns non-zero if the opcode cannot
+   be encoded.  */
+
+extern int
+xtensa_opcode_encode (xtensa_isa isa, xtensa_format fmt, int slot,
+		      xtensa_insnbuf slotbuf, xtensa_opcode opc);
+
+
+/* Get the mnemonic name for an opcode.  Returns null on error.  */
+
+extern const char *
+xtensa_opcode_name (xtensa_isa isa, xtensa_opcode opc);
+
+
+/* Check various properties of opcodes.  These functions return 0 if
+   the condition is false, 1 if the condition is true, and
+   XTENSA_UNDEFINED on error.  The instructions are classified as
+   follows:
+
+   branch: conditional branch; may fall through to next instruction (B*)
+   jump: unconditional branch (J, JX, RET*, RF*)
+   loop: zero-overhead loop (LOOP*)
+   call: unconditional call; control returns to next instruction (CALL*)
+
+   For the opcodes that affect control flow in some way, the branch
+   target may be specified by an immediate operand or it may be an
+   address stored in a register.  You can distinguish these by
+   checking if the instruction has a PC-relative immediate
+   operand.  */
+
+extern int
+xtensa_opcode_is_branch (xtensa_isa isa, xtensa_opcode opc);
+
+extern int
+xtensa_opcode_is_jump (xtensa_isa isa, xtensa_opcode opc);
+
+extern int
+xtensa_opcode_is_loop (xtensa_isa isa, xtensa_opcode opc);
+
+extern int
+xtensa_opcode_is_call (xtensa_isa isa, xtensa_opcode opc);
+
+
+/* Find the number of ordinary operands, state operands, and interface
+   operands for an instruction.  These return XTENSA_UNDEFINED on
+   error.  */
+
+extern int
+xtensa_opcode_num_operands (xtensa_isa isa, xtensa_opcode opc);
+
+extern int
+xtensa_opcode_num_stateOperands (xtensa_isa isa, xtensa_opcode opc);
+
+extern int
+xtensa_opcode_num_interfaceOperands (xtensa_isa isa, xtensa_opcode opc);
+
+
+/* Get functional unit usage requirements for an opcode.  Each "use"
+   is identified by a <functional unit, pipeline stage> pair.  The
+   "num_funcUnit_uses" function returns the number of these "uses" or
+   XTENSA_UNDEFINED on error.  The "funcUnit_use" function returns
+   a pointer to a "use" pair or null on error.  */
+
+typedef struct xtensa_funcUnit_use_struct
+{
+  xtensa_funcUnit unit;
+  int stage;
+} xtensa_funcUnit_use;
+
+extern int
+xtensa_opcode_num_funcUnit_uses (xtensa_isa isa, xtensa_opcode opc);
+
+extern xtensa_funcUnit_use *
+xtensa_opcode_funcUnit_use (xtensa_isa isa, xtensa_opcode opc, int u);
+
+
+
+/* Operand information.  */
+
+/* Get the name of an operand.  Returns null on error.  */
+
+extern const char *
+xtensa_operand_name (xtensa_isa isa, xtensa_opcode opc, int opnd);
+
+
+/* Some operands are "invisible", i.e., not explicitly specified in
+   assembly language.  When assembling an instruction, you need not set
+   the values of invisible operands, since they are either hardwired or
+   derived from other field values.  The values of invisible operands
+   can be examined in the same way as other operands, but remember that
+   an invisible operand may get its value from another visible one, so
+   the entire instruction must be available before examining the
+   invisible operand values.  This function returns 1 if an operand is
+   visible, 0 if it is invisible, or XTENSA_UNDEFINED on error.  Note
+   that whether an operand is visible is orthogonal to whether it is
+   "implicit", i.e., whether it is encoded in a field in the
+   instruction.  */
+
+extern int
+xtensa_operand_is_visible (xtensa_isa isa, xtensa_opcode opc, int opnd);
+
+
+/* Check if an operand is an input ('i'), output ('o'), or inout ('m')
+   operand.  Note: The output operand of a conditional assignment
+   (e.g., movnez) appears here as an inout ('m') even if it is declared
+   in the TIE code as an output ('o'); this allows the compiler to
+   properly handle register allocation for conditional assignments.
+   Returns 0 on error.  */
+
+extern char
+xtensa_operand_inout (xtensa_isa isa, xtensa_opcode opc, int opnd);
+
+
+/* Get and set the raw (encoded) value of the field for the specified
+   operand.  The "set" function does not check if the value fits in the
+   field; that is done by the "encode" function below.  Both of these
+   functions return non-zero on error, e.g., if the field is not defined
+   for the specified slot.  */
+
+extern int
+xtensa_operand_get_field (xtensa_isa isa, xtensa_opcode opc, int opnd,
+			  xtensa_format fmt, int slot,
+			  const xtensa_insnbuf slotbuf, uint32 *valp);
+
+extern int 
+xtensa_operand_set_field (xtensa_isa isa, xtensa_opcode opc, int opnd,
+			  xtensa_format fmt, int slot,
+			  xtensa_insnbuf slotbuf, uint32 val);
+
+
+/* Encode and decode operands.  The raw bits in the operand field may
+   be encoded in a variety of different ways.  These functions hide
+   the details of that encoding.  The result values are returned through
+   the argument pointer.  The return value is non-zero on error.  */
+
+extern int
+xtensa_operand_encode (xtensa_isa isa, xtensa_opcode opc, int opnd,
+		       uint32 *valp);
+
+extern int
+xtensa_operand_decode (xtensa_isa isa, xtensa_opcode opc, int opnd,
+		       uint32 *valp);
+
+
+/* An operand may be either a register operand or an immediate of some
+   sort (e.g., PC-relative or not).  The "is_register" function returns
+   0 if the operand is an immediate, 1 if it is a register, and
+   XTENSA_UNDEFINED on error.  The "regfile" function returns the
+   regfile for a register operand, or XTENSA_UNDEFINED on error.  */
+
+extern int
+xtensa_operand_is_register (xtensa_isa isa, xtensa_opcode opc, int opnd);
+
+extern xtensa_regfile
+xtensa_operand_regfile (xtensa_isa isa, xtensa_opcode opc, int opnd);
+
+
+/* Register operands may span multiple consecutive registers, e.g., a
+   64-bit data type may occupy two 32-bit registers.  Only the first
+   register is encoded in the operand field.  This function specifies
+   the number of consecutive registers occupied by this operand.  For
+   non-register operands, the return value is undefined.  Returns
+   XTENSA_UNDEFINED on error.  */
+
+extern int
+xtensa_operand_num_regs (xtensa_isa isa, xtensa_opcode opc, int opnd);
+				 
+
+/* Some register operands do not completely identify the register being
+   accessed.  For example, the operand value may be added to an internal
+   state value.  By definition, this implies that the corresponding
+   regfile is not allocatable.  Unknown registers should generally be
+   treated with worst-case assumptions.  The function returns 0 if the
+   register value is unknown, 1 if known, and XTENSA_UNDEFINED on
+   error.  */
+
+extern int
+xtensa_operand_is_known_reg (xtensa_isa isa, xtensa_opcode opc, int opnd);
+
+
+/* Check if an immediate operand is PC-relative.  Returns 0 for register
+   operands and non-PC-relative immediates, 1 for PC-relative
+   immediates, and XTENSA_UNDEFINED on error.  */
+ 
+extern int
+xtensa_operand_is_PCrelative (xtensa_isa isa, xtensa_opcode opc, int opnd);
+
+
+/* For PC-relative offset operands, the interpretation of the offset may
+   vary between opcodes, e.g., is it relative to the current PC or that
+   of the next instruction?  The following functions are defined to
+   perform PC-relative relocations and to undo them (as in the
+   disassembler).  The "do_reloc" function takes the desired address
+   value and the PC of the current instruction and sets the value to the
+   corresponding PC-relative offset (which can then be encoded and
+   stored into the operand field).  The "undo_reloc" function takes the
+   unencoded offset value and the current PC and sets the value to the
+   appropriate address.  The return values are non-zero on error.  Note
+   that these functions do not replace the encode/decode functions; the
+   operands must be encoded/decoded separately and the encode functions
+   are responsible for detecting invalid operand values.  */
+
+extern int
+xtensa_operand_do_reloc (xtensa_isa isa, xtensa_opcode opc, int opnd,
+			 uint32 *valp, uint32 pc);
+
+extern int
+xtensa_operand_undo_reloc (xtensa_isa isa, xtensa_opcode opc, int opnd,
+			   uint32 *valp, uint32 pc);
+
+
+
+/* State Operands.  */
+
+/* Get the state accessed by a state operand.  Returns XTENSA_UNDEFINED
+   on error.  */
+
+extern xtensa_state
+xtensa_stateOperand_state (xtensa_isa isa, xtensa_opcode opc, int stOp);
+
+
+/* Check if a state operand is an input ('i'), output ('o'), or inout
+   ('m') operand.  Returns 0 on error.  */
+
+extern char
+xtensa_stateOperand_inout (xtensa_isa isa, xtensa_opcode opc, int stOp);
+
+
+
+/* Interface Operands.  */
+
+/* Get the external interface accessed by an interface operand.
+   Returns XTENSA_UNDEFINED on error.  */
+
+extern xtensa_interface
+xtensa_interfaceOperand_interface (xtensa_isa isa, xtensa_opcode opc,
+				   int ifOp);
+
+
+
+/* Register Files.  */
+
+/* Regfiles include both "real" regfiles and "views", where a view
+   allows a group of adjacent registers in a real "parent" regfile to be
+   viewed as a single register.  A regfile view has all the same
+   properties as its parent except for its (long) name, bit width, number
+   of entries, and default ctype.  You can use the parent function to
+   distinguish these two classes.  */
+
+/* Look up a regfile by either its name or its abbreviated "short name".
+   Returns XTENSA_UNDEFINED on error.  The "lookup_shortname" function
+   ignores "view" regfiles since they always have the same shortname as
+   their parents.  */
+
+extern xtensa_regfile
+xtensa_regfile_lookup (xtensa_isa isa, const char *name);
+
+extern xtensa_regfile
+xtensa_regfile_lookup_shortname (xtensa_isa isa, const char *shortname);
+
+
+/* Get the name or abbreviated "short name" of a regfile.
+   Returns null on error.  */
+
+extern const char *
+xtensa_regfile_name (xtensa_isa isa, xtensa_regfile rf);
+
+extern const char *
+xtensa_regfile_shortname (xtensa_isa isa, xtensa_regfile rf);
+
+
+/* Get the parent regfile of a "view" regfile.  If the regfile is not a
+   view, the result is the same as the input parameter.  Returns
+   XTENSA_UNDEFINED on error.  */
+
+extern xtensa_regfile
+xtensa_regfile_view_parent (xtensa_isa isa, xtensa_regfile rf);
+
+
+/* Get the bit width of a regfile or regfile view.
+   Returns XTENSA_UNDEFINED on error.  */
+
+extern int
+xtensa_regfile_num_bits (xtensa_isa isa, xtensa_regfile rf);
+
+
+/* Get the number of regfile entries.  Returns XTENSA_UNDEFINED on
+   error.  */
+
+extern int
+xtensa_regfile_num_entries (xtensa_isa isa, xtensa_regfile rf);
+
+
+
+/* Processor States.  */
+
+/* Look up a state by name.  Returns XTENSA_UNDEFINED on error.  */
+
+extern xtensa_state
+xtensa_state_lookup (xtensa_isa isa, const char *name);
+
+
+/* Get the name for a processor state.  Returns null on error.  */
+
+extern const char *
+xtensa_state_name (xtensa_isa isa, xtensa_state st);
+
+
+/* Get the bit width for a processor state.
+   Returns XTENSA_UNDEFINED on error.  */
+
+extern int
+xtensa_state_num_bits (xtensa_isa isa, xtensa_state st);
+
+
+/* Check if a state is exported from the processor core.  Returns 0 if
+   the condition is false, 1 if the condition is true, and
+   XTENSA_UNDEFINED on error.  */
+
+extern int
+xtensa_state_is_exported (xtensa_isa isa, xtensa_state st);
+
+
+/* Check for a "shared_or" state.  Returns 0 if the condition is false,
+   1 if the condition is true, and XTENSA_UNDEFINED on error.  */
+
+extern int
+xtensa_state_is_shared_or (xtensa_isa isa, xtensa_state st);
+
+
+
+/* Sysregs ("special registers" and "user registers").  */
+
+/* Look up a register by its number and whether it is a "user register"
+   or a "special register".  Returns XTENSA_UNDEFINED if the sysreg does
+   not exist.  */
+
+extern xtensa_sysreg
+xtensa_sysreg_lookup (xtensa_isa isa, int num, int is_user);
+
+
+/* Check if there exists a sysreg with a given name.
+   If not, this function returns XTENSA_UNDEFINED.  */
+
+extern xtensa_sysreg
+xtensa_sysreg_lookup_name (xtensa_isa isa, const char *name);
+
+
+/* Get the name of a sysreg.  Returns null on error.  */
+
+extern const char *
+xtensa_sysreg_name (xtensa_isa isa, xtensa_sysreg sysreg);
+
+
+/* Get the register number.  Returns XTENSA_UNDEFINED on error.  */
+
+extern int
+xtensa_sysreg_number (xtensa_isa isa, xtensa_sysreg sysreg);
+
+
+/* Check if a sysreg is a "special register" or a "user register".
+   Returns 0 for special registers, 1 for user registers and
+   XTENSA_UNDEFINED on error.  */
+
+extern int
+xtensa_sysreg_is_user (xtensa_isa isa, xtensa_sysreg sysreg);
+
+
+
+/* Interfaces.  */
+
+/* Find an interface by name.  The return value is XTENSA_UNDEFINED if
+   the specified interface is not found.  */
+
+extern xtensa_interface
+xtensa_interface_lookup (xtensa_isa isa, const char *ifname);
+
+
+/* Get the name of an interface.  Returns null on error.  */
+
+extern const char *
+xtensa_interface_name (xtensa_isa isa, xtensa_interface intf);
+
+
+/* Get the bit width for an interface.
+   Returns XTENSA_UNDEFINED on error.  */
+
+extern int
+xtensa_interface_num_bits (xtensa_isa isa, xtensa_interface intf);
+
+
+/* Check if an interface is an input ('i') or output ('o') with respect
+   to the Xtensa processor core.  Returns 0 on error.  */
+
+extern char
+xtensa_interface_inout (xtensa_isa isa, xtensa_interface intf);
+
+
+/* Check if accessing an interface has potential side effects.
+   Currently "data" interfaces have side effects and "control"
+   interfaces do not.  Returns 1 if there are side effects, 0 if not,
+   and XTENSA_UNDEFINED on error.  */
+
+extern int
+xtensa_interface_has_side_effect (xtensa_isa isa, xtensa_interface intf);
+
+
+/* Some interfaces may be related such that accessing one interface
+   has side effects on a set of related interfaces.  The interfaces
+   are partitioned into equivalence classes of related interfaces, and
+   each class is assigned a unique identifier number.  This function
+   returns the class identifier for an interface, or XTENSA_UNDEFINED
+   on error.  These identifiers can be compared to determine if two
+   interfaces are related; the specific values of the identifiers have
+   no particular meaning otherwise.  */
+
+extern int
+xtensa_interface_class_id (xtensa_isa isa, xtensa_interface intf);
+
+
+
+/* Functional Units.  */
+
+/* Find a functional unit by name.  The return value is XTENSA_UNDEFINED if
+   the specified unit is not found.  */
+
+extern xtensa_funcUnit
+xtensa_funcUnit_lookup (xtensa_isa isa, const char *fname);
+
+
+/* Get the name of a functional unit.  Returns null on error.  */
+
+extern const char *
+xtensa_funcUnit_name (xtensa_isa isa, xtensa_funcUnit fun);
+
+
+/* Functional units may be replicated.  See how many instances of a
+   particular function unit exist.  Returns XTENSA_UNDEFINED on error.  */
+
+extern int
+xtensa_funcUnit_num_copies (xtensa_isa isa, xtensa_funcUnit fun);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* XTENSA_LIBISA_H */