diff options
Diffstat (limited to 'binutils-2.25/gas/testsuite/gas/i386/x86-64-avx512er-rcigrd-intel.d')
| -rw-r--r-- | binutils-2.25/gas/testsuite/gas/i386/x86-64-avx512er-rcigrd-intel.d | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/binutils-2.25/gas/testsuite/gas/i386/x86-64-avx512er-rcigrd-intel.d b/binutils-2.25/gas/testsuite/gas/i386/x86-64-avx512er-rcigrd-intel.d new file mode 100644 index 00000000..818ac3b7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/i386/x86-64-avx512er-rcigrd-intel.d @@ -0,0 +1,32 @@ +#as: -mevexrcig=rd +#objdump: -dw -Mintel +#name: x86_64 AVX512ER rcig insns (Intel disassembly) +#source: x86-64-avx512er-rcig.s + +.*: +file format .* + + +Disassembly of section \.text: + +0+ <_start>: +[ ]*[a-f0-9]+:[ ]*62 02 7d 38 c8 f5[ ]*vexp2ps zmm30,zmm29,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 38 c8 f5[ ]*vexp2pd zmm30,zmm29,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 7d 38 ca f5[ ]*vrcp28ps zmm30,zmm29,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 38 ca f5[ ]*vrcp28pd zmm30,zmm29,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 15 30 cb f4[ ]*vrcp28ss xmm30,xmm29,xmm28,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 95 30 cb f4[ ]*vrcp28sd xmm30,xmm29,xmm28,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 7d 38 cc f5[ ]*vrsqrt28ps zmm30,zmm29,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 38 cc f5[ ]*vrsqrt28pd zmm30,zmm29,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 15 30 cd f4[ ]*vrsqrt28ss xmm30,xmm29,xmm28,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 95 30 cd f4[ ]*vrsqrt28sd xmm30,xmm29,xmm28,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 7d 38 c8 f5[ ]*vexp2ps zmm30,zmm29,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 38 c8 f5[ ]*vexp2pd zmm30,zmm29,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 7d 38 ca f5[ ]*vrcp28ps zmm30,zmm29,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 38 ca f5[ ]*vrcp28pd zmm30,zmm29,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 15 30 cb f4[ ]*vrcp28ss xmm30,xmm29,xmm28,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 95 30 cb f4[ ]*vrcp28sd xmm30,xmm29,xmm28,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 7d 38 cc f5[ ]*vrsqrt28ps zmm30,zmm29,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 fd 38 cc f5[ ]*vrsqrt28pd zmm30,zmm29,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 15 30 cd f4[ ]*vrsqrt28ss xmm30,xmm29,xmm28,\{sae\} +[ ]*[a-f0-9]+:[ ]*62 02 95 30 cd f4[ ]*vrsqrt28sd xmm30,xmm29,xmm28,\{sae\} +#pass |