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diff --git a/binutils-2.17/gas/doc/as.1 b/binutils-2.17/gas/doc/as.1 deleted file mode 100644 index 89e3b4c2..00000000 --- a/binutils-2.17/gas/doc/as.1 +++ /dev/null @@ -1,1109 +0,0 @@ -.\" Automatically generated by Pod::Man v1.37, Pod::Parser v1.32 -.\" -.\" Standard preamble: -.\" ======================================================================== -.de Sh \" Subsection heading -.br -.if t .Sp -.ne 5 -.PP -\fB\\$1\fR -.PP -.. -.de Sp \" Vertical space (when we can't use .PP) -.if t .sp .5v -.if n .sp -.. -.de Vb \" Begin verbatim text -.ft CW -.nf -.ne \\$1 -.. -.de Ve \" End verbatim text -.ft R -.fi -.. -.\" Set up some character translations and predefined strings. \*(-- will -.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left -.\" double quote, and \*(R" will give a right double quote. \*(C+ will -.\" give a nicer C++. Capital omega is used to do unbreakable dashes and -.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff, -.\" nothing in troff, for use with C<>. -.tr \(*W- -.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' -.ie n \{\ -. ds -- \(*W- -. ds PI pi -. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch -. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch -. ds L" "" -. ds R" "" -. ds C` "" -. ds C' "" -'br\} -.el\{\ -. ds -- \|\(em\| -. ds PI \(*p -. ds L" `` -. ds R" '' -'br\} -.\" -.\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index -.\" entries marked with X<> in POD. Of course, you'll have to process the -.\" output yourself in some meaningful fashion. -.if \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" -.. -. nr % 0 -. rr F -.\} -.\" -.\" For nroff, turn off justification. Always turn off hyphenation; it makes -.\" way too many mistakes in technical documents. -.hy 0 -.\" -.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). -.\" Fear. Run. Save yourself. No user-serviceable parts. -. \" fudge factors for nroff and troff -.if n \{\ -. ds #H 0 -. ds #V .8m -. ds #F .3m -. ds #[ \f1 -. ds #] \fP -.\} -.if t \{\ -. ds #H ((1u-(\\\\n(.fu%2u))*.13m) -. ds #V .6m -. ds #F 0 -. ds #[ \& -. ds #] \& -.\} -. \" simple accents for nroff and troff -.if n \{\ -. ds ' \& -. ds ` \& -. ds ^ \& -. ds , \& -. ds ~ ~ -. ds / -.\} -.if t \{\ -. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" -. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' -. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' -. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' -. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' -. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' -.\} -. \" troff and (daisy-wheel) nroff accents -.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' -.ds 8 \h'\*(#H'\(*b\h'-\*(#H' -.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] -.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' -.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' -.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] -.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] -.ds ae a\h'-(\w'a'u*4/10)'e -.ds Ae A\h'-(\w'A'u*4/10)'E -. \" corrections for vroff -.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' -.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' -. \" for low resolution devices (crt and lpr) -.if \n(.H>23 .if \n(.V>19 \ -\{\ -. ds : e -. ds 8 ss -. ds o a -. ds d- d\h'-1'\(ga -. ds D- D\h'-1'\(hy -. ds th \o'bp' -. ds Th \o'LP' -. ds ae ae -. ds Ae AE -.\} -.rm #[ #] #H #V #F C -.\" ======================================================================== -.\" -.IX Title "AS 1" -.TH AS 1 "2006-06-23" "binutils-2.17" "GNU Development Tools" -.SH "NAME" -AS \- the portable GNU assembler. -.SH "SYNOPSIS" -.IX Header "SYNOPSIS" -as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR] - [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR] [\fB\-f\fR] [\fB\-g\fR] [\fB\-\-gstabs\fR] - [\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-2\fR] [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] [\fB\-J\fR] - [\fB\-K\fR] [\fB\-L\fR] [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR] - [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR] - [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR] [\fB\-\-keep\-locals\fR] [\fB\-o\fR - \fIobjfile\fR] [\fB\-R\fR] [\fB\-\-reduce\-memory\-overheads\fR] [\fB\-\-statistics\fR] - [\fB\-v\fR] [\fB\-version\fR] [\fB\-\-version\fR] [\fB\-W\fR] [\fB\-\-warn\fR] - [\fB\-\-fatal\-warnings\fR] [\fB\-w\fR] [\fB\-x\fR] [\fB\-Z\fR] [\fB@\fR\fI\s-1FILE\s0\fR] - [\fB\-\-target\-help\fR] [\fItarget-options\fR] - [\fB\-\-\fR|\fIfiles\fR ...] -.PP -\&\fITarget Alpha options:\fR - [\fB\-m\fR\fIcpu\fR] - [\fB\-mdebug\fR | \fB\-no\-mdebug\fR] - [\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR] - [\fB\-F\fR] [\fB\-32addr\fR] -.PP -\&\fITarget \s-1ARC\s0 options:\fR - [\fB\-marc[5|6|7|8]\fR] - [\fB\-EB\fR|\fB\-EL\fR] -.PP -\&\fITarget \s-1ARM\s0 options:\fR - [\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]] - [\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]] - [\fB\-mfpu\fR=\fIfloating-point-format\fR] - [\fB\-mfloat\-abi\fR=\fIabi\fR] - [\fB\-meabi\fR=\fIver\fR] - [\fB\-mthumb\fR] - [\fB\-EB\fR|\fB\-EL\fR] - [\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR| - \fB\-mapcs\-reentrant\fR] - [\fB\-mthumb\-interwork\fR] [\fB\-k\fR] -.PP -\&\fITarget \s-1CRIS\s0 options:\fR - [\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR] - [\fB\-\-pic\fR] [\fB\-N\fR] - [\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR] - [\fB\-\-march=v0_v10\fR | \fB\-\-march=v10\fR | \fB\-\-march=v32\fR | \fB\-\-march=common_v10_v32\fR] -.PP -\&\fITarget D10V options:\fR - [\fB\-O\fR] -.PP -\&\fITarget D30V options:\fR - [\fB\-O\fR|\fB\-n\fR|\fB\-N\fR] -.PP -\&\fITarget i386 options:\fR - [\fB\-\-32\fR|\fB\-\-64\fR] [\fB\-n\fR] -.PP -\&\fITarget i960 options:\fR - [\fB\-ACA\fR|\fB\-ACA_A\fR|\fB\-ACB\fR|\fB\-ACC\fR|\fB\-AKA\fR|\fB\-AKB\fR| - \fB\-AKC\fR|\fB\-AMC\fR] - [\fB\-b\fR] [\fB\-no\-relax\fR] -.PP -\&\fITarget \s-1IA\-64\s0 options:\fR - [\fB\-mconstant\-gp\fR|\fB\-mauto\-pic\fR] - [\fB\-milp32\fR|\fB\-milp64\fR|\fB\-mlp64\fR|\fB\-mp64\fR] - [\fB\-mle\fR|\fBmbe\fR] - [\fB\-mtune=itanium1\fR|\fB\-mtune=itanium2\fR] - [\fB\-munwind\-check=warning\fR|\fB\-munwind\-check=error\fR] - [\fB\-mhint.b=ok\fR|\fB\-mhint.b=warning\fR|\fB\-mhint.b=error\fR] - [\fB\-x\fR|\fB\-xexplicit\fR] [\fB\-xauto\fR] [\fB\-xdebug\fR] -.PP -\&\fITarget \s-1IP2K\s0 options:\fR - [\fB\-mip2022\fR|\fB\-mip2022ext\fR] -.PP -\&\fITarget M32C options:\fR - [\fB\-m32c\fR|\fB\-m16c\fR] -.PP -\&\fITarget M32R options:\fR - [\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR| - \fB\-\-W[n]p\fR] -.PP -\&\fITarget M680X0 options:\fR - [\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...] -.PP -\&\fITarget M68HC11 options:\fR - [\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR] - [\fB\-mshort\fR|\fB\-mlong\fR] - [\fB\-mshort\-double\fR|\fB\-mlong\-double\fR] - [\fB\-\-force\-long\-branchs\fR] [\fB\-\-short\-branchs\fR] - [\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR] - [\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR] -.PP -\&\fITarget \s-1MCORE\s0 options:\fR - [\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR] - [\fB\-mcpu=[210|340]\fR] -.PP -\&\fITarget \s-1MIPS\s0 options:\fR - [\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization level\fR]] - [\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR] - [\fB\-non_shared\fR] [\fB\-xgot\fR] - [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR] - [\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR] - [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR] - [\fB\-mips64\fR] [\fB\-mips64r2\fR] - [\fB\-construct\-floats\fR] [\fB\-no\-construct\-floats\fR] - [\fB\-trap\fR] [\fB\-no\-break\fR] [\fB\-break\fR] [\fB\-no\-trap\fR] - [\fB\-mfix7000\fR] [\fB\-mno\-fix7000\fR] - [\fB\-mips16\fR] [\fB\-no\-mips16\fR] - [\fB\-mips3d\fR] [\fB\-no\-mips3d\fR] - [\fB\-mdmx\fR] [\fB\-no\-mdmx\fR] - [\fB\-mdsp\fR] [\fB\-mno\-dsp\fR] - [\fB\-mmt\fR] [\fB\-mno\-mt\fR] - [\fB\-mdebug\fR] [\fB\-no\-mdebug\fR] - [\fB\-mpdr\fR] [\fB\-mno\-pdr\fR] -.PP -\&\fITarget \s-1MMIX\s0 options:\fR - [\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR] - [\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR] - [\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR] - [\fB\-\-linker\-allocated\-gregs\fR] -.PP -\&\fITarget \s-1PDP11\s0 options:\fR - [\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR] - [\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR] - [\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR] -.PP -\&\fITarget picoJava options:\fR - [\fB\-mb\fR|\fB\-me\fR] -.PP -\&\fITarget PowerPC options:\fR - [\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR| - \fB\-m403\fR|\fB\-m405\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR| - \fB\-mbooke32\fR|\fB\-mbooke64\fR] - [\fB\-mcom\fR|\fB\-many\fR|\fB\-maltivec\fR] [\fB\-memb\fR] - [\fB\-mregnames\fR|\fB\-mno\-regnames\fR] - [\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR] - [\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR] - [\fB\-msolaris\fR|\fB\-mno\-solaris\fR] -.PP -\&\fITarget \s-1SPARC\s0 options:\fR - [\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR - \fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av9\fR|\fB\-Av9a\fR] - [\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR] [\fB\-bump\fR] - [\fB\-32\fR|\fB\-64\fR] -.PP -\&\fITarget \s-1TIC54X\s0 options:\fR - [\fB\-mcpu=54[123589]\fR|\fB\-mcpu=54[56]lp\fR] [\fB\-mfar\-mode\fR|\fB\-mf\fR] - [\fB\-merrors\-to\-file\fR \fI<filename>\fR|\fB\-me\fR \fI<filename>\fR] -.PP -\&\fITarget Z80 options:\fR - [\fB\-z80\fR] [\fB\-r800\fR] - [ \fB\-ignore\-undocumented\-instructions\fR] [\fB\-Wnud\fR] - [ \fB\-ignore\-unportable\-instructions\fR] [\fB\-Wnup\fR] - [ \fB\-warn\-undocumented\-instructions\fR] [\fB\-Wud\fR] - [ \fB\-warn\-unportable\-instructions\fR] [\fB\-Wup\fR] - [ \fB\-forbid\-undocumented\-instructions\fR] [\fB\-Fud\fR] - [ \fB\-forbid\-unportable\-instructions\fR] [\fB\-Fup\fR] -.PP -\&\fITarget Xtensa options:\fR - [\fB\-\-[no\-]text\-section\-literals\fR] [\fB\-\-[no\-]absolute\-literals\fR] - [\fB\-\-[no\-]target\-align\fR] [\fB\-\-[no\-]longcalls\fR] - [\fB\-\-[no\-]transform\fR] - [\fB\-\-rename\-section\fR \fIoldname\fR=\fInewname\fR] -.SH "DESCRIPTION" -.IX Header "DESCRIPTION" -\&\s-1GNU\s0 \fBas\fR is really a family of assemblers. -If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you -should find a fairly similar environment when you use it on another -architecture. Each version has much in common with the others, -including object file formats, most assembler directives (often called -\&\fIpseudo-ops\fR) and assembler syntax. -.PP -\&\fBas\fR is primarily intended to assemble the output of the -\&\s-1GNU\s0 C compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker -\&\f(CW\*(C`ld\*(C'\fR. Nevertheless, we've tried to make \fBas\fR -assemble correctly everything that other assemblers for the same -machine would assemble. -Any exceptions are documented explicitly. -This doesn't mean \fBas\fR always uses the same syntax as another -assembler for the same architecture; for example, we know of several -incompatible versions of 680x0 assembly language syntax. -.PP -Each time you run \fBas\fR it assembles exactly one source -program. The source program is made up of one or more files. -(The standard input is also a file.) -.PP -You give \fBas\fR a command line that has zero or more input file -names. The input files are read (from left file name to right). A -command line argument (in any position) that has no special meaning -is taken to be an input file name. -.PP -If you give \fBas\fR no file names it attempts to read one input file -from the \fBas\fR standard input, which is normally your terminal. You -may have to type \fBctl-D\fR to tell \fBas\fR there is no more program -to assemble. -.PP -Use \fB\-\-\fR if you need to explicitly name the standard input file -in your command line. -.PP -If the source is empty, \fBas\fR produces a small, empty object -file. -.PP -\&\fBas\fR may write warnings and error messages to the standard error -file (usually your terminal). This should not happen when a compiler -runs \fBas\fR automatically. Warnings report an assumption made so -that \fBas\fR could keep assembling a flawed program; errors report a -grave problem that stops the assembly. -.PP -If you are invoking \fBas\fR via the \s-1GNU\s0 C compiler, -you can use the \fB\-Wa\fR option to pass arguments through to the assembler. -The assembler arguments must be separated from each other (and the \fB\-Wa\fR) -by commas. For example: -.PP -.Vb 1 -\& gcc \-c \-g \-O \-Wa,\-alh,\-L file.c -.Ve -.PP -This passes two options to the assembler: \fB\-alh\fR (emit a listing to -standard output with high-level and assembly source) and \fB\-L\fR (retain -local symbols in the symbol table). -.PP -Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler -command-line options are automatically passed to the assembler by the compiler. -(You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see -precisely what options it passes to each compilation pass, including the -assembler.) -.SH "OPTIONS" -.IX Header "OPTIONS" -.IP "\fB@\fR\fIfile\fR" 4 -.IX Item "@file" -Read command-line options from \fIfile\fR. The options read are -inserted in place of the original @\fIfile\fR option. If \fIfile\fR -does not exist, or cannot be read, then the option will be treated -literally, and not removed. -.Sp -Options in \fIfile\fR are separated by whitespace. A whitespace -character may be included in an option by surrounding the entire -option in either single or double quotes. Any character (including a -backslash) may be included by prefixing the character to be included -with a backslash. The \fIfile\fR may itself contain additional -@\fIfile\fR options; any such options will be processed recursively. -.IP "\fB\-a[cdhlmns]\fR" 4 -.IX Item "-a[cdhlmns]" -Turn on listings, in any of a variety of ways: -.RS 4 -.IP "\fB\-ac\fR" 4 -.IX Item "-ac" -omit false conditionals -.IP "\fB\-ad\fR" 4 -.IX Item "-ad" -omit debugging directives -.IP "\fB\-ah\fR" 4 -.IX Item "-ah" -include high-level source -.IP "\fB\-al\fR" 4 -.IX Item "-al" -include assembly -.IP "\fB\-am\fR" 4 -.IX Item "-am" -include macro expansions -.IP "\fB\-an\fR" 4 -.IX Item "-an" -omit forms processing -.IP "\fB\-as\fR" 4 -.IX Item "-as" -include symbols -.IP "\fB=file\fR" 4 -.IX Item "=file" -set the name of the listing file -.RE -.RS 4 -.Sp -You may combine these options; for example, use \fB\-aln\fR for assembly -listing without forms processing. The \fB=file\fR option, if used, must be -the last one. By itself, \fB\-a\fR defaults to \fB\-ahls\fR. -.RE -.IP "\fB\-\-alternate\fR" 4 -.IX Item "--alternate" -Begin in alternate macro mode, see \fBAltmacro,,\f(CB\*(C`.altmacro\*(C'\fB\fR. -.IP "\fB\-D\fR" 4 -.IX Item "-D" -Ignored. This option is accepted for script compatibility with calls to -other assemblers. -.IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4 -.IX Item "--defsym sym=value" -Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file. -\&\fIvalue\fR must be an integer constant. As in C, a leading \fB0x\fR -indicates a hexadecimal value, and a leading \fB0\fR indicates an octal value. -.IP "\fB\-f\fR" 4 -.IX Item "-f" -\&\*(L"fast\*(R"\-\-\-skip whitespace and comment preprocessing (assume source is -compiler output). -.IP "\fB\-g\fR" 4 -.IX Item "-g" -.PD 0 -.IP "\fB\-\-gen\-debug\fR" 4 -.IX Item "--gen-debug" -.PD -Generate debugging information for each assembler source line using whichever -debug format is preferred by the target. This currently means either \s-1STABS\s0, -\&\s-1ECOFF\s0 or \s-1DWARF2\s0. -.IP "\fB\-\-gstabs\fR" 4 -.IX Item "--gstabs" -Generate stabs debugging information for each assembler line. This -may help debugging assembler code, if the debugger can handle it. -.IP "\fB\-\-gstabs+\fR" 4 -.IX Item "--gstabs+" -Generate stabs debugging information for each assembler line, with \s-1GNU\s0 -extensions that probably only gdb can handle, and that could make other -debuggers crash or refuse to read your program. This -may help debugging assembler code. Currently the only \s-1GNU\s0 extension is -the location of the current working directory at assembling time. -.IP "\fB\-\-gdwarf\-2\fR" 4 -.IX Item "--gdwarf-2" -Generate \s-1DWARF2\s0 debugging information for each assembler line. This -may help debugging assembler code, if the debugger can handle it. Note\-\-\-this -option is only supported by some targets, not all of them. -.IP "\fB\-\-help\fR" 4 -.IX Item "--help" -Print a summary of the command line options and exit. -.IP "\fB\-\-target\-help\fR" 4 -.IX Item "--target-help" -Print a summary of all target specific options and exit. -.IP "\fB\-I\fR \fIdir\fR" 4 -.IX Item "-I dir" -Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives. -.IP "\fB\-J\fR" 4 -.IX Item "-J" -Don't warn about signed overflow. -.IP "\fB\-K\fR" 4 -.IX Item "-K" -Issue warnings when difference tables altered for long displacements. -.IP "\fB\-L\fR" 4 -.IX Item "-L" -.PD 0 -.IP "\fB\-\-keep\-locals\fR" 4 -.IX Item "--keep-locals" -.PD -Keep (in the symbol table) local symbols. On traditional a.out systems -these start with \fBL\fR, but different systems have different local -label prefixes. -.IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4 -.IX Item "--listing-lhs-width=number" -Set the maximum width, in words, of the output data column for an assembler -listing to \fInumber\fR. -.IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4 -.IX Item "--listing-lhs-width2=number" -Set the maximum width, in words, of the output data column for continuation -lines in an assembler listing to \fInumber\fR. -.IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4 -.IX Item "--listing-rhs-width=number" -Set the maximum width of an input source line, as displayed in a listing, to -\&\fInumber\fR bytes. -.IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4 -.IX Item "--listing-cont-lines=number" -Set the maximum number of lines printed in a listing for a single line of input -to \fInumber\fR + 1. -.IP "\fB\-o\fR \fIobjfile\fR" 4 -.IX Item "-o objfile" -Name the object-file output from \fBas\fR \fIobjfile\fR. -.IP "\fB\-R\fR" 4 -.IX Item "-R" -Fold the data section into the text section. -.Sp -Set the default size of \s-1GAS\s0's hash tables to a prime number close to -\&\fInumber\fR. Increasing this value can reduce the length of time it takes the -assembler to perform its tasks, at the expense of increasing the assembler's -memory requirements. Similarly reducing this value can reduce the memory -requirements at the expense of speed. -.IP "\fB\-\-reduce\-memory\-overheads\fR" 4 -.IX Item "--reduce-memory-overheads" -This option reduces \s-1GAS\s0's memory requirements, at the expense of making the -assembly processes slower. Currently this switch is a synonym for -\&\fB\-\-hash\-size=4051\fR, but in the future it may have other effects as well. -.IP "\fB\-\-statistics\fR" 4 -.IX Item "--statistics" -Print the maximum space (in bytes) and total time (in seconds) used by -assembly. -.IP "\fB\-\-strip\-local\-absolute\fR" 4 -.IX Item "--strip-local-absolute" -Remove local absolute symbols from the outgoing symbol table. -.IP "\fB\-v\fR" 4 -.IX Item "-v" -.PD 0 -.IP "\fB\-version\fR" 4 -.IX Item "-version" -.PD -Print the \fBas\fR version. -.IP "\fB\-\-version\fR" 4 -.IX Item "--version" -Print the \fBas\fR version and exit. -.IP "\fB\-W\fR" 4 -.IX Item "-W" -.PD 0 -.IP "\fB\-\-no\-warn\fR" 4 -.IX Item "--no-warn" -.PD -Suppress warning messages. -.IP "\fB\-\-fatal\-warnings\fR" 4 -.IX Item "--fatal-warnings" -Treat warnings as errors. -.IP "\fB\-\-warn\fR" 4 -.IX Item "--warn" -Don't suppress warning messages or treat them as errors. -.IP "\fB\-w\fR" 4 -.IX Item "-w" -Ignored. -.IP "\fB\-x\fR" 4 -.IX Item "-x" -Ignored. -.IP "\fB\-Z\fR" 4 -.IX Item "-Z" -Generate an object file even after errors. -.IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4 -.IX Item "-- | files ..." -Standard input, or source files to assemble. -.PP -The following options are available when as is configured for -an \s-1ARC\s0 processor. -.IP "\fB\-marc[5|6|7|8]\fR" 4 -.IX Item "-marc[5|6|7|8]" -This option selects the core processor variant. -.IP "\fB\-EB | \-EL\fR" 4 -.IX Item "-EB | -EL" -Select either big-endian (\-EB) or little-endian (\-EL) output. -.PP -The following options are available when as is configured for the \s-1ARM\s0 -processor family. -.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4 -.IX Item "-mcpu=processor[+extension...]" -Specify which \s-1ARM\s0 processor variant is the target. -.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4 -.IX Item "-march=architecture[+extension...]" -Specify which \s-1ARM\s0 architecture variant is used by the target. -.IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4 -.IX Item "-mfpu=floating-point-format" -Select which Floating Point architecture is the target. -.IP "\fB\-mfloat\-abi=\fR\fIabi\fR" 4 -.IX Item "-mfloat-abi=abi" -Select which floating point \s-1ABI\s0 is in use. -.IP "\fB\-mthumb\fR" 4 -.IX Item "-mthumb" -Enable Thumb only instruction decoding. -.IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant\fR" 4 -.IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant" -Select which procedure calling convention is in use. -.IP "\fB\-EB | \-EL\fR" 4 -.IX Item "-EB | -EL" -Select either big-endian (\-EB) or little-endian (\-EL) output. -.IP "\fB\-mthumb\-interwork\fR" 4 -.IX Item "-mthumb-interwork" -Specify that the code has been generated with interworking between Thumb and -\&\s-1ARM\s0 code in mind. -.IP "\fB\-k\fR" 4 -.IX Item "-k" -Specify that \s-1PIC\s0 code has been generated. -.PP -See the info pages for documentation of the CRIS-specific options. -.PP -The following options are available when as is configured for -a D10V processor. -.IP "\fB\-O\fR" 4 -.IX Item "-O" -Optimize output by parallelizing instructions. -.PP -The following options are available when as is configured for a D30V -processor. -.IP "\fB\-O\fR" 4 -.IX Item "-O" -Optimize output by parallelizing instructions. -.IP "\fB\-n\fR" 4 -.IX Item "-n" -Warn when nops are generated. -.IP "\fB\-N\fR" 4 -.IX Item "-N" -Warn when a nop after a 32\-bit multiply instruction is generated. -.PP -The following options are available when as is configured for the -Intel 80960 processor. -.IP "\fB\-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | \-AKC | \-AMC\fR" 4 -.IX Item "-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC" -Specify which variant of the 960 architecture is the target. -.IP "\fB\-b\fR" 4 -.IX Item "-b" -Add code to collect statistics about branches taken. -.IP "\fB\-no\-relax\fR" 4 -.IX Item "-no-relax" -Do not alter compare-and-branch instructions for long displacements; -error if necessary. -.PP -The following options are available when as is configured for the -Ubicom \s-1IP2K\s0 series. -.IP "\fB\-mip2022ext\fR" 4 -.IX Item "-mip2022ext" -Specifies that the extended \s-1IP2022\s0 instructions are allowed. -.IP "\fB\-mip2022\fR" 4 -.IX Item "-mip2022" -Restores the default behaviour, which restricts the permitted instructions to -just the basic \s-1IP2022\s0 ones. -.PP -The following options are available when as is configured for the -Renesas M32C and M16C processors. -.IP "\fB\-m32c\fR" 4 -.IX Item "-m32c" -Assemble M32C instructions. -.IP "\fB\-m16c\fR" 4 -.IX Item "-m16c" -Assemble M16C instructions (the default). -.PP -The following options are available when as is configured for the -Renesas M32R (formerly Mitsubishi M32R) series. -.IP "\fB\-\-m32rx\fR" 4 -.IX Item "--m32rx" -Specify which processor in the M32R family is the target. The default -is normally the M32R, but this option changes it to the M32RX. -.IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4 -.IX Item "--warn-explicit-parallel-conflicts or --Wp" -Produce warning messages when questionable parallel constructs are -encountered. -.IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4 -.IX Item "--no-warn-explicit-parallel-conflicts or --Wnp" -Do not produce warning messages when questionable parallel constructs are -encountered. -.PP -The following options are available when as is configured for the -Motorola 68000 series. -.IP "\fB\-l\fR" 4 -.IX Item "-l" -Shorten references to undefined symbols, to one word instead of two. -.IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4 -.IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030" -.PD 0 -.IP "\fB| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\fR" 4 -.IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332" -.IP "\fB| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\fR" 4 -.IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200" -.PD -Specify what processor in the 68000 family is the target. The default -is normally the 68020, but this can be changed at configuration time. -.IP "\fB\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\fR" 4 -.IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882" -The target machine does (or does not) have a floating-point coprocessor. -The default is to assume a coprocessor for 68020, 68030, and cpu32. Although -the basic 68000 is not compatible with the 68881, a combination of the -two can be specified, since it's possible to do emulation of the -coprocessor instructions with the main processor. -.IP "\fB\-m68851 | \-mno\-68851\fR" 4 -.IX Item "-m68851 | -mno-68851" -The target machine does (or does not) have a memory-management -unit coprocessor. The default is to assume an \s-1MMU\s0 for 68020 and up. -.PP -For details about the \s-1PDP\-11\s0 machine dependent features options, -see \fBPDP\-11\-Options\fR. -.IP "\fB\-mpic | \-mno\-pic\fR" 4 -.IX Item "-mpic | -mno-pic" -Generate position-independent (or position\-dependent) code. The -default is \fB\-mpic\fR. -.IP "\fB\-mall\fR" 4 -.IX Item "-mall" -.PD 0 -.IP "\fB\-mall\-extensions\fR" 4 -.IX Item "-mall-extensions" -.PD -Enable all instruction set extensions. This is the default. -.IP "\fB\-mno\-extensions\fR" 4 -.IX Item "-mno-extensions" -Disable all instruction set extensions. -.IP "\fB\-m\fR\fIextension\fR \fB| \-mno\-\fR\fIextension\fR" 4 -.IX Item "-mextension | -mno-extension" -Enable (or disable) a particular instruction set extension. -.IP "\fB\-m\fR\fIcpu\fR" 4 -.IX Item "-mcpu" -Enable the instruction set extensions supported by a particular \s-1CPU\s0, and -disable all other extensions. -.IP "\fB\-m\fR\fImachine\fR" 4 -.IX Item "-mmachine" -Enable the instruction set extensions supported by a particular machine -model, and disable all other extensions. -.PP -The following options are available when as is configured for -a picoJava processor. -.IP "\fB\-mb\fR" 4 -.IX Item "-mb" -Generate \*(L"big endian\*(R" format output. -.IP "\fB\-ml\fR" 4 -.IX Item "-ml" -Generate \*(L"little endian\*(R" format output. -.PP -The following options are available when as is configured for the -Motorola 68HC11 or 68HC12 series. -.IP "\fB\-m68hc11 | \-m68hc12 | \-m68hcs12\fR" 4 -.IX Item "-m68hc11 | -m68hc12 | -m68hcs12" -Specify what processor is the target. The default is -defined by the configuration option when building the assembler. -.IP "\fB\-mshort\fR" 4 -.IX Item "-mshort" -Specify to use the 16\-bit integer \s-1ABI\s0. -.IP "\fB\-mlong\fR" 4 -.IX Item "-mlong" -Specify to use the 32\-bit integer \s-1ABI\s0. -.IP "\fB\-mshort\-double\fR" 4 -.IX Item "-mshort-double" -Specify to use the 32\-bit double \s-1ABI\s0. -.IP "\fB\-mlong\-double\fR" 4 -.IX Item "-mlong-double" -Specify to use the 64\-bit double \s-1ABI\s0. -.IP "\fB\-\-force\-long\-branchs\fR" 4 -.IX Item "--force-long-branchs" -Relative branches are turned into absolute ones. This concerns -conditional branches, unconditional branches and branches to a -sub routine. -.IP "\fB\-S | \-\-short\-branchs\fR" 4 -.IX Item "-S | --short-branchs" -Do not turn relative branchs into absolute ones -when the offset is out of range. -.IP "\fB\-\-strict\-direct\-mode\fR" 4 -.IX Item "--strict-direct-mode" -Do not turn the direct addressing mode into extended addressing mode -when the instruction does not support direct addressing mode. -.IP "\fB\-\-print\-insn\-syntax\fR" 4 -.IX Item "--print-insn-syntax" -Print the syntax of instruction in case of error. -.IP "\fB\-\-print\-opcodes\fR" 4 -.IX Item "--print-opcodes" -print the list of instructions with syntax and then exit. -.IP "\fB\-\-generate\-example\fR" 4 -.IX Item "--generate-example" -print an example of instruction for each possible instruction and then exit. -This option is only useful for testing \fBas\fR. -.PP -The following options are available when \fBas\fR is configured -for the \s-1SPARC\s0 architecture: -.IP "\fB\-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite\fR" 4 -.IX Item "-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite" -.PD 0 -.IP "\fB\-Av8plus | \-Av8plusa | \-Av9 | \-Av9a\fR" 4 -.IX Item "-Av8plus | -Av8plusa | -Av9 | -Av9a" -.PD -Explicitly select a variant of the \s-1SPARC\s0 architecture. -.Sp -\&\fB\-Av8plus\fR and \fB\-Av8plusa\fR select a 32 bit environment. -\&\fB\-Av9\fR and \fB\-Av9a\fR select a 64 bit environment. -.Sp -\&\fB\-Av8plusa\fR and \fB\-Av9a\fR enable the \s-1SPARC\s0 V9 instruction set with -UltraSPARC extensions. -.IP "\fB\-xarch=v8plus | \-xarch=v8plusa\fR" 4 -.IX Item "-xarch=v8plus | -xarch=v8plusa" -For compatibility with the Solaris v9 assembler. These options are -equivalent to \-Av8plus and \-Av8plusa, respectively. -.IP "\fB\-bump\fR" 4 -.IX Item "-bump" -Warn when the assembler switches to another architecture. -.PP -The following options are available when as is configured for the 'c54x -architecture. -.IP "\fB\-mfar\-mode\fR" 4 -.IX Item "-mfar-mode" -Enable extended addressing mode. All addresses and relocations will assume -extended addressing (usually 23 bits). -.IP "\fB\-mcpu=\fR\fI\s-1CPU_VERSION\s0\fR" 4 -.IX Item "-mcpu=CPU_VERSION" -Sets the \s-1CPU\s0 version being compiled for. -.IP "\fB\-merrors\-to\-file\fR \fI\s-1FILENAME\s0\fR" 4 -.IX Item "-merrors-to-file FILENAME" -Redirect error output to a file, for broken systems which don't support such -behaviour in the shell. -.PP -The following options are available when as is configured for -a \s-1MIPS\s0 processor. -.IP "\fB\-G\fR \fInum\fR" 4 -.IX Item "-G num" -This option sets the largest size of an object that can be referenced -implicitly with the \f(CW\*(C`gp\*(C'\fR register. It is only accepted for targets that -use \s-1ECOFF\s0 format, such as a DECstation running Ultrix. The default value is 8. -.IP "\fB\-EB\fR" 4 -.IX Item "-EB" -Generate \*(L"big endian\*(R" format output. -.IP "\fB\-EL\fR" 4 -.IX Item "-EL" -Generate \*(L"little endian\*(R" format output. -.IP "\fB\-mips1\fR" 4 -.IX Item "-mips1" -.PD 0 -.IP "\fB\-mips2\fR" 4 -.IX Item "-mips2" -.IP "\fB\-mips3\fR" 4 -.IX Item "-mips3" -.IP "\fB\-mips4\fR" 4 -.IX Item "-mips4" -.IP "\fB\-mips5\fR" 4 -.IX Item "-mips5" -.IP "\fB\-mips32\fR" 4 -.IX Item "-mips32" -.IP "\fB\-mips32r2\fR" 4 -.IX Item "-mips32r2" -.IP "\fB\-mips64\fR" 4 -.IX Item "-mips64" -.IP "\fB\-mips64r2\fR" 4 -.IX Item "-mips64r2" -.PD -Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level. -\&\fB\-mips1\fR is an alias for \fB\-march=r3000\fR, \fB\-mips2\fR is an -alias for \fB\-march=r6000\fR, \fB\-mips3\fR is an alias for -\&\fB\-march=r4000\fR and \fB\-mips4\fR is an alias for \fB\-march=r8000\fR. -\&\fB\-mips5\fR, \fB\-mips32\fR, \fB\-mips32r2\fR, \fB\-mips64\fR, and -\&\fB\-mips64r2\fR -correspond to generic -\&\fB\s-1MIPS\s0 V\fR, \fB\s-1MIPS32\s0\fR, \fB\s-1MIPS32\s0 Release 2\fR, \fB\s-1MIPS64\s0\fR, -and \fB\s-1MIPS64\s0 Release 2\fR -\&\s-1ISA\s0 processors, respectively. -.IP "\fB\-march=\fR\fI\s-1CPU\s0\fR" 4 -.IX Item "-march=CPU" -Generate code for a particular \s-1MIPS\s0 cpu. -.IP "\fB\-mtune=\fR\fIcpu\fR" 4 -.IX Item "-mtune=cpu" -Schedule and tune for a particular \s-1MIPS\s0 cpu. -.IP "\fB\-mfix7000\fR" 4 -.IX Item "-mfix7000" -.PD 0 -.IP "\fB\-mno\-fix7000\fR" 4 -.IX Item "-mno-fix7000" -.PD -Cause nops to be inserted if the read of the destination register -of an mfhi or mflo instruction occurs in the following two instructions. -.IP "\fB\-mdebug\fR" 4 -.IX Item "-mdebug" -.PD 0 -.IP "\fB\-no\-mdebug\fR" 4 -.IX Item "-no-mdebug" -.PD -Cause stabs-style debugging output to go into an ECOFF-style .mdebug -section instead of the standard \s-1ELF\s0 .stabs sections. -.IP "\fB\-mpdr\fR" 4 -.IX Item "-mpdr" -.PD 0 -.IP "\fB\-mno\-pdr\fR" 4 -.IX Item "-mno-pdr" -.PD -Control generation of \f(CW\*(C`.pdr\*(C'\fR sections. -.IP "\fB\-mgp32\fR" 4 -.IX Item "-mgp32" -.PD 0 -.IP "\fB\-mfp32\fR" 4 -.IX Item "-mfp32" -.PD -The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI\s0, but these -flags force a certain group of registers to be treated as 32 bits wide at -all times. \fB\-mgp32\fR controls the size of general-purpose registers -and \fB\-mfp32\fR controls the size of floating-point registers. -.IP "\fB\-mips16\fR" 4 -.IX Item "-mips16" -.PD 0 -.IP "\fB\-no\-mips16\fR" 4 -.IX Item "-no-mips16" -.PD -Generate code for the \s-1MIPS\s0 16 processor. This is equivalent to putting -\&\f(CW\*(C`.set mips16\*(C'\fR at the start of the assembly file. \fB\-no\-mips16\fR -turns off this option. -.IP "\fB\-mips3d\fR" 4 -.IX Item "-mips3d" -.PD 0 -.IP "\fB\-no\-mips3d\fR" 4 -.IX Item "-no-mips3d" -.PD -Generate code for the \s-1MIPS\-3D\s0 Application Specific Extension. -This tells the assembler to accept \s-1MIPS\-3D\s0 instructions. -\&\fB\-no\-mips3d\fR turns off this option. -.IP "\fB\-mdmx\fR" 4 -.IX Item "-mdmx" -.PD 0 -.IP "\fB\-no\-mdmx\fR" 4 -.IX Item "-no-mdmx" -.PD -Generate code for the \s-1MDMX\s0 Application Specific Extension. -This tells the assembler to accept \s-1MDMX\s0 instructions. -\&\fB\-no\-mdmx\fR turns off this option. -.IP "\fB\-mdsp\fR" 4 -.IX Item "-mdsp" -.PD 0 -.IP "\fB\-mno\-dsp\fR" 4 -.IX Item "-mno-dsp" -.PD -Generate code for the \s-1DSP\s0 Application Specific Extension. -This tells the assembler to accept \s-1DSP\s0 instructions. -\&\fB\-mno\-dsp\fR turns off this option. -.IP "\fB\-mmt\fR" 4 -.IX Item "-mmt" -.PD 0 -.IP "\fB\-mno\-mt\fR" 4 -.IX Item "-mno-mt" -.PD -Generate code for the \s-1MT\s0 Application Specific Extension. -This tells the assembler to accept \s-1MT\s0 instructions. -\&\fB\-mno\-mt\fR turns off this option. -.IP "\fB\-\-construct\-floats\fR" 4 -.IX Item "--construct-floats" -.PD 0 -.IP "\fB\-\-no\-construct\-floats\fR" 4 -.IX Item "--no-construct-floats" -.PD -The \fB\-\-no\-construct\-floats\fR option disables the construction of -double width floating point constants by loading the two halves of the -value into the two single width floating point registers that make up -the double width register. By default \fB\-\-construct\-floats\fR is -selected, allowing construction of these floating point constants. -.IP "\fB\-\-emulation=\fR\fIname\fR" 4 -.IX Item "--emulation=name" -This option causes \fBas\fR to emulate \fBas\fR configured -for some other target, in all respects, including output format (choosing -between \s-1ELF\s0 and \s-1ECOFF\s0 only), handling of pseudo-opcodes which may generate -debugging information or store symbol table information, and default -endianness. The available configuration names are: \fBmipsecoff\fR, -\&\fBmipself\fR, \fBmipslecoff\fR, \fBmipsbecoff\fR, \fBmipslelf\fR, -\&\fBmipsbelf\fR. The first two do not alter the default endianness from that -of the primary target for which the assembler was configured; the others change -the default to little\- or big-endian as indicated by the \fBb\fR or \fBl\fR -in the name. Using \fB\-EB\fR or \fB\-EL\fR will override the endianness -selection in any case. -.Sp -This option is currently supported only when the primary target -\&\fBas\fR is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target. -Furthermore, the primary target or others specified with -\&\fB\-\-enable\-targets=...\fR at configuration time must include support for -the other format, if both are to be available. For example, the Irix 5 -configuration includes support for both. -.Sp -Eventually, this option will support more configurations, with more -fine-grained control over the assembler's behavior, and will be supported for -more processors. -.IP "\fB\-nocpp\fR" 4 -.IX Item "-nocpp" -\&\fBas\fR ignores this option. It is accepted for compatibility with -the native tools. -.IP "\fB\-\-trap\fR" 4 -.IX Item "--trap" -.PD 0 -.IP "\fB\-\-no\-trap\fR" 4 -.IX Item "--no-trap" -.IP "\fB\-\-break\fR" 4 -.IX Item "--break" -.IP "\fB\-\-no\-break\fR" 4 -.IX Item "--no-break" -.PD -Control how to deal with multiplication overflow and division by zero. -\&\fB\-\-trap\fR or \fB\-\-no\-break\fR (which are synonyms) take a trap exception -(and only work for Instruction Set Architecture level 2 and higher); -\&\fB\-\-break\fR or \fB\-\-no\-trap\fR (also synonyms, and the default) take a -break exception. -.IP "\fB\-n\fR" 4 -.IX Item "-n" -When this option is used, \fBas\fR will issue a warning every -time it generates a nop instruction from a macro. -.PP -The following options are available when as is configured for -an MCore processor. -.IP "\fB\-jsri2bsr\fR" 4 -.IX Item "-jsri2bsr" -.PD 0 -.IP "\fB\-nojsri2bsr\fR" 4 -.IX Item "-nojsri2bsr" -.PD -Enable or disable the \s-1JSRI\s0 to \s-1BSR\s0 transformation. By default this is enabled. -The command line option \fB\-nojsri2bsr\fR can be used to disable it. -.IP "\fB\-sifilter\fR" 4 -.IX Item "-sifilter" -.PD 0 -.IP "\fB\-nosifilter\fR" 4 -.IX Item "-nosifilter" -.PD -Enable or disable the silicon filter behaviour. By default this is disabled. -The default can be overridden by the \fB\-sifilter\fR command line option. -.IP "\fB\-relax\fR" 4 -.IX Item "-relax" -Alter jump instructions for long displacements. -.IP "\fB\-mcpu=[210|340]\fR" 4 -.IX Item "-mcpu=[210|340]" -Select the cpu type on the target hardware. This controls which instructions -can be assembled. -.IP "\fB\-EB\fR" 4 -.IX Item "-EB" -Assemble for a big endian target. -.IP "\fB\-EL\fR" 4 -.IX Item "-EL" -Assemble for a little endian target. -.PP -See the info pages for documentation of the MMIX-specific options. -.PP -The following options are available when as is configured for -an Xtensa processor. -.IP "\fB\-\-text\-section\-literals | \-\-no\-text\-section\-literals\fR" 4 -.IX Item "--text-section-literals | --no-text-section-literals" -With \fB\-\-text\-section\-literals\fR, literal pools are interspersed -in the text section. The default is -\&\fB\-\-no\-text\-section\-literals\fR, which places literals in a -separate section in the output file. These options only affect literals -referenced via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals for -absolute mode \f(CW\*(C`L32R\*(C'\fR instructions are handled separately. -.IP "\fB\-\-absolute\-literals | \-\-no\-absolute\-literals\fR" 4 -.IX Item "--absolute-literals | --no-absolute-literals" -Indicate to the assembler whether \f(CW\*(C`L32R\*(C'\fR instructions use absolute -or PC-relative addressing. The default is to assume absolute addressing -if the Xtensa processor includes the absolute \f(CW\*(C`L32R\*(C'\fR addressing -option. Otherwise, only the PC-relative \f(CW\*(C`L32R\*(C'\fR mode can be used. -.IP "\fB\-\-target\-align | \-\-no\-target\-align\fR" 4 -.IX Item "--target-align | --no-target-align" -Enable or disable automatic alignment to reduce branch penalties at the -expense of some code density. The default is \fB\-\-target\-align\fR. -.IP "\fB\-\-longcalls | \-\-no\-longcalls\fR" 4 -.IX Item "--longcalls | --no-longcalls" -Enable or disable transformation of call instructions to allow calls -across a greater range of addresses. The default is -\&\fB\-\-no\-longcalls\fR. -.IP "\fB\-\-transform | \-\-no\-transform\fR" 4 -.IX Item "--transform | --no-transform" -Enable or disable all assembler transformations of Xtensa instructions. -The default is \fB\-\-transform\fR; -\&\fB\-\-no\-transform\fR should be used only in the rare cases when the -instructions must be exactly as specified in the assembly source. -.PP -The following options are available when as is configured for -a Z80 family processor. -.IP "\fB\-z80\fR" 4 -.IX Item "-z80" -Assemble for Z80 processor. -.IP "\fB\-r800\fR" 4 -.IX Item "-r800" -Assemble for R800 processor. -.IP "\fB\-ignore\-undocumented\-instructions\fR" 4 -.IX Item "-ignore-undocumented-instructions" -.PD 0 -.IP "\fB\-Wnud\fR" 4 -.IX Item "-Wnud" -.PD -Assemble undocumented Z80 instructions that also work on R800 without warning. -.IP "\fB\-ignore\-unportable\-instructions\fR" 4 -.IX Item "-ignore-unportable-instructions" -.PD 0 -.IP "\fB\-Wnup\fR" 4 -.IX Item "-Wnup" -.PD -Assemble all undocumented Z80 instructions without warning. -.IP "\fB\-warn\-undocumented\-instructions\fR" 4 -.IX Item "-warn-undocumented-instructions" -.PD 0 -.IP "\fB\-Wud\fR" 4 -.IX Item "-Wud" -.PD -Issue a warning for undocumented Z80 instructions that also work on R800. -.IP "\fB\-warn\-unportable\-instructions\fR" 4 -.IX Item "-warn-unportable-instructions" -.PD 0 -.IP "\fB\-Wup\fR" 4 -.IX Item "-Wup" -.PD -Issue a warning for undocumented Z80 instructions that do notwork on R800. -.IP "\fB\-forbid\-undocumented\-instructions\fR" 4 -.IX Item "-forbid-undocumented-instructions" -.PD 0 -.IP "\fB\-Fud\fR" 4 -.IX Item "-Fud" -.PD -Treat all undocumented instructions as errors. -.IP "\fB\-forbid\-unportable\-instructions\fR" 4 -.IX Item "-forbid-unportable-instructions" -.PD 0 -.IP "\fB\-Fup\fR" 4 -.IX Item "-Fup" -.PD -Treat undocumented Z80 intructions that do notwork on R800 as errors. -.SH "SEE ALSO" -.IX Header "SEE ALSO" -\&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR. -.SH "COPYRIGHT" -.IX Header "COPYRIGHT" -Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 Free Software Foundation, Inc. -.PP -Permission is granted to copy, distribute and/or modify this document -under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1 -or any later version published by the Free Software Foundation; -with no Invariant Sections, with no Front-Cover Texts, and with no -Back-Cover Texts. A copy of the license is included in the -section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". |