/* * opyright (C) 2011 Samsung Electronics * * Authors: Adam Hampson * Erik Gilling * * Additional contributions by : Shankar Bandal * Dharam Kumar * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * */ #ifndef _SII9234_DRIVER_H_ #define _SII9234_DRIVER_H_ /*Flag for MHL Factory test*/ #ifndef CONFIG_SS_FACTORY #define CONFIG_SS_FACTORY 1 #endif #ifndef __CONFIG_TMDS_OFFON_WORKAROUND__ #define __CONFIG_TMDS_OFFON_WORKAROUND__ #endif #ifndef __CONFIG_USE_TIMER__ #define __CONFIG_USE_TIMER__ #endif #ifndef CONFIG_SII9234_RCP #define CONFIG_SII9234_RCP 1 #include #endif #include #ifdef CONFIG_SAMSUNG_MHL_9290 #include #endif #ifdef CONFIG_SAMSUNG_SMARTDOCK #define ADC_SMARTDOCK 0x10 /* 40.2K ohm */ #endif #define T_WAIT_TIMEOUT_RGND_INT 2000 #define T_WAIT_TIMEOUT_DISC_INT 1000 #define T_WAIT_TIMEOUT_RSEN_INT 200 #define T_SRC_VBUS_CBUS_TO_STABLE 200 #define T_SRC_WAKE_PULSE_WIDTH_1 19 #define T_SRC_WAKE_PULSE_WIDTH_2 60 #define T_SRC_WAKE_TO_DISCOVER 500 #define T_SRC_VBUS_CBUS_T0_STABLE 500 #define T_WAIT_TIMEOUT_WAKE_PULSE (T_SRC_WAKE_PULSE_WIDTH_1 * 6 \ + T_SRC_WAKE_PULSE_WIDTH_2 \ + T_SRC_WAKE_TO_DISCOVER \ + 150) #define T_SRC_CBUS_FLOAT 100 #define T_HPD_WIDTH 100 #define T_SRC_RXSENSE_DEGLITCH 110 #define T_SRC_CBUS_DEGLITCH 2 /* MHL TX Addr 0x72 Registers */ #define MHL_TX_IDL_REG 0x02 #define MHL_TX_IDH_REG 0x03 #define MHL_TX_REV_REG 0x04 #define MHL_TX_SRST 0x05 #define MHL_TX_INTR1_REG 0x71 #define MHL_TX_INTR2_REG 0x72 /* Not Documented */ #define MHL_TX_INTR3_REG 0x73 /* Not Documented */ #define MHL_TX_INTR4_REG 0x74 #define MHL_TX_INTR1_ENABLE_REG 0x75 #define MHL_TX_INTR2_ENABLE_REG 0x76 /* Not Documented */ #define MHL_TX_INTR3_ENABLE_REG 0x77 /* Not Documented */ #define MHL_TX_INTR4_ENABLE_REG 0x78 #define MHL_TX_INT_CTRL_REG 0x79 #define MHL_TX_TMDS_CCTRL 0x80 #define MHL_TX_DISC_CTRL1_REG 0x90 #define MHL_TX_DISC_CTRL2_REG 0x91 #define MHL_TX_DISC_CTRL3_REG 0x92 #define MHL_TX_DISC_CTRL4_REG 0x93 #define MHL_TX_DISC_CTRL5_REG 0x94 #define MHL_TX_DISC_CTRL6_REG 0x95 #define MHL_TX_DISC_CTRL7_REG 0x96 #define MHL_TX_DISC_CTRL8_REG 0x97 #define MHL_TX_STAT1_REG 0x98 #define MHL_TX_STAT2_REG 0x99 #define MHL_TX_MHLTX_CTL1_REG 0xA0 #define MHL_TX_MHLTX_CTL2_REG 0xA1 #define MHL_TX_MHLTX_CTL4_REG 0xA3 #define MHL_TX_MHLTX_CTL6_REG 0xA5 #define MHL_TX_MHLTX_CTL7_REG 0xA6 /* MHL TX SYS STAT Registers */ #define MHL_TX_SYSSTAT_REG 0x09 /* MHL TX SYS STAT Register Bits */ #define RSEN_STATUS (1<<2) /* MHL TX INTR4 Register Bits */ #define RGND_READY_INT (1<<6) #define VBUS_LOW_INT (1<<5) #define CBUS_LKOUT_INT (1<<4) #define MHL_DISC_FAIL_INT (1<<3) #define MHL_EST_INT (1<<2) /* MHL TX INTR4_ENABLE 0x78 Register Bits */ #define RGND_READY_MASK (1<<6) #define CBUS_LKOUT_MASK (1<<4) #define MHL_DISC_FAIL_MASK (1<<3) #define MHL_EST_MASK (1<<2) /* MHL TX INTR1 Register Bits*/ #define HPD_CHANGE_INT (1<<6) #define RSEN_CHANGE_INT (1<<5) /* MHL TX INTR1_ENABLE 0x75 Register Bits*/ #define HPD_CHANGE_INT_MASK (1<<6) #define RSEN_CHANGE_INT_MASK (1<<5) /* CBUS_INT_1_ENABLE: CBUS Transaction Interrupt #1 Mask */ #define CBUS_INTR1_ENABLE_REG 0x09 #define CBUS_INTR2_ENABLE_REG 0x1F /* CBUS Interrupt Status Registers*/ #define CBUS_INT_STATUS_1_REG 0x08 #define CBUS_INT_STATUS_2_REG 0x1E /* CBUS INTR1 STATUS Register bits */ #define MSC_RESP_ABORT (1<<6) #define MSC_REQ_ABORT (1<<5) #define MSC_REQ_DONE (1<<4) #define MSC_MSG_RECD (1<<3) #define CBUS_DDC_ABORT (1<<2) /* CBUS INTR1 STATUS 0x09 Enable Mask*/ #define MSC_RESP_ABORT_MASK (1<<6) #define MSC_REQ_ABORT_MASK (1<<5) #define MSC_REQ_DONE_MASK (1<<4) #define MSC_MSG_RECD_MASK (1<<3) #define CBUS_DDC_ABORT_MASK (1<<2) /* CBUS INTR2 STATUS Register bits */ #define WRT_STAT_RECD (1<<3) #define SET_INT_RECD (1<<2) #define WRT_BURST_RECD (1<<0) /* CBUS INTR2 STATUS 0x1F Enable Mask*/ #define WRT_STAT_RECD_MASK (1<<3) #define SET_INT_RECD_MASK (1<<2) #define WRT_BURST_RECD_MASK (1<<0) #define MHL_INT_EDID_CHG (1<<1) #define MHL_RCHANGE_INT 0x20 #define MHL_DCHANGE_INT 0x21 #define MHL_INT_DCAP_CHG (1<<0) #define MHL_INT_DSCR_CHG (1<<1) #define MHL_INT_REQ_WRT (1<<2) #define MHL_INT_GRT_WRT (1<<3) /* CBUS Control Registers*/ /* Retry count for all MSC commands*/ #define MSC_RETRY_FAIL_LIM_REG 0x1D #define MSC_REQ_ABORT_REASON_REG 0x0D #define MSC_RESP_ABORT_REASON_REG 0x0E /* MSC Requestor/Responder Abort Reason Register bits*/ #define ABORT_BY_PEER (1<<7) #define UNDEF_CMD (1<<3) #define TIMEOUT (1<<2) #define PROTO_ERROR (1<<1) #define MAX_FAIL (1<<0) #define REG_CBUS_INTR_STATUS 0x08 /* Responder aborted DDC command at translation layer */ #define BIT_DDC_ABORT (1<<2) /* Responder sent a VS_MSG packet (response data or command.) */ #define BIT_MSC_MSG_RCV (1<<3) /* Responder sent ACK packet (not VS_MSG) */ #define BIT_MSC_XFR_DONE (1<<4) /* Command send aborted on TX side */ #define BIT_MSC_XFR_ABORT (1<<5) #define BIT_MSC_ABORT (1<<6) /* Set HPD came from Downstream, */ #define SET_HPD_DOWNSTREAM (1<<6) /* MHL TX DISC1 Register Bits */ #define DISC_EN (1<<0) /* MHL TX DISC2 Register Bits */ #define SKIP_GND (1<<6) #define ATT_THRESH_SHIFT 0x04 #define ATT_THRESH_MASK (0x03 << ATT_THRESH_SHIFT) #define USB_D_OEN (1<<3) #define DEGLITCH_TIME_MASK 0x07 #define DEGLITCH_TIME_2MS 0 #define DEGLITCH_TIME_4MS 1 #define DEGLITCH_TIME_8MS 2 #define DEGLITCH_TIME_16MS 3 #define DEGLITCH_TIME_40MS 4 #define DEGLITCH_TIME_50MS 5 #define DEGLITCH_TIME_60MS 6 #define DEGLITCH_TIME_128MS 7 #define DISC_CTRL3_COMM_IMME (1<<7) #define DISC_CTRL3_FORCE_MHL (1<<6) #define DISC_CTRL3_FORCE_USB (1<<4) #define DISC_CTRL3_USB_EN (1<<3) /* MHL TX DISC4 0x93 Register Bits*/ #define CBUS_DISC_PUP_SEL_SHIFT 6 #define CBUS_DISC_PUP_SEL_MASK (3<