From 1c0c13eb935c95fd2ca0b0aca6dd4860487fb242 Mon Sep 17 00:00:00 2001
From: Aurelien Jarno <aurelien@aurel32.net>
Date: Tue, 25 Sep 2007 15:40:12 +0200
Subject: [MIPS] Add support for BCM47XX CPUs.

Note that the BCM4710 does not support the wait instruction, this
is not a mistake in the code.

It originally comes from the OpenWrt patches.

Cc: Michael Buesch <mb@bu3sch.de>
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Florian Schirmer <jolt@tuxbox.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
 include/asm-mips/cpu.h | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

(limited to 'include/asm-mips/cpu.h')

diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 3857358fb6d..d67f43b0996 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -105,6 +105,13 @@
 
 #define PRID_IMP_SR71000        0x0400
 
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
+ */
+
+#define PRID_IMP_BCM4710	0x4000
+#define PRID_IMP_BCM3302	0x9000
+
 /*
  * Definitions for 7:0 on legacy processors
  */
@@ -217,8 +224,9 @@
 #define CPU_R14000		64
 #define CPU_LOONGSON1           65
 #define CPU_LOONGSON2           66
-
-#define CPU_LAST		66
+#define CPU_BCM3302		67
+#define CPU_BCM4710		68
+#define CPU_LAST		68
 
 /*
  * ISA Level encodings
-- 
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