From 483ba50bd41d14d5325d6cd9935de86a982d08a2 Mon Sep 17 00:00:00 2001 From: Michael Chan Date: Mon, 25 Apr 2005 15:14:03 -0700 Subject: [TG3]: Fix bug in tg3_rx() This patch fixes a bug that causes tg3_has_work() to always return 1. rx work is determined by comparing tp->rx_rcb_ptr with the current hw producer index. The hw producer index is modulo the ring size, but tp- >rx_rcb_ptr is a free running counter that goes up beyond the ring size. After the ring wraps around once, tg3_has_work() will always return 1. The fix is to always do modulo arithmetic on tp->rx_rcb_ptr. Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/tg3.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 10d476153ee..e53c1dc58d0 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -2686,8 +2686,8 @@ static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag) static int tg3_rx(struct tg3 *tp, int budget) { u32 work_mask; - u32 rx_rcb_ptr = tp->rx_rcb_ptr; - u16 hw_idx, sw_idx; + u32 sw_idx = tp->rx_rcb_ptr; + u16 hw_idx; int received; hw_idx = tp->hw_status->idx[0].rx_producer; @@ -2696,7 +2696,6 @@ static int tg3_rx(struct tg3 *tp, int budget) * the opaque cookie. */ rmb(); - sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp); work_mask = 0; received = 0; while (sw_idx != hw_idx && budget > 0) { @@ -2801,14 +2800,13 @@ static int tg3_rx(struct tg3 *tp, int budget) next_pkt: (*post_ptr)++; next_pkt_nopost: - rx_rcb_ptr++; - sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp); + sw_idx++; + sw_idx %= TG3_RX_RCB_RING_SIZE(tp); } /* ACK the status ring. */ - tp->rx_rcb_ptr = rx_rcb_ptr; - tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, - (rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp))); + tp->rx_rcb_ptr = sw_idx; + tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx); /* Refill RX ring(s). */ if (work_mask & RXD_OPAQUE_RING_STD) { -- cgit v1.2.3 From 52f6d697dc0f2c039e8413e780b0f45ddf8161fc Mon Sep 17 00:00:00 2001 From: Michael Chan Date: Mon, 25 Apr 2005 15:14:32 -0700 Subject: [TG3]: Refresh hw index in tg3_rx() This patch refreshes the hw rx producer in tg3_rx() so that additional work posted by the hardware can be processed. Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/tg3.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index e53c1dc58d0..92b0e497513 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -2802,6 +2802,12 @@ next_pkt: next_pkt_nopost: sw_idx++; sw_idx %= TG3_RX_RCB_RING_SIZE(tp); + + /* Refresh hw_idx to see if there is new work */ + if (sw_idx == hw_idx) { + hw_idx = tp->hw_status->idx[0].rx_producer; + rmb(); + } } /* ACK the status ring. */ -- cgit v1.2.3 From 04237dddd14375fce1df4bfb1be92a35aa1c247f Mon Sep 17 00:00:00 2001 From: Michael Chan Date: Mon, 25 Apr 2005 15:17:17 -0700 Subject: [TG3]: Fix tg3_restart_ints() tg3_restart_ints() is called to re-enable interrupts after tg3_poll() has finished all the work. It calls tg3_cond_int() to force an interrupt if the status block updated bit is set. The updated bit will be set if there is a new status block update sometime during tg3_poll() and it can be very often. The worst part is that even if all the work has been processed, the updated bit remains set and an interrupt will be forced unnecessarily. The fix is to call tg3_has_work() instead to determine if new work is posted before forcing an interrupt. The way to force an interrupt is also changed to use "coalesce_now" instead of "SETINT". The former is generally a safer way to force the interrupt. Also deleted the first parameter to tg3_has_work() which is unused. Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/tg3.c | 53 ++++++++++++++++++++++++++++------------------------- 1 file changed, 28 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 92b0e497513..903d0ced7dd 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -426,9 +426,30 @@ static void tg3_enable_ints(struct tg3 *tp) tg3_cond_int(tp); } +static inline unsigned int tg3_has_work(struct tg3 *tp) +{ + struct tg3_hw_status *sblk = tp->hw_status; + unsigned int work_exists = 0; + + /* check for phy events */ + if (!(tp->tg3_flags & + (TG3_FLAG_USE_LINKCHG_REG | + TG3_FLAG_POLL_SERDES))) { + if (sblk->status & SD_STATUS_LINK_CHG) + work_exists = 1; + } + /* check for RX/TX work to do */ + if (sblk->idx[0].tx_consumer != tp->tx_cons || + sblk->idx[0].rx_producer != tp->rx_rcb_ptr) + work_exists = 1; + + return work_exists; +} + /* tg3_restart_ints - * similar to tg3_enable_ints, but it can return without flushing the - * PIO write which reenables interrupts + * similar to tg3_enable_ints, but it accurately determines whether there + * is new work pending and can return without flushing the PIO write + * which reenables interrupts */ static void tg3_restart_ints(struct tg3 *tp) { @@ -437,7 +458,9 @@ static void tg3_restart_ints(struct tg3 *tp) tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000); mmiowb(); - tg3_cond_int(tp); + if (tg3_has_work(tp)) + tw32(HOSTCC_MODE, tp->coalesce_mode | + (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW)); } static inline void tg3_netif_stop(struct tg3 *tp) @@ -2891,26 +2914,6 @@ static int tg3_poll(struct net_device *netdev, int *budget) return (done ? 0 : 1); } -static inline unsigned int tg3_has_work(struct net_device *dev, struct tg3 *tp) -{ - struct tg3_hw_status *sblk = tp->hw_status; - unsigned int work_exists = 0; - - /* check for phy events */ - if (!(tp->tg3_flags & - (TG3_FLAG_USE_LINKCHG_REG | - TG3_FLAG_POLL_SERDES))) { - if (sblk->status & SD_STATUS_LINK_CHG) - work_exists = 1; - } - /* check for RX/TX work to do */ - if (sblk->idx[0].tx_consumer != tp->tx_cons || - sblk->idx[0].rx_producer != tp->rx_rcb_ptr) - work_exists = 1; - - return work_exists; -} - /* MSI ISR - No need to check for interrupt sharing and no need to * flush status block and interrupt mailbox. PCI ordering rules * guarantee that MSI will arrive after the status block. @@ -2934,7 +2937,7 @@ static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs) tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); sblk->status &= ~SD_STATUS_UPDATED; - if (likely(tg3_has_work(dev, tp))) + if (likely(tg3_has_work(tp))) netif_rx_schedule(dev); /* schedule NAPI poll */ else { /* no work, re-enable interrupts @@ -2981,7 +2984,7 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs) tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); sblk->status &= ~SD_STATUS_UPDATED; - if (likely(tg3_has_work(dev, tp))) + if (likely(tg3_has_work(tp))) netif_rx_schedule(dev); /* schedule NAPI poll */ else { /* no work, shared interrupt perhaps? re-enable -- cgit v1.2.3