From d08e44570ed611c527a1062eb4f8c6ac61832e6e Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 19 May 2011 18:48:01 +0800 Subject: powerpc/fsl_lbc: Add workaround for ELBC-A001 erratum Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus monitor timeout. Set the local bus monitor timeout value to the maximum by setting LBCR[BMT] = 0 and LBCR[BMTPS] = 0xF. Signed-off-by: Shengzhou Liu Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/fsl_lbc.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/powerpc/include') diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 5c1bf346674..8a0b5ece8f7 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -157,6 +157,8 @@ struct fsl_lbc_regs { #define LBCR_EPAR_SHIFT 16 #define LBCR_BMT 0x0000FF00 #define LBCR_BMT_SHIFT 8 +#define LBCR_BMTPS 0x0000000F +#define LBCR_BMTPS_SHIFT 0 #define LBCR_INIT 0x00040000 __be32 lcrr; /**< Clock Ratio Register */ #define LCRR_DBYP 0x80000000 -- cgit v1.2.3