From 49535a952bb7ca41dc1c59d89e36f5ff2ef1bc08 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Wed, 26 May 2010 15:12:10 +0300 Subject: mx25: add platform code for imx-keypad Signed-off-by: Baruch Siach Signed-off-by: Sascha Hauer --- arch/arm/mach-mx25/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-mx25/clock.c') diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index 155014993b1..f44d65765b9 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c @@ -217,7 +217,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk) _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk) _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk) - _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk) + _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk) _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk) _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk) -- cgit v1.2.3 From a6e92b49ae5ef48e1791e5df8368af1fe8b3bd9a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Tue, 8 Jun 2010 11:02:57 +0200 Subject: i.MX25: fix get_rate_otg to return the correct value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit usb drivers need to get the right value for otg clock so calculate and return it Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer --- arch/arm/mach-mx25/clock.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-mx25/clock.c') diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index f44d65765b9..84f0f1efea4 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c @@ -131,7 +131,10 @@ static unsigned long get_rate_lcdc(struct clk *clk) static unsigned long get_rate_otg(struct clk *clk) { - return 48000000; /* FIXME */ + unsigned long cctl = readl(CRM_BASE + CCM_CCTL); + unsigned long rate = get_rate_upll(); + + return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1); } static int clk_cgcr_enable(struct clk *clk) -- cgit v1.2.3 From 8402ed30e16c65ad8560ba3293c7cf9c259712eb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Tue, 8 Jun 2010 11:03:00 +0200 Subject: i.MX25: add AUDMUX and SSI support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * add clocks for audmux and ssi 1 & 2 * add irq for ssi 1 & 2 * add devices platform for ssi1 & 2 * update audmux-v2 for i.MX25 * add base addresses for audmux & ssi 1 & 2 * add iomux configuration for GPIO for AUD5 port Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer --- arch/arm/mach-mx25/clock.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm/mach-mx25/clock.c') diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index 84f0f1efea4..caeea755158 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c @@ -109,6 +109,16 @@ static unsigned long get_rate_uart(struct clk *clk) return get_rate_per(15); } +static unsigned long get_rate_ssi2(struct clk *clk) +{ + return get_rate_per(14); +} + +static unsigned long get_rate_ssi1(struct clk *clk) +{ + return get_rate_per(13); +} + static unsigned long get_rate_i2c(struct clk *clk) { return get_rate_per(6); @@ -171,6 +181,8 @@ static void clk_cgcr_disable(struct clk *clk) DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL); DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL); +DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL); +DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); @@ -194,6 +206,9 @@ DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL); DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk); DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk); +DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); +DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); +DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); #define _REGISTER_CLOCK(d, n, c) \ { \ @@ -228,6 +243,9 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("fec.0", NULL, fec_clk) _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) + _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) + _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) + _REGISTER_CLOCK(NULL, "audmux", audmux_clk) }; int __init mx25_clocks_init(void) -- cgit v1.2.3 From 30816abc212587f8dc75dcfb4ef6d383fbe2d68c Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 10 Jun 2010 12:32:15 +0300 Subject: mx25: add watchdog clock Signed-off-by: Baruch Siach Reviewed-by: Wolfram Sang Signed-off-by: Sascha Hauer --- arch/arm/mach-mx25/clock.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/mach-mx25/clock.c') diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index caeea755158..74cf27d48bf 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c @@ -206,6 +206,7 @@ DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL); DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk); DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk); +DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); @@ -243,6 +244,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("fec.0", NULL, fec_clk) _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) + _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk) _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) _REGISTER_CLOCK(NULL, "audmux", audmux_clk) -- cgit v1.2.3 From ac0eb0f3ca3e3fff6ac083ee3a51b98f87d67843 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Thu, 10 Jun 2010 12:14:32 +0300 Subject: mx25: add a comment documenting undocumented IPG clocks The information in the i.MX25 Reference Manual is lacking. Add information from the Freescale BSP. Signed-off-by: Baruch Siach Acked-by: Wolfram Sang Signed-off-by: Sascha Hauer --- arch/arm/mach-mx25/clock.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm/mach-mx25/clock.c') diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index 74cf27d48bf..2bb4f1d73cb 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c @@ -179,6 +179,28 @@ static void clk_cgcr_disable(struct clk *clk) .secondary = s, \ } +/* + * Note: the following IPG clock gating bits are wrongly marked "Reserved" in + * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is + * taken from the Freescale released BSP. + * + * bit reg offset clock + * + * 0 CGCR1 0 AUDMUX + * 12 CGCR1 12 ESAI + * 16 CGCR1 16 GPIO1 + * 17 CGCR1 17 GPIO2 + * 18 CGCR1 18 GPIO3 + * 23 CGCR1 23 I2C1 + * 24 CGCR1 24 I2C2 + * 25 CGCR1 25 I2C3 + * 27 CGCR1 27 IOMUXC + * 28 CGCR1 28 KPP + * 30 CGCR1 30 OWIRE + * 36 CGCR2 4 RTIC + * 51 CGCR2 19 WDOG + */ + DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL); DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL); DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL); -- cgit v1.2.3 From f747847e8f0312ddc50fe7cb7ed4f6399ec154e0 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 21 Jun 2010 08:16:00 +0300 Subject: mx25: add support for the CSI device Signed-off-by: Baruch Siach Signed-off-by: Sascha Hauer --- arch/arm/mach-mx25/clock.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-mx25/clock.c') diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index 2bb4f1d73cb..1a58cae4d5e 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c @@ -139,6 +139,11 @@ static unsigned long get_rate_lcdc(struct clk *clk) return get_rate_per(7); } +static unsigned long get_rate_csi(struct clk *clk) +{ + return get_rate_per(0); +} + static unsigned long get_rate_otg(struct clk *clk) { unsigned long cctl = readl(CRM_BASE + CCM_CCTL); @@ -211,6 +216,8 @@ DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); +DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL); +DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk); DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk); @@ -232,6 +239,7 @@ DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); +DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); #define _REGISTER_CLOCK(d, n, c) \ { \ @@ -269,6 +277,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk) _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) + _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) _REGISTER_CLOCK(NULL, "audmux", audmux_clk) }; @@ -284,8 +293,9 @@ int __init mx25_clocks_init(void) __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); - /* Clock source for lcdc is upll */ - __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64); + /* Clock source for lcdc and csi is upll */ + __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0), + CRM_BASE + 0x64); mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); -- cgit v1.2.3 From 7e688f0d77f90c531747afa552d72ea70c2f0803 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20B=C3=A9nard?= Date: Fri, 16 Jul 2010 15:09:06 +0200 Subject: imx25: fix low level debug MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DEBUG_LL is actually broken on i.MX25, this patch fix it. Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer --- arch/arm/mach-mx25/clock.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/mach-mx25/clock.c') diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index 1a58cae4d5e..02f82478075 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c @@ -292,6 +292,9 @@ int __init mx25_clocks_init(void) __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0); __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); +#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) + clk_enable(&uart1_clk); +#endif /* Clock source for lcdc and csi is upll */ __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0), -- cgit v1.2.3 From e993ade18fcc5f81b26ec031c166880789a9723b Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 22 Jul 2009 17:33:36 +0200 Subject: mx25: flexcan clock support Signed-off-by: Marc Kleine-Budde Signed-off-by: Sascha Hauer --- arch/arm/mach-mx25/clock.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/mach-mx25/clock.c') diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index 02f82478075..40c7cc41cee 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c @@ -240,6 +240,8 @@ DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); +DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL); +DEFINE_CLOCK(can2_clk, 0, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL); #define _REGISTER_CLOCK(d, n, c) \ { \ @@ -279,6 +281,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) _REGISTER_CLOCK(NULL, "audmux", audmux_clk) + _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) + _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) }; int __init mx25_clocks_init(void) -- cgit v1.2.3