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authorLin Ming <ming.m.lin@intel.com>2011-03-02 21:27:04 +0800
committerIngo Molnar <mingo@elte.hu>2011-03-02 14:37:02 +0100
commitb06b3d49699a52e8f9ca056c4f96e81b1987d78e (patch)
tree9cffe092fd4ecd5b579dfd7f7655d6424c53c3d0 /scripts
parenta639dc64e52183a361c260e562e73b0800b89072 (diff)
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perf, x86: Add Intel SandyBridge CPU support
This patch adds basic SandyBridge support, including hardware cache events and PEBS events support. It has been tested on SandyBridge CPUs with perf stat and also with PEBS based profiling - both work fine. The patch does not affect other models. v2 -> v3: - fix PEBS event 0xd0 with right umask combinations - move snb pebs constraint assignment to intel_pmu_init v1 -> v2: - add more raw and PEBS events constraints - use offcore events for LLC-* cache events - remove the call to Nehalem workaround enable_all function Signed-off-by: Lin Ming <ming.m.lin@intel.com> Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Stephane Eranian <eranian@google.com> Cc: Andi Kleen <andi@firstfloor.org> LKML-Reference: <1299072424.2175.24.camel@localhost> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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