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| author | Kumar Gala <galak@freescale.com> | 2005-04-16 15:24:22 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 15:24:22 -0700 |
| commit | f50b153b1966230e78034d5ab1641ca4bb5db56d (patch) | |
| tree | 9f3f0971789ca2cbb59efbd694c172804f4547cd /include/asm-ppc/cputable.h | |
| parent | b464fce5edc08a825907e9d48a2d2f1af0393fef (diff) | |
| download | kernel_samsung_smdk4412-f50b153b1966230e78034d5ab1641ca4bb5db56d.tar.gz kernel_samsung_smdk4412-f50b153b1966230e78034d5ab1641ca4bb5db56d.tar.bz2 kernel_samsung_smdk4412-f50b153b1966230e78034d5ab1641ca4bb5db56d.zip | |
[PATCH] ppc32: Support 36-bit physical addressing on e500
To add support for 36-bit physical addressing on e500 the following changes
have been made. The changes are generalized to support any physical address
size larger than 32-bits:
* Allow FSL Book-E parts to use a 64-bit PTE, it is 44-bits of pfn, 20-bits
of flags.
* Introduced new CPU feature (CPU_FTR_BIG_PHYS) to allow runtime handling of
updating hardware register (SPRN_MAS7) which holds the upper 32-bits of
physical address that will be written into the TLB. This is useful since
not all e500 cores support 36-bit physical addressing.
* Currently have a pass through implementation of fixup_bigphys_addr
* Moved _PAGE_DIRTY in the 64-bit PTE case to free room for three additional
storage attributes that may exist in future FSL Book-E cores and updated
fault handler to copy these bits into the hardware TLBs.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-ppc/cputable.h')
| -rw-r--r-- | include/asm-ppc/cputable.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/asm-ppc/cputable.h b/include/asm-ppc/cputable.h index 22de04fe1b4..41d8f8425c0 100644 --- a/include/asm-ppc/cputable.h +++ b/include/asm-ppc/cputable.h @@ -86,8 +86,9 @@ static inline unsigned int cpu_has_feature(unsigned int feature) #define CPU_FTR_DUAL_PLL_750FX 0x00004000 #define CPU_FTR_NO_DPM 0x00008000 #define CPU_FTR_HAS_HIGH_BATS 0x00010000 -#define CPU_FTR_NEED_COHERENT 0x00020000 +#define CPU_FTR_NEED_COHERENT 0x00020000 #define CPU_FTR_NO_BTIC 0x00040000 +#define CPU_FTR_BIG_PHYS 0x00080000 #ifdef __ASSEMBLY__ |