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| author | Timur Tabi <timur@freescale.com> | 2011-06-08 14:03:05 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-06-22 06:14:54 -0500 |
| commit | f3fed682f78dfab384d3dc3f9ca7a7338a93c142 (patch) | |
| tree | 86fb6bd8b175fc321d8db33aeef643e230fa98b9 /arch/powerpc | |
| parent | c02a02ee4db5cd8b95ee3cc705b535f443612583 (diff) | |
| download | kernel_samsung_smdk4412-f3fed682f78dfab384d3dc3f9ca7a7338a93c142.tar.gz kernel_samsung_smdk4412-f3fed682f78dfab384d3dc3f9ca7a7338a93c142.tar.bz2 kernel_samsung_smdk4412-f3fed682f78dfab384d3dc3f9ca7a7338a93c142.zip | |
powerpc/p1022ds: fix audio-related properties in the device tree
On the Freescale P1022DS reference board, the SSI audio controller is
connected in "asynchronous" mode to the codec's clocks, so the device tree
needs an "fsl,ssi-asynchronous" property.
Also remove the clock-frequency property from the wm8776 node, because
the clock is enabled only if U-Boot enables it, and U-Boot will set the
property if the clock is enabled. A future version of the P1022DS audio
driver will configure the clock itself, but for now, the driver should
not be told that the clock is running when it isn't.
Also fix the FIFO depth to 15, instead of 16.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/boot/dts/p1022ds.dts | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts index 4f685a779f4..98d9426d4b8 100644 --- a/arch/powerpc/boot/dts/p1022ds.dts +++ b/arch/powerpc/boot/dts/p1022ds.dts @@ -209,8 +209,10 @@ wm8776:codec@1a { compatible = "wlf,wm8776"; reg = <0x1a>; - /* MCLK source is a stand-alone oscillator */ - clock-frequency = <12288000>; + /* + * clock-frequency will be set by U-Boot if + * the clock is enabled. + */ }; }; @@ -280,7 +282,8 @@ codec-handle = <&wm8776>; fsl,playback-dma = <&dma00>; fsl,capture-dma = <&dma01>; - fsl,fifo-depth = <16>; + fsl,fifo-depth = <15>; + fsl,ssi-asynchronous; }; dma@c300 { |