external_mesa3d/src/gallium/docs/source/tgsi.rst, branch replicant-6.0

gallium: add opcode and types for 64-bit integers. (v3)

2016-09-21T08:23:05+00:00

This just adds the basic support for 64-bit opcodes,
and the new types.

v2: add conversion opcodes.
add documentation.
v3:
- make docs more consistent
- change TGSI_OPCODE_I2U64 to TGSI_OPCODE_U2I64

Reviewed-by: Marek Olšák  (v2)
Reviewed-by: Roland Scheidegger 
Reviewed-by: Edward O'Callaghan 
Signed-off-by: Dave Airlie 
Signed-off-by: Nicolai Hähnle

tgsi: document semantics for compute shaders

2016-09-12T20:15:10+00:00

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Nicolai Hähnle

tgsi: Add WORK_DIM System Value

2016-07-02T10:21:28+00:00

Add a new WORK_DIM SV type, this is will return the grid dimensions
(1-4) for compute (opencl) kernels.

This is necessary to implement the opencl get_work_dim() function.

Signed-off-by: Hans de Goede 
Reviewed-by: Ilia Mirkin 
Reviewed-by: Samuel Pitoiset

gallium: add VOTE_* opcodes to implement GL_ARB_shader_group_vote

2016-06-07T00:49:28+00:00

Signed-off-by: Ilia Mirkin 
Reviewed-by: Dave Airlie

tgsi: remove culldist semantic.

2016-05-23T01:03:44+00:00

This isn't used anymore in the tree, culldist's
are part of the clipdist semantic, we could in theory
rename it, but I'm not sure there is much point, and
I'd have to be careful with virgl.

Reviewed-by: Roland Scheidegger 
Signed-off-by: Dave Airlie

nouveau: codegen: LOAD: Take src swizzle into account

2016-04-27T14:11:48+00:00

The llvm TGSI backend uses pointers in registers and does things
like:

LOAD TEMP[0].y, MEMORY[0], TEMP[0]

Expecting the data at address TEMP[0].x to get loaded to
TEMP[0].y. But this will cause the data at TEMP[0].x + 4 to be
loaded instead.

This commit adds support for a swizzle suffix for the 1st source
operand, which allows using:

LOAD TEMP[0].y, MEMORY[0].xxxx, TEMP[0]

And actually getting the desired behavior

Signed-off-by: Hans de Goede 
Reviewed-by: Samuel Pitoiset 
Reviewed-by: Ilia Mirkin

tgsi/doc: fix spelling error

2016-04-11T08:43:43+00:00

Signed-off-by: Oded Gabbay 
Reviewed-by: Rob Clark

gallium: add threads per block TGSI property

2016-04-01T23:50:59+00:00

The value 0 for unknown has been chosen to so that
drivers using tgsi_scan_shader do not need to detect
missing properties if they zero-initialize the struct.

Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Ilia Mirkin 
Reviewed-by: Dave Airlie

gallium/docs: s/gven/given/

2016-03-30T00:13:46+00:00

gallium: add TGSI property NEXT_SHADER

2016-03-19T22:20:01+00:00

Radeonsi needs to know which shader stage will execute after a shader
in order to make the best decision about which shader variant to compile
first.

This is only set for VS and TES, because we don't need it elsewhere.

VS has 3 variants:
- next shader is FS
- next shader is GS
- next shader is TCS

TES has 2 variants:
- next shader is FS
- next shader is GS

Currently, radeonsi always assumes the next shader is FS, which is suboptimal,
since st/mesa always knows which shader is next if the GLSL program is not
a "separate shader".

By default, ureg always sets "next shader is FS".

Reviewed-by: Nicolai Hähnle