From 8e5f2c6f65841542e2a7092553fe42a00048e4c7 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Mon, 7 Jul 2008 23:14:23 +0000 Subject: Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/TargetInstrInfoImpl.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'lib/CodeGen/TargetInstrInfoImpl.cpp') diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp index ff9c129994..4e7fec364d 100644 --- a/lib/CodeGen/TargetInstrInfoImpl.cpp +++ b/lib/CodeGen/TargetInstrInfoImpl.cpp @@ -40,7 +40,9 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI, // Create a new instruction. unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); bool Reg0IsDead = MI->getOperand(0).isDead(); - return BuildMI(MI->getDesc()).addReg(Reg0, true, false, false, Reg0IsDead) + MachineFunction &MF = *MI->getParent()->getParent(); + return BuildMI(MF, MI->getDesc()) + .addReg(Reg0, true, false, false, Reg0IsDead) .addReg(Reg2, false, false, Reg2IsKill) .addReg(Reg1, false, false, Reg1IsKill); } @@ -104,7 +106,7 @@ void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, const MachineInstr *Orig) const { - MachineInstr *MI = Orig->clone(); + MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); MI->getOperand(0).setReg(DestReg); MBB.insert(I, MI); } -- cgit v1.2.3